drivers/gpu/drm/i915/i915_reg.h

   1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   2  * All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef _I915_REG_H_
  26 #define _I915_REG_H_
  27
  28 #include <linux/bitfield.h>
  29 #include <linux/bits.h>
  30
  31 /**
  32  * DOC: The i915 register macro definition style guide
  33  *
  34  * Follow the style described here for new macros, and while changing existing
  35  * macros. Do **not** mass change existing definitions just to update the style.
  36  *
  37  * Layout
  38  * ~~~~~~
  39  *
  40  * Keep helper macros near the top. For example, _PIPE() and friends.
  41  *
  42  * Prefix macros that generally should not be used outside of this file with
  43  * underscore '_'. For example, _PIPE() and friends, single instances of
  44  * registers that are defined solely for the use by function-like macros.
  45  *
  46  * Avoid using the underscore prefixed macros outside of this file. There are
  47  * exceptions, but keep them to a minimum.
  48  *
  49  * There are two basic types of register definitions: Single registers and
  50  * register groups. Register groups are registers which have two or more
  51  * instances, for example one per pipe, port, transcoder, etc. Register groups
  52  * should be defined using function-like macros.
  53  *
  54  * For single registers, define the register offset first, followed by register
  55  * contents.
  56  *
  57  * For register groups, define the register instance offsets first, prefixed
  58  * with underscore, followed by a function-like macro choosing the right
  59  * instance based on the parameter, followed by register contents.
  60  *
  61  * Define the register contents (i.e. bit and bit field macros) from most
  62  * significant to least significant bit. Indent the register content macros
  63  * using two extra spaces between ``#define`` and the macro name.
  64  *
  65  * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
  66  * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
  67  * shifted in place, so they can be directly OR'd together. For convenience,
  68  * function-like macros may be used to define bit fields, but do note that the
  69  * macros may be needed to read as well as write the register contents.
  70  *
  71  * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
  72  *
  73  * Group the register and its contents together without blank lines, separate
  74  * from other registers and their contents with one blank line.
  75  *
  76  * Indent macro values from macro names using TABs. Align values vertically. Use
  77  * braces in macro values as needed to avoid unintended precedence after macro
  78  * substitution. Use spaces in macro values according to kernel coding
  79  * style. Use lower case in hexadecimal values.
  80  *
  81  * Naming
  82  * ~~~~~~
  83  *
  84  * Try to name registers according to the specs. If the register name changes in
  85  * the specs from platform to another, stick to the original name.
  86  *
  87  * Try to re-use existing register macro definitions. Only add new macros for
  88  * new register offsets, or when the register contents have changed enough to
  89  * warrant a full redefinition.
  90  *
  91  * When a register macro changes for a new platform, prefix the new macro using
  92  * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
  93  * prefix signifies the start platform/generation using the register.
  94  *
  95  * When a bit (field) macro changes or gets added for a new platform, while
  96  * retaining the existing register macro, add a platform acronym or generation
  97  * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
  98  *
  99  * Examples
 100  * ~~~~~~~~
 101  *
 102  * (Note that the values in the example are indented using spaces instead of
 103  * TABs to avoid misalignment in generated documentation. Use TABs in the
 104  * definitions.)::
 105  *
 106  *  #define _FOO_A                      0xf000
 107  *  #define _FOO_B                      0xf001
 108  *  #define FOO(pipe)                   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
 109  *  #define   FOO_ENABLE                REG_BIT(31)
 110  *  #define   FOO_MODE_MASK             REG_GENMASK(19, 16)
 111  *  #define   FOO_MODE_BAR              REG_FIELD_PREP(FOO_MODE_MASK, 0)
 112  *  #define   FOO_MODE_BAZ              REG_FIELD_PREP(FOO_MODE_MASK, 1)
 113  *  #define   FOO_MODE_QUX_SNB          REG_FIELD_PREP(FOO_MODE_MASK, 2)
 114  *
 115  *  #define BAR                         _MMIO(0xb000)
 116  *  #define GEN8_BAR                    _MMIO(0xb888)
 117  */
 118
 119 /**
 120  * REG_BIT() - Prepare a u32 bit value
 121  * @__n: 0-based bit number
 122  *
 123  * Local wrapper for BIT() to force u32, with compile time checks.
 124  *
 125  * @return: Value with bit @__n set.
 126  */
 127 #define REG_BIT(__n)                                                    \
 128         ((u32)(BIT(__n) +                                               \
 129                BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&         \
 130                                  ((__n) < 0 || (__n) > 31))))
 131
 132 /**
 133  * REG_GENMASK() - Prepare a continuous u32 bitmask
 134  * @__high: 0-based high bit
 135  * @__low: 0-based low bit
 136  *
 137  * Local wrapper for GENMASK() to force u32, with compile time checks.
 138  *
 139  * @return: Continuous bitmask from @__high to @__low, inclusive.
 140  */
 141 #define REG_GENMASK(__high, __low)                                      \
 142         ((u32)(GENMASK(__high, __low) +                                 \
 143                BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&      \
 144                                  __is_constexpr(__low) &&               \
 145                                  ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
 146
 147 /*
 148  * Local integer constant expression version of is_power_of_2().
 149  */
 150 #define IS_POWER_OF_2(__x)              ((__x) && (((__x) & ((__x) - 1)) == 0))
 151
 152 /**
 153  * REG_FIELD_PREP() - Prepare a u32 bitfield value
 154  * @__mask: shifted mask defining the field's length and position
 155  * @__val: value to put in the field
 156  *
 157  * Local copy of FIELD_PREP() to generate an integer constant expression, force
 158  * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
 159  *
 160  * @return: @__val masked and shifted into the field defined by @__mask.
 161  */
 162 #define REG_FIELD_PREP(__mask, __val)                                           \
 163         ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +     \
 164                BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +             \
 165                BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +         \
 166                BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
 167                BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
 168
 169 /**
 170  * REG_FIELD_GET() - Extract a u32 bitfield value
 171  * @__mask: shifted mask defining the field's length and position
 172  * @__val: value to extract the bitfield value from
 173  *
 174  * Local wrapper for FIELD_GET() to force u32 and for consistency with
 175  * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
 176  *
 177  * @return: Masked and shifted value of the field defined by @__mask in @__val.
 178  */
 179 #define REG_FIELD_GET(__mask, __val)    ((u32)FIELD_GET(__mask, __val))
 180
 181 typedef struct {
 182         u32 reg;
 183 } i915_reg_t;
 184
 185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
 186
 187 #define INVALID_MMIO_REG _MMIO(0)
 188
 189 static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
 190 {
 191         return reg.reg;
 192 }
 193
 194 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
 195 {
 196         return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
 197 }
 198
 199 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 200 {
 201         return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
 202 }
 203
 204 #define VLV_DISPLAY_BASE                0x180000
 205 #define VLV_MIPI_BASE                   VLV_DISPLAY_BASE
 206 #define BXT_MIPI_BASE                   0x60000
 207
 208 #define DISPLAY_MMIO_BASE(dev_priv)     (INTEL_INFO(dev_priv)->display_mmio_offset)
 209
 210 /*
 211  * Given the first two numbers __a and __b of arbitrarily many evenly spaced
 212  * numbers, pick the 0-based __index'th value.
 213  *
 214  * Always prefer this over _PICK() if the numbers are evenly spaced.
 215  */
 216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
 217
 218 /*
 219  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
 220  *
 221  * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
 222  */
 223 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
 224
 225 /*
 226  * Named helper wrappers around _PICK_EVEN() and _PICK().
 227  */
 228 #define _PIPE(pipe, a, b)               _PICK_EVEN(pipe, a, b)
 229 #define _PLANE(plane, a, b)             _PICK_EVEN(plane, a, b)
 230 #define _TRANS(tran, a, b)              _PICK_EVEN(tran, a, b)
 231 #define _PORT(port, a, b)               _PICK_EVEN(port, a, b)
 232 #define _PLL(pll, a, b)                 _PICK_EVEN(pll, a, b)
 233
 234 #define _MMIO_PIPE(pipe, a, b)          _MMIO(_PIPE(pipe, a, b))
 235 #define _MMIO_PLANE(plane, a, b)        _MMIO(_PLANE(plane, a, b))
 236 #define _MMIO_TRANS(tran, a, b)         _MMIO(_TRANS(tran, a, b))
 237 #define _MMIO_PORT(port, a, b)          _MMIO(_PORT(port, a, b))
 238 #define _MMIO_PLL(pll, a, b)            _MMIO(_PLL(pll, a, b))
 239
 240 #define _PHY3(phy, ...)                 _PICK(phy, __VA_ARGS__)
 241
 242 #define _MMIO_PIPE3(pipe, a, b, c)      _MMIO(_PICK(pipe, a, b, c))
 243 #define _MMIO_PORT3(pipe, a, b, c)      _MMIO(_PICK(pipe, a, b, c))
 244 #define _MMIO_PHY3(phy, a, b, c)        _MMIO(_PHY3(phy, a, b, c))
 245 #define _MMIO_PLL3(pll, a, b, c)        _MMIO(_PICK(pll, a, b, c))
 246
 247 /*
 248  * Device info offset array based helpers for groups of registers with unevenly
 249  * spaced base offsets.
 250  */
 251 #define _MMIO_PIPE2(pipe, reg)          _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
 252                                               INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
 253                                               DISPLAY_MMIO_BASE(dev_priv))
 254 #define _TRANS2(tran, reg)              (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
 255                                          INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
 256                                          DISPLAY_MMIO_BASE(dev_priv))
 257 #define _MMIO_TRANS2(tran, reg)         _MMIO(_TRANS2(tran, reg))
 258 #define _CURSOR2(pipe, reg)             _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
 259                                               INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
 260                                               DISPLAY_MMIO_BASE(dev_priv))
 261
 262 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
 263 #define _MASKED_FIELD(mask, value) ({                                      \
 264         if (__builtin_constant_p(mask))                                    \
 265                 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
 266         if (__builtin_constant_p(value))                                   \
 267                 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
 268         if (__builtin_constant_p(mask) && __builtin_constant_p(value))     \
 269                 BUILD_BUG_ON_MSG((value) & ~(mask),                        \
 270                                  "Incorrect value for mask");              \
 271         __MASKED_FIELD(mask, value); })
 272 #define _MASKED_BIT_ENABLE(a)   ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
 273 #define _MASKED_BIT_DISABLE(a)  (_MASKED_FIELD((a), 0))
 274
 275 /* PCI config space */
 276
 277 #define MCHBAR_I915 0x44
 278 #define MCHBAR_I965 0x48
 279 #define MCHBAR_SIZE (4 * 4096)
 280
 281 #define DEVEN 0x54
 282 #define   DEVEN_MCHBAR_EN (1 << 28)
 283
 284 /* BSM in include/drm/i915_drm.h */
 285
 286 #define HPLLCC  0xc0 /* 85x only */
 287 #define   GC_CLOCK_CONTROL_MASK         (0x7 << 0)
 288 #define   GC_CLOCK_133_200              (0 << 0)
 289 #define   GC_CLOCK_100_200              (1 << 0)
 290 #define   GC_CLOCK_100_133              (2 << 0)
 291 #define   GC_CLOCK_133_266              (3 << 0)
 292 #define   GC_CLOCK_133_200_2            (4 << 0)
 293 #define   GC_CLOCK_133_266_2            (5 << 0)
 294 #define   GC_CLOCK_166_266              (6 << 0)
 295 #define   GC_CLOCK_166_250              (7 << 0)
 296
 297 #define I915_GDRST 0xc0 /* PCI config register */
 298 #define   GRDOM_FULL            (0 << 2)
 299 #define   GRDOM_RENDER          (1 << 2)
 300 #define   GRDOM_MEDIA           (3 << 2)
 301 #define   GRDOM_MASK            (3 << 2)
 302 #define   GRDOM_RESET_STATUS    (1 << 1)
 303 #define   GRDOM_RESET_ENABLE    (1 << 0)
 304
 305 /* BSpec only has register offset, PCI device and bit found empirically */
 306 #define I830_CLOCK_GATE 0xc8 /* device 0 */
 307 #define   I830_L2_CACHE_CLOCK_GATE_DISABLE      (1 << 2)
 308
 309 #define GCDGMBUS 0xcc
 310
 311 #define GCFGC2  0xda
 312 #define GCFGC   0xf0 /* 915+ only */
 313 #define   GC_LOW_FREQUENCY_ENABLE       (1 << 7)
 314 #define   GC_DISPLAY_CLOCK_190_200_MHZ  (0 << 4)
 315 #define   GC_DISPLAY_CLOCK_333_320_MHZ  (4 << 4)
 316 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV  (0 << 4)
 317 #define   GC_DISPLAY_CLOCK_333_MHZ_PNV  (1 << 4)
 318 #define   GC_DISPLAY_CLOCK_444_MHZ_PNV  (2 << 4)
 319 #define   GC_DISPLAY_CLOCK_200_MHZ_PNV  (5 << 4)
 320 #define   GC_DISPLAY_CLOCK_133_MHZ_PNV  (6 << 4)
 321 #define   GC_DISPLAY_CLOCK_167_MHZ_PNV  (7 << 4)
 322 #define   GC_DISPLAY_CLOCK_MASK         (7 << 4)
 323 #define   GM45_GC_RENDER_CLOCK_MASK     (0xf << 0)
 324 #define   GM45_GC_RENDER_CLOCK_266_MHZ  (8 << 0)
 325 #define   GM45_GC_RENDER_CLOCK_320_MHZ  (9 << 0)
 326 #define   GM45_GC_RENDER_CLOCK_400_MHZ  (0xb << 0)
 327 #define   GM45_GC_RENDER_CLOCK_533_MHZ  (0xc << 0)
 328 #define   I965_GC_RENDER_CLOCK_MASK     (0xf << 0)
 329 #define   I965_GC_RENDER_CLOCK_267_MHZ  (2 << 0)
 330 #define   I965_GC_RENDER_CLOCK_333_MHZ  (3 << 0)
 331 #define   I965_GC_RENDER_CLOCK_444_MHZ  (4 << 0)
 332 #define   I965_GC_RENDER_CLOCK_533_MHZ  (5 << 0)
 333 #define   I945_GC_RENDER_CLOCK_MASK     (7 << 0)
 334 #define   I945_GC_RENDER_CLOCK_166_MHZ  (0 << 0)
 335 #define   I945_GC_RENDER_CLOCK_200_MHZ  (1 << 0)
 336 #define   I945_GC_RENDER_CLOCK_250_MHZ  (3 << 0)
 337 #define   I945_GC_RENDER_CLOCK_400_MHZ  (5 << 0)
 338 #define   I915_GC_RENDER_CLOCK_MASK     (7 << 0)
 339 #define   I915_GC_RENDER_CLOCK_166_MHZ  (0 << 0)
 340 #define   I915_GC_RENDER_CLOCK_200_MHZ  (1 << 0)
 341 #define   I915_GC_RENDER_CLOCK_333_MHZ  (4 << 0)
 342
 343 #define ASLE    0xe4
 344 #define ASLS    0xfc
 345
 346 #define SWSCI   0xe8
 347 #define   SWSCI_SCISEL  (1 << 15)
 348 #define   SWSCI_GSSCIE  (1 << 0)
 349
 350 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
 351
 352
 353 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
 354 #define  ILK_GRDOM_FULL         (0 << 1)
 355 #define  ILK_GRDOM_RENDER       (1 << 1)
 356 #define  ILK_GRDOM_MEDIA        (3 << 1)
 357 #define  ILK_GRDOM_MASK         (3 << 1)
 358 #define  ILK_GRDOM_RESET_ENABLE (1 << 0)
 359
 360 #define GEN6_MBCUNIT_SNPCR      _MMIO(0x900c) /* for LLC config */
 361 #define   GEN6_MBC_SNPCR_SHIFT  21
 362 #define   GEN6_MBC_SNPCR_MASK   (3 << 21)
 363 #define   GEN6_MBC_SNPCR_MAX    (0 << 21)
 364 #define   GEN6_MBC_SNPCR_MED    (1 << 21)
 365 #define   GEN6_MBC_SNPCR_LOW    (2 << 21)
 366 #define   GEN6_MBC_SNPCR_MIN    (3 << 21) /* only 1/16th of the cache is shared */
 367
 368 #define VLV_G3DCTL              _MMIO(0x9024)
 369 #define VLV_GSCKGCTL            _MMIO(0x9028)
 370
 371 #define GEN6_MBCTL              _MMIO(0x0907c)
 372 #define   GEN6_MBCTL_ENABLE_BOOT_FETCH  (1 << 4)
 373 #define   GEN6_MBCTL_CTX_FETCH_NEEDED   (1 << 3)
 374 #define   GEN6_MBCTL_BME_UPDATE_ENABLE  (1 << 2)
 375 #define   GEN6_MBCTL_MAE_UPDATE_ENABLE  (1 << 1)
 376 #define   GEN6_MBCTL_BOOT_FETCH_MECH    (1 << 0)
 377
 378 #define GEN6_GDRST      _MMIO(0x941c)
 379 #define  GEN6_GRDOM_FULL                (1 << 0)
 380 #define  GEN6_GRDOM_RENDER              (1 << 1)
 381 #define  GEN6_GRDOM_MEDIA               (1 << 2)
 382 #define  GEN6_GRDOM_BLT                 (1 << 3)
 383 #define  GEN6_GRDOM_VECS                (1 << 4)
 384 #define  GEN9_GRDOM_GUC                 (1 << 5)
 385 #define  GEN8_GRDOM_MEDIA2              (1 << 7)
 386 /* GEN11 changed all bit defs except for FULL & RENDER */
 387 #define  GEN11_GRDOM_FULL               GEN6_GRDOM_FULL
 388 #define  GEN11_GRDOM_RENDER             GEN6_GRDOM_RENDER
 389 #define  GEN11_GRDOM_BLT                (1 << 2)
 390 #define  GEN11_GRDOM_GUC                (1 << 3)
 391 #define  GEN11_GRDOM_MEDIA              (1 << 5)
 392 #define  GEN11_GRDOM_MEDIA2             (1 << 6)
 393 #define  GEN11_GRDOM_MEDIA3             (1 << 7)
 394 #define  GEN11_GRDOM_MEDIA4             (1 << 8)
 395 #define  GEN11_GRDOM_VECS               (1 << 13)
 396 #define  GEN11_GRDOM_VECS2              (1 << 14)
 397 #define  GEN11_GRDOM_SFC0               (1 << 17)
 398 #define  GEN11_GRDOM_SFC1               (1 << 18)
 399
 400 #define  GEN11_VCS_SFC_RESET_BIT(instance)      (GEN11_GRDOM_SFC0 << ((instance) >> 1))
 401 #define  GEN11_VECS_SFC_RESET_BIT(instance)     (GEN11_GRDOM_SFC0 << (instance))
 402
 403 #define GEN11_VCS_SFC_FORCED_LOCK(engine)       _MMIO((engine)->mmio_base + 0x88C)
 404 #define   GEN11_VCS_SFC_FORCED_LOCK_BIT         (1 << 0)
 405 #define GEN11_VCS_SFC_LOCK_STATUS(engine)       _MMIO((engine)->mmio_base + 0x890)
 406 #define   GEN11_VCS_SFC_USAGE_BIT               (1 << 0)
 407 #define   GEN11_VCS_SFC_LOCK_ACK_BIT            (1 << 1)
 408
 409 #define GEN11_VECS_SFC_FORCED_LOCK(engine)      _MMIO((engine)->mmio_base + 0x201C)
 410 #define   GEN11_VECS_SFC_FORCED_LOCK_BIT        (1 << 0)
 411 #define GEN11_VECS_SFC_LOCK_ACK(engine)         _MMIO((engine)->mmio_base + 0x2018)
 412 #define   GEN11_VECS_SFC_LOCK_ACK_BIT           (1 << 0)
 413 #define GEN11_VECS_SFC_USAGE(engine)            _MMIO((engine)->mmio_base + 0x2014)
 414 #define   GEN11_VECS_SFC_USAGE_BIT              (1 << 0)
 415
 416 #define RING_PP_DIR_BASE(base)          _MMIO((base) + 0x228)
 417 #define RING_PP_DIR_BASE_READ(base)     _MMIO((base) + 0x518)
 418 #define RING_PP_DIR_DCLV(base)          _MMIO((base) + 0x220)
 419 #define   PP_DIR_DCLV_2G                0xffffffff
 420
 421 #define GEN8_RING_PDP_UDW(base, n)      _MMIO((base) + 0x270 + (n) * 8 + 4)
 422 #define GEN8_RING_PDP_LDW(base, n)      _MMIO((base) + 0x270 + (n) * 8)
 423
 424 #define GEN8_R_PWR_CLK_STATE            _MMIO(0x20C8)
 425 #define   GEN8_RPCS_ENABLE              (1 << 31)
 426 #define   GEN8_RPCS_S_CNT_ENABLE        (1 << 18)
 427 #define   GEN8_RPCS_S_CNT_SHIFT         15
 428 #define   GEN8_RPCS_S_CNT_MASK          (0x7 << GEN8_RPCS_S_CNT_SHIFT)
 429 #define   GEN11_RPCS_S_CNT_SHIFT        12
 430 #define   GEN11_RPCS_S_CNT_MASK         (0x3f << GEN11_RPCS_S_CNT_SHIFT)
 431 #define   GEN8_RPCS_SS_CNT_ENABLE       (1 << 11)
 432 #define   GEN8_RPCS_SS_CNT_SHIFT        8
 433 #define   GEN8_RPCS_SS_CNT_MASK         (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
 434 #define   GEN8_RPCS_EU_MAX_SHIFT        4
 435 #define   GEN8_RPCS_EU_MAX_MASK         (0xf << GEN8_RPCS_EU_MAX_SHIFT)
 436 #define   GEN8_RPCS_EU_MIN_SHIFT        0
 437 #define   GEN8_RPCS_EU_MIN_MASK         (0xf << GEN8_RPCS_EU_MIN_SHIFT)
 438
 439 #define WAIT_FOR_RC6_EXIT               _MMIO(0x20CC)
 440 /* HSW only */
 441 #define   HSW_SELECTIVE_READ_ADDRESSING_SHIFT           2
 442 #define   HSW_SELECTIVE_READ_ADDRESSING_MASK            (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
 443 #define   HSW_SELECTIVE_WRITE_ADDRESS_SHIFT             4
 444 #define   HSW_SELECTIVE_WRITE_ADDRESS_MASK              (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
 445 /* HSW+ */
 446 #define   HSW_WAIT_FOR_RC6_EXIT_ENABLE                  (1 << 0)
 447 #define   HSW_RCS_CONTEXT_ENABLE                        (1 << 7)
 448 #define   HSW_RCS_INHIBIT                               (1 << 8)
 449 /* Gen8 */
 450 #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT            4
 451 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK             (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
 452 #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT            4
 453 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK             (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
 454 #define   GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE        (1 << 6)
 455 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT     9
 456 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK      (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
 457 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT        11
 458 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_MASK         (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
 459 #define   GEN8_SELECTIVE_READ_ADDRESSING_ENABLE         (1 << 13)
 460
 461 #define GAM_ECOCHK                      _MMIO(0x4090)
 462 #define   BDW_DISABLE_HDC_INVALIDATION  (1 << 25)
 463 #define   ECOCHK_SNB_BIT                (1 << 10)
 464 #define   ECOCHK_DIS_TLB                (1 << 8)
 465 #define   HSW_ECOCHK_ARB_PRIO_SOL       (1 << 6)
 466 #define   ECOCHK_PPGTT_CACHE64B         (0x3 << 3)
 467 #define   ECOCHK_PPGTT_CACHE4B          (0x0 << 3)
 468 #define   ECOCHK_PPGTT_GFDT_IVB         (0x1 << 4)
 469 #define   ECOCHK_PPGTT_LLC_IVB          (0x1 << 3)
 470 #define   ECOCHK_PPGTT_UC_HSW           (0x1 << 3)
 471 #define   ECOCHK_PPGTT_WT_HSW           (0x2 << 3)
 472 #define   ECOCHK_PPGTT_WB_HSW           (0x3 << 3)
 473
 474 #define GEN8_RC6_CTX_INFO               _MMIO(0x8504)
 475
 476 #define GAC_ECO_BITS                    _MMIO(0x14090)
 477 #define   ECOBITS_SNB_BIT               (1 << 13)
 478 #define   ECOBITS_PPGTT_CACHE64B        (3 << 8)
 479 #define   ECOBITS_PPGTT_CACHE4B         (0 << 8)
 480
 481 #define GAB_CTL                         _MMIO(0x24000)
 482 #define   GAB_CTL_CONT_AFTER_PAGEFAULT  (1 << 8)
 483
 484 #define GEN6_STOLEN_RESERVED            _MMIO(0x1082C0)
 485 #define GEN6_STOLEN_RESERVED_ADDR_MASK  (0xFFF << 20)
 486 #define GEN7_STOLEN_RESERVED_ADDR_MASK  (0x3FFF << 18)
 487 #define GEN6_STOLEN_RESERVED_SIZE_MASK  (3 << 4)
 488 #define GEN6_STOLEN_RESERVED_1M         (0 << 4)
 489 #define GEN6_STOLEN_RESERVED_512K       (1 << 4)
 490 #define GEN6_STOLEN_RESERVED_256K       (2 << 4)
 491 #define GEN6_STOLEN_RESERVED_128K       (3 << 4)
 492 #define GEN7_STOLEN_RESERVED_SIZE_MASK  (1 << 5)
 493 #define GEN7_STOLEN_RESERVED_1M         (0 << 5)
 494 #define GEN7_STOLEN_RESERVED_256K       (1 << 5)
 495 #define GEN8_STOLEN_RESERVED_SIZE_MASK  (3 << 7)
 496 #define GEN8_STOLEN_RESERVED_1M         (0 << 7)
 497 #define GEN8_STOLEN_RESERVED_2M         (1 << 7)
 498 #define GEN8_STOLEN_RESERVED_4M         (2 << 7)
 499 #define GEN8_STOLEN_RESERVED_8M         (3 << 7)
 500 #define GEN6_STOLEN_RESERVED_ENABLE     (1 << 0)
 501 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
 502
 503 /* VGA stuff */
 504
 505 #define VGA_ST01_MDA 0x3ba
 506 #define VGA_ST01_CGA 0x3da
 507
 508 #define _VGA_MSR_WRITE _MMIO(0x3c2)
 509 #define VGA_MSR_WRITE 0x3c2
 510 #define VGA_MSR_READ 0x3cc
 511 #define   VGA_MSR_MEM_EN (1 << 1)
 512 #define   VGA_MSR_CGA_MODE (1 << 0)
 513
 514 #define VGA_SR_INDEX 0x3c4
 515 #define SR01                    1
 516 #define VGA_SR_DATA 0x3c5
 517
 518 #define VGA_AR_INDEX 0x3c0
 519 #define   VGA_AR_VID_EN (1 << 5)
 520 #define VGA_AR_DATA_WRITE 0x3c0
 521 #define VGA_AR_DATA_READ 0x3c1
 522
 523 #define VGA_GR_INDEX 0x3ce
 524 #define VGA_GR_DATA 0x3cf
 525 /* GR05 */
 526 #define   VGA_GR_MEM_READ_MODE_SHIFT 3
 527 #define     VGA_GR_MEM_READ_MODE_PLANE 1
 528 /* GR06 */
 529 #define   VGA_GR_MEM_MODE_MASK 0xc
 530 #define   VGA_GR_MEM_MODE_SHIFT 2
 531 #define   VGA_GR_MEM_A0000_AFFFF 0
 532 #define   VGA_GR_MEM_A0000_BFFFF 1
 533 #define   VGA_GR_MEM_B0000_B7FFF 2
 534 #define   VGA_GR_MEM_B0000_BFFFF 3
 535
 536 #define VGA_DACMASK 0x3c6
 537 #define VGA_DACRX 0x3c7
 538 #define VGA_DACWX 0x3c8
 539 #define VGA_DACDATA 0x3c9
 540
 541 #define VGA_CR_INDEX_MDA 0x3b4
 542 #define VGA_CR_DATA_MDA 0x3b5
 543 #define VGA_CR_INDEX_CGA 0x3d4
 544 #define VGA_CR_DATA_CGA 0x3d5
 545
 546 #define MI_PREDICATE_SRC0       _MMIO(0x2400)
 547 #define MI_PREDICATE_SRC0_UDW   _MMIO(0x2400 + 4)
 548 #define MI_PREDICATE_SRC1       _MMIO(0x2408)
 549 #define MI_PREDICATE_SRC1_UDW   _MMIO(0x2408 + 4)
 550
 551 #define MI_PREDICATE_RESULT_2   _MMIO(0x2214)
 552 #define  LOWER_SLICE_ENABLED    (1 << 0)
 553 #define  LOWER_SLICE_DISABLED   (0 << 0)
 554
 555 /*
 556  * Registers used only by the command parser
 557  */
 558 #define BCS_SWCTRL _MMIO(0x22200)
 559
 560 /* There are 16 GPR registers */
 561 #define BCS_GPR(n)      _MMIO(0x22600 + (n) * 8)
 562 #define BCS_GPR_UDW(n)  _MMIO(0x22600 + (n) * 8 + 4)
 563
 564 #define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
 565 #define GPGPU_THREADS_DISPATCHED_UDW    _MMIO(0x2290 + 4)
 566 #define HS_INVOCATION_COUNT             _MMIO(0x2300)
 567 #define HS_INVOCATION_COUNT_UDW         _MMIO(0x2300 + 4)
 568 #define DS_INVOCATION_COUNT             _MMIO(0x2308)
 569 #define DS_INVOCATION_COUNT_UDW         _MMIO(0x2308 + 4)
 570 #define IA_VERTICES_COUNT               _MMIO(0x2310)
 571 #define IA_VERTICES_COUNT_UDW           _MMIO(0x2310 + 4)
 572 #define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
 573 #define IA_PRIMITIVES_COUNT_UDW         _MMIO(0x2318 + 4)
 574 #define VS_INVOCATION_COUNT             _MMIO(0x2320)
 575 #define VS_INVOCATION_COUNT_UDW         _MMIO(0x2320 + 4)
 576 #define GS_INVOCATION_COUNT             _MMIO(0x2328)
 577 #define GS_INVOCATION_COUNT_UDW         _MMIO(0x2328 + 4)
 578 #define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
 579 #define GS_PRIMITIVES_COUNT_UDW         _MMIO(0x2330 + 4)
 580 #define CL_INVOCATION_COUNT             _MMIO(0x2338)
 581 #define CL_INVOCATION_COUNT_UDW         _MMIO(0x2338 + 4)
 582 #define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
 583 #define CL_PRIMITIVES_COUNT_UDW         _MMIO(0x2340 + 4)
 584 #define PS_INVOCATION_COUNT             _MMIO(0x2348)
 585 #define PS_INVOCATION_COUNT_UDW         _MMIO(0x2348 + 4)
 586 #define PS_DEPTH_COUNT                  _MMIO(0x2350)
 587 #define PS_DEPTH_COUNT_UDW              _MMIO(0x2350 + 4)
 588
 589 /* There are the 4 64-bit counter registers, one for each stream output */
 590 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)            _MMIO(0x5200 + (n) * 8)
 591 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)        _MMIO(0x5200 + (n) * 8 + 4)
 592
 593 #define GEN7_SO_PRIM_STORAGE_NEEDED(n)          _MMIO(0x5240 + (n) * 8)
 594 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)      _MMIO(0x5240 + (n) * 8 + 4)
 595
 596 #define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
 597 #define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
 598 #define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
 599 #define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
 600 #define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
 601 #define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)
 602
 603 #define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
 604 #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
 605 #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
 606
 607 /* There are the 16 64-bit CS General Purpose Registers */
 608 #define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
 609 #define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
 610
 611 #define GEN7_OACONTROL _MMIO(0x2360)
 612 #define  GEN7_OACONTROL_CTX_MASK            0xFFFFF000
 613 #define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
 614 #define  GEN7_OACONTROL_TIMER_PERIOD_SHIFT  6
 615 #define  GEN7_OACONTROL_TIMER_ENABLE        (1 << 5)
 616 #define  GEN7_OACONTROL_FORMAT_A13          (0 << 2)
 617 #define  GEN7_OACONTROL_FORMAT_A29          (1 << 2)
 618 #define  GEN7_OACONTROL_FORMAT_A13_B8_C8    (2 << 2)
 619 #define  GEN7_OACONTROL_FORMAT_A29_B8_C8    (3 << 2)
 620 #define  GEN7_OACONTROL_FORMAT_B4_C8        (4 << 2)
 621 #define  GEN7_OACONTROL_FORMAT_A45_B8_C8    (5 << 2)
 622 #define  GEN7_OACONTROL_FORMAT_B4_C8_A16    (6 << 2)
 623 #define  GEN7_OACONTROL_FORMAT_C4_B8        (7 << 2)
 624 #define  GEN7_OACONTROL_FORMAT_SHIFT        2
 625 #define  GEN7_OACONTROL_PER_CTX_ENABLE      (1 << 1)
 626 #define  GEN7_OACONTROL_ENABLE              (1 << 0)
 627
 628 #define GEN8_OACTXID _MMIO(0x2364)
 629
 630 #define GEN8_OA_DEBUG _MMIO(0x2B04)
 631 #define  GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS    (1 << 5)
 632 #define  GEN9_OA_DEBUG_INCLUDE_CLK_RATIO            (1 << 6)
 633 #define  GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS       (1 << 2)
 634 #define  GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS   (1 << 1)
 635
 636 #define GEN8_OACONTROL _MMIO(0x2B00)
 637 #define  GEN8_OA_REPORT_FORMAT_A12          (0 << 2)
 638 #define  GEN8_OA_REPORT_FORMAT_A12_B8_C8    (2 << 2)
 639 #define  GEN8_OA_REPORT_FORMAT_A36_B8_C8    (5 << 2)
 640 #define  GEN8_OA_REPORT_FORMAT_C4_B8        (7 << 2)
 641 #define  GEN8_OA_REPORT_FORMAT_SHIFT        2
 642 #define  GEN8_OA_SPECIFIC_CONTEXT_ENABLE    (1 << 1)
 643 #define  GEN8_OA_COUNTER_ENABLE             (1 << 0)
 644
 645 #define GEN8_OACTXCONTROL _MMIO(0x2360)
 646 #define  GEN8_OA_TIMER_PERIOD_MASK          0x3F
 647 #define  GEN8_OA_TIMER_PERIOD_SHIFT         2
 648 #define  GEN8_OA_TIMER_ENABLE               (1 << 1)
 649 #define  GEN8_OA_COUNTER_RESUME             (1 << 0)
 650
 651 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
 652 #define  GEN7_OABUFFER_OVERRUN_DISABLE      (1 << 3)
 653 #define  GEN7_OABUFFER_EDGE_TRIGGER         (1 << 2)
 654 #define  GEN7_OABUFFER_STOP_RESUME_ENABLE   (1 << 1)
 655 #define  GEN7_OABUFFER_RESUME               (1 << 0)
 656
 657 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
 658 #define GEN8_OABUFFER _MMIO(0x2b14)
 659 #define  GEN8_OABUFFER_MEM_SELECT_GGTT      (1 << 0)  /* 0: PPGTT, 1: GGTT */
 660
 661 #define GEN7_OASTATUS1 _MMIO(0x2364)
 662 #define  GEN7_OASTATUS1_TAIL_MASK           0xffffffc0
 663 #define  GEN7_OASTATUS1_COUNTER_OVERFLOW    (1 << 2)
 664 #define  GEN7_OASTATUS1_OABUFFER_OVERFLOW   (1 << 1)
 665 #define  GEN7_OASTATUS1_REPORT_LOST         (1 << 0)
 666
 667 #define GEN7_OASTATUS2 _MMIO(0x2368)
 668 #define  GEN7_OASTATUS2_HEAD_MASK           0xffffffc0
 669 #define  GEN7_OASTATUS2_MEM_SELECT_GGTT     (1 << 0) /* 0: PPGTT, 1: GGTT */
 670
 671 #define GEN8_OASTATUS _MMIO(0x2b08)
 672 #define  GEN8_OASTATUS_OVERRUN_STATUS       (1 << 3)
 673 #define  GEN8_OASTATUS_COUNTER_OVERFLOW     (1 << 2)
 674 #define  GEN8_OASTATUS_OABUFFER_OVERFLOW    (1 << 1)
 675 #define  GEN8_OASTATUS_REPORT_LOST          (1 << 0)
 676
 677 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
 678 #define GEN8_OAHEADPTR_MASK    0xffffffc0
 679 #define GEN8_OATAILPTR _MMIO(0x2B10)
 680 #define GEN8_OATAILPTR_MASK    0xffffffc0
 681
 682 #define OABUFFER_SIZE_128K  (0 << 3)
 683 #define OABUFFER_SIZE_256K  (1 << 3)
 684 #define OABUFFER_SIZE_512K  (2 << 3)
 685 #define OABUFFER_SIZE_1M    (3 << 3)
 686 #define OABUFFER_SIZE_2M    (4 << 3)
 687 #define OABUFFER_SIZE_4M    (5 << 3)
 688 #define OABUFFER_SIZE_8M    (6 << 3)
 689 #define OABUFFER_SIZE_16M   (7 << 3)
 690
 691 /*
 692  * Flexible, Aggregate EU Counter Registers.
 693  * Note: these aren't contiguous
 694  */
 695 #define EU_PERF_CNTL0       _MMIO(0xe458)
 696 #define EU_PERF_CNTL1       _MMIO(0xe558)
 697 #define EU_PERF_CNTL2       _MMIO(0xe658)
 698 #define EU_PERF_CNTL3       _MMIO(0xe758)
 699 #define EU_PERF_CNTL4       _MMIO(0xe45c)
 700 #define EU_PERF_CNTL5       _MMIO(0xe55c)
 701 #define EU_PERF_CNTL6       _MMIO(0xe65c)
 702
 703 /*
 704  * OA Boolean state
 705  */
 706
 707 #define OASTARTTRIG1 _MMIO(0x2710)
 708 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
 709 #define OASTARTTRIG1_THRESHOLD_MASK           0xffff
 710
 711 #define OASTARTTRIG2 _MMIO(0x2714)
 712 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
 713 #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
 714 #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
 715 #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
 716 #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
 717 #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
 718 #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
 719 #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
 720 #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
 721 #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
 722 #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
 723 #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
 724 #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
 725 #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
 726 #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
 727 #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
 728 #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
 729 #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
 730 #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
 731 #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
 732 #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
 733 #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
 734 #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
 735 #define OASTARTTRIG2_THRESHOLD_ENABLE       (1 << 23)
 736 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ    (1 << 24)
 737 #define OASTARTTRIG2_EVENT_SELECT_0  (1 << 28)
 738 #define OASTARTTRIG2_EVENT_SELECT_1  (1 << 29)
 739 #define OASTARTTRIG2_EVENT_SELECT_2  (1 << 30)
 740 #define OASTARTTRIG2_EVENT_SELECT_3  (1 << 31)
 741
 742 #define OASTARTTRIG3 _MMIO(0x2718)
 743 #define OASTARTTRIG3_NOA_SELECT_MASK       0xf
 744 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT    0
 745 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT    4
 746 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT   8
 747 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT   12
 748 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT   16
 749 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT   20
 750 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT   24
 751 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT   28
 752
 753 #define OASTARTTRIG4 _MMIO(0x271c)
 754 #define OASTARTTRIG4_NOA_SELECT_MASK        0xf
 755 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT    0
 756 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT    4
 757 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT    8
 758 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT    12
 759 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT    16
 760 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT    20
 761 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT    24
 762 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT    28
 763
 764 #define OASTARTTRIG5 _MMIO(0x2720)
 765 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
 766 #define OASTARTTRIG5_THRESHOLD_MASK           0xffff
 767
 768 #define OASTARTTRIG6 _MMIO(0x2724)
 769 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
 770 #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
 771 #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
 772 #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
 773 #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
 774 #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
 775 #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
 776 #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
 777 #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
 778 #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
 779 #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
 780 #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
 781 #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
 782 #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
 783 #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
 784 #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
 785 #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
 786 #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
 787 #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
 788 #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
 789 #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
 790 #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
 791 #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
 792 #define OASTARTTRIG6_THRESHOLD_ENABLE       (1 << 23)
 793 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ    (1 << 24)
 794 #define OASTARTTRIG6_EVENT_SELECT_4  (1 << 28)
 795 #define OASTARTTRIG6_EVENT_SELECT_5  (1 << 29)
 796 #define OASTARTTRIG6_EVENT_SELECT_6  (1 << 30)
 797 #define OASTARTTRIG6_EVENT_SELECT_7  (1 << 31)
 798
 799 #define OASTARTTRIG7 _MMIO(0x2728)
 800 #define OASTARTTRIG7_NOA_SELECT_MASK       0xf
 801 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT    0
 802 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT    4
 803 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT   8
 804 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT   12
 805 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT   16
 806 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT   20
 807 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT   24
 808 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT   28
 809
 810 #define OASTARTTRIG8 _MMIO(0x272c)
 811 #define OASTARTTRIG8_NOA_SELECT_MASK       0xf
 812 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT    0
 813 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT    4
 814 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT    8
 815 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT    12
 816 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT    16
 817 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT    20
 818 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT    24
 819 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT    28
 820
 821 #define OAREPORTTRIG1 _MMIO(0x2740)
 822 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
 823 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
 824
 825 #define OAREPORTTRIG2 _MMIO(0x2744)
 826 #define OAREPORTTRIG2_INVERT_A_0  (1 << 0)
 827 #define OAREPORTTRIG2_INVERT_A_1  (1 << 1)
 828 #define OAREPORTTRIG2_INVERT_A_2  (1 << 2)
 829 #define OAREPORTTRIG2_INVERT_A_3  (1 << 3)
 830 #define OAREPORTTRIG2_INVERT_A_4  (1 << 4)
 831 #define OAREPORTTRIG2_INVERT_A_5  (1 << 5)
 832 #define OAREPORTTRIG2_INVERT_A_6  (1 << 6)
 833 #define OAREPORTTRIG2_INVERT_A_7  (1 << 7)
 834 #define OAREPORTTRIG2_INVERT_A_8  (1 << 8)
 835 #define OAREPORTTRIG2_INVERT_A_9  (1 << 9)
 836 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
 837 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
 838 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
 839 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
 840 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
 841 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
 842 #define OAREPORTTRIG2_INVERT_B_0  (1 << 16)
 843 #define OAREPORTTRIG2_INVERT_B_1  (1 << 17)
 844 #define OAREPORTTRIG2_INVERT_B_2  (1 << 18)
 845 #define OAREPORTTRIG2_INVERT_B_3  (1 << 19)
 846 #define OAREPORTTRIG2_INVERT_C_0  (1 << 20)
 847 #define OAREPORTTRIG2_INVERT_C_1  (1 << 21)
 848 #define OAREPORTTRIG2_INVERT_D_0  (1 << 22)
 849 #define OAREPORTTRIG2_THRESHOLD_ENABLE      (1 << 23)
 850 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
 851
 852 #define OAREPORTTRIG3 _MMIO(0x2748)
 853 #define OAREPORTTRIG3_NOA_SELECT_MASK       0xf
 854 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT    0
 855 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT    4
 856 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT   8
 857 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT   12
 858 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT   16
 859 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT   20
 860 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT   24
 861 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT   28
 862
 863 #define OAREPORTTRIG4 _MMIO(0x274c)
 864 #define OAREPORTTRIG4_NOA_SELECT_MASK       0xf
 865 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT    0
 866 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT    4
 867 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT    8
 868 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT    12
 869 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT    16
 870 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT    20
 871 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT    24
 872 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT    28
 873
 874 #define OAREPORTTRIG5 _MMIO(0x2750)
 875 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
 876 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
 877
 878 #define OAREPORTTRIG6 _MMIO(0x2754)
 879 #define OAREPORTTRIG6_INVERT_A_0  (1 << 0)
 880 #define OAREPORTTRIG6_INVERT_A_1  (1 << 1)
 881 #define OAREPORTTRIG6_INVERT_A_2  (1 << 2)
 882 #define OAREPORTTRIG6_INVERT_A_3  (1 << 3)
 883 #define OAREPORTTRIG6_INVERT_A_4  (1 << 4)
 884 #define OAREPORTTRIG6_INVERT_A_5  (1 << 5)
 885 #define OAREPORTTRIG6_INVERT_A_6  (1 << 6)
 886 #define OAREPORTTRIG6_INVERT_A_7  (1 << 7)
 887 #define OAREPORTTRIG6_INVERT_A_8  (1 << 8)
 888 #define OAREPORTTRIG6_INVERT_A_9  (1 << 9)
 889 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
 890 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
 891 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
 892 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
 893 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
 894 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
 895 #define OAREPORTTRIG6_INVERT_B_0  (1 << 16)
 896 #define OAREPORTTRIG6_INVERT_B_1  (1 << 17)
 897 #define OAREPORTTRIG6_INVERT_B_2  (1 << 18)
 898 #define OAREPORTTRIG6_INVERT_B_3  (1 << 19)
 899 #define OAREPORTTRIG6_INVERT_C_0  (1 << 20)
 900 #define OAREPORTTRIG6_INVERT_C_1  (1 << 21)
 901 #define OAREPORTTRIG6_INVERT_D_0  (1 << 22)
 902 #define OAREPORTTRIG6_THRESHOLD_ENABLE      (1 << 23)
 903 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
 904
 905 #define OAREPORTTRIG7 _MMIO(0x2758)
 906 #define OAREPORTTRIG7_NOA_SELECT_MASK       0xf
 907 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT    0
 908 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT    4
 909 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT   8
 910 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT   12
 911 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT   16
 912 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT   20
 913 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT   24
 914 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT   28
 915
 916 #define OAREPORTTRIG8 _MMIO(0x275c)
 917 #define OAREPORTTRIG8_NOA_SELECT_MASK       0xf
 918 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT    0
 919 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT    4
 920 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT    8
 921 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT    12
 922 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT    16
 923 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT    20
 924 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT    24
 925 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT    28
 926
 927 /* CECX_0 */
 928 #define OACEC_COMPARE_LESS_OR_EQUAL     6
 929 #define OACEC_COMPARE_NOT_EQUAL         5
 930 #define OACEC_COMPARE_LESS_THAN         4
 931 #define OACEC_COMPARE_GREATER_OR_EQUAL  3
 932 #define OACEC_COMPARE_EQUAL             2
 933 #define OACEC_COMPARE_GREATER_THAN      1
 934 #define OACEC_COMPARE_ANY_EQUAL         0
 935
 936 #define OACEC_COMPARE_VALUE_MASK    0xffff
 937 #define OACEC_COMPARE_VALUE_SHIFT   3
 938
 939 #define OACEC_SELECT_NOA        (0 << 19)
 940 #define OACEC_SELECT_PREV       (1 << 19)
 941 #define OACEC_SELECT_BOOLEAN    (2 << 19)
 942
 943 /* CECX_1 */
 944 #define OACEC_MASK_MASK             0xffff
 945 #define OACEC_CONSIDERATIONS_MASK   0xffff
 946 #define OACEC_CONSIDERATIONS_SHIFT  16
 947
 948 #define OACEC0_0 _MMIO(0x2770)
 949 #define OACEC0_1 _MMIO(0x2774)
 950 #define OACEC1_0 _MMIO(0x2778)
 951 #define OACEC1_1 _MMIO(0x277c)
 952 #define OACEC2_0 _MMIO(0x2780)
 953 #define OACEC2_1 _MMIO(0x2784)
 954 #define OACEC3_0 _MMIO(0x2788)
 955 #define OACEC3_1 _MMIO(0x278c)
 956 #define OACEC4_0 _MMIO(0x2790)
 957 #define OACEC4_1 _MMIO(0x2794)
 958 #define OACEC5_0 _MMIO(0x2798)
 959 #define OACEC5_1 _MMIO(0x279c)
 960 #define OACEC6_0 _MMIO(0x27a0)
 961 #define OACEC6_1 _MMIO(0x27a4)
 962 #define OACEC7_0 _MMIO(0x27a8)
 963 #define OACEC7_1 _MMIO(0x27ac)
 964
 965 /* OA perf counters */
 966 #define OA_PERFCNT1_LO      _MMIO(0x91B8)
 967 #define OA_PERFCNT1_HI      _MMIO(0x91BC)
 968 #define OA_PERFCNT2_LO      _MMIO(0x91C0)
 969 #define OA_PERFCNT2_HI      _MMIO(0x91C4)
 970 #define OA_PERFCNT3_LO      _MMIO(0x91C8)
 971 #define OA_PERFCNT3_HI      _MMIO(0x91CC)
 972 #define OA_PERFCNT4_LO      _MMIO(0x91D8)
 973 #define OA_PERFCNT4_HI      _MMIO(0x91DC)
 974
 975 #define OA_PERFMATRIX_LO    _MMIO(0x91C8)
 976 #define OA_PERFMATRIX_HI    _MMIO(0x91CC)
 977
 978 /* RPM unit config (Gen8+) */
 979 #define RPM_CONFIG0         _MMIO(0x0D00)
 980 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT      3
 981 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK       (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
 982 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ   0
 983 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ     1
 984 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT     3
 985 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK      (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
 986 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ    0
 987 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ  1
 988 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ  2
 989 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ    3
 990 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT    1
 991 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK     (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
 992
 993 #define RPM_CONFIG1         _MMIO(0x0D04)
 994 #define  GEN10_GT_NOA_ENABLE  (1 << 9)
 995
 996 /* GPM unit config (Gen9+) */
 997 #define CTC_MODE                        _MMIO(0xA26C)
 998 #define  CTC_SOURCE_PARAMETER_MASK 1
 999 #define  CTC_SOURCE_CRYSTAL_CLOCK       0
1000 #define  CTC_SOURCE_DIVIDE_LOGIC        1
1001 #define  CTC_SHIFT_PARAMETER_SHIFT      1
1002 #define  CTC_SHIFT_PARAMETER_MASK       (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1003
1004 /* RCP unit config (Gen8+) */
1005 #define RCP_CONFIG          _MMIO(0x0D08)
1006
1007 /* NOA (HSW) */
1008 #define HSW_MBVID2_NOA0         _MMIO(0x9E80)
1009 #define HSW_MBVID2_NOA1         _MMIO(0x9E84)
1010 #define HSW_MBVID2_NOA2         _MMIO(0x9E88)
1011 #define HSW_MBVID2_NOA3         _MMIO(0x9E8C)
1012 #define HSW_MBVID2_NOA4         _MMIO(0x9E90)
1013 #define HSW_MBVID2_NOA5         _MMIO(0x9E94)
1014 #define HSW_MBVID2_NOA6         _MMIO(0x9E98)
1015 #define HSW_MBVID2_NOA7         _MMIO(0x9E9C)
1016 #define HSW_MBVID2_NOA8         _MMIO(0x9EA0)
1017 #define HSW_MBVID2_NOA9         _MMIO(0x9EA4)
1018
1019 #define HSW_MBVID2_MISR0        _MMIO(0x9EC0)
1020
1021 /* NOA (Gen8+) */
1022 #define NOA_CONFIG(i)       _MMIO(0x0D0C + (i) * 4)
1023
1024 #define MICRO_BP0_0         _MMIO(0x9800)
1025 #define MICRO_BP0_2         _MMIO(0x9804)
1026 #define MICRO_BP0_1         _MMIO(0x9808)
1027
1028 #define MICRO_BP1_0         _MMIO(0x980C)
1029 #define MICRO_BP1_2         _MMIO(0x9810)
1030 #define MICRO_BP1_1         _MMIO(0x9814)
1031
1032 #define MICRO_BP2_0         _MMIO(0x9818)
1033 #define MICRO_BP2_2         _MMIO(0x981C)
1034 #define MICRO_BP2_1         _MMIO(0x9820)
1035
1036 #define MICRO_BP3_0         _MMIO(0x9824)
1037 #define MICRO_BP3_2         _MMIO(0x9828)
1038 #define MICRO_BP3_1         _MMIO(0x982C)
1039
1040 #define MICRO_BP_TRIGGER                _MMIO(0x9830)
1041 #define MICRO_BP3_COUNT_STATUS01        _MMIO(0x9834)
1042 #define MICRO_BP3_COUNT_STATUS23        _MMIO(0x9838)
1043 #define MICRO_BP_FIRED_ARMED            _MMIO(0x983C)
1044
1045 #define GDT_CHICKEN_BITS    _MMIO(0x9840)
1046 #define   GT_NOA_ENABLE     0x00000080
1047
1048 #define NOA_DATA            _MMIO(0x986C)
1049 #define NOA_WRITE           _MMIO(0x9888)
1050 #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1051
1052 #define _GEN7_PIPEA_DE_LOAD_SL  0x70068
1053 #define _GEN7_PIPEB_DE_LOAD_SL  0x71068
1054 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1055
1056 /*
1057  * Reset registers
1058  */
1059 #define DEBUG_RESET_I830                _MMIO(0x6070)
1060 #define  DEBUG_RESET_FULL               (1 << 7)
1061 #define  DEBUG_RESET_RENDER             (1 << 8)
1062 #define  DEBUG_RESET_DISPLAY            (1 << 9)
1063
1064 /*
1065  * IOSF sideband
1066  */
1067 #define VLV_IOSF_DOORBELL_REQ                   _MMIO(VLV_DISPLAY_BASE + 0x2100)
1068 #define   IOSF_DEVFN_SHIFT                      24
1069 #define   IOSF_OPCODE_SHIFT                     16
1070 #define   IOSF_PORT_SHIFT                       8
1071 #define   IOSF_BYTE_ENABLES_SHIFT               4
1072 #define   IOSF_BAR_SHIFT                        1
1073 #define   IOSF_SB_BUSY                          (1 << 0)
1074 #define   IOSF_PORT_BUNIT                       0x03
1075 #define   IOSF_PORT_PUNIT                       0x04
1076 #define   IOSF_PORT_NC                          0x11
1077 #define   IOSF_PORT_DPIO                        0x12
1078 #define   IOSF_PORT_GPIO_NC                     0x13
1079 #define   IOSF_PORT_CCK                         0x14
1080 #define   IOSF_PORT_DPIO_2                      0x1a
1081 #define   IOSF_PORT_FLISDSI                     0x1b
1082 #define   IOSF_PORT_GPIO_SC                     0x48
1083 #define   IOSF_PORT_GPIO_SUS                    0xa8
1084 #define   IOSF_PORT_CCU                         0xa9
1085 #define   CHV_IOSF_PORT_GPIO_N                  0x13
1086 #define   CHV_IOSF_PORT_GPIO_SE                 0x48
1087 #define   CHV_IOSF_PORT_GPIO_E                  0xa8
1088 #define   CHV_IOSF_PORT_GPIO_SW                 0xb2
1089 #define VLV_IOSF_DATA                           _MMIO(VLV_DISPLAY_BASE + 0x2104)
1090 #define VLV_IOSF_ADDR                           _MMIO(VLV_DISPLAY_BASE + 0x2108)
1091
1092 /* See configdb bunit SB addr map */
1093 #define BUNIT_REG_BISOC                         0x11
1094
1095 /* PUNIT_REG_*SSPM0 */
1096 #define   _SSPM0_SSC(val)                       ((val) << 0)
1097 #define   SSPM0_SSC_MASK                        _SSPM0_SSC(0x3)
1098 #define   SSPM0_SSC_PWR_ON                      _SSPM0_SSC(0x0)
1099 #define   SSPM0_SSC_CLK_GATE                    _SSPM0_SSC(0x1)
1100 #define   SSPM0_SSC_RESET                       _SSPM0_SSC(0x2)
1101 #define   SSPM0_SSC_PWR_GATE                    _SSPM0_SSC(0x3)
1102 #define   _SSPM0_SSS(val)                       ((val) << 24)
1103 #define   SSPM0_SSS_MASK                        _SSPM0_SSS(0x3)
1104 #define   SSPM0_SSS_PWR_ON                      _SSPM0_SSS(0x0)
1105 #define   SSPM0_SSS_CLK_GATE                    _SSPM0_SSS(0x1)
1106 #define   SSPM0_SSS_RESET                       _SSPM0_SSS(0x2)
1107 #define   SSPM0_SSS_PWR_GATE                    _SSPM0_SSS(0x3)
1108
1109 /* PUNIT_REG_*SSPM1 */
1110 #define   SSPM1_FREQSTAT_SHIFT                  24
1111 #define   SSPM1_FREQSTAT_MASK                   (0x1f << SSPM1_FREQSTAT_SHIFT)
1112 #define   SSPM1_FREQGUAR_SHIFT                  8
1113 #define   SSPM1_FREQGUAR_MASK                   (0x1f << SSPM1_FREQGUAR_SHIFT)
1114 #define   SSPM1_FREQ_SHIFT                      0
1115 #define   SSPM1_FREQ_MASK                       (0x1f << SSPM1_FREQ_SHIFT)
1116
1117 #define PUNIT_REG_VEDSSPM0                      0x32
1118 #define PUNIT_REG_VEDSSPM1                      0x33
1119
1120 #define PUNIT_REG_DSPSSPM                       0x36
1121 #define   DSPFREQSTAT_SHIFT_CHV                 24
1122 #define   DSPFREQSTAT_MASK_CHV                  (0x1f << DSPFREQSTAT_SHIFT_CHV)
1123 #define   DSPFREQGUAR_SHIFT_CHV                 8
1124 #define   DSPFREQGUAR_MASK_CHV                  (0x1f << DSPFREQGUAR_SHIFT_CHV)
1125 #define   DSPFREQSTAT_SHIFT                     30
1126 #define   DSPFREQSTAT_MASK                      (0x3 << DSPFREQSTAT_SHIFT)
1127 #define   DSPFREQGUAR_SHIFT                     14
1128 #define   DSPFREQGUAR_MASK                      (0x3 << DSPFREQGUAR_SHIFT)
1129 #define   DSP_MAXFIFO_PM5_STATUS                (1 << 22) /* chv */
1130 #define   DSP_AUTO_CDCLK_GATE_DISABLE           (1 << 7) /* chv */
1131 #define   DSP_MAXFIFO_PM5_ENABLE                (1 << 6) /* chv */
1132 #define   _DP_SSC(val, pipe)                    ((val) << (2 * (pipe)))
1133 #define   DP_SSC_MASK(pipe)                     _DP_SSC(0x3, (pipe))
1134 #define   DP_SSC_PWR_ON(pipe)                   _DP_SSC(0x0, (pipe))
1135 #define   DP_SSC_CLK_GATE(pipe)                 _DP_SSC(0x1, (pipe))
1136 #define   DP_SSC_RESET(pipe)                    _DP_SSC(0x2, (pipe))
1137 #define   DP_SSC_PWR_GATE(pipe)                 _DP_SSC(0x3, (pipe))
1138 #define   _DP_SSS(val, pipe)                    ((val) << (2 * (pipe) + 16))
1139 #define   DP_SSS_MASK(pipe)                     _DP_SSS(0x3, (pipe))
1140 #define   DP_SSS_PWR_ON(pipe)                   _DP_SSS(0x0, (pipe))
1141 #define   DP_SSS_CLK_GATE(pipe)                 _DP_SSS(0x1, (pipe))
1142 #define   DP_SSS_RESET(pipe)                    _DP_SSS(0x2, (pipe))
1143 #define   DP_SSS_PWR_GATE(pipe)                 _DP_SSS(0x3, (pipe))
1144
1145 #define PUNIT_REG_ISPSSPM0                      0x39
1146 #define PUNIT_REG_ISPSSPM1                      0x3a
1147
1148 #define PUNIT_REG_PWRGT_CTRL                    0x60
1149 #define PUNIT_REG_PWRGT_STATUS                  0x61
1150 #define   PUNIT_PWRGT_MASK(pw_idx)              (3 << ((pw_idx) * 2))
1151 #define   PUNIT_PWRGT_PWR_ON(pw_idx)            (0 << ((pw_idx) * 2))
1152 #define   PUNIT_PWRGT_CLK_GATE(pw_idx)          (1 << ((pw_idx) * 2))
1153 #define   PUNIT_PWRGT_RESET(pw_idx)             (2 << ((pw_idx) * 2))
1154 #define   PUNIT_PWRGT_PWR_GATE(pw_idx)          (3 << ((pw_idx) * 2))
1155
1156 #define PUNIT_PWGT_IDX_RENDER                   0
1157 #define PUNIT_PWGT_IDX_MEDIA                    1
1158 #define PUNIT_PWGT_IDX_DISP2D                   3
1159 #define PUNIT_PWGT_IDX_DPIO_CMN_BC              5
1160 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01       6
1161 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23       7
1162 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01       8
1163 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23       9
1164 #define PUNIT_PWGT_IDX_DPIO_RX0                 10
1165 #define PUNIT_PWGT_IDX_DPIO_RX1                 11
1166 #define PUNIT_PWGT_IDX_DPIO_CMN_D               12
1167
1168 #define PUNIT_REG_GPU_LFM                       0xd3
1169 #define PUNIT_REG_GPU_FREQ_REQ                  0xd4
1170 #define PUNIT_REG_GPU_FREQ_STS                  0xd8
1171 #define   GPLLENABLE                            (1 << 4)
1172 #define   GENFREQSTATUS                         (1 << 0)
1173 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ          0xdc
1174 #define PUNIT_REG_CZ_TIMESTAMP                  0xce
1175
1176 #define PUNIT_FUSE_BUS2                         0xf6 /* bits 47:40 */
1177 #define PUNIT_FUSE_BUS1                         0xf5 /* bits 55:48 */
1178
1179 #define FB_GFX_FMAX_AT_VMAX_FUSE                0x136
1180 #define FB_GFX_FREQ_FUSE_MASK                   0xff
1181 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT   24
1182 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT   16
1183 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT   8
1184
1185 #define FB_GFX_FMIN_AT_VMIN_FUSE                0x137
1186 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT          8
1187
1188 #define PUNIT_REG_DDR_SETUP2                    0x139
1189 #define   FORCE_DDR_FREQ_REQ_ACK                (1 << 8)
1190 #define   FORCE_DDR_LOW_FREQ                    (1 << 1)
1191 #define   FORCE_DDR_HIGH_FREQ                   (1 << 0)
1192
1193 #define PUNIT_GPU_STATUS_REG                    0xdb
1194 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1195 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK          0xff
1196 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT     8
1197 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK      0xff
1198
1199 #define PUNIT_GPU_DUTYCYCLE_REG         0xdf
1200 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT      8
1201 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK       0xff
1202
1203 #define IOSF_NC_FB_GFX_FREQ_FUSE                0x1c
1204 #define   FB_GFX_MAX_FREQ_FUSE_SHIFT            3
1205 #define   FB_GFX_MAX_FREQ_FUSE_MASK             0x000007f8
1206 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT    11
1207 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK     0x0007f800
1208 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI             0x34
1209 #define   FB_FMAX_VMIN_FREQ_HI_MASK             0x00000007
1210 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO             0x30
1211 #define   FB_FMAX_VMIN_FREQ_LO_SHIFT            27
1212 #define   FB_FMAX_VMIN_FREQ_LO_MASK             0xf8000000
1213
1214 #define VLV_TURBO_SOC_OVERRIDE          0x04
1215 #define   VLV_OVERRIDE_EN               1
1216 #define   VLV_SOC_TDP_EN                (1 << 1)
1217 #define   VLV_BIAS_CPU_125_SOC_875      (6 << 2)
1218 #define   CHV_BIAS_CPU_50_SOC_50        (3 << 2)
1219
1220 /* vlv2 north clock has */
1221 #define CCK_FUSE_REG                            0x8
1222 #define  CCK_FUSE_HPLL_FREQ_MASK                0x3
1223 #define CCK_REG_DSI_PLL_FUSE                    0x44
1224 #define CCK_REG_DSI_PLL_CONTROL                 0x48
1225 #define  DSI_PLL_VCO_EN                         (1 << 31)
1226 #define  DSI_PLL_LDO_GATE                       (1 << 30)
1227 #define  DSI_PLL_P1_POST_DIV_SHIFT              17
1228 #define  DSI_PLL_P1_POST_DIV_MASK               (0x1ff << 17)
1229 #define  DSI_PLL_P2_MUX_DSI0_DIV2               (1 << 13)
1230 #define  DSI_PLL_P3_MUX_DSI1_DIV2               (1 << 12)
1231 #define  DSI_PLL_MUX_MASK                       (3 << 9)
1232 #define  DSI_PLL_MUX_DSI0_DSIPLL                (0 << 10)
1233 #define  DSI_PLL_MUX_DSI0_CCK                   (1 << 10)
1234 #define  DSI_PLL_MUX_DSI1_DSIPLL                (0 << 9)
1235 #define  DSI_PLL_MUX_DSI1_CCK                   (1 << 9)
1236 #define  DSI_PLL_CLK_GATE_MASK                  (0xf << 5)
1237 #define  DSI_PLL_CLK_GATE_DSI0_DSIPLL           (1 << 8)
1238 #define  DSI_PLL_CLK_GATE_DSI1_DSIPLL           (1 << 7)
1239 #define  DSI_PLL_CLK_GATE_DSI0_CCK              (1 << 6)
1240 #define  DSI_PLL_CLK_GATE_DSI1_CCK              (1 << 5)
1241 #define  DSI_PLL_LOCK                           (1 << 0)
1242 #define CCK_REG_DSI_PLL_DIVIDER                 0x4c
1243 #define  DSI_PLL_LFSR                           (1 << 31)
1244 #define  DSI_PLL_FRACTION_EN                    (1 << 30)
1245 #define  DSI_PLL_FRAC_COUNTER_SHIFT             27
1246 #define  DSI_PLL_FRAC_COUNTER_MASK              (7 << 27)
1247 #define  DSI_PLL_USYNC_CNT_SHIFT                18
1248 #define  DSI_PLL_USYNC_CNT_MASK                 (0x1ff << 18)
1249 #define  DSI_PLL_N1_DIV_SHIFT                   16
1250 #define  DSI_PLL_N1_DIV_MASK                    (3 << 16)
1251 #define  DSI_PLL_M1_DIV_SHIFT                   0
1252 #define  DSI_PLL_M1_DIV_MASK                    (0x1ff << 0)
1253 #define CCK_CZ_CLOCK_CONTROL                    0x62
1254 #define CCK_GPLL_CLOCK_CONTROL                  0x67
1255 #define CCK_DISPLAY_CLOCK_CONTROL               0x6b
1256 #define CCK_DISPLAY_REF_CLOCK_CONTROL           0x6c
1257 #define  CCK_TRUNK_FORCE_ON                     (1 << 17)
1258 #define  CCK_TRUNK_FORCE_OFF                    (1 << 16)
1259 #define  CCK_FREQUENCY_STATUS                   (0x1f << 8)
1260 #define  CCK_FREQUENCY_STATUS_SHIFT             8
1261 #define  CCK_FREQUENCY_VALUES                   (0x1f << 0)
1262
1263 /* DPIO registers */
1264 #define DPIO_DEVFN                      0
1265
1266 #define DPIO_CTL                        _MMIO(VLV_DISPLAY_BASE + 0x2110)
1267 #define  DPIO_MODSEL1                   (1 << 3) /* if ref clk b == 27 */
1268 #define  DPIO_MODSEL0                   (1 << 2) /* if ref clk a == 27 */
1269 #define  DPIO_SFR_BYPASS                (1 << 1)
1270 #define  DPIO_CMNRST                    (1 << 0)
1271
1272 #define DPIO_PHY(pipe)                  ((pipe) >> 1)
1273 #define DPIO_PHY_IOSF_PORT(phy)         (dev_priv->dpio_phy_iosf_port[phy])
1274
1275 /*
1276  * Per pipe/PLL DPIO regs
1277  */
1278 #define _VLV_PLL_DW3_CH0                0x800c
1279 #define   DPIO_POST_DIV_SHIFT           (28) /* 3 bits */
1280 #define   DPIO_POST_DIV_DAC             0
1281 #define   DPIO_POST_DIV_HDMIDP          1 /* DAC 225-400M rate */
1282 #define   DPIO_POST_DIV_LVDS1           2
1283 #define   DPIO_POST_DIV_LVDS2           3
1284 #define   DPIO_K_SHIFT                  (24) /* 4 bits */
1285 #define   DPIO_P1_SHIFT                 (21) /* 3 bits */
1286 #define   DPIO_P2_SHIFT                 (16) /* 5 bits */
1287 #define   DPIO_N_SHIFT                  (12) /* 4 bits */
1288 #define   DPIO_ENABLE_CALIBRATION       (1 << 11)
1289 #define   DPIO_M1DIV_SHIFT              (8) /* 3 bits */
1290 #define   DPIO_M2DIV_MASK               0xff
1291 #define _VLV_PLL_DW3_CH1                0x802c
1292 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1293
1294 #define _VLV_PLL_DW5_CH0                0x8014
1295 #define   DPIO_REFSEL_OVERRIDE          27
1296 #define   DPIO_PLL_MODESEL_SHIFT        24 /* 3 bits */
1297 #define   DPIO_BIAS_CURRENT_CTL_SHIFT   21 /* 3 bits, always 0x7 */
1298 #define   DPIO_PLL_REFCLK_SEL_SHIFT     16 /* 2 bits */
1299 #define   DPIO_PLL_REFCLK_SEL_MASK      3
1300 #define   DPIO_DRIVER_CTL_SHIFT         12 /* always set to 0x8 */
1301 #define   DPIO_CLK_BIAS_CTL_SHIFT       8 /* always set to 0x5 */
1302 #define _VLV_PLL_DW5_CH1                0x8034
1303 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1304
1305 #define _VLV_PLL_DW7_CH0                0x801c
1306 #define _VLV_PLL_DW7_CH1                0x803c
1307 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1308
1309 #define _VLV_PLL_DW8_CH0                0x8040
1310 #define _VLV_PLL_DW8_CH1                0x8060
1311 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1312
1313 #define VLV_PLL_DW9_BCAST               0xc044
1314 #define _VLV_PLL_DW9_CH0                0x8044
1315 #define _VLV_PLL_DW9_CH1                0x8064
1316 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1317
1318 #define _VLV_PLL_DW10_CH0               0x8048
1319 #define _VLV_PLL_DW10_CH1               0x8068
1320 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1321
1322 #define _VLV_PLL_DW11_CH0               0x804c
1323 #define _VLV_PLL_DW11_CH1               0x806c
1324 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1325
1326 /* Spec for ref block start counts at DW10 */
1327 #define VLV_REF_DW13                    0x80ac
1328
1329 #define VLV_CMN_DW0                     0x8100
1330
1331 /*
1332  * Per DDI channel DPIO regs
1333  */
1334
1335 #define _VLV_PCS_DW0_CH0                0x8200
1336 #define _VLV_PCS_DW0_CH1                0x8400
1337 #define   DPIO_PCS_TX_LANE2_RESET       (1 << 16)
1338 #define   DPIO_PCS_TX_LANE1_RESET       (1 << 7)
1339 #define   DPIO_LEFT_TXFIFO_RST_MASTER2  (1 << 4)
1340 #define   DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
1341 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1342
1343 #define _VLV_PCS01_DW0_CH0              0x200
1344 #define _VLV_PCS23_DW0_CH0              0x400
1345 #define _VLV_PCS01_DW0_CH1              0x2600
1346 #define _VLV_PCS23_DW0_CH1              0x2800
1347 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1348 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1349
1350 #define _VLV_PCS_DW1_CH0                0x8204
1351 #define _VLV_PCS_DW1_CH1                0x8404
1352 #define   CHV_PCS_REQ_SOFTRESET_EN      (1 << 23)
1353 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
1354 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1355 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT  (6)
1356 #define   DPIO_PCS_CLK_SOFT_RESET       (1 << 5)
1357 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1358
1359 #define _VLV_PCS01_DW1_CH0              0x204
1360 #define _VLV_PCS23_DW1_CH0              0x404
1361 #define _VLV_PCS01_DW1_CH1              0x2604
1362 #define _VLV_PCS23_DW1_CH1              0x2804
1363 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1364 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1365
1366 #define _VLV_PCS_DW8_CH0                0x8220
1367 #define _VLV_PCS_DW8_CH1                0x8420
1368 #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE        (1 << 20)
1369 #define   CHV_PCS_USEDCLKCHANNEL                (1 << 21)
1370 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1371
1372 #define _VLV_PCS01_DW8_CH0              0x0220
1373 #define _VLV_PCS23_DW8_CH0              0x0420
1374 #define _VLV_PCS01_DW8_CH1              0x2620
1375 #define _VLV_PCS23_DW8_CH1              0x2820
1376 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1377 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1378
1379 #define _VLV_PCS_DW9_CH0                0x8224
1380 #define _VLV_PCS_DW9_CH1                0x8424
1381 #define   DPIO_PCS_TX2MARGIN_MASK       (0x7 << 13)
1382 #define   DPIO_PCS_TX2MARGIN_000        (0 << 13)
1383 #define   DPIO_PCS_TX2MARGIN_101        (1 << 13)
1384 #define   DPIO_PCS_TX1MARGIN_MASK       (0x7 << 10)
1385 #define   DPIO_PCS_TX1MARGIN_000        (0 << 10)
1386 #define   DPIO_PCS_TX1MARGIN_101        (1 << 10)
1387 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1388
1389 #define _VLV_PCS01_DW9_CH0              0x224
1390 #define _VLV_PCS23_DW9_CH0              0x424
1391 #define _VLV_PCS01_DW9_CH1              0x2624
1392 #define _VLV_PCS23_DW9_CH1              0x2824
1393 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1394 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1395
1396 #define _CHV_PCS_DW10_CH0               0x8228
1397 #define _CHV_PCS_DW10_CH1               0x8428
1398 #define   DPIO_PCS_SWING_CALC_TX0_TX2   (1 << 30)
1399 #define   DPIO_PCS_SWING_CALC_TX1_TX3   (1 << 31)
1400 #define   DPIO_PCS_TX2DEEMP_MASK        (0xf << 24)
1401 #define   DPIO_PCS_TX2DEEMP_9P5         (0 << 24)
1402 #define   DPIO_PCS_TX2DEEMP_6P0         (2 << 24)
1403 #define   DPIO_PCS_TX1DEEMP_MASK        (0xf << 16)
1404 #define   DPIO_PCS_TX1DEEMP_9P5         (0 << 16)
1405 #define   DPIO_PCS_TX1DEEMP_6P0         (2 << 16)
1406 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1407
1408 #define _VLV_PCS01_DW10_CH0             0x0228
1409 #define _VLV_PCS23_DW10_CH0             0x0428
1410 #define _VLV_PCS01_DW10_CH1             0x2628
1411 #define _VLV_PCS23_DW10_CH1             0x2828
1412 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1413 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1414
1415 #define _VLV_PCS_DW11_CH0               0x822c
1416 #define _VLV_PCS_DW11_CH1               0x842c
1417 #define   DPIO_TX2_STAGGER_MASK(x)      ((x) << 24)
1418 #define   DPIO_LANEDESKEW_STRAP_OVRD    (1 << 3)
1419 #define   DPIO_LEFT_TXFIFO_RST_MASTER   (1 << 1)
1420 #define   DPIO_RIGHT_TXFIFO_RST_MASTER  (1 << 0)
1421 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1422
1423 #define _VLV_PCS01_DW11_CH0             0x022c
1424 #define _VLV_PCS23_DW11_CH0             0x042c
1425 #define _VLV_PCS01_DW11_CH1             0x262c
1426 #define _VLV_PCS23_DW11_CH1             0x282c
1427 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1428 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1429
1430 #define _VLV_PCS01_DW12_CH0             0x0230
1431 #define _VLV_PCS23_DW12_CH0             0x0430
1432 #define _VLV_PCS01_DW12_CH1             0x2630
1433 #define _VLV_PCS23_DW12_CH1             0x2830
1434 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1435 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1436
1437 #define _VLV_PCS_DW12_CH0               0x8230
1438 #define _VLV_PCS_DW12_CH1               0x8430
1439 #define   DPIO_TX2_STAGGER_MULT(x)      ((x) << 20)
1440 #define   DPIO_TX1_STAGGER_MULT(x)      ((x) << 16)
1441 #define   DPIO_TX1_STAGGER_MASK(x)      ((x) << 8)
1442 #define   DPIO_LANESTAGGER_STRAP_OVRD   (1 << 6)
1443 #define   DPIO_LANESTAGGER_STRAP(x)     ((x) << 0)
1444 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1445
1446 #define _VLV_PCS_DW14_CH0               0x8238
1447 #define _VLV_PCS_DW14_CH1               0x8438
1448 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1449
1450 #define _VLV_PCS_DW23_CH0               0x825c
1451 #define _VLV_PCS_DW23_CH1               0x845c
1452 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1453
1454 #define _VLV_TX_DW2_CH0                 0x8288
1455 #define _VLV_TX_DW2_CH1                 0x8488
1456 #define   DPIO_SWING_MARGIN000_SHIFT    16
1457 #define   DPIO_SWING_MARGIN000_MASK     (0xff << DPIO_SWING_MARGIN000_SHIFT)
1458 #define   DPIO_UNIQ_TRANS_SCALE_SHIFT   8
1459 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1460
1461 #define _VLV_TX_DW3_CH0                 0x828c
1462 #define _VLV_TX_DW3_CH1                 0x848c
1463 /* The following bit for CHV phy */
1464 #define   DPIO_TX_UNIQ_TRANS_SCALE_EN   (1 << 27)
1465 #define   DPIO_SWING_MARGIN101_SHIFT    16
1466 #define   DPIO_SWING_MARGIN101_MASK     (0xff << DPIO_SWING_MARGIN101_SHIFT)
1467 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1468
1469 #define _VLV_TX_DW4_CH0                 0x8290
1470 #define _VLV_TX_DW4_CH1                 0x8490
1471 #define   DPIO_SWING_DEEMPH9P5_SHIFT    24
1472 #define   DPIO_SWING_DEEMPH9P5_MASK     (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1473 #define   DPIO_SWING_DEEMPH6P0_SHIFT    16
1474 #define   DPIO_SWING_DEEMPH6P0_MASK     (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1475 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1476
1477 #define _VLV_TX3_DW4_CH0                0x690
1478 #define _VLV_TX3_DW4_CH1                0x2a90
1479 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1480
1481 #define _VLV_TX_DW5_CH0                 0x8294
1482 #define _VLV_TX_DW5_CH1                 0x8494
1483 #define   DPIO_TX_OCALINIT_EN           (1 << 31)
1484 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1485
1486 #define _VLV_TX_DW11_CH0                0x82ac
1487 #define _VLV_TX_DW11_CH1                0x84ac
1488 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1489
1490 #define _VLV_TX_DW14_CH0                0x82b8
1491 #define _VLV_TX_DW14_CH1                0x84b8
1492 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1493
1494 /* CHV dpPhy registers */
1495 #define _CHV_PLL_DW0_CH0                0x8000
1496 #define _CHV_PLL_DW0_CH1                0x8180
1497 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1498
1499 #define _CHV_PLL_DW1_CH0                0x8004
1500 #define _CHV_PLL_DW1_CH1                0x8184
1501 #define   DPIO_CHV_N_DIV_SHIFT          8
1502 #define   DPIO_CHV_M1_DIV_BY_2          (0 << 0)
1503 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1504
1505 #define _CHV_PLL_DW2_CH0                0x8008
1506 #define _CHV_PLL_DW2_CH1                0x8188
1507 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1508
1509 #define _CHV_PLL_DW3_CH0                0x800c
1510 #define _CHV_PLL_DW3_CH1                0x818c
1511 #define  DPIO_CHV_FRAC_DIV_EN           (1 << 16)
1512 #define  DPIO_CHV_FIRST_MOD             (0 << 8)
1513 #define  DPIO_CHV_SECOND_MOD            (1 << 8)
1514 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT    0
1515 #define  DPIO_CHV_FEEDFWD_GAIN_MASK             (0xF << 0)
1516 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1517
1518 #define _CHV_PLL_DW6_CH0                0x8018
1519 #define _CHV_PLL_DW6_CH1                0x8198
1520 #define   DPIO_CHV_GAIN_CTRL_SHIFT      16
1521 #define   DPIO_CHV_INT_COEFF_SHIFT      8
1522 #define   DPIO_CHV_PROP_COEFF_SHIFT     0
1523 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1524
1525 #define _CHV_PLL_DW8_CH0                0x8020
1526 #define _CHV_PLL_DW8_CH1                0x81A0
1527 #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1528 #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
1529 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1530
1531 #define _CHV_PLL_DW9_CH0                0x8024
1532 #define _CHV_PLL_DW9_CH1                0x81A4
1533 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT              1 /* 3 bits */
1534 #define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK               (7 << 1)
1535 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine  */
1536 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1537
1538 #define _CHV_CMN_DW0_CH0               0x8100
1539 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0        19
1540 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0        18
1541 #define   DPIO_ALLDL_POWERDOWN                  (1 << 1)
1542 #define   DPIO_ANYDL_POWERDOWN                  (1 << 0)
1543
1544 #define _CHV_CMN_DW5_CH0               0x8114
1545 #define   CHV_BUFRIGHTENA1_DISABLE      (0 << 20)
1546 #define   CHV_BUFRIGHTENA1_NORMAL       (1 << 20)
1547 #define   CHV_BUFRIGHTENA1_FORCE        (3 << 20)
1548 #define   CHV_BUFRIGHTENA1_MASK         (3 << 20)
1549 #define   CHV_BUFLEFTENA1_DISABLE       (0 << 22)
1550 #define   CHV_BUFLEFTENA1_NORMAL        (1 << 22)
1551 #define   CHV_BUFLEFTENA1_FORCE         (3 << 22)
1552 #define   CHV_BUFLEFTENA1_MASK          (3 << 22)
1553
1554 #define _CHV_CMN_DW13_CH0               0x8134
1555 #define _CHV_CMN_DW0_CH1                0x8080
1556 #define   DPIO_CHV_S1_DIV_SHIFT         21
1557 #define   DPIO_CHV_P1_DIV_SHIFT         13 /* 3 bits */
1558 #define   DPIO_CHV_P2_DIV_SHIFT         8  /* 5 bits */
1559 #define   DPIO_CHV_K_DIV_SHIFT          4
1560 #define   DPIO_PLL_FREQLOCK             (1 << 1)
1561 #define   DPIO_PLL_LOCK                 (1 << 0)
1562 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1563
1564 #define _CHV_CMN_DW14_CH0               0x8138
1565 #define _CHV_CMN_DW1_CH1                0x8084
1566 #define   DPIO_AFC_RECAL                (1 << 14)
1567 #define   DPIO_DCLKP_EN                 (1 << 13)
1568 #define   CHV_BUFLEFTENA2_DISABLE       (0 << 17) /* CL2 DW1 only */
1569 #define   CHV_BUFLEFTENA2_NORMAL        (1 << 17) /* CL2 DW1 only */
1570 #define   CHV_BUFLEFTENA2_FORCE         (3 << 17) /* CL2 DW1 only */
1571 #define   CHV_BUFLEFTENA2_MASK          (3 << 17) /* CL2 DW1 only */
1572 #define   CHV_BUFRIGHTENA2_DISABLE      (0 << 19) /* CL2 DW1 only */
1573 #define   CHV_BUFRIGHTENA2_NORMAL       (1 << 19) /* CL2 DW1 only */
1574 #define   CHV_BUFRIGHTENA2_FORCE        (3 << 19) /* CL2 DW1 only */
1575 #define   CHV_BUFRIGHTENA2_MASK         (3 << 19) /* CL2 DW1 only */
1576 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1577
1578 #define _CHV_CMN_DW19_CH0               0x814c
1579 #define _CHV_CMN_DW6_CH1                0x8098
1580 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1        30 /* CL2 DW6 only */
1581 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1        29 /* CL2 DW6 only */
1582 #define   DPIO_DYNPWRDOWNEN_CH1         (1 << 28) /* CL2 DW6 only */
1583 #define   CHV_CMN_USEDCLKCHANNEL        (1 << 13)
1584
1585 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1586
1587 #define CHV_CMN_DW28                    0x8170
1588 #define   DPIO_CL1POWERDOWNEN           (1 << 23)
1589 #define   DPIO_DYNPWRDOWNEN_CH0         (1 << 22)
1590 #define   DPIO_SUS_CLK_CONFIG_ON                (0 << 0)
1591 #define   DPIO_SUS_CLK_CONFIG_CLKREQ            (1 << 0)
1592 #define   DPIO_SUS_CLK_CONFIG_GATE              (2 << 0)
1593 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ       (3 << 0)
1594
1595 #define CHV_CMN_DW30                    0x8178
1596 #define   DPIO_CL2_LDOFUSE_PWRENB       (1 << 6)
1597 #define   DPIO_LRC_BYPASS               (1 << 3)
1598
1599 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1600                                         (lane) * 0x200 + (offset))
1601
1602 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1603 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1604 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1605 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1606 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1607 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1608 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1609 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1610 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1611 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1612 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1613 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1614 #define   DPIO_FRC_LATENCY_SHFIT        8
1615 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1616 #define   DPIO_UPAR_SHIFT               30
1617
1618 /* BXT PHY registers */
1619 #define _BXT_PHY0_BASE                  0x6C000
1620 #define _BXT_PHY1_BASE                  0x162000
1621 #define _BXT_PHY2_BASE                  0x163000
1622 #define BXT_PHY_BASE(phy)               _PHY3((phy), _BXT_PHY0_BASE, \
1623                                                      _BXT_PHY1_BASE, \
1624                                                      _BXT_PHY2_BASE)
1625
1626 #define _BXT_PHY(phy, reg)                                              \
1627         _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1628
1629 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)          \
1630         (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE,    \
1631                                          (reg_ch1) - _BXT_PHY0_BASE))
1632 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)             \
1633         _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1634
1635 #define BXT_P_CR_GT_DISP_PWRON          _MMIO(0x138090)
1636 #define  MIPIO_RST_CTRL                         (1 << 2)
1637
1638 #define _BXT_PHY_CTL_DDI_A              0x64C00
1639 #define _BXT_PHY_CTL_DDI_B              0x64C10
1640 #define _BXT_PHY_CTL_DDI_C              0x64C20
1641 #define   BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1642 #define   BXT_PHY_LANE_POWERDOWN_ACK    (1 << 9)
1643 #define   BXT_PHY_LANE_ENABLED          (1 << 8)
1644 #define BXT_PHY_CTL(port)               _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1645                                                          _BXT_PHY_CTL_DDI_B)
1646
1647 #define _PHY_CTL_FAMILY_EDP             0x64C80
1648 #define _PHY_CTL_FAMILY_DDI             0x64C90
1649 #define _PHY_CTL_FAMILY_DDI_C           0x64CA0
1650 #define   COMMON_RESET_DIS              (1 << 31)
1651 #define BXT_PHY_CTL_FAMILY(phy)         _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1652                                                           _PHY_CTL_FAMILY_EDP, \
1653                                                           _PHY_CTL_FAMILY_DDI_C)
1654
1655 /* BXT PHY PLL registers */
1656 #define _PORT_PLL_A                     0x46074
1657 #define _PORT_PLL_B                     0x46078
1658 #define _PORT_PLL_C                     0x4607c
1659 #define   PORT_PLL_ENABLE               (1 << 31)
1660 #define   PORT_PLL_LOCK                 (1 << 30)
1661 #define   PORT_PLL_REF_SEL              (1 << 27)
1662 #define   PORT_PLL_POWER_ENABLE         (1 << 26)
1663 #define   PORT_PLL_POWER_STATE          (1 << 25)
1664 #define BXT_PORT_PLL_ENABLE(port)       _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1665
1666 #define _PORT_PLL_EBB_0_A               0x162034
1667 #define _PORT_PLL_EBB_0_B               0x6C034
1668 #define _PORT_PLL_EBB_0_C               0x6C340
1669 #define   PORT_PLL_P1_SHIFT             13
1670 #define   PORT_PLL_P1_MASK              (0x07 << PORT_PLL_P1_SHIFT)
1671 #define   PORT_PLL_P1(x)                ((x)  << PORT_PLL_P1_SHIFT)
1672 #define   PORT_PLL_P2_SHIFT             8
1673 #define   PORT_PLL_P2_MASK              (0x1f << PORT_PLL_P2_SHIFT)
1674 #define   PORT_PLL_P2(x)                ((x)  << PORT_PLL_P2_SHIFT)
1675 #define BXT_PORT_PLL_EBB_0(phy, ch)     _MMIO_BXT_PHY_CH(phy, ch, \
1676                                                          _PORT_PLL_EBB_0_B, \
1677                                                          _PORT_PLL_EBB_0_C)
1678
1679 #define _PORT_PLL_EBB_4_A               0x162038
1680 #define _PORT_PLL_EBB_4_B               0x6C038
1681 #define _PORT_PLL_EBB_4_C               0x6C344
1682 #define   PORT_PLL_10BIT_CLK_ENABLE     (1 << 13)
1683 #define   PORT_PLL_RECALIBRATE          (1 << 14)
1684 #define BXT_PORT_PLL_EBB_4(phy, ch)     _MMIO_BXT_PHY_CH(phy, ch, \
1685                                                          _PORT_PLL_EBB_4_B, \
1686                                                          _PORT_PLL_EBB_4_C)
1687
1688 #define _PORT_PLL_0_A                   0x162100
1689 #define _PORT_PLL_0_B                   0x6C100
1690 #define _PORT_PLL_0_C                   0x6C380
1691 /* PORT_PLL_0_A */
1692 #define   PORT_PLL_M2_MASK              0xFF
1693 /* PORT_PLL_1_A */
1694 #define   PORT_PLL_N_SHIFT              8
1695 #define   PORT_PLL_N_MASK               (0x0F << PORT_PLL_N_SHIFT)
1696 #define   PORT_PLL_N(x)                 ((x) << PORT_PLL_N_SHIFT)
1697 /* PORT_PLL_2_A */
1698 #define   PORT_PLL_M2_FRAC_MASK         0x3FFFFF
1699 /* PORT_PLL_3_A */
1700 #define   PORT_PLL_M2_FRAC_ENABLE       (1 << 16)
1701 /* PORT_PLL_6_A */
1702 #define   PORT_PLL_PROP_COEFF_MASK      0xF
1703 #define   PORT_PLL_INT_COEFF_MASK       (0x1F << 8)
1704 #define   PORT_PLL_INT_COEFF(x)         ((x)  << 8)
1705 #define   PORT_PLL_GAIN_CTL_MASK        (0x07 << 16)
1706 #define   PORT_PLL_GAIN_CTL(x)          ((x)  << 16)
1707 /* PORT_PLL_8_A */
1708 #define   PORT_PLL_TARGET_CNT_MASK      0x3FF
1709 /* PORT_PLL_9_A */
1710 #define  PORT_PLL_LOCK_THRESHOLD_SHIFT  1
1711 #define  PORT_PLL_LOCK_THRESHOLD_MASK   (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1712 /* PORT_PLL_10_A */
1713 #define  PORT_PLL_DCO_AMP_OVR_EN_H      (1 << 27)
1714 #define  PORT_PLL_DCO_AMP_DEFAULT       15
1715 #define  PORT_PLL_DCO_AMP_MASK          0x3c00
1716 #define  PORT_PLL_DCO_AMP(x)            ((x) << 10)
1717 #define _PORT_PLL_BASE(phy, ch)         _BXT_PHY_CH(phy, ch, \
1718                                                     _PORT_PLL_0_B, \
1719                                                     _PORT_PLL_0_C)
1720 #define BXT_PORT_PLL(phy, ch, idx)      _MMIO(_PORT_PLL_BASE(phy, ch) + \
1721                                               (idx) * 4)
1722
1723 /* BXT PHY common lane registers */
1724 #define _PORT_CL1CM_DW0_A               0x162000
1725 #define _PORT_CL1CM_DW0_BC              0x6C000
1726 #define   PHY_POWER_GOOD                (1 << 16)
1727 #define   PHY_RESERVED                  (1 << 7)
1728 #define BXT_PORT_CL1CM_DW0(phy)         _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1729
1730 #define _PORT_CL1CM_DW9_A               0x162024
1731 #define _PORT_CL1CM_DW9_BC              0x6C024
1732 #define   IREF0RC_OFFSET_SHIFT          8
1733 #define   IREF0RC_OFFSET_MASK           (0xFF << IREF0RC_OFFSET_SHIFT)
1734 #define BXT_PORT_CL1CM_DW9(phy)         _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1735
1736 #define _PORT_CL1CM_DW10_A              0x162028
1737 #define _PORT_CL1CM_DW10_BC             0x6C028
1738 #define   IREF1RC_OFFSET_SHIFT          8
1739 #define   IREF1RC_OFFSET_MASK           (0xFF << IREF1RC_OFFSET_SHIFT)
1740 #define BXT_PORT_CL1CM_DW10(phy)        _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1741
1742 #define _PORT_CL1CM_DW28_A              0x162070
1743 #define _PORT_CL1CM_DW28_BC             0x6C070
1744 #define   OCL1_POWER_DOWN_EN            (1 << 23)
1745 #define   DW28_OLDO_DYN_PWR_DOWN_EN     (1 << 22)
1746 #define   SUS_CLK_CONFIG                0x3
1747 #define BXT_PORT_CL1CM_DW28(phy)        _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1748
1749 #define _PORT_CL1CM_DW30_A              0x162078
1750 #define _PORT_CL1CM_DW30_BC             0x6C078
1751 #define   OCL2_LDOFUSE_PWR_DIS          (1 << 6)
1752 #define BXT_PORT_CL1CM_DW30(phy)        _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1753
1754 /*
1755  * CNL/ICL Port/COMBO-PHY Registers
1756  */
1757 #define _ICL_COMBOPHY_A                 0x162000
1758 #define _ICL_COMBOPHY_B                 0x6C000
1759 #define _EHL_COMBOPHY_C                 0x160000
1760 #define _ICL_COMBOPHY(phy)              _PICK(phy, _ICL_COMBOPHY_A, \
1761                                               _ICL_COMBOPHY_B, \
1762                                               _EHL_COMBOPHY_C)
1763
1764 /* CNL/ICL Port CL_DW registers */
1765 #define _ICL_PORT_CL_DW(dw, phy)        (_ICL_COMBOPHY(phy) + \
1766                                          4 * (dw))
1767
1768 #define CNL_PORT_CL1CM_DW5              _MMIO(0x162014)
1769 #define ICL_PORT_CL_DW5(phy)            _MMIO(_ICL_PORT_CL_DW(5, phy))
1770 #define   CL_POWER_DOWN_ENABLE          (1 << 4)
1771 #define   SUS_CLOCK_CONFIG              (3 << 0)
1772
1773 #define ICL_PORT_CL_DW10(phy)           _MMIO(_ICL_PORT_CL_DW(10, phy))
1774 #define  PG_SEQ_DELAY_OVERRIDE_MASK     (3 << 25)
1775 #define  PG_SEQ_DELAY_OVERRIDE_SHIFT    25
1776 #define  PG_SEQ_DELAY_OVERRIDE_ENABLE   (1 << 24)
1777 #define  PWR_UP_ALL_LANES               (0x0 << 4)
1778 #define  PWR_DOWN_LN_3_2_1              (0xe << 4)
1779 #define  PWR_DOWN_LN_3_2                (0xc << 4)
1780 #define  PWR_DOWN_LN_3                  (0x8 << 4)
1781 #define  PWR_DOWN_LN_2_1_0              (0x7 << 4)
1782 #define  PWR_DOWN_LN_1_0                (0x3 << 4)
1783 #define  PWR_DOWN_LN_3_1                (0xa << 4)
1784 #define  PWR_DOWN_LN_3_1_0              (0xb << 4)
1785 #define  PWR_DOWN_LN_MASK               (0xf << 4)
1786 #define  PWR_DOWN_LN_SHIFT              4
1787
1788 #define ICL_PORT_CL_DW12(phy)           _MMIO(_ICL_PORT_CL_DW(12, phy))
1789 #define   ICL_LANE_ENABLE_AUX           (1 << 0)
1790
1791 /* CNL/ICL Port COMP_DW registers */
1792 #define _ICL_PORT_COMP                  0x100
1793 #define _ICL_PORT_COMP_DW(dw, phy)      (_ICL_COMBOPHY(phy) + \
1794                                          _ICL_PORT_COMP + 4 * (dw))
1795
1796 #define CNL_PORT_COMP_DW0               _MMIO(0x162100)
1797 #define ICL_PORT_COMP_DW0(phy)          _MMIO(_ICL_PORT_COMP_DW(0, phy))
1798 #define   COMP_INIT                     (1 << 31)
1799
1800 #define CNL_PORT_COMP_DW1               _MMIO(0x162104)
1801 #define ICL_PORT_COMP_DW1(phy)          _MMIO(_ICL_PORT_COMP_DW(1, phy))
1802
1803 #define CNL_PORT_COMP_DW3               _MMIO(0x16210c)
1804 #define ICL_PORT_COMP_DW3(phy)          _MMIO(_ICL_PORT_COMP_DW(3, phy))
1805 #define   PROCESS_INFO_DOT_0            (0 << 26)
1806 #define   PROCESS_INFO_DOT_1            (1 << 26)
1807 #define   PROCESS_INFO_DOT_4            (2 << 26)
1808 #define   PROCESS_INFO_MASK             (7 << 26)
1809 #define   PROCESS_INFO_SHIFT            26
1810 #define   VOLTAGE_INFO_0_85V            (0 << 24)
1811 #define   VOLTAGE_INFO_0_95V            (1 << 24)
1812 #define   VOLTAGE_INFO_1_05V            (2 << 24)
1813 #define   VOLTAGE_INFO_MASK             (3 << 24)
1814 #define   VOLTAGE_INFO_SHIFT            24
1815
1816 #define ICL_PORT_COMP_DW8(phy)          _MMIO(_ICL_PORT_COMP_DW(8, phy))
1817 #define   IREFGEN                       (1 << 24)
1818
1819 #define CNL_PORT_COMP_DW9               _MMIO(0x162124)
1820 #define ICL_PORT_COMP_DW9(phy)          _MMIO(_ICL_PORT_COMP_DW(9, phy))
1821
1822 #define CNL_PORT_COMP_DW10              _MMIO(0x162128)
1823 #define ICL_PORT_COMP_DW10(phy)         _MMIO(_ICL_PORT_COMP_DW(10, phy))
1824
1825 /* CNL/ICL Port PCS registers */
1826 #define _CNL_PORT_PCS_DW1_GRP_AE        0x162304
1827 #define _CNL_PORT_PCS_DW1_GRP_B         0x162384
1828 #define _CNL_PORT_PCS_DW1_GRP_C         0x162B04
1829 #define _CNL_PORT_PCS_DW1_GRP_D         0x162B84
1830 #define _CNL_PORT_PCS_DW1_GRP_F         0x162A04
1831 #define _CNL_PORT_PCS_DW1_LN0_AE        0x162404
1832 #define _CNL_PORT_PCS_DW1_LN0_B         0x162604
1833 #define _CNL_PORT_PCS_DW1_LN0_C         0x162C04
1834 #define _CNL_PORT_PCS_DW1_LN0_D         0x162E04
1835 #define _CNL_PORT_PCS_DW1_LN0_F         0x162804
1836 #define CNL_PORT_PCS_DW1_GRP(phy)       _MMIO(_PICK(phy, \
1837                                                     _CNL_PORT_PCS_DW1_GRP_AE, \
1838                                                     _CNL_PORT_PCS_DW1_GRP_B, \
1839                                                     _CNL_PORT_PCS_DW1_GRP_C, \
1840                                                     _CNL_PORT_PCS_DW1_GRP_D, \
1841                                                     _CNL_PORT_PCS_DW1_GRP_AE, \
1842                                                     _CNL_PORT_PCS_DW1_GRP_F))
1843 #define CNL_PORT_PCS_DW1_LN0(phy)       _MMIO(_PICK(phy, \
1844                                                     _CNL_PORT_PCS_DW1_LN0_AE, \
1845                                                     _CNL_PORT_PCS_DW1_LN0_B, \
1846                                                     _CNL_PORT_PCS_DW1_LN0_C, \
1847                                                     _CNL_PORT_PCS_DW1_LN0_D, \
1848                                                     _CNL_PORT_PCS_DW1_LN0_AE, \
1849                                                     _CNL_PORT_PCS_DW1_LN0_F))
1850
1851 #define _ICL_PORT_PCS_AUX               0x300
1852 #define _ICL_PORT_PCS_GRP               0x600
1853 #define _ICL_PORT_PCS_LN(ln)            (0x800 + (ln) * 0x100)
1854 #define _ICL_PORT_PCS_DW_AUX(dw, phy)   (_ICL_COMBOPHY(phy) + \
1855                                          _ICL_PORT_PCS_AUX + 4 * (dw))
1856 #define _ICL_PORT_PCS_DW_GRP(dw, phy)   (_ICL_COMBOPHY(phy) + \
1857                                          _ICL_PORT_PCS_GRP + 4 * (dw))
1858 #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1859                                           _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1860 #define ICL_PORT_PCS_DW1_AUX(phy)       _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
1861 #define ICL_PORT_PCS_DW1_GRP(phy)       _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
1862 #define ICL_PORT_PCS_DW1_LN0(phy)       _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
1863 #define   COMMON_KEEPER_EN              (1 << 26)
1864 #define   LATENCY_OPTIM_MASK            (0x3 << 2)
1865 #define   LATENCY_OPTIM_VAL(x)          ((x) << 2)
1866
1867 /* CNL/ICL Port TX registers */
1868 #define _CNL_PORT_TX_AE_GRP_OFFSET              0x162340
1869 #define _CNL_PORT_TX_B_GRP_OFFSET               0x1623C0
1870 #define _CNL_PORT_TX_C_GRP_OFFSET               0x162B40
1871 #define _CNL_PORT_TX_D_GRP_OFFSET               0x162BC0
1872 #define _CNL_PORT_TX_F_GRP_OFFSET               0x162A40
1873 #define _CNL_PORT_TX_AE_LN0_OFFSET              0x162440
1874 #define _CNL_PORT_TX_B_LN0_OFFSET               0x162640
1875 #define _CNL_PORT_TX_C_LN0_OFFSET               0x162C40
1876 #define _CNL_PORT_TX_D_LN0_OFFSET               0x162E40
1877 #define _CNL_PORT_TX_F_LN0_OFFSET               0x162840
1878 #define _CNL_PORT_TX_DW_GRP(dw, port)   (_PICK((port), \
1879                                                _CNL_PORT_TX_AE_GRP_OFFSET, \
1880                                                _CNL_PORT_TX_B_GRP_OFFSET, \
1881                                                _CNL_PORT_TX_B_GRP_OFFSET, \
1882                                                _CNL_PORT_TX_D_GRP_OFFSET, \
1883                                                _CNL_PORT_TX_AE_GRP_OFFSET, \
1884                                                _CNL_PORT_TX_F_GRP_OFFSET) + \
1885                                                4 * (dw))
1886 #define _CNL_PORT_TX_DW_LN0(dw, port)   (_PICK((port), \
1887                                                _CNL_PORT_TX_AE_LN0_OFFSET, \
1888                                                _CNL_PORT_TX_B_LN0_OFFSET, \
1889                                                _CNL_PORT_TX_B_LN0_OFFSET, \
1890                                                _CNL_PORT_TX_D_LN0_OFFSET, \
1891                                                _CNL_PORT_TX_AE_LN0_OFFSET, \
1892                                                _CNL_PORT_TX_F_LN0_OFFSET) + \
1893                                                4 * (dw))
1894
1895 #define _ICL_PORT_TX_AUX                0x380
1896 #define _ICL_PORT_TX_GRP                0x680
1897 #define _ICL_PORT_TX_LN(ln)             (0x880 + (ln) * 0x100)
1898
1899 #define _ICL_PORT_TX_DW_AUX(dw, phy)    (_ICL_COMBOPHY(phy) + \
1900                                          _ICL_PORT_TX_AUX + 4 * (dw))
1901 #define _ICL_PORT_TX_DW_GRP(dw, phy)    (_ICL_COMBOPHY(phy) + \
1902                                          _ICL_PORT_TX_GRP + 4 * (dw))
1903 #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1904                                           _ICL_PORT_TX_LN(ln) + 4 * (dw))
1905
1906 #define CNL_PORT_TX_DW2_GRP(port)       _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
1907 #define CNL_PORT_TX_DW2_LN0(port)       _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
1908 #define ICL_PORT_TX_DW2_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
1909 #define ICL_PORT_TX_DW2_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
1910 #define ICL_PORT_TX_DW2_LN0(phy)        _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
1911 #define   SWING_SEL_UPPER(x)            (((x) >> 3) << 15)
1912 #define   SWING_SEL_UPPER_MASK          (1 << 15)
1913 #define   SWING_SEL_LOWER(x)            (((x) & 0x7) << 11)
1914 #define   SWING_SEL_LOWER_MASK          (0x7 << 11)
1915 #define   FRC_LATENCY_OPTIM_MASK        (0x7 << 8)
1916 #define   FRC_LATENCY_OPTIM_VAL(x)      ((x) << 8)
1917 #define   RCOMP_SCALAR(x)               ((x) << 0)
1918 #define   RCOMP_SCALAR_MASK             (0xFF << 0)
1919
1920 #define _CNL_PORT_TX_DW4_LN0_AE         0x162450
1921 #define _CNL_PORT_TX_DW4_LN1_AE         0x1624D0
1922 #define CNL_PORT_TX_DW4_GRP(port)       _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
1923 #define CNL_PORT_TX_DW4_LN0(port)       _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
1924 #define CNL_PORT_TX_DW4_LN(ln, port)   _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
1925                                            ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
1926                                                     _CNL_PORT_TX_DW4_LN0_AE)))
1927 #define ICL_PORT_TX_DW4_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
1928 #define ICL_PORT_TX_DW4_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
1929 #define ICL_PORT_TX_DW4_LN0(phy)        _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
1930 #define ICL_PORT_TX_DW4_LN(ln, phy)     _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
1931 #define   LOADGEN_SELECT                (1 << 31)
1932 #define   POST_CURSOR_1(x)              ((x) << 12)
1933 #define   POST_CURSOR_1_MASK            (0x3F << 12)
1934 #define   POST_CURSOR_2(x)              ((x) << 6)
1935 #define   POST_CURSOR_2_MASK            (0x3F << 6)
1936 #define   CURSOR_COEFF(x)               ((x) << 0)
1937 #define   CURSOR_COEFF_MASK             (0x3F << 0)
1938
1939 #define CNL_PORT_TX_DW5_GRP(port)       _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
1940 #define CNL_PORT_TX_DW5_LN0(port)       _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
1941 #define ICL_PORT_TX_DW5_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
1942 #define ICL_PORT_TX_DW5_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
1943 #define ICL_PORT_TX_DW5_LN0(phy)        _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
1944 #define   TX_TRAINING_EN                (1 << 31)
1945 #define   TAP2_DISABLE                  (1 << 30)
1946 #define   TAP3_DISABLE                  (1 << 29)
1947 #define   SCALING_MODE_SEL(x)           ((x) << 18)
1948 #define   SCALING_MODE_SEL_MASK         (0x7 << 18)
1949 #define   RTERM_SELECT(x)               ((x) << 3)
1950 #define   RTERM_SELECT_MASK             (0x7 << 3)
1951
1952 #define CNL_PORT_TX_DW7_GRP(port)       _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
1953 #define CNL_PORT_TX_DW7_LN0(port)       _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
1954 #define ICL_PORT_TX_DW7_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
1955 #define ICL_PORT_TX_DW7_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
1956 #define ICL_PORT_TX_DW7_LN0(phy)        _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
1957 #define ICL_PORT_TX_DW7_LN(ln, phy)     _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
1958 #define   N_SCALAR(x)                   ((x) << 24)
1959 #define   N_SCALAR_MASK                 (0x7F << 24)
1960
1961 #define _ICL_DPHY_CHKN_REG                      0x194
1962 #define ICL_DPHY_CHKN(port)                     _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
1963 #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP      REG_BIT(7)
1964
1965 #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
1966         _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
1967
1968 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1          0x16812C
1969 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1          0x16852C
1970 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2          0x16912C
1971 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2          0x16952C
1972 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3          0x16A12C
1973 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3          0x16A52C
1974 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4          0x16B12C
1975 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4          0x16B52C
1976 #define MG_TX1_LINK_PARAMS(ln, port) \
1977         MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
1978                                  MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
1979                                  MG_TX_LINK_PARAMS_TX1LN1_PORT1)
1980
1981 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1          0x1680AC
1982 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1          0x1684AC
1983 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2          0x1690AC
1984 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2          0x1694AC
1985 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3          0x16A0AC
1986 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3          0x16A4AC
1987 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4          0x16B0AC
1988 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4          0x16B4AC
1989 #define MG_TX2_LINK_PARAMS(ln, port) \
1990         MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
1991                                  MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
1992                                  MG_TX_LINK_PARAMS_TX2LN1_PORT1)
1993 #define   CRI_USE_FS32                  (1 << 5)
1994
1995 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1                0x16814C
1996 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1                0x16854C
1997 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2                0x16914C
1998 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2                0x16954C
1999 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3                0x16A14C
2000 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3                0x16A54C
2001 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4                0x16B14C
2002 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4                0x16B54C
2003 #define MG_TX1_PISO_READLOAD(ln, port) \
2004         MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2005                                  MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
2006                                  MG_TX_PISO_READLOAD_TX1LN1_PORT1)
2007
2008 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1                0x1680CC
2009 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1                0x1684CC
2010 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2                0x1690CC
2011 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2                0x1694CC
2012 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3                0x16A0CC
2013 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3                0x16A4CC
2014 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4                0x16B0CC
2015 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4                0x16B4CC
2016 #define MG_TX2_PISO_READLOAD(ln, port) \
2017         MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2018                                  MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
2019                                  MG_TX_PISO_READLOAD_TX2LN1_PORT1)
2020 #define   CRI_CALCINIT                                  (1 << 1)
2021
2022 #define MG_TX_SWINGCTRL_TX1LN0_PORT1            0x168148
2023 #define MG_TX_SWINGCTRL_TX1LN1_PORT1            0x168548
2024 #define MG_TX_SWINGCTRL_TX1LN0_PORT2            0x169148
2025 #define MG_TX_SWINGCTRL_TX1LN1_PORT2            0x169548
2026 #define MG_TX_SWINGCTRL_TX1LN0_PORT3            0x16A148
2027 #define MG_TX_SWINGCTRL_TX1LN1_PORT3            0x16A548
2028 #define MG_TX_SWINGCTRL_TX1LN0_PORT4            0x16B148
2029 #define MG_TX_SWINGCTRL_TX1LN1_PORT4            0x16B548
2030 #define MG_TX1_SWINGCTRL(ln, port) \
2031         MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2032                                  MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2033                                  MG_TX_SWINGCTRL_TX1LN1_PORT1)
2034
2035 #define MG_TX_SWINGCTRL_TX2LN0_PORT1            0x1680C8
2036 #define MG_TX_SWINGCTRL_TX2LN1_PORT1            0x1684C8
2037 #define MG_TX_SWINGCTRL_TX2LN0_PORT2            0x1690C8
2038 #define MG_TX_SWINGCTRL_TX2LN1_PORT2            0x1694C8
2039 #define MG_TX_SWINGCTRL_TX2LN0_PORT3            0x16A0C8
2040 #define MG_TX_SWINGCTRL_TX2LN1_PORT3            0x16A4C8
2041 #define MG_TX_SWINGCTRL_TX2LN0_PORT4            0x16B0C8
2042 #define MG_TX_SWINGCTRL_TX2LN1_PORT4            0x16B4C8
2043 #define MG_TX2_SWINGCTRL(ln, port) \
2044         MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2045                                  MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2046                                  MG_TX_SWINGCTRL_TX2LN1_PORT1)
2047 #define   CRI_TXDEEMPH_OVERRIDE_17_12(x)                ((x) << 0)
2048 #define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK              (0x3F << 0)
2049
2050 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1                    0x168144
2051 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1                    0x168544
2052 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2                    0x169144
2053 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2                    0x169544
2054 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3                    0x16A144
2055 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3                    0x16A544
2056 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4                    0x16B144
2057 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4                    0x16B544
2058 #define MG_TX1_DRVCTRL(ln, port) \
2059         MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2060                                  MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
2061                                  MG_TX_DRVCTRL_TX1LN1_TXPORT1)
2062
2063 #define MG_TX_DRVCTRL_TX2LN0_PORT1                      0x1680C4
2064 #define MG_TX_DRVCTRL_TX2LN1_PORT1                      0x1684C4
2065 #define MG_TX_DRVCTRL_TX2LN0_PORT2                      0x1690C4
2066 #define MG_TX_DRVCTRL_TX2LN1_PORT2                      0x1694C4
2067 #define MG_TX_DRVCTRL_TX2LN0_PORT3                      0x16A0C4
2068 #define MG_TX_DRVCTRL_TX2LN1_PORT3                      0x16A4C4
2069 #define MG_TX_DRVCTRL_TX2LN0_PORT4                      0x16B0C4
2070 #define MG_TX_DRVCTRL_TX2LN1_PORT4                      0x16B4C4
2071 #define MG_TX2_DRVCTRL(ln, port) \
2072         MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2073                                  MG_TX_DRVCTRL_TX2LN0_PORT2, \
2074                                  MG_TX_DRVCTRL_TX2LN1_PORT1)
2075 #define   CRI_TXDEEMPH_OVERRIDE_11_6(x)                 ((x) << 24)
2076 #define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK               (0x3F << 24)
2077 #define   CRI_TXDEEMPH_OVERRIDE_EN                      (1 << 22)
2078 #define   CRI_TXDEEMPH_OVERRIDE_5_0(x)                  ((x) << 16)
2079 #define   CRI_TXDEEMPH_OVERRIDE_5_0_MASK                (0x3F << 16)
2080 #define   CRI_LOADGEN_SEL(x)                            ((x) << 12)
2081 #define   CRI_LOADGEN_SEL_MASK                          (0x3 << 12)
2082
2083 #define MG_CLKHUB_LN0_PORT1                     0x16839C
2084 #define MG_CLKHUB_LN1_PORT1                     0x16879C
2085 #define MG_CLKHUB_LN0_PORT2                     0x16939C
2086 #define MG_CLKHUB_LN1_PORT2                     0x16979C
2087 #define MG_CLKHUB_LN0_PORT3                     0x16A39C
2088 #define MG_CLKHUB_LN1_PORT3                     0x16A79C
2089 #define MG_CLKHUB_LN0_PORT4                     0x16B39C
2090 #define MG_CLKHUB_LN1_PORT4                     0x16B79C
2091 #define MG_CLKHUB(ln, port) \
2092         MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \
2093                                  MG_CLKHUB_LN0_PORT2, \
2094                                  MG_CLKHUB_LN1_PORT1)
2095 #define   CFG_LOW_RATE_LKREN_EN                         (1 << 11)
2096
2097 #define MG_TX_DCC_TX1LN0_PORT1                  0x168110
2098 #define MG_TX_DCC_TX1LN1_PORT1                  0x168510
2099 #define MG_TX_DCC_TX1LN0_PORT2                  0x169110
2100 #define MG_TX_DCC_TX1LN1_PORT2                  0x169510
2101 #define MG_TX_DCC_TX1LN0_PORT3                  0x16A110
2102 #define MG_TX_DCC_TX1LN1_PORT3                  0x16A510
2103 #define MG_TX_DCC_TX1LN0_PORT4                  0x16B110
2104 #define MG_TX_DCC_TX1LN1_PORT4                  0x16B510
2105 #define MG_TX1_DCC(ln, port) \
2106         MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \
2107                                  MG_TX_DCC_TX1LN0_PORT2, \
2108                                  MG_TX_DCC_TX1LN1_PORT1)
2109 #define MG_TX_DCC_TX2LN0_PORT1                  0x168090
2110 #define MG_TX_DCC_TX2LN1_PORT1                  0x168490
2111 #define MG_TX_DCC_TX2LN0_PORT2                  0x169090
2112 #define MG_TX_DCC_TX2LN1_PORT2                  0x169490
2113 #define MG_TX_DCC_TX2LN0_PORT3                  0x16A090
2114 #define MG_TX_DCC_TX2LN1_PORT3                  0x16A490
2115 #define MG_TX_DCC_TX2LN0_PORT4                  0x16B090
2116 #define MG_TX_DCC_TX2LN1_PORT4                  0x16B490
2117 #define MG_TX2_DCC(ln, port) \
2118         MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \
2119                                  MG_TX_DCC_TX2LN0_PORT2, \
2120                                  MG_TX_DCC_TX2LN1_PORT1)
2121 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL(x)        ((x) << 25)
2122 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK      (0x3 << 25)
2123 #define   CFG_AMI_CK_DIV_OVERRIDE_EN            (1 << 24)
2124
2125 #define MG_DP_MODE_LN0_ACU_PORT1                        0x1683A0
2126 #define MG_DP_MODE_LN1_ACU_PORT1                        0x1687A0
2127 #define MG_DP_MODE_LN0_ACU_PORT2                        0x1693A0
2128 #define MG_DP_MODE_LN1_ACU_PORT2                        0x1697A0
2129 #define MG_DP_MODE_LN0_ACU_PORT3                        0x16A3A0
2130 #define MG_DP_MODE_LN1_ACU_PORT3                        0x16A7A0
2131 #define MG_DP_MODE_LN0_ACU_PORT4                        0x16B3A0
2132 #define MG_DP_MODE_LN1_ACU_PORT4                        0x16B7A0
2133 #define MG_DP_MODE(ln, port)    \
2134         MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \
2135                                  MG_DP_MODE_LN0_ACU_PORT2, \
2136                                  MG_DP_MODE_LN1_ACU_PORT1)
2137 #define   MG_DP_MODE_CFG_DP_X2_MODE                     (1 << 7)
2138 #define   MG_DP_MODE_CFG_DP_X1_MODE                     (1 << 6)
2139 #define   MG_DP_MODE_CFG_TR2PWR_GATING                  (1 << 5)
2140 #define   MG_DP_MODE_CFG_TRPWR_GATING                   (1 << 4)
2141 #define   MG_DP_MODE_CFG_CLNPWR_GATING                  (1 << 3)
2142 #define   MG_DP_MODE_CFG_DIGPWR_GATING                  (1 << 2)
2143 #define   MG_DP_MODE_CFG_GAONPWR_GATING                 (1 << 1)
2144
2145 #define MG_MISC_SUS0_PORT1                              0x168814
2146 #define MG_MISC_SUS0_PORT2                              0x169814
2147 #define MG_MISC_SUS0_PORT3                              0x16A814
2148 #define MG_MISC_SUS0_PORT4                              0x16B814
2149 #define MG_MISC_SUS0(tc_port) \
2150         _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))
2151 #define   MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK      (3 << 14)
2152 #define   MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x)        ((x) << 14)
2153 #define   MG_MISC_SUS0_CFG_TR2PWR_GATING                (1 << 12)
2154 #define   MG_MISC_SUS0_CFG_CL2PWR_GATING                (1 << 11)
2155 #define   MG_MISC_SUS0_CFG_GAONPWR_GATING               (1 << 10)
2156 #define   MG_MISC_SUS0_CFG_TRPWR_GATING                 (1 << 7)
2157 #define   MG_MISC_SUS0_CFG_CL1PWR_GATING                (1 << 6)
2158 #define   MG_MISC_SUS0_CFG_DGPWR_GATING                 (1 << 5)
2159
2160 /* The spec defines this only for BXT PHY0, but lets assume that this
2161  * would exist for PHY1 too if it had a second channel.
2162  */
2163 #define _PORT_CL2CM_DW6_A               0x162358
2164 #define _PORT_CL2CM_DW6_BC              0x6C358
2165 #define BXT_PORT_CL2CM_DW6(phy)         _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2166 #define   DW6_OLDO_DYN_PWR_DOWN_EN      (1 << 28)
2167
2168 #define FIA1_BASE                       0x163000
2169 #define FIA2_BASE                       0x16E000
2170 #define FIA3_BASE                       0x16F000
2171 #define _FIA(fia)                       _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
2172 #define _MMIO_FIA(fia, off)             _MMIO(_FIA(fia) + (off))
2173
2174 /* ICL PHY DFLEX registers */
2175 #define PORT_TX_DFLEXDPMLE1(fia)        _MMIO_FIA((fia),  0x008C0)
2176 #define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)     (0xf << (4 * (tc_port)))
2177 #define   DFLEXDPMLE1_DPMLETC_ML0(tc_port)      (1 << (4 * (tc_port)))
2178 #define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port)    (3 << (4 * (tc_port)))
2179 #define   DFLEXDPMLE1_DPMLETC_ML3(tc_port)      (8 << (4 * (tc_port)))
2180 #define   DFLEXDPMLE1_DPMLETC_ML3_2(tc_port)    (12 << (4 * (tc_port)))
2181 #define   DFLEXDPMLE1_DPMLETC_ML3_0(tc_port)    (15 << (4 * (tc_port)))
2182
2183 /* BXT PHY Ref registers */
2184 #define _PORT_REF_DW3_A                 0x16218C
2185 #define _PORT_REF_DW3_BC                0x6C18C
2186 #define   GRC_DONE                      (1 << 22)
2187 #define BXT_PORT_REF_DW3(phy)           _BXT_PHY((phy), _PORT_REF_DW3_BC)
2188
2189 #define _PORT_REF_DW6_A                 0x162198
2190 #define _PORT_REF_DW6_BC                0x6C198
2191 #define   GRC_CODE_SHIFT                24
2192 #define   GRC_CODE_MASK                 (0xFF << GRC_CODE_SHIFT)
2193 #define   GRC_CODE_FAST_SHIFT           16
2194 #define   GRC_CODE_FAST_MASK            (0xFF << GRC_CODE_FAST_SHIFT)
2195 #define   GRC_CODE_SLOW_SHIFT           8
2196 #define   GRC_CODE_SLOW_MASK            (0xFF << GRC_CODE_SLOW_SHIFT)
2197 #define   GRC_CODE_NOM_MASK             0xFF
2198 #define BXT_PORT_REF_DW6(phy)           _BXT_PHY((phy), _PORT_REF_DW6_BC)
2199
2200 #define _PORT_REF_DW8_A                 0x1621A0
2201 #define _PORT_REF_DW8_BC                0x6C1A0
2202 #define   GRC_DIS                       (1 << 15)
2203 #define   GRC_RDY_OVRD                  (1 << 1)
2204 #define BXT_PORT_REF_DW8(phy)           _BXT_PHY((phy), _PORT_REF_DW8_BC)
2205
2206 /* BXT PHY PCS registers */
2207 #define _PORT_PCS_DW10_LN01_A           0x162428
2208 #define _PORT_PCS_DW10_LN01_B           0x6C428
2209 #define _PORT_PCS_DW10_LN01_C           0x6C828
2210 #define _PORT_PCS_DW10_GRP_A            0x162C28
2211 #define _PORT_PCS_DW10_GRP_B            0x6CC28
2212 #define _PORT_PCS_DW10_GRP_C            0x6CE28
2213 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2214                                                          _PORT_PCS_DW10_LN01_B, \
2215                                                          _PORT_PCS_DW10_LN01_C)
2216 #define BXT_PORT_PCS_DW10_GRP(phy, ch)  _MMIO_BXT_PHY_CH(phy, ch, \
2217                                                          _PORT_PCS_DW10_GRP_B, \
2218                                                          _PORT_PCS_DW10_GRP_C)
2219
2220 #define   TX2_SWING_CALC_INIT           (1 << 31)
2221 #define   TX1_SWING_CALC_INIT           (1 << 30)
2222
2223 #define _PORT_PCS_DW12_LN01_A           0x162430
2224 #define _PORT_PCS_DW12_LN01_B           0x6C430
2225 #define _PORT_PCS_DW12_LN01_C           0x6C830
2226 #define _PORT_PCS_DW12_LN23_A           0x162630
2227 #define _PORT_PCS_DW12_LN23_B           0x6C630
2228 #define _PORT_PCS_DW12_LN23_C           0x6CA30
2229 #define _PORT_PCS_DW12_GRP_A            0x162c30
2230 #define _PORT_PCS_DW12_GRP_B            0x6CC30
2231 #define _PORT_PCS_DW12_GRP_C            0x6CE30
2232 #define   LANESTAGGER_STRAP_OVRD        (1 << 6)
2233 #define   LANE_STAGGER_MASK             0x1F
2234 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2235                                                          _PORT_PCS_DW12_LN01_B, \
2236                                                          _PORT_PCS_DW12_LN01_C)
2237 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2238                                                          _PORT_PCS_DW12_LN23_B, \
2239                                                          _PORT_PCS_DW12_LN23_C)
2240 #define BXT_PORT_PCS_DW12_GRP(phy, ch)  _MMIO_BXT_PHY_CH(phy, ch, \
2241                                                          _PORT_PCS_DW12_GRP_B, \
2242                                                          _PORT_PCS_DW12_GRP_C)
2243
2244 /* BXT PHY TX registers */
2245 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +       \
2246                                           ((lane) & 1) * 0x80)
2247
2248 #define _PORT_TX_DW2_LN0_A              0x162508
2249 #define _PORT_TX_DW2_LN0_B              0x6C508
2250 #define _PORT_TX_DW2_LN0_C              0x6C908
2251 #define _PORT_TX_DW2_GRP_A              0x162D08
2252 #define _PORT_TX_DW2_GRP_B              0x6CD08
2253 #define _PORT_TX_DW2_GRP_C              0x6CF08
2254 #define BXT_PORT_TX_DW2_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2255                                                          _PORT_TX_DW2_LN0_B, \
2256                                                          _PORT_TX_DW2_LN0_C)
2257 #define BXT_PORT_TX_DW2_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2258                                                          _PORT_TX_DW2_GRP_B, \
2259                                                          _PORT_TX_DW2_GRP_C)
2260 #define   MARGIN_000_SHIFT              16
2261 #define   MARGIN_000                    (0xFF << MARGIN_000_SHIFT)
2262 #define   UNIQ_TRANS_SCALE_SHIFT        8
2263 #define   UNIQ_TRANS_SCALE              (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2264
2265 #define _PORT_TX_DW3_LN0_A              0x16250C
2266 #define _PORT_TX_DW3_LN0_B              0x6C50C
2267 #define _PORT_TX_DW3_LN0_C              0x6C90C
2268 #define _PORT_TX_DW3_GRP_A              0x162D0C
2269 #define _PORT_TX_DW3_GRP_B              0x6CD0C
2270 #define _PORT_TX_DW3_GRP_C              0x6CF0C
2271 #define BXT_PORT_TX_DW3_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2272                                                          _PORT_TX_DW3_LN0_B, \
2273                                                          _PORT_TX_DW3_LN0_C)
2274 #define BXT_PORT_TX_DW3_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2275                                                          _PORT_TX_DW3_GRP_B, \
2276                                                          _PORT_TX_DW3_GRP_C)
2277 #define   SCALE_DCOMP_METHOD            (1 << 26)
2278 #define   UNIQUE_TRANGE_EN_METHOD       (1 << 27)
2279
2280 #define _PORT_TX_DW4_LN0_A              0x162510
2281 #define _PORT_TX_DW4_LN0_B              0x6C510
2282 #define _PORT_TX_DW4_LN0_C              0x6C910
2283 #define _PORT_TX_DW4_GRP_A              0x162D10
2284 #define _PORT_TX_DW4_GRP_B              0x6CD10
2285 #define _PORT_TX_DW4_GRP_C              0x6CF10
2286 #define BXT_PORT_TX_DW4_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2287                                                          _PORT_TX_DW4_LN0_B, \
2288                                                          _PORT_TX_DW4_LN0_C)
2289 #define BXT_PORT_TX_DW4_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2290                                                          _PORT_TX_DW4_GRP_B, \
2291                                                          _PORT_TX_DW4_GRP_C)
2292 #define   DEEMPH_SHIFT                  24
2293 #define   DE_EMPHASIS                   (0xFF << DEEMPH_SHIFT)
2294
2295 #define _PORT_TX_DW5_LN0_A              0x162514
2296 #define _PORT_TX_DW5_LN0_B              0x6C514
2297 #define _PORT_TX_DW5_LN0_C              0x6C914
2298 #define _PORT_TX_DW5_GRP_A              0x162D14
2299 #define _PORT_TX_DW5_GRP_B              0x6CD14
2300 #define _PORT_TX_DW5_GRP_C              0x6CF14
2301 #define BXT_PORT_TX_DW5_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2302                                                          _PORT_TX_DW5_LN0_B, \
2303                                                          _PORT_TX_DW5_LN0_C)
2304 #define BXT_PORT_TX_DW5_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2305                                                          _PORT_TX_DW5_GRP_B, \
2306                                                          _PORT_TX_DW5_GRP_C)
2307 #define   DCC_DELAY_RANGE_1             (1 << 9)
2308 #define   DCC_DELAY_RANGE_2             (1 << 8)
2309
2310 #define _PORT_TX_DW14_LN0_A             0x162538
2311 #define _PORT_TX_DW14_LN0_B             0x6C538
2312 #define _PORT_TX_DW14_LN0_C             0x6C938
2313 #define   LATENCY_OPTIM_SHIFT           30
2314 #define   LATENCY_OPTIM                 (1 << LATENCY_OPTIM_SHIFT)
2315 #define BXT_PORT_TX_DW14_LN(phy, ch, lane)                              \
2316         _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B,                 \
2317                                    _PORT_TX_DW14_LN0_C) +               \
2318               _BXT_LANE_OFFSET(lane))
2319
2320 /* UAIMI scratch pad register 1 */
2321 #define UAIMI_SPR1                      _MMIO(0x4F074)
2322 /* SKL VccIO mask */
2323 #define SKL_VCCIO_MASK                  0x1
2324 /* SKL balance leg register */
2325 #define DISPIO_CR_TX_BMU_CR0            _MMIO(0x6C00C)
2326 /* I_boost values */
2327 #define BALANCE_LEG_SHIFT(port)         (8 + 3 * (port))
2328 #define BALANCE_LEG_MASK(port)          (7 << (8 + 3 * (port)))
2329 /* Balance leg disable bits */
2330 #define BALANCE_LEG_DISABLE_SHIFT       23
2331 #define BALANCE_LEG_DISABLE(port)       (1 << (23 + (port)))
2332
2333 /*
2334  * Fence registers
2335  * [0-7]  @ 0x2000 gen2,gen3
2336  * [8-15] @ 0x3000 945,g33,pnv
2337  *
2338  * [0-15] @ 0x3000 gen4,gen5
2339  *
2340  * [0-15] @ 0x100000 gen6,vlv,chv
2341  * [0-31] @ 0x100000 gen7+
2342  */
2343 #define FENCE_REG(i)                    _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2344 #define   I830_FENCE_START_MASK         0x07f80000
2345 #define   I830_FENCE_TILING_Y_SHIFT     12
2346 #define   I830_FENCE_SIZE_BITS(size)    ((ffs((size) >> 19) - 1) << 8)
2347 #define   I830_FENCE_PITCH_SHIFT        4
2348 #define   I830_FENCE_REG_VALID          (1 << 0)
2349 #define   I915_FENCE_MAX_PITCH_VAL      4
2350 #define   I830_FENCE_MAX_PITCH_VAL      6
2351 #define   I830_FENCE_MAX_SIZE_VAL       (1 << 8)
2352
2353 #define   I915_FENCE_START_MASK         0x0ff00000
2354 #define   I915_FENCE_SIZE_BITS(size)    ((ffs((size) >> 20) - 1) << 8)
2355
2356 #define FENCE_REG_965_LO(i)             _MMIO(0x03000 + (i) * 8)
2357 #define FENCE_REG_965_HI(i)             _MMIO(0x03000 + (i) * 8 + 4)
2358 #define   I965_FENCE_PITCH_SHIFT        2
2359 #define   I965_FENCE_TILING_Y_SHIFT     1
2360 #define   I965_FENCE_REG_VALID          (1 << 0)
2361 #define   I965_FENCE_MAX_PITCH_VAL      0x0400
2362
2363 #define FENCE_REG_GEN6_LO(i)            _MMIO(0x100000 + (i) * 8)
2364 #define FENCE_REG_GEN6_HI(i)            _MMIO(0x100000 + (i) * 8 + 4)
2365 #define   GEN6_FENCE_PITCH_SHIFT        32
2366 #define   GEN7_FENCE_MAX_PITCH_VAL      0x0800
2367
2368
2369 /* control register for cpu gtt access */
2370 #define TILECTL                         _MMIO(0x101000)
2371 #define   TILECTL_SWZCTL                        (1 << 0)
2372 #define   TILECTL_TLBPF                 (1 << 1)
2373 #define   TILECTL_TLB_PREFETCH_DIS      (1 << 2)
2374 #define   TILECTL_BACKSNOOP_DIS         (1 << 3)
2375
2376 /*
2377  * Instruction and interrupt control regs
2378  */
2379 #define PGTBL_CTL       _MMIO(0x02020)
2380 #define   PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2381 #define   PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
2382 #define PGTBL_ER        _MMIO(0x02024)
2383 #define PRB0_BASE       (0x2030 - 0x30)
2384 #define PRB1_BASE       (0x2040 - 0x30) /* 830,gen3 */
2385 #define PRB2_BASE       (0x2050 - 0x30) /* gen3 */
2386 #define SRB0_BASE       (0x2100 - 0x30) /* gen2 */
2387 #define SRB1_BASE       (0x2110 - 0x30) /* gen2 */
2388 #define SRB2_BASE       (0x2120 - 0x30) /* 830 */
2389 #define SRB3_BASE       (0x2130 - 0x30) /* 830 */
2390 #define RENDER_RING_BASE        0x02000
2391 #define BSD_RING_BASE           0x04000
2392 #define GEN6_BSD_RING_BASE      0x12000
2393 #define GEN8_BSD2_RING_BASE     0x1c000
2394 #define GEN11_BSD_RING_BASE     0x1c0000
2395 #define GEN11_BSD2_RING_BASE    0x1c4000
2396 #define GEN11_BSD3_RING_BASE    0x1d0000
2397 #define GEN11_BSD4_RING_BASE    0x1d4000
2398 #define VEBOX_RING_BASE         0x1a000
2399 #define GEN11_VEBOX_RING_BASE           0x1c8000
2400 #define GEN11_VEBOX2_RING_BASE          0x1d8000
2401 #define BLT_RING_BASE           0x22000
2402 #define RING_TAIL(base)         _MMIO((base) + 0x30)
2403 #define RING_HEAD(base)         _MMIO((base) + 0x34)
2404 #define RING_START(base)        _MMIO((base) + 0x38)
2405 #define RING_CTL(base)          _MMIO((base) + 0x3c)
2406 #define   RING_CTL_SIZE(size)   ((size) - PAGE_SIZE) /* in bytes -> pages */
2407 #define RING_SYNC_0(base)       _MMIO((base) + 0x40)
2408 #define RING_SYNC_1(base)       _MMIO((base) + 0x44)
2409 #define RING_SYNC_2(base)       _MMIO((base) + 0x48)
2410 #define GEN6_RVSYNC     (RING_SYNC_0(RENDER_RING_BASE))
2411 #define GEN6_RBSYNC     (RING_SYNC_1(RENDER_RING_BASE))
2412 #define GEN6_RVESYNC    (RING_SYNC_2(RENDER_RING_BASE))
2413 #define GEN6_VBSYNC     (RING_SYNC_0(GEN6_BSD_RING_BASE))
2414 #define GEN6_VRSYNC     (RING_SYNC_1(GEN6_BSD_RING_BASE))
2415 #define GEN6_VVESYNC    (RING_SYNC_2(GEN6_BSD_RING_BASE))
2416 #define GEN6_BRSYNC     (RING_SYNC_0(BLT_RING_BASE))
2417 #define GEN6_BVSYNC     (RING_SYNC_1(BLT_RING_BASE))
2418 #define GEN6_BVESYNC    (RING_SYNC_2(BLT_RING_BASE))
2419 #define GEN6_VEBSYNC    (RING_SYNC_0(VEBOX_RING_BASE))
2420 #define GEN6_VERSYNC    (RING_SYNC_1(VEBOX_RING_BASE))
2421 #define GEN6_VEVSYNC    (RING_SYNC_2(VEBOX_RING_BASE))
2422 #define GEN6_NOSYNC     INVALID_MMIO_REG
2423 #define RING_PSMI_CTL(base)     _MMIO((base) + 0x50)
2424 #define RING_MAX_IDLE(base)     _MMIO((base) + 0x54)
2425 #define RING_HWS_PGA(base)      _MMIO((base) + 0x80)
2426 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2427 #define RING_RESET_CTL(base)    _MMIO((base) + 0xd0)
2428 #define   RESET_CTL_CAT_ERROR      REG_BIT(2)
2429 #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
2430 #define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
2431
2432 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2433
2434 #define HSW_GTT_CACHE_EN        _MMIO(0x4024)
2435 #define   GTT_CACHE_EN_ALL      0xF0007FFF
2436 #define GEN7_WR_WATERMARK       _MMIO(0x4028)
2437 #define GEN7_GFX_PRIO_CTRL      _MMIO(0x402C)
2438 #define ARB_MODE                _MMIO(0x4030)
2439 #define   ARB_MODE_SWIZZLE_SNB  (1 << 4)
2440 #define   ARB_MODE_SWIZZLE_IVB  (1 << 5)
2441 #define GEN7_GFX_PEND_TLB0      _MMIO(0x4034)
2442 #define GEN7_GFX_PEND_TLB1      _MMIO(0x4038)
2443 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2444 #define GEN7_LRA_LIMITS(i)      _MMIO(0x403C + (i) * 4)
2445 #define GEN7_LRA_LIMITS_REG_NUM 13
2446 #define GEN7_MEDIA_MAX_REQ_COUNT        _MMIO(0x4070)
2447 #define GEN7_GFX_MAX_REQ_COUNT          _MMIO(0x4074)
2448
2449 #define GAMTARBMODE             _MMIO(0x04a08)
2450 #define   ARB_MODE_BWGTLB_DISABLE (1 << 9)
2451 #define   ARB_MODE_SWIZZLE_BDW  (1 << 1)
2452 #define RENDER_HWS_PGA_GEN7     _MMIO(0x04080)
2453 #define RING_FAULT_REG(engine)  _MMIO(0x4094 + 0x100 * (engine)->hw_id)
2454 #define GEN8_RING_FAULT_REG     _MMIO(0x4094)
2455 #define GEN12_RING_FAULT_REG    _MMIO(0xcec4)
2456 #define   GEN8_RING_FAULT_ENGINE_ID(x)  (((x) >> 12) & 0x7)
2457 #define   RING_FAULT_GTTSEL_MASK (1 << 11)
2458 #define   RING_FAULT_SRCID(x)   (((x) >> 3) & 0xff)
2459 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2460 #define   RING_FAULT_VALID      (1 << 0)
2461 #define DONE_REG                _MMIO(0x40b0)
2462 #define GEN8_PRIVATE_PAT_LO     _MMIO(0x40e0)
2463 #define GEN8_PRIVATE_PAT_HI     _MMIO(0x40e0 + 4)
2464 #define GEN10_PAT_INDEX(index)  _MMIO(0x40e0 + (index) * 4)
2465 #define GEN12_PAT_INDEX(index)  _MMIO(0x4800 + (index) * 4)
2466 #define BSD_HWS_PGA_GEN7        _MMIO(0x04180)
2467 #define BLT_HWS_PGA_GEN7        _MMIO(0x04280)
2468 #define VEBOX_HWS_PGA_GEN7      _MMIO(0x04380)
2469 #define RING_ACTHD(base)        _MMIO((base) + 0x74)
2470 #define RING_ACTHD_UDW(base)    _MMIO((base) + 0x5c)
2471 #define RING_NOPID(base)        _MMIO((base) + 0x94)
2472 #define RING_IMR(base)          _MMIO((base) + 0xa8)
2473 #define RING_HWSTAM(base)       _MMIO((base) + 0x98)
2474 #define RING_TIMESTAMP(base)            _MMIO((base) + 0x358)
2475 #define RING_TIMESTAMP_UDW(base)        _MMIO((base) + 0x358 + 4)
2476 #define   TAIL_ADDR             0x001FFFF8
2477 #define   HEAD_WRAP_COUNT       0xFFE00000
2478 #define   HEAD_WRAP_ONE         0x00200000
2479 #define   HEAD_ADDR             0x001FFFFC
2480 #define   RING_NR_PAGES         0x001FF000
2481 #define   RING_REPORT_MASK      0x00000006
2482 #define   RING_REPORT_64K       0x00000002
2483 #define   RING_REPORT_128K      0x00000004
2484 #define   RING_NO_REPORT        0x00000000
2485 #define   RING_VALID_MASK       0x00000001
2486 #define   RING_VALID            0x00000001
2487 #define   RING_INVALID          0x00000000
2488 #define   RING_WAIT_I8XX        (1 << 0) /* gen2, PRBx_HEAD */
2489 #define   RING_WAIT             (1 << 11) /* gen3+, PRBx_CTL */
2490 #define   RING_WAIT_SEMAPHORE   (1 << 10) /* gen6+ */
2491
2492 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2493 #define   RING_FORCE_TO_NONPRIV_ACCESS_RW       (0 << 28)    /* CFL+ & Gen11+ */
2494 #define   RING_FORCE_TO_NONPRIV_ACCESS_RD       (1 << 28)
2495 #define   RING_FORCE_TO_NONPRIV_ACCESS_WR       (2 << 28)
2496 #define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID  (3 << 28)
2497 #define   RING_FORCE_TO_NONPRIV_ACCESS_MASK     (3 << 28)
2498 #define   RING_FORCE_TO_NONPRIV_RANGE_1         (0 << 0)     /* CFL+ & Gen11+ */
2499 #define   RING_FORCE_TO_NONPRIV_RANGE_4         (1 << 0)
2500 #define   RING_FORCE_TO_NONPRIV_RANGE_16        (2 << 0)
2501 #define   RING_FORCE_TO_NONPRIV_RANGE_64        (3 << 0)
2502 #define   RING_FORCE_TO_NONPRIV_RANGE_MASK      (3 << 0)
2503 #define   RING_FORCE_TO_NONPRIV_MASK_VALID      \
2504                                         (RING_FORCE_TO_NONPRIV_RANGE_MASK \
2505                                         | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
2506 #define   RING_MAX_NONPRIV_SLOTS  12
2507
2508 #define GEN7_TLB_RD_ADDR        _MMIO(0x4700)
2509
2510 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2511 #define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS   (1 << 18)
2512
2513 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2514 #define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2515 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE       (1 << 7)
2516
2517 #define GAMT_CHKN_BIT_REG       _MMIO(0x4ab8)
2518 #define   GAMT_CHKN_DISABLE_L3_COH_PIPE                 (1 << 31)
2519 #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING      (1 << 28)
2520 #define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT        (1 << 24)
2521
2522 #define GEN8_RTCR       _MMIO(0x4260)
2523 #define GEN8_M1TCR      _MMIO(0x4264)
2524 #define GEN8_M2TCR      _MMIO(0x4268)
2525 #define GEN8_BTCR       _MMIO(0x426c)
2526 #define GEN8_VTCR       _MMIO(0x4270)
2527
2528 #if 0
2529 #define PRB0_TAIL       _MMIO(0x2030)
2530 #define PRB0_HEAD       _MMIO(0x2034)
2531 #define PRB0_START      _MMIO(0x2038)
2532 #define PRB0_CTL        _MMIO(0x203c)
2533 #define PRB1_TAIL       _MMIO(0x2040) /* 915+ only */
2534 #define PRB1_HEAD       _MMIO(0x2044) /* 915+ only */
2535 #define PRB1_START      _MMIO(0x2048) /* 915+ only */
2536 #define PRB1_CTL        _MMIO(0x204c) /* 915+ only */
2537 #endif
2538 #define IPEIR_I965      _MMIO(0x2064)
2539 #define IPEHR_I965      _MMIO(0x2068)
2540 #define GEN7_SC_INSTDONE        _MMIO(0x7100)
2541 #define GEN7_SAMPLER_INSTDONE   _MMIO(0xe160)
2542 #define GEN7_ROW_INSTDONE       _MMIO(0xe164)
2543 #define GEN8_MCR_SELECTOR               _MMIO(0xfdc)
2544 #define   GEN8_MCR_SLICE(slice)         (((slice) & 3) << 26)
2545 #define   GEN8_MCR_SLICE_MASK           GEN8_MCR_SLICE(3)
2546 #define   GEN8_MCR_SUBSLICE(subslice)   (((subslice) & 3) << 24)
2547 #define   GEN8_MCR_SUBSLICE_MASK        GEN8_MCR_SUBSLICE(3)
2548 #define   GEN11_MCR_SLICE(slice)        (((slice) & 0xf) << 27)
2549 #define   GEN11_MCR_SLICE_MASK          GEN11_MCR_SLICE(0xf)
2550 #define   GEN11_MCR_SUBSLICE(subslice)  (((subslice) & 0x7) << 24)
2551 #define   GEN11_MCR_SUBSLICE_MASK       GEN11_MCR_SUBSLICE(0x7)
2552 #define RING_IPEIR(base)        _MMIO((base) + 0x64)
2553 #define RING_IPEHR(base)        _MMIO((base) + 0x68)
2554 /*
2555  * On GEN4, only the render ring INSTDONE exists and has a different
2556  * layout than the GEN7+ version.
2557  * The GEN2 counterpart of this register is GEN2_INSTDONE.
2558  */
2559 #define RING_INSTDONE(base)     _MMIO((base) + 0x6c)
2560 #define RING_INSTPS(base)       _MMIO((base) + 0x70)
2561 #define RING_DMA_FADD(base)     _MMIO((base) + 0x78)
2562 #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
2563 #define RING_INSTPM(base)       _MMIO((base) + 0xc0)
2564 #define RING_MI_MODE(base)      _MMIO((base) + 0x9c)
2565 #define INSTPS          _MMIO(0x2070) /* 965+ only */
2566 #define GEN4_INSTDONE1  _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2567 #define ACTHD_I965      _MMIO(0x2074)
2568 #define HWS_PGA         _MMIO(0x2080)
2569 #define HWS_ADDRESS_MASK        0xfffff000
2570 #define HWS_START_ADDRESS_SHIFT 4
2571 #define PWRCTXA         _MMIO(0x2088) /* 965GM+ only */
2572 #define   PWRCTX_EN     (1 << 0)
2573 #define IPEIR(base)     _MMIO((base) + 0x88)
2574 #define IPEHR(base)     _MMIO((base) + 0x8c)
2575 #define GEN2_INSTDONE   _MMIO(0x2090)
2576 #define NOPID           _MMIO(0x2094)
2577 #define HWSTAM          _MMIO(0x2098)
2578 #define DMA_FADD_I8XX(base)     _MMIO((base) + 0xd0)
2579 #define RING_BBSTATE(base)      _MMIO((base) + 0x110)
2580 #define   RING_BB_PPGTT         (1 << 5)
2581 #define RING_SBBADDR(base)      _MMIO((base) + 0x114) /* hsw+ */
2582 #define RING_SBBSTATE(base)     _MMIO((base) + 0x118) /* hsw+ */
2583 #define RING_SBBADDR_UDW(base)  _MMIO((base) + 0x11c) /* gen8+ */
2584 #define RING_BBADDR(base)       _MMIO((base) + 0x140)
2585 #define RING_BBADDR_UDW(base)   _MMIO((base) + 0x168) /* gen8+ */
2586 #define RING_BB_PER_CTX_PTR(base)       _MMIO((base) + 0x1c0) /* gen8+ */
2587 #define RING_INDIRECT_CTX(base)         _MMIO((base) + 0x1c4) /* gen8+ */
2588 #define RING_INDIRECT_CTX_OFFSET(base)  _MMIO((base) + 0x1c8) /* gen8+ */
2589 #define RING_CTX_TIMESTAMP(base)        _MMIO((base) + 0x3a8) /* gen8+ */
2590
2591 #define ERROR_GEN6      _MMIO(0x40a0)
2592 #define GEN7_ERR_INT    _MMIO(0x44040)
2593 #define   ERR_INT_POISON                (1 << 31)
2594 #define   ERR_INT_MMIO_UNCLAIMED        (1 << 13)
2595 #define   ERR_INT_PIPE_CRC_DONE_C       (1 << 8)
2596 #define   ERR_INT_FIFO_UNDERRUN_C       (1 << 6)
2597 #define   ERR_INT_PIPE_CRC_DONE_B       (1 << 5)
2598 #define   ERR_INT_FIFO_UNDERRUN_B       (1 << 3)
2599 #define   ERR_INT_PIPE_CRC_DONE_A       (1 << 2)
2600 #define   ERR_INT_PIPE_CRC_DONE(pipe)   (1 << (2 + (pipe) * 3))
2601 #define   ERR_INT_FIFO_UNDERRUN_A       (1 << 0)
2602 #define   ERR_INT_FIFO_UNDERRUN(pipe)   (1 << ((pipe) * 3))
2603
2604 #define GEN8_FAULT_TLB_DATA0            _MMIO(0x4b10)
2605 #define GEN8_FAULT_TLB_DATA1            _MMIO(0x4b14)
2606 #define GEN12_FAULT_TLB_DATA0           _MMIO(0xceb8)
2607 #define GEN12_FAULT_TLB_DATA1           _MMIO(0xcebc)
2608 #define   FAULT_VA_HIGH_BITS            (0xf << 0)
2609 #define   FAULT_GTT_SEL                 (1 << 4)
2610
2611 #define GEN12_GFX_TLB_INV_CR    _MMIO(0xced8)
2612 #define GEN12_VD_TLB_INV_CR     _MMIO(0xcedc)
2613 #define GEN12_VE_TLB_INV_CR     _MMIO(0xcee0)
2614 #define GEN12_BLT_TLB_INV_CR    _MMIO(0xcee4)
2615
2616 #define FPGA_DBG                _MMIO(0x42300)
2617 #define   FPGA_DBG_RM_NOCLAIM   (1 << 31)
2618
2619 #define CLAIM_ER                _MMIO(VLV_DISPLAY_BASE + 0x2028)
2620 #define   CLAIM_ER_CLR          (1 << 31)
2621 #define   CLAIM_ER_OVERFLOW     (1 << 16)
2622 #define   CLAIM_ER_CTR_MASK     0xffff
2623
2624 #define DERRMR          _MMIO(0x44050)
2625 /* Note that HBLANK events are reserved on bdw+ */
2626 #define   DERRMR_PIPEA_SCANLINE         (1 << 0)
2627 #define   DERRMR_PIPEA_PRI_FLIP_DONE    (1 << 1)
2628 #define   DERRMR_PIPEA_SPR_FLIP_DONE    (1 << 2)
2629 #define   DERRMR_PIPEA_VBLANK           (1 << 3)
2630 #define   DERRMR_PIPEA_HBLANK           (1 << 5)
2631 #define   DERRMR_PIPEB_SCANLINE         (1 << 8)
2632 #define   DERRMR_PIPEB_PRI_FLIP_DONE    (1 << 9)
2633 #define   DERRMR_PIPEB_SPR_FLIP_DONE    (1 << 10)
2634 #define   DERRMR_PIPEB_VBLANK           (1 << 11)
2635 #define   DERRMR_PIPEB_HBLANK           (1 << 13)
2636 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2637 #define   DERRMR_PIPEC_SCANLINE         (1 << 14)
2638 #define   DERRMR_PIPEC_PRI_FLIP_DONE    (1 << 15)
2639 #define   DERRMR_PIPEC_SPR_FLIP_DONE    (1 << 20)
2640 #define   DERRMR_PIPEC_VBLANK           (1 << 21)
2641 #define   DERRMR_PIPEC_HBLANK           (1 << 22)
2642
2643
2644 /* GM45+ chicken bits -- debug workaround bits that may be required
2645  * for various sorts of correct behavior.  The top 16 bits of each are
2646  * the enables for writing to the corresponding low bit.
2647  */
2648 #define _3D_CHICKEN     _MMIO(0x2084)
2649 #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB      (1 << 10)
2650 #define _3D_CHICKEN2    _MMIO(0x208c)
2651
2652 #define FF_SLICE_CHICKEN        _MMIO(0x2088)
2653 #define  FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX       (1 << 1)
2654
2655 /* Disables pipelining of read flushes past the SF-WIZ interface.
2656  * Required on all Ironlake steppings according to the B-Spec, but the
2657  * particular danger of not doing so is not specified.
2658  */
2659 # define _3D_CHICKEN2_WM_READ_PIPELINED                 (1 << 14)
2660 #define _3D_CHICKEN3    _MMIO(0x2090)
2661 #define  _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX            (1 << 12)
2662 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL             (1 << 10)
2663 #define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE        (1 << 5)
2664 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL          (1 << 5)
2665 #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)       ((x) << 1) /* gen8+ */
2666 #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH   (1 << 1) /* gen6 */
2667
2668 #define MI_MODE         _MMIO(0x209c)
2669 # define VS_TIMER_DISPATCH                              (1 << 6)
2670 # define MI_FLUSH_ENABLE                                (1 << 12)
2671 # define ASYNC_FLIP_PERF_DISABLE                        (1 << 14)
2672 # define MODE_IDLE                                      (1 << 9)
2673 # define STOP_RING                                      (1 << 8)
2674
2675 #define GEN6_GT_MODE    _MMIO(0x20d0)
2676 #define GEN7_GT_MODE    _MMIO(0x7008)
2677 #define   GEN6_WIZ_HASHING(hi, lo)                      (((hi) << 9) | ((lo) << 7))
2678 #define   GEN6_WIZ_HASHING_8x8                          GEN6_WIZ_HASHING(0, 0)
2679 #define   GEN6_WIZ_HASHING_8x4                          GEN6_WIZ_HASHING(0, 1)
2680 #define   GEN6_WIZ_HASHING_16x4                         GEN6_WIZ_HASHING(1, 0)
2681 #define   GEN6_WIZ_HASHING_MASK                         GEN6_WIZ_HASHING(1, 1)
2682 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE             (1 << 5)
2683 #define   GEN9_IZ_HASHING_MASK(slice)                   (0x3 << ((slice) * 2))
2684 #define   GEN9_IZ_HASHING(slice, val)                   ((val) << ((slice) * 2))
2685
2686 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2687 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2688 #define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2689 #define   GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2690
2691 /* WaClearTdlStateAckDirtyBits */
2692 #define GEN8_STATE_ACK          _MMIO(0x20F0)
2693 #define GEN9_STATE_ACK_SLICE1   _MMIO(0x20F8)
2694 #define GEN9_STATE_ACK_SLICE2   _MMIO(0x2100)
2695 #define   GEN9_STATE_ACK_TDL0 (1 << 12)
2696 #define   GEN9_STATE_ACK_TDL1 (1 << 13)
2697 #define   GEN9_STATE_ACK_TDL2 (1 << 14)
2698 #define   GEN9_STATE_ACK_TDL3 (1 << 15)
2699 #define   GEN9_SUBSLICE_TDL_ACK_BITS \
2700         (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2701          GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2702
2703 #define GFX_MODE        _MMIO(0x2520)
2704 #define GFX_MODE_GEN7   _MMIO(0x229c)
2705 #define RING_MODE_GEN7(base)    _MMIO((base) + 0x29c)
2706 #define   GFX_RUN_LIST_ENABLE           (1 << 15)
2707 #define   GFX_INTERRUPT_STEERING        (1 << 14)
2708 #define   GFX_TLB_INVALIDATE_EXPLICIT   (1 << 13)
2709 #define   GFX_SURFACE_FAULT_ENABLE      (1 << 12)
2710 #define   GFX_REPLAY_MODE               (1 << 11)
2711 #define   GFX_PSMI_GRANULARITY          (1 << 10)
2712 #define   GFX_PPGTT_ENABLE              (1 << 9)
2713 #define   GEN8_GFX_PPGTT_48B            (1 << 7)
2714
2715 #define   GFX_FORWARD_VBLANK_MASK       (3 << 5)
2716 #define   GFX_FORWARD_VBLANK_NEVER      (0 << 5)
2717 #define   GFX_FORWARD_VBLANK_ALWAYS     (1 << 5)
2718 #define   GFX_FORWARD_VBLANK_COND       (2 << 5)
2719
2720 #define   GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2721
2722 #define VLV_GU_CTL0     _MMIO(VLV_DISPLAY_BASE + 0x2030)
2723 #define VLV_GU_CTL1     _MMIO(VLV_DISPLAY_BASE + 0x2034)
2724 #define SCPD0           _MMIO(0x209c) /* 915+ only */
2725 #define GEN2_IER        _MMIO(0x20a0)
2726 #define GEN2_IIR        _MMIO(0x20a4)
2727 #define GEN2_IMR        _MMIO(0x20a8)
2728 #define GEN2_ISR        _MMIO(0x20ac)
2729 #define VLV_GUNIT_CLOCK_GATE    _MMIO(VLV_DISPLAY_BASE + 0x2060)
2730 #define   GINT_DIS              (1 << 22)
2731 #define   GCFG_DIS              (1 << 8)
2732 #define VLV_GUNIT_CLOCK_GATE2   _MMIO(VLV_DISPLAY_BASE + 0x2064)
2733 #define VLV_IIR_RW      _MMIO(VLV_DISPLAY_BASE + 0x2084)
2734 #define VLV_IER         _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2735 #define VLV_IIR         _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2736 #define VLV_IMR         _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2737 #define VLV_ISR         _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2738 #define VLV_PCBR        _MMIO(VLV_DISPLAY_BASE + 0x2120)
2739 #define VLV_PCBR_ADDR_SHIFT     12
2740
2741 #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2742 #define EIR             _MMIO(0x20b0)
2743 #define EMR             _MMIO(0x20b4)
2744 #define ESR             _MMIO(0x20b8)
2745 #define   GM45_ERROR_PAGE_TABLE                         (1 << 5)
2746 #define   GM45_ERROR_MEM_PRIV                           (1 << 4)
2747 #define   I915_ERROR_PAGE_TABLE                         (1 << 4)
2748 #define   GM45_ERROR_CP_PRIV                            (1 << 3)
2749 #define   I915_ERROR_MEMORY_REFRESH                     (1 << 1)
2750 #define   I915_ERROR_INSTRUCTION                        (1 << 0)
2751 #define INSTPM          _MMIO(0x20c0)
2752 #define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
2753 #define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
2754                                         will not assert AGPBUSY# and will only
2755                                         be delivered when out of C3. */
2756 #define   INSTPM_FORCE_ORDERING                         (1 << 7) /* GEN6+ */
2757 #define   INSTPM_TLB_INVALIDATE (1 << 9)
2758 #define   INSTPM_SYNC_FLUSH     (1 << 5)
2759 #define ACTHD(base)     _MMIO((base) + 0xc8)
2760 #define MEM_MODE        _MMIO(0x20cc)
2761 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2762 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2763 #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
2764 #define FW_BLC          _MMIO(0x20d8)
2765 #define FW_BLC2         _MMIO(0x20dc)
2766 #define FW_BLC_SELF     _MMIO(0x20e0) /* 915+ only */
2767 #define   FW_BLC_SELF_EN_MASK      (1 << 31)
2768 #define   FW_BLC_SELF_FIFO_MASK    (1 << 16) /* 945 only */
2769 #define   FW_BLC_SELF_EN           (1 << 15) /* 945 only */
2770 #define MM_BURST_LENGTH     0x00700000
2771 #define MM_FIFO_WATERMARK   0x0001F000
2772 #define LM_BURST_LENGTH     0x00000700
2773 #define LM_FIFO_WATERMARK   0x0000001F
2774 #define MI_ARB_STATE    _MMIO(0x20e4) /* 915+ only */
2775
2776 #define MBUS_ABOX_CTL                   _MMIO(0x45038)
2777 #define MBUS_ABOX_BW_CREDIT_MASK        (3 << 20)
2778 #define MBUS_ABOX_BW_CREDIT(x)          ((x) << 20)
2779 #define MBUS_ABOX_B_CREDIT_MASK         (0xF << 16)
2780 #define MBUS_ABOX_B_CREDIT(x)           ((x) << 16)
2781 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK  (0x1F << 8)
2782 #define MBUS_ABOX_BT_CREDIT_POOL2(x)    ((x) << 8)
2783 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK  (0x1F << 0)
2784 #define MBUS_ABOX_BT_CREDIT_POOL1(x)    ((x) << 0)
2785
2786 #define _PIPEA_MBUS_DBOX_CTL            0x7003C
2787 #define _PIPEB_MBUS_DBOX_CTL            0x7103C
2788 #define PIPE_MBUS_DBOX_CTL(pipe)        _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2789                                                    _PIPEB_MBUS_DBOX_CTL)
2790 #define MBUS_DBOX_BW_CREDIT_MASK        (3 << 14)
2791 #define MBUS_DBOX_BW_CREDIT(x)          ((x) << 14)
2792 #define MBUS_DBOX_B_CREDIT_MASK         (0x1F << 8)
2793 #define MBUS_DBOX_B_CREDIT(x)           ((x) << 8)
2794 #define MBUS_DBOX_A_CREDIT_MASK         (0xF << 0)
2795 #define MBUS_DBOX_A_CREDIT(x)           ((x) << 0)
2796
2797 #define MBUS_UBOX_CTL                   _MMIO(0x4503C)
2798 #define MBUS_BBOX_CTL_S1                _MMIO(0x45040)
2799 #define MBUS_BBOX_CTL_S2                _MMIO(0x45044)
2800
2801 /* Make render/texture TLB fetches lower priorty than associated data
2802  *   fetches. This is not turned on by default
2803  */
2804 #define   MI_ARB_RENDER_TLB_LOW_PRIORITY        (1 << 15)
2805
2806 /* Isoch request wait on GTT enable (Display A/B/C streams).
2807  * Make isoch requests stall on the TLB update. May cause
2808  * display underruns (test mode only)
2809  */
2810 #define   MI_ARB_ISOCH_WAIT_GTT                 (1 << 14)
2811
2812 /* Block grant count for isoch requests when block count is
2813  * set to a finite value.
2814  */
2815 #define   MI_ARB_BLOCK_GRANT_MASK               (3 << 12)
2816 #define   MI_ARB_BLOCK_GRANT_8                  (0 << 12)       /* for 3 display planes */
2817 #define   MI_ARB_BLOCK_GRANT_4                  (1 << 12)       /* for 2 display planes */
2818 #define   MI_ARB_BLOCK_GRANT_2                  (2 << 12)       /* for 1 display plane */
2819 #define   MI_ARB_BLOCK_GRANT_0                  (3 << 12)       /* don't use */
2820
2821 /* Enable render writes to complete in C2/C3/C4 power states.
2822  * If this isn't enabled, render writes are prevented in low
2823  * power states. That seems bad to me.
2824  */
2825 #define   MI_ARB_C3_LP_WRITE_ENABLE             (1 << 11)
2826
2827 /* This acknowledges an async flip immediately instead
2828  * of waiting for 2TLB fetches.
2829  */
2830 #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE       (1 << 10)
2831
2832 /* Enables non-sequential data reads through arbiter
2833  */
2834 #define   MI_ARB_DUAL_DATA_PHASE_DISABLE        (1 << 9)
2835
2836 /* Disable FSB snooping of cacheable write cycles from binner/render
2837  * command stream
2838  */
2839 #define   MI_ARB_CACHE_SNOOP_DISABLE            (1 << 8)
2840
2841 /* Arbiter time slice for non-isoch streams */
2842 #define   MI_ARB_TIME_SLICE_MASK                (7 << 5)
2843 #define   MI_ARB_TIME_SLICE_1                   (0 << 5)
2844 #define   MI_ARB_TIME_SLICE_2                   (1 << 5)
2845 #define   MI_ARB_TIME_SLICE_4                   (2 << 5)
2846 #define   MI_ARB_TIME_SLICE_6                   (3 << 5)
2847 #define   MI_ARB_TIME_SLICE_8                   (4 << 5)
2848 #define   MI_ARB_TIME_SLICE_10                  (5 << 5)
2849 #define   MI_ARB_TIME_SLICE_14                  (6 << 5)
2850 #define   MI_ARB_TIME_SLICE_16                  (7 << 5)
2851
2852 /* Low priority grace period page size */
2853 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB         (0 << 4)        /* default */
2854 #define   MI_ARB_LOW_PRIORITY_GRACE_8KB         (1 << 4)
2855
2856 /* Disable display A/B trickle feed */
2857 #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE   (1 << 2)
2858
2859 /* Set display plane priority */
2860 #define   MI_ARB_DISPLAY_PRIORITY_A_B           (0 << 0)        /* display A > display B */
2861 #define   MI_ARB_DISPLAY_PRIORITY_B_A           (1 << 0)        /* display B > display A */
2862
2863 #define MI_STATE        _MMIO(0x20e4) /* gen2 only */
2864 #define   MI_AGPBUSY_INT_EN                     (1 << 1) /* 85x only */
2865 #define   MI_AGPBUSY_830_MODE                   (1 << 0) /* 85x only */
2866
2867 #define CACHE_MODE_0    _MMIO(0x2120) /* 915+ only */
2868 #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
2869 #define   CM0_IZ_OPT_DISABLE      (1 << 6)
2870 #define   CM0_ZR_OPT_DISABLE      (1 << 5)
2871 #define   CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
2872 #define   CM0_DEPTH_EVICT_DISABLE (1 << 4)
2873 #define   CM0_COLOR_EVICT_DISABLE (1 << 3)
2874 #define   CM0_DEPTH_WRITE_DISABLE (1 << 1)
2875 #define   CM0_RC_OP_FLUSH_DISABLE (1 << 0)
2876 #define GFX_FLSH_CNTL   _MMIO(0x2170) /* 915+ only */
2877 #define GFX_FLSH_CNTL_GEN6      _MMIO(0x101008)
2878 #define   GFX_FLSH_CNTL_EN      (1 << 0)
2879 #define ECOSKPD         _MMIO(0x21d0)
2880 #define   ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
2881 #define   ECO_GATING_CX_ONLY    (1 << 3)
2882 #define   ECO_FLIP_DONE         (1 << 0)
2883
2884 #define CACHE_MODE_0_GEN7       _MMIO(0x7000) /* IVB+ */
2885 #define RC_OP_FLUSH_ENABLE (1 << 0)
2886 #define   HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
2887 #define CACHE_MODE_1            _MMIO(0x7004) /* IVB+ */
2888 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE     (1 << 6)
2889 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE     (1 << 6)
2890 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE    (1 << 1)
2891
2892 #define GEN6_BLITTER_ECOSKPD    _MMIO(0x221d0)
2893 #define   GEN6_BLITTER_LOCK_SHIFT                       16
2894 #define   GEN6_BLITTER_FBC_NOTIFY                       (1 << 3)
2895
2896 #define GEN6_RC_SLEEP_PSMI_CONTROL      _MMIO(0x2050)
2897 #define   GEN6_PSMI_SLEEP_MSG_DISABLE   (1 << 0)
2898 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2899 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE        (1 << 10)
2900
2901 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2902 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2903
2904 #define GEN10_CACHE_MODE_SS                     _MMIO(0xe420)
2905 #define   FLOAT_BLEND_OPTIMIZATION_ENABLE       (1 << 4)
2906
2907 /* Fuse readout registers for GT */
2908 #define HSW_PAVP_FUSE1                  _MMIO(0x911C)
2909 #define   HSW_F1_EU_DIS_SHIFT           16
2910 #define   HSW_F1_EU_DIS_MASK            (0x3 << HSW_F1_EU_DIS_SHIFT)
2911 #define   HSW_F1_EU_DIS_10EUS           0
2912 #define   HSW_F1_EU_DIS_8EUS            1
2913 #define   HSW_F1_EU_DIS_6EUS            2
2914
2915 #define CHV_FUSE_GT                     _MMIO(VLV_DISPLAY_BASE + 0x2168)
2916 #define   CHV_FGT_DISABLE_SS0           (1 << 10)
2917 #define   CHV_FGT_DISABLE_SS1           (1 << 11)
2918 #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT   16
2919 #define   CHV_FGT_EU_DIS_SS0_R0_MASK    (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2920 #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT   20
2921 #define   CHV_FGT_EU_DIS_SS0_R1_MASK    (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2922 #define   CHV_FGT_EU_DIS_SS1_R0_SHIFT   24
2923 #define   CHV_FGT_EU_DIS_SS1_R0_MASK    (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2924 #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT   28
2925 #define   CHV_FGT_EU_DIS_SS1_R1_MASK    (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2926
2927 #define GEN8_FUSE2                      _MMIO(0x9120)
2928 #define   GEN8_F2_SS_DIS_SHIFT          21
2929 #define   GEN8_F2_SS_DIS_MASK           (0x7 << GEN8_F2_SS_DIS_SHIFT)
2930 #define   GEN8_F2_S_ENA_SHIFT           25
2931 #define   GEN8_F2_S_ENA_MASK            (0x7 << GEN8_F2_S_ENA_SHIFT)
2932
2933 #define   GEN9_F2_SS_DIS_SHIFT          20
2934 #define   GEN9_F2_SS_DIS_MASK           (0xf << GEN9_F2_SS_DIS_SHIFT)
2935
2936 #define   GEN10_F2_S_ENA_SHIFT          22
2937 #define   GEN10_F2_S_ENA_MASK           (0x3f << GEN10_F2_S_ENA_SHIFT)
2938 #define   GEN10_F2_SS_DIS_SHIFT         18
2939 #define   GEN10_F2_SS_DIS_MASK          (0xf << GEN10_F2_SS_DIS_SHIFT)
2940
2941 #define GEN10_MIRROR_FUSE3              _MMIO(0x9118)
2942 #define GEN10_L3BANK_PAIR_COUNT     4
2943 #define GEN10_L3BANK_MASK   0x0F
2944
2945 #define GEN8_EU_DISABLE0                _MMIO(0x9134)
2946 #define   GEN8_EU_DIS0_S0_MASK          0xffffff
2947 #define   GEN8_EU_DIS0_S1_SHIFT         24
2948 #define   GEN8_EU_DIS0_S1_MASK          (0xff << GEN8_EU_DIS0_S1_SHIFT)
2949
2950 #define GEN8_EU_DISABLE1                _MMIO(0x9138)
2951 #define   GEN8_EU_DIS1_S1_MASK          0xffff
2952 #define   GEN8_EU_DIS1_S2_SHIFT         16
2953 #define   GEN8_EU_DIS1_S2_MASK          (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2954
2955 #define GEN8_EU_DISABLE2                _MMIO(0x913c)
2956 #define   GEN8_EU_DIS2_S2_MASK          0xff
2957
2958 #define GEN9_EU_DISABLE(slice)          _MMIO(0x9134 + (slice) * 0x4)
2959
2960 #define GEN10_EU_DISABLE3               _MMIO(0x9140)
2961 #define   GEN10_EU_DIS_SS_MASK          0xff
2962
2963 #define GEN11_GT_VEBOX_VDBOX_DISABLE    _MMIO(0x9140)
2964 #define   GEN11_GT_VDBOX_DISABLE_MASK   0xff
2965 #define   GEN11_GT_VEBOX_DISABLE_SHIFT  16
2966 #define   GEN11_GT_VEBOX_DISABLE_MASK   (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
2967
2968 #define GEN11_EU_DISABLE _MMIO(0x9134)
2969 #define GEN11_EU_DIS_MASK 0xFF
2970
2971 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
2972 #define GEN11_GT_S_ENA_MASK 0xFF
2973
2974 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
2975
2976 #define GEN6_BSD_SLEEP_PSMI_CONTROL     _MMIO(0x12050)
2977 #define   GEN6_BSD_SLEEP_MSG_DISABLE    (1 << 0)
2978 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE  (1 << 2)
2979 #define   GEN6_BSD_SLEEP_INDICATOR      (1 << 3)
2980 #define   GEN6_BSD_GO_INDICATOR         (1 << 4)
2981
2982 /* On modern GEN architectures interrupt control consists of two sets
2983  * of registers. The first set pertains to the ring generating the
2984  * interrupt. The second control is for the functional block generating the
2985  * interrupt. These are PM, GT, DE, etc.
2986  *
2987  * Luckily *knocks on wood* all the ring interrupt bits match up with the
2988  * GT interrupt bits, so we don't need to duplicate the defines.
2989  *
2990  * These defines should cover us well from SNB->HSW with minor exceptions
2991  * it can also work on ILK.
2992  */
2993 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT         (1 << 26)
2994 #define GT_BLT_CS_ERROR_INTERRUPT               (1 << 25)
2995 #define GT_BLT_USER_INTERRUPT                   (1 << 22)
2996 #define GT_BSD_CS_ERROR_INTERRUPT               (1 << 15)
2997 #define GT_BSD_USER_INTERRUPT                   (1 << 12)
2998 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1  (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2999 #define GT_CONTEXT_SWITCH_INTERRUPT             (1 <<  8)
3000 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT     (1 <<  5) /* !snb */
3001 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT      (1 <<  4)
3002 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT     (1 <<  3)
3003 #define GT_RENDER_SYNC_STATUS_INTERRUPT         (1 <<  2)
3004 #define GT_RENDER_DEBUG_INTERRUPT               (1 <<  1)
3005 #define GT_RENDER_USER_INTERRUPT                (1 <<  0)
3006
3007 #define PM_VEBOX_CS_ERROR_INTERRUPT             (1 << 12) /* hsw+ */
3008 #define PM_VEBOX_USER_INTERRUPT                 (1 << 10) /* hsw+ */
3009
3010 #define GT_PARITY_ERROR(dev_priv) \
3011         (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
3012          (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3013
3014 /* These are all the "old" interrupts */
3015 #define ILK_BSD_USER_INTERRUPT                          (1 << 5)
3016
3017 #define I915_PM_INTERRUPT                               (1 << 31)
3018 #define I915_ISP_INTERRUPT                              (1 << 22)
3019 #define I915_LPE_PIPE_B_INTERRUPT                       (1 << 21)
3020 #define I915_LPE_PIPE_A_INTERRUPT                       (1 << 20)
3021 #define I915_MIPIC_INTERRUPT                            (1 << 19)
3022 #define I915_MIPIA_INTERRUPT                            (1 << 18)
3023 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT              (1 << 18)
3024 #define I915_DISPLAY_PORT_INTERRUPT                     (1 << 17)
3025 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT            (1 << 16)
3026 #define I915_MASTER_ERROR_INTERRUPT                     (1 << 15)
3027 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT            (1 << 14)
3028 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT        (1 << 14) /* p-state */
3029 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT            (1 << 13)
3030 #define I915_HWB_OOM_INTERRUPT                          (1 << 13)
3031 #define I915_LPE_PIPE_C_INTERRUPT                       (1 << 12)
3032 #define I915_SYNC_STATUS_INTERRUPT                      (1 << 12)
3033 #define I915_MISC_INTERRUPT                             (1 << 11)
3034 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT     (1 << 11)
3035 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT            (1 << 10)
3036 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT     (1 << 10)
3037 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT             (1 << 9)
3038 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT       (1 << 9)
3039 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT              (1 << 8)
3040 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT     (1 << 8)
3041 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT            (1 << 7)
3042 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT             (1 << 6)
3043 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT            (1 << 5)
3044 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT             (1 << 4)
3045 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT              (1 << 3)
3046 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT              (1 << 2)
3047 #define I915_DEBUG_INTERRUPT                            (1 << 2)
3048 #define I915_WINVALID_INTERRUPT                         (1 << 1)
3049 #define I915_USER_INTERRUPT                             (1 << 1)
3050 #define I915_ASLE_INTERRUPT                             (1 << 0)
3051 #define I915_BSD_USER_INTERRUPT                         (1 << 25)
3052
3053 #define I915_HDMI_LPE_AUDIO_BASE        (VLV_DISPLAY_BASE + 0x65000)
3054 #define I915_HDMI_LPE_AUDIO_SIZE        0x1000
3055
3056 /* DisplayPort Audio w/ LPE */
3057 #define VLV_AUD_CHICKEN_BIT_REG         _MMIO(VLV_DISPLAY_BASE + 0x62F38)
3058 #define VLV_CHICKEN_BIT_DBG_ENABLE      (1 << 0)
3059
3060 #define _VLV_AUD_PORT_EN_B_DBG          (VLV_DISPLAY_BASE + 0x62F20)
3061 #define _VLV_AUD_PORT_EN_C_DBG          (VLV_DISPLAY_BASE + 0x62F30)
3062 #define _VLV_AUD_PORT_EN_D_DBG          (VLV_DISPLAY_BASE + 0x62F34)
3063 #define VLV_AUD_PORT_EN_DBG(port)       _MMIO_PORT3((port) - PORT_B,       \
3064                                                     _VLV_AUD_PORT_EN_B_DBG, \
3065                                                     _VLV_AUD_PORT_EN_C_DBG, \
3066                                                     _VLV_AUD_PORT_EN_D_DBG)
3067 #define VLV_AMP_MUTE                    (1 << 1)
3068
3069 #define GEN6_BSD_RNCID                  _MMIO(0x12198)
3070
3071 #define GEN7_FF_THREAD_MODE             _MMIO(0x20a0)
3072 #define   GEN7_FF_SCHED_MASK            0x0077070
3073 #define   GEN8_FF_DS_REF_CNT_FFME       (1 << 19)
3074 #define   GEN7_FF_TS_SCHED_HS1          (0x5 << 16)
3075 #define   GEN7_FF_TS_SCHED_HS0          (0x3 << 16)
3076 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
3077 #define   GEN7_FF_TS_SCHED_HW           (0x0 << 16) /* Default */
3078 #define   GEN7_FF_VS_REF_CNT_FFME       (1 << 15)
3079 #define   GEN7_FF_VS_SCHED_HS1          (0x5 << 12)
3080 #define   GEN7_FF_VS_SCHED_HS0          (0x3 << 12)
3081 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
3082 #define   GEN7_FF_VS_SCHED_HW           (0x0 << 12)
3083 #define   GEN7_FF_DS_SCHED_HS1          (0x5 << 4)
3084 #define   GEN7_FF_DS_SCHED_HS0          (0x3 << 4)
3085 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4)  /* Default */
3086 #define   GEN7_FF_DS_SCHED_HW           (0x0 << 4)
3087
3088 /*
3089  * Framebuffer compression (915+ only)
3090  */
3091
3092 #define FBC_CFB_BASE            _MMIO(0x3200) /* 4k page aligned */
3093 #define FBC_LL_BASE             _MMIO(0x3204) /* 4k page aligned */
3094 #define FBC_CONTROL             _MMIO(0x3208)
3095 #define   FBC_CTL_EN            (1 << 31)
3096 #define   FBC_CTL_PERIODIC      (1 << 30)
3097 #define   FBC_CTL_INTERVAL_SHIFT (16)
3098 #define   FBC_CTL_UNCOMPRESSIBLE (1 << 14)
3099 #define   FBC_CTL_C3_IDLE       (1 << 13)
3100 #define   FBC_CTL_STRIDE_SHIFT  (5)
3101 #define   FBC_CTL_FENCENO_SHIFT (0)
3102 #define FBC_COMMAND             _MMIO(0x320c)
3103 #define   FBC_CMD_COMPRESS      (1 << 0)
3104 #define FBC_STATUS              _MMIO(0x3210)
3105 #define   FBC_STAT_COMPRESSING  (1 << 31)
3106 #define   FBC_STAT_COMPRESSED   (1 << 30)
3107 #define   FBC_STAT_MODIFIED     (1 << 29)
3108 #define   FBC_STAT_CURRENT_LINE_SHIFT   (0)
3109 #define FBC_CONTROL2            _MMIO(0x3214)
3110 #define   FBC_CTL_FENCE_DBL     (0 << 4)
3111 #define   FBC_CTL_IDLE_IMM      (0 << 2)
3112 #define   FBC_CTL_IDLE_FULL     (1 << 2)
3113 #define   FBC_CTL_IDLE_LINE     (2 << 2)
3114 #define   FBC_CTL_IDLE_DEBUG    (3 << 2)
3115 #define   FBC_CTL_CPU_FENCE     (1 << 1)
3116 #define   FBC_CTL_PLANE(plane)  ((plane) << 0)
3117 #define FBC_FENCE_OFF           _MMIO(0x3218) /* BSpec typo has 321Bh */
3118 #define FBC_TAG(i)              _MMIO(0x3300 + (i) * 4)
3119
3120 #define FBC_LL_SIZE             (1536)
3121
3122 #define FBC_LLC_READ_CTRL       _MMIO(0x9044)
3123 #define   FBC_LLC_FULLY_OPEN    (1 << 30)
3124
3125 /* Framebuffer compression for GM45+ */
3126 #define DPFC_CB_BASE            _MMIO(0x3200)
3127 #define DPFC_CONTROL            _MMIO(0x3208)
3128 #define   DPFC_CTL_EN           (1 << 31)
3129 #define   DPFC_CTL_PLANE(plane) ((plane) << 30)
3130 #define   IVB_DPFC_CTL_PLANE(plane)     ((plane) << 29)
3131 #define   DPFC_CTL_FENCE_EN     (1 << 29)
3132 #define   IVB_DPFC_CTL_FENCE_EN (1 << 28)
3133 #define   DPFC_CTL_PERSISTENT_MODE      (1 << 25)
3134 #define   DPFC_SR_EN            (1 << 10)
3135 #define   DPFC_CTL_LIMIT_1X     (0 << 6)
3136 #define   DPFC_CTL_LIMIT_2X     (1 << 6)
3137 #define   DPFC_CTL_LIMIT_4X     (2 << 6)
3138 #define DPFC_RECOMP_CTL         _MMIO(0x320c)
3139 #define   DPFC_RECOMP_STALL_EN  (1 << 27)
3140 #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
3141 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3142 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3143 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3144 #define DPFC_STATUS             _MMIO(0x3210)
3145 #define   DPFC_INVAL_SEG_SHIFT  (16)
3146 #define   DPFC_INVAL_SEG_MASK   (0x07ff0000)
3147 #define   DPFC_COMP_SEG_SHIFT   (0)
3148 #define   DPFC_COMP_SEG_MASK    (0x000007ff)
3149 #define DPFC_STATUS2            _MMIO(0x3214)
3150 #define DPFC_FENCE_YOFF         _MMIO(0x3218)
3151 #define DPFC_CHICKEN            _MMIO(0x3224)
3152 #define   DPFC_HT_MODIFY        (1 << 31)
3153
3154 /* Framebuffer compression for Ironlake */
3155 #define ILK_DPFC_CB_BASE        _MMIO(0x43200)
3156 #define ILK_DPFC_CONTROL        _MMIO(0x43208)
3157 #define   FBC_CTL_FALSE_COLOR   (1 << 10)
3158 /* The bit 28-8 is reserved */
3159 #define   DPFC_RESERVED         (0x1FFFFF00)
3160 #define ILK_DPFC_RECOMP_CTL     _MMIO(0x4320c)
3161 #define ILK_DPFC_STATUS         _MMIO(0x43210)
3162 #define  ILK_DPFC_COMP_SEG_MASK 0x7ff
3163 #define IVB_FBC_STATUS2         _MMIO(0x43214)
3164 #define  IVB_FBC_COMP_SEG_MASK  0x7ff
3165 #define  BDW_FBC_COMP_SEG_MASK  0xfff
3166 #define ILK_DPFC_FENCE_YOFF     _MMIO(0x43218)
3167 #define ILK_DPFC_CHICKEN        _MMIO(0x43224)
3168 #define   ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3169 #define   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL     (1 << 14)
3170 #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION     (1 << 23)
3171 #define ILK_FBC_RT_BASE         _MMIO(0x2128)
3172 #define   ILK_FBC_RT_VALID      (1 << 0)
3173 #define   SNB_FBC_FRONT_BUFFER  (1 << 1)
3174
3175 #define ILK_DISPLAY_CHICKEN1    _MMIO(0x42000)
3176 #define   ILK_FBCQ_DIS          (1 << 22)
3177 #define   ILK_PABSTRETCH_DIS    (1 << 21)
3178
3179
3180 /*
3181  * Framebuffer compression for Sandybridge
3182  *
3183  * The following two registers are of type GTTMMADR
3184  */
3185 #define SNB_DPFC_CTL_SA         _MMIO(0x100100)
3186 #define   SNB_CPU_FENCE_ENABLE  (1 << 29)
3187 #define DPFC_CPU_FENCE_OFFSET   _MMIO(0x100104)
3188
3189 /* Framebuffer compression for Ivybridge */
3190 #define IVB_FBC_RT_BASE                 _MMIO(0x7020)
3191
3192 #define IPS_CTL         _MMIO(0x43408)
3193 #define   IPS_ENABLE    (1 << 31)
3194
3195 #define MSG_FBC_REND_STATE      _MMIO(0x50380)
3196 #define   FBC_REND_NUKE         (1 << 2)
3197 #define   FBC_REND_CACHE_CLEAN  (1 << 1)
3198
3199 /*
3200  * GPIO regs
3201  */
3202 #define GPIO(gpio)              _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3203                                       4 * (gpio))
3204
3205 # define GPIO_CLOCK_DIR_MASK            (1 << 0)
3206 # define GPIO_CLOCK_DIR_IN              (0 << 1)
3207 # define GPIO_CLOCK_DIR_OUT             (1 << 1)
3208 # define GPIO_CLOCK_VAL_MASK            (1 << 2)
3209 # define GPIO_CLOCK_VAL_OUT             (1 << 3)
3210 # define GPIO_CLOCK_VAL_IN              (1 << 4)
3211 # define GPIO_CLOCK_PULLUP_DISABLE      (1 << 5)
3212 # define GPIO_DATA_DIR_MASK             (1 << 8)
3213 # define GPIO_DATA_DIR_IN               (0 << 9)
3214 # define GPIO_DATA_DIR_OUT              (1 << 9)
3215 # define GPIO_DATA_VAL_MASK             (1 << 10)
3216 # define GPIO_DATA_VAL_OUT              (1 << 11)
3217 # define GPIO_DATA_VAL_IN               (1 << 12)
3218 # define GPIO_DATA_PULLUP_DISABLE       (1 << 13)
3219
3220 #define GMBUS0                  _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3221 #define   GMBUS_AKSV_SELECT     (1 << 11)
3222 #define   GMBUS_RATE_100KHZ     (0 << 8)
3223 #define   GMBUS_RATE_50KHZ      (1 << 8)
3224 #define   GMBUS_RATE_400KHZ     (2 << 8) /* reserved on Pineview */
3225 #define   GMBUS_RATE_1MHZ       (3 << 8) /* reserved on Pineview */
3226 #define   GMBUS_HOLD_EXT        (1 << 7) /* 300ns hold time, rsvd on Pineview */
3227 #define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3228
3229 #define GMBUS1                  _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3230 #define   GMBUS_SW_CLR_INT      (1 << 31)
3231 #define   GMBUS_SW_RDY          (1 << 30)
3232 #define   GMBUS_ENT             (1 << 29) /* enable timeout */
3233 #define   GMBUS_CYCLE_NONE      (0 << 25)
3234 #define   GMBUS_CYCLE_WAIT      (1 << 25)
3235 #define   GMBUS_CYCLE_INDEX     (2 << 25)
3236 #define   GMBUS_CYCLE_STOP      (4 << 25)
3237 #define   GMBUS_BYTE_COUNT_SHIFT 16
3238 #define   GMBUS_BYTE_COUNT_MAX   256U
3239 #define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
3240 #define   GMBUS_SLAVE_INDEX_SHIFT 8
3241 #define   GMBUS_SLAVE_ADDR_SHIFT 1
3242 #define   GMBUS_SLAVE_READ      (1 << 0)
3243 #define   GMBUS_SLAVE_WRITE     (0 << 0)
3244 #define GMBUS2                  _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3245 #define   GMBUS_INUSE           (1 << 15)
3246 #define   GMBUS_HW_WAIT_PHASE   (1 << 14)
3247 #define   GMBUS_STALL_TIMEOUT   (1 << 13)
3248 #define   GMBUS_INT             (1 << 12)
3249 #define   GMBUS_HW_RDY          (1 << 11)
3250 #define   GMBUS_SATOER          (1 << 10)
3251 #define   GMBUS_ACTIVE          (1 << 9)
3252 #define GMBUS3                  _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3253 #define GMBUS4                  _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3254 #define   GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3255 #define   GMBUS_NAK_EN          (1 << 3)
3256 #define   GMBUS_IDLE_EN         (1 << 2)
3257 #define   GMBUS_HW_WAIT_EN      (1 << 1)
3258 #define   GMBUS_HW_RDY_EN       (1 << 0)
3259 #define GMBUS5                  _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3260 #define   GMBUS_2BYTE_INDEX_EN  (1 << 31)
3261
3262 /*
3263  * Clock control & power management
3264  */
3265 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3266 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3267 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3268 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3269
3270 #define VGA0    _MMIO(0x6000)
3271 #define VGA1    _MMIO(0x6004)
3272 #define VGA_PD  _MMIO(0x6010)
3273 #define   VGA0_PD_P2_DIV_4      (1 << 7)
3274 #define   VGA0_PD_P1_DIV_2      (1 << 5)
3275 #define   VGA0_PD_P1_SHIFT      0
3276 #define   VGA0_PD_P1_MASK       (0x1f << 0)
3277 #define   VGA1_PD_P2_DIV_4      (1 << 15)
3278 #define   VGA1_PD_P1_DIV_2      (1 << 13)
3279 #define   VGA1_PD_P1_SHIFT      8
3280 #define   VGA1_PD_P1_MASK       (0x1f << 8)
3281 #define   DPLL_VCO_ENABLE               (1 << 31)
3282 #define   DPLL_SDVO_HIGH_SPEED          (1 << 30)
3283 #define   DPLL_DVO_2X_MODE              (1 << 30)
3284 #define   DPLL_EXT_BUFFER_ENABLE_VLV    (1 << 30)
3285 #define   DPLL_SYNCLOCK_ENABLE          (1 << 29)
3286 #define   DPLL_REF_CLK_ENABLE_VLV       (1 << 29)
3287 #define   DPLL_VGA_MODE_DIS             (1 << 28)
3288 #define   DPLLB_MODE_DAC_SERIAL         (1 << 26) /* i915 */
3289 #define   DPLLB_MODE_LVDS               (2 << 26) /* i915 */
3290 #define   DPLL_MODE_MASK                (3 << 26)
3291 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3292 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3293 #define   DPLLB_LVDS_P2_CLOCK_DIV_14    (0 << 24) /* i915 */
3294 #define   DPLLB_LVDS_P2_CLOCK_DIV_7     (1 << 24) /* i915 */
3295 #define   DPLL_P2_CLOCK_DIV_MASK        0x03000000 /* i915 */
3296 #define   DPLL_FPA01_P1_POST_DIV_MASK   0x00ff0000 /* i915 */
3297 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW  0x00ff8000 /* Pineview */
3298 #define   DPLL_LOCK_VLV                 (1 << 15)
3299 #define   DPLL_INTEGRATED_CRI_CLK_VLV   (1 << 14)
3300 #define   DPLL_INTEGRATED_REF_CLK_VLV   (1 << 13)
3301 #define   DPLL_SSC_REF_CLK_CHV          (1 << 13)
3302 #define   DPLL_PORTC_READY_MASK         (0xf << 4)
3303 #define   DPLL_PORTB_READY_MASK         (0xf)
3304
3305 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830      0x001f0000
3306
3307 /* Additional CHV pll/phy registers */
3308 #define DPIO_PHY_STATUS                 _MMIO(VLV_DISPLAY_BASE + 0x6240)
3309 #define   DPLL_PORTD_READY_MASK         (0xf)
3310 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3311 #define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)    (1 << (2 * (phy) + (ch) + 27))
3312 #define   PHY_LDO_DELAY_0NS                     0x0
3313 #define   PHY_LDO_DELAY_200NS                   0x1
3314 #define   PHY_LDO_DELAY_600NS                   0x2
3315 #define   PHY_LDO_SEQ_DELAY(delay, phy)         ((delay) << (2 * (phy) + 23))
3316 #define   PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
3317 #define   PHY_CH_SU_PSR                         0x1
3318 #define   PHY_CH_DEEP_PSR                       0x7
3319 #define   PHY_CH_POWER_MODE(mode, phy, ch)      ((mode) << (6 * (phy) + 3 * (ch) + 2))
3320 #define   PHY_COM_LANE_RESET_DEASSERT(phy)      (1 << (phy))
3321 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3322 #define   PHY_POWERGOOD(phy)    (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3323 #define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6 - (6 * (phy) + 3 * (ch))))
3324 #define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3325
3326 /*
3327  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3328  * this field (only one bit may be set).
3329  */
3330 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3331 #define   DPLL_FPA01_P1_POST_DIV_SHIFT  16
3332 #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3333 /* i830, required in DVO non-gang */
3334 #define   PLL_P2_DIVIDE_BY_4            (1 << 23)
3335 #define   PLL_P1_DIVIDE_BY_TWO          (1 << 21) /* i830 */
3336 #define   PLL_REF_INPUT_DREFCLK         (0 << 13)
3337 #define   PLL_REF_INPUT_TVCLKINA        (1 << 13) /* i830 */
3338 #define   PLL_REF_INPUT_TVCLKINBC       (2 << 13) /* SDVO TVCLKIN */
3339 #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3340 #define   PLL_REF_INPUT_MASK            (3 << 13)
3341 #define   PLL_LOAD_PULSE_PHASE_SHIFT            9
3342 /* Ironlake */
3343 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
3344 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
3345 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)        (((x) - 1) << 9)
3346 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
3347 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
3348
3349 /*
3350  * Parallel to Serial Load Pulse phase selection.
3351  * Selects the phase for the 10X DPLL clock for the PCIe
3352  * digital display port. The range is 4 to 13; 10 or more
3353  * is just a flip delay. The default is 6
3354  */
3355 #define   PLL_LOAD_PULSE_PHASE_MASK             (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3356 #define   DISPLAY_RATE_SELECT_FPA1              (1 << 8)
3357 /*
3358  * SDVO multiplier for 945G/GM. Not used on 965.
3359  */
3360 #define   SDVO_MULTIPLIER_MASK                  0x000000ff
3361 #define   SDVO_MULTIPLIER_SHIFT_HIRES           4
3362 #define   SDVO_MULTIPLIER_SHIFT_VGA             0
3363
3364 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3365 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3366 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3367 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3368
3369 /*
3370  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3371  *
3372  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
3373  */
3374 #define   DPLL_MD_UDI_DIVIDER_MASK              0x3f000000
3375 #define   DPLL_MD_UDI_DIVIDER_SHIFT             24
3376 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3377 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK          0x003f0000
3378 #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT         16
3379 /*
3380  * SDVO/UDI pixel multiplier.
3381  *
3382  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3383  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
3384  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3385  * dummy bytes in the datastream at an increased clock rate, with both sides of
3386  * the link knowing how many bytes are fill.
3387  *
3388  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3389  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
3390  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3391  * through an SDVO command.
3392  *
3393  * This register field has values of multiplication factor minus 1, with
3394  * a maximum multiplier of 5 for SDVO.
3395  */
3396 #define   DPLL_MD_UDI_MULTIPLIER_MASK           0x00003f00
3397 #define   DPLL_MD_UDI_MULTIPLIER_SHIFT          8
3398 /*
3399  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3400  * This best be set to the default value (3) or the CRT won't work. No,
3401  * I don't entirely understand what this does...
3402  */
3403 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK       0x0000003f
3404 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT      0
3405
3406 #define RAWCLK_FREQ_VLV         _MMIO(VLV_DISPLAY_BASE + 0x6024)
3407
3408 #define _FPA0   0x6040
3409 #define _FPA1   0x6044
3410 #define _FPB0   0x6048
3411 #define _FPB1   0x604c
3412 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3413 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3414 #define   FP_N_DIV_MASK         0x003f0000
3415 #define   FP_N_PINEVIEW_DIV_MASK        0x00ff0000
3416 #define   FP_N_DIV_SHIFT                16
3417 #define   FP_M1_DIV_MASK        0x00003f00
3418 #define   FP_M1_DIV_SHIFT                8
3419 #define   FP_M2_DIV_MASK        0x0000003f
3420 #define   FP_M2_PINEVIEW_DIV_MASK       0x000000ff
3421 #define   FP_M2_DIV_SHIFT                0
3422 #define DPLL_TEST       _MMIO(0x606c)
3423 #define   DPLLB_TEST_SDVO_DIV_1         (0 << 22)
3424 #define   DPLLB_TEST_SDVO_DIV_2         (1 << 22)
3425 #define   DPLLB_TEST_SDVO_DIV_4         (2 << 22)
3426 #define   DPLLB_TEST_SDVO_DIV_MASK      (3 << 22)
3427 #define   DPLLB_TEST_N_BYPASS           (1 << 19)
3428 #define   DPLLB_TEST_M_BYPASS           (1 << 18)
3429 #define   DPLLB_INPUT_BUFFER_ENABLE     (1 << 16)
3430 #define   DPLLA_TEST_N_BYPASS           (1 << 3)
3431 #define   DPLLA_TEST_M_BYPASS           (1 << 2)
3432 #define   DPLLA_INPUT_BUFFER_ENABLE     (1 << 0)
3433 #define D_STATE         _MMIO(0x6104)
3434 #define  DSTATE_GFX_RESET_I830                  (1 << 6)
3435 #define  DSTATE_PLL_D3_OFF                      (1 << 3)
3436 #define  DSTATE_GFX_CLOCK_GATING                (1 << 1)
3437 #define  DSTATE_DOT_CLOCK_GATING                (1 << 0)
3438 #define DSPCLK_GATE_D   _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3439 # define DPUNIT_B_CLOCK_GATE_DISABLE            (1 << 30) /* 965 */
3440 # define VSUNIT_CLOCK_GATE_DISABLE              (1 << 29) /* 965 */
3441 # define VRHUNIT_CLOCK_GATE_DISABLE             (1 << 28) /* 965 */
3442 # define VRDUNIT_CLOCK_GATE_DISABLE             (1 << 27) /* 965 */
3443 # define AUDUNIT_CLOCK_GATE_DISABLE             (1 << 26) /* 965 */
3444 # define DPUNIT_A_CLOCK_GATE_DISABLE            (1 << 25) /* 965 */
3445 # define DPCUNIT_CLOCK_GATE_DISABLE             (1 << 24) /* 965 */
3446 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE       (1 << 24) /* pnv */
3447 # define TVRUNIT_CLOCK_GATE_DISABLE             (1 << 23) /* 915-945 */
3448 # define TVCUNIT_CLOCK_GATE_DISABLE             (1 << 22) /* 915-945 */
3449 # define TVFUNIT_CLOCK_GATE_DISABLE             (1 << 21) /* 915-945 */
3450 # define TVEUNIT_CLOCK_GATE_DISABLE             (1 << 20) /* 915-945 */
3451 # define DVSUNIT_CLOCK_GATE_DISABLE             (1 << 19) /* 915-945 */
3452 # define DSSUNIT_CLOCK_GATE_DISABLE             (1 << 18) /* 915-945 */
3453 # define DDBUNIT_CLOCK_GATE_DISABLE             (1 << 17) /* 915-945 */
3454 # define DPRUNIT_CLOCK_GATE_DISABLE             (1 << 16) /* 915-945 */
3455 # define DPFUNIT_CLOCK_GATE_DISABLE             (1 << 15) /* 915-945 */
3456 # define DPBMUNIT_CLOCK_GATE_DISABLE            (1 << 14) /* 915-945 */
3457 # define DPLSUNIT_CLOCK_GATE_DISABLE            (1 << 13) /* 915-945 */
3458 # define DPLUNIT_CLOCK_GATE_DISABLE             (1 << 12) /* 915-945 */
3459 # define DPOUNIT_CLOCK_GATE_DISABLE             (1 << 11)
3460 # define DPBUNIT_CLOCK_GATE_DISABLE             (1 << 10)
3461 # define DCUNIT_CLOCK_GATE_DISABLE              (1 << 9)
3462 # define DPUNIT_CLOCK_GATE_DISABLE              (1 << 8)
3463 # define VRUNIT_CLOCK_GATE_DISABLE              (1 << 7) /* 915+: reserved */
3464 # define OVHUNIT_CLOCK_GATE_DISABLE             (1 << 6) /* 830-865 */
3465 # define DPIOUNIT_CLOCK_GATE_DISABLE            (1 << 6) /* 915-945 */
3466 # define OVFUNIT_CLOCK_GATE_DISABLE             (1 << 5)
3467 # define OVBUNIT_CLOCK_GATE_DISABLE             (1 << 4)
3468 /*
3469  * This bit must be set on the 830 to prevent hangs when turning off the
3470  * overlay scaler.
3471  */
3472 # define OVRUNIT_CLOCK_GATE_DISABLE             (1 << 3)
3473 # define OVCUNIT_CLOCK_GATE_DISABLE             (1 << 2)
3474 # define OVUUNIT_CLOCK_GATE_DISABLE             (1 << 1)
3475 # define ZVUNIT_CLOCK_GATE_DISABLE              (1 << 0) /* 830 */
3476 # define OVLUNIT_CLOCK_GATE_DISABLE             (1 << 0) /* 845,865 */
3477
3478 #define RENCLK_GATE_D1          _MMIO(0x6204)
3479 # define BLITTER_CLOCK_GATE_DISABLE             (1 << 13) /* 945GM only */
3480 # define MPEG_CLOCK_GATE_DISABLE                (1 << 12) /* 945GM only */
3481 # define PC_FE_CLOCK_GATE_DISABLE               (1 << 11)
3482 # define PC_BE_CLOCK_GATE_DISABLE               (1 << 10)
3483 # define WINDOWER_CLOCK_GATE_DISABLE            (1 << 9)
3484 # define INTERPOLATOR_CLOCK_GATE_DISABLE        (1 << 8)
3485 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE    (1 << 7)
3486 # define MOTION_COMP_CLOCK_GATE_DISABLE         (1 << 6)
3487 # define MAG_CLOCK_GATE_DISABLE                 (1 << 5)
3488 /* This bit must be unset on 855,865 */
3489 # define MECI_CLOCK_GATE_DISABLE                (1 << 4)
3490 # define DCMP_CLOCK_GATE_DISABLE                (1 << 3)
3491 # define MEC_CLOCK_GATE_DISABLE                 (1 << 2)
3492 # define MECO_CLOCK_GATE_DISABLE                (1 << 1)
3493 /* This bit must be set on 855,865. */
3494 # define SV_CLOCK_GATE_DISABLE                  (1 << 0)
3495 # define I915_MPEG_CLOCK_GATE_DISABLE           (1 << 16)
3496 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE      (1 << 15)
3497 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE    (1 << 14)
3498 # define I915_BD_BF_CLOCK_GATE_DISABLE          (1 << 13)
3499 # define I915_SF_SE_CLOCK_GATE_DISABLE          (1 << 12)
3500 # define I915_WM_CLOCK_GATE_DISABLE             (1 << 11)
3501 # define I915_IZ_CLOCK_GATE_DISABLE             (1 << 10)
3502 # define I915_PI_CLOCK_GATE_DISABLE             (1 << 9)
3503 # define I915_DI_CLOCK_GATE_DISABLE             (1 << 8)
3504 # define I915_SH_SV_CLOCK_GATE_DISABLE          (1 << 7)
3505 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE    (1 << 6)
3506 # define I915_SC_CLOCK_GATE_DISABLE             (1 << 5)
3507 # define I915_FL_CLOCK_GATE_DISABLE             (1 << 4)
3508 # define I915_DM_CLOCK_GATE_DISABLE             (1 << 3)
3509 # define I915_PS_CLOCK_GATE_DISABLE             (1 << 2)
3510 # define I915_CC_CLOCK_GATE_DISABLE             (1 << 1)
3511 # define I915_BY_CLOCK_GATE_DISABLE             (1 << 0)
3512
3513 # define I965_RCZ_CLOCK_GATE_DISABLE            (1 << 30)
3514 /* This bit must always be set on 965G/965GM */
3515 # define I965_RCC_CLOCK_GATE_DISABLE            (1 << 29)
3516 # define I965_RCPB_CLOCK_GATE_DISABLE           (1 << 28)
3517 # define I965_DAP_CLOCK_GATE_DISABLE            (1 << 27)
3518 # define I965_ROC_CLOCK_GATE_DISABLE            (1 << 26)
3519 # define I965_GW_CLOCK_GATE_DISABLE             (1 << 25)
3520 # define I965_TD_CLOCK_GATE_DISABLE             (1 << 24)
3521 /* This bit must always be set on 965G */
3522 # define I965_ISC_CLOCK_GATE_DISABLE            (1 << 23)
3523 # define I965_IC_CLOCK_GATE_DISABLE             (1 << 22)
3524 # define I965_EU_CLOCK_GATE_DISABLE             (1 << 21)
3525 # define I965_IF_CLOCK_GATE_DISABLE             (1 << 20)
3526 # define I965_TC_CLOCK_GATE_DISABLE             (1 << 19)
3527 # define I965_SO_CLOCK_GATE_DISABLE             (1 << 17)
3528 # define I965_FBC_CLOCK_GATE_DISABLE            (1 << 16)
3529 # define I965_MARI_CLOCK_GATE_DISABLE           (1 << 15)
3530 # define I965_MASF_CLOCK_GATE_DISABLE           (1 << 14)
3531 # define I965_MAWB_CLOCK_GATE_DISABLE           (1 << 13)
3532 # define I965_EM_CLOCK_GATE_DISABLE             (1 << 12)
3533 # define I965_UC_CLOCK_GATE_DISABLE             (1 << 11)
3534 # define I965_SI_CLOCK_GATE_DISABLE             (1 << 6)
3535 # define I965_MT_CLOCK_GATE_DISABLE             (1 << 5)
3536 # define I965_PL_CLOCK_GATE_DISABLE             (1 << 4)
3537 # define I965_DG_CLOCK_GATE_DISABLE             (1 << 3)
3538 # define I965_QC_CLOCK_GATE_DISABLE             (1 << 2)
3539 # define I965_FT_CLOCK_GATE_DISABLE             (1 << 1)
3540 # define I965_DM_CLOCK_GATE_DISABLE             (1 << 0)
3541
3542 #define RENCLK_GATE_D2          _MMIO(0x6208)
3543 #define VF_UNIT_CLOCK_GATE_DISABLE              (1 << 9)
3544 #define GS_UNIT_CLOCK_GATE_DISABLE              (1 << 7)
3545 #define CL_UNIT_CLOCK_GATE_DISABLE              (1 << 6)
3546
3547 #define VDECCLK_GATE_D          _MMIO(0x620C)           /* g4x only */
3548 #define  VCP_UNIT_CLOCK_GATE_DISABLE            (1 << 4)
3549
3550 #define RAMCLK_GATE_D           _MMIO(0x6210)           /* CRL only */
3551 #define DEUC                    _MMIO(0x6214)          /* CRL only */
3552
3553 #define FW_BLC_SELF_VLV         _MMIO(VLV_DISPLAY_BASE + 0x6500)
3554 #define  FW_CSPWRDWNEN          (1 << 15)
3555
3556 #define MI_ARB_VLV              _MMIO(VLV_DISPLAY_BASE + 0x6504)
3557
3558 #define CZCLK_CDCLK_FREQ_RATIO  _MMIO(VLV_DISPLAY_BASE + 0x6508)
3559 #define   CDCLK_FREQ_SHIFT      4
3560 #define   CDCLK_FREQ_MASK       (0x1f << CDCLK_FREQ_SHIFT)
3561 #define   CZCLK_FREQ_MASK       0xf
3562
3563 #define GCI_CONTROL             _MMIO(VLV_DISPLAY_BASE + 0x650C)
3564 #define   PFI_CREDIT_63         (9 << 28)               /* chv only */
3565 #define   PFI_CREDIT_31         (8 << 28)               /* chv only */
3566 #define   PFI_CREDIT(x)         (((x) - 8) << 28)       /* 8-15 */
3567 #define   PFI_CREDIT_RESEND     (1 << 27)
3568 #define   VGA_FAST_MODE_DISABLE (1 << 14)
3569
3570 #define GMBUSFREQ_VLV           _MMIO(VLV_DISPLAY_BASE + 0x6510)
3571
3572 /*
3573  * Palette regs
3574  */
3575 #define _PALETTE_A              0xa000
3576 #define _PALETTE_B              0xa800
3577 #define _CHV_PALETTE_C          0xc000
3578 #define PALETTE(pipe, i)        _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
3579                                       _PICK((pipe), _PALETTE_A,         \
3580                                             _PALETTE_B, _CHV_PALETTE_C) + \
3581                                       (i) * 4)
3582
3583 /* MCH MMIO space */
3584
3585 /*
3586  * MCHBAR mirror.
3587  *
3588  * This mirrors the MCHBAR MMIO space whose location is determined by
3589  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3590  * every way.  It is not accessible from the CP register read instructions.
3591  *
3592  * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3593  * just read.
3594  */
3595 #define MCHBAR_MIRROR_BASE      0x10000
3596
3597 #define MCHBAR_MIRROR_BASE_SNB  0x140000
3598
3599 #define CTG_STOLEN_RESERVED             _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3600 #define ELK_STOLEN_RESERVED             _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3601 #define G4X_STOLEN_RESERVED_ADDR1_MASK  (0xFFFF << 16)
3602 #define G4X_STOLEN_RESERVED_ADDR2_MASK  (0xFFF << 4)
3603 #define G4X_STOLEN_RESERVED_ENABLE      (1 << 0)
3604
3605 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3606 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3607
3608 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3609 #define DCC                     _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3610 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL              (0 << 0)
3611 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC     (1 << 0)
3612 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED    (2 << 0)
3613 #define DCC_ADDRESSING_MODE_MASK                        (3 << 0)
3614 #define DCC_CHANNEL_XOR_DISABLE                         (1 << 10)
3615 #define DCC_CHANNEL_XOR_BIT_17                          (1 << 9)
3616 #define DCC2                    _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3617 #define DCC2_MODIFIED_ENHANCED_DISABLE                  (1 << 20)
3618
3619 /* Pineview MCH register contains DDR3 setting */
3620 #define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3621 #define CSHRDDR3CTL_DDR3       (1 << 2)
3622
3623 /* 965 MCH register controlling DRAM channel configuration */
3624 #define C0DRB3                  _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3625 #define C1DRB3                  _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3626
3627 /* snb MCH registers for reading the DRAM channel configuration */
3628 #define MAD_DIMM_C0                     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3629 #define MAD_DIMM_C1                     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3630 #define MAD_DIMM_C2                     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3631 #define   MAD_DIMM_ECC_MASK             (0x3 << 24)
3632 #define   MAD_DIMM_ECC_OFF              (0x0 << 24)
3633 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF  (0x1 << 24)
3634 #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON  (0x2 << 24)
3635 #define   MAD_DIMM_ECC_ON               (0x3 << 24)
3636 #define   MAD_DIMM_ENH_INTERLEAVE       (0x1 << 22)
3637 #define   MAD_DIMM_RANK_INTERLEAVE      (0x1 << 21)
3638 #define   MAD_DIMM_B_WIDTH_X16          (0x1 << 20) /* X8 chips if unset */
3639 #define   MAD_DIMM_A_WIDTH_X16          (0x1 << 19) /* X8 chips if unset */
3640 #define   MAD_DIMM_B_DUAL_RANK          (0x1 << 18)
3641 #define   MAD_DIMM_A_DUAL_RANK          (0x1 << 17)
3642 #define   MAD_DIMM_A_SELECT             (0x1 << 16)
3643 /* DIMM sizes are in multiples of 256mb. */
3644 #define   MAD_DIMM_B_SIZE_SHIFT         8
3645 #define   MAD_DIMM_B_SIZE_MASK          (0xff << MAD_DIMM_B_SIZE_SHIFT)
3646 #define   MAD_DIMM_A_SIZE_SHIFT         0
3647 #define   MAD_DIMM_A_SIZE_MASK          (0xff << MAD_DIMM_A_SIZE_SHIFT)
3648
3649 /* snb MCH registers for priority tuning */
3650 #define MCH_SSKPD                       _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3651 #define   MCH_SSKPD_WM0_MASK            0x3f
3652 #define   MCH_SSKPD_WM0_VAL             0xc
3653
3654 #define MCH_SECP_NRG_STTS               _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3655
3656 /* Clocking configuration register */
3657 #define CLKCFG                  _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3658 #define CLKCFG_FSB_400                                  (5 << 0)        /* hrawclk 100 */
3659 #define CLKCFG_FSB_533                                  (1 << 0)        /* hrawclk 133 */
3660 #define CLKCFG_FSB_667                                  (3 << 0)        /* hrawclk 166 */
3661 #define CLKCFG_FSB_800                                  (2 << 0)        /* hrawclk 200 */
3662 #define CLKCFG_FSB_1067                                 (6 << 0)        /* hrawclk 266 */
3663 #define CLKCFG_FSB_1067_ALT                             (0 << 0)        /* hrawclk 266 */
3664 #define CLKCFG_FSB_1333                                 (7 << 0)        /* hrawclk 333 */
3665 /*
3666  * Note that on at least on ELK the below value is reported for both
3667  * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3668  * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3669  */
3670 #define CLKCFG_FSB_1333_ALT                             (4 << 0)        /* hrawclk 333 */
3671 #define CLKCFG_FSB_MASK                                 (7 << 0)
3672 #define CLKCFG_MEM_533                                  (1 << 4)
3673 #define CLKCFG_MEM_667                                  (2 << 4)
3674 #define CLKCFG_MEM_800                                  (3 << 4)
3675 #define CLKCFG_MEM_MASK                                 (7 << 4)
3676
3677 #define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3678 #define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3679
3680 #define TSC1                    _MMIO(0x11001)
3681 #define   TSE                   (1 << 0)
3682 #define TR1                     _MMIO(0x11006)
3683 #define TSFS                    _MMIO(0x11020)
3684 #define   TSFS_SLOPE_MASK       0x0000ff00
3685 #define   TSFS_SLOPE_SHIFT      8
3686 #define   TSFS_INTR_MASK        0x000000ff
3687
3688 #define CRSTANDVID              _MMIO(0x11100)
3689 #define PXVFREQ(fstart)         _MMIO(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3690 #define   PXVFREQ_PX_MASK       0x7f000000
3691 #define   PXVFREQ_PX_SHIFT      24
3692 #define VIDFREQ_BASE            _MMIO(0x11110)
3693 #define VIDFREQ1                _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3694 #define VIDFREQ2                _MMIO(0x11114)
3695 #define VIDFREQ3                _MMIO(0x11118)
3696 #define VIDFREQ4                _MMIO(0x1111c)
3697 #define   VIDFREQ_P0_MASK       0x1f000000
3698 #define   VIDFREQ_P0_SHIFT      24
3699 #define   VIDFREQ_P0_CSCLK_MASK 0x00f00000
3700 #define   VIDFREQ_P0_CSCLK_SHIFT 20
3701 #define   VIDFREQ_P0_CRCLK_MASK 0x000f0000
3702 #define   VIDFREQ_P0_CRCLK_SHIFT 16
3703 #define   VIDFREQ_P1_MASK       0x00001f00
3704 #define   VIDFREQ_P1_SHIFT      8
3705 #define   VIDFREQ_P1_CSCLK_MASK 0x000000f0
3706 #define   VIDFREQ_P1_CSCLK_SHIFT 4
3707 #define   VIDFREQ_P1_CRCLK_MASK 0x0000000f
3708 #define INTTOEXT_BASE_ILK       _MMIO(0x11300)
3709 #define INTTOEXT_BASE           _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3710 #define   INTTOEXT_MAP3_SHIFT   24
3711 #define   INTTOEXT_MAP3_MASK    (0x1f << INTTOEXT_MAP3_SHIFT)
3712 #define   INTTOEXT_MAP2_SHIFT   16
3713 #define   INTTOEXT_MAP2_MASK    (0x1f << INTTOEXT_MAP2_SHIFT)
3714 #define   INTTOEXT_MAP1_SHIFT   8
3715 #define   INTTOEXT_MAP1_MASK    (0x1f << INTTOEXT_MAP1_SHIFT)
3716 #define   INTTOEXT_MAP0_SHIFT   0
3717 #define   INTTOEXT_MAP0_MASK    (0x1f << INTTOEXT_MAP0_SHIFT)
3718 #define MEMSWCTL                _MMIO(0x11170) /* Ironlake only */
3719 #define   MEMCTL_CMD_MASK       0xe000
3720 #define   MEMCTL_CMD_SHIFT      13
3721 #define   MEMCTL_CMD_RCLK_OFF   0
3722 #define   MEMCTL_CMD_RCLK_ON    1
3723 #define   MEMCTL_CMD_CHFREQ     2
3724 #define   MEMCTL_CMD_CHVID      3
3725 #define   MEMCTL_CMD_VMMOFF     4
3726 #define   MEMCTL_CMD_VMMON      5
3727 #define   MEMCTL_CMD_STS        (1 << 12) /* write 1 triggers command, clears
3728                                            when command complete */
3729 #define   MEMCTL_FREQ_MASK      0x0f00 /* jitter, from 0-15 */
3730 #define   MEMCTL_FREQ_SHIFT     8
3731 #define   MEMCTL_SFCAVM         (1 << 7)
3732 #define   MEMCTL_TGT_VID_MASK   0x007f
3733 #define MEMIHYST                _MMIO(0x1117c)
3734 #define MEMINTREN               _MMIO(0x11180) /* 16 bits */
3735 #define   MEMINT_RSEXIT_EN      (1 << 8)
3736 #define   MEMINT_CX_SUPR_EN     (1 << 7)
3737 #define   MEMINT_CONT_BUSY_EN   (1 << 6)
3738 #define   MEMINT_AVG_BUSY_EN    (1 << 5)
3739 #define   MEMINT_EVAL_CHG_EN    (1 << 4)
3740 #define   MEMINT_MON_IDLE_EN    (1 << 3)
3741 #define   MEMINT_UP_EVAL_EN     (1 << 2)
3742 #define   MEMINT_DOWN_EVAL_EN   (1 << 1)
3743 #define   MEMINT_SW_CMD_EN      (1 << 0)
3744 #define MEMINTRSTR              _MMIO(0x11182) /* 16 bits */
3745 #define   MEM_RSEXIT_MASK       0xc000
3746 #define   MEM_RSEXIT_SHIFT      14
3747 #define   MEM_CONT_BUSY_MASK    0x3000
3748 #define   MEM_CONT_BUSY_SHIFT   12
3749 #define   MEM_AVG_BUSY_MASK     0x0c00
3750 #define   MEM_AVG_BUSY_SHIFT    10
3751 #define   MEM_EVAL_CHG_MASK     0x0300
3752 #define   MEM_EVAL_BUSY_SHIFT   8
3753 #define   MEM_MON_IDLE_MASK     0x00c0
3754 #define   MEM_MON_IDLE_SHIFT    6
3755 #define   MEM_UP_EVAL_MASK      0x0030
3756 #define   MEM_UP_EVAL_SHIFT     4
3757 #define   MEM_DOWN_EVAL_MASK    0x000c
3758 #define   MEM_DOWN_EVAL_SHIFT   2
3759 #define   MEM_SW_CMD_MASK       0x0003
3760 #define   MEM_INT_STEER_GFX     0
3761 #define   MEM_INT_STEER_CMR     1
3762 #define   MEM_INT_STEER_SMI     2
3763 #define   MEM_INT_STEER_SCI     3
3764 #define MEMINTRSTS              _MMIO(0x11184)
3765 #define   MEMINT_RSEXIT         (1 << 7)
3766 #define   MEMINT_CONT_BUSY      (1 << 6)
3767 #define   MEMINT_AVG_BUSY       (1 << 5)
3768 #define   MEMINT_EVAL_CHG       (1 << 4)
3769 #define   MEMINT_MON_IDLE       (1 << 3)
3770 #define   MEMINT_UP_EVAL        (1 << 2)
3771 #define   MEMINT_DOWN_EVAL      (1 << 1)
3772 #define   MEMINT_SW_CMD         (1 << 0)
3773 #define MEMMODECTL              _MMIO(0x11190)
3774 #define   MEMMODE_BOOST_EN      (1 << 31)
3775 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3776 #define   MEMMODE_BOOST_FREQ_SHIFT 24
3777 #define   MEMMODE_IDLE_MODE_MASK 0x00030000
3778 #define   MEMMODE_IDLE_MODE_SHIFT 16
3779 #define   MEMMODE_IDLE_MODE_EVAL 0
3780 #define   MEMMODE_IDLE_MODE_CONT 1
3781 #define   MEMMODE_HWIDLE_EN     (1 << 15)
3782 #define   MEMMODE_SWMODE_EN     (1 << 14)
3783 #define   MEMMODE_RCLK_GATE     (1 << 13)
3784 #define   MEMMODE_HW_UPDATE     (1 << 12)
3785 #define   MEMMODE_FSTART_MASK   0x00000f00 /* starting jitter, 0-15 */
3786 #define   MEMMODE_FSTART_SHIFT  8
3787 #define   MEMMODE_FMAX_MASK     0x000000f0 /* max jitter, 0-15 */
3788 #define   MEMMODE_FMAX_SHIFT    4
3789 #define   MEMMODE_FMIN_MASK     0x0000000f /* min jitter, 0-15 */
3790 #define RCBMAXAVG               _MMIO(0x1119c)
3791 #define MEMSWCTL2               _MMIO(0x1119e) /* Cantiga only */
3792 #define   SWMEMCMD_RENDER_OFF   (0 << 13)
3793 #define   SWMEMCMD_RENDER_ON    (1 << 13)
3794 #define   SWMEMCMD_SWFREQ       (2 << 13)
3795 #define   SWMEMCMD_TARVID       (3 << 13)
3796 #define   SWMEMCMD_VRM_OFF      (4 << 13)
3797 #define   SWMEMCMD_VRM_ON       (5 << 13)
3798 #define   CMDSTS                (1 << 12)
3799 #define   SFCAVM                (1 << 11)
3800 #define   SWFREQ_MASK           0x0380 /* P0-7 */
3801 #define   SWFREQ_SHIFT          7
3802 #define   TARVID_MASK           0x001f
3803 #define MEMSTAT_CTG             _MMIO(0x111a0)
3804 #define RCBMINAVG               _MMIO(0x111a0)
3805 #define RCUPEI                  _MMIO(0x111b0)
3806 #define RCDNEI                  _MMIO(0x111b4)
3807 #define RSTDBYCTL               _MMIO(0x111b8)
3808 #define   RS1EN                 (1 << 31)
3809 #define   RS2EN                 (1 << 30)
3810 #define   RS3EN                 (1 << 29)
3811 #define   D3RS3EN               (1 << 28) /* Display D3 imlies RS3 */
3812 #define   SWPROMORSX            (1 << 27) /* RSx promotion timers ignored */
3813 #define   RCWAKERW              (1 << 26) /* Resetwarn from PCH causes wakeup */
3814 #define   DPRSLPVREN            (1 << 25) /* Fast voltage ramp enable */
3815 #define   GFXTGHYST             (1 << 24) /* Hysteresis to allow trunk gating */
3816 #define   RCX_SW_EXIT           (1 << 23) /* Leave RSx and prevent re-entry */
3817 #define   RSX_STATUS_MASK       (7 << 20)
3818 #define   RSX_STATUS_ON         (0 << 20)
3819 #define   RSX_STATUS_RC1        (1 << 20)
3820 #define   RSX_STATUS_RC1E       (2 << 20)
3821 #define   RSX_STATUS_RS1        (3 << 20)
3822 #define   RSX_STATUS_RS2        (4 << 20) /* aka rc6 */
3823 #define   RSX_STATUS_RSVD       (5 << 20) /* deep rc6 unsupported on ilk */
3824 #define   RSX_STATUS_RS3        (6 << 20) /* rs3 unsupported on ilk */
3825 #define   RSX_STATUS_RSVD2      (7 << 20)
3826 #define   UWRCRSXE              (1 << 19) /* wake counter limit prevents rsx */
3827 #define   RSCRP                 (1 << 18) /* rs requests control on rs1/2 reqs */
3828 #define   JRSC                  (1 << 17) /* rsx coupled to cpu c-state */
3829 #define   RS2INC0               (1 << 16) /* allow rs2 in cpu c0 */
3830 #define   RS1CONTSAV_MASK       (3 << 14)
3831 #define   RS1CONTSAV_NO_RS1     (0 << 14) /* rs1 doesn't save/restore context */
3832 #define   RS1CONTSAV_RSVD       (1 << 14)
3833 #define   RS1CONTSAV_SAVE_RS1   (2 << 14) /* rs1 saves context */
3834 #define   RS1CONTSAV_FULL_RS1   (3 << 14) /* rs1 saves and restores context */
3835 #define   NORMSLEXLAT_MASK      (3 << 12)
3836 #define   SLOW_RS123            (0 << 12)
3837 #define   SLOW_RS23             (1 << 12)
3838 #define   SLOW_RS3              (2 << 12)
3839 #define   NORMAL_RS123          (3 << 12)
3840 #define   RCMODE_TIMEOUT        (1 << 11) /* 0 is eval interval method */
3841 #define   IMPROMOEN             (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3842 #define   RCENTSYNC             (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3843 #define   STATELOCK             (1 << 7) /* locked to rs_cstate if 0 */
3844 #define   RS_CSTATE_MASK        (3 << 4)
3845 #define   RS_CSTATE_C367_RS1    (0 << 4)
3846 #define   RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
3847 #define   RS_CSTATE_RSVD        (2 << 4)
3848 #define   RS_CSTATE_C367_RS2    (3 << 4)
3849 #define   REDSAVES              (1 << 3) /* no context save if was idle during rs0 */
3850 #define   REDRESTORES           (1 << 2) /* no restore if was idle during rs0 */
3851 #define VIDCTL                  _MMIO(0x111c0)
3852 #define VIDSTS                  _MMIO(0x111c8)
3853 #define VIDSTART                _MMIO(0x111cc) /* 8 bits */
3854 #define MEMSTAT_ILK             _MMIO(0x111f8)
3855 #define   MEMSTAT_VID_MASK      0x7f00
3856 #define   MEMSTAT_VID_SHIFT     8
3857 #define   MEMSTAT_PSTATE_MASK   0x00f8
3858 #define   MEMSTAT_PSTATE_SHIFT  3
3859 #define   MEMSTAT_MON_ACTV      (1 << 2)
3860 #define   MEMSTAT_SRC_CTL_MASK  0x0003
3861 #define   MEMSTAT_SRC_CTL_CORE  0
3862 #define   MEMSTAT_SRC_CTL_TRB   1
3863 #define   MEMSTAT_SRC_CTL_THM   2
3864 #define   MEMSTAT_SRC_CTL_STDBY 3
3865 #define RCPREVBSYTUPAVG         _MMIO(0x113b8)
3866 #define RCPREVBSYTDNAVG         _MMIO(0x113bc)
3867 #define PMMISC                  _MMIO(0x11214)
3868 #define   MCPPCE_EN             (1 << 0) /* enable PM_MSG from PCH->MPC */
3869 #define SDEW                    _MMIO(0x1124c)
3870 #define CSIEW0                  _MMIO(0x11250)
3871 #define CSIEW1                  _MMIO(0x11254)
3872 #define CSIEW2                  _MMIO(0x11258)
3873 #define PEW(i)                  _MMIO(0x1125c + (i) * 4) /* 5 registers */
3874 #define DEW(i)                  _MMIO(0x11270 + (i) * 4) /* 3 registers */
3875 #define MCHAFE                  _MMIO(0x112c0)
3876 #define CSIEC                   _MMIO(0x112e0)
3877 #define DMIEC                   _MMIO(0x112e4)
3878 #define DDREC                   _MMIO(0x112e8)
3879 #define PEG0EC                  _MMIO(0x112ec)
3880 #define PEG1EC                  _MMIO(0x112f0)
3881 #define GFXEC                   _MMIO(0x112f4)
3882 #define RPPREVBSYTUPAVG         _MMIO(0x113b8)
3883 #define RPPREVBSYTDNAVG         _MMIO(0x113bc)
3884 #define ECR                     _MMIO(0x11600)
3885 #define   ECR_GPFE              (1 << 31)
3886 #define   ECR_IMONE             (1 << 30)
3887 #define   ECR_CAP_MASK          0x0000001f /* Event range, 0-31 */
3888 #define OGW0                    _MMIO(0x11608)
3889 #define OGW1                    _MMIO(0x1160c)
3890 #define EG0                     _MMIO(0x11610)
3891 #define EG1                     _MMIO(0x11614)
3892 #define EG2                     _MMIO(0x11618)
3893 #define EG3                     _MMIO(0x1161c)
3894 #define EG4                     _MMIO(0x11620)
3895 #define EG5                     _MMIO(0x11624)
3896 #define EG6                     _MMIO(0x11628)
3897 #define EG7                     _MMIO(0x1162c)
3898 #define PXW(i)                  _MMIO(0x11664 + (i) * 4) /* 4 registers */
3899 #define PXWL(i)                 _MMIO(0x11680 + (i) * 8) /* 8 registers */
3900 #define LCFUSE02                _MMIO(0x116c0)
3901 #define   LCFUSE_HIV_MASK       0x000000ff
3902 #define CSIPLL0                 _MMIO(0x12c10)
3903 #define DDRMPLL1                _MMIO(0X12c20)
3904 #define PEG_BAND_GAP_DATA       _MMIO(0x14d68)
3905
3906 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3907 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
3908
3909 #define GEN6_GT_PERF_STATUS     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3910 #define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3911 #define GEN6_RP_STATE_LIMITS    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3912 #define GEN6_RP_STATE_CAP       _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3913 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
3914
3915 /*
3916  * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3917  * 8300) freezing up around GPU hangs. Looks as if even
3918  * scheduling/timer interrupts start misbehaving if the RPS
3919  * EI/thresholds are "bad", leading to a very sluggish or even
3920  * frozen machine.
3921  */
3922 #define INTERVAL_1_28_US(us)    roundup(((us) * 100) >> 7, 25)
3923 #define INTERVAL_1_33_US(us)    (((us) * 3)   >> 2)
3924 #define INTERVAL_0_833_US(us)   (((us) * 6) / 5)
3925 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3926                                 (IS_GEN9_LP(dev_priv) ? \
3927                                 INTERVAL_0_833_US(us) : \
3928                                 INTERVAL_1_33_US(us)) : \
3929                                 INTERVAL_1_28_US(us))
3930
3931 #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
3932 #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
3933 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
3934 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3935                            (IS_GEN9_LP(dev_priv) ? \
3936                            INTERVAL_0_833_TO_US(interval) : \
3937                            INTERVAL_1_33_TO_US(interval)) : \
3938                            INTERVAL_1_28_TO_US(interval))
3939
3940 /*
3941  * Logical Context regs
3942  */
3943 #define CCID(base)                      _MMIO((base) + 0x180)
3944 #define   CCID_EN                       BIT(0)
3945 #define   CCID_EXTENDED_STATE_RESTORE   BIT(2)
3946 #define   CCID_EXTENDED_STATE_SAVE      BIT(3)
3947 /*
3948  * Notes on SNB/IVB/VLV context size:
3949  * - Power context is saved elsewhere (LLC or stolen)
3950  * - Ring/execlist context is saved on SNB, not on IVB
3951  * - Extended context size already includes render context size
3952  * - We always need to follow the extended context size.
3953  *   SNB BSpec has comments indicating that we should use the
3954  *   render context size instead if execlists are disabled, but
3955  *   based on empirical testing that's just nonsense.
3956  * - Pipelined/VF state is saved on SNB/IVB respectively
3957  * - GT1 size just indicates how much of render context
3958  *   doesn't need saving on GT1
3959  */
3960 #define CXT_SIZE                _MMIO(0x21a0)
3961 #define GEN6_CXT_POWER_SIZE(cxt_reg)    (((cxt_reg) >> 24) & 0x3f)
3962 #define GEN6_CXT_RING_SIZE(cxt_reg)     (((cxt_reg) >> 18) & 0x3f)
3963 #define GEN6_CXT_RENDER_SIZE(cxt_reg)   (((cxt_reg) >> 12) & 0x3f)
3964 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3965 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
3966 #define GEN6_CXT_TOTAL_SIZE(cxt_reg)    (GEN6_CXT_RING_SIZE(cxt_reg) + \
3967                                         GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3968                                         GEN6_CXT_PIPELINE_SIZE(cxt_reg))
3969 #define GEN7_CXT_SIZE           _MMIO(0x21a8)
3970 #define GEN7_CXT_POWER_SIZE(ctx_reg)    (((ctx_reg) >> 25) & 0x7f)
3971 #define GEN7_CXT_RING_SIZE(ctx_reg)     (((ctx_reg) >> 22) & 0x7)
3972 #define GEN7_CXT_RENDER_SIZE(ctx_reg)   (((ctx_reg) >> 16) & 0x3f)
3973 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3974 #define GEN7_CXT_GT1_SIZE(ctx_reg)      (((ctx_reg) >> 6) & 0x7)
3975 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)  (((ctx_reg) >> 0) & 0x3f)
3976 #define GEN7_CXT_TOTAL_SIZE(ctx_reg)    (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3977                                          GEN7_CXT_VFSTATE_SIZE(ctx_reg))
3978
3979 enum {
3980         INTEL_ADVANCED_CONTEXT = 0,
3981         INTEL_LEGACY_32B_CONTEXT,
3982         INTEL_ADVANCED_AD_CONTEXT,
3983         INTEL_LEGACY_64B_CONTEXT
3984 };
3985
3986 enum {
3987         FAULT_AND_HANG = 0,
3988         FAULT_AND_HALT, /* Debug only */
3989         FAULT_AND_STREAM,
3990         FAULT_AND_CONTINUE /* Unsupported */
3991 };
3992
3993 #define GEN8_CTX_VALID (1 << 0)
3994 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
3995 #define GEN8_CTX_FORCE_RESTORE (1 << 2)
3996 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
3997 #define GEN8_CTX_PRIVILEGE (1 << 8)
3998 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
3999
4000 #define GEN8_CTX_ID_SHIFT 32
4001 #define GEN8_CTX_ID_WIDTH 21
4002 #define GEN11_SW_CTX_ID_SHIFT 37
4003 #define GEN11_SW_CTX_ID_WIDTH 11
4004 #define GEN11_ENGINE_CLASS_SHIFT 61
4005 #define GEN11_ENGINE_CLASS_WIDTH 3
4006 #define GEN11_ENGINE_INSTANCE_SHIFT 48
4007 #define GEN11_ENGINE_INSTANCE_WIDTH 6
4008
4009 #define CHV_CLK_CTL1                    _MMIO(0x101100)
4010 #define VLV_CLK_CTL2                    _MMIO(0x101104)
4011 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT   28
4012
4013 /*
4014  * Overlay regs
4015  */
4016
4017 #define OVADD                   _MMIO(0x30000)
4018 #define DOVSTA                  _MMIO(0x30008)
4019 #define OC_BUF                  (0x3 << 20)
4020 #define OGAMC5                  _MMIO(0x30010)
4021 #define OGAMC4                  _MMIO(0x30014)
4022 #define OGAMC3                  _MMIO(0x30018)
4023 #define OGAMC2                  _MMIO(0x3001c)
4024 #define OGAMC1                  _MMIO(0x30020)
4025 #define OGAMC0                  _MMIO(0x30024)
4026
4027 /*
4028  * GEN9 clock gating regs
4029  */
4030 #define GEN9_CLKGATE_DIS_0              _MMIO(0x46530)
4031 #define   DARBF_GATING_DIS              (1 << 27)
4032 #define   PWM2_GATING_DIS               (1 << 14)
4033 #define   PWM1_GATING_DIS               (1 << 13)
4034
4035 #define GEN9_CLKGATE_DIS_4              _MMIO(0x4653C)
4036 #define   BXT_GMBUS_GATING_DIS          (1 << 14)
4037
4038 #define _CLKGATE_DIS_PSL_A              0x46520
4039 #define _CLKGATE_DIS_PSL_B              0x46524
4040 #define _CLKGATE_DIS_PSL_C              0x46528
4041 #define   DUPS1_GATING_DIS              (1 << 15)
4042 #define   DUPS2_GATING_DIS              (1 << 19)
4043 #define   DUPS3_GATING_DIS              (1 << 23)
4044 #define   DPF_GATING_DIS                (1 << 10)
4045 #define   DPF_RAM_GATING_DIS            (1 << 9)
4046 #define   DPFR_GATING_DIS               (1 << 8)
4047
4048 #define CLKGATE_DIS_PSL(pipe) \
4049         _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
4050
4051 /*
4052  * GEN10 clock gating regs
4053  */
4054 #define SLICE_UNIT_LEVEL_CLKGATE        _MMIO(0x94d4)
4055 #define  SARBUNIT_CLKGATE_DIS           (1 << 5)
4056 #define  RCCUNIT_CLKGATE_DIS            (1 << 7)
4057 #define  MSCUNIT_CLKGATE_DIS            (1 << 10)
4058
4059 #define SUBSLICE_UNIT_LEVEL_CLKGATE     _MMIO(0x9524)
4060 #define  GWUNIT_CLKGATE_DIS             (1 << 16)
4061
4062 #define UNSLICE_UNIT_LEVEL_CLKGATE      _MMIO(0x9434)
4063 #define   VFUNIT_CLKGATE_DIS            REG_BIT(20)
4064 #define   HSUNIT_CLKGATE_DIS            REG_BIT(8)
4065 #define   VSUNIT_CLKGATE_DIS            REG_BIT(3)
4066
4067 #define UNSLICE_UNIT_LEVEL_CLKGATE2     _MMIO(0x94e4)
4068 #define   VSUNIT_CLKGATE_DIS_TGL        REG_BIT(19)
4069 #define   PSDUNIT_CLKGATE_DIS           REG_BIT(5)
4070
4071 #define INF_UNIT_LEVEL_CLKGATE          _MMIO(0x9560)
4072 #define   CGPSF_CLKGATE_DIS             (1 << 3)
4073
4074 /*
4075  * Display engine regs
4076  */
4077
4078 /* Pipe A CRC regs */
4079 #define _PIPE_CRC_CTL_A                 0x60050
4080 #define   PIPE_CRC_ENABLE               (1 << 31)
4081 /* skl+ source selection */
4082 #define   PIPE_CRC_SOURCE_PLANE_1_SKL   (0 << 28)
4083 #define   PIPE_CRC_SOURCE_PLANE_2_SKL   (2 << 28)
4084 #define   PIPE_CRC_SOURCE_DMUX_SKL      (4 << 28)
4085 #define   PIPE_CRC_SOURCE_PLANE_3_SKL   (6 << 28)
4086 #define   PIPE_CRC_SOURCE_PLANE_4_SKL   (7 << 28)
4087 #define   PIPE_CRC_SOURCE_PLANE_5_SKL   (5 << 28)
4088 #define   PIPE_CRC_SOURCE_PLANE_6_SKL   (3 << 28)
4089 #define   PIPE_CRC_SOURCE_PLANE_7_SKL   (1 << 28)
4090 /* ivb+ source selection */
4091 #define   PIPE_CRC_SOURCE_PRIMARY_IVB   (0 << 29)
4092 #define   PIPE_CRC_SOURCE_SPRITE_IVB    (1 << 29)
4093 #define   PIPE_CRC_SOURCE_PF_IVB        (2 << 29)
4094 /* ilk+ source selection */
4095 #define   PIPE_CRC_SOURCE_PRIMARY_ILK   (0 << 28)
4096 #define   PIPE_CRC_SOURCE_SPRITE_ILK    (1 << 28)
4097 #define   PIPE_CRC_SOURCE_PIPE_ILK      (2 << 28)
4098 /* embedded DP port on the north display block, reserved on ivb */
4099 #define   PIPE_CRC_SOURCE_PORT_A_ILK    (4 << 28)
4100 #define   PIPE_CRC_SOURCE_FDI_ILK       (5 << 28) /* reserved on ivb */
4101 /* vlv source selection */
4102 #define   PIPE_CRC_SOURCE_PIPE_VLV      (0 << 27)
4103 #define   PIPE_CRC_SOURCE_HDMIB_VLV     (1 << 27)
4104 #define   PIPE_CRC_SOURCE_HDMIC_VLV     (2 << 27)
4105 /* with DP port the pipe source is invalid */
4106 #define   PIPE_CRC_SOURCE_DP_D_VLV      (3 << 27)
4107 #define   PIPE_CRC_SOURCE_DP_B_VLV      (6 << 27)
4108 #define   PIPE_CRC_SOURCE_DP_C_VLV      (7 << 27)
4109 /* gen3+ source selection */
4110 #define   PIPE_CRC_SOURCE_PIPE_I9XX     (0 << 28)
4111 #define   PIPE_CRC_SOURCE_SDVOB_I9XX    (1 << 28)
4112 #define   PIPE_CRC_SOURCE_SDVOC_I9XX    (2 << 28)
4113 /* with DP/TV port the pipe source is invalid */
4114 #define   PIPE_CRC_SOURCE_DP_D_G4X      (3 << 28)
4115 #define   PIPE_CRC_SOURCE_TV_PRE        (4 << 28)
4116 #define   PIPE_CRC_SOURCE_TV_POST       (5 << 28)
4117 #define   PIPE_CRC_SOURCE_DP_B_G4X      (6 << 28)
4118 #define   PIPE_CRC_SOURCE_DP_C_G4X      (7 << 28)
4119 /* gen2 doesn't have source selection bits */
4120 #define   PIPE_CRC_INCLUDE_BORDER_I8XX  (1 << 30)
4121
4122 #define _PIPE_CRC_RES_1_A_IVB           0x60064
4123 #define _PIPE_CRC_RES_2_A_IVB           0x60068
4124 #define _PIPE_CRC_RES_3_A_IVB           0x6006c
4125 #define _PIPE_CRC_RES_4_A_IVB           0x60070
4126 #define _PIPE_CRC_RES_5_A_IVB           0x60074
4127
4128 #define _PIPE_CRC_RES_RED_A             0x60060
4129 #define _PIPE_CRC_RES_GREEN_A           0x60064
4130 #define _PIPE_CRC_RES_BLUE_A            0x60068
4131 #define _PIPE_CRC_RES_RES1_A_I915       0x6006c
4132 #define _PIPE_CRC_RES_RES2_A_G4X        0x60080
4133
4134 /* Pipe B CRC regs */
4135 #define _PIPE_CRC_RES_1_B_IVB           0x61064
4136 #define _PIPE_CRC_RES_2_B_IVB           0x61068
4137 #define _PIPE_CRC_RES_3_B_IVB           0x6106c
4138 #define _PIPE_CRC_RES_4_B_IVB           0x61070
4139 #define _PIPE_CRC_RES_5_B_IVB           0x61074
4140
4141 #define PIPE_CRC_CTL(pipe)              _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4142 #define PIPE_CRC_RES_1_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4143 #define PIPE_CRC_RES_2_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4144 #define PIPE_CRC_RES_3_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4145 #define PIPE_CRC_RES_4_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4146 #define PIPE_CRC_RES_5_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4147
4148 #define PIPE_CRC_RES_RED(pipe)          _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4149 #define PIPE_CRC_RES_GREEN(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4150 #define PIPE_CRC_RES_BLUE(pipe)         _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4151 #define PIPE_CRC_RES_RES1_I915(pipe)    _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4152 #define PIPE_CRC_RES_RES2_G4X(pipe)     _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4153
4154 /* Pipe A timing regs */
4155 #define _HTOTAL_A       0x60000
4156 #define _HBLANK_A       0x60004
4157 #define _HSYNC_A        0x60008
4158 #define _VTOTAL_A       0x6000c
4159 #define _VBLANK_A       0x60010
4160 #define _VSYNC_A        0x60014
4161 #define _PIPEASRC       0x6001c
4162 #define _BCLRPAT_A      0x60020
4163 #define _VSYNCSHIFT_A   0x60028
4164 #define _PIPE_MULT_A    0x6002c
4165
4166 /* Pipe B timing regs */
4167 #define _HTOTAL_B       0x61000
4168 #define _HBLANK_B       0x61004
4169 #define _HSYNC_B        0x61008
4170 #define _VTOTAL_B       0x6100c
4171 #define _VBLANK_B       0x61010
4172 #define _VSYNC_B        0x61014
4173 #define _PIPEBSRC       0x6101c
4174 #define _BCLRPAT_B      0x61020
4175 #define _VSYNCSHIFT_B   0x61028
4176 #define _PIPE_MULT_B    0x6102c
4177
4178 /* DSI 0 timing regs */
4179 #define _HTOTAL_DSI0            0x6b000
4180 #define _HSYNC_DSI0             0x6b008
4181 #define _VTOTAL_DSI0            0x6b00c
4182 #define _VSYNC_DSI0             0x6b014
4183 #define _VSYNCSHIFT_DSI0        0x6b028
4184
4185 /* DSI 1 timing regs */
4186 #define _HTOTAL_DSI1            0x6b800
4187 #define _HSYNC_DSI1             0x6b808
4188 #define _VTOTAL_DSI1            0x6b80c
4189 #define _VSYNC_DSI1             0x6b814
4190 #define _VSYNCSHIFT_DSI1        0x6b828
4191
4192 #define TRANSCODER_A_OFFSET 0x60000
4193 #define TRANSCODER_B_OFFSET 0x61000
4194 #define TRANSCODER_C_OFFSET 0x62000
4195 #define CHV_TRANSCODER_C_OFFSET 0x63000
4196 #define TRANSCODER_D_OFFSET 0x63000
4197 #define TRANSCODER_EDP_OFFSET 0x6f000
4198 #define TRANSCODER_DSI0_OFFSET  0x6b000
4199 #define TRANSCODER_DSI1_OFFSET  0x6b800
4200
4201 #define HTOTAL(trans)           _MMIO_TRANS2(trans, _HTOTAL_A)
4202 #define HBLANK(trans)           _MMIO_TRANS2(trans, _HBLANK_A)
4203 #define HSYNC(trans)            _MMIO_TRANS2(trans, _HSYNC_A)
4204 #define VTOTAL(trans)           _MMIO_TRANS2(trans, _VTOTAL_A)
4205 #define VBLANK(trans)           _MMIO_TRANS2(trans, _VBLANK_A)
4206 #define VSYNC(trans)            _MMIO_TRANS2(trans, _VSYNC_A)
4207 #define BCLRPAT(trans)          _MMIO_TRANS2(trans, _BCLRPAT_A)
4208 #define VSYNCSHIFT(trans)       _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4209 #define PIPESRC(trans)          _MMIO_TRANS2(trans, _PIPEASRC)
4210 #define PIPE_MULT(trans)        _MMIO_TRANS2(trans, _PIPE_MULT_A)
4211
4212 /* HSW+ eDP PSR registers */
4213 #define HSW_EDP_PSR_BASE        0x64800
4214 #define BDW_EDP_PSR_BASE        0x6f800
4215 #define EDP_PSR_CTL                             _MMIO(dev_priv->psr_mmio_base + 0)
4216 #define   EDP_PSR_ENABLE                        (1 << 31)
4217 #define   BDW_PSR_SINGLE_FRAME                  (1 << 30)
4218 #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK   (1 << 29) /* SW can't modify */
4219 #define   EDP_PSR_LINK_STANDBY                  (1 << 27)
4220 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK      (3 << 25)
4221 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES   (0 << 25)
4222 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES   (1 << 25)
4223 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES   (2 << 25)
4224 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES   (3 << 25)
4225 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT          20
4226 #define   EDP_PSR_SKIP_AUX_EXIT                 (1 << 12)
4227 #define   EDP_PSR_TP1_TP2_SEL                   (0 << 11)
4228 #define   EDP_PSR_TP1_TP3_SEL                   (1 << 11)
4229 #define   EDP_PSR_CRC_ENABLE                    (1 << 10) /* BDW+ */
4230 #define   EDP_PSR_TP2_TP3_TIME_500us            (0 << 8)
4231 #define   EDP_PSR_TP2_TP3_TIME_100us            (1 << 8)
4232 #define   EDP_PSR_TP2_TP3_TIME_2500us           (2 << 8)
4233 #define   EDP_PSR_TP2_TP3_TIME_0us              (3 << 8)
4234 #define   EDP_PSR_TP4_TIME_0US                  (3 << 6) /* ICL+ */
4235 #define   EDP_PSR_TP1_TIME_500us                (0 << 4)
4236 #define   EDP_PSR_TP1_TIME_100us                (1 << 4)
4237 #define   EDP_PSR_TP1_TIME_2500us               (2 << 4)
4238 #define   EDP_PSR_TP1_TIME_0us                  (3 << 4)
4239 #define   EDP_PSR_IDLE_FRAME_SHIFT              0
4240
4241 /* Bspec claims those aren't shifted but stay at 0x64800 */
4242 #define EDP_PSR_IMR                             _MMIO(0x64834)
4243 #define EDP_PSR_IIR                             _MMIO(0x64838)
4244 #define   EDP_PSR_ERROR(shift)                  (1 << ((shift) + 2))
4245 #define   EDP_PSR_POST_EXIT(shift)              (1 << ((shift) + 1))
4246 #define   EDP_PSR_PRE_ENTRY(shift)              (1 << (shift))
4247 #define   EDP_PSR_TRANSCODER_C_SHIFT            24
4248 #define   EDP_PSR_TRANSCODER_B_SHIFT            16
4249 #define   EDP_PSR_TRANSCODER_A_SHIFT            8
4250 #define   EDP_PSR_TRANSCODER_EDP_SHIFT          0
4251
4252 #define EDP_PSR_AUX_CTL                         _MMIO(dev_priv->psr_mmio_base + 0x10)
4253 #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK         (3 << 26)
4254 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK     (0x1f << 20)
4255 #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK    (0xf << 16)
4256 #define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT       (1 << 11)
4257 #define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK     (0x7ff)
4258
4259 #define EDP_PSR_AUX_DATA(i)                     _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
4260
4261 #define EDP_PSR_STATUS                          _MMIO(dev_priv->psr_mmio_base + 0x40)
4262 #define   EDP_PSR_STATUS_STATE_MASK             (7 << 29)
4263 #define   EDP_PSR_STATUS_STATE_SHIFT            29
4264 #define   EDP_PSR_STATUS_STATE_IDLE             (0 << 29)
4265 #define   EDP_PSR_STATUS_STATE_SRDONACK         (1 << 29)
4266 #define   EDP_PSR_STATUS_STATE_SRDENT           (2 << 29)
4267 #define   EDP_PSR_STATUS_STATE_BUFOFF           (3 << 29)
4268 #define   EDP_PSR_STATUS_STATE_BUFON            (4 << 29)
4269 #define   EDP_PSR_STATUS_STATE_AUXACK           (5 << 29)
4270 #define   EDP_PSR_STATUS_STATE_SRDOFFACK        (6 << 29)
4271 #define   EDP_PSR_STATUS_LINK_MASK              (3 << 26)
4272 #define   EDP_PSR_STATUS_LINK_FULL_OFF          (0 << 26)
4273 #define   EDP_PSR_STATUS_LINK_FULL_ON           (1 << 26)
4274 #define   EDP_PSR_STATUS_LINK_STANDBY           (2 << 26)
4275 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT  20
4276 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK   0x1f
4277 #define   EDP_PSR_STATUS_COUNT_SHIFT            16
4278 #define   EDP_PSR_STATUS_COUNT_MASK             0xf
4279 #define   EDP_PSR_STATUS_AUX_ERROR              (1 << 15)
4280 #define   EDP_PSR_STATUS_AUX_SENDING            (1 << 12)
4281 #define   EDP_PSR_STATUS_SENDING_IDLE           (1 << 9)
4282 #define   EDP_PSR_STATUS_SENDING_TP2_TP3        (1 << 8)
4283 #define   EDP_PSR_STATUS_SENDING_TP1            (1 << 4)
4284 #define   EDP_PSR_STATUS_IDLE_MASK              0xf
4285
4286 #define EDP_PSR_PERF_CNT                _MMIO(dev_priv->psr_mmio_base + 0x44)
4287 #define   EDP_PSR_PERF_CNT_MASK         0xffffff
4288
4289 #define EDP_PSR_DEBUG                           _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
4290 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1 << 28)
4291 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
4292 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
4293 #define   EDP_PSR_DEBUG_MASK_HPD               (1 << 25)
4294 #define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
4295 #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4296
4297 #define EDP_PSR2_CTL                    _MMIO(0x6f900)
4298 #define   EDP_PSR2_ENABLE               (1 << 31)
4299 #define   EDP_SU_TRACK_ENABLE           (1 << 30)
4300 #define   EDP_Y_COORDINATE_VALID        (1 << 26) /* GLK and CNL+ */
4301 #define   EDP_Y_COORDINATE_ENABLE       (1 << 25) /* GLK and CNL+ */
4302 #define   EDP_MAX_SU_DISABLE_TIME(t)    ((t) << 20)
4303 #define   EDP_MAX_SU_DISABLE_TIME_MASK  (0x1f << 20)
4304 #define   EDP_PSR2_TP2_TIME_500us       (0 << 8)
4305 #define   EDP_PSR2_TP2_TIME_100us       (1 << 8)
4306 #define   EDP_PSR2_TP2_TIME_2500us      (2 << 8)
4307 #define   EDP_PSR2_TP2_TIME_50us        (3 << 8)
4308 #define   EDP_PSR2_TP2_TIME_MASK        (3 << 8)
4309 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4310 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4311 #define   EDP_PSR2_FRAME_BEFORE_SU(a)   ((a) << 4)
4312 #define   EDP_PSR2_IDLE_FRAME_MASK      0xf
4313 #define   EDP_PSR2_IDLE_FRAME_SHIFT     0
4314
4315 #define _PSR_EVENT_TRANS_A                      0x60848
4316 #define _PSR_EVENT_TRANS_B                      0x61848
4317 #define _PSR_EVENT_TRANS_C                      0x62848
4318 #define _PSR_EVENT_TRANS_D                      0x63848
4319 #define _PSR_EVENT_TRANS_EDP                    0x6F848
4320 #define PSR_EVENT(trans)                        _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
4321 #define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE         (1 << 17)
4322 #define  PSR_EVENT_PSR2_DISABLED                (1 << 16)
4323 #define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN       (1 << 15)
4324 #define  PSR_EVENT_SU_CRC_FIFO_UNDERRUN         (1 << 14)
4325 #define  PSR_EVENT_GRAPHICS_RESET               (1 << 12)
4326 #define  PSR_EVENT_PCH_INTERRUPT                (1 << 11)
4327 #define  PSR_EVENT_MEMORY_UP                    (1 << 10)
4328 #define  PSR_EVENT_FRONT_BUFFER_MODIFY          (1 << 9)
4329 #define  PSR_EVENT_WD_TIMER_EXPIRE              (1 << 8)
4330 #define  PSR_EVENT_PIPE_REGISTERS_UPDATE        (1 << 6)
4331 #define  PSR_EVENT_REGISTER_UPDATE              (1 << 5) /* Reserved in ICL+ */
4332 #define  PSR_EVENT_HDCP_ENABLE                  (1 << 4)
4333 #define  PSR_EVENT_KVMR_SESSION_ENABLE          (1 << 3)
4334 #define  PSR_EVENT_VBI_ENABLE                   (1 << 2)
4335 #define  PSR_EVENT_LPSP_MODE_EXIT               (1 << 1)
4336 #define  PSR_EVENT_PSR_DISABLE                  (1 << 0)
4337
4338 #define EDP_PSR2_STATUS                 _MMIO(0x6f940)
4339 #define EDP_PSR2_STATUS_STATE_MASK     (0xf << 28)
4340 #define EDP_PSR2_STATUS_STATE_SHIFT    28
4341
4342 #define _PSR2_SU_STATUS_0               0x6F914
4343 #define _PSR2_SU_STATUS_1               0x6F918
4344 #define _PSR2_SU_STATUS_2               0x6F91C
4345 #define _PSR2_SU_STATUS(index)          _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
4346 #define PSR2_SU_STATUS(frame)           (_PSR2_SU_STATUS((frame) / 3))
4347 #define PSR2_SU_STATUS_SHIFT(frame)     (((frame) % 3) * 10)
4348 #define PSR2_SU_STATUS_MASK(frame)      (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4349 #define PSR2_SU_STATUS_FRAMES           8
4350
4351 /* VGA port control */
4352 #define ADPA                    _MMIO(0x61100)
4353 #define PCH_ADPA                _MMIO(0xe1100)
4354 #define VLV_ADPA                _MMIO(VLV_DISPLAY_BASE + 0x61100)
4355
4356 #define   ADPA_DAC_ENABLE       (1 << 31)
4357 #define   ADPA_DAC_DISABLE      0
4358 #define   ADPA_PIPE_SEL_SHIFT           30
4359 #define   ADPA_PIPE_SEL_MASK            (1 << 30)
4360 #define   ADPA_PIPE_SEL(pipe)           ((pipe) << 30)
4361 #define   ADPA_PIPE_SEL_SHIFT_CPT       29
4362 #define   ADPA_PIPE_SEL_MASK_CPT        (3 << 29)
4363 #define   ADPA_PIPE_SEL_CPT(pipe)       ((pipe) << 29)
4364 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
4365 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
4366 #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3 << 24)
4367 #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4368 #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2 << 24)
4369 #define   ADPA_CRT_HOTPLUG_ENABLE        (1 << 23)
4370 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
4371 #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1 << 22)
4372 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
4373 #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1 << 21)
4374 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
4375 #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1 << 20)
4376 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
4377 #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1 << 18)
4378 #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2 << 18)
4379 #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3 << 18)
4380 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
4381 #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1 << 17)
4382 #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4383 #define   ADPA_USE_VGA_HVPOLARITY (1 << 15)
4384 #define   ADPA_SETS_HVPOLARITY  0
4385 #define   ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4386 #define   ADPA_VSYNC_CNTL_ENABLE 0
4387 #define   ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4388 #define   ADPA_HSYNC_CNTL_ENABLE 0
4389 #define   ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4390 #define   ADPA_VSYNC_ACTIVE_LOW 0
4391 #define   ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4392 #define   ADPA_HSYNC_ACTIVE_LOW 0
4393 #define   ADPA_DPMS_MASK        (~(3 << 10))
4394 #define   ADPA_DPMS_ON          (0 << 10)
4395 #define   ADPA_DPMS_SUSPEND     (1 << 10)
4396 #define   ADPA_DPMS_STANDBY     (2 << 10)
4397 #define   ADPA_DPMS_OFF         (3 << 10)
4398
4399
4400 /* Hotplug control (945+ only) */
4401 #define PORT_HOTPLUG_EN         _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4402 #define   PORTB_HOTPLUG_INT_EN                  (1 << 29)
4403 #define   PORTC_HOTPLUG_INT_EN                  (1 << 28)
4404 #define   PORTD_HOTPLUG_INT_EN                  (1 << 27)
4405 #define   SDVOB_HOTPLUG_INT_EN                  (1 << 26)
4406 #define   SDVOC_HOTPLUG_INT_EN                  (1 << 25)
4407 #define   TV_HOTPLUG_INT_EN                     (1 << 18)
4408 #define   CRT_HOTPLUG_INT_EN                    (1 << 9)
4409 #define HOTPLUG_INT_EN_MASK                     (PORTB_HOTPLUG_INT_EN | \
4410                                                  PORTC_HOTPLUG_INT_EN | \
4411                                                  PORTD_HOTPLUG_INT_EN | \
4412                                                  SDVOC_HOTPLUG_INT_EN | \
4413                                                  SDVOB_HOTPLUG_INT_EN | \
4414                                                  CRT_HOTPLUG_INT_EN)
4415 #define   CRT_HOTPLUG_FORCE_DETECT              (1 << 3)
4416 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32        (0 << 8)
4417 /* must use period 64 on GM45 according to docs */
4418 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64        (1 << 8)
4419 #define CRT_HOTPLUG_DAC_ON_TIME_2M              (0 << 7)
4420 #define CRT_HOTPLUG_DAC_ON_TIME_4M              (1 << 7)
4421 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40          (0 << 5)
4422 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50          (1 << 5)
4423 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60          (2 << 5)
4424 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70          (3 << 5)
4425 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK        (3 << 5)
4426 #define CRT_HOTPLUG_DETECT_DELAY_1G             (0 << 4)
4427 #define CRT_HOTPLUG_DETECT_DELAY_2G             (1 << 4)
4428 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV        (0 << 2)
4429 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV        (1 << 2)
4430
4431 #define PORT_HOTPLUG_STAT       _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4432 /*
4433  * HDMI/DP bits are g4x+
4434  *
4435  * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4436  * Please check the detailed lore in the commit message for for experimental
4437  * evidence.
4438  */
4439 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4440 #define   PORTD_HOTPLUG_LIVE_STATUS_GM45        (1 << 29)
4441 #define   PORTC_HOTPLUG_LIVE_STATUS_GM45        (1 << 28)
4442 #define   PORTB_HOTPLUG_LIVE_STATUS_GM45        (1 << 27)
4443 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4444 #define   PORTD_HOTPLUG_LIVE_STATUS_G4X         (1 << 27)
4445 #define   PORTC_HOTPLUG_LIVE_STATUS_G4X         (1 << 28)
4446 #define   PORTB_HOTPLUG_LIVE_STATUS_G4X         (1 << 29)
4447 #define   PORTD_HOTPLUG_INT_STATUS              (3 << 21)
4448 #define   PORTD_HOTPLUG_INT_LONG_PULSE          (2 << 21)
4449 #define   PORTD_HOTPLUG_INT_SHORT_PULSE         (1 << 21)
4450 #define   PORTC_HOTPLUG_INT_STATUS              (3 << 19)
4451 #define   PORTC_HOTPLUG_INT_LONG_PULSE          (2 << 19)
4452 #define   PORTC_HOTPLUG_INT_SHORT_PULSE         (1 << 19)
4453 #define   PORTB_HOTPLUG_INT_STATUS              (3 << 17)
4454 #define   PORTB_HOTPLUG_INT_LONG_PULSE          (2 << 17)
4455 #define   PORTB_HOTPLUG_INT_SHORT_PLUSE         (1 << 17)
4456 /* CRT/TV common between gen3+ */
4457 #define   CRT_HOTPLUG_INT_STATUS                (1 << 11)
4458 #define   TV_HOTPLUG_INT_STATUS                 (1 << 10)
4459 #define   CRT_HOTPLUG_MONITOR_MASK              (3 << 8)
4460 #define   CRT_HOTPLUG_MONITOR_COLOR             (3 << 8)
4461 #define   CRT_HOTPLUG_MONITOR_MONO              (2 << 8)
4462 #define   CRT_HOTPLUG_MONITOR_NONE              (0 << 8)
4463 #define   DP_AUX_CHANNEL_D_INT_STATUS_G4X       (1 << 6)
4464 #define   DP_AUX_CHANNEL_C_INT_STATUS_G4X       (1 << 5)
4465 #define   DP_AUX_CHANNEL_B_INT_STATUS_G4X       (1 << 4)
4466 #define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X    (7 << 4)
4467
4468 /* SDVO is different across gen3/4 */
4469 #define   SDVOC_HOTPLUG_INT_STATUS_G4X          (1 << 3)
4470 #define   SDVOB_HOTPLUG_INT_STATUS_G4X          (1 << 2)
4471 /*
4472  * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4473  * since reality corrobates that they're the same as on gen3. But keep these
4474  * bits here (and the comment!) to help any other lost wanderers back onto the
4475  * right tracks.
4476  */
4477 #define   SDVOC_HOTPLUG_INT_STATUS_I965         (3 << 4)
4478 #define   SDVOB_HOTPLUG_INT_STATUS_I965         (3 << 2)
4479 #define   SDVOC_HOTPLUG_INT_STATUS_I915         (1 << 7)
4480 #define   SDVOB_HOTPLUG_INT_STATUS_I915         (1 << 6)
4481 #define   HOTPLUG_INT_STATUS_G4X                (CRT_HOTPLUG_INT_STATUS | \
4482                                                  SDVOB_HOTPLUG_INT_STATUS_G4X | \
4483                                                  SDVOC_HOTPLUG_INT_STATUS_G4X | \
4484                                                  PORTB_HOTPLUG_INT_STATUS | \
4485                                                  PORTC_HOTPLUG_INT_STATUS | \
4486                                                  PORTD_HOTPLUG_INT_STATUS)
4487
4488 #define HOTPLUG_INT_STATUS_I915                 (CRT_HOTPLUG_INT_STATUS | \
4489                                                  SDVOB_HOTPLUG_INT_STATUS_I915 | \
4490                                                  SDVOC_HOTPLUG_INT_STATUS_I915 | \
4491                                                  PORTB_HOTPLUG_INT_STATUS | \
4492                                                  PORTC_HOTPLUG_INT_STATUS | \
4493                                                  PORTD_HOTPLUG_INT_STATUS)
4494
4495 /* SDVO and HDMI port control.
4496  * The same register may be used for SDVO or HDMI */
4497 #define _GEN3_SDVOB     0x61140
4498 #define _GEN3_SDVOC     0x61160
4499 #define GEN3_SDVOB      _MMIO(_GEN3_SDVOB)
4500 #define GEN3_SDVOC      _MMIO(_GEN3_SDVOC)
4501 #define GEN4_HDMIB      GEN3_SDVOB
4502 #define GEN4_HDMIC      GEN3_SDVOC
4503 #define VLV_HDMIB       _MMIO(VLV_DISPLAY_BASE + 0x61140)
4504 #define VLV_HDMIC       _MMIO(VLV_DISPLAY_BASE + 0x61160)
4505 #define CHV_HDMID       _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4506 #define PCH_SDVOB       _MMIO(0xe1140)
4507 #define PCH_HDMIB       PCH_SDVOB
4508 #define PCH_HDMIC       _MMIO(0xe1150)
4509 #define PCH_HDMID       _MMIO(0xe1160)
4510
4511 #define PORT_DFT_I9XX                           _MMIO(0x61150)
4512 #define   DC_BALANCE_RESET                      (1 << 25)
4513 #define PORT_DFT2_G4X           _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4514 #define   DC_BALANCE_RESET_VLV                  (1 << 31)
4515 #define   PIPE_SCRAMBLE_RESET_MASK              ((1 << 14) | (0x3 << 0))
4516 #define   PIPE_C_SCRAMBLE_RESET                 (1 << 14) /* chv */
4517 #define   PIPE_B_SCRAMBLE_RESET                 (1 << 1)
4518 #define   PIPE_A_SCRAMBLE_RESET                 (1 << 0)
4519
4520 /* Gen 3 SDVO bits: */
4521 #define   SDVO_ENABLE                           (1 << 31)
4522 #define   SDVO_PIPE_SEL_SHIFT                   30
4523 #define   SDVO_PIPE_SEL_MASK                    (1 << 30)
4524 #define   SDVO_PIPE_SEL(pipe)                   ((pipe) << 30)
4525 #define   SDVO_STALL_SELECT                     (1 << 29)
4526 #define   SDVO_INTERRUPT_ENABLE                 (1 << 26)
4527 /*
4528  * 915G/GM SDVO pixel multiplier.
4529  * Programmed value is multiplier - 1, up to 5x.
4530  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4531  */
4532 #define   SDVO_PORT_MULTIPLY_MASK               (7 << 23)
4533 #define   SDVO_PORT_MULTIPLY_SHIFT              23
4534 #define   SDVO_PHASE_SELECT_MASK                (15 << 19)
4535 #define   SDVO_PHASE_SELECT_DEFAULT             (6 << 19)
4536 #define   SDVO_CLOCK_OUTPUT_INVERT              (1 << 18)
4537 #define   SDVOC_GANG_MODE                       (1 << 16) /* Port C only */
4538 #define   SDVO_BORDER_ENABLE                    (1 << 7) /* SDVO only */
4539 #define   SDVOB_PCIE_CONCURRENCY                (1 << 3) /* Port B only */
4540 #define   SDVO_DETECTED                         (1 << 2)
4541 /* Bits to be preserved when writing */
4542 #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4543                                SDVO_INTERRUPT_ENABLE)
4544 #define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4545
4546 /* Gen 4 SDVO/HDMI bits: */
4547 #define   SDVO_COLOR_FORMAT_8bpc                (0 << 26)
4548 #define   SDVO_COLOR_FORMAT_MASK                (7 << 26)
4549 #define   SDVO_ENCODING_SDVO                    (0 << 10)
4550 #define   SDVO_ENCODING_HDMI                    (2 << 10)
4551 #define   HDMI_MODE_SELECT_HDMI                 (1 << 9) /* HDMI only */
4552 #define   HDMI_MODE_SELECT_DVI                  (0 << 9) /* HDMI only */
4553 #define   HDMI_COLOR_RANGE_16_235               (1 << 8) /* HDMI only */
4554 #define   HDMI_AUDIO_ENABLE                     (1 << 6) /* HDMI only */
4555 /* VSYNC/HSYNC bits new with 965, default is to be set */
4556 #define   SDVO_VSYNC_ACTIVE_HIGH                (1 << 4)
4557 #define   SDVO_HSYNC_ACTIVE_HIGH                (1 << 3)
4558
4559 /* Gen 5 (IBX) SDVO/HDMI bits: */
4560 #define   HDMI_COLOR_FORMAT_12bpc               (3 << 26) /* HDMI only */
4561 #define   SDVOB_HOTPLUG_ENABLE                  (1 << 23) /* SDVO only */
4562
4563 /* Gen 6 (CPT) SDVO/HDMI bits: */
4564 #define   SDVO_PIPE_SEL_SHIFT_CPT               29
4565 #define   SDVO_PIPE_SEL_MASK_CPT                (3 << 29)
4566 #define   SDVO_PIPE_SEL_CPT(pipe)               ((pipe) << 29)
4567
4568 /* CHV SDVO/HDMI bits: */
4569 #define   SDVO_PIPE_SEL_SHIFT_CHV               24
4570 #define   SDVO_PIPE_SEL_MASK_CHV                (3 << 24)
4571 #define   SDVO_PIPE_SEL_CHV(pipe)               ((pipe) << 24)
4572
4573
4574 /* DVO port control */
4575 #define _DVOA                   0x61120
4576 #define DVOA                    _MMIO(_DVOA)
4577 #define _DVOB                   0x61140
4578 #define DVOB                    _MMIO(_DVOB)
4579 #define _DVOC                   0x61160
4580 #define DVOC                    _MMIO(_DVOC)
4581 #define   DVO_ENABLE                    (1 << 31)
4582 #define   DVO_PIPE_SEL_SHIFT            30
4583 #define   DVO_PIPE_SEL_MASK             (1 << 30)
4584 #define   DVO_PIPE_SEL(pipe)            ((pipe) << 30)
4585 #define   DVO_PIPE_STALL_UNUSED         (0 << 28)
4586 #define   DVO_PIPE_STALL                (1 << 28)
4587 #define   DVO_PIPE_STALL_TV             (2 << 28)
4588 #define   DVO_PIPE_STALL_MASK           (3 << 28)
4589 #define   DVO_USE_VGA_SYNC              (1 << 15)
4590 #define   DVO_DATA_ORDER_I740           (0 << 14)
4591 #define   DVO_DATA_ORDER_FP             (1 << 14)
4592 #define   DVO_VSYNC_DISABLE             (1 << 11)
4593 #define   DVO_HSYNC_DISABLE             (1 << 10)
4594 #define   DVO_VSYNC_TRISTATE            (1 << 9)
4595 #define   DVO_HSYNC_TRISTATE            (1 << 8)
4596 #define   DVO_BORDER_ENABLE             (1 << 7)
4597 #define   DVO_DATA_ORDER_GBRG           (1 << 6)
4598 #define   DVO_DATA_ORDER_RGGB           (0 << 6)
4599 #define   DVO_DATA_ORDER_GBRG_ERRATA    (0 << 6)
4600 #define   DVO_DATA_ORDER_RGGB_ERRATA    (1 << 6)
4601 #define   DVO_VSYNC_ACTIVE_HIGH         (1 << 4)
4602 #define   DVO_HSYNC_ACTIVE_HIGH         (1 << 3)
4603 #define   DVO_BLANK_ACTIVE_HIGH         (1 << 2)
4604 #define   DVO_OUTPUT_CSTATE_PIXELS      (1 << 1)        /* SDG only */
4605 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0)        /* SDG only */
4606 #define   DVO_PRESERVE_MASK             (0x7 << 24)
4607 #define DVOA_SRCDIM             _MMIO(0x61124)
4608 #define DVOB_SRCDIM             _MMIO(0x61144)
4609 #define DVOC_SRCDIM             _MMIO(0x61164)
4610 #define   DVO_SRCDIM_HORIZONTAL_SHIFT   12
4611 #define   DVO_SRCDIM_VERTICAL_SHIFT     0
4612
4613 /* LVDS port control */
4614 #define LVDS                    _MMIO(0x61180)
4615 /*
4616  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
4617  * the DPLL semantics change when the LVDS is assigned to that pipe.
4618  */
4619 #define   LVDS_PORT_EN                  (1 << 31)
4620 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
4621 #define   LVDS_PIPE_SEL_SHIFT           30
4622 #define   LVDS_PIPE_SEL_MASK            (1 << 30)
4623 #define   LVDS_PIPE_SEL(pipe)           ((pipe) << 30)
4624 #define   LVDS_PIPE_SEL_SHIFT_CPT       29
4625 #define   LVDS_PIPE_SEL_MASK_CPT        (3 << 29)
4626 #define   LVDS_PIPE_SEL_CPT(pipe)       ((pipe) << 29)
4627 /* LVDS dithering flag on 965/g4x platform */
4628 #define   LVDS_ENABLE_DITHER            (1 << 25)
4629 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4630 #define   LVDS_VSYNC_POLARITY           (1 << 21)
4631 #define   LVDS_HSYNC_POLARITY           (1 << 20)
4632
4633 /* Enable border for unscaled (or aspect-scaled) display */
4634 #define   LVDS_BORDER_ENABLE            (1 << 15)
4635 /*
4636  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4637  * pixel.
4638  */
4639 #define   LVDS_A0A2_CLKA_POWER_MASK     (3 << 8)
4640 #define   LVDS_A0A2_CLKA_POWER_DOWN     (0 << 8)
4641 #define   LVDS_A0A2_CLKA_POWER_UP       (3 << 8)
4642 /*
4643  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4644  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4645  * on.
4646  */
4647 #define   LVDS_A3_POWER_MASK            (3 << 6)
4648 #define   LVDS_A3_POWER_DOWN            (0 << 6)
4649 #define   LVDS_A3_POWER_UP              (3 << 6)
4650 /*
4651  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
4652  * is set.
4653  */
4654 #define   LVDS_CLKB_POWER_MASK          (3 << 4)
4655 #define   LVDS_CLKB_POWER_DOWN          (0 << 4)
4656 #define   LVDS_CLKB_POWER_UP            (3 << 4)
4657 /*
4658  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
4659  * setting for whether we are in dual-channel mode.  The B3 pair will
4660  * additionally only be powered up when LVDS_A3_POWER_UP is set.
4661  */
4662 #define   LVDS_B0B3_POWER_MASK          (3 << 2)
4663 #define   LVDS_B0B3_POWER_DOWN          (0 << 2)
4664 #define   LVDS_B0B3_POWER_UP            (3 << 2)
4665
4666 /* Video Data Island Packet control */
4667 #define VIDEO_DIP_DATA          _MMIO(0x61178)
4668 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4669  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4670  * of the infoframe structure specified by CEA-861. */
4671 #define   VIDEO_DIP_DATA_SIZE   32
4672 #define   VIDEO_DIP_VSC_DATA_SIZE       36
4673 #define   VIDEO_DIP_PPS_DATA_SIZE       132
4674 #define VIDEO_DIP_CTL           _MMIO(0x61170)
4675 /* Pre HSW: */
4676 #define   VIDEO_DIP_ENABLE              (1 << 31)
4677 #define   VIDEO_DIP_PORT(port)          ((port) << 29)
4678 #define   VIDEO_DIP_PORT_MASK           (3 << 29)
4679 #define   VIDEO_DIP_ENABLE_GCP          (1 << 25) /* ilk+ */
4680 #define   VIDEO_DIP_ENABLE_AVI          (1 << 21)
4681 #define   VIDEO_DIP_ENABLE_VENDOR       (2 << 21)
4682 #define   VIDEO_DIP_ENABLE_GAMUT        (4 << 21) /* ilk+ */
4683 #define   VIDEO_DIP_ENABLE_SPD          (8 << 21)
4684 #define   VIDEO_DIP_SELECT_AVI          (0 << 19)
4685 #define   VIDEO_DIP_SELECT_VENDOR       (1 << 19)
4686 #define   VIDEO_DIP_SELECT_GAMUT        (2 << 19)
4687 #define   VIDEO_DIP_SELECT_SPD          (3 << 19)
4688 #define   VIDEO_DIP_SELECT_MASK         (3 << 19)
4689 #define   VIDEO_DIP_FREQ_ONCE           (0 << 16)
4690 #define   VIDEO_DIP_FREQ_VSYNC          (1 << 16)
4691 #define   VIDEO_DIP_FREQ_2VSYNC         (2 << 16)
4692 #define   VIDEO_DIP_FREQ_MASK           (3 << 16)
4693 /* HSW and later: */
4694 #define   VIDEO_DIP_ENABLE_DRM_GLK      (1 << 28)
4695 #define   PSR_VSC_BIT_7_SET             (1 << 27)
4696 #define   VSC_SELECT_MASK               (0x3 << 25)
4697 #define   VSC_SELECT_SHIFT              25
4698 #define   VSC_DIP_HW_HEA_DATA           (0 << 25)
4699 #define   VSC_DIP_HW_HEA_SW_DATA        (1 << 25)
4700 #define   VSC_DIP_HW_DATA_SW_HEA        (2 << 25)
4701 #define   VSC_DIP_SW_HEA_DATA           (3 << 25)
4702 #define   VDIP_ENABLE_PPS               (1 << 24)
4703 #define   VIDEO_DIP_ENABLE_VSC_HSW      (1 << 20)
4704 #define   VIDEO_DIP_ENABLE_GCP_HSW      (1 << 16)
4705 #define   VIDEO_DIP_ENABLE_AVI_HSW      (1 << 12)
4706 #define   VIDEO_DIP_ENABLE_VS_HSW       (1 << 8)
4707 #define   VIDEO_DIP_ENABLE_GMP_HSW      (1 << 4)
4708 #define   VIDEO_DIP_ENABLE_SPD_HSW      (1 << 0)
4709
4710 /* Panel power sequencing */
4711 #define PPS_BASE                        0x61200
4712 #define VLV_PPS_BASE                    (VLV_DISPLAY_BASE + PPS_BASE)
4713 #define PCH_PPS_BASE                    0xC7200
4714
4715 #define _MMIO_PPS(pps_idx, reg)         _MMIO(dev_priv->pps_mmio_base - \
4716                                               PPS_BASE + (reg) +        \
4717                                               (pps_idx) * 0x100)
4718
4719 #define _PP_STATUS                      0x61200
4720 #define PP_STATUS(pps_idx)              _MMIO_PPS(pps_idx, _PP_STATUS)
4721 #define   PP_ON                         REG_BIT(31)
4722
4723 #define _PP_CONTROL_1                   0xc7204
4724 #define _PP_CONTROL_2                   0xc7304
4725 #define ICP_PP_CONTROL(x)               _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
4726                                               _PP_CONTROL_2)
4727 #define  POWER_CYCLE_DELAY_MASK         REG_GENMASK(8, 4)
4728 #define  VDD_OVERRIDE_FORCE             REG_BIT(3)
4729 #define  BACKLIGHT_ENABLE               REG_BIT(2)
4730 #define  PWR_DOWN_ON_RESET              REG_BIT(1)
4731 #define  PWR_STATE_TARGET               REG_BIT(0)
4732 /*
4733  * Indicates that all dependencies of the panel are on:
4734  *
4735  * - PLL enabled
4736  * - pipe enabled
4737  * - LVDS/DVOB/DVOC on
4738  */
4739 #define   PP_READY                      REG_BIT(30)
4740 #define   PP_SEQUENCE_MASK              REG_GENMASK(29, 28)
4741 #define   PP_SEQUENCE_NONE              REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
4742 #define   PP_SEQUENCE_POWER_UP          REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
4743 #define   PP_SEQUENCE_POWER_DOWN        REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
4744 #define   PP_CYCLE_DELAY_ACTIVE         REG_BIT(27)
4745 #define   PP_SEQUENCE_STATE_MASK        REG_GENMASK(3, 0)
4746 #define   PP_SEQUENCE_STATE_OFF_IDLE    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
4747 #define   PP_SEQUENCE_STATE_OFF_S0_1    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
4748 #define   PP_SEQUENCE_STATE_OFF_S0_2    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
4749 #define   PP_SEQUENCE_STATE_OFF_S0_3    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
4750 #define   PP_SEQUENCE_STATE_ON_IDLE     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
4751 #define   PP_SEQUENCE_STATE_ON_S1_1     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
4752 #define   PP_SEQUENCE_STATE_ON_S1_2     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
4753 #define   PP_SEQUENCE_STATE_ON_S1_3     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
4754 #define   PP_SEQUENCE_STATE_RESET       REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
4755
4756 #define _PP_CONTROL                     0x61204
4757 #define PP_CONTROL(pps_idx)             _MMIO_PPS(pps_idx, _PP_CONTROL)
4758 #define  PANEL_UNLOCK_MASK              REG_GENMASK(31, 16)
4759 #define  PANEL_UNLOCK_REGS              REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
4760 #define  BXT_POWER_CYCLE_DELAY_MASK     REG_GENMASK(8, 4)
4761 #define  EDP_FORCE_VDD                  REG_BIT(3)
4762 #define  EDP_BLC_ENABLE                 REG_BIT(2)
4763 #define  PANEL_POWER_RESET              REG_BIT(1)
4764 #define  PANEL_POWER_ON                 REG_BIT(0)
4765
4766 #define _PP_ON_DELAYS                   0x61208
4767 #define PP_ON_DELAYS(pps_idx)           _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4768 #define  PANEL_PORT_SELECT_MASK         REG_GENMASK(31, 30)
4769 #define  PANEL_PORT_SELECT_LVDS         REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
4770 #define  PANEL_PORT_SELECT_DPA          REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
4771 #define  PANEL_PORT_SELECT_DPC          REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
4772 #define  PANEL_PORT_SELECT_DPD          REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
4773 #define  PANEL_PORT_SELECT_VLV(port)    REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
4774 #define  PANEL_POWER_UP_DELAY_MASK      REG_GENMASK(28, 16)
4775 #define  PANEL_LIGHT_ON_DELAY_MASK      REG_GENMASK(12, 0)
4776
4777 #define _PP_OFF_DELAYS                  0x6120C
4778 #define PP_OFF_DELAYS(pps_idx)          _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4779 #define  PANEL_POWER_DOWN_DELAY_MASK    REG_GENMASK(28, 16)
4780 #define  PANEL_LIGHT_OFF_DELAY_MASK     REG_GENMASK(12, 0)
4781
4782 #define _PP_DIVISOR                     0x61210
4783 #define PP_DIVISOR(pps_idx)             _MMIO_PPS(pps_idx, _PP_DIVISOR)
4784 #define  PP_REFERENCE_DIVIDER_MASK      REG_GENMASK(31, 8)
4785 #define  PANEL_POWER_CYCLE_DELAY_MASK   REG_GENMASK(4, 0)
4786
4787 /* Panel fitting */
4788 #define PFIT_CONTROL    _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
4789 #define   PFIT_ENABLE           (1 << 31)
4790 #define   PFIT_PIPE_MASK        (3 << 29)
4791 #define   PFIT_PIPE_SHIFT       29
4792 #define   VERT_INTERP_DISABLE   (0 << 10)
4793 #define   VERT_INTERP_BILINEAR  (1 << 10)
4794 #define   VERT_INTERP_MASK      (3 << 10)
4795 #define   VERT_AUTO_SCALE       (1 << 9)
4796 #define   HORIZ_INTERP_DISABLE  (0 << 6)
4797 #define   HORIZ_INTERP_BILINEAR (1 << 6)
4798 #define   HORIZ_INTERP_MASK     (3 << 6)
4799 #define   HORIZ_AUTO_SCALE      (1 << 5)
4800 #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
4801 #define   PFIT_FILTER_FUZZY     (0 << 24)
4802 #define   PFIT_SCALING_AUTO     (0 << 26)
4803 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
4804 #define   PFIT_SCALING_PILLAR   (2 << 26)
4805 #define   PFIT_SCALING_LETTER   (3 << 26)
4806 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
4807 /* Pre-965 */
4808 #define         PFIT_VERT_SCALE_SHIFT           20
4809 #define         PFIT_VERT_SCALE_MASK            0xfff00000
4810 #define         PFIT_HORIZ_SCALE_SHIFT          4
4811 #define         PFIT_HORIZ_SCALE_MASK           0x0000fff0
4812 /* 965+ */
4813 #define         PFIT_VERT_SCALE_SHIFT_965       16
4814 #define         PFIT_VERT_SCALE_MASK_965        0x1fff0000
4815 #define         PFIT_HORIZ_SCALE_SHIFT_965      0
4816 #define         PFIT_HORIZ_SCALE_MASK_965       0x00001fff
4817
4818 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
4819
4820 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
4821 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
4822 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4823                                          _VLV_BLC_PWM_CTL2_B)
4824
4825 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4826 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
4827 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4828                                         _VLV_BLC_PWM_CTL_B)
4829
4830 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4831 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
4832 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4833                                          _VLV_BLC_HIST_CTL_B)
4834
4835 /* Backlight control */
4836 #define BLC_PWM_CTL2    _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
4837 #define   BLM_PWM_ENABLE                (1 << 31)
4838 #define   BLM_COMBINATION_MODE          (1 << 30) /* gen4 only */
4839 #define   BLM_PIPE_SELECT               (1 << 29)
4840 #define   BLM_PIPE_SELECT_IVB           (3 << 29)
4841 #define   BLM_PIPE_A                    (0 << 29)
4842 #define   BLM_PIPE_B                    (1 << 29)
4843 #define   BLM_PIPE_C                    (2 << 29) /* ivb + */
4844 #define   BLM_TRANSCODER_A              BLM_PIPE_A /* hsw */
4845 #define   BLM_TRANSCODER_B              BLM_PIPE_B
4846 #define   BLM_TRANSCODER_C              BLM_PIPE_C
4847 #define   BLM_TRANSCODER_EDP            (3 << 29)
4848 #define   BLM_PIPE(pipe)                ((pipe) << 29)
4849 #define   BLM_POLARITY_I965             (1 << 28) /* gen4 only */
4850 #define   BLM_PHASE_IN_INTERUPT_STATUS  (1 << 26)
4851 #define   BLM_PHASE_IN_ENABLE           (1 << 25)
4852 #define   BLM_PHASE_IN_INTERUPT_ENABL   (1 << 24)
4853 #define   BLM_PHASE_IN_TIME_BASE_SHIFT  (16)
4854 #define   BLM_PHASE_IN_TIME_BASE_MASK   (0xff << 16)
4855 #define   BLM_PHASE_IN_COUNT_SHIFT      (8)
4856 #define   BLM_PHASE_IN_COUNT_MASK       (0xff << 8)
4857 #define   BLM_PHASE_IN_INCR_SHIFT       (0)
4858 #define   BLM_PHASE_IN_INCR_MASK        (0xff << 0)
4859 #define BLC_PWM_CTL     _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4860 /*
4861  * This is the most significant 15 bits of the number of backlight cycles in a
4862  * complete cycle of the modulated backlight control.
4863  *
4864  * The actual value is this field multiplied by two.
4865  */
4866 #define   BACKLIGHT_MODULATION_FREQ_SHIFT       (17)
4867 #define   BACKLIGHT_MODULATION_FREQ_MASK        (0x7fff << 17)
4868 #define   BLM_LEGACY_MODE                       (1 << 16) /* gen2 only */
4869 /*
4870  * This is the number of cycles out of the backlight modulation cycle for which
4871  * the backlight is on.
4872  *
4873  * This field must be no greater than the number of cycles in the complete
4874  * backlight modulation cycle.
4875  */
4876 #define   BACKLIGHT_DUTY_CYCLE_SHIFT            (0)
4877 #define   BACKLIGHT_DUTY_CYCLE_MASK             (0xffff)
4878 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV         (0xfffe)
4879 #define   BLM_POLARITY_PNV                      (1 << 0) /* pnv only */
4880
4881 #define BLC_HIST_CTL    _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4882 #define  BLM_HISTOGRAM_ENABLE                   (1 << 31)
4883
4884 /* New registers for PCH-split platforms. Safe where new bits show up, the
4885  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
4886 #define BLC_PWM_CPU_CTL2        _MMIO(0x48250)
4887 #define BLC_PWM_CPU_CTL         _MMIO(0x48254)
4888
4889 #define HSW_BLC_PWM2_CTL        _MMIO(0x48350)
4890
4891 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
4892  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
4893 #define BLC_PWM_PCH_CTL1        _MMIO(0xc8250)
4894 #define   BLM_PCH_PWM_ENABLE                    (1 << 31)
4895 #define   BLM_PCH_OVERRIDE_ENABLE               (1 << 30)
4896 #define   BLM_PCH_POLARITY                      (1 << 29)
4897 #define BLC_PWM_PCH_CTL2        _MMIO(0xc8254)
4898
4899 #define UTIL_PIN_CTL            _MMIO(0x48400)
4900 #define   UTIL_PIN_ENABLE       (1 << 31)
4901
4902 #define   UTIL_PIN_PIPE(x)     ((x) << 29)
4903 #define   UTIL_PIN_PIPE_MASK   (3 << 29)
4904 #define   UTIL_PIN_MODE_PWM    (1 << 24)
4905 #define   UTIL_PIN_MODE_MASK   (0xf << 24)
4906 #define   UTIL_PIN_POLARITY    (1 << 22)
4907
4908 /* BXT backlight register definition. */
4909 #define _BXT_BLC_PWM_CTL1                       0xC8250
4910 #define   BXT_BLC_PWM_ENABLE                    (1 << 31)
4911 #define   BXT_BLC_PWM_POLARITY                  (1 << 29)
4912 #define _BXT_BLC_PWM_FREQ1                      0xC8254
4913 #define _BXT_BLC_PWM_DUTY1                      0xC8258
4914
4915 #define _BXT_BLC_PWM_CTL2                       0xC8350
4916 #define _BXT_BLC_PWM_FREQ2                      0xC8354
4917 #define _BXT_BLC_PWM_DUTY2                      0xC8358
4918
4919 #define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,           \
4920                                         _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
4921 #define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
4922                                         _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
4923 #define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
4924                                         _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
4925
4926 #define PCH_GTC_CTL             _MMIO(0xe7000)
4927 #define   PCH_GTC_ENABLE        (1 << 31)
4928
4929 /* TV port control */
4930 #define TV_CTL                  _MMIO(0x68000)
4931 /* Enables the TV encoder */
4932 # define TV_ENC_ENABLE                  (1 << 31)
4933 /* Sources the TV encoder input from pipe B instead of A. */
4934 # define TV_ENC_PIPE_SEL_SHIFT          30
4935 # define TV_ENC_PIPE_SEL_MASK           (1 << 30)
4936 # define TV_ENC_PIPE_SEL(pipe)          ((pipe) << 30)
4937 /* Outputs composite video (DAC A only) */
4938 # define TV_ENC_OUTPUT_COMPOSITE        (0 << 28)
4939 /* Outputs SVideo video (DAC B/C) */
4940 # define TV_ENC_OUTPUT_SVIDEO           (1 << 28)
4941 /* Outputs Component video (DAC A/B/C) */
4942 # define TV_ENC_OUTPUT_COMPONENT        (2 << 28)
4943 /* Outputs Composite and SVideo (DAC A/B/C) */
4944 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
4945 # define TV_TRILEVEL_SYNC               (1 << 21)
4946 /* Enables slow sync generation (945GM only) */
4947 # define TV_SLOW_SYNC                   (1 << 20)
4948 /* Selects 4x oversampling for 480i and 576p */
4949 # define TV_OVERSAMPLE_4X               (0 << 18)
4950 /* Selects 2x oversampling for 720p and 1080i */
4951 # define TV_OVERSAMPLE_2X               (1 << 18)
4952 /* Selects no oversampling for 1080p */
4953 # define TV_OVERSAMPLE_NONE             (2 << 18)
4954 /* Selects 8x oversampling */
4955 # define TV_OVERSAMPLE_8X               (3 << 18)
4956 # define TV_OVERSAMPLE_MASK             (3 << 18)
4957 /* Selects progressive mode rather than interlaced */
4958 # define TV_PROGRESSIVE                 (1 << 17)
4959 /* Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
4960 # define TV_PAL_BURST                   (1 << 16)
4961 /* Field for setting delay of Y compared to C */
4962 # define TV_YC_SKEW_MASK                (7 << 12)
4963 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
4964 # define TV_ENC_SDP_FIX                 (1 << 11)
4965 /*
4966  * Enables a fix for the 915GM only.
4967  *
4968  * Not sure what it does.
4969  */
4970 # define TV_ENC_C0_FIX                  (1 << 10)
4971 /* Bits that must be preserved by software */
4972 # define TV_CTL_SAVE                    ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
4973 # define TV_FUSE_STATE_MASK             (3 << 4)
4974 /* Read-only state that reports all features enabled */
4975 # define TV_FUSE_STATE_ENABLED          (0 << 4)
4976 /* Read-only state that reports that Macrovision is disabled in hardware*/
4977 # define TV_FUSE_STATE_NO_MACROVISION   (1 << 4)
4978 /* Read-only state that reports that TV-out is disabled in hardware. */
4979 # define TV_FUSE_STATE_DISABLED         (2 << 4)
4980 /* Normal operation */
4981 # define TV_TEST_MODE_NORMAL            (0 << 0)
4982 /* Encoder test pattern 1 - combo pattern */
4983 # define TV_TEST_MODE_PATTERN_1         (1 << 0)
4984 /* Encoder test pattern 2 - full screen vertical 75% color bars */
4985 # define TV_TEST_MODE_PATTERN_2         (2 << 0)
4986 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
4987 # define TV_TEST_MODE_PATTERN_3         (3 << 0)
4988 /* Encoder test pattern 4 - random noise */
4989 # define TV_TEST_MODE_PATTERN_4         (4 << 0)
4990 /* Encoder test pattern 5 - linear color ramps */
4991 # define TV_TEST_MODE_PATTERN_5         (5 << 0)
4992 /*
4993  * This test mode forces the DACs to 50% of full output.
4994  *
4995  * This is used for load detection in combination with TVDAC_SENSE_MASK
4996  */
4997 # define TV_TEST_MODE_MONITOR_DETECT    (7 << 0)
4998 # define TV_TEST_MODE_MASK              (7 << 0)
4999
5000 #define TV_DAC                  _MMIO(0x68004)
5001 # define TV_DAC_SAVE            0x00ffff00
5002 /*
5003  * Reports that DAC state change logic has reported change (RO).
5004  *
5005  * This gets cleared when TV_DAC_STATE_EN is cleared
5006 */
5007 # define TVDAC_STATE_CHG                (1 << 31)
5008 # define TVDAC_SENSE_MASK               (7 << 28)
5009 /* Reports that DAC A voltage is above the detect threshold */
5010 # define TVDAC_A_SENSE                  (1 << 30)
5011 /* Reports that DAC B voltage is above the detect threshold */
5012 # define TVDAC_B_SENSE                  (1 << 29)
5013 /* Reports that DAC C voltage is above the detect threshold */
5014 # define TVDAC_C_SENSE                  (1 << 28)
5015 /*
5016  * Enables DAC state detection logic, for load-based TV detection.
5017  *
5018  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
5019  * to off, for load detection to work.
5020  */
5021 # define TVDAC_STATE_CHG_EN             (1 << 27)
5022 /* Sets the DAC A sense value to high */
5023 # define TVDAC_A_SENSE_CTL              (1 << 26)
5024 /* Sets the DAC B sense value to high */
5025 # define TVDAC_B_SENSE_CTL              (1 << 25)
5026 /* Sets the DAC C sense value to high */
5027 # define TVDAC_C_SENSE_CTL              (1 << 24)
5028 /* Overrides the ENC_ENABLE and DAC voltage levels */
5029 # define DAC_CTL_OVERRIDE               (1 << 7)
5030 /* Sets the slew rate.  Must be preserved in software */
5031 # define ENC_TVDAC_SLEW_FAST            (1 << 6)
5032 # define DAC_A_1_3_V                    (0 << 4)
5033 # define DAC_A_1_1_V                    (1 << 4)
5034 # define DAC_A_0_7_V                    (2 << 4)
5035 # define DAC_A_MASK                     (3 << 4)
5036 # define DAC_B_1_3_V                    (0 << 2)
5037 # define DAC_B_1_1_V                    (1 << 2)
5038 # define DAC_B_0_7_V                    (2 << 2)
5039 # define DAC_B_MASK                     (3 << 2)
5040 # define DAC_C_1_3_V                    (0 << 0)
5041 # define DAC_C_1_1_V                    (1 << 0)
5042 # define DAC_C_0_7_V                    (2 << 0)
5043 # define DAC_C_MASK                     (3 << 0)
5044
5045 /*
5046  * CSC coefficients are stored in a floating point format with 9 bits of
5047  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
5048  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5049  * -1 (0x3) being the only legal negative value.
5050  */
5051 #define TV_CSC_Y                _MMIO(0x68010)
5052 # define TV_RY_MASK                     0x07ff0000
5053 # define TV_RY_SHIFT                    16
5054 # define TV_GY_MASK                     0x00000fff
5055 # define TV_GY_SHIFT                    0
5056
5057 #define TV_CSC_Y2               _MMIO(0x68014)
5058 # define TV_BY_MASK                     0x07ff0000
5059 # define TV_BY_SHIFT                    16
5060 /*
5061  * Y attenuation for component video.
5062  *
5063  * Stored in 1.9 fixed point.
5064  */
5065 # define TV_AY_MASK                     0x000003ff
5066 # define TV_AY_SHIFT                    0
5067
5068 #define TV_CSC_U                _MMIO(0x68018)
5069 # define TV_RU_MASK                     0x07ff0000
5070 # define TV_RU_SHIFT                    16
5071 # define TV_GU_MASK                     0x000007ff
5072 # define TV_GU_SHIFT                    0
5073
5074 #define TV_CSC_U2               _MMIO(0x6801c)
5075 # define TV_BU_MASK                     0x07ff0000
5076 # define TV_BU_SHIFT                    16
5077 /*
5078  * U attenuation for component video.
5079  *
5080  * Stored in 1.9 fixed point.
5081  */
5082 # define TV_AU_MASK                     0x000003ff
5083 # define TV_AU_SHIFT                    0
5084
5085 #define TV_CSC_V                _MMIO(0x68020)
5086 # define TV_RV_MASK                     0x0fff0000
5087 # define TV_RV_SHIFT                    16
5088 # define TV_GV_MASK                     0x000007ff
5089 # define TV_GV_SHIFT                    0
5090
5091 #define TV_CSC_V2               _MMIO(0x68024)
5092 # define TV_BV_MASK                     0x07ff0000
5093 # define TV_BV_SHIFT                    16
5094 /*
5095  * V attenuation for component video.
5096  *
5097  * Stored in 1.9 fixed point.
5098  */
5099 # define TV_AV_MASK                     0x000007ff
5100 # define TV_AV_SHIFT                    0
5101
5102 #define TV_CLR_KNOBS            _MMIO(0x68028)
5103 /* 2s-complement brightness adjustment */
5104 # define TV_BRIGHTNESS_MASK             0xff000000
5105 # define TV_BRIGHTNESS_SHIFT            24
5106 /* Contrast adjustment, as a 2.6 unsigned floating point number */
5107 # define TV_CONTRAST_MASK               0x00ff0000
5108 # define TV_CONTRAST_SHIFT              16
5109 /* Saturation adjustment, as a 2.6 unsigned floating point number */
5110 # define TV_SATURATION_MASK             0x0000ff00
5111 # define TV_SATURATION_SHIFT            8
5112 /* Hue adjustment, as an integer phase angle in degrees */
5113 # define TV_HUE_MASK                    0x000000ff
5114 # define TV_HUE_SHIFT                   0
5115
5116 #define TV_CLR_LEVEL            _MMIO(0x6802c)
5117 /* Controls the DAC level for black */
5118 # define TV_BLACK_LEVEL_MASK            0x01ff0000
5119 # define TV_BLACK_LEVEL_SHIFT           16
5120 /* Controls the DAC level for blanking */
5121 # define TV_BLANK_LEVEL_MASK            0x000001ff
5122 # define TV_BLANK_LEVEL_SHIFT           0
5123
5124 #define TV_H_CTL_1              _MMIO(0x68030)
5125 /* Number of pixels in the hsync. */
5126 # define TV_HSYNC_END_MASK              0x1fff0000
5127 # define TV_HSYNC_END_SHIFT             16
5128 /* Total number of pixels minus one in the line (display and blanking). */
5129 # define TV_HTOTAL_MASK                 0x00001fff
5130 # define TV_HTOTAL_SHIFT                0
5131
5132 #define TV_H_CTL_2              _MMIO(0x68034)
5133 /* Enables the colorburst (needed for non-component color) */
5134 # define TV_BURST_ENA                   (1 << 31)
5135 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
5136 # define TV_HBURST_START_SHIFT          16
5137 # define TV_HBURST_START_MASK           0x1fff0000
5138 /* Length of the colorburst */
5139 # define TV_HBURST_LEN_SHIFT            0
5140 # define TV_HBURST_LEN_MASK             0x0001fff
5141
5142 #define TV_H_CTL_3              _MMIO(0x68038)
5143 /* End of hblank, measured in pixels minus one from start of hsync */
5144 # define TV_HBLANK_END_SHIFT            16
5145 # define TV_HBLANK_END_MASK             0x1fff0000
5146 /* Start of hblank, measured in pixels minus one from start of hsync */
5147 # define TV_HBLANK_START_SHIFT          0
5148 # define TV_HBLANK_START_MASK           0x0001fff
5149
5150 #define TV_V_CTL_1              _MMIO(0x6803c)
5151 /* XXX */
5152 # define TV_NBR_END_SHIFT               16
5153 # define TV_NBR_END_MASK                0x07ff0000
5154 /* XXX */
5155 # define TV_VI_END_F1_SHIFT             8
5156 # define TV_VI_END_F1_MASK              0x00003f00
5157 /* XXX */
5158 # define TV_VI_END_F2_SHIFT             0
5159 # define TV_VI_END_F2_MASK              0x0000003f
5160
5161 #define TV_V_CTL_2              _MMIO(0x68040)
5162 /* Length of vsync, in half lines */
5163 # define TV_VSYNC_LEN_MASK              0x07ff0000
5164 # define TV_VSYNC_LEN_SHIFT             16
5165 /* Offset of the start of vsync in field 1, measured in one less than the
5166  * number of half lines.
5167  */
5168 # define TV_VSYNC_START_F1_MASK         0x00007f00
5169 # define TV_VSYNC_START_F1_SHIFT        8
5170 /*
5171  * Offset of the start of vsync in field 2, measured in one less than the
5172  * number of half lines.
5173  */
5174 # define TV_VSYNC_START_F2_MASK         0x0000007f
5175 # define TV_VSYNC_START_F2_SHIFT        0
5176
5177 #define TV_V_CTL_3              _MMIO(0x68044)
5178 /* Enables generation of the equalization signal */
5179 # define TV_EQUAL_ENA                   (1 << 31)
5180 /* Length of vsync, in half lines */
5181 # define TV_VEQ_LEN_MASK                0x007f0000
5182 # define TV_VEQ_LEN_SHIFT               16
5183 /* Offset of the start of equalization in field 1, measured in one less than
5184  * the number of half lines.
5185  */
5186 # define TV_VEQ_START_F1_MASK           0x0007f00
5187 # define TV_VEQ_START_F1_SHIFT          8
5188 /*
5189  * Offset of the start of equalization in field 2, measured in one less than
5190  * the number of half lines.
5191  */
5192 # define TV_VEQ_START_F2_MASK           0x000007f
5193 # define TV_VEQ_START_F2_SHIFT          0
5194
5195 #define TV_V_CTL_4              _MMIO(0x68048)
5196 /*
5197  * Offset to start of vertical colorburst, measured in one less than the
5198  * number of lines from vertical start.
5199  */
5200 # define TV_VBURST_START_F1_MASK        0x003f0000
5201 # define TV_VBURST_START_F1_SHIFT       16
5202 /*
5203  * Offset to the end of vertical colorburst, measured in one less than the
5204  * number of lines from the start of NBR.
5205  */
5206 # define TV_VBURST_END_F1_MASK          0x000000ff
5207 # define TV_VBURST_END_F1_SHIFT         0
5208
5209 #define TV_V_CTL_5              _MMIO(0x6804c)
5210 /*
5211  * Offset to start of vertical colorburst, measured in one less than the
5212  * number of lines from vertical start.
5213  */
5214 # define TV_VBURST_START_F2_MASK        0x003f0000
5215 # define TV_VBURST_START_F2_SHIFT       16
5216 /*
5217  * Offset to the end of vertical colorburst, measured in one less than the
5218  * number of lines from the start of NBR.
5219  */
5220 # define TV_VBURST_END_F2_MASK          0x000000ff
5221 # define TV_VBURST_END_F2_SHIFT         0
5222
5223 #define TV_V_CTL_6              _MMIO(0x68050)
5224 /*
5225  * Offset to start of vertical colorburst, measured in one less than the
5226  * number of lines from vertical start.
5227  */
5228 # define TV_VBURST_START_F3_MASK        0x003f0000
5229 # define TV_VBURST_START_F3_SHIFT       16
5230 /*
5231  * Offset to the end of vertical colorburst, measured in one less than the
5232  * number of lines from the start of NBR.
5233  */
5234 # define TV_VBURST_END_F3_MASK          0x000000ff
5235 # define TV_VBURST_END_F3_SHIFT         0
5236
5237 #define TV_V_CTL_7              _MMIO(0x68054)
5238 /*
5239  * Offset to start of vertical colorburst, measured in one less than the
5240  * number of lines from vertical start.
5241  */
5242 # define TV_VBURST_START_F4_MASK        0x003f0000
5243 # define TV_VBURST_START_F4_SHIFT       16
5244 /*
5245  * Offset to the end of vertical colorburst, measured in one less than the
5246  * number of lines from the start of NBR.
5247  */
5248 # define TV_VBURST_END_F4_MASK          0x000000ff
5249 # define TV_VBURST_END_F4_SHIFT         0
5250
5251 #define TV_SC_CTL_1             _MMIO(0x68060)
5252 /* Turns on the first subcarrier phase generation DDA */
5253 # define TV_SC_DDA1_EN                  (1 << 31)
5254 /* Turns on the first subcarrier phase generation DDA */
5255 # define TV_SC_DDA2_EN                  (1 << 30)
5256 /* Turns on the first subcarrier phase generation DDA */
5257 # define TV_SC_DDA3_EN                  (1 << 29)
5258 /* Sets the subcarrier DDA to reset frequency every other field */
5259 # define TV_SC_RESET_EVERY_2            (0 << 24)
5260 /* Sets the subcarrier DDA to reset frequency every fourth field */
5261 # define TV_SC_RESET_EVERY_4            (1 << 24)
5262 /* Sets the subcarrier DDA to reset frequency every eighth field */
5263 # define TV_SC_RESET_EVERY_8            (2 << 24)
5264 /* Sets the subcarrier DDA to never reset the frequency */
5265 # define TV_SC_RESET_NEVER              (3 << 24)
5266 /* Sets the peak amplitude of the colorburst.*/
5267 # define TV_BURST_LEVEL_MASK            0x00ff0000
5268 # define TV_BURST_LEVEL_SHIFT           16
5269 /* Sets the increment of the first subcarrier phase generation DDA */
5270 # define TV_SCDDA1_INC_MASK             0x00000fff
5271 # define TV_SCDDA1_INC_SHIFT            0
5272
5273 #define TV_SC_CTL_2             _MMIO(0x68064)
5274 /* Sets the rollover for the second subcarrier phase generation DDA */
5275 # define TV_SCDDA2_SIZE_MASK            0x7fff0000
5276 # define TV_SCDDA2_SIZE_SHIFT           16
5277 /* Sets the increent of the second subcarrier phase generation DDA */
5278 # define TV_SCDDA2_INC_MASK             0x00007fff
5279 # define TV_SCDDA2_INC_SHIFT            0
5280
5281 #define TV_SC_CTL_3             _MMIO(0x68068)
5282 /* Sets the rollover for the third subcarrier phase generation DDA */
5283 # define TV_SCDDA3_SIZE_MASK            0x7fff0000
5284 # define TV_SCDDA3_SIZE_SHIFT           16
5285 /* Sets the increent of the third subcarrier phase generation DDA */
5286 # define TV_SCDDA3_INC_MASK             0x00007fff
5287 # define TV_SCDDA3_INC_SHIFT            0
5288
5289 #define TV_WIN_POS              _MMIO(0x68070)
5290 /* X coordinate of the display from the start of horizontal active */
5291 # define TV_XPOS_MASK                   0x1fff0000
5292 # define TV_XPOS_SHIFT                  16
5293 /* Y coordinate of the display from the start of vertical active (NBR) */
5294 # define TV_YPOS_MASK                   0x00000fff
5295 # define TV_YPOS_SHIFT                  0
5296
5297 #define TV_WIN_SIZE             _MMIO(0x68074)
5298 /* Horizontal size of the display window, measured in pixels*/
5299 # define TV_XSIZE_MASK                  0x1fff0000
5300 # define TV_XSIZE_SHIFT                 16
5301 /*
5302  * Vertical size of the display window, measured in pixels.
5303  *
5304  * Must be even for interlaced modes.
5305  */
5306 # define TV_YSIZE_MASK                  0x00000fff
5307 # define TV_YSIZE_SHIFT                 0
5308
5309 #define TV_FILTER_CTL_1         _MMIO(0x68080)
5310 /*
5311  * Enables automatic scaling calculation.
5312  *
5313  * If set, the rest of the registers are ignored, and the calculated values can
5314  * be read back from the register.
5315  */
5316 # define TV_AUTO_SCALE                  (1 << 31)
5317 /*
5318  * Disables the vertical filter.
5319  *
5320  * This is required on modes more than 1024 pixels wide */
5321 # define TV_V_FILTER_BYPASS             (1 << 29)
5322 /* Enables adaptive vertical filtering */
5323 # define TV_VADAPT                      (1 << 28)
5324 # define TV_VADAPT_MODE_MASK            (3 << 26)
5325 /* Selects the least adaptive vertical filtering mode */
5326 # define TV_VADAPT_MODE_LEAST           (0 << 26)
5327 /* Selects the moderately adaptive vertical filtering mode */
5328 # define TV_VADAPT_MODE_MODERATE        (1 << 26)
5329 /* Selects the most adaptive vertical filtering mode */
5330 # define TV_VADAPT_MODE_MOST            (3 << 26)
5331 /*
5332  * Sets the horizontal scaling factor.
5333  *
5334  * This should be the fractional part of the horizontal scaling factor divided
5335  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
5336  *
5337  * (src width - 1) / ((oversample * dest width) - 1)
5338  */
5339 # define TV_HSCALE_FRAC_MASK            0x00003fff
5340 # define TV_HSCALE_FRAC_SHIFT           0
5341
5342 #define TV_FILTER_CTL_2         _MMIO(0x68084)
5343 /*
5344  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5345  *
5346  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5347  */
5348 # define TV_VSCALE_INT_MASK             0x00038000
5349 # define TV_VSCALE_INT_SHIFT            15
5350 /*
5351  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5352  *
5353  * \sa TV_VSCALE_INT_MASK
5354  */
5355 # define TV_VSCALE_FRAC_MASK            0x00007fff
5356 # define TV_VSCALE_FRAC_SHIFT           0
5357
5358 #define TV_FILTER_CTL_3         _MMIO(0x68088)
5359 /*
5360  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5361  *
5362  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5363  *
5364  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5365  */
5366 # define TV_VSCALE_IP_INT_MASK          0x00038000
5367 # define TV_VSCALE_IP_INT_SHIFT         15
5368 /*
5369  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5370  *
5371  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5372  *
5373  * \sa TV_VSCALE_IP_INT_MASK
5374  */
5375 # define TV_VSCALE_IP_FRAC_MASK         0x00007fff
5376 # define TV_VSCALE_IP_FRAC_SHIFT                0
5377
5378 #define TV_CC_CONTROL           _MMIO(0x68090)
5379 # define TV_CC_ENABLE                   (1 << 31)
5380 /*
5381  * Specifies which field to send the CC data in.
5382  *
5383  * CC data is usually sent in field 0.
5384  */
5385 # define TV_CC_FID_MASK                 (1 << 27)
5386 # define TV_CC_FID_SHIFT                27
5387 /* Sets the horizontal position of the CC data.  Usually 135. */
5388 # define TV_CC_HOFF_MASK                0x03ff0000
5389 # define TV_CC_HOFF_SHIFT               16
5390 /* Sets the vertical position of the CC data.  Usually 21 */
5391 # define TV_CC_LINE_MASK                0x0000003f
5392 # define TV_CC_LINE_SHIFT               0
5393
5394 #define TV_CC_DATA              _MMIO(0x68094)
5395 # define TV_CC_RDY                      (1 << 31)
5396 /* Second word of CC data to be transmitted. */
5397 # define TV_CC_DATA_2_MASK              0x007f0000
5398 # define TV_CC_DATA_2_SHIFT             16
5399 /* First word of CC data to be transmitted. */
5400 # define TV_CC_DATA_1_MASK              0x0000007f
5401 # define TV_CC_DATA_1_SHIFT             0
5402
5403 #define TV_H_LUMA(i)            _MMIO(0x68100 + (i) * 4) /* 60 registers */
5404 #define TV_H_CHROMA(i)          _MMIO(0x68200 + (i) * 4) /* 60 registers */
5405 #define TV_V_LUMA(i)            _MMIO(0x68300 + (i) * 4) /* 43 registers */
5406 #define TV_V_CHROMA(i)          _MMIO(0x68400 + (i) * 4) /* 43 registers */
5407
5408 /* Display Port */
5409 #define DP_A                    _MMIO(0x64000) /* eDP */
5410 #define DP_B                    _MMIO(0x64100)
5411 #define DP_C                    _MMIO(0x64200)
5412 #define DP_D                    _MMIO(0x64300)
5413
5414 #define VLV_DP_B                _MMIO(VLV_DISPLAY_BASE + 0x64100)
5415 #define VLV_DP_C                _MMIO(VLV_DISPLAY_BASE + 0x64200)
5416 #define CHV_DP_D                _MMIO(VLV_DISPLAY_BASE + 0x64300)
5417
5418 #define   DP_PORT_EN                    (1 << 31)
5419 #define   DP_PIPE_SEL_SHIFT             30
5420 #define   DP_PIPE_SEL_MASK              (1 << 30)
5421 #define   DP_PIPE_SEL(pipe)             ((pipe) << 30)
5422 #define   DP_PIPE_SEL_SHIFT_IVB         29
5423 #define   DP_PIPE_SEL_MASK_IVB          (3 << 29)
5424 #define   DP_PIPE_SEL_IVB(pipe)         ((pipe) << 29)
5425 #define   DP_PIPE_SEL_SHIFT_CHV         16
5426 #define   DP_PIPE_SEL_MASK_CHV          (3 << 16)
5427 #define   DP_PIPE_SEL_CHV(pipe)         ((pipe) << 16)
5428
5429 /* Link training mode - select a suitable mode for each stage */
5430 #define   DP_LINK_TRAIN_PAT_1           (0 << 28)
5431 #define   DP_LINK_TRAIN_PAT_2           (1 << 28)
5432 #define   DP_LINK_TRAIN_PAT_IDLE        (2 << 28)
5433 #define   DP_LINK_TRAIN_OFF             (3 << 28)
5434 #define   DP_LINK_TRAIN_MASK            (3 << 28)
5435 #define   DP_LINK_TRAIN_SHIFT           28
5436
5437 /* CPT Link training mode */
5438 #define   DP_LINK_TRAIN_PAT_1_CPT       (0 << 8)
5439 #define   DP_LINK_TRAIN_PAT_2_CPT       (1 << 8)
5440 #define   DP_LINK_TRAIN_PAT_IDLE_CPT    (2 << 8)
5441 #define   DP_LINK_TRAIN_OFF_CPT         (3 << 8)
5442 #define   DP_LINK_TRAIN_MASK_CPT        (7 << 8)
5443 #define   DP_LINK_TRAIN_SHIFT_CPT       8
5444
5445 /* Signal voltages. These are mostly controlled by the other end */
5446 #define   DP_VOLTAGE_0_4                (0 << 25)
5447 #define   DP_VOLTAGE_0_6                (1 << 25)
5448 #define   DP_VOLTAGE_0_8                (2 << 25)
5449 #define   DP_VOLTAGE_1_2                (3 << 25)
5450 #define   DP_VOLTAGE_MASK               (7 << 25)
5451 #define   DP_VOLTAGE_SHIFT              25
5452
5453 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5454  * they want
5455  */
5456 #define   DP_PRE_EMPHASIS_0             (0 << 22)
5457 #define   DP_PRE_EMPHASIS_3_5           (1 << 22)
5458 #define   DP_PRE_EMPHASIS_6             (2 << 22)
5459 #define   DP_PRE_EMPHASIS_9_5           (3 << 22)
5460 #define   DP_PRE_EMPHASIS_MASK          (7 << 22)
5461 #define   DP_PRE_EMPHASIS_SHIFT         22
5462
5463 /* How many wires to use. I guess 3 was too hard */
5464 #define   DP_PORT_WIDTH(width)          (((width) - 1) << 19)
5465 #define   DP_PORT_WIDTH_MASK            (7 << 19)
5466 #define   DP_PORT_WIDTH_SHIFT           19
5467
5468 /* Mystic DPCD version 1.1 special mode */
5469 #define   DP_ENHANCED_FRAMING           (1 << 18)
5470
5471 /* eDP */
5472 #define   DP_PLL_FREQ_270MHZ            (0 << 16)
5473 #define   DP_PLL_FREQ_162MHZ            (1 << 16)
5474 #define   DP_PLL_FREQ_MASK              (3 << 16)
5475
5476 /* locked once port is enabled */
5477 #define   DP_PORT_REVERSAL              (1 << 15)
5478
5479 /* eDP */
5480 #define   DP_PLL_ENABLE                 (1 << 14)
5481
5482 /* sends the clock on lane 15 of the PEG for debug */
5483 #define   DP_CLOCK_OUTPUT_ENABLE        (1 << 13)
5484
5485 #define   DP_SCRAMBLING_DISABLE         (1 << 12)
5486 #define   DP_SCRAMBLING_DISABLE_IRONLAKE        (1 << 7)
5487
5488 /* limit RGB values to avoid confusing TVs */
5489 #define   DP_COLOR_RANGE_16_235         (1 << 8)
5490
5491 /* Turn on the audio link */
5492 #define   DP_AUDIO_OUTPUT_ENABLE        (1 << 6)
5493
5494 /* vs and hs sync polarity */
5495 #define   DP_SYNC_VS_HIGH               (1 << 4)
5496 #define   DP_SYNC_HS_HIGH               (1 << 3)
5497
5498 /* A fantasy */
5499 #define   DP_DETECTED                   (1 << 2)
5500
5501 /* The aux channel provides a way to talk to the
5502  * signal sink for DDC etc. Max packet size supported
5503  * is 20 bytes in each direction, hence the 5 fixed
5504  * data registers
5505  */
5506 #define _DPA_AUX_CH_CTL         (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
5507 #define _DPA_AUX_CH_DATA1       (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5508 #define _DPA_AUX_CH_DATA2       (DISPLAY_MMIO_BASE(dev_priv) + 0x64018)
5509 #define _DPA_AUX_CH_DATA3       (DISPLAY_MMIO_BASE(dev_priv) + 0x6401c)
5510 #define _DPA_AUX_CH_DATA4       (DISPLAY_MMIO_BASE(dev_priv) + 0x64020)
5511 #define _DPA_AUX_CH_DATA5       (DISPLAY_MMIO_BASE(dev_priv) + 0x64024)
5512
5513 #define _DPB_AUX_CH_CTL         (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
5514 #define _DPB_AUX_CH_DATA1       (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5515 #define _DPB_AUX_CH_DATA2       (DISPLAY_MMIO_BASE(dev_priv) + 0x64118)
5516 #define _DPB_AUX_CH_DATA3       (DISPLAY_MMIO_BASE(dev_priv) + 0x6411c)
5517 #define _DPB_AUX_CH_DATA4       (DISPLAY_MMIO_BASE(dev_priv) + 0x64120)
5518 #define _DPB_AUX_CH_DATA5       (DISPLAY_MMIO_BASE(dev_priv) + 0x64124)
5519
5520 #define _DPC_AUX_CH_CTL         (DISPLAY_MMIO_BASE(dev_priv) + 0x64210)
5521 #define _DPC_AUX_CH_DATA1       (DISPLAY_MMIO_BASE(dev_priv) + 0x64214)
5522 #define _DPC_AUX_CH_DATA2       (DISPLAY_MMIO_BASE(dev_priv) + 0x64218)
5523 #define _DPC_AUX_CH_DATA3       (DISPLAY_MMIO_BASE(dev_priv) + 0x6421c)
5524 #define _DPC_AUX_CH_DATA4       (DISPLAY_MMIO_BASE(dev_priv) + 0x64220)
5525 #define _DPC_AUX_CH_DATA5       (DISPLAY_MMIO_BASE(dev_priv) + 0x64224)
5526
5527 #define _DPD_AUX_CH_CTL         (DISPLAY_MMIO_BASE(dev_priv) + 0x64310)
5528 #define _DPD_AUX_CH_DATA1       (DISPLAY_MMIO_BASE(dev_priv) + 0x64314)
5529 #define _DPD_AUX_CH_DATA2       (DISPLAY_MMIO_BASE(dev_priv) + 0x64318)
5530 #define _DPD_AUX_CH_DATA3       (DISPLAY_MMIO_BASE(dev_priv) + 0x6431c)
5531 #define _DPD_AUX_CH_DATA4       (DISPLAY_MMIO_BASE(dev_priv) + 0x64320)
5532 #define _DPD_AUX_CH_DATA5       (DISPLAY_MMIO_BASE(dev_priv) + 0x64324)
5533
5534 #define _DPE_AUX_CH_CTL         (DISPLAY_MMIO_BASE(dev_priv) + 0x64410)
5535 #define _DPE_AUX_CH_DATA1       (DISPLAY_MMIO_BASE(dev_priv) + 0x64414)
5536 #define _DPE_AUX_CH_DATA2       (DISPLAY_MMIO_BASE(dev_priv) + 0x64418)
5537 #define _DPE_AUX_CH_DATA3       (DISPLAY_MMIO_BASE(dev_priv) + 0x6441c)
5538 #define _DPE_AUX_CH_DATA4       (DISPLAY_MMIO_BASE(dev_priv) + 0x64420)
5539 #define _DPE_AUX_CH_DATA5       (DISPLAY_MMIO_BASE(dev_priv) + 0x64424)
5540
5541 #define _DPF_AUX_CH_CTL         (DISPLAY_MMIO_BASE(dev_priv) + 0x64510)
5542 #define _DPF_AUX_CH_DATA1       (DISPLAY_MMIO_BASE(dev_priv) + 0x64514)
5543 #define _DPF_AUX_CH_DATA2       (DISPLAY_MMIO_BASE(dev_priv) + 0x64518)
5544 #define _DPF_AUX_CH_DATA3       (DISPLAY_MMIO_BASE(dev_priv) + 0x6451c)
5545 #define _DPF_AUX_CH_DATA4       (DISPLAY_MMIO_BASE(dev_priv) + 0x64520)
5546 #define _DPF_AUX_CH_DATA5       (DISPLAY_MMIO_BASE(dev_priv) + 0x64524)
5547
5548 #define DP_AUX_CH_CTL(aux_ch)   _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5549 #define DP_AUX_CH_DATA(aux_ch, i)       _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5550
5551 #define   DP_AUX_CH_CTL_SEND_BUSY           (1 << 31)
5552 #define   DP_AUX_CH_CTL_DONE                (1 << 30)
5553 #define   DP_AUX_CH_CTL_INTERRUPT           (1 << 29)
5554 #define   DP_AUX_CH_CTL_TIME_OUT_ERROR      (1 << 28)
5555 #define   DP_AUX_CH_CTL_TIME_OUT_400us      (0 << 26)
5556 #define   DP_AUX_CH_CTL_TIME_OUT_600us      (1 << 26)
5557 #define   DP_AUX_CH_CTL_TIME_OUT_800us      (2 << 26)
5558 #define   DP_AUX_CH_CTL_TIME_OUT_MAX        (3 << 26) /* Varies per platform */
5559 #define   DP_AUX_CH_CTL_TIME_OUT_MASK       (3 << 26)
5560 #define   DP_AUX_CH_CTL_RECEIVE_ERROR       (1 << 25)
5561 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
5562 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
5563 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
5564 #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
5565 #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT     (1 << 15)
5566 #define   DP_AUX_CH_CTL_MANCHESTER_TEST     (1 << 14)
5567 #define   DP_AUX_CH_CTL_SYNC_TEST           (1 << 13)
5568 #define   DP_AUX_CH_CTL_DEGLITCH_TEST       (1 << 12)
5569 #define   DP_AUX_CH_CTL_PRECHARGE_TEST      (1 << 11)
5570 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
5571 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
5572 #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL    (1 << 14)
5573 #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL     (1 << 13)
5574 #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL    (1 << 12)
5575 #define   DP_AUX_CH_CTL_TBT_IO                  (1 << 11)
5576 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5577 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5578 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
5579
5580 /*
5581  * Computing GMCH M and N values for the Display Port link
5582  *
5583  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5584  *
5585  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5586  *
5587  * The GMCH value is used internally
5588  *
5589  * bytes_per_pixel is the number of bytes coming out of the plane,
5590  * which is after the LUTs, so we want the bytes for our color format.
5591  * For our current usage, this is always 3, one byte for R, G and B.
5592  */
5593 #define _PIPEA_DATA_M_G4X       0x70050
5594 #define _PIPEB_DATA_M_G4X       0x71050
5595
5596 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5597 #define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
5598 #define  TU_SIZE_SHIFT          25
5599 #define  TU_SIZE_MASK           (0x3f << 25)
5600
5601 #define  DATA_LINK_M_N_MASK     (0xffffff)
5602 #define  DATA_LINK_N_MAX        (0x800000)
5603
5604 #define _PIPEA_DATA_N_G4X       0x70054
5605 #define _PIPEB_DATA_N_G4X       0x71054
5606 #define   PIPE_GMCH_DATA_N_MASK                 (0xffffff)
5607
5608 /*
5609  * Computing Link M and N values for the Display Port link
5610  *
5611  * Link M / N = pixel_clock / ls_clk
5612  *
5613  * (the DP spec calls pixel_clock the 'strm_clk')
5614  *
5615  * The Link value is transmitted in the Main Stream
5616  * Attributes and VB-ID.
5617  */
5618
5619 #define _PIPEA_LINK_M_G4X       0x70060
5620 #define _PIPEB_LINK_M_G4X       0x71060
5621 #define   PIPEA_DP_LINK_M_MASK                  (0xffffff)
5622
5623 #define _PIPEA_LINK_N_G4X       0x70064
5624 #define _PIPEB_LINK_N_G4X       0x71064
5625 #define   PIPEA_DP_LINK_N_MASK                  (0xffffff)
5626
5627 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5628 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5629 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5630 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5631
5632 /* Display & cursor control */
5633
5634 /* Pipe A */
5635 #define _PIPEADSL               0x70000
5636 #define   DSL_LINEMASK_GEN2     0x00000fff
5637 #define   DSL_LINEMASK_GEN3     0x00001fff
5638 #define _PIPEACONF              0x70008
5639 #define   PIPECONF_ENABLE       (1 << 31)
5640 #define   PIPECONF_DISABLE      0
5641 #define   PIPECONF_DOUBLE_WIDE  (1 << 30)
5642 #define   I965_PIPECONF_ACTIVE  (1 << 30)
5643 #define   PIPECONF_DSI_PLL_LOCKED       (1 << 29) /* vlv & pipe A only */
5644 #define   PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
5645 #define   PIPECONF_SINGLE_WIDE  0
5646 #define   PIPECONF_PIPE_UNLOCKED 0
5647 #define   PIPECONF_PIPE_LOCKED  (1 << 25)
5648 #define   PIPECONF_FORCE_BORDER (1 << 25)
5649 #define   PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */
5650 #define   PIPECONF_GAMMA_MODE_MASK_ILK  (3 << 24) /* ilk-ivb */
5651 #define   PIPECONF_GAMMA_MODE_8BIT      (0 << 24) /* gmch,ilk-ivb */
5652 #define   PIPECONF_GAMMA_MODE_10BIT     (1 << 24) /* gmch,ilk-ivb */
5653 #define   PIPECONF_GAMMA_MODE_12BIT     (2 << 24) /* ilk-ivb */
5654 #define   PIPECONF_GAMMA_MODE_SPLIT     (3 << 24) /* ivb */
5655 #define   PIPECONF_GAMMA_MODE(x)        ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
5656 #define   PIPECONF_GAMMA_MODE_SHIFT     24
5657 #define   PIPECONF_INTERLACE_MASK       (7 << 21)
5658 #define   PIPECONF_INTERLACE_MASK_HSW   (3 << 21)
5659 /* Note that pre-gen3 does not support interlaced display directly. Panel
5660  * fitting must be disabled on pre-ilk for interlaced. */
5661 #define   PIPECONF_PROGRESSIVE                  (0 << 21)
5662 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
5663 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT       (5 << 21) /* gen4 only */
5664 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5665 #define   PIPECONF_INTERLACE_FIELD_0_ONLY       (7 << 21) /* gen3 only */
5666 /* Ironlake and later have a complete new set of values for interlaced. PFIT
5667  * means panel fitter required, PF means progressive fetch, DBL means power
5668  * saving pixel doubling. */
5669 #define   PIPECONF_PFIT_PF_INTERLACED_ILK       (1 << 21)
5670 #define   PIPECONF_INTERLACED_ILK               (3 << 21)
5671 #define   PIPECONF_INTERLACED_DBL_ILK           (4 << 21) /* ilk/snb only */
5672 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK   (5 << 21) /* ilk/snb only */
5673 #define   PIPECONF_INTERLACE_MODE_MASK          (7 << 21)
5674 #define   PIPECONF_EDP_RR_MODE_SWITCH           (1 << 20)
5675 #define   PIPECONF_CXSR_DOWNCLOCK       (1 << 16)
5676 #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV       (1 << 14)
5677 #define   PIPECONF_COLOR_RANGE_SELECT   (1 << 13)
5678 #define   PIPECONF_BPC_MASK     (0x7 << 5)
5679 #define   PIPECONF_8BPC         (0 << 5)
5680 #define   PIPECONF_10BPC        (1 << 5)
5681 #define   PIPECONF_6BPC         (2 << 5)
5682 #define   PIPECONF_12BPC        (3 << 5)
5683 #define   PIPECONF_DITHER_EN    (1 << 4)
5684 #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5685 #define   PIPECONF_DITHER_TYPE_SP (0 << 2)
5686 #define   PIPECONF_DITHER_TYPE_ST1 (1 << 2)
5687 #define   PIPECONF_DITHER_TYPE_ST2 (2 << 2)
5688 #define   PIPECONF_DITHER_TYPE_TEMP (3 << 2)
5689 #define _PIPEASTAT              0x70024
5690 #define   PIPE_FIFO_UNDERRUN_STATUS             (1UL << 31)
5691 #define   SPRITE1_FLIP_DONE_INT_EN_VLV          (1UL << 30)
5692 #define   PIPE_CRC_ERROR_ENABLE                 (1UL << 29)
5693 #define   PIPE_CRC_DONE_ENABLE                  (1UL << 28)
5694 #define   PERF_COUNTER2_INTERRUPT_EN            (1UL << 27)
5695 #define   PIPE_GMBUS_EVENT_ENABLE               (1UL << 27)
5696 #define   PLANE_FLIP_DONE_INT_EN_VLV            (1UL << 26)
5697 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE         (1UL << 26)
5698 #define   PIPE_VSYNC_INTERRUPT_ENABLE           (1UL << 25)
5699 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE      (1UL << 24)
5700 #define   PIPE_DPST_EVENT_ENABLE                (1UL << 23)
5701 #define   SPRITE0_FLIP_DONE_INT_EN_VLV          (1UL << 22)
5702 #define   PIPE_LEGACY_BLC_EVENT_ENABLE          (1UL << 22)
5703 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE       (1UL << 21)
5704 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE      (1UL << 20)
5705 #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV       (1UL << 19)
5706 #define   PERF_COUNTER_INTERRUPT_EN             (1UL << 19)
5707 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE      (1UL << 18) /* pre-965 */
5708 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE    (1UL << 18) /* 965 or later */
5709 #define   PIPE_FRAMESTART_INTERRUPT_ENABLE      (1UL << 17)
5710 #define   PIPE_VBLANK_INTERRUPT_ENABLE          (1UL << 17)
5711 #define   PIPEA_HBLANK_INT_EN_VLV               (1UL << 16)
5712 #define   PIPE_OVERLAY_UPDATED_ENABLE           (1UL << 16)
5713 #define   SPRITE1_FLIP_DONE_INT_STATUS_VLV      (1UL << 15)
5714 #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV      (1UL << 14)
5715 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS       (1UL << 13)
5716 #define   PIPE_CRC_DONE_INTERRUPT_STATUS        (1UL << 12)
5717 #define   PERF_COUNTER2_INTERRUPT_STATUS        (1UL << 11)
5718 #define   PIPE_GMBUS_INTERRUPT_STATUS           (1UL << 11)
5719 #define   PLANE_FLIP_DONE_INT_STATUS_VLV        (1UL << 10)
5720 #define   PIPE_HOTPLUG_INTERRUPT_STATUS         (1UL << 10)
5721 #define   PIPE_VSYNC_INTERRUPT_STATUS           (1UL << 9)
5722 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS      (1UL << 8)
5723 #define   PIPE_DPST_EVENT_STATUS                (1UL << 7)
5724 #define   PIPE_A_PSR_STATUS_VLV                 (1UL << 6)
5725 #define   PIPE_LEGACY_BLC_EVENT_STATUS          (1UL << 6)
5726 #define   PIPE_ODD_FIELD_INTERRUPT_STATUS       (1UL << 5)
5727 #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS      (1UL << 4)
5728 #define   PIPE_B_PSR_STATUS_VLV                 (1UL << 3)
5729 #define   PERF_COUNTER_INTERRUPT_STATUS         (1UL << 3)
5730 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS      (1UL << 2) /* pre-965 */
5731 #define   PIPE_START_VBLANK_INTERRUPT_STATUS    (1UL << 2) /* 965 or later */
5732 #define   PIPE_FRAMESTART_INTERRUPT_STATUS      (1UL << 1)
5733 #define   PIPE_VBLANK_INTERRUPT_STATUS          (1UL << 1)
5734 #define   PIPE_HBLANK_INT_STATUS                (1UL << 0)
5735 #define   PIPE_OVERLAY_UPDATED_STATUS           (1UL << 0)
5736
5737 #define PIPESTAT_INT_ENABLE_MASK                0x7fff0000
5738 #define PIPESTAT_INT_STATUS_MASK                0x0000ffff
5739
5740 #define PIPE_A_OFFSET           0x70000
5741 #define PIPE_B_OFFSET           0x71000
5742 #define PIPE_C_OFFSET           0x72000
5743 #define PIPE_D_OFFSET           0x73000
5744 #define CHV_PIPE_C_OFFSET       0x74000
5745 /*
5746  * There's actually no pipe EDP. Some pipe registers have
5747  * simply shifted from the pipe to the transcoder, while
5748  * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5749  * to access such registers in transcoder EDP.
5750  */
5751 #define PIPE_EDP_OFFSET 0x7f000
5752
5753 /* ICL DSI 0 and 1 */
5754 #define PIPE_DSI0_OFFSET        0x7b000
5755 #define PIPE_DSI1_OFFSET        0x7b800
5756
5757 #define PIPECONF(pipe)          _MMIO_PIPE2(pipe, _PIPEACONF)
5758 #define PIPEDSL(pipe)           _MMIO_PIPE2(pipe, _PIPEADSL)
5759 #define PIPEFRAME(pipe)         _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5760 #define PIPEFRAMEPIXEL(pipe)    _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5761 #define PIPESTAT(pipe)          _MMIO_PIPE2(pipe, _PIPEASTAT)
5762
5763 #define  _PIPEAGCMAX           0x70010
5764 #define  _PIPEBGCMAX           0x71010
5765 #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
5766
5767 #define _PIPE_MISC_A                    0x70030
5768 #define _PIPE_MISC_B                    0x71030
5769 #define   PIPEMISC_YUV420_ENABLE        (1 << 27)
5770 #define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
5771 #define   PIPEMISC_HDR_MODE_PRECISION   (1 << 23) /* icl+ */
5772 #define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
5773 #define   PIPEMISC_DITHER_BPC_MASK      (7 << 5)
5774 #define   PIPEMISC_DITHER_8_BPC         (0 << 5)
5775 #define   PIPEMISC_DITHER_10_BPC        (1 << 5)
5776 #define   PIPEMISC_DITHER_6_BPC         (2 << 5)
5777 #define   PIPEMISC_DITHER_12_BPC        (3 << 5)
5778 #define   PIPEMISC_DITHER_ENABLE        (1 << 4)
5779 #define   PIPEMISC_DITHER_TYPE_MASK     (3 << 2)
5780 #define   PIPEMISC_DITHER_TYPE_SP       (0 << 2)
5781 #define PIPEMISC(pipe)                  _MMIO_PIPE2(pipe, _PIPE_MISC_A)
5782
5783 /* Skylake+ pipe bottom (background) color */
5784 #define _SKL_BOTTOM_COLOR_A             0x70034
5785 #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
5786 #define   SKL_BOTTOM_COLOR_CSC_ENABLE   (1 << 30)
5787 #define SKL_BOTTOM_COLOR(pipe)          _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
5788
5789 #define VLV_DPFLIPSTAT                          _MMIO(VLV_DISPLAY_BASE + 0x70028)
5790 #define   PIPEB_LINE_COMPARE_INT_EN             (1 << 29)
5791 #define   PIPEB_HLINE_INT_EN                    (1 << 28)
5792 #define   PIPEB_VBLANK_INT_EN                   (1 << 27)
5793 #define   SPRITED_FLIP_DONE_INT_EN              (1 << 26)
5794 #define   SPRITEC_FLIP_DONE_INT_EN              (1 << 25)
5795 #define   PLANEB_FLIP_DONE_INT_EN               (1 << 24)
5796 #define   PIPE_PSR_INT_EN                       (1 << 22)
5797 #define   PIPEA_LINE_COMPARE_INT_EN             (1 << 21)
5798 #define   PIPEA_HLINE_INT_EN                    (1 << 20)
5799 #define   PIPEA_VBLANK_INT_EN                   (1 << 19)
5800 #define   SPRITEB_FLIP_DONE_INT_EN              (1 << 18)
5801 #define   SPRITEA_FLIP_DONE_INT_EN              (1 << 17)
5802 #define   PLANEA_FLIPDONE_INT_EN                (1 << 16)
5803 #define   PIPEC_LINE_COMPARE_INT_EN             (1 << 13)
5804 #define   PIPEC_HLINE_INT_EN                    (1 << 12)
5805 #define   PIPEC_VBLANK_INT_EN                   (1 << 11)
5806 #define   SPRITEF_FLIPDONE_INT_EN               (1 << 10)
5807 #define   SPRITEE_FLIPDONE_INT_EN               (1 << 9)
5808 #define   PLANEC_FLIPDONE_INT_EN                (1 << 8)
5809
5810 #define DPINVGTT                                _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5811 #define   SPRITEF_INVALID_GTT_INT_EN            (1 << 27)
5812 #define   SPRITEE_INVALID_GTT_INT_EN            (1 << 26)
5813 #define   PLANEC_INVALID_GTT_INT_EN             (1 << 25)
5814 #define   CURSORC_INVALID_GTT_INT_EN            (1 << 24)
5815 #define   CURSORB_INVALID_GTT_INT_EN            (1 << 23)
5816 #define   CURSORA_INVALID_GTT_INT_EN            (1 << 22)
5817 #define   SPRITED_INVALID_GTT_INT_EN            (1 << 21)
5818 #define   SPRITEC_INVALID_GTT_INT_EN            (1 << 20)
5819 #define   PLANEB_INVALID_GTT_INT_EN             (1 << 19)
5820 #define   SPRITEB_INVALID_GTT_INT_EN            (1 << 18)
5821 #define   SPRITEA_INVALID_GTT_INT_EN            (1 << 17)
5822 #define   PLANEA_INVALID_GTT_INT_EN             (1 << 16)
5823 #define   DPINVGTT_EN_MASK                      0xff0000
5824 #define   DPINVGTT_EN_MASK_CHV                  0xfff0000
5825 #define   SPRITEF_INVALID_GTT_STATUS            (1 << 11)
5826 #define   SPRITEE_INVALID_GTT_STATUS            (1 << 10)
5827 #define   PLANEC_INVALID_GTT_STATUS             (1 << 9)
5828 #define   CURSORC_INVALID_GTT_STATUS            (1 << 8)
5829 #define   CURSORB_INVALID_GTT_STATUS            (1 << 7)
5830 #define   CURSORA_INVALID_GTT_STATUS            (1 << 6)
5831 #define   SPRITED_INVALID_GTT_STATUS            (1 << 5)
5832 #define   SPRITEC_INVALID_GTT_STATUS            (1 << 4)
5833 #define   PLANEB_INVALID_GTT_STATUS             (1 << 3)
5834 #define   SPRITEB_INVALID_GTT_STATUS            (1 << 2)
5835 #define   SPRITEA_INVALID_GTT_STATUS            (1 << 1)
5836 #define   PLANEA_INVALID_GTT_STATUS             (1 << 0)
5837 #define   DPINVGTT_STATUS_MASK                  0xff
5838 #define   DPINVGTT_STATUS_MASK_CHV              0xfff
5839
5840 #define DSPARB                  _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
5841 #define   DSPARB_CSTART_MASK    (0x7f << 7)
5842 #define   DSPARB_CSTART_SHIFT   7
5843 #define   DSPARB_BSTART_MASK    (0x7f)
5844 #define   DSPARB_BSTART_SHIFT   0
5845 #define   DSPARB_BEND_SHIFT     9 /* on 855 */
5846 #define   DSPARB_AEND_SHIFT     0
5847 #define   DSPARB_SPRITEA_SHIFT_VLV      0
5848 #define   DSPARB_SPRITEA_MASK_VLV       (0xff << 0)
5849 #define   DSPARB_SPRITEB_SHIFT_VLV      8
5850 #define   DSPARB_SPRITEB_MASK_VLV       (0xff << 8)
5851 #define   DSPARB_SPRITEC_SHIFT_VLV      16
5852 #define   DSPARB_SPRITEC_MASK_VLV       (0xff << 16)
5853 #define   DSPARB_SPRITED_SHIFT_VLV      24
5854 #define   DSPARB_SPRITED_MASK_VLV       (0xff << 24)
5855 #define DSPARB2                         _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5856 #define   DSPARB_SPRITEA_HI_SHIFT_VLV   0
5857 #define   DSPARB_SPRITEA_HI_MASK_VLV    (0x1 << 0)
5858 #define   DSPARB_SPRITEB_HI_SHIFT_VLV   4
5859 #define   DSPARB_SPRITEB_HI_MASK_VLV    (0x1 << 4)
5860 #define   DSPARB_SPRITEC_HI_SHIFT_VLV   8
5861 #define   DSPARB_SPRITEC_HI_MASK_VLV    (0x1 << 8)
5862 #define   DSPARB_SPRITED_HI_SHIFT_VLV   12
5863 #define   DSPARB_SPRITED_HI_MASK_VLV    (0x1 << 12)
5864 #define   DSPARB_SPRITEE_HI_SHIFT_VLV   16
5865 #define   DSPARB_SPRITEE_HI_MASK_VLV    (0x1 << 16)
5866 #define   DSPARB_SPRITEF_HI_SHIFT_VLV   20
5867 #define   DSPARB_SPRITEF_HI_MASK_VLV    (0x1 << 20)
5868 #define DSPARB3                         _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5869 #define   DSPARB_SPRITEE_SHIFT_VLV      0
5870 #define   DSPARB_SPRITEE_MASK_VLV       (0xff << 0)
5871 #define   DSPARB_SPRITEF_SHIFT_VLV      8
5872 #define   DSPARB_SPRITEF_MASK_VLV       (0xff << 8)
5873
5874 /* pnv/gen4/g4x/vlv/chv */
5875 #define DSPFW1          _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
5876 #define   DSPFW_SR_SHIFT                23
5877 #define   DSPFW_SR_MASK                 (0x1ff << 23)
5878 #define   DSPFW_CURSORB_SHIFT           16
5879 #define   DSPFW_CURSORB_MASK            (0x3f << 16)
5880 #define   DSPFW_PLANEB_SHIFT            8
5881 #define   DSPFW_PLANEB_MASK             (0x7f << 8)
5882 #define   DSPFW_PLANEB_MASK_VLV         (0xff << 8) /* vlv/chv */
5883 #define   DSPFW_PLANEA_SHIFT            0
5884 #define   DSPFW_PLANEA_MASK             (0x7f << 0)
5885 #define   DSPFW_PLANEA_MASK_VLV         (0xff << 0) /* vlv/chv */
5886 #define DSPFW2          _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
5887 #define   DSPFW_FBC_SR_EN               (1 << 31)         /* g4x */
5888 #define   DSPFW_FBC_SR_SHIFT            28
5889 #define   DSPFW_FBC_SR_MASK             (0x7 << 28) /* g4x */
5890 #define   DSPFW_FBC_HPLL_SR_SHIFT       24
5891 #define   DSPFW_FBC_HPLL_SR_MASK        (0xf << 24) /* g4x */
5892 #define   DSPFW_SPRITEB_SHIFT           (16)
5893 #define   DSPFW_SPRITEB_MASK            (0x7f << 16) /* g4x */
5894 #define   DSPFW_SPRITEB_MASK_VLV        (0xff << 16) /* vlv/chv */
5895 #define   DSPFW_CURSORA_SHIFT           8
5896 #define   DSPFW_CURSORA_MASK            (0x3f << 8)
5897 #define   DSPFW_PLANEC_OLD_SHIFT        0
5898 #define   DSPFW_PLANEC_OLD_MASK         (0x7f << 0) /* pre-gen4 sprite C */
5899 #define   DSPFW_SPRITEA_SHIFT           0
5900 #define   DSPFW_SPRITEA_MASK            (0x7f << 0) /* g4x */
5901 #define   DSPFW_SPRITEA_MASK_VLV        (0xff << 0) /* vlv/chv */
5902 #define DSPFW3          _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
5903 #define   DSPFW_HPLL_SR_EN              (1 << 31)
5904 #define   PINEVIEW_SELF_REFRESH_EN      (1 << 30)
5905 #define   DSPFW_CURSOR_SR_SHIFT         24
5906 #define   DSPFW_CURSOR_SR_MASK          (0x3f << 24)
5907 #define   DSPFW_HPLL_CURSOR_SHIFT       16
5908 #define   DSPFW_HPLL_CURSOR_MASK        (0x3f << 16)
5909 #define   DSPFW_HPLL_SR_SHIFT           0
5910 #define   DSPFW_HPLL_SR_MASK            (0x1ff << 0)
5911
5912 /* vlv/chv */
5913 #define DSPFW4          _MMIO(VLV_DISPLAY_BASE + 0x70070)
5914 #define   DSPFW_SPRITEB_WM1_SHIFT       16
5915 #define   DSPFW_SPRITEB_WM1_MASK        (0xff << 16)
5916 #define   DSPFW_CURSORA_WM1_SHIFT       8
5917 #define   DSPFW_CURSORA_WM1_MASK        (0x3f << 8)
5918 #define   DSPFW_SPRITEA_WM1_SHIFT       0
5919 #define   DSPFW_SPRITEA_WM1_MASK        (0xff << 0)
5920 #define DSPFW5          _MMIO(VLV_DISPLAY_BASE + 0x70074)
5921 #define   DSPFW_PLANEB_WM1_SHIFT        24
5922 #define   DSPFW_PLANEB_WM1_MASK         (0xff << 24)
5923 #define   DSPFW_PLANEA_WM1_SHIFT        16
5924 #define   DSPFW_PLANEA_WM1_MASK         (0xff << 16)
5925 #define   DSPFW_CURSORB_WM1_SHIFT       8
5926 #define   DSPFW_CURSORB_WM1_MASK        (0x3f << 8)
5927 #define   DSPFW_CURSOR_SR_WM1_SHIFT     0
5928 #define   DSPFW_CURSOR_SR_WM1_MASK      (0x3f << 0)
5929 #define DSPFW6          _MMIO(VLV_DISPLAY_BASE + 0x70078)
5930 #define   DSPFW_SR_WM1_SHIFT            0
5931 #define   DSPFW_SR_WM1_MASK             (0x1ff << 0)
5932 #define DSPFW7          _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5933 #define DSPFW7_CHV      _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5934 #define   DSPFW_SPRITED_WM1_SHIFT       24
5935 #define   DSPFW_SPRITED_WM1_MASK        (0xff << 24)
5936 #define   DSPFW_SPRITED_SHIFT           16
5937 #define   DSPFW_SPRITED_MASK_VLV        (0xff << 16)
5938 #define   DSPFW_SPRITEC_WM1_SHIFT       8
5939 #define   DSPFW_SPRITEC_WM1_MASK        (0xff << 8)
5940 #define   DSPFW_SPRITEC_SHIFT           0
5941 #define   DSPFW_SPRITEC_MASK_VLV        (0xff << 0)
5942 #define DSPFW8_CHV      _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5943 #define   DSPFW_SPRITEF_WM1_SHIFT       24
5944 #define   DSPFW_SPRITEF_WM1_MASK        (0xff << 24)
5945 #define   DSPFW_SPRITEF_SHIFT           16
5946 #define   DSPFW_SPRITEF_MASK_VLV        (0xff << 16)
5947 #define   DSPFW_SPRITEE_WM1_SHIFT       8
5948 #define   DSPFW_SPRITEE_WM1_MASK        (0xff << 8)
5949 #define   DSPFW_SPRITEE_SHIFT           0
5950 #define   DSPFW_SPRITEE_MASK_VLV        (0xff << 0)
5951 #define DSPFW9_CHV      _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5952 #define   DSPFW_PLANEC_WM1_SHIFT        24
5953 #define   DSPFW_PLANEC_WM1_MASK         (0xff << 24)
5954 #define   DSPFW_PLANEC_SHIFT            16
5955 #define   DSPFW_PLANEC_MASK_VLV         (0xff << 16)
5956 #define   DSPFW_CURSORC_WM1_SHIFT       8
5957 #define   DSPFW_CURSORC_WM1_MASK        (0x3f << 16)
5958 #define   DSPFW_CURSORC_SHIFT           0
5959 #define   DSPFW_CURSORC_MASK            (0x3f << 0)
5960
5961 /* vlv/chv high order bits */
5962 #define DSPHOWM         _MMIO(VLV_DISPLAY_BASE + 0x70064)
5963 #define   DSPFW_SR_HI_SHIFT             24
5964 #define   DSPFW_SR_HI_MASK              (3 << 24) /* 2 bits for chv, 1 for vlv */
5965 #define   DSPFW_SPRITEF_HI_SHIFT        23
5966 #define   DSPFW_SPRITEF_HI_MASK         (1 << 23)
5967 #define   DSPFW_SPRITEE_HI_SHIFT        22
5968 #define   DSPFW_SPRITEE_HI_MASK         (1 << 22)
5969 #define   DSPFW_PLANEC_HI_SHIFT         21
5970 #define   DSPFW_PLANEC_HI_MASK          (1 << 21)
5971 #define   DSPFW_SPRITED_HI_SHIFT        20
5972 #define   DSPFW_SPRITED_HI_MASK         (1 << 20)
5973 #define   DSPFW_SPRITEC_HI_SHIFT        16
5974 #define   DSPFW_SPRITEC_HI_MASK         (1 << 16)
5975 #define   DSPFW_PLANEB_HI_SHIFT         12
5976 #define   DSPFW_PLANEB_HI_MASK          (1 << 12)
5977 #define   DSPFW_SPRITEB_HI_SHIFT        8
5978 #define   DSPFW_SPRITEB_HI_MASK         (1 << 8)
5979 #define   DSPFW_SPRITEA_HI_SHIFT        4
5980 #define   DSPFW_SPRITEA_HI_MASK         (1 << 4)
5981 #define   DSPFW_PLANEA_HI_SHIFT         0
5982 #define   DSPFW_PLANEA_HI_MASK          (1 << 0)
5983 #define DSPHOWM1        _MMIO(VLV_DISPLAY_BASE + 0x70068)
5984 #define   DSPFW_SR_WM1_HI_SHIFT         24
5985 #define   DSPFW_SR_WM1_HI_MASK          (3 << 24) /* 2 bits for chv, 1 for vlv */
5986 #define   DSPFW_SPRITEF_WM1_HI_SHIFT    23
5987 #define   DSPFW_SPRITEF_WM1_HI_MASK     (1 << 23)
5988 #define   DSPFW_SPRITEE_WM1_HI_SHIFT    22
5989 #define   DSPFW_SPRITEE_WM1_HI_MASK     (1 << 22)
5990 #define   DSPFW_PLANEC_WM1_HI_SHIFT     21
5991 #define   DSPFW_PLANEC_WM1_HI_MASK      (1 << 21)
5992 #define   DSPFW_SPRITED_WM1_HI_SHIFT    20
5993 #define   DSPFW_SPRITED_WM1_HI_MASK     (1 << 20)
5994 #define   DSPFW_SPRITEC_WM1_HI_SHIFT    16
5995 #define   DSPFW_SPRITEC_WM1_HI_MASK     (1 << 16)
5996 #define   DSPFW_PLANEB_WM1_HI_SHIFT     12
5997 #define   DSPFW_PLANEB_WM1_HI_MASK      (1 << 12)
5998 #define   DSPFW_SPRITEB_WM1_HI_SHIFT    8
5999 #define   DSPFW_SPRITEB_WM1_HI_MASK     (1 << 8)
6000 #define   DSPFW_SPRITEA_WM1_HI_SHIFT    4
6001 #define   DSPFW_SPRITEA_WM1_HI_MASK     (1 << 4)
6002 #define   DSPFW_PLANEA_WM1_HI_SHIFT     0
6003 #define   DSPFW_PLANEA_WM1_HI_MASK      (1 << 0)
6004
6005 /* drain latency register values*/
6006 #define VLV_DDL(pipe)                   _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
6007 #define DDL_CURSOR_SHIFT                24
6008 #define DDL_SPRITE_SHIFT(sprite)        (8 + 8 * (sprite))
6009 #define DDL_PLANE_SHIFT                 0
6010 #define DDL_PRECISION_HIGH              (1 << 7)
6011 #define DDL_PRECISION_LOW               (0 << 7)
6012 #define DRAIN_LATENCY_MASK              0x7f
6013
6014 #define CBR1_VLV                        _MMIO(VLV_DISPLAY_BASE + 0x70400)
6015 #define  CBR_PND_DEADLINE_DISABLE       (1 << 31)
6016 #define  CBR_PWM_CLOCK_MUX_SELECT       (1 << 30)
6017
6018 #define CBR4_VLV                        _MMIO(VLV_DISPLAY_BASE + 0x70450)
6019 #define  CBR_DPLLBMD_PIPE(pipe)         (1 << (7 + (pipe) * 11)) /* pipes B and C */
6020
6021 /* FIFO watermark sizes etc */
6022 #define G4X_FIFO_LINE_SIZE      64
6023 #define I915_FIFO_LINE_SIZE     64
6024 #define I830_FIFO_LINE_SIZE     32
6025
6026 #define VALLEYVIEW_FIFO_SIZE    255
6027 #define G4X_FIFO_SIZE           127
6028 #define I965_FIFO_SIZE          512
6029 #define I945_FIFO_SIZE          127
6030 #define I915_FIFO_SIZE          95
6031 #define I855GM_FIFO_SIZE        127 /* In cachelines */
6032 #define I830_FIFO_SIZE          95
6033
6034 #define VALLEYVIEW_MAX_WM       0xff
6035 #define G4X_MAX_WM              0x3f
6036 #define I915_MAX_WM             0x3f
6037
6038 #define PINEVIEW_DISPLAY_FIFO   512 /* in 64byte unit */
6039 #define PINEVIEW_FIFO_LINE_SIZE 64
6040 #define PINEVIEW_MAX_WM         0x1ff
6041 #define PINEVIEW_DFT_WM         0x3f
6042 #define PINEVIEW_DFT_HPLLOFF_WM 0
6043 #define PINEVIEW_GUARD_WM               10
6044 #define PINEVIEW_CURSOR_FIFO            64
6045 #define PINEVIEW_CURSOR_MAX_WM  0x3f
6046 #define PINEVIEW_CURSOR_DFT_WM  0
6047 #define PINEVIEW_CURSOR_GUARD_WM        5
6048
6049 #define VALLEYVIEW_CURSOR_MAX_WM 64
6050 #define I965_CURSOR_FIFO        64
6051 #define I965_CURSOR_MAX_WM      32
6052 #define I965_CURSOR_DFT_WM      8
6053
6054 /* Watermark register definitions for SKL */
6055 #define _CUR_WM_A_0             0x70140
6056 #define _CUR_WM_B_0             0x71140
6057 #define _PLANE_WM_1_A_0         0x70240
6058 #define _PLANE_WM_1_B_0         0x71240
6059 #define _PLANE_WM_2_A_0         0x70340
6060 #define _PLANE_WM_2_B_0         0x71340
6061 #define _PLANE_WM_TRANS_1_A_0   0x70268
6062 #define _PLANE_WM_TRANS_1_B_0   0x71268
6063 #define _PLANE_WM_TRANS_2_A_0   0x70368
6064 #define _PLANE_WM_TRANS_2_B_0   0x71368
6065 #define _CUR_WM_TRANS_A_0       0x70168
6066 #define _CUR_WM_TRANS_B_0       0x71168
6067 #define   PLANE_WM_EN           (1 << 31)
6068 #define   PLANE_WM_IGNORE_LINES (1 << 30)
6069 #define   PLANE_WM_LINES_SHIFT  14
6070 #define   PLANE_WM_LINES_MASK   0x1f
6071 #define   PLANE_WM_BLOCKS_MASK  0x7ff /* skl+: 10 bits, icl+ 11 bits */
6072
6073 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
6074 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
6075 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
6076
6077 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
6078 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
6079 #define _PLANE_WM_BASE(pipe, plane)     \
6080                         _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
6081 #define PLANE_WM(pipe, plane, level)    \
6082                         _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
6083 #define _PLANE_WM_TRANS_1(pipe) \
6084                         _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
6085 #define _PLANE_WM_TRANS_2(pipe) \
6086                         _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
6087 #define PLANE_WM_TRANS(pipe, plane)     \
6088         _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
6089
6090 /* define the Watermark register on Ironlake */
6091 #define WM0_PIPEA_ILK           _MMIO(0x45100)
6092 #define  WM0_PIPE_PLANE_MASK    (0xffff << 16)
6093 #define  WM0_PIPE_PLANE_SHIFT   16
6094 #define  WM0_PIPE_SPRITE_MASK   (0xff << 8)
6095 #define  WM0_PIPE_SPRITE_SHIFT  8
6096 #define  WM0_PIPE_CURSOR_MASK   (0xff)
6097
6098 #define WM0_PIPEB_ILK           _MMIO(0x45104)
6099 #define WM0_PIPEC_IVB           _MMIO(0x45200)
6100 #define WM1_LP_ILK              _MMIO(0x45108)
6101 #define  WM1_LP_SR_EN           (1 << 31)
6102 #define  WM1_LP_LATENCY_SHIFT   24
6103 #define  WM1_LP_LATENCY_MASK    (0x7f << 24)
6104 #define  WM1_LP_FBC_MASK        (0xf << 20)
6105 #define  WM1_LP_FBC_SHIFT       20
6106 #define  WM1_LP_FBC_SHIFT_BDW   19
6107 #define  WM1_LP_SR_MASK         (0x7ff << 8)
6108 #define  WM1_LP_SR_SHIFT        8
6109 #define  WM1_LP_CURSOR_MASK     (0xff)
6110 #define WM2_LP_ILK              _MMIO(0x4510c)
6111 #define  WM2_LP_EN              (1 << 31)
6112 #define WM3_LP_ILK              _MMIO(0x45110)
6113 #define  WM3_LP_EN              (1 << 31)
6114 #define WM1S_LP_ILK             _MMIO(0x45120)
6115 #define WM2S_LP_IVB             _MMIO(0x45124)
6116 #define WM3S_LP_IVB             _MMIO(0x45128)
6117 #define  WM1S_LP_EN             (1 << 31)
6118
6119 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6120         (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6121          ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6122
6123 /* Memory latency timer register */
6124 #define MLTR_ILK                _MMIO(0x11222)
6125 #define  MLTR_WM1_SHIFT         0
6126 #define  MLTR_WM2_SHIFT         8
6127 /* the unit of memory self-refresh latency time is 0.5us */
6128 #define  ILK_SRLT_MASK          0x3f
6129
6130
6131 /* the address where we get all kinds of latency value */
6132 #define SSKPD                   _MMIO(0x5d10)
6133 #define SSKPD_WM_MASK           0x3f
6134 #define SSKPD_WM0_SHIFT         0
6135 #define SSKPD_WM1_SHIFT         8
6136 #define SSKPD_WM2_SHIFT         16
6137 #define SSKPD_WM3_SHIFT         24
6138
6139 /*
6140  * The two pipe frame counter registers are not synchronized, so
6141  * reading a stable value is somewhat tricky. The following code
6142  * should work:
6143  *
6144  *  do {
6145  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6146  *             PIPE_FRAME_HIGH_SHIFT;
6147  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6148  *             PIPE_FRAME_LOW_SHIFT);
6149  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6150  *             PIPE_FRAME_HIGH_SHIFT);
6151  *  } while (high1 != high2);
6152  *  frame = (high1 << 8) | low1;
6153  */
6154 #define _PIPEAFRAMEHIGH          0x70040
6155 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
6156 #define   PIPE_FRAME_HIGH_SHIFT   0
6157 #define _PIPEAFRAMEPIXEL         0x70044
6158 #define   PIPE_FRAME_LOW_MASK     0xff000000
6159 #define   PIPE_FRAME_LOW_SHIFT    24
6160 #define   PIPE_PIXEL_MASK         0x00ffffff
6161 #define   PIPE_PIXEL_SHIFT        0
6162 /* GM45+ just has to be different */
6163 #define _PIPEA_FRMCOUNT_G4X     0x70040
6164 #define _PIPEA_FLIPCOUNT_G4X    0x70044
6165 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6166 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6167
6168 /* Cursor A & B regs */
6169 #define _CURACNTR               0x70080
6170 /* Old style CUR*CNTR flags (desktop 8xx) */
6171 #define   CURSOR_ENABLE         0x80000000
6172 #define   CURSOR_GAMMA_ENABLE   0x40000000
6173 #define   CURSOR_STRIDE_SHIFT   28
6174 #define   CURSOR_STRIDE(x)      ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6175 #define   CURSOR_FORMAT_SHIFT   24
6176 #define   CURSOR_FORMAT_MASK    (0x07 << CURSOR_FORMAT_SHIFT)
6177 #define   CURSOR_FORMAT_2C      (0x00 << CURSOR_FORMAT_SHIFT)
6178 #define   CURSOR_FORMAT_3C      (0x01 << CURSOR_FORMAT_SHIFT)
6179 #define   CURSOR_FORMAT_4C      (0x02 << CURSOR_FORMAT_SHIFT)
6180 #define   CURSOR_FORMAT_ARGB    (0x04 << CURSOR_FORMAT_SHIFT)
6181 #define   CURSOR_FORMAT_XRGB    (0x05 << CURSOR_FORMAT_SHIFT)
6182 /* New style CUR*CNTR flags */
6183 #define   MCURSOR_MODE          0x27
6184 #define   MCURSOR_MODE_DISABLE   0x00
6185 #define   MCURSOR_MODE_128_32B_AX 0x02
6186 #define   MCURSOR_MODE_256_32B_AX 0x03
6187 #define   MCURSOR_MODE_64_32B_AX 0x07
6188 #define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6189 #define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6190 #define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6191 #define   MCURSOR_PIPE_SELECT_MASK      (0x3 << 28)
6192 #define   MCURSOR_PIPE_SELECT_SHIFT     28
6193 #define   MCURSOR_PIPE_SELECT(pipe)     ((pipe) << 28)
6194 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
6195 #define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6196 #define   MCURSOR_ROTATE_180    (1 << 15)
6197 #define   MCURSOR_TRICKLE_FEED_DISABLE  (1 << 14)
6198 #define _CURABASE               0x70084
6199 #define _CURAPOS                0x70088
6200 #define   CURSOR_POS_MASK       0x007FF
6201 #define   CURSOR_POS_SIGN       0x8000
6202 #define   CURSOR_X_SHIFT        0
6203 #define   CURSOR_Y_SHIFT        16
6204 #define CURSIZE                 _MMIO(0x700a0) /* 845/865 */
6205 #define _CUR_FBC_CTL_A          0x700a0 /* ivb+ */
6206 #define   CUR_FBC_CTL_EN        (1 << 31)
6207 #define _CURASURFLIVE           0x700ac /* g4x+ */
6208 #define _CURBCNTR               0x700c0
6209 #define _CURBBASE               0x700c4
6210 #define _CURBPOS                0x700c8
6211
6212 #define _CURBCNTR_IVB           0x71080
6213 #define _CURBBASE_IVB           0x71084
6214 #define _CURBPOS_IVB            0x71088
6215
6216 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6217 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6218 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6219 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6220 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6221
6222 #define CURSOR_A_OFFSET 0x70080
6223 #define CURSOR_B_OFFSET 0x700c0
6224 #define CHV_CURSOR_C_OFFSET 0x700e0
6225 #define IVB_CURSOR_B_OFFSET 0x71080
6226 #define IVB_CURSOR_C_OFFSET 0x72080
6227
6228 /* Display A control */
6229 #define _DSPACNTR                               0x70180
6230 #define   DISPLAY_PLANE_ENABLE                  (1 << 31)
6231 #define   DISPLAY_PLANE_DISABLE                 0
6232 #define   DISPPLANE_GAMMA_ENABLE                (1 << 30)
6233 #define   DISPPLANE_GAMMA_DISABLE               0
6234 #define   DISPPLANE_PIXFORMAT_MASK              (0xf << 26)
6235 #define   DISPPLANE_YUV422                      (0x0 << 26)
6236 #define   DISPPLANE_8BPP                        (0x2 << 26)
6237 #define   DISPPLANE_BGRA555                     (0x3 << 26)
6238 #define   DISPPLANE_BGRX555                     (0x4 << 26)
6239 #define   DISPPLANE_BGRX565                     (0x5 << 26)
6240 #define   DISPPLANE_BGRX888                     (0x6 << 26)
6241 #define   DISPPLANE_BGRA888                     (0x7 << 26)
6242 #define   DISPPLANE_RGBX101010                  (0x8 << 26)
6243 #define   DISPPLANE_RGBA101010                  (0x9 << 26)
6244 #define   DISPPLANE_BGRX101010                  (0xa << 26)
6245 #define   DISPPLANE_RGBX161616                  (0xc << 26)
6246 #define   DISPPLANE_RGBX888                     (0xe << 26)
6247 #define   DISPPLANE_RGBA888                     (0xf << 26)
6248 #define   DISPPLANE_STEREO_ENABLE               (1 << 25)
6249 #define   DISPPLANE_STEREO_DISABLE              0
6250 #define   DISPPLANE_PIPE_CSC_ENABLE             (1 << 24) /* ilk+ */
6251 #define   DISPPLANE_SEL_PIPE_SHIFT              24
6252 #define   DISPPLANE_SEL_PIPE_MASK               (3 << DISPPLANE_SEL_PIPE_SHIFT)
6253 #define   DISPPLANE_SEL_PIPE(pipe)              ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6254 #define   DISPPLANE_SRC_KEY_ENABLE              (1 << 22)
6255 #define   DISPPLANE_SRC_KEY_DISABLE             0
6256 #define   DISPPLANE_LINE_DOUBLE                 (1 << 20)
6257 #define   DISPPLANE_NO_LINE_DOUBLE              0
6258 #define   DISPPLANE_STEREO_POLARITY_FIRST       0
6259 #define   DISPPLANE_STEREO_POLARITY_SECOND      (1 << 18)
6260 #define   DISPPLANE_ALPHA_PREMULTIPLY           (1 << 16) /* CHV pipe B */
6261 #define   DISPPLANE_ROTATE_180                  (1 << 15)
6262 #define   DISPPLANE_TRICKLE_FEED_DISABLE        (1 << 14) /* Ironlake */
6263 #define   DISPPLANE_TILED                       (1 << 10)
6264 #define   DISPPLANE_MIRROR                      (1 << 8) /* CHV pipe B */
6265 #define _DSPAADDR                               0x70184
6266 #define _DSPASTRIDE                             0x70188
6267 #define _DSPAPOS                                0x7018C /* reserved */
6268 #define _DSPASIZE                               0x70190
6269 #define _DSPASURF                               0x7019C /* 965+ only */
6270 #define _DSPATILEOFF                            0x701A4 /* 965+ only */
6271 #define _DSPAOFFSET                             0x701A4 /* HSW */
6272 #define _DSPASURFLIVE                           0x701AC
6273 #define _DSPAGAMC                               0x701E0
6274
6275 #define DSPCNTR(plane)          _MMIO_PIPE2(plane, _DSPACNTR)
6276 #define DSPADDR(plane)          _MMIO_PIPE2(plane, _DSPAADDR)
6277 #define DSPSTRIDE(plane)        _MMIO_PIPE2(plane, _DSPASTRIDE)
6278 #define DSPPOS(plane)           _MMIO_PIPE2(plane, _DSPAPOS)
6279 #define DSPSIZE(plane)          _MMIO_PIPE2(plane, _DSPASIZE)
6280 #define DSPSURF(plane)          _MMIO_PIPE2(plane, _DSPASURF)
6281 #define DSPTILEOFF(plane)       _MMIO_PIPE2(plane, _DSPATILEOFF)
6282 #define DSPLINOFF(plane)        DSPADDR(plane)
6283 #define DSPOFFSET(plane)        _MMIO_PIPE2(plane, _DSPAOFFSET)
6284 #define DSPSURFLIVE(plane)      _MMIO_PIPE2(plane, _DSPASURFLIVE)
6285 #define DSPGAMC(plane, i)       _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
6286
6287 /* CHV pipe B blender and primary plane */
6288 #define _CHV_BLEND_A            0x60a00
6289 #define   CHV_BLEND_LEGACY              (0 << 30)
6290 #define   CHV_BLEND_ANDROID             (1 << 30)
6291 #define   CHV_BLEND_MPO                 (2 << 30)
6292 #define   CHV_BLEND_MASK                (3 << 30)
6293 #define _CHV_CANVAS_A           0x60a04
6294 #define _PRIMPOS_A              0x60a08
6295 #define _PRIMSIZE_A             0x60a0c
6296 #define _PRIMCNSTALPHA_A        0x60a10
6297 #define   PRIM_CONST_ALPHA_ENABLE       (1 << 31)
6298
6299 #define CHV_BLEND(pipe)         _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6300 #define CHV_CANVAS(pipe)        _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6301 #define PRIMPOS(plane)          _MMIO_TRANS2(plane, _PRIMPOS_A)
6302 #define PRIMSIZE(plane)         _MMIO_TRANS2(plane, _PRIMSIZE_A)
6303 #define PRIMCNSTALPHA(plane)    _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6304
6305 /* Display/Sprite base address macros */
6306 #define DISP_BASEADDR_MASK      (0xfffff000)
6307 #define I915_LO_DISPBASE(val)   ((val) & ~DISP_BASEADDR_MASK)
6308 #define I915_HI_DISPBASE(val)   ((val) & DISP_BASEADDR_MASK)
6309
6310 /*
6311  * VBIOS flags
6312  * gen2:
6313  * [00:06] alm,mgm
6314  * [10:16] all
6315  * [30:32] alm,mgm
6316  * gen3+:
6317  * [00:0f] all
6318  * [10:1f] all
6319  * [30:32] all
6320  */
6321 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6322 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6323 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6324 #define SWF_ILK(i)      _MMIO(0x4F000 + (i) * 4)
6325
6326 /* Pipe B */
6327 #define _PIPEBDSL               (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6328 #define _PIPEBCONF              (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6329 #define _PIPEBSTAT              (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6330 #define _PIPEBFRAMEHIGH         0x71040
6331 #define _PIPEBFRAMEPIXEL        0x71044
6332 #define _PIPEB_FRMCOUNT_G4X     (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6333 #define _PIPEB_FLIPCOUNT_G4X    (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6334
6335
6336 /* Display B control */
6337 #define _DSPBCNTR               (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6338 #define   DISPPLANE_ALPHA_TRANS_ENABLE          (1 << 15)
6339 #define   DISPPLANE_ALPHA_TRANS_DISABLE         0
6340 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY        0
6341 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY        (1)
6342 #define _DSPBADDR               (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6343 #define _DSPBSTRIDE             (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6344 #define _DSPBPOS                (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6345 #define _DSPBSIZE               (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6346 #define _DSPBSURF               (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6347 #define _DSPBTILEOFF            (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6348 #define _DSPBOFFSET             (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6349 #define _DSPBSURFLIVE           (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6350
6351 /* ICL DSI 0 and 1 */
6352 #define _PIPEDSI0CONF           0x7b008
6353 #define _PIPEDSI1CONF           0x7b808
6354
6355 /* Sprite A control */
6356 #define _DVSACNTR               0x72180
6357 #define   DVS_ENABLE            (1 << 31)
6358 #define   DVS_GAMMA_ENABLE      (1 << 30)
6359 #define   DVS_YUV_RANGE_CORRECTION_DISABLE      (1 << 27)
6360 #define   DVS_PIXFORMAT_MASK    (3 << 25)
6361 #define   DVS_FORMAT_YUV422     (0 << 25)
6362 #define   DVS_FORMAT_RGBX101010 (1 << 25)
6363 #define   DVS_FORMAT_RGBX888    (2 << 25)
6364 #define   DVS_FORMAT_RGBX161616 (3 << 25)
6365 #define   DVS_PIPE_CSC_ENABLE   (1 << 24)
6366 #define   DVS_SOURCE_KEY        (1 << 22)
6367 #define   DVS_RGB_ORDER_XBGR    (1 << 20)
6368 #define   DVS_YUV_FORMAT_BT709  (1 << 18)
6369 #define   DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6370 #define   DVS_YUV_ORDER_YUYV    (0 << 16)
6371 #define   DVS_YUV_ORDER_UYVY    (1 << 16)
6372 #define   DVS_YUV_ORDER_YVYU    (2 << 16)
6373 #define   DVS_YUV_ORDER_VYUY    (3 << 16)
6374 #define   DVS_ROTATE_180        (1 << 15)
6375 #define   DVS_DEST_KEY          (1 << 2)
6376 #define   DVS_TRICKLE_FEED_DISABLE (1 << 14)
6377 #define   DVS_TILED             (1 << 10)
6378 #define _DVSALINOFF             0x72184
6379 #define _DVSASTRIDE             0x72188
6380 #define _DVSAPOS                0x7218c
6381 #define _DVSASIZE               0x72190
6382 #define _DVSAKEYVAL             0x72194
6383 #define _DVSAKEYMSK             0x72198
6384 #define _DVSASURF               0x7219c
6385 #define _DVSAKEYMAXVAL          0x721a0
6386 #define _DVSATILEOFF            0x721a4
6387 #define _DVSASURFLIVE           0x721ac
6388 #define _DVSAGAMC_G4X           0x721e0 /* g4x */
6389 #define _DVSASCALE              0x72204
6390 #define   DVS_SCALE_ENABLE      (1 << 31)
6391 #define   DVS_FILTER_MASK       (3 << 29)
6392 #define   DVS_FILTER_MEDIUM     (0 << 29)
6393 #define   DVS_FILTER_ENHANCING  (1 << 29)
6394 #define   DVS_FILTER_SOFTENING  (2 << 29)
6395 #define   DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6396 #define   DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6397 #define _DVSAGAMC_ILK           0x72300 /* ilk/snb */
6398 #define _DVSAGAMCMAX_ILK        0x72340 /* ilk/snb */
6399
6400 #define _DVSBCNTR               0x73180
6401 #define _DVSBLINOFF             0x73184
6402 #define _DVSBSTRIDE             0x73188
6403 #define _DVSBPOS                0x7318c
6404 #define _DVSBSIZE               0x73190
6405 #define _DVSBKEYVAL             0x73194
6406 #define _DVSBKEYMSK             0x73198
6407 #define _DVSBSURF               0x7319c
6408 #define _DVSBKEYMAXVAL          0x731a0
6409 #define _DVSBTILEOFF            0x731a4
6410 #define _DVSBSURFLIVE           0x731ac
6411 #define _DVSBGAMC_G4X           0x731e0 /* g4x */
6412 #define _DVSBSCALE              0x73204
6413 #define _DVSBGAMC_ILK           0x73300 /* ilk/snb */
6414 #define _DVSBGAMCMAX_ILK        0x73340 /* ilk/snb */
6415
6416 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6417 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6418 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6419 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6420 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6421 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6422 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6423 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6424 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6425 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6426 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6427 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6428 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
6429 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
6430 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
6431
6432 #define _SPRA_CTL               0x70280
6433 #define   SPRITE_ENABLE                 (1 << 31)
6434 #define   SPRITE_GAMMA_ENABLE           (1 << 30)
6435 #define   SPRITE_YUV_RANGE_CORRECTION_DISABLE   (1 << 28)
6436 #define   SPRITE_PIXFORMAT_MASK         (7 << 25)
6437 #define   SPRITE_FORMAT_YUV422          (0 << 25)
6438 #define   SPRITE_FORMAT_RGBX101010      (1 << 25)
6439 #define   SPRITE_FORMAT_RGBX888         (2 << 25)
6440 #define   SPRITE_FORMAT_RGBX161616      (3 << 25)
6441 #define   SPRITE_FORMAT_YUV444          (4 << 25)
6442 #define   SPRITE_FORMAT_XR_BGR101010    (5 << 25) /* Extended range */
6443 #define   SPRITE_PIPE_CSC_ENABLE        (1 << 24)
6444 #define   SPRITE_SOURCE_KEY             (1 << 22)
6445 #define   SPRITE_RGB_ORDER_RGBX         (1 << 20) /* only for 888 and 161616 */
6446 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
6447 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709    (1 << 18) /* 0 is BT601 */
6448 #define   SPRITE_YUV_BYTE_ORDER_MASK    (3 << 16)
6449 #define   SPRITE_YUV_ORDER_YUYV         (0 << 16)
6450 #define   SPRITE_YUV_ORDER_UYVY         (1 << 16)
6451 #define   SPRITE_YUV_ORDER_YVYU         (2 << 16)
6452 #define   SPRITE_YUV_ORDER_VYUY         (3 << 16)
6453 #define   SPRITE_ROTATE_180             (1 << 15)
6454 #define   SPRITE_TRICKLE_FEED_DISABLE   (1 << 14)
6455 #define   SPRITE_INT_GAMMA_DISABLE      (1 << 13)
6456 #define   SPRITE_TILED                  (1 << 10)
6457 #define   SPRITE_DEST_KEY               (1 << 2)
6458 #define _SPRA_LINOFF            0x70284
6459 #define _SPRA_STRIDE            0x70288
6460 #define _SPRA_POS               0x7028c
6461 #define _SPRA_SIZE              0x70290
6462 #define _SPRA_KEYVAL            0x70294
6463 #define _SPRA_KEYMSK            0x70298
6464 #define _SPRA_SURF              0x7029c
6465 #define _SPRA_KEYMAX            0x702a0
6466 #define _SPRA_TILEOFF           0x702a4
6467 #define _SPRA_OFFSET            0x702a4
6468 #define _SPRA_SURFLIVE          0x702ac
6469 #define _SPRA_SCALE             0x70304
6470 #define   SPRITE_SCALE_ENABLE   (1 << 31)
6471 #define   SPRITE_FILTER_MASK    (3 << 29)
6472 #define   SPRITE_FILTER_MEDIUM  (0 << 29)
6473 #define   SPRITE_FILTER_ENHANCING       (1 << 29)
6474 #define   SPRITE_FILTER_SOFTENING       (2 << 29)
6475 #define   SPRITE_VERTICAL_OFFSET_HALF   (1 << 28) /* must be enabled below */
6476 #define   SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
6477 #define _SPRA_GAMC              0x70400
6478 #define _SPRA_GAMC16            0x70440
6479 #define _SPRA_GAMC17            0x7044c
6480
6481 #define _SPRB_CTL               0x71280
6482 #define _SPRB_LINOFF            0x71284
6483 #define _SPRB_STRIDE            0x71288
6484 #define _SPRB_POS               0x7128c
6485 #define _SPRB_SIZE              0x71290
6486 #define _SPRB_KEYVAL            0x71294
6487 #define _SPRB_KEYMSK            0x71298
6488 #define _SPRB_SURF              0x7129c
6489 #define _SPRB_KEYMAX            0x712a0
6490 #define _SPRB_TILEOFF           0x712a4
6491 #define _SPRB_OFFSET            0x712a4
6492 #define _SPRB_SURFLIVE          0x712ac
6493 #define _SPRB_SCALE             0x71304
6494 #define _SPRB_GAMC              0x71400
6495 #define _SPRB_GAMC16            0x71440
6496 #define _SPRB_GAMC17            0x7144c
6497
6498 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6499 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6500 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6501 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6502 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6503 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6504 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6505 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6506 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6507 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6508 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6509 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6510 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
6511 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
6512 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
6513 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6514
6515 #define _SPACNTR                (VLV_DISPLAY_BASE + 0x72180)
6516 #define   SP_ENABLE                     (1 << 31)
6517 #define   SP_GAMMA_ENABLE               (1 << 30)
6518 #define   SP_PIXFORMAT_MASK             (0xf << 26)
6519 #define   SP_FORMAT_YUV422              (0 << 26)
6520 #define   SP_FORMAT_BGR565              (5 << 26)
6521 #define   SP_FORMAT_BGRX8888            (6 << 26)
6522 #define   SP_FORMAT_BGRA8888            (7 << 26)
6523 #define   SP_FORMAT_RGBX1010102         (8 << 26)
6524 #define   SP_FORMAT_RGBA1010102         (9 << 26)
6525 #define   SP_FORMAT_RGBX8888            (0xe << 26)
6526 #define   SP_FORMAT_RGBA8888            (0xf << 26)
6527 #define   SP_ALPHA_PREMULTIPLY          (1 << 23) /* CHV pipe B */
6528 #define   SP_SOURCE_KEY                 (1 << 22)
6529 #define   SP_YUV_FORMAT_BT709           (1 << 18)
6530 #define   SP_YUV_BYTE_ORDER_MASK        (3 << 16)
6531 #define   SP_YUV_ORDER_YUYV             (0 << 16)
6532 #define   SP_YUV_ORDER_UYVY             (1 << 16)
6533 #define   SP_YUV_ORDER_YVYU             (2 << 16)
6534 #define   SP_YUV_ORDER_VYUY             (3 << 16)
6535 #define   SP_ROTATE_180                 (1 << 15)
6536 #define   SP_TILED                      (1 << 10)
6537 #define   SP_MIRROR                     (1 << 8) /* CHV pipe B */
6538 #define _SPALINOFF              (VLV_DISPLAY_BASE + 0x72184)
6539 #define _SPASTRIDE              (VLV_DISPLAY_BASE + 0x72188)
6540 #define _SPAPOS                 (VLV_DISPLAY_BASE + 0x7218c)
6541 #define _SPASIZE                (VLV_DISPLAY_BASE + 0x72190)
6542 #define _SPAKEYMINVAL           (VLV_DISPLAY_BASE + 0x72194)
6543 #define _SPAKEYMSK              (VLV_DISPLAY_BASE + 0x72198)
6544 #define _SPASURF                (VLV_DISPLAY_BASE + 0x7219c)
6545 #define _SPAKEYMAXVAL           (VLV_DISPLAY_BASE + 0x721a0)
6546 #define _SPATILEOFF             (VLV_DISPLAY_BASE + 0x721a4)
6547 #define _SPACONSTALPHA          (VLV_DISPLAY_BASE + 0x721a8)
6548 #define   SP_CONST_ALPHA_ENABLE         (1 << 31)
6549 #define _SPACLRC0               (VLV_DISPLAY_BASE + 0x721d0)
6550 #define   SP_CONTRAST(x)                ((x) << 18) /* u3.6 */
6551 #define   SP_BRIGHTNESS(x)              ((x) & 0xff) /* s8 */
6552 #define _SPACLRC1               (VLV_DISPLAY_BASE + 0x721d4)
6553 #define   SP_SH_SIN(x)                  (((x) & 0x7ff) << 16) /* s4.7 */
6554 #define   SP_SH_COS(x)                  (x) /* u3.7 */
6555 #define _SPAGAMC                (VLV_DISPLAY_BASE + 0x721e0)
6556
6557 #define _SPBCNTR                (VLV_DISPLAY_BASE + 0x72280)
6558 #define _SPBLINOFF              (VLV_DISPLAY_BASE + 0x72284)
6559 #define _SPBSTRIDE              (VLV_DISPLAY_BASE + 0x72288)
6560 #define _SPBPOS                 (VLV_DISPLAY_BASE + 0x7228c)
6561 #define _SPBSIZE                (VLV_DISPLAY_BASE + 0x72290)
6562 #define _SPBKEYMINVAL           (VLV_DISPLAY_BASE + 0x72294)
6563 #define _SPBKEYMSK              (VLV_DISPLAY_BASE + 0x72298)
6564 #define _SPBSURF                (VLV_DISPLAY_BASE + 0x7229c)
6565 #define _SPBKEYMAXVAL           (VLV_DISPLAY_BASE + 0x722a0)
6566 #define _SPBTILEOFF             (VLV_DISPLAY_BASE + 0x722a4)
6567 #define _SPBCONSTALPHA          (VLV_DISPLAY_BASE + 0x722a8)
6568 #define _SPBCLRC0               (VLV_DISPLAY_BASE + 0x722d0)
6569 #define _SPBCLRC1               (VLV_DISPLAY_BASE + 0x722d4)
6570 #define _SPBGAMC                (VLV_DISPLAY_BASE + 0x722e0)
6571
6572 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6573         _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6574 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6575         _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
6576
6577 #define SPCNTR(pipe, plane_id)          _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6578 #define SPLINOFF(pipe, plane_id)        _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6579 #define SPSTRIDE(pipe, plane_id)        _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6580 #define SPPOS(pipe, plane_id)           _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6581 #define SPSIZE(pipe, plane_id)          _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6582 #define SPKEYMINVAL(pipe, plane_id)     _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6583 #define SPKEYMSK(pipe, plane_id)        _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6584 #define SPSURF(pipe, plane_id)          _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6585 #define SPKEYMAXVAL(pipe, plane_id)     _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6586 #define SPTILEOFF(pipe, plane_id)       _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6587 #define SPCONSTALPHA(pipe, plane_id)    _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6588 #define SPCLRC0(pipe, plane_id)         _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6589 #define SPCLRC1(pipe, plane_id)         _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6590 #define SPGAMC(pipe, plane_id, i)       _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
6591
6592 /*
6593  * CHV pipe B sprite CSC
6594  *
6595  * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
6596  * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6597  * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
6598  */
6599 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6600         _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6601
6602 #define SPCSCYGOFF(plane_id)    _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6603 #define SPCSCCBOFF(plane_id)    _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6604 #define SPCSCCROFF(plane_id)    _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6605 #define  SPCSC_OOFF(x)          (((x) & 0x7ff) << 16) /* s11 */
6606 #define  SPCSC_IOFF(x)          (((x) & 0x7ff) << 0) /* s11 */
6607
6608 #define SPCSCC01(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6609 #define SPCSCC23(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6610 #define SPCSCC45(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6611 #define SPCSCC67(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6612 #define SPCSCC8(plane_id)       _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6613 #define  SPCSC_C1(x)            (((x) & 0x7fff) << 16) /* s3.12 */
6614 #define  SPCSC_C0(x)            (((x) & 0x7fff) << 0) /* s3.12 */
6615
6616 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6617 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6618 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6619 #define  SPCSC_IMAX(x)          (((x) & 0x7ff) << 16) /* s11 */
6620 #define  SPCSC_IMIN(x)          (((x) & 0x7ff) << 0) /* s11 */
6621
6622 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6623 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6624 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6625 #define  SPCSC_OMAX(x)          ((x) << 16) /* u10 */
6626 #define  SPCSC_OMIN(x)          ((x) << 0) /* u10 */
6627
6628 /* Skylake plane registers */
6629
6630 #define _PLANE_CTL_1_A                          0x70180
6631 #define _PLANE_CTL_2_A                          0x70280
6632 #define _PLANE_CTL_3_A                          0x70380
6633 #define   PLANE_CTL_ENABLE                      (1 << 31)
6634 #define   PLANE_CTL_PIPE_GAMMA_ENABLE           (1 << 30)   /* Pre-GLK */
6635 #define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE        (1 << 28)
6636 /*
6637  * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6638  * expanded to include bit 23 as well. However, the shift-24 based values
6639  * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6640  */
6641 #define   PLANE_CTL_FORMAT_MASK                 (0xf << 24)
6642 #define   PLANE_CTL_FORMAT_YUV422               (0 << 24)
6643 #define   PLANE_CTL_FORMAT_NV12                 (1 << 24)
6644 #define   PLANE_CTL_FORMAT_XRGB_2101010         (2 << 24)
6645 #define   PLANE_CTL_FORMAT_P010                 (3 << 24)
6646 #define   PLANE_CTL_FORMAT_XRGB_8888            (4 << 24)
6647 #define   PLANE_CTL_FORMAT_P012                 (5 << 24)
6648 #define   PLANE_CTL_FORMAT_XRGB_16161616F       (6 << 24)
6649 #define   PLANE_CTL_FORMAT_P016                 (7 << 24)
6650 #define   PLANE_CTL_FORMAT_AYUV                 (8 << 24)
6651 #define   PLANE_CTL_FORMAT_INDEXED              (12 << 24)
6652 #define   PLANE_CTL_FORMAT_RGB_565              (14 << 24)
6653 #define   ICL_PLANE_CTL_FORMAT_MASK             (0x1f << 23)
6654 #define   PLANE_CTL_PIPE_CSC_ENABLE             (1 << 23) /* Pre-GLK */
6655 #define   PLANE_CTL_FORMAT_Y210                 (1 << 23)
6656 #define   PLANE_CTL_FORMAT_Y212                 (3 << 23)
6657 #define   PLANE_CTL_FORMAT_Y216                 (5 << 23)
6658 #define   PLANE_CTL_FORMAT_Y410                 (7 << 23)
6659 #define   PLANE_CTL_FORMAT_Y412                 (9 << 23)
6660 #define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
6661 #define   PLANE_CTL_KEY_ENABLE_MASK             (0x3 << 21)
6662 #define   PLANE_CTL_KEY_ENABLE_SOURCE           (1 << 21)
6663 #define   PLANE_CTL_KEY_ENABLE_DESTINATION      (2 << 21)
6664 #define   PLANE_CTL_ORDER_BGRX                  (0 << 20)
6665 #define   PLANE_CTL_ORDER_RGBX                  (1 << 20)
6666 #define   PLANE_CTL_YUV420_Y_PLANE              (1 << 19)
6667 #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6668 #define   PLANE_CTL_YUV422_ORDER_MASK           (0x3 << 16)
6669 #define   PLANE_CTL_YUV422_YUYV                 (0 << 16)
6670 #define   PLANE_CTL_YUV422_UYVY                 (1 << 16)
6671 #define   PLANE_CTL_YUV422_YVYU                 (2 << 16)
6672 #define   PLANE_CTL_YUV422_VYUY                 (3 << 16)
6673 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
6674 #define   PLANE_CTL_TRICKLE_FEED_DISABLE        (1 << 14)
6675 #define   PLANE_CTL_PLANE_GAMMA_DISABLE         (1 << 13) /* Pre-GLK */
6676 #define   PLANE_CTL_TILED_MASK                  (0x7 << 10)
6677 #define   PLANE_CTL_TILED_LINEAR                (0 << 10)
6678 #define   PLANE_CTL_TILED_X                     (1 << 10)
6679 #define   PLANE_CTL_TILED_Y                     (4 << 10)
6680 #define   PLANE_CTL_TILED_YF                    (5 << 10)
6681 #define   PLANE_CTL_FLIP_HORIZONTAL             (1 << 8)
6682 #define   PLANE_CTL_ALPHA_MASK                  (0x3 << 4) /* Pre-GLK */
6683 #define   PLANE_CTL_ALPHA_DISABLE               (0 << 4)
6684 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY        (2 << 4)
6685 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY        (3 << 4)
6686 #define   PLANE_CTL_ROTATE_MASK                 0x3
6687 #define   PLANE_CTL_ROTATE_0                    0x0
6688 #define   PLANE_CTL_ROTATE_90                   0x1
6689 #define   PLANE_CTL_ROTATE_180                  0x2
6690 #define   PLANE_CTL_ROTATE_270                  0x3
6691 #define _PLANE_STRIDE_1_A                       0x70188
6692 #define _PLANE_STRIDE_2_A                       0x70288
6693 #define _PLANE_STRIDE_3_A                       0x70388
6694 #define _PLANE_POS_1_A                          0x7018c
6695 #define _PLANE_POS_2_A                          0x7028c
6696 #define _PLANE_POS_3_A                          0x7038c
6697 #define _PLANE_SIZE_1_A                         0x70190
6698 #define _PLANE_SIZE_2_A                         0x70290
6699 #define _PLANE_SIZE_3_A                         0x70390
6700 #define _PLANE_SURF_1_A                         0x7019c
6701 #define _PLANE_SURF_2_A                         0x7029c
6702 #define _PLANE_SURF_3_A                         0x7039c
6703 #define _PLANE_OFFSET_1_A                       0x701a4
6704 #define _PLANE_OFFSET_2_A                       0x702a4
6705 #define _PLANE_OFFSET_3_A                       0x703a4
6706 #define _PLANE_KEYVAL_1_A                       0x70194
6707 #define _PLANE_KEYVAL_2_A                       0x70294
6708 #define _PLANE_KEYMSK_1_A                       0x70198
6709 #define _PLANE_KEYMSK_2_A                       0x70298
6710 #define  PLANE_KEYMSK_ALPHA_ENABLE              (1 << 31)
6711 #define _PLANE_KEYMAX_1_A                       0x701a0
6712 #define _PLANE_KEYMAX_2_A                       0x702a0
6713 #define  PLANE_KEYMAX_ALPHA(a)                  ((a) << 24)
6714 #define _PLANE_AUX_DIST_1_A                     0x701c0
6715 #define _PLANE_AUX_DIST_2_A                     0x702c0
6716 #define _PLANE_AUX_OFFSET_1_A                   0x701c4
6717 #define _PLANE_AUX_OFFSET_2_A                   0x702c4
6718 #define _PLANE_CUS_CTL_1_A                      0x701c8
6719 #define _PLANE_CUS_CTL_2_A                      0x702c8
6720 #define  PLANE_CUS_ENABLE                       (1 << 31)
6721 #define  PLANE_CUS_PLANE_6                      (0 << 30)
6722 #define  PLANE_CUS_PLANE_7                      (1 << 30)
6723 #define  PLANE_CUS_HPHASE_SIGN_NEGATIVE         (1 << 19)
6724 #define  PLANE_CUS_HPHASE_0                     (0 << 16)
6725 #define  PLANE_CUS_HPHASE_0_25                  (1 << 16)
6726 #define  PLANE_CUS_HPHASE_0_5                   (2 << 16)
6727 #define  PLANE_CUS_VPHASE_SIGN_NEGATIVE         (1 << 15)
6728 #define  PLANE_CUS_VPHASE_0                     (0 << 12)
6729 #define  PLANE_CUS_VPHASE_0_25                  (1 << 12)
6730 #define  PLANE_CUS_VPHASE_0_5                   (2 << 12)
6731 #define _PLANE_COLOR_CTL_1_A                    0x701CC /* GLK+ */
6732 #define _PLANE_COLOR_CTL_2_A                    0x702CC /* GLK+ */
6733 #define _PLANE_COLOR_CTL_3_A                    0x703CC /* GLK+ */
6734 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE         (1 << 30) /* Pre-ICL */
6735 #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE      (1 << 28)
6736 #define   PLANE_COLOR_INPUT_CSC_ENABLE          (1 << 20) /* ICL+ */
6737 #define   PLANE_COLOR_PIPE_CSC_ENABLE           (1 << 23) /* Pre-ICL */
6738 #define   PLANE_COLOR_CSC_MODE_BYPASS                   (0 << 17)
6739 #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709         (1 << 17)
6740 #define   PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709         (2 << 17)
6741 #define   PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020       (3 << 17)
6742 #define   PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020        (4 << 17)
6743 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE       (1 << 13)
6744 #define   PLANE_COLOR_ALPHA_MASK                (0x3 << 4)
6745 #define   PLANE_COLOR_ALPHA_DISABLE             (0 << 4)
6746 #define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY      (2 << 4)
6747 #define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY      (3 << 4)
6748 #define _PLANE_BUF_CFG_1_A                      0x7027c
6749 #define _PLANE_BUF_CFG_2_A                      0x7037c
6750 #define _PLANE_NV12_BUF_CFG_1_A         0x70278
6751 #define _PLANE_NV12_BUF_CFG_2_A         0x70378
6752
6753 /* Input CSC Register Definitions */
6754 #define _PLANE_INPUT_CSC_RY_GY_1_A      0x701E0
6755 #define _PLANE_INPUT_CSC_RY_GY_2_A      0x702E0
6756
6757 #define _PLANE_INPUT_CSC_RY_GY_1_B      0x711E0
6758 #define _PLANE_INPUT_CSC_RY_GY_2_B      0x712E0
6759
6760 #define _PLANE_INPUT_CSC_RY_GY_1(pipe)  \
6761         _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
6762              _PLANE_INPUT_CSC_RY_GY_1_B)
6763 #define _PLANE_INPUT_CSC_RY_GY_2(pipe)  \
6764         _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
6765              _PLANE_INPUT_CSC_RY_GY_2_B)
6766
6767 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index)       \
6768         _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
6769                     _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
6770
6771 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A          0x701F8
6772 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A          0x702F8
6773
6774 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B          0x711F8
6775 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B          0x712F8
6776
6777 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)      \
6778         _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
6779              _PLANE_INPUT_CSC_PREOFF_HI_1_B)
6780 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)      \
6781         _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
6782              _PLANE_INPUT_CSC_PREOFF_HI_2_B)
6783 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index)      \
6784         _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
6785                     _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
6786
6787 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A         0x70204
6788 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A         0x70304
6789
6790 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B         0x71204
6791 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B         0x71304
6792
6793 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)     \
6794         _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
6795              _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
6796 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)     \
6797         _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
6798              _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
6799 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)     \
6800         _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
6801                     _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
6802
6803 #define _PLANE_CTL_1_B                          0x71180
6804 #define _PLANE_CTL_2_B                          0x71280
6805 #define _PLANE_CTL_3_B                          0x71380
6806 #define _PLANE_CTL_1(pipe)      _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6807 #define _PLANE_CTL_2(pipe)      _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6808 #define _PLANE_CTL_3(pipe)      _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6809 #define PLANE_CTL(pipe, plane)  \
6810         _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6811
6812 #define _PLANE_STRIDE_1_B                       0x71188
6813 #define _PLANE_STRIDE_2_B                       0x71288
6814 #define _PLANE_STRIDE_3_B                       0x71388
6815 #define _PLANE_STRIDE_1(pipe)   \
6816         _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6817 #define _PLANE_STRIDE_2(pipe)   \
6818         _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6819 #define _PLANE_STRIDE_3(pipe)   \
6820         _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6821 #define PLANE_STRIDE(pipe, plane)       \
6822         _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6823
6824 #define _PLANE_POS_1_B                          0x7118c
6825 #define _PLANE_POS_2_B                          0x7128c
6826 #define _PLANE_POS_3_B                          0x7138c
6827 #define _PLANE_POS_1(pipe)      _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6828 #define _PLANE_POS_2(pipe)      _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6829 #define _PLANE_POS_3(pipe)      _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6830 #define PLANE_POS(pipe, plane)  \
6831         _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6832
6833 #define _PLANE_SIZE_1_B                         0x71190
6834 #define _PLANE_SIZE_2_B                         0x71290
6835 #define _PLANE_SIZE_3_B                         0x71390
6836 #define _PLANE_SIZE_1(pipe)     _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6837 #define _PLANE_SIZE_2(pipe)     _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6838 #define _PLANE_SIZE_3(pipe)     _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6839 #define PLANE_SIZE(pipe, plane) \
6840         _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6841
6842 #define _PLANE_SURF_1_B                         0x7119c
6843 #define _PLANE_SURF_2_B                         0x7129c
6844 #define _PLANE_SURF_3_B                         0x7139c
6845 #define _PLANE_SURF_1(pipe)     _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6846 #define _PLANE_SURF_2(pipe)     _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6847 #define _PLANE_SURF_3(pipe)     _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6848 #define PLANE_SURF(pipe, plane) \
6849         _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6850
6851 #define _PLANE_OFFSET_1_B                       0x711a4
6852 #define _PLANE_OFFSET_2_B                       0x712a4
6853 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6854 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6855 #define PLANE_OFFSET(pipe, plane)       \
6856         _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6857
6858 #define _PLANE_KEYVAL_1_B                       0x71194
6859 #define _PLANE_KEYVAL_2_B                       0x71294
6860 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6861 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6862 #define PLANE_KEYVAL(pipe, plane)       \
6863         _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6864
6865 #define _PLANE_KEYMSK_1_B                       0x71198
6866 #define _PLANE_KEYMSK_2_B                       0x71298
6867 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6868 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6869 #define PLANE_KEYMSK(pipe, plane)       \
6870         _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6871
6872 #define _PLANE_KEYMAX_1_B                       0x711a0
6873 #define _PLANE_KEYMAX_2_B                       0x712a0
6874 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6875 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6876 #define PLANE_KEYMAX(pipe, plane)       \
6877         _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6878
6879 #define _PLANE_BUF_CFG_1_B                      0x7127c
6880 #define _PLANE_BUF_CFG_2_B                      0x7137c
6881 #define  DDB_ENTRY_MASK                         0x7FF /* skl+: 10 bits, icl+ 11 bits */
6882 #define  DDB_ENTRY_END_SHIFT                    16
6883 #define _PLANE_BUF_CFG_1(pipe)  \
6884         _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6885 #define _PLANE_BUF_CFG_2(pipe)  \
6886         _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6887 #define PLANE_BUF_CFG(pipe, plane)      \
6888         _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
6889
6890 #define _PLANE_NV12_BUF_CFG_1_B         0x71278
6891 #define _PLANE_NV12_BUF_CFG_2_B         0x71378
6892 #define _PLANE_NV12_BUF_CFG_1(pipe)     \
6893         _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6894 #define _PLANE_NV12_BUF_CFG_2(pipe)     \
6895         _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6896 #define PLANE_NV12_BUF_CFG(pipe, plane) \
6897         _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6898
6899 #define _PLANE_AUX_DIST_1_B             0x711c0
6900 #define _PLANE_AUX_DIST_2_B             0x712c0
6901 #define _PLANE_AUX_DIST_1(pipe) \
6902                         _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6903 #define _PLANE_AUX_DIST_2(pipe) \
6904                         _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6905 #define PLANE_AUX_DIST(pipe, plane)     \
6906         _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6907
6908 #define _PLANE_AUX_OFFSET_1_B           0x711c4
6909 #define _PLANE_AUX_OFFSET_2_B           0x712c4
6910 #define _PLANE_AUX_OFFSET_1(pipe)       \
6911                 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6912 #define _PLANE_AUX_OFFSET_2(pipe)       \
6913                 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6914 #define PLANE_AUX_OFFSET(pipe, plane)   \
6915         _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6916
6917 #define _PLANE_CUS_CTL_1_B              0x711c8
6918 #define _PLANE_CUS_CTL_2_B              0x712c8
6919 #define _PLANE_CUS_CTL_1(pipe)       \
6920                 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
6921 #define _PLANE_CUS_CTL_2(pipe)       \
6922                 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
6923 #define PLANE_CUS_CTL(pipe, plane)   \
6924         _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
6925
6926 #define _PLANE_COLOR_CTL_1_B                    0x711CC
6927 #define _PLANE_COLOR_CTL_2_B                    0x712CC
6928 #define _PLANE_COLOR_CTL_3_B                    0x713CC
6929 #define _PLANE_COLOR_CTL_1(pipe)        \
6930         _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6931 #define _PLANE_COLOR_CTL_2(pipe)        \
6932         _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6933 #define PLANE_COLOR_CTL(pipe, plane)    \
6934         _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6935
6936 #/* SKL new cursor registers */
6937 #define _CUR_BUF_CFG_A                          0x7017c
6938 #define _CUR_BUF_CFG_B                          0x7117c
6939 #define CUR_BUF_CFG(pipe)       _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
6940
6941 /* VBIOS regs */
6942 #define VGACNTRL                _MMIO(0x71400)
6943 # define VGA_DISP_DISABLE                       (1 << 31)
6944 # define VGA_2X_MODE                            (1 << 30)
6945 # define VGA_PIPE_B_SELECT                      (1 << 29)
6946
6947 #define VLV_VGACNTRL            _MMIO(VLV_DISPLAY_BASE + 0x71400)
6948
6949 /* Ironlake */
6950
6951 #define CPU_VGACNTRL    _MMIO(0x41000)
6952
6953 #define DIGITAL_PORT_HOTPLUG_CNTRL      _MMIO(0x44030)
6954 #define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
6955 #define  DIGITAL_PORTA_PULSE_DURATION_2ms       (0 << 2) /* pre-HSW */
6956 #define  DIGITAL_PORTA_PULSE_DURATION_4_5ms     (1 << 2) /* pre-HSW */
6957 #define  DIGITAL_PORTA_PULSE_DURATION_6ms       (2 << 2) /* pre-HSW */
6958 #define  DIGITAL_PORTA_PULSE_DURATION_100ms     (3 << 2) /* pre-HSW */
6959 #define  DIGITAL_PORTA_PULSE_DURATION_MASK      (3 << 2) /* pre-HSW */
6960 #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK      (3 << 0)
6961 #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT        (0 << 0)
6962 #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT     (1 << 0)
6963 #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT      (2 << 0)
6964
6965 /* refresh rate hardware control */
6966 #define RR_HW_CTL       _MMIO(0x45300)
6967 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
6968 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
6969
6970 #define FDI_PLL_BIOS_0  _MMIO(0x46000)
6971 #define  FDI_PLL_FB_CLOCK_MASK  0xff
6972 #define FDI_PLL_BIOS_1  _MMIO(0x46004)
6973 #define FDI_PLL_BIOS_2  _MMIO(0x46008)
6974 #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
6975 #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
6976 #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
6977
6978 #define PCH_3DCGDIS0            _MMIO(0x46020)
6979 # define MARIUNIT_CLOCK_GATE_DISABLE            (1 << 18)
6980 # define SVSMUNIT_CLOCK_GATE_DISABLE            (1 << 1)
6981
6982 #define PCH_3DCGDIS1            _MMIO(0x46024)
6983 # define VFMUNIT_CLOCK_GATE_DISABLE             (1 << 11)
6984
6985 #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
6986 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1 << 24)
6987 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
6988 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
6989
6990
6991 #define _PIPEA_DATA_M1          0x60030
6992 #define  PIPE_DATA_M1_OFFSET    0
6993 #define _PIPEA_DATA_N1          0x60034
6994 #define  PIPE_DATA_N1_OFFSET    0
6995
6996 #define _PIPEA_DATA_M2          0x60038
6997 #define  PIPE_DATA_M2_OFFSET    0
6998 #define _PIPEA_DATA_N2          0x6003c
6999 #define  PIPE_DATA_N2_OFFSET    0
7000
7001 #define _PIPEA_LINK_M1          0x60040
7002 #define  PIPE_LINK_M1_OFFSET    0
7003 #define _PIPEA_LINK_N1          0x60044
7004 #define  PIPE_LINK_N1_OFFSET    0
7005
7006 #define _PIPEA_LINK_M2          0x60048
7007 #define  PIPE_LINK_M2_OFFSET    0
7008 #define _PIPEA_LINK_N2          0x6004c
7009 #define  PIPE_LINK_N2_OFFSET    0
7010
7011 /* PIPEB timing regs are same start from 0x61000 */
7012
7013 #define _PIPEB_DATA_M1          0x61030
7014 #define _PIPEB_DATA_N1          0x61034
7015 #define _PIPEB_DATA_M2          0x61038
7016 #define _PIPEB_DATA_N2          0x6103c
7017 #define _PIPEB_LINK_M1          0x61040
7018 #define _PIPEB_LINK_N1          0x61044
7019 #define _PIPEB_LINK_M2          0x61048
7020 #define _PIPEB_LINK_N2          0x6104c
7021
7022 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
7023 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
7024 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
7025 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
7026 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
7027 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
7028 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
7029 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
7030
7031 /* CPU panel fitter */
7032 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7033 #define _PFA_CTL_1               0x68080
7034 #define _PFB_CTL_1               0x68880
7035 #define  PF_ENABLE              (1 << 31)
7036 #define  PF_PIPE_SEL_MASK_IVB   (3 << 29)
7037 #define  PF_PIPE_SEL_IVB(pipe)  ((pipe) << 29)
7038 #define  PF_FILTER_MASK         (3 << 23)
7039 #define  PF_FILTER_PROGRAMMED   (0 << 23)
7040 #define  PF_FILTER_MED_3x3      (1 << 23)
7041 #define  PF_FILTER_EDGE_ENHANCE (2 << 23)
7042 #define  PF_FILTER_EDGE_SOFTEN  (3 << 23)
7043 #define _PFA_WIN_SZ             0x68074
7044 #define _PFB_WIN_SZ             0x68874
7045 #define _PFA_WIN_POS            0x68070
7046 #define _PFB_WIN_POS            0x68870
7047 #define _PFA_VSCALE             0x68084
7048 #define _PFB_VSCALE             0x68884
7049 #define _PFA_HSCALE             0x68090
7050 #define _PFB_HSCALE             0x68890
7051
7052 #define PF_CTL(pipe)            _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
7053 #define PF_WIN_SZ(pipe)         _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
7054 #define PF_WIN_POS(pipe)        _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
7055 #define PF_VSCALE(pipe)         _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
7056 #define PF_HSCALE(pipe)         _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
7057
7058 #define _PSA_CTL                0x68180
7059 #define _PSB_CTL                0x68980
7060 #define PS_ENABLE               (1 << 31)
7061 #define _PSA_WIN_SZ             0x68174
7062 #define _PSB_WIN_SZ             0x68974
7063 #define _PSA_WIN_POS            0x68170
7064 #define _PSB_WIN_POS            0x68970
7065
7066 #define PS_CTL(pipe)            _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
7067 #define PS_WIN_SZ(pipe)         _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
7068 #define PS_WIN_POS(pipe)        _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
7069
7070 /*
7071  * Skylake scalers
7072  */
7073 #define _PS_1A_CTRL      0x68180
7074 #define _PS_2A_CTRL      0x68280
7075 #define _PS_1B_CTRL      0x68980
7076 #define _PS_2B_CTRL      0x68A80
7077 #define _PS_1C_CTRL      0x69180
7078 #define PS_SCALER_EN        (1 << 31)
7079 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
7080 #define SKL_PS_SCALER_MODE_DYN  (0 << 28)
7081 #define SKL_PS_SCALER_MODE_HQ  (1 << 28)
7082 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
7083 #define PS_SCALER_MODE_PLANAR (1 << 29)
7084 #define PS_SCALER_MODE_NORMAL (0 << 29)
7085 #define PS_PLANE_SEL_MASK  (7 << 25)
7086 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
7087 #define PS_FILTER_MASK         (3 << 23)
7088 #define PS_FILTER_MEDIUM       (0 << 23)
7089 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
7090 #define PS_FILTER_BILINEAR     (3 << 23)
7091 #define PS_VERT3TAP            (1 << 21)
7092 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7093 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
7094 #define PS_PWRUP_PROGRESS         (1 << 17)
7095 #define PS_V_FILTER_BYPASS        (1 << 8)
7096 #define PS_VADAPT_EN              (1 << 7)
7097 #define PS_VADAPT_MODE_MASK        (3 << 5)
7098 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7099 #define PS_VADAPT_MODE_MOD_ADAPT   (1 << 5)
7100 #define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)
7101 #define PS_PLANE_Y_SEL_MASK  (7 << 5)
7102 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
7103
7104 #define _PS_PWR_GATE_1A     0x68160
7105 #define _PS_PWR_GATE_2A     0x68260
7106 #define _PS_PWR_GATE_1B     0x68960
7107 #define _PS_PWR_GATE_2B     0x68A60
7108 #define _PS_PWR_GATE_1C     0x69160
7109 #define PS_PWR_GATE_DIS_OVERRIDE       (1 << 31)
7110 #define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
7111 #define PS_PWR_GATE_SETTLING_TIME_64   (1 << 3)
7112 #define PS_PWR_GATE_SETTLING_TIME_96   (2 << 3)
7113 #define PS_PWR_GATE_SETTLING_TIME_128  (3 << 3)
7114 #define PS_PWR_GATE_SLPEN_8             0
7115 #define PS_PWR_GATE_SLPEN_16            1
7116 #define PS_PWR_GATE_SLPEN_24            2
7117 #define PS_PWR_GATE_SLPEN_32            3
7118
7119 #define _PS_WIN_POS_1A      0x68170
7120 #define _PS_WIN_POS_2A      0x68270
7121 #define _PS_WIN_POS_1B      0x68970
7122 #define _PS_WIN_POS_2B      0x68A70
7123 #define _PS_WIN_POS_1C      0x69170
7124
7125 #define _PS_WIN_SZ_1A       0x68174
7126 #define _PS_WIN_SZ_2A       0x68274
7127 #define _PS_WIN_SZ_1B       0x68974
7128 #define _PS_WIN_SZ_2B       0x68A74
7129 #define _PS_WIN_SZ_1C       0x69174
7130
7131 #define _PS_VSCALE_1A       0x68184
7132 #define _PS_VSCALE_2A       0x68284
7133 #define _PS_VSCALE_1B       0x68984
7134 #define _PS_VSCALE_2B       0x68A84
7135 #define _PS_VSCALE_1C       0x69184
7136
7137 #define _PS_HSCALE_1A       0x68190
7138 #define _PS_HSCALE_2A       0x68290
7139 #define _PS_HSCALE_1B       0x68990
7140 #define _PS_HSCALE_2B       0x68A90
7141 #define _PS_HSCALE_1C       0x69190
7142
7143 #define _PS_VPHASE_1A       0x68188
7144 #define _PS_VPHASE_2A       0x68288
7145 #define _PS_VPHASE_1B       0x68988
7146 #define _PS_VPHASE_2B       0x68A88
7147 #define _PS_VPHASE_1C       0x69188
7148 #define  PS_Y_PHASE(x)          ((x) << 16)
7149 #define  PS_UV_RGB_PHASE(x)     ((x) << 0)
7150 #define   PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
7151 #define   PS_PHASE_TRIP (1 << 0)
7152
7153 #define _PS_HPHASE_1A       0x68194
7154 #define _PS_HPHASE_2A       0x68294
7155 #define _PS_HPHASE_1B       0x68994
7156 #define _PS_HPHASE_2B       0x68A94
7157 #define _PS_HPHASE_1C       0x69194
7158
7159 #define _PS_ECC_STAT_1A     0x681D0
7160 #define _PS_ECC_STAT_2A     0x682D0
7161 #define _PS_ECC_STAT_1B     0x689D0
7162 #define _PS_ECC_STAT_2B     0x68AD0
7163 #define _PS_ECC_STAT_1C     0x691D0
7164
7165 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
7166 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe,        \
7167                         _ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
7168                         _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
7169 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe,    \
7170                         _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7171                         _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
7172 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe,     \
7173                         _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7174                         _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
7175 #define SKL_PS_WIN_SZ(pipe, id)  _MMIO_PIPE(pipe,     \
7176                         _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A),   \
7177                         _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
7178 #define SKL_PS_VSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
7179                         _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A),   \
7180                         _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
7181 #define SKL_PS_HSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
7182                         _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A),   \
7183                         _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
7184 #define SKL_PS_VPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
7185                         _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A),   \
7186                         _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
7187 #define SKL_PS_HPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
7188                         _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A),   \
7189                         _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
7190 #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
7191                         _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
7192                         _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
7193
7194 /* legacy palette */
7195 #define _LGC_PALETTE_A           0x4a000
7196 #define _LGC_PALETTE_B           0x4a800
7197 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
7198
7199 /* ilk/snb precision palette */
7200 #define _PREC_PALETTE_A           0x4b000
7201 #define _PREC_PALETTE_B           0x4c000
7202 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
7203
7204 #define  _PREC_PIPEAGCMAX              0x4d000
7205 #define  _PREC_PIPEBGCMAX              0x4d010
7206 #define PREC_PIPEGCMAX(pipe, i)        _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
7207
7208 #define _GAMMA_MODE_A           0x4a480
7209 #define _GAMMA_MODE_B           0x4ac80
7210 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
7211 #define  PRE_CSC_GAMMA_ENABLE   (1 << 31)
7212 #define  POST_CSC_GAMMA_ENABLE  (1 << 30)
7213 #define  GAMMA_MODE_MODE_MASK   (3 << 0)
7214 #define  GAMMA_MODE_MODE_8BIT   (0 << 0)
7215 #define  GAMMA_MODE_MODE_10BIT  (1 << 0)
7216 #define  GAMMA_MODE_MODE_12BIT  (2 << 0)
7217 #define  GAMMA_MODE_MODE_SPLIT  (3 << 0) /* ivb-bdw */
7218 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED  (3 << 0) /* icl + */
7219
7220 /* DMC/CSR */
7221 #define CSR_PROGRAM(i)          _MMIO(0x80000 + (i) * 4)
7222 #define CSR_SSP_BASE_ADDR_GEN9  0x00002FC0
7223 #define CSR_HTP_ADDR_SKL        0x00500034
7224 #define CSR_SSP_BASE            _MMIO(0x8F074)
7225 #define CSR_HTP_SKL             _MMIO(0x8F004)
7226 #define CSR_LAST_WRITE          _MMIO(0x8F034)
7227 #define CSR_LAST_WRITE_VALUE    0xc003b400
7228 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7229 #define CSR_MMIO_START_RANGE    0x80000
7230 #define CSR_MMIO_END_RANGE      0x8FFFF
7231 #define SKL_CSR_DC3_DC5_COUNT   _MMIO(0x80030)
7232 #define SKL_CSR_DC5_DC6_COUNT   _MMIO(0x8002C)
7233 #define BXT_CSR_DC3_DC5_COUNT   _MMIO(0x80038)
7234 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
7235 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
7236
7237 /* Display Internal Timeout Register */
7238 #define RM_TIMEOUT              _MMIO(0x42060)
7239 #define  MMIO_TIMEOUT_US(us)    ((us) << 0)
7240
7241 /* interrupts */
7242 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
7243 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
7244 #define DE_SPRITEA_FLIP_DONE    (1 << 28)
7245 #define DE_PLANEB_FLIP_DONE     (1 << 27)
7246 #define DE_PLANEA_FLIP_DONE     (1 << 26)
7247 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7248 #define DE_PCU_EVENT            (1 << 25)
7249 #define DE_GTT_FAULT            (1 << 24)
7250 #define DE_POISON               (1 << 23)
7251 #define DE_PERFORM_COUNTER      (1 << 22)
7252 #define DE_PCH_EVENT            (1 << 21)
7253 #define DE_AUX_CHANNEL_A        (1 << 20)
7254 #define DE_DP_A_HOTPLUG         (1 << 19)
7255 #define DE_GSE                  (1 << 18)
7256 #define DE_PIPEB_VBLANK         (1 << 15)
7257 #define DE_PIPEB_EVEN_FIELD     (1 << 14)
7258 #define DE_PIPEB_ODD_FIELD      (1 << 13)
7259 #define DE_PIPEB_LINE_COMPARE   (1 << 12)
7260 #define DE_PIPEB_VSYNC          (1 << 11)
7261 #define DE_PIPEB_CRC_DONE       (1 << 10)
7262 #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
7263 #define DE_PIPEA_VBLANK         (1 << 7)
7264 #define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
7265 #define DE_PIPEA_EVEN_FIELD     (1 << 6)
7266 #define DE_PIPEA_ODD_FIELD      (1 << 5)
7267 #define DE_PIPEA_LINE_COMPARE   (1 << 4)
7268 #define DE_PIPEA_VSYNC          (1 << 3)
7269 #define DE_PIPEA_CRC_DONE       (1 << 2)
7270 #define DE_PIPE_CRC_DONE(pipe)  (1 << (2 + 8 * (pipe)))
7271 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
7272 #define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
7273
7274 /* More Ivybridge lolz */
7275 #define DE_ERR_INT_IVB                  (1 << 30)
7276 #define DE_GSE_IVB                      (1 << 29)
7277 #define DE_PCH_EVENT_IVB                (1 << 28)
7278 #define DE_DP_A_HOTPLUG_IVB             (1 << 27)
7279 #define DE_AUX_CHANNEL_A_IVB            (1 << 26)
7280 #define DE_EDP_PSR_INT_HSW              (1 << 19)
7281 #define DE_SPRITEC_FLIP_DONE_IVB        (1 << 14)
7282 #define DE_PLANEC_FLIP_DONE_IVB         (1 << 13)
7283 #define DE_PIPEC_VBLANK_IVB             (1 << 10)
7284 #define DE_SPRITEB_FLIP_DONE_IVB        (1 << 9)
7285 #define DE_PLANEB_FLIP_DONE_IVB         (1 << 8)
7286 #define DE_PIPEB_VBLANK_IVB             (1 << 5)
7287 #define DE_SPRITEA_FLIP_DONE_IVB        (1 << 4)
7288 #define DE_PLANEA_FLIP_DONE_IVB         (1 << 3)
7289 #define DE_PLANE_FLIP_DONE_IVB(plane)   (1 << (3 + 5 * (plane)))
7290 #define DE_PIPEA_VBLANK_IVB             (1 << 0)
7291 #define DE_PIPE_VBLANK_IVB(pipe)        (1 << ((pipe) * 5))
7292
7293 #define VLV_MASTER_IER                  _MMIO(0x4400c) /* Gunit master IER */
7294 #define   MASTER_INTERRUPT_ENABLE       (1 << 31)
7295
7296 #define DEISR   _MMIO(0x44000)
7297 #define DEIMR   _MMIO(0x44004)
7298 #define DEIIR   _MMIO(0x44008)
7299 #define DEIER   _MMIO(0x4400c)
7300
7301 #define GTISR   _MMIO(0x44010)
7302 #define GTIMR   _MMIO(0x44014)
7303 #define GTIIR   _MMIO(0x44018)
7304 #define GTIER   _MMIO(0x4401c)
7305
7306 #define GEN8_MASTER_IRQ                 _MMIO(0x44200)
7307 #define  GEN8_MASTER_IRQ_CONTROL        (1 << 31)
7308 #define  GEN8_PCU_IRQ                   (1 << 30)
7309 #define  GEN8_DE_PCH_IRQ                (1 << 23)
7310 #define  GEN8_DE_MISC_IRQ               (1 << 22)
7311 #define  GEN8_DE_PORT_IRQ               (1 << 20)
7312 #define  GEN8_DE_PIPE_C_IRQ             (1 << 18)
7313 #define  GEN8_DE_PIPE_B_IRQ             (1 << 17)
7314 #define  GEN8_DE_PIPE_A_IRQ             (1 << 16)
7315 #define  GEN8_DE_PIPE_IRQ(pipe)         (1 << (16 + (pipe)))
7316 #define  GEN8_GT_VECS_IRQ               (1 << 6)
7317 #define  GEN8_GT_GUC_IRQ                (1 << 5)
7318 #define  GEN8_GT_PM_IRQ                 (1 << 4)
7319 #define  GEN8_GT_VCS1_IRQ               (1 << 3) /* NB: VCS2 in bspec! */
7320 #define  GEN8_GT_VCS0_IRQ               (1 << 2) /* NB: VCS1 in bpsec! */
7321 #define  GEN8_GT_BCS_IRQ                (1 << 1)
7322 #define  GEN8_GT_RCS_IRQ                (1 << 0)
7323
7324 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7325 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7326 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7327 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7328
7329 #define GEN8_RCS_IRQ_SHIFT 0
7330 #define GEN8_BCS_IRQ_SHIFT 16
7331 #define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
7332 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
7333 #define GEN8_VECS_IRQ_SHIFT 0
7334 #define GEN8_WD_IRQ_SHIFT 16
7335
7336 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7337 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7338 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7339 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7340 #define  GEN8_PIPE_FIFO_UNDERRUN        (1 << 31)
7341 #define  GEN8_PIPE_CDCLK_CRC_ERROR      (1 << 29)
7342 #define  GEN8_PIPE_CDCLK_CRC_DONE       (1 << 28)
7343 #define  GEN8_PIPE_CURSOR_FAULT         (1 << 10)
7344 #define  GEN8_PIPE_SPRITE_FAULT         (1 << 9)
7345 #define  GEN8_PIPE_PRIMARY_FAULT        (1 << 8)
7346 #define  GEN8_PIPE_SPRITE_FLIP_DONE     (1 << 5)
7347 #define  GEN8_PIPE_PRIMARY_FLIP_DONE    (1 << 4)
7348 #define  GEN8_PIPE_SCAN_LINE_EVENT      (1 << 2)
7349 #define  GEN8_PIPE_VSYNC                (1 << 1)
7350 #define  GEN8_PIPE_VBLANK               (1 << 0)
7351 #define  GEN9_PIPE_CURSOR_FAULT         (1 << 11)
7352 #define  GEN9_PIPE_PLANE4_FAULT         (1 << 10)
7353 #define  GEN9_PIPE_PLANE3_FAULT         (1 << 9)
7354 #define  GEN9_PIPE_PLANE2_FAULT         (1 << 8)
7355 #define  GEN9_PIPE_PLANE1_FAULT         (1 << 7)
7356 #define  GEN9_PIPE_PLANE4_FLIP_DONE     (1 << 6)
7357 #define  GEN9_PIPE_PLANE3_FLIP_DONE     (1 << 5)
7358 #define  GEN9_PIPE_PLANE2_FLIP_DONE     (1 << 4)
7359 #define  GEN9_PIPE_PLANE1_FLIP_DONE     (1 << 3)
7360 #define  GEN9_PIPE_PLANE_FLIP_DONE(p)   (1 << (3 + (p)))
7361 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7362         (GEN8_PIPE_CURSOR_FAULT | \
7363          GEN8_PIPE_SPRITE_FAULT | \
7364          GEN8_PIPE_PRIMARY_FAULT)
7365 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7366         (GEN9_PIPE_CURSOR_FAULT | \
7367          GEN9_PIPE_PLANE4_FAULT | \
7368          GEN9_PIPE_PLANE3_FAULT | \
7369          GEN9_PIPE_PLANE2_FAULT | \
7370          GEN9_PIPE_PLANE1_FAULT)
7371
7372 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7373 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7374 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7375 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7376 #define  ICL_AUX_CHANNEL_E              (1 << 29)
7377 #define  CNL_AUX_CHANNEL_F              (1 << 28)
7378 #define  GEN9_AUX_CHANNEL_D             (1 << 27)
7379 #define  GEN9_AUX_CHANNEL_C             (1 << 26)
7380 #define  GEN9_AUX_CHANNEL_B             (1 << 25)
7381 #define  BXT_DE_PORT_HP_DDIC            (1 << 5)
7382 #define  BXT_DE_PORT_HP_DDIB            (1 << 4)
7383 #define  BXT_DE_PORT_HP_DDIA            (1 << 3)
7384 #define  BXT_DE_PORT_HOTPLUG_MASK       (BXT_DE_PORT_HP_DDIA | \
7385                                          BXT_DE_PORT_HP_DDIB | \
7386                                          BXT_DE_PORT_HP_DDIC)
7387 #define  GEN8_PORT_DP_A_HOTPLUG         (1 << 3)
7388 #define  BXT_DE_PORT_GMBUS              (1 << 1)
7389 #define  GEN8_AUX_CHANNEL_A             (1 << 0)
7390 #define  TGL_DE_PORT_AUX_DDIC           (1 << 2)
7391 #define  TGL_DE_PORT_AUX_DDIB           (1 << 1)
7392 #define  TGL_DE_PORT_AUX_DDIA           (1 << 0)
7393
7394 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
7395 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
7396 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7397 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7398 #define  GEN8_DE_MISC_GSE               (1 << 27)
7399 #define  GEN8_DE_EDP_PSR                (1 << 19)
7400
7401 #define GEN8_PCU_ISR _MMIO(0x444e0)
7402 #define GEN8_PCU_IMR _MMIO(0x444e4)
7403 #define GEN8_PCU_IIR _MMIO(0x444e8)
7404 #define GEN8_PCU_IER _MMIO(0x444ec)
7405
7406 #define GEN11_GU_MISC_ISR       _MMIO(0x444f0)
7407 #define GEN11_GU_MISC_IMR       _MMIO(0x444f4)
7408 #define GEN11_GU_MISC_IIR       _MMIO(0x444f8)
7409 #define GEN11_GU_MISC_IER       _MMIO(0x444fc)
7410 #define  GEN11_GU_MISC_GSE      (1 << 27)
7411
7412 #define GEN11_GFX_MSTR_IRQ              _MMIO(0x190010)
7413 #define  GEN11_MASTER_IRQ               (1 << 31)
7414 #define  GEN11_PCU_IRQ                  (1 << 30)
7415 #define  GEN11_GU_MISC_IRQ              (1 << 29)
7416 #define  GEN11_DISPLAY_IRQ              (1 << 16)
7417 #define  GEN11_GT_DW_IRQ(x)             (1 << (x))
7418 #define  GEN11_GT_DW1_IRQ               (1 << 1)
7419 #define  GEN11_GT_DW0_IRQ               (1 << 0)
7420
7421 #define GEN11_DISPLAY_INT_CTL           _MMIO(0x44200)
7422 #define  GEN11_DISPLAY_IRQ_ENABLE       (1 << 31)
7423 #define  GEN11_AUDIO_CODEC_IRQ          (1 << 24)
7424 #define  GEN11_DE_PCH_IRQ               (1 << 23)
7425 #define  GEN11_DE_MISC_IRQ              (1 << 22)
7426 #define  GEN11_DE_HPD_IRQ               (1 << 21)
7427 #define  GEN11_DE_PORT_IRQ              (1 << 20)
7428 #define  GEN11_DE_PIPE_C                (1 << 18)
7429 #define  GEN11_DE_PIPE_B                (1 << 17)
7430 #define  GEN11_DE_PIPE_A                (1 << 16)
7431
7432 #define GEN11_DE_HPD_ISR                _MMIO(0x44470)
7433 #define GEN11_DE_HPD_IMR                _MMIO(0x44474)
7434 #define GEN11_DE_HPD_IIR                _MMIO(0x44478)
7435 #define GEN11_DE_HPD_IER                _MMIO(0x4447c)
7436 #define  GEN12_TC6_HOTPLUG                      (1 << 21)
7437 #define  GEN12_TC5_HOTPLUG                      (1 << 20)
7438 #define  GEN11_TC4_HOTPLUG                      (1 << 19)
7439 #define  GEN11_TC3_HOTPLUG                      (1 << 18)
7440 #define  GEN11_TC2_HOTPLUG                      (1 << 17)
7441 #define  GEN11_TC1_HOTPLUG                      (1 << 16)
7442 #define  GEN11_TC_HOTPLUG(tc_port)              (1 << ((tc_port) + 16))
7443 #define  GEN11_DE_TC_HOTPLUG_MASK               (GEN12_TC6_HOTPLUG | \
7444                                                  GEN12_TC5_HOTPLUG | \
7445                                                  GEN11_TC4_HOTPLUG | \
7446                                                  GEN11_TC3_HOTPLUG | \
7447                                                  GEN11_TC2_HOTPLUG | \
7448                                                  GEN11_TC1_HOTPLUG)
7449 #define  GEN12_TBT6_HOTPLUG                     (1 << 5)
7450 #define  GEN12_TBT5_HOTPLUG                     (1 << 4)
7451 #define  GEN11_TBT4_HOTPLUG                     (1 << 3)
7452 #define  GEN11_TBT3_HOTPLUG                     (1 << 2)
7453 #define  GEN11_TBT2_HOTPLUG                     (1 << 1)
7454 #define  GEN11_TBT1_HOTPLUG                     (1 << 0)
7455 #define  GEN11_TBT_HOTPLUG(tc_port)             (1 << (tc_port))
7456 #define  GEN11_DE_TBT_HOTPLUG_MASK              (GEN12_TBT6_HOTPLUG | \
7457                                                  GEN12_TBT5_HOTPLUG | \
7458                                                  GEN11_TBT4_HOTPLUG | \
7459                                                  GEN11_TBT3_HOTPLUG | \
7460                                                  GEN11_TBT2_HOTPLUG | \
7461                                                  GEN11_TBT1_HOTPLUG)
7462
7463 #define GEN11_TBT_HOTPLUG_CTL                           _MMIO(0x44030)
7464 #define GEN11_TC_HOTPLUG_CTL                            _MMIO(0x44038)
7465 #define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)              (8 << (tc_port) * 4)
7466 #define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)         (2 << (tc_port) * 4)
7467 #define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)        (1 << (tc_port) * 4)
7468 #define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)           (0 << (tc_port) * 4)
7469
7470 #define GEN11_GT_INTR_DW0               _MMIO(0x190018)
7471 #define  GEN11_CSME                     (31)
7472 #define  GEN11_GUNIT                    (28)
7473 #define  GEN11_GUC                      (25)
7474 #define  GEN11_WDPERF                   (20)
7475 #define  GEN11_KCR                      (19)
7476 #define  GEN11_GTPM                     (16)
7477 #define  GEN11_BCS                      (15)
7478 #define  GEN11_RCS0                     (0)
7479
7480 #define GEN11_GT_INTR_DW1               _MMIO(0x19001c)
7481 #define  GEN11_VECS(x)                  (31 - (x))
7482 #define  GEN11_VCS(x)                   (x)
7483
7484 #define GEN11_GT_INTR_DW(x)             _MMIO(0x190018 + ((x) * 4))
7485
7486 #define GEN11_INTR_IDENTITY_REG0        _MMIO(0x190060)
7487 #define GEN11_INTR_IDENTITY_REG1        _MMIO(0x190064)
7488 #define  GEN11_INTR_DATA_VALID          (1 << 31)
7489 #define  GEN11_INTR_ENGINE_CLASS(x)     (((x) & GENMASK(18, 16)) >> 16)
7490 #define  GEN11_INTR_ENGINE_INSTANCE(x)  (((x) & GENMASK(25, 20)) >> 20)
7491 #define  GEN11_INTR_ENGINE_INTR(x)      ((x) & 0xffff)
7492 /* irq instances for OTHER_CLASS */
7493 #define OTHER_GUC_INSTANCE      0
7494 #define OTHER_GTPM_INSTANCE     1
7495
7496 #define GEN11_INTR_IDENTITY_REG(x)      _MMIO(0x190060 + ((x) * 4))
7497
7498 #define GEN11_IIR_REG0_SELECTOR         _MMIO(0x190070)
7499 #define GEN11_IIR_REG1_SELECTOR         _MMIO(0x190074)
7500
7501 #define GEN11_IIR_REG_SELECTOR(x)       _MMIO(0x190070 + ((x) * 4))
7502
7503 #define GEN11_RENDER_COPY_INTR_ENABLE   _MMIO(0x190030)
7504 #define GEN11_VCS_VECS_INTR_ENABLE      _MMIO(0x190034)
7505 #define GEN11_GUC_SG_INTR_ENABLE        _MMIO(0x190038)
7506 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7507 #define GEN11_CRYPTO_RSVD_INTR_ENABLE   _MMIO(0x190040)
7508 #define GEN11_GUNIT_CSME_INTR_ENABLE    _MMIO(0x190044)
7509
7510 #define GEN11_RCS0_RSVD_INTR_MASK       _MMIO(0x190090)
7511 #define GEN11_BCS_RSVD_INTR_MASK        _MMIO(0x1900a0)
7512 #define GEN11_VCS0_VCS1_INTR_MASK       _MMIO(0x1900a8)
7513 #define GEN11_VCS2_VCS3_INTR_MASK       _MMIO(0x1900ac)
7514 #define GEN11_VECS0_VECS1_INTR_MASK     _MMIO(0x1900d0)
7515 #define GEN11_GUC_SG_INTR_MASK          _MMIO(0x1900e8)
7516 #define GEN11_GPM_WGBOXPERF_INTR_MASK   _MMIO(0x1900ec)
7517 #define GEN11_CRYPTO_RSVD_INTR_MASK     _MMIO(0x1900f0)
7518 #define GEN11_GUNIT_CSME_INTR_MASK      _MMIO(0x1900f4)
7519
7520 #define   ENGINE1_MASK                  REG_GENMASK(31, 16)
7521 #define   ENGINE0_MASK                  REG_GENMASK(15, 0)
7522
7523 #define ILK_DISPLAY_CHICKEN2    _MMIO(0x42004)
7524 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7525 #define  ILK_ELPIN_409_SELECT   (1 << 25)
7526 #define  ILK_DPARB_GATE (1 << 22)
7527 #define  ILK_VSDPFD_FULL        (1 << 21)
7528 #define FUSE_STRAP                      _MMIO(0x42014)
7529 #define  ILK_INTERNAL_GRAPHICS_DISABLE  (1 << 31)
7530 #define  ILK_INTERNAL_DISPLAY_DISABLE   (1 << 30)
7531 #define  ILK_DISPLAY_DEBUG_DISABLE      (1 << 29)
7532 #define  IVB_PIPE_C_DISABLE             (1 << 28)
7533 #define  ILK_HDCP_DISABLE               (1 << 25)
7534 #define  ILK_eDP_A_DISABLE              (1 << 24)
7535 #define  HSW_CDCLK_LIMIT                (1 << 24)
7536 #define  ILK_DESKTOP                    (1 << 23)
7537 #define  HSW_CPU_SSC_ENABLE             (1 << 21)
7538
7539 #define FUSE_STRAP3                     _MMIO(0x42020)
7540 #define  HSW_REF_CLK_SELECT             (1 << 1)
7541
7542 #define ILK_DSPCLK_GATE_D                       _MMIO(0x42020)
7543 #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE        (1 << 28)
7544 #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE       (1 << 9)
7545 #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE      (1 << 8)
7546 #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE        (1 << 7)
7547 #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE       (1 << 5)
7548
7549 #define IVB_CHICKEN3    _MMIO(0x4200c)
7550 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE      (1 << 5)
7551 # define CHICKEN3_DGMG_DONE_FIX_DISABLE         (1 << 2)
7552
7553 #define CHICKEN_PAR1_1          _MMIO(0x42080)
7554 #define  SKL_DE_COMPRESSED_HASH_MODE    (1 << 15)
7555 #define  DPA_MASK_VBLANK_SRD    (1 << 15)
7556 #define  FORCE_ARB_IDLE_PLANES  (1 << 14)
7557 #define  SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
7558
7559 #define CHICKEN_PAR2_1          _MMIO(0x42090)
7560 #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT  (1 << 14)
7561
7562 #define CHICKEN_MISC_2          _MMIO(0x42084)
7563 #define  CNL_COMP_PWR_DOWN      (1 << 23)
7564 #define  GLK_CL2_PWR_DOWN       (1 << 12)
7565 #define  GLK_CL1_PWR_DOWN       (1 << 11)
7566 #define  GLK_CL0_PWR_DOWN       (1 << 10)
7567
7568 #define CHICKEN_MISC_4          _MMIO(0x4208c)
7569 #define   FBC_STRIDE_OVERRIDE   (1 << 13)
7570 #define   FBC_STRIDE_MASK       0x1FFF
7571
7572 #define _CHICKEN_PIPESL_1_A     0x420b0
7573 #define _CHICKEN_PIPESL_1_B     0x420b4
7574 #define  HSW_FBCQ_DIS                   (1 << 22)
7575 #define  BDW_DPRS_MASK_VBLANK_SRD       (1 << 0)
7576 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7577
7578 #define CHICKEN_TRANS_A         _MMIO(0x420c0)
7579 #define CHICKEN_TRANS_B         _MMIO(0x420c4)
7580 #define CHICKEN_TRANS_C         _MMIO(0x420c8)
7581 #define CHICKEN_TRANS_EDP       _MMIO(0x420cc)
7582 #define  VSC_DATA_SEL_SOFTWARE_CONTROL  (1 << 25) /* GLK and CNL+ */
7583 #define  DDI_TRAINING_OVERRIDE_ENABLE   (1 << 19)
7584 #define  DDI_TRAINING_OVERRIDE_VALUE    (1 << 18)
7585 #define  DDIE_TRAINING_OVERRIDE_ENABLE  (1 << 17) /* CHICKEN_TRANS_A only */
7586 #define  DDIE_TRAINING_OVERRIDE_VALUE   (1 << 16) /* CHICKEN_TRANS_A only */
7587 #define  PSR2_ADD_VERTICAL_LINE_COUNT   (1 << 15)
7588 #define  PSR2_VSC_ENABLE_PROG_HEADER    (1 << 12)
7589
7590 #define DISP_ARB_CTL    _MMIO(0x45000)
7591 #define  DISP_FBC_MEMORY_WAKE           (1 << 31)
7592 #define  DISP_TILE_SURFACE_SWIZZLING    (1 << 13)
7593 #define  DISP_FBC_WM_DIS                (1 << 15)
7594 #define DISP_ARB_CTL2   _MMIO(0x45004)
7595 #define  DISP_DATA_PARTITION_5_6        (1 << 6)
7596 #define  DISP_IPC_ENABLE                (1 << 3)
7597 #define DBUF_CTL        _MMIO(0x45008)
7598 #define DBUF_CTL_S1     _MMIO(0x45008)
7599 #define DBUF_CTL_S2     _MMIO(0x44FE8)
7600 #define  DBUF_POWER_REQUEST             (1 << 31)
7601 #define  DBUF_POWER_STATE               (1 << 30)
7602 #define GEN7_MSG_CTL    _MMIO(0x45010)
7603 #define  WAIT_FOR_PCH_RESET_ACK         (1 << 1)
7604 #define  WAIT_FOR_PCH_FLR_ACK           (1 << 0)
7605 #define HSW_NDE_RSTWRN_OPT      _MMIO(0x46408)
7606 #define  RESET_PCH_HANDSHAKE_ENABLE     (1 << 4)
7607
7608 #define GEN8_CHICKEN_DCPR_1             _MMIO(0x46430)
7609 #define   SKL_SELECT_ALTERNATE_DC_EXIT  (1 << 30)
7610 #define   MASK_WAKEMEM                  (1 << 13)
7611 #define   CNL_DDI_CLOCK_REG_ACCESS_ON   (1 << 7)
7612
7613 #define SKL_DFSM                        _MMIO(0x51000)
7614 #define SKL_DFSM_CDCLK_LIMIT_MASK       (3 << 23)
7615 #define SKL_DFSM_CDCLK_LIMIT_675        (0 << 23)
7616 #define SKL_DFSM_CDCLK_LIMIT_540        (1 << 23)
7617 #define SKL_DFSM_CDCLK_LIMIT_450        (2 << 23)
7618 #define SKL_DFSM_CDCLK_LIMIT_337_5      (3 << 23)
7619 #define SKL_DFSM_PIPE_A_DISABLE         (1 << 30)
7620 #define SKL_DFSM_PIPE_B_DISABLE         (1 << 21)
7621 #define SKL_DFSM_PIPE_C_DISABLE         (1 << 28)
7622 #define TGL_DFSM_PIPE_D_DISABLE         (1 << 22)
7623
7624 #define SKL_DSSM                                _MMIO(0x51004)
7625 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz         (1 << 31)
7626 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK          (7 << 29)
7627 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz         (0 << 29)
7628 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz       (1 << 29)
7629 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz       (2 << 29)
7630
7631 #define GEN7_FF_SLICE_CS_CHICKEN1       _MMIO(0x20e0)
7632 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
7633
7634 #define FF_SLICE_CS_CHICKEN2                    _MMIO(0x20e4)
7635 #define  GEN9_TSG_BARRIER_ACK_DISABLE           (1 << 8)
7636 #define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1 << 10)
7637
7638 #define GEN9_CS_DEBUG_MODE1             _MMIO(0x20ec)
7639 #define GEN9_CTX_PREEMPT_REG            _MMIO(0x2248)
7640 #define GEN8_CS_CHICKEN1                _MMIO(0x2580)
7641 #define GEN9_PREEMPT_3D_OBJECT_LEVEL            (1 << 0)
7642 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo)        (((hi) << 2) | ((lo) << 1))
7643 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL     GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7644 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL   GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7645 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL        GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7646 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK           GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7647
7648 /* GEN7 chicken */
7649 #define GEN7_COMMON_SLICE_CHICKEN1              _MMIO(0x7010)
7650   #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC     ((1 << 10) | (1 << 26))
7651   #define GEN9_RHWO_OPTIMIZATION_DISABLE        (1 << 14)
7652
7653 #define COMMON_SLICE_CHICKEN2                                   _MMIO(0x7014)
7654   #define GEN9_PBE_COMPRESSED_HASH_SELECTION                    (1 << 13)
7655   #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE        (1 << 12)
7656   #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION              (1 << 8)
7657   #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE                  (1 << 0)
7658
7659 #define GEN8_L3CNTLREG  _MMIO(0x7034)
7660   #define GEN8_ERRDETBCTRL (1 << 9)
7661
7662 #define GEN11_COMMON_SLICE_CHICKEN3             _MMIO(0x7304)
7663   #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC    (1 << 11)
7664
7665 #define HIZ_CHICKEN                                     _MMIO(0x7018)
7666 # define CHV_HZ_8X8_MODE_IN_1X                          (1 << 15)
7667 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE    (1 << 3)
7668
7669 #define GEN9_SLICE_COMMON_ECO_CHICKEN0          _MMIO(0x7308)
7670 #define  DISABLE_PIXEL_MASK_CAMMING             (1 << 14)
7671
7672 #define GEN9_SLICE_COMMON_ECO_CHICKEN1          _MMIO(0x731c)
7673 #define   GEN11_STATE_CACHE_REDIRECT_TO_CS      (1 << 11)
7674
7675 #define GEN7_SARCHKMD                           _MMIO(0xB000)
7676 #define GEN7_DISABLE_DEMAND_PREFETCH            (1 << 31)
7677 #define GEN7_DISABLE_SAMPLER_PREFETCH           (1 << 30)
7678
7679 #define GEN7_L3SQCREG1                          _MMIO(0xB010)
7680 #define  VLV_B0_WA_L3SQCREG1_VALUE              0x00D30000
7681
7682 #define GEN8_L3SQCREG1                          _MMIO(0xB100)
7683 /*
7684  * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7685  * Using the formula in BSpec leads to a hang, while the formula here works
7686  * fine and matches the formulas for all other platforms. A BSpec change
7687  * request has been filed to clarify this.
7688  */
7689 #define  L3_GENERAL_PRIO_CREDITS(x)             (((x) >> 1) << 19)
7690 #define  L3_HIGH_PRIO_CREDITS(x)                (((x) >> 1) << 14)
7691 #define  L3_PRIO_CREDITS_MASK                   ((0x1f << 19) | (0x1f << 14))
7692
7693 #define GEN7_L3CNTLREG1                         _MMIO(0xB01C)
7694 #define  GEN7_WA_FOR_GEN7_L3_CONTROL                    0x3C47FF8C
7695 #define  GEN7_L3AGDIS                           (1 << 19)
7696 #define GEN7_L3CNTLREG2                         _MMIO(0xB020)
7697 #define GEN7_L3CNTLREG3                         _MMIO(0xB024)
7698
7699 #define GEN7_L3_CHICKEN_MODE_REGISTER           _MMIO(0xB030)
7700 #define   GEN7_WA_L3_CHICKEN_MODE               0x20000000
7701 #define GEN10_L3_CHICKEN_MODE_REGISTER          _MMIO(0xB114)
7702 #define   GEN11_I2M_WRITE_DISABLE               (1 << 28)
7703
7704 #define GEN7_L3SQCREG4                          _MMIO(0xb034)
7705 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE        (1 << 27)
7706
7707 #define GEN11_SCRATCH2                                  _MMIO(0xb140)
7708 #define  GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE      (1 << 19)
7709
7710 #define GEN8_L3SQCREG4                          _MMIO(0xb118)
7711 #define  GEN11_LQSC_CLEAN_EVICT_DISABLE         (1 << 6)
7712 #define  GEN8_LQSC_RO_PERF_DIS                  (1 << 27)
7713 #define  GEN8_LQSC_FLUSH_COHERENT_LINES         (1 << 21)
7714
7715 /* GEN8 chicken */
7716 #define HDC_CHICKEN0                            _MMIO(0x7300)
7717 #define CNL_HDC_CHICKEN0                        _MMIO(0xE5F0)
7718 #define ICL_HDC_MODE                            _MMIO(0xE5F4)
7719 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
7720 #define  HDC_FENCE_DEST_SLM_DISABLE             (1 << 14)
7721 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED        (1 << 11)
7722 #define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT    (1 << 5)
7723 #define  HDC_FORCE_NON_COHERENT                 (1 << 4)
7724 #define  HDC_BARRIER_PERFORMANCE_DISABLE        (1 << 10)
7725
7726 #define GEN8_HDC_CHICKEN1                       _MMIO(0x7304)
7727
7728 /* GEN9 chicken */
7729 #define SLICE_ECO_CHICKEN0                      _MMIO(0x7308)
7730 #define   PIXEL_MASK_CAMMING_DISABLE            (1 << 14)
7731
7732 #define GEN9_WM_CHICKEN3                        _MMIO(0x5588)
7733 #define   GEN9_FACTOR_IN_CLR_VAL_HIZ            (1 << 9)
7734
7735 /* WaCatErrorRejectionIssue */
7736 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG          _MMIO(0x9030)
7737 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB       (1 << 11)
7738
7739 #define HSW_SCRATCH1                            _MMIO(0xb038)
7740 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE   (1 << 27)
7741
7742 #define BDW_SCRATCH1                                    _MMIO(0xb11c)
7743 #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE      (1 << 2)
7744
7745 /*GEN11 chicken */
7746 #define _PIPEA_CHICKEN                          0x70038
7747 #define _PIPEB_CHICKEN                          0x71038
7748 #define _PIPEC_CHICKEN                          0x72038
7749 #define PIPE_CHICKEN(pipe)                      _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
7750                                                            _PIPEB_CHICKEN)
7751 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU      (1 << 15)
7752 #define   PER_PIXEL_ALPHA_BYPASS_EN             (1 << 7)
7753
7754 /* PCH */
7755
7756 #define PCH_DISPLAY_BASE        0xc0000u
7757
7758 /* south display engine interrupt: IBX */
7759 #define SDE_AUDIO_POWER_D       (1 << 27)
7760 #define SDE_AUDIO_POWER_C       (1 << 26)
7761 #define SDE_AUDIO_POWER_B       (1 << 25)
7762 #define SDE_AUDIO_POWER_SHIFT   (25)
7763 #define SDE_AUDIO_POWER_MASK    (7 << SDE_AUDIO_POWER_SHIFT)
7764 #define SDE_GMBUS               (1 << 24)
7765 #define SDE_AUDIO_HDCP_TRANSB   (1 << 23)
7766 #define SDE_AUDIO_HDCP_TRANSA   (1 << 22)
7767 #define SDE_AUDIO_HDCP_MASK     (3 << 22)
7768 #define SDE_AUDIO_TRANSB        (1 << 21)
7769 #define SDE_AUDIO_TRANSA        (1 << 20)
7770 #define SDE_AUDIO_TRANS_MASK    (3 << 20)
7771 #define SDE_POISON              (1 << 19)
7772 /* 18 reserved */
7773 #define SDE_FDI_RXB             (1 << 17)
7774 #define SDE_FDI_RXA             (1 << 16)
7775 #define SDE_FDI_MASK            (3 << 16)
7776 #define SDE_AUXD                (1 << 15)
7777 #define SDE_AUXC                (1 << 14)
7778 #define SDE_AUXB                (1 << 13)
7779 #define SDE_AUX_MASK            (7 << 13)
7780 /* 12 reserved */
7781 #define SDE_CRT_HOTPLUG         (1 << 11)
7782 #define SDE_PORTD_HOTPLUG       (1 << 10)
7783 #define SDE_PORTC_HOTPLUG       (1 << 9)
7784 #define SDE_PORTB_HOTPLUG       (1 << 8)
7785 #define SDE_SDVOB_HOTPLUG       (1 << 6)
7786 #define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
7787                                  SDE_SDVOB_HOTPLUG |    \
7788                                  SDE_PORTB_HOTPLUG |    \
7789                                  SDE_PORTC_HOTPLUG |    \
7790                                  SDE_PORTD_HOTPLUG)
7791 #define SDE_TRANSB_CRC_DONE     (1 << 5)
7792 #define SDE_TRANSB_CRC_ERR      (1 << 4)
7793 #define SDE_TRANSB_FIFO_UNDER   (1 << 3)
7794 #define SDE_TRANSA_CRC_DONE     (1 << 2)
7795 #define SDE_TRANSA_CRC_ERR      (1 << 1)
7796 #define SDE_TRANSA_FIFO_UNDER   (1 << 0)
7797 #define SDE_TRANS_MASK          (0x3f)
7798
7799 /* south display engine interrupt: CPT - CNP */
7800 #define SDE_AUDIO_POWER_D_CPT   (1 << 31)
7801 #define SDE_AUDIO_POWER_C_CPT   (1 << 30)
7802 #define SDE_AUDIO_POWER_B_CPT   (1 << 29)
7803 #define SDE_AUDIO_POWER_SHIFT_CPT   29
7804 #define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
7805 #define SDE_AUXD_CPT            (1 << 27)
7806 #define SDE_AUXC_CPT            (1 << 26)
7807 #define SDE_AUXB_CPT            (1 << 25)
7808 #define SDE_AUX_MASK_CPT        (7 << 25)
7809 #define SDE_PORTE_HOTPLUG_SPT   (1 << 25)
7810 #define SDE_PORTA_HOTPLUG_SPT   (1 << 24)
7811 #define SDE_PORTD_HOTPLUG_CPT   (1 << 23)
7812 #define SDE_PORTC_HOTPLUG_CPT   (1 << 22)
7813 #define SDE_PORTB_HOTPLUG_CPT   (1 << 21)
7814 #define SDE_CRT_HOTPLUG_CPT     (1 << 19)
7815 #define SDE_SDVOB_HOTPLUG_CPT   (1 << 18)
7816 #define SDE_HOTPLUG_MASK_CPT    (SDE_CRT_HOTPLUG_CPT |          \
7817                                  SDE_SDVOB_HOTPLUG_CPT |        \
7818                                  SDE_PORTD_HOTPLUG_CPT |        \
7819                                  SDE_PORTC_HOTPLUG_CPT |        \
7820                                  SDE_PORTB_HOTPLUG_CPT)
7821 #define SDE_HOTPLUG_MASK_SPT    (SDE_PORTE_HOTPLUG_SPT |        \
7822                                  SDE_PORTD_HOTPLUG_CPT |        \
7823                                  SDE_PORTC_HOTPLUG_CPT |        \
7824                                  SDE_PORTB_HOTPLUG_CPT |        \
7825                                  SDE_PORTA_HOTPLUG_SPT)
7826 #define SDE_GMBUS_CPT           (1 << 17)
7827 #define SDE_ERROR_CPT           (1 << 16)
7828 #define SDE_AUDIO_CP_REQ_C_CPT  (1 << 10)
7829 #define SDE_AUDIO_CP_CHG_C_CPT  (1 << 9)
7830 #define SDE_FDI_RXC_CPT         (1 << 8)
7831 #define SDE_AUDIO_CP_REQ_B_CPT  (1 << 6)
7832 #define SDE_AUDIO_CP_CHG_B_CPT  (1 << 5)
7833 #define SDE_FDI_RXB_CPT         (1 << 4)
7834 #define SDE_AUDIO_CP_REQ_A_CPT  (1 << 2)
7835 #define SDE_AUDIO_CP_CHG_A_CPT  (1 << 1)
7836 #define SDE_FDI_RXA_CPT         (1 << 0)
7837 #define SDE_AUDIO_CP_REQ_CPT    (SDE_AUDIO_CP_REQ_C_CPT | \
7838                                  SDE_AUDIO_CP_REQ_B_CPT | \
7839                                  SDE_AUDIO_CP_REQ_A_CPT)
7840 #define SDE_AUDIO_CP_CHG_CPT    (SDE_AUDIO_CP_CHG_C_CPT | \
7841                                  SDE_AUDIO_CP_CHG_B_CPT | \
7842                                  SDE_AUDIO_CP_CHG_A_CPT)
7843 #define SDE_FDI_MASK_CPT        (SDE_FDI_RXC_CPT | \
7844                                  SDE_FDI_RXB_CPT | \
7845                                  SDE_FDI_RXA_CPT)
7846
7847 /* south display engine interrupt: ICP/TGP */
7848 #define SDE_TC6_HOTPLUG_TGP             (1 << 29)
7849 #define SDE_TC5_HOTPLUG_TGP             (1 << 28)
7850 #define SDE_TC4_HOTPLUG_ICP             (1 << 27)
7851 #define SDE_TC3_HOTPLUG_ICP             (1 << 26)
7852 #define SDE_TC2_HOTPLUG_ICP             (1 << 25)
7853 #define SDE_TC1_HOTPLUG_ICP             (1 << 24)
7854 #define SDE_GMBUS_ICP                   (1 << 23)
7855 #define SDE_DDIC_HOTPLUG_TGP            (1 << 18)
7856 #define SDE_DDIB_HOTPLUG_ICP            (1 << 17)
7857 #define SDE_DDIA_HOTPLUG_ICP            (1 << 16)
7858 #define SDE_TC_HOTPLUG_ICP(tc_port)     (1 << ((tc_port) + 24))
7859 #define SDE_DDI_HOTPLUG_ICP(port)       (1 << ((port) + 16))
7860 #define SDE_DDI_MASK_ICP                (SDE_DDIB_HOTPLUG_ICP | \
7861                                          SDE_DDIA_HOTPLUG_ICP)
7862 #define SDE_TC_MASK_ICP                 (SDE_TC4_HOTPLUG_ICP |  \
7863                                          SDE_TC3_HOTPLUG_ICP |  \
7864                                          SDE_TC2_HOTPLUG_ICP |  \
7865                                          SDE_TC1_HOTPLUG_ICP)
7866 #define SDE_DDI_MASK_TGP                (SDE_DDIC_HOTPLUG_TGP | \
7867                                          SDE_DDI_MASK_ICP)
7868 #define SDE_TC_MASK_TGP                 (SDE_TC6_HOTPLUG_TGP |  \
7869                                          SDE_TC5_HOTPLUG_TGP |  \
7870                                          SDE_TC_MASK_ICP)
7871
7872 #define SDEISR  _MMIO(0xc4000)
7873 #define SDEIMR  _MMIO(0xc4004)
7874 #define SDEIIR  _MMIO(0xc4008)
7875 #define SDEIER  _MMIO(0xc400c)
7876
7877 #define SERR_INT                        _MMIO(0xc4040)
7878 #define  SERR_INT_POISON                (1 << 31)
7879 #define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)     (1 << ((pipe) * 3))
7880
7881 /* digital port hotplug */
7882 #define PCH_PORT_HOTPLUG                _MMIO(0xc4030)  /* SHOTPLUG_CTL */
7883 #define  PORTA_HOTPLUG_ENABLE           (1 << 28) /* LPT:LP+ & BXT */
7884 #define  BXT_DDIA_HPD_INVERT            (1 << 27)
7885 #define  PORTA_HOTPLUG_STATUS_MASK      (3 << 24) /* SPT+ & BXT */
7886 #define  PORTA_HOTPLUG_NO_DETECT        (0 << 24) /* SPT+ & BXT */
7887 #define  PORTA_HOTPLUG_SHORT_DETECT     (1 << 24) /* SPT+ & BXT */
7888 #define  PORTA_HOTPLUG_LONG_DETECT      (2 << 24) /* SPT+ & BXT */
7889 #define  PORTD_HOTPLUG_ENABLE           (1 << 20)
7890 #define  PORTD_PULSE_DURATION_2ms       (0 << 18) /* pre-LPT */
7891 #define  PORTD_PULSE_DURATION_4_5ms     (1 << 18) /* pre-LPT */
7892 #define  PORTD_PULSE_DURATION_6ms       (2 << 18) /* pre-LPT */
7893 #define  PORTD_PULSE_DURATION_100ms     (3 << 18) /* pre-LPT */
7894 #define  PORTD_PULSE_DURATION_MASK      (3 << 18) /* pre-LPT */
7895 #define  PORTD_HOTPLUG_STATUS_MASK      (3 << 16)
7896 #define  PORTD_HOTPLUG_NO_DETECT        (0 << 16)
7897 #define  PORTD_HOTPLUG_SHORT_DETECT     (1 << 16)
7898 #define  PORTD_HOTPLUG_LONG_DETECT      (2 << 16)
7899 #define  PORTC_HOTPLUG_ENABLE           (1 << 12)
7900 #define  BXT_DDIC_HPD_INVERT            (1 << 11)
7901 #define  PORTC_PULSE_DURATION_2ms       (0 << 10) /* pre-LPT */
7902 #define  PORTC_PULSE_DURATION_4_5ms     (1 << 10) /* pre-LPT */
7903 #define  PORTC_PULSE_DURATION_6ms       (2 << 10) /* pre-LPT */
7904 #define  PORTC_PULSE_DURATION_100ms     (3 << 10) /* pre-LPT */
7905 #define  PORTC_PULSE_DURATION_MASK      (3 << 10) /* pre-LPT */
7906 #define  PORTC_HOTPLUG_STATUS_MASK      (3 << 8)
7907 #define  PORTC_HOTPLUG_NO_DETECT        (0 << 8)
7908 #define  PORTC_HOTPLUG_SHORT_DETECT     (1 << 8)
7909 #define  PORTC_HOTPLUG_LONG_DETECT      (2 << 8)
7910 #define  PORTB_HOTPLUG_ENABLE           (1 << 4)
7911 #define  BXT_DDIB_HPD_INVERT            (1 << 3)
7912 #define  PORTB_PULSE_DURATION_2ms       (0 << 2) /* pre-LPT */
7913 #define  PORTB_PULSE_DURATION_4_5ms     (1 << 2) /* pre-LPT */
7914 #define  PORTB_PULSE_DURATION_6ms       (2 << 2) /* pre-LPT */
7915 #define  PORTB_PULSE_DURATION_100ms     (3 << 2) /* pre-LPT */
7916 #define  PORTB_PULSE_DURATION_MASK      (3 << 2) /* pre-LPT */
7917 #define  PORTB_HOTPLUG_STATUS_MASK      (3 << 0)
7918 #define  PORTB_HOTPLUG_NO_DETECT        (0 << 0)
7919 #define  PORTB_HOTPLUG_SHORT_DETECT     (1 << 0)
7920 #define  PORTB_HOTPLUG_LONG_DETECT      (2 << 0)
7921 #define  BXT_DDI_HPD_INVERT_MASK        (BXT_DDIA_HPD_INVERT | \
7922                                         BXT_DDIB_HPD_INVERT | \
7923                                         BXT_DDIC_HPD_INVERT)
7924
7925 #define PCH_PORT_HOTPLUG2               _MMIO(0xc403C)  /* SHOTPLUG_CTL2 SPT+ */
7926 #define  PORTE_HOTPLUG_ENABLE           (1 << 4)
7927 #define  PORTE_HOTPLUG_STATUS_MASK      (3 << 0)
7928 #define  PORTE_HOTPLUG_NO_DETECT        (0 << 0)
7929 #define  PORTE_HOTPLUG_SHORT_DETECT     (1 << 0)
7930 #define  PORTE_HOTPLUG_LONG_DETECT      (2 << 0)
7931
7932 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
7933  * functionality covered in PCH_PORT_HOTPLUG is split into
7934  * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
7935  */
7936
7937 #define SHOTPLUG_CTL_DDI                        _MMIO(0xc4030)
7938 #define   TGP_DDIC_HPD_ENABLE                   (1 << 11)
7939 #define   TGP_DDIC_HPD_STATUS_MASK              (3 << 8)
7940 #define   TGP_DDIC_HPD_NO_DETECT                (0 << 8)
7941 #define   TGP_DDIC_HPD_SHORT_DETECT             (1 << 8)
7942 #define   TGP_DDIC_HPD_LONG_DETECT              (2 << 8)
7943 #define   TGP_DDIC_HPD_SHORT_LONG_DETECT        (3 << 8)
7944 #define   ICP_DDIB_HPD_ENABLE                   (1 << 7)
7945 #define   ICP_DDIB_HPD_STATUS_MASK              (3 << 4)
7946 #define   ICP_DDIB_HPD_NO_DETECT                (0 << 4)
7947 #define   ICP_DDIB_HPD_SHORT_DETECT             (1 << 4)
7948 #define   ICP_DDIB_HPD_LONG_DETECT              (2 << 4)
7949 #define   ICP_DDIB_HPD_SHORT_LONG_DETECT        (3 << 4)
7950 #define   ICP_DDIA_HPD_ENABLE                   (1 << 3)
7951 #define   ICP_DDIA_HPD_OP_DRIVE_1               (1 << 2)
7952 #define   ICP_DDIA_HPD_STATUS_MASK              (3 << 0)
7953 #define   ICP_DDIA_HPD_NO_DETECT                (0 << 0)
7954 #define   ICP_DDIA_HPD_SHORT_DETECT             (1 << 0)
7955 #define   ICP_DDIA_HPD_LONG_DETECT              (2 << 0)
7956 #define   ICP_DDIA_HPD_SHORT_LONG_DETECT        (3 << 0)
7957
7958 #define SHOTPLUG_CTL_TC                         _MMIO(0xc4034)
7959 #define   ICP_TC_HPD_ENABLE(tc_port)            (8 << (tc_port) * 4)
7960 /* Icelake DSC Rate Control Range Parameter Registers */
7961 #define DSCA_RC_RANGE_PARAMETERS_0              _MMIO(0x6B240)
7962 #define DSCA_RC_RANGE_PARAMETERS_0_UDW          _MMIO(0x6B240 + 4)
7963 #define DSCC_RC_RANGE_PARAMETERS_0              _MMIO(0x6BA40)
7964 #define DSCC_RC_RANGE_PARAMETERS_0_UDW          _MMIO(0x6BA40 + 4)
7965 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB      (0x78208)
7966 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB  (0x78208 + 4)
7967 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB      (0x78308)
7968 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB  (0x78308 + 4)
7969 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC      (0x78408)
7970 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC  (0x78408 + 4)
7971 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC      (0x78508)
7972 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC  (0x78508 + 4)
7973 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
7974                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
7975                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
7976 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
7977                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
7978                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
7979 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
7980                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
7981                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
7982 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
7983                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
7984                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
7985 #define RC_BPG_OFFSET_SHIFT                     10
7986 #define RC_MAX_QP_SHIFT                         5
7987 #define RC_MIN_QP_SHIFT                         0
7988
7989 #define DSCA_RC_RANGE_PARAMETERS_1              _MMIO(0x6B248)
7990 #define DSCA_RC_RANGE_PARAMETERS_1_UDW          _MMIO(0x6B248 + 4)
7991 #define DSCC_RC_RANGE_PARAMETERS_1              _MMIO(0x6BA48)
7992 #define DSCC_RC_RANGE_PARAMETERS_1_UDW          _MMIO(0x6BA48 + 4)
7993 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB      (0x78210)
7994 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB  (0x78210 + 4)
7995 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB      (0x78310)
7996 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB  (0x78310 + 4)
7997 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC      (0x78410)
7998 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC  (0x78410 + 4)
7999 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC      (0x78510)
8000 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC  (0x78510 + 4)
8001 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8002                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
8003                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
8004 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8005                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
8006                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
8007 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8008                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
8009                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
8010 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8011                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
8012                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
8013
8014 #define DSCA_RC_RANGE_PARAMETERS_2              _MMIO(0x6B250)
8015 #define DSCA_RC_RANGE_PARAMETERS_2_UDW          _MMIO(0x6B250 + 4)
8016 #define DSCC_RC_RANGE_PARAMETERS_2              _MMIO(0x6BA50)
8017 #define DSCC_RC_RANGE_PARAMETERS_2_UDW          _MMIO(0x6BA50 + 4)
8018 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB      (0x78218)
8019 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB  (0x78218 + 4)
8020 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB      (0x78318)
8021 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB  (0x78318 + 4)
8022 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC      (0x78418)
8023 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC  (0x78418 + 4)
8024 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC      (0x78518)
8025 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC  (0x78518 + 4)
8026 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8027                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
8028                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
8029 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8030                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
8031                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
8032 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8033                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
8034                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
8035 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8036                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
8037                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
8038
8039 #define DSCA_RC_RANGE_PARAMETERS_3              _MMIO(0x6B258)
8040 #define DSCA_RC_RANGE_PARAMETERS_3_UDW          _MMIO(0x6B258 + 4)
8041 #define DSCC_RC_RANGE_PARAMETERS_3              _MMIO(0x6BA58)
8042 #define DSCC_RC_RANGE_PARAMETERS_3_UDW          _MMIO(0x6BA58 + 4)
8043 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB      (0x78220)
8044 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB  (0x78220 + 4)
8045 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB      (0x78320)
8046 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB  (0x78320 + 4)
8047 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC      (0x78420)
8048 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC  (0x78420 + 4)
8049 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC      (0x78520)
8050 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC  (0x78520 + 4)
8051 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8052                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
8053                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
8054 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8055                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
8056                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
8057 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8058                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
8059                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
8060 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8061                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
8062                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
8063
8064 #define   ICP_TC_HPD_LONG_DETECT(tc_port)       (2 << (tc_port) * 4)
8065 #define   ICP_TC_HPD_SHORT_DETECT(tc_port)      (1 << (tc_port) * 4)
8066
8067 #define ICP_DDI_HPD_ENABLE_MASK         (ICP_DDIB_HPD_ENABLE |  \
8068                                          ICP_DDIA_HPD_ENABLE)
8069 #define ICP_TC_HPD_ENABLE_MASK          (ICP_TC_HPD_ENABLE(PORT_TC4) | \
8070                                          ICP_TC_HPD_ENABLE(PORT_TC3) | \
8071                                          ICP_TC_HPD_ENABLE(PORT_TC2) | \
8072                                          ICP_TC_HPD_ENABLE(PORT_TC1))
8073 #define TGP_DDI_HPD_ENABLE_MASK         (TGP_DDIC_HPD_ENABLE |  \
8074                                          ICP_DDI_HPD_ENABLE_MASK)
8075 #define TGP_TC_HPD_ENABLE_MASK          (ICP_TC_HPD_ENABLE(PORT_TC6) | \
8076                                          ICP_TC_HPD_ENABLE(PORT_TC5) | \
8077                                          ICP_TC_HPD_ENABLE_MASK)
8078
8079 #define _PCH_DPLL_A              0xc6014
8080 #define _PCH_DPLL_B              0xc6018
8081 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
8082
8083 #define _PCH_FPA0                0xc6040
8084 #define  FP_CB_TUNE             (0x3 << 22)
8085 #define _PCH_FPA1                0xc6044
8086 #define _PCH_FPB0                0xc6048
8087 #define _PCH_FPB1                0xc604c
8088 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8089 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
8090
8091 #define PCH_DPLL_TEST           _MMIO(0xc606c)
8092
8093 #define PCH_DREF_CONTROL        _MMIO(0xC6200)
8094 #define  DREF_CONTROL_MASK      0x7fc3
8095 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0 << 13)
8096 #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2 << 13)
8097 #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3 << 13)
8098 #define  DREF_CPU_SOURCE_OUTPUT_MASK            (3 << 13)
8099 #define  DREF_SSC_SOURCE_DISABLE                (0 << 11)
8100 #define  DREF_SSC_SOURCE_ENABLE                 (2 << 11)
8101 #define  DREF_SSC_SOURCE_MASK                   (3 << 11)
8102 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0 << 9)
8103 #define  DREF_NONSPREAD_CK505_ENABLE            (1 << 9)
8104 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2 << 9)
8105 #define  DREF_NONSPREAD_SOURCE_MASK             (3 << 9)
8106 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0 << 7)
8107 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2 << 7)
8108 #define  DREF_SUPERSPREAD_SOURCE_MASK           (3 << 7)
8109 #define  DREF_SSC4_DOWNSPREAD                   (0 << 6)
8110 #define  DREF_SSC4_CENTERSPREAD                 (1 << 6)
8111 #define  DREF_SSC1_DISABLE                      (0 << 1)
8112 #define  DREF_SSC1_ENABLE                       (1 << 1)
8113 #define  DREF_SSC4_DISABLE                      (0)
8114 #define  DREF_SSC4_ENABLE                       (1)
8115
8116 #define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
8117 #define  FDL_TP1_TIMER_SHIFT    12
8118 #define  FDL_TP1_TIMER_MASK     (3 << 12)
8119 #define  FDL_TP2_TIMER_SHIFT    10
8120 #define  FDL_TP2_TIMER_MASK     (3 << 10)
8121 #define  RAWCLK_FREQ_MASK       0x3ff
8122 #define  CNP_RAWCLK_DIV_MASK    (0x3ff << 16)
8123 #define  CNP_RAWCLK_DIV(div)    ((div) << 16)
8124 #define  CNP_RAWCLK_FRAC_MASK   (0xf << 26)
8125 #define  CNP_RAWCLK_DEN(den)    ((den) << 26)
8126 #define  ICP_RAWCLK_NUM(num)    ((num) << 11)
8127
8128 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
8129
8130 #define PCH_SSC4_PARMS          _MMIO(0xc6210)
8131 #define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
8132
8133 #define PCH_DPLL_SEL            _MMIO(0xc7000)
8134 #define  TRANS_DPLLB_SEL(pipe)          (1 << ((pipe) * 4))
8135 #define  TRANS_DPLLA_SEL(pipe)          0
8136 #define  TRANS_DPLL_ENABLE(pipe)        (1 << ((pipe) * 4 + 3))
8137
8138 /* transcoder */
8139
8140 #define _PCH_TRANS_HTOTAL_A             0xe0000
8141 #define  TRANS_HTOTAL_SHIFT             16
8142 #define  TRANS_HACTIVE_SHIFT            0
8143 #define _PCH_TRANS_HBLANK_A             0xe0004
8144 #define  TRANS_HBLANK_END_SHIFT         16
8145 #define  TRANS_HBLANK_START_SHIFT       0
8146 #define _PCH_TRANS_HSYNC_A              0xe0008
8147 #define  TRANS_HSYNC_END_SHIFT          16
8148 #define  TRANS_HSYNC_START_SHIFT        0
8149 #define _PCH_TRANS_VTOTAL_A             0xe000c
8150 #define  TRANS_VTOTAL_SHIFT             16
8151 #define  TRANS_VACTIVE_SHIFT            0
8152 #define _PCH_TRANS_VBLANK_A             0xe0010
8153 #define  TRANS_VBLANK_END_SHIFT         16
8154 #define  TRANS_VBLANK_START_SHIFT       0
8155 #define _PCH_TRANS_VSYNC_A              0xe0014
8156 #define  TRANS_VSYNC_END_SHIFT          16
8157 #define  TRANS_VSYNC_START_SHIFT        0
8158 #define _PCH_TRANS_VSYNCSHIFT_A         0xe0028
8159
8160 #define _PCH_TRANSA_DATA_M1     0xe0030
8161 #define _PCH_TRANSA_DATA_N1     0xe0034
8162 #define _PCH_TRANSA_DATA_M2     0xe0038
8163 #define _PCH_TRANSA_DATA_N2     0xe003c
8164 #define _PCH_TRANSA_LINK_M1     0xe0040
8165 #define _PCH_TRANSA_LINK_N1     0xe0044
8166 #define _PCH_TRANSA_LINK_M2     0xe0048
8167 #define _PCH_TRANSA_LINK_N2     0xe004c
8168
8169 /* Per-transcoder DIP controls (PCH) */
8170 #define _VIDEO_DIP_CTL_A         0xe0200
8171 #define _VIDEO_DIP_DATA_A        0xe0208
8172 #define _VIDEO_DIP_GCP_A         0xe0210
8173 #define  GCP_COLOR_INDICATION           (1 << 2)
8174 #define  GCP_DEFAULT_PHASE_ENABLE       (1 << 1)
8175 #define  GCP_AV_MUTE                    (1 << 0)
8176
8177 #define _VIDEO_DIP_CTL_B         0xe1200
8178 #define _VIDEO_DIP_DATA_B        0xe1208
8179 #define _VIDEO_DIP_GCP_B         0xe1210
8180
8181 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
8182 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
8183 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
8184
8185 /* Per-transcoder DIP controls (VLV) */
8186 #define _VLV_VIDEO_DIP_CTL_A            (VLV_DISPLAY_BASE + 0x60200)
8187 #define _VLV_VIDEO_DIP_DATA_A           (VLV_DISPLAY_BASE + 0x60208)
8188 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A   (VLV_DISPLAY_BASE + 0x60210)
8189
8190 #define _VLV_VIDEO_DIP_CTL_B            (VLV_DISPLAY_BASE + 0x61170)
8191 #define _VLV_VIDEO_DIP_DATA_B           (VLV_DISPLAY_BASE + 0x61174)
8192 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B   (VLV_DISPLAY_BASE + 0x61178)
8193
8194 #define _CHV_VIDEO_DIP_CTL_C            (VLV_DISPLAY_BASE + 0x611f0)
8195 #define _CHV_VIDEO_DIP_DATA_C           (VLV_DISPLAY_BASE + 0x611f4)
8196 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C   (VLV_DISPLAY_BASE + 0x611f8)
8197
8198 #define VLV_TVIDEO_DIP_CTL(pipe) \
8199         _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
8200                _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
8201 #define VLV_TVIDEO_DIP_DATA(pipe) \
8202         _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
8203                _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
8204 #define VLV_TVIDEO_DIP_GCP(pipe) \
8205         _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
8206                 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
8207
8208 /* Haswell DIP controls */
8209
8210 #define _HSW_VIDEO_DIP_CTL_A            0x60200
8211 #define _HSW_VIDEO_DIP_AVI_DATA_A       0x60220
8212 #define _HSW_VIDEO_DIP_VS_DATA_A        0x60260
8213 #define _HSW_VIDEO_DIP_SPD_DATA_A       0x602A0
8214 #define _HSW_VIDEO_DIP_GMP_DATA_A       0x602E0
8215 #define _HSW_VIDEO_DIP_VSC_DATA_A       0x60320
8216 #define _GLK_VIDEO_DIP_DRM_DATA_A       0x60440
8217 #define _HSW_VIDEO_DIP_AVI_ECC_A        0x60240
8218 #define _HSW_VIDEO_DIP_VS_ECC_A         0x60280
8219 #define _HSW_VIDEO_DIP_SPD_ECC_A        0x602C0
8220 #define _HSW_VIDEO_DIP_GMP_ECC_A        0x60300
8221 #define _HSW_VIDEO_DIP_VSC_ECC_A        0x60344
8222 #define _HSW_VIDEO_DIP_GCP_A            0x60210
8223
8224 #define _HSW_VIDEO_DIP_CTL_B            0x61200
8225 #define _HSW_VIDEO_DIP_AVI_DATA_B       0x61220
8226 #define _HSW_VIDEO_DIP_VS_DATA_B        0x61260
8227 #define _HSW_VIDEO_DIP_SPD_DATA_B       0x612A0
8228 #define _HSW_VIDEO_DIP_GMP_DATA_B       0x612E0
8229 #define _HSW_VIDEO_DIP_VSC_DATA_B       0x61320
8230 #define _GLK_VIDEO_DIP_DRM_DATA_B       0x61440
8231 #define _HSW_VIDEO_DIP_BVI_ECC_B        0x61240
8232 #define _HSW_VIDEO_DIP_VS_ECC_B         0x61280
8233 #define _HSW_VIDEO_DIP_SPD_ECC_B        0x612C0
8234 #define _HSW_VIDEO_DIP_GMP_ECC_B        0x61300
8235 #define _HSW_VIDEO_DIP_VSC_ECC_B        0x61344
8236 #define _HSW_VIDEO_DIP_GCP_B            0x61210
8237
8238 /* Icelake PPS_DATA and _ECC DIP Registers.
8239  * These are available for transcoders B,C and eDP.
8240  * Adding the _A so as to reuse the _MMIO_TRANS2
8241  * definition, with which it offsets to the right location.
8242  */
8243
8244 #define _ICL_VIDEO_DIP_PPS_DATA_A       0x60350
8245 #define _ICL_VIDEO_DIP_PPS_DATA_B       0x61350
8246 #define _ICL_VIDEO_DIP_PPS_ECC_A        0x603D4
8247 #define _ICL_VIDEO_DIP_PPS_ECC_B        0x613D4
8248
8249 #define HSW_TVIDEO_DIP_CTL(trans)               _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
8250 #define HSW_TVIDEO_DIP_GCP(trans)               _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
8251 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i)       _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8252 #define HSW_TVIDEO_DIP_VS_DATA(trans, i)        _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8253 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)       _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
8254 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i)       _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
8255 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i)       _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
8256 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i)       _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
8257 #define ICL_VIDEO_DIP_PPS_DATA(trans, i)        _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8258 #define ICL_VIDEO_DIP_PPS_ECC(trans, i)         _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8259
8260 #define _HSW_STEREO_3D_CTL_A            0x70020
8261 #define   S3D_ENABLE                    (1 << 31)
8262 #define _HSW_STEREO_3D_CTL_B            0x71020
8263
8264 #define HSW_STEREO_3D_CTL(trans)        _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
8265
8266 #define _PCH_TRANS_HTOTAL_B          0xe1000
8267 #define _PCH_TRANS_HBLANK_B          0xe1004
8268 #define _PCH_TRANS_HSYNC_B           0xe1008
8269 #define _PCH_TRANS_VTOTAL_B          0xe100c
8270 #define _PCH_TRANS_VBLANK_B          0xe1010
8271 #define _PCH_TRANS_VSYNC_B           0xe1014
8272 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8273
8274 #define PCH_TRANS_HTOTAL(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8275 #define PCH_TRANS_HBLANK(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8276 #define PCH_TRANS_HSYNC(pipe)           _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8277 #define PCH_TRANS_VTOTAL(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8278 #define PCH_TRANS_VBLANK(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8279 #define PCH_TRANS_VSYNC(pipe)           _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8280 #define PCH_TRANS_VSYNCSHIFT(pipe)      _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
8281
8282 #define _PCH_TRANSB_DATA_M1     0xe1030
8283 #define _PCH_TRANSB_DATA_N1     0xe1034
8284 #define _PCH_TRANSB_DATA_M2     0xe1038
8285 #define _PCH_TRANSB_DATA_N2     0xe103c
8286 #define _PCH_TRANSB_LINK_M1     0xe1040
8287 #define _PCH_TRANSB_LINK_N1     0xe1044
8288 #define _PCH_TRANSB_LINK_M2     0xe1048
8289 #define _PCH_TRANSB_LINK_N2     0xe104c
8290
8291 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
8292 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
8293 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
8294 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
8295 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
8296 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8297 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8298 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8299
8300 #define _PCH_TRANSACONF              0xf0008
8301 #define _PCH_TRANSBCONF              0xf1008
8302 #define PCH_TRANSCONF(pipe)     _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8303 #define LPT_TRANSCONF           PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
8304 #define  TRANS_DISABLE          (0 << 31)
8305 #define  TRANS_ENABLE           (1 << 31)
8306 #define  TRANS_STATE_MASK       (1 << 30)
8307 #define  TRANS_STATE_DISABLE    (0 << 30)
8308 #define  TRANS_STATE_ENABLE     (1 << 30)
8309 #define  TRANS_FSYNC_DELAY_HB1  (0 << 27)
8310 #define  TRANS_FSYNC_DELAY_HB2  (1 << 27)
8311 #define  TRANS_FSYNC_DELAY_HB3  (2 << 27)
8312 #define  TRANS_FSYNC_DELAY_HB4  (3 << 27)
8313 #define  TRANS_INTERLACE_MASK   (7 << 21)
8314 #define  TRANS_PROGRESSIVE      (0 << 21)
8315 #define  TRANS_INTERLACED       (3 << 21)
8316 #define  TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8317 #define  TRANS_8BPC             (0 << 5)
8318 #define  TRANS_10BPC            (1 << 5)
8319 #define  TRANS_6BPC             (2 << 5)
8320 #define  TRANS_12BPC            (3 << 5)
8321
8322 #define _TRANSA_CHICKEN1         0xf0060
8323 #define _TRANSB_CHICKEN1         0xf1060
8324 #define TRANS_CHICKEN1(pipe)    _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8325 #define  TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE     (1 << 10)
8326 #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE      (1 << 4)
8327 #define _TRANSA_CHICKEN2         0xf0064
8328 #define _TRANSB_CHICKEN2         0xf1064
8329 #define TRANS_CHICKEN2(pipe)    _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8330 #define  TRANS_CHICKEN2_TIMING_OVERRIDE                 (1 << 31)
8331 #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED           (1 << 29)
8332 #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK          (3 << 27)
8333 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER      (1 << 26)
8334 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH   (1 << 25)
8335
8336 #define SOUTH_CHICKEN1          _MMIO(0xc2000)
8337 #define  FDIA_PHASE_SYNC_SHIFT_OVR      19
8338 #define  FDIA_PHASE_SYNC_SHIFT_EN       18
8339 #define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8340 #define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8341 #define  FDI_BC_BIFURCATION_SELECT      (1 << 12)
8342 #define  CHASSIS_CLK_REQ_DURATION_MASK  (0xf << 8)
8343 #define  CHASSIS_CLK_REQ_DURATION(x)    ((x) << 8)
8344 #define  SPT_PWM_GRANULARITY            (1 << 0)
8345 #define SOUTH_CHICKEN2          _MMIO(0xc2004)
8346 #define  FDI_MPHY_IOSFSB_RESET_STATUS   (1 << 13)
8347 #define  FDI_MPHY_IOSFSB_RESET_CTL      (1 << 12)
8348 #define  LPT_PWM_GRANULARITY            (1 << 5)
8349 #define  DPLS_EDP_PPS_FIX_DIS           (1 << 0)
8350
8351 #define _FDI_RXA_CHICKEN        0xc200c
8352 #define _FDI_RXB_CHICKEN        0xc2010
8353 #define  FDI_RX_PHASE_SYNC_POINTER_OVR  (1 << 1)
8354 #define  FDI_RX_PHASE_SYNC_POINTER_EN   (1 << 0)
8355 #define FDI_RX_CHICKEN(pipe)    _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8356
8357 #define SOUTH_DSPCLK_GATE_D     _MMIO(0xc2020)
8358 #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8359 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8360 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8361 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8362 #define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8363 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
8364
8365 /* CPU: FDI_TX */
8366 #define _FDI_TXA_CTL            0x60100
8367 #define _FDI_TXB_CTL            0x61100
8368 #define FDI_TX_CTL(pipe)        _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8369 #define  FDI_TX_DISABLE         (0 << 31)
8370 #define  FDI_TX_ENABLE          (1 << 31)
8371 #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
8372 #define  FDI_LINK_TRAIN_PATTERN_2       (1 << 28)
8373 #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2 << 28)
8374 #define  FDI_LINK_TRAIN_NONE            (3 << 28)
8375 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
8376 #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1 << 25)
8377 #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2 << 25)
8378 #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3 << 25)
8379 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8380 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8381 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2 << 22)
8382 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3 << 22)
8383 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8384    SNB has different settings. */
8385 /* SNB A-stepping */
8386 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A         (0x38 << 22)
8387 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A         (0x02 << 22)
8388 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01 << 22)
8389 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A         (0x0 << 22)
8390 /* SNB B-stepping */
8391 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B         (0x0 << 22)
8392 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B         (0x3a << 22)
8393 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B       (0x39 << 22)
8394 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B         (0x38 << 22)
8395 #define  FDI_LINK_TRAIN_VOL_EMP_MASK            (0x3f << 22)
8396 #define  FDI_DP_PORT_WIDTH_SHIFT                19
8397 #define  FDI_DP_PORT_WIDTH_MASK                 (7 << FDI_DP_PORT_WIDTH_SHIFT)
8398 #define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8399 #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1 << 18)
8400 /* Ironlake: hardwired to 1 */
8401 #define  FDI_TX_PLL_ENABLE              (1 << 14)
8402
8403 /* Ivybridge has different bits for lolz */
8404 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
8405 #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1 << 8)
8406 #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2 << 8)
8407 #define  FDI_LINK_TRAIN_NONE_IVB            (3 << 8)
8408
8409 /* both Tx and Rx */
8410 #define  FDI_COMPOSITE_SYNC             (1 << 11)
8411 #define  FDI_LINK_TRAIN_AUTO            (1 << 10)
8412 #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
8413 #define  FDI_SCRAMBLING_DISABLE         (1 << 7)
8414
8415 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8416 #define _FDI_RXA_CTL             0xf000c
8417 #define _FDI_RXB_CTL             0xf100c
8418 #define FDI_RX_CTL(pipe)        _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8419 #define  FDI_RX_ENABLE          (1 << 31)
8420 /* train, dp width same as FDI_TX */
8421 #define  FDI_FS_ERRC_ENABLE             (1 << 27)
8422 #define  FDI_FE_ERRC_ENABLE             (1 << 26)
8423 #define  FDI_RX_POLARITY_REVERSED_LPT   (1 << 16)
8424 #define  FDI_8BPC                       (0 << 16)
8425 #define  FDI_10BPC                      (1 << 16)
8426 #define  FDI_6BPC                       (2 << 16)
8427 #define  FDI_12BPC                      (3 << 16)
8428 #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1 << 15)
8429 #define  FDI_DMI_LINK_REVERSE_MASK      (1 << 14)
8430 #define  FDI_RX_PLL_ENABLE              (1 << 13)
8431 #define  FDI_FS_ERR_CORRECT_ENABLE      (1 << 11)
8432 #define  FDI_FE_ERR_CORRECT_ENABLE      (1 << 10)
8433 #define  FDI_FS_ERR_REPORT_ENABLE       (1 << 9)
8434 #define  FDI_FE_ERR_REPORT_ENABLE       (1 << 8)
8435 #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1 << 6)
8436 #define  FDI_PCDCLK                     (1 << 4)
8437 /* CPT */
8438 #define  FDI_AUTO_TRAINING                      (1 << 10)
8439 #define  FDI_LINK_TRAIN_PATTERN_1_CPT           (0 << 8)
8440 #define  FDI_LINK_TRAIN_PATTERN_2_CPT           (1 << 8)
8441 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT        (2 << 8)
8442 #define  FDI_LINK_TRAIN_NORMAL_CPT              (3 << 8)
8443 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT        (3 << 8)
8444
8445 #define _FDI_RXA_MISC                   0xf0010
8446 #define _FDI_RXB_MISC                   0xf1010
8447 #define  FDI_RX_PWRDN_LANE1_MASK        (3 << 26)
8448 #define  FDI_RX_PWRDN_LANE1_VAL(x)      ((x) << 26)
8449 #define  FDI_RX_PWRDN_LANE0_MASK        (3 << 24)
8450 #define  FDI_RX_PWRDN_LANE0_VAL(x)      ((x) << 24)
8451 #define  FDI_RX_TP1_TO_TP2_48           (2 << 20)
8452 #define  FDI_RX_TP1_TO_TP2_64           (3 << 20)
8453 #define  FDI_RX_FDI_DELAY_90            (0x90 << 0)
8454 #define FDI_RX_MISC(pipe)       _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
8455
8456 #define _FDI_RXA_TUSIZE1        0xf0030
8457 #define _FDI_RXA_TUSIZE2        0xf0038
8458 #define _FDI_RXB_TUSIZE1        0xf1030
8459 #define _FDI_RXB_TUSIZE2        0xf1038
8460 #define FDI_RX_TUSIZE1(pipe)    _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
8461 #define FDI_RX_TUSIZE2(pipe)    _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
8462
8463 /* FDI_RX interrupt register format */
8464 #define FDI_RX_INTER_LANE_ALIGN         (1 << 10)
8465 #define FDI_RX_SYMBOL_LOCK              (1 << 9) /* train 2 */
8466 #define FDI_RX_BIT_LOCK                 (1 << 8) /* train 1 */
8467 #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1 << 7)
8468 #define FDI_RX_FS_CODE_ERR              (1 << 6)
8469 #define FDI_RX_FE_CODE_ERR              (1 << 5)
8470 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1 << 4)
8471 #define FDI_RX_HDCP_LINK_FAIL           (1 << 3)
8472 #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1 << 2)
8473 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1 << 1)
8474 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
8475
8476 #define _FDI_RXA_IIR            0xf0014
8477 #define _FDI_RXA_IMR            0xf0018
8478 #define _FDI_RXB_IIR            0xf1014
8479 #define _FDI_RXB_IMR            0xf1018
8480 #define FDI_RX_IIR(pipe)        _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
8481 #define FDI_RX_IMR(pipe)        _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
8482
8483 #define FDI_PLL_CTL_1           _MMIO(0xfe000)
8484 #define FDI_PLL_CTL_2           _MMIO(0xfe004)
8485
8486 #define PCH_LVDS        _MMIO(0xe1180)
8487 #define  LVDS_DETECTED  (1 << 1)
8488
8489 #define _PCH_DP_B               0xe4100
8490 #define PCH_DP_B                _MMIO(_PCH_DP_B)
8491 #define _PCH_DPB_AUX_CH_CTL     0xe4110
8492 #define _PCH_DPB_AUX_CH_DATA1   0xe4114
8493 #define _PCH_DPB_AUX_CH_DATA2   0xe4118
8494 #define _PCH_DPB_AUX_CH_DATA3   0xe411c
8495 #define _PCH_DPB_AUX_CH_DATA4   0xe4120
8496 #define _PCH_DPB_AUX_CH_DATA5   0xe4124
8497
8498 #define _PCH_DP_C               0xe4200
8499 #define PCH_DP_C                _MMIO(_PCH_DP_C)
8500 #define _PCH_DPC_AUX_CH_CTL     0xe4210
8501 #define _PCH_DPC_AUX_CH_DATA1   0xe4214
8502 #define _PCH_DPC_AUX_CH_DATA2   0xe4218
8503 #define _PCH_DPC_AUX_CH_DATA3   0xe421c
8504 #define _PCH_DPC_AUX_CH_DATA4   0xe4220
8505 #define _PCH_DPC_AUX_CH_DATA5   0xe4224
8506
8507 #define _PCH_DP_D               0xe4300
8508 #define PCH_DP_D                _MMIO(_PCH_DP_D)
8509 #define _PCH_DPD_AUX_CH_CTL     0xe4310
8510 #define _PCH_DPD_AUX_CH_DATA1   0xe4314
8511 #define _PCH_DPD_AUX_CH_DATA2   0xe4318
8512 #define _PCH_DPD_AUX_CH_DATA3   0xe431c
8513 #define _PCH_DPD_AUX_CH_DATA4   0xe4320
8514 #define _PCH_DPD_AUX_CH_DATA5   0xe4324
8515
8516 #define PCH_DP_AUX_CH_CTL(aux_ch)               _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
8517 #define PCH_DP_AUX_CH_DATA(aux_ch, i)   _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
8518
8519 /* CPT */
8520 #define _TRANS_DP_CTL_A         0xe0300
8521 #define _TRANS_DP_CTL_B         0xe1300
8522 #define _TRANS_DP_CTL_C         0xe2300
8523 #define TRANS_DP_CTL(pipe)      _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8524 #define  TRANS_DP_OUTPUT_ENABLE (1 << 31)
8525 #define  TRANS_DP_PORT_SEL_MASK         (3 << 29)
8526 #define  TRANS_DP_PORT_SEL_NONE         (3 << 29)
8527 #define  TRANS_DP_PORT_SEL(port)        (((port) - PORT_B) << 29)
8528 #define  TRANS_DP_AUDIO_ONLY    (1 << 26)
8529 #define  TRANS_DP_ENH_FRAMING   (1 << 18)
8530 #define  TRANS_DP_8BPC          (0 << 9)
8531 #define  TRANS_DP_10BPC         (1 << 9)
8532 #define  TRANS_DP_6BPC          (2 << 9)
8533 #define  TRANS_DP_12BPC         (3 << 9)
8534 #define  TRANS_DP_BPC_MASK      (3 << 9)
8535 #define  TRANS_DP_VSYNC_ACTIVE_HIGH     (1 << 4)
8536 #define  TRANS_DP_VSYNC_ACTIVE_LOW      0
8537 #define  TRANS_DP_HSYNC_ACTIVE_HIGH     (1 << 3)
8538 #define  TRANS_DP_HSYNC_ACTIVE_LOW      0
8539 #define  TRANS_DP_SYNC_MASK     (3 << 3)
8540
8541 /* SNB eDP training params */
8542 /* SNB A-stepping */
8543 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A         (0x38 << 22)
8544 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A         (0x02 << 22)
8545 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01 << 22)
8546 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A         (0x0 << 22)
8547 /* SNB B-stepping */
8548 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B     (0x0 << 22)
8549 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B       (0x1 << 22)
8550 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B     (0x3a << 22)
8551 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B   (0x39 << 22)
8552 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B    (0x38 << 22)
8553 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB        (0x3f << 22)
8554
8555 /* IVB */
8556 #define EDP_LINK_TRAIN_400MV_0DB_IVB            (0x24 << 22)
8557 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB          (0x2a << 22)
8558 #define EDP_LINK_TRAIN_400MV_6DB_IVB            (0x2f << 22)
8559 #define EDP_LINK_TRAIN_600MV_0DB_IVB            (0x30 << 22)
8560 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB          (0x36 << 22)
8561 #define EDP_LINK_TRAIN_800MV_0DB_IVB            (0x38 << 22)
8562 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB          (0x3e << 22)
8563
8564 /* legacy values */
8565 #define EDP_LINK_TRAIN_500MV_0DB_IVB            (0x00 << 22)
8566 #define EDP_LINK_TRAIN_1000MV_0DB_IVB           (0x20 << 22)
8567 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB          (0x02 << 22)
8568 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB         (0x22 << 22)
8569 #define EDP_LINK_TRAIN_1000MV_6DB_IVB           (0x23 << 22)
8570
8571 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB        (0x3f << 22)
8572
8573 #define  VLV_PMWGICZ                            _MMIO(0x1300a4)
8574
8575 #define  RC6_LOCATION                           _MMIO(0xD40)
8576 #define    RC6_CTX_IN_DRAM                      (1 << 0)
8577 #define  RC6_CTX_BASE                           _MMIO(0xD48)
8578 #define    RC6_CTX_BASE_MASK                    0xFFFFFFF0
8579 #define  PWRCTX_MAXCNT_RCSUNIT                  _MMIO(0x2054)
8580 #define  PWRCTX_MAXCNT_VCSUNIT0                 _MMIO(0x12054)
8581 #define  PWRCTX_MAXCNT_BCSUNIT                  _MMIO(0x22054)
8582 #define  PWRCTX_MAXCNT_VECSUNIT                 _MMIO(0x1A054)
8583 #define  PWRCTX_MAXCNT_VCSUNIT1                 _MMIO(0x1C054)
8584 #define    IDLE_TIME_MASK                       0xFFFFF
8585 #define  FORCEWAKE                              _MMIO(0xA18C)
8586 #define  FORCEWAKE_VLV                          _MMIO(0x1300b0)
8587 #define  FORCEWAKE_ACK_VLV                      _MMIO(0x1300b4)
8588 #define  FORCEWAKE_MEDIA_VLV                    _MMIO(0x1300b8)
8589 #define  FORCEWAKE_ACK_MEDIA_VLV                _MMIO(0x1300bc)
8590 #define  FORCEWAKE_ACK_HSW                      _MMIO(0x130044)
8591 #define  FORCEWAKE_ACK                          _MMIO(0x130090)
8592 #define  VLV_GTLC_WAKE_CTRL                     _MMIO(0x130090)
8593 #define   VLV_GTLC_RENDER_CTX_EXISTS            (1 << 25)
8594 #define   VLV_GTLC_MEDIA_CTX_EXISTS             (1 << 24)
8595 #define   VLV_GTLC_ALLOWWAKEREQ                 (1 << 0)
8596
8597 #define  VLV_GTLC_PW_STATUS                     _MMIO(0x130094)
8598 #define   VLV_GTLC_ALLOWWAKEACK                 (1 << 0)
8599 #define   VLV_GTLC_ALLOWWAKEERR                 (1 << 1)
8600 #define   VLV_GTLC_PW_MEDIA_STATUS_MASK         (1 << 5)
8601 #define   VLV_GTLC_PW_RENDER_STATUS_MASK        (1 << 7)
8602 #define  FORCEWAKE_MT                           _MMIO(0xa188) /* multi-threaded */
8603 #define  FORCEWAKE_MEDIA_GEN9                   _MMIO(0xa270)
8604 #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)         _MMIO(0xa540 + (n) * 4)
8605 #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)         _MMIO(0xa560 + (n) * 4)
8606 #define  FORCEWAKE_RENDER_GEN9                  _MMIO(0xa278)
8607 #define  FORCEWAKE_BLITTER_GEN9                 _MMIO(0xa188)
8608 #define  FORCEWAKE_ACK_MEDIA_GEN9               _MMIO(0x0D88)
8609 #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)     _MMIO(0x0D50 + (n) * 4)
8610 #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)     _MMIO(0x0D70 + (n) * 4)
8611 #define  FORCEWAKE_ACK_RENDER_GEN9              _MMIO(0x0D84)
8612 #define  FORCEWAKE_ACK_BLITTER_GEN9             _MMIO(0x130044)
8613 #define   FORCEWAKE_KERNEL                      BIT(0)
8614 #define   FORCEWAKE_USER                        BIT(1)
8615 #define   FORCEWAKE_KERNEL_FALLBACK             BIT(15)
8616 #define  FORCEWAKE_MT_ACK                       _MMIO(0x130040)
8617 #define  ECOBUS                                 _MMIO(0xa180)
8618 #define    FORCEWAKE_MT_ENABLE                  (1 << 5)
8619 #define  VLV_SPAREG2H                           _MMIO(0xA194)
8620 #define  GEN9_PWRGT_DOMAIN_STATUS               _MMIO(0xA2A0)
8621 #define   GEN9_PWRGT_MEDIA_STATUS_MASK          (1 << 0)
8622 #define   GEN9_PWRGT_RENDER_STATUS_MASK         (1 << 1)
8623
8624 #define  GTFIFODBG                              _MMIO(0x120000)
8625 #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV    (0x1f << 20)
8626 #define    GT_FIFO_FREE_ENTRIES_CHV             (0x7f << 13)
8627 #define    GT_FIFO_SBDROPERR                    (1 << 6)
8628 #define    GT_FIFO_BLOBDROPERR                  (1 << 5)
8629 #define    GT_FIFO_SB_READ_ABORTERR             (1 << 4)
8630 #define    GT_FIFO_DROPERR                      (1 << 3)
8631 #define    GT_FIFO_OVFERR                       (1 << 2)
8632 #define    GT_FIFO_IAWRERR                      (1 << 1)
8633 #define    GT_FIFO_IARDERR                      (1 << 0)
8634
8635 #define  GTFIFOCTL                              _MMIO(0x120008)
8636 #define    GT_FIFO_FREE_ENTRIES_MASK            0x7f
8637 #define    GT_FIFO_NUM_RESERVED_ENTRIES         20
8638 #define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1 << 12)
8639 #define    GT_FIFO_CTL_RC6_POLICY_STALL         (1 << 11)
8640
8641 #define  HSW_IDICR                              _MMIO(0x9008)
8642 #define    IDIHASHMSK(x)                        (((x) & 0x3f) << 16)
8643 #define  HSW_EDRAM_CAP                          _MMIO(0x120010)
8644 #define    EDRAM_ENABLED                        0x1
8645 #define    EDRAM_NUM_BANKS(cap)                 (((cap) >> 1) & 0xf)
8646 #define    EDRAM_WAYS_IDX(cap)                  (((cap) >> 5) & 0x7)
8647 #define    EDRAM_SETS_IDX(cap)                  (((cap) >> 8) & 0x3)
8648
8649 #define GEN6_UCGCTL1                            _MMIO(0x9400)
8650 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE                (1 << 22)
8651 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE              (1 << 16)
8652 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE                (1 << 5)
8653 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE                 (1 << 7)
8654
8655 #define GEN6_UCGCTL2                            _MMIO(0x9404)
8656 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE                 (1 << 31)
8657 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE                (1 << 30)
8658 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE                (1 << 22)
8659 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE                (1 << 13)
8660 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE               (1 << 12)
8661 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE                (1 << 11)
8662
8663 #define GEN6_UCGCTL3                            _MMIO(0x9408)
8664 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE               (1 << 20)
8665
8666 #define GEN7_UCGCTL4                            _MMIO(0x940c)
8667 #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE       (1 << 25)
8668 #define  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE      (1 << 14)
8669
8670 #define GEN6_RCGCTL1                            _MMIO(0x9410)
8671 #define GEN6_RCGCTL2                            _MMIO(0x9414)
8672 #define GEN6_RSTCTL                             _MMIO(0x9420)
8673
8674 #define GEN8_UCGCTL6                            _MMIO(0x9430)
8675 #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE      (1 << 24)
8676 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE       (1 << 14)
8677 #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
8678
8679 #define GEN6_GFXPAUSE                           _MMIO(0xA000)
8680 #define GEN6_RPNSWREQ                           _MMIO(0xA008)
8681 #define   GEN6_TURBO_DISABLE                    (1 << 31)
8682 #define   GEN6_FREQUENCY(x)                     ((x) << 25)
8683 #define   HSW_FREQUENCY(x)                      ((x) << 24)
8684 #define   GEN9_FREQUENCY(x)                     ((x) << 23)
8685 #define   GEN6_OFFSET(x)                        ((x) << 19)
8686 #define   GEN6_AGGRESSIVE_TURBO                 (0 << 15)
8687 #define GEN6_RC_VIDEO_FREQ                      _MMIO(0xA00C)
8688 #define GEN6_RC_CONTROL                         _MMIO(0xA090)
8689 #define   GEN6_RC_CTL_RC6pp_ENABLE              (1 << 16)
8690 #define   GEN6_RC_CTL_RC6p_ENABLE               (1 << 17)
8691 #define   GEN6_RC_CTL_RC6_ENABLE                (1 << 18)
8692 #define   GEN6_RC_CTL_RC1e_ENABLE               (1 << 20)
8693 #define   GEN6_RC_CTL_RC7_ENABLE                (1 << 22)
8694 #define   VLV_RC_CTL_CTX_RST_PARALLEL           (1 << 24)
8695 #define   GEN7_RC_CTL_TO_MODE                   (1 << 28)
8696 #define   GEN6_RC_CTL_EI_MODE(x)                ((x) << 27)
8697 #define   GEN6_RC_CTL_HW_ENABLE                 (1 << 31)
8698 #define GEN6_RP_DOWN_TIMEOUT                    _MMIO(0xA010)
8699 #define GEN6_RP_INTERRUPT_LIMITS                _MMIO(0xA014)
8700 #define GEN6_RPSTAT1                            _MMIO(0xA01C)
8701 #define   GEN6_CAGF_SHIFT                       8
8702 #define   HSW_CAGF_SHIFT                        7
8703 #define   GEN9_CAGF_SHIFT                       23
8704 #define   GEN6_CAGF_MASK                        (0x7f << GEN6_CAGF_SHIFT)
8705 #define   HSW_CAGF_MASK                         (0x7f << HSW_CAGF_SHIFT)
8706 #define   GEN9_CAGF_MASK                        (0x1ff << GEN9_CAGF_SHIFT)
8707 #define GEN6_RP_CONTROL                         _MMIO(0xA024)
8708 #define   GEN6_RP_MEDIA_TURBO                   (1 << 11)
8709 #define   GEN6_RP_MEDIA_MODE_MASK               (3 << 9)
8710 #define   GEN6_RP_MEDIA_HW_TURBO_MODE           (3 << 9)
8711 #define   GEN6_RP_MEDIA_HW_NORMAL_MODE          (2 << 9)
8712 #define   GEN6_RP_MEDIA_HW_MODE                 (1 << 9)
8713 #define   GEN6_RP_MEDIA_SW_MODE                 (0 << 9)
8714 #define   GEN6_RP_MEDIA_IS_GFX                  (1 << 8)
8715 #define   GEN6_RP_ENABLE                        (1 << 7)
8716 #define   GEN6_RP_UP_IDLE_MIN                   (0x1 << 3)
8717 #define   GEN6_RP_UP_BUSY_AVG                   (0x2 << 3)
8718 #define   GEN6_RP_UP_BUSY_CONT                  (0x4 << 3)
8719 #define   GEN6_RP_DOWN_IDLE_AVG                 (0x2 << 0)
8720 #define   GEN6_RP_DOWN_IDLE_CONT                (0x1 << 0)
8721 #define GEN6_RP_UP_THRESHOLD                    _MMIO(0xA02C)
8722 #define GEN6_RP_DOWN_THRESHOLD                  _MMIO(0xA030)
8723 #define GEN6_RP_CUR_UP_EI                       _MMIO(0xA050)
8724 #define   GEN6_RP_EI_MASK                       0xffffff
8725 #define   GEN6_CURICONT_MASK                    GEN6_RP_EI_MASK
8726 #define GEN6_RP_CUR_UP                          _MMIO(0xA054)
8727 #define   GEN6_CURBSYTAVG_MASK                  GEN6_RP_EI_MASK
8728 #define GEN6_RP_PREV_UP                         _MMIO(0xA058)
8729 #define GEN6_RP_CUR_DOWN_EI                     _MMIO(0xA05C)
8730 #define   GEN6_CURIAVG_MASK                     GEN6_RP_EI_MASK
8731 #define GEN6_RP_CUR_DOWN                        _MMIO(0xA060)
8732 #define GEN6_RP_PREV_DOWN                       _MMIO(0xA064)
8733 #define GEN6_RP_UP_EI                           _MMIO(0xA068)
8734 #define GEN6_RP_DOWN_EI                         _MMIO(0xA06C)
8735 #define GEN6_RP_IDLE_HYSTERSIS                  _MMIO(0xA070)
8736 #define GEN6_RPDEUHWTC                          _MMIO(0xA080)
8737 #define GEN6_RPDEUC                             _MMIO(0xA084)
8738 #define GEN6_RPDEUCSW                           _MMIO(0xA088)
8739 #define GEN6_RC_STATE                           _MMIO(0xA094)
8740 #define   RC_SW_TARGET_STATE_SHIFT              16
8741 #define   RC_SW_TARGET_STATE_MASK               (7 << RC_SW_TARGET_STATE_SHIFT)
8742 #define GEN6_RC1_WAKE_RATE_LIMIT                _MMIO(0xA098)
8743 #define GEN6_RC6_WAKE_RATE_LIMIT                _MMIO(0xA09C)
8744 #define GEN6_RC6pp_WAKE_RATE_LIMIT              _MMIO(0xA0A0)
8745 #define GEN10_MEDIA_WAKE_RATE_LIMIT             _MMIO(0xA0A0)
8746 #define GEN6_RC_EVALUATION_INTERVAL             _MMIO(0xA0A8)
8747 #define GEN6_RC_IDLE_HYSTERSIS                  _MMIO(0xA0AC)
8748 #define GEN6_RC_SLEEP                           _MMIO(0xA0B0)
8749 #define GEN6_RCUBMABDTMR                        _MMIO(0xA0B0)
8750 #define GEN6_RC1e_THRESHOLD                     _MMIO(0xA0B4)
8751 #define GEN6_RC6_THRESHOLD                      _MMIO(0xA0B8)
8752 #define GEN6_RC6p_THRESHOLD                     _MMIO(0xA0BC)
8753 #define VLV_RCEDATA                             _MMIO(0xA0BC)
8754 #define GEN6_RC6pp_THRESHOLD                    _MMIO(0xA0C0)
8755 #define GEN6_PMINTRMSK                          _MMIO(0xA168)
8756 #define   GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC   (1 << 31)
8757 #define   ARAT_EXPIRED_INTRMSK                  (1 << 9)
8758 #define GEN8_MISC_CTRL0                         _MMIO(0xA180)
8759 #define VLV_PWRDWNUPCTL                         _MMIO(0xA294)
8760 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS           _MMIO(0xA0C4)
8761 #define GEN9_RENDER_PG_IDLE_HYSTERESIS          _MMIO(0xA0C8)
8762 #define GEN9_PG_ENABLE                          _MMIO(0xA210)
8763 #define GEN9_RENDER_PG_ENABLE                   REG_BIT(0)
8764 #define GEN9_MEDIA_PG_ENABLE                    REG_BIT(1)
8765 #define GEN11_MEDIA_SAMPLER_PG_ENABLE           REG_BIT(2)
8766 #define GEN8_PUSHBUS_CONTROL                    _MMIO(0xA248)
8767 #define GEN8_PUSHBUS_ENABLE                     _MMIO(0xA250)
8768 #define GEN8_PUSHBUS_SHIFT                      _MMIO(0xA25C)
8769
8770 #define VLV_CHICKEN_3                           _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8771 #define  PIXEL_OVERLAP_CNT_MASK                 (3 << 30)
8772 #define  PIXEL_OVERLAP_CNT_SHIFT                30
8773
8774 #define GEN6_PMISR                              _MMIO(0x44020)
8775 #define GEN6_PMIMR                              _MMIO(0x44024) /* rps_lock */
8776 #define GEN6_PMIIR                              _MMIO(0x44028)
8777 #define GEN6_PMIER                              _MMIO(0x4402C)
8778 #define  GEN6_PM_MBOX_EVENT                     (1 << 25)
8779 #define  GEN6_PM_THERMAL_EVENT                  (1 << 24)
8780
8781 /*
8782  * For Gen11 these are in the upper word of the GPM_WGBOXPERF
8783  * registers. Shifting is handled on accessing the imr and ier.
8784  */
8785 #define  GEN6_PM_RP_DOWN_TIMEOUT                (1 << 6)
8786 #define  GEN6_PM_RP_UP_THRESHOLD                (1 << 5)
8787 #define  GEN6_PM_RP_DOWN_THRESHOLD              (1 << 4)
8788 #define  GEN6_PM_RP_UP_EI_EXPIRED               (1 << 2)
8789 #define  GEN6_PM_RP_DOWN_EI_EXPIRED             (1 << 1)
8790 #define  GEN6_PM_RPS_EVENTS                     (GEN6_PM_RP_UP_EI_EXPIRED   | \
8791                                                  GEN6_PM_RP_UP_THRESHOLD    | \
8792                                                  GEN6_PM_RP_DOWN_EI_EXPIRED | \
8793                                                  GEN6_PM_RP_DOWN_THRESHOLD  | \
8794                                                  GEN6_PM_RP_DOWN_TIMEOUT)
8795
8796 #define GEN7_GT_SCRATCH(i)                      _MMIO(0x4F100 + (i) * 4)
8797 #define GEN7_GT_SCRATCH_REG_NUM                 8
8798
8799 #define VLV_GTLC_SURVIVABILITY_REG              _MMIO(0x130098)
8800 #define VLV_GFX_CLK_STATUS_BIT                  (1 << 3)
8801 #define VLV_GFX_CLK_FORCE_ON_BIT                (1 << 2)
8802
8803 #define GEN6_GT_GFX_RC6_LOCKED                  _MMIO(0x138104)
8804 #define VLV_COUNTER_CONTROL                     _MMIO(0x138104)
8805 #define   VLV_COUNT_RANGE_HIGH                  (1 << 15)
8806 #define   VLV_MEDIA_RC0_COUNT_EN                (1 << 5)
8807 #define   VLV_RENDER_RC0_COUNT_EN               (1 << 4)
8808 #define   VLV_MEDIA_RC6_COUNT_EN                (1 << 1)
8809 #define   VLV_RENDER_RC6_COUNT_EN               (1 << 0)
8810 #define GEN6_GT_GFX_RC6                         _MMIO(0x138108)
8811 #define VLV_GT_RENDER_RC6                       _MMIO(0x138108)
8812 #define VLV_GT_MEDIA_RC6                        _MMIO(0x13810C)
8813
8814 #define GEN6_GT_GFX_RC6p                        _MMIO(0x13810C)
8815 #define GEN6_GT_GFX_RC6pp                       _MMIO(0x138110)
8816 #define VLV_RENDER_C0_COUNT                     _MMIO(0x138118)
8817 #define VLV_MEDIA_C0_COUNT                      _MMIO(0x13811C)
8818
8819 #define GEN6_PCODE_MAILBOX                      _MMIO(0x138124)
8820 #define   GEN6_PCODE_READY                      (1 << 31)
8821 #define   GEN6_PCODE_ERROR_MASK                 0xFF
8822 #define     GEN6_PCODE_SUCCESS                  0x0
8823 #define     GEN6_PCODE_ILLEGAL_CMD              0x1
8824 #define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8825 #define     GEN6_PCODE_TIMEOUT                  0x3
8826 #define     GEN6_PCODE_UNIMPLEMENTED_CMD        0xFF
8827 #define     GEN7_PCODE_TIMEOUT                  0x2
8828 #define     GEN7_PCODE_ILLEGAL_DATA             0x3
8829 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8830 #define   GEN6_PCODE_WRITE_RC6VIDS              0x4
8831 #define   GEN6_PCODE_READ_RC6VIDS               0x5
8832 #define     GEN6_ENCODE_RC6_VID(mv)             (((mv) - 245) / 5)
8833 #define     GEN6_DECODE_RC6_VID(vids)           (((vids) * 5) + 245)
8834 #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ     0x18
8835 #define   GEN9_PCODE_READ_MEM_LATENCY           0x6
8836 #define     GEN9_MEM_LATENCY_LEVEL_MASK         0xFF
8837 #define     GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT    8
8838 #define     GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT    16
8839 #define     GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT    24
8840 #define   SKL_PCODE_LOAD_HDCP_KEYS              0x5
8841 #define   SKL_PCODE_CDCLK_CONTROL               0x7
8842 #define     SKL_CDCLK_PREPARE_FOR_CHANGE        0x3
8843 #define     SKL_CDCLK_READY_FOR_CHANGE          0x1
8844 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE       0x8
8845 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE        0x9
8846 #define   GEN6_READ_OC_PARAMS                   0xc
8847 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO        0xd
8848 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO   (0x0 << 8)
8849 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
8850 #define   GEN6_PCODE_READ_D_COMP                0x10
8851 #define   GEN6_PCODE_WRITE_D_COMP               0x11
8852 #define   ICL_PCODE_EXIT_TCCOLD                 0x12
8853 #define   HSW_PCODE_DE_WRITE_FREQ_REQ           0x17
8854 #define   DISPLAY_IPS_CONTROL                   0x19
8855 #define   TGL_PCODE_TCCOLD                      0x26
8856 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED    REG_BIT(0)
8857 #define     TGL_PCODE_EXIT_TCCOLD_DATA_H_BLOCK_REQ      0
8858 #define     TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ    REG_BIT(0)
8859             /* See also IPS_CTL */
8860 #define     IPS_PCODE_CONTROL                   (1 << 30)
8861 #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL  0x1A
8862 #define   GEN9_PCODE_SAGV_CONTROL               0x21
8863 #define     GEN9_SAGV_DISABLE                   0x0
8864 #define     GEN9_SAGV_IS_DISABLED               0x1
8865 #define     GEN9_SAGV_ENABLE                    0x3
8866 #define GEN6_PCODE_DATA                         _MMIO(0x138128)
8867 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT        8
8868 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT      16
8869 #define GEN6_PCODE_DATA1                        _MMIO(0x13812C)
8870
8871 #define GEN6_GT_CORE_STATUS             _MMIO(0x138060)
8872 #define   GEN6_CORE_CPD_STATE_MASK      (7 << 4)
8873 #define   GEN6_RCn_MASK                 7
8874 #define   GEN6_RC0                      0
8875 #define   GEN6_RC3                      2
8876 #define   GEN6_RC6                      3
8877 #define   GEN6_RC7                      4
8878
8879 #define GEN8_GT_SLICE_INFO              _MMIO(0x138064)
8880 #define   GEN8_LSLICESTAT_MASK          0x7
8881
8882 #define CHV_POWER_SS0_SIG1              _MMIO(0xa720)
8883 #define CHV_POWER_SS1_SIG1              _MMIO(0xa728)
8884 #define   CHV_SS_PG_ENABLE              (1 << 1)
8885 #define   CHV_EU08_PG_ENABLE            (1 << 9)
8886 #define   CHV_EU19_PG_ENABLE            (1 << 17)
8887 #define   CHV_EU210_PG_ENABLE           (1 << 25)
8888
8889 #define CHV_POWER_SS0_SIG2              _MMIO(0xa724)
8890 #define CHV_POWER_SS1_SIG2              _MMIO(0xa72c)
8891 #define   CHV_EU311_PG_ENABLE           (1 << 1)
8892
8893 #define GEN9_SLICE_PGCTL_ACK(slice)     _MMIO(0x804c + (slice) * 0x4)
8894 #define GEN10_SLICE_PGCTL_ACK(slice)    _MMIO(0x804c + ((slice) / 3) * 0x34 + \
8895                                               ((slice) % 3) * 0x4)
8896 #define   GEN9_PGCTL_SLICE_ACK          (1 << 0)
8897 #define   GEN9_PGCTL_SS_ACK(subslice)   (1 << (2 + (subslice) * 2))
8898 #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
8899
8900 #define GEN9_SS01_EU_PGCTL_ACK(slice)   _MMIO(0x805c + (slice) * 0x8)
8901 #define GEN10_SS01_EU_PGCTL_ACK(slice)  _MMIO(0x805c + ((slice) / 3) * 0x30 + \
8902                                               ((slice) % 3) * 0x8)
8903 #define GEN9_SS23_EU_PGCTL_ACK(slice)   _MMIO(0x8060 + (slice) * 0x8)
8904 #define GEN10_SS23_EU_PGCTL_ACK(slice)  _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8905                                               ((slice) % 3) * 0x8)
8906 #define   GEN9_PGCTL_SSA_EU08_ACK       (1 << 0)
8907 #define   GEN9_PGCTL_SSA_EU19_ACK       (1 << 2)
8908 #define   GEN9_PGCTL_SSA_EU210_ACK      (1 << 4)
8909 #define   GEN9_PGCTL_SSA_EU311_ACK      (1 << 6)
8910 #define   GEN9_PGCTL_SSB_EU08_ACK       (1 << 8)
8911 #define   GEN9_PGCTL_SSB_EU19_ACK       (1 << 10)
8912 #define   GEN9_PGCTL_SSB_EU210_ACK      (1 << 12)
8913 #define   GEN9_PGCTL_SSB_EU311_ACK      (1 << 14)
8914
8915 #define GEN7_MISCCPCTL                          _MMIO(0x9424)
8916 #define   GEN7_DOP_CLOCK_GATE_ENABLE            (1 << 0)
8917 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE      (1 << 2)
8918 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE        (1 << 4)
8919 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1 << 6)
8920
8921 #define GEN8_GARBCNTL                           _MMIO(0xB004)
8922 #define   GEN9_GAPS_TSV_CREDIT_DISABLE          (1 << 7)
8923 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK     (0x3f << 22)
8924 #define   GEN11_HASH_CTRL_EXCL_MASK             (0x7f << 0)
8925 #define   GEN11_HASH_CTRL_EXCL_BIT0             (1 << 0)
8926
8927 #define GEN11_GLBLINVL                          _MMIO(0xB404)
8928 #define   GEN11_BANK_HASH_ADDR_EXCL_MASK        (0x7f << 5)
8929 #define   GEN11_BANK_HASH_ADDR_EXCL_BIT0        (1 << 5)
8930
8931 #define GEN10_DFR_RATIO_EN_AND_CHICKEN  _MMIO(0x9550)
8932 #define   DFR_DISABLE                   (1 << 9)
8933
8934 #define GEN11_GACB_PERF_CTRL                    _MMIO(0x4B80)
8935 #define   GEN11_HASH_CTRL_MASK                  (0x3 << 12 | 0xf << 0)
8936 #define   GEN11_HASH_CTRL_BIT0                  (1 << 0)
8937 #define   GEN11_HASH_CTRL_BIT4                  (1 << 12)
8938
8939 #define GEN11_LSN_UNSLCVC                               _MMIO(0xB43C)
8940 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC      (1 << 9)
8941 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC       (1 << 7)
8942
8943 #define GEN10_SAMPLER_MODE              _MMIO(0xE18C)
8944 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG     REG_BIT(5)
8945
8946 /* IVYBRIDGE DPF */
8947 #define GEN7_L3CDERRST1(slice)          _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
8948 #define   GEN7_L3CDERRST1_ROW_MASK      (0x7ff << 14)
8949 #define   GEN7_PARITY_ERROR_VALID       (1 << 13)
8950 #define   GEN7_L3CDERRST1_BANK_MASK     (3 << 11)
8951 #define   GEN7_L3CDERRST1_SUBBANK_MASK  (7 << 8)
8952 #define GEN7_PARITY_ERROR_ROW(reg) \
8953                 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8954 #define GEN7_PARITY_ERROR_BANK(reg) \
8955                 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8956 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
8957                 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8958 #define   GEN7_L3CDERRST1_ENABLE        (1 << 7)
8959
8960 #define GEN7_L3LOG(slice, i)            _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
8961 #define GEN7_L3LOG_SIZE                 0x80
8962
8963 #define GEN7_HALF_SLICE_CHICKEN1        _MMIO(0xe100) /* IVB GT1 + VLV */
8964 #define GEN7_HALF_SLICE_CHICKEN1_GT2    _MMIO(0xf100)
8965 #define   GEN7_MAX_PS_THREAD_DEP                (8 << 12)
8966 #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE   (1 << 10)
8967 #define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE       (1 << 4)
8968 #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE  (1 << 3)
8969
8970 #define GEN9_HALF_SLICE_CHICKEN5        _MMIO(0xe188)
8971 #define   GEN9_DG_MIRROR_FIX_ENABLE     (1 << 5)
8972 #define   GEN9_CCS_TLB_PREFETCH_ENABLE  (1 << 3)
8973
8974 #define GEN8_ROW_CHICKEN                _MMIO(0xe4f0)
8975 #define   FLOW_CONTROL_ENABLE           (1 << 15)
8976 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
8977 #define   STALL_DOP_GATING_DISABLE              (1 << 5)
8978 #define   THROTTLE_12_5                         (7 << 2)
8979 #define   DISABLE_EARLY_EOT                     (1 << 1)
8980
8981 #define GEN7_ROW_CHICKEN2               _MMIO(0xe4f4)
8982 #define GEN7_ROW_CHICKEN2_GT2           _MMIO(0xf4f4)
8983 #define   DOP_CLOCK_GATING_DISABLE      (1 << 0)
8984 #define   PUSH_CONSTANT_DEREF_DISABLE   (1 << 8)
8985 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE    (1 << 1)
8986
8987 #define HSW_ROW_CHICKEN3                _MMIO(0xe49c)
8988 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
8989
8990 #define HALF_SLICE_CHICKEN2             _MMIO(0xe180)
8991 #define   GEN8_ST_PO_DISABLE            (1 << 13)
8992
8993 #define HALF_SLICE_CHICKEN3             _MMIO(0xe184)
8994 #define   HSW_SAMPLE_C_PERFORMANCE      (1 << 9)
8995 #define   GEN8_CENTROID_PIXEL_OPT_DIS   (1 << 8)
8996 #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC   (1 << 5)
8997 #define   CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
8998 #define   GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
8999
9000 #define GEN9_HALF_SLICE_CHICKEN7        _MMIO(0xe194)
9001 #define   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR        (1 << 8)
9002 #define   GEN9_ENABLE_YV12_BUGFIX       (1 << 4)
9003 #define   GEN9_ENABLE_GPGPU_PREEMPTION  (1 << 2)
9004
9005 /* Audio */
9006 #define G4X_AUD_VID_DID                 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
9007 #define   INTEL_AUDIO_DEVCL             0x808629FB
9008 #define   INTEL_AUDIO_DEVBLC            0x80862801
9009 #define   INTEL_AUDIO_DEVCTG            0x80862802
9010
9011 #define G4X_AUD_CNTL_ST                 _MMIO(0x620B4)
9012 #define   G4X_ELDV_DEVCL_DEVBLC         (1 << 13)
9013 #define   G4X_ELDV_DEVCTG               (1 << 14)
9014 #define   G4X_ELD_ADDR_MASK             (0xf << 5)
9015 #define   G4X_ELD_ACK                   (1 << 4)
9016 #define G4X_HDMIW_HDMIEDID              _MMIO(0x6210C)
9017
9018 #define _IBX_HDMIW_HDMIEDID_A           0xE2050
9019 #define _IBX_HDMIW_HDMIEDID_B           0xE2150
9020 #define IBX_HDMIW_HDMIEDID(pipe)        _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
9021                                                   _IBX_HDMIW_HDMIEDID_B)
9022 #define _IBX_AUD_CNTL_ST_A              0xE20B4
9023 #define _IBX_AUD_CNTL_ST_B              0xE21B4
9024 #define IBX_AUD_CNTL_ST(pipe)           _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
9025                                                   _IBX_AUD_CNTL_ST_B)
9026 #define   IBX_ELD_BUFFER_SIZE_MASK      (0x1f << 10)
9027 #define   IBX_ELD_ADDRESS_MASK          (0x1f << 5)
9028 #define   IBX_ELD_ACK                   (1 << 4)
9029 #define IBX_AUD_CNTL_ST2                _MMIO(0xE20C0)
9030 #define   IBX_CP_READY(port)            ((1 << 1) << (((port) - 1) * 4))
9031 #define   IBX_ELD_VALID(port)           ((1 << 0) << (((port) - 1) * 4))
9032
9033 #define _CPT_HDMIW_HDMIEDID_A           0xE5050
9034 #define _CPT_HDMIW_HDMIEDID_B           0xE5150
9035 #define CPT_HDMIW_HDMIEDID(pipe)        _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
9036 #define _CPT_AUD_CNTL_ST_A              0xE50B4
9037 #define _CPT_AUD_CNTL_ST_B              0xE51B4
9038 #define CPT_AUD_CNTL_ST(pipe)           _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
9039 #define CPT_AUD_CNTRL_ST2               _MMIO(0xE50C0)
9040
9041 #define _VLV_HDMIW_HDMIEDID_A           (VLV_DISPLAY_BASE + 0x62050)
9042 #define _VLV_HDMIW_HDMIEDID_B           (VLV_DISPLAY_BASE + 0x62150)
9043 #define VLV_HDMIW_HDMIEDID(pipe)        _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
9044 #define _VLV_AUD_CNTL_ST_A              (VLV_DISPLAY_BASE + 0x620B4)
9045 #define _VLV_AUD_CNTL_ST_B              (VLV_DISPLAY_BASE + 0x621B4)
9046 #define VLV_AUD_CNTL_ST(pipe)           _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
9047 #define VLV_AUD_CNTL_ST2                _MMIO(VLV_DISPLAY_BASE + 0x620C0)
9048
9049 /* These are the 4 32-bit write offset registers for each stream
9050  * output buffer.  It determines the offset from the
9051  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
9052  */
9053 #define GEN7_SO_WRITE_OFFSET(n)         _MMIO(0x5280 + (n) * 4)
9054
9055 #define _IBX_AUD_CONFIG_A               0xe2000
9056 #define _IBX_AUD_CONFIG_B               0xe2100
9057 #define IBX_AUD_CFG(pipe)               _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
9058 #define _CPT_AUD_CONFIG_A               0xe5000
9059 #define _CPT_AUD_CONFIG_B               0xe5100
9060 #define CPT_AUD_CFG(pipe)               _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
9061 #define _VLV_AUD_CONFIG_A               (VLV_DISPLAY_BASE + 0x62000)
9062 #define _VLV_AUD_CONFIG_B               (VLV_DISPLAY_BASE + 0x62100)
9063 #define VLV_AUD_CFG(pipe)               _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
9064
9065 #define   AUD_CONFIG_N_VALUE_INDEX              (1 << 29)
9066 #define   AUD_CONFIG_N_PROG_ENABLE              (1 << 28)
9067 #define   AUD_CONFIG_UPPER_N_SHIFT              20
9068 #define   AUD_CONFIG_UPPER_N_MASK               (0xff << 20)
9069 #define   AUD_CONFIG_LOWER_N_SHIFT              4
9070 #define   AUD_CONFIG_LOWER_N_MASK               (0xfff << 4)
9071 #define   AUD_CONFIG_N_MASK                     (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
9072 #define   AUD_CONFIG_N(n) \
9073         (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |   \
9074          (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
9075 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT     16
9076 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK      (0xf << 16)
9077 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175     (0 << 16)
9078 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200     (1 << 16)
9079 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000     (2 << 16)
9080 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027     (3 << 16)
9081 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000     (4 << 16)
9082 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054     (5 << 16)
9083 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176     (6 << 16)
9084 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250     (7 << 16)
9085 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352    (8 << 16)
9086 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500    (9 << 16)
9087 #define   AUD_CONFIG_DISABLE_NCTS               (1 << 3)
9088
9089 /* HSW Audio */
9090 #define _HSW_AUD_CONFIG_A               0x65000
9091 #define _HSW_AUD_CONFIG_B               0x65100
9092 #define HSW_AUD_CFG(trans)              _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
9093
9094 #define _HSW_AUD_MISC_CTRL_A            0x65010
9095 #define _HSW_AUD_MISC_CTRL_B            0x65110
9096 #define HSW_AUD_MISC_CTRL(trans)        _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
9097
9098 #define _HSW_AUD_M_CTS_ENABLE_A         0x65028
9099 #define _HSW_AUD_M_CTS_ENABLE_B         0x65128
9100 #define HSW_AUD_M_CTS_ENABLE(trans)     _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
9101 #define   AUD_M_CTS_M_VALUE_INDEX       (1 << 21)
9102 #define   AUD_M_CTS_M_PROG_ENABLE       (1 << 20)
9103 #define   AUD_CONFIG_M_MASK             0xfffff
9104
9105 #define _HSW_AUD_DIP_ELD_CTRL_ST_A      0x650b4
9106 #define _HSW_AUD_DIP_ELD_CTRL_ST_B      0x651b4
9107 #define HSW_AUD_DIP_ELD_CTRL(trans)     _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
9108
9109 /* Audio Digital Converter */
9110 #define _HSW_AUD_DIG_CNVT_1             0x65080
9111 #define _HSW_AUD_DIG_CNVT_2             0x65180
9112 #define AUD_DIG_CNVT(trans)             _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
9113 #define DIP_PORT_SEL_MASK               0x3
9114
9115 #define _HSW_AUD_EDID_DATA_A            0x65050
9116 #define _HSW_AUD_EDID_DATA_B            0x65150
9117 #define HSW_AUD_EDID_DATA(trans)        _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
9118
9119 #define HSW_AUD_PIPE_CONV_CFG           _MMIO(0x6507c)
9120 #define HSW_AUD_PIN_ELD_CP_VLD          _MMIO(0x650c0)
9121 #define   AUDIO_INACTIVE(trans)         ((1 << 3) << ((trans) * 4))
9122 #define   AUDIO_OUTPUT_ENABLE(trans)    ((1 << 2) << ((trans) * 4))
9123 #define   AUDIO_CP_READY(trans)         ((1 << 1) << ((trans) * 4))
9124 #define   AUDIO_ELD_VALID(trans)        ((1 << 0) << ((trans) * 4))
9125
9126 #define HSW_AUD_CHICKENBIT                      _MMIO(0x65f10)
9127 #define   SKL_AUD_CODEC_WAKE_SIGNAL             (1 << 15)
9128
9129 #define AUD_PIN_BUF_CTL         _MMIO(0x48414)
9130 #define   AUD_PIN_BUF_ENABLE            REG_BIT(31)
9131
9132 /*
9133  * HSW - ICL power wells
9134  *
9135  * Platforms have up to 3 power well control register sets, each set
9136  * controlling up to 16 power wells via a request/status HW flag tuple:
9137  * - main (HSW_PWR_WELL_CTL[1-4])
9138  * - AUX  (ICL_PWR_WELL_CTL_AUX[1-4])
9139  * - DDI  (ICL_PWR_WELL_CTL_DDI[1-4])
9140  * Each control register set consists of up to 4 registers used by different
9141  * sources that can request a power well to be enabled:
9142  * - BIOS   (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9143  * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9144  * - KVMR   (HSW_PWR_WELL_CTL3)   (only in the main register set)
9145  * - DEBUG  (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9146  */
9147 #define HSW_PWR_WELL_CTL1                       _MMIO(0x45400)
9148 #define HSW_PWR_WELL_CTL2                       _MMIO(0x45404)
9149 #define HSW_PWR_WELL_CTL3                       _MMIO(0x45408)
9150 #define HSW_PWR_WELL_CTL4                       _MMIO(0x4540C)
9151 #define   HSW_PWR_WELL_CTL_REQ(pw_idx)          (0x2 << ((pw_idx) * 2))
9152 #define   HSW_PWR_WELL_CTL_STATE(pw_idx)        (0x1 << ((pw_idx) * 2))
9153
9154 /* HSW/BDW power well */
9155 #define   HSW_PW_CTL_IDX_GLOBAL                 15
9156
9157 /* SKL/BXT/GLK/CNL power wells */
9158 #define   SKL_PW_CTL_IDX_PW_2                   15
9159 #define   SKL_PW_CTL_IDX_PW_1                   14
9160 #define   CNL_PW_CTL_IDX_AUX_F                  12
9161 #define   CNL_PW_CTL_IDX_AUX_D                  11
9162 #define   GLK_PW_CTL_IDX_AUX_C                  10
9163 #define   GLK_PW_CTL_IDX_AUX_B                  9
9164 #define   GLK_PW_CTL_IDX_AUX_A                  8
9165 #define   CNL_PW_CTL_IDX_DDI_F                  6
9166 #define   SKL_PW_CTL_IDX_DDI_D                  4
9167 #define   SKL_PW_CTL_IDX_DDI_C                  3
9168 #define   SKL_PW_CTL_IDX_DDI_B                  2
9169 #define   SKL_PW_CTL_IDX_DDI_A_E                1
9170 #define   GLK_PW_CTL_IDX_DDI_A                  1
9171 #define   SKL_PW_CTL_IDX_MISC_IO                0
9172
9173 /* ICL/TGL - power wells */
9174 #define   TGL_PW_CTL_IDX_PW_5                   4
9175 #define   ICL_PW_CTL_IDX_PW_4                   3
9176 #define   ICL_PW_CTL_IDX_PW_3                   2
9177 #define   ICL_PW_CTL_IDX_PW_2                   1
9178 #define   ICL_PW_CTL_IDX_PW_1                   0
9179
9180 #define ICL_PWR_WELL_CTL_AUX1                   _MMIO(0x45440)
9181 #define ICL_PWR_WELL_CTL_AUX2                   _MMIO(0x45444)
9182 #define ICL_PWR_WELL_CTL_AUX4                   _MMIO(0x4544C)
9183 #define   TGL_PW_CTL_IDX_AUX_TBT6               14
9184 #define   TGL_PW_CTL_IDX_AUX_TBT5               13
9185 #define   TGL_PW_CTL_IDX_AUX_TBT4               12
9186 #define   ICL_PW_CTL_IDX_AUX_TBT4               11
9187 #define   TGL_PW_CTL_IDX_AUX_TBT3               11
9188 #define   ICL_PW_CTL_IDX_AUX_TBT3               10
9189 #define   TGL_PW_CTL_IDX_AUX_TBT2               10
9190 #define   ICL_PW_CTL_IDX_AUX_TBT2               9
9191 #define   TGL_PW_CTL_IDX_AUX_TBT1               9
9192 #define   ICL_PW_CTL_IDX_AUX_TBT1               8
9193 #define   TGL_PW_CTL_IDX_AUX_TC6                8
9194 #define   TGL_PW_CTL_IDX_AUX_TC5                7
9195 #define   TGL_PW_CTL_IDX_AUX_TC4                6
9196 #define   ICL_PW_CTL_IDX_AUX_F                  5
9197 #define   TGL_PW_CTL_IDX_AUX_TC3                5
9198 #define   ICL_PW_CTL_IDX_AUX_E                  4
9199 #define   TGL_PW_CTL_IDX_AUX_TC2                4
9200 #define   ICL_PW_CTL_IDX_AUX_D                  3
9201 #define   TGL_PW_CTL_IDX_AUX_TC1                3
9202 #define   ICL_PW_CTL_IDX_AUX_C                  2
9203 #define   ICL_PW_CTL_IDX_AUX_B                  1
9204 #define   ICL_PW_CTL_IDX_AUX_A                  0
9205
9206 #define ICL_PWR_WELL_CTL_DDI1                   _MMIO(0x45450)
9207 #define ICL_PWR_WELL_CTL_DDI2                   _MMIO(0x45454)
9208 #define ICL_PWR_WELL_CTL_DDI4                   _MMIO(0x4545C)
9209 #define   TGL_PW_CTL_IDX_DDI_TC6                8
9210 #define   TGL_PW_CTL_IDX_DDI_TC5                7
9211 #define   TGL_PW_CTL_IDX_DDI_TC4                6
9212 #define   ICL_PW_CTL_IDX_DDI_F                  5
9213 #define   TGL_PW_CTL_IDX_DDI_TC3                5
9214 #define   ICL_PW_CTL_IDX_DDI_E                  4
9215 #define   TGL_PW_CTL_IDX_DDI_TC2                4
9216 #define   ICL_PW_CTL_IDX_DDI_D                  3
9217 #define   TGL_PW_CTL_IDX_DDI_TC1                3
9218 #define   ICL_PW_CTL_IDX_DDI_C                  2
9219 #define   ICL_PW_CTL_IDX_DDI_B                  1
9220 #define   ICL_PW_CTL_IDX_DDI_A                  0
9221
9222 /* HSW - power well misc debug registers */
9223 #define HSW_PWR_WELL_CTL5                       _MMIO(0x45410)
9224 #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP       (1 << 31)
9225 #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE        (1 << 20)
9226 #define   HSW_PWR_WELL_FORCE_ON                 (1 << 19)
9227 #define HSW_PWR_WELL_CTL6                       _MMIO(0x45414)
9228
9229 /* SKL Fuse Status */
9230 enum skl_power_gate {
9231         SKL_PG0,
9232         SKL_PG1,
9233         SKL_PG2,
9234         ICL_PG3,
9235         ICL_PG4,
9236 };
9237
9238 #define SKL_FUSE_STATUS                         _MMIO(0x42000)
9239 #define  SKL_FUSE_DOWNLOAD_STATUS               (1 << 31)
9240 /*
9241  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9242  * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9243  */
9244 #define  SKL_PW_CTL_IDX_TO_PG(pw_idx)           \
9245         ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9246 /*
9247  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9248  * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9249  */
9250 #define  ICL_PW_CTL_IDX_TO_PG(pw_idx)           \
9251         ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9252 #define  SKL_FUSE_PG_DIST_STATUS(pg)            (1 << (27 - (pg)))
9253
9254 #define _CNL_AUX_REG_IDX(pw_idx)        ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
9255 #define _CNL_AUX_ANAOVRD1_B             0x162250
9256 #define _CNL_AUX_ANAOVRD1_C             0x162210
9257 #define _CNL_AUX_ANAOVRD1_D             0x1622D0
9258 #define _CNL_AUX_ANAOVRD1_F             0x162A90
9259 #define CNL_AUX_ANAOVRD1(pw_idx)        _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
9260                                                     _CNL_AUX_ANAOVRD1_B, \
9261                                                     _CNL_AUX_ANAOVRD1_C, \
9262                                                     _CNL_AUX_ANAOVRD1_D, \
9263                                                     _CNL_AUX_ANAOVRD1_F))
9264 #define   CNL_AUX_ANAOVRD1_ENABLE       (1 << 16)
9265 #define   CNL_AUX_ANAOVRD1_LDO_BYPASS   (1 << 23)
9266
9267 #define _ICL_AUX_REG_IDX(pw_idx)        ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9268 #define _ICL_AUX_ANAOVRD1_A             0x162398
9269 #define _ICL_AUX_ANAOVRD1_B             0x6C398
9270 #define _TGL_AUX_ANAOVRD1_C             0x160398
9271 #define ICL_AUX_ANAOVRD1(pw_idx)        _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9272                                                     _ICL_AUX_ANAOVRD1_A, \
9273                                                     _ICL_AUX_ANAOVRD1_B, \
9274                                                     _TGL_AUX_ANAOVRD1_C))
9275 #define   ICL_AUX_ANAOVRD1_LDO_BYPASS   (1 << 7)
9276 #define   ICL_AUX_ANAOVRD1_ENABLE       (1 << 0)
9277
9278 /* HDCP Key Registers */
9279 #define HDCP_KEY_CONF                   _MMIO(0x66c00)
9280 #define  HDCP_AKSV_SEND_TRIGGER         BIT(31)
9281 #define  HDCP_CLEAR_KEYS_TRIGGER        BIT(30)
9282 #define  HDCP_KEY_LOAD_TRIGGER          BIT(8)
9283 #define HDCP_KEY_STATUS                 _MMIO(0x66c04)
9284 #define  HDCP_FUSE_IN_PROGRESS          BIT(7)
9285 #define  HDCP_FUSE_ERROR                BIT(6)
9286 #define  HDCP_FUSE_DONE                 BIT(5)
9287 #define  HDCP_KEY_LOAD_STATUS           BIT(1)
9288 #define  HDCP_KEY_LOAD_DONE             BIT(0)
9289 #define HDCP_AKSV_LO                    _MMIO(0x66c10)
9290 #define HDCP_AKSV_HI                    _MMIO(0x66c14)
9291
9292 /* HDCP Repeater Registers */
9293 #define HDCP_REP_CTL                    _MMIO(0x66d00)
9294 #define  HDCP_DDIB_REP_PRESENT          BIT(30)
9295 #define  HDCP_DDIA_REP_PRESENT          BIT(29)
9296 #define  HDCP_DDIC_REP_PRESENT          BIT(28)
9297 #define  HDCP_DDID_REP_PRESENT          BIT(27)
9298 #define  HDCP_DDIF_REP_PRESENT          BIT(26)
9299 #define  HDCP_DDIE_REP_PRESENT          BIT(25)
9300 #define  HDCP_DDIB_SHA1_M0              (1 << 20)
9301 #define  HDCP_DDIA_SHA1_M0              (2 << 20)
9302 #define  HDCP_DDIC_SHA1_M0              (3 << 20)
9303 #define  HDCP_DDID_SHA1_M0              (4 << 20)
9304 #define  HDCP_DDIF_SHA1_M0              (5 << 20)
9305 #define  HDCP_DDIE_SHA1_M0              (6 << 20) /* Bspec says 5? */
9306 #define  HDCP_SHA1_BUSY                 BIT(16)
9307 #define  HDCP_SHA1_READY                BIT(17)
9308 #define  HDCP_SHA1_COMPLETE             BIT(18)
9309 #define  HDCP_SHA1_V_MATCH              BIT(19)
9310 #define  HDCP_SHA1_TEXT_32              (1 << 1)
9311 #define  HDCP_SHA1_COMPLETE_HASH        (2 << 1)
9312 #define  HDCP_SHA1_TEXT_24              (4 << 1)
9313 #define  HDCP_SHA1_TEXT_16              (5 << 1)
9314 #define  HDCP_SHA1_TEXT_8               (6 << 1)
9315 #define  HDCP_SHA1_TEXT_0               (7 << 1)
9316 #define HDCP_SHA_V_PRIME_H0             _MMIO(0x66d04)
9317 #define HDCP_SHA_V_PRIME_H1             _MMIO(0x66d08)
9318 #define HDCP_SHA_V_PRIME_H2             _MMIO(0x66d0C)
9319 #define HDCP_SHA_V_PRIME_H3             _MMIO(0x66d10)
9320 #define HDCP_SHA_V_PRIME_H4             _MMIO(0x66d14)
9321 #define HDCP_SHA_V_PRIME(h)             _MMIO((0x66d04 + (h) * 4))
9322 #define HDCP_SHA_TEXT                   _MMIO(0x66d18)
9323
9324 /* HDCP Auth Registers */
9325 #define _PORTA_HDCP_AUTHENC             0x66800
9326 #define _PORTB_HDCP_AUTHENC             0x66500
9327 #define _PORTC_HDCP_AUTHENC             0x66600
9328 #define _PORTD_HDCP_AUTHENC             0x66700
9329 #define _PORTE_HDCP_AUTHENC             0x66A00
9330 #define _PORTF_HDCP_AUTHENC             0x66900
9331 #define _PORT_HDCP_AUTHENC(port, x)     _MMIO(_PICK(port, \
9332                                           _PORTA_HDCP_AUTHENC, \
9333                                           _PORTB_HDCP_AUTHENC, \
9334                                           _PORTC_HDCP_AUTHENC, \
9335                                           _PORTD_HDCP_AUTHENC, \
9336                                           _PORTE_HDCP_AUTHENC, \
9337                                           _PORTF_HDCP_AUTHENC) + (x))
9338 #define PORT_HDCP_CONF(port)            _PORT_HDCP_AUTHENC(port, 0x0)
9339 #define  HDCP_CONF_CAPTURE_AN           BIT(0)
9340 #define  HDCP_CONF_AUTH_AND_ENC         (BIT(1) | BIT(0))
9341 #define PORT_HDCP_ANINIT(port)          _PORT_HDCP_AUTHENC(port, 0x4)
9342 #define PORT_HDCP_ANLO(port)            _PORT_HDCP_AUTHENC(port, 0x8)
9343 #define PORT_HDCP_ANHI(port)            _PORT_HDCP_AUTHENC(port, 0xC)
9344 #define PORT_HDCP_BKSVLO(port)          _PORT_HDCP_AUTHENC(port, 0x10)
9345 #define PORT_HDCP_BKSVHI(port)          _PORT_HDCP_AUTHENC(port, 0x14)
9346 #define PORT_HDCP_RPRIME(port)          _PORT_HDCP_AUTHENC(port, 0x18)
9347 #define PORT_HDCP_STATUS(port)          _PORT_HDCP_AUTHENC(port, 0x1C)
9348 #define  HDCP_STATUS_STREAM_A_ENC       BIT(31)
9349 #define  HDCP_STATUS_STREAM_B_ENC       BIT(30)
9350 #define  HDCP_STATUS_STREAM_C_ENC       BIT(29)
9351 #define  HDCP_STATUS_STREAM_D_ENC       BIT(28)
9352 #define  HDCP_STATUS_AUTH               BIT(21)
9353 #define  HDCP_STATUS_ENC                BIT(20)
9354 #define  HDCP_STATUS_RI_MATCH           BIT(19)
9355 #define  HDCP_STATUS_R0_READY           BIT(18)
9356 #define  HDCP_STATUS_AN_READY           BIT(17)
9357 #define  HDCP_STATUS_CIPHER             BIT(16)
9358 #define  HDCP_STATUS_FRAME_CNT(x)       (((x) >> 8) & 0xff)
9359
9360 /* HDCP2.2 Registers */
9361 #define _PORTA_HDCP2_BASE               0x66800
9362 #define _PORTB_HDCP2_BASE               0x66500
9363 #define _PORTC_HDCP2_BASE               0x66600
9364 #define _PORTD_HDCP2_BASE               0x66700
9365 #define _PORTE_HDCP2_BASE               0x66A00
9366 #define _PORTF_HDCP2_BASE               0x66900
9367 #define _PORT_HDCP2_BASE(port, x)       _MMIO(_PICK((port), \
9368                                           _PORTA_HDCP2_BASE, \
9369                                           _PORTB_HDCP2_BASE, \
9370                                           _PORTC_HDCP2_BASE, \
9371                                           _PORTD_HDCP2_BASE, \
9372                                           _PORTE_HDCP2_BASE, \
9373                                           _PORTF_HDCP2_BASE) + (x))
9374
9375 #define HDCP2_AUTH_DDI(port)            _PORT_HDCP2_BASE(port, 0x98)
9376 #define   AUTH_LINK_AUTHENTICATED       BIT(31)
9377 #define   AUTH_LINK_TYPE                BIT(30)
9378 #define   AUTH_FORCE_CLR_INPUTCTR       BIT(19)
9379 #define   AUTH_CLR_KEYS                 BIT(18)
9380
9381 #define HDCP2_CTL_DDI(port)             _PORT_HDCP2_BASE(port, 0xB0)
9382 #define   CTL_LINK_ENCRYPTION_REQ       BIT(31)
9383
9384 #define HDCP2_STATUS_DDI(port)          _PORT_HDCP2_BASE(port, 0xB4)
9385 #define   STREAM_ENCRYPTION_STATUS_A    BIT(31)
9386 #define   STREAM_ENCRYPTION_STATUS_B    BIT(30)
9387 #define   STREAM_ENCRYPTION_STATUS_C    BIT(29)
9388 #define   LINK_TYPE_STATUS              BIT(22)
9389 #define   LINK_AUTH_STATUS              BIT(21)
9390 #define   LINK_ENCRYPTION_STATUS        BIT(20)
9391
9392 /* Per-pipe DDI Function Control */
9393 #define _TRANS_DDI_FUNC_CTL_A           0x60400
9394 #define _TRANS_DDI_FUNC_CTL_B           0x61400
9395 #define _TRANS_DDI_FUNC_CTL_C           0x62400
9396 #define _TRANS_DDI_FUNC_CTL_D           0x63400
9397 #define _TRANS_DDI_FUNC_CTL_EDP         0x6F400
9398 #define _TRANS_DDI_FUNC_CTL_DSI0        0x6b400
9399 #define _TRANS_DDI_FUNC_CTL_DSI1        0x6bc00
9400 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9401
9402 #define  TRANS_DDI_FUNC_ENABLE          (1 << 31)
9403 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9404 #define  TRANS_DDI_PORT_SHIFT           28
9405 #define  TGL_TRANS_DDI_PORT_SHIFT       27
9406 #define  TRANS_DDI_PORT_MASK            (7 << TRANS_DDI_PORT_SHIFT)
9407 #define  TGL_TRANS_DDI_PORT_MASK        (0xf << TGL_TRANS_DDI_PORT_SHIFT)
9408 #define  TRANS_DDI_SELECT_PORT(x)       ((x) << TRANS_DDI_PORT_SHIFT)
9409 #define  TGL_TRANS_DDI_SELECT_PORT(x)   (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
9410 #define  TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val)     (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
9411 #define  TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
9412 #define  TRANS_DDI_MODE_SELECT_MASK     (7 << 24)
9413 #define  TRANS_DDI_MODE_SELECT_HDMI     (0 << 24)
9414 #define  TRANS_DDI_MODE_SELECT_DVI      (1 << 24)
9415 #define  TRANS_DDI_MODE_SELECT_DP_SST   (2 << 24)
9416 #define  TRANS_DDI_MODE_SELECT_DP_MST   (3 << 24)
9417 #define  TRANS_DDI_MODE_SELECT_FDI      (4 << 24)
9418 #define  TRANS_DDI_BPC_MASK             (7 << 20)
9419 #define  TRANS_DDI_BPC_8                (0 << 20)
9420 #define  TRANS_DDI_BPC_10               (1 << 20)
9421 #define  TRANS_DDI_BPC_6                (2 << 20)
9422 #define  TRANS_DDI_BPC_12               (3 << 20)
9423 #define  TRANS_DDI_PVSYNC               (1 << 17)
9424 #define  TRANS_DDI_PHSYNC               (1 << 16)
9425 #define  TRANS_DDI_EDP_INPUT_MASK       (7 << 12)
9426 #define  TRANS_DDI_EDP_INPUT_A_ON       (0 << 12)
9427 #define  TRANS_DDI_EDP_INPUT_A_ONOFF    (4 << 12)
9428 #define  TRANS_DDI_EDP_INPUT_B_ONOFF    (5 << 12)
9429 #define  TRANS_DDI_EDP_INPUT_C_ONOFF    (6 << 12)
9430 #define  TRANS_DDI_HDCP_SIGNALLING      (1 << 9)
9431 #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC  (1 << 8)
9432 #define  TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
9433 #define  TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
9434 #define  TRANS_DDI_BFI_ENABLE           (1 << 4)
9435 #define  TRANS_DDI_HIGH_TMDS_CHAR_RATE  (1 << 4)
9436 #define  TRANS_DDI_HDMI_SCRAMBLING      (1 << 0)
9437 #define  TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
9438                                         | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9439                                         | TRANS_DDI_HDMI_SCRAMBLING)
9440
9441 #define _TRANS_DDI_FUNC_CTL2_A          0x60404
9442 #define _TRANS_DDI_FUNC_CTL2_B          0x61404
9443 #define _TRANS_DDI_FUNC_CTL2_C          0x62404
9444 #define _TRANS_DDI_FUNC_CTL2_EDP        0x6f404
9445 #define _TRANS_DDI_FUNC_CTL2_DSI0       0x6b404
9446 #define _TRANS_DDI_FUNC_CTL2_DSI1       0x6bc04
9447 #define TRANS_DDI_FUNC_CTL2(tran)       _MMIO_TRANS2(tran, \
9448                                                      _TRANS_DDI_FUNC_CTL2_A)
9449 #define  PORT_SYNC_MODE_ENABLE                  (1 << 4)
9450 #define  PORT_SYNC_MODE_MASTER_SELECT(x)        ((x) << 0)
9451 #define  PORT_SYNC_MODE_MASTER_SELECT_MASK      (0x7 << 0)
9452 #define  PORT_SYNC_MODE_MASTER_SELECT_SHIFT     0
9453
9454 /* DisplayPort Transport Control */
9455 #define _DP_TP_CTL_A                    0x64040
9456 #define _DP_TP_CTL_B                    0x64140
9457 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
9458 #define  DP_TP_CTL_ENABLE                       (1 << 31)
9459 #define  DP_TP_CTL_FEC_ENABLE                   (1 << 30)
9460 #define  DP_TP_CTL_MODE_SST                     (0 << 27)
9461 #define  DP_TP_CTL_MODE_MST                     (1 << 27)
9462 #define  DP_TP_CTL_FORCE_ACT                    (1 << 25)
9463 #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE        (1 << 18)
9464 #define  DP_TP_CTL_FDI_AUTOTRAIN                (1 << 15)
9465 #define  DP_TP_CTL_LINK_TRAIN_MASK              (7 << 8)
9466 #define  DP_TP_CTL_LINK_TRAIN_PAT1              (0 << 8)
9467 #define  DP_TP_CTL_LINK_TRAIN_PAT2              (1 << 8)
9468 #define  DP_TP_CTL_LINK_TRAIN_PAT3              (4 << 8)
9469 #define  DP_TP_CTL_LINK_TRAIN_PAT4              (5 << 8)
9470 #define  DP_TP_CTL_LINK_TRAIN_IDLE              (2 << 8)
9471 #define  DP_TP_CTL_LINK_TRAIN_NORMAL            (3 << 8)
9472 #define  DP_TP_CTL_SCRAMBLE_DISABLE             (1 << 7)
9473
9474 /* DisplayPort Transport Status */
9475 #define _DP_TP_STATUS_A                 0x64044
9476 #define _DP_TP_STATUS_B                 0x64144
9477 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
9478 #define  DP_TP_STATUS_FEC_ENABLE_LIVE           (1 << 28)
9479 #define  DP_TP_STATUS_IDLE_DONE                 (1 << 25)
9480 #define  DP_TP_STATUS_ACT_SENT                  (1 << 24)
9481 #define  DP_TP_STATUS_MODE_STATUS_MST           (1 << 23)
9482 #define  DP_TP_STATUS_AUTOTRAIN_DONE            (1 << 12)
9483 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC2       (3 << 8)
9484 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC1       (3 << 4)
9485 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0       (3 << 0)
9486
9487 /* DDI Buffer Control */
9488 #define _DDI_BUF_CTL_A                          0x64000
9489 #define _DDI_BUF_CTL_B                          0x64100
9490 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
9491 #define  DDI_BUF_CTL_ENABLE                     (1 << 31)
9492 #define  DDI_BUF_TRANS_SELECT(n)        ((n) << 24)
9493 #define  DDI_BUF_EMP_MASK                       (0xf << 24)
9494 #define  DDI_BUF_PORT_REVERSAL                  (1 << 16)
9495 #define  DDI_BUF_IS_IDLE                        (1 << 7)
9496 #define  DDI_A_4_LANES                          (1 << 4)
9497 #define  DDI_PORT_WIDTH(width)                  (((width) - 1) << 1)
9498 #define  DDI_PORT_WIDTH_MASK                    (7 << 1)
9499 #define  DDI_PORT_WIDTH_SHIFT                   1
9500 #define  DDI_INIT_DISPLAY_DETECTED              (1 << 0)
9501
9502 /* DDI Buffer Translations */
9503 #define _DDI_BUF_TRANS_A                0x64E00
9504 #define _DDI_BUF_TRANS_B                0x64E60
9505 #define DDI_BUF_TRANS_LO(port, i)       _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
9506 #define  DDI_BUF_BALANCE_LEG_ENABLE     (1 << 31)
9507 #define DDI_BUF_TRANS_HI(port, i)       _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
9508
9509 /* Sideband Interface (SBI) is programmed indirectly, via
9510  * SBI_ADDR, which contains the register offset; and SBI_DATA,
9511  * which contains the payload */
9512 #define SBI_ADDR                        _MMIO(0xC6000)
9513 #define SBI_DATA                        _MMIO(0xC6004)
9514 #define SBI_CTL_STAT                    _MMIO(0xC6008)
9515 #define  SBI_CTL_DEST_ICLK              (0x0 << 16)
9516 #define  SBI_CTL_DEST_MPHY              (0x1 << 16)
9517 #define  SBI_CTL_OP_IORD                (0x2 << 8)
9518 #define  SBI_CTL_OP_IOWR                (0x3 << 8)
9519 #define  SBI_CTL_OP_CRRD                (0x6 << 8)
9520 #define  SBI_CTL_OP_CRWR                (0x7 << 8)
9521 #define  SBI_RESPONSE_FAIL              (0x1 << 1)
9522 #define  SBI_RESPONSE_SUCCESS           (0x0 << 1)
9523 #define  SBI_BUSY                       (0x1 << 0)
9524 #define  SBI_READY                      (0x0 << 0)
9525
9526 /* SBI offsets */
9527 #define  SBI_SSCDIVINTPHASE                     0x0200
9528 #define  SBI_SSCDIVINTPHASE6                    0x0600
9529 #define   SBI_SSCDIVINTPHASE_DIVSEL_SHIFT       1
9530 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK        (0x7f << 1)
9531 #define   SBI_SSCDIVINTPHASE_DIVSEL(x)          ((x) << 1)
9532 #define   SBI_SSCDIVINTPHASE_INCVAL_SHIFT       8
9533 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK        (0x7f << 8)
9534 #define   SBI_SSCDIVINTPHASE_INCVAL(x)          ((x) << 8)
9535 #define   SBI_SSCDIVINTPHASE_DIR(x)             ((x) << 15)
9536 #define   SBI_SSCDIVINTPHASE_PROPAGATE          (1 << 0)
9537 #define  SBI_SSCDITHPHASE                       0x0204
9538 #define  SBI_SSCCTL                             0x020c
9539 #define  SBI_SSCCTL6                            0x060C
9540 #define   SBI_SSCCTL_PATHALT                    (1 << 3)
9541 #define   SBI_SSCCTL_DISABLE                    (1 << 0)
9542 #define  SBI_SSCAUXDIV6                         0x0610
9543 #define   SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT      4
9544 #define   SBI_SSCAUXDIV_FINALDIV2SEL_MASK       (1 << 4)
9545 #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)         ((x) << 4)
9546 #define  SBI_DBUFF0                             0x2a00
9547 #define  SBI_GEN0                               0x1f00
9548 #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE       (1 << 0)
9549
9550 /* LPT PIXCLK_GATE */
9551 #define PIXCLK_GATE                     _MMIO(0xC6020)
9552 #define  PIXCLK_GATE_UNGATE             (1 << 0)
9553 #define  PIXCLK_GATE_GATE               (0 << 0)
9554
9555 /* SPLL */
9556 #define SPLL_CTL                        _MMIO(0x46020)
9557 #define  SPLL_PLL_ENABLE                (1 << 31)
9558 #define  SPLL_REF_BCLK                  (0 << 28)
9559 #define  SPLL_REF_MUXED_SSC             (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
9560 #define  SPLL_REF_NON_SSC_HSW           (2 << 28)
9561 #define  SPLL_REF_PCH_SSC_BDW           (2 << 28)
9562 #define  SPLL_REF_LCPLL                 (3 << 28)
9563 #define  SPLL_REF_MASK                  (3 << 28)
9564 #define  SPLL_FREQ_810MHz               (0 << 26)
9565 #define  SPLL_FREQ_1350MHz              (1 << 26)
9566 #define  SPLL_FREQ_2700MHz              (2 << 26)
9567 #define  SPLL_FREQ_MASK                 (3 << 26)
9568
9569 /* WRPLL */
9570 #define _WRPLL_CTL1                     0x46040
9571 #define _WRPLL_CTL2                     0x46060
9572 #define WRPLL_CTL(pll)                  _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
9573 #define  WRPLL_PLL_ENABLE               (1 << 31)
9574 #define  WRPLL_REF_BCLK                 (0 << 28)
9575 #define  WRPLL_REF_PCH_SSC              (1 << 28)
9576 #define  WRPLL_REF_MUXED_SSC_BDW        (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
9577 #define  WRPLL_REF_SPECIAL_HSW          (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
9578 #define  WRPLL_REF_LCPLL                (3 << 28)
9579 #define  WRPLL_REF_MASK                 (3 << 28)
9580 /* WRPLL divider programming */
9581 #define  WRPLL_DIVIDER_REFERENCE(x)     ((x) << 0)
9582 #define  WRPLL_DIVIDER_REF_MASK         (0xff)
9583 #define  WRPLL_DIVIDER_POST(x)          ((x) << 8)
9584 #define  WRPLL_DIVIDER_POST_MASK        (0x3f << 8)
9585 #define  WRPLL_DIVIDER_POST_SHIFT       8
9586 #define  WRPLL_DIVIDER_FEEDBACK(x)      ((x) << 16)
9587 #define  WRPLL_DIVIDER_FB_SHIFT         16
9588 #define  WRPLL_DIVIDER_FB_MASK          (0xff << 16)
9589
9590 /* Port clock selection */
9591 #define _PORT_CLK_SEL_A                 0x46100
9592 #define _PORT_CLK_SEL_B                 0x46104
9593 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
9594 #define  PORT_CLK_SEL_LCPLL_2700        (0 << 29)
9595 #define  PORT_CLK_SEL_LCPLL_1350        (1 << 29)
9596 #define  PORT_CLK_SEL_LCPLL_810         (2 << 29)
9597 #define  PORT_CLK_SEL_SPLL              (3 << 29)
9598 #define  PORT_CLK_SEL_WRPLL(pll)        (((pll) + 4) << 29)
9599 #define  PORT_CLK_SEL_WRPLL1            (4 << 29)
9600 #define  PORT_CLK_SEL_WRPLL2            (5 << 29)
9601 #define  PORT_CLK_SEL_NONE              (7 << 29)
9602 #define  PORT_CLK_SEL_MASK              (7 << 29)
9603
9604 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
9605 #define DDI_CLK_SEL(port)               PORT_CLK_SEL(port)
9606 #define  DDI_CLK_SEL_NONE               (0x0 << 28)
9607 #define  DDI_CLK_SEL_MG                 (0x8 << 28)
9608 #define  DDI_CLK_SEL_TBT_162            (0xC << 28)
9609 #define  DDI_CLK_SEL_TBT_270            (0xD << 28)
9610 #define  DDI_CLK_SEL_TBT_540            (0xE << 28)
9611 #define  DDI_CLK_SEL_TBT_810            (0xF << 28)
9612 #define  DDI_CLK_SEL_MASK               (0xF << 28)
9613
9614 /* Transcoder clock selection */
9615 #define _TRANS_CLK_SEL_A                0x46140
9616 #define _TRANS_CLK_SEL_B                0x46144
9617 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
9618 /* For each transcoder, we need to select the corresponding port clock */
9619 #define  TRANS_CLK_SEL_DISABLED         (0x0 << 29)
9620 #define  TRANS_CLK_SEL_PORT(x)          (((x) + 1) << 29)
9621 #define  TGL_TRANS_CLK_SEL_DISABLED     (0x0 << 28)
9622 #define  TGL_TRANS_CLK_SEL_PORT(x)      (((x) + 1) << 28)
9623
9624
9625 #define CDCLK_FREQ                      _MMIO(0x46200)
9626
9627 #define _TRANSA_MSA_MISC                0x60410
9628 #define _TRANSB_MSA_MISC                0x61410
9629 #define _TRANSC_MSA_MISC                0x62410
9630 #define _TRANS_EDP_MSA_MISC             0x6f410
9631 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9632
9633 #define  TRANS_MSA_SYNC_CLK             (1 << 0)
9634 #define  TRANS_MSA_SAMPLING_444         (2 << 1)
9635 #define  TRANS_MSA_CLRSP_YCBCR          (2 << 3)
9636 #define  TRANS_MSA_6_BPC                (0 << 5)
9637 #define  TRANS_MSA_8_BPC                (1 << 5)
9638 #define  TRANS_MSA_10_BPC               (2 << 5)
9639 #define  TRANS_MSA_12_BPC               (3 << 5)
9640 #define  TRANS_MSA_16_BPC               (4 << 5)
9641 #define  TRANS_MSA_CEA_RANGE            (1 << 3)
9642 #define  TRANS_MSA_USE_VSC_SDP          (1 << 14)
9643
9644 /* LCPLL Control */
9645 #define LCPLL_CTL                       _MMIO(0x130040)
9646 #define  LCPLL_PLL_DISABLE              (1 << 31)
9647 #define  LCPLL_PLL_LOCK                 (1 << 30)
9648 #define  LCPLL_REF_NON_SSC              (0 << 28)
9649 #define  LCPLL_REF_BCLK                 (2 << 28)
9650 #define  LCPLL_REF_PCH_SSC              (3 << 28)
9651 #define  LCPLL_REF_MASK                 (3 << 28)
9652 #define  LCPLL_CLK_FREQ_MASK            (3 << 26)
9653 #define  LCPLL_CLK_FREQ_450             (0 << 26)
9654 #define  LCPLL_CLK_FREQ_54O_BDW         (1 << 26)
9655 #define  LCPLL_CLK_FREQ_337_5_BDW       (2 << 26)
9656 #define  LCPLL_CLK_FREQ_675_BDW         (3 << 26)
9657 #define  LCPLL_CD_CLOCK_DISABLE         (1 << 25)
9658 #define  LCPLL_ROOT_CD_CLOCK_DISABLE    (1 << 24)
9659 #define  LCPLL_CD2X_CLOCK_DISABLE       (1 << 23)
9660 #define  LCPLL_POWER_DOWN_ALLOW         (1 << 22)
9661 #define  LCPLL_CD_SOURCE_FCLK           (1 << 21)
9662 #define  LCPLL_CD_SOURCE_FCLK_DONE      (1 << 19)
9663
9664 /*
9665  * SKL Clocks
9666  */
9667
9668 /* CDCLK_CTL */
9669 #define CDCLK_CTL                       _MMIO(0x46000)
9670 #define  CDCLK_FREQ_SEL_MASK            (3 << 26)
9671 #define  CDCLK_FREQ_450_432             (0 << 26)
9672 #define  CDCLK_FREQ_540                 (1 << 26)
9673 #define  CDCLK_FREQ_337_308             (2 << 26)
9674 #define  CDCLK_FREQ_675_617             (3 << 26)
9675 #define  BXT_CDCLK_CD2X_DIV_SEL_MASK    (3 << 22)
9676 #define  BXT_CDCLK_CD2X_DIV_SEL_1       (0 << 22)
9677 #define  BXT_CDCLK_CD2X_DIV_SEL_1_5     (1 << 22)
9678 #define  BXT_CDCLK_CD2X_DIV_SEL_2       (2 << 22)
9679 #define  BXT_CDCLK_CD2X_DIV_SEL_4       (3 << 22)
9680 #define  BXT_CDCLK_CD2X_PIPE(pipe)      ((pipe) << 20)
9681 #define  CDCLK_DIVMUX_CD_OVERRIDE       (1 << 19)
9682 #define  BXT_CDCLK_CD2X_PIPE_NONE       BXT_CDCLK_CD2X_PIPE(3)
9683 #define  ICL_CDCLK_CD2X_PIPE_NONE       (7 << 19)
9684 #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
9685 #define  CDCLK_FREQ_DECIMAL_MASK        (0x7ff)
9686
9687 /* LCPLL_CTL */
9688 #define LCPLL1_CTL              _MMIO(0x46010)
9689 #define LCPLL2_CTL              _MMIO(0x46014)
9690 #define  LCPLL_PLL_ENABLE       (1 << 31)
9691
9692 /* DPLL control1 */
9693 #define DPLL_CTRL1              _MMIO(0x6C058)
9694 #define  DPLL_CTRL1_HDMI_MODE(id)               (1 << ((id) * 6 + 5))
9695 #define  DPLL_CTRL1_SSC(id)                     (1 << ((id) * 6 + 4))
9696 #define  DPLL_CTRL1_LINK_RATE_MASK(id)          (7 << ((id) * 6 + 1))
9697 #define  DPLL_CTRL1_LINK_RATE_SHIFT(id)         ((id) * 6 + 1)
9698 #define  DPLL_CTRL1_LINK_RATE(linkrate, id)     ((linkrate) << ((id) * 6 + 1))
9699 #define  DPLL_CTRL1_OVERRIDE(id)                (1 << ((id) * 6))
9700 #define  DPLL_CTRL1_LINK_RATE_2700              0
9701 #define  DPLL_CTRL1_LINK_RATE_1350              1
9702 #define  DPLL_CTRL1_LINK_RATE_810               2
9703 #define  DPLL_CTRL1_LINK_RATE_1620              3
9704 #define  DPLL_CTRL1_LINK_RATE_1080              4
9705 #define  DPLL_CTRL1_LINK_RATE_2160              5
9706
9707 /* DPLL control2 */
9708 #define DPLL_CTRL2                              _MMIO(0x6C05C)
9709 #define  DPLL_CTRL2_DDI_CLK_OFF(port)           (1 << ((port) + 15))
9710 #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)      (3 << ((port) * 3 + 1))
9711 #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port) * 3 + 1)
9712 #define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)      ((clk) << ((port) * 3 + 1))
9713 #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1 << ((port) * 3))
9714
9715 /* DPLL Status */
9716 #define DPLL_STATUS     _MMIO(0x6C060)
9717 #define  DPLL_LOCK(id) (1 << ((id) * 8))
9718
9719 /* DPLL cfg */
9720 #define _DPLL1_CFGCR1   0x6C040
9721 #define _DPLL2_CFGCR1   0x6C048
9722 #define _DPLL3_CFGCR1   0x6C050
9723 #define  DPLL_CFGCR1_FREQ_ENABLE        (1 << 31)
9724 #define  DPLL_CFGCR1_DCO_FRACTION_MASK  (0x7fff << 9)
9725 #define  DPLL_CFGCR1_DCO_FRACTION(x)    ((x) << 9)
9726 #define  DPLL_CFGCR1_DCO_INTEGER_MASK   (0x1ff)
9727
9728 #define _DPLL1_CFGCR2   0x6C044
9729 #define _DPLL2_CFGCR2   0x6C04C
9730 #define _DPLL3_CFGCR2   0x6C054
9731 #define  DPLL_CFGCR2_QDIV_RATIO_MASK    (0xff << 8)
9732 #define  DPLL_CFGCR2_QDIV_RATIO(x)      ((x) << 8)
9733 #define  DPLL_CFGCR2_QDIV_MODE(x)       ((x) << 7)
9734 #define  DPLL_CFGCR2_KDIV_MASK          (3 << 5)
9735 #define  DPLL_CFGCR2_KDIV(x)            ((x) << 5)
9736 #define  DPLL_CFGCR2_KDIV_5 (0 << 5)
9737 #define  DPLL_CFGCR2_KDIV_2 (1 << 5)
9738 #define  DPLL_CFGCR2_KDIV_3 (2 << 5)
9739 #define  DPLL_CFGCR2_KDIV_1 (3 << 5)
9740 #define  DPLL_CFGCR2_PDIV_MASK          (7 << 2)
9741 #define  DPLL_CFGCR2_PDIV(x)            ((x) << 2)
9742 #define  DPLL_CFGCR2_PDIV_1 (0 << 2)
9743 #define  DPLL_CFGCR2_PDIV_2 (1 << 2)
9744 #define  DPLL_CFGCR2_PDIV_3 (2 << 2)
9745 #define  DPLL_CFGCR2_PDIV_7 (4 << 2)
9746 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK  (3)
9747
9748 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
9749 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
9750
9751 /*
9752  * CNL Clocks
9753  */
9754 #define DPCLKA_CFGCR0                           _MMIO(0x6C200)
9755 #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)        (1 << ((port) ==  PORT_F ? 23 : \
9756                                                       (port) + 10))
9757 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)  ((port) == PORT_F ? 21 : \
9758                                                 (port) * 2)
9759 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)   (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9760 #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)   ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9761
9762 #define ICL_DPCLKA_CFGCR0                       _MMIO(0x164280)
9763 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)     (1 << _PICK(phy, 10, 11, 24))
9764 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)  (1 << ((tc_port) < PORT_TC4 ? \
9765                                                        (tc_port) + 12 : \
9766                                                        (tc_port) - PORT_TC4 + 21))
9767 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)       ((phy) * 2)
9768 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)        (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
9769 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)        ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
9770
9771 /* CNL PLL */
9772 #define DPLL0_ENABLE            0x46010
9773 #define DPLL1_ENABLE            0x46014
9774 #define  PLL_ENABLE             (1 << 31)
9775 #define  PLL_LOCK               (1 << 30)
9776 #define  PLL_POWER_ENABLE       (1 << 27)
9777 #define  PLL_POWER_STATE        (1 << 26)
9778 #define CNL_DPLL_ENABLE(pll)    _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
9779
9780 #define TBT_PLL_ENABLE          _MMIO(0x46020)
9781
9782 #define _MG_PLL1_ENABLE         0x46030
9783 #define _MG_PLL2_ENABLE         0x46034
9784 #define _MG_PLL3_ENABLE         0x46038
9785 #define _MG_PLL4_ENABLE         0x4603C
9786 /* Bits are the same as DPLL0_ENABLE */
9787 #define MG_PLL_ENABLE(tc_port)  _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
9788                                            _MG_PLL2_ENABLE)
9789
9790 #define _MG_REFCLKIN_CTL_PORT1                          0x16892C
9791 #define _MG_REFCLKIN_CTL_PORT2                          0x16992C
9792 #define _MG_REFCLKIN_CTL_PORT3                          0x16A92C
9793 #define _MG_REFCLKIN_CTL_PORT4                          0x16B92C
9794 #define   MG_REFCLKIN_CTL_OD_2_MUX(x)                   ((x) << 8)
9795 #define   MG_REFCLKIN_CTL_OD_2_MUX_MASK                 (0x7 << 8)
9796 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
9797                                             _MG_REFCLKIN_CTL_PORT1, \
9798                                             _MG_REFCLKIN_CTL_PORT2)
9799
9800 #define _MG_CLKTOP2_CORECLKCTL1_PORT1                   0x1688D8
9801 #define _MG_CLKTOP2_CORECLKCTL1_PORT2                   0x1698D8
9802 #define _MG_CLKTOP2_CORECLKCTL1_PORT3                   0x16A8D8
9803 #define _MG_CLKTOP2_CORECLKCTL1_PORT4                   0x16B8D8
9804 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)          ((x) << 16)
9805 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK        (0xff << 16)
9806 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)          ((x) << 8)
9807 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK        (0xff << 8)
9808 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
9809                                                    _MG_CLKTOP2_CORECLKCTL1_PORT1, \
9810                                                    _MG_CLKTOP2_CORECLKCTL1_PORT2)
9811
9812 #define _MG_CLKTOP2_HSCLKCTL_PORT1                      0x1688D4
9813 #define _MG_CLKTOP2_HSCLKCTL_PORT2                      0x1698D4
9814 #define _MG_CLKTOP2_HSCLKCTL_PORT3                      0x16A8D4
9815 #define _MG_CLKTOP2_HSCLKCTL_PORT4                      0x16B8D4
9816 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)          ((x) << 16)
9817 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK        (0x1 << 16)
9818 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)        ((x) << 14)
9819 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK      (0x3 << 14)
9820 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK          (0x3 << 12)
9821 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2             (0 << 12)
9822 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3             (1 << 12)
9823 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5             (2 << 12)
9824 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7             (3 << 12)
9825 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)            ((x) << 8)
9826 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT         8
9827 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK          (0xf << 8)
9828 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
9829                                                 _MG_CLKTOP2_HSCLKCTL_PORT1, \
9830                                                 _MG_CLKTOP2_HSCLKCTL_PORT2)
9831
9832 #define _MG_PLL_DIV0_PORT1                              0x168A00
9833 #define _MG_PLL_DIV0_PORT2                              0x169A00
9834 #define _MG_PLL_DIV0_PORT3                              0x16AA00
9835 #define _MG_PLL_DIV0_PORT4                              0x16BA00
9836 #define   MG_PLL_DIV0_FRACNEN_H                         (1 << 30)
9837 #define   MG_PLL_DIV0_FBDIV_FRAC_MASK                   (0x3fffff << 8)
9838 #define   MG_PLL_DIV0_FBDIV_FRAC_SHIFT                  8
9839 #define   MG_PLL_DIV0_FBDIV_FRAC(x)                     ((x) << 8)
9840 #define   MG_PLL_DIV0_FBDIV_INT_MASK                    (0xff << 0)
9841 #define   MG_PLL_DIV0_FBDIV_INT(x)                      ((x) << 0)
9842 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
9843                                         _MG_PLL_DIV0_PORT2)
9844
9845 #define _MG_PLL_DIV1_PORT1                              0x168A04
9846 #define _MG_PLL_DIV1_PORT2                              0x169A04
9847 #define _MG_PLL_DIV1_PORT3                              0x16AA04
9848 #define _MG_PLL_DIV1_PORT4                              0x16BA04
9849 #define   MG_PLL_DIV1_IREF_NDIVRATIO(x)                 ((x) << 16)
9850 #define   MG_PLL_DIV1_DITHER_DIV_1                      (0 << 12)
9851 #define   MG_PLL_DIV1_DITHER_DIV_2                      (1 << 12)
9852 #define   MG_PLL_DIV1_DITHER_DIV_4                      (2 << 12)
9853 #define   MG_PLL_DIV1_DITHER_DIV_8                      (3 << 12)
9854 #define   MG_PLL_DIV1_NDIVRATIO(x)                      ((x) << 4)
9855 #define   MG_PLL_DIV1_FBPREDIV_MASK                     (0xf << 0)
9856 #define   MG_PLL_DIV1_FBPREDIV(x)                       ((x) << 0)
9857 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
9858                                         _MG_PLL_DIV1_PORT2)
9859
9860 #define _MG_PLL_LF_PORT1                                0x168A08
9861 #define _MG_PLL_LF_PORT2                                0x169A08
9862 #define _MG_PLL_LF_PORT3                                0x16AA08
9863 #define _MG_PLL_LF_PORT4                                0x16BA08
9864 #define   MG_PLL_LF_TDCTARGETCNT(x)                     ((x) << 24)
9865 #define   MG_PLL_LF_AFCCNTSEL_256                       (0 << 20)
9866 #define   MG_PLL_LF_AFCCNTSEL_512                       (1 << 20)
9867 #define   MG_PLL_LF_GAINCTRL(x)                         ((x) << 16)
9868 #define   MG_PLL_LF_INT_COEFF(x)                        ((x) << 8)
9869 #define   MG_PLL_LF_PROP_COEFF(x)                       ((x) << 0)
9870 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
9871                                       _MG_PLL_LF_PORT2)
9872
9873 #define _MG_PLL_FRAC_LOCK_PORT1                         0x168A0C
9874 #define _MG_PLL_FRAC_LOCK_PORT2                         0x169A0C
9875 #define _MG_PLL_FRAC_LOCK_PORT3                         0x16AA0C
9876 #define _MG_PLL_FRAC_LOCK_PORT4                         0x16BA0C
9877 #define   MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32             (1 << 18)
9878 #define   MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32            (1 << 16)
9879 #define   MG_PLL_FRAC_LOCK_LOCKTHRESH(x)                ((x) << 11)
9880 #define   MG_PLL_FRAC_LOCK_DCODITHEREN                  (1 << 10)
9881 #define   MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN               (1 << 8)
9882 #define   MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)              ((x) << 0)
9883 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
9884                                              _MG_PLL_FRAC_LOCK_PORT1, \
9885                                              _MG_PLL_FRAC_LOCK_PORT2)
9886
9887 #define _MG_PLL_SSC_PORT1                               0x168A10
9888 #define _MG_PLL_SSC_PORT2                               0x169A10
9889 #define _MG_PLL_SSC_PORT3                               0x16AA10
9890 #define _MG_PLL_SSC_PORT4                               0x16BA10
9891 #define   MG_PLL_SSC_EN                                 (1 << 28)
9892 #define   MG_PLL_SSC_TYPE(x)                            ((x) << 26)
9893 #define   MG_PLL_SSC_STEPLENGTH(x)                      ((x) << 16)
9894 #define   MG_PLL_SSC_STEPNUM(x)                         ((x) << 10)
9895 #define   MG_PLL_SSC_FLLEN                              (1 << 9)
9896 #define   MG_PLL_SSC_STEPSIZE(x)                        ((x) << 0)
9897 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
9898                                        _MG_PLL_SSC_PORT2)
9899
9900 #define _MG_PLL_BIAS_PORT1                              0x168A14
9901 #define _MG_PLL_BIAS_PORT2                              0x169A14
9902 #define _MG_PLL_BIAS_PORT3                              0x16AA14
9903 #define _MG_PLL_BIAS_PORT4                              0x16BA14
9904 #define   MG_PLL_BIAS_BIAS_GB_SEL(x)                    ((x) << 30)
9905 #define   MG_PLL_BIAS_BIAS_GB_SEL_MASK                  (0x3 << 30)
9906 #define   MG_PLL_BIAS_INIT_DCOAMP(x)                    ((x) << 24)
9907 #define   MG_PLL_BIAS_INIT_DCOAMP_MASK                  (0x3f << 24)
9908 #define   MG_PLL_BIAS_BIAS_BONUS(x)                     ((x) << 16)
9909 #define   MG_PLL_BIAS_BIAS_BONUS_MASK                   (0xff << 16)
9910 #define   MG_PLL_BIAS_BIASCAL_EN                        (1 << 15)
9911 #define   MG_PLL_BIAS_CTRIM(x)                          ((x) << 8)
9912 #define   MG_PLL_BIAS_CTRIM_MASK                        (0x1f << 8)
9913 #define   MG_PLL_BIAS_VREF_RDAC(x)                      ((x) << 5)
9914 #define   MG_PLL_BIAS_VREF_RDAC_MASK                    (0x7 << 5)
9915 #define   MG_PLL_BIAS_IREFTRIM(x)                       ((x) << 0)
9916 #define   MG_PLL_BIAS_IREFTRIM_MASK                     (0x1f << 0)
9917 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
9918                                         _MG_PLL_BIAS_PORT2)
9919
9920 #define _MG_PLL_TDC_COLDST_BIAS_PORT1                   0x168A18
9921 #define _MG_PLL_TDC_COLDST_BIAS_PORT2                   0x169A18
9922 #define _MG_PLL_TDC_COLDST_BIAS_PORT3                   0x16AA18
9923 #define _MG_PLL_TDC_COLDST_BIAS_PORT4                   0x16BA18
9924 #define   MG_PLL_TDC_COLDST_IREFINT_EN                  (1 << 27)
9925 #define   MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x)    ((x) << 17)
9926 #define   MG_PLL_TDC_COLDST_COLDSTART                   (1 << 16)
9927 #define   MG_PLL_TDC_TDCOVCCORR_EN                      (1 << 2)
9928 #define   MG_PLL_TDC_TDCSEL(x)                          ((x) << 0)
9929 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
9930                                                    _MG_PLL_TDC_COLDST_BIAS_PORT1, \
9931                                                    _MG_PLL_TDC_COLDST_BIAS_PORT2)
9932
9933 #define _CNL_DPLL0_CFGCR0               0x6C000
9934 #define _CNL_DPLL1_CFGCR0               0x6C080
9935 #define  DPLL_CFGCR0_HDMI_MODE          (1 << 30)
9936 #define  DPLL_CFGCR0_SSC_ENABLE         (1 << 29)
9937 #define  DPLL_CFGCR0_SSC_ENABLE_ICL     (1 << 25)
9938 #define  DPLL_CFGCR0_LINK_RATE_MASK     (0xf << 25)
9939 #define  DPLL_CFGCR0_LINK_RATE_2700     (0 << 25)
9940 #define  DPLL_CFGCR0_LINK_RATE_1350     (1 << 25)
9941 #define  DPLL_CFGCR0_LINK_RATE_810      (2 << 25)
9942 #define  DPLL_CFGCR0_LINK_RATE_1620     (3 << 25)
9943 #define  DPLL_CFGCR0_LINK_RATE_1080     (4 << 25)
9944 #define  DPLL_CFGCR0_LINK_RATE_2160     (5 << 25)
9945 #define  DPLL_CFGCR0_LINK_RATE_3240     (6 << 25)
9946 #define  DPLL_CFGCR0_LINK_RATE_4050     (7 << 25)
9947 #define  DPLL_CFGCR0_DCO_FRACTION_MASK  (0x7fff << 10)
9948 #define  DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
9949 #define  DPLL_CFGCR0_DCO_FRACTION(x)    ((x) << 10)
9950 #define  DPLL_CFGCR0_DCO_INTEGER_MASK   (0x3ff)
9951 #define CNL_DPLL_CFGCR0(pll)            _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
9952
9953 #define _CNL_DPLL0_CFGCR1               0x6C004
9954 #define _CNL_DPLL1_CFGCR1               0x6C084
9955 #define  DPLL_CFGCR1_QDIV_RATIO_MASK    (0xff << 10)
9956 #define  DPLL_CFGCR1_QDIV_RATIO_SHIFT   (10)
9957 #define  DPLL_CFGCR1_QDIV_RATIO(x)      ((x) << 10)
9958 #define  DPLL_CFGCR1_QDIV_MODE_SHIFT    (9)
9959 #define  DPLL_CFGCR1_QDIV_MODE(x)       ((x) << 9)
9960 #define  DPLL_CFGCR1_KDIV_MASK          (7 << 6)
9961 #define  DPLL_CFGCR1_KDIV_SHIFT         (6)
9962 #define  DPLL_CFGCR1_KDIV(x)            ((x) << 6)
9963 #define  DPLL_CFGCR1_KDIV_1             (1 << 6)
9964 #define  DPLL_CFGCR1_KDIV_2             (2 << 6)
9965 #define  DPLL_CFGCR1_KDIV_3             (4 << 6)
9966 #define  DPLL_CFGCR1_PDIV_MASK          (0xf << 2)
9967 #define  DPLL_CFGCR1_PDIV_SHIFT         (2)
9968 #define  DPLL_CFGCR1_PDIV(x)            ((x) << 2)
9969 #define  DPLL_CFGCR1_PDIV_2             (1 << 2)
9970 #define  DPLL_CFGCR1_PDIV_3             (2 << 2)
9971 #define  DPLL_CFGCR1_PDIV_5             (4 << 2)
9972 #define  DPLL_CFGCR1_PDIV_7             (8 << 2)
9973 #define  DPLL_CFGCR1_CENTRAL_FREQ       (3 << 0)
9974 #define  DPLL_CFGCR1_CENTRAL_FREQ_8400  (3 << 0)
9975 #define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL  (0 << 0)
9976 #define CNL_DPLL_CFGCR1(pll)            _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
9977
9978 #define _ICL_DPLL0_CFGCR0               0x164000
9979 #define _ICL_DPLL1_CFGCR0               0x164080
9980 #define ICL_DPLL_CFGCR0(pll)            _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
9981                                                   _ICL_DPLL1_CFGCR0)
9982
9983 #define _ICL_DPLL0_CFGCR1               0x164004
9984 #define _ICL_DPLL1_CFGCR1               0x164084
9985 #define ICL_DPLL_CFGCR1(pll)            _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
9986                                                   _ICL_DPLL1_CFGCR1)
9987
9988 #define _TGL_DPLL0_CFGCR0               0x164284
9989 #define _TGL_DPLL1_CFGCR0               0x16428C
9990 /* TODO: add DPLL4 */
9991 #define _TGL_TBTPLL_CFGCR0              0x16429C
9992 #define TGL_DPLL_CFGCR0(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
9993                                                   _TGL_DPLL1_CFGCR0, \
9994                                                   _TGL_TBTPLL_CFGCR0)
9995
9996 #define _TGL_DPLL0_CFGCR1               0x164288
9997 #define _TGL_DPLL1_CFGCR1               0x164290
9998 /* TODO: add DPLL4 */
9999 #define _TGL_TBTPLL_CFGCR1              0x1642A0
10000 #define TGL_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
10001                                                    _TGL_DPLL1_CFGCR1, \
10002                                                    _TGL_TBTPLL_CFGCR1)
10003
10004 /* BXT display engine PLL */
10005 #define BXT_DE_PLL_CTL                  _MMIO(0x6d000)
10006 #define   BXT_DE_PLL_RATIO(x)           (x)     /* {60,65,100} * 19.2MHz */
10007 #define   BXT_DE_PLL_RATIO_MASK         0xff
10008
10009 #define BXT_DE_PLL_ENABLE               _MMIO(0x46070)
10010 #define   BXT_DE_PLL_PLL_ENABLE         (1 << 31)
10011 #define   BXT_DE_PLL_LOCK               (1 << 30)
10012 #define   CNL_CDCLK_PLL_RATIO(x)        (x)
10013 #define   CNL_CDCLK_PLL_RATIO_MASK      0xff
10014
10015 /* GEN9 DC */
10016 #define DC_STATE_EN                     _MMIO(0x45504)
10017 #define  DC_STATE_DISABLE               0
10018 #define  DC_STATE_EN_UPTO_DC5           (1 << 0)
10019 #define  DC_STATE_EN_DC9                (1 << 3)
10020 #define  DC_STATE_EN_UPTO_DC6           (2 << 0)
10021 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
10022
10023 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
10024 #define  DC_STATE_DEBUG_MASK_CORES      (1 << 0)
10025 #define  DC_STATE_DEBUG_MASK_MEMORY_UP  (1 << 1)
10026
10027 #define BXT_P_CR_MC_BIOS_REQ_0_0_0      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
10028 #define  BXT_REQ_DATA_MASK                      0x3F
10029 #define  BXT_DRAM_CHANNEL_ACTIVE_SHIFT          12
10030 #define  BXT_DRAM_CHANNEL_ACTIVE_MASK           (0xF << 12)
10031 #define  BXT_MEMORY_FREQ_MULTIPLIER_HZ          133333333
10032
10033 #define BXT_D_CR_DRP0_DUNIT8                    0x1000
10034 #define BXT_D_CR_DRP0_DUNIT9                    0x1200
10035 #define  BXT_D_CR_DRP0_DUNIT_START              8
10036 #define  BXT_D_CR_DRP0_DUNIT_END                11
10037 #define BXT_D_CR_DRP0_DUNIT(x)  _MMIO(MCHBAR_MIRROR_BASE_SNB + \
10038                                       _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
10039                                                  BXT_D_CR_DRP0_DUNIT9))
10040 #define  BXT_DRAM_RANK_MASK                     0x3
10041 #define  BXT_DRAM_RANK_SINGLE                   0x1
10042 #define  BXT_DRAM_RANK_DUAL                     0x3
10043 #define  BXT_DRAM_WIDTH_MASK                    (0x3 << 4)
10044 #define  BXT_DRAM_WIDTH_SHIFT                   4
10045 #define  BXT_DRAM_WIDTH_X8                      (0x0 << 4)
10046 #define  BXT_DRAM_WIDTH_X16                     (0x1 << 4)
10047 #define  BXT_DRAM_WIDTH_X32                     (0x2 << 4)
10048 #define  BXT_DRAM_WIDTH_X64                     (0x3 << 4)
10049 #define  BXT_DRAM_SIZE_MASK                     (0x7 << 6)
10050 #define  BXT_DRAM_SIZE_SHIFT                    6
10051 #define  BXT_DRAM_SIZE_4GBIT                    (0x0 << 6)
10052 #define  BXT_DRAM_SIZE_6GBIT                    (0x1 << 6)
10053 #define  BXT_DRAM_SIZE_8GBIT                    (0x2 << 6)
10054 #define  BXT_DRAM_SIZE_12GBIT                   (0x3 << 6)
10055 #define  BXT_DRAM_SIZE_16GBIT                   (0x4 << 6)
10056 #define  BXT_DRAM_TYPE_MASK                     (0x7 << 22)
10057 #define  BXT_DRAM_TYPE_SHIFT                    22
10058 #define  BXT_DRAM_TYPE_DDR3                     (0x0 << 22)
10059 #define  BXT_DRAM_TYPE_LPDDR3                   (0x1 << 22)
10060 #define  BXT_DRAM_TYPE_LPDDR4                   (0x2 << 22)
10061 #define  BXT_DRAM_TYPE_DDR4                     (0x4 << 22)
10062
10063 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ           266666666
10064 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU       _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
10065 #define  SKL_REQ_DATA_MASK                      (0xF << 0)
10066
10067 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
10068 #define  SKL_DRAM_DDR_TYPE_MASK                 (0x3 << 0)
10069 #define  SKL_DRAM_DDR_TYPE_DDR4                 (0 << 0)
10070 #define  SKL_DRAM_DDR_TYPE_DDR3                 (1 << 0)
10071 #define  SKL_DRAM_DDR_TYPE_LPDDR3               (2 << 0)
10072 #define  SKL_DRAM_DDR_TYPE_LPDDR4               (3 << 0)
10073
10074 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
10075 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
10076 #define  SKL_DRAM_S_SHIFT                       16
10077 #define  SKL_DRAM_SIZE_MASK                     0x3F
10078 #define  SKL_DRAM_WIDTH_MASK                    (0x3 << 8)
10079 #define  SKL_DRAM_WIDTH_SHIFT                   8
10080 #define  SKL_DRAM_WIDTH_X8                      (0x0 << 8)
10081 #define  SKL_DRAM_WIDTH_X16                     (0x1 << 8)
10082 #define  SKL_DRAM_WIDTH_X32                     (0x2 << 8)
10083 #define  SKL_DRAM_RANK_MASK                     (0x1 << 10)
10084 #define  SKL_DRAM_RANK_SHIFT                    10
10085 #define  SKL_DRAM_RANK_1                        (0x0 << 10)
10086 #define  SKL_DRAM_RANK_2                        (0x1 << 10)
10087 #define  SKL_DRAM_RANK_MASK                     (0x1 << 10)
10088 #define  CNL_DRAM_SIZE_MASK                     0x7F
10089 #define  CNL_DRAM_WIDTH_MASK                    (0x3 << 7)
10090 #define  CNL_DRAM_WIDTH_SHIFT                   7
10091 #define  CNL_DRAM_WIDTH_X8                      (0x0 << 7)
10092 #define  CNL_DRAM_WIDTH_X16                     (0x1 << 7)
10093 #define  CNL_DRAM_WIDTH_X32                     (0x2 << 7)
10094 #define  CNL_DRAM_RANK_MASK                     (0x3 << 9)
10095 #define  CNL_DRAM_RANK_SHIFT                    9
10096 #define  CNL_DRAM_RANK_1                        (0x0 << 9)
10097 #define  CNL_DRAM_RANK_2                        (0x1 << 9)
10098 #define  CNL_DRAM_RANK_3                        (0x2 << 9)
10099 #define  CNL_DRAM_RANK_4                        (0x3 << 9)
10100
10101 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
10102  * since on HSW we can't write to it using I915_WRITE. */
10103 #define D_COMP_HSW                      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
10104 #define D_COMP_BDW                      _MMIO(0x138144)
10105 #define  D_COMP_RCOMP_IN_PROGRESS       (1 << 9)
10106 #define  D_COMP_COMP_FORCE              (1 << 8)
10107 #define  D_COMP_COMP_DISABLE            (1 << 0)
10108
10109 /* Pipe WM_LINETIME - watermark line time */
10110 #define _PIPE_WM_LINETIME_A             0x45270
10111 #define _PIPE_WM_LINETIME_B             0x45274
10112 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
10113 #define   PIPE_WM_LINETIME_MASK                 (0x1ff)
10114 #define   PIPE_WM_LINETIME_TIME(x)              ((x))
10115 #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK    (0x1ff << 16)
10116 #define   PIPE_WM_LINETIME_IPS_LINETIME(x)      ((x) << 16)
10117
10118 /* SFUSE_STRAP */
10119 #define SFUSE_STRAP                     _MMIO(0xc2014)
10120 #define  SFUSE_STRAP_FUSE_LOCK          (1 << 13)
10121 #define  SFUSE_STRAP_RAW_FREQUENCY      (1 << 8)
10122 #define  SFUSE_STRAP_DISPLAY_DISABLED   (1 << 7)
10123 #define  SFUSE_STRAP_CRT_DISABLED       (1 << 6)
10124 #define  SFUSE_STRAP_DDIF_DETECTED      (1 << 3)
10125 #define  SFUSE_STRAP_DDIB_DETECTED      (1 << 2)
10126 #define  SFUSE_STRAP_DDIC_DETECTED      (1 << 1)
10127 #define  SFUSE_STRAP_DDID_DETECTED      (1 << 0)
10128
10129 #define WM_MISC                         _MMIO(0x45260)
10130 #define  WM_MISC_DATA_PARTITION_5_6     (1 << 0)
10131
10132 #define WM_DBG                          _MMIO(0x45280)
10133 #define  WM_DBG_DISALLOW_MULTIPLE_LP    (1 << 0)
10134 #define  WM_DBG_DISALLOW_MAXFIFO        (1 << 1)
10135 #define  WM_DBG_DISALLOW_SPRITE         (1 << 2)
10136
10137 /* pipe CSC */
10138 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
10139 #define _PIPE_A_CSC_COEFF_BY    0x49014
10140 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
10141 #define _PIPE_A_CSC_COEFF_BU    0x4901c
10142 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
10143 #define _PIPE_A_CSC_COEFF_BV    0x49024
10144
10145 #define _PIPE_A_CSC_MODE        0x49028
10146 #define  ICL_CSC_ENABLE                 (1 << 31)
10147 #define  ICL_OUTPUT_CSC_ENABLE          (1 << 30)
10148 #define  CSC_BLACK_SCREEN_OFFSET        (1 << 2)
10149 #define  CSC_POSITION_BEFORE_GAMMA      (1 << 1)
10150 #define  CSC_MODE_YUV_TO_RGB            (1 << 0)
10151
10152 #define _PIPE_A_CSC_PREOFF_HI   0x49030
10153 #define _PIPE_A_CSC_PREOFF_ME   0x49034
10154 #define _PIPE_A_CSC_PREOFF_LO   0x49038
10155 #define _PIPE_A_CSC_POSTOFF_HI  0x49040
10156 #define _PIPE_A_CSC_POSTOFF_ME  0x49044
10157 #define _PIPE_A_CSC_POSTOFF_LO  0x49048
10158
10159 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
10160 #define _PIPE_B_CSC_COEFF_BY    0x49114
10161 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
10162 #define _PIPE_B_CSC_COEFF_BU    0x4911c
10163 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
10164 #define _PIPE_B_CSC_COEFF_BV    0x49124
10165 #define _PIPE_B_CSC_MODE        0x49128
10166 #define _PIPE_B_CSC_PREOFF_HI   0x49130
10167 #define _PIPE_B_CSC_PREOFF_ME   0x49134
10168 #define _PIPE_B_CSC_PREOFF_LO   0x49138
10169 #define _PIPE_B_CSC_POSTOFF_HI  0x49140
10170 #define _PIPE_B_CSC_POSTOFF_ME  0x49144
10171 #define _PIPE_B_CSC_POSTOFF_LO  0x49148
10172
10173 #define PIPE_CSC_COEFF_RY_GY(pipe)      _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
10174 #define PIPE_CSC_COEFF_BY(pipe)         _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
10175 #define PIPE_CSC_COEFF_RU_GU(pipe)      _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
10176 #define PIPE_CSC_COEFF_BU(pipe)         _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
10177 #define PIPE_CSC_COEFF_RV_GV(pipe)      _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
10178 #define PIPE_CSC_COEFF_BV(pipe)         _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
10179 #define PIPE_CSC_MODE(pipe)             _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
10180 #define PIPE_CSC_PREOFF_HI(pipe)        _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
10181 #define PIPE_CSC_PREOFF_ME(pipe)        _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
10182 #define PIPE_CSC_PREOFF_LO(pipe)        _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
10183 #define PIPE_CSC_POSTOFF_HI(pipe)       _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
10184 #define PIPE_CSC_POSTOFF_ME(pipe)       _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
10185 #define PIPE_CSC_POSTOFF_LO(pipe)       _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
10186
10187 /* Pipe Output CSC */
10188 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY  0x49050
10189 #define _PIPE_A_OUTPUT_CSC_COEFF_BY     0x49054
10190 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU  0x49058
10191 #define _PIPE_A_OUTPUT_CSC_COEFF_BU     0x4905c
10192 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV  0x49060
10193 #define _PIPE_A_OUTPUT_CSC_COEFF_BV     0x49064
10194 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI    0x49068
10195 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME    0x4906c
10196 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO    0x49070
10197 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI   0x49074
10198 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME   0x49078
10199 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO   0x4907c
10200
10201 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY  0x49150
10202 #define _PIPE_B_OUTPUT_CSC_COEFF_BY     0x49154
10203 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU  0x49158
10204 #define _PIPE_B_OUTPUT_CSC_COEFF_BU     0x4915c
10205 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV  0x49160
10206 #define _PIPE_B_OUTPUT_CSC_COEFF_BV     0x49164
10207 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI    0x49168
10208 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME    0x4916c
10209 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO    0x49170
10210 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI   0x49174
10211 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME   0x49178
10212 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO   0x4917c
10213
10214 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)       _MMIO_PIPE(pipe,\
10215                                                            _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
10216                                                            _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
10217 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe)          _MMIO_PIPE(pipe, \
10218                                                            _PIPE_A_OUTPUT_CSC_COEFF_BY, \
10219                                                            _PIPE_B_OUTPUT_CSC_COEFF_BY)
10220 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)       _MMIO_PIPE(pipe, \
10221                                                            _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
10222                                                            _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
10223 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe)          _MMIO_PIPE(pipe, \
10224                                                            _PIPE_A_OUTPUT_CSC_COEFF_BU, \
10225                                                            _PIPE_B_OUTPUT_CSC_COEFF_BU)
10226 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)       _MMIO_PIPE(pipe, \
10227                                                            _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
10228                                                            _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
10229 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe)          _MMIO_PIPE(pipe, \
10230                                                            _PIPE_A_OUTPUT_CSC_COEFF_BV, \
10231                                                            _PIPE_B_OUTPUT_CSC_COEFF_BV)
10232 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)         _MMIO_PIPE(pipe, \
10233                                                            _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
10234                                                            _PIPE_B_OUTPUT_CSC_PREOFF_HI)
10235 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)         _MMIO_PIPE(pipe, \
10236                                                            _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
10237                                                            _PIPE_B_OUTPUT_CSC_PREOFF_ME)
10238 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)         _MMIO_PIPE(pipe, \
10239                                                            _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
10240                                                            _PIPE_B_OUTPUT_CSC_PREOFF_LO)
10241 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)        _MMIO_PIPE(pipe, \
10242                                                            _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
10243                                                            _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
10244 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)        _MMIO_PIPE(pipe, \
10245                                                            _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
10246                                                            _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
10247 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)        _MMIO_PIPE(pipe, \
10248                                                            _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
10249                                                            _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
10250
10251 /* pipe degamma/gamma LUTs on IVB+ */
10252 #define _PAL_PREC_INDEX_A       0x4A400
10253 #define _PAL_PREC_INDEX_B       0x4AC00
10254 #define _PAL_PREC_INDEX_C       0x4B400
10255 #define   PAL_PREC_10_12_BIT            (0 << 31)
10256 #define   PAL_PREC_SPLIT_MODE           (1 << 31)
10257 #define   PAL_PREC_AUTO_INCREMENT       (1 << 15)
10258 #define   PAL_PREC_INDEX_VALUE_MASK     (0x3ff << 0)
10259 #define   PAL_PREC_INDEX_VALUE(x)       ((x) << 0)
10260 #define _PAL_PREC_DATA_A        0x4A404
10261 #define _PAL_PREC_DATA_B        0x4AC04
10262 #define _PAL_PREC_DATA_C        0x4B404
10263 #define _PAL_PREC_GC_MAX_A      0x4A410
10264 #define _PAL_PREC_GC_MAX_B      0x4AC10
10265 #define _PAL_PREC_GC_MAX_C      0x4B410
10266 #define _PAL_PREC_EXT_GC_MAX_A  0x4A420
10267 #define _PAL_PREC_EXT_GC_MAX_B  0x4AC20
10268 #define _PAL_PREC_EXT_GC_MAX_C  0x4B420
10269 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
10270 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
10271 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
10272
10273 #define PREC_PAL_INDEX(pipe)            _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
10274 #define PREC_PAL_DATA(pipe)             _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
10275 #define PREC_PAL_GC_MAX(pipe, i)        _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
10276 #define PREC_PAL_EXT_GC_MAX(pipe, i)    _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
10277 #define PREC_PAL_EXT2_GC_MAX(pipe, i)   _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
10278
10279 #define _PRE_CSC_GAMC_INDEX_A   0x4A484
10280 #define _PRE_CSC_GAMC_INDEX_B   0x4AC84
10281 #define _PRE_CSC_GAMC_INDEX_C   0x4B484
10282 #define   PRE_CSC_GAMC_AUTO_INCREMENT   (1 << 10)
10283 #define _PRE_CSC_GAMC_DATA_A    0x4A488
10284 #define _PRE_CSC_GAMC_DATA_B    0x4AC88
10285 #define _PRE_CSC_GAMC_DATA_C    0x4B488
10286
10287 #define PRE_CSC_GAMC_INDEX(pipe)        _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
10288 #define PRE_CSC_GAMC_DATA(pipe)         _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
10289
10290 /* ICL Multi segmented gamma */
10291 #define _PAL_PREC_MULTI_SEG_INDEX_A     0x4A408
10292 #define _PAL_PREC_MULTI_SEG_INDEX_B     0x4AC08
10293 #define  PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT          REG_BIT(15)
10294 #define  PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK        REG_GENMASK(4, 0)
10295
10296 #define _PAL_PREC_MULTI_SEG_DATA_A      0x4A40C
10297 #define _PAL_PREC_MULTI_SEG_DATA_B      0x4AC0C
10298
10299 #define PREC_PAL_MULTI_SEG_INDEX(pipe)  _MMIO_PIPE(pipe, \
10300                                         _PAL_PREC_MULTI_SEG_INDEX_A, \
10301                                         _PAL_PREC_MULTI_SEG_INDEX_B)
10302 #define PREC_PAL_MULTI_SEG_DATA(pipe)   _MMIO_PIPE(pipe, \
10303                                         _PAL_PREC_MULTI_SEG_DATA_A, \
10304                                         _PAL_PREC_MULTI_SEG_DATA_B)
10305
10306 /* pipe CSC & degamma/gamma LUTs on CHV */
10307 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
10308 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
10309 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
10310 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
10311 #define _CGM_PIPE_A_CSC_COEFF8  (VLV_DISPLAY_BASE + 0x67910)
10312 #define _CGM_PIPE_A_DEGAMMA     (VLV_DISPLAY_BASE + 0x66000)
10313 #define _CGM_PIPE_A_GAMMA       (VLV_DISPLAY_BASE + 0x67000)
10314 #define _CGM_PIPE_A_MODE        (VLV_DISPLAY_BASE + 0x67A00)
10315 #define   CGM_PIPE_MODE_GAMMA   (1 << 2)
10316 #define   CGM_PIPE_MODE_CSC     (1 << 1)
10317 #define   CGM_PIPE_MODE_DEGAMMA (1 << 0)
10318
10319 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
10320 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
10321 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
10322 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
10323 #define _CGM_PIPE_B_CSC_COEFF8  (VLV_DISPLAY_BASE + 0x69910)
10324 #define _CGM_PIPE_B_DEGAMMA     (VLV_DISPLAY_BASE + 0x68000)
10325 #define _CGM_PIPE_B_GAMMA       (VLV_DISPLAY_BASE + 0x69000)
10326 #define _CGM_PIPE_B_MODE        (VLV_DISPLAY_BASE + 0x69A00)
10327
10328 #define CGM_PIPE_CSC_COEFF01(pipe)      _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
10329 #define CGM_PIPE_CSC_COEFF23(pipe)      _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
10330 #define CGM_PIPE_CSC_COEFF45(pipe)      _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
10331 #define CGM_PIPE_CSC_COEFF67(pipe)      _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
10332 #define CGM_PIPE_CSC_COEFF8(pipe)       _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
10333 #define CGM_PIPE_DEGAMMA(pipe, i, w)    _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
10334 #define CGM_PIPE_GAMMA(pipe, i, w)      _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
10335 #define CGM_PIPE_MODE(pipe)             _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
10336
10337 /* MIPI DSI registers */
10338
10339 #define _MIPI_PORT(port, a, c)  (((port) == PORT_A) ? a : c)    /* ports A and C only */
10340 #define _MMIO_MIPI(port, a, c)  _MMIO(_MIPI_PORT(port, a, c))
10341
10342 /* Gen11 DSI */
10343 #define _MMIO_DSI(tc, dsi0, dsi1)       _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
10344                                                     dsi0, dsi1)
10345
10346 #define MIPIO_TXESC_CLK_DIV1                    _MMIO(0x160004)
10347 #define  GLK_TX_ESC_CLK_DIV1_MASK                       0x3FF
10348 #define MIPIO_TXESC_CLK_DIV2                    _MMIO(0x160008)
10349 #define  GLK_TX_ESC_CLK_DIV2_MASK                       0x3FF
10350
10351 #define _ICL_DSI_ESC_CLK_DIV0           0x6b090
10352 #define _ICL_DSI_ESC_CLK_DIV1           0x6b890
10353 #define ICL_DSI_ESC_CLK_DIV(port)       _MMIO_PORT((port),      \
10354                                                         _ICL_DSI_ESC_CLK_DIV0, \
10355                                                         _ICL_DSI_ESC_CLK_DIV1)
10356 #define _ICL_DPHY_ESC_CLK_DIV0          0x162190
10357 #define _ICL_DPHY_ESC_CLK_DIV1          0x6C190
10358 #define ICL_DPHY_ESC_CLK_DIV(port)      _MMIO_PORT((port),      \
10359                                                 _ICL_DPHY_ESC_CLK_DIV0, \
10360                                                 _ICL_DPHY_ESC_CLK_DIV1)
10361 #define  ICL_BYTE_CLK_PER_ESC_CLK_MASK          (0x1f << 16)
10362 #define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
10363 #define  ICL_ESC_CLK_DIV_MASK                   0x1ff
10364 #define  ICL_ESC_CLK_DIV_SHIFT                  0
10365 #define DSI_MAX_ESC_CLK                 20000           /* in KHz */
10366
10367 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
10368 #define GEN4_TIMESTAMP          _MMIO(0x2358)
10369 #define ILK_TIMESTAMP_HI        _MMIO(0x70070)
10370 #define IVB_TIMESTAMP_CTR       _MMIO(0x44070)
10371
10372 #define GEN9_TIMESTAMP_OVERRIDE                         _MMIO(0x44074)
10373 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT       0
10374 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK        0x3ff
10375 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT   12
10376 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK    (0xf << 12)
10377
10378 #define _PIPE_FRMTMSTMP_A               0x70048
10379 #define PIPE_FRMTMSTMP(pipe)            \
10380                         _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
10381
10382 /* BXT MIPI clock controls */
10383 #define BXT_MAX_VAR_OUTPUT_KHZ                  39500
10384
10385 #define BXT_MIPI_CLOCK_CTL                      _MMIO(0x46090)
10386 #define  BXT_MIPI1_DIV_SHIFT                    26
10387 #define  BXT_MIPI2_DIV_SHIFT                    10
10388 #define  BXT_MIPI_DIV_SHIFT(port)               \
10389                         _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
10390                                         BXT_MIPI2_DIV_SHIFT)
10391
10392 /* TX control divider to select actual TX clock output from (8x/var) */
10393 #define  BXT_MIPI1_TX_ESCLK_SHIFT               26
10394 #define  BXT_MIPI2_TX_ESCLK_SHIFT               10
10395 #define  BXT_MIPI_TX_ESCLK_SHIFT(port)          \
10396                         _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
10397                                         BXT_MIPI2_TX_ESCLK_SHIFT)
10398 #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK         (0x3F << 26)
10399 #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK         (0x3F << 10)
10400 #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)    \
10401                         _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
10402                                         BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
10403 #define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)   \
10404                 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
10405 /* RX upper control divider to select actual RX clock output from 8x */
10406 #define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT         21
10407 #define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT         5
10408 #define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)            \
10409                         _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
10410                                         BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
10411 #define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK           (3 << 21)
10412 #define  BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK           (3 << 5)
10413 #define  BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)      \
10414                         _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
10415                                         BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
10416 #define  BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val)     \
10417                 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
10418 /* 8/3X divider to select the actual 8/3X clock output from 8x */
10419 #define  BXT_MIPI1_8X_BY3_SHIFT                19
10420 #define  BXT_MIPI2_8X_BY3_SHIFT                3
10421 #define  BXT_MIPI_8X_BY3_SHIFT(port)          \
10422                         _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
10423                                         BXT_MIPI2_8X_BY3_SHIFT)
10424 #define  BXT_MIPI1_8X_BY3_DIVIDER_MASK         (3 << 19)
10425 #define  BXT_MIPI2_8X_BY3_DIVIDER_MASK         (3 << 3)
10426 #define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)    \
10427                         _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
10428                                                 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
10429 #define  BXT_MIPI_8X_BY3_DIVIDER(port, val)    \
10430                         (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
10431 /* RX lower control divider to select actual RX clock output from 8x */
10432 #define  BXT_MIPI1_RX_ESCLK_LOWER_SHIFT         16
10433 #define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT         0
10434 #define  BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)            \
10435                         _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
10436                                         BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
10437 #define  BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK           (3 << 16)
10438 #define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK           (3 << 0)
10439 #define  BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)      \
10440                         _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
10441                                         BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
10442 #define  BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val)     \
10443                 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
10444
10445 #define RX_DIVIDER_BIT_1_2                     0x3
10446 #define RX_DIVIDER_BIT_3_4                     0xC
10447
10448 /* BXT MIPI mode configure */
10449 #define  _BXT_MIPIA_TRANS_HACTIVE                       0x6B0F8
10450 #define  _BXT_MIPIC_TRANS_HACTIVE                       0x6B8F8
10451 #define  BXT_MIPI_TRANS_HACTIVE(tc)     _MMIO_MIPI(tc, \
10452                 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
10453
10454 #define  _BXT_MIPIA_TRANS_VACTIVE                       0x6B0FC
10455 #define  _BXT_MIPIC_TRANS_VACTIVE                       0x6B8FC
10456 #define  BXT_MIPI_TRANS_VACTIVE(tc)     _MMIO_MIPI(tc, \
10457                 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
10458
10459 #define  _BXT_MIPIA_TRANS_VTOTAL                        0x6B100
10460 #define  _BXT_MIPIC_TRANS_VTOTAL                        0x6B900
10461 #define  BXT_MIPI_TRANS_VTOTAL(tc)      _MMIO_MIPI(tc, \
10462                 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
10463
10464 #define BXT_DSI_PLL_CTL                 _MMIO(0x161000)
10465 #define  BXT_DSI_PLL_PVD_RATIO_SHIFT    16
10466 #define  BXT_DSI_PLL_PVD_RATIO_MASK     (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10467 #define  BXT_DSI_PLL_PVD_RATIO_1        (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10468 #define  BXT_DSIC_16X_BY1               (0 << 10)
10469 #define  BXT_DSIC_16X_BY2               (1 << 10)
10470 #define  BXT_DSIC_16X_BY3               (2 << 10)
10471 #define  BXT_DSIC_16X_BY4               (3 << 10)
10472 #define  BXT_DSIC_16X_MASK              (3 << 10)
10473 #define  BXT_DSIA_16X_BY1               (0 << 8)
10474 #define  BXT_DSIA_16X_BY2               (1 << 8)
10475 #define  BXT_DSIA_16X_BY3               (2 << 8)
10476 #define  BXT_DSIA_16X_BY4               (3 << 8)
10477 #define  BXT_DSIA_16X_MASK              (3 << 8)
10478 #define  BXT_DSI_FREQ_SEL_SHIFT         8
10479 #define  BXT_DSI_FREQ_SEL_MASK          (0xF << BXT_DSI_FREQ_SEL_SHIFT)
10480
10481 #define BXT_DSI_PLL_RATIO_MAX           0x7D
10482 #define BXT_DSI_PLL_RATIO_MIN           0x22
10483 #define GLK_DSI_PLL_RATIO_MAX           0x6F
10484 #define GLK_DSI_PLL_RATIO_MIN           0x22
10485 #define BXT_DSI_PLL_RATIO_MASK          0xFF
10486 #define BXT_REF_CLOCK_KHZ               19200
10487
10488 #define BXT_DSI_PLL_ENABLE              _MMIO(0x46080)
10489 #define  BXT_DSI_PLL_DO_ENABLE          (1 << 31)
10490 #define  BXT_DSI_PLL_LOCKED             (1 << 30)
10491
10492 #define _MIPIA_PORT_CTRL                        (VLV_DISPLAY_BASE + 0x61190)
10493 #define _MIPIC_PORT_CTRL                        (VLV_DISPLAY_BASE + 0x61700)
10494 #define MIPI_PORT_CTRL(port)    _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
10495
10496  /* BXT port control */
10497 #define _BXT_MIPIA_PORT_CTRL                            0x6B0C0
10498 #define _BXT_MIPIC_PORT_CTRL                            0x6B8C0
10499 #define BXT_MIPI_PORT_CTRL(tc)  _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
10500
10501 /* ICL DSI MODE control */
10502 #define _ICL_DSI_IO_MODECTL_0                           0x6B094
10503 #define _ICL_DSI_IO_MODECTL_1                           0x6B894
10504 #define ICL_DSI_IO_MODECTL(port)        _MMIO_PORT(port,        \
10505                                                     _ICL_DSI_IO_MODECTL_0, \
10506                                                     _ICL_DSI_IO_MODECTL_1)
10507 #define  COMBO_PHY_MODE_DSI                             (1 << 0)
10508
10509 /* Display Stream Splitter Control */
10510 #define DSS_CTL1                                _MMIO(0x67400)
10511 #define  SPLITTER_ENABLE                        (1 << 31)
10512 #define  JOINER_ENABLE                          (1 << 30)
10513 #define  DUAL_LINK_MODE_INTERLEAVE              (1 << 24)
10514 #define  DUAL_LINK_MODE_FRONTBACK               (0 << 24)
10515 #define  OVERLAP_PIXELS_MASK                    (0xf << 16)
10516 #define  OVERLAP_PIXELS(pixels)                 ((pixels) << 16)
10517 #define  LEFT_DL_BUF_TARGET_DEPTH_MASK          (0xfff << 0)
10518 #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)       ((pixels) << 0)
10519 #define  MAX_DL_BUFFER_TARGET_DEPTH             0x5a0
10520
10521 #define DSS_CTL2                                _MMIO(0x67404)
10522 #define  LEFT_BRANCH_VDSC_ENABLE                (1 << 31)
10523 #define  RIGHT_BRANCH_VDSC_ENABLE               (1 << 15)
10524 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK         (0xfff << 0)
10525 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)      ((pixels) << 0)
10526
10527 #define _ICL_PIPE_DSS_CTL1_PB                   0x78200
10528 #define _ICL_PIPE_DSS_CTL1_PC                   0x78400
10529 #define ICL_PIPE_DSS_CTL1(pipe)                 _MMIO_PIPE((pipe) - PIPE_B, \
10530                                                            _ICL_PIPE_DSS_CTL1_PB, \
10531                                                            _ICL_PIPE_DSS_CTL1_PC)
10532 #define  BIG_JOINER_ENABLE                      (1 << 29)
10533 #define  MASTER_BIG_JOINER_ENABLE               (1 << 28)
10534 #define  VGA_CENTERING_ENABLE                   (1 << 27)
10535
10536 #define _ICL_PIPE_DSS_CTL2_PB                   0x78204
10537 #define _ICL_PIPE_DSS_CTL2_PC                   0x78404
10538 #define ICL_PIPE_DSS_CTL2(pipe)                 _MMIO_PIPE((pipe) - PIPE_B, \
10539                                                            _ICL_PIPE_DSS_CTL2_PB, \
10540                                                            _ICL_PIPE_DSS_CTL2_PC)
10541
10542 #define BXT_P_DSI_REGULATOR_CFG                 _MMIO(0x160020)
10543 #define  STAP_SELECT                                    (1 << 0)
10544
10545 #define BXT_P_DSI_REGULATOR_TX_CTRL             _MMIO(0x160054)
10546 #define  HS_IO_CTRL_SELECT                              (1 << 0)
10547
10548 #define  DPI_ENABLE                                     (1 << 31) /* A + C */
10549 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT              27
10550 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK               (0xf << 27)
10551 #define  DUAL_LINK_MODE_SHIFT                           26
10552 #define  DUAL_LINK_MODE_MASK                            (1 << 26)
10553 #define  DUAL_LINK_MODE_FRONT_BACK                      (0 << 26)
10554 #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE               (1 << 26)
10555 #define  DITHERING_ENABLE                               (1 << 25) /* A + C */
10556 #define  FLOPPED_HSTX                                   (1 << 23)
10557 #define  DE_INVERT                                      (1 << 19) /* XXX */
10558 #define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT                18
10559 #define  MIPIA_FLISDSI_DELAY_COUNT_MASK                 (0xf << 18)
10560 #define  AFE_LATCHOUT                                   (1 << 17)
10561 #define  LP_OUTPUT_HOLD                                 (1 << 16)
10562 #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT           15
10563 #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK            (1 << 15)
10564 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT              11
10565 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK               (0xf << 11)
10566 #define  CSB_SHIFT                                      9
10567 #define  CSB_MASK                                       (3 << 9)
10568 #define  CSB_20MHZ                                      (0 << 9)
10569 #define  CSB_10MHZ                                      (1 << 9)
10570 #define  CSB_40MHZ                                      (2 << 9)
10571 #define  BANDGAP_MASK                                   (1 << 8)
10572 #define  BANDGAP_PNW_CIRCUIT                            (0 << 8)
10573 #define  BANDGAP_LNC_CIRCUIT                            (1 << 8)
10574 #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT            5
10575 #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK             (7 << 5)
10576 #define  TEARING_EFFECT_DELAY                           (1 << 4) /* A + C */
10577 #define  TEARING_EFFECT_SHIFT                           2 /* A + C */
10578 #define  TEARING_EFFECT_MASK                            (3 << 2)
10579 #define  TEARING_EFFECT_OFF                             (0 << 2)
10580 #define  TEARING_EFFECT_DSI                             (1 << 2)
10581 #define  TEARING_EFFECT_GPIO                            (2 << 2)
10582 #define  LANE_CONFIGURATION_SHIFT                       0
10583 #define  LANE_CONFIGURATION_MASK                        (3 << 0)
10584 #define  LANE_CONFIGURATION_4LANE                       (0 << 0)
10585 #define  LANE_CONFIGURATION_DUAL_LINK_A                 (1 << 0)
10586 #define  LANE_CONFIGURATION_DUAL_LINK_B                 (2 << 0)
10587
10588 #define _MIPIA_TEARING_CTRL                     (VLV_DISPLAY_BASE + 0x61194)
10589 #define _MIPIC_TEARING_CTRL                     (VLV_DISPLAY_BASE + 0x61704)
10590 #define MIPI_TEARING_CTRL(port)                 _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
10591 #define  TEARING_EFFECT_DELAY_SHIFT                     0
10592 #define  TEARING_EFFECT_DELAY_MASK                      (0xffff << 0)
10593
10594 /* XXX: all bits reserved */
10595 #define _MIPIA_AUTOPWG                  (VLV_DISPLAY_BASE + 0x611a0)
10596
10597 /* MIPI DSI Controller and D-PHY registers */
10598
10599 #define _MIPIA_DEVICE_READY             (dev_priv->mipi_mmio_base + 0xb000)
10600 #define _MIPIC_DEVICE_READY             (dev_priv->mipi_mmio_base + 0xb800)
10601 #define MIPI_DEVICE_READY(port)         _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
10602 #define  BUS_POSSESSION                                 (1 << 3) /* set to give bus to receiver */
10603 #define  ULPS_STATE_MASK                                (3 << 1)
10604 #define  ULPS_STATE_ENTER                               (2 << 1)
10605 #define  ULPS_STATE_EXIT                                (1 << 1)
10606 #define  ULPS_STATE_NORMAL_OPERATION                    (0 << 1)
10607 #define  DEVICE_READY                                   (1 << 0)
10608
10609 #define _MIPIA_INTR_STAT                (dev_priv->mipi_mmio_base + 0xb004)
10610 #define _MIPIC_INTR_STAT                (dev_priv->mipi_mmio_base + 0xb804)
10611 #define MIPI_INTR_STAT(port)            _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
10612 #define _MIPIA_INTR_EN                  (dev_priv->mipi_mmio_base + 0xb008)
10613 #define _MIPIC_INTR_EN                  (dev_priv->mipi_mmio_base + 0xb808)
10614 #define MIPI_INTR_EN(port)              _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
10615 #define  TEARING_EFFECT                                 (1 << 31)
10616 #define  SPL_PKT_SENT_INTERRUPT                         (1 << 30)
10617 #define  GEN_READ_DATA_AVAIL                            (1 << 29)
10618 #define  LP_GENERIC_WR_FIFO_FULL                        (1 << 28)
10619 #define  HS_GENERIC_WR_FIFO_FULL                        (1 << 27)
10620 #define  RX_PROT_VIOLATION                              (1 << 26)
10621 #define  RX_INVALID_TX_LENGTH                           (1 << 25)
10622 #define  ACK_WITH_NO_ERROR                              (1 << 24)
10623 #define  TURN_AROUND_ACK_TIMEOUT                        (1 << 23)
10624 #define  LP_RX_TIMEOUT                                  (1 << 22)
10625 #define  HS_TX_TIMEOUT                                  (1 << 21)
10626 #define  DPI_FIFO_UNDERRUN                              (1 << 20)
10627 #define  LOW_CONTENTION                                 (1 << 19)
10628 #define  HIGH_CONTENTION                                (1 << 18)
10629 #define  TXDSI_VC_ID_INVALID                            (1 << 17)
10630 #define  TXDSI_DATA_TYPE_NOT_RECOGNISED                 (1 << 16)
10631 #define  TXCHECKSUM_ERROR                               (1 << 15)
10632 #define  TXECC_MULTIBIT_ERROR                           (1 << 14)
10633 #define  TXECC_SINGLE_BIT_ERROR                         (1 << 13)
10634 #define  TXFALSE_CONTROL_ERROR                          (1 << 12)
10635 #define  RXDSI_VC_ID_INVALID                            (1 << 11)
10636 #define  RXDSI_DATA_TYPE_NOT_REGOGNISED                 (1 << 10)
10637 #define  RXCHECKSUM_ERROR                               (1 << 9)
10638 #define  RXECC_MULTIBIT_ERROR                           (1 << 8)
10639 #define  RXECC_SINGLE_BIT_ERROR                         (1 << 7)
10640 #define  RXFALSE_CONTROL_ERROR                          (1 << 6)
10641 #define  RXHS_RECEIVE_TIMEOUT_ERROR                     (1 << 5)
10642 #define  RX_LP_TX_SYNC_ERROR                            (1 << 4)
10643 #define  RXEXCAPE_MODE_ENTRY_ERROR                      (1 << 3)
10644 #define  RXEOT_SYNC_ERROR                               (1 << 2)
10645 #define  RXSOT_SYNC_ERROR                               (1 << 1)
10646 #define  RXSOT_ERROR                                    (1 << 0)
10647
10648 #define _MIPIA_DSI_FUNC_PRG             (dev_priv->mipi_mmio_base + 0xb00c)
10649 #define _MIPIC_DSI_FUNC_PRG             (dev_priv->mipi_mmio_base + 0xb80c)
10650 #define MIPI_DSI_FUNC_PRG(port)         _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
10651 #define  CMD_MODE_DATA_WIDTH_MASK                       (7 << 13)
10652 #define  CMD_MODE_NOT_SUPPORTED                         (0 << 13)
10653 #define  CMD_MODE_DATA_WIDTH_16_BIT                     (1 << 13)
10654 #define  CMD_MODE_DATA_WIDTH_9_BIT                      (2 << 13)
10655 #define  CMD_MODE_DATA_WIDTH_8_BIT                      (3 << 13)
10656 #define  CMD_MODE_DATA_WIDTH_OPTION1                    (4 << 13)
10657 #define  CMD_MODE_DATA_WIDTH_OPTION2                    (5 << 13)
10658 #define  VID_MODE_FORMAT_MASK                           (0xf << 7)
10659 #define  VID_MODE_NOT_SUPPORTED                         (0 << 7)
10660 #define  VID_MODE_FORMAT_RGB565                         (1 << 7)
10661 #define  VID_MODE_FORMAT_RGB666_PACKED                  (2 << 7)
10662 #define  VID_MODE_FORMAT_RGB666                         (3 << 7)
10663 #define  VID_MODE_FORMAT_RGB888                         (4 << 7)
10664 #define  CMD_MODE_CHANNEL_NUMBER_SHIFT                  5
10665 #define  CMD_MODE_CHANNEL_NUMBER_MASK                   (3 << 5)
10666 #define  VID_MODE_CHANNEL_NUMBER_SHIFT                  3
10667 #define  VID_MODE_CHANNEL_NUMBER_MASK                   (3 << 3)
10668 #define  DATA_LANES_PRG_REG_SHIFT                       0
10669 #define  DATA_LANES_PRG_REG_MASK                        (7 << 0)
10670
10671 #define _MIPIA_HS_TX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb010)
10672 #define _MIPIC_HS_TX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb810)
10673 #define MIPI_HS_TX_TIMEOUT(port)        _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
10674 #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK             0xffffff
10675
10676 #define _MIPIA_LP_RX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb014)
10677 #define _MIPIC_LP_RX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb814)
10678 #define MIPI_LP_RX_TIMEOUT(port)        _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
10679 #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK              0xffffff
10680
10681 #define _MIPIA_TURN_AROUND_TIMEOUT      (dev_priv->mipi_mmio_base + 0xb018)
10682 #define _MIPIC_TURN_AROUND_TIMEOUT      (dev_priv->mipi_mmio_base + 0xb818)
10683 #define MIPI_TURN_AROUND_TIMEOUT(port)  _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
10684 #define  TURN_AROUND_TIMEOUT_MASK                       0x3f
10685
10686 #define _MIPIA_DEVICE_RESET_TIMER       (dev_priv->mipi_mmio_base + 0xb01c)
10687 #define _MIPIC_DEVICE_RESET_TIMER       (dev_priv->mipi_mmio_base + 0xb81c)
10688 #define MIPI_DEVICE_RESET_TIMER(port)   _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
10689 #define  DEVICE_RESET_TIMER_MASK                        0xffff
10690
10691 #define _MIPIA_DPI_RESOLUTION           (dev_priv->mipi_mmio_base + 0xb020)
10692 #define _MIPIC_DPI_RESOLUTION           (dev_priv->mipi_mmio_base + 0xb820)
10693 #define MIPI_DPI_RESOLUTION(port)       _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
10694 #define  VERTICAL_ADDRESS_SHIFT                         16
10695 #define  VERTICAL_ADDRESS_MASK                          (0xffff << 16)
10696 #define  HORIZONTAL_ADDRESS_SHIFT                       0
10697 #define  HORIZONTAL_ADDRESS_MASK                        0xffff
10698
10699 #define _MIPIA_DBI_FIFO_THROTTLE        (dev_priv->mipi_mmio_base + 0xb024)
10700 #define _MIPIC_DBI_FIFO_THROTTLE        (dev_priv->mipi_mmio_base + 0xb824)
10701 #define MIPI_DBI_FIFO_THROTTLE(port)    _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
10702 #define  DBI_FIFO_EMPTY_HALF                            (0 << 0)
10703 #define  DBI_FIFO_EMPTY_QUARTER                         (1 << 0)
10704 #define  DBI_FIFO_EMPTY_7_LOCATIONS                     (2 << 0)
10705
10706 /* regs below are bits 15:0 */
10707 #define _MIPIA_HSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb028)
10708 #define _MIPIC_HSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb828)
10709 #define MIPI_HSYNC_PADDING_COUNT(port)  _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
10710
10711 #define _MIPIA_HBP_COUNT                (dev_priv->mipi_mmio_base + 0xb02c)
10712 #define _MIPIC_HBP_COUNT                (dev_priv->mipi_mmio_base + 0xb82c)
10713 #define MIPI_HBP_COUNT(port)            _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
10714
10715 #define _MIPIA_HFP_COUNT                (dev_priv->mipi_mmio_base + 0xb030)
10716 #define _MIPIC_HFP_COUNT                (dev_priv->mipi_mmio_base + 0xb830)
10717 #define MIPI_HFP_COUNT(port)            _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
10718
10719 #define _MIPIA_HACTIVE_AREA_COUNT       (dev_priv->mipi_mmio_base + 0xb034)
10720 #define _MIPIC_HACTIVE_AREA_COUNT       (dev_priv->mipi_mmio_base + 0xb834)
10721 #define MIPI_HACTIVE_AREA_COUNT(port)   _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
10722
10723 #define _MIPIA_VSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb038)
10724 #define _MIPIC_VSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb838)
10725 #define MIPI_VSYNC_PADDING_COUNT(port)  _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
10726
10727 #define _MIPIA_VBP_COUNT                (dev_priv->mipi_mmio_base + 0xb03c)
10728 #define _MIPIC_VBP_COUNT                (dev_priv->mipi_mmio_base + 0xb83c)
10729 #define MIPI_VBP_COUNT(port)            _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
10730
10731 #define _MIPIA_VFP_COUNT                (dev_priv->mipi_mmio_base + 0xb040)
10732 #define _MIPIC_VFP_COUNT                (dev_priv->mipi_mmio_base + 0xb840)
10733 #define MIPI_VFP_COUNT(port)            _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
10734
10735 #define _MIPIA_HIGH_LOW_SWITCH_COUNT    (dev_priv->mipi_mmio_base + 0xb044)
10736 #define _MIPIC_HIGH_LOW_SWITCH_COUNT    (dev_priv->mipi_mmio_base + 0xb844)
10737 #define MIPI_HIGH_LOW_SWITCH_COUNT(port)        _MMIO_MIPI(port,        _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
10738
10739 /* regs above are bits 15:0 */
10740
10741 #define _MIPIA_DPI_CONTROL              (dev_priv->mipi_mmio_base + 0xb048)
10742 #define _MIPIC_DPI_CONTROL              (dev_priv->mipi_mmio_base + 0xb848)
10743 #define MIPI_DPI_CONTROL(port)          _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
10744 #define  DPI_LP_MODE                                    (1 << 6)
10745 #define  BACKLIGHT_OFF                                  (1 << 5)
10746 #define  BACKLIGHT_ON                                   (1 << 4)
10747 #define  COLOR_MODE_OFF                                 (1 << 3)
10748 #define  COLOR_MODE_ON                                  (1 << 2)
10749 #define  TURN_ON                                        (1 << 1)
10750 #define  SHUTDOWN                                       (1 << 0)
10751
10752 #define _MIPIA_DPI_DATA                 (dev_priv->mipi_mmio_base + 0xb04c)
10753 #define _MIPIC_DPI_DATA                 (dev_priv->mipi_mmio_base + 0xb84c)
10754 #define MIPI_DPI_DATA(port)             _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
10755 #define  COMMAND_BYTE_SHIFT                             0
10756 #define  COMMAND_BYTE_MASK                              (0x3f << 0)
10757
10758 #define _MIPIA_INIT_COUNT               (dev_priv->mipi_mmio_base + 0xb050)
10759 #define _MIPIC_INIT_COUNT               (dev_priv->mipi_mmio_base + 0xb850)
10760 #define MIPI_INIT_COUNT(port)           _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
10761 #define  MASTER_INIT_TIMER_SHIFT                        0
10762 #define  MASTER_INIT_TIMER_MASK                         (0xffff << 0)
10763
10764 #define _MIPIA_MAX_RETURN_PKT_SIZE      (dev_priv->mipi_mmio_base + 0xb054)
10765 #define _MIPIC_MAX_RETURN_PKT_SIZE      (dev_priv->mipi_mmio_base + 0xb854)
10766 #define MIPI_MAX_RETURN_PKT_SIZE(port)  _MMIO_MIPI(port, \
10767                         _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
10768 #define  MAX_RETURN_PKT_SIZE_SHIFT                      0
10769 #define  MAX_RETURN_PKT_SIZE_MASK                       (0x3ff << 0)
10770
10771 #define _MIPIA_VIDEO_MODE_FORMAT        (dev_priv->mipi_mmio_base + 0xb058)
10772 #define _MIPIC_VIDEO_MODE_FORMAT        (dev_priv->mipi_mmio_base + 0xb858)
10773 #define MIPI_VIDEO_MODE_FORMAT(port)    _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
10774 #define  RANDOM_DPI_DISPLAY_RESOLUTION                  (1 << 4)
10775 #define  DISABLE_VIDEO_BTA                              (1 << 3)
10776 #define  IP_TG_CONFIG                                   (1 << 2)
10777 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE           (1 << 0)
10778 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS          (2 << 0)
10779 #define  VIDEO_MODE_BURST                               (3 << 0)
10780
10781 #define _MIPIA_EOT_DISABLE              (dev_priv->mipi_mmio_base + 0xb05c)
10782 #define _MIPIC_EOT_DISABLE              (dev_priv->mipi_mmio_base + 0xb85c)
10783 #define MIPI_EOT_DISABLE(port)          _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
10784 #define  BXT_DEFEATURE_DPI_FIFO_CTR                     (1 << 9)
10785 #define  BXT_DPHY_DEFEATURE_EN                          (1 << 8)
10786 #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE           (1 << 7)
10787 #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE           (1 << 6)
10788 #define  LOW_CONTENTION_RECOVERY_DISABLE                (1 << 5)
10789 #define  HIGH_CONTENTION_RECOVERY_DISABLE               (1 << 4)
10790 #define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
10791 #define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE          (1 << 2)
10792 #define  CLOCKSTOP                                      (1 << 1)
10793 #define  EOT_DISABLE                                    (1 << 0)
10794
10795 #define _MIPIA_LP_BYTECLK               (dev_priv->mipi_mmio_base + 0xb060)
10796 #define _MIPIC_LP_BYTECLK               (dev_priv->mipi_mmio_base + 0xb860)
10797 #define MIPI_LP_BYTECLK(port)           _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
10798 #define  LP_BYTECLK_SHIFT                               0
10799 #define  LP_BYTECLK_MASK                                (0xffff << 0)
10800
10801 #define _MIPIA_TLPX_TIME_COUNT          (dev_priv->mipi_mmio_base + 0xb0a4)
10802 #define _MIPIC_TLPX_TIME_COUNT          (dev_priv->mipi_mmio_base + 0xb8a4)
10803 #define MIPI_TLPX_TIME_COUNT(port)       _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
10804
10805 #define _MIPIA_CLK_LANE_TIMING          (dev_priv->mipi_mmio_base + 0xb098)
10806 #define _MIPIC_CLK_LANE_TIMING          (dev_priv->mipi_mmio_base + 0xb898)
10807 #define MIPI_CLK_LANE_TIMING(port)       _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
10808
10809 /* bits 31:0 */
10810 #define _MIPIA_LP_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb064)
10811 #define _MIPIC_LP_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb864)
10812 #define MIPI_LP_GEN_DATA(port)          _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
10813
10814 /* bits 31:0 */
10815 #define _MIPIA_HS_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb068)
10816 #define _MIPIC_HS_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb868)
10817 #define MIPI_HS_GEN_DATA(port)          _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
10818
10819 #define _MIPIA_LP_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb06c)
10820 #define _MIPIC_LP_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb86c)
10821 #define MIPI_LP_GEN_CTRL(port)          _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
10822 #define _MIPIA_HS_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb070)
10823 #define _MIPIC_HS_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb870)
10824 #define MIPI_HS_GEN_CTRL(port)          _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
10825 #define  LONG_PACKET_WORD_COUNT_SHIFT                   8
10826 #define  LONG_PACKET_WORD_COUNT_MASK                    (0xffff << 8)
10827 #define  SHORT_PACKET_PARAM_SHIFT                       8
10828 #define  SHORT_PACKET_PARAM_MASK                        (0xffff << 8)
10829 #define  VIRTUAL_CHANNEL_SHIFT                          6
10830 #define  VIRTUAL_CHANNEL_MASK                           (3 << 6)
10831 #define  DATA_TYPE_SHIFT                                0
10832 #define  DATA_TYPE_MASK                                 (0x3f << 0)
10833 /* data type values, see include/video/mipi_display.h */
10834
10835 #define _MIPIA_GEN_FIFO_STAT            (dev_priv->mipi_mmio_base + 0xb074)
10836 #define _MIPIC_GEN_FIFO_STAT            (dev_priv->mipi_mmio_base + 0xb874)
10837 #define MIPI_GEN_FIFO_STAT(port)        _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
10838 #define  DPI_FIFO_EMPTY                                 (1 << 28)
10839 #define  DBI_FIFO_EMPTY                                 (1 << 27)
10840 #define  LP_CTRL_FIFO_EMPTY                             (1 << 26)
10841 #define  LP_CTRL_FIFO_HALF_EMPTY                        (1 << 25)
10842 #define  LP_CTRL_FIFO_FULL                              (1 << 24)
10843 #define  HS_CTRL_FIFO_EMPTY                             (1 << 18)
10844 #define  HS_CTRL_FIFO_HALF_EMPTY                        (1 << 17)
10845 #define  HS_CTRL_FIFO_FULL                              (1 << 16)
10846 #define  LP_DATA_FIFO_EMPTY                             (1 << 10)
10847 #define  LP_DATA_FIFO_HALF_EMPTY                        (1 << 9)
10848 #define  LP_DATA_FIFO_FULL                              (1 << 8)
10849 #define  HS_DATA_FIFO_EMPTY                             (1 << 2)
10850 #define  HS_DATA_FIFO_HALF_EMPTY                        (1 << 1)
10851 #define  HS_DATA_FIFO_FULL                              (1 << 0)
10852
10853 #define _MIPIA_HS_LS_DBI_ENABLE         (dev_priv->mipi_mmio_base + 0xb078)
10854 #define _MIPIC_HS_LS_DBI_ENABLE         (dev_priv->mipi_mmio_base + 0xb878)
10855 #define MIPI_HS_LP_DBI_ENABLE(port)     _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
10856 #define  DBI_HS_LP_MODE_MASK                            (1 << 0)
10857 #define  DBI_LP_MODE                                    (1 << 0)
10858 #define  DBI_HS_MODE                                    (0 << 0)
10859
10860 #define _MIPIA_DPHY_PARAM               (dev_priv->mipi_mmio_base + 0xb080)
10861 #define _MIPIC_DPHY_PARAM               (dev_priv->mipi_mmio_base + 0xb880)
10862 #define MIPI_DPHY_PARAM(port)           _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
10863 #define  EXIT_ZERO_COUNT_SHIFT                          24
10864 #define  EXIT_ZERO_COUNT_MASK                           (0x3f << 24)
10865 #define  TRAIL_COUNT_SHIFT                              16
10866 #define  TRAIL_COUNT_MASK                               (0x1f << 16)
10867 #define  CLK_ZERO_COUNT_SHIFT                           8
10868 #define  CLK_ZERO_COUNT_MASK                            (0xff << 8)
10869 #define  PREPARE_COUNT_SHIFT                            0
10870 #define  PREPARE_COUNT_MASK                             (0x3f << 0)
10871
10872 #define _ICL_DSI_T_INIT_MASTER_0        0x6b088
10873 #define _ICL_DSI_T_INIT_MASTER_1        0x6b888
10874 #define ICL_DSI_T_INIT_MASTER(port)     _MMIO_PORT(port,        \
10875                                                    _ICL_DSI_T_INIT_MASTER_0,\
10876                                                    _ICL_DSI_T_INIT_MASTER_1)
10877
10878 #define _DPHY_CLK_TIMING_PARAM_0        0x162180
10879 #define _DPHY_CLK_TIMING_PARAM_1        0x6c180
10880 #define DPHY_CLK_TIMING_PARAM(port)     _MMIO_PORT(port,        \
10881                                                    _DPHY_CLK_TIMING_PARAM_0,\
10882                                                    _DPHY_CLK_TIMING_PARAM_1)
10883 #define _DSI_CLK_TIMING_PARAM_0         0x6b080
10884 #define _DSI_CLK_TIMING_PARAM_1         0x6b880
10885 #define DSI_CLK_TIMING_PARAM(port)      _MMIO_PORT(port,        \
10886                                                    _DSI_CLK_TIMING_PARAM_0,\
10887                                                    _DSI_CLK_TIMING_PARAM_1)
10888 #define  CLK_PREPARE_OVERRIDE           (1 << 31)
10889 #define  CLK_PREPARE(x)         ((x) << 28)
10890 #define  CLK_PREPARE_MASK               (0x7 << 28)
10891 #define  CLK_PREPARE_SHIFT              28
10892 #define  CLK_ZERO_OVERRIDE              (1 << 27)
10893 #define  CLK_ZERO(x)                    ((x) << 20)
10894 #define  CLK_ZERO_MASK                  (0xf << 20)
10895 #define  CLK_ZERO_SHIFT         20
10896 #define  CLK_PRE_OVERRIDE               (1 << 19)
10897 #define  CLK_PRE(x)                     ((x) << 16)
10898 #define  CLK_PRE_MASK                   (0x3 << 16)
10899 #define  CLK_PRE_SHIFT                  16
10900 #define  CLK_POST_OVERRIDE              (1 << 15)
10901 #define  CLK_POST(x)                    ((x) << 8)
10902 #define  CLK_POST_MASK                  (0x7 << 8)
10903 #define  CLK_POST_SHIFT         8
10904 #define  CLK_TRAIL_OVERRIDE             (1 << 7)
10905 #define  CLK_TRAIL(x)                   ((x) << 0)
10906 #define  CLK_TRAIL_MASK         (0xf << 0)
10907 #define  CLK_TRAIL_SHIFT                0
10908
10909 #define _DPHY_DATA_TIMING_PARAM_0       0x162184
10910 #define _DPHY_DATA_TIMING_PARAM_1       0x6c184
10911 #define DPHY_DATA_TIMING_PARAM(port)    _MMIO_PORT(port,        \
10912                                                    _DPHY_DATA_TIMING_PARAM_0,\
10913                                                    _DPHY_DATA_TIMING_PARAM_1)
10914 #define _DSI_DATA_TIMING_PARAM_0        0x6B084
10915 #define _DSI_DATA_TIMING_PARAM_1        0x6B884
10916 #define DSI_DATA_TIMING_PARAM(port)     _MMIO_PORT(port,        \
10917                                                    _DSI_DATA_TIMING_PARAM_0,\
10918                                                    _DSI_DATA_TIMING_PARAM_1)
10919 #define  HS_PREPARE_OVERRIDE            (1 << 31)
10920 #define  HS_PREPARE(x)                  ((x) << 24)
10921 #define  HS_PREPARE_MASK                (0x7 << 24)
10922 #define  HS_PREPARE_SHIFT               24
10923 #define  HS_ZERO_OVERRIDE               (1 << 23)
10924 #define  HS_ZERO(x)                     ((x) << 16)
10925 #define  HS_ZERO_MASK                   (0xf << 16)
10926 #define  HS_ZERO_SHIFT                  16
10927 #define  HS_TRAIL_OVERRIDE              (1 << 15)
10928 #define  HS_TRAIL(x)                    ((x) << 8)
10929 #define  HS_TRAIL_MASK                  (0x7 << 8)
10930 #define  HS_TRAIL_SHIFT         8
10931 #define  HS_EXIT_OVERRIDE               (1 << 7)
10932 #define  HS_EXIT(x)                     ((x) << 0)
10933 #define  HS_EXIT_MASK                   (0x7 << 0)
10934 #define  HS_EXIT_SHIFT                  0
10935
10936 #define _DPHY_TA_TIMING_PARAM_0         0x162188
10937 #define _DPHY_TA_TIMING_PARAM_1         0x6c188
10938 #define DPHY_TA_TIMING_PARAM(port)      _MMIO_PORT(port,        \
10939                                                    _DPHY_TA_TIMING_PARAM_0,\
10940                                                    _DPHY_TA_TIMING_PARAM_1)
10941 #define _DSI_TA_TIMING_PARAM_0          0x6b098
10942 #define _DSI_TA_TIMING_PARAM_1          0x6b898
10943 #define DSI_TA_TIMING_PARAM(port)       _MMIO_PORT(port,        \
10944                                                    _DSI_TA_TIMING_PARAM_0,\
10945                                                    _DSI_TA_TIMING_PARAM_1)
10946 #define  TA_SURE_OVERRIDE               (1 << 31)
10947 #define  TA_SURE(x)                     ((x) << 16)
10948 #define  TA_SURE_MASK                   (0x1f << 16)
10949 #define  TA_SURE_SHIFT                  16
10950 #define  TA_GO_OVERRIDE         (1 << 15)
10951 #define  TA_GO(x)                       ((x) << 8)
10952 #define  TA_GO_MASK                     (0xf << 8)
10953 #define  TA_GO_SHIFT                    8
10954 #define  TA_GET_OVERRIDE                (1 << 7)
10955 #define  TA_GET(x)                      ((x) << 0)
10956 #define  TA_GET_MASK                    (0xf << 0)
10957 #define  TA_GET_SHIFT                   0
10958
10959 /* DSI transcoder configuration */
10960 #define _DSI_TRANS_FUNC_CONF_0          0x6b030
10961 #define _DSI_TRANS_FUNC_CONF_1          0x6b830
10962 #define DSI_TRANS_FUNC_CONF(tc)         _MMIO_DSI(tc,   \
10963                                                   _DSI_TRANS_FUNC_CONF_0,\
10964                                                   _DSI_TRANS_FUNC_CONF_1)
10965 #define  OP_MODE_MASK                   (0x3 << 28)
10966 #define  OP_MODE_SHIFT                  28
10967 #define  CMD_MODE_NO_GATE               (0x0 << 28)
10968 #define  CMD_MODE_TE_GATE               (0x1 << 28)
10969 #define  VIDEO_MODE_SYNC_EVENT          (0x2 << 28)
10970 #define  VIDEO_MODE_SYNC_PULSE          (0x3 << 28)
10971 #define  LINK_READY                     (1 << 20)
10972 #define  PIX_FMT_MASK                   (0x3 << 16)
10973 #define  PIX_FMT_SHIFT                  16
10974 #define  PIX_FMT_RGB565                 (0x0 << 16)
10975 #define  PIX_FMT_RGB666_PACKED          (0x1 << 16)
10976 #define  PIX_FMT_RGB666_LOOSE           (0x2 << 16)
10977 #define  PIX_FMT_RGB888                 (0x3 << 16)
10978 #define  PIX_FMT_RGB101010              (0x4 << 16)
10979 #define  PIX_FMT_RGB121212              (0x5 << 16)
10980 #define  PIX_FMT_COMPRESSED             (0x6 << 16)
10981 #define  BGR_TRANSMISSION               (1 << 15)
10982 #define  PIX_VIRT_CHAN(x)               ((x) << 12)
10983 #define  PIX_VIRT_CHAN_MASK             (0x3 << 12)
10984 #define  PIX_VIRT_CHAN_SHIFT            12
10985 #define  PIX_BUF_THRESHOLD_MASK         (0x3 << 10)
10986 #define  PIX_BUF_THRESHOLD_SHIFT        10
10987 #define  PIX_BUF_THRESHOLD_1_4          (0x0 << 10)
10988 #define  PIX_BUF_THRESHOLD_1_2          (0x1 << 10)
10989 #define  PIX_BUF_THRESHOLD_3_4          (0x2 << 10)
10990 #define  PIX_BUF_THRESHOLD_FULL         (0x3 << 10)
10991 #define  CONTINUOUS_CLK_MASK            (0x3 << 8)
10992 #define  CONTINUOUS_CLK_SHIFT           8
10993 #define  CLK_ENTER_LP_AFTER_DATA        (0x0 << 8)
10994 #define  CLK_HS_OR_LP                   (0x2 << 8)
10995 #define  CLK_HS_CONTINUOUS              (0x3 << 8)
10996 #define  LINK_CALIBRATION_MASK          (0x3 << 4)
10997 #define  LINK_CALIBRATION_SHIFT         4
10998 #define  CALIBRATION_DISABLED           (0x0 << 4)
10999 #define  CALIBRATION_ENABLED_INITIAL_ONLY       (0x2 << 4)
11000 #define  CALIBRATION_ENABLED_INITIAL_PERIODIC   (0x3 << 4)
11001 #define  BLANKING_PACKET_ENABLE         (1 << 2)
11002 #define  S3D_ORIENTATION_LANDSCAPE      (1 << 1)
11003 #define  EOTP_DISABLED                  (1 << 0)
11004
11005 #define _DSI_CMD_RXCTL_0                0x6b0d4
11006 #define _DSI_CMD_RXCTL_1                0x6b8d4
11007 #define DSI_CMD_RXCTL(tc)               _MMIO_DSI(tc,   \
11008                                                   _DSI_CMD_RXCTL_0,\
11009                                                   _DSI_CMD_RXCTL_1)
11010 #define  READ_UNLOADS_DW                (1 << 16)
11011 #define  RECEIVED_UNASSIGNED_TRIGGER    (1 << 15)
11012 #define  RECEIVED_ACKNOWLEDGE_TRIGGER   (1 << 14)
11013 #define  RECEIVED_TEAR_EFFECT_TRIGGER   (1 << 13)
11014 #define  RECEIVED_RESET_TRIGGER         (1 << 12)
11015 #define  RECEIVED_PAYLOAD_WAS_LOST      (1 << 11)
11016 #define  RECEIVED_CRC_WAS_LOST          (1 << 10)
11017 #define  NUMBER_RX_PLOAD_DW_MASK        (0xff << 0)
11018 #define  NUMBER_RX_PLOAD_DW_SHIFT       0
11019
11020 #define _DSI_CMD_TXCTL_0                0x6b0d0
11021 #define _DSI_CMD_TXCTL_1                0x6b8d0
11022 #define DSI_CMD_TXCTL(tc)               _MMIO_DSI(tc,   \
11023                                                   _DSI_CMD_TXCTL_0,\
11024                                                   _DSI_CMD_TXCTL_1)
11025 #define  KEEP_LINK_IN_HS                (1 << 24)
11026 #define  FREE_HEADER_CREDIT_MASK        (0x1f << 8)
11027 #define  FREE_HEADER_CREDIT_SHIFT       0x8
11028 #define  FREE_PLOAD_CREDIT_MASK         (0xff << 0)
11029 #define  FREE_PLOAD_CREDIT_SHIFT        0
11030 #define  MAX_HEADER_CREDIT              0x10
11031 #define  MAX_PLOAD_CREDIT               0x40
11032
11033 #define _DSI_CMD_TXHDR_0                0x6b100
11034 #define _DSI_CMD_TXHDR_1                0x6b900
11035 #define DSI_CMD_TXHDR(tc)               _MMIO_DSI(tc,   \
11036                                                   _DSI_CMD_TXHDR_0,\
11037                                                   _DSI_CMD_TXHDR_1)
11038 #define  PAYLOAD_PRESENT                (1 << 31)
11039 #define  LP_DATA_TRANSFER               (1 << 30)
11040 #define  VBLANK_FENCE                   (1 << 29)
11041 #define  PARAM_WC_MASK                  (0xffff << 8)
11042 #define  PARAM_WC_LOWER_SHIFT           8
11043 #define  PARAM_WC_UPPER_SHIFT           16
11044 #define  VC_MASK                        (0x3 << 6)
11045 #define  VC_SHIFT                       6
11046 #define  DT_MASK                        (0x3f << 0)
11047 #define  DT_SHIFT                       0
11048
11049 #define _DSI_CMD_TXPYLD_0               0x6b104
11050 #define _DSI_CMD_TXPYLD_1               0x6b904
11051 #define DSI_CMD_TXPYLD(tc)              _MMIO_DSI(tc,   \
11052                                                   _DSI_CMD_TXPYLD_0,\
11053                                                   _DSI_CMD_TXPYLD_1)
11054
11055 #define _DSI_LP_MSG_0                   0x6b0d8
11056 #define _DSI_LP_MSG_1                   0x6b8d8
11057 #define DSI_LP_MSG(tc)                  _MMIO_DSI(tc,   \
11058                                                   _DSI_LP_MSG_0,\
11059                                                   _DSI_LP_MSG_1)
11060 #define  LPTX_IN_PROGRESS               (1 << 17)
11061 #define  LINK_IN_ULPS                   (1 << 16)
11062 #define  LINK_ULPS_TYPE_LP11            (1 << 8)
11063 #define  LINK_ENTER_ULPS                (1 << 0)
11064
11065 /* DSI timeout registers */
11066 #define _DSI_HSTX_TO_0                  0x6b044
11067 #define _DSI_HSTX_TO_1                  0x6b844
11068 #define DSI_HSTX_TO(tc)                 _MMIO_DSI(tc,   \
11069                                                   _DSI_HSTX_TO_0,\
11070                                                   _DSI_HSTX_TO_1)
11071 #define  HSTX_TIMEOUT_VALUE_MASK        (0xffff << 16)
11072 #define  HSTX_TIMEOUT_VALUE_SHIFT       16
11073 #define  HSTX_TIMEOUT_VALUE(x)          ((x) << 16)
11074 #define  HSTX_TIMED_OUT                 (1 << 0)
11075
11076 #define _DSI_LPRX_HOST_TO_0             0x6b048
11077 #define _DSI_LPRX_HOST_TO_1             0x6b848
11078 #define DSI_LPRX_HOST_TO(tc)            _MMIO_DSI(tc,   \
11079                                                   _DSI_LPRX_HOST_TO_0,\
11080                                                   _DSI_LPRX_HOST_TO_1)
11081 #define  LPRX_TIMED_OUT                 (1 << 16)
11082 #define  LPRX_TIMEOUT_VALUE_MASK        (0xffff << 0)
11083 #define  LPRX_TIMEOUT_VALUE_SHIFT       0
11084 #define  LPRX_TIMEOUT_VALUE(x)          ((x) << 0)
11085
11086 #define _DSI_PWAIT_TO_0                 0x6b040
11087 #define _DSI_PWAIT_TO_1                 0x6b840
11088 #define DSI_PWAIT_TO(tc)                _MMIO_DSI(tc,   \
11089                                                   _DSI_PWAIT_TO_0,\
11090                                                   _DSI_PWAIT_TO_1)
11091 #define  PRESET_TIMEOUT_VALUE_MASK      (0xffff << 16)
11092 #define  PRESET_TIMEOUT_VALUE_SHIFT     16
11093 #define  PRESET_TIMEOUT_VALUE(x)        ((x) << 16)
11094 #define  PRESPONSE_TIMEOUT_VALUE_MASK   (0xffff << 0)
11095 #define  PRESPONSE_TIMEOUT_VALUE_SHIFT  0
11096 #define  PRESPONSE_TIMEOUT_VALUE(x)     ((x) << 0)
11097
11098 #define _DSI_TA_TO_0                    0x6b04c
11099 #define _DSI_TA_TO_1                    0x6b84c
11100 #define DSI_TA_TO(tc)                   _MMIO_DSI(tc,   \
11101                                                   _DSI_TA_TO_0,\
11102                                                   _DSI_TA_TO_1)
11103 #define  TA_TIMED_OUT                   (1 << 16)
11104 #define  TA_TIMEOUT_VALUE_MASK          (0xffff << 0)
11105 #define  TA_TIMEOUT_VALUE_SHIFT         0
11106 #define  TA_TIMEOUT_VALUE(x)            ((x) << 0)
11107
11108 /* bits 31:0 */
11109 #define _MIPIA_DBI_BW_CTRL              (dev_priv->mipi_mmio_base + 0xb084)
11110 #define _MIPIC_DBI_BW_CTRL              (dev_priv->mipi_mmio_base + 0xb884)
11111 #define MIPI_DBI_BW_CTRL(port)          _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
11112
11113 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT         (dev_priv->mipi_mmio_base + 0xb088)
11114 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT         (dev_priv->mipi_mmio_base + 0xb888)
11115 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)     _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
11116 #define  LP_HS_SSW_CNT_SHIFT                            16
11117 #define  LP_HS_SSW_CNT_MASK                             (0xffff << 16)
11118 #define  HS_LP_PWR_SW_CNT_SHIFT                         0
11119 #define  HS_LP_PWR_SW_CNT_MASK                          (0xffff << 0)
11120
11121 #define _MIPIA_STOP_STATE_STALL         (dev_priv->mipi_mmio_base + 0xb08c)
11122 #define _MIPIC_STOP_STATE_STALL         (dev_priv->mipi_mmio_base + 0xb88c)
11123 #define MIPI_STOP_STATE_STALL(port)     _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
11124 #define  STOP_STATE_STALL_COUNTER_SHIFT                 0
11125 #define  STOP_STATE_STALL_COUNTER_MASK                  (0xff << 0)
11126
11127 #define _MIPIA_INTR_STAT_REG_1          (dev_priv->mipi_mmio_base + 0xb090)
11128 #define _MIPIC_INTR_STAT_REG_1          (dev_priv->mipi_mmio_base + 0xb890)
11129 #define MIPI_INTR_STAT_REG_1(port)      _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
11130 #define _MIPIA_INTR_EN_REG_1            (dev_priv->mipi_mmio_base + 0xb094)
11131 #define _MIPIC_INTR_EN_REG_1            (dev_priv->mipi_mmio_base + 0xb894)
11132 #define MIPI_INTR_EN_REG_1(port)        _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
11133 #define  RX_CONTENTION_DETECTED                         (1 << 0)
11134
11135 /* XXX: only pipe A ?!? */
11136 #define MIPIA_DBI_TYPEC_CTRL            (dev_priv->mipi_mmio_base + 0xb100)
11137 #define  DBI_TYPEC_ENABLE                               (1 << 31)
11138 #define  DBI_TYPEC_WIP                                  (1 << 30)
11139 #define  DBI_TYPEC_OPTION_SHIFT                         28
11140 #define  DBI_TYPEC_OPTION_MASK                          (3 << 28)
11141 #define  DBI_TYPEC_FREQ_SHIFT                           24
11142 #define  DBI_TYPEC_FREQ_MASK                            (0xf << 24)
11143 #define  DBI_TYPEC_OVERRIDE                             (1 << 8)
11144 #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT               0
11145 #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK                (0xff << 0)
11146
11147
11148 /* MIPI adapter registers */
11149
11150 #define _MIPIA_CTRL                     (dev_priv->mipi_mmio_base + 0xb104)
11151 #define _MIPIC_CTRL                     (dev_priv->mipi_mmio_base + 0xb904)
11152 #define MIPI_CTRL(port)                 _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
11153 #define  ESCAPE_CLOCK_DIVIDER_SHIFT                     5 /* A only */
11154 #define  ESCAPE_CLOCK_DIVIDER_MASK                      (3 << 5)
11155 #define  ESCAPE_CLOCK_DIVIDER_1                         (0 << 5)
11156 #define  ESCAPE_CLOCK_DIVIDER_2                         (1 << 5)
11157 #define  ESCAPE_CLOCK_DIVIDER_4                         (2 << 5)
11158 #define  READ_REQUEST_PRIORITY_SHIFT                    3
11159 #define  READ_REQUEST_PRIORITY_MASK                     (3 << 3)
11160 #define  READ_REQUEST_PRIORITY_LOW                      (0 << 3)
11161 #define  READ_REQUEST_PRIORITY_HIGH                     (3 << 3)
11162 #define  RGB_FLIP_TO_BGR                                (1 << 2)
11163
11164 #define  BXT_PIPE_SELECT_SHIFT                          7
11165 #define  BXT_PIPE_SELECT_MASK                           (7 << 7)
11166 #define  BXT_PIPE_SELECT(pipe)                          ((pipe) << 7)
11167 #define  GLK_PHY_STATUS_PORT_READY                      (1 << 31) /* RO */
11168 #define  GLK_ULPS_NOT_ACTIVE                            (1 << 30) /* RO */
11169 #define  GLK_MIPIIO_RESET_RELEASED                      (1 << 28)
11170 #define  GLK_CLOCK_LANE_STOP_STATE                      (1 << 27) /* RO */
11171 #define  GLK_DATA_LANE_STOP_STATE                       (1 << 26) /* RO */
11172 #define  GLK_LP_WAKE                                    (1 << 22)
11173 #define  GLK_LP11_LOW_PWR_MODE                          (1 << 21)
11174 #define  GLK_LP00_LOW_PWR_MODE                          (1 << 20)
11175 #define  GLK_FIREWALL_ENABLE                            (1 << 16)
11176 #define  BXT_PIXEL_OVERLAP_CNT_MASK                     (0xf << 10)
11177 #define  BXT_PIXEL_OVERLAP_CNT_SHIFT                    10
11178 #define  BXT_DSC_ENABLE                                 (1 << 3)
11179 #define  BXT_RGB_FLIP                                   (1 << 2)
11180 #define  GLK_MIPIIO_PORT_POWERED                        (1 << 1) /* RO */
11181 #define  GLK_MIPIIO_ENABLE                              (1 << 0)
11182
11183 #define _MIPIA_DATA_ADDRESS             (dev_priv->mipi_mmio_base + 0xb108)
11184 #define _MIPIC_DATA_ADDRESS             (dev_priv->mipi_mmio_base + 0xb908)
11185 #define MIPI_DATA_ADDRESS(port)         _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
11186 #define  DATA_MEM_ADDRESS_SHIFT                         5
11187 #define  DATA_MEM_ADDRESS_MASK                          (0x7ffffff << 5)
11188 #define  DATA_VALID                                     (1 << 0)
11189
11190 #define _MIPIA_DATA_LENGTH              (dev_priv->mipi_mmio_base + 0xb10c)
11191 #define _MIPIC_DATA_LENGTH              (dev_priv->mipi_mmio_base + 0xb90c)
11192 #define MIPI_DATA_LENGTH(port)          _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
11193 #define  DATA_LENGTH_SHIFT                              0
11194 #define  DATA_LENGTH_MASK                               (0xfffff << 0)
11195
11196 #define _MIPIA_COMMAND_ADDRESS          (dev_priv->mipi_mmio_base + 0xb110)
11197 #define _MIPIC_COMMAND_ADDRESS          (dev_priv->mipi_mmio_base + 0xb910)
11198 #define MIPI_COMMAND_ADDRESS(port)      _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
11199 #define  COMMAND_MEM_ADDRESS_SHIFT                      5
11200 #define  COMMAND_MEM_ADDRESS_MASK                       (0x7ffffff << 5)
11201 #define  AUTO_PWG_ENABLE                                (1 << 2)
11202 #define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING          (1 << 1)
11203 #define  COMMAND_VALID                                  (1 << 0)
11204
11205 #define _MIPIA_COMMAND_LENGTH           (dev_priv->mipi_mmio_base + 0xb114)
11206 #define _MIPIC_COMMAND_LENGTH           (dev_priv->mipi_mmio_base + 0xb914)
11207 #define MIPI_COMMAND_LENGTH(port)       _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
11208 #define  COMMAND_LENGTH_SHIFT(n)                        (8 * (n)) /* n: 0...3 */
11209 #define  COMMAND_LENGTH_MASK(n)                         (0xff << (8 * (n)))
11210
11211 #define _MIPIA_READ_DATA_RETURN0        (dev_priv->mipi_mmio_base + 0xb118)
11212 #define _MIPIC_READ_DATA_RETURN0        (dev_priv->mipi_mmio_base + 0xb918)
11213 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
11214
11215 #define _MIPIA_READ_DATA_VALID          (dev_priv->mipi_mmio_base + 0xb138)
11216 #define _MIPIC_READ_DATA_VALID          (dev_priv->mipi_mmio_base + 0xb938)
11217 #define MIPI_READ_DATA_VALID(port)      _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
11218 #define  READ_DATA_VALID(n)                             (1 << (n))
11219
11220 /* MOCS (Memory Object Control State) registers */
11221 #define GEN9_LNCFCMOCS(i)       _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
11222
11223 #define GEN9_GFX_MOCS(i)        _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
11224 #define GEN9_MFX0_MOCS(i)       _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
11225 #define GEN9_MFX1_MOCS(i)       _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
11226 #define GEN9_VEBOX_MOCS(i)      _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
11227 #define GEN9_BLT_MOCS(i)        _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
11228 /* Media decoder 2 MOCS registers */
11229 #define GEN11_MFX2_MOCS(i)      _MMIO(0x10000 + (i) * 4)
11230
11231 #define GEN10_SCRATCH_LNCF2             _MMIO(0xb0a0)
11232 #define   PMFLUSHDONE_LNICRSDROP        (1 << 20)
11233 #define   PMFLUSH_GAPL3UNBLOCK          (1 << 21)
11234 #define   PMFLUSHDONE_LNEBLK            (1 << 22)
11235
11236 #define GEN12_GLOBAL_MOCS(i)    _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
11237
11238 /* gamt regs */
11239 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
11240 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
11241 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
11242 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
11243 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
11244
11245 #define MMCD_MISC_CTRL          _MMIO(0x4ddc) /* skl+ */
11246 #define  MMCD_PCLA              (1 << 31)
11247 #define  MMCD_HOTSPOT_EN        (1 << 27)
11248
11249 #define _ICL_PHY_MISC_A         0x64C00
11250 #define _ICL_PHY_MISC_B         0x64C04
11251 #define ICL_PHY_MISC(port)      _MMIO_PORT(port, _ICL_PHY_MISC_A, \
11252                                                  _ICL_PHY_MISC_B)
11253 #define  ICL_PHY_MISC_MUX_DDID                  (1 << 28)
11254 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN       (1 << 23)
11255
11256 /* Icelake Display Stream Compression Registers */
11257 #define DSCA_PICTURE_PARAMETER_SET_0            _MMIO(0x6B200)
11258 #define DSCC_PICTURE_PARAMETER_SET_0            _MMIO(0x6BA00)
11259 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB    0x78270
11260 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB    0x78370
11261 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC    0x78470
11262 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC    0x78570
11263 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11264                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
11265                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
11266 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11267                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
11268                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
11269 #define  DSC_VBR_ENABLE                 (1 << 19)
11270 #define  DSC_422_ENABLE                 (1 << 18)
11271 #define  DSC_COLOR_SPACE_CONVERSION     (1 << 17)
11272 #define  DSC_BLOCK_PREDICTION           (1 << 16)
11273 #define  DSC_LINE_BUF_DEPTH_SHIFT       12
11274 #define  DSC_BPC_SHIFT                  8
11275 #define  DSC_VER_MIN_SHIFT              4
11276 #define  DSC_VER_MAJ                    (0x1 << 0)
11277
11278 #define DSCA_PICTURE_PARAMETER_SET_1            _MMIO(0x6B204)
11279 #define DSCC_PICTURE_PARAMETER_SET_1            _MMIO(0x6BA04)
11280 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB    0x78274
11281 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB    0x78374
11282 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC    0x78474
11283 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC    0x78574
11284 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11285                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
11286                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
11287 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11288                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
11289                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
11290 #define  DSC_BPP(bpp)                           ((bpp) << 0)
11291
11292 #define DSCA_PICTURE_PARAMETER_SET_2            _MMIO(0x6B208)
11293 #define DSCC_PICTURE_PARAMETER_SET_2            _MMIO(0x6BA08)
11294 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB    0x78278
11295 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB    0x78378
11296 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC    0x78478
11297 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC    0x78578
11298 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11299                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
11300                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
11301 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11302                                             _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
11303                                             _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
11304 #define  DSC_PIC_WIDTH(pic_width)       ((pic_width) << 16)
11305 #define  DSC_PIC_HEIGHT(pic_height)     ((pic_height) << 0)
11306
11307 #define DSCA_PICTURE_PARAMETER_SET_3            _MMIO(0x6B20C)
11308 #define DSCC_PICTURE_PARAMETER_SET_3            _MMIO(0x6BA0C)
11309 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB    0x7827C
11310 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB    0x7837C
11311 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC    0x7847C
11312 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC    0x7857C
11313 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11314                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
11315                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
11316 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11317                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
11318                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
11319 #define  DSC_SLICE_WIDTH(slice_width)   ((slice_width) << 16)
11320 #define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
11321
11322 #define DSCA_PICTURE_PARAMETER_SET_4            _MMIO(0x6B210)
11323 #define DSCC_PICTURE_PARAMETER_SET_4            _MMIO(0x6BA10)
11324 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB    0x78280
11325 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB    0x78380
11326 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC    0x78480
11327 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC    0x78580
11328 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11329                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
11330                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
11331 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11332                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
11333                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
11334 #define  DSC_INITIAL_DEC_DELAY(dec_delay)       ((dec_delay) << 16)
11335 #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
11336
11337 #define DSCA_PICTURE_PARAMETER_SET_5            _MMIO(0x6B214)
11338 #define DSCC_PICTURE_PARAMETER_SET_5            _MMIO(0x6BA14)
11339 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB    0x78284
11340 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB    0x78384
11341 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC    0x78484
11342 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC    0x78584
11343 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11344                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
11345                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
11346 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11347                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
11348                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
11349 #define  DSC_SCALE_DEC_INT(scale_dec)   ((scale_dec) << 16)
11350 #define  DSC_SCALE_INC_INT(scale_inc)           ((scale_inc) << 0)
11351
11352 #define DSCA_PICTURE_PARAMETER_SET_6            _MMIO(0x6B218)
11353 #define DSCC_PICTURE_PARAMETER_SET_6            _MMIO(0x6BA18)
11354 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB    0x78288
11355 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB    0x78388
11356 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC    0x78488
11357 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC    0x78588
11358 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11359                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
11360                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
11361 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11362                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
11363                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
11364 #define  DSC_FLATNESS_MAX_QP(max_qp)            ((max_qp) << 24)
11365 #define  DSC_FLATNESS_MIN_QP(min_qp)            ((min_qp) << 16)
11366 #define  DSC_FIRST_LINE_BPG_OFFSET(offset)      ((offset) << 8)
11367 #define  DSC_INITIAL_SCALE_VALUE(value)         ((value) << 0)
11368
11369 #define DSCA_PICTURE_PARAMETER_SET_7            _MMIO(0x6B21C)
11370 #define DSCC_PICTURE_PARAMETER_SET_7            _MMIO(0x6BA1C)
11371 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB    0x7828C
11372 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB    0x7838C
11373 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC    0x7848C
11374 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC    0x7858C
11375 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11376                                                             _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
11377                                                             _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
11378 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11379                                                             _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
11380                                                             _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
11381 #define  DSC_NFL_BPG_OFFSET(bpg_offset)         ((bpg_offset) << 16)
11382 #define  DSC_SLICE_BPG_OFFSET(bpg_offset)       ((bpg_offset) << 0)
11383
11384 #define DSCA_PICTURE_PARAMETER_SET_8            _MMIO(0x6B220)
11385 #define DSCC_PICTURE_PARAMETER_SET_8            _MMIO(0x6BA20)
11386 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB    0x78290
11387 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB    0x78390
11388 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC    0x78490
11389 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC    0x78590
11390 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11391                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
11392                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
11393 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11394                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
11395                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
11396 #define  DSC_INITIAL_OFFSET(initial_offset)             ((initial_offset) << 16)
11397 #define  DSC_FINAL_OFFSET(final_offset)                 ((final_offset) << 0)
11398
11399 #define DSCA_PICTURE_PARAMETER_SET_9            _MMIO(0x6B224)
11400 #define DSCC_PICTURE_PARAMETER_SET_9            _MMIO(0x6BA24)
11401 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB    0x78294
11402 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB    0x78394
11403 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC    0x78494
11404 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC    0x78594
11405 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11406                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
11407                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
11408 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11409                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
11410                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
11411 #define  DSC_RC_EDGE_FACTOR(rc_edge_fact)       ((rc_edge_fact) << 16)
11412 #define  DSC_RC_MODEL_SIZE(rc_model_size)       ((rc_model_size) << 0)
11413
11414 #define DSCA_PICTURE_PARAMETER_SET_10           _MMIO(0x6B228)
11415 #define DSCC_PICTURE_PARAMETER_SET_10           _MMIO(0x6BA28)
11416 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB   0x78298
11417 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB   0x78398
11418 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC   0x78498
11419 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC   0x78598
11420 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11421                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
11422                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
11423 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11424                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
11425                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
11426 #define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)          ((rc_tgt_off_low) << 20)
11427 #define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)        ((rc_tgt_off_high) << 16)
11428 #define  DSC_RC_QUANT_INC_LIMIT1(lim)                   ((lim) << 8)
11429 #define  DSC_RC_QUANT_INC_LIMIT0(lim)                   ((lim) << 0)
11430
11431 #define DSCA_PICTURE_PARAMETER_SET_11           _MMIO(0x6B22C)
11432 #define DSCC_PICTURE_PARAMETER_SET_11           _MMIO(0x6BA2C)
11433 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB   0x7829C
11434 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB   0x7839C
11435 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC   0x7849C
11436 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC   0x7859C
11437 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11438                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
11439                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
11440 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11441                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
11442                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
11443
11444 #define DSCA_PICTURE_PARAMETER_SET_12           _MMIO(0x6B260)
11445 #define DSCC_PICTURE_PARAMETER_SET_12           _MMIO(0x6BA60)
11446 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB   0x782A0
11447 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB   0x783A0
11448 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC   0x784A0
11449 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC   0x785A0
11450 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11451                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
11452                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
11453 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11454                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
11455                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
11456
11457 #define DSCA_PICTURE_PARAMETER_SET_13           _MMIO(0x6B264)
11458 #define DSCC_PICTURE_PARAMETER_SET_13           _MMIO(0x6BA64)
11459 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB   0x782A4
11460 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB   0x783A4
11461 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC   0x784A4
11462 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC   0x785A4
11463 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11464                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
11465                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
11466 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11467                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
11468                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
11469
11470 #define DSCA_PICTURE_PARAMETER_SET_14           _MMIO(0x6B268)
11471 #define DSCC_PICTURE_PARAMETER_SET_14           _MMIO(0x6BA68)
11472 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB   0x782A8
11473 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB   0x783A8
11474 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC   0x784A8
11475 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC   0x785A8
11476 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11477                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
11478                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
11479 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11480                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
11481                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
11482
11483 #define DSCA_PICTURE_PARAMETER_SET_15           _MMIO(0x6B26C)
11484 #define DSCC_PICTURE_PARAMETER_SET_15           _MMIO(0x6BA6C)
11485 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB   0x782AC
11486 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB   0x783AC
11487 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC   0x784AC
11488 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC   0x785AC
11489 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11490                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
11491                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
11492 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11493                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
11494                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
11495
11496 #define DSCA_PICTURE_PARAMETER_SET_16           _MMIO(0x6B270)
11497 #define DSCC_PICTURE_PARAMETER_SET_16           _MMIO(0x6BA70)
11498 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB   0x782B0
11499 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB   0x783B0
11500 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC   0x784B0
11501 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC   0x785B0
11502 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11503                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
11504                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
11505 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11506                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
11507                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
11508 #define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)   ((slice_row_per_frame) << 20)
11509 #define  DSC_SLICE_PER_LINE(slice_per_line)             ((slice_per_line) << 16)
11510 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)         ((slice_chunk_size) << 0)
11511
11512 /* Icelake Rate Control Buffer Threshold Registers */
11513 #define DSCA_RC_BUF_THRESH_0                    _MMIO(0x6B230)
11514 #define DSCA_RC_BUF_THRESH_0_UDW                _MMIO(0x6B230 + 4)
11515 #define DSCC_RC_BUF_THRESH_0                    _MMIO(0x6BA30)
11516 #define DSCC_RC_BUF_THRESH_0_UDW                _MMIO(0x6BA30 + 4)
11517 #define _ICL_DSC0_RC_BUF_THRESH_0_PB            (0x78254)
11518 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB        (0x78254 + 4)
11519 #define _ICL_DSC1_RC_BUF_THRESH_0_PB            (0x78354)
11520 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB        (0x78354 + 4)
11521 #define _ICL_DSC0_RC_BUF_THRESH_0_PC            (0x78454)
11522 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC        (0x78454 + 4)
11523 #define _ICL_DSC1_RC_BUF_THRESH_0_PC            (0x78554)
11524 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC        (0x78554 + 4)
11525 #define ICL_DSC0_RC_BUF_THRESH_0(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
11526                                                 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
11527                                                 _ICL_DSC0_RC_BUF_THRESH_0_PC)
11528 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
11529                                                 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
11530                                                 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
11531 #define ICL_DSC1_RC_BUF_THRESH_0(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
11532                                                 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
11533                                                 _ICL_DSC1_RC_BUF_THRESH_0_PC)
11534 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
11535                                                 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
11536                                                 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
11537
11538 #define DSCA_RC_BUF_THRESH_1                    _MMIO(0x6B238)
11539 #define DSCA_RC_BUF_THRESH_1_UDW                _MMIO(0x6B238 + 4)
11540 #define DSCC_RC_BUF_THRESH_1                    _MMIO(0x6BA38)
11541 #define DSCC_RC_BUF_THRESH_1_UDW                _MMIO(0x6BA38 + 4)
11542 #define _ICL_DSC0_RC_BUF_THRESH_1_PB            (0x7825C)
11543 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB        (0x7825C + 4)
11544 #define _ICL_DSC1_RC_BUF_THRESH_1_PB            (0x7835C)
11545 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB        (0x7835C + 4)
11546 #define _ICL_DSC0_RC_BUF_THRESH_1_PC            (0x7845C)
11547 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC        (0x7845C + 4)
11548 #define _ICL_DSC1_RC_BUF_THRESH_1_PC            (0x7855C)
11549 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC        (0x7855C + 4)
11550 #define ICL_DSC0_RC_BUF_THRESH_1(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
11551                                                 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
11552                                                 _ICL_DSC0_RC_BUF_THRESH_1_PC)
11553 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
11554                                                 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
11555                                                 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
11556 #define ICL_DSC1_RC_BUF_THRESH_1(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
11557                                                 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
11558                                                 _ICL_DSC1_RC_BUF_THRESH_1_PC)
11559 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
11560                                                 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
11561                                                 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
11562
11563 #define PORT_TX_DFLEXDPSP(fia)                  _MMIO_FIA((fia), 0x008A0)
11564 #define   MODULAR_FIA_MASK                      (1 << 4)
11565 #define   TC_LIVE_STATE_TBT(tc_port)            (1 << ((tc_port) * 8 + 6))
11566 #define   TC_LIVE_STATE_TC(tc_port)             (1 << ((tc_port) * 8 + 5))
11567 #define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)     ((tc_port) * 8)
11568 #define   DP_LANE_ASSIGNMENT_MASK(tc_port)      (0xf << ((tc_port) * 8))
11569 #define   DP_LANE_ASSIGNMENT(tc_port, x)        ((x) << ((tc_port) * 8))
11570
11571 #define PORT_TX_DFLEXDPPMS(fia)                 _MMIO_FIA((fia), 0x00890)
11572 #define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)         (1 << (tc_port))
11573
11574 #define PORT_TX_DFLEXDPCSSS(fia)                _MMIO_FIA((fia), 0x00894)
11575 #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)          (1 << (tc_port))
11576
11577 #endif /* _I915_REG_H_ */