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pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / i915_sysfs.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 *
26 */
27
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/stat.h>
31 #include <linux/sysfs.h>
32 #include "intel_drv.h"
33 #include "i915_drv.h"
34
35 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
36 {
37 struct drm_minor *minor = dev_get_drvdata(kdev);
38 return to_i915(minor->dev);
39 }
40
41 #ifdef CONFIG_PM
42 static u32 calc_residency(struct drm_i915_private *dev_priv,
43 i915_reg_t reg)
44 {
45 u64 res;
46
47 intel_runtime_pm_get(dev_priv);
48 res = intel_rc6_residency_us(dev_priv, reg);
49 intel_runtime_pm_put(dev_priv);
50
51 return DIV_ROUND_CLOSEST_ULL(res, 1000);
52 }
53
54 static ssize_t
55 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
56 {
57 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
58 unsigned int mask;
59
60 mask = 0;
61 if (HAS_RC6(dev_priv))
62 mask |= BIT(0);
63 if (HAS_RC6p(dev_priv))
64 mask |= BIT(1);
65 if (HAS_RC6pp(dev_priv))
66 mask |= BIT(2);
67
68 return snprintf(buf, PAGE_SIZE, "%x\n", mask);
69 }
70
71 static ssize_t
72 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
73 {
74 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
75 u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
76 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
77 }
78
79 static ssize_t
80 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
81 {
82 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
83 u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
84 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
85 }
86
87 static ssize_t
88 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
89 {
90 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
91 u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
92 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
93 }
94
95 static ssize_t
96 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
97 {
98 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
99 u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
100 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
101 }
102
103 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
104 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
105 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
106 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
107 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
108
109 static struct attribute *rc6_attrs[] = {
110 &dev_attr_rc6_enable.attr,
111 &dev_attr_rc6_residency_ms.attr,
112 NULL
113 };
114
115 static const struct attribute_group rc6_attr_group = {
116 .name = power_group_name,
117 .attrs = rc6_attrs
118 };
119
120 static struct attribute *rc6p_attrs[] = {
121 &dev_attr_rc6p_residency_ms.attr,
122 &dev_attr_rc6pp_residency_ms.attr,
123 NULL
124 };
125
126 static const struct attribute_group rc6p_attr_group = {
127 .name = power_group_name,
128 .attrs = rc6p_attrs
129 };
130
131 static struct attribute *media_rc6_attrs[] = {
132 &dev_attr_media_rc6_residency_ms.attr,
133 NULL
134 };
135
136 static const struct attribute_group media_rc6_attr_group = {
137 .name = power_group_name,
138 .attrs = media_rc6_attrs
139 };
140 #endif
141
142 static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset)
143 {
144 if (!HAS_L3_DPF(dev_priv))
145 return -EPERM;
146
147 if (offset % 4 != 0)
148 return -EINVAL;
149
150 if (offset >= GEN7_L3LOG_SIZE)
151 return -ENXIO;
152
153 return 0;
154 }
155
156 static ssize_t
157 i915_l3_read(struct file *filp, struct kobject *kobj,
158 struct bin_attribute *attr, char *buf,
159 loff_t offset, size_t count)
160 {
161 struct device *kdev = kobj_to_dev(kobj);
162 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
163 struct drm_device *dev = &dev_priv->drm;
164 int slice = (int)(uintptr_t)attr->private;
165 int ret;
166
167 count = round_down(count, 4);
168
169 ret = l3_access_valid(dev_priv, offset);
170 if (ret)
171 return ret;
172
173 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
174
175 ret = i915_mutex_lock_interruptible(dev);
176 if (ret)
177 return ret;
178
179 if (dev_priv->l3_parity.remap_info[slice])
180 memcpy(buf,
181 dev_priv->l3_parity.remap_info[slice] + (offset/4),
182 count);
183 else
184 memset(buf, 0, count);
185
186 mutex_unlock(&dev->struct_mutex);
187
188 return count;
189 }
190
191 static ssize_t
192 i915_l3_write(struct file *filp, struct kobject *kobj,
193 struct bin_attribute *attr, char *buf,
194 loff_t offset, size_t count)
195 {
196 struct device *kdev = kobj_to_dev(kobj);
197 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
198 struct drm_device *dev = &dev_priv->drm;
199 struct i915_gem_context *ctx;
200 int slice = (int)(uintptr_t)attr->private;
201 u32 **remap_info;
202 int ret;
203
204 ret = l3_access_valid(dev_priv, offset);
205 if (ret)
206 return ret;
207
208 ret = i915_mutex_lock_interruptible(dev);
209 if (ret)
210 return ret;
211
212 remap_info = &dev_priv->l3_parity.remap_info[slice];
213 if (!*remap_info) {
214 *remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
215 if (!*remap_info) {
216 ret = -ENOMEM;
217 goto out;
218 }
219 }
220
221 /* TODO: Ideally we really want a GPU reset here to make sure errors
222 * aren't propagated. Since I cannot find a stable way to reset the GPU
223 * at this point it is left as a TODO.
224 */
225 memcpy(*remap_info + (offset/4), buf, count);
226
227 /* NB: We defer the remapping until we switch to the context */
228 list_for_each_entry(ctx, &dev_priv->contexts.list, link)
229 ctx->remap_slice |= (1<<slice);
230
231 ret = count;
232
233 out:
234 mutex_unlock(&dev->struct_mutex);
235
236 return ret;
237 }
238
239 static const struct bin_attribute dpf_attrs = {
240 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
241 .size = GEN7_L3LOG_SIZE,
242 .read = i915_l3_read,
243 .write = i915_l3_write,
244 .mmap = NULL,
245 .private = (void *)0
246 };
247
248 static const struct bin_attribute dpf_attrs_1 = {
249 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
250 .size = GEN7_L3LOG_SIZE,
251 .read = i915_l3_read,
252 .write = i915_l3_write,
253 .mmap = NULL,
254 .private = (void *)1
255 };
256
257 static ssize_t gt_act_freq_mhz_show(struct device *kdev,
258 struct device_attribute *attr, char *buf)
259 {
260 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
261 int ret;
262
263 intel_runtime_pm_get(dev_priv);
264
265 mutex_lock(&dev_priv->pcu_lock);
266 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
267 u32 freq;
268 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
269 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
270 } else {
271 ret = intel_gpu_freq(dev_priv,
272 intel_get_cagf(dev_priv,
273 I915_READ(GEN6_RPSTAT1)));
274 }
275 mutex_unlock(&dev_priv->pcu_lock);
276
277 intel_runtime_pm_put(dev_priv);
278
279 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
280 }
281
282 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
283 struct device_attribute *attr, char *buf)
284 {
285 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
286
287 return snprintf(buf, PAGE_SIZE, "%d\n",
288 intel_gpu_freq(dev_priv,
289 dev_priv->gt_pm.rps.cur_freq));
290 }
291
292 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
293 {
294 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
295
296 return snprintf(buf, PAGE_SIZE, "%d\n",
297 intel_gpu_freq(dev_priv,
298 dev_priv->gt_pm.rps.boost_freq));
299 }
300
301 static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
302 struct device_attribute *attr,
303 const char *buf, size_t count)
304 {
305 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
306 struct intel_rps *rps = &dev_priv->gt_pm.rps;
307 bool boost = false;
308 ssize_t ret;
309 u32 val;
310
311 ret = kstrtou32(buf, 0, &val);
312 if (ret)
313 return ret;
314
315 /* Validate against (static) hardware limits */
316 val = intel_freq_opcode(dev_priv, val);
317 if (val < rps->min_freq || val > rps->max_freq)
318 return -EINVAL;
319
320 mutex_lock(&dev_priv->pcu_lock);
321 if (val != rps->boost_freq) {
322 rps->boost_freq = val;
323 boost = atomic_read(&rps->num_waiters);
324 }
325 mutex_unlock(&dev_priv->pcu_lock);
326 if (boost)
327 schedule_work(&rps->work);
328
329 return count;
330 }
331
332 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
333 struct device_attribute *attr, char *buf)
334 {
335 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
336
337 return snprintf(buf, PAGE_SIZE, "%d\n",
338 intel_gpu_freq(dev_priv,
339 dev_priv->gt_pm.rps.efficient_freq));
340 }
341
342 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
343 {
344 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
345
346 return snprintf(buf, PAGE_SIZE, "%d\n",
347 intel_gpu_freq(dev_priv,
348 dev_priv->gt_pm.rps.max_freq_softlimit));
349 }
350
351 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
352 struct device_attribute *attr,
353 const char *buf, size_t count)
354 {
355 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
356 struct intel_rps *rps = &dev_priv->gt_pm.rps;
357 u32 val;
358 ssize_t ret;
359
360 ret = kstrtou32(buf, 0, &val);
361 if (ret)
362 return ret;
363
364 intel_runtime_pm_get(dev_priv);
365
366 mutex_lock(&dev_priv->pcu_lock);
367
368 val = intel_freq_opcode(dev_priv, val);
369
370 if (val < rps->min_freq ||
371 val > rps->max_freq ||
372 val < rps->min_freq_softlimit) {
373 mutex_unlock(&dev_priv->pcu_lock);
374 intel_runtime_pm_put(dev_priv);
375 return -EINVAL;
376 }
377
378 if (val > rps->rp0_freq)
379 DRM_DEBUG("User requested overclocking to %d\n",
380 intel_gpu_freq(dev_priv, val));
381
382 rps->max_freq_softlimit = val;
383
384 val = clamp_t(int, rps->cur_freq,
385 rps->min_freq_softlimit,
386 rps->max_freq_softlimit);
387
388 /* We still need *_set_rps to process the new max_delay and
389 * update the interrupt limits and PMINTRMSK even though
390 * frequency request may be unchanged. */
391 ret = intel_set_rps(dev_priv, val);
392
393 mutex_unlock(&dev_priv->pcu_lock);
394
395 intel_runtime_pm_put(dev_priv);
396
397 return ret ?: count;
398 }
399
400 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
401 {
402 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
403
404 return snprintf(buf, PAGE_SIZE, "%d\n",
405 intel_gpu_freq(dev_priv,
406 dev_priv->gt_pm.rps.min_freq_softlimit));
407 }
408
409 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
410 struct device_attribute *attr,
411 const char *buf, size_t count)
412 {
413 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
414 struct intel_rps *rps = &dev_priv->gt_pm.rps;
415 u32 val;
416 ssize_t ret;
417
418 ret = kstrtou32(buf, 0, &val);
419 if (ret)
420 return ret;
421
422 intel_runtime_pm_get(dev_priv);
423
424 mutex_lock(&dev_priv->pcu_lock);
425
426 val = intel_freq_opcode(dev_priv, val);
427
428 if (val < rps->min_freq ||
429 val > rps->max_freq ||
430 val > rps->max_freq_softlimit) {
431 mutex_unlock(&dev_priv->pcu_lock);
432 intel_runtime_pm_put(dev_priv);
433 return -EINVAL;
434 }
435
436 rps->min_freq_softlimit = val;
437
438 val = clamp_t(int, rps->cur_freq,
439 rps->min_freq_softlimit,
440 rps->max_freq_softlimit);
441
442 /* We still need *_set_rps to process the new min_delay and
443 * update the interrupt limits and PMINTRMSK even though
444 * frequency request may be unchanged. */
445 ret = intel_set_rps(dev_priv, val);
446
447 mutex_unlock(&dev_priv->pcu_lock);
448
449 intel_runtime_pm_put(dev_priv);
450
451 return ret ?: count;
452 }
453
454 static DEVICE_ATTR_RO(gt_act_freq_mhz);
455 static DEVICE_ATTR_RO(gt_cur_freq_mhz);
456 static DEVICE_ATTR_RW(gt_boost_freq_mhz);
457 static DEVICE_ATTR_RW(gt_max_freq_mhz);
458 static DEVICE_ATTR_RW(gt_min_freq_mhz);
459
460 static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
461
462 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
463 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
464 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
465 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
466
467 /* For now we have a static number of RP states */
468 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
469 {
470 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
471 struct intel_rps *rps = &dev_priv->gt_pm.rps;
472 u32 val;
473
474 if (attr == &dev_attr_gt_RP0_freq_mhz)
475 val = intel_gpu_freq(dev_priv, rps->rp0_freq);
476 else if (attr == &dev_attr_gt_RP1_freq_mhz)
477 val = intel_gpu_freq(dev_priv, rps->rp1_freq);
478 else if (attr == &dev_attr_gt_RPn_freq_mhz)
479 val = intel_gpu_freq(dev_priv, rps->min_freq);
480 else
481 BUG();
482
483 return snprintf(buf, PAGE_SIZE, "%d\n", val);
484 }
485
486 static const struct attribute * const gen6_attrs[] = {
487 &dev_attr_gt_act_freq_mhz.attr,
488 &dev_attr_gt_cur_freq_mhz.attr,
489 &dev_attr_gt_boost_freq_mhz.attr,
490 &dev_attr_gt_max_freq_mhz.attr,
491 &dev_attr_gt_min_freq_mhz.attr,
492 &dev_attr_gt_RP0_freq_mhz.attr,
493 &dev_attr_gt_RP1_freq_mhz.attr,
494 &dev_attr_gt_RPn_freq_mhz.attr,
495 NULL,
496 };
497
498 static const struct attribute * const vlv_attrs[] = {
499 &dev_attr_gt_act_freq_mhz.attr,
500 &dev_attr_gt_cur_freq_mhz.attr,
501 &dev_attr_gt_boost_freq_mhz.attr,
502 &dev_attr_gt_max_freq_mhz.attr,
503 &dev_attr_gt_min_freq_mhz.attr,
504 &dev_attr_gt_RP0_freq_mhz.attr,
505 &dev_attr_gt_RP1_freq_mhz.attr,
506 &dev_attr_gt_RPn_freq_mhz.attr,
507 &dev_attr_vlv_rpe_freq_mhz.attr,
508 NULL,
509 };
510
511 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
512
513 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
514 struct bin_attribute *attr, char *buf,
515 loff_t off, size_t count)
516 {
517
518 struct device *kdev = kobj_to_dev(kobj);
519 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
520 struct i915_gpu_state *gpu;
521 ssize_t ret;
522
523 gpu = i915_first_error_state(i915);
524 if (gpu) {
525 ret = i915_gpu_state_copy_to_buffer(gpu, buf, off, count);
526 i915_gpu_state_put(gpu);
527 } else {
528 const char *str = "No error state collected\n";
529 size_t len = strlen(str);
530
531 ret = min_t(size_t, count, len - off);
532 memcpy(buf, str + off, ret);
533 }
534
535 return ret;
536 }
537
538 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
539 struct bin_attribute *attr, char *buf,
540 loff_t off, size_t count)
541 {
542 struct device *kdev = kobj_to_dev(kobj);
543 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
544
545 DRM_DEBUG_DRIVER("Resetting error state\n");
546 i915_reset_error_state(dev_priv);
547
548 return count;
549 }
550
551 static const struct bin_attribute error_state_attr = {
552 .attr.name = "error",
553 .attr.mode = S_IRUSR | S_IWUSR,
554 .size = 0,
555 .read = error_state_read,
556 .write = error_state_write,
557 };
558
559 static void i915_setup_error_capture(struct device *kdev)
560 {
561 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
562 DRM_ERROR("error_state sysfs setup failed\n");
563 }
564
565 static void i915_teardown_error_capture(struct device *kdev)
566 {
567 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
568 }
569 #else
570 static void i915_setup_error_capture(struct device *kdev) {}
571 static void i915_teardown_error_capture(struct device *kdev) {}
572 #endif
573
574 void i915_setup_sysfs(struct drm_i915_private *dev_priv)
575 {
576 struct device *kdev = dev_priv->drm.primary->kdev;
577 int ret;
578
579 #ifdef CONFIG_PM
580 if (HAS_RC6(dev_priv)) {
581 ret = sysfs_merge_group(&kdev->kobj,
582 &rc6_attr_group);
583 if (ret)
584 DRM_ERROR("RC6 residency sysfs setup failed\n");
585 }
586 if (HAS_RC6p(dev_priv)) {
587 ret = sysfs_merge_group(&kdev->kobj,
588 &rc6p_attr_group);
589 if (ret)
590 DRM_ERROR("RC6p residency sysfs setup failed\n");
591 }
592 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
593 ret = sysfs_merge_group(&kdev->kobj,
594 &media_rc6_attr_group);
595 if (ret)
596 DRM_ERROR("Media RC6 residency sysfs setup failed\n");
597 }
598 #endif
599 if (HAS_L3_DPF(dev_priv)) {
600 ret = device_create_bin_file(kdev, &dpf_attrs);
601 if (ret)
602 DRM_ERROR("l3 parity sysfs setup failed\n");
603
604 if (NUM_L3_SLICES(dev_priv) > 1) {
605 ret = device_create_bin_file(kdev,
606 &dpf_attrs_1);
607 if (ret)
608 DRM_ERROR("l3 parity slice 1 setup failed\n");
609 }
610 }
611
612 ret = 0;
613 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
614 ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
615 else if (INTEL_GEN(dev_priv) >= 6)
616 ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
617 if (ret)
618 DRM_ERROR("RPS sysfs setup failed\n");
619
620 i915_setup_error_capture(kdev);
621 }
622
623 void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
624 {
625 struct device *kdev = dev_priv->drm.primary->kdev;
626
627 i915_teardown_error_capture(kdev);
628
629 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
630 sysfs_remove_files(&kdev->kobj, vlv_attrs);
631 else
632 sysfs_remove_files(&kdev->kobj, gen6_attrs);
633 device_remove_bin_file(kdev, &dpf_attrs_1);
634 device_remove_bin_file(kdev, &dpf_attrs);
635 #ifdef CONFIG_PM
636 sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
637 sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
638 #endif
639 }