2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include <drm/intel_lpe_audio.h>
28 #include "intel_drv.h"
31 #include <drm/drm_edid.h>
35 * DOC: High Definition Audio over HDMI and Display Port
37 * The graphics and audio drivers together support High Definition Audio over
38 * HDMI and Display Port. The audio programming sequences are divided into audio
39 * codec and controller enable and disable sequences. The graphics driver
40 * handles the audio codec sequences, while the audio driver handles the audio
41 * controller sequences.
43 * The disable sequences must be performed before disabling the transcoder or
44 * port. The enable sequences may only be performed after enabling the
45 * transcoder and port, and after completed link training. Therefore the audio
46 * enable/disable sequences are part of the modeset sequence.
48 * The codec and controller sequences could be done either parallel or serial,
49 * but generally the ELDV/PD change in the codec sequence indicates to the audio
50 * driver that the controller sequence should start. Indeed, most of the
51 * co-operation between the graphics and audio drivers is handled via audio
52 * related registers. (The notable exception is the power management, not
55 * The struct &i915_audio_component is used to interact between the graphics
56 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
57 * defined in graphics driver and called in audio driver. The
58 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
62 #define LC_540M 540000
63 #define LC_270M 270000
64 #define LC_162M 162000
73 /* Values according to DP 1.4 Table 2-104 */
74 static const struct dp_aud_n_m dp_aud_n_m
[] = {
75 { 32000, LC_162M
, 1024, 10125 },
76 { 44100, LC_162M
, 784, 5625 },
77 { 48000, LC_162M
, 512, 3375 },
78 { 64000, LC_162M
, 2048, 10125 },
79 { 88200, LC_162M
, 1568, 5625 },
80 { 96000, LC_162M
, 1024, 3375 },
81 { 128000, LC_162M
, 4096, 10125 },
82 { 176400, LC_162M
, 3136, 5625 },
83 { 192000, LC_162M
, 2048, 3375 },
84 { 32000, LC_270M
, 1024, 16875 },
85 { 44100, LC_270M
, 784, 9375 },
86 { 48000, LC_270M
, 512, 5625 },
87 { 64000, LC_270M
, 2048, 16875 },
88 { 88200, LC_270M
, 1568, 9375 },
89 { 96000, LC_270M
, 1024, 5625 },
90 { 128000, LC_270M
, 4096, 16875 },
91 { 176400, LC_270M
, 3136, 9375 },
92 { 192000, LC_270M
, 2048, 5625 },
93 { 32000, LC_540M
, 1024, 33750 },
94 { 44100, LC_540M
, 784, 18750 },
95 { 48000, LC_540M
, 512, 11250 },
96 { 64000, LC_540M
, 2048, 33750 },
97 { 88200, LC_540M
, 1568, 18750 },
98 { 96000, LC_540M
, 1024, 11250 },
99 { 128000, LC_540M
, 4096, 33750 },
100 { 176400, LC_540M
, 3136, 18750 },
101 { 192000, LC_540M
, 2048, 11250 },
104 static const struct dp_aud_n_m
*
105 audio_config_dp_get_n_m(struct intel_crtc
*intel_crtc
, int rate
)
109 for (i
= 0; i
< ARRAY_SIZE(dp_aud_n_m
); i
++) {
110 if (rate
== dp_aud_n_m
[i
].sample_rate
&&
111 intel_crtc
->config
->port_clock
== dp_aud_n_m
[i
].clock
)
112 return &dp_aud_n_m
[i
];
118 static const struct {
121 } hdmi_audio_clock
[] = {
122 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
123 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
124 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
125 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
126 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
127 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
128 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
129 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
130 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
131 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
134 /* HDMI N/CTS table */
135 #define TMDS_297M 297000
136 #define TMDS_296M 296703
137 static const struct {
142 } hdmi_aud_ncts
[] = {
143 { 44100, TMDS_296M
, 4459, 234375 },
144 { 44100, TMDS_297M
, 4704, 247500 },
145 { 48000, TMDS_296M
, 5824, 281250 },
146 { 48000, TMDS_297M
, 5120, 247500 },
147 { 32000, TMDS_296M
, 5824, 421875 },
148 { 32000, TMDS_297M
, 3072, 222750 },
149 { 88200, TMDS_296M
, 8918, 234375 },
150 { 88200, TMDS_297M
, 9408, 247500 },
151 { 96000, TMDS_296M
, 11648, 281250 },
152 { 96000, TMDS_297M
, 10240, 247500 },
153 { 176400, TMDS_296M
, 17836, 234375 },
154 { 176400, TMDS_297M
, 18816, 247500 },
155 { 192000, TMDS_296M
, 23296, 281250 },
156 { 192000, TMDS_297M
, 20480, 247500 },
159 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
160 static u32
audio_config_hdmi_pixel_clock(const struct drm_display_mode
*adjusted_mode
)
164 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
165 if (adjusted_mode
->crtc_clock
== hdmi_audio_clock
[i
].clock
)
169 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
170 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
171 adjusted_mode
->crtc_clock
);
175 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
176 hdmi_audio_clock
[i
].clock
,
177 hdmi_audio_clock
[i
].config
);
179 return hdmi_audio_clock
[i
].config
;
182 static int audio_config_hdmi_get_n(const struct drm_display_mode
*adjusted_mode
,
187 for (i
= 0; i
< ARRAY_SIZE(hdmi_aud_ncts
); i
++) {
188 if (rate
== hdmi_aud_ncts
[i
].sample_rate
&&
189 adjusted_mode
->crtc_clock
== hdmi_aud_ncts
[i
].clock
) {
190 return hdmi_aud_ncts
[i
].n
;
196 static bool intel_eld_uptodate(struct drm_connector
*connector
,
197 i915_reg_t reg_eldv
, uint32_t bits_eldv
,
198 i915_reg_t reg_elda
, uint32_t bits_elda
,
201 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
202 uint8_t *eld
= connector
->eld
;
206 tmp
= I915_READ(reg_eldv
);
212 tmp
= I915_READ(reg_elda
);
214 I915_WRITE(reg_elda
, tmp
);
216 for (i
= 0; i
< drm_eld_size(eld
) / 4; i
++)
217 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
223 static void g4x_audio_codec_disable(struct intel_encoder
*encoder
)
225 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
228 DRM_DEBUG_KMS("Disable audio codec\n");
230 tmp
= I915_READ(G4X_AUD_VID_DID
);
231 if (tmp
== INTEL_AUDIO_DEVBLC
|| tmp
== INTEL_AUDIO_DEVCL
)
232 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
234 eldv
= G4X_ELDV_DEVCTG
;
237 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
239 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
242 static void g4x_audio_codec_enable(struct drm_connector
*connector
,
243 struct intel_encoder
*encoder
,
244 const struct drm_display_mode
*adjusted_mode
)
246 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
247 uint8_t *eld
= connector
->eld
;
252 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld
[2]);
254 tmp
= I915_READ(G4X_AUD_VID_DID
);
255 if (tmp
== INTEL_AUDIO_DEVBLC
|| tmp
== INTEL_AUDIO_DEVCL
)
256 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
258 eldv
= G4X_ELDV_DEVCTG
;
260 if (intel_eld_uptodate(connector
,
261 G4X_AUD_CNTL_ST
, eldv
,
262 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR_MASK
,
266 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
267 tmp
&= ~(eldv
| G4X_ELD_ADDR_MASK
);
268 len
= (tmp
>> 9) & 0x1f; /* ELD buffer size */
269 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
271 len
= min(drm_eld_size(eld
) / 4, len
);
272 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
273 for (i
= 0; i
< len
; i
++)
274 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
276 tmp
= I915_READ(G4X_AUD_CNTL_ST
);
278 I915_WRITE(G4X_AUD_CNTL_ST
, tmp
);
282 hsw_dp_audio_config_update(struct intel_crtc
*intel_crtc
, enum port port
,
283 const struct drm_display_mode
*adjusted_mode
)
285 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
286 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
287 int rate
= acomp
? acomp
->aud_sample_rate
[port
] : 0;
288 const struct dp_aud_n_m
*nm
= audio_config_dp_get_n_m(intel_crtc
, rate
);
289 enum pipe pipe
= intel_crtc
->pipe
;
293 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm
->m
, nm
->n
);
295 DRM_DEBUG_KMS("using automatic Maud, Naud\n");
297 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
298 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
299 tmp
&= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK
;
300 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
301 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
304 tmp
&= ~AUD_CONFIG_N_MASK
;
305 tmp
|= AUD_CONFIG_N(nm
->n
);
306 tmp
|= AUD_CONFIG_N_PROG_ENABLE
;
309 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
311 tmp
= I915_READ(HSW_AUD_M_CTS_ENABLE(pipe
));
312 tmp
&= ~AUD_CONFIG_M_MASK
;
313 tmp
&= ~AUD_M_CTS_M_VALUE_INDEX
;
314 tmp
&= ~AUD_M_CTS_M_PROG_ENABLE
;
318 tmp
|= AUD_M_CTS_M_VALUE_INDEX
;
319 tmp
|= AUD_M_CTS_M_PROG_ENABLE
;
322 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe
), tmp
);
326 hsw_hdmi_audio_config_update(struct intel_crtc
*intel_crtc
, enum port port
,
327 const struct drm_display_mode
*adjusted_mode
)
329 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
330 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
331 int rate
= acomp
? acomp
->aud_sample_rate
[port
] : 0;
332 enum pipe pipe
= intel_crtc
->pipe
;
336 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
337 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
338 tmp
&= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK
;
339 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
340 tmp
|= audio_config_hdmi_pixel_clock(adjusted_mode
);
342 n
= audio_config_hdmi_get_n(adjusted_mode
, rate
);
344 DRM_DEBUG_KMS("using N %d\n", n
);
346 tmp
&= ~AUD_CONFIG_N_MASK
;
347 tmp
|= AUD_CONFIG_N(n
);
348 tmp
|= AUD_CONFIG_N_PROG_ENABLE
;
350 DRM_DEBUG_KMS("using automatic N\n");
353 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
356 * Let's disable "Enable CTS or M Prog bit"
357 * and let HW calculate the value
359 tmp
= I915_READ(HSW_AUD_M_CTS_ENABLE(pipe
));
360 tmp
&= ~AUD_M_CTS_M_PROG_ENABLE
;
361 tmp
&= ~AUD_M_CTS_M_VALUE_INDEX
;
362 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe
), tmp
);
366 hsw_audio_config_update(struct intel_crtc
*intel_crtc
, enum port port
,
367 const struct drm_display_mode
*adjusted_mode
)
369 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
370 hsw_dp_audio_config_update(intel_crtc
, port
, adjusted_mode
);
372 hsw_hdmi_audio_config_update(intel_crtc
, port
, adjusted_mode
);
375 static void hsw_audio_codec_disable(struct intel_encoder
*encoder
)
377 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
378 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
379 enum pipe pipe
= intel_crtc
->pipe
;
382 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe
));
384 mutex_lock(&dev_priv
->av_mutex
);
386 /* Disable timestamps */
387 tmp
= I915_READ(HSW_AUD_CFG(pipe
));
388 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
389 tmp
|= AUD_CONFIG_N_PROG_ENABLE
;
390 tmp
&= ~AUD_CONFIG_UPPER_N_MASK
;
391 tmp
&= ~AUD_CONFIG_LOWER_N_MASK
;
392 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
393 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
394 I915_WRITE(HSW_AUD_CFG(pipe
), tmp
);
397 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
398 tmp
&= ~AUDIO_ELD_VALID(pipe
);
399 tmp
&= ~AUDIO_OUTPUT_ENABLE(pipe
);
400 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
402 mutex_unlock(&dev_priv
->av_mutex
);
405 static void hsw_audio_codec_enable(struct drm_connector
*connector
,
406 struct intel_encoder
*intel_encoder
,
407 const struct drm_display_mode
*adjusted_mode
)
409 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
410 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
411 enum pipe pipe
= intel_crtc
->pipe
;
412 enum port port
= intel_encoder
->port
;
413 const uint8_t *eld
= connector
->eld
;
417 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
418 pipe_name(pipe
), drm_eld_size(eld
));
420 mutex_lock(&dev_priv
->av_mutex
);
422 /* Enable audio presence detect, invalidate ELD */
423 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
424 tmp
|= AUDIO_OUTPUT_ENABLE(pipe
);
425 tmp
&= ~AUDIO_ELD_VALID(pipe
);
426 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
429 * FIXME: We're supposed to wait for vblank here, but we have vblanks
430 * disabled during the mode set. The proper fix would be to push the
431 * rest of the setup into a vblank work item, queued here, but the
432 * infrastructure is not there yet.
435 /* Reset ELD write address */
436 tmp
= I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe
));
437 tmp
&= ~IBX_ELD_ADDRESS_MASK
;
438 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe
), tmp
);
440 /* Up to 84 bytes of hw ELD buffer */
441 len
= min(drm_eld_size(eld
), 84);
442 for (i
= 0; i
< len
/ 4; i
++)
443 I915_WRITE(HSW_AUD_EDID_DATA(pipe
), *((uint32_t *)eld
+ i
));
446 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
447 tmp
|= AUDIO_ELD_VALID(pipe
);
448 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
450 /* Enable timestamps */
451 hsw_audio_config_update(intel_crtc
, port
, adjusted_mode
);
453 mutex_unlock(&dev_priv
->av_mutex
);
456 static void ilk_audio_codec_disable(struct intel_encoder
*intel_encoder
)
458 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
459 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
460 enum pipe pipe
= intel_crtc
->pipe
;
461 enum port port
= intel_encoder
->port
;
463 i915_reg_t aud_config
, aud_cntrl_st2
;
465 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
466 port_name(port
), pipe_name(pipe
));
468 if (WARN_ON(port
== PORT_A
))
471 if (HAS_PCH_IBX(dev_priv
)) {
472 aud_config
= IBX_AUD_CFG(pipe
);
473 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
474 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
475 aud_config
= VLV_AUD_CFG(pipe
);
476 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
478 aud_config
= CPT_AUD_CFG(pipe
);
479 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
482 /* Disable timestamps */
483 tmp
= I915_READ(aud_config
);
484 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
485 tmp
|= AUD_CONFIG_N_PROG_ENABLE
;
486 tmp
&= ~AUD_CONFIG_UPPER_N_MASK
;
487 tmp
&= ~AUD_CONFIG_LOWER_N_MASK
;
488 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
489 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
490 I915_WRITE(aud_config
, tmp
);
492 eldv
= IBX_ELD_VALID(port
);
495 tmp
= I915_READ(aud_cntrl_st2
);
497 I915_WRITE(aud_cntrl_st2
, tmp
);
500 static void ilk_audio_codec_enable(struct drm_connector
*connector
,
501 struct intel_encoder
*intel_encoder
,
502 const struct drm_display_mode
*adjusted_mode
)
504 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
505 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
506 enum pipe pipe
= intel_crtc
->pipe
;
507 enum port port
= intel_encoder
->port
;
508 uint8_t *eld
= connector
->eld
;
511 i915_reg_t hdmiw_hdmiedid
, aud_config
, aud_cntl_st
, aud_cntrl_st2
;
513 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
514 port_name(port
), pipe_name(pipe
), drm_eld_size(eld
));
516 if (WARN_ON(port
== PORT_A
))
520 * FIXME: We're supposed to wait for vblank here, but we have vblanks
521 * disabled during the mode set. The proper fix would be to push the
522 * rest of the setup into a vblank work item, queued here, but the
523 * infrastructure is not there yet.
526 if (HAS_PCH_IBX(dev_priv
)) {
527 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
528 aud_config
= IBX_AUD_CFG(pipe
);
529 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
530 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
531 } else if (IS_VALLEYVIEW(dev_priv
) ||
532 IS_CHERRYVIEW(dev_priv
)) {
533 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
534 aud_config
= VLV_AUD_CFG(pipe
);
535 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
536 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
538 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
539 aud_config
= CPT_AUD_CFG(pipe
);
540 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
541 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
544 eldv
= IBX_ELD_VALID(port
);
547 tmp
= I915_READ(aud_cntrl_st2
);
549 I915_WRITE(aud_cntrl_st2
, tmp
);
551 /* Reset ELD write address */
552 tmp
= I915_READ(aud_cntl_st
);
553 tmp
&= ~IBX_ELD_ADDRESS_MASK
;
554 I915_WRITE(aud_cntl_st
, tmp
);
556 /* Up to 84 bytes of hw ELD buffer */
557 len
= min(drm_eld_size(eld
), 84);
558 for (i
= 0; i
< len
/ 4; i
++)
559 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
562 tmp
= I915_READ(aud_cntrl_st2
);
564 I915_WRITE(aud_cntrl_st2
, tmp
);
566 /* Enable timestamps */
567 tmp
= I915_READ(aud_config
);
568 tmp
&= ~AUD_CONFIG_N_VALUE_INDEX
;
569 tmp
&= ~AUD_CONFIG_N_PROG_ENABLE
;
570 tmp
&= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK
;
571 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
572 tmp
|= AUD_CONFIG_N_VALUE_INDEX
;
574 tmp
|= audio_config_hdmi_pixel_clock(adjusted_mode
);
575 I915_WRITE(aud_config
, tmp
);
579 * intel_audio_codec_enable - Enable the audio codec for HD audio
580 * @intel_encoder: encoder on which to enable audio
581 * @crtc_state: pointer to the current crtc state.
582 * @conn_state: pointer to the current connector state.
584 * The enable sequences may only be performed after enabling the transcoder and
585 * port, and after completed link training.
587 void intel_audio_codec_enable(struct intel_encoder
*intel_encoder
,
588 const struct intel_crtc_state
*crtc_state
,
589 const struct drm_connector_state
*conn_state
)
591 struct drm_encoder
*encoder
= &intel_encoder
->base
;
592 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->base
.adjusted_mode
;
593 struct drm_connector
*connector
;
594 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
595 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
596 enum port port
= intel_encoder
->port
;
597 enum pipe pipe
= to_intel_crtc(crtc_state
->base
.crtc
)->pipe
;
599 connector
= conn_state
->connector
;
600 if (!connector
|| !connector
->eld
[0])
603 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
606 connector
->encoder
->base
.id
,
607 connector
->encoder
->name
);
610 connector
->eld
[5] &= ~(3 << 2);
611 if (intel_crtc_has_dp_encoder(crtc_state
))
612 connector
->eld
[5] |= (1 << 2);
614 connector
->eld
[6] = drm_av_sync_delay(connector
, adjusted_mode
) / 2;
616 if (dev_priv
->display
.audio_codec_enable
)
617 dev_priv
->display
.audio_codec_enable(connector
, intel_encoder
,
620 mutex_lock(&dev_priv
->av_mutex
);
621 intel_encoder
->audio_connector
= connector
;
623 /* referred in audio callbacks */
624 dev_priv
->av_enc_map
[pipe
] = intel_encoder
;
625 mutex_unlock(&dev_priv
->av_mutex
);
627 if (acomp
&& acomp
->audio_ops
&& acomp
->audio_ops
->pin_eld_notify
) {
628 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
629 if (intel_encoder
->type
!= INTEL_OUTPUT_DP_MST
)
631 acomp
->audio_ops
->pin_eld_notify(acomp
->audio_ops
->audio_ptr
,
632 (int) port
, (int) pipe
);
635 intel_lpe_audio_notify(dev_priv
, pipe
, port
, connector
->eld
,
636 crtc_state
->port_clock
,
637 intel_encoder
->type
== INTEL_OUTPUT_DP
);
641 * intel_audio_codec_disable - Disable the audio codec for HD audio
642 * @intel_encoder: encoder on which to disable audio
644 * The disable sequences must be performed before disabling the transcoder or
647 void intel_audio_codec_disable(struct intel_encoder
*intel_encoder
)
649 struct drm_encoder
*encoder
= &intel_encoder
->base
;
650 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
651 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
652 enum port port
= intel_encoder
->port
;
653 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
654 enum pipe pipe
= crtc
->pipe
;
656 if (dev_priv
->display
.audio_codec_disable
)
657 dev_priv
->display
.audio_codec_disable(intel_encoder
);
659 mutex_lock(&dev_priv
->av_mutex
);
660 intel_encoder
->audio_connector
= NULL
;
661 dev_priv
->av_enc_map
[pipe
] = NULL
;
662 mutex_unlock(&dev_priv
->av_mutex
);
664 if (acomp
&& acomp
->audio_ops
&& acomp
->audio_ops
->pin_eld_notify
) {
665 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
666 if (intel_encoder
->type
!= INTEL_OUTPUT_DP_MST
)
668 acomp
->audio_ops
->pin_eld_notify(acomp
->audio_ops
->audio_ptr
,
669 (int) port
, (int) pipe
);
672 intel_lpe_audio_notify(dev_priv
, pipe
, port
, NULL
, 0, false);
676 * intel_init_audio_hooks - Set up chip specific audio hooks
677 * @dev_priv: device private
679 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
)
681 if (IS_G4X(dev_priv
)) {
682 dev_priv
->display
.audio_codec_enable
= g4x_audio_codec_enable
;
683 dev_priv
->display
.audio_codec_disable
= g4x_audio_codec_disable
;
684 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
685 dev_priv
->display
.audio_codec_enable
= ilk_audio_codec_enable
;
686 dev_priv
->display
.audio_codec_disable
= ilk_audio_codec_disable
;
687 } else if (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8) {
688 dev_priv
->display
.audio_codec_enable
= hsw_audio_codec_enable
;
689 dev_priv
->display
.audio_codec_disable
= hsw_audio_codec_disable
;
690 } else if (HAS_PCH_SPLIT(dev_priv
)) {
691 dev_priv
->display
.audio_codec_enable
= ilk_audio_codec_enable
;
692 dev_priv
->display
.audio_codec_disable
= ilk_audio_codec_disable
;
696 static void i915_audio_component_get_power(struct device
*kdev
)
698 intel_display_power_get(kdev_to_i915(kdev
), POWER_DOMAIN_AUDIO
);
701 static void i915_audio_component_put_power(struct device
*kdev
)
703 intel_display_power_put(kdev_to_i915(kdev
), POWER_DOMAIN_AUDIO
);
706 static void i915_audio_component_codec_wake_override(struct device
*kdev
,
709 struct drm_i915_private
*dev_priv
= kdev_to_i915(kdev
);
712 if (!IS_GEN9_BC(dev_priv
))
715 i915_audio_component_get_power(kdev
);
718 * Enable/disable generating the codec wake signal, overriding the
719 * internal logic to generate the codec wake to controller.
721 tmp
= I915_READ(HSW_AUD_CHICKENBIT
);
722 tmp
&= ~SKL_AUD_CODEC_WAKE_SIGNAL
;
723 I915_WRITE(HSW_AUD_CHICKENBIT
, tmp
);
724 usleep_range(1000, 1500);
727 tmp
= I915_READ(HSW_AUD_CHICKENBIT
);
728 tmp
|= SKL_AUD_CODEC_WAKE_SIGNAL
;
729 I915_WRITE(HSW_AUD_CHICKENBIT
, tmp
);
730 usleep_range(1000, 1500);
733 i915_audio_component_put_power(kdev
);
736 /* Get CDCLK in kHz */
737 static int i915_audio_component_get_cdclk_freq(struct device
*kdev
)
739 struct drm_i915_private
*dev_priv
= kdev_to_i915(kdev
);
741 if (WARN_ON_ONCE(!HAS_DDI(dev_priv
)))
744 return dev_priv
->cdclk
.hw
.cdclk
;
748 * get the intel_encoder according to the parameter port and pipe
749 * intel_encoder is saved by the index of pipe
750 * MST & (pipe >= 0): return the av_enc_map[pipe],
751 * when port is matched
752 * MST & (pipe < 0): this is invalid
753 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
754 * will get the right intel_encoder with port matched
755 * Non-MST & (pipe < 0): get the right intel_encoder with port matched
757 static struct intel_encoder
*get_saved_enc(struct drm_i915_private
*dev_priv
,
760 struct intel_encoder
*encoder
;
762 if (WARN_ON(pipe
>= I915_MAX_PIPES
))
767 encoder
= dev_priv
->av_enc_map
[pipe
];
769 * when bootup, audio driver may not know it is
770 * MST or not. So it will poll all the port & pipe
773 if (encoder
!= NULL
&& encoder
->port
== port
&&
774 encoder
->type
== INTEL_OUTPUT_DP_MST
)
782 for_each_pipe(dev_priv
, pipe
) {
783 encoder
= dev_priv
->av_enc_map
[pipe
];
787 if (encoder
->type
== INTEL_OUTPUT_DP_MST
)
790 if (port
== encoder
->port
)
797 static int i915_audio_component_sync_audio_rate(struct device
*kdev
, int port
,
800 struct drm_i915_private
*dev_priv
= kdev_to_i915(kdev
);
801 struct intel_encoder
*intel_encoder
;
802 struct intel_crtc
*crtc
;
803 struct drm_display_mode
*adjusted_mode
;
804 struct i915_audio_component
*acomp
= dev_priv
->audio_component
;
807 if (!HAS_DDI(dev_priv
))
810 i915_audio_component_get_power(kdev
);
811 mutex_lock(&dev_priv
->av_mutex
);
813 /* 1. get the pipe */
814 intel_encoder
= get_saved_enc(dev_priv
, port
, pipe
);
815 if (!intel_encoder
|| !intel_encoder
->base
.crtc
) {
816 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port
));
821 /* pipe passed from the audio driver will be -1 for Non-MST case */
822 crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
825 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
827 /* port must be valid now, otherwise the pipe will be invalid */
828 acomp
->aud_sample_rate
[port
] = rate
;
830 hsw_audio_config_update(crtc
, port
, adjusted_mode
);
833 mutex_unlock(&dev_priv
->av_mutex
);
834 i915_audio_component_put_power(kdev
);
838 static int i915_audio_component_get_eld(struct device
*kdev
, int port
,
839 int pipe
, bool *enabled
,
840 unsigned char *buf
, int max_bytes
)
842 struct drm_i915_private
*dev_priv
= kdev_to_i915(kdev
);
843 struct intel_encoder
*intel_encoder
;
847 mutex_lock(&dev_priv
->av_mutex
);
849 intel_encoder
= get_saved_enc(dev_priv
, port
, pipe
);
850 if (!intel_encoder
) {
851 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port
));
852 mutex_unlock(&dev_priv
->av_mutex
);
857 *enabled
= intel_encoder
->audio_connector
!= NULL
;
859 eld
= intel_encoder
->audio_connector
->eld
;
860 ret
= drm_eld_size(eld
);
861 memcpy(buf
, eld
, min(max_bytes
, ret
));
864 mutex_unlock(&dev_priv
->av_mutex
);
868 static const struct i915_audio_component_ops i915_audio_component_ops
= {
869 .owner
= THIS_MODULE
,
870 .get_power
= i915_audio_component_get_power
,
871 .put_power
= i915_audio_component_put_power
,
872 .codec_wake_override
= i915_audio_component_codec_wake_override
,
873 .get_cdclk_freq
= i915_audio_component_get_cdclk_freq
,
874 .sync_audio_rate
= i915_audio_component_sync_audio_rate
,
875 .get_eld
= i915_audio_component_get_eld
,
878 static int i915_audio_component_bind(struct device
*i915_kdev
,
879 struct device
*hda_kdev
, void *data
)
881 struct i915_audio_component
*acomp
= data
;
882 struct drm_i915_private
*dev_priv
= kdev_to_i915(i915_kdev
);
885 if (WARN_ON(acomp
->ops
|| acomp
->dev
))
888 drm_modeset_lock_all(&dev_priv
->drm
);
889 acomp
->ops
= &i915_audio_component_ops
;
890 acomp
->dev
= i915_kdev
;
891 BUILD_BUG_ON(MAX_PORTS
!= I915_MAX_PORTS
);
892 for (i
= 0; i
< ARRAY_SIZE(acomp
->aud_sample_rate
); i
++)
893 acomp
->aud_sample_rate
[i
] = 0;
894 dev_priv
->audio_component
= acomp
;
895 drm_modeset_unlock_all(&dev_priv
->drm
);
900 static void i915_audio_component_unbind(struct device
*i915_kdev
,
901 struct device
*hda_kdev
, void *data
)
903 struct i915_audio_component
*acomp
= data
;
904 struct drm_i915_private
*dev_priv
= kdev_to_i915(i915_kdev
);
906 drm_modeset_lock_all(&dev_priv
->drm
);
909 dev_priv
->audio_component
= NULL
;
910 drm_modeset_unlock_all(&dev_priv
->drm
);
913 static const struct component_ops i915_audio_component_bind_ops
= {
914 .bind
= i915_audio_component_bind
,
915 .unbind
= i915_audio_component_unbind
,
919 * i915_audio_component_init - initialize and register the audio component
920 * @dev_priv: i915 device instance
922 * This will register with the component framework a child component which
923 * will bind dynamically to the snd_hda_intel driver's corresponding master
924 * component when the latter is registered. During binding the child
925 * initializes an instance of struct i915_audio_component which it receives
926 * from the master. The master can then start to use the interface defined by
927 * this struct. Each side can break the binding at any point by deregistering
928 * its own component after which each side's component unbind callback is
931 * We ignore any error during registration and continue with reduced
932 * functionality (i.e. without HDMI audio).
934 void i915_audio_component_init(struct drm_i915_private
*dev_priv
)
938 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
941 ret
= component_add(dev_priv
->drm
.dev
, &i915_audio_component_bind_ops
);
943 DRM_ERROR("failed to add audio component (%d)\n", ret
);
944 /* continue with reduced functionality */
948 dev_priv
->audio_component_registered
= true;
952 * i915_audio_component_cleanup - deregister the audio component
953 * @dev_priv: i915 device instance
955 * Deregisters the audio component, breaking any existing binding to the
956 * corresponding snd_hda_intel driver's master component.
958 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
)
960 if (!dev_priv
->audio_component_registered
)
963 component_del(dev_priv
->drm
.dev
, &i915_audio_component_bind_ops
);
964 dev_priv
->audio_component_registered
= false;
968 * intel_audio_init() - Initialize the audio driver either using
969 * component framework or using lpe audio bridge
970 * @dev_priv: the i915 drm device private data
973 void intel_audio_init(struct drm_i915_private
*dev_priv
)
975 if (intel_lpe_audio_init(dev_priv
) < 0)
976 i915_audio_component_init(dev_priv
);
980 * intel_audio_deinit() - deinitialize the audio driver
981 * @dev_priv: the i915 drm device private data
984 void intel_audio_deinit(struct drm_i915_private
*dev_priv
)
986 if ((dev_priv
)->lpe_audio
.platdev
!= NULL
)
987 intel_lpe_audio_teardown(dev_priv
);
989 i915_audio_component_cleanup(dev_priv
);