drivers/gpu/drm/i915/intel_bios.h

   1 /*
   2  * Copyright © 2006 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #ifndef _I830_BIOS_H_
  29 #define _I830_BIOS_H_
  30
  31 #include "drmP.h"
  32
  33 struct vbt_header {
  34         u8 signature[20];               /**< Always starts with 'VBT$' */
  35         u16 version;                    /**< decimal */
  36         u16 header_size;                /**< in bytes */
  37         u16 vbt_size;                   /**< in bytes */
  38         u8 vbt_checksum;
  39         u8 reserved0;
  40         u32 bdb_offset;                 /**< from beginning of VBT */
  41         u32 aim_offset[4];              /**< from beginning of VBT */
  42 } __attribute__((packed));
  43
  44 struct bdb_header {
  45         u8 signature[16];               /**< Always 'BIOS_DATA_BLOCK' */
  46         u16 version;                    /**< decimal */
  47         u16 header_size;                /**< in bytes */
  48         u16 bdb_size;                   /**< in bytes */
  49 };
  50
  51 /* strictly speaking, this is a "skip" block, but it has interesting info */
  52 struct vbios_data {
  53         u8 type; /* 0 == desktop, 1 == mobile */
  54         u8 relstage;
  55         u8 chipset;
  56         u8 lvds_present:1;
  57         u8 tv_present:1;
  58         u8 rsvd2:6; /* finish byte */
  59         u8 rsvd3[4];
  60         u8 signon[155];
  61         u8 copyright[61];
  62         u16 code_segment;
  63         u8 dos_boot_mode;
  64         u8 bandwidth_percent;
  65         u8 rsvd4; /* popup memory size */
  66         u8 resize_pci_bios;
  67         u8 rsvd5; /* is crt already on ddc2 */
  68 } __attribute__((packed));
  69
  70 /*
  71  * There are several types of BIOS data blocks (BDBs), each block has
  72  * an ID and size in the first 3 bytes (ID in first, size in next 2).
  73  * Known types are listed below.
  74  */
  75 #define BDB_GENERAL_FEATURES      1
  76 #define BDB_GENERAL_DEFINITIONS   2
  77 #define BDB_OLD_TOGGLE_LIST       3
  78 #define BDB_MODE_SUPPORT_LIST     4
  79 #define BDB_GENERIC_MODE_TABLE    5
  80 #define BDB_EXT_MMIO_REGS         6
  81 #define BDB_SWF_IO                7
  82 #define BDB_SWF_MMIO              8
  83 #define BDB_DOT_CLOCK_TABLE       9
  84 #define BDB_MODE_REMOVAL_TABLE   10
  85 #define BDB_CHILD_DEVICE_TABLE   11
  86 #define BDB_DRIVER_FEATURES      12
  87 #define BDB_DRIVER_PERSISTENCE   13
  88 #define BDB_EXT_TABLE_PTRS       14
  89 #define BDB_DOT_CLOCK_OVERRIDE   15
  90 #define BDB_DISPLAY_SELECT       16
  91 /* 17 rsvd */
  92 #define BDB_DRIVER_ROTATION      18
  93 #define BDB_DISPLAY_REMOVE       19
  94 #define BDB_OEM_CUSTOM           20
  95 #define BDB_EFP_LIST             21 /* workarounds for VGA hsync/vsync */
  96 #define BDB_SDVO_LVDS_OPTIONS    22
  97 #define BDB_SDVO_PANEL_DTDS      23
  98 #define BDB_SDVO_LVDS_PNP_IDS    24
  99 #define BDB_SDVO_LVDS_POWER_SEQ  25
 100 #define BDB_TV_OPTIONS           26
 101 #define BDB_LVDS_OPTIONS         40
 102 #define BDB_LVDS_LFP_DATA_PTRS   41
 103 #define BDB_LVDS_LFP_DATA        42
 104 #define BDB_LVDS_BACKLIGHT       43
 105 #define BDB_LVDS_POWER           44
 106 #define BDB_SKIP                254 /* VBIOS private block, ignore */
 107
 108 struct bdb_general_features {
 109         /* bits 1 */
 110         u8 panel_fitting:2;
 111         u8 flexaim:1;
 112         u8 msg_enable:1;
 113         u8 clear_screen:3;
 114         u8 color_flip:1;
 115
 116         /* bits 2 */
 117         u8 download_ext_vbt:1;
 118         u8 enable_ssc:1;
 119         u8 ssc_freq:1;
 120         u8 enable_lfp_on_override:1;
 121         u8 disable_ssc_ddt:1;
 122         u8 rsvd8:3; /* finish byte */
 123
 124         /* bits 3 */
 125         u8 disable_smooth_vision:1;
 126         u8 single_dvi:1;
 127         u8 rsvd9:6; /* finish byte */
 128
 129         /* bits 4 */
 130         u8 legacy_monitor_detect;
 131
 132         /* bits 5 */
 133         u8 int_crt_support:1;
 134         u8 int_tv_support:1;
 135         u8 rsvd11:6; /* finish byte */
 136 } __attribute__((packed));
 137
 138 struct bdb_general_definitions {
 139         /* DDC GPIO */
 140         u8 crt_ddc_gmbus_pin;
 141
 142         /* DPMS bits */
 143         u8 dpms_acpi:1;
 144         u8 skip_boot_crt_detect:1;
 145         u8 dpms_aim:1;
 146         u8 rsvd1:5; /* finish byte */
 147
 148         /* boot device bits */
 149         u8 boot_display[2];
 150         u8 child_dev_size;
 151
 152         /* device info */
 153         u8 tv_or_lvds_info[33];
 154         u8 dev1[33];
 155         u8 dev2[33];
 156         u8 dev3[33];
 157         u8 dev4[33];
 158         /* may be another device block here on some platforms */
 159 };
 160
 161 struct bdb_lvds_options {
 162         u8 panel_type;
 163         u8 rsvd1;
 164         /* LVDS capabilities, stored in a dword */
 165         u8 pfit_mode:2;
 166         u8 pfit_text_mode_enhanced:1;
 167         u8 pfit_gfx_mode_enhanced:1;
 168         u8 pfit_ratio_auto:1;
 169         u8 pixel_dither:1;
 170         u8 lvds_edid:1;
 171         u8 rsvd2:1;
 172         u8 rsvd4;
 173 } __attribute__((packed));
 174
 175 /* LFP pointer table contains entries to the struct below */
 176 struct bdb_lvds_lfp_data_ptr {
 177         u16 fp_timing_offset; /* offsets are from start of bdb */
 178         u8 fp_table_size;
 179         u16 dvo_timing_offset;
 180         u8 dvo_table_size;
 181         u16 panel_pnp_id_offset;
 182         u8 pnp_table_size;
 183 } __attribute__((packed));
 184
 185 struct bdb_lvds_lfp_data_ptrs {
 186         u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
 187         struct bdb_lvds_lfp_data_ptr ptr[16];
 188 } __attribute__((packed));
 189
 190 /* LFP data has 3 blocks per entry */
 191 struct lvds_fp_timing {
 192         u16 x_res;
 193         u16 y_res;
 194         u32 lvds_reg;
 195         u32 lvds_reg_val;
 196         u32 pp_on_reg;
 197         u32 pp_on_reg_val;
 198         u32 pp_off_reg;
 199         u32 pp_off_reg_val;
 200         u32 pp_cycle_reg;
 201         u32 pp_cycle_reg_val;
 202         u32 pfit_reg;
 203         u32 pfit_reg_val;
 204         u16 terminator;
 205 } __attribute__((packed));
 206
 207 struct lvds_dvo_timing {
 208         u16 clock;              /**< In 10khz */
 209         u8 hactive_lo;
 210         u8 hblank_lo;
 211         u8 hblank_hi:4;
 212         u8 hactive_hi:4;
 213         u8 vactive_lo;
 214         u8 vblank_lo;
 215         u8 vblank_hi:4;
 216         u8 vactive_hi:4;
 217         u8 hsync_off_lo;
 218         u8 hsync_pulse_width;
 219         u8 vsync_pulse_width:4;
 220         u8 vsync_off:4;
 221         u8 rsvd0:6;
 222         u8 hsync_off_hi:2;
 223         u8 h_image;
 224         u8 v_image;
 225         u8 max_hv;
 226         u8 h_border;
 227         u8 v_border;
 228         u8 rsvd1:3;
 229         u8 digital:2;
 230         u8 vsync_positive:1;
 231         u8 hsync_positive:1;
 232         u8 rsvd2:1;
 233 } __attribute__((packed));
 234
 235 struct lvds_pnp_id {
 236         u16 mfg_name;
 237         u16 product_code;
 238         u32 serial;
 239         u8 mfg_week;
 240         u8 mfg_year;
 241 } __attribute__((packed));
 242
 243 struct bdb_lvds_lfp_data_entry {
 244         struct lvds_fp_timing fp_timing;
 245         struct lvds_dvo_timing dvo_timing;
 246         struct lvds_pnp_id pnp_id;
 247 } __attribute__((packed));
 248
 249 struct bdb_lvds_lfp_data {
 250         struct bdb_lvds_lfp_data_entry data[16];
 251 } __attribute__((packed));
 252
 253 struct aimdb_header {
 254         char signature[16];
 255         char oem_device[20];
 256         u16 aimdb_version;
 257         u16 aimdb_header_size;
 258         u16 aimdb_size;
 259 } __attribute__((packed));
 260
 261 struct aimdb_block {
 262         u8 aimdb_id;
 263         u16 aimdb_size;
 264 } __attribute__((packed));
 265
 266 struct vch_panel_data {
 267         u16 fp_timing_offset;
 268         u8 fp_timing_size;
 269         u16 dvo_timing_offset;
 270         u8 dvo_timing_size;
 271         u16 text_fitting_offset;
 272         u8 text_fitting_size;
 273         u16 graphics_fitting_offset;
 274         u8 graphics_fitting_size;
 275 } __attribute__((packed));
 276
 277 struct vch_bdb_22 {
 278         struct aimdb_block aimdb_block;
 279         struct vch_panel_data panels[16];
 280 } __attribute__((packed));
 281
 282 bool intel_init_bios(struct drm_device *dev);
 283
 284 /*
 285  * Driver<->VBIOS interaction occurs through scratch bits in
 286  * GR18 & SWF*.
 287  */
 288
 289 /* GR18 bits are set on display switch and hotkey events */
 290 #define GR18_DRIVER_SWITCH_EN   (1<<7) /* 0: VBIOS control, 1: driver control */
 291 #define GR18_HOTKEY_MASK        0x78 /* See also SWF4 15:0 */
 292 #define   GR18_HK_NONE          (0x0<<3)
 293 #define   GR18_HK_LFP_STRETCH   (0x1<<3)
 294 #define   GR18_HK_TOGGLE_DISP   (0x2<<3)
 295 #define   GR18_HK_DISP_SWITCH   (0x4<<3) /* see SWF14 15:0 for what to enable */
 296 #define   GR18_HK_POPUP_DISABLED (0x6<<3)
 297 #define   GR18_HK_POPUP_ENABLED (0x7<<3)
 298 #define   GR18_HK_PFIT          (0x8<<3)
 299 #define   GR18_HK_APM_CHANGE    (0xa<<3)
 300 #define   GR18_HK_MULTIPLE      (0xc<<3)
 301 #define GR18_USER_INT_EN        (1<<2)
 302 #define GR18_A0000_FLUSH_EN     (1<<1)
 303 #define GR18_SMM_EN             (1<<0)
 304
 305 /* Set by driver, cleared by VBIOS */
 306 #define SWF00_YRES_SHIFT        16
 307 #define SWF00_XRES_SHIFT        0
 308 #define SWF00_RES_MASK          0xffff
 309
 310 /* Set by VBIOS at boot time and driver at runtime */
 311 #define SWF01_TV2_FORMAT_SHIFT  8
 312 #define SWF01_TV1_FORMAT_SHIFT  0
 313 #define SWF01_TV_FORMAT_MASK    0xffff
 314
 315 #define SWF10_VBIOS_BLC_I2C_EN  (1<<29)
 316 #define SWF10_GTT_OVERRIDE_EN   (1<<28)
 317 #define SWF10_LFP_DPMS_OVR      (1<<27) /* override DPMS on display switch */
 318 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
 319 #define   SWF10_OLD_TOGGLE      0x0
 320 #define   SWF10_TOGGLE_LIST_1   0x1
 321 #define   SWF10_TOGGLE_LIST_2   0x2
 322 #define   SWF10_TOGGLE_LIST_3   0x3
 323 #define   SWF10_TOGGLE_LIST_4   0x4
 324 #define SWF10_PANNING_EN        (1<<23)
 325 #define SWF10_DRIVER_LOADED     (1<<22)
 326 #define SWF10_EXTENDED_DESKTOP  (1<<21)
 327 #define SWF10_EXCLUSIVE_MODE    (1<<20)
 328 #define SWF10_OVERLAY_EN        (1<<19)
 329 #define SWF10_PLANEB_HOLDOFF    (1<<18)
 330 #define SWF10_PLANEA_HOLDOFF    (1<<17)
 331 #define SWF10_VGA_HOLDOFF       (1<<16)
 332 #define SWF10_ACTIVE_DISP_MASK  0xffff
 333 #define   SWF10_PIPEB_LFP2      (1<<15)
 334 #define   SWF10_PIPEB_EFP2      (1<<14)
 335 #define   SWF10_PIPEB_TV2       (1<<13)
 336 #define   SWF10_PIPEB_CRT2      (1<<12)
 337 #define   SWF10_PIPEB_LFP       (1<<11)
 338 #define   SWF10_PIPEB_EFP       (1<<10)
 339 #define   SWF10_PIPEB_TV        (1<<9)
 340 #define   SWF10_PIPEB_CRT       (1<<8)
 341 #define   SWF10_PIPEA_LFP2      (1<<7)
 342 #define   SWF10_PIPEA_EFP2      (1<<6)
 343 #define   SWF10_PIPEA_TV2       (1<<5)
 344 #define   SWF10_PIPEA_CRT2      (1<<4)
 345 #define   SWF10_PIPEA_LFP       (1<<3)
 346 #define   SWF10_PIPEA_EFP       (1<<2)
 347 #define   SWF10_PIPEA_TV        (1<<1)
 348 #define   SWF10_PIPEA_CRT       (1<<0)
 349
 350 #define SWF11_MEMORY_SIZE_SHIFT 16
 351 #define SWF11_SV_TEST_EN        (1<<15)
 352 #define SWF11_IS_AGP            (1<<14)
 353 #define SWF11_DISPLAY_HOLDOFF   (1<<13)
 354 #define SWF11_DPMS_REDUCED      (1<<12)
 355 #define SWF11_IS_VBE_MODE       (1<<11)
 356 #define SWF11_PIPEB_ACCESS      (1<<10) /* 0 here means pipe a */
 357 #define SWF11_DPMS_MASK         0x07
 358 #define   SWF11_DPMS_OFF        (1<<2)
 359 #define   SWF11_DPMS_SUSPEND    (1<<1)
 360 #define   SWF11_DPMS_STANDBY    (1<<0)
 361 #define   SWF11_DPMS_ON         0
 362
 363 #define SWF14_GFX_PFIT_EN       (1<<31)
 364 #define SWF14_TEXT_PFIT_EN      (1<<30)
 365 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
 366 #define SWF14_POPUP_EN          (1<<28)
 367 #define SWF14_DISPLAY_HOLDOFF   (1<<27)
 368 #define SWF14_DISP_DETECT_EN    (1<<26)
 369 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
 370 #define SWF14_DRIVER_STATUS     (1<<24)
 371 #define SWF14_OS_TYPE_WIN9X     (1<<23)
 372 #define SWF14_OS_TYPE_WINNT     (1<<22)
 373 /* 21:19 rsvd */
 374 #define SWF14_PM_TYPE_MASK      0x00070000
 375 #define   SWF14_PM_ACPI_VIDEO   (0x4 << 16)
 376 #define   SWF14_PM_ACPI         (0x3 << 16)
 377 #define   SWF14_PM_APM_12       (0x2 << 16)
 378 #define   SWF14_PM_APM_11       (0x1 << 16)
 379 #define SWF14_HK_REQUEST_MASK   0x0000ffff /* see GR18 6:3 for event type */
 380           /* if GR18 indicates a display switch */
 381 #define   SWF14_DS_PIPEB_LFP2_EN (1<<15)
 382 #define   SWF14_DS_PIPEB_EFP2_EN (1<<14)
 383 #define   SWF14_DS_PIPEB_TV2_EN  (1<<13)
 384 #define   SWF14_DS_PIPEB_CRT2_EN (1<<12)
 385 #define   SWF14_DS_PIPEB_LFP_EN  (1<<11)
 386 #define   SWF14_DS_PIPEB_EFP_EN  (1<<10)
 387 #define   SWF14_DS_PIPEB_TV_EN   (1<<9)
 388 #define   SWF14_DS_PIPEB_CRT_EN  (1<<8)
 389 #define   SWF14_DS_PIPEA_LFP2_EN (1<<7)
 390 #define   SWF14_DS_PIPEA_EFP2_EN (1<<6)
 391 #define   SWF14_DS_PIPEA_TV2_EN  (1<<5)
 392 #define   SWF14_DS_PIPEA_CRT2_EN (1<<4)
 393 #define   SWF14_DS_PIPEA_LFP_EN  (1<<3)
 394 #define   SWF14_DS_PIPEA_EFP_EN  (1<<2)
 395 #define   SWF14_DS_PIPEA_TV_EN   (1<<1)
 396 #define   SWF14_DS_PIPEA_CRT_EN  (1<<0)
 397           /* if GR18 indicates a panel fitting request */
 398 #define   SWF14_PFIT_EN         (1<<0) /* 0 means disable */
 399           /* if GR18 indicates an APM change request */
 400 #define   SWF14_APM_HIBERNATE   0x4
 401 #define   SWF14_APM_SUSPEND     0x3
 402 #define   SWF14_APM_STANDBY     0x1
 403 #define   SWF14_APM_RESTORE     0x0
 404
 405 #endif /* _I830_BIOS_H_ */