drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: CDCLK / RAWCLK
  28  *
  29  * The display engine uses several different clocks to do its work. There
  30  * are two main clocks involved that aren't directly related to the actual
  31  * pixel clock or any symbol/bit clock of the actual output port. These
  32  * are the core display clock (CDCLK) and RAWCLK.
  33  *
  34  * CDCLK clocks most of the display pipe logic, and thus its frequency
  35  * must be high enough to support the rate at which pixels are flowing
  36  * through the pipes. Downscaling must also be accounted as that increases
  37  * the effective pixel rate.
  38  *
  39  * On several platforms the CDCLK frequency can be changed dynamically
  40  * to minimize power consumption for a given display configuration.
  41  * Typically changes to the CDCLK frequency require all the display pipes
  42  * to be shut down while the frequency is being changed.
  43  *
  44  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  45  * DMC will not change the active CDCLK frequency however, so that part
  46  * will still be performed by the driver directly.
  47  *
  48  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  49  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  50  * really need to know about RAWCLK is its frequency so that various
  51  * dividers can be programmed correctly.
  52  */
  53
  54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  55                                    struct intel_cdclk_state *cdclk_state)
  56 {
  57         cdclk_state->cdclk = 133333;
  58 }
  59
  60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  61                                    struct intel_cdclk_state *cdclk_state)
  62 {
  63         cdclk_state->cdclk = 200000;
  64 }
  65
  66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  67                                    struct intel_cdclk_state *cdclk_state)
  68 {
  69         cdclk_state->cdclk = 266667;
  70 }
  71
  72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  73                                    struct intel_cdclk_state *cdclk_state)
  74 {
  75         cdclk_state->cdclk = 333333;
  76 }
  77
  78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  79                                    struct intel_cdclk_state *cdclk_state)
  80 {
  81         cdclk_state->cdclk = 400000;
  82 }
  83
  84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  85                                    struct intel_cdclk_state *cdclk_state)
  86 {
  87         cdclk_state->cdclk = 450000;
  88 }
  89
  90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  91                            struct intel_cdclk_state *cdclk_state)
  92 {
  93         struct pci_dev *pdev = dev_priv->drm.pdev;
  94         u16 hpllcc = 0;
  95
  96         /*
  97          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  98          * encoding is different :(
  99          * FIXME is this the right way to detect 852GM/852GMV?
 100          */
 101         if (pdev->revision == 0x1) {
 102                 cdclk_state->cdclk = 133333;
 103                 return;
 104         }
 105
 106         pci_bus_read_config_word(pdev->bus,
 107                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 108
 109         /* Assume that the hardware is in the high speed state.  This
 110          * should be the default.
 111          */
 112         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 113         case GC_CLOCK_133_200:
 114         case GC_CLOCK_133_200_2:
 115         case GC_CLOCK_100_200:
 116                 cdclk_state->cdclk = 200000;
 117                 break;
 118         case GC_CLOCK_166_250:
 119                 cdclk_state->cdclk = 250000;
 120                 break;
 121         case GC_CLOCK_100_133:
 122                 cdclk_state->cdclk = 133333;
 123                 break;
 124         case GC_CLOCK_133_266:
 125         case GC_CLOCK_133_266_2:
 126         case GC_CLOCK_166_266:
 127                 cdclk_state->cdclk = 266667;
 128                 break;
 129         }
 130 }
 131
 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 133                              struct intel_cdclk_state *cdclk_state)
 134 {
 135         struct pci_dev *pdev = dev_priv->drm.pdev;
 136         u16 gcfgc = 0;
 137
 138         pci_read_config_word(pdev, GCFGC, &gcfgc);
 139
 140         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 141                 cdclk_state->cdclk = 133333;
 142                 return;
 143         }
 144
 145         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 146         case GC_DISPLAY_CLOCK_333_320_MHZ:
 147                 cdclk_state->cdclk = 333333;
 148                 break;
 149         default:
 150         case GC_DISPLAY_CLOCK_190_200_MHZ:
 151                 cdclk_state->cdclk = 190000;
 152                 break;
 153         }
 154 }
 155
 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 157                              struct intel_cdclk_state *cdclk_state)
 158 {
 159         struct pci_dev *pdev = dev_priv->drm.pdev;
 160         u16 gcfgc = 0;
 161
 162         pci_read_config_word(pdev, GCFGC, &gcfgc);
 163
 164         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 165                 cdclk_state->cdclk = 133333;
 166                 return;
 167         }
 168
 169         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 170         case GC_DISPLAY_CLOCK_333_320_MHZ:
 171                 cdclk_state->cdclk = 320000;
 172                 break;
 173         default:
 174         case GC_DISPLAY_CLOCK_190_200_MHZ:
 175                 cdclk_state->cdclk = 200000;
 176                 break;
 177         }
 178 }
 179
 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         static const unsigned int blb_vco[8] = {
 183                 [0] = 3200000,
 184                 [1] = 4000000,
 185                 [2] = 5333333,
 186                 [3] = 4800000,
 187                 [4] = 6400000,
 188         };
 189         static const unsigned int pnv_vco[8] = {
 190                 [0] = 3200000,
 191                 [1] = 4000000,
 192                 [2] = 5333333,
 193                 [3] = 4800000,
 194                 [4] = 2666667,
 195         };
 196         static const unsigned int cl_vco[8] = {
 197                 [0] = 3200000,
 198                 [1] = 4000000,
 199                 [2] = 5333333,
 200                 [3] = 6400000,
 201                 [4] = 3333333,
 202                 [5] = 3566667,
 203                 [6] = 4266667,
 204         };
 205         static const unsigned int elk_vco[8] = {
 206                 [0] = 3200000,
 207                 [1] = 4000000,
 208                 [2] = 5333333,
 209                 [3] = 4800000,
 210         };
 211         static const unsigned int ctg_vco[8] = {
 212                 [0] = 3200000,
 213                 [1] = 4000000,
 214                 [2] = 5333333,
 215                 [3] = 6400000,
 216                 [4] = 2666667,
 217                 [5] = 4266667,
 218         };
 219         const unsigned int *vco_table;
 220         unsigned int vco;
 221         uint8_t tmp = 0;
 222
 223         /* FIXME other chipsets? */
 224         if (IS_GM45(dev_priv))
 225                 vco_table = ctg_vco;
 226         else if (IS_G45(dev_priv))
 227                 vco_table = elk_vco;
 228         else if (IS_I965GM(dev_priv))
 229                 vco_table = cl_vco;
 230         else if (IS_PINEVIEW(dev_priv))
 231                 vco_table = pnv_vco;
 232         else if (IS_G33(dev_priv))
 233                 vco_table = blb_vco;
 234         else
 235                 return 0;
 236
 237         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 238
 239         vco = vco_table[tmp & 0x7];
 240         if (vco == 0)
 241                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 242         else
 243                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 244
 245         return vco;
 246 }
 247
 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 249                           struct intel_cdclk_state *cdclk_state)
 250 {
 251         struct pci_dev *pdev = dev_priv->drm.pdev;
 252         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
 253         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
 254         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
 255         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
 256         const uint8_t *div_table;
 257         unsigned int cdclk_sel;
 258         uint16_t tmp = 0;
 259
 260         cdclk_state->vco = intel_hpll_vco(dev_priv);
 261
 262         pci_read_config_word(pdev, GCFGC, &tmp);
 263
 264         cdclk_sel = (tmp >> 4) & 0x7;
 265
 266         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 267                 goto fail;
 268
 269         switch (cdclk_state->vco) {
 270         case 3200000:
 271                 div_table = div_3200;
 272                 break;
 273         case 4000000:
 274                 div_table = div_4000;
 275                 break;
 276         case 4800000:
 277                 div_table = div_4800;
 278                 break;
 279         case 5333333:
 280                 div_table = div_5333;
 281                 break;
 282         default:
 283                 goto fail;
 284         }
 285
 286         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 287                                                div_table[cdclk_sel]);
 288         return;
 289
 290 fail:
 291         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 292                   cdclk_state->vco, tmp);
 293         cdclk_state->cdclk = 190476;
 294 }
 295
 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 297                           struct intel_cdclk_state *cdclk_state)
 298 {
 299         struct pci_dev *pdev = dev_priv->drm.pdev;
 300         u16 gcfgc = 0;
 301
 302         pci_read_config_word(pdev, GCFGC, &gcfgc);
 303
 304         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 305         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 306                 cdclk_state->cdclk = 266667;
 307                 break;
 308         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 309                 cdclk_state->cdclk = 333333;
 310                 break;
 311         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 312                 cdclk_state->cdclk = 444444;
 313                 break;
 314         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 315                 cdclk_state->cdclk = 200000;
 316                 break;
 317         default:
 318                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 319         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 320                 cdclk_state->cdclk = 133333;
 321                 break;
 322         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 323                 cdclk_state->cdclk = 166667;
 324                 break;
 325         }
 326 }
 327
 328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 329                              struct intel_cdclk_state *cdclk_state)
 330 {
 331         struct pci_dev *pdev = dev_priv->drm.pdev;
 332         static const uint8_t div_3200[] = { 16, 10,  8 };
 333         static const uint8_t div_4000[] = { 20, 12, 10 };
 334         static const uint8_t div_5333[] = { 24, 16, 14 };
 335         const uint8_t *div_table;
 336         unsigned int cdclk_sel;
 337         uint16_t tmp = 0;
 338
 339         cdclk_state->vco = intel_hpll_vco(dev_priv);
 340
 341         pci_read_config_word(pdev, GCFGC, &tmp);
 342
 343         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 344
 345         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 346                 goto fail;
 347
 348         switch (cdclk_state->vco) {
 349         case 3200000:
 350                 div_table = div_3200;
 351                 break;
 352         case 4000000:
 353                 div_table = div_4000;
 354                 break;
 355         case 5333333:
 356                 div_table = div_5333;
 357                 break;
 358         default:
 359                 goto fail;
 360         }
 361
 362         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 363                                                div_table[cdclk_sel]);
 364         return;
 365
 366 fail:
 367         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 368                   cdclk_state->vco, tmp);
 369         cdclk_state->cdclk = 200000;
 370 }
 371
 372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 373                            struct intel_cdclk_state *cdclk_state)
 374 {
 375         struct pci_dev *pdev = dev_priv->drm.pdev;
 376         unsigned int cdclk_sel;
 377         uint16_t tmp = 0;
 378
 379         cdclk_state->vco = intel_hpll_vco(dev_priv);
 380
 381         pci_read_config_word(pdev, GCFGC, &tmp);
 382
 383         cdclk_sel = (tmp >> 12) & 0x1;
 384
 385         switch (cdclk_state->vco) {
 386         case 2666667:
 387         case 4000000:
 388         case 5333333:
 389                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 390                 break;
 391         case 3200000:
 392                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 393                 break;
 394         default:
 395                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 396                           cdclk_state->vco, tmp);
 397                 cdclk_state->cdclk = 222222;
 398                 break;
 399         }
 400 }
 401
 402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 403                           struct intel_cdclk_state *cdclk_state)
 404 {
 405         uint32_t lcpll = I915_READ(LCPLL_CTL);
 406         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 407
 408         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 409                 cdclk_state->cdclk = 800000;
 410         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 411                 cdclk_state->cdclk = 450000;
 412         else if (freq == LCPLL_CLK_FREQ_450)
 413                 cdclk_state->cdclk = 450000;
 414         else if (IS_HSW_ULT(dev_priv))
 415                 cdclk_state->cdclk = 337500;
 416         else
 417                 cdclk_state->cdclk = 540000;
 418 }
 419
 420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv,
 421                           int max_pixclk)
 422 {
 423         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 424                 333333 : 320000;
 425         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
 426
 427         /*
 428          * We seem to get an unstable or solid color picture at 200MHz.
 429          * Not sure what's wrong. For now use 200MHz only when all pipes
 430          * are off.
 431          */
 432         if (!IS_CHERRYVIEW(dev_priv) &&
 433             max_pixclk > freq_320*limit/100)
 434                 return 400000;
 435         else if (max_pixclk > 266667*limit/100)
 436                 return freq_320;
 437         else if (max_pixclk > 0)
 438                 return 266667;
 439         else
 440                 return 200000;
 441 }
 442
 443 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 444                           struct intel_cdclk_state *cdclk_state)
 445 {
 446         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 447         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 448                                                CCK_DISPLAY_CLOCK_CONTROL,
 449                                                cdclk_state->vco);
 450 }
 451
 452 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 453 {
 454         unsigned int credits, default_credits;
 455
 456         if (IS_CHERRYVIEW(dev_priv))
 457                 default_credits = PFI_CREDIT(12);
 458         else
 459                 default_credits = PFI_CREDIT(8);
 460
 461         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 462                 /* CHV suggested value is 31 or 63 */
 463                 if (IS_CHERRYVIEW(dev_priv))
 464                         credits = PFI_CREDIT_63;
 465                 else
 466                         credits = PFI_CREDIT(15);
 467         } else {
 468                 credits = default_credits;
 469         }
 470
 471         /*
 472          * WA - write default credits before re-programming
 473          * FIXME: should we also set the resend bit here?
 474          */
 475         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 476                    default_credits);
 477
 478         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 479                    credits | PFI_CREDIT_RESEND);
 480
 481         /*
 482          * FIXME is this guaranteed to clear
 483          * immediately or should we poll for it?
 484          */
 485         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 486 }
 487
 488 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 489                           const struct intel_cdclk_state *cdclk_state)
 490 {
 491         int cdclk = cdclk_state->cdclk;
 492         u32 val, cmd;
 493
 494         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 495                 cmd = 2;
 496         else if (cdclk == 266667)
 497                 cmd = 1;
 498         else
 499                 cmd = 0;
 500
 501         mutex_lock(&dev_priv->rps.hw_lock);
 502         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 503         val &= ~DSPFREQGUAR_MASK;
 504         val |= (cmd << DSPFREQGUAR_SHIFT);
 505         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 506         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 507                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 508                      50)) {
 509                 DRM_ERROR("timed out waiting for CDclk change\n");
 510         }
 511         mutex_unlock(&dev_priv->rps.hw_lock);
 512
 513         mutex_lock(&dev_priv->sb_lock);
 514
 515         if (cdclk == 400000) {
 516                 u32 divider;
 517
 518                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 519                                             cdclk) - 1;
 520
 521                 /* adjust cdclk divider */
 522                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 523                 val &= ~CCK_FREQUENCY_VALUES;
 524                 val |= divider;
 525                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 526
 527                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 528                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 529                              50))
 530                         DRM_ERROR("timed out waiting for CDclk change\n");
 531         }
 532
 533         /* adjust self-refresh exit latency value */
 534         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 535         val &= ~0x7f;
 536
 537         /*
 538          * For high bandwidth configs, we set a higher latency in the bunit
 539          * so that the core display fetch happens in time to avoid underruns.
 540          */
 541         if (cdclk == 400000)
 542                 val |= 4500 / 250; /* 4.5 usec */
 543         else
 544                 val |= 3000 / 250; /* 3.0 usec */
 545         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 546
 547         mutex_unlock(&dev_priv->sb_lock);
 548
 549         intel_update_cdclk(dev_priv);
 550
 551         vlv_program_pfi_credits(dev_priv);
 552 }
 553
 554 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 555                           const struct intel_cdclk_state *cdclk_state)
 556 {
 557         int cdclk = cdclk_state->cdclk;
 558         u32 val, cmd;
 559
 560         switch (cdclk) {
 561         case 333333:
 562         case 320000:
 563         case 266667:
 564         case 200000:
 565                 break;
 566         default:
 567                 MISSING_CASE(cdclk);
 568                 return;
 569         }
 570
 571         /*
 572          * Specs are full of misinformation, but testing on actual
 573          * hardware has shown that we just need to write the desired
 574          * CCK divider into the Punit register.
 575          */
 576         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 577
 578         mutex_lock(&dev_priv->rps.hw_lock);
 579         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 580         val &= ~DSPFREQGUAR_MASK_CHV;
 581         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 582         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 583         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 584                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 585                      50)) {
 586                 DRM_ERROR("timed out waiting for CDclk change\n");
 587         }
 588         mutex_unlock(&dev_priv->rps.hw_lock);
 589
 590         intel_update_cdclk(dev_priv);
 591
 592         vlv_program_pfi_credits(dev_priv);
 593 }
 594
 595 static int bdw_calc_cdclk(int max_pixclk)
 596 {
 597         if (max_pixclk > 540000)
 598                 return 675000;
 599         else if (max_pixclk > 450000)
 600                 return 540000;
 601         else if (max_pixclk > 337500)
 602                 return 450000;
 603         else
 604                 return 337500;
 605 }
 606
 607 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 608                           struct intel_cdclk_state *cdclk_state)
 609 {
 610         uint32_t lcpll = I915_READ(LCPLL_CTL);
 611         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 612
 613         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 614                 cdclk_state->cdclk = 800000;
 615         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 616                 cdclk_state->cdclk = 450000;
 617         else if (freq == LCPLL_CLK_FREQ_450)
 618                 cdclk_state->cdclk = 450000;
 619         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 620                 cdclk_state->cdclk = 540000;
 621         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 622                 cdclk_state->cdclk = 337500;
 623         else
 624                 cdclk_state->cdclk = 675000;
 625 }
 626
 627 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 628                           const struct intel_cdclk_state *cdclk_state)
 629 {
 630         int cdclk = cdclk_state->cdclk;
 631         uint32_t val, data;
 632         int ret;
 633
 634         if (WARN((I915_READ(LCPLL_CTL) &
 635                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 636                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 637                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 638                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 639                  "trying to change cdclk frequency with cdclk not enabled\n"))
 640                 return;
 641
 642         mutex_lock(&dev_priv->rps.hw_lock);
 643         ret = sandybridge_pcode_write(dev_priv,
 644                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 645         mutex_unlock(&dev_priv->rps.hw_lock);
 646         if (ret) {
 647                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 648                 return;
 649         }
 650
 651         val = I915_READ(LCPLL_CTL);
 652         val |= LCPLL_CD_SOURCE_FCLK;
 653         I915_WRITE(LCPLL_CTL, val);
 654
 655         if (wait_for_us(I915_READ(LCPLL_CTL) &
 656                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
 657                 DRM_ERROR("Switching to FCLK failed\n");
 658
 659         val = I915_READ(LCPLL_CTL);
 660         val &= ~LCPLL_CLK_FREQ_MASK;
 661
 662         switch (cdclk) {
 663         case 450000:
 664                 val |= LCPLL_CLK_FREQ_450;
 665                 data = 0;
 666                 break;
 667         case 540000:
 668                 val |= LCPLL_CLK_FREQ_54O_BDW;
 669                 data = 1;
 670                 break;
 671         case 337500:
 672                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 673                 data = 2;
 674                 break;
 675         case 675000:
 676                 val |= LCPLL_CLK_FREQ_675_BDW;
 677                 data = 3;
 678                 break;
 679         default:
 680                 WARN(1, "invalid cdclk frequency\n");
 681                 return;
 682         }
 683
 684         I915_WRITE(LCPLL_CTL, val);
 685
 686         val = I915_READ(LCPLL_CTL);
 687         val &= ~LCPLL_CD_SOURCE_FCLK;
 688         I915_WRITE(LCPLL_CTL, val);
 689
 690         if (wait_for_us((I915_READ(LCPLL_CTL) &
 691                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 692                 DRM_ERROR("Switching back to LCPLL failed\n");
 693
 694         mutex_lock(&dev_priv->rps.hw_lock);
 695         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
 696         mutex_unlock(&dev_priv->rps.hw_lock);
 697
 698         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 699
 700         intel_update_cdclk(dev_priv);
 701
 702         WARN(cdclk != dev_priv->cdclk.hw.cdclk,
 703              "cdclk requested %d kHz but got %d kHz\n",
 704              cdclk, dev_priv->cdclk.hw.cdclk);
 705 }
 706
 707 static int skl_calc_cdclk(int max_pixclk, int vco)
 708 {
 709         if (vco == 8640000) {
 710                 if (max_pixclk > 540000)
 711                         return 617143;
 712                 else if (max_pixclk > 432000)
 713                         return 540000;
 714                 else if (max_pixclk > 308571)
 715                         return 432000;
 716                 else
 717                         return 308571;
 718         } else {
 719                 if (max_pixclk > 540000)
 720                         return 675000;
 721                 else if (max_pixclk > 450000)
 722                         return 540000;
 723                 else if (max_pixclk > 337500)
 724                         return 450000;
 725                 else
 726                         return 337500;
 727         }
 728 }
 729
 730 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 731                              struct intel_cdclk_state *cdclk_state)
 732 {
 733         u32 val;
 734
 735         cdclk_state->ref = 24000;
 736         cdclk_state->vco = 0;
 737
 738         val = I915_READ(LCPLL1_CTL);
 739         if ((val & LCPLL_PLL_ENABLE) == 0)
 740                 return;
 741
 742         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 743                 return;
 744
 745         val = I915_READ(DPLL_CTRL1);
 746
 747         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 748                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 749                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 750                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 751                 return;
 752
 753         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 754         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 755         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 756         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 757         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 758                 cdclk_state->vco = 8100000;
 759                 break;
 760         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 761         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 762                 cdclk_state->vco = 8640000;
 763                 break;
 764         default:
 765                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 766                 break;
 767         }
 768 }
 769
 770 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 771                           struct intel_cdclk_state *cdclk_state)
 772 {
 773         u32 cdctl;
 774
 775         skl_dpll0_update(dev_priv, cdclk_state);
 776
 777         cdclk_state->cdclk = cdclk_state->ref;
 778
 779         if (cdclk_state->vco == 0)
 780                 return;
 781
 782         cdctl = I915_READ(CDCLK_CTL);
 783
 784         if (cdclk_state->vco == 8640000) {
 785                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 786                 case CDCLK_FREQ_450_432:
 787                         cdclk_state->cdclk = 432000;
 788                         break;
 789                 case CDCLK_FREQ_337_308:
 790                         cdclk_state->cdclk = 308571;
 791                         break;
 792                 case CDCLK_FREQ_540:
 793                         cdclk_state->cdclk = 540000;
 794                         break;
 795                 case CDCLK_FREQ_675_617:
 796                         cdclk_state->cdclk = 617143;
 797                         break;
 798                 default:
 799                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 800                         break;
 801                 }
 802         } else {
 803                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 804                 case CDCLK_FREQ_450_432:
 805                         cdclk_state->cdclk = 450000;
 806                         break;
 807                 case CDCLK_FREQ_337_308:
 808                         cdclk_state->cdclk = 337500;
 809                         break;
 810                 case CDCLK_FREQ_540:
 811                         cdclk_state->cdclk = 540000;
 812                         break;
 813                 case CDCLK_FREQ_675_617:
 814                         cdclk_state->cdclk = 675000;
 815                         break;
 816                 default:
 817                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 818                         break;
 819                 }
 820         }
 821 }
 822
 823 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 824 static int skl_cdclk_decimal(int cdclk)
 825 {
 826         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 827 }
 828
 829 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 830                                         int vco)
 831 {
 832         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 833
 834         dev_priv->skl_preferred_vco_freq = vco;
 835
 836         if (changed)
 837                 intel_update_max_cdclk(dev_priv);
 838 }
 839
 840 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 841 {
 842         int min_cdclk = skl_calc_cdclk(0, vco);
 843         u32 val;
 844
 845         WARN_ON(vco != 8100000 && vco != 8640000);
 846
 847         /* select the minimum CDCLK before enabling DPLL 0 */
 848         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
 849         I915_WRITE(CDCLK_CTL, val);
 850         POSTING_READ(CDCLK_CTL);
 851
 852         /*
 853          * We always enable DPLL0 with the lowest link rate possible, but still
 854          * taking into account the VCO required to operate the eDP panel at the
 855          * desired frequency. The usual DP link rates operate with a VCO of
 856          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 857          * The modeset code is responsible for the selection of the exact link
 858          * rate later on, with the constraint of choosing a frequency that
 859          * works with vco.
 860          */
 861         val = I915_READ(DPLL_CTRL1);
 862
 863         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 864                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 865         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 866         if (vco == 8640000)
 867                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 868                                             SKL_DPLL0);
 869         else
 870                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 871                                             SKL_DPLL0);
 872
 873         I915_WRITE(DPLL_CTRL1, val);
 874         POSTING_READ(DPLL_CTRL1);
 875
 876         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 877
 878         if (intel_wait_for_register(dev_priv,
 879                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 880                                     5))
 881                 DRM_ERROR("DPLL0 not locked\n");
 882
 883         dev_priv->cdclk.hw.vco = vco;
 884
 885         /* We'll want to keep using the current vco from now on. */
 886         skl_set_preferred_cdclk_vco(dev_priv, vco);
 887 }
 888
 889 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 890 {
 891         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 892         if (intel_wait_for_register(dev_priv,
 893                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 894                                    1))
 895                 DRM_ERROR("Couldn't disable DPLL0\n");
 896
 897         dev_priv->cdclk.hw.vco = 0;
 898 }
 899
 900 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 901                           const struct intel_cdclk_state *cdclk_state)
 902 {
 903         int cdclk = cdclk_state->cdclk;
 904         int vco = cdclk_state->vco;
 905         u32 freq_select, pcu_ack;
 906         int ret;
 907
 908         WARN_ON((cdclk == 24000) != (vco == 0));
 909
 910         mutex_lock(&dev_priv->rps.hw_lock);
 911         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 912                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
 913                                 SKL_CDCLK_READY_FOR_CHANGE,
 914                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
 915         mutex_unlock(&dev_priv->rps.hw_lock);
 916         if (ret) {
 917                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
 918                           ret);
 919                 return;
 920         }
 921
 922         /* set CDCLK_CTL */
 923         switch (cdclk) {
 924         case 450000:
 925         case 432000:
 926                 freq_select = CDCLK_FREQ_450_432;
 927                 pcu_ack = 1;
 928                 break;
 929         case 540000:
 930                 freq_select = CDCLK_FREQ_540;
 931                 pcu_ack = 2;
 932                 break;
 933         case 308571:
 934         case 337500:
 935         default:
 936                 freq_select = CDCLK_FREQ_337_308;
 937                 pcu_ack = 0;
 938                 break;
 939         case 617143:
 940         case 675000:
 941                 freq_select = CDCLK_FREQ_675_617;
 942                 pcu_ack = 3;
 943                 break;
 944         }
 945
 946         if (dev_priv->cdclk.hw.vco != 0 &&
 947             dev_priv->cdclk.hw.vco != vco)
 948                 skl_dpll0_disable(dev_priv);
 949
 950         if (dev_priv->cdclk.hw.vco != vco)
 951                 skl_dpll0_enable(dev_priv, vco);
 952
 953         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
 954         POSTING_READ(CDCLK_CTL);
 955
 956         /* inform PCU of the change */
 957         mutex_lock(&dev_priv->rps.hw_lock);
 958         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
 959         mutex_unlock(&dev_priv->rps.hw_lock);
 960
 961         intel_update_cdclk(dev_priv);
 962 }
 963
 964 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 965 {
 966         uint32_t cdctl, expected;
 967
 968         /*
 969          * check if the pre-os initialized the display
 970          * There is SWF18 scratchpad register defined which is set by the
 971          * pre-os which can be used by the OS drivers to check the status
 972          */
 973         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
 974                 goto sanitize;
 975
 976         intel_update_cdclk(dev_priv);
 977         /* Is PLL enabled and locked ? */
 978         if (dev_priv->cdclk.hw.vco == 0 ||
 979             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
 980                 goto sanitize;
 981
 982         /* DPLL okay; verify the cdclock
 983          *
 984          * Noticed in some instances that the freq selection is correct but
 985          * decimal part is programmed wrong from BIOS where pre-os does not
 986          * enable display. Verify the same as well.
 987          */
 988         cdctl = I915_READ(CDCLK_CTL);
 989         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
 990                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
 991         if (cdctl == expected)
 992                 /* All well; nothing to sanitize */
 993                 return;
 994
 995 sanitize:
 996         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
 997
 998         /* force cdclk programming */
 999         dev_priv->cdclk.hw.cdclk = 0;
1000         /* force full PLL disable + enable */
1001         dev_priv->cdclk.hw.vco = -1;
1002 }
1003
1004 /**
1005  * skl_init_cdclk - Initialize CDCLK on SKL
1006  * @dev_priv: i915 device
1007  *
1008  * Initialize CDCLK for SKL and derivatives. This is generally
1009  * done only during the display core initialization sequence,
1010  * after which the DMC will take care of turning CDCLK off/on
1011  * as needed.
1012  */
1013 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1014 {
1015         struct intel_cdclk_state cdclk_state;
1016
1017         skl_sanitize_cdclk(dev_priv);
1018
1019         if (dev_priv->cdclk.hw.cdclk != 0 &&
1020             dev_priv->cdclk.hw.vco != 0) {
1021                 /*
1022                  * Use the current vco as our initial
1023                  * guess as to what the preferred vco is.
1024                  */
1025                 if (dev_priv->skl_preferred_vco_freq == 0)
1026                         skl_set_preferred_cdclk_vco(dev_priv,
1027                                                     dev_priv->cdclk.hw.vco);
1028                 return;
1029         }
1030
1031         cdclk_state = dev_priv->cdclk.hw;
1032
1033         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1034         if (cdclk_state.vco == 0)
1035                 cdclk_state.vco = 8100000;
1036         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1037
1038         skl_set_cdclk(dev_priv, &cdclk_state);
1039 }
1040
1041 /**
1042  * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1043  * @dev_priv: i915 device
1044  *
1045  * Uninitialize CDCLK for SKL and derivatives. This is done only
1046  * during the display core uninitialization sequence.
1047  */
1048 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1049 {
1050         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1051
1052         cdclk_state.cdclk = cdclk_state.ref;
1053         cdclk_state.vco = 0;
1054
1055         skl_set_cdclk(dev_priv, &cdclk_state);
1056 }
1057
1058 static int bxt_calc_cdclk(int max_pixclk)
1059 {
1060         if (max_pixclk > 576000)
1061                 return 624000;
1062         else if (max_pixclk > 384000)
1063                 return 576000;
1064         else if (max_pixclk > 288000)
1065                 return 384000;
1066         else if (max_pixclk > 144000)
1067                 return 288000;
1068         else
1069                 return 144000;
1070 }
1071
1072 static int glk_calc_cdclk(int max_pixclk)
1073 {
1074         if (max_pixclk > 2 * 158400)
1075                 return 316800;
1076         else if (max_pixclk > 2 * 79200)
1077                 return 158400;
1078         else
1079                 return 79200;
1080 }
1081
1082 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1083 {
1084         int ratio;
1085
1086         if (cdclk == dev_priv->cdclk.hw.ref)
1087                 return 0;
1088
1089         switch (cdclk) {
1090         default:
1091                 MISSING_CASE(cdclk);
1092         case 144000:
1093         case 288000:
1094         case 384000:
1095         case 576000:
1096                 ratio = 60;
1097                 break;
1098         case 624000:
1099                 ratio = 65;
1100                 break;
1101         }
1102
1103         return dev_priv->cdclk.hw.ref * ratio;
1104 }
1105
1106 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1107 {
1108         int ratio;
1109
1110         if (cdclk == dev_priv->cdclk.hw.ref)
1111                 return 0;
1112
1113         switch (cdclk) {
1114         default:
1115                 MISSING_CASE(cdclk);
1116         case  79200:
1117         case 158400:
1118         case 316800:
1119                 ratio = 33;
1120                 break;
1121         }
1122
1123         return dev_priv->cdclk.hw.ref * ratio;
1124 }
1125
1126 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1127                               struct intel_cdclk_state *cdclk_state)
1128 {
1129         u32 val;
1130
1131         cdclk_state->ref = 19200;
1132         cdclk_state->vco = 0;
1133
1134         val = I915_READ(BXT_DE_PLL_ENABLE);
1135         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1136                 return;
1137
1138         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1139                 return;
1140
1141         val = I915_READ(BXT_DE_PLL_CTL);
1142         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1143 }
1144
1145 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1146                           struct intel_cdclk_state *cdclk_state)
1147 {
1148         u32 divider;
1149         int div;
1150
1151         bxt_de_pll_update(dev_priv, cdclk_state);
1152
1153         cdclk_state->cdclk = cdclk_state->ref;
1154
1155         if (cdclk_state->vco == 0)
1156                 return;
1157
1158         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1159
1160         switch (divider) {
1161         case BXT_CDCLK_CD2X_DIV_SEL_1:
1162                 div = 2;
1163                 break;
1164         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1165                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1166                 div = 3;
1167                 break;
1168         case BXT_CDCLK_CD2X_DIV_SEL_2:
1169                 div = 4;
1170                 break;
1171         case BXT_CDCLK_CD2X_DIV_SEL_4:
1172                 div = 8;
1173                 break;
1174         default:
1175                 MISSING_CASE(divider);
1176                 return;
1177         }
1178
1179         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1180 }
1181
1182 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1183 {
1184         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1185
1186         /* Timeout 200us */
1187         if (intel_wait_for_register(dev_priv,
1188                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1189                                     1))
1190                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1191
1192         dev_priv->cdclk.hw.vco = 0;
1193 }
1194
1195 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1196 {
1197         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1198         u32 val;
1199
1200         val = I915_READ(BXT_DE_PLL_CTL);
1201         val &= ~BXT_DE_PLL_RATIO_MASK;
1202         val |= BXT_DE_PLL_RATIO(ratio);
1203         I915_WRITE(BXT_DE_PLL_CTL, val);
1204
1205         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1206
1207         /* Timeout 200us */
1208         if (intel_wait_for_register(dev_priv,
1209                                     BXT_DE_PLL_ENABLE,
1210                                     BXT_DE_PLL_LOCK,
1211                                     BXT_DE_PLL_LOCK,
1212                                     1))
1213                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1214
1215         dev_priv->cdclk.hw.vco = vco;
1216 }
1217
1218 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1219                           const struct intel_cdclk_state *cdclk_state)
1220 {
1221         int cdclk = cdclk_state->cdclk;
1222         int vco = cdclk_state->vco;
1223         u32 val, divider;
1224         int ret;
1225
1226         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1227         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1228         case 8:
1229                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1230                 break;
1231         case 4:
1232                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1233                 break;
1234         case 3:
1235                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1236                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1237                 break;
1238         case 2:
1239                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1240                 break;
1241         default:
1242                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1243                 WARN_ON(vco != 0);
1244
1245                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1246                 break;
1247         }
1248
1249         /* Inform power controller of upcoming frequency change */
1250         mutex_lock(&dev_priv->rps.hw_lock);
1251         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1252                                       0x80000000);
1253         mutex_unlock(&dev_priv->rps.hw_lock);
1254
1255         if (ret) {
1256                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1257                           ret, cdclk);
1258                 return;
1259         }
1260
1261         if (dev_priv->cdclk.hw.vco != 0 &&
1262             dev_priv->cdclk.hw.vco != vco)
1263                 bxt_de_pll_disable(dev_priv);
1264
1265         if (dev_priv->cdclk.hw.vco != vco)
1266                 bxt_de_pll_enable(dev_priv, vco);
1267
1268         val = divider | skl_cdclk_decimal(cdclk);
1269         /*
1270          * FIXME if only the cd2x divider needs changing, it could be done
1271          * without shutting off the pipe (if only one pipe is active).
1272          */
1273         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1274         /*
1275          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1276          * enable otherwise.
1277          */
1278         if (cdclk >= 500000)
1279                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1280         I915_WRITE(CDCLK_CTL, val);
1281
1282         mutex_lock(&dev_priv->rps.hw_lock);
1283         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
1284                                       DIV_ROUND_UP(cdclk, 25000));
1285         mutex_unlock(&dev_priv->rps.hw_lock);
1286
1287         if (ret) {
1288                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1289                           ret, cdclk);
1290                 return;
1291         }
1292
1293         intel_update_cdclk(dev_priv);
1294 }
1295
1296 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1297 {
1298         u32 cdctl, expected;
1299
1300         intel_update_cdclk(dev_priv);
1301
1302         if (dev_priv->cdclk.hw.vco == 0 ||
1303             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1304                 goto sanitize;
1305
1306         /* DPLL okay; verify the cdclock
1307          *
1308          * Some BIOS versions leave an incorrect decimal frequency value and
1309          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1310          * so sanitize this register.
1311          */
1312         cdctl = I915_READ(CDCLK_CTL);
1313         /*
1314          * Let's ignore the pipe field, since BIOS could have configured the
1315          * dividers both synching to an active pipe, or asynchronously
1316          * (PIPE_NONE).
1317          */
1318         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1319
1320         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1321                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1322         /*
1323          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1324          * enable otherwise.
1325          */
1326         if (dev_priv->cdclk.hw.cdclk >= 500000)
1327                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1328
1329         if (cdctl == expected)
1330                 /* All well; nothing to sanitize */
1331                 return;
1332
1333 sanitize:
1334         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1335
1336         /* force cdclk programming */
1337         dev_priv->cdclk.hw.cdclk = 0;
1338
1339         /* force full PLL disable + enable */
1340         dev_priv->cdclk.hw.vco = -1;
1341 }
1342
1343 /**
1344  * bxt_init_cdclk - Initialize CDCLK on BXT
1345  * @dev_priv: i915 device
1346  *
1347  * Initialize CDCLK for BXT and derivatives. This is generally
1348  * done only during the display core initialization sequence,
1349  * after which the DMC will take care of turning CDCLK off/on
1350  * as needed.
1351  */
1352 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1353 {
1354         struct intel_cdclk_state cdclk_state;
1355
1356         bxt_sanitize_cdclk(dev_priv);
1357
1358         if (dev_priv->cdclk.hw.cdclk != 0 &&
1359             dev_priv->cdclk.hw.vco != 0)
1360                 return;
1361
1362         cdclk_state = dev_priv->cdclk.hw;
1363
1364         /*
1365          * FIXME:
1366          * - The initial CDCLK needs to be read from VBT.
1367          *   Need to make this change after VBT has changes for BXT.
1368          */
1369         if (IS_GEMINILAKE(dev_priv)) {
1370                 cdclk_state.cdclk = glk_calc_cdclk(0);
1371                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1372         } else {
1373                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1374                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1375         }
1376
1377         bxt_set_cdclk(dev_priv, &cdclk_state);
1378 }
1379
1380 /**
1381  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1382  * @dev_priv: i915 device
1383  *
1384  * Uninitialize CDCLK for BXT and derivatives. This is done only
1385  * during the display core uninitialization sequence.
1386  */
1387 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1388 {
1389         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1390
1391         cdclk_state.cdclk = cdclk_state.ref;
1392         cdclk_state.vco = 0;
1393
1394         bxt_set_cdclk(dev_priv, &cdclk_state);
1395 }
1396
1397 /**
1398  * intel_cdclk_state_compare - Determine if two CDCLK states differ
1399  * @a: first CDCLK state
1400  * @b: second CDCLK state
1401  *
1402  * Returns:
1403  * True if the CDCLK states are identical, false if they differ.
1404  */
1405 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1406                                const struct intel_cdclk_state *b)
1407 {
1408         return memcmp(a, b, sizeof(*a)) == 0;
1409 }
1410
1411 /**
1412  * intel_set_cdclk - Push the CDCLK state to the hardware
1413  * @dev_priv: i915 device
1414  * @cdclk_state: new CDCLK state
1415  *
1416  * Program the hardware based on the passed in CDCLK state,
1417  * if necessary.
1418  */
1419 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1420                      const struct intel_cdclk_state *cdclk_state)
1421 {
1422         if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
1423                 return;
1424
1425         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1426                 return;
1427
1428         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
1429                          cdclk_state->cdclk, cdclk_state->vco,
1430                          cdclk_state->ref);
1431
1432         dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1433 }
1434
1435 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
1436                                           int pixel_rate)
1437 {
1438         struct drm_i915_private *dev_priv =
1439                 to_i915(crtc_state->base.crtc->dev);
1440
1441         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1442         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1443                 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
1444
1445         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1446          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1447          * there may be audio corruption or screen corruption." This cdclk
1448          * restriction for GLK is 316.8 MHz and since GLK can output two
1449          * pixels per clock, the pixel rate becomes 2 * 316.8 MHz.
1450          */
1451         if (intel_crtc_has_dp_encoder(crtc_state) &&
1452             crtc_state->has_audio &&
1453             crtc_state->port_clock >= 540000 &&
1454             crtc_state->lane_count == 4) {
1455                 if (IS_GEMINILAKE(dev_priv))
1456                         pixel_rate = max(2 * 316800, pixel_rate);
1457                 else
1458                         pixel_rate = max(432000, pixel_rate);
1459         }
1460
1461         /* According to BSpec, "The CD clock frequency must be at least twice
1462          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1463          * The check for GLK has to be adjusted as the platform can output
1464          * two pixels per clock.
1465          */
1466         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
1467                 if (IS_GEMINILAKE(dev_priv))
1468                         pixel_rate = max(2 * 2 * 96000, pixel_rate);
1469                 else
1470                         pixel_rate = max(2 * 96000, pixel_rate);
1471         }
1472
1473         return pixel_rate;
1474 }
1475
1476 /* compute the max rate for new configuration */
1477 static int intel_max_pixel_rate(struct drm_atomic_state *state)
1478 {
1479         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1480         struct drm_i915_private *dev_priv = to_i915(state->dev);
1481         struct drm_crtc *crtc;
1482         struct drm_crtc_state *cstate;
1483         struct intel_crtc_state *crtc_state;
1484         unsigned int max_pixel_rate = 0, i;
1485         enum pipe pipe;
1486
1487         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
1488                sizeof(intel_state->min_pixclk));
1489
1490         for_each_new_crtc_in_state(state, crtc, cstate, i) {
1491                 int pixel_rate;
1492
1493                 crtc_state = to_intel_crtc_state(cstate);
1494                 if (!crtc_state->base.enable) {
1495                         intel_state->min_pixclk[i] = 0;
1496                         continue;
1497                 }
1498
1499                 pixel_rate = crtc_state->pixel_rate;
1500
1501                 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
1502                         pixel_rate =
1503                                 bdw_adjust_min_pipe_pixel_rate(crtc_state,
1504                                                                pixel_rate);
1505
1506                 intel_state->min_pixclk[i] = pixel_rate;
1507         }
1508
1509         for_each_pipe(dev_priv, pipe)
1510                 max_pixel_rate = max(intel_state->min_pixclk[pipe],
1511                                      max_pixel_rate);
1512
1513         return max_pixel_rate;
1514 }
1515
1516 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1517 {
1518         struct drm_i915_private *dev_priv = to_i915(state->dev);
1519         int max_pixclk = intel_max_pixel_rate(state);
1520         struct intel_atomic_state *intel_state =
1521                 to_intel_atomic_state(state);
1522         int cdclk;
1523
1524         cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
1525
1526         if (cdclk > dev_priv->max_cdclk_freq) {
1527                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1528                               cdclk, dev_priv->max_cdclk_freq);
1529                 return -EINVAL;
1530         }
1531
1532         intel_state->cdclk.logical.cdclk = cdclk;
1533
1534         if (!intel_state->active_crtcs) {
1535                 cdclk = vlv_calc_cdclk(dev_priv, 0);
1536
1537                 intel_state->cdclk.actual.cdclk = cdclk;
1538         } else {
1539                 intel_state->cdclk.actual =
1540                         intel_state->cdclk.logical;
1541         }
1542
1543         return 0;
1544 }
1545
1546 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1547 {
1548         struct drm_i915_private *dev_priv = to_i915(state->dev);
1549         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1550         int max_pixclk = intel_max_pixel_rate(state);
1551         int cdclk;
1552
1553         /*
1554          * FIXME should also account for plane ratio
1555          * once 64bpp pixel formats are supported.
1556          */
1557         cdclk = bdw_calc_cdclk(max_pixclk);
1558
1559         if (cdclk > dev_priv->max_cdclk_freq) {
1560                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1561                               cdclk, dev_priv->max_cdclk_freq);
1562                 return -EINVAL;
1563         }
1564
1565         intel_state->cdclk.logical.cdclk = cdclk;
1566
1567         if (!intel_state->active_crtcs) {
1568                 cdclk = bdw_calc_cdclk(0);
1569
1570                 intel_state->cdclk.actual.cdclk = cdclk;
1571         } else {
1572                 intel_state->cdclk.actual =
1573                         intel_state->cdclk.logical;
1574         }
1575
1576         return 0;
1577 }
1578
1579 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1580 {
1581         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1582         struct drm_i915_private *dev_priv = to_i915(state->dev);
1583         const int max_pixclk = intel_max_pixel_rate(state);
1584         int cdclk, vco;
1585
1586         vco = intel_state->cdclk.logical.vco;
1587         if (!vco)
1588                 vco = dev_priv->skl_preferred_vco_freq;
1589
1590         /*
1591          * FIXME should also account for plane ratio
1592          * once 64bpp pixel formats are supported.
1593          */
1594         cdclk = skl_calc_cdclk(max_pixclk, vco);
1595
1596         if (cdclk > dev_priv->max_cdclk_freq) {
1597                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1598                               cdclk, dev_priv->max_cdclk_freq);
1599                 return -EINVAL;
1600         }
1601
1602         intel_state->cdclk.logical.vco = vco;
1603         intel_state->cdclk.logical.cdclk = cdclk;
1604
1605         if (!intel_state->active_crtcs) {
1606                 cdclk = skl_calc_cdclk(0, vco);
1607
1608                 intel_state->cdclk.actual.vco = vco;
1609                 intel_state->cdclk.actual.cdclk = cdclk;
1610         } else {
1611                 intel_state->cdclk.actual =
1612                         intel_state->cdclk.logical;
1613         }
1614
1615         return 0;
1616 }
1617
1618 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1619 {
1620         struct drm_i915_private *dev_priv = to_i915(state->dev);
1621         int max_pixclk = intel_max_pixel_rate(state);
1622         struct intel_atomic_state *intel_state =
1623                 to_intel_atomic_state(state);
1624         int cdclk, vco;
1625
1626         if (IS_GEMINILAKE(dev_priv)) {
1627                 cdclk = glk_calc_cdclk(max_pixclk);
1628                 vco = glk_de_pll_vco(dev_priv, cdclk);
1629         } else {
1630                 cdclk = bxt_calc_cdclk(max_pixclk);
1631                 vco = bxt_de_pll_vco(dev_priv, cdclk);
1632         }
1633
1634         if (cdclk > dev_priv->max_cdclk_freq) {
1635                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1636                               cdclk, dev_priv->max_cdclk_freq);
1637                 return -EINVAL;
1638         }
1639
1640         intel_state->cdclk.logical.vco = vco;
1641         intel_state->cdclk.logical.cdclk = cdclk;
1642
1643         if (!intel_state->active_crtcs) {
1644                 if (IS_GEMINILAKE(dev_priv)) {
1645                         cdclk = glk_calc_cdclk(0);
1646                         vco = glk_de_pll_vco(dev_priv, cdclk);
1647                 } else {
1648                         cdclk = bxt_calc_cdclk(0);
1649                         vco = bxt_de_pll_vco(dev_priv, cdclk);
1650                 }
1651
1652                 intel_state->cdclk.actual.vco = vco;
1653                 intel_state->cdclk.actual.cdclk = cdclk;
1654         } else {
1655                 intel_state->cdclk.actual =
1656                         intel_state->cdclk.logical;
1657         }
1658
1659         return 0;
1660 }
1661
1662 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
1663 {
1664         int max_cdclk_freq = dev_priv->max_cdclk_freq;
1665
1666         if (IS_GEMINILAKE(dev_priv))
1667                 return 2 * max_cdclk_freq;
1668         else if (INTEL_INFO(dev_priv)->gen >= 9 ||
1669                  IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1670                 return max_cdclk_freq;
1671         else if (IS_CHERRYVIEW(dev_priv))
1672                 return max_cdclk_freq*95/100;
1673         else if (INTEL_INFO(dev_priv)->gen < 4)
1674                 return 2*max_cdclk_freq*90/100;
1675         else
1676                 return max_cdclk_freq*90/100;
1677 }
1678
1679 /**
1680  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
1681  * @dev_priv: i915 device
1682  *
1683  * Determine the maximum CDCLK frequency the platform supports, and also
1684  * derive the maximum dot clock frequency the maximum CDCLK frequency
1685  * allows.
1686  */
1687 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
1688 {
1689         if (IS_GEN9_BC(dev_priv)) {
1690                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
1691                 int max_cdclk, vco;
1692
1693                 vco = dev_priv->skl_preferred_vco_freq;
1694                 WARN_ON(vco != 8100000 && vco != 8640000);
1695
1696                 /*
1697                  * Use the lower (vco 8640) cdclk values as a
1698                  * first guess. skl_calc_cdclk() will correct it
1699                  * if the preferred vco is 8100 instead.
1700                  */
1701                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
1702                         max_cdclk = 617143;
1703                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
1704                         max_cdclk = 540000;
1705                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
1706                         max_cdclk = 432000;
1707                 else
1708                         max_cdclk = 308571;
1709
1710                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
1711         } else if (IS_GEMINILAKE(dev_priv)) {
1712                 dev_priv->max_cdclk_freq = 316800;
1713         } else if (IS_BROXTON(dev_priv)) {
1714                 dev_priv->max_cdclk_freq = 624000;
1715         } else if (IS_BROADWELL(dev_priv))  {
1716                 /*
1717                  * FIXME with extra cooling we can allow
1718                  * 540 MHz for ULX and 675 Mhz for ULT.
1719                  * How can we know if extra cooling is
1720                  * available? PCI ID, VTB, something else?
1721                  */
1722                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1723                         dev_priv->max_cdclk_freq = 450000;
1724                 else if (IS_BDW_ULX(dev_priv))
1725                         dev_priv->max_cdclk_freq = 450000;
1726                 else if (IS_BDW_ULT(dev_priv))
1727                         dev_priv->max_cdclk_freq = 540000;
1728                 else
1729                         dev_priv->max_cdclk_freq = 675000;
1730         } else if (IS_CHERRYVIEW(dev_priv)) {
1731                 dev_priv->max_cdclk_freq = 320000;
1732         } else if (IS_VALLEYVIEW(dev_priv)) {
1733                 dev_priv->max_cdclk_freq = 400000;
1734         } else {
1735                 /* otherwise assume cdclk is fixed */
1736                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
1737         }
1738
1739         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
1740
1741         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
1742                          dev_priv->max_cdclk_freq);
1743
1744         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
1745                          dev_priv->max_dotclk_freq);
1746 }
1747
1748 /**
1749  * intel_update_cdclk - Determine the current CDCLK frequency
1750  * @dev_priv: i915 device
1751  *
1752  * Determine the current CDCLK frequency.
1753  */
1754 void intel_update_cdclk(struct drm_i915_private *dev_priv)
1755 {
1756         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
1757
1758         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
1759                          dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
1760                          dev_priv->cdclk.hw.ref);
1761
1762         /*
1763          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
1764          * Programmng [sic] note: bit[9:2] should be programmed to the number
1765          * of cdclk that generates 4MHz reference clock freq which is used to
1766          * generate GMBus clock. This will vary with the cdclk freq.
1767          */
1768         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1769                 I915_WRITE(GMBUSFREQ_VLV,
1770                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
1771 }
1772
1773 static int pch_rawclk(struct drm_i915_private *dev_priv)
1774 {
1775         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
1776 }
1777
1778 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
1779 {
1780         /* RAWCLK_FREQ_VLV register updated from power well code */
1781         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
1782                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
1783 }
1784
1785 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
1786 {
1787         uint32_t clkcfg;
1788
1789         /* hrawclock is 1/4 the FSB frequency */
1790         clkcfg = I915_READ(CLKCFG);
1791         switch (clkcfg & CLKCFG_FSB_MASK) {
1792         case CLKCFG_FSB_400:
1793                 return 100000;
1794         case CLKCFG_FSB_533:
1795                 return 133333;
1796         case CLKCFG_FSB_667:
1797                 return 166667;
1798         case CLKCFG_FSB_800:
1799                 return 200000;
1800         case CLKCFG_FSB_1067:
1801         case CLKCFG_FSB_1067_ALT:
1802                 return 266667;
1803         case CLKCFG_FSB_1333:
1804         case CLKCFG_FSB_1333_ALT:
1805                 return 333333;
1806         default:
1807                 return 133333;
1808         }
1809 }
1810
1811 /**
1812  * intel_update_rawclk - Determine the current RAWCLK frequency
1813  * @dev_priv: i915 device
1814  *
1815  * Determine the current RAWCLK frequency. RAWCLK is a fixed
1816  * frequency clock so this needs to done only once.
1817  */
1818 void intel_update_rawclk(struct drm_i915_private *dev_priv)
1819 {
1820         if (HAS_PCH_SPLIT(dev_priv))
1821                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
1822         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1823                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
1824         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
1825                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
1826         else
1827                 /* no rawclk on other platforms, or no need to know it */
1828                 return;
1829
1830         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
1831 }
1832
1833 /**
1834  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
1835  * @dev_priv: i915 device
1836  */
1837 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
1838 {
1839         if (IS_CHERRYVIEW(dev_priv)) {
1840                 dev_priv->display.set_cdclk = chv_set_cdclk;
1841                 dev_priv->display.modeset_calc_cdclk =
1842                         vlv_modeset_calc_cdclk;
1843         } else if (IS_VALLEYVIEW(dev_priv)) {
1844                 dev_priv->display.set_cdclk = vlv_set_cdclk;
1845                 dev_priv->display.modeset_calc_cdclk =
1846                         vlv_modeset_calc_cdclk;
1847         } else if (IS_BROADWELL(dev_priv)) {
1848                 dev_priv->display.set_cdclk = bdw_set_cdclk;
1849                 dev_priv->display.modeset_calc_cdclk =
1850                         bdw_modeset_calc_cdclk;
1851         } else if (IS_GEN9_LP(dev_priv)) {
1852                 dev_priv->display.set_cdclk = bxt_set_cdclk;
1853                 dev_priv->display.modeset_calc_cdclk =
1854                         bxt_modeset_calc_cdclk;
1855         } else if (IS_GEN9_BC(dev_priv)) {
1856                 dev_priv->display.set_cdclk = skl_set_cdclk;
1857                 dev_priv->display.modeset_calc_cdclk =
1858                         skl_modeset_calc_cdclk;
1859         }
1860
1861         if (IS_GEN9_BC(dev_priv))
1862                 dev_priv->display.get_cdclk = skl_get_cdclk;
1863         else if (IS_GEN9_LP(dev_priv))
1864                 dev_priv->display.get_cdclk = bxt_get_cdclk;
1865         else if (IS_BROADWELL(dev_priv))
1866                 dev_priv->display.get_cdclk = bdw_get_cdclk;
1867         else if (IS_HASWELL(dev_priv))
1868                 dev_priv->display.get_cdclk = hsw_get_cdclk;
1869         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1870                 dev_priv->display.get_cdclk = vlv_get_cdclk;
1871         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
1872                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
1873         else if (IS_GEN5(dev_priv))
1874                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
1875         else if (IS_GM45(dev_priv))
1876                 dev_priv->display.get_cdclk = gm45_get_cdclk;
1877         else if (IS_G45(dev_priv))
1878                 dev_priv->display.get_cdclk = g33_get_cdclk;
1879         else if (IS_I965GM(dev_priv))
1880                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
1881         else if (IS_I965G(dev_priv))
1882                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
1883         else if (IS_PINEVIEW(dev_priv))
1884                 dev_priv->display.get_cdclk = pnv_get_cdclk;
1885         else if (IS_G33(dev_priv))
1886                 dev_priv->display.get_cdclk = g33_get_cdclk;
1887         else if (IS_I945GM(dev_priv))
1888                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
1889         else if (IS_I945G(dev_priv))
1890                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
1891         else if (IS_I915GM(dev_priv))
1892                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
1893         else if (IS_I915G(dev_priv))
1894                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
1895         else if (IS_I865G(dev_priv))
1896                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
1897         else if (IS_I85X(dev_priv))
1898                 dev_priv->display.get_cdclk = i85x_get_cdclk;
1899         else if (IS_I845G(dev_priv))
1900                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
1901         else { /* 830 */
1902                 WARN(!IS_I830(dev_priv),
1903                      "Unknown platform. Assuming 133 MHz CDCLK\n");
1904                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
1905         }
1906 }