2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 #include "intel_drv.h"
27 #define CTM_COEFF_SIGN (1ULL << 63)
29 #define CTM_COEFF_1_0 (1ULL << 32)
30 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
31 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
32 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
33 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
34 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
35 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
37 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
39 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
40 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
42 #define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256)
45 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
46 * format). This macro takes the coefficient we want transformed and the
47 * number of fractional bits.
49 * We only have a 9 bits precision window which slides depending on the value
50 * of the CTM coefficient and we write the value from bit 3. We also round the
53 #define I9XX_CSC_COEFF_FP(coeff, fbits) \
54 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
56 #define I9XX_CSC_COEFF_LIMITED_RANGE \
57 I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
58 #define I9XX_CSC_COEFF_1_0 \
59 ((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
61 static bool crtc_state_is_legacy(struct drm_crtc_state
*state
)
63 return !state
->degamma_lut
&&
66 state
->gamma_lut
->length
== LEGACY_LUT_LENGTH
;
70 * When using limited range, multiply the matrix given by userspace by
71 * the matrix that we would use for the limited range. We do the
72 * multiplication in U2.30 format.
74 static void ctm_mult_by_limited(uint64_t *result
, int64_t *input
)
78 for (i
= 0; i
< 9; i
++)
81 for (i
= 0; i
< 3; i
++) {
82 int64_t user_coeff
= input
[i
* 3 + i
];
83 uint64_t limited_coeff
= CTM_COEFF_LIMITED_RANGE
>> 2;
84 uint64_t abs_coeff
= clamp_val(CTM_COEFF_ABS(user_coeff
),
86 CTM_COEFF_4_0
- 1) >> 2;
88 result
[i
* 3 + i
] = (limited_coeff
* abs_coeff
) >> 27;
89 if (CTM_COEFF_NEGATIVE(user_coeff
))
90 result
[i
* 3 + i
] |= CTM_COEFF_SIGN
;
94 /* Set up the pipe CSC unit. */
95 static void i9xx_load_csc_matrix(struct drm_crtc_state
*crtc_state
)
97 struct drm_crtc
*crtc
= crtc_state
->crtc
;
98 struct drm_device
*dev
= crtc
->dev
;
99 struct drm_i915_private
*dev_priv
= to_i915(dev
);
100 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
101 int i
, pipe
= intel_crtc
->pipe
;
102 uint16_t coeffs
[9] = { 0, };
103 struct intel_crtc_state
*intel_crtc_state
= to_intel_crtc_state(crtc_state
);
105 if (crtc_state
->ctm
) {
106 struct drm_color_ctm
*ctm
=
107 (struct drm_color_ctm
*)crtc_state
->ctm
->data
;
108 uint64_t input
[9] = { 0, };
110 if (intel_crtc_state
->limited_color_range
) {
111 ctm_mult_by_limited(input
, ctm
->matrix
);
113 for (i
= 0; i
< ARRAY_SIZE(input
); i
++)
114 input
[i
] = ctm
->matrix
[i
];
118 * Convert fixed point S31.32 input to format supported by the
121 for (i
= 0; i
< ARRAY_SIZE(coeffs
); i
++) {
122 uint64_t abs_coeff
= ((1ULL << 63) - 1) & input
[i
];
125 * Clamp input value to min/max supported by
128 abs_coeff
= clamp_val(abs_coeff
, 0, CTM_COEFF_4_0
- 1);
131 if (CTM_COEFF_NEGATIVE(input
[i
]))
132 coeffs
[i
] |= 1 << 15;
134 if (abs_coeff
< CTM_COEFF_0_125
)
135 coeffs
[i
] |= (3 << 12) |
136 I9XX_CSC_COEFF_FP(abs_coeff
, 12);
137 else if (abs_coeff
< CTM_COEFF_0_25
)
138 coeffs
[i
] |= (2 << 12) |
139 I9XX_CSC_COEFF_FP(abs_coeff
, 11);
140 else if (abs_coeff
< CTM_COEFF_0_5
)
141 coeffs
[i
] |= (1 << 12) |
142 I9XX_CSC_COEFF_FP(abs_coeff
, 10);
143 else if (abs_coeff
< CTM_COEFF_1_0
)
144 coeffs
[i
] |= I9XX_CSC_COEFF_FP(abs_coeff
, 9);
145 else if (abs_coeff
< CTM_COEFF_2_0
)
146 coeffs
[i
] |= (7 << 12) |
147 I9XX_CSC_COEFF_FP(abs_coeff
, 8);
149 coeffs
[i
] |= (6 << 12) |
150 I9XX_CSC_COEFF_FP(abs_coeff
, 7);
154 * Load an identity matrix if no coefficients are provided.
156 * TODO: Check what kind of values actually come out of the
157 * pipe with these coeff/postoff values and adjust to get the
158 * best accuracy. Perhaps we even need to take the bpc value
159 * into consideration.
161 for (i
= 0; i
< 3; i
++) {
162 if (intel_crtc_state
->limited_color_range
)
164 I9XX_CSC_COEFF_LIMITED_RANGE
;
166 coeffs
[i
* 3 + i
] = I9XX_CSC_COEFF_1_0
;
170 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeffs
[0] << 16 | coeffs
[1]);
171 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), coeffs
[2] << 16);
173 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeffs
[3] << 16 | coeffs
[4]);
174 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), coeffs
[5] << 16);
176 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), coeffs
[6] << 16 | coeffs
[7]);
177 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeffs
[8] << 16);
179 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
180 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
181 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
183 if (INTEL_INFO(dev
)->gen
> 6) {
184 uint16_t postoff
= 0;
186 if (intel_crtc_state
->limited_color_range
)
187 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
189 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
190 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
191 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
193 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
195 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
197 if (intel_crtc_state
->limited_color_range
)
198 mode
|= CSC_BLACK_SCREEN_OFFSET
;
200 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
205 * Set up the pipe CSC unit on CherryView.
207 static void cherryview_load_csc_matrix(struct drm_crtc_state
*state
)
209 struct drm_crtc
*crtc
= state
->crtc
;
210 struct drm_device
*dev
= crtc
->dev
;
211 struct drm_i915_private
*dev_priv
= to_i915(dev
);
212 int pipe
= to_intel_crtc(crtc
)->pipe
;
216 struct drm_color_ctm
*ctm
=
217 (struct drm_color_ctm
*) state
->ctm
->data
;
218 uint16_t coeffs
[9] = { 0, };
221 for (i
= 0; i
< ARRAY_SIZE(coeffs
); i
++) {
223 ((1ULL << 63) - 1) & ctm
->matrix
[i
];
225 /* Round coefficient. */
226 abs_coeff
+= 1 << (32 - 13);
227 /* Clamp to hardware limits. */
228 abs_coeff
= clamp_val(abs_coeff
, 0, CTM_COEFF_8_0
- 1);
230 /* Write coefficients in S3.12 format. */
231 if (ctm
->matrix
[i
] & (1ULL << 63))
233 coeffs
[i
] |= ((abs_coeff
>> 32) & 7) << 12;
234 coeffs
[i
] |= (abs_coeff
>> 20) & 0xfff;
237 I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe
),
238 coeffs
[1] << 16 | coeffs
[0]);
239 I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe
),
240 coeffs
[3] << 16 | coeffs
[2]);
241 I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe
),
242 coeffs
[5] << 16 | coeffs
[4]);
243 I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe
),
244 coeffs
[7] << 16 | coeffs
[6]);
245 I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe
), coeffs
[8]);
248 mode
= (state
->ctm
? CGM_PIPE_MODE_CSC
: 0);
249 if (!crtc_state_is_legacy(state
)) {
250 mode
|= (state
->degamma_lut
? CGM_PIPE_MODE_DEGAMMA
: 0) |
251 (state
->gamma_lut
? CGM_PIPE_MODE_GAMMA
: 0);
253 I915_WRITE(CGM_PIPE_MODE(pipe
), mode
);
256 void intel_color_set_csc(struct drm_crtc_state
*crtc_state
)
258 struct drm_device
*dev
= crtc_state
->crtc
->dev
;
259 struct drm_i915_private
*dev_priv
= to_i915(dev
);
261 if (dev_priv
->display
.load_csc_matrix
)
262 dev_priv
->display
.load_csc_matrix(crtc_state
);
265 /* Loads the legacy palette/gamma unit for the CRTC. */
266 static void i9xx_load_luts_internal(struct drm_crtc
*crtc
,
267 struct drm_property_blob
*blob
,
268 struct intel_crtc_state
*crtc_state
)
270 struct drm_device
*dev
= crtc
->dev
;
271 struct drm_i915_private
*dev_priv
= to_i915(dev
);
272 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
273 enum pipe pipe
= intel_crtc
->pipe
;
276 if (HAS_GMCH_DISPLAY(dev_priv
)) {
277 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
))
278 assert_dsi_pll_enabled(dev_priv
);
280 assert_pll_enabled(dev_priv
, pipe
);
284 struct drm_color_lut
*lut
= (struct drm_color_lut
*) blob
->data
;
285 for (i
= 0; i
< 256; i
++) {
287 (drm_color_lut_extract(lut
[i
].red
, 8) << 16) |
288 (drm_color_lut_extract(lut
[i
].green
, 8) << 8) |
289 drm_color_lut_extract(lut
[i
].blue
, 8);
291 if (HAS_GMCH_DISPLAY(dev_priv
))
292 I915_WRITE(PALETTE(pipe
, i
), word
);
294 I915_WRITE(LGC_PALETTE(pipe
, i
), word
);
297 for (i
= 0; i
< 256; i
++) {
298 uint32_t word
= (i
<< 16) | (i
<< 8) | i
;
300 if (HAS_GMCH_DISPLAY(dev_priv
))
301 I915_WRITE(PALETTE(pipe
, i
), word
);
303 I915_WRITE(LGC_PALETTE(pipe
, i
), word
);
308 static void i9xx_load_luts(struct drm_crtc_state
*crtc_state
)
310 i9xx_load_luts_internal(crtc_state
->crtc
, crtc_state
->gamma_lut
,
311 to_intel_crtc_state(crtc_state
));
314 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
315 static void haswell_load_luts(struct drm_crtc_state
*crtc_state
)
317 struct drm_crtc
*crtc
= crtc_state
->crtc
;
318 struct drm_device
*dev
= crtc
->dev
;
319 struct drm_i915_private
*dev_priv
= to_i915(dev
);
320 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
321 struct intel_crtc_state
*intel_crtc_state
=
322 to_intel_crtc_state(crtc_state
);
323 bool reenable_ips
= false;
326 * Workaround : Do not read or write the pipe palette/gamma data while
327 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
329 if (IS_HASWELL(dev
) && intel_crtc_state
->ips_enabled
&&
330 (intel_crtc_state
->gamma_mode
== GAMMA_MODE_MODE_SPLIT
)) {
331 hsw_disable_ips(intel_crtc
);
335 intel_crtc_state
->gamma_mode
= GAMMA_MODE_MODE_8BIT
;
336 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
338 i9xx_load_luts(crtc_state
);
341 hsw_enable_ips(intel_crtc
);
344 /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
345 static void broadwell_load_luts(struct drm_crtc_state
*state
)
347 struct drm_crtc
*crtc
= state
->crtc
;
348 struct drm_device
*dev
= crtc
->dev
;
349 struct drm_i915_private
*dev_priv
= to_i915(dev
);
350 struct intel_crtc_state
*intel_state
= to_intel_crtc_state(state
);
351 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
352 uint32_t i
, lut_size
= INTEL_INFO(dev
)->color
.degamma_lut_size
;
354 if (crtc_state_is_legacy(state
)) {
355 haswell_load_luts(state
);
359 I915_WRITE(PREC_PAL_INDEX(pipe
),
360 PAL_PREC_SPLIT_MODE
| PAL_PREC_AUTO_INCREMENT
);
362 if (state
->degamma_lut
) {
363 struct drm_color_lut
*lut
=
364 (struct drm_color_lut
*) state
->degamma_lut
->data
;
366 for (i
= 0; i
< lut_size
; i
++) {
368 drm_color_lut_extract(lut
[i
].red
, 10) << 20 |
369 drm_color_lut_extract(lut
[i
].green
, 10) << 10 |
370 drm_color_lut_extract(lut
[i
].blue
, 10);
372 I915_WRITE(PREC_PAL_DATA(pipe
), word
);
375 for (i
= 0; i
< lut_size
; i
++) {
376 uint32_t v
= (i
* ((1 << 10) - 1)) / (lut_size
- 1);
378 I915_WRITE(PREC_PAL_DATA(pipe
),
379 (v
<< 20) | (v
<< 10) | v
);
383 if (state
->gamma_lut
) {
384 struct drm_color_lut
*lut
=
385 (struct drm_color_lut
*) state
->gamma_lut
->data
;
387 for (i
= 0; i
< lut_size
; i
++) {
389 (drm_color_lut_extract(lut
[i
].red
, 10) << 20) |
390 (drm_color_lut_extract(lut
[i
].green
, 10) << 10) |
391 drm_color_lut_extract(lut
[i
].blue
, 10);
393 I915_WRITE(PREC_PAL_DATA(pipe
), word
);
396 /* Program the max register to clamp values > 1.0. */
397 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 0),
398 drm_color_lut_extract(lut
[i
].red
, 16));
399 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 1),
400 drm_color_lut_extract(lut
[i
].green
, 16));
401 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 2),
402 drm_color_lut_extract(lut
[i
].blue
, 16));
404 for (i
= 0; i
< lut_size
; i
++) {
405 uint32_t v
= (i
* ((1 << 10) - 1)) / (lut_size
- 1);
407 I915_WRITE(PREC_PAL_DATA(pipe
),
408 (v
<< 20) | (v
<< 10) | v
);
411 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 0), (1 << 16) - 1);
412 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 1), (1 << 16) - 1);
413 I915_WRITE(PREC_PAL_GC_MAX(pipe
, 2), (1 << 16) - 1);
416 intel_state
->gamma_mode
= GAMMA_MODE_MODE_SPLIT
;
417 I915_WRITE(GAMMA_MODE(pipe
), GAMMA_MODE_MODE_SPLIT
);
418 POSTING_READ(GAMMA_MODE(pipe
));
421 * Reset the index, otherwise it prevents the legacy palette to be
424 I915_WRITE(PREC_PAL_INDEX(pipe
), 0);
427 /* Loads the palette/gamma unit for the CRTC on CherryView. */
428 static void cherryview_load_luts(struct drm_crtc_state
*state
)
430 struct drm_crtc
*crtc
= state
->crtc
;
431 struct drm_device
*dev
= crtc
->dev
;
432 struct drm_i915_private
*dev_priv
= to_i915(dev
);
433 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
434 struct drm_color_lut
*lut
;
435 uint32_t i
, lut_size
;
436 uint32_t word0
, word1
;
438 if (crtc_state_is_legacy(state
)) {
439 /* Turn off degamma/gamma on CGM block. */
440 I915_WRITE(CGM_PIPE_MODE(pipe
),
441 (state
->ctm
? CGM_PIPE_MODE_CSC
: 0));
442 i9xx_load_luts_internal(crtc
, state
->gamma_lut
,
443 to_intel_crtc_state(state
));
447 if (state
->degamma_lut
) {
448 lut
= (struct drm_color_lut
*) state
->degamma_lut
->data
;
449 lut_size
= INTEL_INFO(dev
)->color
.degamma_lut_size
;
450 for (i
= 0; i
< lut_size
; i
++) {
451 /* Write LUT in U0.14 format. */
453 (drm_color_lut_extract(lut
[i
].green
, 14) << 16) |
454 drm_color_lut_extract(lut
[i
].blue
, 14);
455 word1
= drm_color_lut_extract(lut
[i
].red
, 14);
457 I915_WRITE(CGM_PIPE_DEGAMMA(pipe
, i
, 0), word0
);
458 I915_WRITE(CGM_PIPE_DEGAMMA(pipe
, i
, 1), word1
);
462 if (state
->gamma_lut
) {
463 lut
= (struct drm_color_lut
*) state
->gamma_lut
->data
;
464 lut_size
= INTEL_INFO(dev
)->color
.gamma_lut_size
;
465 for (i
= 0; i
< lut_size
; i
++) {
466 /* Write LUT in U0.10 format. */
468 (drm_color_lut_extract(lut
[i
].green
, 10) << 16) |
469 drm_color_lut_extract(lut
[i
].blue
, 10);
470 word1
= drm_color_lut_extract(lut
[i
].red
, 10);
472 I915_WRITE(CGM_PIPE_GAMMA(pipe
, i
, 0), word0
);
473 I915_WRITE(CGM_PIPE_GAMMA(pipe
, i
, 1), word1
);
477 I915_WRITE(CGM_PIPE_MODE(pipe
),
478 (state
->ctm
? CGM_PIPE_MODE_CSC
: 0) |
479 (state
->degamma_lut
? CGM_PIPE_MODE_DEGAMMA
: 0) |
480 (state
->gamma_lut
? CGM_PIPE_MODE_GAMMA
: 0));
483 * Also program a linear LUT in the legacy block (behind the
486 i9xx_load_luts_internal(crtc
, NULL
, to_intel_crtc_state(state
));
489 void intel_color_load_luts(struct drm_crtc_state
*crtc_state
)
491 struct drm_device
*dev
= crtc_state
->crtc
->dev
;
492 struct drm_i915_private
*dev_priv
= to_i915(dev
);
494 dev_priv
->display
.load_luts(crtc_state
);
497 int intel_color_check(struct drm_crtc
*crtc
,
498 struct drm_crtc_state
*crtc_state
)
500 struct drm_device
*dev
= crtc
->dev
;
501 size_t gamma_length
, degamma_length
;
503 degamma_length
= INTEL_INFO(dev
)->color
.degamma_lut_size
*
504 sizeof(struct drm_color_lut
);
505 gamma_length
= INTEL_INFO(dev
)->color
.gamma_lut_size
*
506 sizeof(struct drm_color_lut
);
509 * We allow both degamma & gamma luts at the right size or
512 if ((!crtc_state
->degamma_lut
||
513 crtc_state
->degamma_lut
->length
== degamma_length
) &&
514 (!crtc_state
->gamma_lut
||
515 crtc_state
->gamma_lut
->length
== gamma_length
))
519 * We also allow no degamma lut and a gamma lut at the legacy
520 * size (256 entries).
522 if (!crtc_state
->degamma_lut
&&
523 crtc_state
->gamma_lut
&&
524 crtc_state
->gamma_lut
->length
== LEGACY_LUT_LENGTH
)
530 void intel_color_init(struct drm_crtc
*crtc
)
532 struct drm_device
*dev
= crtc
->dev
;
533 struct drm_i915_private
*dev_priv
= to_i915(dev
);
535 drm_mode_crtc_set_gamma_size(crtc
, 256);
537 if (IS_CHERRYVIEW(dev
)) {
538 dev_priv
->display
.load_csc_matrix
= cherryview_load_csc_matrix
;
539 dev_priv
->display
.load_luts
= cherryview_load_luts
;
540 } else if (IS_HASWELL(dev
)) {
541 dev_priv
->display
.load_csc_matrix
= i9xx_load_csc_matrix
;
542 dev_priv
->display
.load_luts
= haswell_load_luts
;
543 } else if (IS_BROADWELL(dev_priv
) || IS_SKYLAKE(dev_priv
) ||
544 IS_BROXTON(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
545 dev_priv
->display
.load_csc_matrix
= i9xx_load_csc_matrix
;
546 dev_priv
->display
.load_luts
= broadwell_load_luts
;
548 dev_priv
->display
.load_luts
= i9xx_load_luts
;
551 /* Enable color management support when we have degamma & gamma LUTs. */
552 if (INTEL_INFO(dev
)->color
.degamma_lut_size
!= 0 &&
553 INTEL_INFO(dev
)->color
.gamma_lut_size
!= 0)
554 drm_crtc_enable_color_mgmt(crtc
,
555 INTEL_INFO(dev
)->color
.degamma_lut_size
,
557 INTEL_INFO(dev
)->color
.gamma_lut_size
);