drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         i915_reg_t adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67                                    enum pipe *pipe)
  68 {
  69         struct drm_device *dev = encoder->base.dev;
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72         enum intel_display_power_domain power_domain;
  73         u32 tmp;
  74
  75         power_domain = intel_display_port_power_domain(encoder);
  76         if (!intel_display_power_is_enabled(dev_priv, power_domain))
  77                 return false;
  78
  79         tmp = I915_READ(crt->adpa_reg);
  80
  81         if (!(tmp & ADPA_DAC_ENABLE))
  82                 return false;
  83
  84         if (HAS_PCH_CPT(dev))
  85                 *pipe = PORT_TO_PIPE_CPT(tmp);
  86         else
  87                 *pipe = PORT_TO_PIPE(tmp);
  88
  89         return true;
  90 }
  91
  92 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
  93 {
  94         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  95         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  96         u32 tmp, flags = 0;
  97
  98         tmp = I915_READ(crt->adpa_reg);
  99
 100         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 101                 flags |= DRM_MODE_FLAG_PHSYNC;
 102         else
 103                 flags |= DRM_MODE_FLAG_NHSYNC;
 104
 105         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 106                 flags |= DRM_MODE_FLAG_PVSYNC;
 107         else
 108                 flags |= DRM_MODE_FLAG_NVSYNC;
 109
 110         return flags;
 111 }
 112
 113 static void intel_crt_get_config(struct intel_encoder *encoder,
 114                                  struct intel_crtc_state *pipe_config)
 115 {
 116         struct drm_device *dev = encoder->base.dev;
 117         int dotclock;
 118
 119         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 120
 121         dotclock = pipe_config->port_clock;
 122
 123         if (HAS_PCH_SPLIT(dev))
 124                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 125
 126         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 127 }
 128
 129 static void hsw_crt_get_config(struct intel_encoder *encoder,
 130                                struct intel_crtc_state *pipe_config)
 131 {
 132         intel_ddi_get_config(encoder, pipe_config);
 133
 134         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 135                                               DRM_MODE_FLAG_NHSYNC |
 136                                               DRM_MODE_FLAG_PVSYNC |
 137                                               DRM_MODE_FLAG_NVSYNC);
 138         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 139 }
 140
 141 /* Note: The caller is required to filter out dpms modes not supported by the
 142  * platform. */
 143 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
 144 {
 145         struct drm_device *dev = encoder->base.dev;
 146         struct drm_i915_private *dev_priv = dev->dev_private;
 147         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 148         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 149         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 150         u32 adpa;
 151
 152         if (INTEL_INFO(dev)->gen >= 5)
 153                 adpa = ADPA_HOTPLUG_BITS;
 154         else
 155                 adpa = 0;
 156
 157         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 158                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 159         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 160                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 161
 162         /* For CPT allow 3 pipe config, for others just use A or B */
 163         if (HAS_PCH_LPT(dev))
 164                 ; /* Those bits don't exist here */
 165         else if (HAS_PCH_CPT(dev))
 166                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
 167         else if (crtc->pipe == 0)
 168                 adpa |= ADPA_PIPE_A_SELECT;
 169         else
 170                 adpa |= ADPA_PIPE_B_SELECT;
 171
 172         if (!HAS_PCH_SPLIT(dev))
 173                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 174
 175         switch (mode) {
 176         case DRM_MODE_DPMS_ON:
 177                 adpa |= ADPA_DAC_ENABLE;
 178                 break;
 179         case DRM_MODE_DPMS_STANDBY:
 180                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 181                 break;
 182         case DRM_MODE_DPMS_SUSPEND:
 183                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 184                 break;
 185         case DRM_MODE_DPMS_OFF:
 186                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 187                 break;
 188         }
 189
 190         I915_WRITE(crt->adpa_reg, adpa);
 191 }
 192
 193 static void intel_disable_crt(struct intel_encoder *encoder)
 194 {
 195         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
 196 }
 197
 198 static void pch_disable_crt(struct intel_encoder *encoder)
 199 {
 200 }
 201
 202 static void pch_post_disable_crt(struct intel_encoder *encoder)
 203 {
 204         intel_disable_crt(encoder);
 205 }
 206
 207 static void intel_enable_crt(struct intel_encoder *encoder)
 208 {
 209         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 210
 211         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
 212 }
 213
 214 static enum drm_mode_status
 215 intel_crt_mode_valid(struct drm_connector *connector,
 216                      struct drm_display_mode *mode)
 217 {
 218         struct drm_device *dev = connector->dev;
 219
 220         int max_clock = 0;
 221         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 222                 return MODE_NO_DBLESCAN;
 223
 224         if (mode->clock < 25000)
 225                 return MODE_CLOCK_LOW;
 226
 227         if (IS_GEN2(dev))
 228                 max_clock = 350000;
 229         else
 230                 max_clock = 400000;
 231         if (mode->clock > max_clock)
 232                 return MODE_CLOCK_HIGH;
 233
 234         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 235         if (HAS_PCH_LPT(dev) &&
 236             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 237                 return MODE_CLOCK_HIGH;
 238
 239         return MODE_OK;
 240 }
 241
 242 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 243                                      struct intel_crtc_state *pipe_config)
 244 {
 245         struct drm_device *dev = encoder->base.dev;
 246
 247         if (HAS_PCH_SPLIT(dev))
 248                 pipe_config->has_pch_encoder = true;
 249
 250         /* LPT FDI RX only supports 8bpc. */
 251         if (HAS_PCH_LPT(dev))
 252                 pipe_config->pipe_bpp = 24;
 253
 254         /* FDI must always be 2.7 GHz */
 255         if (HAS_DDI(dev)) {
 256                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
 257                 pipe_config->port_clock = 135000 * 2;
 258
 259                 pipe_config->dpll_hw_state.wrpll = 0;
 260                 pipe_config->dpll_hw_state.spll =
 261                         SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
 262         }
 263
 264         return true;
 265 }
 266
 267 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 268 {
 269         struct drm_device *dev = connector->dev;
 270         struct intel_crt *crt = intel_attached_crt(connector);
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272         u32 adpa;
 273         bool ret;
 274
 275         /* The first time through, trigger an explicit detection cycle */
 276         if (crt->force_hotplug_required) {
 277                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
 278                 u32 save_adpa;
 279
 280                 crt->force_hotplug_required = 0;
 281
 282                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 283                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 284
 285                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 286                 if (turn_off_dac)
 287                         adpa &= ~ADPA_DAC_ENABLE;
 288
 289                 I915_WRITE(crt->adpa_reg, adpa);
 290
 291                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 292                              1000))
 293                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 294
 295                 if (turn_off_dac) {
 296                         I915_WRITE(crt->adpa_reg, save_adpa);
 297                         POSTING_READ(crt->adpa_reg);
 298                 }
 299         }
 300
 301         /* Check the status to see if both blue and green are on now */
 302         adpa = I915_READ(crt->adpa_reg);
 303         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 304                 ret = true;
 305         else
 306                 ret = false;
 307         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 308
 309         return ret;
 310 }
 311
 312 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 313 {
 314         struct drm_device *dev = connector->dev;
 315         struct intel_crt *crt = intel_attached_crt(connector);
 316         struct drm_i915_private *dev_priv = dev->dev_private;
 317         u32 adpa;
 318         bool ret;
 319         u32 save_adpa;
 320
 321         save_adpa = adpa = I915_READ(crt->adpa_reg);
 322         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 323
 324         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 325
 326         I915_WRITE(crt->adpa_reg, adpa);
 327
 328         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 329                      1000)) {
 330                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 331                 I915_WRITE(crt->adpa_reg, save_adpa);
 332         }
 333
 334         /* Check the status to see if both blue and green are on now */
 335         adpa = I915_READ(crt->adpa_reg);
 336         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 337                 ret = true;
 338         else
 339                 ret = false;
 340
 341         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 342
 343         return ret;
 344 }
 345
 346 /**
 347  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 348  *
 349  * Not for i915G/i915GM
 350  *
 351  * \return true if CRT is connected.
 352  * \return false if CRT is disconnected.
 353  */
 354 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 355 {
 356         struct drm_device *dev = connector->dev;
 357         struct drm_i915_private *dev_priv = dev->dev_private;
 358         u32 stat;
 359         bool ret = false;
 360         int i, tries = 0;
 361
 362         if (HAS_PCH_SPLIT(dev))
 363                 return intel_ironlake_crt_detect_hotplug(connector);
 364
 365         if (IS_VALLEYVIEW(dev))
 366                 return valleyview_crt_detect_hotplug(connector);
 367
 368         /*
 369          * On 4 series desktop, CRT detect sequence need to be done twice
 370          * to get a reliable result.
 371          */
 372
 373         if (IS_G4X(dev) && !IS_GM45(dev))
 374                 tries = 2;
 375         else
 376                 tries = 1;
 377
 378         for (i = 0; i < tries ; i++) {
 379                 /* turn on the FORCE_DETECT */
 380                 i915_hotplug_interrupt_update(dev_priv,
 381                                               CRT_HOTPLUG_FORCE_DETECT,
 382                                               CRT_HOTPLUG_FORCE_DETECT);
 383                 /* wait for FORCE_DETECT to go off */
 384                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
 385                               CRT_HOTPLUG_FORCE_DETECT) == 0,
 386                              1000))
 387                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 388         }
 389
 390         stat = I915_READ(PORT_HOTPLUG_STAT);
 391         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 392                 ret = true;
 393
 394         /* clear the interrupt we just generated, if any */
 395         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 396
 397         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 398
 399         return ret;
 400 }
 401
 402 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 403                                 struct i2c_adapter *i2c)
 404 {
 405         struct edid *edid;
 406
 407         edid = drm_get_edid(connector, i2c);
 408
 409         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 410                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 411                 intel_gmbus_force_bit(i2c, true);
 412                 edid = drm_get_edid(connector, i2c);
 413                 intel_gmbus_force_bit(i2c, false);
 414         }
 415
 416         return edid;
 417 }
 418
 419 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 420 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 421                                 struct i2c_adapter *adapter)
 422 {
 423         struct edid *edid;
 424         int ret;
 425
 426         edid = intel_crt_get_edid(connector, adapter);
 427         if (!edid)
 428                 return 0;
 429
 430         ret = intel_connector_update_modes(connector, edid);
 431         kfree(edid);
 432
 433         return ret;
 434 }
 435
 436 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 437 {
 438         struct intel_crt *crt = intel_attached_crt(connector);
 439         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
 440         struct edid *edid;
 441         struct i2c_adapter *i2c;
 442
 443         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 444
 445         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 446         edid = intel_crt_get_edid(connector, i2c);
 447
 448         if (edid) {
 449                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 450
 451                 /*
 452                  * This may be a DVI-I connector with a shared DDC
 453                  * link between analog and digital outputs, so we
 454                  * have to check the EDID input spec of the attached device.
 455                  */
 456                 if (!is_digital) {
 457                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 458                         return true;
 459                 }
 460
 461                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 462         } else {
 463                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 464         }
 465
 466         kfree(edid);
 467
 468         return false;
 469 }
 470
 471 static enum drm_connector_status
 472 intel_crt_load_detect(struct intel_crt *crt)
 473 {
 474         struct drm_device *dev = crt->base.base.dev;
 475         struct drm_i915_private *dev_priv = dev->dev_private;
 476         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
 477         uint32_t save_bclrpat;
 478         uint32_t save_vtotal;
 479         uint32_t vtotal, vactive;
 480         uint32_t vsample;
 481         uint32_t vblank, vblank_start, vblank_end;
 482         uint32_t dsl;
 483         i915_reg_t bclrpat_reg, vtotal_reg,
 484                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 485         uint8_t st00;
 486         enum drm_connector_status status;
 487
 488         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 489
 490         bclrpat_reg = BCLRPAT(pipe);
 491         vtotal_reg = VTOTAL(pipe);
 492         vblank_reg = VBLANK(pipe);
 493         vsync_reg = VSYNC(pipe);
 494         pipeconf_reg = PIPECONF(pipe);
 495         pipe_dsl_reg = PIPEDSL(pipe);
 496
 497         save_bclrpat = I915_READ(bclrpat_reg);
 498         save_vtotal = I915_READ(vtotal_reg);
 499         vblank = I915_READ(vblank_reg);
 500
 501         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 502         vactive = (save_vtotal & 0x7ff) + 1;
 503
 504         vblank_start = (vblank & 0xfff) + 1;
 505         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 506
 507         /* Set the border color to purple. */
 508         I915_WRITE(bclrpat_reg, 0x500050);
 509
 510         if (!IS_GEN2(dev)) {
 511                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 512                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 513                 POSTING_READ(pipeconf_reg);
 514                 /* Wait for next Vblank to substitue
 515                  * border color for Color info */
 516                 intel_wait_for_vblank(dev, pipe);
 517                 st00 = I915_READ8(_VGA_MSR_WRITE);
 518                 status = ((st00 & (1 << 4)) != 0) ?
 519                         connector_status_connected :
 520                         connector_status_disconnected;
 521
 522                 I915_WRITE(pipeconf_reg, pipeconf);
 523         } else {
 524                 bool restore_vblank = false;
 525                 int count, detect;
 526
 527                 /*
 528                 * If there isn't any border, add some.
 529                 * Yes, this will flicker
 530                 */
 531                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 532                         uint32_t vsync = I915_READ(vsync_reg);
 533                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 534
 535                         vblank_start = vsync_start;
 536                         I915_WRITE(vblank_reg,
 537                                    (vblank_start - 1) |
 538                                    ((vblank_end - 1) << 16));
 539                         restore_vblank = true;
 540                 }
 541                 /* sample in the vertical border, selecting the larger one */
 542                 if (vblank_start - vactive >= vtotal - vblank_end)
 543                         vsample = (vblank_start + vactive) >> 1;
 544                 else
 545                         vsample = (vtotal + vblank_end) >> 1;
 546
 547                 /*
 548                  * Wait for the border to be displayed
 549                  */
 550                 while (I915_READ(pipe_dsl_reg) >= vactive)
 551                         ;
 552                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 553                         ;
 554                 /*
 555                  * Watch ST00 for an entire scanline
 556                  */
 557                 detect = 0;
 558                 count = 0;
 559                 do {
 560                         count++;
 561                         /* Read the ST00 VGA status register */
 562                         st00 = I915_READ8(_VGA_MSR_WRITE);
 563                         if (st00 & (1 << 4))
 564                                 detect++;
 565                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 566
 567                 /* restore vblank if necessary */
 568                 if (restore_vblank)
 569                         I915_WRITE(vblank_reg, vblank);
 570                 /*
 571                  * If more than 3/4 of the scanline detected a monitor,
 572                  * then it is assumed to be present. This works even on i830,
 573                  * where there isn't any way to force the border color across
 574                  * the screen
 575                  */
 576                 status = detect * 4 > count * 3 ?
 577                          connector_status_connected :
 578                          connector_status_disconnected;
 579         }
 580
 581         /* Restore previous settings */
 582         I915_WRITE(bclrpat_reg, save_bclrpat);
 583
 584         return status;
 585 }
 586
 587 static enum drm_connector_status
 588 intel_crt_detect(struct drm_connector *connector, bool force)
 589 {
 590         struct drm_device *dev = connector->dev;
 591         struct drm_i915_private *dev_priv = dev->dev_private;
 592         struct intel_crt *crt = intel_attached_crt(connector);
 593         struct intel_encoder *intel_encoder = &crt->base;
 594         enum intel_display_power_domain power_domain;
 595         enum drm_connector_status status;
 596         struct intel_load_detect_pipe tmp;
 597         struct drm_modeset_acquire_ctx ctx;
 598
 599         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 600                       connector->base.id, connector->name,
 601                       force);
 602
 603         power_domain = intel_display_port_power_domain(intel_encoder);
 604         intel_display_power_get(dev_priv, power_domain);
 605
 606         if (I915_HAS_HOTPLUG(dev)) {
 607                 /* We can not rely on the HPD pin always being correctly wired
 608                  * up, for example many KVM do not pass it through, and so
 609                  * only trust an assertion that the monitor is connected.
 610                  */
 611                 if (intel_crt_detect_hotplug(connector)) {
 612                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 613                         status = connector_status_connected;
 614                         goto out;
 615                 } else
 616                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 617         }
 618
 619         if (intel_crt_detect_ddc(connector)) {
 620                 status = connector_status_connected;
 621                 goto out;
 622         }
 623
 624         /* Load detection is broken on HPD capable machines. Whoever wants a
 625          * broken monitor (without edid) to work behind a broken kvm (that fails
 626          * to have the right resistors for HP detection) needs to fix this up.
 627          * For now just bail out. */
 628         if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
 629                 status = connector_status_disconnected;
 630                 goto out;
 631         }
 632
 633         if (!force) {
 634                 status = connector->status;
 635                 goto out;
 636         }
 637
 638         drm_modeset_acquire_init(&ctx, 0);
 639
 640         /* for pre-945g platforms use load detect */
 641         if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
 642                 if (intel_crt_detect_ddc(connector))
 643                         status = connector_status_connected;
 644                 else if (INTEL_INFO(dev)->gen < 4)
 645                         status = intel_crt_load_detect(crt);
 646                 else
 647                         status = connector_status_unknown;
 648                 intel_release_load_detect_pipe(connector, &tmp, &ctx);
 649         } else
 650                 status = connector_status_unknown;
 651
 652         drm_modeset_drop_locks(&ctx);
 653         drm_modeset_acquire_fini(&ctx);
 654
 655 out:
 656         intel_display_power_put(dev_priv, power_domain);
 657         return status;
 658 }
 659
 660 static void intel_crt_destroy(struct drm_connector *connector)
 661 {
 662         drm_connector_cleanup(connector);
 663         kfree(connector);
 664 }
 665
 666 static int intel_crt_get_modes(struct drm_connector *connector)
 667 {
 668         struct drm_device *dev = connector->dev;
 669         struct drm_i915_private *dev_priv = dev->dev_private;
 670         struct intel_crt *crt = intel_attached_crt(connector);
 671         struct intel_encoder *intel_encoder = &crt->base;
 672         enum intel_display_power_domain power_domain;
 673         int ret;
 674         struct i2c_adapter *i2c;
 675
 676         power_domain = intel_display_port_power_domain(intel_encoder);
 677         intel_display_power_get(dev_priv, power_domain);
 678
 679         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 680         ret = intel_crt_ddc_get_modes(connector, i2c);
 681         if (ret || !IS_G4X(dev))
 682                 goto out;
 683
 684         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 685         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 686         ret = intel_crt_ddc_get_modes(connector, i2c);
 687
 688 out:
 689         intel_display_power_put(dev_priv, power_domain);
 690
 691         return ret;
 692 }
 693
 694 static int intel_crt_set_property(struct drm_connector *connector,
 695                                   struct drm_property *property,
 696                                   uint64_t value)
 697 {
 698         return 0;
 699 }
 700
 701 static void intel_crt_reset(struct drm_connector *connector)
 702 {
 703         struct drm_device *dev = connector->dev;
 704         struct drm_i915_private *dev_priv = dev->dev_private;
 705         struct intel_crt *crt = intel_attached_crt(connector);
 706
 707         if (INTEL_INFO(dev)->gen >= 5) {
 708                 u32 adpa;
 709
 710                 adpa = I915_READ(crt->adpa_reg);
 711                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 712                 adpa |= ADPA_HOTPLUG_BITS;
 713                 I915_WRITE(crt->adpa_reg, adpa);
 714                 POSTING_READ(crt->adpa_reg);
 715
 716                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 717                 crt->force_hotplug_required = 1;
 718         }
 719
 720 }
 721
 722 /*
 723  * Routines for controlling stuff on the analog port
 724  */
 725
 726 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 727         .reset = intel_crt_reset,
 728         .dpms = drm_atomic_helper_connector_dpms,
 729         .detect = intel_crt_detect,
 730         .fill_modes = drm_helper_probe_single_connector_modes,
 731         .destroy = intel_crt_destroy,
 732         .set_property = intel_crt_set_property,
 733         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 734         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 735         .atomic_get_property = intel_connector_atomic_get_property,
 736 };
 737
 738 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 739         .mode_valid = intel_crt_mode_valid,
 740         .get_modes = intel_crt_get_modes,
 741         .best_encoder = intel_best_encoder,
 742 };
 743
 744 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 745         .destroy = intel_encoder_destroy,
 746 };
 747
 748 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
 749 {
 750         DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
 751         return 1;
 752 }
 753
 754 static const struct dmi_system_id intel_no_crt[] = {
 755         {
 756                 .callback = intel_no_crt_dmi_callback,
 757                 .ident = "ACER ZGB",
 758                 .matches = {
 759                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 760                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 761                 },
 762         },
 763         {
 764                 .callback = intel_no_crt_dmi_callback,
 765                 .ident = "DELL XPS 8700",
 766                 .matches = {
 767                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 768                         DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
 769                 },
 770         },
 771         { }
 772 };
 773
 774 void intel_crt_init(struct drm_device *dev)
 775 {
 776         struct drm_connector *connector;
 777         struct intel_crt *crt;
 778         struct intel_connector *intel_connector;
 779         struct drm_i915_private *dev_priv = dev->dev_private;
 780
 781         /* Skip machines without VGA that falsely report hotplug events */
 782         if (dmi_check_system(intel_no_crt))
 783                 return;
 784
 785         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 786         if (!crt)
 787                 return;
 788
 789         intel_connector = intel_connector_alloc();
 790         if (!intel_connector) {
 791                 kfree(crt);
 792                 return;
 793         }
 794
 795         connector = &intel_connector->base;
 796         crt->connector = intel_connector;
 797         drm_connector_init(dev, &intel_connector->base,
 798                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 799
 800         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
 801                          DRM_MODE_ENCODER_DAC);
 802
 803         intel_connector_attach_encoder(intel_connector, &crt->base);
 804
 805         crt->base.type = INTEL_OUTPUT_ANALOG;
 806         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 807         if (IS_I830(dev))
 808                 crt->base.crtc_mask = (1 << 0);
 809         else
 810                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 811
 812         if (IS_GEN2(dev))
 813                 connector->interlace_allowed = 0;
 814         else
 815                 connector->interlace_allowed = 1;
 816         connector->doublescan_allowed = 0;
 817
 818         if (HAS_PCH_SPLIT(dev))
 819                 crt->adpa_reg = PCH_ADPA;
 820         else if (IS_VALLEYVIEW(dev))
 821                 crt->adpa_reg = VLV_ADPA;
 822         else
 823                 crt->adpa_reg = ADPA;
 824
 825         crt->base.compute_config = intel_crt_compute_config;
 826         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) {
 827                 crt->base.disable = pch_disable_crt;
 828                 crt->base.post_disable = pch_post_disable_crt;
 829         } else {
 830                 crt->base.disable = intel_disable_crt;
 831         }
 832         crt->base.enable = intel_enable_crt;
 833         if (I915_HAS_HOTPLUG(dev))
 834                 crt->base.hpd_pin = HPD_CRT;
 835         if (HAS_DDI(dev)) {
 836                 crt->base.get_config = hsw_crt_get_config;
 837                 crt->base.get_hw_state = intel_ddi_get_hw_state;
 838         } else {
 839                 crt->base.get_config = intel_crt_get_config;
 840                 crt->base.get_hw_state = intel_crt_get_hw_state;
 841         }
 842         intel_connector->get_hw_state = intel_connector_get_hw_state;
 843         intel_connector->unregister = intel_connector_unregister;
 844
 845         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 846
 847         drm_connector_register(connector);
 848
 849         if (!I915_HAS_HOTPLUG(dev))
 850                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 851
 852         /*
 853          * Configure the automatic hotplug detection stuff
 854          */
 855         crt->force_hotplug_required = 0;
 856
 857         /*
 858          * TODO: find a proper way to discover whether we need to set the the
 859          * polarity and link reversal bits or not, instead of relying on the
 860          * BIOS.
 861          */
 862         if (HAS_PCH_LPT(dev)) {
 863                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
 864                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
 865
 866                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
 867         }
 868
 869         intel_crt_reset(connector);
 870 }