drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         i915_reg_t adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67                                    enum pipe *pipe)
  68 {
  69         struct drm_device *dev = encoder->base.dev;
  70         struct drm_i915_private *dev_priv = to_i915(dev);
  71         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72         u32 tmp;
  73         bool ret;
  74
  75         if (!intel_display_power_get_if_enabled(dev_priv,
  76                                                 encoder->power_domain))
  77                 return false;
  78
  79         ret = false;
  80
  81         tmp = I915_READ(crt->adpa_reg);
  82
  83         if (!(tmp & ADPA_DAC_ENABLE))
  84                 goto out;
  85
  86         if (HAS_PCH_CPT(dev_priv))
  87                 *pipe = PORT_TO_PIPE_CPT(tmp);
  88         else
  89                 *pipe = PORT_TO_PIPE(tmp);
  90
  91         ret = true;
  92 out:
  93         intel_display_power_put(dev_priv, encoder->power_domain);
  94
  95         return ret;
  96 }
  97
  98 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
  99 {
 100         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 101         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 102         u32 tmp, flags = 0;
 103
 104         tmp = I915_READ(crt->adpa_reg);
 105
 106         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 107                 flags |= DRM_MODE_FLAG_PHSYNC;
 108         else
 109                 flags |= DRM_MODE_FLAG_NHSYNC;
 110
 111         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 112                 flags |= DRM_MODE_FLAG_PVSYNC;
 113         else
 114                 flags |= DRM_MODE_FLAG_NVSYNC;
 115
 116         return flags;
 117 }
 118
 119 static void intel_crt_get_config(struct intel_encoder *encoder,
 120                                  struct intel_crtc_state *pipe_config)
 121 {
 122         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 123
 124         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 125 }
 126
 127 static void hsw_crt_get_config(struct intel_encoder *encoder,
 128                                struct intel_crtc_state *pipe_config)
 129 {
 130         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 131
 132         intel_ddi_get_config(encoder, pipe_config);
 133
 134         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 135                                               DRM_MODE_FLAG_NHSYNC |
 136                                               DRM_MODE_FLAG_PVSYNC |
 137                                               DRM_MODE_FLAG_NVSYNC);
 138         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 139
 140         pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 141 }
 142
 143 /* Note: The caller is required to filter out dpms modes not supported by the
 144  * platform. */
 145 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 146                                const struct intel_crtc_state *crtc_state,
 147                                int mode)
 148 {
 149         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 150         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 151         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 152         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 153         u32 adpa;
 154
 155         if (INTEL_GEN(dev_priv) >= 5)
 156                 adpa = ADPA_HOTPLUG_BITS;
 157         else
 158                 adpa = 0;
 159
 160         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 161                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 162         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 163                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 164
 165         /* For CPT allow 3 pipe config, for others just use A or B */
 166         if (HAS_PCH_LPT(dev_priv))
 167                 ; /* Those bits don't exist here */
 168         else if (HAS_PCH_CPT(dev_priv))
 169                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
 170         else if (crtc->pipe == 0)
 171                 adpa |= ADPA_PIPE_A_SELECT;
 172         else
 173                 adpa |= ADPA_PIPE_B_SELECT;
 174
 175         if (!HAS_PCH_SPLIT(dev_priv))
 176                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 177
 178         switch (mode) {
 179         case DRM_MODE_DPMS_ON:
 180                 adpa |= ADPA_DAC_ENABLE;
 181                 break;
 182         case DRM_MODE_DPMS_STANDBY:
 183                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 184                 break;
 185         case DRM_MODE_DPMS_SUSPEND:
 186                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 187                 break;
 188         case DRM_MODE_DPMS_OFF:
 189                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 190                 break;
 191         }
 192
 193         I915_WRITE(crt->adpa_reg, adpa);
 194 }
 195
 196 static void intel_disable_crt(struct intel_encoder *encoder,
 197                               const struct intel_crtc_state *old_crtc_state,
 198                               const struct drm_connector_state *old_conn_state)
 199 {
 200         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 201 }
 202
 203 static void pch_disable_crt(struct intel_encoder *encoder,
 204                             const struct intel_crtc_state *old_crtc_state,
 205                             const struct drm_connector_state *old_conn_state)
 206 {
 207 }
 208
 209 static void pch_post_disable_crt(struct intel_encoder *encoder,
 210                                  const struct intel_crtc_state *old_crtc_state,
 211                                  const struct drm_connector_state *old_conn_state)
 212 {
 213         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 214 }
 215
 216 static void hsw_disable_crt(struct intel_encoder *encoder,
 217                             const struct intel_crtc_state *old_crtc_state,
 218                             const struct drm_connector_state *old_conn_state)
 219 {
 220         struct drm_crtc *crtc = old_crtc_state->base.crtc;
 221         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 223
 224         WARN_ON(!intel_crtc->config->has_pch_encoder);
 225
 226         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 227 }
 228
 229 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 230                                  const struct intel_crtc_state *old_crtc_state,
 231                                  const struct drm_connector_state *old_conn_state)
 232 {
 233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 234
 235         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 236
 237         lpt_disable_pch_transcoder(dev_priv);
 238         lpt_disable_iclkip(dev_priv);
 239
 240         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 241
 242         WARN_ON(!old_crtc_state->has_pch_encoder);
 243
 244         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 245 }
 246
 247 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
 248                                    const struct intel_crtc_state *pipe_config,
 249                                    const struct drm_connector_state *conn_state)
 250 {
 251         struct drm_crtc *crtc = pipe_config->base.crtc;
 252         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 254
 255         WARN_ON(!intel_crtc->config->has_pch_encoder);
 256
 257         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 258 }
 259
 260 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 261                                const struct intel_crtc_state *pipe_config,
 262                                const struct drm_connector_state *conn_state)
 263 {
 264         struct drm_crtc *crtc = pipe_config->base.crtc;
 265         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 267         int pipe = intel_crtc->pipe;
 268
 269         WARN_ON(!intel_crtc->config->has_pch_encoder);
 270
 271         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 272
 273         dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
 274 }
 275
 276 static void hsw_enable_crt(struct intel_encoder *encoder,
 277                            const struct intel_crtc_state *pipe_config,
 278                            const struct drm_connector_state *conn_state)
 279 {
 280         struct drm_crtc *crtc = pipe_config->base.crtc;
 281         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 283         int pipe = intel_crtc->pipe;
 284
 285         WARN_ON(!intel_crtc->config->has_pch_encoder);
 286
 287         intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON);
 288
 289         intel_wait_for_vblank(dev_priv, pipe);
 290         intel_wait_for_vblank(dev_priv, pipe);
 291         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 292         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 293 }
 294
 295 static void intel_enable_crt(struct intel_encoder *encoder,
 296                              const struct intel_crtc_state *pipe_config,
 297                              const struct drm_connector_state *conn_state)
 298 {
 299         intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON);
 300 }
 301
 302 static enum drm_mode_status
 303 intel_crt_mode_valid(struct drm_connector *connector,
 304                      struct drm_display_mode *mode)
 305 {
 306         struct drm_device *dev = connector->dev;
 307         struct drm_i915_private *dev_priv = to_i915(dev);
 308         int max_dotclk = dev_priv->max_dotclk_freq;
 309         int max_clock;
 310
 311         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 312                 return MODE_NO_DBLESCAN;
 313
 314         if (mode->clock < 25000)
 315                 return MODE_CLOCK_LOW;
 316
 317         if (HAS_PCH_LPT(dev_priv))
 318                 max_clock = 180000;
 319         else if (IS_VALLEYVIEW(dev_priv))
 320                 /*
 321                  * 270 MHz due to current DPLL limits,
 322                  * DAC limit supposedly 355 MHz.
 323                  */
 324                 max_clock = 270000;
 325         else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
 326                 max_clock = 400000;
 327         else
 328                 max_clock = 350000;
 329         if (mode->clock > max_clock)
 330                 return MODE_CLOCK_HIGH;
 331
 332         if (mode->clock > max_dotclk)
 333                 return MODE_CLOCK_HIGH;
 334
 335         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 336         if (HAS_PCH_LPT(dev_priv) &&
 337             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 338                 return MODE_CLOCK_HIGH;
 339
 340         return MODE_OK;
 341 }
 342
 343 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 344                                      struct intel_crtc_state *pipe_config,
 345                                      struct drm_connector_state *conn_state)
 346 {
 347         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 348
 349         if (HAS_PCH_SPLIT(dev_priv))
 350                 pipe_config->has_pch_encoder = true;
 351
 352         /* LPT FDI RX only supports 8bpc. */
 353         if (HAS_PCH_LPT(dev_priv)) {
 354                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 355                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 356                         return false;
 357                 }
 358
 359                 pipe_config->pipe_bpp = 24;
 360         }
 361
 362         /* FDI must always be 2.7 GHz */
 363         if (HAS_DDI(dev_priv))
 364                 pipe_config->port_clock = 135000 * 2;
 365
 366         return true;
 367 }
 368
 369 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 370 {
 371         struct drm_device *dev = connector->dev;
 372         struct intel_crt *crt = intel_attached_crt(connector);
 373         struct drm_i915_private *dev_priv = to_i915(dev);
 374         u32 adpa;
 375         bool ret;
 376
 377         /* The first time through, trigger an explicit detection cycle */
 378         if (crt->force_hotplug_required) {
 379                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 380                 u32 save_adpa;
 381
 382                 crt->force_hotplug_required = 0;
 383
 384                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 385                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 386
 387                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 388                 if (turn_off_dac)
 389                         adpa &= ~ADPA_DAC_ENABLE;
 390
 391                 I915_WRITE(crt->adpa_reg, adpa);
 392
 393                 if (intel_wait_for_register(dev_priv,
 394                                             crt->adpa_reg,
 395                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 396                                             1000))
 397                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 398
 399                 if (turn_off_dac) {
 400                         I915_WRITE(crt->adpa_reg, save_adpa);
 401                         POSTING_READ(crt->adpa_reg);
 402                 }
 403         }
 404
 405         /* Check the status to see if both blue and green are on now */
 406         adpa = I915_READ(crt->adpa_reg);
 407         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 408                 ret = true;
 409         else
 410                 ret = false;
 411         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 412
 413         return ret;
 414 }
 415
 416 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 417 {
 418         struct drm_device *dev = connector->dev;
 419         struct intel_crt *crt = intel_attached_crt(connector);
 420         struct drm_i915_private *dev_priv = to_i915(dev);
 421         bool reenable_hpd;
 422         u32 adpa;
 423         bool ret;
 424         u32 save_adpa;
 425
 426         /*
 427          * Doing a force trigger causes a hpd interrupt to get sent, which can
 428          * get us stuck in a loop if we're polling:
 429          *  - We enable power wells and reset the ADPA
 430          *  - output_poll_exec does force probe on VGA, triggering a hpd
 431          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 432          *  - output_poll_exec shuts off the ADPA, unlocks
 433          *    dev->mode_config.mutex
 434          *  - HPD handler runs, resets ADPA and brings us back to the start
 435          *
 436          * Just disable HPD interrupts here to prevent this
 437          */
 438         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 439
 440         save_adpa = adpa = I915_READ(crt->adpa_reg);
 441         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 442
 443         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 444
 445         I915_WRITE(crt->adpa_reg, adpa);
 446
 447         if (intel_wait_for_register(dev_priv,
 448                                     crt->adpa_reg,
 449                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 450                                     1000)) {
 451                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 452                 I915_WRITE(crt->adpa_reg, save_adpa);
 453         }
 454
 455         /* Check the status to see if both blue and green are on now */
 456         adpa = I915_READ(crt->adpa_reg);
 457         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 458                 ret = true;
 459         else
 460                 ret = false;
 461
 462         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 463
 464         if (reenable_hpd)
 465                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 466
 467         return ret;
 468 }
 469
 470 /**
 471  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 472  *
 473  * Not for i915G/i915GM
 474  *
 475  * \return true if CRT is connected.
 476  * \return false if CRT is disconnected.
 477  */
 478 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 479 {
 480         struct drm_device *dev = connector->dev;
 481         struct drm_i915_private *dev_priv = to_i915(dev);
 482         u32 stat;
 483         bool ret = false;
 484         int i, tries = 0;
 485
 486         if (HAS_PCH_SPLIT(dev_priv))
 487                 return intel_ironlake_crt_detect_hotplug(connector);
 488
 489         if (IS_VALLEYVIEW(dev_priv))
 490                 return valleyview_crt_detect_hotplug(connector);
 491
 492         /*
 493          * On 4 series desktop, CRT detect sequence need to be done twice
 494          * to get a reliable result.
 495          */
 496
 497         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv))
 498                 tries = 2;
 499         else
 500                 tries = 1;
 501
 502         for (i = 0; i < tries ; i++) {
 503                 /* turn on the FORCE_DETECT */
 504                 i915_hotplug_interrupt_update(dev_priv,
 505                                               CRT_HOTPLUG_FORCE_DETECT,
 506                                               CRT_HOTPLUG_FORCE_DETECT);
 507                 /* wait for FORCE_DETECT to go off */
 508                 if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
 509                                             CRT_HOTPLUG_FORCE_DETECT, 0,
 510                                             1000))
 511                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 512         }
 513
 514         stat = I915_READ(PORT_HOTPLUG_STAT);
 515         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 516                 ret = true;
 517
 518         /* clear the interrupt we just generated, if any */
 519         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 520
 521         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 522
 523         return ret;
 524 }
 525
 526 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 527                                 struct i2c_adapter *i2c)
 528 {
 529         struct edid *edid;
 530
 531         edid = drm_get_edid(connector, i2c);
 532
 533         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 534                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 535                 intel_gmbus_force_bit(i2c, true);
 536                 edid = drm_get_edid(connector, i2c);
 537                 intel_gmbus_force_bit(i2c, false);
 538         }
 539
 540         return edid;
 541 }
 542
 543 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 544 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 545                                 struct i2c_adapter *adapter)
 546 {
 547         struct edid *edid;
 548         int ret;
 549
 550         edid = intel_crt_get_edid(connector, adapter);
 551         if (!edid)
 552                 return 0;
 553
 554         ret = intel_connector_update_modes(connector, edid);
 555         kfree(edid);
 556
 557         return ret;
 558 }
 559
 560 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 561 {
 562         struct intel_crt *crt = intel_attached_crt(connector);
 563         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 564         struct edid *edid;
 565         struct i2c_adapter *i2c;
 566         bool ret = false;
 567
 568         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 569
 570         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 571         edid = intel_crt_get_edid(connector, i2c);
 572
 573         if (edid) {
 574                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 575
 576                 /*
 577                  * This may be a DVI-I connector with a shared DDC
 578                  * link between analog and digital outputs, so we
 579                  * have to check the EDID input spec of the attached device.
 580                  */
 581                 if (!is_digital) {
 582                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 583                         ret = true;
 584                 } else {
 585                         DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 586                 }
 587         } else {
 588                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 589         }
 590
 591         kfree(edid);
 592
 593         return ret;
 594 }
 595
 596 static enum drm_connector_status
 597 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
 598 {
 599         struct drm_device *dev = crt->base.base.dev;
 600         struct drm_i915_private *dev_priv = to_i915(dev);
 601         uint32_t save_bclrpat;
 602         uint32_t save_vtotal;
 603         uint32_t vtotal, vactive;
 604         uint32_t vsample;
 605         uint32_t vblank, vblank_start, vblank_end;
 606         uint32_t dsl;
 607         i915_reg_t bclrpat_reg, vtotal_reg,
 608                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 609         uint8_t st00;
 610         enum drm_connector_status status;
 611
 612         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 613
 614         bclrpat_reg = BCLRPAT(pipe);
 615         vtotal_reg = VTOTAL(pipe);
 616         vblank_reg = VBLANK(pipe);
 617         vsync_reg = VSYNC(pipe);
 618         pipeconf_reg = PIPECONF(pipe);
 619         pipe_dsl_reg = PIPEDSL(pipe);
 620
 621         save_bclrpat = I915_READ(bclrpat_reg);
 622         save_vtotal = I915_READ(vtotal_reg);
 623         vblank = I915_READ(vblank_reg);
 624
 625         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 626         vactive = (save_vtotal & 0x7ff) + 1;
 627
 628         vblank_start = (vblank & 0xfff) + 1;
 629         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 630
 631         /* Set the border color to purple. */
 632         I915_WRITE(bclrpat_reg, 0x500050);
 633
 634         if (!IS_GEN2(dev_priv)) {
 635                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 636                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 637                 POSTING_READ(pipeconf_reg);
 638                 /* Wait for next Vblank to substitue
 639                  * border color for Color info */
 640                 intel_wait_for_vblank(dev_priv, pipe);
 641                 st00 = I915_READ8(_VGA_MSR_WRITE);
 642                 status = ((st00 & (1 << 4)) != 0) ?
 643                         connector_status_connected :
 644                         connector_status_disconnected;
 645
 646                 I915_WRITE(pipeconf_reg, pipeconf);
 647         } else {
 648                 bool restore_vblank = false;
 649                 int count, detect;
 650
 651                 /*
 652                 * If there isn't any border, add some.
 653                 * Yes, this will flicker
 654                 */
 655                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 656                         uint32_t vsync = I915_READ(vsync_reg);
 657                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 658
 659                         vblank_start = vsync_start;
 660                         I915_WRITE(vblank_reg,
 661                                    (vblank_start - 1) |
 662                                    ((vblank_end - 1) << 16));
 663                         restore_vblank = true;
 664                 }
 665                 /* sample in the vertical border, selecting the larger one */
 666                 if (vblank_start - vactive >= vtotal - vblank_end)
 667                         vsample = (vblank_start + vactive) >> 1;
 668                 else
 669                         vsample = (vtotal + vblank_end) >> 1;
 670
 671                 /*
 672                  * Wait for the border to be displayed
 673                  */
 674                 while (I915_READ(pipe_dsl_reg) >= vactive)
 675                         ;
 676                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 677                         ;
 678                 /*
 679                  * Watch ST00 for an entire scanline
 680                  */
 681                 detect = 0;
 682                 count = 0;
 683                 do {
 684                         count++;
 685                         /* Read the ST00 VGA status register */
 686                         st00 = I915_READ8(_VGA_MSR_WRITE);
 687                         if (st00 & (1 << 4))
 688                                 detect++;
 689                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 690
 691                 /* restore vblank if necessary */
 692                 if (restore_vblank)
 693                         I915_WRITE(vblank_reg, vblank);
 694                 /*
 695                  * If more than 3/4 of the scanline detected a monitor,
 696                  * then it is assumed to be present. This works even on i830,
 697                  * where there isn't any way to force the border color across
 698                  * the screen
 699                  */
 700                 status = detect * 4 > count * 3 ?
 701                          connector_status_connected :
 702                          connector_status_disconnected;
 703         }
 704
 705         /* Restore previous settings */
 706         I915_WRITE(bclrpat_reg, save_bclrpat);
 707
 708         return status;
 709 }
 710
 711 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 712 {
 713         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 714         return 1;
 715 }
 716
 717 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 718         {
 719                 .callback = intel_spurious_crt_detect_dmi_callback,
 720                 .ident = "ACER ZGB",
 721                 .matches = {
 722                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 723                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 724                 },
 725         },
 726         {
 727                 .callback = intel_spurious_crt_detect_dmi_callback,
 728                 .ident = "Intel DZ77BH-55K",
 729                 .matches = {
 730                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 731                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 732                 },
 733         },
 734         { }
 735 };
 736
 737 static int
 738 intel_crt_detect(struct drm_connector *connector,
 739                  struct drm_modeset_acquire_ctx *ctx,
 740                  bool force)
 741 {
 742         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 743         struct intel_crt *crt = intel_attached_crt(connector);
 744         struct intel_encoder *intel_encoder = &crt->base;
 745         int status, ret;
 746         struct intel_load_detect_pipe tmp;
 747
 748         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 749                       connector->base.id, connector->name,
 750                       force);
 751
 752         /* Skip machines without VGA that falsely report hotplug events */
 753         if (dmi_check_system(intel_spurious_crt_detect))
 754                 return connector_status_disconnected;
 755
 756         intel_display_power_get(dev_priv, intel_encoder->power_domain);
 757
 758         if (I915_HAS_HOTPLUG(dev_priv)) {
 759                 /* We can not rely on the HPD pin always being correctly wired
 760                  * up, for example many KVM do not pass it through, and so
 761                  * only trust an assertion that the monitor is connected.
 762                  */
 763                 if (intel_crt_detect_hotplug(connector)) {
 764                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 765                         status = connector_status_connected;
 766                         goto out;
 767                 } else
 768                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 769         }
 770
 771         if (intel_crt_detect_ddc(connector)) {
 772                 status = connector_status_connected;
 773                 goto out;
 774         }
 775
 776         /* Load detection is broken on HPD capable machines. Whoever wants a
 777          * broken monitor (without edid) to work behind a broken kvm (that fails
 778          * to have the right resistors for HP detection) needs to fix this up.
 779          * For now just bail out. */
 780         if (I915_HAS_HOTPLUG(dev_priv) && !i915_modparams.load_detect_test) {
 781                 status = connector_status_disconnected;
 782                 goto out;
 783         }
 784
 785         if (!force) {
 786                 status = connector->status;
 787                 goto out;
 788         }
 789
 790         /* for pre-945g platforms use load detect */
 791         ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
 792         if (ret > 0) {
 793                 if (intel_crt_detect_ddc(connector))
 794                         status = connector_status_connected;
 795                 else if (INTEL_GEN(dev_priv) < 4)
 796                         status = intel_crt_load_detect(crt,
 797                                 to_intel_crtc(connector->state->crtc)->pipe);
 798                 else if (i915_modparams.load_detect_test)
 799                         status = connector_status_disconnected;
 800                 else
 801                         status = connector_status_unknown;
 802                 intel_release_load_detect_pipe(connector, &tmp, ctx);
 803         } else if (ret == 0)
 804                 status = connector_status_unknown;
 805         else if (ret < 0)
 806                 status = ret;
 807
 808 out:
 809         intel_display_power_put(dev_priv, intel_encoder->power_domain);
 810         return status;
 811 }
 812
 813 static void intel_crt_destroy(struct drm_connector *connector)
 814 {
 815         drm_connector_cleanup(connector);
 816         kfree(connector);
 817 }
 818
 819 static int intel_crt_get_modes(struct drm_connector *connector)
 820 {
 821         struct drm_device *dev = connector->dev;
 822         struct drm_i915_private *dev_priv = to_i915(dev);
 823         struct intel_crt *crt = intel_attached_crt(connector);
 824         struct intel_encoder *intel_encoder = &crt->base;
 825         int ret;
 826         struct i2c_adapter *i2c;
 827
 828         intel_display_power_get(dev_priv, intel_encoder->power_domain);
 829
 830         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 831         ret = intel_crt_ddc_get_modes(connector, i2c);
 832         if (ret || !IS_G4X(dev_priv))
 833                 goto out;
 834
 835         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 836         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 837         ret = intel_crt_ddc_get_modes(connector, i2c);
 838
 839 out:
 840         intel_display_power_put(dev_priv, intel_encoder->power_domain);
 841
 842         return ret;
 843 }
 844
 845 void intel_crt_reset(struct drm_encoder *encoder)
 846 {
 847         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 848         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 849
 850         if (INTEL_GEN(dev_priv) >= 5) {
 851                 u32 adpa;
 852
 853                 adpa = I915_READ(crt->adpa_reg);
 854                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 855                 adpa |= ADPA_HOTPLUG_BITS;
 856                 I915_WRITE(crt->adpa_reg, adpa);
 857                 POSTING_READ(crt->adpa_reg);
 858
 859                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 860                 crt->force_hotplug_required = 1;
 861         }
 862
 863 }
 864
 865 /*
 866  * Routines for controlling stuff on the analog port
 867  */
 868
 869 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 870         .fill_modes = drm_helper_probe_single_connector_modes,
 871         .late_register = intel_connector_register,
 872         .early_unregister = intel_connector_unregister,
 873         .destroy = intel_crt_destroy,
 874         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 875         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 876 };
 877
 878 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 879         .detect_ctx = intel_crt_detect,
 880         .mode_valid = intel_crt_mode_valid,
 881         .get_modes = intel_crt_get_modes,
 882 };
 883
 884 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 885         .reset = intel_crt_reset,
 886         .destroy = intel_encoder_destroy,
 887 };
 888
 889 void intel_crt_init(struct drm_i915_private *dev_priv)
 890 {
 891         struct drm_connector *connector;
 892         struct intel_crt *crt;
 893         struct intel_connector *intel_connector;
 894         i915_reg_t adpa_reg;
 895         u32 adpa;
 896
 897         if (HAS_PCH_SPLIT(dev_priv))
 898                 adpa_reg = PCH_ADPA;
 899         else if (IS_VALLEYVIEW(dev_priv))
 900                 adpa_reg = VLV_ADPA;
 901         else
 902                 adpa_reg = ADPA;
 903
 904         adpa = I915_READ(adpa_reg);
 905         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 906                 /*
 907                  * On some machines (some IVB at least) CRT can be
 908                  * fused off, but there's no known fuse bit to
 909                  * indicate that. On these machine the ADPA register
 910                  * works normally, except the DAC enable bit won't
 911                  * take. So the only way to tell is attempt to enable
 912                  * it and see what happens.
 913                  */
 914                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 915                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 916                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 917                         return;
 918                 I915_WRITE(adpa_reg, adpa);
 919         }
 920
 921         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 922         if (!crt)
 923                 return;
 924
 925         intel_connector = intel_connector_alloc();
 926         if (!intel_connector) {
 927                 kfree(crt);
 928                 return;
 929         }
 930
 931         connector = &intel_connector->base;
 932         crt->connector = intel_connector;
 933         drm_connector_init(&dev_priv->drm, &intel_connector->base,
 934                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 935
 936         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
 937                          DRM_MODE_ENCODER_DAC, "CRT");
 938
 939         intel_connector_attach_encoder(intel_connector, &crt->base);
 940
 941         crt->base.type = INTEL_OUTPUT_ANALOG;
 942         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 943         if (IS_I830(dev_priv))
 944                 crt->base.crtc_mask = (1 << 0);
 945         else
 946                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 947
 948         if (IS_GEN2(dev_priv))
 949                 connector->interlace_allowed = 0;
 950         else
 951                 connector->interlace_allowed = 1;
 952         connector->doublescan_allowed = 0;
 953
 954         crt->adpa_reg = adpa_reg;
 955
 956         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
 957
 958         crt->base.compute_config = intel_crt_compute_config;
 959         if (HAS_PCH_SPLIT(dev_priv)) {
 960                 crt->base.disable = pch_disable_crt;
 961                 crt->base.post_disable = pch_post_disable_crt;
 962         } else {
 963                 crt->base.disable = intel_disable_crt;
 964         }
 965         if (I915_HAS_HOTPLUG(dev_priv) &&
 966             !dmi_check_system(intel_spurious_crt_detect))
 967                 crt->base.hpd_pin = HPD_CRT;
 968         if (HAS_DDI(dev_priv)) {
 969                 crt->base.port = PORT_E;
 970                 crt->base.get_config = hsw_crt_get_config;
 971                 crt->base.get_hw_state = intel_ddi_get_hw_state;
 972                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
 973                 crt->base.pre_enable = hsw_pre_enable_crt;
 974                 crt->base.enable = hsw_enable_crt;
 975                 crt->base.disable = hsw_disable_crt;
 976                 crt->base.post_disable = hsw_post_disable_crt;
 977         } else {
 978                 crt->base.port = PORT_NONE;
 979                 crt->base.get_config = intel_crt_get_config;
 980                 crt->base.get_hw_state = intel_crt_get_hw_state;
 981                 crt->base.enable = intel_enable_crt;
 982         }
 983         intel_connector->get_hw_state = intel_connector_get_hw_state;
 984
 985         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 986
 987         if (!I915_HAS_HOTPLUG(dev_priv))
 988                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 989
 990         /*
 991          * Configure the automatic hotplug detection stuff
 992          */
 993         crt->force_hotplug_required = 0;
 994
 995         /*
 996          * TODO: find a proper way to discover whether we need to set the the
 997          * polarity and link reversal bits or not, instead of relying on the
 998          * BIOS.
 999          */
1000         if (HAS_PCH_LPT(dev_priv)) {
1001                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1002                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1003
1004                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
1005         }
1006
1007         intel_crt_reset(&crt->base.base);
1008 }