drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         i915_reg_t adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67                                    enum pipe *pipe)
  68 {
  69         struct drm_device *dev = encoder->base.dev;
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72         enum intel_display_power_domain power_domain;
  73         u32 tmp;
  74         bool ret;
  75
  76         power_domain = intel_display_port_power_domain(encoder);
  77         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  78                 return false;
  79
  80         ret = false;
  81
  82         tmp = I915_READ(crt->adpa_reg);
  83
  84         if (!(tmp & ADPA_DAC_ENABLE))
  85                 goto out;
  86
  87         if (HAS_PCH_CPT(dev))
  88                 *pipe = PORT_TO_PIPE_CPT(tmp);
  89         else
  90                 *pipe = PORT_TO_PIPE(tmp);
  91
  92         ret = true;
  93 out:
  94         intel_display_power_put(dev_priv, power_domain);
  95
  96         return ret;
  97 }
  98
  99 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 100 {
 101         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 102         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 103         u32 tmp, flags = 0;
 104
 105         tmp = I915_READ(crt->adpa_reg);
 106
 107         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 108                 flags |= DRM_MODE_FLAG_PHSYNC;
 109         else
 110                 flags |= DRM_MODE_FLAG_NHSYNC;
 111
 112         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 113                 flags |= DRM_MODE_FLAG_PVSYNC;
 114         else
 115                 flags |= DRM_MODE_FLAG_NVSYNC;
 116
 117         return flags;
 118 }
 119
 120 static void intel_crt_get_config(struct intel_encoder *encoder,
 121                                  struct intel_crtc_state *pipe_config)
 122 {
 123         struct drm_device *dev = encoder->base.dev;
 124         int dotclock;
 125
 126         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 127
 128         dotclock = pipe_config->port_clock;
 129
 130         if (HAS_PCH_SPLIT(dev))
 131                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 132
 133         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 134 }
 135
 136 static void hsw_crt_get_config(struct intel_encoder *encoder,
 137                                struct intel_crtc_state *pipe_config)
 138 {
 139         intel_ddi_get_config(encoder, pipe_config);
 140
 141         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 142                                               DRM_MODE_FLAG_NHSYNC |
 143                                               DRM_MODE_FLAG_PVSYNC |
 144                                               DRM_MODE_FLAG_NVSYNC);
 145         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 146 }
 147
 148 /* Note: The caller is required to filter out dpms modes not supported by the
 149  * platform. */
 150 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
 151 {
 152         struct drm_device *dev = encoder->base.dev;
 153         struct drm_i915_private *dev_priv = dev->dev_private;
 154         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 155         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 156         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 157         u32 adpa;
 158
 159         if (INTEL_INFO(dev)->gen >= 5)
 160                 adpa = ADPA_HOTPLUG_BITS;
 161         else
 162                 adpa = 0;
 163
 164         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 165                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 166         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 167                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 168
 169         /* For CPT allow 3 pipe config, for others just use A or B */
 170         if (HAS_PCH_LPT(dev))
 171                 ; /* Those bits don't exist here */
 172         else if (HAS_PCH_CPT(dev))
 173                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
 174         else if (crtc->pipe == 0)
 175                 adpa |= ADPA_PIPE_A_SELECT;
 176         else
 177                 adpa |= ADPA_PIPE_B_SELECT;
 178
 179         if (!HAS_PCH_SPLIT(dev))
 180                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 181
 182         switch (mode) {
 183         case DRM_MODE_DPMS_ON:
 184                 adpa |= ADPA_DAC_ENABLE;
 185                 break;
 186         case DRM_MODE_DPMS_STANDBY:
 187                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 188                 break;
 189         case DRM_MODE_DPMS_SUSPEND:
 190                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 191                 break;
 192         case DRM_MODE_DPMS_OFF:
 193                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 194                 break;
 195         }
 196
 197         I915_WRITE(crt->adpa_reg, adpa);
 198 }
 199
 200 static void intel_disable_crt(struct intel_encoder *encoder)
 201 {
 202         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
 203 }
 204
 205 static void pch_disable_crt(struct intel_encoder *encoder)
 206 {
 207 }
 208
 209 static void pch_post_disable_crt(struct intel_encoder *encoder)
 210 {
 211         intel_disable_crt(encoder);
 212 }
 213
 214 static void intel_enable_crt(struct intel_encoder *encoder)
 215 {
 216         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 217
 218         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
 219 }
 220
 221 static enum drm_mode_status
 222 intel_crt_mode_valid(struct drm_connector *connector,
 223                      struct drm_display_mode *mode)
 224 {
 225         struct drm_device *dev = connector->dev;
 226
 227         int max_clock = 0;
 228         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 229                 return MODE_NO_DBLESCAN;
 230
 231         if (mode->clock < 25000)
 232                 return MODE_CLOCK_LOW;
 233
 234         if (IS_GEN2(dev))
 235                 max_clock = 350000;
 236         else
 237                 max_clock = 400000;
 238         if (mode->clock > max_clock)
 239                 return MODE_CLOCK_HIGH;
 240
 241         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 242         if (HAS_PCH_LPT(dev) &&
 243             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 244                 return MODE_CLOCK_HIGH;
 245
 246         return MODE_OK;
 247 }
 248
 249 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 250                                      struct intel_crtc_state *pipe_config)
 251 {
 252         struct drm_device *dev = encoder->base.dev;
 253
 254         if (HAS_PCH_SPLIT(dev))
 255                 pipe_config->has_pch_encoder = true;
 256
 257         /* LPT FDI RX only supports 8bpc. */
 258         if (HAS_PCH_LPT(dev))
 259                 pipe_config->pipe_bpp = 24;
 260
 261         /* FDI must always be 2.7 GHz */
 262         if (HAS_DDI(dev)) {
 263                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
 264                 pipe_config->port_clock = 135000 * 2;
 265
 266                 pipe_config->dpll_hw_state.wrpll = 0;
 267                 pipe_config->dpll_hw_state.spll =
 268                         SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
 269         }
 270
 271         return true;
 272 }
 273
 274 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 275 {
 276         struct drm_device *dev = connector->dev;
 277         struct intel_crt *crt = intel_attached_crt(connector);
 278         struct drm_i915_private *dev_priv = dev->dev_private;
 279         u32 adpa;
 280         bool ret;
 281
 282         /* The first time through, trigger an explicit detection cycle */
 283         if (crt->force_hotplug_required) {
 284                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
 285                 u32 save_adpa;
 286
 287                 crt->force_hotplug_required = 0;
 288
 289                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 290                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 291
 292                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 293                 if (turn_off_dac)
 294                         adpa &= ~ADPA_DAC_ENABLE;
 295
 296                 I915_WRITE(crt->adpa_reg, adpa);
 297
 298                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 299                              1000))
 300                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 301
 302                 if (turn_off_dac) {
 303                         I915_WRITE(crt->adpa_reg, save_adpa);
 304                         POSTING_READ(crt->adpa_reg);
 305                 }
 306         }
 307
 308         /* Check the status to see if both blue and green are on now */
 309         adpa = I915_READ(crt->adpa_reg);
 310         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 311                 ret = true;
 312         else
 313                 ret = false;
 314         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 315
 316         return ret;
 317 }
 318
 319 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 320 {
 321         struct drm_device *dev = connector->dev;
 322         struct intel_crt *crt = intel_attached_crt(connector);
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324         u32 adpa;
 325         bool ret;
 326         u32 save_adpa;
 327
 328         save_adpa = adpa = I915_READ(crt->adpa_reg);
 329         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 330
 331         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 332
 333         I915_WRITE(crt->adpa_reg, adpa);
 334
 335         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
 336                      1000)) {
 337                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 338                 I915_WRITE(crt->adpa_reg, save_adpa);
 339         }
 340
 341         /* Check the status to see if both blue and green are on now */
 342         adpa = I915_READ(crt->adpa_reg);
 343         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 344                 ret = true;
 345         else
 346                 ret = false;
 347
 348         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 349
 350         return ret;
 351 }
 352
 353 /**
 354  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 355  *
 356  * Not for i915G/i915GM
 357  *
 358  * \return true if CRT is connected.
 359  * \return false if CRT is disconnected.
 360  */
 361 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 362 {
 363         struct drm_device *dev = connector->dev;
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365         u32 stat;
 366         bool ret = false;
 367         int i, tries = 0;
 368
 369         if (HAS_PCH_SPLIT(dev))
 370                 return intel_ironlake_crt_detect_hotplug(connector);
 371
 372         if (IS_VALLEYVIEW(dev))
 373                 return valleyview_crt_detect_hotplug(connector);
 374
 375         /*
 376          * On 4 series desktop, CRT detect sequence need to be done twice
 377          * to get a reliable result.
 378          */
 379
 380         if (IS_G4X(dev) && !IS_GM45(dev))
 381                 tries = 2;
 382         else
 383                 tries = 1;
 384
 385         for (i = 0; i < tries ; i++) {
 386                 /* turn on the FORCE_DETECT */
 387                 i915_hotplug_interrupt_update(dev_priv,
 388                                               CRT_HOTPLUG_FORCE_DETECT,
 389                                               CRT_HOTPLUG_FORCE_DETECT);
 390                 /* wait for FORCE_DETECT to go off */
 391                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
 392                               CRT_HOTPLUG_FORCE_DETECT) == 0,
 393                              1000))
 394                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 395         }
 396
 397         stat = I915_READ(PORT_HOTPLUG_STAT);
 398         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 399                 ret = true;
 400
 401         /* clear the interrupt we just generated, if any */
 402         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 403
 404         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 405
 406         return ret;
 407 }
 408
 409 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 410                                 struct i2c_adapter *i2c)
 411 {
 412         struct edid *edid;
 413
 414         edid = drm_get_edid(connector, i2c);
 415
 416         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 417                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 418                 intel_gmbus_force_bit(i2c, true);
 419                 edid = drm_get_edid(connector, i2c);
 420                 intel_gmbus_force_bit(i2c, false);
 421         }
 422
 423         return edid;
 424 }
 425
 426 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 427 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 428                                 struct i2c_adapter *adapter)
 429 {
 430         struct edid *edid;
 431         int ret;
 432
 433         edid = intel_crt_get_edid(connector, adapter);
 434         if (!edid)
 435                 return 0;
 436
 437         ret = intel_connector_update_modes(connector, edid);
 438         kfree(edid);
 439
 440         return ret;
 441 }
 442
 443 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 444 {
 445         struct intel_crt *crt = intel_attached_crt(connector);
 446         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
 447         struct edid *edid;
 448         struct i2c_adapter *i2c;
 449
 450         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 451
 452         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 453         edid = intel_crt_get_edid(connector, i2c);
 454
 455         if (edid) {
 456                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 457
 458                 /*
 459                  * This may be a DVI-I connector with a shared DDC
 460                  * link between analog and digital outputs, so we
 461                  * have to check the EDID input spec of the attached device.
 462                  */
 463                 if (!is_digital) {
 464                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 465                         return true;
 466                 }
 467
 468                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 469         } else {
 470                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 471         }
 472
 473         kfree(edid);
 474
 475         return false;
 476 }
 477
 478 static enum drm_connector_status
 479 intel_crt_load_detect(struct intel_crt *crt)
 480 {
 481         struct drm_device *dev = crt->base.base.dev;
 482         struct drm_i915_private *dev_priv = dev->dev_private;
 483         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
 484         uint32_t save_bclrpat;
 485         uint32_t save_vtotal;
 486         uint32_t vtotal, vactive;
 487         uint32_t vsample;
 488         uint32_t vblank, vblank_start, vblank_end;
 489         uint32_t dsl;
 490         i915_reg_t bclrpat_reg, vtotal_reg,
 491                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 492         uint8_t st00;
 493         enum drm_connector_status status;
 494
 495         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 496
 497         bclrpat_reg = BCLRPAT(pipe);
 498         vtotal_reg = VTOTAL(pipe);
 499         vblank_reg = VBLANK(pipe);
 500         vsync_reg = VSYNC(pipe);
 501         pipeconf_reg = PIPECONF(pipe);
 502         pipe_dsl_reg = PIPEDSL(pipe);
 503
 504         save_bclrpat = I915_READ(bclrpat_reg);
 505         save_vtotal = I915_READ(vtotal_reg);
 506         vblank = I915_READ(vblank_reg);
 507
 508         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 509         vactive = (save_vtotal & 0x7ff) + 1;
 510
 511         vblank_start = (vblank & 0xfff) + 1;
 512         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 513
 514         /* Set the border color to purple. */
 515         I915_WRITE(bclrpat_reg, 0x500050);
 516
 517         if (!IS_GEN2(dev)) {
 518                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 519                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 520                 POSTING_READ(pipeconf_reg);
 521                 /* Wait for next Vblank to substitue
 522                  * border color for Color info */
 523                 intel_wait_for_vblank(dev, pipe);
 524                 st00 = I915_READ8(_VGA_MSR_WRITE);
 525                 status = ((st00 & (1 << 4)) != 0) ?
 526                         connector_status_connected :
 527                         connector_status_disconnected;
 528
 529                 I915_WRITE(pipeconf_reg, pipeconf);
 530         } else {
 531                 bool restore_vblank = false;
 532                 int count, detect;
 533
 534                 /*
 535                 * If there isn't any border, add some.
 536                 * Yes, this will flicker
 537                 */
 538                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 539                         uint32_t vsync = I915_READ(vsync_reg);
 540                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 541
 542                         vblank_start = vsync_start;
 543                         I915_WRITE(vblank_reg,
 544                                    (vblank_start - 1) |
 545                                    ((vblank_end - 1) << 16));
 546                         restore_vblank = true;
 547                 }
 548                 /* sample in the vertical border, selecting the larger one */
 549                 if (vblank_start - vactive >= vtotal - vblank_end)
 550                         vsample = (vblank_start + vactive) >> 1;
 551                 else
 552                         vsample = (vtotal + vblank_end) >> 1;
 553
 554                 /*
 555                  * Wait for the border to be displayed
 556                  */
 557                 while (I915_READ(pipe_dsl_reg) >= vactive)
 558                         ;
 559                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 560                         ;
 561                 /*
 562                  * Watch ST00 for an entire scanline
 563                  */
 564                 detect = 0;
 565                 count = 0;
 566                 do {
 567                         count++;
 568                         /* Read the ST00 VGA status register */
 569                         st00 = I915_READ8(_VGA_MSR_WRITE);
 570                         if (st00 & (1 << 4))
 571                                 detect++;
 572                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 573
 574                 /* restore vblank if necessary */
 575                 if (restore_vblank)
 576                         I915_WRITE(vblank_reg, vblank);
 577                 /*
 578                  * If more than 3/4 of the scanline detected a monitor,
 579                  * then it is assumed to be present. This works even on i830,
 580                  * where there isn't any way to force the border color across
 581                  * the screen
 582                  */
 583                 status = detect * 4 > count * 3 ?
 584                          connector_status_connected :
 585                          connector_status_disconnected;
 586         }
 587
 588         /* Restore previous settings */
 589         I915_WRITE(bclrpat_reg, save_bclrpat);
 590
 591         return status;
 592 }
 593
 594 static enum drm_connector_status
 595 intel_crt_detect(struct drm_connector *connector, bool force)
 596 {
 597         struct drm_device *dev = connector->dev;
 598         struct drm_i915_private *dev_priv = dev->dev_private;
 599         struct intel_crt *crt = intel_attached_crt(connector);
 600         struct intel_encoder *intel_encoder = &crt->base;
 601         enum intel_display_power_domain power_domain;
 602         enum drm_connector_status status;
 603         struct intel_load_detect_pipe tmp;
 604         struct drm_modeset_acquire_ctx ctx;
 605
 606         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 607                       connector->base.id, connector->name,
 608                       force);
 609
 610         power_domain = intel_display_port_power_domain(intel_encoder);
 611         intel_display_power_get(dev_priv, power_domain);
 612
 613         if (I915_HAS_HOTPLUG(dev)) {
 614                 /* We can not rely on the HPD pin always being correctly wired
 615                  * up, for example many KVM do not pass it through, and so
 616                  * only trust an assertion that the monitor is connected.
 617                  */
 618                 if (intel_crt_detect_hotplug(connector)) {
 619                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 620                         status = connector_status_connected;
 621                         goto out;
 622                 } else
 623                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 624         }
 625
 626         if (intel_crt_detect_ddc(connector)) {
 627                 status = connector_status_connected;
 628                 goto out;
 629         }
 630
 631         /* Load detection is broken on HPD capable machines. Whoever wants a
 632          * broken monitor (without edid) to work behind a broken kvm (that fails
 633          * to have the right resistors for HP detection) needs to fix this up.
 634          * For now just bail out. */
 635         if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
 636                 status = connector_status_disconnected;
 637                 goto out;
 638         }
 639
 640         if (!force) {
 641                 status = connector->status;
 642                 goto out;
 643         }
 644
 645         drm_modeset_acquire_init(&ctx, 0);
 646
 647         /* for pre-945g platforms use load detect */
 648         if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
 649                 if (intel_crt_detect_ddc(connector))
 650                         status = connector_status_connected;
 651                 else if (INTEL_INFO(dev)->gen < 4)
 652                         status = intel_crt_load_detect(crt);
 653                 else
 654                         status = connector_status_unknown;
 655                 intel_release_load_detect_pipe(connector, &tmp, &ctx);
 656         } else
 657                 status = connector_status_unknown;
 658
 659         drm_modeset_drop_locks(&ctx);
 660         drm_modeset_acquire_fini(&ctx);
 661
 662 out:
 663         intel_display_power_put(dev_priv, power_domain);
 664         return status;
 665 }
 666
 667 static void intel_crt_destroy(struct drm_connector *connector)
 668 {
 669         drm_connector_cleanup(connector);
 670         kfree(connector);
 671 }
 672
 673 static int intel_crt_get_modes(struct drm_connector *connector)
 674 {
 675         struct drm_device *dev = connector->dev;
 676         struct drm_i915_private *dev_priv = dev->dev_private;
 677         struct intel_crt *crt = intel_attached_crt(connector);
 678         struct intel_encoder *intel_encoder = &crt->base;
 679         enum intel_display_power_domain power_domain;
 680         int ret;
 681         struct i2c_adapter *i2c;
 682
 683         power_domain = intel_display_port_power_domain(intel_encoder);
 684         intel_display_power_get(dev_priv, power_domain);
 685
 686         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 687         ret = intel_crt_ddc_get_modes(connector, i2c);
 688         if (ret || !IS_G4X(dev))
 689                 goto out;
 690
 691         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 692         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 693         ret = intel_crt_ddc_get_modes(connector, i2c);
 694
 695 out:
 696         intel_display_power_put(dev_priv, power_domain);
 697
 698         return ret;
 699 }
 700
 701 static int intel_crt_set_property(struct drm_connector *connector,
 702                                   struct drm_property *property,
 703                                   uint64_t value)
 704 {
 705         return 0;
 706 }
 707
 708 static void intel_crt_reset(struct drm_connector *connector)
 709 {
 710         struct drm_device *dev = connector->dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         struct intel_crt *crt = intel_attached_crt(connector);
 713
 714         if (INTEL_INFO(dev)->gen >= 5) {
 715                 u32 adpa;
 716
 717                 adpa = I915_READ(crt->adpa_reg);
 718                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 719                 adpa |= ADPA_HOTPLUG_BITS;
 720                 I915_WRITE(crt->adpa_reg, adpa);
 721                 POSTING_READ(crt->adpa_reg);
 722
 723                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 724                 crt->force_hotplug_required = 1;
 725         }
 726
 727 }
 728
 729 /*
 730  * Routines for controlling stuff on the analog port
 731  */
 732
 733 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 734         .reset = intel_crt_reset,
 735         .dpms = drm_atomic_helper_connector_dpms,
 736         .detect = intel_crt_detect,
 737         .fill_modes = drm_helper_probe_single_connector_modes,
 738         .destroy = intel_crt_destroy,
 739         .set_property = intel_crt_set_property,
 740         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 741         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 742         .atomic_get_property = intel_connector_atomic_get_property,
 743 };
 744
 745 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 746         .mode_valid = intel_crt_mode_valid,
 747         .get_modes = intel_crt_get_modes,
 748         .best_encoder = intel_best_encoder,
 749 };
 750
 751 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 752         .destroy = intel_encoder_destroy,
 753 };
 754
 755 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
 756 {
 757         DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
 758         return 1;
 759 }
 760
 761 static const struct dmi_system_id intel_no_crt[] = {
 762         {
 763                 .callback = intel_no_crt_dmi_callback,
 764                 .ident = "ACER ZGB",
 765                 .matches = {
 766                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 767                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 768                 },
 769         },
 770         {
 771                 .callback = intel_no_crt_dmi_callback,
 772                 .ident = "DELL XPS 8700",
 773                 .matches = {
 774                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 775                         DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
 776                 },
 777         },
 778         { }
 779 };
 780
 781 void intel_crt_init(struct drm_device *dev)
 782 {
 783         struct drm_connector *connector;
 784         struct intel_crt *crt;
 785         struct intel_connector *intel_connector;
 786         struct drm_i915_private *dev_priv = dev->dev_private;
 787         i915_reg_t adpa_reg;
 788         u32 adpa;
 789
 790         /* Skip machines without VGA that falsely report hotplug events */
 791         if (dmi_check_system(intel_no_crt))
 792                 return;
 793
 794         if (HAS_PCH_SPLIT(dev))
 795                 adpa_reg = PCH_ADPA;
 796         else if (IS_VALLEYVIEW(dev))
 797                 adpa_reg = VLV_ADPA;
 798         else
 799                 adpa_reg = ADPA;
 800
 801         adpa = I915_READ(adpa_reg);
 802         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 803                 /*
 804                  * On some machines (some IVB at least) CRT can be
 805                  * fused off, but there's no known fuse bit to
 806                  * indicate that. On these machine the ADPA register
 807                  * works normally, except the DAC enable bit won't
 808                  * take. So the only way to tell is attempt to enable
 809                  * it and see what happens.
 810                  */
 811                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 812                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 813                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 814                         return;
 815                 I915_WRITE(adpa_reg, adpa);
 816         }
 817
 818         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 819         if (!crt)
 820                 return;
 821
 822         intel_connector = intel_connector_alloc();
 823         if (!intel_connector) {
 824                 kfree(crt);
 825                 return;
 826         }
 827
 828         connector = &intel_connector->base;
 829         crt->connector = intel_connector;
 830         drm_connector_init(dev, &intel_connector->base,
 831                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 832
 833         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
 834                          DRM_MODE_ENCODER_DAC, NULL);
 835
 836         intel_connector_attach_encoder(intel_connector, &crt->base);
 837
 838         crt->base.type = INTEL_OUTPUT_ANALOG;
 839         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 840         if (IS_I830(dev))
 841                 crt->base.crtc_mask = (1 << 0);
 842         else
 843                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 844
 845         if (IS_GEN2(dev))
 846                 connector->interlace_allowed = 0;
 847         else
 848                 connector->interlace_allowed = 1;
 849         connector->doublescan_allowed = 0;
 850
 851         crt->adpa_reg = adpa_reg;
 852
 853         crt->base.compute_config = intel_crt_compute_config;
 854         if (HAS_PCH_SPLIT(dev)) {
 855                 crt->base.disable = pch_disable_crt;
 856                 crt->base.post_disable = pch_post_disable_crt;
 857         } else {
 858                 crt->base.disable = intel_disable_crt;
 859         }
 860         crt->base.enable = intel_enable_crt;
 861         if (I915_HAS_HOTPLUG(dev))
 862                 crt->base.hpd_pin = HPD_CRT;
 863         if (HAS_DDI(dev)) {
 864                 crt->base.get_config = hsw_crt_get_config;
 865                 crt->base.get_hw_state = intel_ddi_get_hw_state;
 866         } else {
 867                 crt->base.get_config = intel_crt_get_config;
 868                 crt->base.get_hw_state = intel_crt_get_hw_state;
 869         }
 870         intel_connector->get_hw_state = intel_connector_get_hw_state;
 871         intel_connector->unregister = intel_connector_unregister;
 872
 873         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 874
 875         drm_connector_register(connector);
 876
 877         if (!I915_HAS_HOTPLUG(dev))
 878                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
 879
 880         /*
 881          * Configure the automatic hotplug detection stuff
 882          */
 883         crt->force_hotplug_required = 0;
 884
 885         /*
 886          * TODO: find a proper way to discover whether we need to set the the
 887          * polarity and link reversal bits or not, instead of relying on the
 888          * BIOS.
 889          */
 890         if (HAS_PCH_LPT(dev)) {
 891                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
 892                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
 893
 894                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
 895         }
 896
 897         intel_crt_reset(connector);
 898 }