drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 #define I915_CSR_SKL "i915/skl_dmc_ver4.bin"
  29
  30 MODULE_FIRMWARE(I915_CSR_SKL);
  31
  32 /*
  33 * SKL CSR registers for DC5 and DC6
  34 */
  35 #define CSR_PROGRAM_BASE                0x80000
  36 #define CSR_SSP_BASE_ADDR_GEN9          0x00002FC0
  37 #define CSR_HTP_ADDR_SKL                0x00500034
  38 #define CSR_SSP_BASE                    0x8F074
  39 #define CSR_HTP_SKL                     0x8F004
  40 #define CSR_LAST_WRITE                  0x8F034
  41 #define CSR_LAST_WRITE_VALUE            0xc003b400
  42 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
  43 #define CSR_MAX_FW_SIZE                 0x2FFF
  44 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  45 #define CSR_MMIO_START_RANGE    0x80000
  46 #define CSR_MMIO_END_RANGE              0x8FFFF
  47
  48 struct intel_css_header {
  49         /* 0x09 for DMC */
  50         uint32_t module_type;
  51
  52         /* Includes the DMC specific header in dwords */
  53         uint32_t header_len;
  54
  55         /* always value would be 0x10000 */
  56         uint32_t header_ver;
  57
  58         /* Not used */
  59         uint32_t module_id;
  60
  61         /* Not used */
  62         uint32_t module_vendor;
  63
  64         /* in YYYYMMDD format */
  65         uint32_t date;
  66
  67         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  68         uint32_t size;
  69
  70         /* Not used */
  71         uint32_t key_size;
  72
  73         /* Not used */
  74         uint32_t modulus_size;
  75
  76         /* Not used */
  77         uint32_t exponent_size;
  78
  79         /* Not used */
  80         uint32_t reserved1[12];
  81
  82         /* Major Minor */
  83         uint32_t version;
  84
  85         /* Not used */
  86         uint32_t reserved2[8];
  87
  88         /* Not used */
  89         uint32_t kernel_header_info;
  90 } __packed;
  91
  92 struct intel_fw_info {
  93         uint16_t reserved1;
  94
  95         /* Stepping (A, B, C, ..., *). * is a wildcard */
  96         char stepping;
  97
  98         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
  99         char substepping;
 100
 101         uint32_t offset;
 102         uint32_t reserved2;
 103 } __packed;
 104
 105 struct intel_package_header {
 106         /* DMC container header length in dwords */
 107         unsigned char header_len;
 108
 109         /* always value would be 0x01 */
 110         unsigned char header_ver;
 111
 112         unsigned char reserved[10];
 113
 114         /* Number of valid entries in the FWInfo array below */
 115         uint32_t num_entries;
 116
 117         struct intel_fw_info fw_info[20];
 118 } __packed;
 119
 120 struct intel_dmc_header {
 121         /* always value would be 0x40403E3E */
 122         uint32_t signature;
 123
 124         /* DMC binary header length */
 125         unsigned char header_len;
 126
 127         /* 0x01 */
 128         unsigned char header_ver;
 129
 130         /* Reserved */
 131         uint16_t dmcc_ver;
 132
 133         /* Major, Minor */
 134         uint32_t        project;
 135
 136         /* Firmware program size (excluding header) in dwords */
 137         uint32_t        fw_size;
 138
 139         /* Major Minor version */
 140         uint32_t fw_version;
 141
 142         /* Number of valid MMIO cycles present. */
 143         uint32_t mmio_count;
 144
 145         /* MMIO address */
 146         uint32_t mmioaddr[8];
 147
 148         /* MMIO data */
 149         uint32_t mmiodata[8];
 150
 151         /* FW filename  */
 152         unsigned char dfile[32];
 153
 154         uint32_t reserved1[2];
 155 } __packed;
 156
 157 struct stepping_info {
 158         char stepping;
 159         char substepping;
 160 };
 161
 162 static const struct stepping_info skl_stepping_info[] = {
 163                 {'A', '0'}, {'B', '0'}, {'C', '0'},
 164                 {'D', '0'}, {'E', '0'}, {'F', '0'},
 165                 {'G', '0'}, {'H', '0'}, {'I', '0'}
 166 };
 167
 168 static char intel_get_stepping(struct drm_device *dev)
 169 {
 170         if (IS_SKYLAKE(dev) && (dev->pdev->revision <
 171                         ARRAY_SIZE(skl_stepping_info)))
 172                 return skl_stepping_info[dev->pdev->revision].stepping;
 173         else
 174                 return -ENODATA;
 175 }
 176
 177 static char intel_get_substepping(struct drm_device *dev)
 178 {
 179         if (IS_SKYLAKE(dev) && (dev->pdev->revision <
 180                         ARRAY_SIZE(skl_stepping_info)))
 181                 return skl_stepping_info[dev->pdev->revision].substepping;
 182         else
 183                 return -ENODATA;
 184 }
 185
 186 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
 187 {
 188         enum csr_state state;
 189
 190         mutex_lock(&dev_priv->csr_lock);
 191         state = dev_priv->csr.state;
 192         mutex_unlock(&dev_priv->csr_lock);
 193
 194         return state;
 195 }
 196
 197 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
 198                         enum csr_state state)
 199 {
 200         mutex_lock(&dev_priv->csr_lock);
 201         dev_priv->csr.state = state;
 202         mutex_unlock(&dev_priv->csr_lock);
 203 }
 204
 205 void intel_csr_load_program(struct drm_device *dev)
 206 {
 207         struct drm_i915_private *dev_priv = dev->dev_private;
 208         __be32 *payload = dev_priv->csr.dmc_payload;
 209         uint32_t i, fw_size;
 210
 211         if (!IS_GEN9(dev)) {
 212                 DRM_ERROR("No CSR support available for this platform\n");
 213                 return;
 214         }
 215
 216         mutex_lock(&dev_priv->csr_lock);
 217         fw_size = dev_priv->csr.dmc_fw_size;
 218         for (i = 0; i < fw_size; i++)
 219                 I915_WRITE(CSR_PROGRAM_BASE + i * 4,
 220                         (u32 __force)payload[i]);
 221
 222         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 223                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 224                         dev_priv->csr.mmiodata[i]);
 225         }
 226
 227         dev_priv->csr.state = FW_LOADED;
 228         mutex_unlock(&dev_priv->csr_lock);
 229 }
 230
 231 static void finish_csr_load(const struct firmware *fw, void *context)
 232 {
 233         struct drm_i915_private *dev_priv = context;
 234         struct drm_device *dev = dev_priv->dev;
 235         struct intel_css_header *css_header;
 236         struct intel_package_header *package_header;
 237         struct intel_dmc_header *dmc_header;
 238         struct intel_csr *csr = &dev_priv->csr;
 239         char stepping = intel_get_stepping(dev);
 240         char substepping = intel_get_substepping(dev);
 241         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 242         uint32_t i;
 243         __be32 *dmc_payload;
 244         bool fw_loaded = false;
 245
 246         if (!fw) {
 247                 i915_firmware_load_error_print(csr->fw_path, 0);
 248                 goto out;
 249         }
 250
 251         if ((stepping == -ENODATA) || (substepping == -ENODATA)) {
 252                 DRM_ERROR("Unknown stepping info, firmware loading failed\n");
 253                 goto out;
 254         }
 255
 256         /* Extract CSS Header information*/
 257         css_header = (struct intel_css_header *)fw->data;
 258         if (sizeof(struct intel_css_header) !=
 259                 (css_header->header_len * 4)) {
 260                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
 261                         (css_header->header_len * 4));
 262                 goto out;
 263         }
 264         readcount += sizeof(struct intel_css_header);
 265
 266         /* Extract Package Header information*/
 267         package_header = (struct intel_package_header *)
 268                                         &fw->data[readcount];
 269         if (sizeof(struct intel_package_header) !=
 270                 (package_header->header_len * 4)) {
 271                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
 272                         (package_header->header_len * 4));
 273                 goto out;
 274         }
 275         readcount += sizeof(struct intel_package_header);
 276
 277         /* Search for dmc_offset to find firware binary. */
 278         for (i = 0; i < package_header->num_entries; i++) {
 279                 if (package_header->fw_info[i].substepping == '*' &&
 280                         stepping == package_header->fw_info[i].stepping) {
 281                         dmc_offset = package_header->fw_info[i].offset;
 282                         break;
 283                 } else if (stepping == package_header->fw_info[i].stepping &&
 284                         substepping == package_header->fw_info[i].substepping) {
 285                         dmc_offset = package_header->fw_info[i].offset;
 286                         break;
 287                 } else if (package_header->fw_info[i].stepping == '*' &&
 288                         package_header->fw_info[i].substepping == '*')
 289                         dmc_offset = package_header->fw_info[i].offset;
 290         }
 291         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 292                 DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
 293                 goto out;
 294         }
 295         readcount += dmc_offset;
 296
 297         /* Extract dmc_header information. */
 298         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 299         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 300                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
 301                                 (dmc_header->header_len));
 302                 goto out;
 303         }
 304         readcount += sizeof(struct intel_dmc_header);
 305
 306         /* Cache the dmc header info. */
 307         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 308                 DRM_ERROR("Firmware has wrong mmio count %u\n",
 309                                                 dmc_header->mmio_count);
 310                 goto out;
 311         }
 312         csr->mmio_count = dmc_header->mmio_count;
 313         for (i = 0; i < dmc_header->mmio_count; i++) {
 314                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE &&
 315                         dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 316                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
 317                                                 dmc_header->mmioaddr[i]);
 318                         goto out;
 319                 }
 320                 csr->mmioaddr[i] = dmc_header->mmioaddr[i];
 321                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 322         }
 323
 324         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 325         nbytes = dmc_header->fw_size * 4;
 326         if (nbytes > CSR_MAX_FW_SIZE) {
 327                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
 328                 goto out;
 329         }
 330         csr->dmc_fw_size = dmc_header->fw_size;
 331
 332         csr->dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 333         if (!csr->dmc_payload) {
 334                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 335                 goto out;
 336         }
 337
 338         dmc_payload = csr->dmc_payload;
 339         for (i = 0; i < dmc_header->fw_size; i++) {
 340                 uint32_t *tmp = (u32 *)&fw->data[readcount + i * 4];
 341                 /*
 342                  * The firmware payload is an array of 32 bit words stored in
 343                  * little-endian format in the firmware image and programmed
 344                  * as 32 bit big-endian format to memory.
 345                  */
 346                 dmc_payload[i] = cpu_to_be32(*tmp);
 347         }
 348
 349         /* load csr program during system boot, as needed for DC states */
 350         intel_csr_load_program(dev);
 351         fw_loaded = true;
 352
 353 out:
 354         if (fw_loaded)
 355                 intel_runtime_pm_put(dev_priv);
 356         else
 357                 intel_csr_load_status_set(dev_priv, FW_FAILED);
 358
 359         release_firmware(fw);
 360 }
 361
 362 void intel_csr_ucode_init(struct drm_device *dev)
 363 {
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365         struct intel_csr *csr = &dev_priv->csr;
 366         int ret;
 367
 368         if (!HAS_CSR(dev))
 369                 return;
 370
 371         if (IS_SKYLAKE(dev))
 372                 csr->fw_path = I915_CSR_SKL;
 373         else {
 374                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 375                 intel_csr_load_status_set(dev_priv, FW_FAILED);
 376                 return;
 377         }
 378
 379         /*
 380          * Obtain a runtime pm reference, until CSR is loaded,
 381          * to avoid entering runtime-suspend.
 382          */
 383         intel_runtime_pm_get(dev_priv);
 384
 385         /* CSR supported for platform, load firmware */
 386         ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path,
 387                                 &dev_priv->dev->pdev->dev,
 388                                 GFP_KERNEL, dev_priv,
 389                                 finish_csr_load);
 390         if (ret) {
 391                 i915_firmware_load_error_print(csr->fw_path, ret);
 392                 intel_csr_load_status_set(dev_priv, FW_FAILED);
 393         }
 394 }
 395
 396 void intel_csr_ucode_fini(struct drm_device *dev)
 397 {
 398         struct drm_i915_private *dev_priv = dev->dev_private;
 399
 400         if (!HAS_CSR(dev))
 401                 return;
 402
 403         intel_csr_load_status_set(dev_priv, FW_FAILED);
 404         kfree(dev_priv->csr.dmc_payload);
 405 }
 406
 407 void assert_csr_loaded(struct drm_i915_private *dev_priv)
 408 {
 409         WARN((intel_csr_load_status_get(dev_priv) != FW_LOADED), "CSR is not loaded.\n");
 410         WARN(!I915_READ(CSR_PROGRAM_BASE),
 411                                 "CSR program storage start is NULL\n");
 412         WARN(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 413         WARN(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 414 }