drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  */
  36
  37 #define I915_CSR_GLK "i915/glk_dmc_ver1_01.bin"
  38 MODULE_FIRMWARE(I915_CSR_GLK);
  39 #define GLK_CSR_VERSION_REQUIRED        CSR_VERSION(1, 1)
  40
  41 #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
  42 MODULE_FIRMWARE(I915_CSR_KBL);
  43 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 1)
  44
  45 #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
  46 MODULE_FIRMWARE(I915_CSR_SKL);
  47 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 26)
  48
  49 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
  50 MODULE_FIRMWARE(I915_CSR_BXT);
  51 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  52
  53 #define FIRMWARE_URL  "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
  54
  55
  56
  57
  58 #define CSR_MAX_FW_SIZE                 0x2FFF
  59 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  60
  61 struct intel_css_header {
  62         /* 0x09 for DMC */
  63         uint32_t module_type;
  64
  65         /* Includes the DMC specific header in dwords */
  66         uint32_t header_len;
  67
  68         /* always value would be 0x10000 */
  69         uint32_t header_ver;
  70
  71         /* Not used */
  72         uint32_t module_id;
  73
  74         /* Not used */
  75         uint32_t module_vendor;
  76
  77         /* in YYYYMMDD format */
  78         uint32_t date;
  79
  80         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  81         uint32_t size;
  82
  83         /* Not used */
  84         uint32_t key_size;
  85
  86         /* Not used */
  87         uint32_t modulus_size;
  88
  89         /* Not used */
  90         uint32_t exponent_size;
  91
  92         /* Not used */
  93         uint32_t reserved1[12];
  94
  95         /* Major Minor */
  96         uint32_t version;
  97
  98         /* Not used */
  99         uint32_t reserved2[8];
 100
 101         /* Not used */
 102         uint32_t kernel_header_info;
 103 } __packed;
 104
 105 struct intel_fw_info {
 106         uint16_t reserved1;
 107
 108         /* Stepping (A, B, C, ..., *). * is a wildcard */
 109         char stepping;
 110
 111         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 112         char substepping;
 113
 114         uint32_t offset;
 115         uint32_t reserved2;
 116 } __packed;
 117
 118 struct intel_package_header {
 119         /* DMC container header length in dwords */
 120         unsigned char header_len;
 121
 122         /* always value would be 0x01 */
 123         unsigned char header_ver;
 124
 125         unsigned char reserved[10];
 126
 127         /* Number of valid entries in the FWInfo array below */
 128         uint32_t num_entries;
 129
 130         struct intel_fw_info fw_info[20];
 131 } __packed;
 132
 133 struct intel_dmc_header {
 134         /* always value would be 0x40403E3E */
 135         uint32_t signature;
 136
 137         /* DMC binary header length */
 138         unsigned char header_len;
 139
 140         /* 0x01 */
 141         unsigned char header_ver;
 142
 143         /* Reserved */
 144         uint16_t dmcc_ver;
 145
 146         /* Major, Minor */
 147         uint32_t        project;
 148
 149         /* Firmware program size (excluding header) in dwords */
 150         uint32_t        fw_size;
 151
 152         /* Major Minor version */
 153         uint32_t fw_version;
 154
 155         /* Number of valid MMIO cycles present. */
 156         uint32_t mmio_count;
 157
 158         /* MMIO address */
 159         uint32_t mmioaddr[8];
 160
 161         /* MMIO data */
 162         uint32_t mmiodata[8];
 163
 164         /* FW filename  */
 165         unsigned char dfile[32];
 166
 167         uint32_t reserved1[2];
 168 } __packed;
 169
 170 struct stepping_info {
 171         char stepping;
 172         char substepping;
 173 };
 174
 175 static const struct stepping_info skl_stepping_info[] = {
 176         {'A', '0'}, {'B', '0'}, {'C', '0'},
 177         {'D', '0'}, {'E', '0'}, {'F', '0'},
 178         {'G', '0'}, {'H', '0'}, {'I', '0'},
 179         {'J', '0'}, {'K', '0'}
 180 };
 181
 182 static const struct stepping_info bxt_stepping_info[] = {
 183         {'A', '0'}, {'A', '1'}, {'A', '2'},
 184         {'B', '0'}, {'B', '1'}, {'B', '2'}
 185 };
 186
 187 static const struct stepping_info no_stepping_info = { '*', '*' };
 188
 189 static const struct stepping_info *
 190 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 191 {
 192         const struct stepping_info *si;
 193         unsigned int size;
 194
 195         if (IS_SKYLAKE(dev_priv)) {
 196                 size = ARRAY_SIZE(skl_stepping_info);
 197                 si = skl_stepping_info;
 198         } else if (IS_BROXTON(dev_priv)) {
 199                 size = ARRAY_SIZE(bxt_stepping_info);
 200                 si = bxt_stepping_info;
 201         } else {
 202                 size = 0;
 203         }
 204
 205         if (INTEL_REVID(dev_priv) < size)
 206                 return si + INTEL_REVID(dev_priv);
 207
 208         return &no_stepping_info;
 209 }
 210
 211 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 212 {
 213         uint32_t val, mask;
 214
 215         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 216
 217         if (IS_BROXTON(dev_priv))
 218                 mask |= DC_STATE_DEBUG_MASK_CORES;
 219
 220         /* The below bit doesn't need to be cleared ever afterwards */
 221         val = I915_READ(DC_STATE_DEBUG);
 222         if ((val & mask) != mask) {
 223                 val |= mask;
 224                 I915_WRITE(DC_STATE_DEBUG, val);
 225                 POSTING_READ(DC_STATE_DEBUG);
 226         }
 227 }
 228
 229 /**
 230  * intel_csr_load_program() - write the firmware from memory to register.
 231  * @dev_priv: i915 drm device.
 232  *
 233  * CSR firmware is read from a .bin file and kept in internal memory one time.
 234  * Everytime display comes back from low power state this function is called to
 235  * copy the firmware from internal memory to registers.
 236  */
 237 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 238 {
 239         u32 *payload = dev_priv->csr.dmc_payload;
 240         uint32_t i, fw_size;
 241
 242         if (!IS_GEN9(dev_priv)) {
 243                 DRM_ERROR("No CSR support available for this platform\n");
 244                 return;
 245         }
 246
 247         if (!dev_priv->csr.dmc_payload) {
 248                 DRM_ERROR("Tried to program CSR with empty payload\n");
 249                 return;
 250         }
 251
 252         fw_size = dev_priv->csr.dmc_fw_size;
 253         for (i = 0; i < fw_size; i++)
 254                 I915_WRITE(CSR_PROGRAM(i), payload[i]);
 255
 256         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 257                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 258                            dev_priv->csr.mmiodata[i]);
 259         }
 260
 261         dev_priv->csr.dc_state = 0;
 262
 263         gen9_set_dc_state_debugmask(dev_priv);
 264 }
 265
 266 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 267                               const struct firmware *fw)
 268 {
 269         struct intel_css_header *css_header;
 270         struct intel_package_header *package_header;
 271         struct intel_dmc_header *dmc_header;
 272         struct intel_csr *csr = &dev_priv->csr;
 273         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 274         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 275         uint32_t i;
 276         uint32_t *dmc_payload;
 277         uint32_t required_version;
 278
 279         if (!fw)
 280                 return NULL;
 281
 282         /* Extract CSS Header information*/
 283         css_header = (struct intel_css_header *)fw->data;
 284         if (sizeof(struct intel_css_header) !=
 285             (css_header->header_len * 4)) {
 286                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
 287                           (css_header->header_len * 4));
 288                 return NULL;
 289         }
 290
 291         csr->version = css_header->version;
 292
 293         if (IS_GEMINILAKE(dev_priv)) {
 294                 required_version = GLK_CSR_VERSION_REQUIRED;
 295         } else if (IS_KABYLAKE(dev_priv)) {
 296                 required_version = KBL_CSR_VERSION_REQUIRED;
 297         } else if (IS_SKYLAKE(dev_priv)) {
 298                 required_version = SKL_CSR_VERSION_REQUIRED;
 299         } else if (IS_BROXTON(dev_priv)) {
 300                 required_version = BXT_CSR_VERSION_REQUIRED;
 301         } else {
 302                 MISSING_CASE(INTEL_REVID(dev_priv));
 303                 required_version = 0;
 304         }
 305
 306         if (csr->version != required_version) {
 307                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 308                          " please use v%u.%u [" FIRMWARE_URL "].\n",
 309                          CSR_VERSION_MAJOR(csr->version),
 310                          CSR_VERSION_MINOR(csr->version),
 311                          CSR_VERSION_MAJOR(required_version),
 312                          CSR_VERSION_MINOR(required_version));
 313                 return NULL;
 314         }
 315
 316         readcount += sizeof(struct intel_css_header);
 317
 318         /* Extract Package Header information*/
 319         package_header = (struct intel_package_header *)
 320                 &fw->data[readcount];
 321         if (sizeof(struct intel_package_header) !=
 322             (package_header->header_len * 4)) {
 323                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
 324                           (package_header->header_len * 4));
 325                 return NULL;
 326         }
 327         readcount += sizeof(struct intel_package_header);
 328
 329         /* Search for dmc_offset to find firware binary. */
 330         for (i = 0; i < package_header->num_entries; i++) {
 331                 if (package_header->fw_info[i].substepping == '*' &&
 332                     si->stepping == package_header->fw_info[i].stepping) {
 333                         dmc_offset = package_header->fw_info[i].offset;
 334                         break;
 335                 } else if (si->stepping == package_header->fw_info[i].stepping &&
 336                            si->substepping == package_header->fw_info[i].substepping) {
 337                         dmc_offset = package_header->fw_info[i].offset;
 338                         break;
 339                 } else if (package_header->fw_info[i].stepping == '*' &&
 340                            package_header->fw_info[i].substepping == '*')
 341                         dmc_offset = package_header->fw_info[i].offset;
 342         }
 343         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 344                 DRM_ERROR("Firmware not supported for %c stepping\n",
 345                           si->stepping);
 346                 return NULL;
 347         }
 348         readcount += dmc_offset;
 349
 350         /* Extract dmc_header information. */
 351         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 352         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 353                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
 354                           (dmc_header->header_len));
 355                 return NULL;
 356         }
 357         readcount += sizeof(struct intel_dmc_header);
 358
 359         /* Cache the dmc header info. */
 360         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 361                 DRM_ERROR("Firmware has wrong mmio count %u\n",
 362                           dmc_header->mmio_count);
 363                 return NULL;
 364         }
 365         csr->mmio_count = dmc_header->mmio_count;
 366         for (i = 0; i < dmc_header->mmio_count; i++) {
 367                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 368                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 369                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
 370                                   dmc_header->mmioaddr[i]);
 371                         return NULL;
 372                 }
 373                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 374                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 375         }
 376
 377         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 378         nbytes = dmc_header->fw_size * 4;
 379         if (nbytes > CSR_MAX_FW_SIZE) {
 380                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
 381                 return NULL;
 382         }
 383         csr->dmc_fw_size = dmc_header->fw_size;
 384
 385         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 386         if (!dmc_payload) {
 387                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 388                 return NULL;
 389         }
 390
 391         return memcpy(dmc_payload, &fw->data[readcount], nbytes);
 392 }
 393
 394 static void csr_load_work_fn(struct work_struct *work)
 395 {
 396         struct drm_i915_private *dev_priv;
 397         struct intel_csr *csr;
 398         const struct firmware *fw = NULL;
 399         int ret;
 400
 401         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 402         csr = &dev_priv->csr;
 403
 404         ret = request_firmware(&fw, dev_priv->csr.fw_path,
 405                                &dev_priv->drm.pdev->dev);
 406         if (fw)
 407                 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 408
 409         if (dev_priv->csr.dmc_payload) {
 410                 intel_csr_load_program(dev_priv);
 411
 412                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 413
 414                 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
 415                          dev_priv->csr.fw_path,
 416                          CSR_VERSION_MAJOR(csr->version),
 417                          CSR_VERSION_MINOR(csr->version));
 418         } else {
 419                 dev_notice(dev_priv->drm.dev,
 420                            "Failed to load DMC firmware"
 421                            " [" FIRMWARE_URL "],"
 422                            " disabling runtime power management.\n");
 423         }
 424
 425         release_firmware(fw);
 426 }
 427
 428 /**
 429  * intel_csr_ucode_init() - initialize the firmware loading.
 430  * @dev_priv: i915 drm device.
 431  *
 432  * This function is called at the time of loading the display driver to read
 433  * firmware from a .bin file and copied into a internal memory.
 434  */
 435 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 436 {
 437         struct intel_csr *csr = &dev_priv->csr;
 438
 439         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 440
 441         if (!HAS_CSR(dev_priv))
 442                 return;
 443
 444         if (IS_GEMINILAKE(dev_priv))
 445                 csr->fw_path = I915_CSR_GLK;
 446         else if (IS_KABYLAKE(dev_priv))
 447                 csr->fw_path = I915_CSR_KBL;
 448         else if (IS_SKYLAKE(dev_priv))
 449                 csr->fw_path = I915_CSR_SKL;
 450         else if (IS_BROXTON(dev_priv))
 451                 csr->fw_path = I915_CSR_BXT;
 452         else {
 453                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 454                 return;
 455         }
 456
 457         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 458
 459         /*
 460          * Obtain a runtime pm reference, until CSR is loaded,
 461          * to avoid entering runtime-suspend.
 462          */
 463         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 464
 465         schedule_work(&dev_priv->csr.work);
 466 }
 467
 468 /**
 469  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 470  * @dev_priv: i915 drm device
 471  *
 472  * Prepare the DMC firmware before entering system suspend. This includes
 473  * flushing pending work items and releasing any resources acquired during
 474  * init.
 475  */
 476 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 477 {
 478         if (!HAS_CSR(dev_priv))
 479                 return;
 480
 481         flush_work(&dev_priv->csr.work);
 482
 483         /* Drop the reference held in case DMC isn't loaded. */
 484         if (!dev_priv->csr.dmc_payload)
 485                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 486 }
 487
 488 /**
 489  * intel_csr_ucode_resume() - init CSR firmware during system resume
 490  * @dev_priv: i915 drm device
 491  *
 492  * Reinitialize the DMC firmware during system resume, reacquiring any
 493  * resources released in intel_csr_ucode_suspend().
 494  */
 495 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 496 {
 497         if (!HAS_CSR(dev_priv))
 498                 return;
 499
 500         /*
 501          * Reacquire the reference to keep RPM disabled in case DMC isn't
 502          * loaded.
 503          */
 504         if (!dev_priv->csr.dmc_payload)
 505                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 506 }
 507
 508 /**
 509  * intel_csr_ucode_fini() - unload the CSR firmware.
 510  * @dev_priv: i915 drm device.
 511  *
 512  * Firmmware unloading includes freeing the internal memory and reset the
 513  * firmware loading status.
 514  */
 515 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 516 {
 517         if (!HAS_CSR(dev_priv))
 518                 return;
 519
 520         intel_csr_ucode_suspend(dev_priv);
 521
 522         kfree(dev_priv->csr.dmc_payload);
 523 }