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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
34 */
35 static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 };
46
47 static const u32 hsw_ddi_translations_fdi[] = {
48 0x00FFFFFF, 0x0007000E, /* FDI parameters */
49 0x00D75FFF, 0x000F000A,
50 0x00C30FFF, 0x00060006,
51 0x00AAAFFF, 0x001E0000,
52 0x00FFFFFF, 0x000F000A,
53 0x00D75FFF, 0x00160004,
54 0x00C30FFF, 0x001E0000,
55 0x00FFFFFF, 0x00060006,
56 0x00D75FFF, 0x001E0000,
57 };
58
59 static const u32 hsw_ddi_translations_hdmi[] = {
60 /* Idx NT mV diff T mV diff db */
61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
73 };
74
75 static const u32 bdw_ddi_translations_edp[] = {
76 0x00FFFFFF, 0x00000012, /* eDP parameters */
77 0x00EBAFFF, 0x00020011,
78 0x00C71FFF, 0x0006000F,
79 0x00FFFFFF, 0x00020011,
80 0x00DB6FFF, 0x0005000F,
81 0x00BEEFFF, 0x000A000C,
82 0x00FFFFFF, 0x0005000F,
83 0x00DB6FFF, 0x000A000C,
84 0x00FFFFFF, 0x000A000C,
85 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
86 };
87
88 static const u32 bdw_ddi_translations_dp[] = {
89 0x00FFFFFF, 0x0007000E, /* DP parameters */
90 0x00D75FFF, 0x000E000A,
91 0x00BEFFFF, 0x00140006,
92 0x00FFFFFF, 0x000E000A,
93 0x00D75FFF, 0x00180004,
94 0x80CB2FFF, 0x001B0002,
95 0x00F7DFFF, 0x00180004,
96 0x80D75FFF, 0x001B0002,
97 0x80FFFFFF, 0x001B0002,
98 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
99 };
100
101 static const u32 bdw_ddi_translations_fdi[] = {
102 0x00FFFFFF, 0x0001000E, /* FDI parameters */
103 0x00D75FFF, 0x0004000A,
104 0x00C30FFF, 0x00070006,
105 0x00AAAFFF, 0x000C0000,
106 0x00FFFFFF, 0x0004000A,
107 0x00D75FFF, 0x00090004,
108 0x00C30FFF, 0x000C0000,
109 0x00FFFFFF, 0x00070006,
110 0x00D75FFF, 0x000C0000,
111 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
112 };
113
114 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
115 {
116 struct drm_encoder *encoder = &intel_encoder->base;
117 int type = intel_encoder->type;
118
119 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
120 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
121 struct intel_digital_port *intel_dig_port =
122 enc_to_dig_port(encoder);
123 return intel_dig_port->port;
124
125 } else if (type == INTEL_OUTPUT_ANALOG) {
126 return PORT_E;
127
128 } else {
129 DRM_ERROR("Invalid DDI encoder type %d\n", type);
130 BUG();
131 }
132 }
133
134 /*
135 * Starting with Haswell, DDI port buffers must be programmed with correct
136 * values in advance. The buffer values are different for FDI and DP modes,
137 * but the HDMI/DVI fields are shared among those. So we program the DDI
138 * in either FDI or DP modes only, as HDMI connections will work with both
139 * of those
140 */
141 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
142 {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 u32 reg;
145 int i;
146 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
147 const u32 *ddi_translations_fdi;
148 const u32 *ddi_translations_dp;
149 const u32 *ddi_translations_edp;
150 const u32 *ddi_translations;
151
152 if (IS_BROADWELL(dev)) {
153 ddi_translations_fdi = bdw_ddi_translations_fdi;
154 ddi_translations_dp = bdw_ddi_translations_dp;
155 ddi_translations_edp = bdw_ddi_translations_edp;
156 } else if (IS_HASWELL(dev)) {
157 ddi_translations_fdi = hsw_ddi_translations_fdi;
158 ddi_translations_dp = hsw_ddi_translations_dp;
159 ddi_translations_edp = hsw_ddi_translations_dp;
160 } else {
161 WARN(1, "ddi translation table missing\n");
162 ddi_translations_edp = bdw_ddi_translations_dp;
163 ddi_translations_fdi = bdw_ddi_translations_fdi;
164 ddi_translations_dp = bdw_ddi_translations_dp;
165 }
166
167 switch (port) {
168 case PORT_A:
169 ddi_translations = ddi_translations_edp;
170 break;
171 case PORT_B:
172 case PORT_C:
173 ddi_translations = ddi_translations_dp;
174 break;
175 case PORT_D:
176 if (intel_dp_is_edp(dev, PORT_D))
177 ddi_translations = ddi_translations_edp;
178 else
179 ddi_translations = ddi_translations_dp;
180 break;
181 case PORT_E:
182 ddi_translations = ddi_translations_fdi;
183 break;
184 default:
185 BUG();
186 }
187
188 for (i = 0, reg = DDI_BUF_TRANS(port);
189 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
190 I915_WRITE(reg, ddi_translations[i]);
191 reg += 4;
192 }
193 /* Entry 9 is for HDMI: */
194 for (i = 0; i < 2; i++) {
195 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
196 reg += 4;
197 }
198 }
199
200 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
201 * mode and port E for FDI.
202 */
203 void intel_prepare_ddi(struct drm_device *dev)
204 {
205 int port;
206
207 if (!HAS_DDI(dev))
208 return;
209
210 for (port = PORT_A; port <= PORT_E; port++)
211 intel_prepare_ddi_buffers(dev, port);
212 }
213
214 static const long hsw_ddi_buf_ctl_values[] = {
215 DDI_BUF_EMP_400MV_0DB_HSW,
216 DDI_BUF_EMP_400MV_3_5DB_HSW,
217 DDI_BUF_EMP_400MV_6DB_HSW,
218 DDI_BUF_EMP_400MV_9_5DB_HSW,
219 DDI_BUF_EMP_600MV_0DB_HSW,
220 DDI_BUF_EMP_600MV_3_5DB_HSW,
221 DDI_BUF_EMP_600MV_6DB_HSW,
222 DDI_BUF_EMP_800MV_0DB_HSW,
223 DDI_BUF_EMP_800MV_3_5DB_HSW
224 };
225
226 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
227 enum port port)
228 {
229 uint32_t reg = DDI_BUF_CTL(port);
230 int i;
231
232 for (i = 0; i < 8; i++) {
233 udelay(1);
234 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
235 return;
236 }
237 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
238 }
239
240 /* Starting with Haswell, different DDI ports can work in FDI mode for
241 * connection to the PCH-located connectors. For this, it is necessary to train
242 * both the DDI port and PCH receiver for the desired DDI buffer settings.
243 *
244 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
245 * please note that when FDI mode is active on DDI E, it shares 2 lines with
246 * DDI A (which is used for eDP)
247 */
248
249 void hsw_fdi_link_train(struct drm_crtc *crtc)
250 {
251 struct drm_device *dev = crtc->dev;
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
254 u32 temp, i, rx_ctl_val;
255
256 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
257 * mode set "sequence for CRT port" document:
258 * - TP1 to TP2 time with the default value
259 * - FDI delay to 90h
260 *
261 * WaFDIAutoLinkSetTimingOverrride:hsw
262 */
263 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
264 FDI_RX_PWRDN_LANE0_VAL(2) |
265 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
266
267 /* Enable the PCH Receiver FDI PLL */
268 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
269 FDI_RX_PLL_ENABLE |
270 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
271 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
272 POSTING_READ(_FDI_RXA_CTL);
273 udelay(220);
274
275 /* Switch from Rawclk to PCDclk */
276 rx_ctl_val |= FDI_PCDCLK;
277 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
278
279 /* Configure Port Clock Select */
280 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
281
282 /* Start the training iterating through available voltages and emphasis,
283 * testing each value twice. */
284 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
285 /* Configure DP_TP_CTL with auto-training */
286 I915_WRITE(DP_TP_CTL(PORT_E),
287 DP_TP_CTL_FDI_AUTOTRAIN |
288 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
289 DP_TP_CTL_LINK_TRAIN_PAT1 |
290 DP_TP_CTL_ENABLE);
291
292 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
293 * DDI E does not support port reversal, the functionality is
294 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
295 * port reversal bit */
296 I915_WRITE(DDI_BUF_CTL(PORT_E),
297 DDI_BUF_CTL_ENABLE |
298 ((intel_crtc->config.fdi_lanes - 1) << 1) |
299 hsw_ddi_buf_ctl_values[i / 2]);
300 POSTING_READ(DDI_BUF_CTL(PORT_E));
301
302 udelay(600);
303
304 /* Program PCH FDI Receiver TU */
305 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
306
307 /* Enable PCH FDI Receiver with auto-training */
308 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
309 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
310 POSTING_READ(_FDI_RXA_CTL);
311
312 /* Wait for FDI receiver lane calibration */
313 udelay(30);
314
315 /* Unset FDI_RX_MISC pwrdn lanes */
316 temp = I915_READ(_FDI_RXA_MISC);
317 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
318 I915_WRITE(_FDI_RXA_MISC, temp);
319 POSTING_READ(_FDI_RXA_MISC);
320
321 /* Wait for FDI auto training time */
322 udelay(5);
323
324 temp = I915_READ(DP_TP_STATUS(PORT_E));
325 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
326 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
327
328 /* Enable normal pixel sending for FDI */
329 I915_WRITE(DP_TP_CTL(PORT_E),
330 DP_TP_CTL_FDI_AUTOTRAIN |
331 DP_TP_CTL_LINK_TRAIN_NORMAL |
332 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
333 DP_TP_CTL_ENABLE);
334
335 return;
336 }
337
338 temp = I915_READ(DDI_BUF_CTL(PORT_E));
339 temp &= ~DDI_BUF_CTL_ENABLE;
340 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
341 POSTING_READ(DDI_BUF_CTL(PORT_E));
342
343 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
344 temp = I915_READ(DP_TP_CTL(PORT_E));
345 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
346 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
347 I915_WRITE(DP_TP_CTL(PORT_E), temp);
348 POSTING_READ(DP_TP_CTL(PORT_E));
349
350 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
351
352 rx_ctl_val &= ~FDI_RX_ENABLE;
353 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
354 POSTING_READ(_FDI_RXA_CTL);
355
356 /* Reset FDI_RX_MISC pwrdn lanes */
357 temp = I915_READ(_FDI_RXA_MISC);
358 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
359 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
360 I915_WRITE(_FDI_RXA_MISC, temp);
361 POSTING_READ(_FDI_RXA_MISC);
362 }
363
364 DRM_ERROR("FDI link training failed!\n");
365 }
366
367 static void intel_ddi_mode_set(struct intel_encoder *encoder)
368 {
369 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
370 int port = intel_ddi_get_encoder_port(encoder);
371 int pipe = crtc->pipe;
372 int type = encoder->type;
373 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
374
375 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
376 port_name(port), pipe_name(pipe));
377
378 crtc->eld_vld = false;
379 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
380 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
381 struct intel_digital_port *intel_dig_port =
382 enc_to_dig_port(&encoder->base);
383
384 intel_dp->DP = intel_dig_port->saved_port_bits |
385 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
386 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
387
388 if (intel_dp->has_audio) {
389 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
390 pipe_name(crtc->pipe));
391
392 /* write eld */
393 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
394 intel_write_eld(&encoder->base, adjusted_mode);
395 }
396 } else if (type == INTEL_OUTPUT_HDMI) {
397 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
398
399 if (intel_hdmi->has_audio) {
400 /* Proper support for digital audio needs a new logic
401 * and a new set of registers, so we leave it for future
402 * patch bombing.
403 */
404 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
405 pipe_name(crtc->pipe));
406
407 /* write eld */
408 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
409 intel_write_eld(&encoder->base, adjusted_mode);
410 }
411
412 intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
413 }
414 }
415
416 static struct intel_encoder *
417 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
418 {
419 struct drm_device *dev = crtc->dev;
420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
421 struct intel_encoder *intel_encoder, *ret = NULL;
422 int num_encoders = 0;
423
424 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
425 ret = intel_encoder;
426 num_encoders++;
427 }
428
429 if (num_encoders != 1)
430 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
431 pipe_name(intel_crtc->pipe));
432
433 BUG_ON(ret == NULL);
434 return ret;
435 }
436
437 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
438 {
439 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
440 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
442 uint32_t val;
443
444 switch (intel_crtc->ddi_pll_sel) {
445 case PORT_CLK_SEL_SPLL:
446 plls->spll_refcount--;
447 if (plls->spll_refcount == 0) {
448 DRM_DEBUG_KMS("Disabling SPLL\n");
449 val = I915_READ(SPLL_CTL);
450 WARN_ON(!(val & SPLL_PLL_ENABLE));
451 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
452 POSTING_READ(SPLL_CTL);
453 }
454 break;
455 case PORT_CLK_SEL_WRPLL1:
456 plls->wrpll1_refcount--;
457 if (plls->wrpll1_refcount == 0) {
458 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
459 val = I915_READ(WRPLL_CTL1);
460 WARN_ON(!(val & WRPLL_PLL_ENABLE));
461 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
462 POSTING_READ(WRPLL_CTL1);
463 }
464 break;
465 case PORT_CLK_SEL_WRPLL2:
466 plls->wrpll2_refcount--;
467 if (plls->wrpll2_refcount == 0) {
468 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
469 val = I915_READ(WRPLL_CTL2);
470 WARN_ON(!(val & WRPLL_PLL_ENABLE));
471 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
472 POSTING_READ(WRPLL_CTL2);
473 }
474 break;
475 }
476
477 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
478 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
479 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
480
481 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
482 }
483
484 #define LC_FREQ 2700
485 #define LC_FREQ_2K (LC_FREQ * 2000)
486
487 #define P_MIN 2
488 #define P_MAX 64
489 #define P_INC 2
490
491 /* Constraints for PLL good behavior */
492 #define REF_MIN 48
493 #define REF_MAX 400
494 #define VCO_MIN 2400
495 #define VCO_MAX 4800
496
497 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
498
499 struct wrpll_rnp {
500 unsigned p, n2, r2;
501 };
502
503 static unsigned wrpll_get_budget_for_freq(int clock)
504 {
505 unsigned budget;
506
507 switch (clock) {
508 case 25175000:
509 case 25200000:
510 case 27000000:
511 case 27027000:
512 case 37762500:
513 case 37800000:
514 case 40500000:
515 case 40541000:
516 case 54000000:
517 case 54054000:
518 case 59341000:
519 case 59400000:
520 case 72000000:
521 case 74176000:
522 case 74250000:
523 case 81000000:
524 case 81081000:
525 case 89012000:
526 case 89100000:
527 case 108000000:
528 case 108108000:
529 case 111264000:
530 case 111375000:
531 case 148352000:
532 case 148500000:
533 case 162000000:
534 case 162162000:
535 case 222525000:
536 case 222750000:
537 case 296703000:
538 case 297000000:
539 budget = 0;
540 break;
541 case 233500000:
542 case 245250000:
543 case 247750000:
544 case 253250000:
545 case 298000000:
546 budget = 1500;
547 break;
548 case 169128000:
549 case 169500000:
550 case 179500000:
551 case 202000000:
552 budget = 2000;
553 break;
554 case 256250000:
555 case 262500000:
556 case 270000000:
557 case 272500000:
558 case 273750000:
559 case 280750000:
560 case 281250000:
561 case 286000000:
562 case 291750000:
563 budget = 4000;
564 break;
565 case 267250000:
566 case 268500000:
567 budget = 5000;
568 break;
569 default:
570 budget = 1000;
571 break;
572 }
573
574 return budget;
575 }
576
577 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
578 unsigned r2, unsigned n2, unsigned p,
579 struct wrpll_rnp *best)
580 {
581 uint64_t a, b, c, d, diff, diff_best;
582
583 /* No best (r,n,p) yet */
584 if (best->p == 0) {
585 best->p = p;
586 best->n2 = n2;
587 best->r2 = r2;
588 return;
589 }
590
591 /*
592 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
593 * freq2k.
594 *
595 * delta = 1e6 *
596 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
597 * freq2k;
598 *
599 * and we would like delta <= budget.
600 *
601 * If the discrepancy is above the PPM-based budget, always prefer to
602 * improve upon the previous solution. However, if you're within the
603 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
604 */
605 a = freq2k * budget * p * r2;
606 b = freq2k * budget * best->p * best->r2;
607 diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
608 diff_best = ABS_DIFF((freq2k * best->p * best->r2),
609 (LC_FREQ_2K * best->n2));
610 c = 1000000 * diff;
611 d = 1000000 * diff_best;
612
613 if (a < c && b < d) {
614 /* If both are above the budget, pick the closer */
615 if (best->p * best->r2 * diff < p * r2 * diff_best) {
616 best->p = p;
617 best->n2 = n2;
618 best->r2 = r2;
619 }
620 } else if (a >= c && b < d) {
621 /* If A is below the threshold but B is above it? Update. */
622 best->p = p;
623 best->n2 = n2;
624 best->r2 = r2;
625 } else if (a >= c && b >= d) {
626 /* Both are below the limit, so pick the higher n2/(r2*r2) */
627 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
628 best->p = p;
629 best->n2 = n2;
630 best->r2 = r2;
631 }
632 }
633 /* Otherwise a < c && b >= d, do nothing */
634 }
635
636 static void
637 intel_ddi_calculate_wrpll(int clock /* in Hz */,
638 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
639 {
640 uint64_t freq2k;
641 unsigned p, n2, r2;
642 struct wrpll_rnp best = { 0, 0, 0 };
643 unsigned budget;
644
645 freq2k = clock / 100;
646
647 budget = wrpll_get_budget_for_freq(clock);
648
649 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
650 * and directly pass the LC PLL to it. */
651 if (freq2k == 5400000) {
652 *n2_out = 2;
653 *p_out = 1;
654 *r2_out = 2;
655 return;
656 }
657
658 /*
659 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
660 * the WR PLL.
661 *
662 * We want R so that REF_MIN <= Ref <= REF_MAX.
663 * Injecting R2 = 2 * R gives:
664 * REF_MAX * r2 > LC_FREQ * 2 and
665 * REF_MIN * r2 < LC_FREQ * 2
666 *
667 * Which means the desired boundaries for r2 are:
668 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
669 *
670 */
671 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
672 r2 <= LC_FREQ * 2 / REF_MIN;
673 r2++) {
674
675 /*
676 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
677 *
678 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
679 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
680 * VCO_MAX * r2 > n2 * LC_FREQ and
681 * VCO_MIN * r2 < n2 * LC_FREQ)
682 *
683 * Which means the desired boundaries for n2 are:
684 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
685 */
686 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
687 n2 <= VCO_MAX * r2 / LC_FREQ;
688 n2++) {
689
690 for (p = P_MIN; p <= P_MAX; p += P_INC)
691 wrpll_update_rnp(freq2k, budget,
692 r2, n2, p, &best);
693 }
694 }
695
696 *n2_out = best.n2;
697 *p_out = best.p;
698 *r2_out = best.r2;
699 }
700
701 /*
702 * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
703 * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
704 * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
705 * enable the PLL.
706 */
707 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
708 {
709 struct drm_crtc *crtc = &intel_crtc->base;
710 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
711 struct drm_encoder *encoder = &intel_encoder->base;
712 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
713 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
714 int type = intel_encoder->type;
715 enum pipe pipe = intel_crtc->pipe;
716 int clock = intel_crtc->config.port_clock;
717
718 intel_ddi_put_crtc_pll(crtc);
719
720 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
721 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
722
723 switch (intel_dp->link_bw) {
724 case DP_LINK_BW_1_62:
725 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
726 break;
727 case DP_LINK_BW_2_7:
728 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
729 break;
730 case DP_LINK_BW_5_4:
731 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
732 break;
733 default:
734 DRM_ERROR("Link bandwidth %d unsupported\n",
735 intel_dp->link_bw);
736 return false;
737 }
738
739 } else if (type == INTEL_OUTPUT_HDMI) {
740 uint32_t reg, val;
741 unsigned p, n2, r2;
742
743 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
744
745 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
746 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
747 WRPLL_DIVIDER_POST(p);
748
749 if (val == I915_READ(WRPLL_CTL1)) {
750 DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
751 pipe_name(pipe));
752 reg = WRPLL_CTL1;
753 } else if (val == I915_READ(WRPLL_CTL2)) {
754 DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
755 pipe_name(pipe));
756 reg = WRPLL_CTL2;
757 } else if (plls->wrpll1_refcount == 0) {
758 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
759 pipe_name(pipe));
760 reg = WRPLL_CTL1;
761 } else if (plls->wrpll2_refcount == 0) {
762 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
763 pipe_name(pipe));
764 reg = WRPLL_CTL2;
765 } else {
766 DRM_ERROR("No WRPLLs available!\n");
767 return false;
768 }
769
770 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
771 clock, p, n2, r2);
772
773 if (reg == WRPLL_CTL1) {
774 plls->wrpll1_refcount++;
775 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
776 } else {
777 plls->wrpll2_refcount++;
778 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
779 }
780
781 } else if (type == INTEL_OUTPUT_ANALOG) {
782 if (plls->spll_refcount == 0) {
783 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
784 pipe_name(pipe));
785 plls->spll_refcount++;
786 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
787 } else {
788 DRM_ERROR("SPLL already in use\n");
789 return false;
790 }
791
792 } else {
793 WARN(1, "Invalid DDI encoder type %d\n", type);
794 return false;
795 }
796
797 return true;
798 }
799
800 /*
801 * To be called after intel_ddi_pll_select(). That one selects the PLL to be
802 * used, this one actually enables the PLL.
803 */
804 void intel_ddi_pll_enable(struct intel_crtc *crtc)
805 {
806 struct drm_device *dev = crtc->base.dev;
807 struct drm_i915_private *dev_priv = dev->dev_private;
808 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
809 int clock = crtc->config.port_clock;
810 uint32_t reg, cur_val, new_val;
811 int refcount;
812 const char *pll_name;
813 uint32_t enable_bit = (1 << 31);
814 unsigned int p, n2, r2;
815
816 BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
817 BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
818
819 switch (crtc->ddi_pll_sel) {
820 case PORT_CLK_SEL_LCPLL_2700:
821 case PORT_CLK_SEL_LCPLL_1350:
822 case PORT_CLK_SEL_LCPLL_810:
823 /*
824 * LCPLL should always be enabled at this point of the mode set
825 * sequence, so nothing to do.
826 */
827 return;
828
829 case PORT_CLK_SEL_SPLL:
830 pll_name = "SPLL";
831 reg = SPLL_CTL;
832 refcount = plls->spll_refcount;
833 new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
834 SPLL_PLL_SSC;
835 break;
836
837 case PORT_CLK_SEL_WRPLL1:
838 case PORT_CLK_SEL_WRPLL2:
839 if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
840 pll_name = "WRPLL1";
841 reg = WRPLL_CTL1;
842 refcount = plls->wrpll1_refcount;
843 } else {
844 pll_name = "WRPLL2";
845 reg = WRPLL_CTL2;
846 refcount = plls->wrpll2_refcount;
847 }
848
849 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
850
851 new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
852 WRPLL_DIVIDER_REFERENCE(r2) |
853 WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
854
855 break;
856
857 case PORT_CLK_SEL_NONE:
858 WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
859 return;
860 default:
861 WARN(1, "Bad selected pll: 0x%08x\n", crtc->ddi_pll_sel);
862 return;
863 }
864
865 cur_val = I915_READ(reg);
866
867 WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
868 if (refcount == 1) {
869 WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
870 I915_WRITE(reg, new_val);
871 POSTING_READ(reg);
872 udelay(20);
873 } else {
874 WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
875 }
876 }
877
878 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
879 {
880 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
883 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
884 int type = intel_encoder->type;
885 uint32_t temp;
886
887 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
888
889 temp = TRANS_MSA_SYNC_CLK;
890 switch (intel_crtc->config.pipe_bpp) {
891 case 18:
892 temp |= TRANS_MSA_6_BPC;
893 break;
894 case 24:
895 temp |= TRANS_MSA_8_BPC;
896 break;
897 case 30:
898 temp |= TRANS_MSA_10_BPC;
899 break;
900 case 36:
901 temp |= TRANS_MSA_12_BPC;
902 break;
903 default:
904 BUG();
905 }
906 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
907 }
908 }
909
910 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
911 {
912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
913 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
914 struct drm_encoder *encoder = &intel_encoder->base;
915 struct drm_device *dev = crtc->dev;
916 struct drm_i915_private *dev_priv = dev->dev_private;
917 enum pipe pipe = intel_crtc->pipe;
918 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
919 enum port port = intel_ddi_get_encoder_port(intel_encoder);
920 int type = intel_encoder->type;
921 uint32_t temp;
922
923 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
924 temp = TRANS_DDI_FUNC_ENABLE;
925 temp |= TRANS_DDI_SELECT_PORT(port);
926
927 switch (intel_crtc->config.pipe_bpp) {
928 case 18:
929 temp |= TRANS_DDI_BPC_6;
930 break;
931 case 24:
932 temp |= TRANS_DDI_BPC_8;
933 break;
934 case 30:
935 temp |= TRANS_DDI_BPC_10;
936 break;
937 case 36:
938 temp |= TRANS_DDI_BPC_12;
939 break;
940 default:
941 BUG();
942 }
943
944 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
945 temp |= TRANS_DDI_PVSYNC;
946 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
947 temp |= TRANS_DDI_PHSYNC;
948
949 if (cpu_transcoder == TRANSCODER_EDP) {
950 switch (pipe) {
951 case PIPE_A:
952 /* On Haswell, can only use the always-on power well for
953 * eDP when not using the panel fitter, and when not
954 * using motion blur mitigation (which we don't
955 * support). */
956 if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
957 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
958 else
959 temp |= TRANS_DDI_EDP_INPUT_A_ON;
960 break;
961 case PIPE_B:
962 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
963 break;
964 case PIPE_C:
965 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
966 break;
967 default:
968 BUG();
969 break;
970 }
971 }
972
973 if (type == INTEL_OUTPUT_HDMI) {
974 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
975
976 if (intel_hdmi->has_hdmi_sink)
977 temp |= TRANS_DDI_MODE_SELECT_HDMI;
978 else
979 temp |= TRANS_DDI_MODE_SELECT_DVI;
980
981 } else if (type == INTEL_OUTPUT_ANALOG) {
982 temp |= TRANS_DDI_MODE_SELECT_FDI;
983 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
984
985 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
986 type == INTEL_OUTPUT_EDP) {
987 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
988
989 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
990
991 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
992 } else {
993 WARN(1, "Invalid encoder type %d for pipe %c\n",
994 intel_encoder->type, pipe_name(pipe));
995 }
996
997 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
998 }
999
1000 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1001 enum transcoder cpu_transcoder)
1002 {
1003 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1004 uint32_t val = I915_READ(reg);
1005
1006 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1007 val |= TRANS_DDI_PORT_NONE;
1008 I915_WRITE(reg, val);
1009 }
1010
1011 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1012 {
1013 struct drm_device *dev = intel_connector->base.dev;
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1015 struct intel_encoder *intel_encoder = intel_connector->encoder;
1016 int type = intel_connector->base.connector_type;
1017 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1018 enum pipe pipe = 0;
1019 enum transcoder cpu_transcoder;
1020 uint32_t tmp;
1021
1022 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1023 return false;
1024
1025 if (port == PORT_A)
1026 cpu_transcoder = TRANSCODER_EDP;
1027 else
1028 cpu_transcoder = (enum transcoder) pipe;
1029
1030 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1031
1032 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1033 case TRANS_DDI_MODE_SELECT_HDMI:
1034 case TRANS_DDI_MODE_SELECT_DVI:
1035 return (type == DRM_MODE_CONNECTOR_HDMIA);
1036
1037 case TRANS_DDI_MODE_SELECT_DP_SST:
1038 if (type == DRM_MODE_CONNECTOR_eDP)
1039 return true;
1040 case TRANS_DDI_MODE_SELECT_DP_MST:
1041 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1042
1043 case TRANS_DDI_MODE_SELECT_FDI:
1044 return (type == DRM_MODE_CONNECTOR_VGA);
1045
1046 default:
1047 return false;
1048 }
1049 }
1050
1051 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1052 enum pipe *pipe)
1053 {
1054 struct drm_device *dev = encoder->base.dev;
1055 struct drm_i915_private *dev_priv = dev->dev_private;
1056 enum port port = intel_ddi_get_encoder_port(encoder);
1057 u32 tmp;
1058 int i;
1059
1060 tmp = I915_READ(DDI_BUF_CTL(port));
1061
1062 if (!(tmp & DDI_BUF_CTL_ENABLE))
1063 return false;
1064
1065 if (port == PORT_A) {
1066 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1067
1068 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1069 case TRANS_DDI_EDP_INPUT_A_ON:
1070 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1071 *pipe = PIPE_A;
1072 break;
1073 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1074 *pipe = PIPE_B;
1075 break;
1076 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1077 *pipe = PIPE_C;
1078 break;
1079 }
1080
1081 return true;
1082 } else {
1083 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1084 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1085
1086 if ((tmp & TRANS_DDI_PORT_MASK)
1087 == TRANS_DDI_SELECT_PORT(port)) {
1088 *pipe = i;
1089 return true;
1090 }
1091 }
1092 }
1093
1094 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1095
1096 return false;
1097 }
1098
1099 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1100 enum pipe pipe)
1101 {
1102 uint32_t temp, ret;
1103 enum port port = I915_MAX_PORTS;
1104 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1105 pipe);
1106 int i;
1107
1108 if (cpu_transcoder == TRANSCODER_EDP) {
1109 port = PORT_A;
1110 } else {
1111 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1112 temp &= TRANS_DDI_PORT_MASK;
1113
1114 for (i = PORT_B; i <= PORT_E; i++)
1115 if (temp == TRANS_DDI_SELECT_PORT(i))
1116 port = i;
1117 }
1118
1119 if (port == I915_MAX_PORTS) {
1120 WARN(1, "Pipe %c enabled on an unknown port\n",
1121 pipe_name(pipe));
1122 ret = PORT_CLK_SEL_NONE;
1123 } else {
1124 ret = I915_READ(PORT_CLK_SEL(port));
1125 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1126 "0x%08x\n", pipe_name(pipe), port_name(port),
1127 ret);
1128 }
1129
1130 return ret;
1131 }
1132
1133 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1134 {
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 enum pipe pipe;
1137 struct intel_crtc *intel_crtc;
1138
1139 dev_priv->ddi_plls.spll_refcount = 0;
1140 dev_priv->ddi_plls.wrpll1_refcount = 0;
1141 dev_priv->ddi_plls.wrpll2_refcount = 0;
1142
1143 for_each_pipe(pipe) {
1144 intel_crtc =
1145 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1146
1147 if (!intel_crtc->active) {
1148 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
1149 continue;
1150 }
1151
1152 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1153 pipe);
1154
1155 switch (intel_crtc->ddi_pll_sel) {
1156 case PORT_CLK_SEL_SPLL:
1157 dev_priv->ddi_plls.spll_refcount++;
1158 break;
1159 case PORT_CLK_SEL_WRPLL1:
1160 dev_priv->ddi_plls.wrpll1_refcount++;
1161 break;
1162 case PORT_CLK_SEL_WRPLL2:
1163 dev_priv->ddi_plls.wrpll2_refcount++;
1164 break;
1165 }
1166 }
1167 }
1168
1169 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1170 {
1171 struct drm_crtc *crtc = &intel_crtc->base;
1172 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1173 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1174 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1175 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1176
1177 if (cpu_transcoder != TRANSCODER_EDP)
1178 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1179 TRANS_CLK_SEL_PORT(port));
1180 }
1181
1182 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1183 {
1184 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1185 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1186
1187 if (cpu_transcoder != TRANSCODER_EDP)
1188 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1189 TRANS_CLK_SEL_DISABLED);
1190 }
1191
1192 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1193 {
1194 struct drm_encoder *encoder = &intel_encoder->base;
1195 struct drm_crtc *crtc = encoder->crtc;
1196 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1198 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1199 int type = intel_encoder->type;
1200
1201 if (type == INTEL_OUTPUT_EDP) {
1202 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1203 ironlake_edp_panel_on(intel_dp);
1204 }
1205
1206 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1207 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1208
1209 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1210 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1211
1212 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1213 intel_dp_start_link_train(intel_dp);
1214 intel_dp_complete_link_train(intel_dp);
1215 if (port != PORT_A)
1216 intel_dp_stop_link_train(intel_dp);
1217 }
1218 }
1219
1220 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1221 {
1222 struct drm_encoder *encoder = &intel_encoder->base;
1223 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1224 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1225 int type = intel_encoder->type;
1226 uint32_t val;
1227 bool wait = false;
1228
1229 val = I915_READ(DDI_BUF_CTL(port));
1230 if (val & DDI_BUF_CTL_ENABLE) {
1231 val &= ~DDI_BUF_CTL_ENABLE;
1232 I915_WRITE(DDI_BUF_CTL(port), val);
1233 wait = true;
1234 }
1235
1236 val = I915_READ(DP_TP_CTL(port));
1237 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1238 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1239 I915_WRITE(DP_TP_CTL(port), val);
1240
1241 if (wait)
1242 intel_wait_ddi_buf_idle(dev_priv, port);
1243
1244 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1245 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1246 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1247 ironlake_edp_panel_vdd_on(intel_dp);
1248 ironlake_edp_panel_off(intel_dp);
1249 }
1250
1251 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1252 }
1253
1254 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1255 {
1256 struct drm_encoder *encoder = &intel_encoder->base;
1257 struct drm_crtc *crtc = encoder->crtc;
1258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1259 int pipe = intel_crtc->pipe;
1260 struct drm_device *dev = encoder->dev;
1261 struct drm_i915_private *dev_priv = dev->dev_private;
1262 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1263 int type = intel_encoder->type;
1264 uint32_t tmp;
1265
1266 if (type == INTEL_OUTPUT_HDMI) {
1267 struct intel_digital_port *intel_dig_port =
1268 enc_to_dig_port(encoder);
1269
1270 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1271 * are ignored so nothing special needs to be done besides
1272 * enabling the port.
1273 */
1274 I915_WRITE(DDI_BUF_CTL(port),
1275 intel_dig_port->saved_port_bits |
1276 DDI_BUF_CTL_ENABLE);
1277 } else if (type == INTEL_OUTPUT_EDP) {
1278 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1279
1280 if (port == PORT_A)
1281 intel_dp_stop_link_train(intel_dp);
1282
1283 ironlake_edp_backlight_on(intel_dp);
1284 intel_edp_psr_enable(intel_dp);
1285 }
1286
1287 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1288 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1289 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1290 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1291 }
1292 }
1293
1294 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1295 {
1296 struct drm_encoder *encoder = &intel_encoder->base;
1297 struct drm_crtc *crtc = encoder->crtc;
1298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1299 int pipe = intel_crtc->pipe;
1300 int type = intel_encoder->type;
1301 struct drm_device *dev = encoder->dev;
1302 struct drm_i915_private *dev_priv = dev->dev_private;
1303 uint32_t tmp;
1304
1305 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1306 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1307 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1308 (pipe * 4));
1309 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1310 }
1311
1312 if (type == INTEL_OUTPUT_EDP) {
1313 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1314
1315 intel_edp_psr_disable(intel_dp);
1316 ironlake_edp_backlight_off(intel_dp);
1317 }
1318 }
1319
1320 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1321 {
1322 struct drm_device *dev = dev_priv->dev;
1323 uint32_t lcpll = I915_READ(LCPLL_CTL);
1324 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1325
1326 if (lcpll & LCPLL_CD_SOURCE_FCLK) {
1327 return 800000;
1328 } else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) {
1329 return 450000;
1330 } else if (freq == LCPLL_CLK_FREQ_450) {
1331 return 450000;
1332 } else if (IS_HASWELL(dev)) {
1333 if (IS_ULT(dev))
1334 return 337500;
1335 else
1336 return 540000;
1337 } else {
1338 if (freq == LCPLL_CLK_FREQ_54O_BDW)
1339 return 540000;
1340 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1341 return 337500;
1342 else
1343 return 675000;
1344 }
1345 }
1346
1347 void intel_ddi_pll_init(struct drm_device *dev)
1348 {
1349 struct drm_i915_private *dev_priv = dev->dev_private;
1350 uint32_t val = I915_READ(LCPLL_CTL);
1351
1352 /* The LCPLL register should be turned on by the BIOS. For now let's
1353 * just check its state and print errors in case something is wrong.
1354 * Don't even try to turn it on.
1355 */
1356
1357 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1358 intel_ddi_get_cdclk_freq(dev_priv));
1359
1360 if (val & LCPLL_CD_SOURCE_FCLK)
1361 DRM_ERROR("CDCLK source is not LCPLL\n");
1362
1363 if (val & LCPLL_PLL_DISABLE)
1364 DRM_ERROR("LCPLL is disabled\n");
1365 }
1366
1367 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1368 {
1369 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1370 struct intel_dp *intel_dp = &intel_dig_port->dp;
1371 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1372 enum port port = intel_dig_port->port;
1373 uint32_t val;
1374 bool wait = false;
1375
1376 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1377 val = I915_READ(DDI_BUF_CTL(port));
1378 if (val & DDI_BUF_CTL_ENABLE) {
1379 val &= ~DDI_BUF_CTL_ENABLE;
1380 I915_WRITE(DDI_BUF_CTL(port), val);
1381 wait = true;
1382 }
1383
1384 val = I915_READ(DP_TP_CTL(port));
1385 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1386 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1387 I915_WRITE(DP_TP_CTL(port), val);
1388 POSTING_READ(DP_TP_CTL(port));
1389
1390 if (wait)
1391 intel_wait_ddi_buf_idle(dev_priv, port);
1392 }
1393
1394 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1395 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1396 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1397 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1398 I915_WRITE(DP_TP_CTL(port), val);
1399 POSTING_READ(DP_TP_CTL(port));
1400
1401 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1402 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1403 POSTING_READ(DDI_BUF_CTL(port));
1404
1405 udelay(600);
1406 }
1407
1408 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1409 {
1410 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1411 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1412 uint32_t val;
1413
1414 intel_ddi_post_disable(intel_encoder);
1415
1416 val = I915_READ(_FDI_RXA_CTL);
1417 val &= ~FDI_RX_ENABLE;
1418 I915_WRITE(_FDI_RXA_CTL, val);
1419
1420 val = I915_READ(_FDI_RXA_MISC);
1421 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1422 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1423 I915_WRITE(_FDI_RXA_MISC, val);
1424
1425 val = I915_READ(_FDI_RXA_CTL);
1426 val &= ~FDI_PCDCLK;
1427 I915_WRITE(_FDI_RXA_CTL, val);
1428
1429 val = I915_READ(_FDI_RXA_CTL);
1430 val &= ~FDI_RX_PLL_ENABLE;
1431 I915_WRITE(_FDI_RXA_CTL, val);
1432 }
1433
1434 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1435 {
1436 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1437 int type = intel_encoder->type;
1438
1439 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1440 intel_dp_check_link_status(intel_dp);
1441 }
1442
1443 void intel_ddi_get_config(struct intel_encoder *encoder,
1444 struct intel_crtc_config *pipe_config)
1445 {
1446 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1447 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1448 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1449 u32 temp, flags = 0;
1450
1451 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1452 if (temp & TRANS_DDI_PHSYNC)
1453 flags |= DRM_MODE_FLAG_PHSYNC;
1454 else
1455 flags |= DRM_MODE_FLAG_NHSYNC;
1456 if (temp & TRANS_DDI_PVSYNC)
1457 flags |= DRM_MODE_FLAG_PVSYNC;
1458 else
1459 flags |= DRM_MODE_FLAG_NVSYNC;
1460
1461 pipe_config->adjusted_mode.flags |= flags;
1462
1463 switch (temp & TRANS_DDI_BPC_MASK) {
1464 case TRANS_DDI_BPC_6:
1465 pipe_config->pipe_bpp = 18;
1466 break;
1467 case TRANS_DDI_BPC_8:
1468 pipe_config->pipe_bpp = 24;
1469 break;
1470 case TRANS_DDI_BPC_10:
1471 pipe_config->pipe_bpp = 30;
1472 break;
1473 case TRANS_DDI_BPC_12:
1474 pipe_config->pipe_bpp = 36;
1475 break;
1476 default:
1477 break;
1478 }
1479
1480 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1481 case TRANS_DDI_MODE_SELECT_HDMI:
1482 case TRANS_DDI_MODE_SELECT_DVI:
1483 case TRANS_DDI_MODE_SELECT_FDI:
1484 break;
1485 case TRANS_DDI_MODE_SELECT_DP_SST:
1486 case TRANS_DDI_MODE_SELECT_DP_MST:
1487 pipe_config->has_dp_encoder = true;
1488 intel_dp_get_m_n(intel_crtc, pipe_config);
1489 break;
1490 default:
1491 break;
1492 }
1493
1494 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1495 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1496 /*
1497 * This is a big fat ugly hack.
1498 *
1499 * Some machines in UEFI boot mode provide us a VBT that has 18
1500 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1501 * unknown we fail to light up. Yet the same BIOS boots up with
1502 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1503 * max, not what it tells us to use.
1504 *
1505 * Note: This will still be broken if the eDP panel is not lit
1506 * up by the BIOS, and thus we can't get the mode at module
1507 * load.
1508 */
1509 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1510 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1511 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1512 }
1513 }
1514
1515 static void intel_ddi_destroy(struct drm_encoder *encoder)
1516 {
1517 /* HDMI has nothing special to destroy, so we can go with this. */
1518 intel_dp_encoder_destroy(encoder);
1519 }
1520
1521 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1522 struct intel_crtc_config *pipe_config)
1523 {
1524 int type = encoder->type;
1525 int port = intel_ddi_get_encoder_port(encoder);
1526
1527 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1528
1529 if (port == PORT_A)
1530 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1531
1532 if (type == INTEL_OUTPUT_HDMI)
1533 return intel_hdmi_compute_config(encoder, pipe_config);
1534 else
1535 return intel_dp_compute_config(encoder, pipe_config);
1536 }
1537
1538 static const struct drm_encoder_funcs intel_ddi_funcs = {
1539 .destroy = intel_ddi_destroy,
1540 };
1541
1542 static struct intel_connector *
1543 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1544 {
1545 struct intel_connector *connector;
1546 enum port port = intel_dig_port->port;
1547
1548 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1549 if (!connector)
1550 return NULL;
1551
1552 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1553 if (!intel_dp_init_connector(intel_dig_port, connector)) {
1554 kfree(connector);
1555 return NULL;
1556 }
1557
1558 return connector;
1559 }
1560
1561 static struct intel_connector *
1562 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1563 {
1564 struct intel_connector *connector;
1565 enum port port = intel_dig_port->port;
1566
1567 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1568 if (!connector)
1569 return NULL;
1570
1571 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1572 intel_hdmi_init_connector(intel_dig_port, connector);
1573
1574 return connector;
1575 }
1576
1577 void intel_ddi_init(struct drm_device *dev, enum port port)
1578 {
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580 struct intel_digital_port *intel_dig_port;
1581 struct intel_encoder *intel_encoder;
1582 struct drm_encoder *encoder;
1583 struct intel_connector *hdmi_connector = NULL;
1584 struct intel_connector *dp_connector = NULL;
1585 bool init_hdmi, init_dp;
1586
1587 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1588 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1589 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1590 if (!init_dp && !init_hdmi) {
1591 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1592 port_name(port));
1593 init_hdmi = true;
1594 init_dp = true;
1595 }
1596
1597 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1598 if (!intel_dig_port)
1599 return;
1600
1601 intel_encoder = &intel_dig_port->base;
1602 encoder = &intel_encoder->base;
1603
1604 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1605 DRM_MODE_ENCODER_TMDS);
1606
1607 intel_encoder->compute_config = intel_ddi_compute_config;
1608 intel_encoder->mode_set = intel_ddi_mode_set;
1609 intel_encoder->enable = intel_enable_ddi;
1610 intel_encoder->pre_enable = intel_ddi_pre_enable;
1611 intel_encoder->disable = intel_disable_ddi;
1612 intel_encoder->post_disable = intel_ddi_post_disable;
1613 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1614 intel_encoder->get_config = intel_ddi_get_config;
1615
1616 intel_dig_port->port = port;
1617 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1618 (DDI_BUF_PORT_REVERSAL |
1619 DDI_A_4_LANES);
1620
1621 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1622 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1623 intel_encoder->cloneable = false;
1624 intel_encoder->hot_plug = intel_ddi_hot_plug;
1625
1626 if (init_dp)
1627 dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
1628
1629 /* In theory we don't need the encoder->type check, but leave it just in
1630 * case we have some really bad VBTs... */
1631 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
1632 hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
1633
1634 if (!dp_connector && !hdmi_connector) {
1635 drm_encoder_cleanup(encoder);
1636 kfree(intel_dig_port);
1637 }
1638 }
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