2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
34 u8 i_boost
; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
37 static const u8 index_to_dp_signal_levels
[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
,
50 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
54 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
66 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
78 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
79 /* Idx NT mV d T mV d db */
80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
94 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
106 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
118 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
130 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
131 /* Idx NT mV d T mV df db */
132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
144 /* Skylake H and S */
145 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x000000DF, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
158 static const struct ddi_buf_trans skl_u_ddi_translations_dp
[] = {
159 { 0x0000201B, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x1 },
162 { 0x80009010, 0x000000C0, 0x1 },
163 { 0x0000201B, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
166 { 0x00002016, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x1 },
171 static const struct ddi_buf_trans skl_y_ddi_translations_dp
[] = {
172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
174 { 0x80007011, 0x000000CD, 0x3 },
175 { 0x80009010, 0x000000C0, 0x3 },
176 { 0x00000018, 0x0000009D, 0x0 },
177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
179 { 0x00000018, 0x00000088, 0x0 },
180 { 0x80005012, 0x000000C0, 0x3 },
183 /* Kabylake H and S */
184 static const struct ddi_buf_trans kbl_ddi_translations_dp
[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
197 static const struct ddi_buf_trans kbl_u_ddi_translations_dp
[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
210 static const struct ddi_buf_trans kbl_y_ddi_translations_dp
[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
223 * Skylake/Kabylake H and S
224 * eDP 1.4 low vswing translation parameters
226 static const struct ddi_buf_trans skl_ddi_translations_edp
[] = {
227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
241 * eDP 1.4 low vswing translation parameters
243 static const struct ddi_buf_trans skl_u_ddi_translations_edp
[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
258 * eDP 1.4 low vswing translation parameters
260 static const struct ddi_buf_trans skl_y_ddi_translations_edp
[] = {
261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
273 /* Skylake/Kabylake U, H and S */
274 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
281 { 0x80006012, 0x000000CD, 0x1 },
282 { 0x00000018, 0x000000DF, 0x0 },
283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
288 /* Skylake/Kabylake Y */
289 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi
[] = {
290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
292 { 0x80007011, 0x000000CB, 0x3 },
293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
296 { 0x80006013, 0x000000C0, 0x3 },
297 { 0x00000018, 0x0000008A, 0x0 },
298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
303 struct bxt_ddi_buf_trans
{
304 u8 margin
; /* swing value */
305 u8 scale
; /* scale value */
306 u8 enable
; /* scale enable */
310 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp
[] = {
311 /* Idx NT mV diff db */
312 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
313 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
314 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
315 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
316 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
317 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
318 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
319 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
320 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
321 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
324 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp
[] = {
325 /* Idx NT mV diff db */
326 { 26, 0, 0, 128, }, /* 0: 200 0 */
327 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
328 { 48, 0, 0, 96, }, /* 2: 200 4 */
329 { 54, 0, 0, 69, }, /* 3: 200 6 */
330 { 32, 0, 0, 128, }, /* 4: 250 0 */
331 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
332 { 54, 0, 0, 85, }, /* 6: 250 4 */
333 { 43, 0, 0, 128, }, /* 7: 300 0 */
334 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
335 { 48, 0, 0, 128, }, /* 9: 300 0 */
338 /* BSpec has 2 recommended values - entries 0 and 8.
339 * Using the entry with higher vswing.
341 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi
[] = {
342 /* Idx NT mV diff db */
343 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
344 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
345 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
346 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
347 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
348 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
349 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
350 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
351 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
352 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
355 struct cnl_ddi_buf_trans
{
359 u8 dw4_post_cursor_2
;
360 u8 dw4_post_cursor_1
;
363 /* Voltage Swing Programming for VccIO 0.85V for DP */
364 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V
[] = {
365 /* NT mV Trans mV db */
366 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
367 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
368 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
369 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
370 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
371 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
372 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
373 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
374 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
375 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
378 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
379 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V
[] = {
380 /* NT mV Trans mV db */
381 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
382 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
383 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
384 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
385 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
386 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
387 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
390 /* Voltage Swing Programming for VccIO 0.85V for eDP */
391 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V
[] = {
392 /* NT mV Trans mV db */
393 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
394 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
395 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
396 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
397 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
398 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
399 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
400 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
401 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
404 /* Voltage Swing Programming for VccIO 0.95V for DP */
405 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V
[] = {
406 /* NT mV Trans mV db */
407 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
408 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
409 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
410 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
411 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
412 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
413 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
414 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
415 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
416 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
419 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
420 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V
[] = {
421 /* NT mV Trans mV db */
422 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
423 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
424 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
425 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
426 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
427 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
428 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
429 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
430 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
431 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
432 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
435 /* Voltage Swing Programming for VccIO 0.95V for eDP */
436 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V
[] = {
437 /* NT mV Trans mV db */
438 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
439 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
440 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
441 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
442 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
443 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
444 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
445 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
446 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
447 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
450 /* Voltage Swing Programming for VccIO 1.05V for DP */
451 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V
[] = {
452 /* NT mV Trans mV db */
453 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
454 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
455 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
456 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
457 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
458 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
459 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
460 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
461 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
462 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
465 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
466 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V
[] = {
467 /* NT mV Trans mV db */
468 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
469 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
470 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
471 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
472 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
473 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
474 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
475 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
476 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
477 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
478 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
481 /* Voltage Swing Programming for VccIO 1.05V for eDP */
482 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V
[] = {
483 /* NT mV Trans mV db */
484 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
485 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
486 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
487 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
488 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
489 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
490 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
491 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
492 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
495 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*encoder
)
497 switch (encoder
->type
) {
498 case INTEL_OUTPUT_DP_MST
:
499 return enc_to_mst(&encoder
->base
)->primary
->port
;
500 case INTEL_OUTPUT_DP
:
501 case INTEL_OUTPUT_EDP
:
502 case INTEL_OUTPUT_HDMI
:
503 case INTEL_OUTPUT_UNKNOWN
:
504 return enc_to_dig_port(&encoder
->base
)->port
;
505 case INTEL_OUTPUT_ANALOG
:
508 MISSING_CASE(encoder
->type
);
513 static const struct ddi_buf_trans
*
514 bdw_get_buf_trans_edp(struct drm_i915_private
*dev_priv
, int *n_entries
)
516 if (dev_priv
->vbt
.edp
.low_vswing
) {
517 *n_entries
= ARRAY_SIZE(bdw_ddi_translations_edp
);
518 return bdw_ddi_translations_edp
;
520 *n_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
521 return bdw_ddi_translations_dp
;
525 static const struct ddi_buf_trans
*
526 skl_get_buf_trans_dp(struct drm_i915_private
*dev_priv
, int *n_entries
)
528 if (IS_SKL_ULX(dev_priv
)) {
529 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_dp
);
530 return skl_y_ddi_translations_dp
;
531 } else if (IS_SKL_ULT(dev_priv
)) {
532 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_dp
);
533 return skl_u_ddi_translations_dp
;
535 *n_entries
= ARRAY_SIZE(skl_ddi_translations_dp
);
536 return skl_ddi_translations_dp
;
540 static const struct ddi_buf_trans
*
541 kbl_get_buf_trans_dp(struct drm_i915_private
*dev_priv
, int *n_entries
)
543 if (IS_KBL_ULX(dev_priv
)) {
544 *n_entries
= ARRAY_SIZE(kbl_y_ddi_translations_dp
);
545 return kbl_y_ddi_translations_dp
;
546 } else if (IS_KBL_ULT(dev_priv
) || IS_CFL_ULT(dev_priv
)) {
547 *n_entries
= ARRAY_SIZE(kbl_u_ddi_translations_dp
);
548 return kbl_u_ddi_translations_dp
;
550 *n_entries
= ARRAY_SIZE(kbl_ddi_translations_dp
);
551 return kbl_ddi_translations_dp
;
555 static const struct ddi_buf_trans
*
556 skl_get_buf_trans_edp(struct drm_i915_private
*dev_priv
, int *n_entries
)
558 if (dev_priv
->vbt
.edp
.low_vswing
) {
559 if (IS_SKL_ULX(dev_priv
) || IS_KBL_ULX(dev_priv
)) {
560 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_edp
);
561 return skl_y_ddi_translations_edp
;
562 } else if (IS_SKL_ULT(dev_priv
) || IS_KBL_ULT(dev_priv
) ||
563 IS_CFL_ULT(dev_priv
)) {
564 *n_entries
= ARRAY_SIZE(skl_u_ddi_translations_edp
);
565 return skl_u_ddi_translations_edp
;
567 *n_entries
= ARRAY_SIZE(skl_ddi_translations_edp
);
568 return skl_ddi_translations_edp
;
572 if (IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
))
573 return kbl_get_buf_trans_dp(dev_priv
, n_entries
);
575 return skl_get_buf_trans_dp(dev_priv
, n_entries
);
578 static const struct ddi_buf_trans
*
579 skl_get_buf_trans_hdmi(struct drm_i915_private
*dev_priv
, int *n_entries
)
581 if (IS_SKL_ULX(dev_priv
) || IS_KBL_ULX(dev_priv
)) {
582 *n_entries
= ARRAY_SIZE(skl_y_ddi_translations_hdmi
);
583 return skl_y_ddi_translations_hdmi
;
585 *n_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
586 return skl_ddi_translations_hdmi
;
590 static int skl_buf_trans_num_entries(enum port port
, int n_entries
)
592 /* Only DDIA and DDIE can select the 10th register with DP */
593 if (port
== PORT_A
|| port
== PORT_E
)
594 return min(n_entries
, 10);
596 return min(n_entries
, 9);
599 static const struct ddi_buf_trans
*
600 intel_ddi_get_buf_trans_dp(struct drm_i915_private
*dev_priv
,
601 enum port port
, int *n_entries
)
603 if (IS_KABYLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
)) {
604 const struct ddi_buf_trans
*ddi_translations
=
605 kbl_get_buf_trans_dp(dev_priv
, n_entries
);
606 *n_entries
= skl_buf_trans_num_entries(port
, *n_entries
);
607 return ddi_translations
;
608 } else if (IS_SKYLAKE(dev_priv
)) {
609 const struct ddi_buf_trans
*ddi_translations
=
610 skl_get_buf_trans_dp(dev_priv
, n_entries
);
611 *n_entries
= skl_buf_trans_num_entries(port
, *n_entries
);
612 return ddi_translations
;
613 } else if (IS_BROADWELL(dev_priv
)) {
614 *n_entries
= ARRAY_SIZE(bdw_ddi_translations_dp
);
615 return bdw_ddi_translations_dp
;
616 } else if (IS_HASWELL(dev_priv
)) {
617 *n_entries
= ARRAY_SIZE(hsw_ddi_translations_dp
);
618 return hsw_ddi_translations_dp
;
625 static const struct ddi_buf_trans
*
626 intel_ddi_get_buf_trans_edp(struct drm_i915_private
*dev_priv
,
627 enum port port
, int *n_entries
)
629 if (IS_GEN9_BC(dev_priv
)) {
630 const struct ddi_buf_trans
*ddi_translations
=
631 skl_get_buf_trans_edp(dev_priv
, n_entries
);
632 *n_entries
= skl_buf_trans_num_entries(port
, *n_entries
);
633 return ddi_translations
;
634 } else if (IS_BROADWELL(dev_priv
)) {
635 return bdw_get_buf_trans_edp(dev_priv
, n_entries
);
636 } else if (IS_HASWELL(dev_priv
)) {
637 *n_entries
= ARRAY_SIZE(hsw_ddi_translations_dp
);
638 return hsw_ddi_translations_dp
;
645 static const struct ddi_buf_trans
*
646 intel_ddi_get_buf_trans_fdi(struct drm_i915_private
*dev_priv
,
649 if (IS_BROADWELL(dev_priv
)) {
650 *n_entries
= ARRAY_SIZE(bdw_ddi_translations_fdi
);
651 return bdw_ddi_translations_fdi
;
652 } else if (IS_HASWELL(dev_priv
)) {
653 *n_entries
= ARRAY_SIZE(hsw_ddi_translations_fdi
);
654 return hsw_ddi_translations_fdi
;
661 static const struct ddi_buf_trans
*
662 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private
*dev_priv
,
665 if (IS_GEN9_BC(dev_priv
)) {
666 return skl_get_buf_trans_hdmi(dev_priv
, n_entries
);
667 } else if (IS_BROADWELL(dev_priv
)) {
668 *n_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
669 return bdw_ddi_translations_hdmi
;
670 } else if (IS_HASWELL(dev_priv
)) {
671 *n_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
672 return hsw_ddi_translations_hdmi
;
679 static const struct bxt_ddi_buf_trans
*
680 bxt_get_buf_trans_dp(struct drm_i915_private
*dev_priv
, int *n_entries
)
682 *n_entries
= ARRAY_SIZE(bxt_ddi_translations_dp
);
683 return bxt_ddi_translations_dp
;
686 static const struct bxt_ddi_buf_trans
*
687 bxt_get_buf_trans_edp(struct drm_i915_private
*dev_priv
, int *n_entries
)
689 if (dev_priv
->vbt
.edp
.low_vswing
) {
690 *n_entries
= ARRAY_SIZE(bxt_ddi_translations_edp
);
691 return bxt_ddi_translations_edp
;
694 return bxt_get_buf_trans_dp(dev_priv
, n_entries
);
697 static const struct bxt_ddi_buf_trans
*
698 bxt_get_buf_trans_hdmi(struct drm_i915_private
*dev_priv
, int *n_entries
)
700 *n_entries
= ARRAY_SIZE(bxt_ddi_translations_hdmi
);
701 return bxt_ddi_translations_hdmi
;
704 static const struct cnl_ddi_buf_trans
*
705 cnl_get_buf_trans_hdmi(struct drm_i915_private
*dev_priv
, int *n_entries
)
707 u32 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
709 if (voltage
== VOLTAGE_INFO_0_85V
) {
710 *n_entries
= ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V
);
711 return cnl_ddi_translations_hdmi_0_85V
;
712 } else if (voltage
== VOLTAGE_INFO_0_95V
) {
713 *n_entries
= ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V
);
714 return cnl_ddi_translations_hdmi_0_95V
;
715 } else if (voltage
== VOLTAGE_INFO_1_05V
) {
716 *n_entries
= ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V
);
717 return cnl_ddi_translations_hdmi_1_05V
;
719 *n_entries
= 1; /* shut up gcc */
720 MISSING_CASE(voltage
);
725 static const struct cnl_ddi_buf_trans
*
726 cnl_get_buf_trans_dp(struct drm_i915_private
*dev_priv
, int *n_entries
)
728 u32 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
730 if (voltage
== VOLTAGE_INFO_0_85V
) {
731 *n_entries
= ARRAY_SIZE(cnl_ddi_translations_dp_0_85V
);
732 return cnl_ddi_translations_dp_0_85V
;
733 } else if (voltage
== VOLTAGE_INFO_0_95V
) {
734 *n_entries
= ARRAY_SIZE(cnl_ddi_translations_dp_0_95V
);
735 return cnl_ddi_translations_dp_0_95V
;
736 } else if (voltage
== VOLTAGE_INFO_1_05V
) {
737 *n_entries
= ARRAY_SIZE(cnl_ddi_translations_dp_1_05V
);
738 return cnl_ddi_translations_dp_1_05V
;
740 *n_entries
= 1; /* shut up gcc */
741 MISSING_CASE(voltage
);
746 static const struct cnl_ddi_buf_trans
*
747 cnl_get_buf_trans_edp(struct drm_i915_private
*dev_priv
, int *n_entries
)
749 u32 voltage
= I915_READ(CNL_PORT_COMP_DW3
) & VOLTAGE_INFO_MASK
;
751 if (dev_priv
->vbt
.edp
.low_vswing
) {
752 if (voltage
== VOLTAGE_INFO_0_85V
) {
753 *n_entries
= ARRAY_SIZE(cnl_ddi_translations_edp_0_85V
);
754 return cnl_ddi_translations_edp_0_85V
;
755 } else if (voltage
== VOLTAGE_INFO_0_95V
) {
756 *n_entries
= ARRAY_SIZE(cnl_ddi_translations_edp_0_95V
);
757 return cnl_ddi_translations_edp_0_95V
;
758 } else if (voltage
== VOLTAGE_INFO_1_05V
) {
759 *n_entries
= ARRAY_SIZE(cnl_ddi_translations_edp_1_05V
);
760 return cnl_ddi_translations_edp_1_05V
;
762 *n_entries
= 1; /* shut up gcc */
763 MISSING_CASE(voltage
);
767 return cnl_get_buf_trans_dp(dev_priv
, n_entries
);
771 static int intel_ddi_hdmi_level(struct drm_i915_private
*dev_priv
, enum port port
)
773 int n_entries
, level
, default_entry
;
775 level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
777 if (IS_CANNONLAKE(dev_priv
)) {
778 cnl_get_buf_trans_hdmi(dev_priv
, &n_entries
);
779 default_entry
= n_entries
- 1;
780 } else if (IS_GEN9_LP(dev_priv
)) {
781 bxt_get_buf_trans_hdmi(dev_priv
, &n_entries
);
782 default_entry
= n_entries
- 1;
783 } else if (IS_GEN9_BC(dev_priv
)) {
784 intel_ddi_get_buf_trans_hdmi(dev_priv
, &n_entries
);
786 } else if (IS_BROADWELL(dev_priv
)) {
787 intel_ddi_get_buf_trans_hdmi(dev_priv
, &n_entries
);
789 } else if (IS_HASWELL(dev_priv
)) {
790 intel_ddi_get_buf_trans_hdmi(dev_priv
, &n_entries
);
793 WARN(1, "ddi translation table missing\n");
797 /* Choose a good default if VBT is badly populated */
798 if (level
== HDMI_LEVEL_SHIFT_UNKNOWN
|| level
>= n_entries
)
799 level
= default_entry
;
801 if (WARN_ON_ONCE(n_entries
== 0))
803 if (WARN_ON_ONCE(level
>= n_entries
))
804 level
= n_entries
- 1;
810 * Starting with Haswell, DDI port buffers must be programmed with correct
811 * values in advance. This function programs the correct values for
812 * DP/eDP/FDI use cases.
814 static void intel_prepare_dp_ddi_buffers(struct intel_encoder
*encoder
)
816 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
819 enum port port
= intel_ddi_get_encoder_port(encoder
);
820 const struct ddi_buf_trans
*ddi_translations
;
822 switch (encoder
->type
) {
823 case INTEL_OUTPUT_EDP
:
824 ddi_translations
= intel_ddi_get_buf_trans_edp(dev_priv
, port
,
827 case INTEL_OUTPUT_DP
:
828 ddi_translations
= intel_ddi_get_buf_trans_dp(dev_priv
, port
,
831 case INTEL_OUTPUT_ANALOG
:
832 ddi_translations
= intel_ddi_get_buf_trans_fdi(dev_priv
,
836 MISSING_CASE(encoder
->type
);
840 /* If we're boosting the current, set bit 31 of trans1 */
841 if (IS_GEN9_BC(dev_priv
) &&
842 dev_priv
->vbt
.ddi_port_info
[port
].dp_boost_level
)
843 iboost_bit
= DDI_BUF_BALANCE_LEG_ENABLE
;
845 for (i
= 0; i
< n_entries
; i
++) {
846 I915_WRITE(DDI_BUF_TRANS_LO(port
, i
),
847 ddi_translations
[i
].trans1
| iboost_bit
);
848 I915_WRITE(DDI_BUF_TRANS_HI(port
, i
),
849 ddi_translations
[i
].trans2
);
854 * Starting with Haswell, DDI port buffers must be programmed with correct
855 * values in advance. This function programs the correct values for
856 * HDMI/DVI use cases.
858 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder
*encoder
,
861 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
864 enum port port
= intel_ddi_get_encoder_port(encoder
);
865 const struct ddi_buf_trans
*ddi_translations
;
867 ddi_translations
= intel_ddi_get_buf_trans_hdmi(dev_priv
, &n_entries
);
869 if (WARN_ON_ONCE(!ddi_translations
))
871 if (WARN_ON_ONCE(level
>= n_entries
))
872 level
= n_entries
- 1;
874 /* If we're boosting the current, set bit 31 of trans1 */
875 if (IS_GEN9_BC(dev_priv
) &&
876 dev_priv
->vbt
.ddi_port_info
[port
].hdmi_boost_level
)
877 iboost_bit
= DDI_BUF_BALANCE_LEG_ENABLE
;
879 /* Entry 9 is for HDMI: */
880 I915_WRITE(DDI_BUF_TRANS_LO(port
, 9),
881 ddi_translations
[level
].trans1
| iboost_bit
);
882 I915_WRITE(DDI_BUF_TRANS_HI(port
, 9),
883 ddi_translations
[level
].trans2
);
886 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
889 i915_reg_t reg
= DDI_BUF_CTL(port
);
892 for (i
= 0; i
< 16; i
++) {
894 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
897 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
900 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll
*pll
)
904 return PORT_CLK_SEL_WRPLL1
;
906 return PORT_CLK_SEL_WRPLL2
;
908 return PORT_CLK_SEL_SPLL
;
909 case DPLL_ID_LCPLL_810
:
910 return PORT_CLK_SEL_LCPLL_810
;
911 case DPLL_ID_LCPLL_1350
:
912 return PORT_CLK_SEL_LCPLL_1350
;
913 case DPLL_ID_LCPLL_2700
:
914 return PORT_CLK_SEL_LCPLL_2700
;
916 MISSING_CASE(pll
->id
);
917 return PORT_CLK_SEL_NONE
;
921 /* Starting with Haswell, different DDI ports can work in FDI mode for
922 * connection to the PCH-located connectors. For this, it is necessary to train
923 * both the DDI port and PCH receiver for the desired DDI buffer settings.
925 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
926 * please note that when FDI mode is active on DDI E, it shares 2 lines with
927 * DDI A (which is used for eDP)
930 void hsw_fdi_link_train(struct intel_crtc
*crtc
,
931 const struct intel_crtc_state
*crtc_state
)
933 struct drm_device
*dev
= crtc
->base
.dev
;
934 struct drm_i915_private
*dev_priv
= to_i915(dev
);
935 struct intel_encoder
*encoder
;
936 u32 temp
, i
, rx_ctl_val
, ddi_pll_sel
;
938 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
939 WARN_ON(encoder
->type
!= INTEL_OUTPUT_ANALOG
);
940 intel_prepare_dp_ddi_buffers(encoder
);
943 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
944 * mode set "sequence for CRT port" document:
945 * - TP1 to TP2 time with the default value
948 * WaFDIAutoLinkSetTimingOverrride:hsw
950 I915_WRITE(FDI_RX_MISC(PIPE_A
), FDI_RX_PWRDN_LANE1_VAL(2) |
951 FDI_RX_PWRDN_LANE0_VAL(2) |
952 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
954 /* Enable the PCH Receiver FDI PLL */
955 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
957 FDI_DP_PORT_WIDTH(crtc_state
->fdi_lanes
);
958 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
959 POSTING_READ(FDI_RX_CTL(PIPE_A
));
962 /* Switch from Rawclk to PCDclk */
963 rx_ctl_val
|= FDI_PCDCLK
;
964 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
966 /* Configure Port Clock Select */
967 ddi_pll_sel
= hsw_pll_to_ddi_pll_sel(crtc_state
->shared_dpll
);
968 I915_WRITE(PORT_CLK_SEL(PORT_E
), ddi_pll_sel
);
969 WARN_ON(ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
971 /* Start the training iterating through available voltages and emphasis,
972 * testing each value twice. */
973 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
974 /* Configure DP_TP_CTL with auto-training */
975 I915_WRITE(DP_TP_CTL(PORT_E
),
976 DP_TP_CTL_FDI_AUTOTRAIN
|
977 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
978 DP_TP_CTL_LINK_TRAIN_PAT1
|
981 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
982 * DDI E does not support port reversal, the functionality is
983 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
984 * port reversal bit */
985 I915_WRITE(DDI_BUF_CTL(PORT_E
),
987 ((crtc_state
->fdi_lanes
- 1) << 1) |
988 DDI_BUF_TRANS_SELECT(i
/ 2));
989 POSTING_READ(DDI_BUF_CTL(PORT_E
));
993 /* Program PCH FDI Receiver TU */
994 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A
), TU_SIZE(64));
996 /* Enable PCH FDI Receiver with auto-training */
997 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
998 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
999 POSTING_READ(FDI_RX_CTL(PIPE_A
));
1001 /* Wait for FDI receiver lane calibration */
1004 /* Unset FDI_RX_MISC pwrdn lanes */
1005 temp
= I915_READ(FDI_RX_MISC(PIPE_A
));
1006 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1007 I915_WRITE(FDI_RX_MISC(PIPE_A
), temp
);
1008 POSTING_READ(FDI_RX_MISC(PIPE_A
));
1010 /* Wait for FDI auto training time */
1013 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
1014 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
1015 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
1020 * Leave things enabled even if we failed to train FDI.
1021 * Results in less fireworks from the state checker.
1023 if (i
== ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2 - 1) {
1024 DRM_ERROR("FDI link training failed!\n");
1028 rx_ctl_val
&= ~FDI_RX_ENABLE
;
1029 I915_WRITE(FDI_RX_CTL(PIPE_A
), rx_ctl_val
);
1030 POSTING_READ(FDI_RX_CTL(PIPE_A
));
1032 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
1033 temp
&= ~DDI_BUF_CTL_ENABLE
;
1034 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
1035 POSTING_READ(DDI_BUF_CTL(PORT_E
));
1037 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1038 temp
= I915_READ(DP_TP_CTL(PORT_E
));
1039 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1040 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1041 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
1042 POSTING_READ(DP_TP_CTL(PORT_E
));
1044 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
1046 /* Reset FDI_RX_MISC pwrdn lanes */
1047 temp
= I915_READ(FDI_RX_MISC(PIPE_A
));
1048 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1049 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1050 I915_WRITE(FDI_RX_MISC(PIPE_A
), temp
);
1051 POSTING_READ(FDI_RX_MISC(PIPE_A
));
1054 /* Enable normal pixel sending for FDI */
1055 I915_WRITE(DP_TP_CTL(PORT_E
),
1056 DP_TP_CTL_FDI_AUTOTRAIN
|
1057 DP_TP_CTL_LINK_TRAIN_NORMAL
|
1058 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
1062 static void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
1064 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1065 struct intel_digital_port
*intel_dig_port
=
1066 enc_to_dig_port(&encoder
->base
);
1068 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
1069 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
1070 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1073 static struct intel_encoder
*
1074 intel_ddi_get_crtc_encoder(struct intel_crtc
*crtc
)
1076 struct drm_device
*dev
= crtc
->base
.dev
;
1077 struct intel_encoder
*encoder
, *ret
= NULL
;
1078 int num_encoders
= 0;
1080 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
1085 if (num_encoders
!= 1)
1086 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
1087 pipe_name(crtc
->pipe
));
1089 BUG_ON(ret
== NULL
);
1093 /* Finds the only possible encoder associated with the given CRTC. */
1094 struct intel_encoder
*
1095 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
)
1097 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1098 struct intel_encoder
*ret
= NULL
;
1099 struct drm_atomic_state
*state
;
1100 struct drm_connector
*connector
;
1101 struct drm_connector_state
*connector_state
;
1102 int num_encoders
= 0;
1105 state
= crtc_state
->base
.state
;
1107 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
1108 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
1111 ret
= to_intel_encoder(connector_state
->best_encoder
);
1115 WARN(num_encoders
!= 1, "%d encoders on crtc for pipe %c\n", num_encoders
,
1116 pipe_name(crtc
->pipe
));
1118 BUG_ON(ret
== NULL
);
1122 #define LC_FREQ 2700
1124 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
1127 int refclk
= LC_FREQ
;
1131 wrpll
= I915_READ(reg
);
1132 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
1134 case WRPLL_PLL_NON_SSC
:
1136 * We could calculate spread here, but our checking
1137 * code only cares about 5% accuracy, and spread is a max of
1142 case WRPLL_PLL_LCPLL
:
1146 WARN(1, "bad wrpll refclk\n");
1150 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
1151 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
1152 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
1154 /* Convert to KHz, p & r have a fixed point portion */
1155 return (refclk
* n
* 100) / (p
* r
);
1158 static int skl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
1159 enum intel_dpll_id pll_id
)
1161 i915_reg_t cfgcr1_reg
, cfgcr2_reg
;
1162 uint32_t cfgcr1_val
, cfgcr2_val
;
1163 uint32_t p0
, p1
, p2
, dco_freq
;
1165 cfgcr1_reg
= DPLL_CFGCR1(pll_id
);
1166 cfgcr2_reg
= DPLL_CFGCR2(pll_id
);
1168 cfgcr1_val
= I915_READ(cfgcr1_reg
);
1169 cfgcr2_val
= I915_READ(cfgcr2_reg
);
1171 p0
= cfgcr2_val
& DPLL_CFGCR2_PDIV_MASK
;
1172 p2
= cfgcr2_val
& DPLL_CFGCR2_KDIV_MASK
;
1174 if (cfgcr2_val
& DPLL_CFGCR2_QDIV_MODE(1))
1175 p1
= (cfgcr2_val
& DPLL_CFGCR2_QDIV_RATIO_MASK
) >> 8;
1181 case DPLL_CFGCR2_PDIV_1
:
1184 case DPLL_CFGCR2_PDIV_2
:
1187 case DPLL_CFGCR2_PDIV_3
:
1190 case DPLL_CFGCR2_PDIV_7
:
1196 case DPLL_CFGCR2_KDIV_5
:
1199 case DPLL_CFGCR2_KDIV_2
:
1202 case DPLL_CFGCR2_KDIV_3
:
1205 case DPLL_CFGCR2_KDIV_1
:
1210 dco_freq
= (cfgcr1_val
& DPLL_CFGCR1_DCO_INTEGER_MASK
) * 24 * 1000;
1212 dco_freq
+= (((cfgcr1_val
& DPLL_CFGCR1_DCO_FRACTION_MASK
) >> 9) * 24 *
1215 return dco_freq
/ (p0
* p1
* p2
* 5);
1218 static int cnl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
1219 enum intel_dpll_id pll_id
)
1221 uint32_t cfgcr0
, cfgcr1
;
1222 uint32_t p0
, p1
, p2
, dco_freq
, ref_clock
;
1224 cfgcr0
= I915_READ(CNL_DPLL_CFGCR0(pll_id
));
1225 cfgcr1
= I915_READ(CNL_DPLL_CFGCR1(pll_id
));
1227 p0
= cfgcr1
& DPLL_CFGCR1_PDIV_MASK
;
1228 p2
= cfgcr1
& DPLL_CFGCR1_KDIV_MASK
;
1230 if (cfgcr1
& DPLL_CFGCR1_QDIV_MODE(1))
1231 p1
= (cfgcr1
& DPLL_CFGCR1_QDIV_RATIO_MASK
) >>
1232 DPLL_CFGCR1_QDIV_RATIO_SHIFT
;
1238 case DPLL_CFGCR1_PDIV_2
:
1241 case DPLL_CFGCR1_PDIV_3
:
1244 case DPLL_CFGCR1_PDIV_5
:
1247 case DPLL_CFGCR1_PDIV_7
:
1253 case DPLL_CFGCR1_KDIV_1
:
1256 case DPLL_CFGCR1_KDIV_2
:
1259 case DPLL_CFGCR1_KDIV_4
:
1264 ref_clock
= dev_priv
->cdclk
.hw
.ref
;
1266 dco_freq
= (cfgcr0
& DPLL_CFGCR0_DCO_INTEGER_MASK
) * ref_clock
;
1268 dco_freq
+= (((cfgcr0
& DPLL_CFGCR0_DCO_FRACTION_MASK
) >>
1269 DPLL_CFGCR0_DCO_FRACTION_SHIFT
) * ref_clock
) / 0x8000;
1271 if (WARN_ON(p0
== 0 || p1
== 0 || p2
== 0))
1274 return dco_freq
/ (p0
* p1
* p2
* 5);
1277 static void ddi_dotclock_get(struct intel_crtc_state
*pipe_config
)
1281 if (pipe_config
->has_pch_encoder
)
1282 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1283 &pipe_config
->fdi_m_n
);
1284 else if (intel_crtc_has_dp_encoder(pipe_config
))
1285 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1286 &pipe_config
->dp_m_n
);
1287 else if (pipe_config
->has_hdmi_sink
&& pipe_config
->pipe_bpp
== 36)
1288 dotclock
= pipe_config
->port_clock
* 2 / 3;
1290 dotclock
= pipe_config
->port_clock
;
1292 if (pipe_config
->ycbcr420
)
1295 if (pipe_config
->pixel_multiplier
)
1296 dotclock
/= pipe_config
->pixel_multiplier
;
1298 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
1301 static void cnl_ddi_clock_get(struct intel_encoder
*encoder
,
1302 struct intel_crtc_state
*pipe_config
)
1304 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1307 enum intel_dpll_id pll_id
;
1309 pll_id
= intel_get_shared_dpll_id(dev_priv
, pipe_config
->shared_dpll
);
1311 cfgcr0
= I915_READ(CNL_DPLL_CFGCR0(pll_id
));
1313 if (cfgcr0
& DPLL_CFGCR0_HDMI_MODE
) {
1314 link_clock
= cnl_calc_wrpll_link(dev_priv
, pll_id
);
1316 link_clock
= cfgcr0
& DPLL_CFGCR0_LINK_RATE_MASK
;
1318 switch (link_clock
) {
1319 case DPLL_CFGCR0_LINK_RATE_810
:
1322 case DPLL_CFGCR0_LINK_RATE_1080
:
1323 link_clock
= 108000;
1325 case DPLL_CFGCR0_LINK_RATE_1350
:
1326 link_clock
= 135000;
1328 case DPLL_CFGCR0_LINK_RATE_1620
:
1329 link_clock
= 162000;
1331 case DPLL_CFGCR0_LINK_RATE_2160
:
1332 link_clock
= 216000;
1334 case DPLL_CFGCR0_LINK_RATE_2700
:
1335 link_clock
= 270000;
1337 case DPLL_CFGCR0_LINK_RATE_3240
:
1338 link_clock
= 324000;
1340 case DPLL_CFGCR0_LINK_RATE_4050
:
1341 link_clock
= 405000;
1344 WARN(1, "Unsupported link rate\n");
1350 pipe_config
->port_clock
= link_clock
;
1352 ddi_dotclock_get(pipe_config
);
1355 static void skl_ddi_clock_get(struct intel_encoder
*encoder
,
1356 struct intel_crtc_state
*pipe_config
)
1358 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1361 enum intel_dpll_id pll_id
;
1363 pll_id
= intel_get_shared_dpll_id(dev_priv
, pipe_config
->shared_dpll
);
1365 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
1367 if (dpll_ctl1
& DPLL_CTRL1_HDMI_MODE(pll_id
)) {
1368 link_clock
= skl_calc_wrpll_link(dev_priv
, pll_id
);
1370 link_clock
= dpll_ctl1
& DPLL_CTRL1_LINK_RATE_MASK(pll_id
);
1371 link_clock
>>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id
);
1373 switch (link_clock
) {
1374 case DPLL_CTRL1_LINK_RATE_810
:
1377 case DPLL_CTRL1_LINK_RATE_1080
:
1378 link_clock
= 108000;
1380 case DPLL_CTRL1_LINK_RATE_1350
:
1381 link_clock
= 135000;
1383 case DPLL_CTRL1_LINK_RATE_1620
:
1384 link_clock
= 162000;
1386 case DPLL_CTRL1_LINK_RATE_2160
:
1387 link_clock
= 216000;
1389 case DPLL_CTRL1_LINK_RATE_2700
:
1390 link_clock
= 270000;
1393 WARN(1, "Unsupported link rate\n");
1399 pipe_config
->port_clock
= link_clock
;
1401 ddi_dotclock_get(pipe_config
);
1404 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
1405 struct intel_crtc_state
*pipe_config
)
1407 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1411 val
= hsw_pll_to_ddi_pll_sel(pipe_config
->shared_dpll
);
1412 switch (val
& PORT_CLK_SEL_MASK
) {
1413 case PORT_CLK_SEL_LCPLL_810
:
1416 case PORT_CLK_SEL_LCPLL_1350
:
1417 link_clock
= 135000;
1419 case PORT_CLK_SEL_LCPLL_2700
:
1420 link_clock
= 270000;
1422 case PORT_CLK_SEL_WRPLL1
:
1423 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL(0));
1425 case PORT_CLK_SEL_WRPLL2
:
1426 link_clock
= hsw_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL(1));
1428 case PORT_CLK_SEL_SPLL
:
1429 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
1430 if (pll
== SPLL_PLL_FREQ_810MHz
)
1432 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
1433 link_clock
= 135000;
1434 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
1435 link_clock
= 270000;
1437 WARN(1, "bad spll freq\n");
1442 WARN(1, "bad port clock sel\n");
1446 pipe_config
->port_clock
= link_clock
* 2;
1448 ddi_dotclock_get(pipe_config
);
1451 static int bxt_calc_pll_link(struct drm_i915_private
*dev_priv
,
1452 enum intel_dpll_id pll_id
)
1454 struct intel_shared_dpll
*pll
;
1455 struct intel_dpll_hw_state
*state
;
1458 /* For DDI ports we always use a shared PLL. */
1459 if (WARN_ON(pll_id
== DPLL_ID_PRIVATE
))
1462 pll
= &dev_priv
->shared_dplls
[pll_id
];
1463 state
= &pll
->state
.hw_state
;
1466 clock
.m2
= (state
->pll0
& PORT_PLL_M2_MASK
) << 22;
1467 if (state
->pll3
& PORT_PLL_M2_FRAC_ENABLE
)
1468 clock
.m2
|= state
->pll2
& PORT_PLL_M2_FRAC_MASK
;
1469 clock
.n
= (state
->pll1
& PORT_PLL_N_MASK
) >> PORT_PLL_N_SHIFT
;
1470 clock
.p1
= (state
->ebb0
& PORT_PLL_P1_MASK
) >> PORT_PLL_P1_SHIFT
;
1471 clock
.p2
= (state
->ebb0
& PORT_PLL_P2_MASK
) >> PORT_PLL_P2_SHIFT
;
1473 return chv_calc_dpll_params(100000, &clock
);
1476 static void bxt_ddi_clock_get(struct intel_encoder
*encoder
,
1477 struct intel_crtc_state
*pipe_config
)
1479 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1480 enum port port
= intel_ddi_get_encoder_port(encoder
);
1481 enum intel_dpll_id pll_id
= port
;
1483 pipe_config
->port_clock
= bxt_calc_pll_link(dev_priv
, pll_id
);
1485 ddi_dotclock_get(pipe_config
);
1488 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1489 struct intel_crtc_state
*pipe_config
)
1491 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1493 if (INTEL_GEN(dev_priv
) <= 8)
1494 hsw_ddi_clock_get(encoder
, pipe_config
);
1495 else if (IS_GEN9_BC(dev_priv
))
1496 skl_ddi_clock_get(encoder
, pipe_config
);
1497 else if (IS_GEN9_LP(dev_priv
))
1498 bxt_ddi_clock_get(encoder
, pipe_config
);
1499 else if (IS_CANNONLAKE(dev_priv
))
1500 cnl_ddi_clock_get(encoder
, pipe_config
);
1503 void intel_ddi_set_pipe_settings(const struct intel_crtc_state
*crtc_state
)
1505 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1506 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1507 struct intel_encoder
*encoder
= intel_ddi_get_crtc_encoder(crtc
);
1508 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1509 int type
= encoder
->type
;
1512 if (type
== INTEL_OUTPUT_DP
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
1513 WARN_ON(transcoder_is_dsi(cpu_transcoder
));
1515 temp
= TRANS_MSA_SYNC_CLK
;
1516 switch (crtc_state
->pipe_bpp
) {
1518 temp
|= TRANS_MSA_6_BPC
;
1521 temp
|= TRANS_MSA_8_BPC
;
1524 temp
|= TRANS_MSA_10_BPC
;
1527 temp
|= TRANS_MSA_12_BPC
;
1532 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1536 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state
*crtc_state
,
1539 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1540 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1541 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1543 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1545 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1547 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1548 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1551 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state
*crtc_state
)
1553 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1554 struct intel_encoder
*encoder
= intel_ddi_get_crtc_encoder(crtc
);
1555 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1556 enum pipe pipe
= crtc
->pipe
;
1557 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1558 enum port port
= intel_ddi_get_encoder_port(encoder
);
1559 int type
= encoder
->type
;
1562 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1563 temp
= TRANS_DDI_FUNC_ENABLE
;
1564 temp
|= TRANS_DDI_SELECT_PORT(port
);
1566 switch (crtc_state
->pipe_bpp
) {
1568 temp
|= TRANS_DDI_BPC_6
;
1571 temp
|= TRANS_DDI_BPC_8
;
1574 temp
|= TRANS_DDI_BPC_10
;
1577 temp
|= TRANS_DDI_BPC_12
;
1583 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1584 temp
|= TRANS_DDI_PVSYNC
;
1585 if (crtc_state
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1586 temp
|= TRANS_DDI_PHSYNC
;
1588 if (cpu_transcoder
== TRANSCODER_EDP
) {
1591 /* On Haswell, can only use the always-on power well for
1592 * eDP when not using the panel fitter, and when not
1593 * using motion blur mitigation (which we don't
1595 if (IS_HASWELL(dev_priv
) &&
1596 (crtc_state
->pch_pfit
.enabled
||
1597 crtc_state
->pch_pfit
.force_thru
))
1598 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1600 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1603 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1606 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1614 if (type
== INTEL_OUTPUT_HDMI
) {
1615 if (crtc_state
->has_hdmi_sink
)
1616 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1618 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1620 if (crtc_state
->hdmi_scrambling
)
1621 temp
|= TRANS_DDI_HDMI_SCRAMBLING_MASK
;
1622 if (crtc_state
->hdmi_high_tmds_clock_ratio
)
1623 temp
|= TRANS_DDI_HIGH_TMDS_CHAR_RATE
;
1624 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1625 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1626 temp
|= (crtc_state
->fdi_lanes
- 1) << 1;
1627 } else if (type
== INTEL_OUTPUT_DP
||
1628 type
== INTEL_OUTPUT_EDP
) {
1629 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1630 temp
|= DDI_PORT_WIDTH(crtc_state
->lane_count
);
1631 } else if (type
== INTEL_OUTPUT_DP_MST
) {
1632 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1633 temp
|= DDI_PORT_WIDTH(crtc_state
->lane_count
);
1635 WARN(1, "Invalid encoder type %d for pipe %c\n",
1636 encoder
->type
, pipe_name(pipe
));
1639 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1642 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1643 enum transcoder cpu_transcoder
)
1645 i915_reg_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1646 uint32_t val
= I915_READ(reg
);
1648 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
1649 val
|= TRANS_DDI_PORT_NONE
;
1650 I915_WRITE(reg
, val
);
1653 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1655 struct drm_device
*dev
= intel_connector
->base
.dev
;
1656 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1657 struct intel_encoder
*encoder
= intel_connector
->encoder
;
1658 int type
= intel_connector
->base
.connector_type
;
1659 enum port port
= intel_ddi_get_encoder_port(encoder
);
1661 enum transcoder cpu_transcoder
;
1665 if (!intel_display_power_get_if_enabled(dev_priv
,
1666 encoder
->power_domain
))
1669 if (!encoder
->get_hw_state(encoder
, &pipe
)) {
1675 cpu_transcoder
= TRANSCODER_EDP
;
1677 cpu_transcoder
= (enum transcoder
) pipe
;
1679 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1681 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1682 case TRANS_DDI_MODE_SELECT_HDMI
:
1683 case TRANS_DDI_MODE_SELECT_DVI
:
1684 ret
= type
== DRM_MODE_CONNECTOR_HDMIA
;
1687 case TRANS_DDI_MODE_SELECT_DP_SST
:
1688 ret
= type
== DRM_MODE_CONNECTOR_eDP
||
1689 type
== DRM_MODE_CONNECTOR_DisplayPort
;
1692 case TRANS_DDI_MODE_SELECT_DP_MST
:
1693 /* if the transcoder is in MST state then
1694 * connector isn't connected */
1698 case TRANS_DDI_MODE_SELECT_FDI
:
1699 ret
= type
== DRM_MODE_CONNECTOR_VGA
;
1708 intel_display_power_put(dev_priv
, encoder
->power_domain
);
1713 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1716 struct drm_device
*dev
= encoder
->base
.dev
;
1717 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1718 enum port port
= intel_ddi_get_encoder_port(encoder
);
1723 if (!intel_display_power_get_if_enabled(dev_priv
,
1724 encoder
->power_domain
))
1729 tmp
= I915_READ(DDI_BUF_CTL(port
));
1731 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1734 if (port
== PORT_A
) {
1735 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1737 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1738 case TRANS_DDI_EDP_INPUT_A_ON
:
1739 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1742 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1745 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1755 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1756 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1758 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(port
)) {
1759 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) ==
1760 TRANS_DDI_MODE_SELECT_DP_MST
)
1770 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1773 if (ret
&& IS_GEN9_LP(dev_priv
)) {
1774 tmp
= I915_READ(BXT_PHY_CTL(port
));
1775 if ((tmp
& (BXT_PHY_CMNLANE_POWERDOWN_ACK
|
1776 BXT_PHY_LANE_POWERDOWN_ACK
|
1777 BXT_PHY_LANE_ENABLED
)) != BXT_PHY_LANE_ENABLED
)
1778 DRM_ERROR("Port %c enabled but PHY powered down? "
1779 "(PHY_CTL %08x)\n", port_name(port
), tmp
);
1782 intel_display_power_put(dev_priv
, encoder
->power_domain
);
1787 static u64
intel_ddi_get_power_domains(struct intel_encoder
*encoder
)
1789 struct intel_digital_port
*dig_port
= enc_to_dig_port(&encoder
->base
);
1792 if (intel_ddi_get_hw_state(encoder
, &pipe
))
1793 return BIT_ULL(dig_port
->ddi_io_power_domain
);
1798 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state
*crtc_state
)
1800 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1801 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1802 struct intel_encoder
*encoder
= intel_ddi_get_crtc_encoder(crtc
);
1803 enum port port
= intel_ddi_get_encoder_port(encoder
);
1804 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1806 if (cpu_transcoder
!= TRANSCODER_EDP
)
1807 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1808 TRANS_CLK_SEL_PORT(port
));
1811 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state
*crtc_state
)
1813 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
1814 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
1816 if (cpu_transcoder
!= TRANSCODER_EDP
)
1817 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1818 TRANS_CLK_SEL_DISABLED
);
1821 static void _skl_ddi_set_iboost(struct drm_i915_private
*dev_priv
,
1822 enum port port
, uint8_t iboost
)
1826 tmp
= I915_READ(DISPIO_CR_TX_BMU_CR0
);
1827 tmp
&= ~(BALANCE_LEG_MASK(port
) | BALANCE_LEG_DISABLE(port
));
1829 tmp
|= iboost
<< BALANCE_LEG_SHIFT(port
);
1831 tmp
|= BALANCE_LEG_DISABLE(port
);
1832 I915_WRITE(DISPIO_CR_TX_BMU_CR0
, tmp
);
1835 static void skl_ddi_set_iboost(struct intel_encoder
*encoder
,
1836 int level
, enum intel_output_type type
)
1838 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(&encoder
->base
);
1839 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
1840 enum port port
= intel_dig_port
->port
;
1843 if (type
== INTEL_OUTPUT_HDMI
)
1844 iboost
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_boost_level
;
1846 iboost
= dev_priv
->vbt
.ddi_port_info
[port
].dp_boost_level
;
1849 const struct ddi_buf_trans
*ddi_translations
;
1852 if (type
== INTEL_OUTPUT_HDMI
)
1853 ddi_translations
= intel_ddi_get_buf_trans_hdmi(dev_priv
, &n_entries
);
1854 else if (type
== INTEL_OUTPUT_EDP
)
1855 ddi_translations
= intel_ddi_get_buf_trans_edp(dev_priv
, port
, &n_entries
);
1857 ddi_translations
= intel_ddi_get_buf_trans_dp(dev_priv
, port
, &n_entries
);
1859 if (WARN_ON_ONCE(!ddi_translations
))
1861 if (WARN_ON_ONCE(level
>= n_entries
))
1862 level
= n_entries
- 1;
1864 iboost
= ddi_translations
[level
].i_boost
;
1867 /* Make sure that the requested I_boost is valid */
1868 if (iboost
&& iboost
!= 0x1 && iboost
!= 0x3 && iboost
!= 0x7) {
1869 DRM_ERROR("Invalid I_boost value %u\n", iboost
);
1873 _skl_ddi_set_iboost(dev_priv
, port
, iboost
);
1875 if (port
== PORT_A
&& intel_dig_port
->max_lanes
== 4)
1876 _skl_ddi_set_iboost(dev_priv
, PORT_E
, iboost
);
1879 static void bxt_ddi_vswing_sequence(struct intel_encoder
*encoder
,
1880 int level
, enum intel_output_type type
)
1882 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1883 const struct bxt_ddi_buf_trans
*ddi_translations
;
1884 enum port port
= encoder
->port
;
1887 if (type
== INTEL_OUTPUT_HDMI
)
1888 ddi_translations
= bxt_get_buf_trans_hdmi(dev_priv
, &n_entries
);
1889 else if (type
== INTEL_OUTPUT_EDP
)
1890 ddi_translations
= bxt_get_buf_trans_edp(dev_priv
, &n_entries
);
1892 ddi_translations
= bxt_get_buf_trans_dp(dev_priv
, &n_entries
);
1894 if (WARN_ON_ONCE(!ddi_translations
))
1896 if (WARN_ON_ONCE(level
>= n_entries
))
1897 level
= n_entries
- 1;
1899 bxt_ddi_phy_set_signal_level(dev_priv
, port
,
1900 ddi_translations
[level
].margin
,
1901 ddi_translations
[level
].scale
,
1902 ddi_translations
[level
].enable
,
1903 ddi_translations
[level
].deemphasis
);
1906 u8
intel_ddi_dp_voltage_max(struct intel_encoder
*encoder
)
1908 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1909 enum port port
= encoder
->port
;
1912 if (IS_CANNONLAKE(dev_priv
)) {
1913 if (encoder
->type
== INTEL_OUTPUT_EDP
)
1914 cnl_get_buf_trans_edp(dev_priv
, &n_entries
);
1916 cnl_get_buf_trans_dp(dev_priv
, &n_entries
);
1917 } else if (IS_GEN9_LP(dev_priv
)) {
1918 if (encoder
->type
== INTEL_OUTPUT_EDP
)
1919 bxt_get_buf_trans_edp(dev_priv
, &n_entries
);
1921 bxt_get_buf_trans_dp(dev_priv
, &n_entries
);
1923 if (encoder
->type
== INTEL_OUTPUT_EDP
)
1924 intel_ddi_get_buf_trans_edp(dev_priv
, port
, &n_entries
);
1926 intel_ddi_get_buf_trans_dp(dev_priv
, port
, &n_entries
);
1929 if (WARN_ON(n_entries
< 1))
1931 if (WARN_ON(n_entries
> ARRAY_SIZE(index_to_dp_signal_levels
)))
1932 n_entries
= ARRAY_SIZE(index_to_dp_signal_levels
);
1934 return index_to_dp_signal_levels
[n_entries
- 1] &
1935 DP_TRAIN_VOLTAGE_SWING_MASK
;
1938 static void cnl_ddi_vswing_program(struct intel_encoder
*encoder
,
1939 int level
, enum intel_output_type type
)
1941 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1942 enum port port
= intel_ddi_get_encoder_port(encoder
);
1943 const struct cnl_ddi_buf_trans
*ddi_translations
;
1947 if (type
== INTEL_OUTPUT_HDMI
)
1948 ddi_translations
= cnl_get_buf_trans_hdmi(dev_priv
, &n_entries
);
1949 else if (type
== INTEL_OUTPUT_EDP
)
1950 ddi_translations
= cnl_get_buf_trans_edp(dev_priv
, &n_entries
);
1952 ddi_translations
= cnl_get_buf_trans_dp(dev_priv
, &n_entries
);
1954 if (WARN_ON_ONCE(!ddi_translations
))
1956 if (WARN_ON_ONCE(level
>= n_entries
))
1957 level
= n_entries
- 1;
1959 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1960 val
= I915_READ(CNL_PORT_TX_DW5_LN0(port
));
1961 val
&= ~SCALING_MODE_SEL_MASK
;
1962 val
|= SCALING_MODE_SEL(2);
1963 I915_WRITE(CNL_PORT_TX_DW5_GRP(port
), val
);
1965 /* Program PORT_TX_DW2 */
1966 val
= I915_READ(CNL_PORT_TX_DW2_LN0(port
));
1967 val
&= ~(SWING_SEL_LOWER_MASK
| SWING_SEL_UPPER_MASK
|
1969 val
|= SWING_SEL_UPPER(ddi_translations
[level
].dw2_swing_sel
);
1970 val
|= SWING_SEL_LOWER(ddi_translations
[level
].dw2_swing_sel
);
1971 /* Rcomp scalar is fixed as 0x98 for every table entry */
1972 val
|= RCOMP_SCALAR(0x98);
1973 I915_WRITE(CNL_PORT_TX_DW2_GRP(port
), val
);
1975 /* Program PORT_TX_DW4 */
1976 /* We cannot write to GRP. It would overrite individual loadgen */
1977 for (ln
= 0; ln
< 4; ln
++) {
1978 val
= I915_READ(CNL_PORT_TX_DW4_LN(port
, ln
));
1979 val
&= ~(POST_CURSOR_1_MASK
| POST_CURSOR_2_MASK
|
1981 val
|= POST_CURSOR_1(ddi_translations
[level
].dw4_post_cursor_1
);
1982 val
|= POST_CURSOR_2(ddi_translations
[level
].dw4_post_cursor_2
);
1983 val
|= CURSOR_COEFF(ddi_translations
[level
].dw4_cursor_coeff
);
1984 I915_WRITE(CNL_PORT_TX_DW4_LN(port
, ln
), val
);
1987 /* Program PORT_TX_DW5 */
1988 /* All DW5 values are fixed for every table entry */
1989 val
= I915_READ(CNL_PORT_TX_DW5_LN0(port
));
1990 val
&= ~RTERM_SELECT_MASK
;
1991 val
|= RTERM_SELECT(6);
1992 val
|= TAP3_DISABLE
;
1993 I915_WRITE(CNL_PORT_TX_DW5_GRP(port
), val
);
1995 /* Program PORT_TX_DW7 */
1996 val
= I915_READ(CNL_PORT_TX_DW7_LN0(port
));
1997 val
&= ~N_SCALAR_MASK
;
1998 val
|= N_SCALAR(ddi_translations
[level
].dw7_n_scalar
);
1999 I915_WRITE(CNL_PORT_TX_DW7_GRP(port
), val
);
2002 static void cnl_ddi_vswing_sequence(struct intel_encoder
*encoder
,
2003 int level
, enum intel_output_type type
)
2005 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2006 enum port port
= intel_ddi_get_encoder_port(encoder
);
2007 int width
, rate
, ln
;
2010 if (type
== INTEL_OUTPUT_HDMI
) {
2012 rate
= 0; /* Rate is always < than 6GHz for HDMI */
2014 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2016 width
= intel_dp
->lane_count
;
2017 rate
= intel_dp
->link_rate
;
2021 * 1. If port type is eDP or DP,
2022 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2025 val
= I915_READ(CNL_PORT_PCS_DW1_LN0(port
));
2026 if (type
!= INTEL_OUTPUT_HDMI
)
2027 val
|= COMMON_KEEPER_EN
;
2029 val
&= ~COMMON_KEEPER_EN
;
2030 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port
), val
);
2032 /* 2. Program loadgen select */
2034 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2035 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2036 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2037 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2039 for (ln
= 0; ln
<= 3; ln
++) {
2040 val
= I915_READ(CNL_PORT_TX_DW4_LN(port
, ln
));
2041 val
&= ~LOADGEN_SELECT
;
2043 if ((rate
<= 600000 && width
== 4 && ln
>= 1) ||
2044 (rate
<= 600000 && width
< 4 && (ln
== 1 || ln
== 2))) {
2045 val
|= LOADGEN_SELECT
;
2047 I915_WRITE(CNL_PORT_TX_DW4_LN(port
, ln
), val
);
2050 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2051 val
= I915_READ(CNL_PORT_CL1CM_DW5
);
2052 val
|= SUS_CLOCK_CONFIG
;
2053 I915_WRITE(CNL_PORT_CL1CM_DW5
, val
);
2055 /* 4. Clear training enable to change swing values */
2056 val
= I915_READ(CNL_PORT_TX_DW5_LN0(port
));
2057 val
&= ~TX_TRAINING_EN
;
2058 I915_WRITE(CNL_PORT_TX_DW5_GRP(port
), val
);
2060 /* 5. Program swing and de-emphasis */
2061 cnl_ddi_vswing_program(encoder
, level
, type
);
2063 /* 6. Set training enable to trigger update */
2064 val
= I915_READ(CNL_PORT_TX_DW5_LN0(port
));
2065 val
|= TX_TRAINING_EN
;
2066 I915_WRITE(CNL_PORT_TX_DW5_GRP(port
), val
);
2069 static uint32_t translate_signal_level(int signal_levels
)
2073 for (i
= 0; i
< ARRAY_SIZE(index_to_dp_signal_levels
); i
++) {
2074 if (index_to_dp_signal_levels
[i
] == signal_levels
)
2078 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2084 static uint32_t intel_ddi_dp_level(struct intel_dp
*intel_dp
)
2086 uint8_t train_set
= intel_dp
->train_set
[0];
2087 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
2088 DP_TRAIN_PRE_EMPHASIS_MASK
);
2090 return translate_signal_level(signal_levels
);
2093 u32
bxt_signal_levels(struct intel_dp
*intel_dp
)
2095 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2096 struct drm_i915_private
*dev_priv
= to_i915(dport
->base
.base
.dev
);
2097 struct intel_encoder
*encoder
= &dport
->base
;
2098 int level
= intel_ddi_dp_level(intel_dp
);
2100 if (IS_CANNONLAKE(dev_priv
))
2101 cnl_ddi_vswing_sequence(encoder
, level
, encoder
->type
);
2103 bxt_ddi_vswing_sequence(encoder
, level
, encoder
->type
);
2108 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
)
2110 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2111 struct drm_i915_private
*dev_priv
= to_i915(dport
->base
.base
.dev
);
2112 struct intel_encoder
*encoder
= &dport
->base
;
2113 int level
= intel_ddi_dp_level(intel_dp
);
2115 if (IS_GEN9_BC(dev_priv
))
2116 skl_ddi_set_iboost(encoder
, level
, encoder
->type
);
2118 return DDI_BUF_TRANS_SELECT(level
);
2121 static void intel_ddi_clk_select(struct intel_encoder
*encoder
,
2122 const struct intel_shared_dpll
*pll
)
2124 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2125 enum port port
= intel_ddi_get_encoder_port(encoder
);
2131 if (IS_CANNONLAKE(dev_priv
)) {
2132 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2133 val
= I915_READ(DPCLKA_CFGCR0
);
2134 val
|= DPCLKA_CFGCR0_DDI_CLK_SEL(pll
->id
, port
);
2135 I915_WRITE(DPCLKA_CFGCR0
, val
);
2138 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2139 * This step and the step before must be done with separate
2142 val
= I915_READ(DPCLKA_CFGCR0
);
2143 val
&= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port
);
2144 I915_WRITE(DPCLKA_CFGCR0
, val
);
2145 } else if (IS_GEN9_BC(dev_priv
)) {
2146 /* DDI -> PLL mapping */
2147 val
= I915_READ(DPLL_CTRL2
);
2149 val
&= ~(DPLL_CTRL2_DDI_CLK_OFF(port
) |
2150 DPLL_CTRL2_DDI_CLK_SEL_MASK(port
));
2151 val
|= (DPLL_CTRL2_DDI_CLK_SEL(pll
->id
, port
) |
2152 DPLL_CTRL2_DDI_SEL_OVERRIDE(port
));
2154 I915_WRITE(DPLL_CTRL2
, val
);
2156 } else if (INTEL_INFO(dev_priv
)->gen
< 9) {
2157 I915_WRITE(PORT_CLK_SEL(port
), hsw_pll_to_ddi_pll_sel(pll
));
2161 static void intel_ddi_clk_disable(struct intel_encoder
*encoder
)
2163 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2164 enum port port
= intel_ddi_get_encoder_port(encoder
);
2166 if (IS_CANNONLAKE(dev_priv
))
2167 I915_WRITE(DPCLKA_CFGCR0
, I915_READ(DPCLKA_CFGCR0
) |
2168 DPCLKA_CFGCR0_DDI_CLK_OFF(port
));
2169 else if (IS_GEN9_BC(dev_priv
))
2170 I915_WRITE(DPLL_CTRL2
, I915_READ(DPLL_CTRL2
) |
2171 DPLL_CTRL2_DDI_CLK_OFF(port
));
2172 else if (INTEL_GEN(dev_priv
) < 9)
2173 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
2176 static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder
,
2177 const struct intel_crtc_state
*crtc_state
,
2178 const struct drm_connector_state
*conn_state
)
2180 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2181 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2182 enum port port
= intel_ddi_get_encoder_port(encoder
);
2183 struct intel_digital_port
*dig_port
= enc_to_dig_port(&encoder
->base
);
2184 bool is_mst
= intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DP_MST
);
2185 int level
= intel_ddi_dp_level(intel_dp
);
2187 WARN_ON(is_mst
&& (port
== PORT_A
|| port
== PORT_E
));
2189 intel_dp_set_link_params(intel_dp
, crtc_state
->port_clock
,
2190 crtc_state
->lane_count
, is_mst
);
2192 intel_edp_panel_on(intel_dp
);
2194 intel_ddi_clk_select(encoder
, crtc_state
->shared_dpll
);
2196 intel_display_power_get(dev_priv
, dig_port
->ddi_io_power_domain
);
2198 if (IS_CANNONLAKE(dev_priv
))
2199 cnl_ddi_vswing_sequence(encoder
, level
, encoder
->type
);
2200 else if (IS_GEN9_LP(dev_priv
))
2201 bxt_ddi_vswing_sequence(encoder
, level
, encoder
->type
);
2203 intel_prepare_dp_ddi_buffers(encoder
);
2205 intel_ddi_init_dp_buf_reg(encoder
);
2207 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2208 intel_dp_start_link_train(intel_dp
);
2209 if (port
!= PORT_A
|| INTEL_GEN(dev_priv
) >= 9)
2210 intel_dp_stop_link_train(intel_dp
);
2213 static void intel_ddi_pre_enable_hdmi(struct intel_encoder
*encoder
,
2214 const struct intel_crtc_state
*crtc_state
,
2215 const struct drm_connector_state
*conn_state
)
2217 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(&encoder
->base
);
2218 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
2219 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2220 enum port port
= intel_ddi_get_encoder_port(encoder
);
2221 int level
= intel_ddi_hdmi_level(dev_priv
, port
);
2222 struct intel_digital_port
*dig_port
= enc_to_dig_port(&encoder
->base
);
2224 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, true);
2225 intel_ddi_clk_select(encoder
, crtc_state
->shared_dpll
);
2227 intel_display_power_get(dev_priv
, dig_port
->ddi_io_power_domain
);
2229 if (IS_CANNONLAKE(dev_priv
))
2230 cnl_ddi_vswing_sequence(encoder
, level
, INTEL_OUTPUT_HDMI
);
2231 else if (IS_GEN9_LP(dev_priv
))
2232 bxt_ddi_vswing_sequence(encoder
, level
, INTEL_OUTPUT_HDMI
);
2234 intel_prepare_hdmi_ddi_buffers(encoder
, level
);
2236 if (IS_GEN9_BC(dev_priv
))
2237 skl_ddi_set_iboost(encoder
, level
, INTEL_OUTPUT_HDMI
);
2239 intel_dig_port
->set_infoframes(&encoder
->base
,
2240 crtc_state
->has_infoframe
,
2241 crtc_state
, conn_state
);
2244 static void intel_ddi_pre_enable(struct intel_encoder
*encoder
,
2245 const struct intel_crtc_state
*crtc_state
,
2246 const struct drm_connector_state
*conn_state
)
2248 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2249 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2250 enum pipe pipe
= crtc
->pipe
;
2252 WARN_ON(crtc_state
->has_pch_encoder
);
2254 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
2256 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
2257 intel_ddi_pre_enable_hdmi(encoder
, crtc_state
, conn_state
);
2259 intel_ddi_pre_enable_dp(encoder
, crtc_state
, conn_state
);
2262 static void intel_disable_ddi_buf(struct intel_encoder
*encoder
)
2264 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2265 enum port port
= intel_ddi_get_encoder_port(encoder
);
2269 val
= I915_READ(DDI_BUF_CTL(port
));
2270 if (val
& DDI_BUF_CTL_ENABLE
) {
2271 val
&= ~DDI_BUF_CTL_ENABLE
;
2272 I915_WRITE(DDI_BUF_CTL(port
), val
);
2276 val
= I915_READ(DP_TP_CTL(port
));
2277 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2278 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2279 I915_WRITE(DP_TP_CTL(port
), val
);
2282 intel_wait_ddi_buf_idle(dev_priv
, port
);
2285 static void intel_ddi_post_disable_dp(struct intel_encoder
*encoder
,
2286 const struct intel_crtc_state
*old_crtc_state
,
2287 const struct drm_connector_state
*old_conn_state
)
2289 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2290 struct intel_digital_port
*dig_port
= enc_to_dig_port(&encoder
->base
);
2291 struct intel_dp
*intel_dp
= &dig_port
->dp
;
2293 * old_crtc_state and old_conn_state are NULL when called from
2294 * DP_MST. The main connector associated with this port is never
2295 * bound to a crtc for MST.
2297 bool is_mst
= !old_crtc_state
;
2300 * Power down sink before disabling the port, otherwise we end
2301 * up getting interrupts from the sink on detecting link loss.
2304 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2306 intel_disable_ddi_buf(encoder
);
2308 intel_edp_panel_vdd_on(intel_dp
);
2309 intel_edp_panel_off(intel_dp
);
2311 intel_display_power_put(dev_priv
, dig_port
->ddi_io_power_domain
);
2313 intel_ddi_clk_disable(encoder
);
2316 static void intel_ddi_post_disable_hdmi(struct intel_encoder
*encoder
,
2317 const struct intel_crtc_state
*old_crtc_state
,
2318 const struct drm_connector_state
*old_conn_state
)
2320 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2321 struct intel_digital_port
*dig_port
= enc_to_dig_port(&encoder
->base
);
2322 struct intel_hdmi
*intel_hdmi
= &dig_port
->hdmi
;
2324 intel_disable_ddi_buf(encoder
);
2326 dig_port
->set_infoframes(&encoder
->base
, false,
2327 old_crtc_state
, old_conn_state
);
2329 intel_display_power_put(dev_priv
, dig_port
->ddi_io_power_domain
);
2331 intel_ddi_clk_disable(encoder
);
2333 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, false);
2336 static void intel_ddi_post_disable(struct intel_encoder
*encoder
,
2337 const struct intel_crtc_state
*old_crtc_state
,
2338 const struct drm_connector_state
*old_conn_state
)
2341 * old_crtc_state and old_conn_state are NULL when called from
2342 * DP_MST. The main connector associated with this port is never
2343 * bound to a crtc for MST.
2345 if (old_crtc_state
&&
2346 intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_HDMI
))
2347 intel_ddi_post_disable_hdmi(encoder
,
2348 old_crtc_state
, old_conn_state
);
2350 intel_ddi_post_disable_dp(encoder
,
2351 old_crtc_state
, old_conn_state
);
2354 void intel_ddi_fdi_post_disable(struct intel_encoder
*encoder
,
2355 const struct intel_crtc_state
*old_crtc_state
,
2356 const struct drm_connector_state
*old_conn_state
)
2358 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2362 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2363 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2364 * step 13 is the correct place for it. Step 18 is where it was
2365 * originally before the BUN.
2367 val
= I915_READ(FDI_RX_CTL(PIPE_A
));
2368 val
&= ~FDI_RX_ENABLE
;
2369 I915_WRITE(FDI_RX_CTL(PIPE_A
), val
);
2371 intel_disable_ddi_buf(encoder
);
2372 intel_ddi_clk_disable(encoder
);
2374 val
= I915_READ(FDI_RX_MISC(PIPE_A
));
2375 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
2376 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2377 I915_WRITE(FDI_RX_MISC(PIPE_A
), val
);
2379 val
= I915_READ(FDI_RX_CTL(PIPE_A
));
2381 I915_WRITE(FDI_RX_CTL(PIPE_A
), val
);
2383 val
= I915_READ(FDI_RX_CTL(PIPE_A
));
2384 val
&= ~FDI_RX_PLL_ENABLE
;
2385 I915_WRITE(FDI_RX_CTL(PIPE_A
), val
);
2388 static void intel_enable_ddi_dp(struct intel_encoder
*encoder
,
2389 const struct intel_crtc_state
*crtc_state
,
2390 const struct drm_connector_state
*conn_state
)
2392 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2393 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2394 enum port port
= intel_ddi_get_encoder_port(encoder
);
2396 if (port
== PORT_A
&& INTEL_GEN(dev_priv
) < 9)
2397 intel_dp_stop_link_train(intel_dp
);
2399 intel_edp_backlight_on(crtc_state
, conn_state
);
2400 intel_psr_enable(intel_dp
, crtc_state
);
2401 intel_edp_drrs_enable(intel_dp
, crtc_state
);
2403 if (crtc_state
->has_audio
)
2404 intel_audio_codec_enable(encoder
, crtc_state
, conn_state
);
2407 static void intel_enable_ddi_hdmi(struct intel_encoder
*encoder
,
2408 const struct intel_crtc_state
*crtc_state
,
2409 const struct drm_connector_state
*conn_state
)
2411 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2412 struct intel_digital_port
*dig_port
= enc_to_dig_port(&encoder
->base
);
2413 enum port port
= intel_ddi_get_encoder_port(encoder
);
2415 intel_hdmi_handle_sink_scrambling(encoder
,
2416 conn_state
->connector
,
2417 crtc_state
->hdmi_high_tmds_clock_ratio
,
2418 crtc_state
->hdmi_scrambling
);
2420 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2421 * are ignored so nothing special needs to be done besides
2422 * enabling the port.
2424 I915_WRITE(DDI_BUF_CTL(port
),
2425 dig_port
->saved_port_bits
| DDI_BUF_CTL_ENABLE
);
2427 if (crtc_state
->has_audio
)
2428 intel_audio_codec_enable(encoder
, crtc_state
, conn_state
);
2431 static void intel_enable_ddi(struct intel_encoder
*encoder
,
2432 const struct intel_crtc_state
*crtc_state
,
2433 const struct drm_connector_state
*conn_state
)
2435 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
2436 intel_enable_ddi_hdmi(encoder
, crtc_state
, conn_state
);
2438 intel_enable_ddi_dp(encoder
, crtc_state
, conn_state
);
2441 static void intel_disable_ddi_dp(struct intel_encoder
*encoder
,
2442 const struct intel_crtc_state
*old_crtc_state
,
2443 const struct drm_connector_state
*old_conn_state
)
2445 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2447 if (old_crtc_state
->has_audio
)
2448 intel_audio_codec_disable(encoder
);
2450 intel_edp_drrs_disable(intel_dp
, old_crtc_state
);
2451 intel_psr_disable(intel_dp
, old_crtc_state
);
2452 intel_edp_backlight_off(old_conn_state
);
2455 static void intel_disable_ddi_hdmi(struct intel_encoder
*encoder
,
2456 const struct intel_crtc_state
*old_crtc_state
,
2457 const struct drm_connector_state
*old_conn_state
)
2459 if (old_crtc_state
->has_audio
)
2460 intel_audio_codec_disable(encoder
);
2462 intel_hdmi_handle_sink_scrambling(encoder
,
2463 old_conn_state
->connector
,
2467 static void intel_disable_ddi(struct intel_encoder
*encoder
,
2468 const struct intel_crtc_state
*old_crtc_state
,
2469 const struct drm_connector_state
*old_conn_state
)
2471 if (intel_crtc_has_type(old_crtc_state
, INTEL_OUTPUT_HDMI
))
2472 intel_disable_ddi_hdmi(encoder
, old_crtc_state
, old_conn_state
);
2474 intel_disable_ddi_dp(encoder
, old_crtc_state
, old_conn_state
);
2477 static void bxt_ddi_pre_pll_enable(struct intel_encoder
*encoder
,
2478 const struct intel_crtc_state
*pipe_config
,
2479 const struct drm_connector_state
*conn_state
)
2481 uint8_t mask
= pipe_config
->lane_lat_optim_mask
;
2483 bxt_ddi_phy_set_lane_optim_mask(encoder
, mask
);
2486 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
)
2488 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2489 struct drm_i915_private
*dev_priv
=
2490 to_i915(intel_dig_port
->base
.base
.dev
);
2491 enum port port
= intel_dig_port
->port
;
2495 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
2496 val
= I915_READ(DDI_BUF_CTL(port
));
2497 if (val
& DDI_BUF_CTL_ENABLE
) {
2498 val
&= ~DDI_BUF_CTL_ENABLE
;
2499 I915_WRITE(DDI_BUF_CTL(port
), val
);
2503 val
= I915_READ(DP_TP_CTL(port
));
2504 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
2505 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2506 I915_WRITE(DP_TP_CTL(port
), val
);
2507 POSTING_READ(DP_TP_CTL(port
));
2510 intel_wait_ddi_buf_idle(dev_priv
, port
);
2513 val
= DP_TP_CTL_ENABLE
|
2514 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
2515 if (intel_dp
->link_mst
)
2516 val
|= DP_TP_CTL_MODE_MST
;
2518 val
|= DP_TP_CTL_MODE_SST
;
2519 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
2520 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
2522 I915_WRITE(DP_TP_CTL(port
), val
);
2523 POSTING_READ(DP_TP_CTL(port
));
2525 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
2526 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
2527 POSTING_READ(DDI_BUF_CTL(port
));
2532 bool intel_ddi_is_audio_enabled(struct drm_i915_private
*dev_priv
,
2533 struct intel_crtc
*intel_crtc
)
2537 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
2538 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
2539 if (temp
& AUDIO_OUTPUT_ENABLE(intel_crtc
->pipe
))
2545 void intel_ddi_get_config(struct intel_encoder
*encoder
,
2546 struct intel_crtc_state
*pipe_config
)
2548 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2549 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2550 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
2551 struct intel_digital_port
*intel_dig_port
;
2552 u32 temp
, flags
= 0;
2554 /* XXX: DSI transcoder paranoia */
2555 if (WARN_ON(transcoder_is_dsi(cpu_transcoder
)))
2558 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
2559 if (temp
& TRANS_DDI_PHSYNC
)
2560 flags
|= DRM_MODE_FLAG_PHSYNC
;
2562 flags
|= DRM_MODE_FLAG_NHSYNC
;
2563 if (temp
& TRANS_DDI_PVSYNC
)
2564 flags
|= DRM_MODE_FLAG_PVSYNC
;
2566 flags
|= DRM_MODE_FLAG_NVSYNC
;
2568 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2570 switch (temp
& TRANS_DDI_BPC_MASK
) {
2571 case TRANS_DDI_BPC_6
:
2572 pipe_config
->pipe_bpp
= 18;
2574 case TRANS_DDI_BPC_8
:
2575 pipe_config
->pipe_bpp
= 24;
2577 case TRANS_DDI_BPC_10
:
2578 pipe_config
->pipe_bpp
= 30;
2580 case TRANS_DDI_BPC_12
:
2581 pipe_config
->pipe_bpp
= 36;
2587 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
2588 case TRANS_DDI_MODE_SELECT_HDMI
:
2589 pipe_config
->has_hdmi_sink
= true;
2590 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
2592 if (intel_dig_port
->infoframe_enabled(&encoder
->base
, pipe_config
))
2593 pipe_config
->has_infoframe
= true;
2595 if ((temp
& TRANS_DDI_HDMI_SCRAMBLING_MASK
) ==
2596 TRANS_DDI_HDMI_SCRAMBLING_MASK
)
2597 pipe_config
->hdmi_scrambling
= true;
2598 if (temp
& TRANS_DDI_HIGH_TMDS_CHAR_RATE
)
2599 pipe_config
->hdmi_high_tmds_clock_ratio
= true;
2601 case TRANS_DDI_MODE_SELECT_DVI
:
2602 pipe_config
->lane_count
= 4;
2604 case TRANS_DDI_MODE_SELECT_FDI
:
2606 case TRANS_DDI_MODE_SELECT_DP_SST
:
2607 case TRANS_DDI_MODE_SELECT_DP_MST
:
2608 pipe_config
->lane_count
=
2609 ((temp
& DDI_PORT_WIDTH_MASK
) >> DDI_PORT_WIDTH_SHIFT
) + 1;
2610 intel_dp_get_m_n(intel_crtc
, pipe_config
);
2616 pipe_config
->has_audio
=
2617 intel_ddi_is_audio_enabled(dev_priv
, intel_crtc
);
2619 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp
.bpp
&&
2620 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2622 * This is a big fat ugly hack.
2624 * Some machines in UEFI boot mode provide us a VBT that has 18
2625 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2626 * unknown we fail to light up. Yet the same BIOS boots up with
2627 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2628 * max, not what it tells us to use.
2630 * Note: This will still be broken if the eDP panel is not lit
2631 * up by the BIOS, and thus we can't get the mode at module
2634 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2635 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2636 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2639 intel_ddi_clock_get(encoder
, pipe_config
);
2641 if (IS_GEN9_LP(dev_priv
))
2642 pipe_config
->lane_lat_optim_mask
=
2643 bxt_ddi_phy_get_lane_lat_optim_mask(encoder
);
2646 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
2647 struct intel_crtc_state
*pipe_config
,
2648 struct drm_connector_state
*conn_state
)
2650 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2651 int type
= encoder
->type
;
2652 int port
= intel_ddi_get_encoder_port(encoder
);
2655 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
2658 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
2660 if (type
== INTEL_OUTPUT_HDMI
)
2661 ret
= intel_hdmi_compute_config(encoder
, pipe_config
, conn_state
);
2663 ret
= intel_dp_compute_config(encoder
, pipe_config
, conn_state
);
2665 if (IS_GEN9_LP(dev_priv
) && ret
)
2666 pipe_config
->lane_lat_optim_mask
=
2667 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder
,
2668 pipe_config
->lane_count
);
2674 static const struct drm_encoder_funcs intel_ddi_funcs
= {
2675 .reset
= intel_dp_encoder_reset
,
2676 .destroy
= intel_dp_encoder_destroy
,
2679 static struct intel_connector
*
2680 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
2682 struct intel_connector
*connector
;
2683 enum port port
= intel_dig_port
->port
;
2685 connector
= intel_connector_alloc();
2689 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
2690 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
2698 static struct intel_connector
*
2699 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
2701 struct intel_connector
*connector
;
2702 enum port port
= intel_dig_port
->port
;
2704 connector
= intel_connector_alloc();
2708 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
2709 intel_hdmi_init_connector(intel_dig_port
, connector
);
2714 void intel_ddi_init(struct drm_i915_private
*dev_priv
, enum port port
)
2716 struct intel_digital_port
*intel_dig_port
;
2717 struct intel_encoder
*intel_encoder
;
2718 struct drm_encoder
*encoder
;
2719 bool init_hdmi
, init_dp
, init_lspcon
= false;
2722 if (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
) {
2748 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
2749 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
2750 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
2752 if (intel_bios_is_lspcon_present(dev_priv
, port
)) {
2754 * Lspcon device needs to be driven with DP connector
2755 * with special detection sequence. So make sure DP
2756 * is initialized before lspcon.
2761 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port
));
2764 if (!init_dp
&& !init_hdmi
) {
2765 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2770 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
2771 if (!intel_dig_port
)
2774 intel_encoder
= &intel_dig_port
->base
;
2775 encoder
= &intel_encoder
->base
;
2777 drm_encoder_init(&dev_priv
->drm
, encoder
, &intel_ddi_funcs
,
2778 DRM_MODE_ENCODER_TMDS
, "DDI %c", port_name(port
));
2780 intel_encoder
->compute_config
= intel_ddi_compute_config
;
2781 intel_encoder
->enable
= intel_enable_ddi
;
2782 if (IS_GEN9_LP(dev_priv
))
2783 intel_encoder
->pre_pll_enable
= bxt_ddi_pre_pll_enable
;
2784 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
2785 intel_encoder
->disable
= intel_disable_ddi
;
2786 intel_encoder
->post_disable
= intel_ddi_post_disable
;
2787 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
2788 intel_encoder
->get_config
= intel_ddi_get_config
;
2789 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
2790 intel_encoder
->get_power_domains
= intel_ddi_get_power_domains
;
2792 intel_dig_port
->port
= port
;
2793 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
2794 (DDI_BUF_PORT_REVERSAL
|
2799 intel_dig_port
->ddi_io_power_domain
=
2800 POWER_DOMAIN_PORT_DDI_A_IO
;
2803 intel_dig_port
->ddi_io_power_domain
=
2804 POWER_DOMAIN_PORT_DDI_B_IO
;
2807 intel_dig_port
->ddi_io_power_domain
=
2808 POWER_DOMAIN_PORT_DDI_C_IO
;
2811 intel_dig_port
->ddi_io_power_domain
=
2812 POWER_DOMAIN_PORT_DDI_D_IO
;
2815 intel_dig_port
->ddi_io_power_domain
=
2816 POWER_DOMAIN_PORT_DDI_E_IO
;
2823 * Bspec says that DDI_A_4_LANES is the only supported configuration
2824 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2825 * wasn't lit up at boot. Force this bit on in our internal
2826 * configuration so that we use the proper lane count for our
2829 if (IS_GEN9_LP(dev_priv
) && port
== PORT_A
) {
2830 if (!(intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
)) {
2831 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2832 intel_dig_port
->saved_port_bits
|= DDI_A_4_LANES
;
2837 intel_dig_port
->max_lanes
= max_lanes
;
2839 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
2840 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
2841 intel_encoder
->port
= port
;
2842 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2843 intel_encoder
->cloneable
= 0;
2845 intel_infoframe_init(intel_dig_port
);
2848 if (!intel_ddi_init_dp_connector(intel_dig_port
))
2851 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
2852 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
2855 /* In theory we don't need the encoder->type check, but leave it just in
2856 * case we have some really bad VBTs... */
2857 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
2858 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
2863 if (lspcon_init(intel_dig_port
))
2864 /* TODO: handle hdmi info frame part */
2865 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2869 * LSPCON init faied, but DP init was success, so
2870 * lets try to drive as DP++ port.
2872 DRM_ERROR("LSPCON init failed on port %c\n",
2879 drm_encoder_cleanup(encoder
);
2880 kfree(intel_dig_port
);