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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 };
35
36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
40 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
50 };
51
52 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
62 };
63
64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
78 };
79
80 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
90 };
91
92 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
98 { 0x00DB6FFF, 0x00160005 },
99 { 0x80C71FFF, 0x001A0002 },
100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
102 };
103
104 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
114 };
115
116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
128 };
129
130 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
131 { 0x00000018, 0x000000a0 },
132 { 0x00004014, 0x00000098 },
133 { 0x00006012, 0x00000088 },
134 { 0x00008010, 0x00000080 },
135 { 0x00000018, 0x00000098 },
136 { 0x00004014, 0x00000088 },
137 { 0x00006012, 0x00000080 },
138 { 0x00000018, 0x00000088 },
139 { 0x00004014, 0x00000080 },
140 };
141
142 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
143 /* Idx NT mV T mV db */
144 { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */
145 { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */
146 { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */
147 { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */
148 { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */
149 { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */
150 { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */
151 { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */
152 { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */
153 { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */
154 };
155
156 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
157 {
158 struct drm_encoder *encoder = &intel_encoder->base;
159 int type = intel_encoder->type;
160
161 if (type == INTEL_OUTPUT_DP_MST) {
162 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
163 return intel_dig_port->port;
164 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
165 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
166 struct intel_digital_port *intel_dig_port =
167 enc_to_dig_port(encoder);
168 return intel_dig_port->port;
169
170 } else if (type == INTEL_OUTPUT_ANALOG) {
171 return PORT_E;
172
173 } else {
174 DRM_ERROR("Invalid DDI encoder type %d\n", type);
175 BUG();
176 }
177 }
178
179 /*
180 * Starting with Haswell, DDI port buffers must be programmed with correct
181 * values in advance. The buffer values are different for FDI and DP modes,
182 * but the HDMI/DVI fields are shared among those. So we program the DDI
183 * in either FDI or DP modes only, as HDMI connections will work with both
184 * of those
185 */
186 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
187 {
188 struct drm_i915_private *dev_priv = dev->dev_private;
189 u32 reg;
190 int i, n_hdmi_entries, hdmi_800mV_0dB;
191 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
192 const struct ddi_buf_trans *ddi_translations_fdi;
193 const struct ddi_buf_trans *ddi_translations_dp;
194 const struct ddi_buf_trans *ddi_translations_edp;
195 const struct ddi_buf_trans *ddi_translations_hdmi;
196 const struct ddi_buf_trans *ddi_translations;
197
198 if (IS_SKYLAKE(dev)) {
199 ddi_translations_fdi = NULL;
200 ddi_translations_dp = skl_ddi_translations_dp;
201 ddi_translations_edp = skl_ddi_translations_dp;
202 ddi_translations_hdmi = skl_ddi_translations_hdmi;
203 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
204 hdmi_800mV_0dB = 7;
205 } else if (IS_BROADWELL(dev)) {
206 ddi_translations_fdi = bdw_ddi_translations_fdi;
207 ddi_translations_dp = bdw_ddi_translations_dp;
208 ddi_translations_edp = bdw_ddi_translations_edp;
209 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
210 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
211 hdmi_800mV_0dB = 7;
212 } else if (IS_HASWELL(dev)) {
213 ddi_translations_fdi = hsw_ddi_translations_fdi;
214 ddi_translations_dp = hsw_ddi_translations_dp;
215 ddi_translations_edp = hsw_ddi_translations_dp;
216 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
217 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
218 hdmi_800mV_0dB = 6;
219 } else {
220 WARN(1, "ddi translation table missing\n");
221 ddi_translations_edp = bdw_ddi_translations_dp;
222 ddi_translations_fdi = bdw_ddi_translations_fdi;
223 ddi_translations_dp = bdw_ddi_translations_dp;
224 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
225 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
226 hdmi_800mV_0dB = 7;
227 }
228
229 switch (port) {
230 case PORT_A:
231 ddi_translations = ddi_translations_edp;
232 break;
233 case PORT_B:
234 case PORT_C:
235 ddi_translations = ddi_translations_dp;
236 break;
237 case PORT_D:
238 if (intel_dp_is_edp(dev, PORT_D))
239 ddi_translations = ddi_translations_edp;
240 else
241 ddi_translations = ddi_translations_dp;
242 break;
243 case PORT_E:
244 if (ddi_translations_fdi)
245 ddi_translations = ddi_translations_fdi;
246 else
247 ddi_translations = ddi_translations_dp;
248 break;
249 default:
250 BUG();
251 }
252
253 for (i = 0, reg = DDI_BUF_TRANS(port);
254 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
255 I915_WRITE(reg, ddi_translations[i].trans1);
256 reg += 4;
257 I915_WRITE(reg, ddi_translations[i].trans2);
258 reg += 4;
259 }
260
261 /* Choose a good default if VBT is badly populated */
262 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
263 hdmi_level >= n_hdmi_entries)
264 hdmi_level = hdmi_800mV_0dB;
265
266 /* Entry 9 is for HDMI: */
267 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
268 reg += 4;
269 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
270 reg += 4;
271 }
272
273 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
274 * mode and port E for FDI.
275 */
276 void intel_prepare_ddi(struct drm_device *dev)
277 {
278 int port;
279
280 if (!HAS_DDI(dev))
281 return;
282
283 for (port = PORT_A; port <= PORT_E; port++)
284 intel_prepare_ddi_buffers(dev, port);
285 }
286
287 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
288 enum port port)
289 {
290 uint32_t reg = DDI_BUF_CTL(port);
291 int i;
292
293 for (i = 0; i < 8; i++) {
294 udelay(1);
295 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
296 return;
297 }
298 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
299 }
300
301 /* Starting with Haswell, different DDI ports can work in FDI mode for
302 * connection to the PCH-located connectors. For this, it is necessary to train
303 * both the DDI port and PCH receiver for the desired DDI buffer settings.
304 *
305 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
306 * please note that when FDI mode is active on DDI E, it shares 2 lines with
307 * DDI A (which is used for eDP)
308 */
309
310 void hsw_fdi_link_train(struct drm_crtc *crtc)
311 {
312 struct drm_device *dev = crtc->dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
315 u32 temp, i, rx_ctl_val;
316
317 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
318 * mode set "sequence for CRT port" document:
319 * - TP1 to TP2 time with the default value
320 * - FDI delay to 90h
321 *
322 * WaFDIAutoLinkSetTimingOverrride:hsw
323 */
324 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
325 FDI_RX_PWRDN_LANE0_VAL(2) |
326 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
327
328 /* Enable the PCH Receiver FDI PLL */
329 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
330 FDI_RX_PLL_ENABLE |
331 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
332 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
333 POSTING_READ(_FDI_RXA_CTL);
334 udelay(220);
335
336 /* Switch from Rawclk to PCDclk */
337 rx_ctl_val |= FDI_PCDCLK;
338 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
339
340 /* Configure Port Clock Select */
341 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
342 WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
343
344 /* Start the training iterating through available voltages and emphasis,
345 * testing each value twice. */
346 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
347 /* Configure DP_TP_CTL with auto-training */
348 I915_WRITE(DP_TP_CTL(PORT_E),
349 DP_TP_CTL_FDI_AUTOTRAIN |
350 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
351 DP_TP_CTL_LINK_TRAIN_PAT1 |
352 DP_TP_CTL_ENABLE);
353
354 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
355 * DDI E does not support port reversal, the functionality is
356 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
357 * port reversal bit */
358 I915_WRITE(DDI_BUF_CTL(PORT_E),
359 DDI_BUF_CTL_ENABLE |
360 ((intel_crtc->config.fdi_lanes - 1) << 1) |
361 DDI_BUF_TRANS_SELECT(i / 2));
362 POSTING_READ(DDI_BUF_CTL(PORT_E));
363
364 udelay(600);
365
366 /* Program PCH FDI Receiver TU */
367 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
368
369 /* Enable PCH FDI Receiver with auto-training */
370 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
371 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
372 POSTING_READ(_FDI_RXA_CTL);
373
374 /* Wait for FDI receiver lane calibration */
375 udelay(30);
376
377 /* Unset FDI_RX_MISC pwrdn lanes */
378 temp = I915_READ(_FDI_RXA_MISC);
379 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
380 I915_WRITE(_FDI_RXA_MISC, temp);
381 POSTING_READ(_FDI_RXA_MISC);
382
383 /* Wait for FDI auto training time */
384 udelay(5);
385
386 temp = I915_READ(DP_TP_STATUS(PORT_E));
387 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
388 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
389
390 /* Enable normal pixel sending for FDI */
391 I915_WRITE(DP_TP_CTL(PORT_E),
392 DP_TP_CTL_FDI_AUTOTRAIN |
393 DP_TP_CTL_LINK_TRAIN_NORMAL |
394 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
395 DP_TP_CTL_ENABLE);
396
397 return;
398 }
399
400 temp = I915_READ(DDI_BUF_CTL(PORT_E));
401 temp &= ~DDI_BUF_CTL_ENABLE;
402 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
403 POSTING_READ(DDI_BUF_CTL(PORT_E));
404
405 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
406 temp = I915_READ(DP_TP_CTL(PORT_E));
407 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
408 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
409 I915_WRITE(DP_TP_CTL(PORT_E), temp);
410 POSTING_READ(DP_TP_CTL(PORT_E));
411
412 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
413
414 rx_ctl_val &= ~FDI_RX_ENABLE;
415 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
416 POSTING_READ(_FDI_RXA_CTL);
417
418 /* Reset FDI_RX_MISC pwrdn lanes */
419 temp = I915_READ(_FDI_RXA_MISC);
420 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
421 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
422 I915_WRITE(_FDI_RXA_MISC, temp);
423 POSTING_READ(_FDI_RXA_MISC);
424 }
425
426 DRM_ERROR("FDI link training failed!\n");
427 }
428
429 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
430 {
431 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
432 struct intel_digital_port *intel_dig_port =
433 enc_to_dig_port(&encoder->base);
434
435 intel_dp->DP = intel_dig_port->saved_port_bits |
436 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
437 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
438
439 }
440
441 static struct intel_encoder *
442 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
443 {
444 struct drm_device *dev = crtc->dev;
445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
446 struct intel_encoder *intel_encoder, *ret = NULL;
447 int num_encoders = 0;
448
449 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
450 ret = intel_encoder;
451 num_encoders++;
452 }
453
454 if (num_encoders != 1)
455 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
456 pipe_name(intel_crtc->pipe));
457
458 BUG_ON(ret == NULL);
459 return ret;
460 }
461
462 #define LC_FREQ 2700
463 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
464
465 #define P_MIN 2
466 #define P_MAX 64
467 #define P_INC 2
468
469 /* Constraints for PLL good behavior */
470 #define REF_MIN 48
471 #define REF_MAX 400
472 #define VCO_MIN 2400
473 #define VCO_MAX 4800
474
475 #define abs_diff(a, b) ({ \
476 typeof(a) __a = (a); \
477 typeof(b) __b = (b); \
478 (void) (&__a == &__b); \
479 __a > __b ? (__a - __b) : (__b - __a); })
480
481 struct wrpll_rnp {
482 unsigned p, n2, r2;
483 };
484
485 static unsigned wrpll_get_budget_for_freq(int clock)
486 {
487 unsigned budget;
488
489 switch (clock) {
490 case 25175000:
491 case 25200000:
492 case 27000000:
493 case 27027000:
494 case 37762500:
495 case 37800000:
496 case 40500000:
497 case 40541000:
498 case 54000000:
499 case 54054000:
500 case 59341000:
501 case 59400000:
502 case 72000000:
503 case 74176000:
504 case 74250000:
505 case 81000000:
506 case 81081000:
507 case 89012000:
508 case 89100000:
509 case 108000000:
510 case 108108000:
511 case 111264000:
512 case 111375000:
513 case 148352000:
514 case 148500000:
515 case 162000000:
516 case 162162000:
517 case 222525000:
518 case 222750000:
519 case 296703000:
520 case 297000000:
521 budget = 0;
522 break;
523 case 233500000:
524 case 245250000:
525 case 247750000:
526 case 253250000:
527 case 298000000:
528 budget = 1500;
529 break;
530 case 169128000:
531 case 169500000:
532 case 179500000:
533 case 202000000:
534 budget = 2000;
535 break;
536 case 256250000:
537 case 262500000:
538 case 270000000:
539 case 272500000:
540 case 273750000:
541 case 280750000:
542 case 281250000:
543 case 286000000:
544 case 291750000:
545 budget = 4000;
546 break;
547 case 267250000:
548 case 268500000:
549 budget = 5000;
550 break;
551 default:
552 budget = 1000;
553 break;
554 }
555
556 return budget;
557 }
558
559 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
560 unsigned r2, unsigned n2, unsigned p,
561 struct wrpll_rnp *best)
562 {
563 uint64_t a, b, c, d, diff, diff_best;
564
565 /* No best (r,n,p) yet */
566 if (best->p == 0) {
567 best->p = p;
568 best->n2 = n2;
569 best->r2 = r2;
570 return;
571 }
572
573 /*
574 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
575 * freq2k.
576 *
577 * delta = 1e6 *
578 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
579 * freq2k;
580 *
581 * and we would like delta <= budget.
582 *
583 * If the discrepancy is above the PPM-based budget, always prefer to
584 * improve upon the previous solution. However, if you're within the
585 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
586 */
587 a = freq2k * budget * p * r2;
588 b = freq2k * budget * best->p * best->r2;
589 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
590 diff_best = abs_diff(freq2k * best->p * best->r2,
591 LC_FREQ_2K * best->n2);
592 c = 1000000 * diff;
593 d = 1000000 * diff_best;
594
595 if (a < c && b < d) {
596 /* If both are above the budget, pick the closer */
597 if (best->p * best->r2 * diff < p * r2 * diff_best) {
598 best->p = p;
599 best->n2 = n2;
600 best->r2 = r2;
601 }
602 } else if (a >= c && b < d) {
603 /* If A is below the threshold but B is above it? Update. */
604 best->p = p;
605 best->n2 = n2;
606 best->r2 = r2;
607 } else if (a >= c && b >= d) {
608 /* Both are below the limit, so pick the higher n2/(r2*r2) */
609 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
610 best->p = p;
611 best->n2 = n2;
612 best->r2 = r2;
613 }
614 }
615 /* Otherwise a < c && b >= d, do nothing */
616 }
617
618 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
619 int reg)
620 {
621 int refclk = LC_FREQ;
622 int n, p, r;
623 u32 wrpll;
624
625 wrpll = I915_READ(reg);
626 switch (wrpll & WRPLL_PLL_REF_MASK) {
627 case WRPLL_PLL_SSC:
628 case WRPLL_PLL_NON_SSC:
629 /*
630 * We could calculate spread here, but our checking
631 * code only cares about 5% accuracy, and spread is a max of
632 * 0.5% downspread.
633 */
634 refclk = 135;
635 break;
636 case WRPLL_PLL_LCPLL:
637 refclk = LC_FREQ;
638 break;
639 default:
640 WARN(1, "bad wrpll refclk\n");
641 return 0;
642 }
643
644 r = wrpll & WRPLL_DIVIDER_REF_MASK;
645 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
646 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
647
648 /* Convert to KHz, p & r have a fixed point portion */
649 return (refclk * n * 100) / (p * r);
650 }
651
652 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
653 struct intel_crtc_config *pipe_config)
654 {
655 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
656 int link_clock = 0;
657 u32 val, pll;
658
659 val = pipe_config->ddi_pll_sel;
660 switch (val & PORT_CLK_SEL_MASK) {
661 case PORT_CLK_SEL_LCPLL_810:
662 link_clock = 81000;
663 break;
664 case PORT_CLK_SEL_LCPLL_1350:
665 link_clock = 135000;
666 break;
667 case PORT_CLK_SEL_LCPLL_2700:
668 link_clock = 270000;
669 break;
670 case PORT_CLK_SEL_WRPLL1:
671 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
672 break;
673 case PORT_CLK_SEL_WRPLL2:
674 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
675 break;
676 case PORT_CLK_SEL_SPLL:
677 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
678 if (pll == SPLL_PLL_FREQ_810MHz)
679 link_clock = 81000;
680 else if (pll == SPLL_PLL_FREQ_1350MHz)
681 link_clock = 135000;
682 else if (pll == SPLL_PLL_FREQ_2700MHz)
683 link_clock = 270000;
684 else {
685 WARN(1, "bad spll freq\n");
686 return;
687 }
688 break;
689 default:
690 WARN(1, "bad port clock sel\n");
691 return;
692 }
693
694 pipe_config->port_clock = link_clock * 2;
695
696 if (pipe_config->has_pch_encoder)
697 pipe_config->adjusted_mode.crtc_clock =
698 intel_dotclock_calculate(pipe_config->port_clock,
699 &pipe_config->fdi_m_n);
700 else if (pipe_config->has_dp_encoder)
701 pipe_config->adjusted_mode.crtc_clock =
702 intel_dotclock_calculate(pipe_config->port_clock,
703 &pipe_config->dp_m_n);
704 else
705 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
706 }
707
708 void intel_ddi_clock_get(struct intel_encoder *encoder,
709 struct intel_crtc_config *pipe_config)
710 {
711 hsw_ddi_clock_get(encoder, pipe_config);
712 }
713
714 static void
715 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
716 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
717 {
718 uint64_t freq2k;
719 unsigned p, n2, r2;
720 struct wrpll_rnp best = { 0, 0, 0 };
721 unsigned budget;
722
723 freq2k = clock / 100;
724
725 budget = wrpll_get_budget_for_freq(clock);
726
727 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
728 * and directly pass the LC PLL to it. */
729 if (freq2k == 5400000) {
730 *n2_out = 2;
731 *p_out = 1;
732 *r2_out = 2;
733 return;
734 }
735
736 /*
737 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
738 * the WR PLL.
739 *
740 * We want R so that REF_MIN <= Ref <= REF_MAX.
741 * Injecting R2 = 2 * R gives:
742 * REF_MAX * r2 > LC_FREQ * 2 and
743 * REF_MIN * r2 < LC_FREQ * 2
744 *
745 * Which means the desired boundaries for r2 are:
746 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
747 *
748 */
749 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
750 r2 <= LC_FREQ * 2 / REF_MIN;
751 r2++) {
752
753 /*
754 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
755 *
756 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
757 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
758 * VCO_MAX * r2 > n2 * LC_FREQ and
759 * VCO_MIN * r2 < n2 * LC_FREQ)
760 *
761 * Which means the desired boundaries for n2 are:
762 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
763 */
764 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
765 n2 <= VCO_MAX * r2 / LC_FREQ;
766 n2++) {
767
768 for (p = P_MIN; p <= P_MAX; p += P_INC)
769 wrpll_update_rnp(freq2k, budget,
770 r2, n2, p, &best);
771 }
772 }
773
774 *n2_out = best.n2;
775 *p_out = best.p;
776 *r2_out = best.r2;
777 }
778
779 static bool
780 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
781 struct intel_encoder *intel_encoder,
782 int clock)
783 {
784 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
785 struct intel_shared_dpll *pll;
786 uint32_t val;
787 unsigned p, n2, r2;
788
789 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
790
791 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
792 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
793 WRPLL_DIVIDER_POST(p);
794
795 intel_crtc->config.dpll_hw_state.wrpll = val;
796
797 pll = intel_get_shared_dpll(intel_crtc);
798 if (pll == NULL) {
799 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
800 pipe_name(intel_crtc->pipe));
801 return false;
802 }
803
804 intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
805 }
806
807 return true;
808 }
809
810
811 /*
812 * Tries to find a *shared* PLL for the CRTC and store it in
813 * intel_crtc->ddi_pll_sel.
814 *
815 * For private DPLLs, compute_config() should do the selection for us. This
816 * function should be folded into compute_config() eventually.
817 */
818 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
819 {
820 struct drm_crtc *crtc = &intel_crtc->base;
821 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
822 int clock = intel_crtc->config.port_clock;
823
824 intel_put_shared_dpll(intel_crtc);
825
826 return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
827 }
828
829 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
830 {
831 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
833 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
834 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
835 int type = intel_encoder->type;
836 uint32_t temp;
837
838 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
839 temp = TRANS_MSA_SYNC_CLK;
840 switch (intel_crtc->config.pipe_bpp) {
841 case 18:
842 temp |= TRANS_MSA_6_BPC;
843 break;
844 case 24:
845 temp |= TRANS_MSA_8_BPC;
846 break;
847 case 30:
848 temp |= TRANS_MSA_10_BPC;
849 break;
850 case 36:
851 temp |= TRANS_MSA_12_BPC;
852 break;
853 default:
854 BUG();
855 }
856 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
857 }
858 }
859
860 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
861 {
862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
866 uint32_t temp;
867 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
868 if (state == true)
869 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
870 else
871 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
872 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
873 }
874
875 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
876 {
877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
878 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
879 struct drm_encoder *encoder = &intel_encoder->base;
880 struct drm_device *dev = crtc->dev;
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 enum pipe pipe = intel_crtc->pipe;
883 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
884 enum port port = intel_ddi_get_encoder_port(intel_encoder);
885 int type = intel_encoder->type;
886 uint32_t temp;
887
888 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
889 temp = TRANS_DDI_FUNC_ENABLE;
890 temp |= TRANS_DDI_SELECT_PORT(port);
891
892 switch (intel_crtc->config.pipe_bpp) {
893 case 18:
894 temp |= TRANS_DDI_BPC_6;
895 break;
896 case 24:
897 temp |= TRANS_DDI_BPC_8;
898 break;
899 case 30:
900 temp |= TRANS_DDI_BPC_10;
901 break;
902 case 36:
903 temp |= TRANS_DDI_BPC_12;
904 break;
905 default:
906 BUG();
907 }
908
909 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
910 temp |= TRANS_DDI_PVSYNC;
911 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
912 temp |= TRANS_DDI_PHSYNC;
913
914 if (cpu_transcoder == TRANSCODER_EDP) {
915 switch (pipe) {
916 case PIPE_A:
917 /* On Haswell, can only use the always-on power well for
918 * eDP when not using the panel fitter, and when not
919 * using motion blur mitigation (which we don't
920 * support). */
921 if (IS_HASWELL(dev) &&
922 (intel_crtc->config.pch_pfit.enabled ||
923 intel_crtc->config.pch_pfit.force_thru))
924 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
925 else
926 temp |= TRANS_DDI_EDP_INPUT_A_ON;
927 break;
928 case PIPE_B:
929 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
930 break;
931 case PIPE_C:
932 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
933 break;
934 default:
935 BUG();
936 break;
937 }
938 }
939
940 if (type == INTEL_OUTPUT_HDMI) {
941 if (intel_crtc->config.has_hdmi_sink)
942 temp |= TRANS_DDI_MODE_SELECT_HDMI;
943 else
944 temp |= TRANS_DDI_MODE_SELECT_DVI;
945
946 } else if (type == INTEL_OUTPUT_ANALOG) {
947 temp |= TRANS_DDI_MODE_SELECT_FDI;
948 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
949
950 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
951 type == INTEL_OUTPUT_EDP) {
952 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
953
954 if (intel_dp->is_mst) {
955 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
956 } else
957 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
958
959 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
960 } else if (type == INTEL_OUTPUT_DP_MST) {
961 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
962
963 if (intel_dp->is_mst) {
964 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
965 } else
966 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
967
968 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
969 } else {
970 WARN(1, "Invalid encoder type %d for pipe %c\n",
971 intel_encoder->type, pipe_name(pipe));
972 }
973
974 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
975 }
976
977 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
978 enum transcoder cpu_transcoder)
979 {
980 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
981 uint32_t val = I915_READ(reg);
982
983 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
984 val |= TRANS_DDI_PORT_NONE;
985 I915_WRITE(reg, val);
986 }
987
988 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
989 {
990 struct drm_device *dev = intel_connector->base.dev;
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 struct intel_encoder *intel_encoder = intel_connector->encoder;
993 int type = intel_connector->base.connector_type;
994 enum port port = intel_ddi_get_encoder_port(intel_encoder);
995 enum pipe pipe = 0;
996 enum transcoder cpu_transcoder;
997 enum intel_display_power_domain power_domain;
998 uint32_t tmp;
999
1000 power_domain = intel_display_port_power_domain(intel_encoder);
1001 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1002 return false;
1003
1004 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1005 return false;
1006
1007 if (port == PORT_A)
1008 cpu_transcoder = TRANSCODER_EDP;
1009 else
1010 cpu_transcoder = (enum transcoder) pipe;
1011
1012 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1013
1014 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1015 case TRANS_DDI_MODE_SELECT_HDMI:
1016 case TRANS_DDI_MODE_SELECT_DVI:
1017 return (type == DRM_MODE_CONNECTOR_HDMIA);
1018
1019 case TRANS_DDI_MODE_SELECT_DP_SST:
1020 if (type == DRM_MODE_CONNECTOR_eDP)
1021 return true;
1022 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1023 case TRANS_DDI_MODE_SELECT_DP_MST:
1024 /* if the transcoder is in MST state then
1025 * connector isn't connected */
1026 return false;
1027
1028 case TRANS_DDI_MODE_SELECT_FDI:
1029 return (type == DRM_MODE_CONNECTOR_VGA);
1030
1031 default:
1032 return false;
1033 }
1034 }
1035
1036 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1037 enum pipe *pipe)
1038 {
1039 struct drm_device *dev = encoder->base.dev;
1040 struct drm_i915_private *dev_priv = dev->dev_private;
1041 enum port port = intel_ddi_get_encoder_port(encoder);
1042 enum intel_display_power_domain power_domain;
1043 u32 tmp;
1044 int i;
1045
1046 power_domain = intel_display_port_power_domain(encoder);
1047 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1048 return false;
1049
1050 tmp = I915_READ(DDI_BUF_CTL(port));
1051
1052 if (!(tmp & DDI_BUF_CTL_ENABLE))
1053 return false;
1054
1055 if (port == PORT_A) {
1056 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1057
1058 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1059 case TRANS_DDI_EDP_INPUT_A_ON:
1060 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1061 *pipe = PIPE_A;
1062 break;
1063 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1064 *pipe = PIPE_B;
1065 break;
1066 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1067 *pipe = PIPE_C;
1068 break;
1069 }
1070
1071 return true;
1072 } else {
1073 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1074 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1075
1076 if ((tmp & TRANS_DDI_PORT_MASK)
1077 == TRANS_DDI_SELECT_PORT(port)) {
1078 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1079 return false;
1080
1081 *pipe = i;
1082 return true;
1083 }
1084 }
1085 }
1086
1087 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1088
1089 return false;
1090 }
1091
1092 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1093 {
1094 struct drm_crtc *crtc = &intel_crtc->base;
1095 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1096 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1097 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1098 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1099
1100 if (cpu_transcoder != TRANSCODER_EDP)
1101 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1102 TRANS_CLK_SEL_PORT(port));
1103 }
1104
1105 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1106 {
1107 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1108 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1109
1110 if (cpu_transcoder != TRANSCODER_EDP)
1111 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1112 TRANS_CLK_SEL_DISABLED);
1113 }
1114
1115 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1116 {
1117 struct drm_encoder *encoder = &intel_encoder->base;
1118 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1119 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1120 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1121 int type = intel_encoder->type;
1122
1123 if (crtc->config.has_audio) {
1124 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1125 pipe_name(crtc->pipe));
1126
1127 /* write eld */
1128 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1129 intel_write_eld(encoder, &crtc->config.adjusted_mode);
1130 }
1131
1132 if (type == INTEL_OUTPUT_EDP) {
1133 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1134 intel_edp_panel_on(intel_dp);
1135 }
1136
1137 WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1138 I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1139
1140 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1141 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1142
1143 intel_ddi_init_dp_buf_reg(intel_encoder);
1144
1145 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1146 intel_dp_start_link_train(intel_dp);
1147 intel_dp_complete_link_train(intel_dp);
1148 if (port != PORT_A)
1149 intel_dp_stop_link_train(intel_dp);
1150 } else if (type == INTEL_OUTPUT_HDMI) {
1151 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1152
1153 intel_hdmi->set_infoframes(encoder,
1154 crtc->config.has_hdmi_sink,
1155 &crtc->config.adjusted_mode);
1156 }
1157 }
1158
1159 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1160 {
1161 struct drm_encoder *encoder = &intel_encoder->base;
1162 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1163 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1164 int type = intel_encoder->type;
1165 uint32_t val;
1166 bool wait = false;
1167
1168 val = I915_READ(DDI_BUF_CTL(port));
1169 if (val & DDI_BUF_CTL_ENABLE) {
1170 val &= ~DDI_BUF_CTL_ENABLE;
1171 I915_WRITE(DDI_BUF_CTL(port), val);
1172 wait = true;
1173 }
1174
1175 val = I915_READ(DP_TP_CTL(port));
1176 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1177 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1178 I915_WRITE(DP_TP_CTL(port), val);
1179
1180 if (wait)
1181 intel_wait_ddi_buf_idle(dev_priv, port);
1182
1183 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1184 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1185 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1186 intel_edp_panel_vdd_on(intel_dp);
1187 intel_edp_panel_off(intel_dp);
1188 }
1189
1190 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1191 }
1192
1193 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1194 {
1195 struct drm_encoder *encoder = &intel_encoder->base;
1196 struct drm_crtc *crtc = encoder->crtc;
1197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1198 int pipe = intel_crtc->pipe;
1199 struct drm_device *dev = encoder->dev;
1200 struct drm_i915_private *dev_priv = dev->dev_private;
1201 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1202 int type = intel_encoder->type;
1203 uint32_t tmp;
1204
1205 if (type == INTEL_OUTPUT_HDMI) {
1206 struct intel_digital_port *intel_dig_port =
1207 enc_to_dig_port(encoder);
1208
1209 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1210 * are ignored so nothing special needs to be done besides
1211 * enabling the port.
1212 */
1213 I915_WRITE(DDI_BUF_CTL(port),
1214 intel_dig_port->saved_port_bits |
1215 DDI_BUF_CTL_ENABLE);
1216 } else if (type == INTEL_OUTPUT_EDP) {
1217 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1218
1219 if (port == PORT_A)
1220 intel_dp_stop_link_train(intel_dp);
1221
1222 intel_edp_backlight_on(intel_dp);
1223 intel_edp_psr_enable(intel_dp);
1224 }
1225
1226 if (intel_crtc->config.has_audio) {
1227 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1228 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1229 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1230 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1231 }
1232 }
1233
1234 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1235 {
1236 struct drm_encoder *encoder = &intel_encoder->base;
1237 struct drm_crtc *crtc = encoder->crtc;
1238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1239 int pipe = intel_crtc->pipe;
1240 int type = intel_encoder->type;
1241 struct drm_device *dev = encoder->dev;
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 uint32_t tmp;
1244
1245 /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1246 * register is part of the power well on Haswell. */
1247 if (intel_crtc->config.has_audio) {
1248 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1249 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1250 (pipe * 4));
1251 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1252 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1253 }
1254
1255 if (type == INTEL_OUTPUT_EDP) {
1256 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1257
1258 intel_edp_psr_disable(intel_dp);
1259 intel_edp_backlight_off(intel_dp);
1260 }
1261 }
1262
1263 static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1264 {
1265 uint32_t lcpll = I915_READ(LCPLL_CTL);
1266 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1267
1268 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1269 return 800000;
1270 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1271 return 450000;
1272 else if (freq == LCPLL_CLK_FREQ_450)
1273 return 450000;
1274 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1275 return 540000;
1276 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1277 return 337500;
1278 else
1279 return 675000;
1280 }
1281
1282 static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1283 {
1284 struct drm_device *dev = dev_priv->dev;
1285 uint32_t lcpll = I915_READ(LCPLL_CTL);
1286 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1287
1288 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1289 return 800000;
1290 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1291 return 450000;
1292 else if (freq == LCPLL_CLK_FREQ_450)
1293 return 450000;
1294 else if (IS_HSW_ULT(dev))
1295 return 337500;
1296 else
1297 return 540000;
1298 }
1299
1300 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1301 {
1302 struct drm_device *dev = dev_priv->dev;
1303
1304 if (IS_BROADWELL(dev))
1305 return bdw_get_cdclk_freq(dev_priv);
1306
1307 /* Haswell */
1308 return hsw_get_cdclk_freq(dev_priv);
1309 }
1310
1311 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1312 struct intel_shared_dpll *pll)
1313 {
1314 I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);
1315 POSTING_READ(WRPLL_CTL(pll->id));
1316 udelay(20);
1317 }
1318
1319 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1320 struct intel_shared_dpll *pll)
1321 {
1322 uint32_t val;
1323
1324 val = I915_READ(WRPLL_CTL(pll->id));
1325 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1326 POSTING_READ(WRPLL_CTL(pll->id));
1327 }
1328
1329 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1330 struct intel_shared_dpll *pll,
1331 struct intel_dpll_hw_state *hw_state)
1332 {
1333 uint32_t val;
1334
1335 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1336 return false;
1337
1338 val = I915_READ(WRPLL_CTL(pll->id));
1339 hw_state->wrpll = val;
1340
1341 return val & WRPLL_PLL_ENABLE;
1342 }
1343
1344 static const char * const hsw_ddi_pll_names[] = {
1345 "WRPLL 1",
1346 "WRPLL 2",
1347 };
1348
1349 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1350 {
1351 int i;
1352
1353 dev_priv->num_shared_dpll = 2;
1354
1355 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1356 dev_priv->shared_dplls[i].id = i;
1357 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1358 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1359 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1360 dev_priv->shared_dplls[i].get_hw_state =
1361 hsw_ddi_pll_get_hw_state;
1362 }
1363 }
1364
1365 void intel_ddi_pll_init(struct drm_device *dev)
1366 {
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 uint32_t val = I915_READ(LCPLL_CTL);
1369
1370 hsw_shared_dplls_init(dev_priv);
1371
1372 /* The LCPLL register should be turned on by the BIOS. For now let's
1373 * just check its state and print errors in case something is wrong.
1374 * Don't even try to turn it on.
1375 */
1376
1377 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1378 intel_ddi_get_cdclk_freq(dev_priv));
1379
1380 if (val & LCPLL_CD_SOURCE_FCLK)
1381 DRM_ERROR("CDCLK source is not LCPLL\n");
1382
1383 if (val & LCPLL_PLL_DISABLE)
1384 DRM_ERROR("LCPLL is disabled\n");
1385 }
1386
1387 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1388 {
1389 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1390 struct intel_dp *intel_dp = &intel_dig_port->dp;
1391 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1392 enum port port = intel_dig_port->port;
1393 uint32_t val;
1394 bool wait = false;
1395
1396 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1397 val = I915_READ(DDI_BUF_CTL(port));
1398 if (val & DDI_BUF_CTL_ENABLE) {
1399 val &= ~DDI_BUF_CTL_ENABLE;
1400 I915_WRITE(DDI_BUF_CTL(port), val);
1401 wait = true;
1402 }
1403
1404 val = I915_READ(DP_TP_CTL(port));
1405 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1406 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1407 I915_WRITE(DP_TP_CTL(port), val);
1408 POSTING_READ(DP_TP_CTL(port));
1409
1410 if (wait)
1411 intel_wait_ddi_buf_idle(dev_priv, port);
1412 }
1413
1414 val = DP_TP_CTL_ENABLE |
1415 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1416 if (intel_dp->is_mst)
1417 val |= DP_TP_CTL_MODE_MST;
1418 else {
1419 val |= DP_TP_CTL_MODE_SST;
1420 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1421 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1422 }
1423 I915_WRITE(DP_TP_CTL(port), val);
1424 POSTING_READ(DP_TP_CTL(port));
1425
1426 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1427 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1428 POSTING_READ(DDI_BUF_CTL(port));
1429
1430 udelay(600);
1431 }
1432
1433 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1434 {
1435 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1436 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1437 uint32_t val;
1438
1439 intel_ddi_post_disable(intel_encoder);
1440
1441 val = I915_READ(_FDI_RXA_CTL);
1442 val &= ~FDI_RX_ENABLE;
1443 I915_WRITE(_FDI_RXA_CTL, val);
1444
1445 val = I915_READ(_FDI_RXA_MISC);
1446 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1447 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1448 I915_WRITE(_FDI_RXA_MISC, val);
1449
1450 val = I915_READ(_FDI_RXA_CTL);
1451 val &= ~FDI_PCDCLK;
1452 I915_WRITE(_FDI_RXA_CTL, val);
1453
1454 val = I915_READ(_FDI_RXA_CTL);
1455 val &= ~FDI_RX_PLL_ENABLE;
1456 I915_WRITE(_FDI_RXA_CTL, val);
1457 }
1458
1459 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1460 {
1461 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
1462 int type = intel_dig_port->base.type;
1463
1464 if (type != INTEL_OUTPUT_DISPLAYPORT &&
1465 type != INTEL_OUTPUT_EDP &&
1466 type != INTEL_OUTPUT_UNKNOWN) {
1467 return;
1468 }
1469
1470 intel_dp_hot_plug(intel_encoder);
1471 }
1472
1473 void intel_ddi_get_config(struct intel_encoder *encoder,
1474 struct intel_crtc_config *pipe_config)
1475 {
1476 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1477 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1478 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1479 u32 temp, flags = 0;
1480
1481 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1482 if (temp & TRANS_DDI_PHSYNC)
1483 flags |= DRM_MODE_FLAG_PHSYNC;
1484 else
1485 flags |= DRM_MODE_FLAG_NHSYNC;
1486 if (temp & TRANS_DDI_PVSYNC)
1487 flags |= DRM_MODE_FLAG_PVSYNC;
1488 else
1489 flags |= DRM_MODE_FLAG_NVSYNC;
1490
1491 pipe_config->adjusted_mode.flags |= flags;
1492
1493 switch (temp & TRANS_DDI_BPC_MASK) {
1494 case TRANS_DDI_BPC_6:
1495 pipe_config->pipe_bpp = 18;
1496 break;
1497 case TRANS_DDI_BPC_8:
1498 pipe_config->pipe_bpp = 24;
1499 break;
1500 case TRANS_DDI_BPC_10:
1501 pipe_config->pipe_bpp = 30;
1502 break;
1503 case TRANS_DDI_BPC_12:
1504 pipe_config->pipe_bpp = 36;
1505 break;
1506 default:
1507 break;
1508 }
1509
1510 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1511 case TRANS_DDI_MODE_SELECT_HDMI:
1512 pipe_config->has_hdmi_sink = true;
1513 case TRANS_DDI_MODE_SELECT_DVI:
1514 case TRANS_DDI_MODE_SELECT_FDI:
1515 break;
1516 case TRANS_DDI_MODE_SELECT_DP_SST:
1517 case TRANS_DDI_MODE_SELECT_DP_MST:
1518 pipe_config->has_dp_encoder = true;
1519 intel_dp_get_m_n(intel_crtc, pipe_config);
1520 break;
1521 default:
1522 break;
1523 }
1524
1525 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1526 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1527 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1528 pipe_config->has_audio = true;
1529 }
1530
1531 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1532 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1533 /*
1534 * This is a big fat ugly hack.
1535 *
1536 * Some machines in UEFI boot mode provide us a VBT that has 18
1537 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1538 * unknown we fail to light up. Yet the same BIOS boots up with
1539 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1540 * max, not what it tells us to use.
1541 *
1542 * Note: This will still be broken if the eDP panel is not lit
1543 * up by the BIOS, and thus we can't get the mode at module
1544 * load.
1545 */
1546 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1547 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1548 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1549 }
1550
1551 hsw_ddi_clock_get(encoder, pipe_config);
1552 }
1553
1554 static void intel_ddi_destroy(struct drm_encoder *encoder)
1555 {
1556 /* HDMI has nothing special to destroy, so we can go with this. */
1557 intel_dp_encoder_destroy(encoder);
1558 }
1559
1560 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1561 struct intel_crtc_config *pipe_config)
1562 {
1563 int type = encoder->type;
1564 int port = intel_ddi_get_encoder_port(encoder);
1565
1566 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1567
1568 if (port == PORT_A)
1569 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1570
1571 if (type == INTEL_OUTPUT_HDMI)
1572 return intel_hdmi_compute_config(encoder, pipe_config);
1573 else
1574 return intel_dp_compute_config(encoder, pipe_config);
1575 }
1576
1577 static const struct drm_encoder_funcs intel_ddi_funcs = {
1578 .destroy = intel_ddi_destroy,
1579 };
1580
1581 static struct intel_connector *
1582 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1583 {
1584 struct intel_connector *connector;
1585 enum port port = intel_dig_port->port;
1586
1587 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1588 if (!connector)
1589 return NULL;
1590
1591 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1592 if (!intel_dp_init_connector(intel_dig_port, connector)) {
1593 kfree(connector);
1594 return NULL;
1595 }
1596
1597 return connector;
1598 }
1599
1600 static struct intel_connector *
1601 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1602 {
1603 struct intel_connector *connector;
1604 enum port port = intel_dig_port->port;
1605
1606 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1607 if (!connector)
1608 return NULL;
1609
1610 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1611 intel_hdmi_init_connector(intel_dig_port, connector);
1612
1613 return connector;
1614 }
1615
1616 void intel_ddi_init(struct drm_device *dev, enum port port)
1617 {
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619 struct intel_digital_port *intel_dig_port;
1620 struct intel_encoder *intel_encoder;
1621 struct drm_encoder *encoder;
1622 bool init_hdmi, init_dp;
1623
1624 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1625 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1626 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1627 if (!init_dp && !init_hdmi) {
1628 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
1629 port_name(port));
1630 init_hdmi = true;
1631 init_dp = true;
1632 }
1633
1634 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1635 if (!intel_dig_port)
1636 return;
1637
1638 intel_encoder = &intel_dig_port->base;
1639 encoder = &intel_encoder->base;
1640
1641 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1642 DRM_MODE_ENCODER_TMDS);
1643
1644 intel_encoder->compute_config = intel_ddi_compute_config;
1645 intel_encoder->enable = intel_enable_ddi;
1646 intel_encoder->pre_enable = intel_ddi_pre_enable;
1647 intel_encoder->disable = intel_disable_ddi;
1648 intel_encoder->post_disable = intel_ddi_post_disable;
1649 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1650 intel_encoder->get_config = intel_ddi_get_config;
1651
1652 intel_dig_port->port = port;
1653 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1654 (DDI_BUF_PORT_REVERSAL |
1655 DDI_A_4_LANES);
1656
1657 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1658 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1659 intel_encoder->cloneable = 0;
1660 intel_encoder->hot_plug = intel_ddi_hot_plug;
1661
1662 if (init_dp) {
1663 if (!intel_ddi_init_dp_connector(intel_dig_port))
1664 goto err;
1665
1666 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1667 dev_priv->hpd_irq_port[port] = intel_dig_port;
1668 }
1669
1670 /* In theory we don't need the encoder->type check, but leave it just in
1671 * case we have some really bad VBTs... */
1672 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
1673 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
1674 goto err;
1675 }
1676
1677 return;
1678
1679 err:
1680 drm_encoder_cleanup(encoder);
1681 kfree(intel_dig_port);
1682 }
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