2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans
{
32 u32 trans1
; /* balance leg enable, de-emph level */
33 u32 trans2
; /* vref sel, vswing */
36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
40 static const struct ddi_buf_trans hsw_ddi_translations_dp
[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
52 static const struct ddi_buf_trans hsw_ddi_translations_fdi
[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi
[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
80 static const struct ddi_buf_trans bdw_ddi_translations_edp
[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
92 static const struct ddi_buf_trans bdw_ddi_translations_dp
[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
98 { 0x00DB6FFF, 0x00160005 },
99 { 0x80C71FFF, 0x001A0002 },
100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
104 static const struct ddi_buf_trans bdw_ddi_translations_fdi
[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi
[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
130 static const struct ddi_buf_trans skl_ddi_translations_dp
[] = {
131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
133 { 0x00006012, 0x00000088 },
134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
136 { 0x00004014, 0x00000088 },
137 { 0x00006012, 0x00000087 },
138 { 0x00000018, 0x00000088 },
139 { 0x00004014, 0x00000087 },
142 static const struct ddi_buf_trans skl_ddi_translations_hdmi
[] = {
143 /* Idx NT mV T mV db */
144 { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */
145 { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */
146 { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */
147 { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */
148 { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */
149 { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */
150 { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */
151 { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */
152 { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */
153 { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */
156 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
158 struct drm_encoder
*encoder
= &intel_encoder
->base
;
159 int type
= intel_encoder
->type
;
161 if (type
== INTEL_OUTPUT_DP_MST
) {
162 struct intel_digital_port
*intel_dig_port
= enc_to_mst(encoder
)->primary
;
163 return intel_dig_port
->port
;
164 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
165 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
166 struct intel_digital_port
*intel_dig_port
=
167 enc_to_dig_port(encoder
);
168 return intel_dig_port
->port
;
170 } else if (type
== INTEL_OUTPUT_ANALOG
) {
174 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
180 * Starting with Haswell, DDI port buffers must be programmed with correct
181 * values in advance. The buffer values are different for FDI and DP modes,
182 * but the HDMI/DVI fields are shared among those. So we program the DDI
183 * in either FDI or DP modes only, as HDMI connections will work with both
186 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
)
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
190 int i
, n_hdmi_entries
, hdmi_800mV_0dB
;
191 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
192 const struct ddi_buf_trans
*ddi_translations_fdi
;
193 const struct ddi_buf_trans
*ddi_translations_dp
;
194 const struct ddi_buf_trans
*ddi_translations_edp
;
195 const struct ddi_buf_trans
*ddi_translations_hdmi
;
196 const struct ddi_buf_trans
*ddi_translations
;
198 if (IS_SKYLAKE(dev
)) {
199 ddi_translations_fdi
= NULL
;
200 ddi_translations_dp
= skl_ddi_translations_dp
;
201 ddi_translations_edp
= skl_ddi_translations_dp
;
202 ddi_translations_hdmi
= skl_ddi_translations_hdmi
;
203 n_hdmi_entries
= ARRAY_SIZE(skl_ddi_translations_hdmi
);
205 } else if (IS_BROADWELL(dev
)) {
206 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
207 ddi_translations_dp
= bdw_ddi_translations_dp
;
208 ddi_translations_edp
= bdw_ddi_translations_edp
;
209 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
210 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
212 } else if (IS_HASWELL(dev
)) {
213 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
214 ddi_translations_dp
= hsw_ddi_translations_dp
;
215 ddi_translations_edp
= hsw_ddi_translations_dp
;
216 ddi_translations_hdmi
= hsw_ddi_translations_hdmi
;
217 n_hdmi_entries
= ARRAY_SIZE(hsw_ddi_translations_hdmi
);
220 WARN(1, "ddi translation table missing\n");
221 ddi_translations_edp
= bdw_ddi_translations_dp
;
222 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
223 ddi_translations_dp
= bdw_ddi_translations_dp
;
224 ddi_translations_hdmi
= bdw_ddi_translations_hdmi
;
225 n_hdmi_entries
= ARRAY_SIZE(bdw_ddi_translations_hdmi
);
231 ddi_translations
= ddi_translations_edp
;
235 ddi_translations
= ddi_translations_dp
;
238 if (intel_dp_is_edp(dev
, PORT_D
))
239 ddi_translations
= ddi_translations_edp
;
241 ddi_translations
= ddi_translations_dp
;
244 if (ddi_translations_fdi
)
245 ddi_translations
= ddi_translations_fdi
;
247 ddi_translations
= ddi_translations_dp
;
253 for (i
= 0, reg
= DDI_BUF_TRANS(port
);
254 i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
255 I915_WRITE(reg
, ddi_translations
[i
].trans1
);
257 I915_WRITE(reg
, ddi_translations
[i
].trans2
);
261 /* Choose a good default if VBT is badly populated */
262 if (hdmi_level
== HDMI_LEVEL_SHIFT_UNKNOWN
||
263 hdmi_level
>= n_hdmi_entries
)
264 hdmi_level
= hdmi_800mV_0dB
;
266 /* Entry 9 is for HDMI: */
267 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans1
);
269 I915_WRITE(reg
, ddi_translations_hdmi
[hdmi_level
].trans2
);
273 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
274 * mode and port E for FDI.
276 void intel_prepare_ddi(struct drm_device
*dev
)
283 for (port
= PORT_A
; port
<= PORT_E
; port
++)
284 intel_prepare_ddi_buffers(dev
, port
);
287 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
290 uint32_t reg
= DDI_BUF_CTL(port
);
293 for (i
= 0; i
< 8; i
++) {
295 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
298 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
301 /* Starting with Haswell, different DDI ports can work in FDI mode for
302 * connection to the PCH-located connectors. For this, it is necessary to train
303 * both the DDI port and PCH receiver for the desired DDI buffer settings.
305 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
306 * please note that when FDI mode is active on DDI E, it shares 2 lines with
307 * DDI A (which is used for eDP)
310 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
312 struct drm_device
*dev
= crtc
->dev
;
313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
314 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
315 u32 temp
, i
, rx_ctl_val
;
317 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
318 * mode set "sequence for CRT port" document:
319 * - TP1 to TP2 time with the default value
322 * WaFDIAutoLinkSetTimingOverrride:hsw
324 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
325 FDI_RX_PWRDN_LANE0_VAL(2) |
326 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
328 /* Enable the PCH Receiver FDI PLL */
329 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
331 FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
332 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
333 POSTING_READ(_FDI_RXA_CTL
);
336 /* Switch from Rawclk to PCDclk */
337 rx_ctl_val
|= FDI_PCDCLK
;
338 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
340 /* Configure Port Clock Select */
341 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->config
->ddi_pll_sel
);
342 WARN_ON(intel_crtc
->config
->ddi_pll_sel
!= PORT_CLK_SEL_SPLL
);
344 /* Start the training iterating through available voltages and emphasis,
345 * testing each value twice. */
346 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_translations_fdi
) * 2; i
++) {
347 /* Configure DP_TP_CTL with auto-training */
348 I915_WRITE(DP_TP_CTL(PORT_E
),
349 DP_TP_CTL_FDI_AUTOTRAIN
|
350 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
351 DP_TP_CTL_LINK_TRAIN_PAT1
|
354 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
355 * DDI E does not support port reversal, the functionality is
356 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
357 * port reversal bit */
358 I915_WRITE(DDI_BUF_CTL(PORT_E
),
360 ((intel_crtc
->config
->fdi_lanes
- 1) << 1) |
361 DDI_BUF_TRANS_SELECT(i
/ 2));
362 POSTING_READ(DDI_BUF_CTL(PORT_E
));
366 /* Program PCH FDI Receiver TU */
367 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
369 /* Enable PCH FDI Receiver with auto-training */
370 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
371 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
372 POSTING_READ(_FDI_RXA_CTL
);
374 /* Wait for FDI receiver lane calibration */
377 /* Unset FDI_RX_MISC pwrdn lanes */
378 temp
= I915_READ(_FDI_RXA_MISC
);
379 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
380 I915_WRITE(_FDI_RXA_MISC
, temp
);
381 POSTING_READ(_FDI_RXA_MISC
);
383 /* Wait for FDI auto training time */
386 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
387 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
388 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
390 /* Enable normal pixel sending for FDI */
391 I915_WRITE(DP_TP_CTL(PORT_E
),
392 DP_TP_CTL_FDI_AUTOTRAIN
|
393 DP_TP_CTL_LINK_TRAIN_NORMAL
|
394 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
400 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
401 temp
&= ~DDI_BUF_CTL_ENABLE
;
402 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
403 POSTING_READ(DDI_BUF_CTL(PORT_E
));
405 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
406 temp
= I915_READ(DP_TP_CTL(PORT_E
));
407 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
408 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
409 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
410 POSTING_READ(DP_TP_CTL(PORT_E
));
412 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
414 rx_ctl_val
&= ~FDI_RX_ENABLE
;
415 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
416 POSTING_READ(_FDI_RXA_CTL
);
418 /* Reset FDI_RX_MISC pwrdn lanes */
419 temp
= I915_READ(_FDI_RXA_MISC
);
420 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
421 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
422 I915_WRITE(_FDI_RXA_MISC
, temp
);
423 POSTING_READ(_FDI_RXA_MISC
);
426 DRM_ERROR("FDI link training failed!\n");
429 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
)
431 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
432 struct intel_digital_port
*intel_dig_port
=
433 enc_to_dig_port(&encoder
->base
);
435 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
436 DDI_BUF_CTL_ENABLE
| DDI_BUF_TRANS_SELECT(0);
437 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
441 static struct intel_encoder
*
442 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
444 struct drm_device
*dev
= crtc
->dev
;
445 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
446 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
447 int num_encoders
= 0;
449 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
454 if (num_encoders
!= 1)
455 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
456 pipe_name(intel_crtc
->pipe
));
462 static struct intel_encoder
*
463 intel_ddi_get_crtc_new_encoder(struct intel_crtc
*crtc
)
465 struct drm_device
*dev
= crtc
->base
.dev
;
466 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
467 int num_encoders
= 0;
469 for_each_intel_encoder(dev
, intel_encoder
) {
470 if (intel_encoder
->new_crtc
== crtc
) {
476 WARN(num_encoders
!= 1, "%d encoders on crtc for pipe %c\n", num_encoders
,
477 pipe_name(crtc
->pipe
));
484 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
490 /* Constraints for PLL good behavior */
496 #define abs_diff(a, b) ({ \
497 typeof(a) __a = (a); \
498 typeof(b) __b = (b); \
499 (void) (&__a == &__b); \
500 __a > __b ? (__a - __b) : (__b - __a); })
506 static unsigned wrpll_get_budget_for_freq(int clock
)
580 static void wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
581 unsigned r2
, unsigned n2
, unsigned p
,
582 struct wrpll_rnp
*best
)
584 uint64_t a
, b
, c
, d
, diff
, diff_best
;
586 /* No best (r,n,p) yet */
595 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
599 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
602 * and we would like delta <= budget.
604 * If the discrepancy is above the PPM-based budget, always prefer to
605 * improve upon the previous solution. However, if you're within the
606 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
608 a
= freq2k
* budget
* p
* r2
;
609 b
= freq2k
* budget
* best
->p
* best
->r2
;
610 diff
= abs_diff(freq2k
* p
* r2
, LC_FREQ_2K
* n2
);
611 diff_best
= abs_diff(freq2k
* best
->p
* best
->r2
,
612 LC_FREQ_2K
* best
->n2
);
614 d
= 1000000 * diff_best
;
616 if (a
< c
&& b
< d
) {
617 /* If both are above the budget, pick the closer */
618 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
623 } else if (a
>= c
&& b
< d
) {
624 /* If A is below the threshold but B is above it? Update. */
628 } else if (a
>= c
&& b
>= d
) {
629 /* Both are below the limit, so pick the higher n2/(r2*r2) */
630 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
636 /* Otherwise a < c && b >= d, do nothing */
639 static int intel_ddi_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
642 int refclk
= LC_FREQ
;
646 wrpll
= I915_READ(reg
);
647 switch (wrpll
& WRPLL_PLL_REF_MASK
) {
649 case WRPLL_PLL_NON_SSC
:
651 * We could calculate spread here, but our checking
652 * code only cares about 5% accuracy, and spread is a max of
657 case WRPLL_PLL_LCPLL
:
661 WARN(1, "bad wrpll refclk\n");
665 r
= wrpll
& WRPLL_DIVIDER_REF_MASK
;
666 p
= (wrpll
& WRPLL_DIVIDER_POST_MASK
) >> WRPLL_DIVIDER_POST_SHIFT
;
667 n
= (wrpll
& WRPLL_DIVIDER_FB_MASK
) >> WRPLL_DIVIDER_FB_SHIFT
;
669 /* Convert to KHz, p & r have a fixed point portion */
670 return (refclk
* n
* 100) / (p
* r
);
673 static int skl_calc_wrpll_link(struct drm_i915_private
*dev_priv
,
676 uint32_t cfgcr1_reg
, cfgcr2_reg
;
677 uint32_t cfgcr1_val
, cfgcr2_val
;
678 uint32_t p0
, p1
, p2
, dco_freq
;
680 cfgcr1_reg
= GET_CFG_CR1_REG(dpll
);
681 cfgcr2_reg
= GET_CFG_CR2_REG(dpll
);
683 cfgcr1_val
= I915_READ(cfgcr1_reg
);
684 cfgcr2_val
= I915_READ(cfgcr2_reg
);
686 p0
= cfgcr2_val
& DPLL_CFGCR2_PDIV_MASK
;
687 p2
= cfgcr2_val
& DPLL_CFGCR2_KDIV_MASK
;
689 if (cfgcr2_val
& DPLL_CFGCR2_QDIV_MODE(1))
690 p1
= (cfgcr2_val
& DPLL_CFGCR2_QDIV_RATIO_MASK
) >> 8;
696 case DPLL_CFGCR2_PDIV_1
:
699 case DPLL_CFGCR2_PDIV_2
:
702 case DPLL_CFGCR2_PDIV_3
:
705 case DPLL_CFGCR2_PDIV_7
:
711 case DPLL_CFGCR2_KDIV_5
:
714 case DPLL_CFGCR2_KDIV_2
:
717 case DPLL_CFGCR2_KDIV_3
:
720 case DPLL_CFGCR2_KDIV_1
:
725 dco_freq
= (cfgcr1_val
& DPLL_CFGCR1_DCO_INTEGER_MASK
) * 24 * 1000;
727 dco_freq
+= (((cfgcr1_val
& DPLL_CFGCR1_DCO_FRACTION_MASK
) >> 9) * 24 *
730 return dco_freq
/ (p0
* p1
* p2
* 5);
734 static void skl_ddi_clock_get(struct intel_encoder
*encoder
,
735 struct intel_crtc_state
*pipe_config
)
737 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
739 uint32_t dpll_ctl1
, dpll
;
741 dpll
= pipe_config
->ddi_pll_sel
;
743 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
745 if (dpll_ctl1
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
746 link_clock
= skl_calc_wrpll_link(dev_priv
, dpll
);
748 link_clock
= dpll_ctl1
& DPLL_CRTL1_LINK_RATE_MASK(dpll
);
749 link_clock
>>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll
);
751 switch (link_clock
) {
752 case DPLL_CRTL1_LINK_RATE_810
:
755 case DPLL_CRTL1_LINK_RATE_1350
:
758 case DPLL_CRTL1_LINK_RATE_2700
:
762 WARN(1, "Unsupported link rate\n");
768 pipe_config
->port_clock
= link_clock
;
770 if (pipe_config
->has_dp_encoder
)
771 pipe_config
->base
.adjusted_mode
.crtc_clock
=
772 intel_dotclock_calculate(pipe_config
->port_clock
,
773 &pipe_config
->dp_m_n
);
775 pipe_config
->base
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
778 static void hsw_ddi_clock_get(struct intel_encoder
*encoder
,
779 struct intel_crtc_state
*pipe_config
)
781 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
785 val
= pipe_config
->ddi_pll_sel
;
786 switch (val
& PORT_CLK_SEL_MASK
) {
787 case PORT_CLK_SEL_LCPLL_810
:
790 case PORT_CLK_SEL_LCPLL_1350
:
793 case PORT_CLK_SEL_LCPLL_2700
:
796 case PORT_CLK_SEL_WRPLL1
:
797 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL1
);
799 case PORT_CLK_SEL_WRPLL2
:
800 link_clock
= intel_ddi_calc_wrpll_link(dev_priv
, WRPLL_CTL2
);
802 case PORT_CLK_SEL_SPLL
:
803 pll
= I915_READ(SPLL_CTL
) & SPLL_PLL_FREQ_MASK
;
804 if (pll
== SPLL_PLL_FREQ_810MHz
)
806 else if (pll
== SPLL_PLL_FREQ_1350MHz
)
808 else if (pll
== SPLL_PLL_FREQ_2700MHz
)
811 WARN(1, "bad spll freq\n");
816 WARN(1, "bad port clock sel\n");
820 pipe_config
->port_clock
= link_clock
* 2;
822 if (pipe_config
->has_pch_encoder
)
823 pipe_config
->base
.adjusted_mode
.crtc_clock
=
824 intel_dotclock_calculate(pipe_config
->port_clock
,
825 &pipe_config
->fdi_m_n
);
826 else if (pipe_config
->has_dp_encoder
)
827 pipe_config
->base
.adjusted_mode
.crtc_clock
=
828 intel_dotclock_calculate(pipe_config
->port_clock
,
829 &pipe_config
->dp_m_n
);
831 pipe_config
->base
.adjusted_mode
.crtc_clock
= pipe_config
->port_clock
;
834 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
835 struct intel_crtc_state
*pipe_config
)
837 struct drm_device
*dev
= encoder
->base
.dev
;
839 if (INTEL_INFO(dev
)->gen
<= 8)
840 hsw_ddi_clock_get(encoder
, pipe_config
);
842 skl_ddi_clock_get(encoder
, pipe_config
);
846 hsw_ddi_calculate_wrpll(int clock
/* in Hz */,
847 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
851 struct wrpll_rnp best
= { 0, 0, 0 };
854 freq2k
= clock
/ 100;
856 budget
= wrpll_get_budget_for_freq(clock
);
858 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
859 * and directly pass the LC PLL to it. */
860 if (freq2k
== 5400000) {
868 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
871 * We want R so that REF_MIN <= Ref <= REF_MAX.
872 * Injecting R2 = 2 * R gives:
873 * REF_MAX * r2 > LC_FREQ * 2 and
874 * REF_MIN * r2 < LC_FREQ * 2
876 * Which means the desired boundaries for r2 are:
877 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
880 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
881 r2
<= LC_FREQ
* 2 / REF_MIN
;
885 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
887 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
888 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
889 * VCO_MAX * r2 > n2 * LC_FREQ and
890 * VCO_MIN * r2 < n2 * LC_FREQ)
892 * Which means the desired boundaries for n2 are:
893 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
895 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
896 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
899 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
900 wrpll_update_rnp(freq2k
, budget
,
911 hsw_ddi_pll_select(struct intel_crtc
*intel_crtc
,
912 struct intel_crtc_state
*crtc_state
,
913 struct intel_encoder
*intel_encoder
,
916 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
917 struct intel_shared_dpll
*pll
;
921 hsw_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
923 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_LCPLL
|
924 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
925 WRPLL_DIVIDER_POST(p
);
927 crtc_state
->dpll_hw_state
.wrpll
= val
;
929 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
931 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
932 pipe_name(intel_crtc
->pipe
));
936 crtc_state
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL(pll
->id
);
942 struct skl_wrpll_params
{
943 uint32_t dco_fraction
;
944 uint32_t dco_integer
;
949 uint32_t central_freq
;
953 skl_ddi_calculate_wrpll(int clock
/* in Hz */,
954 struct skl_wrpll_params
*wrpll_params
)
956 uint64_t afe_clock
= clock
* 5; /* AFE Clock is 5x Pixel clock */
957 uint64_t dco_central_freq
[3] = {8400000000ULL,
960 uint32_t min_dco_deviation
= 400;
961 uint32_t min_dco_index
= 3;
962 uint32_t P0
[4] = {1, 2, 3, 7};
963 uint32_t P2
[4] = {1, 2, 3, 5};
965 uint32_t candidate_p
= 0;
966 uint32_t candidate_p0
[3] = {0}, candidate_p1
[3] = {0};
967 uint32_t candidate_p2
[3] = {0};
968 uint32_t dco_central_freq_deviation
[3];
969 uint32_t i
, P1
, k
, dco_count
;
970 bool retry_with_odd
= false;
973 /* Determine P0, P1 or P2 */
974 for (dco_count
= 0; dco_count
< 3; dco_count
++) {
977 div64_u64(dco_central_freq
[dco_count
], afe_clock
);
978 if (retry_with_odd
== false)
979 candidate_p
= (candidate_p
% 2 == 0 ?
980 candidate_p
: candidate_p
+ 1);
982 for (P1
= 1; P1
< candidate_p
; P1
++) {
983 for (i
= 0; i
< 4; i
++) {
984 if (!(P0
[i
] != 1 || P1
== 1))
987 for (k
= 0; k
< 4; k
++) {
988 if (P1
!= 1 && P2
[k
] != 2)
991 if (candidate_p
== P0
[i
] * P1
* P2
[k
]) {
992 /* Found possible P0, P1, P2 */
994 candidate_p0
[dco_count
] = P0
[i
];
995 candidate_p1
[dco_count
] = P1
;
996 candidate_p2
[dco_count
] = P2
[k
];
1006 dco_central_freq_deviation
[dco_count
] =
1008 abs_diff((candidate_p
* afe_clock
),
1009 dco_central_freq
[dco_count
]),
1010 dco_central_freq
[dco_count
]);
1012 if (dco_central_freq_deviation
[dco_count
] <
1013 min_dco_deviation
) {
1015 dco_central_freq_deviation
[dco_count
];
1016 min_dco_index
= dco_count
;
1020 if (min_dco_index
> 2 && dco_count
== 2) {
1021 retry_with_odd
= true;
1026 if (min_dco_index
> 2) {
1027 WARN(1, "No valid values found for the given pixel clock\n");
1029 wrpll_params
->central_freq
= dco_central_freq
[min_dco_index
];
1031 switch (dco_central_freq
[min_dco_index
]) {
1033 wrpll_params
->central_freq
= 0;
1036 wrpll_params
->central_freq
= 1;
1039 wrpll_params
->central_freq
= 3;
1042 switch (candidate_p0
[min_dco_index
]) {
1044 wrpll_params
->pdiv
= 0;
1047 wrpll_params
->pdiv
= 1;
1050 wrpll_params
->pdiv
= 2;
1053 wrpll_params
->pdiv
= 4;
1056 WARN(1, "Incorrect PDiv\n");
1059 switch (candidate_p2
[min_dco_index
]) {
1061 wrpll_params
->kdiv
= 0;
1064 wrpll_params
->kdiv
= 1;
1067 wrpll_params
->kdiv
= 2;
1070 wrpll_params
->kdiv
= 3;
1073 WARN(1, "Incorrect KDiv\n");
1076 wrpll_params
->qdiv_ratio
= candidate_p1
[min_dco_index
];
1077 wrpll_params
->qdiv_mode
=
1078 (wrpll_params
->qdiv_ratio
== 1) ? 0 : 1;
1080 dco_freq
= candidate_p0
[min_dco_index
] *
1081 candidate_p1
[min_dco_index
] *
1082 candidate_p2
[min_dco_index
] * afe_clock
;
1085 * Intermediate values are in Hz.
1086 * Divide by MHz to match bsepc
1088 wrpll_params
->dco_integer
= div_u64(dco_freq
, (24 * MHz(1)));
1089 wrpll_params
->dco_fraction
=
1090 div_u64(((div_u64(dco_freq
, 24) -
1091 wrpll_params
->dco_integer
* MHz(1)) * 0x8000), MHz(1));
1098 skl_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1099 struct intel_crtc_state
*crtc_state
,
1100 struct intel_encoder
*intel_encoder
,
1103 struct intel_shared_dpll
*pll
;
1104 uint32_t ctrl1
, cfgcr1
, cfgcr2
;
1107 * See comment in intel_dpll_hw_state to understand why we always use 0
1108 * as the DPLL id in this function.
1111 ctrl1
= DPLL_CTRL1_OVERRIDE(0);
1113 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
1114 struct skl_wrpll_params wrpll_params
= { 0, };
1116 ctrl1
|= DPLL_CTRL1_HDMI_MODE(0);
1118 skl_ddi_calculate_wrpll(clock
* 1000, &wrpll_params
);
1120 cfgcr1
= DPLL_CFGCR1_FREQ_ENABLE
|
1121 DPLL_CFGCR1_DCO_FRACTION(wrpll_params
.dco_fraction
) |
1122 wrpll_params
.dco_integer
;
1124 cfgcr2
= DPLL_CFGCR2_QDIV_RATIO(wrpll_params
.qdiv_ratio
) |
1125 DPLL_CFGCR2_QDIV_MODE(wrpll_params
.qdiv_mode
) |
1126 DPLL_CFGCR2_KDIV(wrpll_params
.kdiv
) |
1127 DPLL_CFGCR2_PDIV(wrpll_params
.pdiv
) |
1128 wrpll_params
.central_freq
;
1129 } else if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
) {
1130 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1131 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1133 switch (intel_dp
->link_bw
) {
1134 case DP_LINK_BW_1_62
:
1135 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810
, 0);
1137 case DP_LINK_BW_2_7
:
1138 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350
, 0);
1140 case DP_LINK_BW_5_4
:
1141 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700
, 0);
1145 cfgcr1
= cfgcr2
= 0;
1149 crtc_state
->dpll_hw_state
.ctrl1
= ctrl1
;
1150 crtc_state
->dpll_hw_state
.cfgcr1
= cfgcr1
;
1151 crtc_state
->dpll_hw_state
.cfgcr2
= cfgcr2
;
1153 pll
= intel_get_shared_dpll(intel_crtc
, crtc_state
);
1155 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1156 pipe_name(intel_crtc
->pipe
));
1160 /* shared DPLL id 0 is DPLL 1 */
1161 crtc_state
->ddi_pll_sel
= pll
->id
+ 1;
1167 * Tries to find a *shared* PLL for the CRTC and store it in
1168 * intel_crtc->ddi_pll_sel.
1170 * For private DPLLs, compute_config() should do the selection for us. This
1171 * function should be folded into compute_config() eventually.
1173 bool intel_ddi_pll_select(struct intel_crtc
*intel_crtc
,
1174 struct intel_crtc_state
*crtc_state
)
1176 struct drm_device
*dev
= intel_crtc
->base
.dev
;
1177 struct intel_encoder
*intel_encoder
=
1178 intel_ddi_get_crtc_new_encoder(intel_crtc
);
1179 int clock
= crtc_state
->port_clock
;
1181 if (IS_SKYLAKE(dev
))
1182 return skl_ddi_pll_select(intel_crtc
, crtc_state
,
1183 intel_encoder
, clock
);
1185 return hsw_ddi_pll_select(intel_crtc
, crtc_state
,
1186 intel_encoder
, clock
);
1189 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
1191 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1192 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1193 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1194 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1195 int type
= intel_encoder
->type
;
1198 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
|| type
== INTEL_OUTPUT_DP_MST
) {
1199 temp
= TRANS_MSA_SYNC_CLK
;
1200 switch (intel_crtc
->config
->pipe_bpp
) {
1202 temp
|= TRANS_MSA_6_BPC
;
1205 temp
|= TRANS_MSA_8_BPC
;
1208 temp
|= TRANS_MSA_10_BPC
;
1211 temp
|= TRANS_MSA_12_BPC
;
1216 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
1220 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
)
1222 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1223 struct drm_device
*dev
= crtc
->dev
;
1224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1225 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1227 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1229 temp
|= TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1231 temp
&= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC
;
1232 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1235 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
1237 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1238 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1239 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1240 struct drm_device
*dev
= crtc
->dev
;
1241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1242 enum pipe pipe
= intel_crtc
->pipe
;
1243 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1244 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1245 int type
= intel_encoder
->type
;
1248 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1249 temp
= TRANS_DDI_FUNC_ENABLE
;
1250 temp
|= TRANS_DDI_SELECT_PORT(port
);
1252 switch (intel_crtc
->config
->pipe_bpp
) {
1254 temp
|= TRANS_DDI_BPC_6
;
1257 temp
|= TRANS_DDI_BPC_8
;
1260 temp
|= TRANS_DDI_BPC_10
;
1263 temp
|= TRANS_DDI_BPC_12
;
1269 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
1270 temp
|= TRANS_DDI_PVSYNC
;
1271 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
1272 temp
|= TRANS_DDI_PHSYNC
;
1274 if (cpu_transcoder
== TRANSCODER_EDP
) {
1277 /* On Haswell, can only use the always-on power well for
1278 * eDP when not using the panel fitter, and when not
1279 * using motion blur mitigation (which we don't
1281 if (IS_HASWELL(dev
) &&
1282 (intel_crtc
->config
->pch_pfit
.enabled
||
1283 intel_crtc
->config
->pch_pfit
.force_thru
))
1284 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
1286 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
1289 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
1292 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1300 if (type
== INTEL_OUTPUT_HDMI
) {
1301 if (intel_crtc
->config
->has_hdmi_sink
)
1302 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1304 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1306 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1307 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1308 temp
|= (intel_crtc
->config
->fdi_lanes
- 1) << 1;
1310 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1311 type
== INTEL_OUTPUT_EDP
) {
1312 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1314 if (intel_dp
->is_mst
) {
1315 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1317 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1319 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1320 } else if (type
== INTEL_OUTPUT_DP_MST
) {
1321 struct intel_dp
*intel_dp
= &enc_to_mst(encoder
)->primary
->dp
;
1323 if (intel_dp
->is_mst
) {
1324 temp
|= TRANS_DDI_MODE_SELECT_DP_MST
;
1326 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1328 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
1330 WARN(1, "Invalid encoder type %d for pipe %c\n",
1331 intel_encoder
->type
, pipe_name(pipe
));
1334 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1337 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1338 enum transcoder cpu_transcoder
)
1340 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1341 uint32_t val
= I915_READ(reg
);
1343 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
| TRANS_DDI_DP_VC_PAYLOAD_ALLOC
);
1344 val
|= TRANS_DDI_PORT_NONE
;
1345 I915_WRITE(reg
, val
);
1348 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1350 struct drm_device
*dev
= intel_connector
->base
.dev
;
1351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1352 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1353 int type
= intel_connector
->base
.connector_type
;
1354 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1356 enum transcoder cpu_transcoder
;
1357 enum intel_display_power_domain power_domain
;
1360 power_domain
= intel_display_port_power_domain(intel_encoder
);
1361 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1364 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1368 cpu_transcoder
= TRANSCODER_EDP
;
1370 cpu_transcoder
= (enum transcoder
) pipe
;
1372 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1374 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1375 case TRANS_DDI_MODE_SELECT_HDMI
:
1376 case TRANS_DDI_MODE_SELECT_DVI
:
1377 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1379 case TRANS_DDI_MODE_SELECT_DP_SST
:
1380 if (type
== DRM_MODE_CONNECTOR_eDP
)
1382 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1383 case TRANS_DDI_MODE_SELECT_DP_MST
:
1384 /* if the transcoder is in MST state then
1385 * connector isn't connected */
1388 case TRANS_DDI_MODE_SELECT_FDI
:
1389 return (type
== DRM_MODE_CONNECTOR_VGA
);
1396 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1399 struct drm_device
*dev
= encoder
->base
.dev
;
1400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1401 enum port port
= intel_ddi_get_encoder_port(encoder
);
1402 enum intel_display_power_domain power_domain
;
1406 power_domain
= intel_display_port_power_domain(encoder
);
1407 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1410 tmp
= I915_READ(DDI_BUF_CTL(port
));
1412 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1415 if (port
== PORT_A
) {
1416 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1418 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1419 case TRANS_DDI_EDP_INPUT_A_ON
:
1420 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1423 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1426 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1433 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1434 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1436 if ((tmp
& TRANS_DDI_PORT_MASK
)
1437 == TRANS_DDI_SELECT_PORT(port
)) {
1438 if ((tmp
& TRANS_DDI_MODE_SELECT_MASK
) == TRANS_DDI_MODE_SELECT_DP_MST
)
1447 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1452 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1454 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1455 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1456 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1457 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1458 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1460 if (cpu_transcoder
!= TRANSCODER_EDP
)
1461 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1462 TRANS_CLK_SEL_PORT(port
));
1465 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1467 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1468 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
1470 if (cpu_transcoder
!= TRANSCODER_EDP
)
1471 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1472 TRANS_CLK_SEL_DISABLED
);
1475 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1477 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1478 struct drm_device
*dev
= encoder
->dev
;
1479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1480 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->crtc
);
1481 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1482 int type
= intel_encoder
->type
;
1484 if (type
== INTEL_OUTPUT_EDP
) {
1485 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1486 intel_edp_panel_on(intel_dp
);
1489 if (IS_SKYLAKE(dev
)) {
1490 uint32_t dpll
= crtc
->config
->ddi_pll_sel
;
1494 * DPLL0 is used for eDP and is the only "private" DPLL (as
1495 * opposed to shared) on SKL
1497 if (type
== INTEL_OUTPUT_EDP
) {
1498 WARN_ON(dpll
!= SKL_DPLL0
);
1500 val
= I915_READ(DPLL_CTRL1
);
1502 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) |
1503 DPLL_CTRL1_SSC(dpll
) |
1504 DPLL_CRTL1_LINK_RATE_MASK(dpll
));
1505 val
|= crtc
->config
->dpll_hw_state
.ctrl1
<< (dpll
* 6);
1507 I915_WRITE(DPLL_CTRL1
, val
);
1508 POSTING_READ(DPLL_CTRL1
);
1511 /* DDI -> PLL mapping */
1512 val
= I915_READ(DPLL_CTRL2
);
1514 val
&= ~(DPLL_CTRL2_DDI_CLK_OFF(port
) |
1515 DPLL_CTRL2_DDI_CLK_SEL_MASK(port
));
1516 val
|= (DPLL_CTRL2_DDI_CLK_SEL(dpll
, port
) |
1517 DPLL_CTRL2_DDI_SEL_OVERRIDE(port
));
1519 I915_WRITE(DPLL_CTRL2
, val
);
1522 WARN_ON(crtc
->config
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1523 I915_WRITE(PORT_CLK_SEL(port
), crtc
->config
->ddi_pll_sel
);
1526 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1527 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1529 intel_ddi_init_dp_buf_reg(intel_encoder
);
1531 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1532 intel_dp_start_link_train(intel_dp
);
1533 intel_dp_complete_link_train(intel_dp
);
1534 if (port
!= PORT_A
|| INTEL_INFO(dev
)->gen
>= 9)
1535 intel_dp_stop_link_train(intel_dp
);
1536 } else if (type
== INTEL_OUTPUT_HDMI
) {
1537 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1539 intel_hdmi
->set_infoframes(encoder
,
1540 crtc
->config
->has_hdmi_sink
,
1541 &crtc
->config
->base
.adjusted_mode
);
1545 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1547 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1548 struct drm_device
*dev
= encoder
->dev
;
1549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1550 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1551 int type
= intel_encoder
->type
;
1555 val
= I915_READ(DDI_BUF_CTL(port
));
1556 if (val
& DDI_BUF_CTL_ENABLE
) {
1557 val
&= ~DDI_BUF_CTL_ENABLE
;
1558 I915_WRITE(DDI_BUF_CTL(port
), val
);
1562 val
= I915_READ(DP_TP_CTL(port
));
1563 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1564 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1565 I915_WRITE(DP_TP_CTL(port
), val
);
1568 intel_wait_ddi_buf_idle(dev_priv
, port
);
1570 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1571 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1572 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1573 intel_edp_panel_vdd_on(intel_dp
);
1574 intel_edp_panel_off(intel_dp
);
1577 if (IS_SKYLAKE(dev
))
1578 I915_WRITE(DPLL_CTRL2
, (I915_READ(DPLL_CTRL2
) |
1579 DPLL_CTRL2_DDI_CLK_OFF(port
)));
1581 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1584 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1586 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1587 struct drm_crtc
*crtc
= encoder
->crtc
;
1588 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1589 struct drm_device
*dev
= encoder
->dev
;
1590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1591 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1592 int type
= intel_encoder
->type
;
1594 if (type
== INTEL_OUTPUT_HDMI
) {
1595 struct intel_digital_port
*intel_dig_port
=
1596 enc_to_dig_port(encoder
);
1598 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1599 * are ignored so nothing special needs to be done besides
1600 * enabling the port.
1602 I915_WRITE(DDI_BUF_CTL(port
),
1603 intel_dig_port
->saved_port_bits
|
1604 DDI_BUF_CTL_ENABLE
);
1605 } else if (type
== INTEL_OUTPUT_EDP
) {
1606 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1608 if (port
== PORT_A
&& INTEL_INFO(dev
)->gen
< 9)
1609 intel_dp_stop_link_train(intel_dp
);
1611 intel_edp_backlight_on(intel_dp
);
1612 intel_psr_enable(intel_dp
);
1613 intel_edp_drrs_enable(intel_dp
);
1616 if (intel_crtc
->config
->has_audio
) {
1617 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
1618 intel_audio_codec_enable(intel_encoder
);
1622 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1624 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1625 struct drm_crtc
*crtc
= encoder
->crtc
;
1626 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1627 int type
= intel_encoder
->type
;
1628 struct drm_device
*dev
= encoder
->dev
;
1629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1631 if (intel_crtc
->config
->has_audio
) {
1632 intel_audio_codec_disable(intel_encoder
);
1633 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
1636 if (type
== INTEL_OUTPUT_EDP
) {
1637 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1639 intel_edp_drrs_disable(intel_dp
);
1640 intel_psr_disable(intel_dp
);
1641 intel_edp_backlight_off(intel_dp
);
1645 static int skl_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1647 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
1648 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
1651 if (!(lcpll1
& LCPLL_PLL_ENABLE
)) {
1652 WARN(1, "LCPLL1 not enabled\n");
1653 return 24000; /* 24MHz is the cd freq with NSSC ref */
1656 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
1659 linkrate
= (I915_READ(DPLL_CTRL1
) &
1660 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
1662 if (linkrate
== DPLL_CRTL1_LINK_RATE_2160
||
1663 linkrate
== DPLL_CRTL1_LINK_RATE_1080
) {
1665 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
1666 case CDCLK_FREQ_450_432
:
1668 case CDCLK_FREQ_337_308
:
1670 case CDCLK_FREQ_675_617
:
1673 WARN(1, "Unknown cd freq selection\n");
1677 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
1678 case CDCLK_FREQ_450_432
:
1680 case CDCLK_FREQ_337_308
:
1682 case CDCLK_FREQ_675_617
:
1685 WARN(1, "Unknown cd freq selection\n");
1689 /* error case, do as if DPLL0 isn't enabled */
1693 static int bdw_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1695 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
1696 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
1698 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
1700 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1702 else if (freq
== LCPLL_CLK_FREQ_450
)
1704 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
1706 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
1712 static int hsw_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1714 struct drm_device
*dev
= dev_priv
->dev
;
1715 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
1716 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
1718 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
1720 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1722 else if (freq
== LCPLL_CLK_FREQ_450
)
1724 else if (IS_HSW_ULT(dev
))
1730 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1732 struct drm_device
*dev
= dev_priv
->dev
;
1734 if (IS_SKYLAKE(dev
))
1735 return skl_get_cdclk_freq(dev_priv
);
1737 if (IS_BROADWELL(dev
))
1738 return bdw_get_cdclk_freq(dev_priv
);
1741 return hsw_get_cdclk_freq(dev_priv
);
1744 static void hsw_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
1745 struct intel_shared_dpll
*pll
)
1747 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
1748 POSTING_READ(WRPLL_CTL(pll
->id
));
1752 static void hsw_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
1753 struct intel_shared_dpll
*pll
)
1757 val
= I915_READ(WRPLL_CTL(pll
->id
));
1758 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
1759 POSTING_READ(WRPLL_CTL(pll
->id
));
1762 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
1763 struct intel_shared_dpll
*pll
,
1764 struct intel_dpll_hw_state
*hw_state
)
1768 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
1771 val
= I915_READ(WRPLL_CTL(pll
->id
));
1772 hw_state
->wrpll
= val
;
1774 return val
& WRPLL_PLL_ENABLE
;
1777 static const char * const hsw_ddi_pll_names
[] = {
1782 static void hsw_shared_dplls_init(struct drm_i915_private
*dev_priv
)
1786 dev_priv
->num_shared_dpll
= 2;
1788 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
1789 dev_priv
->shared_dplls
[i
].id
= i
;
1790 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
1791 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_pll_disable
;
1792 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_pll_enable
;
1793 dev_priv
->shared_dplls
[i
].get_hw_state
=
1794 hsw_ddi_pll_get_hw_state
;
1798 static const char * const skl_ddi_pll_names
[] = {
1804 struct skl_dpll_regs
{
1805 u32 ctl
, cfgcr1
, cfgcr2
;
1808 /* this array is indexed by the *shared* pll id */
1809 static const struct skl_dpll_regs skl_dpll_regs
[3] = {
1813 .cfgcr1
= DPLL1_CFGCR1
,
1814 .cfgcr2
= DPLL1_CFGCR2
,
1819 .cfgcr1
= DPLL2_CFGCR1
,
1820 .cfgcr2
= DPLL2_CFGCR2
,
1825 .cfgcr1
= DPLL3_CFGCR1
,
1826 .cfgcr2
= DPLL3_CFGCR2
,
1830 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
1831 struct intel_shared_dpll
*pll
)
1835 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
1837 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1840 val
= I915_READ(DPLL_CTRL1
);
1842 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) | DPLL_CTRL1_SSC(dpll
) |
1843 DPLL_CRTL1_LINK_RATE_MASK(dpll
));
1844 val
|= pll
->config
.hw_state
.ctrl1
<< (dpll
* 6);
1846 I915_WRITE(DPLL_CTRL1
, val
);
1847 POSTING_READ(DPLL_CTRL1
);
1849 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
1850 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
1851 POSTING_READ(regs
[pll
->id
].cfgcr1
);
1852 POSTING_READ(regs
[pll
->id
].cfgcr2
);
1854 /* the enable bit is always bit 31 */
1855 I915_WRITE(regs
[pll
->id
].ctl
,
1856 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
1858 if (wait_for(I915_READ(DPLL_STATUS
) & DPLL_LOCK(dpll
), 5))
1859 DRM_ERROR("DPLL %d not locked\n", dpll
);
1862 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
1863 struct intel_shared_dpll
*pll
)
1865 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
1867 /* the enable bit is always bit 31 */
1868 I915_WRITE(regs
[pll
->id
].ctl
,
1869 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
1870 POSTING_READ(regs
[pll
->id
].ctl
);
1873 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
1874 struct intel_shared_dpll
*pll
,
1875 struct intel_dpll_hw_state
*hw_state
)
1879 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
1881 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
1884 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1887 val
= I915_READ(regs
[pll
->id
].ctl
);
1888 if (!(val
& LCPLL_PLL_ENABLE
))
1891 val
= I915_READ(DPLL_CTRL1
);
1892 hw_state
->ctrl1
= (val
>> (dpll
* 6)) & 0x3f;
1894 /* avoid reading back stale values if HDMI mode is not enabled */
1895 if (val
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
1896 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
1897 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
1903 static void skl_shared_dplls_init(struct drm_i915_private
*dev_priv
)
1907 dev_priv
->num_shared_dpll
= 3;
1909 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
1910 dev_priv
->shared_dplls
[i
].id
= i
;
1911 dev_priv
->shared_dplls
[i
].name
= skl_ddi_pll_names
[i
];
1912 dev_priv
->shared_dplls
[i
].disable
= skl_ddi_pll_disable
;
1913 dev_priv
->shared_dplls
[i
].enable
= skl_ddi_pll_enable
;
1914 dev_priv
->shared_dplls
[i
].get_hw_state
=
1915 skl_ddi_pll_get_hw_state
;
1919 void intel_ddi_pll_init(struct drm_device
*dev
)
1921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1922 uint32_t val
= I915_READ(LCPLL_CTL
);
1924 if (IS_SKYLAKE(dev
))
1925 skl_shared_dplls_init(dev_priv
);
1927 hsw_shared_dplls_init(dev_priv
);
1929 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1930 intel_ddi_get_cdclk_freq(dev_priv
));
1932 if (IS_SKYLAKE(dev
)) {
1933 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
))
1934 DRM_ERROR("LCPLL1 is disabled\n");
1937 * The LCPLL register should be turned on by the BIOS. For now
1938 * let's just check its state and print errors in case
1939 * something is wrong. Don't even try to turn it on.
1942 if (val
& LCPLL_CD_SOURCE_FCLK
)
1943 DRM_ERROR("CDCLK source is not LCPLL\n");
1945 if (val
& LCPLL_PLL_DISABLE
)
1946 DRM_ERROR("LCPLL is disabled\n");
1950 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1952 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1953 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1954 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1955 enum port port
= intel_dig_port
->port
;
1959 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1960 val
= I915_READ(DDI_BUF_CTL(port
));
1961 if (val
& DDI_BUF_CTL_ENABLE
) {
1962 val
&= ~DDI_BUF_CTL_ENABLE
;
1963 I915_WRITE(DDI_BUF_CTL(port
), val
);
1967 val
= I915_READ(DP_TP_CTL(port
));
1968 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1969 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1970 I915_WRITE(DP_TP_CTL(port
), val
);
1971 POSTING_READ(DP_TP_CTL(port
));
1974 intel_wait_ddi_buf_idle(dev_priv
, port
);
1977 val
= DP_TP_CTL_ENABLE
|
1978 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1979 if (intel_dp
->is_mst
)
1980 val
|= DP_TP_CTL_MODE_MST
;
1982 val
|= DP_TP_CTL_MODE_SST
;
1983 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1984 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1986 I915_WRITE(DP_TP_CTL(port
), val
);
1987 POSTING_READ(DP_TP_CTL(port
));
1989 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1990 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1991 POSTING_READ(DDI_BUF_CTL(port
));
1996 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1998 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1999 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
2002 intel_ddi_post_disable(intel_encoder
);
2004 val
= I915_READ(_FDI_RXA_CTL
);
2005 val
&= ~FDI_RX_ENABLE
;
2006 I915_WRITE(_FDI_RXA_CTL
, val
);
2008 val
= I915_READ(_FDI_RXA_MISC
);
2009 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
2010 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2011 I915_WRITE(_FDI_RXA_MISC
, val
);
2013 val
= I915_READ(_FDI_RXA_CTL
);
2015 I915_WRITE(_FDI_RXA_CTL
, val
);
2017 val
= I915_READ(_FDI_RXA_CTL
);
2018 val
&= ~FDI_RX_PLL_ENABLE
;
2019 I915_WRITE(_FDI_RXA_CTL
, val
);
2022 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
2024 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
2025 int type
= intel_dig_port
->base
.type
;
2027 if (type
!= INTEL_OUTPUT_DISPLAYPORT
&&
2028 type
!= INTEL_OUTPUT_EDP
&&
2029 type
!= INTEL_OUTPUT_UNKNOWN
) {
2033 intel_dp_hot_plug(intel_encoder
);
2036 void intel_ddi_get_config(struct intel_encoder
*encoder
,
2037 struct intel_crtc_state
*pipe_config
)
2039 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
2040 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2041 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
2042 struct intel_hdmi
*intel_hdmi
;
2043 u32 temp
, flags
= 0;
2045 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
2046 if (temp
& TRANS_DDI_PHSYNC
)
2047 flags
|= DRM_MODE_FLAG_PHSYNC
;
2049 flags
|= DRM_MODE_FLAG_NHSYNC
;
2050 if (temp
& TRANS_DDI_PVSYNC
)
2051 flags
|= DRM_MODE_FLAG_PVSYNC
;
2053 flags
|= DRM_MODE_FLAG_NVSYNC
;
2055 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2057 switch (temp
& TRANS_DDI_BPC_MASK
) {
2058 case TRANS_DDI_BPC_6
:
2059 pipe_config
->pipe_bpp
= 18;
2061 case TRANS_DDI_BPC_8
:
2062 pipe_config
->pipe_bpp
= 24;
2064 case TRANS_DDI_BPC_10
:
2065 pipe_config
->pipe_bpp
= 30;
2067 case TRANS_DDI_BPC_12
:
2068 pipe_config
->pipe_bpp
= 36;
2074 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
2075 case TRANS_DDI_MODE_SELECT_HDMI
:
2076 pipe_config
->has_hdmi_sink
= true;
2077 intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
2079 if (intel_hdmi
->infoframe_enabled(&encoder
->base
))
2080 pipe_config
->has_infoframe
= true;
2082 case TRANS_DDI_MODE_SELECT_DVI
:
2083 case TRANS_DDI_MODE_SELECT_FDI
:
2085 case TRANS_DDI_MODE_SELECT_DP_SST
:
2086 case TRANS_DDI_MODE_SELECT_DP_MST
:
2087 pipe_config
->has_dp_encoder
= true;
2088 intel_dp_get_m_n(intel_crtc
, pipe_config
);
2094 if (intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_AUDIO
)) {
2095 temp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
2096 if (temp
& AUDIO_OUTPUT_ENABLE(intel_crtc
->pipe
))
2097 pipe_config
->has_audio
= true;
2100 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
2101 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2103 * This is a big fat ugly hack.
2105 * Some machines in UEFI boot mode provide us a VBT that has 18
2106 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2107 * unknown we fail to light up. Yet the same BIOS boots up with
2108 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2109 * max, not what it tells us to use.
2111 * Note: This will still be broken if the eDP panel is not lit
2112 * up by the BIOS, and thus we can't get the mode at module
2115 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2116 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2117 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2120 intel_ddi_clock_get(encoder
, pipe_config
);
2123 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
2125 /* HDMI has nothing special to destroy, so we can go with this. */
2126 intel_dp_encoder_destroy(encoder
);
2129 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
2130 struct intel_crtc_state
*pipe_config
)
2132 int type
= encoder
->type
;
2133 int port
= intel_ddi_get_encoder_port(encoder
);
2135 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
2138 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
2140 if (type
== INTEL_OUTPUT_HDMI
)
2141 return intel_hdmi_compute_config(encoder
, pipe_config
);
2143 return intel_dp_compute_config(encoder
, pipe_config
);
2146 static const struct drm_encoder_funcs intel_ddi_funcs
= {
2147 .destroy
= intel_ddi_destroy
,
2150 static struct intel_connector
*
2151 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
2153 struct intel_connector
*connector
;
2154 enum port port
= intel_dig_port
->port
;
2156 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
2160 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
2161 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
2169 static struct intel_connector
*
2170 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
2172 struct intel_connector
*connector
;
2173 enum port port
= intel_dig_port
->port
;
2175 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
2179 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
2180 intel_hdmi_init_connector(intel_dig_port
, connector
);
2185 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
2187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2188 struct intel_digital_port
*intel_dig_port
;
2189 struct intel_encoder
*intel_encoder
;
2190 struct drm_encoder
*encoder
;
2191 bool init_hdmi
, init_dp
;
2193 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
2194 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
2195 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
2196 if (!init_dp
&& !init_hdmi
) {
2197 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2203 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
2204 if (!intel_dig_port
)
2207 intel_encoder
= &intel_dig_port
->base
;
2208 encoder
= &intel_encoder
->base
;
2210 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
2211 DRM_MODE_ENCODER_TMDS
);
2213 intel_encoder
->compute_config
= intel_ddi_compute_config
;
2214 intel_encoder
->enable
= intel_enable_ddi
;
2215 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
2216 intel_encoder
->disable
= intel_disable_ddi
;
2217 intel_encoder
->post_disable
= intel_ddi_post_disable
;
2218 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
2219 intel_encoder
->get_config
= intel_ddi_get_config
;
2221 intel_dig_port
->port
= port
;
2222 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
2223 (DDI_BUF_PORT_REVERSAL
|
2226 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
2227 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2228 intel_encoder
->cloneable
= 0;
2229 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
2232 if (!intel_ddi_init_dp_connector(intel_dig_port
))
2235 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
2236 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
2239 /* In theory we don't need the encoder->type check, but leave it just in
2240 * case we have some really bad VBTs... */
2241 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
) {
2242 if (!intel_ddi_init_hdmi_connector(intel_dig_port
))
2249 drm_encoder_cleanup(encoder
);
2250 kfree(intel_dig_port
);