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drm/i915/cnl: Change the macro name to DPLL_CFGCR0_DCO_FRACTION_SHIFT
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
35 };
36
37 static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48 };
49
50 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
54 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
64 };
65
66 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
76 };
77
78 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
92 };
93
94 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
104 };
105
106 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
116 };
117
118 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
128 };
129
130 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
142 };
143
144 /* Skylake H and S */
145 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x000000DF, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
155 };
156
157 /* Skylake U */
158 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
159 { 0x0000201B, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x1 },
162 { 0x80009010, 0x000000C0, 0x1 },
163 { 0x0000201B, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
166 { 0x00002016, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x1 },
168 };
169
170 /* Skylake Y */
171 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
174 { 0x80007011, 0x000000CD, 0x3 },
175 { 0x80009010, 0x000000C0, 0x3 },
176 { 0x00000018, 0x0000009D, 0x0 },
177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
179 { 0x00000018, 0x00000088, 0x0 },
180 { 0x80005012, 0x000000C0, 0x3 },
181 };
182
183 /* Kabylake H and S */
184 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194 };
195
196 /* Kabylake U */
197 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207 };
208
209 /* Kabylake Y */
210 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220 };
221
222 /*
223 * Skylake/Kabylake H and S
224 * eDP 1.4 low vswing translation parameters
225 */
226 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
237 };
238
239 /*
240 * Skylake/Kabylake U
241 * eDP 1.4 low vswing translation parameters
242 */
243 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
254 };
255
256 /*
257 * Skylake/Kabylake Y
258 * eDP 1.4 low vswing translation parameters
259 */
260 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271 };
272
273 /* Skylake/Kabylake U, H and S */
274 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
281 { 0x80006012, 0x000000CD, 0x1 },
282 { 0x00000018, 0x000000DF, 0x0 },
283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
286 };
287
288 /* Skylake/Kabylake Y */
289 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
292 { 0x80007011, 0x000000CB, 0x3 },
293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
296 { 0x80006013, 0x000000C0, 0x3 },
297 { 0x00000018, 0x0000008A, 0x0 },
298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
301 };
302
303 struct bxt_ddi_buf_trans {
304 u32 margin; /* swing value */
305 u32 scale; /* scale value */
306 u32 enable; /* scale enable */
307 u32 deemphasis;
308 bool default_index; /* true if the entry represents default value */
309 };
310
311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
313 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
322 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
323 };
324
325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, false }, /* 0: 200 0 */
328 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, false }, /* 2: 200 4 */
330 { 54, 0, 0, 69, false }, /* 3: 200 6 */
331 { 32, 0, 0, 128, false }, /* 4: 250 0 */
332 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, false }, /* 6: 250 4 */
334 { 43, 0, 0, 128, false }, /* 7: 300 0 */
335 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, false }, /* 9: 300 0 */
337 };
338
339 /* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
341 */
342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
344 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
353 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
354 };
355
356 struct cnl_ddi_buf_trans {
357 u32 dw2_swing_sel;
358 u32 dw7_n_scalar;
359 u32 dw4_cursor_coeff;
360 u32 dw4_post_cursor_2;
361 u32 dw4_post_cursor_1;
362 };
363
364 /* Voltage Swing Programming for VccIO 0.85V for DP */
365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
377 };
378
379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
389 };
390
391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
403 };
404
405 /* Voltage Swing Programming for VccIO 0.95V for DP */
406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
418 };
419
420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
434 };
435
436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
449 };
450
451 /* Voltage Swing Programming for VccIO 1.05V for DP */
452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
464 };
465
466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
480 };
481
482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
494 };
495
496 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
497 {
498 switch (encoder->type) {
499 case INTEL_OUTPUT_DP_MST:
500 return enc_to_mst(&encoder->base)->primary->port;
501 case INTEL_OUTPUT_DP:
502 case INTEL_OUTPUT_EDP:
503 case INTEL_OUTPUT_HDMI:
504 case INTEL_OUTPUT_UNKNOWN:
505 return enc_to_dig_port(&encoder->base)->port;
506 case INTEL_OUTPUT_ANALOG:
507 return PORT_E;
508 default:
509 MISSING_CASE(encoder->type);
510 return PORT_A;
511 }
512 }
513
514 static const struct ddi_buf_trans *
515 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
516 {
517 if (dev_priv->vbt.edp.low_vswing) {
518 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
519 return bdw_ddi_translations_edp;
520 } else {
521 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
522 return bdw_ddi_translations_dp;
523 }
524 }
525
526 static const struct ddi_buf_trans *
527 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
528 {
529 if (IS_SKL_ULX(dev_priv)) {
530 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
531 return skl_y_ddi_translations_dp;
532 } else if (IS_SKL_ULT(dev_priv)) {
533 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
534 return skl_u_ddi_translations_dp;
535 } else {
536 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
537 return skl_ddi_translations_dp;
538 }
539 }
540
541 static const struct ddi_buf_trans *
542 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
543 {
544 if (IS_KBL_ULX(dev_priv)) {
545 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
546 return kbl_y_ddi_translations_dp;
547 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
548 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
549 return kbl_u_ddi_translations_dp;
550 } else {
551 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
552 return kbl_ddi_translations_dp;
553 }
554 }
555
556 static const struct ddi_buf_trans *
557 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
558 {
559 if (dev_priv->vbt.edp.low_vswing) {
560 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
561 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
562 return skl_y_ddi_translations_edp;
563 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
564 IS_CFL_ULT(dev_priv)) {
565 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
566 return skl_u_ddi_translations_edp;
567 } else {
568 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
569 return skl_ddi_translations_edp;
570 }
571 }
572
573 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
574 return kbl_get_buf_trans_dp(dev_priv, n_entries);
575 else
576 return skl_get_buf_trans_dp(dev_priv, n_entries);
577 }
578
579 static const struct ddi_buf_trans *
580 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
581 {
582 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
583 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
584 return skl_y_ddi_translations_hdmi;
585 } else {
586 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
587 return skl_ddi_translations_hdmi;
588 }
589 }
590
591 static const struct cnl_ddi_buf_trans *
592 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
593 {
594 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
595
596 if (voltage == VOLTAGE_INFO_0_85V) {
597 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
598 return cnl_ddi_translations_hdmi_0_85V;
599 } else if (voltage == VOLTAGE_INFO_0_95V) {
600 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
601 return cnl_ddi_translations_hdmi_0_95V;
602 } else if (voltage == VOLTAGE_INFO_1_05V) {
603 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
604 return cnl_ddi_translations_hdmi_1_05V;
605 } else
606 MISSING_CASE(voltage);
607 return NULL;
608 }
609
610 static const struct cnl_ddi_buf_trans *
611 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
612 {
613 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
614
615 if (voltage == VOLTAGE_INFO_0_85V) {
616 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
617 return cnl_ddi_translations_dp_0_85V;
618 } else if (voltage == VOLTAGE_INFO_0_95V) {
619 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
620 return cnl_ddi_translations_dp_0_95V;
621 } else if (voltage == VOLTAGE_INFO_1_05V) {
622 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
623 return cnl_ddi_translations_dp_1_05V;
624 } else
625 MISSING_CASE(voltage);
626 return NULL;
627 }
628
629 static const struct cnl_ddi_buf_trans *
630 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
631 {
632 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
633
634 if (dev_priv->vbt.edp.low_vswing) {
635 if (voltage == VOLTAGE_INFO_0_85V) {
636 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
637 return cnl_ddi_translations_edp_0_85V;
638 } else if (voltage == VOLTAGE_INFO_0_95V) {
639 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
640 return cnl_ddi_translations_edp_0_95V;
641 } else if (voltage == VOLTAGE_INFO_1_05V) {
642 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
643 return cnl_ddi_translations_edp_1_05V;
644 } else
645 MISSING_CASE(voltage);
646 return NULL;
647 } else {
648 return cnl_get_buf_trans_dp(dev_priv, n_entries);
649 }
650 }
651
652 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
653 {
654 int n_hdmi_entries;
655 int hdmi_level;
656 int hdmi_default_entry;
657
658 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
659
660 if (IS_GEN9_LP(dev_priv))
661 return hdmi_level;
662
663 if (IS_CANNONLAKE(dev_priv)) {
664 cnl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
665 hdmi_default_entry = n_hdmi_entries - 1;
666 } else if (IS_GEN9_BC(dev_priv)) {
667 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
668 hdmi_default_entry = 8;
669 } else if (IS_BROADWELL(dev_priv)) {
670 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
671 hdmi_default_entry = 7;
672 } else if (IS_HASWELL(dev_priv)) {
673 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
674 hdmi_default_entry = 6;
675 } else {
676 WARN(1, "ddi translation table missing\n");
677 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
678 hdmi_default_entry = 7;
679 }
680
681 /* Choose a good default if VBT is badly populated */
682 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
683 hdmi_level >= n_hdmi_entries)
684 hdmi_level = hdmi_default_entry;
685
686 return hdmi_level;
687 }
688
689 static const struct ddi_buf_trans *
690 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
691 int *n_entries)
692 {
693 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
694 return kbl_get_buf_trans_dp(dev_priv, n_entries);
695 } else if (IS_SKYLAKE(dev_priv)) {
696 return skl_get_buf_trans_dp(dev_priv, n_entries);
697 } else if (IS_BROADWELL(dev_priv)) {
698 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
699 return bdw_ddi_translations_dp;
700 } else if (IS_HASWELL(dev_priv)) {
701 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
702 return hsw_ddi_translations_dp;
703 }
704
705 *n_entries = 0;
706 return NULL;
707 }
708
709 static const struct ddi_buf_trans *
710 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
711 int *n_entries)
712 {
713 if (IS_GEN9_BC(dev_priv)) {
714 return skl_get_buf_trans_edp(dev_priv, n_entries);
715 } else if (IS_BROADWELL(dev_priv)) {
716 return bdw_get_buf_trans_edp(dev_priv, n_entries);
717 } else if (IS_HASWELL(dev_priv)) {
718 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
719 return hsw_ddi_translations_dp;
720 }
721
722 *n_entries = 0;
723 return NULL;
724 }
725
726 static const struct ddi_buf_trans *
727 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
728 int *n_entries)
729 {
730 if (IS_BROADWELL(dev_priv)) {
731 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
732 return hsw_ddi_translations_fdi;
733 } else if (IS_HASWELL(dev_priv)) {
734 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
735 return hsw_ddi_translations_fdi;
736 }
737
738 *n_entries = 0;
739 return NULL;
740 }
741
742 /*
743 * Starting with Haswell, DDI port buffers must be programmed with correct
744 * values in advance. This function programs the correct values for
745 * DP/eDP/FDI use cases.
746 */
747 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
748 {
749 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
750 u32 iboost_bit = 0;
751 int i, n_entries;
752 enum port port = intel_ddi_get_encoder_port(encoder);
753 const struct ddi_buf_trans *ddi_translations;
754
755 switch (encoder->type) {
756 case INTEL_OUTPUT_EDP:
757 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
758 &n_entries);
759 break;
760 case INTEL_OUTPUT_DP:
761 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
762 &n_entries);
763 break;
764 case INTEL_OUTPUT_ANALOG:
765 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
766 &n_entries);
767 break;
768 default:
769 MISSING_CASE(encoder->type);
770 return;
771 }
772
773 if (IS_GEN9_BC(dev_priv)) {
774 /* If we're boosting the current, set bit 31 of trans1 */
775 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
776 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
777
778 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
779 port != PORT_A && port != PORT_E &&
780 n_entries > 9))
781 n_entries = 9;
782 }
783
784 for (i = 0; i < n_entries; i++) {
785 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
786 ddi_translations[i].trans1 | iboost_bit);
787 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
788 ddi_translations[i].trans2);
789 }
790 }
791
792 /*
793 * Starting with Haswell, DDI port buffers must be programmed with correct
794 * values in advance. This function programs the correct values for
795 * HDMI/DVI use cases.
796 */
797 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
798 {
799 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
800 u32 iboost_bit = 0;
801 int n_hdmi_entries, hdmi_level;
802 enum port port = intel_ddi_get_encoder_port(encoder);
803 const struct ddi_buf_trans *ddi_translations_hdmi;
804
805 hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
806
807 if (IS_GEN9_BC(dev_priv)) {
808 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
809
810 /* If we're boosting the current, set bit 31 of trans1 */
811 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
812 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
813 } else if (IS_BROADWELL(dev_priv)) {
814 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
815 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
816 } else if (IS_HASWELL(dev_priv)) {
817 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
818 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
819 } else {
820 WARN(1, "ddi translation table missing\n");
821 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
822 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
823 }
824
825 /* Entry 9 is for HDMI: */
826 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
827 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
828 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
829 ddi_translations_hdmi[hdmi_level].trans2);
830 }
831
832 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
833 enum port port)
834 {
835 i915_reg_t reg = DDI_BUF_CTL(port);
836 int i;
837
838 for (i = 0; i < 16; i++) {
839 udelay(1);
840 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
841 return;
842 }
843 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
844 }
845
846 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
847 {
848 switch (pll->id) {
849 case DPLL_ID_WRPLL1:
850 return PORT_CLK_SEL_WRPLL1;
851 case DPLL_ID_WRPLL2:
852 return PORT_CLK_SEL_WRPLL2;
853 case DPLL_ID_SPLL:
854 return PORT_CLK_SEL_SPLL;
855 case DPLL_ID_LCPLL_810:
856 return PORT_CLK_SEL_LCPLL_810;
857 case DPLL_ID_LCPLL_1350:
858 return PORT_CLK_SEL_LCPLL_1350;
859 case DPLL_ID_LCPLL_2700:
860 return PORT_CLK_SEL_LCPLL_2700;
861 default:
862 MISSING_CASE(pll->id);
863 return PORT_CLK_SEL_NONE;
864 }
865 }
866
867 /* Starting with Haswell, different DDI ports can work in FDI mode for
868 * connection to the PCH-located connectors. For this, it is necessary to train
869 * both the DDI port and PCH receiver for the desired DDI buffer settings.
870 *
871 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
872 * please note that when FDI mode is active on DDI E, it shares 2 lines with
873 * DDI A (which is used for eDP)
874 */
875
876 void hsw_fdi_link_train(struct intel_crtc *crtc,
877 const struct intel_crtc_state *crtc_state)
878 {
879 struct drm_device *dev = crtc->base.dev;
880 struct drm_i915_private *dev_priv = to_i915(dev);
881 struct intel_encoder *encoder;
882 u32 temp, i, rx_ctl_val, ddi_pll_sel;
883
884 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
885 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
886 intel_prepare_dp_ddi_buffers(encoder);
887 }
888
889 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
890 * mode set "sequence for CRT port" document:
891 * - TP1 to TP2 time with the default value
892 * - FDI delay to 90h
893 *
894 * WaFDIAutoLinkSetTimingOverrride:hsw
895 */
896 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
897 FDI_RX_PWRDN_LANE0_VAL(2) |
898 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
899
900 /* Enable the PCH Receiver FDI PLL */
901 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
902 FDI_RX_PLL_ENABLE |
903 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
904 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
905 POSTING_READ(FDI_RX_CTL(PIPE_A));
906 udelay(220);
907
908 /* Switch from Rawclk to PCDclk */
909 rx_ctl_val |= FDI_PCDCLK;
910 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
911
912 /* Configure Port Clock Select */
913 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
914 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
915 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
916
917 /* Start the training iterating through available voltages and emphasis,
918 * testing each value twice. */
919 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
920 /* Configure DP_TP_CTL with auto-training */
921 I915_WRITE(DP_TP_CTL(PORT_E),
922 DP_TP_CTL_FDI_AUTOTRAIN |
923 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
924 DP_TP_CTL_LINK_TRAIN_PAT1 |
925 DP_TP_CTL_ENABLE);
926
927 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
928 * DDI E does not support port reversal, the functionality is
929 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
930 * port reversal bit */
931 I915_WRITE(DDI_BUF_CTL(PORT_E),
932 DDI_BUF_CTL_ENABLE |
933 ((crtc_state->fdi_lanes - 1) << 1) |
934 DDI_BUF_TRANS_SELECT(i / 2));
935 POSTING_READ(DDI_BUF_CTL(PORT_E));
936
937 udelay(600);
938
939 /* Program PCH FDI Receiver TU */
940 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
941
942 /* Enable PCH FDI Receiver with auto-training */
943 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
944 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
945 POSTING_READ(FDI_RX_CTL(PIPE_A));
946
947 /* Wait for FDI receiver lane calibration */
948 udelay(30);
949
950 /* Unset FDI_RX_MISC pwrdn lanes */
951 temp = I915_READ(FDI_RX_MISC(PIPE_A));
952 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
953 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
954 POSTING_READ(FDI_RX_MISC(PIPE_A));
955
956 /* Wait for FDI auto training time */
957 udelay(5);
958
959 temp = I915_READ(DP_TP_STATUS(PORT_E));
960 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
961 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
962 break;
963 }
964
965 /*
966 * Leave things enabled even if we failed to train FDI.
967 * Results in less fireworks from the state checker.
968 */
969 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
970 DRM_ERROR("FDI link training failed!\n");
971 break;
972 }
973
974 rx_ctl_val &= ~FDI_RX_ENABLE;
975 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
976 POSTING_READ(FDI_RX_CTL(PIPE_A));
977
978 temp = I915_READ(DDI_BUF_CTL(PORT_E));
979 temp &= ~DDI_BUF_CTL_ENABLE;
980 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
981 POSTING_READ(DDI_BUF_CTL(PORT_E));
982
983 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
984 temp = I915_READ(DP_TP_CTL(PORT_E));
985 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
986 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
987 I915_WRITE(DP_TP_CTL(PORT_E), temp);
988 POSTING_READ(DP_TP_CTL(PORT_E));
989
990 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
991
992 /* Reset FDI_RX_MISC pwrdn lanes */
993 temp = I915_READ(FDI_RX_MISC(PIPE_A));
994 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
995 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
996 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
997 POSTING_READ(FDI_RX_MISC(PIPE_A));
998 }
999
1000 /* Enable normal pixel sending for FDI */
1001 I915_WRITE(DP_TP_CTL(PORT_E),
1002 DP_TP_CTL_FDI_AUTOTRAIN |
1003 DP_TP_CTL_LINK_TRAIN_NORMAL |
1004 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1005 DP_TP_CTL_ENABLE);
1006 }
1007
1008 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1009 {
1010 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1011 struct intel_digital_port *intel_dig_port =
1012 enc_to_dig_port(&encoder->base);
1013
1014 intel_dp->DP = intel_dig_port->saved_port_bits |
1015 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1016 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1017 }
1018
1019 static struct intel_encoder *
1020 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1021 {
1022 struct drm_device *dev = crtc->base.dev;
1023 struct intel_encoder *encoder, *ret = NULL;
1024 int num_encoders = 0;
1025
1026 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1027 ret = encoder;
1028 num_encoders++;
1029 }
1030
1031 if (num_encoders != 1)
1032 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1033 pipe_name(crtc->pipe));
1034
1035 BUG_ON(ret == NULL);
1036 return ret;
1037 }
1038
1039 /* Finds the only possible encoder associated with the given CRTC. */
1040 struct intel_encoder *
1041 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
1042 {
1043 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1044 struct intel_encoder *ret = NULL;
1045 struct drm_atomic_state *state;
1046 struct drm_connector *connector;
1047 struct drm_connector_state *connector_state;
1048 int num_encoders = 0;
1049 int i;
1050
1051 state = crtc_state->base.state;
1052
1053 for_each_new_connector_in_state(state, connector, connector_state, i) {
1054 if (connector_state->crtc != crtc_state->base.crtc)
1055 continue;
1056
1057 ret = to_intel_encoder(connector_state->best_encoder);
1058 num_encoders++;
1059 }
1060
1061 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1062 pipe_name(crtc->pipe));
1063
1064 BUG_ON(ret == NULL);
1065 return ret;
1066 }
1067
1068 #define LC_FREQ 2700
1069
1070 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1071 i915_reg_t reg)
1072 {
1073 int refclk = LC_FREQ;
1074 int n, p, r;
1075 u32 wrpll;
1076
1077 wrpll = I915_READ(reg);
1078 switch (wrpll & WRPLL_PLL_REF_MASK) {
1079 case WRPLL_PLL_SSC:
1080 case WRPLL_PLL_NON_SSC:
1081 /*
1082 * We could calculate spread here, but our checking
1083 * code only cares about 5% accuracy, and spread is a max of
1084 * 0.5% downspread.
1085 */
1086 refclk = 135;
1087 break;
1088 case WRPLL_PLL_LCPLL:
1089 refclk = LC_FREQ;
1090 break;
1091 default:
1092 WARN(1, "bad wrpll refclk\n");
1093 return 0;
1094 }
1095
1096 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1097 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1098 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1099
1100 /* Convert to KHz, p & r have a fixed point portion */
1101 return (refclk * n * 100) / (p * r);
1102 }
1103
1104 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1105 uint32_t dpll)
1106 {
1107 i915_reg_t cfgcr1_reg, cfgcr2_reg;
1108 uint32_t cfgcr1_val, cfgcr2_val;
1109 uint32_t p0, p1, p2, dco_freq;
1110
1111 cfgcr1_reg = DPLL_CFGCR1(dpll);
1112 cfgcr2_reg = DPLL_CFGCR2(dpll);
1113
1114 cfgcr1_val = I915_READ(cfgcr1_reg);
1115 cfgcr2_val = I915_READ(cfgcr2_reg);
1116
1117 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1118 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1119
1120 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1121 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1122 else
1123 p1 = 1;
1124
1125
1126 switch (p0) {
1127 case DPLL_CFGCR2_PDIV_1:
1128 p0 = 1;
1129 break;
1130 case DPLL_CFGCR2_PDIV_2:
1131 p0 = 2;
1132 break;
1133 case DPLL_CFGCR2_PDIV_3:
1134 p0 = 3;
1135 break;
1136 case DPLL_CFGCR2_PDIV_7:
1137 p0 = 7;
1138 break;
1139 }
1140
1141 switch (p2) {
1142 case DPLL_CFGCR2_KDIV_5:
1143 p2 = 5;
1144 break;
1145 case DPLL_CFGCR2_KDIV_2:
1146 p2 = 2;
1147 break;
1148 case DPLL_CFGCR2_KDIV_3:
1149 p2 = 3;
1150 break;
1151 case DPLL_CFGCR2_KDIV_1:
1152 p2 = 1;
1153 break;
1154 }
1155
1156 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1157
1158 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1159 1000) / 0x8000;
1160
1161 return dco_freq / (p0 * p1 * p2 * 5);
1162 }
1163
1164 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1165 uint32_t pll_id)
1166 {
1167 uint32_t cfgcr0, cfgcr1;
1168 uint32_t p0, p1, p2, dco_freq, ref_clock;
1169
1170 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1171 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1172
1173 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1174 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1175
1176 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1177 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1178 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1179 else
1180 p1 = 1;
1181
1182
1183 switch (p0) {
1184 case DPLL_CFGCR1_PDIV_2:
1185 p0 = 2;
1186 break;
1187 case DPLL_CFGCR1_PDIV_3:
1188 p0 = 3;
1189 break;
1190 case DPLL_CFGCR1_PDIV_5:
1191 p0 = 5;
1192 break;
1193 case DPLL_CFGCR1_PDIV_7:
1194 p0 = 7;
1195 break;
1196 }
1197
1198 switch (p2) {
1199 case DPLL_CFGCR1_KDIV_1:
1200 p2 = 1;
1201 break;
1202 case DPLL_CFGCR1_KDIV_2:
1203 p2 = 2;
1204 break;
1205 case DPLL_CFGCR1_KDIV_4:
1206 p2 = 4;
1207 break;
1208 }
1209
1210 ref_clock = dev_priv->cdclk.hw.ref;
1211
1212 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1213
1214 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1215 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1216
1217 return dco_freq / (p0 * p1 * p2 * 5);
1218 }
1219
1220 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1221 {
1222 int dotclock;
1223
1224 if (pipe_config->has_pch_encoder)
1225 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1226 &pipe_config->fdi_m_n);
1227 else if (intel_crtc_has_dp_encoder(pipe_config))
1228 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1229 &pipe_config->dp_m_n);
1230 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1231 dotclock = pipe_config->port_clock * 2 / 3;
1232 else
1233 dotclock = pipe_config->port_clock;
1234
1235 if (pipe_config->ycbcr420)
1236 dotclock *= 2;
1237
1238 if (pipe_config->pixel_multiplier)
1239 dotclock /= pipe_config->pixel_multiplier;
1240
1241 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1242 }
1243
1244 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1245 struct intel_crtc_state *pipe_config)
1246 {
1247 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1248 int link_clock = 0;
1249 uint32_t cfgcr0, pll_id;
1250
1251 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1252
1253 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1254
1255 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1256 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1257 } else {
1258 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1259
1260 switch (link_clock) {
1261 case DPLL_CFGCR0_LINK_RATE_810:
1262 link_clock = 81000;
1263 break;
1264 case DPLL_CFGCR0_LINK_RATE_1080:
1265 link_clock = 108000;
1266 break;
1267 case DPLL_CFGCR0_LINK_RATE_1350:
1268 link_clock = 135000;
1269 break;
1270 case DPLL_CFGCR0_LINK_RATE_1620:
1271 link_clock = 162000;
1272 break;
1273 case DPLL_CFGCR0_LINK_RATE_2160:
1274 link_clock = 216000;
1275 break;
1276 case DPLL_CFGCR0_LINK_RATE_2700:
1277 link_clock = 270000;
1278 break;
1279 case DPLL_CFGCR0_LINK_RATE_3240:
1280 link_clock = 324000;
1281 break;
1282 case DPLL_CFGCR0_LINK_RATE_4050:
1283 link_clock = 405000;
1284 break;
1285 default:
1286 WARN(1, "Unsupported link rate\n");
1287 break;
1288 }
1289 link_clock *= 2;
1290 }
1291
1292 pipe_config->port_clock = link_clock;
1293
1294 ddi_dotclock_get(pipe_config);
1295 }
1296
1297 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1298 struct intel_crtc_state *pipe_config)
1299 {
1300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1301 int link_clock = 0;
1302 uint32_t dpll_ctl1, dpll;
1303
1304 dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1305
1306 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1307
1308 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1309 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1310 } else {
1311 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1312 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1313
1314 switch (link_clock) {
1315 case DPLL_CTRL1_LINK_RATE_810:
1316 link_clock = 81000;
1317 break;
1318 case DPLL_CTRL1_LINK_RATE_1080:
1319 link_clock = 108000;
1320 break;
1321 case DPLL_CTRL1_LINK_RATE_1350:
1322 link_clock = 135000;
1323 break;
1324 case DPLL_CTRL1_LINK_RATE_1620:
1325 link_clock = 162000;
1326 break;
1327 case DPLL_CTRL1_LINK_RATE_2160:
1328 link_clock = 216000;
1329 break;
1330 case DPLL_CTRL1_LINK_RATE_2700:
1331 link_clock = 270000;
1332 break;
1333 default:
1334 WARN(1, "Unsupported link rate\n");
1335 break;
1336 }
1337 link_clock *= 2;
1338 }
1339
1340 pipe_config->port_clock = link_clock;
1341
1342 ddi_dotclock_get(pipe_config);
1343 }
1344
1345 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1346 struct intel_crtc_state *pipe_config)
1347 {
1348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1349 int link_clock = 0;
1350 u32 val, pll;
1351
1352 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1353 switch (val & PORT_CLK_SEL_MASK) {
1354 case PORT_CLK_SEL_LCPLL_810:
1355 link_clock = 81000;
1356 break;
1357 case PORT_CLK_SEL_LCPLL_1350:
1358 link_clock = 135000;
1359 break;
1360 case PORT_CLK_SEL_LCPLL_2700:
1361 link_clock = 270000;
1362 break;
1363 case PORT_CLK_SEL_WRPLL1:
1364 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1365 break;
1366 case PORT_CLK_SEL_WRPLL2:
1367 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1368 break;
1369 case PORT_CLK_SEL_SPLL:
1370 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1371 if (pll == SPLL_PLL_FREQ_810MHz)
1372 link_clock = 81000;
1373 else if (pll == SPLL_PLL_FREQ_1350MHz)
1374 link_clock = 135000;
1375 else if (pll == SPLL_PLL_FREQ_2700MHz)
1376 link_clock = 270000;
1377 else {
1378 WARN(1, "bad spll freq\n");
1379 return;
1380 }
1381 break;
1382 default:
1383 WARN(1, "bad port clock sel\n");
1384 return;
1385 }
1386
1387 pipe_config->port_clock = link_clock * 2;
1388
1389 ddi_dotclock_get(pipe_config);
1390 }
1391
1392 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1393 enum intel_dpll_id dpll)
1394 {
1395 struct intel_shared_dpll *pll;
1396 struct intel_dpll_hw_state *state;
1397 struct dpll clock;
1398
1399 /* For DDI ports we always use a shared PLL. */
1400 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1401 return 0;
1402
1403 pll = &dev_priv->shared_dplls[dpll];
1404 state = &pll->state.hw_state;
1405
1406 clock.m1 = 2;
1407 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1408 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1409 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1410 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1411 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1412 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1413
1414 return chv_calc_dpll_params(100000, &clock);
1415 }
1416
1417 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1418 struct intel_crtc_state *pipe_config)
1419 {
1420 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1421 enum port port = intel_ddi_get_encoder_port(encoder);
1422 uint32_t dpll = port;
1423
1424 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1425
1426 ddi_dotclock_get(pipe_config);
1427 }
1428
1429 void intel_ddi_clock_get(struct intel_encoder *encoder,
1430 struct intel_crtc_state *pipe_config)
1431 {
1432 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1433
1434 if (INTEL_GEN(dev_priv) <= 8)
1435 hsw_ddi_clock_get(encoder, pipe_config);
1436 else if (IS_GEN9_BC(dev_priv))
1437 skl_ddi_clock_get(encoder, pipe_config);
1438 else if (IS_GEN9_LP(dev_priv))
1439 bxt_ddi_clock_get(encoder, pipe_config);
1440 else if (IS_CANNONLAKE(dev_priv))
1441 cnl_ddi_clock_get(encoder, pipe_config);
1442 }
1443
1444 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1445 {
1446 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1447 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1448 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1449 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1450 int type = encoder->type;
1451 uint32_t temp;
1452
1453 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1454 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1455
1456 temp = TRANS_MSA_SYNC_CLK;
1457 switch (crtc_state->pipe_bpp) {
1458 case 18:
1459 temp |= TRANS_MSA_6_BPC;
1460 break;
1461 case 24:
1462 temp |= TRANS_MSA_8_BPC;
1463 break;
1464 case 30:
1465 temp |= TRANS_MSA_10_BPC;
1466 break;
1467 case 36:
1468 temp |= TRANS_MSA_12_BPC;
1469 break;
1470 default:
1471 BUG();
1472 }
1473 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1474 }
1475 }
1476
1477 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1478 bool state)
1479 {
1480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1481 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1482 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1483 uint32_t temp;
1484 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1485 if (state == true)
1486 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1487 else
1488 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1489 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1490 }
1491
1492 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1493 {
1494 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1495 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1496 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497 enum pipe pipe = crtc->pipe;
1498 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1499 enum port port = intel_ddi_get_encoder_port(encoder);
1500 int type = encoder->type;
1501 uint32_t temp;
1502
1503 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1504 temp = TRANS_DDI_FUNC_ENABLE;
1505 temp |= TRANS_DDI_SELECT_PORT(port);
1506
1507 switch (crtc_state->pipe_bpp) {
1508 case 18:
1509 temp |= TRANS_DDI_BPC_6;
1510 break;
1511 case 24:
1512 temp |= TRANS_DDI_BPC_8;
1513 break;
1514 case 30:
1515 temp |= TRANS_DDI_BPC_10;
1516 break;
1517 case 36:
1518 temp |= TRANS_DDI_BPC_12;
1519 break;
1520 default:
1521 BUG();
1522 }
1523
1524 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1525 temp |= TRANS_DDI_PVSYNC;
1526 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1527 temp |= TRANS_DDI_PHSYNC;
1528
1529 if (cpu_transcoder == TRANSCODER_EDP) {
1530 switch (pipe) {
1531 case PIPE_A:
1532 /* On Haswell, can only use the always-on power well for
1533 * eDP when not using the panel fitter, and when not
1534 * using motion blur mitigation (which we don't
1535 * support). */
1536 if (IS_HASWELL(dev_priv) &&
1537 (crtc_state->pch_pfit.enabled ||
1538 crtc_state->pch_pfit.force_thru))
1539 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1540 else
1541 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1542 break;
1543 case PIPE_B:
1544 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1545 break;
1546 case PIPE_C:
1547 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1548 break;
1549 default:
1550 BUG();
1551 break;
1552 }
1553 }
1554
1555 if (type == INTEL_OUTPUT_HDMI) {
1556 if (crtc_state->has_hdmi_sink)
1557 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1558 else
1559 temp |= TRANS_DDI_MODE_SELECT_DVI;
1560
1561 if (crtc_state->hdmi_scrambling)
1562 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1563 if (crtc_state->hdmi_high_tmds_clock_ratio)
1564 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1565 } else if (type == INTEL_OUTPUT_ANALOG) {
1566 temp |= TRANS_DDI_MODE_SELECT_FDI;
1567 temp |= (crtc_state->fdi_lanes - 1) << 1;
1568 } else if (type == INTEL_OUTPUT_DP ||
1569 type == INTEL_OUTPUT_EDP) {
1570 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1572 } else if (type == INTEL_OUTPUT_DP_MST) {
1573 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1574 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1575 } else {
1576 WARN(1, "Invalid encoder type %d for pipe %c\n",
1577 encoder->type, pipe_name(pipe));
1578 }
1579
1580 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1581 }
1582
1583 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1584 enum transcoder cpu_transcoder)
1585 {
1586 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1587 uint32_t val = I915_READ(reg);
1588
1589 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1590 val |= TRANS_DDI_PORT_NONE;
1591 I915_WRITE(reg, val);
1592 }
1593
1594 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1595 {
1596 struct drm_device *dev = intel_connector->base.dev;
1597 struct drm_i915_private *dev_priv = to_i915(dev);
1598 struct intel_encoder *encoder = intel_connector->encoder;
1599 int type = intel_connector->base.connector_type;
1600 enum port port = intel_ddi_get_encoder_port(encoder);
1601 enum pipe pipe = 0;
1602 enum transcoder cpu_transcoder;
1603 uint32_t tmp;
1604 bool ret;
1605
1606 if (!intel_display_power_get_if_enabled(dev_priv,
1607 encoder->power_domain))
1608 return false;
1609
1610 if (!encoder->get_hw_state(encoder, &pipe)) {
1611 ret = false;
1612 goto out;
1613 }
1614
1615 if (port == PORT_A)
1616 cpu_transcoder = TRANSCODER_EDP;
1617 else
1618 cpu_transcoder = (enum transcoder) pipe;
1619
1620 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1621
1622 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1623 case TRANS_DDI_MODE_SELECT_HDMI:
1624 case TRANS_DDI_MODE_SELECT_DVI:
1625 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1626 break;
1627
1628 case TRANS_DDI_MODE_SELECT_DP_SST:
1629 ret = type == DRM_MODE_CONNECTOR_eDP ||
1630 type == DRM_MODE_CONNECTOR_DisplayPort;
1631 break;
1632
1633 case TRANS_DDI_MODE_SELECT_DP_MST:
1634 /* if the transcoder is in MST state then
1635 * connector isn't connected */
1636 ret = false;
1637 break;
1638
1639 case TRANS_DDI_MODE_SELECT_FDI:
1640 ret = type == DRM_MODE_CONNECTOR_VGA;
1641 break;
1642
1643 default:
1644 ret = false;
1645 break;
1646 }
1647
1648 out:
1649 intel_display_power_put(dev_priv, encoder->power_domain);
1650
1651 return ret;
1652 }
1653
1654 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1655 enum pipe *pipe)
1656 {
1657 struct drm_device *dev = encoder->base.dev;
1658 struct drm_i915_private *dev_priv = to_i915(dev);
1659 enum port port = intel_ddi_get_encoder_port(encoder);
1660 u32 tmp;
1661 int i;
1662 bool ret;
1663
1664 if (!intel_display_power_get_if_enabled(dev_priv,
1665 encoder->power_domain))
1666 return false;
1667
1668 ret = false;
1669
1670 tmp = I915_READ(DDI_BUF_CTL(port));
1671
1672 if (!(tmp & DDI_BUF_CTL_ENABLE))
1673 goto out;
1674
1675 if (port == PORT_A) {
1676 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1677
1678 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1679 case TRANS_DDI_EDP_INPUT_A_ON:
1680 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1681 *pipe = PIPE_A;
1682 break;
1683 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1684 *pipe = PIPE_B;
1685 break;
1686 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1687 *pipe = PIPE_C;
1688 break;
1689 }
1690
1691 ret = true;
1692
1693 goto out;
1694 }
1695
1696 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1697 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1698
1699 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1700 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1701 TRANS_DDI_MODE_SELECT_DP_MST)
1702 goto out;
1703
1704 *pipe = i;
1705 ret = true;
1706
1707 goto out;
1708 }
1709 }
1710
1711 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1712
1713 out:
1714 if (ret && IS_GEN9_LP(dev_priv)) {
1715 tmp = I915_READ(BXT_PHY_CTL(port));
1716 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1717 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1718 DRM_ERROR("Port %c enabled but PHY powered down? "
1719 "(PHY_CTL %08x)\n", port_name(port), tmp);
1720 }
1721
1722 intel_display_power_put(dev_priv, encoder->power_domain);
1723
1724 return ret;
1725 }
1726
1727 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1728 {
1729 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1730 enum pipe pipe;
1731
1732 if (intel_ddi_get_hw_state(encoder, &pipe))
1733 return BIT_ULL(dig_port->ddi_io_power_domain);
1734
1735 return 0;
1736 }
1737
1738 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1739 {
1740 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1741 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1742 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1743 enum port port = intel_ddi_get_encoder_port(encoder);
1744 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1745
1746 if (cpu_transcoder != TRANSCODER_EDP)
1747 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1748 TRANS_CLK_SEL_PORT(port));
1749 }
1750
1751 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1752 {
1753 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1754 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1755
1756 if (cpu_transcoder != TRANSCODER_EDP)
1757 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1758 TRANS_CLK_SEL_DISABLED);
1759 }
1760
1761 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1762 enum port port, uint8_t iboost)
1763 {
1764 u32 tmp;
1765
1766 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1767 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1768 if (iboost)
1769 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1770 else
1771 tmp |= BALANCE_LEG_DISABLE(port);
1772 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1773 }
1774
1775 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
1776 {
1777 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1778 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1779 enum port port = intel_dig_port->port;
1780 int type = encoder->type;
1781 const struct ddi_buf_trans *ddi_translations;
1782 uint8_t iboost;
1783 uint8_t dp_iboost, hdmi_iboost;
1784 int n_entries;
1785
1786 /* VBT may override standard boost values */
1787 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1788 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1789
1790 if (type == INTEL_OUTPUT_DP) {
1791 if (dp_iboost) {
1792 iboost = dp_iboost;
1793 } else {
1794 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
1795 ddi_translations = kbl_get_buf_trans_dp(dev_priv,
1796 &n_entries);
1797 else
1798 ddi_translations = skl_get_buf_trans_dp(dev_priv,
1799 &n_entries);
1800 iboost = ddi_translations[level].i_boost;
1801 }
1802 } else if (type == INTEL_OUTPUT_EDP) {
1803 if (dp_iboost) {
1804 iboost = dp_iboost;
1805 } else {
1806 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1807
1808 if (WARN_ON(port != PORT_A &&
1809 port != PORT_E && n_entries > 9))
1810 n_entries = 9;
1811
1812 iboost = ddi_translations[level].i_boost;
1813 }
1814 } else if (type == INTEL_OUTPUT_HDMI) {
1815 if (hdmi_iboost) {
1816 iboost = hdmi_iboost;
1817 } else {
1818 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1819 iboost = ddi_translations[level].i_boost;
1820 }
1821 } else {
1822 return;
1823 }
1824
1825 /* Make sure that the requested I_boost is valid */
1826 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1827 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1828 return;
1829 }
1830
1831 _skl_ddi_set_iboost(dev_priv, port, iboost);
1832
1833 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1834 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1835 }
1836
1837 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1838 u32 level, enum port port, int type)
1839 {
1840 const struct bxt_ddi_buf_trans *ddi_translations;
1841 u32 n_entries, i;
1842
1843 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1844 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1845 ddi_translations = bxt_ddi_translations_edp;
1846 } else if (type == INTEL_OUTPUT_DP
1847 || type == INTEL_OUTPUT_EDP) {
1848 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1849 ddi_translations = bxt_ddi_translations_dp;
1850 } else if (type == INTEL_OUTPUT_HDMI) {
1851 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1852 ddi_translations = bxt_ddi_translations_hdmi;
1853 } else {
1854 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1855 type);
1856 return;
1857 }
1858
1859 /* Check if default value has to be used */
1860 if (level >= n_entries ||
1861 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1862 for (i = 0; i < n_entries; i++) {
1863 if (ddi_translations[i].default_index) {
1864 level = i;
1865 break;
1866 }
1867 }
1868 }
1869
1870 bxt_ddi_phy_set_signal_level(dev_priv, port,
1871 ddi_translations[level].margin,
1872 ddi_translations[level].scale,
1873 ddi_translations[level].enable,
1874 ddi_translations[level].deemphasis);
1875 }
1876
1877 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1878 {
1879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1880 int n_entries;
1881
1882 if (IS_CANNONLAKE(dev_priv)) {
1883 if (encoder->type == INTEL_OUTPUT_EDP)
1884 cnl_get_buf_trans_edp(dev_priv, &n_entries);
1885 else
1886 cnl_get_buf_trans_dp(dev_priv, &n_entries);
1887 } else {
1888 if (encoder->type == INTEL_OUTPUT_EDP)
1889 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
1890 else
1891 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
1892 }
1893
1894 if (WARN_ON(n_entries < 1))
1895 n_entries = 1;
1896 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1897 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1898
1899 return index_to_dp_signal_levels[n_entries - 1] &
1900 DP_TRAIN_VOLTAGE_SWING_MASK;
1901 }
1902
1903 static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
1904 u32 level, enum port port, int type)
1905 {
1906 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
1907 u32 n_entries, val;
1908 int ln;
1909
1910 if (type == INTEL_OUTPUT_HDMI) {
1911 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
1912 } else if (type == INTEL_OUTPUT_DP) {
1913 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
1914 } else if (type == INTEL_OUTPUT_EDP) {
1915 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
1916 }
1917
1918 if (WARN_ON(ddi_translations == NULL))
1919 return;
1920
1921 if (level >= n_entries) {
1922 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
1923 level = n_entries - 1;
1924 }
1925
1926 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1927 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1928 val &= ~SCALING_MODE_SEL_MASK;
1929 val |= SCALING_MODE_SEL(2);
1930 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1931
1932 /* Program PORT_TX_DW2 */
1933 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1934 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1935 RCOMP_SCALAR_MASK);
1936 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1937 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1938 /* Rcomp scalar is fixed as 0x98 for every table entry */
1939 val |= RCOMP_SCALAR(0x98);
1940 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1941
1942 /* Program PORT_TX_DW4 */
1943 /* We cannot write to GRP. It would overrite individual loadgen */
1944 for (ln = 0; ln < 4; ln++) {
1945 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1946 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1947 CURSOR_COEFF_MASK);
1948 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1949 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1950 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1951 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1952 }
1953
1954 /* Program PORT_TX_DW5 */
1955 /* All DW5 values are fixed for every table entry */
1956 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1957 val &= ~RTERM_SELECT_MASK;
1958 val |= RTERM_SELECT(6);
1959 val |= TAP3_DISABLE;
1960 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1961
1962 /* Program PORT_TX_DW7 */
1963 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1964 val &= ~N_SCALAR_MASK;
1965 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1966 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1967 }
1968
1969 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
1970 {
1971 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1972 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1973 enum port port = intel_ddi_get_encoder_port(encoder);
1974 int type = encoder->type;
1975 int width = 0;
1976 int rate = 0;
1977 u32 val;
1978 int ln = 0;
1979
1980 if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
1981 width = intel_dp->lane_count;
1982 rate = intel_dp->link_rate;
1983 } else if (type == INTEL_OUTPUT_HDMI) {
1984 width = 4;
1985 /* Rate is always < than 6GHz for HDMI */
1986 } else {
1987 MISSING_CASE(type);
1988 return;
1989 }
1990
1991 /*
1992 * 1. If port type is eDP or DP,
1993 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1994 * else clear to 0b.
1995 */
1996 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
1997 if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
1998 val |= COMMON_KEEPER_EN;
1999 else
2000 val &= ~COMMON_KEEPER_EN;
2001 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2002
2003 /* 2. Program loadgen select */
2004 /*
2005 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2006 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2007 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2008 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2009 */
2010 for (ln = 0; ln <= 3; ln++) {
2011 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2012 val &= ~LOADGEN_SELECT;
2013
2014 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2015 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2016 val |= LOADGEN_SELECT;
2017 }
2018 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2019 }
2020
2021 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2022 val = I915_READ(CNL_PORT_CL1CM_DW5);
2023 val |= SUS_CLOCK_CONFIG;
2024 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2025
2026 /* 4. Clear training enable to change swing values */
2027 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2028 val &= ~TX_TRAINING_EN;
2029 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2030
2031 /* 5. Program swing and de-emphasis */
2032 cnl_ddi_vswing_program(dev_priv, level, port, type);
2033
2034 /* 6. Set training enable to trigger update */
2035 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2036 val |= TX_TRAINING_EN;
2037 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2038 }
2039
2040 static uint32_t translate_signal_level(int signal_levels)
2041 {
2042 int i;
2043
2044 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2045 if (index_to_dp_signal_levels[i] == signal_levels)
2046 return i;
2047 }
2048
2049 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2050 signal_levels);
2051
2052 return 0;
2053 }
2054
2055 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2056 {
2057 uint8_t train_set = intel_dp->train_set[0];
2058 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2059 DP_TRAIN_PRE_EMPHASIS_MASK);
2060
2061 return translate_signal_level(signal_levels);
2062 }
2063
2064 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2065 {
2066 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2067 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2068 struct intel_encoder *encoder = &dport->base;
2069 enum port port = dport->port;
2070 u32 level = intel_ddi_dp_level(intel_dp);
2071
2072 if (IS_CANNONLAKE(dev_priv))
2073 cnl_ddi_vswing_sequence(encoder, level);
2074 else
2075 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2076
2077 return 0;
2078 }
2079
2080 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2081 {
2082 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2083 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2084 struct intel_encoder *encoder = &dport->base;
2085 uint32_t level = intel_ddi_dp_level(intel_dp);
2086
2087 if (IS_GEN9_BC(dev_priv))
2088 skl_ddi_set_iboost(encoder, level);
2089
2090 return DDI_BUF_TRANS_SELECT(level);
2091 }
2092
2093 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2094 const struct intel_shared_dpll *pll)
2095 {
2096 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2097 enum port port = intel_ddi_get_encoder_port(encoder);
2098 uint32_t val;
2099
2100 if (WARN_ON(!pll))
2101 return;
2102
2103 if (IS_CANNONLAKE(dev_priv)) {
2104 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2105 val = I915_READ(DPCLKA_CFGCR0);
2106 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2107 I915_WRITE(DPCLKA_CFGCR0, val);
2108
2109 /*
2110 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2111 * This step and the step before must be done with separate
2112 * register writes.
2113 */
2114 val = I915_READ(DPCLKA_CFGCR0);
2115 val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
2116 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
2117 I915_WRITE(DPCLKA_CFGCR0, val);
2118 } else if (IS_GEN9_BC(dev_priv)) {
2119 /* DDI -> PLL mapping */
2120 val = I915_READ(DPLL_CTRL2);
2121
2122 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2123 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2124 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
2125 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2126
2127 I915_WRITE(DPLL_CTRL2, val);
2128
2129 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2130 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2131 }
2132 }
2133
2134 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2135 int link_rate, uint32_t lane_count,
2136 struct intel_shared_dpll *pll,
2137 bool link_mst)
2138 {
2139 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2140 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2141 enum port port = intel_ddi_get_encoder_port(encoder);
2142 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2143 uint32_t level = intel_ddi_dp_level(intel_dp);
2144
2145 WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
2146
2147 intel_dp_set_link_params(intel_dp, link_rate, lane_count,
2148 link_mst);
2149 if (encoder->type == INTEL_OUTPUT_EDP)
2150 intel_edp_panel_on(intel_dp);
2151
2152 intel_ddi_clk_select(encoder, pll);
2153
2154 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2155
2156 if (IS_CANNONLAKE(dev_priv))
2157 cnl_ddi_vswing_sequence(encoder, level);
2158 else if (IS_GEN9_LP(dev_priv))
2159 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2160 else
2161 intel_prepare_dp_ddi_buffers(encoder);
2162
2163 intel_ddi_init_dp_buf_reg(encoder);
2164 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2165 intel_dp_start_link_train(intel_dp);
2166 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2167 intel_dp_stop_link_train(intel_dp);
2168 }
2169
2170 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2171 bool has_infoframe,
2172 const struct intel_crtc_state *crtc_state,
2173 const struct drm_connector_state *conn_state,
2174 const struct intel_shared_dpll *pll)
2175 {
2176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2177 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2179 enum port port = intel_ddi_get_encoder_port(encoder);
2180 int level = intel_ddi_hdmi_level(dev_priv, port);
2181 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2182
2183 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2184 intel_ddi_clk_select(encoder, pll);
2185
2186 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2187
2188 if (IS_CANNONLAKE(dev_priv))
2189 cnl_ddi_vswing_sequence(encoder, level);
2190 else if (IS_GEN9_LP(dev_priv))
2191 bxt_ddi_vswing_sequence(dev_priv, level, port,
2192 INTEL_OUTPUT_HDMI);
2193 else
2194 intel_prepare_hdmi_ddi_buffers(encoder);
2195
2196 if (IS_GEN9_BC(dev_priv))
2197 skl_ddi_set_iboost(encoder, level);
2198
2199 intel_dig_port->set_infoframes(&encoder->base,
2200 has_infoframe,
2201 crtc_state, conn_state);
2202 }
2203
2204 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2205 const struct intel_crtc_state *pipe_config,
2206 const struct drm_connector_state *conn_state)
2207 {
2208 int type = encoder->type;
2209
2210 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2211 intel_ddi_pre_enable_dp(encoder,
2212 pipe_config->port_clock,
2213 pipe_config->lane_count,
2214 pipe_config->shared_dpll,
2215 intel_crtc_has_type(pipe_config,
2216 INTEL_OUTPUT_DP_MST));
2217 }
2218 if (type == INTEL_OUTPUT_HDMI) {
2219 intel_ddi_pre_enable_hdmi(encoder,
2220 pipe_config->has_infoframe,
2221 pipe_config, conn_state,
2222 pipe_config->shared_dpll);
2223 }
2224 }
2225
2226 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
2227 const struct intel_crtc_state *old_crtc_state,
2228 const struct drm_connector_state *old_conn_state)
2229 {
2230 struct drm_encoder *encoder = &intel_encoder->base;
2231 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2232 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2233 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2234 int type = intel_encoder->type;
2235 uint32_t val;
2236 bool wait = false;
2237
2238 /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
2239
2240 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2241 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2242
2243 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2244 }
2245
2246 val = I915_READ(DDI_BUF_CTL(port));
2247 if (val & DDI_BUF_CTL_ENABLE) {
2248 val &= ~DDI_BUF_CTL_ENABLE;
2249 I915_WRITE(DDI_BUF_CTL(port), val);
2250 wait = true;
2251 }
2252
2253 val = I915_READ(DP_TP_CTL(port));
2254 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2255 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2256 I915_WRITE(DP_TP_CTL(port), val);
2257
2258 if (wait)
2259 intel_wait_ddi_buf_idle(dev_priv, port);
2260
2261 if (type == INTEL_OUTPUT_HDMI) {
2262 dig_port->set_infoframes(encoder, false,
2263 old_crtc_state, old_conn_state);
2264 }
2265
2266 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2267 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2268
2269 intel_edp_panel_vdd_on(intel_dp);
2270 intel_edp_panel_off(intel_dp);
2271 }
2272
2273 if (dig_port)
2274 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2275
2276 if (IS_CANNONLAKE(dev_priv))
2277 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2278 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2279 else if (IS_GEN9_BC(dev_priv))
2280 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2281 DPLL_CTRL2_DDI_CLK_OFF(port)));
2282 else if (INTEL_GEN(dev_priv) < 9)
2283 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2284
2285 if (type == INTEL_OUTPUT_HDMI) {
2286 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2287
2288 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2289 }
2290 }
2291
2292 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2293 const struct intel_crtc_state *old_crtc_state,
2294 const struct drm_connector_state *old_conn_state)
2295 {
2296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2297 uint32_t val;
2298
2299 /*
2300 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2301 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2302 * step 13 is the correct place for it. Step 18 is where it was
2303 * originally before the BUN.
2304 */
2305 val = I915_READ(FDI_RX_CTL(PIPE_A));
2306 val &= ~FDI_RX_ENABLE;
2307 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2308
2309 intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
2310
2311 val = I915_READ(FDI_RX_MISC(PIPE_A));
2312 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2313 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2314 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2315
2316 val = I915_READ(FDI_RX_CTL(PIPE_A));
2317 val &= ~FDI_PCDCLK;
2318 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2319
2320 val = I915_READ(FDI_RX_CTL(PIPE_A));
2321 val &= ~FDI_RX_PLL_ENABLE;
2322 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2323 }
2324
2325 static void intel_enable_ddi(struct intel_encoder *intel_encoder,
2326 const struct intel_crtc_state *pipe_config,
2327 const struct drm_connector_state *conn_state)
2328 {
2329 struct drm_encoder *encoder = &intel_encoder->base;
2330 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2331 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2332 int type = intel_encoder->type;
2333
2334 if (type == INTEL_OUTPUT_HDMI) {
2335 struct intel_digital_port *intel_dig_port =
2336 enc_to_dig_port(encoder);
2337 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
2338 bool scrambling = pipe_config->hdmi_scrambling;
2339
2340 intel_hdmi_handle_sink_scrambling(intel_encoder,
2341 conn_state->connector,
2342 clock_ratio, scrambling);
2343
2344 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2345 * are ignored so nothing special needs to be done besides
2346 * enabling the port.
2347 */
2348 I915_WRITE(DDI_BUF_CTL(port),
2349 intel_dig_port->saved_port_bits |
2350 DDI_BUF_CTL_ENABLE);
2351 } else if (type == INTEL_OUTPUT_EDP) {
2352 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2353
2354 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2355 intel_dp_stop_link_train(intel_dp);
2356
2357 intel_edp_backlight_on(pipe_config, conn_state);
2358 intel_psr_enable(intel_dp, pipe_config);
2359 intel_edp_drrs_enable(intel_dp, pipe_config);
2360 }
2361
2362 if (pipe_config->has_audio)
2363 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
2364 }
2365
2366 static void intel_disable_ddi(struct intel_encoder *intel_encoder,
2367 const struct intel_crtc_state *old_crtc_state,
2368 const struct drm_connector_state *old_conn_state)
2369 {
2370 struct drm_encoder *encoder = &intel_encoder->base;
2371 int type = intel_encoder->type;
2372
2373 if (old_crtc_state->has_audio)
2374 intel_audio_codec_disable(intel_encoder);
2375
2376 if (type == INTEL_OUTPUT_HDMI) {
2377 intel_hdmi_handle_sink_scrambling(intel_encoder,
2378 old_conn_state->connector,
2379 false, false);
2380 }
2381
2382 if (type == INTEL_OUTPUT_EDP) {
2383 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2384
2385 intel_edp_drrs_disable(intel_dp, old_crtc_state);
2386 intel_psr_disable(intel_dp, old_crtc_state);
2387 intel_edp_backlight_off(old_conn_state);
2388 }
2389 }
2390
2391 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2392 const struct intel_crtc_state *pipe_config,
2393 const struct drm_connector_state *conn_state)
2394 {
2395 uint8_t mask = pipe_config->lane_lat_optim_mask;
2396
2397 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2398 }
2399
2400 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2401 {
2402 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2403 struct drm_i915_private *dev_priv =
2404 to_i915(intel_dig_port->base.base.dev);
2405 enum port port = intel_dig_port->port;
2406 uint32_t val;
2407 bool wait = false;
2408
2409 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2410 val = I915_READ(DDI_BUF_CTL(port));
2411 if (val & DDI_BUF_CTL_ENABLE) {
2412 val &= ~DDI_BUF_CTL_ENABLE;
2413 I915_WRITE(DDI_BUF_CTL(port), val);
2414 wait = true;
2415 }
2416
2417 val = I915_READ(DP_TP_CTL(port));
2418 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2419 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2420 I915_WRITE(DP_TP_CTL(port), val);
2421 POSTING_READ(DP_TP_CTL(port));
2422
2423 if (wait)
2424 intel_wait_ddi_buf_idle(dev_priv, port);
2425 }
2426
2427 val = DP_TP_CTL_ENABLE |
2428 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2429 if (intel_dp->link_mst)
2430 val |= DP_TP_CTL_MODE_MST;
2431 else {
2432 val |= DP_TP_CTL_MODE_SST;
2433 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2434 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2435 }
2436 I915_WRITE(DP_TP_CTL(port), val);
2437 POSTING_READ(DP_TP_CTL(port));
2438
2439 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2440 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2441 POSTING_READ(DDI_BUF_CTL(port));
2442
2443 udelay(600);
2444 }
2445
2446 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2447 struct intel_crtc *intel_crtc)
2448 {
2449 u32 temp;
2450
2451 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2452 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2453 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2454 return true;
2455 }
2456 return false;
2457 }
2458
2459 void intel_ddi_get_config(struct intel_encoder *encoder,
2460 struct intel_crtc_state *pipe_config)
2461 {
2462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2463 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2464 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2465 struct intel_digital_port *intel_dig_port;
2466 u32 temp, flags = 0;
2467
2468 /* XXX: DSI transcoder paranoia */
2469 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2470 return;
2471
2472 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2473 if (temp & TRANS_DDI_PHSYNC)
2474 flags |= DRM_MODE_FLAG_PHSYNC;
2475 else
2476 flags |= DRM_MODE_FLAG_NHSYNC;
2477 if (temp & TRANS_DDI_PVSYNC)
2478 flags |= DRM_MODE_FLAG_PVSYNC;
2479 else
2480 flags |= DRM_MODE_FLAG_NVSYNC;
2481
2482 pipe_config->base.adjusted_mode.flags |= flags;
2483
2484 switch (temp & TRANS_DDI_BPC_MASK) {
2485 case TRANS_DDI_BPC_6:
2486 pipe_config->pipe_bpp = 18;
2487 break;
2488 case TRANS_DDI_BPC_8:
2489 pipe_config->pipe_bpp = 24;
2490 break;
2491 case TRANS_DDI_BPC_10:
2492 pipe_config->pipe_bpp = 30;
2493 break;
2494 case TRANS_DDI_BPC_12:
2495 pipe_config->pipe_bpp = 36;
2496 break;
2497 default:
2498 break;
2499 }
2500
2501 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2502 case TRANS_DDI_MODE_SELECT_HDMI:
2503 pipe_config->has_hdmi_sink = true;
2504 intel_dig_port = enc_to_dig_port(&encoder->base);
2505
2506 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
2507 pipe_config->has_infoframe = true;
2508
2509 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2510 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2511 pipe_config->hdmi_scrambling = true;
2512 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2513 pipe_config->hdmi_high_tmds_clock_ratio = true;
2514 /* fall through */
2515 case TRANS_DDI_MODE_SELECT_DVI:
2516 pipe_config->lane_count = 4;
2517 break;
2518 case TRANS_DDI_MODE_SELECT_FDI:
2519 break;
2520 case TRANS_DDI_MODE_SELECT_DP_SST:
2521 case TRANS_DDI_MODE_SELECT_DP_MST:
2522 pipe_config->lane_count =
2523 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2524 intel_dp_get_m_n(intel_crtc, pipe_config);
2525 break;
2526 default:
2527 break;
2528 }
2529
2530 pipe_config->has_audio =
2531 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
2532
2533 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2534 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2535 /*
2536 * This is a big fat ugly hack.
2537 *
2538 * Some machines in UEFI boot mode provide us a VBT that has 18
2539 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2540 * unknown we fail to light up. Yet the same BIOS boots up with
2541 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2542 * max, not what it tells us to use.
2543 *
2544 * Note: This will still be broken if the eDP panel is not lit
2545 * up by the BIOS, and thus we can't get the mode at module
2546 * load.
2547 */
2548 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2549 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2550 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2551 }
2552
2553 intel_ddi_clock_get(encoder, pipe_config);
2554
2555 if (IS_GEN9_LP(dev_priv))
2556 pipe_config->lane_lat_optim_mask =
2557 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2558 }
2559
2560 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2561 struct intel_crtc_state *pipe_config,
2562 struct drm_connector_state *conn_state)
2563 {
2564 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2565 int type = encoder->type;
2566 int port = intel_ddi_get_encoder_port(encoder);
2567 int ret;
2568
2569 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2570
2571 if (port == PORT_A)
2572 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2573
2574 if (type == INTEL_OUTPUT_HDMI)
2575 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2576 else
2577 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2578
2579 if (IS_GEN9_LP(dev_priv) && ret)
2580 pipe_config->lane_lat_optim_mask =
2581 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2582 pipe_config->lane_count);
2583
2584 return ret;
2585
2586 }
2587
2588 static const struct drm_encoder_funcs intel_ddi_funcs = {
2589 .reset = intel_dp_encoder_reset,
2590 .destroy = intel_dp_encoder_destroy,
2591 };
2592
2593 static struct intel_connector *
2594 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2595 {
2596 struct intel_connector *connector;
2597 enum port port = intel_dig_port->port;
2598
2599 connector = intel_connector_alloc();
2600 if (!connector)
2601 return NULL;
2602
2603 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2604 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2605 kfree(connector);
2606 return NULL;
2607 }
2608
2609 return connector;
2610 }
2611
2612 static struct intel_connector *
2613 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2614 {
2615 struct intel_connector *connector;
2616 enum port port = intel_dig_port->port;
2617
2618 connector = intel_connector_alloc();
2619 if (!connector)
2620 return NULL;
2621
2622 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2623 intel_hdmi_init_connector(intel_dig_port, connector);
2624
2625 return connector;
2626 }
2627
2628 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
2629 {
2630 struct intel_digital_port *intel_dig_port;
2631 struct intel_encoder *intel_encoder;
2632 struct drm_encoder *encoder;
2633 bool init_hdmi, init_dp, init_lspcon = false;
2634 int max_lanes;
2635
2636 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2637 switch (port) {
2638 case PORT_A:
2639 max_lanes = 4;
2640 break;
2641 case PORT_E:
2642 max_lanes = 0;
2643 break;
2644 default:
2645 max_lanes = 4;
2646 break;
2647 }
2648 } else {
2649 switch (port) {
2650 case PORT_A:
2651 max_lanes = 2;
2652 break;
2653 case PORT_E:
2654 max_lanes = 2;
2655 break;
2656 default:
2657 max_lanes = 4;
2658 break;
2659 }
2660 }
2661
2662 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2663 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2664 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2665
2666 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2667 /*
2668 * Lspcon device needs to be driven with DP connector
2669 * with special detection sequence. So make sure DP
2670 * is initialized before lspcon.
2671 */
2672 init_dp = true;
2673 init_lspcon = true;
2674 init_hdmi = false;
2675 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2676 }
2677
2678 if (!init_dp && !init_hdmi) {
2679 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2680 port_name(port));
2681 return;
2682 }
2683
2684 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2685 if (!intel_dig_port)
2686 return;
2687
2688 intel_encoder = &intel_dig_port->base;
2689 encoder = &intel_encoder->base;
2690
2691 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
2692 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2693
2694 intel_encoder->compute_config = intel_ddi_compute_config;
2695 intel_encoder->enable = intel_enable_ddi;
2696 if (IS_GEN9_LP(dev_priv))
2697 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2698 intel_encoder->pre_enable = intel_ddi_pre_enable;
2699 intel_encoder->disable = intel_disable_ddi;
2700 intel_encoder->post_disable = intel_ddi_post_disable;
2701 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2702 intel_encoder->get_config = intel_ddi_get_config;
2703 intel_encoder->suspend = intel_dp_encoder_suspend;
2704 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
2705
2706 intel_dig_port->port = port;
2707 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2708 (DDI_BUF_PORT_REVERSAL |
2709 DDI_A_4_LANES);
2710
2711 switch (port) {
2712 case PORT_A:
2713 intel_dig_port->ddi_io_power_domain =
2714 POWER_DOMAIN_PORT_DDI_A_IO;
2715 break;
2716 case PORT_B:
2717 intel_dig_port->ddi_io_power_domain =
2718 POWER_DOMAIN_PORT_DDI_B_IO;
2719 break;
2720 case PORT_C:
2721 intel_dig_port->ddi_io_power_domain =
2722 POWER_DOMAIN_PORT_DDI_C_IO;
2723 break;
2724 case PORT_D:
2725 intel_dig_port->ddi_io_power_domain =
2726 POWER_DOMAIN_PORT_DDI_D_IO;
2727 break;
2728 case PORT_E:
2729 intel_dig_port->ddi_io_power_domain =
2730 POWER_DOMAIN_PORT_DDI_E_IO;
2731 break;
2732 default:
2733 MISSING_CASE(port);
2734 }
2735
2736 /*
2737 * Bspec says that DDI_A_4_LANES is the only supported configuration
2738 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2739 * wasn't lit up at boot. Force this bit on in our internal
2740 * configuration so that we use the proper lane count for our
2741 * calculations.
2742 */
2743 if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
2744 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2745 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2746 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2747 max_lanes = 4;
2748 }
2749 }
2750
2751 intel_dig_port->max_lanes = max_lanes;
2752
2753 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2754 intel_encoder->power_domain = intel_port_to_power_domain(port);
2755 intel_encoder->port = port;
2756 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2757 intel_encoder->cloneable = 0;
2758
2759 intel_infoframe_init(intel_dig_port);
2760
2761 if (init_dp) {
2762 if (!intel_ddi_init_dp_connector(intel_dig_port))
2763 goto err;
2764
2765 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2766 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2767 }
2768
2769 /* In theory we don't need the encoder->type check, but leave it just in
2770 * case we have some really bad VBTs... */
2771 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2772 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2773 goto err;
2774 }
2775
2776 if (init_lspcon) {
2777 if (lspcon_init(intel_dig_port))
2778 /* TODO: handle hdmi info frame part */
2779 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2780 port_name(port));
2781 else
2782 /*
2783 * LSPCON init faied, but DP init was success, so
2784 * lets try to drive as DP++ port.
2785 */
2786 DRM_ERROR("LSPCON init failed on port %c\n",
2787 port_name(port));
2788 }
2789
2790 return;
2791
2792 err:
2793 drm_encoder_cleanup(encoder);
2794 kfree(intel_dig_port);
2795 }
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