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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "i915_drv.h"
29 #include "intel_drv.h"
30
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
35 };
36
37 static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48 };
49
50 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
53 */
54 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
64 };
65
66 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
76 };
77
78 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
92 };
93
94 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
104 };
105
106 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
116 };
117
118 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
128 };
129
130 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
142 };
143
144 /* Skylake H and S */
145 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x000000DF, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
155 };
156
157 /* Skylake U */
158 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
159 { 0x0000201B, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x1 },
162 { 0x80009010, 0x000000C0, 0x1 },
163 { 0x0000201B, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
166 { 0x00002016, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x1 },
168 };
169
170 /* Skylake Y */
171 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
174 { 0x80007011, 0x000000CD, 0x3 },
175 { 0x80009010, 0x000000C0, 0x3 },
176 { 0x00000018, 0x0000009D, 0x0 },
177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
179 { 0x00000018, 0x00000088, 0x0 },
180 { 0x80005012, 0x000000C0, 0x3 },
181 };
182
183 /* Kabylake H and S */
184 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
194 };
195
196 /* Kabylake U */
197 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
207 };
208
209 /* Kabylake Y */
210 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
220 };
221
222 /*
223 * Skylake/Kabylake H and S
224 * eDP 1.4 low vswing translation parameters
225 */
226 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
237 };
238
239 /*
240 * Skylake/Kabylake U
241 * eDP 1.4 low vswing translation parameters
242 */
243 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
254 };
255
256 /*
257 * Skylake/Kabylake Y
258 * eDP 1.4 low vswing translation parameters
259 */
260 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
271 };
272
273 /* Skylake/Kabylake U, H and S */
274 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
281 { 0x80006012, 0x000000CD, 0x1 },
282 { 0x00000018, 0x000000DF, 0x0 },
283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
286 };
287
288 /* Skylake/Kabylake Y */
289 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
292 { 0x80007011, 0x000000CB, 0x3 },
293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
296 { 0x80006013, 0x000000C0, 0x3 },
297 { 0x00000018, 0x0000008A, 0x0 },
298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
301 };
302
303 struct bxt_ddi_buf_trans {
304 u8 margin; /* swing value */
305 u8 scale; /* scale value */
306 u8 enable; /* scale enable */
307 u8 deemphasis;
308 };
309
310 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
311 /* Idx NT mV diff db */
312 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
313 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
314 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
315 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
316 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
317 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
318 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
319 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
320 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
321 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
322 };
323
324 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
325 /* Idx NT mV diff db */
326 { 26, 0, 0, 128, }, /* 0: 200 0 */
327 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
328 { 48, 0, 0, 96, }, /* 2: 200 4 */
329 { 54, 0, 0, 69, }, /* 3: 200 6 */
330 { 32, 0, 0, 128, }, /* 4: 250 0 */
331 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
332 { 54, 0, 0, 85, }, /* 6: 250 4 */
333 { 43, 0, 0, 128, }, /* 7: 300 0 */
334 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
335 { 48, 0, 0, 128, }, /* 9: 300 0 */
336 };
337
338 /* BSpec has 2 recommended values - entries 0 and 8.
339 * Using the entry with higher vswing.
340 */
341 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
342 /* Idx NT mV diff db */
343 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
344 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
345 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
346 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
347 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
348 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
349 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
350 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
351 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
352 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
353 };
354
355 struct cnl_ddi_buf_trans {
356 u8 dw2_swing_sel;
357 u8 dw7_n_scalar;
358 u8 dw4_cursor_coeff;
359 u8 dw4_post_cursor_2;
360 u8 dw4_post_cursor_1;
361 };
362
363 /* Voltage Swing Programming for VccIO 0.85V for DP */
364 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
365 /* NT mV Trans mV db */
366 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
367 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
368 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
369 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
370 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
371 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
372 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
373 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
374 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
375 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
376 };
377
378 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
379 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
380 /* NT mV Trans mV db */
381 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
382 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
383 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
384 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
385 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
386 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
387 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
388 };
389
390 /* Voltage Swing Programming for VccIO 0.85V for eDP */
391 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
392 /* NT mV Trans mV db */
393 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
394 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
395 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
396 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
397 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
398 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
399 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
400 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
401 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
402 };
403
404 /* Voltage Swing Programming for VccIO 0.95V for DP */
405 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
406 /* NT mV Trans mV db */
407 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
408 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
409 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
410 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
411 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
412 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
413 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
414 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
415 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
416 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
417 };
418
419 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
420 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
421 /* NT mV Trans mV db */
422 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
423 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
424 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
425 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
426 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
427 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
428 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
429 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
430 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
431 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
432 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
433 };
434
435 /* Voltage Swing Programming for VccIO 0.95V for eDP */
436 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
437 /* NT mV Trans mV db */
438 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
439 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
440 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
441 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
442 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
443 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
444 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
445 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
446 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
447 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
448 };
449
450 /* Voltage Swing Programming for VccIO 1.05V for DP */
451 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
452 /* NT mV Trans mV db */
453 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
454 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
455 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
456 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
457 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
458 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
459 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
460 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
461 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
462 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
463 };
464
465 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
466 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
467 /* NT mV Trans mV db */
468 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
469 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
470 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
471 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
472 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
473 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
474 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
475 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
476 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
477 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
478 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
479 };
480
481 /* Voltage Swing Programming for VccIO 1.05V for eDP */
482 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
483 /* NT mV Trans mV db */
484 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
485 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
486 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
487 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
488 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
489 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
490 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
491 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
492 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
493 };
494
495 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
496 {
497 switch (encoder->type) {
498 case INTEL_OUTPUT_DP_MST:
499 return enc_to_mst(&encoder->base)->primary->port;
500 case INTEL_OUTPUT_DP:
501 case INTEL_OUTPUT_EDP:
502 case INTEL_OUTPUT_HDMI:
503 case INTEL_OUTPUT_UNKNOWN:
504 return enc_to_dig_port(&encoder->base)->port;
505 case INTEL_OUTPUT_ANALOG:
506 return PORT_E;
507 default:
508 MISSING_CASE(encoder->type);
509 return PORT_A;
510 }
511 }
512
513 static const struct ddi_buf_trans *
514 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
515 {
516 if (dev_priv->vbt.edp.low_vswing) {
517 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
518 return bdw_ddi_translations_edp;
519 } else {
520 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
521 return bdw_ddi_translations_dp;
522 }
523 }
524
525 static const struct ddi_buf_trans *
526 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
527 {
528 if (IS_SKL_ULX(dev_priv)) {
529 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
530 return skl_y_ddi_translations_dp;
531 } else if (IS_SKL_ULT(dev_priv)) {
532 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
533 return skl_u_ddi_translations_dp;
534 } else {
535 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
536 return skl_ddi_translations_dp;
537 }
538 }
539
540 static const struct ddi_buf_trans *
541 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
542 {
543 if (IS_KBL_ULX(dev_priv)) {
544 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
545 return kbl_y_ddi_translations_dp;
546 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
547 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
548 return kbl_u_ddi_translations_dp;
549 } else {
550 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
551 return kbl_ddi_translations_dp;
552 }
553 }
554
555 static const struct ddi_buf_trans *
556 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
557 {
558 if (dev_priv->vbt.edp.low_vswing) {
559 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
560 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
561 return skl_y_ddi_translations_edp;
562 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
563 IS_CFL_ULT(dev_priv)) {
564 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
565 return skl_u_ddi_translations_edp;
566 } else {
567 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
568 return skl_ddi_translations_edp;
569 }
570 }
571
572 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
573 return kbl_get_buf_trans_dp(dev_priv, n_entries);
574 else
575 return skl_get_buf_trans_dp(dev_priv, n_entries);
576 }
577
578 static const struct ddi_buf_trans *
579 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
580 {
581 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
582 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
583 return skl_y_ddi_translations_hdmi;
584 } else {
585 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
586 return skl_ddi_translations_hdmi;
587 }
588 }
589
590 static int skl_buf_trans_num_entries(enum port port, int n_entries)
591 {
592 /* Only DDIA and DDIE can select the 10th register with DP */
593 if (port == PORT_A || port == PORT_E)
594 return min(n_entries, 10);
595 else
596 return min(n_entries, 9);
597 }
598
599 static const struct ddi_buf_trans *
600 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
601 enum port port, int *n_entries)
602 {
603 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
604 const struct ddi_buf_trans *ddi_translations =
605 kbl_get_buf_trans_dp(dev_priv, n_entries);
606 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
607 return ddi_translations;
608 } else if (IS_SKYLAKE(dev_priv)) {
609 const struct ddi_buf_trans *ddi_translations =
610 skl_get_buf_trans_dp(dev_priv, n_entries);
611 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
612 return ddi_translations;
613 } else if (IS_BROADWELL(dev_priv)) {
614 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
615 return bdw_ddi_translations_dp;
616 } else if (IS_HASWELL(dev_priv)) {
617 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
618 return hsw_ddi_translations_dp;
619 }
620
621 *n_entries = 0;
622 return NULL;
623 }
624
625 static const struct ddi_buf_trans *
626 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
627 enum port port, int *n_entries)
628 {
629 if (IS_GEN9_BC(dev_priv)) {
630 const struct ddi_buf_trans *ddi_translations =
631 skl_get_buf_trans_edp(dev_priv, n_entries);
632 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
633 return ddi_translations;
634 } else if (IS_BROADWELL(dev_priv)) {
635 return bdw_get_buf_trans_edp(dev_priv, n_entries);
636 } else if (IS_HASWELL(dev_priv)) {
637 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
638 return hsw_ddi_translations_dp;
639 }
640
641 *n_entries = 0;
642 return NULL;
643 }
644
645 static const struct ddi_buf_trans *
646 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
647 int *n_entries)
648 {
649 if (IS_BROADWELL(dev_priv)) {
650 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
651 return bdw_ddi_translations_fdi;
652 } else if (IS_HASWELL(dev_priv)) {
653 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
654 return hsw_ddi_translations_fdi;
655 }
656
657 *n_entries = 0;
658 return NULL;
659 }
660
661 static const struct ddi_buf_trans *
662 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
663 int *n_entries)
664 {
665 if (IS_GEN9_BC(dev_priv)) {
666 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
667 } else if (IS_BROADWELL(dev_priv)) {
668 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
669 return bdw_ddi_translations_hdmi;
670 } else if (IS_HASWELL(dev_priv)) {
671 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
672 return hsw_ddi_translations_hdmi;
673 }
674
675 *n_entries = 0;
676 return NULL;
677 }
678
679 static const struct bxt_ddi_buf_trans *
680 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
681 {
682 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
683 return bxt_ddi_translations_dp;
684 }
685
686 static const struct bxt_ddi_buf_trans *
687 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
688 {
689 if (dev_priv->vbt.edp.low_vswing) {
690 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
691 return bxt_ddi_translations_edp;
692 }
693
694 return bxt_get_buf_trans_dp(dev_priv, n_entries);
695 }
696
697 static const struct bxt_ddi_buf_trans *
698 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
699 {
700 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
701 return bxt_ddi_translations_hdmi;
702 }
703
704 static const struct cnl_ddi_buf_trans *
705 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
706 {
707 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
708
709 if (voltage == VOLTAGE_INFO_0_85V) {
710 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
711 return cnl_ddi_translations_hdmi_0_85V;
712 } else if (voltage == VOLTAGE_INFO_0_95V) {
713 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
714 return cnl_ddi_translations_hdmi_0_95V;
715 } else if (voltage == VOLTAGE_INFO_1_05V) {
716 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
717 return cnl_ddi_translations_hdmi_1_05V;
718 } else {
719 *n_entries = 1; /* shut up gcc */
720 MISSING_CASE(voltage);
721 }
722 return NULL;
723 }
724
725 static const struct cnl_ddi_buf_trans *
726 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
727 {
728 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
729
730 if (voltage == VOLTAGE_INFO_0_85V) {
731 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
732 return cnl_ddi_translations_dp_0_85V;
733 } else if (voltage == VOLTAGE_INFO_0_95V) {
734 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
735 return cnl_ddi_translations_dp_0_95V;
736 } else if (voltage == VOLTAGE_INFO_1_05V) {
737 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
738 return cnl_ddi_translations_dp_1_05V;
739 } else {
740 *n_entries = 1; /* shut up gcc */
741 MISSING_CASE(voltage);
742 }
743 return NULL;
744 }
745
746 static const struct cnl_ddi_buf_trans *
747 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
748 {
749 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
750
751 if (dev_priv->vbt.edp.low_vswing) {
752 if (voltage == VOLTAGE_INFO_0_85V) {
753 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
754 return cnl_ddi_translations_edp_0_85V;
755 } else if (voltage == VOLTAGE_INFO_0_95V) {
756 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
757 return cnl_ddi_translations_edp_0_95V;
758 } else if (voltage == VOLTAGE_INFO_1_05V) {
759 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
760 return cnl_ddi_translations_edp_1_05V;
761 } else {
762 *n_entries = 1; /* shut up gcc */
763 MISSING_CASE(voltage);
764 }
765 return NULL;
766 } else {
767 return cnl_get_buf_trans_dp(dev_priv, n_entries);
768 }
769 }
770
771 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
772 {
773 int n_entries, level, default_entry;
774
775 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
776
777 if (IS_CANNONLAKE(dev_priv)) {
778 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
779 default_entry = n_entries - 1;
780 } else if (IS_GEN9_LP(dev_priv)) {
781 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
782 default_entry = n_entries - 1;
783 } else if (IS_GEN9_BC(dev_priv)) {
784 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
785 default_entry = 8;
786 } else if (IS_BROADWELL(dev_priv)) {
787 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
788 default_entry = 7;
789 } else if (IS_HASWELL(dev_priv)) {
790 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
791 default_entry = 6;
792 } else {
793 WARN(1, "ddi translation table missing\n");
794 return 0;
795 }
796
797 /* Choose a good default if VBT is badly populated */
798 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
799 level = default_entry;
800
801 if (WARN_ON_ONCE(n_entries == 0))
802 return 0;
803 if (WARN_ON_ONCE(level >= n_entries))
804 level = n_entries - 1;
805
806 return level;
807 }
808
809 /*
810 * Starting with Haswell, DDI port buffers must be programmed with correct
811 * values in advance. This function programs the correct values for
812 * DP/eDP/FDI use cases.
813 */
814 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
815 {
816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
817 u32 iboost_bit = 0;
818 int i, n_entries;
819 enum port port = intel_ddi_get_encoder_port(encoder);
820 const struct ddi_buf_trans *ddi_translations;
821
822 switch (encoder->type) {
823 case INTEL_OUTPUT_EDP:
824 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
825 &n_entries);
826 break;
827 case INTEL_OUTPUT_DP:
828 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
829 &n_entries);
830 break;
831 case INTEL_OUTPUT_ANALOG:
832 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
833 &n_entries);
834 break;
835 default:
836 MISSING_CASE(encoder->type);
837 return;
838 }
839
840 /* If we're boosting the current, set bit 31 of trans1 */
841 if (IS_GEN9_BC(dev_priv) &&
842 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
843 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
844
845 for (i = 0; i < n_entries; i++) {
846 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
847 ddi_translations[i].trans1 | iboost_bit);
848 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
849 ddi_translations[i].trans2);
850 }
851 }
852
853 /*
854 * Starting with Haswell, DDI port buffers must be programmed with correct
855 * values in advance. This function programs the correct values for
856 * HDMI/DVI use cases.
857 */
858 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
859 int level)
860 {
861 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
862 u32 iboost_bit = 0;
863 int n_entries;
864 enum port port = intel_ddi_get_encoder_port(encoder);
865 const struct ddi_buf_trans *ddi_translations;
866
867 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
868
869 if (WARN_ON_ONCE(!ddi_translations))
870 return;
871 if (WARN_ON_ONCE(level >= n_entries))
872 level = n_entries - 1;
873
874 /* If we're boosting the current, set bit 31 of trans1 */
875 if (IS_GEN9_BC(dev_priv) &&
876 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
877 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
878
879 /* Entry 9 is for HDMI: */
880 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
881 ddi_translations[level].trans1 | iboost_bit);
882 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
883 ddi_translations[level].trans2);
884 }
885
886 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
887 enum port port)
888 {
889 i915_reg_t reg = DDI_BUF_CTL(port);
890 int i;
891
892 for (i = 0; i < 16; i++) {
893 udelay(1);
894 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
895 return;
896 }
897 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
898 }
899
900 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
901 {
902 switch (pll->id) {
903 case DPLL_ID_WRPLL1:
904 return PORT_CLK_SEL_WRPLL1;
905 case DPLL_ID_WRPLL2:
906 return PORT_CLK_SEL_WRPLL2;
907 case DPLL_ID_SPLL:
908 return PORT_CLK_SEL_SPLL;
909 case DPLL_ID_LCPLL_810:
910 return PORT_CLK_SEL_LCPLL_810;
911 case DPLL_ID_LCPLL_1350:
912 return PORT_CLK_SEL_LCPLL_1350;
913 case DPLL_ID_LCPLL_2700:
914 return PORT_CLK_SEL_LCPLL_2700;
915 default:
916 MISSING_CASE(pll->id);
917 return PORT_CLK_SEL_NONE;
918 }
919 }
920
921 /* Starting with Haswell, different DDI ports can work in FDI mode for
922 * connection to the PCH-located connectors. For this, it is necessary to train
923 * both the DDI port and PCH receiver for the desired DDI buffer settings.
924 *
925 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
926 * please note that when FDI mode is active on DDI E, it shares 2 lines with
927 * DDI A (which is used for eDP)
928 */
929
930 void hsw_fdi_link_train(struct intel_crtc *crtc,
931 const struct intel_crtc_state *crtc_state)
932 {
933 struct drm_device *dev = crtc->base.dev;
934 struct drm_i915_private *dev_priv = to_i915(dev);
935 struct intel_encoder *encoder;
936 u32 temp, i, rx_ctl_val, ddi_pll_sel;
937
938 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
939 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
940 intel_prepare_dp_ddi_buffers(encoder);
941 }
942
943 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
944 * mode set "sequence for CRT port" document:
945 * - TP1 to TP2 time with the default value
946 * - FDI delay to 90h
947 *
948 * WaFDIAutoLinkSetTimingOverrride:hsw
949 */
950 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
951 FDI_RX_PWRDN_LANE0_VAL(2) |
952 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
953
954 /* Enable the PCH Receiver FDI PLL */
955 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
956 FDI_RX_PLL_ENABLE |
957 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
958 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
959 POSTING_READ(FDI_RX_CTL(PIPE_A));
960 udelay(220);
961
962 /* Switch from Rawclk to PCDclk */
963 rx_ctl_val |= FDI_PCDCLK;
964 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
965
966 /* Configure Port Clock Select */
967 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
968 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
969 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
970
971 /* Start the training iterating through available voltages and emphasis,
972 * testing each value twice. */
973 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
974 /* Configure DP_TP_CTL with auto-training */
975 I915_WRITE(DP_TP_CTL(PORT_E),
976 DP_TP_CTL_FDI_AUTOTRAIN |
977 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
978 DP_TP_CTL_LINK_TRAIN_PAT1 |
979 DP_TP_CTL_ENABLE);
980
981 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
982 * DDI E does not support port reversal, the functionality is
983 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
984 * port reversal bit */
985 I915_WRITE(DDI_BUF_CTL(PORT_E),
986 DDI_BUF_CTL_ENABLE |
987 ((crtc_state->fdi_lanes - 1) << 1) |
988 DDI_BUF_TRANS_SELECT(i / 2));
989 POSTING_READ(DDI_BUF_CTL(PORT_E));
990
991 udelay(600);
992
993 /* Program PCH FDI Receiver TU */
994 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
995
996 /* Enable PCH FDI Receiver with auto-training */
997 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
998 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
999 POSTING_READ(FDI_RX_CTL(PIPE_A));
1000
1001 /* Wait for FDI receiver lane calibration */
1002 udelay(30);
1003
1004 /* Unset FDI_RX_MISC pwrdn lanes */
1005 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1006 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1007 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1008 POSTING_READ(FDI_RX_MISC(PIPE_A));
1009
1010 /* Wait for FDI auto training time */
1011 udelay(5);
1012
1013 temp = I915_READ(DP_TP_STATUS(PORT_E));
1014 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1015 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1016 break;
1017 }
1018
1019 /*
1020 * Leave things enabled even if we failed to train FDI.
1021 * Results in less fireworks from the state checker.
1022 */
1023 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1024 DRM_ERROR("FDI link training failed!\n");
1025 break;
1026 }
1027
1028 rx_ctl_val &= ~FDI_RX_ENABLE;
1029 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1030 POSTING_READ(FDI_RX_CTL(PIPE_A));
1031
1032 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1033 temp &= ~DDI_BUF_CTL_ENABLE;
1034 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1035 POSTING_READ(DDI_BUF_CTL(PORT_E));
1036
1037 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1038 temp = I915_READ(DP_TP_CTL(PORT_E));
1039 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1040 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1041 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1042 POSTING_READ(DP_TP_CTL(PORT_E));
1043
1044 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1045
1046 /* Reset FDI_RX_MISC pwrdn lanes */
1047 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1048 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1049 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1050 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1051 POSTING_READ(FDI_RX_MISC(PIPE_A));
1052 }
1053
1054 /* Enable normal pixel sending for FDI */
1055 I915_WRITE(DP_TP_CTL(PORT_E),
1056 DP_TP_CTL_FDI_AUTOTRAIN |
1057 DP_TP_CTL_LINK_TRAIN_NORMAL |
1058 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1059 DP_TP_CTL_ENABLE);
1060 }
1061
1062 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1063 {
1064 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1065 struct intel_digital_port *intel_dig_port =
1066 enc_to_dig_port(&encoder->base);
1067
1068 intel_dp->DP = intel_dig_port->saved_port_bits |
1069 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1070 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1071 }
1072
1073 static struct intel_encoder *
1074 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1075 {
1076 struct drm_device *dev = crtc->base.dev;
1077 struct intel_encoder *encoder, *ret = NULL;
1078 int num_encoders = 0;
1079
1080 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1081 ret = encoder;
1082 num_encoders++;
1083 }
1084
1085 if (num_encoders != 1)
1086 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1087 pipe_name(crtc->pipe));
1088
1089 BUG_ON(ret == NULL);
1090 return ret;
1091 }
1092
1093 /* Finds the only possible encoder associated with the given CRTC. */
1094 struct intel_encoder *
1095 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
1096 {
1097 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1098 struct intel_encoder *ret = NULL;
1099 struct drm_atomic_state *state;
1100 struct drm_connector *connector;
1101 struct drm_connector_state *connector_state;
1102 int num_encoders = 0;
1103 int i;
1104
1105 state = crtc_state->base.state;
1106
1107 for_each_new_connector_in_state(state, connector, connector_state, i) {
1108 if (connector_state->crtc != crtc_state->base.crtc)
1109 continue;
1110
1111 ret = to_intel_encoder(connector_state->best_encoder);
1112 num_encoders++;
1113 }
1114
1115 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1116 pipe_name(crtc->pipe));
1117
1118 BUG_ON(ret == NULL);
1119 return ret;
1120 }
1121
1122 #define LC_FREQ 2700
1123
1124 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1125 i915_reg_t reg)
1126 {
1127 int refclk = LC_FREQ;
1128 int n, p, r;
1129 u32 wrpll;
1130
1131 wrpll = I915_READ(reg);
1132 switch (wrpll & WRPLL_PLL_REF_MASK) {
1133 case WRPLL_PLL_SSC:
1134 case WRPLL_PLL_NON_SSC:
1135 /*
1136 * We could calculate spread here, but our checking
1137 * code only cares about 5% accuracy, and spread is a max of
1138 * 0.5% downspread.
1139 */
1140 refclk = 135;
1141 break;
1142 case WRPLL_PLL_LCPLL:
1143 refclk = LC_FREQ;
1144 break;
1145 default:
1146 WARN(1, "bad wrpll refclk\n");
1147 return 0;
1148 }
1149
1150 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1151 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1152 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1153
1154 /* Convert to KHz, p & r have a fixed point portion */
1155 return (refclk * n * 100) / (p * r);
1156 }
1157
1158 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1159 enum intel_dpll_id pll_id)
1160 {
1161 i915_reg_t cfgcr1_reg, cfgcr2_reg;
1162 uint32_t cfgcr1_val, cfgcr2_val;
1163 uint32_t p0, p1, p2, dco_freq;
1164
1165 cfgcr1_reg = DPLL_CFGCR1(pll_id);
1166 cfgcr2_reg = DPLL_CFGCR2(pll_id);
1167
1168 cfgcr1_val = I915_READ(cfgcr1_reg);
1169 cfgcr2_val = I915_READ(cfgcr2_reg);
1170
1171 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1172 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1173
1174 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1175 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1176 else
1177 p1 = 1;
1178
1179
1180 switch (p0) {
1181 case DPLL_CFGCR2_PDIV_1:
1182 p0 = 1;
1183 break;
1184 case DPLL_CFGCR2_PDIV_2:
1185 p0 = 2;
1186 break;
1187 case DPLL_CFGCR2_PDIV_3:
1188 p0 = 3;
1189 break;
1190 case DPLL_CFGCR2_PDIV_7:
1191 p0 = 7;
1192 break;
1193 }
1194
1195 switch (p2) {
1196 case DPLL_CFGCR2_KDIV_5:
1197 p2 = 5;
1198 break;
1199 case DPLL_CFGCR2_KDIV_2:
1200 p2 = 2;
1201 break;
1202 case DPLL_CFGCR2_KDIV_3:
1203 p2 = 3;
1204 break;
1205 case DPLL_CFGCR2_KDIV_1:
1206 p2 = 1;
1207 break;
1208 }
1209
1210 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1211
1212 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1213 1000) / 0x8000;
1214
1215 return dco_freq / (p0 * p1 * p2 * 5);
1216 }
1217
1218 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1219 enum intel_dpll_id pll_id)
1220 {
1221 uint32_t cfgcr0, cfgcr1;
1222 uint32_t p0, p1, p2, dco_freq, ref_clock;
1223
1224 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1225 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1226
1227 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1228 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1229
1230 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1231 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1232 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1233 else
1234 p1 = 1;
1235
1236
1237 switch (p0) {
1238 case DPLL_CFGCR1_PDIV_2:
1239 p0 = 2;
1240 break;
1241 case DPLL_CFGCR1_PDIV_3:
1242 p0 = 3;
1243 break;
1244 case DPLL_CFGCR1_PDIV_5:
1245 p0 = 5;
1246 break;
1247 case DPLL_CFGCR1_PDIV_7:
1248 p0 = 7;
1249 break;
1250 }
1251
1252 switch (p2) {
1253 case DPLL_CFGCR1_KDIV_1:
1254 p2 = 1;
1255 break;
1256 case DPLL_CFGCR1_KDIV_2:
1257 p2 = 2;
1258 break;
1259 case DPLL_CFGCR1_KDIV_4:
1260 p2 = 4;
1261 break;
1262 }
1263
1264 ref_clock = dev_priv->cdclk.hw.ref;
1265
1266 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1267
1268 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1269 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1270
1271 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1272 return 0;
1273
1274 return dco_freq / (p0 * p1 * p2 * 5);
1275 }
1276
1277 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1278 {
1279 int dotclock;
1280
1281 if (pipe_config->has_pch_encoder)
1282 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1283 &pipe_config->fdi_m_n);
1284 else if (intel_crtc_has_dp_encoder(pipe_config))
1285 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1286 &pipe_config->dp_m_n);
1287 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1288 dotclock = pipe_config->port_clock * 2 / 3;
1289 else
1290 dotclock = pipe_config->port_clock;
1291
1292 if (pipe_config->ycbcr420)
1293 dotclock *= 2;
1294
1295 if (pipe_config->pixel_multiplier)
1296 dotclock /= pipe_config->pixel_multiplier;
1297
1298 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1299 }
1300
1301 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1302 struct intel_crtc_state *pipe_config)
1303 {
1304 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1305 int link_clock = 0;
1306 uint32_t cfgcr0;
1307 enum intel_dpll_id pll_id;
1308
1309 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1310
1311 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1312
1313 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1314 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1315 } else {
1316 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1317
1318 switch (link_clock) {
1319 case DPLL_CFGCR0_LINK_RATE_810:
1320 link_clock = 81000;
1321 break;
1322 case DPLL_CFGCR0_LINK_RATE_1080:
1323 link_clock = 108000;
1324 break;
1325 case DPLL_CFGCR0_LINK_RATE_1350:
1326 link_clock = 135000;
1327 break;
1328 case DPLL_CFGCR0_LINK_RATE_1620:
1329 link_clock = 162000;
1330 break;
1331 case DPLL_CFGCR0_LINK_RATE_2160:
1332 link_clock = 216000;
1333 break;
1334 case DPLL_CFGCR0_LINK_RATE_2700:
1335 link_clock = 270000;
1336 break;
1337 case DPLL_CFGCR0_LINK_RATE_3240:
1338 link_clock = 324000;
1339 break;
1340 case DPLL_CFGCR0_LINK_RATE_4050:
1341 link_clock = 405000;
1342 break;
1343 default:
1344 WARN(1, "Unsupported link rate\n");
1345 break;
1346 }
1347 link_clock *= 2;
1348 }
1349
1350 pipe_config->port_clock = link_clock;
1351
1352 ddi_dotclock_get(pipe_config);
1353 }
1354
1355 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1356 struct intel_crtc_state *pipe_config)
1357 {
1358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1359 int link_clock = 0;
1360 uint32_t dpll_ctl1;
1361 enum intel_dpll_id pll_id;
1362
1363 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1364
1365 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1366
1367 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1368 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1369 } else {
1370 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1371 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1372
1373 switch (link_clock) {
1374 case DPLL_CTRL1_LINK_RATE_810:
1375 link_clock = 81000;
1376 break;
1377 case DPLL_CTRL1_LINK_RATE_1080:
1378 link_clock = 108000;
1379 break;
1380 case DPLL_CTRL1_LINK_RATE_1350:
1381 link_clock = 135000;
1382 break;
1383 case DPLL_CTRL1_LINK_RATE_1620:
1384 link_clock = 162000;
1385 break;
1386 case DPLL_CTRL1_LINK_RATE_2160:
1387 link_clock = 216000;
1388 break;
1389 case DPLL_CTRL1_LINK_RATE_2700:
1390 link_clock = 270000;
1391 break;
1392 default:
1393 WARN(1, "Unsupported link rate\n");
1394 break;
1395 }
1396 link_clock *= 2;
1397 }
1398
1399 pipe_config->port_clock = link_clock;
1400
1401 ddi_dotclock_get(pipe_config);
1402 }
1403
1404 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1405 struct intel_crtc_state *pipe_config)
1406 {
1407 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1408 int link_clock = 0;
1409 u32 val, pll;
1410
1411 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1412 switch (val & PORT_CLK_SEL_MASK) {
1413 case PORT_CLK_SEL_LCPLL_810:
1414 link_clock = 81000;
1415 break;
1416 case PORT_CLK_SEL_LCPLL_1350:
1417 link_clock = 135000;
1418 break;
1419 case PORT_CLK_SEL_LCPLL_2700:
1420 link_clock = 270000;
1421 break;
1422 case PORT_CLK_SEL_WRPLL1:
1423 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1424 break;
1425 case PORT_CLK_SEL_WRPLL2:
1426 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1427 break;
1428 case PORT_CLK_SEL_SPLL:
1429 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1430 if (pll == SPLL_PLL_FREQ_810MHz)
1431 link_clock = 81000;
1432 else if (pll == SPLL_PLL_FREQ_1350MHz)
1433 link_clock = 135000;
1434 else if (pll == SPLL_PLL_FREQ_2700MHz)
1435 link_clock = 270000;
1436 else {
1437 WARN(1, "bad spll freq\n");
1438 return;
1439 }
1440 break;
1441 default:
1442 WARN(1, "bad port clock sel\n");
1443 return;
1444 }
1445
1446 pipe_config->port_clock = link_clock * 2;
1447
1448 ddi_dotclock_get(pipe_config);
1449 }
1450
1451 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1452 enum intel_dpll_id pll_id)
1453 {
1454 struct intel_shared_dpll *pll;
1455 struct intel_dpll_hw_state *state;
1456 struct dpll clock;
1457
1458 /* For DDI ports we always use a shared PLL. */
1459 if (WARN_ON(pll_id == DPLL_ID_PRIVATE))
1460 return 0;
1461
1462 pll = &dev_priv->shared_dplls[pll_id];
1463 state = &pll->state.hw_state;
1464
1465 clock.m1 = 2;
1466 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1467 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1468 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1469 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1470 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1471 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1472
1473 return chv_calc_dpll_params(100000, &clock);
1474 }
1475
1476 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1477 struct intel_crtc_state *pipe_config)
1478 {
1479 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1480 enum port port = intel_ddi_get_encoder_port(encoder);
1481 enum intel_dpll_id pll_id = port;
1482
1483 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, pll_id);
1484
1485 ddi_dotclock_get(pipe_config);
1486 }
1487
1488 void intel_ddi_clock_get(struct intel_encoder *encoder,
1489 struct intel_crtc_state *pipe_config)
1490 {
1491 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1492
1493 if (INTEL_GEN(dev_priv) <= 8)
1494 hsw_ddi_clock_get(encoder, pipe_config);
1495 else if (IS_GEN9_BC(dev_priv))
1496 skl_ddi_clock_get(encoder, pipe_config);
1497 else if (IS_GEN9_LP(dev_priv))
1498 bxt_ddi_clock_get(encoder, pipe_config);
1499 else if (IS_CANNONLAKE(dev_priv))
1500 cnl_ddi_clock_get(encoder, pipe_config);
1501 }
1502
1503 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1504 {
1505 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1506 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1507 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1508 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1509 int type = encoder->type;
1510 uint32_t temp;
1511
1512 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1513 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1514
1515 temp = TRANS_MSA_SYNC_CLK;
1516 switch (crtc_state->pipe_bpp) {
1517 case 18:
1518 temp |= TRANS_MSA_6_BPC;
1519 break;
1520 case 24:
1521 temp |= TRANS_MSA_8_BPC;
1522 break;
1523 case 30:
1524 temp |= TRANS_MSA_10_BPC;
1525 break;
1526 case 36:
1527 temp |= TRANS_MSA_12_BPC;
1528 break;
1529 default:
1530 BUG();
1531 }
1532 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1533 }
1534 }
1535
1536 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1537 bool state)
1538 {
1539 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1540 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1541 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1542 uint32_t temp;
1543 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1544 if (state == true)
1545 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1546 else
1547 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1548 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1549 }
1550
1551 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1552 {
1553 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1554 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1555 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1556 enum pipe pipe = crtc->pipe;
1557 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1558 enum port port = intel_ddi_get_encoder_port(encoder);
1559 int type = encoder->type;
1560 uint32_t temp;
1561
1562 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1563 temp = TRANS_DDI_FUNC_ENABLE;
1564 temp |= TRANS_DDI_SELECT_PORT(port);
1565
1566 switch (crtc_state->pipe_bpp) {
1567 case 18:
1568 temp |= TRANS_DDI_BPC_6;
1569 break;
1570 case 24:
1571 temp |= TRANS_DDI_BPC_8;
1572 break;
1573 case 30:
1574 temp |= TRANS_DDI_BPC_10;
1575 break;
1576 case 36:
1577 temp |= TRANS_DDI_BPC_12;
1578 break;
1579 default:
1580 BUG();
1581 }
1582
1583 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1584 temp |= TRANS_DDI_PVSYNC;
1585 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1586 temp |= TRANS_DDI_PHSYNC;
1587
1588 if (cpu_transcoder == TRANSCODER_EDP) {
1589 switch (pipe) {
1590 case PIPE_A:
1591 /* On Haswell, can only use the always-on power well for
1592 * eDP when not using the panel fitter, and when not
1593 * using motion blur mitigation (which we don't
1594 * support). */
1595 if (IS_HASWELL(dev_priv) &&
1596 (crtc_state->pch_pfit.enabled ||
1597 crtc_state->pch_pfit.force_thru))
1598 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1599 else
1600 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1601 break;
1602 case PIPE_B:
1603 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1604 break;
1605 case PIPE_C:
1606 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1607 break;
1608 default:
1609 BUG();
1610 break;
1611 }
1612 }
1613
1614 if (type == INTEL_OUTPUT_HDMI) {
1615 if (crtc_state->has_hdmi_sink)
1616 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1617 else
1618 temp |= TRANS_DDI_MODE_SELECT_DVI;
1619
1620 if (crtc_state->hdmi_scrambling)
1621 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1622 if (crtc_state->hdmi_high_tmds_clock_ratio)
1623 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1624 } else if (type == INTEL_OUTPUT_ANALOG) {
1625 temp |= TRANS_DDI_MODE_SELECT_FDI;
1626 temp |= (crtc_state->fdi_lanes - 1) << 1;
1627 } else if (type == INTEL_OUTPUT_DP ||
1628 type == INTEL_OUTPUT_EDP) {
1629 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1630 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1631 } else if (type == INTEL_OUTPUT_DP_MST) {
1632 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1633 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1634 } else {
1635 WARN(1, "Invalid encoder type %d for pipe %c\n",
1636 encoder->type, pipe_name(pipe));
1637 }
1638
1639 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1640 }
1641
1642 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1643 enum transcoder cpu_transcoder)
1644 {
1645 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1646 uint32_t val = I915_READ(reg);
1647
1648 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1649 val |= TRANS_DDI_PORT_NONE;
1650 I915_WRITE(reg, val);
1651 }
1652
1653 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1654 {
1655 struct drm_device *dev = intel_connector->base.dev;
1656 struct drm_i915_private *dev_priv = to_i915(dev);
1657 struct intel_encoder *encoder = intel_connector->encoder;
1658 int type = intel_connector->base.connector_type;
1659 enum port port = intel_ddi_get_encoder_port(encoder);
1660 enum pipe pipe = 0;
1661 enum transcoder cpu_transcoder;
1662 uint32_t tmp;
1663 bool ret;
1664
1665 if (!intel_display_power_get_if_enabled(dev_priv,
1666 encoder->power_domain))
1667 return false;
1668
1669 if (!encoder->get_hw_state(encoder, &pipe)) {
1670 ret = false;
1671 goto out;
1672 }
1673
1674 if (port == PORT_A)
1675 cpu_transcoder = TRANSCODER_EDP;
1676 else
1677 cpu_transcoder = (enum transcoder) pipe;
1678
1679 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1680
1681 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1682 case TRANS_DDI_MODE_SELECT_HDMI:
1683 case TRANS_DDI_MODE_SELECT_DVI:
1684 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1685 break;
1686
1687 case TRANS_DDI_MODE_SELECT_DP_SST:
1688 ret = type == DRM_MODE_CONNECTOR_eDP ||
1689 type == DRM_MODE_CONNECTOR_DisplayPort;
1690 break;
1691
1692 case TRANS_DDI_MODE_SELECT_DP_MST:
1693 /* if the transcoder is in MST state then
1694 * connector isn't connected */
1695 ret = false;
1696 break;
1697
1698 case TRANS_DDI_MODE_SELECT_FDI:
1699 ret = type == DRM_MODE_CONNECTOR_VGA;
1700 break;
1701
1702 default:
1703 ret = false;
1704 break;
1705 }
1706
1707 out:
1708 intel_display_power_put(dev_priv, encoder->power_domain);
1709
1710 return ret;
1711 }
1712
1713 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1714 enum pipe *pipe)
1715 {
1716 struct drm_device *dev = encoder->base.dev;
1717 struct drm_i915_private *dev_priv = to_i915(dev);
1718 enum port port = intel_ddi_get_encoder_port(encoder);
1719 u32 tmp;
1720 int i;
1721 bool ret;
1722
1723 if (!intel_display_power_get_if_enabled(dev_priv,
1724 encoder->power_domain))
1725 return false;
1726
1727 ret = false;
1728
1729 tmp = I915_READ(DDI_BUF_CTL(port));
1730
1731 if (!(tmp & DDI_BUF_CTL_ENABLE))
1732 goto out;
1733
1734 if (port == PORT_A) {
1735 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1736
1737 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1738 case TRANS_DDI_EDP_INPUT_A_ON:
1739 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1740 *pipe = PIPE_A;
1741 break;
1742 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1743 *pipe = PIPE_B;
1744 break;
1745 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1746 *pipe = PIPE_C;
1747 break;
1748 }
1749
1750 ret = true;
1751
1752 goto out;
1753 }
1754
1755 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1756 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1757
1758 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1759 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1760 TRANS_DDI_MODE_SELECT_DP_MST)
1761 goto out;
1762
1763 *pipe = i;
1764 ret = true;
1765
1766 goto out;
1767 }
1768 }
1769
1770 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1771
1772 out:
1773 if (ret && IS_GEN9_LP(dev_priv)) {
1774 tmp = I915_READ(BXT_PHY_CTL(port));
1775 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1776 BXT_PHY_LANE_POWERDOWN_ACK |
1777 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1778 DRM_ERROR("Port %c enabled but PHY powered down? "
1779 "(PHY_CTL %08x)\n", port_name(port), tmp);
1780 }
1781
1782 intel_display_power_put(dev_priv, encoder->power_domain);
1783
1784 return ret;
1785 }
1786
1787 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1788 {
1789 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1790 enum pipe pipe;
1791
1792 if (intel_ddi_get_hw_state(encoder, &pipe))
1793 return BIT_ULL(dig_port->ddi_io_power_domain);
1794
1795 return 0;
1796 }
1797
1798 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1799 {
1800 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1801 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1802 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1803 enum port port = intel_ddi_get_encoder_port(encoder);
1804 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1805
1806 if (cpu_transcoder != TRANSCODER_EDP)
1807 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1808 TRANS_CLK_SEL_PORT(port));
1809 }
1810
1811 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1812 {
1813 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1814 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1815
1816 if (cpu_transcoder != TRANSCODER_EDP)
1817 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1818 TRANS_CLK_SEL_DISABLED);
1819 }
1820
1821 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1822 enum port port, uint8_t iboost)
1823 {
1824 u32 tmp;
1825
1826 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1827 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1828 if (iboost)
1829 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1830 else
1831 tmp |= BALANCE_LEG_DISABLE(port);
1832 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1833 }
1834
1835 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1836 int level, enum intel_output_type type)
1837 {
1838 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1839 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
1840 enum port port = intel_dig_port->port;
1841 uint8_t iboost;
1842
1843 if (type == INTEL_OUTPUT_HDMI)
1844 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1845 else
1846 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1847
1848 if (iboost == 0) {
1849 const struct ddi_buf_trans *ddi_translations;
1850 int n_entries;
1851
1852 if (type == INTEL_OUTPUT_HDMI)
1853 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1854 else if (type == INTEL_OUTPUT_EDP)
1855 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
1856 else
1857 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1858
1859 if (WARN_ON_ONCE(!ddi_translations))
1860 return;
1861 if (WARN_ON_ONCE(level >= n_entries))
1862 level = n_entries - 1;
1863
1864 iboost = ddi_translations[level].i_boost;
1865 }
1866
1867 /* Make sure that the requested I_boost is valid */
1868 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1869 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1870 return;
1871 }
1872
1873 _skl_ddi_set_iboost(dev_priv, port, iboost);
1874
1875 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1876 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1877 }
1878
1879 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
1880 int level, enum intel_output_type type)
1881 {
1882 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1883 const struct bxt_ddi_buf_trans *ddi_translations;
1884 enum port port = encoder->port;
1885 int n_entries;
1886
1887 if (type == INTEL_OUTPUT_HDMI)
1888 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
1889 else if (type == INTEL_OUTPUT_EDP)
1890 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
1891 else
1892 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
1893
1894 if (WARN_ON_ONCE(!ddi_translations))
1895 return;
1896 if (WARN_ON_ONCE(level >= n_entries))
1897 level = n_entries - 1;
1898
1899 bxt_ddi_phy_set_signal_level(dev_priv, port,
1900 ddi_translations[level].margin,
1901 ddi_translations[level].scale,
1902 ddi_translations[level].enable,
1903 ddi_translations[level].deemphasis);
1904 }
1905
1906 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1907 {
1908 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1909 enum port port = encoder->port;
1910 int n_entries;
1911
1912 if (IS_CANNONLAKE(dev_priv)) {
1913 if (encoder->type == INTEL_OUTPUT_EDP)
1914 cnl_get_buf_trans_edp(dev_priv, &n_entries);
1915 else
1916 cnl_get_buf_trans_dp(dev_priv, &n_entries);
1917 } else if (IS_GEN9_LP(dev_priv)) {
1918 if (encoder->type == INTEL_OUTPUT_EDP)
1919 bxt_get_buf_trans_edp(dev_priv, &n_entries);
1920 else
1921 bxt_get_buf_trans_dp(dev_priv, &n_entries);
1922 } else {
1923 if (encoder->type == INTEL_OUTPUT_EDP)
1924 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
1925 else
1926 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1927 }
1928
1929 if (WARN_ON(n_entries < 1))
1930 n_entries = 1;
1931 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1932 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1933
1934 return index_to_dp_signal_levels[n_entries - 1] &
1935 DP_TRAIN_VOLTAGE_SWING_MASK;
1936 }
1937
1938 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
1939 int level, enum intel_output_type type)
1940 {
1941 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1942 enum port port = intel_ddi_get_encoder_port(encoder);
1943 const struct cnl_ddi_buf_trans *ddi_translations;
1944 int n_entries, ln;
1945 u32 val;
1946
1947 if (type == INTEL_OUTPUT_HDMI)
1948 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
1949 else if (type == INTEL_OUTPUT_EDP)
1950 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
1951 else
1952 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
1953
1954 if (WARN_ON_ONCE(!ddi_translations))
1955 return;
1956 if (WARN_ON_ONCE(level >= n_entries))
1957 level = n_entries - 1;
1958
1959 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1960 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1961 val &= ~SCALING_MODE_SEL_MASK;
1962 val |= SCALING_MODE_SEL(2);
1963 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1964
1965 /* Program PORT_TX_DW2 */
1966 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1967 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1968 RCOMP_SCALAR_MASK);
1969 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1970 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1971 /* Rcomp scalar is fixed as 0x98 for every table entry */
1972 val |= RCOMP_SCALAR(0x98);
1973 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1974
1975 /* Program PORT_TX_DW4 */
1976 /* We cannot write to GRP. It would overrite individual loadgen */
1977 for (ln = 0; ln < 4; ln++) {
1978 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1979 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1980 CURSOR_COEFF_MASK);
1981 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1982 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1983 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1984 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1985 }
1986
1987 /* Program PORT_TX_DW5 */
1988 /* All DW5 values are fixed for every table entry */
1989 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1990 val &= ~RTERM_SELECT_MASK;
1991 val |= RTERM_SELECT(6);
1992 val |= TAP3_DISABLE;
1993 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1994
1995 /* Program PORT_TX_DW7 */
1996 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1997 val &= ~N_SCALAR_MASK;
1998 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1999 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2000 }
2001
2002 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2003 int level, enum intel_output_type type)
2004 {
2005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2006 enum port port = intel_ddi_get_encoder_port(encoder);
2007 int width, rate, ln;
2008 u32 val;
2009
2010 if (type == INTEL_OUTPUT_HDMI) {
2011 width = 4;
2012 rate = 0; /* Rate is always < than 6GHz for HDMI */
2013 } else {
2014 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2015
2016 width = intel_dp->lane_count;
2017 rate = intel_dp->link_rate;
2018 }
2019
2020 /*
2021 * 1. If port type is eDP or DP,
2022 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2023 * else clear to 0b.
2024 */
2025 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2026 if (type != INTEL_OUTPUT_HDMI)
2027 val |= COMMON_KEEPER_EN;
2028 else
2029 val &= ~COMMON_KEEPER_EN;
2030 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2031
2032 /* 2. Program loadgen select */
2033 /*
2034 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2035 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2036 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2037 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2038 */
2039 for (ln = 0; ln <= 3; ln++) {
2040 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2041 val &= ~LOADGEN_SELECT;
2042
2043 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2044 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2045 val |= LOADGEN_SELECT;
2046 }
2047 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2048 }
2049
2050 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2051 val = I915_READ(CNL_PORT_CL1CM_DW5);
2052 val |= SUS_CLOCK_CONFIG;
2053 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2054
2055 /* 4. Clear training enable to change swing values */
2056 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2057 val &= ~TX_TRAINING_EN;
2058 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2059
2060 /* 5. Program swing and de-emphasis */
2061 cnl_ddi_vswing_program(encoder, level, type);
2062
2063 /* 6. Set training enable to trigger update */
2064 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2065 val |= TX_TRAINING_EN;
2066 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2067 }
2068
2069 static uint32_t translate_signal_level(int signal_levels)
2070 {
2071 int i;
2072
2073 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2074 if (index_to_dp_signal_levels[i] == signal_levels)
2075 return i;
2076 }
2077
2078 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2079 signal_levels);
2080
2081 return 0;
2082 }
2083
2084 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2085 {
2086 uint8_t train_set = intel_dp->train_set[0];
2087 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2088 DP_TRAIN_PRE_EMPHASIS_MASK);
2089
2090 return translate_signal_level(signal_levels);
2091 }
2092
2093 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2094 {
2095 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2096 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2097 struct intel_encoder *encoder = &dport->base;
2098 int level = intel_ddi_dp_level(intel_dp);
2099
2100 if (IS_CANNONLAKE(dev_priv))
2101 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2102 else
2103 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2104
2105 return 0;
2106 }
2107
2108 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2109 {
2110 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2111 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2112 struct intel_encoder *encoder = &dport->base;
2113 int level = intel_ddi_dp_level(intel_dp);
2114
2115 if (IS_GEN9_BC(dev_priv))
2116 skl_ddi_set_iboost(encoder, level, encoder->type);
2117
2118 return DDI_BUF_TRANS_SELECT(level);
2119 }
2120
2121 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2122 const struct intel_shared_dpll *pll)
2123 {
2124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2125 enum port port = intel_ddi_get_encoder_port(encoder);
2126 uint32_t val;
2127
2128 if (WARN_ON(!pll))
2129 return;
2130
2131 if (IS_CANNONLAKE(dev_priv)) {
2132 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2133 val = I915_READ(DPCLKA_CFGCR0);
2134 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2135 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2136 I915_WRITE(DPCLKA_CFGCR0, val);
2137
2138 /*
2139 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2140 * This step and the step before must be done with separate
2141 * register writes.
2142 */
2143 val = I915_READ(DPCLKA_CFGCR0);
2144 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2145 I915_WRITE(DPCLKA_CFGCR0, val);
2146 } else if (IS_GEN9_BC(dev_priv)) {
2147 /* DDI -> PLL mapping */
2148 val = I915_READ(DPLL_CTRL2);
2149
2150 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2151 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2152 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
2153 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2154
2155 I915_WRITE(DPLL_CTRL2, val);
2156
2157 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2158 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2159 }
2160 }
2161
2162 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2163 {
2164 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2165 enum port port = intel_ddi_get_encoder_port(encoder);
2166
2167 if (IS_CANNONLAKE(dev_priv))
2168 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2169 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2170 else if (IS_GEN9_BC(dev_priv))
2171 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2172 DPLL_CTRL2_DDI_CLK_OFF(port));
2173 else if (INTEL_GEN(dev_priv) < 9)
2174 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2175 }
2176
2177 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2178 const struct intel_crtc_state *crtc_state,
2179 const struct drm_connector_state *conn_state)
2180 {
2181 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2182 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2183 enum port port = intel_ddi_get_encoder_port(encoder);
2184 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2185 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2186 int level = intel_ddi_dp_level(intel_dp);
2187
2188 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2189
2190 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2191 crtc_state->lane_count, is_mst);
2192
2193 intel_edp_panel_on(intel_dp);
2194
2195 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2196
2197 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2198
2199 if (IS_CANNONLAKE(dev_priv))
2200 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2201 else if (IS_GEN9_LP(dev_priv))
2202 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2203 else
2204 intel_prepare_dp_ddi_buffers(encoder);
2205
2206 intel_ddi_init_dp_buf_reg(encoder);
2207 if (!is_mst)
2208 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2209 intel_dp_start_link_train(intel_dp);
2210 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2211 intel_dp_stop_link_train(intel_dp);
2212 }
2213
2214 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2215 const struct intel_crtc_state *crtc_state,
2216 const struct drm_connector_state *conn_state)
2217 {
2218 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2219 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2221 enum port port = intel_ddi_get_encoder_port(encoder);
2222 int level = intel_ddi_hdmi_level(dev_priv, port);
2223 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2224
2225 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2226 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2227
2228 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2229
2230 if (IS_CANNONLAKE(dev_priv))
2231 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2232 else if (IS_GEN9_LP(dev_priv))
2233 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2234 else
2235 intel_prepare_hdmi_ddi_buffers(encoder, level);
2236
2237 if (IS_GEN9_BC(dev_priv))
2238 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2239
2240 intel_dig_port->set_infoframes(&encoder->base,
2241 crtc_state->has_infoframe,
2242 crtc_state, conn_state);
2243 }
2244
2245 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2246 const struct intel_crtc_state *crtc_state,
2247 const struct drm_connector_state *conn_state)
2248 {
2249 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2250 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2251 enum pipe pipe = crtc->pipe;
2252
2253 WARN_ON(crtc_state->has_pch_encoder);
2254
2255 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2256
2257 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2258 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2259 else
2260 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
2261 }
2262
2263 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2264 {
2265 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2266 enum port port = intel_ddi_get_encoder_port(encoder);
2267 bool wait = false;
2268 u32 val;
2269
2270 val = I915_READ(DDI_BUF_CTL(port));
2271 if (val & DDI_BUF_CTL_ENABLE) {
2272 val &= ~DDI_BUF_CTL_ENABLE;
2273 I915_WRITE(DDI_BUF_CTL(port), val);
2274 wait = true;
2275 }
2276
2277 val = I915_READ(DP_TP_CTL(port));
2278 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2279 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2280 I915_WRITE(DP_TP_CTL(port), val);
2281
2282 if (wait)
2283 intel_wait_ddi_buf_idle(dev_priv, port);
2284 }
2285
2286 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2287 const struct intel_crtc_state *old_crtc_state,
2288 const struct drm_connector_state *old_conn_state)
2289 {
2290 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2291 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2292 struct intel_dp *intel_dp = &dig_port->dp;
2293 /*
2294 * old_crtc_state and old_conn_state are NULL when called from
2295 * DP_MST. The main connector associated with this port is never
2296 * bound to a crtc for MST.
2297 */
2298 bool is_mst = !old_crtc_state;
2299
2300 /*
2301 * Power down sink before disabling the port, otherwise we end
2302 * up getting interrupts from the sink on detecting link loss.
2303 */
2304 if (!is_mst)
2305 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2306
2307 intel_disable_ddi_buf(encoder);
2308
2309 intel_edp_panel_vdd_on(intel_dp);
2310 intel_edp_panel_off(intel_dp);
2311
2312 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2313
2314 intel_ddi_clk_disable(encoder);
2315 }
2316
2317 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2318 const struct intel_crtc_state *old_crtc_state,
2319 const struct drm_connector_state *old_conn_state)
2320 {
2321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2322 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2323 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2324
2325 intel_disable_ddi_buf(encoder);
2326
2327 dig_port->set_infoframes(&encoder->base, false,
2328 old_crtc_state, old_conn_state);
2329
2330 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2331
2332 intel_ddi_clk_disable(encoder);
2333
2334 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2335 }
2336
2337 static void intel_ddi_post_disable(struct intel_encoder *encoder,
2338 const struct intel_crtc_state *old_crtc_state,
2339 const struct drm_connector_state *old_conn_state)
2340 {
2341 /*
2342 * old_crtc_state and old_conn_state are NULL when called from
2343 * DP_MST. The main connector associated with this port is never
2344 * bound to a crtc for MST.
2345 */
2346 if (old_crtc_state &&
2347 intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2348 intel_ddi_post_disable_hdmi(encoder,
2349 old_crtc_state, old_conn_state);
2350 else
2351 intel_ddi_post_disable_dp(encoder,
2352 old_crtc_state, old_conn_state);
2353 }
2354
2355 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2356 const struct intel_crtc_state *old_crtc_state,
2357 const struct drm_connector_state *old_conn_state)
2358 {
2359 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2360 uint32_t val;
2361
2362 /*
2363 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2364 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2365 * step 13 is the correct place for it. Step 18 is where it was
2366 * originally before the BUN.
2367 */
2368 val = I915_READ(FDI_RX_CTL(PIPE_A));
2369 val &= ~FDI_RX_ENABLE;
2370 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2371
2372 intel_disable_ddi_buf(encoder);
2373 intel_ddi_clk_disable(encoder);
2374
2375 val = I915_READ(FDI_RX_MISC(PIPE_A));
2376 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2377 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2378 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2379
2380 val = I915_READ(FDI_RX_CTL(PIPE_A));
2381 val &= ~FDI_PCDCLK;
2382 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2383
2384 val = I915_READ(FDI_RX_CTL(PIPE_A));
2385 val &= ~FDI_RX_PLL_ENABLE;
2386 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2387 }
2388
2389 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
2390 const struct intel_crtc_state *crtc_state,
2391 const struct drm_connector_state *conn_state)
2392 {
2393 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2394 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2395 enum port port = intel_ddi_get_encoder_port(encoder);
2396
2397 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2398 intel_dp_stop_link_train(intel_dp);
2399
2400 intel_edp_backlight_on(crtc_state, conn_state);
2401 intel_psr_enable(intel_dp, crtc_state);
2402 intel_edp_drrs_enable(intel_dp, crtc_state);
2403
2404 if (crtc_state->has_audio)
2405 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2406 }
2407
2408 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
2409 const struct intel_crtc_state *crtc_state,
2410 const struct drm_connector_state *conn_state)
2411 {
2412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2413 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2414 enum port port = intel_ddi_get_encoder_port(encoder);
2415
2416 intel_hdmi_handle_sink_scrambling(encoder,
2417 conn_state->connector,
2418 crtc_state->hdmi_high_tmds_clock_ratio,
2419 crtc_state->hdmi_scrambling);
2420
2421 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2422 * are ignored so nothing special needs to be done besides
2423 * enabling the port.
2424 */
2425 I915_WRITE(DDI_BUF_CTL(port),
2426 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
2427
2428 if (crtc_state->has_audio)
2429 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2430 }
2431
2432 static void intel_enable_ddi(struct intel_encoder *encoder,
2433 const struct intel_crtc_state *crtc_state,
2434 const struct drm_connector_state *conn_state)
2435 {
2436 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2437 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
2438 else
2439 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
2440 }
2441
2442 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
2443 const struct intel_crtc_state *old_crtc_state,
2444 const struct drm_connector_state *old_conn_state)
2445 {
2446 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2447
2448 if (old_crtc_state->has_audio)
2449 intel_audio_codec_disable(encoder);
2450
2451 intel_edp_drrs_disable(intel_dp, old_crtc_state);
2452 intel_psr_disable(intel_dp, old_crtc_state);
2453 intel_edp_backlight_off(old_conn_state);
2454 }
2455
2456 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
2457 const struct intel_crtc_state *old_crtc_state,
2458 const struct drm_connector_state *old_conn_state)
2459 {
2460 if (old_crtc_state->has_audio)
2461 intel_audio_codec_disable(encoder);
2462
2463 intel_hdmi_handle_sink_scrambling(encoder,
2464 old_conn_state->connector,
2465 false, false);
2466 }
2467
2468 static void intel_disable_ddi(struct intel_encoder *encoder,
2469 const struct intel_crtc_state *old_crtc_state,
2470 const struct drm_connector_state *old_conn_state)
2471 {
2472 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2473 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
2474 else
2475 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
2476 }
2477
2478 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2479 const struct intel_crtc_state *pipe_config,
2480 const struct drm_connector_state *conn_state)
2481 {
2482 uint8_t mask = pipe_config->lane_lat_optim_mask;
2483
2484 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2485 }
2486
2487 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2488 {
2489 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2490 struct drm_i915_private *dev_priv =
2491 to_i915(intel_dig_port->base.base.dev);
2492 enum port port = intel_dig_port->port;
2493 uint32_t val;
2494 bool wait = false;
2495
2496 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2497 val = I915_READ(DDI_BUF_CTL(port));
2498 if (val & DDI_BUF_CTL_ENABLE) {
2499 val &= ~DDI_BUF_CTL_ENABLE;
2500 I915_WRITE(DDI_BUF_CTL(port), val);
2501 wait = true;
2502 }
2503
2504 val = I915_READ(DP_TP_CTL(port));
2505 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2506 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2507 I915_WRITE(DP_TP_CTL(port), val);
2508 POSTING_READ(DP_TP_CTL(port));
2509
2510 if (wait)
2511 intel_wait_ddi_buf_idle(dev_priv, port);
2512 }
2513
2514 val = DP_TP_CTL_ENABLE |
2515 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2516 if (intel_dp->link_mst)
2517 val |= DP_TP_CTL_MODE_MST;
2518 else {
2519 val |= DP_TP_CTL_MODE_SST;
2520 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2521 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2522 }
2523 I915_WRITE(DP_TP_CTL(port), val);
2524 POSTING_READ(DP_TP_CTL(port));
2525
2526 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2527 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2528 POSTING_READ(DDI_BUF_CTL(port));
2529
2530 udelay(600);
2531 }
2532
2533 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2534 struct intel_crtc *intel_crtc)
2535 {
2536 u32 temp;
2537
2538 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2539 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2540 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2541 return true;
2542 }
2543 return false;
2544 }
2545
2546 void intel_ddi_get_config(struct intel_encoder *encoder,
2547 struct intel_crtc_state *pipe_config)
2548 {
2549 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2550 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2551 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2552 struct intel_digital_port *intel_dig_port;
2553 u32 temp, flags = 0;
2554
2555 /* XXX: DSI transcoder paranoia */
2556 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2557 return;
2558
2559 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2560 if (temp & TRANS_DDI_PHSYNC)
2561 flags |= DRM_MODE_FLAG_PHSYNC;
2562 else
2563 flags |= DRM_MODE_FLAG_NHSYNC;
2564 if (temp & TRANS_DDI_PVSYNC)
2565 flags |= DRM_MODE_FLAG_PVSYNC;
2566 else
2567 flags |= DRM_MODE_FLAG_NVSYNC;
2568
2569 pipe_config->base.adjusted_mode.flags |= flags;
2570
2571 switch (temp & TRANS_DDI_BPC_MASK) {
2572 case TRANS_DDI_BPC_6:
2573 pipe_config->pipe_bpp = 18;
2574 break;
2575 case TRANS_DDI_BPC_8:
2576 pipe_config->pipe_bpp = 24;
2577 break;
2578 case TRANS_DDI_BPC_10:
2579 pipe_config->pipe_bpp = 30;
2580 break;
2581 case TRANS_DDI_BPC_12:
2582 pipe_config->pipe_bpp = 36;
2583 break;
2584 default:
2585 break;
2586 }
2587
2588 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2589 case TRANS_DDI_MODE_SELECT_HDMI:
2590 pipe_config->has_hdmi_sink = true;
2591 intel_dig_port = enc_to_dig_port(&encoder->base);
2592
2593 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
2594 pipe_config->has_infoframe = true;
2595
2596 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2597 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2598 pipe_config->hdmi_scrambling = true;
2599 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2600 pipe_config->hdmi_high_tmds_clock_ratio = true;
2601 /* fall through */
2602 case TRANS_DDI_MODE_SELECT_DVI:
2603 pipe_config->lane_count = 4;
2604 break;
2605 case TRANS_DDI_MODE_SELECT_FDI:
2606 break;
2607 case TRANS_DDI_MODE_SELECT_DP_SST:
2608 case TRANS_DDI_MODE_SELECT_DP_MST:
2609 pipe_config->lane_count =
2610 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2611 intel_dp_get_m_n(intel_crtc, pipe_config);
2612 break;
2613 default:
2614 break;
2615 }
2616
2617 pipe_config->has_audio =
2618 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
2619
2620 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2621 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2622 /*
2623 * This is a big fat ugly hack.
2624 *
2625 * Some machines in UEFI boot mode provide us a VBT that has 18
2626 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2627 * unknown we fail to light up. Yet the same BIOS boots up with
2628 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2629 * max, not what it tells us to use.
2630 *
2631 * Note: This will still be broken if the eDP panel is not lit
2632 * up by the BIOS, and thus we can't get the mode at module
2633 * load.
2634 */
2635 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2636 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2637 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2638 }
2639
2640 intel_ddi_clock_get(encoder, pipe_config);
2641
2642 if (IS_GEN9_LP(dev_priv))
2643 pipe_config->lane_lat_optim_mask =
2644 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2645 }
2646
2647 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2648 struct intel_crtc_state *pipe_config,
2649 struct drm_connector_state *conn_state)
2650 {
2651 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2652 int type = encoder->type;
2653 int port = intel_ddi_get_encoder_port(encoder);
2654 int ret;
2655
2656 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2657
2658 if (port == PORT_A)
2659 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2660
2661 if (type == INTEL_OUTPUT_HDMI)
2662 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2663 else
2664 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2665
2666 if (IS_GEN9_LP(dev_priv) && ret)
2667 pipe_config->lane_lat_optim_mask =
2668 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2669 pipe_config->lane_count);
2670
2671 return ret;
2672
2673 }
2674
2675 static const struct drm_encoder_funcs intel_ddi_funcs = {
2676 .reset = intel_dp_encoder_reset,
2677 .destroy = intel_dp_encoder_destroy,
2678 };
2679
2680 static struct intel_connector *
2681 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2682 {
2683 struct intel_connector *connector;
2684 enum port port = intel_dig_port->port;
2685
2686 connector = intel_connector_alloc();
2687 if (!connector)
2688 return NULL;
2689
2690 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2691 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2692 kfree(connector);
2693 return NULL;
2694 }
2695
2696 return connector;
2697 }
2698
2699 static struct intel_connector *
2700 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2701 {
2702 struct intel_connector *connector;
2703 enum port port = intel_dig_port->port;
2704
2705 connector = intel_connector_alloc();
2706 if (!connector)
2707 return NULL;
2708
2709 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2710 intel_hdmi_init_connector(intel_dig_port, connector);
2711
2712 return connector;
2713 }
2714
2715 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
2716 {
2717 struct intel_digital_port *intel_dig_port;
2718 struct intel_encoder *intel_encoder;
2719 struct drm_encoder *encoder;
2720 bool init_hdmi, init_dp, init_lspcon = false;
2721 int max_lanes;
2722
2723 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2724 switch (port) {
2725 case PORT_A:
2726 max_lanes = 4;
2727 break;
2728 case PORT_E:
2729 max_lanes = 0;
2730 break;
2731 default:
2732 max_lanes = 4;
2733 break;
2734 }
2735 } else {
2736 switch (port) {
2737 case PORT_A:
2738 max_lanes = 2;
2739 break;
2740 case PORT_E:
2741 max_lanes = 2;
2742 break;
2743 default:
2744 max_lanes = 4;
2745 break;
2746 }
2747 }
2748
2749 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2750 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2751 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2752
2753 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2754 /*
2755 * Lspcon device needs to be driven with DP connector
2756 * with special detection sequence. So make sure DP
2757 * is initialized before lspcon.
2758 */
2759 init_dp = true;
2760 init_lspcon = true;
2761 init_hdmi = false;
2762 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2763 }
2764
2765 if (!init_dp && !init_hdmi) {
2766 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2767 port_name(port));
2768 return;
2769 }
2770
2771 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2772 if (!intel_dig_port)
2773 return;
2774
2775 intel_encoder = &intel_dig_port->base;
2776 encoder = &intel_encoder->base;
2777
2778 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
2779 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2780
2781 intel_encoder->compute_config = intel_ddi_compute_config;
2782 intel_encoder->enable = intel_enable_ddi;
2783 if (IS_GEN9_LP(dev_priv))
2784 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2785 intel_encoder->pre_enable = intel_ddi_pre_enable;
2786 intel_encoder->disable = intel_disable_ddi;
2787 intel_encoder->post_disable = intel_ddi_post_disable;
2788 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2789 intel_encoder->get_config = intel_ddi_get_config;
2790 intel_encoder->suspend = intel_dp_encoder_suspend;
2791 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
2792
2793 intel_dig_port->port = port;
2794 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2795 (DDI_BUF_PORT_REVERSAL |
2796 DDI_A_4_LANES);
2797
2798 switch (port) {
2799 case PORT_A:
2800 intel_dig_port->ddi_io_power_domain =
2801 POWER_DOMAIN_PORT_DDI_A_IO;
2802 break;
2803 case PORT_B:
2804 intel_dig_port->ddi_io_power_domain =
2805 POWER_DOMAIN_PORT_DDI_B_IO;
2806 break;
2807 case PORT_C:
2808 intel_dig_port->ddi_io_power_domain =
2809 POWER_DOMAIN_PORT_DDI_C_IO;
2810 break;
2811 case PORT_D:
2812 intel_dig_port->ddi_io_power_domain =
2813 POWER_DOMAIN_PORT_DDI_D_IO;
2814 break;
2815 case PORT_E:
2816 intel_dig_port->ddi_io_power_domain =
2817 POWER_DOMAIN_PORT_DDI_E_IO;
2818 break;
2819 default:
2820 MISSING_CASE(port);
2821 }
2822
2823 /*
2824 * Bspec says that DDI_A_4_LANES is the only supported configuration
2825 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2826 * wasn't lit up at boot. Force this bit on in our internal
2827 * configuration so that we use the proper lane count for our
2828 * calculations.
2829 */
2830 if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
2831 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2832 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2833 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2834 max_lanes = 4;
2835 }
2836 }
2837
2838 intel_dig_port->max_lanes = max_lanes;
2839
2840 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2841 intel_encoder->power_domain = intel_port_to_power_domain(port);
2842 intel_encoder->port = port;
2843 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2844 intel_encoder->cloneable = 0;
2845
2846 intel_infoframe_init(intel_dig_port);
2847
2848 if (init_dp) {
2849 if (!intel_ddi_init_dp_connector(intel_dig_port))
2850 goto err;
2851
2852 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2853 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2854 }
2855
2856 /* In theory we don't need the encoder->type check, but leave it just in
2857 * case we have some really bad VBTs... */
2858 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2859 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2860 goto err;
2861 }
2862
2863 if (init_lspcon) {
2864 if (lspcon_init(intel_dig_port))
2865 /* TODO: handle hdmi info frame part */
2866 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
2867 port_name(port));
2868 else
2869 /*
2870 * LSPCON init faied, but DP init was success, so
2871 * lets try to drive as DP++ port.
2872 */
2873 DRM_ERROR("LSPCON init failed on port %c\n",
2874 port_name(port));
2875 }
2876
2877 return;
2878
2879 err:
2880 drm_encoder_cleanup(encoder);
2881 kfree(intel_dig_port);
2882 }
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