2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
47 static const u32 hsw_ddi_translations_fdi
[] = {
48 0x00FFFFFF, 0x0007000E, /* FDI parameters */
49 0x00D75FFF, 0x000F000A,
50 0x00C30FFF, 0x00060006,
51 0x00AAAFFF, 0x001E0000,
52 0x00FFFFFF, 0x000F000A,
53 0x00D75FFF, 0x00160004,
54 0x00C30FFF, 0x001E0000,
55 0x00FFFFFF, 0x00060006,
56 0x00D75FFF, 0x001E0000,
59 static const u32 hsw_ddi_translations_hdmi
[] = {
60 /* Idx NT mV diff T mV diff db */
61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
75 static const u32 bdw_ddi_translations_edp
[] = {
76 0x00FFFFFF, 0x00000012, /* DP parameters */
77 0x00EBAFFF, 0x00020011,
78 0x00C71FFF, 0x0006000F,
79 0x00FFFFFF, 0x00020011,
80 0x00DB6FFF, 0x0005000F,
81 0x00BEEFFF, 0x000A000C,
82 0x00FFFFFF, 0x0005000F,
83 0x00DB6FFF, 0x000A000C,
84 0x00FFFFFF, 0x000A000C,
85 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
88 static const u32 bdw_ddi_translations_dp
[] = {
89 0x00FFFFFF, 0x0007000E, /* DP parameters */
90 0x00D75FFF, 0x000E000A,
91 0x00BEFFFF, 0x00140006,
92 0x00FFFFFF, 0x000E000A,
93 0x00D75FFF, 0x00180004,
94 0x80CB2FFF, 0x001B0002,
95 0x00F7DFFF, 0x00180004,
96 0x80D75FFF, 0x001B0002,
97 0x80FFFFFF, 0x001B0002,
98 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
101 static const u32 bdw_ddi_translations_fdi
[] = {
102 0x00FFFFFF, 0x0001000E, /* FDI parameters */
103 0x00D75FFF, 0x0004000A,
104 0x00C30FFF, 0x00070006,
105 0x00AAAFFF, 0x000C0000,
106 0x00FFFFFF, 0x0004000A,
107 0x00D75FFF, 0x00090004,
108 0x00C30FFF, 0x000C0000,
109 0x00FFFFFF, 0x00070006,
110 0x00D75FFF, 0x000C0000,
111 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
114 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
116 struct drm_encoder
*encoder
= &intel_encoder
->base
;
117 int type
= intel_encoder
->type
;
119 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
120 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
121 struct intel_digital_port
*intel_dig_port
=
122 enc_to_dig_port(encoder
);
123 return intel_dig_port
->port
;
125 } else if (type
== INTEL_OUTPUT_ANALOG
) {
129 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
135 * Starting with Haswell, DDI port buffers must be programmed with correct
136 * values in advance. The buffer values are different for FDI and DP modes,
137 * but the HDMI/DVI fields are shared among those. So we program the DDI
138 * in either FDI or DP modes only, as HDMI connections will work with both
141 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
)
143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
146 int hdmi_level
= dev_priv
->vbt
.ddi_port_info
[port
].hdmi_level_shift
;
147 const u32
*ddi_translations_fdi
;
148 const u32
*ddi_translations_dp
;
149 const u32
*ddi_translations_edp
;
150 const u32
*ddi_translations
;
152 if (IS_BROADWELL(dev
)) {
153 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
154 ddi_translations_dp
= bdw_ddi_translations_dp
;
155 ddi_translations_edp
= bdw_ddi_translations_edp
;
156 } else if (IS_HASWELL(dev
)) {
157 ddi_translations_fdi
= hsw_ddi_translations_fdi
;
158 ddi_translations_dp
= hsw_ddi_translations_dp
;
159 ddi_translations_edp
= hsw_ddi_translations_dp
;
161 WARN(1, "ddi translation table missing\n");
162 ddi_translations_edp
= bdw_ddi_translations_dp
;
163 ddi_translations_fdi
= bdw_ddi_translations_fdi
;
164 ddi_translations_dp
= bdw_ddi_translations_dp
;
169 ddi_translations
= ddi_translations_edp
;
173 ddi_translations
= ddi_translations_dp
;
176 if (intel_dp_is_edp(dev
, PORT_D
))
177 ddi_translations
= ddi_translations_edp
;
179 ddi_translations
= ddi_translations_dp
;
182 ddi_translations
= ddi_translations_fdi
;
188 for (i
= 0, reg
= DDI_BUF_TRANS(port
);
189 i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
190 I915_WRITE(reg
, ddi_translations
[i
]);
193 /* Entry 9 is for HDMI: */
194 for (i
= 0; i
< 2; i
++) {
195 I915_WRITE(reg
, hsw_ddi_translations_hdmi
[hdmi_level
* 2 + i
]);
200 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
201 * mode and port E for FDI.
203 void intel_prepare_ddi(struct drm_device
*dev
)
210 for (port
= PORT_A
; port
<= PORT_E
; port
++)
211 intel_prepare_ddi_buffers(dev
, port
);
214 static const long hsw_ddi_buf_ctl_values
[] = {
215 DDI_BUF_EMP_400MV_0DB_HSW
,
216 DDI_BUF_EMP_400MV_3_5DB_HSW
,
217 DDI_BUF_EMP_400MV_6DB_HSW
,
218 DDI_BUF_EMP_400MV_9_5DB_HSW
,
219 DDI_BUF_EMP_600MV_0DB_HSW
,
220 DDI_BUF_EMP_600MV_3_5DB_HSW
,
221 DDI_BUF_EMP_600MV_6DB_HSW
,
222 DDI_BUF_EMP_800MV_0DB_HSW
,
223 DDI_BUF_EMP_800MV_3_5DB_HSW
226 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
229 uint32_t reg
= DDI_BUF_CTL(port
);
232 for (i
= 0; i
< 8; i
++) {
234 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
237 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
240 /* Starting with Haswell, different DDI ports can work in FDI mode for
241 * connection to the PCH-located connectors. For this, it is necessary to train
242 * both the DDI port and PCH receiver for the desired DDI buffer settings.
244 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
245 * please note that when FDI mode is active on DDI E, it shares 2 lines with
246 * DDI A (which is used for eDP)
249 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
251 struct drm_device
*dev
= crtc
->dev
;
252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
253 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
254 u32 temp
, i
, rx_ctl_val
;
256 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
257 * mode set "sequence for CRT port" document:
258 * - TP1 to TP2 time with the default value
261 * WaFDIAutoLinkSetTimingOverrride:hsw
263 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
264 FDI_RX_PWRDN_LANE0_VAL(2) |
265 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
267 /* Enable the PCH Receiver FDI PLL */
268 rx_ctl_val
= dev_priv
->fdi_rx_config
| FDI_RX_ENHANCE_FRAME_ENABLE
|
270 FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
271 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
272 POSTING_READ(_FDI_RXA_CTL
);
275 /* Switch from Rawclk to PCDclk */
276 rx_ctl_val
|= FDI_PCDCLK
;
277 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
279 /* Configure Port Clock Select */
280 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->ddi_pll_sel
);
282 /* Start the training iterating through available voltages and emphasis,
283 * testing each value twice. */
284 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
) * 2; i
++) {
285 /* Configure DP_TP_CTL with auto-training */
286 I915_WRITE(DP_TP_CTL(PORT_E
),
287 DP_TP_CTL_FDI_AUTOTRAIN
|
288 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
289 DP_TP_CTL_LINK_TRAIN_PAT1
|
292 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
293 * DDI E does not support port reversal, the functionality is
294 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
295 * port reversal bit */
296 I915_WRITE(DDI_BUF_CTL(PORT_E
),
298 ((intel_crtc
->config
.fdi_lanes
- 1) << 1) |
299 hsw_ddi_buf_ctl_values
[i
/ 2]);
300 POSTING_READ(DDI_BUF_CTL(PORT_E
));
304 /* Program PCH FDI Receiver TU */
305 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
307 /* Enable PCH FDI Receiver with auto-training */
308 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
309 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
310 POSTING_READ(_FDI_RXA_CTL
);
312 /* Wait for FDI receiver lane calibration */
315 /* Unset FDI_RX_MISC pwrdn lanes */
316 temp
= I915_READ(_FDI_RXA_MISC
);
317 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
318 I915_WRITE(_FDI_RXA_MISC
, temp
);
319 POSTING_READ(_FDI_RXA_MISC
);
321 /* Wait for FDI auto training time */
324 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
325 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
326 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
328 /* Enable normal pixel sending for FDI */
329 I915_WRITE(DP_TP_CTL(PORT_E
),
330 DP_TP_CTL_FDI_AUTOTRAIN
|
331 DP_TP_CTL_LINK_TRAIN_NORMAL
|
332 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
338 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
339 temp
&= ~DDI_BUF_CTL_ENABLE
;
340 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
341 POSTING_READ(DDI_BUF_CTL(PORT_E
));
343 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
344 temp
= I915_READ(DP_TP_CTL(PORT_E
));
345 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
346 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
347 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
348 POSTING_READ(DP_TP_CTL(PORT_E
));
350 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
352 rx_ctl_val
&= ~FDI_RX_ENABLE
;
353 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
354 POSTING_READ(_FDI_RXA_CTL
);
356 /* Reset FDI_RX_MISC pwrdn lanes */
357 temp
= I915_READ(_FDI_RXA_MISC
);
358 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
359 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
360 I915_WRITE(_FDI_RXA_MISC
, temp
);
361 POSTING_READ(_FDI_RXA_MISC
);
364 DRM_ERROR("FDI link training failed!\n");
367 static void intel_ddi_mode_set(struct intel_encoder
*encoder
)
369 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
370 int port
= intel_ddi_get_encoder_port(encoder
);
371 int pipe
= crtc
->pipe
;
372 int type
= encoder
->type
;
373 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
375 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
376 port_name(port
), pipe_name(pipe
));
378 crtc
->eld_vld
= false;
379 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
380 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
381 struct intel_digital_port
*intel_dig_port
=
382 enc_to_dig_port(&encoder
->base
);
384 intel_dp
->DP
= intel_dig_port
->saved_port_bits
|
385 DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
386 intel_dp
->DP
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
388 if (intel_dp
->has_audio
) {
389 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
390 pipe_name(crtc
->pipe
));
393 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
394 intel_write_eld(&encoder
->base
, adjusted_mode
);
396 } else if (type
== INTEL_OUTPUT_HDMI
) {
397 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
399 if (intel_hdmi
->has_audio
) {
400 /* Proper support for digital audio needs a new logic
401 * and a new set of registers, so we leave it for future
404 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
405 pipe_name(crtc
->pipe
));
408 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
409 intel_write_eld(&encoder
->base
, adjusted_mode
);
412 intel_hdmi
->set_infoframes(&encoder
->base
, adjusted_mode
);
416 static struct intel_encoder
*
417 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
419 struct drm_device
*dev
= crtc
->dev
;
420 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
421 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
422 int num_encoders
= 0;
424 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
429 if (num_encoders
!= 1)
430 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders
,
431 pipe_name(intel_crtc
->pipe
));
437 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
439 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
440 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
441 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
444 switch (intel_crtc
->ddi_pll_sel
) {
445 case PORT_CLK_SEL_SPLL
:
446 plls
->spll_refcount
--;
447 if (plls
->spll_refcount
== 0) {
448 DRM_DEBUG_KMS("Disabling SPLL\n");
449 val
= I915_READ(SPLL_CTL
);
450 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
451 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
452 POSTING_READ(SPLL_CTL
);
455 case PORT_CLK_SEL_WRPLL1
:
456 plls
->wrpll1_refcount
--;
457 if (plls
->wrpll1_refcount
== 0) {
458 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
459 val
= I915_READ(WRPLL_CTL1
);
460 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
461 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
462 POSTING_READ(WRPLL_CTL1
);
465 case PORT_CLK_SEL_WRPLL2
:
466 plls
->wrpll2_refcount
--;
467 if (plls
->wrpll2_refcount
== 0) {
468 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
469 val
= I915_READ(WRPLL_CTL2
);
470 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
471 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
472 POSTING_READ(WRPLL_CTL2
);
477 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
478 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
479 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
481 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
485 #define LC_FREQ_2K (LC_FREQ * 2000)
491 /* Constraints for PLL good behavior */
497 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
503 static unsigned wrpll_get_budget_for_freq(int clock
)
577 static void wrpll_update_rnp(uint64_t freq2k
, unsigned budget
,
578 unsigned r2
, unsigned n2
, unsigned p
,
579 struct wrpll_rnp
*best
)
581 uint64_t a
, b
, c
, d
, diff
, diff_best
;
583 /* No best (r,n,p) yet */
592 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
596 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
599 * and we would like delta <= budget.
601 * If the discrepancy is above the PPM-based budget, always prefer to
602 * improve upon the previous solution. However, if you're within the
603 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
605 a
= freq2k
* budget
* p
* r2
;
606 b
= freq2k
* budget
* best
->p
* best
->r2
;
607 diff
= ABS_DIFF((freq2k
* p
* r2
), (LC_FREQ_2K
* n2
));
608 diff_best
= ABS_DIFF((freq2k
* best
->p
* best
->r2
),
609 (LC_FREQ_2K
* best
->n2
));
611 d
= 1000000 * diff_best
;
613 if (a
< c
&& b
< d
) {
614 /* If both are above the budget, pick the closer */
615 if (best
->p
* best
->r2
* diff
< p
* r2
* diff_best
) {
620 } else if (a
>= c
&& b
< d
) {
621 /* If A is below the threshold but B is above it? Update. */
625 } else if (a
>= c
&& b
>= d
) {
626 /* Both are below the limit, so pick the higher n2/(r2*r2) */
627 if (n2
* best
->r2
* best
->r2
> best
->n2
* r2
* r2
) {
633 /* Otherwise a < c && b >= d, do nothing */
637 intel_ddi_calculate_wrpll(int clock
/* in Hz */,
638 unsigned *r2_out
, unsigned *n2_out
, unsigned *p_out
)
642 struct wrpll_rnp best
= { 0, 0, 0 };
645 freq2k
= clock
/ 100;
647 budget
= wrpll_get_budget_for_freq(clock
);
649 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
650 * and directly pass the LC PLL to it. */
651 if (freq2k
== 5400000) {
659 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
662 * We want R so that REF_MIN <= Ref <= REF_MAX.
663 * Injecting R2 = 2 * R gives:
664 * REF_MAX * r2 > LC_FREQ * 2 and
665 * REF_MIN * r2 < LC_FREQ * 2
667 * Which means the desired boundaries for r2 are:
668 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
671 for (r2
= LC_FREQ
* 2 / REF_MAX
+ 1;
672 r2
<= LC_FREQ
* 2 / REF_MIN
;
676 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
678 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
679 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
680 * VCO_MAX * r2 > n2 * LC_FREQ and
681 * VCO_MIN * r2 < n2 * LC_FREQ)
683 * Which means the desired boundaries for n2 are:
684 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
686 for (n2
= VCO_MIN
* r2
/ LC_FREQ
+ 1;
687 n2
<= VCO_MAX
* r2
/ LC_FREQ
;
690 for (p
= P_MIN
; p
<= P_MAX
; p
+= P_INC
)
691 wrpll_update_rnp(freq2k
, budget
,
700 DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
701 clock
, *p_out
, *n2_out
, *r2_out
);
704 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
)
706 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
707 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
708 struct drm_encoder
*encoder
= &intel_encoder
->base
;
709 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
710 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
711 int type
= intel_encoder
->type
;
712 enum pipe pipe
= intel_crtc
->pipe
;
714 int clock
= intel_crtc
->config
.port_clock
;
716 /* TODO: reuse PLLs when possible (compare values) */
718 intel_ddi_put_crtc_pll(crtc
);
720 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
721 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
723 switch (intel_dp
->link_bw
) {
724 case DP_LINK_BW_1_62
:
725 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
728 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
731 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
734 DRM_ERROR("Link bandwidth %d unsupported\n",
739 /* We don't need to turn any PLL on because we'll use LCPLL. */
742 } else if (type
== INTEL_OUTPUT_HDMI
) {
745 if (plls
->wrpll1_refcount
== 0) {
746 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
748 plls
->wrpll1_refcount
++;
750 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
751 } else if (plls
->wrpll2_refcount
== 0) {
752 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
754 plls
->wrpll2_refcount
++;
756 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
758 DRM_ERROR("No WRPLLs available!\n");
762 WARN(I915_READ(reg
) & WRPLL_PLL_ENABLE
,
763 "WRPLL already enabled\n");
765 intel_ddi_calculate_wrpll(clock
* 1000, &r2
, &n2
, &p
);
767 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
768 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
769 WRPLL_DIVIDER_POST(p
);
771 } else if (type
== INTEL_OUTPUT_ANALOG
) {
772 if (plls
->spll_refcount
== 0) {
773 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
775 plls
->spll_refcount
++;
777 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
779 DRM_ERROR("SPLL already in use\n");
783 WARN(I915_READ(reg
) & SPLL_PLL_ENABLE
,
784 "SPLL already enabled\n");
786 val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
789 WARN(1, "Invalid DDI encoder type %d\n", type
);
793 I915_WRITE(reg
, val
);
799 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
801 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
802 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
803 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
804 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
805 int type
= intel_encoder
->type
;
808 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
810 temp
= TRANS_MSA_SYNC_CLK
;
811 switch (intel_crtc
->config
.pipe_bpp
) {
813 temp
|= TRANS_MSA_6_BPC
;
816 temp
|= TRANS_MSA_8_BPC
;
819 temp
|= TRANS_MSA_10_BPC
;
822 temp
|= TRANS_MSA_12_BPC
;
827 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
831 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
)
833 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
834 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
835 struct drm_encoder
*encoder
= &intel_encoder
->base
;
836 struct drm_device
*dev
= crtc
->dev
;
837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
838 enum pipe pipe
= intel_crtc
->pipe
;
839 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
840 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
841 int type
= intel_encoder
->type
;
844 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
845 temp
= TRANS_DDI_FUNC_ENABLE
;
846 temp
|= TRANS_DDI_SELECT_PORT(port
);
848 switch (intel_crtc
->config
.pipe_bpp
) {
850 temp
|= TRANS_DDI_BPC_6
;
853 temp
|= TRANS_DDI_BPC_8
;
856 temp
|= TRANS_DDI_BPC_10
;
859 temp
|= TRANS_DDI_BPC_12
;
865 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
866 temp
|= TRANS_DDI_PVSYNC
;
867 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
868 temp
|= TRANS_DDI_PHSYNC
;
870 if (cpu_transcoder
== TRANSCODER_EDP
) {
873 /* On Haswell, can only use the always-on power well for
874 * eDP when not using the panel fitter, and when not
875 * using motion blur mitigation (which we don't
877 if (IS_HASWELL(dev
) && intel_crtc
->config
.pch_pfit
.enabled
)
878 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
880 temp
|= TRANS_DDI_EDP_INPUT_A_ON
;
883 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
886 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
894 if (type
== INTEL_OUTPUT_HDMI
) {
895 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
897 if (intel_hdmi
->has_hdmi_sink
)
898 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
900 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
902 } else if (type
== INTEL_OUTPUT_ANALOG
) {
903 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
904 temp
|= (intel_crtc
->config
.fdi_lanes
- 1) << 1;
906 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
907 type
== INTEL_OUTPUT_EDP
) {
908 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
910 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
912 temp
|= DDI_PORT_WIDTH(intel_dp
->lane_count
);
914 WARN(1, "Invalid encoder type %d for pipe %c\n",
915 intel_encoder
->type
, pipe_name(pipe
));
918 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
921 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
922 enum transcoder cpu_transcoder
)
924 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
925 uint32_t val
= I915_READ(reg
);
927 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
928 val
|= TRANS_DDI_PORT_NONE
;
929 I915_WRITE(reg
, val
);
932 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
934 struct drm_device
*dev
= intel_connector
->base
.dev
;
935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
936 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
937 int type
= intel_connector
->base
.connector_type
;
938 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
940 enum transcoder cpu_transcoder
;
943 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
947 cpu_transcoder
= TRANSCODER_EDP
;
949 cpu_transcoder
= (enum transcoder
) pipe
;
951 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
953 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
954 case TRANS_DDI_MODE_SELECT_HDMI
:
955 case TRANS_DDI_MODE_SELECT_DVI
:
956 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
958 case TRANS_DDI_MODE_SELECT_DP_SST
:
959 if (type
== DRM_MODE_CONNECTOR_eDP
)
961 case TRANS_DDI_MODE_SELECT_DP_MST
:
962 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
964 case TRANS_DDI_MODE_SELECT_FDI
:
965 return (type
== DRM_MODE_CONNECTOR_VGA
);
972 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
975 struct drm_device
*dev
= encoder
->base
.dev
;
976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
977 enum port port
= intel_ddi_get_encoder_port(encoder
);
981 tmp
= I915_READ(DDI_BUF_CTL(port
));
983 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
986 if (port
== PORT_A
) {
987 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
989 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
990 case TRANS_DDI_EDP_INPUT_A_ON
:
991 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
994 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
997 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1004 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1005 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1007 if ((tmp
& TRANS_DDI_PORT_MASK
)
1008 == TRANS_DDI_SELECT_PORT(port
)) {
1015 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port
));
1020 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
1024 enum port port
= I915_MAX_PORTS
;
1025 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1029 if (cpu_transcoder
== TRANSCODER_EDP
) {
1032 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1033 temp
&= TRANS_DDI_PORT_MASK
;
1035 for (i
= PORT_B
; i
<= PORT_E
; i
++)
1036 if (temp
== TRANS_DDI_SELECT_PORT(i
))
1040 if (port
== I915_MAX_PORTS
) {
1041 WARN(1, "Pipe %c enabled on an unknown port\n",
1043 ret
= PORT_CLK_SEL_NONE
;
1045 ret
= I915_READ(PORT_CLK_SEL(port
));
1046 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1047 "0x%08x\n", pipe_name(pipe
), port_name(port
),
1054 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
1056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1058 struct intel_crtc
*intel_crtc
;
1060 for_each_pipe(pipe
) {
1062 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1064 if (!intel_crtc
->active
)
1067 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
1070 switch (intel_crtc
->ddi_pll_sel
) {
1071 case PORT_CLK_SEL_SPLL
:
1072 dev_priv
->ddi_plls
.spll_refcount
++;
1074 case PORT_CLK_SEL_WRPLL1
:
1075 dev_priv
->ddi_plls
.wrpll1_refcount
++;
1077 case PORT_CLK_SEL_WRPLL2
:
1078 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1084 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1086 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1087 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1088 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1089 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1090 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1092 if (cpu_transcoder
!= TRANSCODER_EDP
)
1093 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1094 TRANS_CLK_SEL_PORT(port
));
1097 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1099 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1100 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1102 if (cpu_transcoder
!= TRANSCODER_EDP
)
1103 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1104 TRANS_CLK_SEL_DISABLED
);
1107 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1109 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1110 struct drm_crtc
*crtc
= encoder
->crtc
;
1111 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1112 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1113 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1114 int type
= intel_encoder
->type
;
1116 if (type
== INTEL_OUTPUT_EDP
) {
1117 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1118 ironlake_edp_panel_vdd_on(intel_dp
);
1119 ironlake_edp_panel_on(intel_dp
);
1120 ironlake_edp_panel_vdd_off(intel_dp
, true);
1123 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1124 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1126 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1127 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1129 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1130 intel_dp_start_link_train(intel_dp
);
1131 intel_dp_complete_link_train(intel_dp
);
1133 intel_dp_stop_link_train(intel_dp
);
1137 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1139 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1140 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1141 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1142 int type
= intel_encoder
->type
;
1146 val
= I915_READ(DDI_BUF_CTL(port
));
1147 if (val
& DDI_BUF_CTL_ENABLE
) {
1148 val
&= ~DDI_BUF_CTL_ENABLE
;
1149 I915_WRITE(DDI_BUF_CTL(port
), val
);
1153 val
= I915_READ(DP_TP_CTL(port
));
1154 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1155 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1156 I915_WRITE(DP_TP_CTL(port
), val
);
1159 intel_wait_ddi_buf_idle(dev_priv
, port
);
1161 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1162 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1163 ironlake_edp_panel_vdd_on(intel_dp
);
1164 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
1165 ironlake_edp_panel_off(intel_dp
);
1168 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1171 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1173 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1174 struct drm_crtc
*crtc
= encoder
->crtc
;
1175 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1176 int pipe
= intel_crtc
->pipe
;
1177 struct drm_device
*dev
= encoder
->dev
;
1178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1179 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1180 int type
= intel_encoder
->type
;
1183 if (type
== INTEL_OUTPUT_HDMI
) {
1184 struct intel_digital_port
*intel_dig_port
=
1185 enc_to_dig_port(encoder
);
1187 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1188 * are ignored so nothing special needs to be done besides
1189 * enabling the port.
1191 I915_WRITE(DDI_BUF_CTL(port
),
1192 intel_dig_port
->saved_port_bits
|
1193 DDI_BUF_CTL_ENABLE
);
1194 } else if (type
== INTEL_OUTPUT_EDP
) {
1195 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1198 intel_dp_stop_link_train(intel_dp
);
1200 ironlake_edp_backlight_on(intel_dp
);
1201 intel_edp_psr_enable(intel_dp
);
1204 if (intel_crtc
->eld_vld
&& type
!= INTEL_OUTPUT_EDP
) {
1205 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1206 tmp
|= ((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) << (pipe
* 4));
1207 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1211 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1213 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1214 struct drm_crtc
*crtc
= encoder
->crtc
;
1215 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1216 int pipe
= intel_crtc
->pipe
;
1217 int type
= intel_encoder
->type
;
1218 struct drm_device
*dev
= encoder
->dev
;
1219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1222 if (intel_crtc
->eld_vld
&& type
!= INTEL_OUTPUT_EDP
) {
1223 tmp
= I915_READ(HSW_AUD_PIN_ELD_CP_VLD
);
1224 tmp
&= ~((AUDIO_OUTPUT_ENABLE_A
| AUDIO_ELD_VALID_A
) <<
1226 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD
, tmp
);
1229 if (type
== INTEL_OUTPUT_EDP
) {
1230 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1232 intel_edp_psr_disable(intel_dp
);
1233 ironlake_edp_backlight_off(intel_dp
);
1237 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1239 struct drm_device
*dev
= dev_priv
->dev
;
1240 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
1241 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
1243 if (lcpll
& LCPLL_CD_SOURCE_FCLK
) {
1245 } else if (I915_READ(HSW_FUSE_STRAP
) & HSW_CDCLK_LIMIT
) {
1247 } else if (freq
== LCPLL_CLK_FREQ_450
) {
1249 } else if (IS_HASWELL(dev
)) {
1255 if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
1257 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
1264 void intel_ddi_pll_init(struct drm_device
*dev
)
1266 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1267 uint32_t val
= I915_READ(LCPLL_CTL
);
1269 /* The LCPLL register should be turned on by the BIOS. For now let's
1270 * just check its state and print errors in case something is wrong.
1271 * Don't even try to turn it on.
1274 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1275 intel_ddi_get_cdclk_freq(dev_priv
));
1277 if (val
& LCPLL_CD_SOURCE_FCLK
)
1278 DRM_ERROR("CDCLK source is not LCPLL\n");
1280 if (val
& LCPLL_PLL_DISABLE
)
1281 DRM_ERROR("LCPLL is disabled\n");
1284 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1286 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1287 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1288 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1289 enum port port
= intel_dig_port
->port
;
1293 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1294 val
= I915_READ(DDI_BUF_CTL(port
));
1295 if (val
& DDI_BUF_CTL_ENABLE
) {
1296 val
&= ~DDI_BUF_CTL_ENABLE
;
1297 I915_WRITE(DDI_BUF_CTL(port
), val
);
1301 val
= I915_READ(DP_TP_CTL(port
));
1302 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1303 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1304 I915_WRITE(DP_TP_CTL(port
), val
);
1305 POSTING_READ(DP_TP_CTL(port
));
1308 intel_wait_ddi_buf_idle(dev_priv
, port
);
1311 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1312 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1313 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1314 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1315 I915_WRITE(DP_TP_CTL(port
), val
);
1316 POSTING_READ(DP_TP_CTL(port
));
1318 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1319 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1320 POSTING_READ(DDI_BUF_CTL(port
));
1325 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1327 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1328 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1331 intel_ddi_post_disable(intel_encoder
);
1333 val
= I915_READ(_FDI_RXA_CTL
);
1334 val
&= ~FDI_RX_ENABLE
;
1335 I915_WRITE(_FDI_RXA_CTL
, val
);
1337 val
= I915_READ(_FDI_RXA_MISC
);
1338 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1339 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1340 I915_WRITE(_FDI_RXA_MISC
, val
);
1342 val
= I915_READ(_FDI_RXA_CTL
);
1344 I915_WRITE(_FDI_RXA_CTL
, val
);
1346 val
= I915_READ(_FDI_RXA_CTL
);
1347 val
&= ~FDI_RX_PLL_ENABLE
;
1348 I915_WRITE(_FDI_RXA_CTL
, val
);
1351 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
1353 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
1354 int type
= intel_encoder
->type
;
1356 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
)
1357 intel_dp_check_link_status(intel_dp
);
1360 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1361 struct intel_crtc_config
*pipe_config
)
1363 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1364 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
1365 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
1366 u32 temp
, flags
= 0;
1368 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1369 if (temp
& TRANS_DDI_PHSYNC
)
1370 flags
|= DRM_MODE_FLAG_PHSYNC
;
1372 flags
|= DRM_MODE_FLAG_NHSYNC
;
1373 if (temp
& TRANS_DDI_PVSYNC
)
1374 flags
|= DRM_MODE_FLAG_PVSYNC
;
1376 flags
|= DRM_MODE_FLAG_NVSYNC
;
1378 pipe_config
->adjusted_mode
.flags
|= flags
;
1380 switch (temp
& TRANS_DDI_BPC_MASK
) {
1381 case TRANS_DDI_BPC_6
:
1382 pipe_config
->pipe_bpp
= 18;
1384 case TRANS_DDI_BPC_8
:
1385 pipe_config
->pipe_bpp
= 24;
1387 case TRANS_DDI_BPC_10
:
1388 pipe_config
->pipe_bpp
= 30;
1390 case TRANS_DDI_BPC_12
:
1391 pipe_config
->pipe_bpp
= 36;
1397 switch (temp
& TRANS_DDI_MODE_SELECT_MASK
) {
1398 case TRANS_DDI_MODE_SELECT_HDMI
:
1399 case TRANS_DDI_MODE_SELECT_DVI
:
1400 case TRANS_DDI_MODE_SELECT_FDI
:
1402 case TRANS_DDI_MODE_SELECT_DP_SST
:
1403 case TRANS_DDI_MODE_SELECT_DP_MST
:
1404 pipe_config
->has_dp_encoder
= true;
1405 intel_dp_get_m_n(intel_crtc
, pipe_config
);
1411 if (encoder
->type
== INTEL_OUTPUT_EDP
&& dev_priv
->vbt
.edp_bpp
&&
1412 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1414 * This is a big fat ugly hack.
1416 * Some machines in UEFI boot mode provide us a VBT that has 18
1417 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1418 * unknown we fail to light up. Yet the same BIOS boots up with
1419 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1420 * max, not what it tells us to use.
1422 * Note: This will still be broken if the eDP panel is not lit
1423 * up by the BIOS, and thus we can't get the mode at module
1426 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1427 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1428 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1432 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
1434 /* HDMI has nothing special to destroy, so we can go with this. */
1435 intel_dp_encoder_destroy(encoder
);
1438 static bool intel_ddi_compute_config(struct intel_encoder
*encoder
,
1439 struct intel_crtc_config
*pipe_config
)
1441 int type
= encoder
->type
;
1442 int port
= intel_ddi_get_encoder_port(encoder
);
1444 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "compute_config() on unknown output!\n");
1447 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
1449 if (type
== INTEL_OUTPUT_HDMI
)
1450 return intel_hdmi_compute_config(encoder
, pipe_config
);
1452 return intel_dp_compute_config(encoder
, pipe_config
);
1455 static const struct drm_encoder_funcs intel_ddi_funcs
= {
1456 .destroy
= intel_ddi_destroy
,
1459 static struct intel_connector
*
1460 intel_ddi_init_dp_connector(struct intel_digital_port
*intel_dig_port
)
1462 struct intel_connector
*connector
;
1463 enum port port
= intel_dig_port
->port
;
1465 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
1469 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
1470 if (!intel_dp_init_connector(intel_dig_port
, connector
)) {
1478 static struct intel_connector
*
1479 intel_ddi_init_hdmi_connector(struct intel_digital_port
*intel_dig_port
)
1481 struct intel_connector
*connector
;
1482 enum port port
= intel_dig_port
->port
;
1484 connector
= kzalloc(sizeof(*connector
), GFP_KERNEL
);
1488 intel_dig_port
->hdmi
.hdmi_reg
= DDI_BUF_CTL(port
);
1489 intel_hdmi_init_connector(intel_dig_port
, connector
);
1494 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
1496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1497 struct intel_digital_port
*intel_dig_port
;
1498 struct intel_encoder
*intel_encoder
;
1499 struct drm_encoder
*encoder
;
1500 struct intel_connector
*hdmi_connector
= NULL
;
1501 struct intel_connector
*dp_connector
= NULL
;
1502 bool init_hdmi
, init_dp
;
1504 init_hdmi
= (dev_priv
->vbt
.ddi_port_info
[port
].supports_dvi
||
1505 dev_priv
->vbt
.ddi_port_info
[port
].supports_hdmi
);
1506 init_dp
= dev_priv
->vbt
.ddi_port_info
[port
].supports_dp
;
1507 if (!init_dp
&& !init_hdmi
) {
1508 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1514 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
1515 if (!intel_dig_port
)
1518 intel_encoder
= &intel_dig_port
->base
;
1519 encoder
= &intel_encoder
->base
;
1521 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
1522 DRM_MODE_ENCODER_TMDS
);
1524 intel_encoder
->compute_config
= intel_ddi_compute_config
;
1525 intel_encoder
->mode_set
= intel_ddi_mode_set
;
1526 intel_encoder
->enable
= intel_enable_ddi
;
1527 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
1528 intel_encoder
->disable
= intel_disable_ddi
;
1529 intel_encoder
->post_disable
= intel_ddi_post_disable
;
1530 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1531 intel_encoder
->get_config
= intel_ddi_get_config
;
1533 intel_dig_port
->port
= port
;
1534 intel_dig_port
->saved_port_bits
= I915_READ(DDI_BUF_CTL(port
)) &
1535 (DDI_BUF_PORT_REVERSAL
|
1538 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
1539 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1540 intel_encoder
->cloneable
= false;
1541 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
1544 dp_connector
= intel_ddi_init_dp_connector(intel_dig_port
);
1546 /* In theory we don't need the encoder->type check, but leave it just in
1547 * case we have some really bad VBTs... */
1548 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
&& init_hdmi
)
1549 hdmi_connector
= intel_ddi_init_hdmi_connector(intel_dig_port
);
1551 if (!dp_connector
&& !hdmi_connector
) {
1552 drm_encoder_cleanup(encoder
);
1553 kfree(intel_dig_port
);