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drm/i915: Add DP dpll limit on ironlake and use existing DPLL search function
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include "drmP.h"
32 #include "intel_drv.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "drm_dp_helper.h"
36
37 #include "drm_crtc_helper.h"
38
39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
40
41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
42 static void intel_update_watermarks(struct drm_device *dev);
43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
44
45 typedef struct {
46 /* given values */
47 int n;
48 int m1, m2;
49 int p1, p2;
50 /* derived values */
51 int dot;
52 int vco;
53 int m;
54 int p;
55 } intel_clock_t;
56
57 typedef struct {
58 int min, max;
59 } intel_range_t;
60
61 typedef struct {
62 int dot_limit;
63 int p2_slow, p2_fast;
64 } intel_p2_t;
65
66 #define INTEL_P2_NUM 2
67 typedef struct intel_limit intel_limit_t;
68 struct intel_limit {
69 intel_range_t dot, vco, n, m, m1, m2, p, p1;
70 intel_p2_t p2;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
73 bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
74 int, int, intel_clock_t *);
75 };
76
77 #define I8XX_DOT_MIN 25000
78 #define I8XX_DOT_MAX 350000
79 #define I8XX_VCO_MIN 930000
80 #define I8XX_VCO_MAX 1400000
81 #define I8XX_N_MIN 3
82 #define I8XX_N_MAX 16
83 #define I8XX_M_MIN 96
84 #define I8XX_M_MAX 140
85 #define I8XX_M1_MIN 18
86 #define I8XX_M1_MAX 26
87 #define I8XX_M2_MIN 6
88 #define I8XX_M2_MAX 16
89 #define I8XX_P_MIN 4
90 #define I8XX_P_MAX 128
91 #define I8XX_P1_MIN 2
92 #define I8XX_P1_MAX 33
93 #define I8XX_P1_LVDS_MIN 1
94 #define I8XX_P1_LVDS_MAX 6
95 #define I8XX_P2_SLOW 4
96 #define I8XX_P2_FAST 2
97 #define I8XX_P2_LVDS_SLOW 14
98 #define I8XX_P2_LVDS_FAST 7
99 #define I8XX_P2_SLOW_LIMIT 165000
100
101 #define I9XX_DOT_MIN 20000
102 #define I9XX_DOT_MAX 400000
103 #define I9XX_VCO_MIN 1400000
104 #define I9XX_VCO_MAX 2800000
105 #define PINEVIEW_VCO_MIN 1700000
106 #define PINEVIEW_VCO_MAX 3500000
107 #define I9XX_N_MIN 1
108 #define I9XX_N_MAX 6
109 /* Pineview's Ncounter is a ring counter */
110 #define PINEVIEW_N_MIN 3
111 #define PINEVIEW_N_MAX 6
112 #define I9XX_M_MIN 70
113 #define I9XX_M_MAX 120
114 #define PINEVIEW_M_MIN 2
115 #define PINEVIEW_M_MAX 256
116 #define I9XX_M1_MIN 10
117 #define I9XX_M1_MAX 22
118 #define I9XX_M2_MIN 5
119 #define I9XX_M2_MAX 9
120 /* Pineview M1 is reserved, and must be 0 */
121 #define PINEVIEW_M1_MIN 0
122 #define PINEVIEW_M1_MAX 0
123 #define PINEVIEW_M2_MIN 0
124 #define PINEVIEW_M2_MAX 254
125 #define I9XX_P_SDVO_DAC_MIN 5
126 #define I9XX_P_SDVO_DAC_MAX 80
127 #define I9XX_P_LVDS_MIN 7
128 #define I9XX_P_LVDS_MAX 98
129 #define PINEVIEW_P_LVDS_MIN 7
130 #define PINEVIEW_P_LVDS_MAX 112
131 #define I9XX_P1_MIN 1
132 #define I9XX_P1_MAX 8
133 #define I9XX_P2_SDVO_DAC_SLOW 10
134 #define I9XX_P2_SDVO_DAC_FAST 5
135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
136 #define I9XX_P2_LVDS_SLOW 14
137 #define I9XX_P2_LVDS_FAST 7
138 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
139
140 /*The parameter is for SDVO on G4x platform*/
141 #define G4X_DOT_SDVO_MIN 25000
142 #define G4X_DOT_SDVO_MAX 270000
143 #define G4X_VCO_MIN 1750000
144 #define G4X_VCO_MAX 3500000
145 #define G4X_N_SDVO_MIN 1
146 #define G4X_N_SDVO_MAX 4
147 #define G4X_M_SDVO_MIN 104
148 #define G4X_M_SDVO_MAX 138
149 #define G4X_M1_SDVO_MIN 17
150 #define G4X_M1_SDVO_MAX 23
151 #define G4X_M2_SDVO_MIN 5
152 #define G4X_M2_SDVO_MAX 11
153 #define G4X_P_SDVO_MIN 10
154 #define G4X_P_SDVO_MAX 30
155 #define G4X_P1_SDVO_MIN 1
156 #define G4X_P1_SDVO_MAX 3
157 #define G4X_P2_SDVO_SLOW 10
158 #define G4X_P2_SDVO_FAST 10
159 #define G4X_P2_SDVO_LIMIT 270000
160
161 /*The parameter is for HDMI_DAC on G4x platform*/
162 #define G4X_DOT_HDMI_DAC_MIN 22000
163 #define G4X_DOT_HDMI_DAC_MAX 400000
164 #define G4X_N_HDMI_DAC_MIN 1
165 #define G4X_N_HDMI_DAC_MAX 4
166 #define G4X_M_HDMI_DAC_MIN 104
167 #define G4X_M_HDMI_DAC_MAX 138
168 #define G4X_M1_HDMI_DAC_MIN 16
169 #define G4X_M1_HDMI_DAC_MAX 23
170 #define G4X_M2_HDMI_DAC_MIN 5
171 #define G4X_M2_HDMI_DAC_MAX 11
172 #define G4X_P_HDMI_DAC_MIN 5
173 #define G4X_P_HDMI_DAC_MAX 80
174 #define G4X_P1_HDMI_DAC_MIN 1
175 #define G4X_P1_HDMI_DAC_MAX 8
176 #define G4X_P2_HDMI_DAC_SLOW 10
177 #define G4X_P2_HDMI_DAC_FAST 5
178 #define G4X_P2_HDMI_DAC_LIMIT 165000
179
180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
198
199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
217
218 /*The parameter is for DISPLAY PORT on G4x platform*/
219 #define G4X_DOT_DISPLAY_PORT_MIN 161670
220 #define G4X_DOT_DISPLAY_PORT_MAX 227000
221 #define G4X_N_DISPLAY_PORT_MIN 1
222 #define G4X_N_DISPLAY_PORT_MAX 2
223 #define G4X_M_DISPLAY_PORT_MIN 97
224 #define G4X_M_DISPLAY_PORT_MAX 108
225 #define G4X_M1_DISPLAY_PORT_MIN 0x10
226 #define G4X_M1_DISPLAY_PORT_MAX 0x12
227 #define G4X_M2_DISPLAY_PORT_MIN 0x05
228 #define G4X_M2_DISPLAY_PORT_MAX 0x06
229 #define G4X_P_DISPLAY_PORT_MIN 10
230 #define G4X_P_DISPLAY_PORT_MAX 20
231 #define G4X_P1_DISPLAY_PORT_MIN 1
232 #define G4X_P1_DISPLAY_PORT_MAX 2
233 #define G4X_P2_DISPLAY_PORT_SLOW 10
234 #define G4X_P2_DISPLAY_PORT_FAST 10
235 #define G4X_P2_DISPLAY_PORT_LIMIT 0
236
237 /* Ironlake */
238 /* as we calculate clock using (register_value + 2) for
239 N/M1/M2, so here the range value for them is (actual_value-2).
240 */
241 #define IRONLAKE_DOT_MIN 25000
242 #define IRONLAKE_DOT_MAX 350000
243 #define IRONLAKE_VCO_MIN 1760000
244 #define IRONLAKE_VCO_MAX 3510000
245 #define IRONLAKE_N_MIN 1
246 #define IRONLAKE_N_MAX 5
247 #define IRONLAKE_M_MIN 79
248 #define IRONLAKE_M_MAX 118
249 #define IRONLAKE_M1_MIN 12
250 #define IRONLAKE_M1_MAX 23
251 #define IRONLAKE_M2_MIN 5
252 #define IRONLAKE_M2_MAX 9
253 #define IRONLAKE_P_SDVO_DAC_MIN 5
254 #define IRONLAKE_P_SDVO_DAC_MAX 80
255 #define IRONLAKE_P_LVDS_MIN 28
256 #define IRONLAKE_P_LVDS_MAX 112
257 #define IRONLAKE_P1_MIN 1
258 #define IRONLAKE_P1_MAX 8
259 #define IRONLAKE_P2_SDVO_DAC_SLOW 10
260 #define IRONLAKE_P2_SDVO_DAC_FAST 5
261 #define IRONLAKE_P2_LVDS_SLOW 14 /* single channel */
262 #define IRONLAKE_P2_LVDS_FAST 7 /* double channel */
263 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
264
265 #define IRONLAKE_P_DISPLAY_PORT_MIN 10
266 #define IRONLAKE_P_DISPLAY_PORT_MAX 20
267 #define IRONLAKE_P2_DISPLAY_PORT_FAST 10
268 #define IRONLAKE_P2_DISPLAY_PORT_SLOW 10
269 #define IRONLAKE_P2_DISPLAY_PORT_LIMIT 0
270 #define IRONLAKE_P1_DISPLAY_PORT_MIN 1
271 #define IRONLAKE_P1_DISPLAY_PORT_MAX 2
272
273 static bool
274 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
275 int target, int refclk, intel_clock_t *best_clock);
276 static bool
277 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
278 int target, int refclk, intel_clock_t *best_clock);
279 static bool
280 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
281 int target, int refclk, intel_clock_t *best_clock);
282
283 static bool
284 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
285 int target, int refclk, intel_clock_t *best_clock);
286 static bool
287 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
288 int target, int refclk, intel_clock_t *best_clock);
289
290 static const intel_limit_t intel_limits_i8xx_dvo = {
291 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
292 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
293 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
294 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
295 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
296 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
297 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
298 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
299 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
300 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
301 .find_pll = intel_find_best_PLL,
302 .find_reduced_pll = intel_find_best_reduced_PLL,
303 };
304
305 static const intel_limit_t intel_limits_i8xx_lvds = {
306 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
307 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
308 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
309 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
310 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
311 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
312 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
313 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
314 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
315 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
316 .find_pll = intel_find_best_PLL,
317 .find_reduced_pll = intel_find_best_reduced_PLL,
318 };
319
320 static const intel_limit_t intel_limits_i9xx_sdvo = {
321 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
322 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
323 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
324 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
325 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
326 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
327 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
328 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
329 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
330 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
331 .find_pll = intel_find_best_PLL,
332 .find_reduced_pll = intel_find_best_reduced_PLL,
333 };
334
335 static const intel_limit_t intel_limits_i9xx_lvds = {
336 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
337 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
338 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
339 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
340 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
341 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
342 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
343 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
344 /* The single-channel range is 25-112Mhz, and dual-channel
345 * is 80-224Mhz. Prefer single channel as much as possible.
346 */
347 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
348 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
349 .find_pll = intel_find_best_PLL,
350 .find_reduced_pll = intel_find_best_reduced_PLL,
351 };
352
353 /* below parameter and function is for G4X Chipset Family*/
354 static const intel_limit_t intel_limits_g4x_sdvo = {
355 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
356 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
357 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
358 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
359 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
360 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
361 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
362 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
363 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
364 .p2_slow = G4X_P2_SDVO_SLOW,
365 .p2_fast = G4X_P2_SDVO_FAST
366 },
367 .find_pll = intel_g4x_find_best_PLL,
368 .find_reduced_pll = intel_g4x_find_best_PLL,
369 };
370
371 static const intel_limit_t intel_limits_g4x_hdmi = {
372 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
373 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
374 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
375 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
376 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
377 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
378 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
379 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
380 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
381 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
382 .p2_fast = G4X_P2_HDMI_DAC_FAST
383 },
384 .find_pll = intel_g4x_find_best_PLL,
385 .find_reduced_pll = intel_g4x_find_best_PLL,
386 };
387
388 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
389 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
390 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
391 .vco = { .min = G4X_VCO_MIN,
392 .max = G4X_VCO_MAX },
393 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
394 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
395 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
396 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
397 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
398 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
399 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
400 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
401 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
402 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
403 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
404 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
405 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
406 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
407 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
408 },
409 .find_pll = intel_g4x_find_best_PLL,
410 .find_reduced_pll = intel_g4x_find_best_PLL,
411 };
412
413 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
414 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
415 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
416 .vco = { .min = G4X_VCO_MIN,
417 .max = G4X_VCO_MAX },
418 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
419 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
420 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
421 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
422 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
423 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
424 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
425 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
426 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
427 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
428 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
429 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
430 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
431 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
432 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
433 },
434 .find_pll = intel_g4x_find_best_PLL,
435 .find_reduced_pll = intel_g4x_find_best_PLL,
436 };
437
438 static const intel_limit_t intel_limits_g4x_display_port = {
439 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
440 .max = G4X_DOT_DISPLAY_PORT_MAX },
441 .vco = { .min = G4X_VCO_MIN,
442 .max = G4X_VCO_MAX},
443 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
444 .max = G4X_N_DISPLAY_PORT_MAX },
445 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
446 .max = G4X_M_DISPLAY_PORT_MAX },
447 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
448 .max = G4X_M1_DISPLAY_PORT_MAX },
449 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
450 .max = G4X_M2_DISPLAY_PORT_MAX },
451 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
452 .max = G4X_P_DISPLAY_PORT_MAX },
453 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
454 .max = G4X_P1_DISPLAY_PORT_MAX},
455 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
456 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
457 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
458 .find_pll = intel_find_pll_g4x_dp,
459 };
460
461 static const intel_limit_t intel_limits_pineview_sdvo = {
462 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
463 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
464 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
465 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
466 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
467 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
468 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
469 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
470 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
471 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
472 .find_pll = intel_find_best_PLL,
473 .find_reduced_pll = intel_find_best_reduced_PLL,
474 };
475
476 static const intel_limit_t intel_limits_pineview_lvds = {
477 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
478 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
479 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
480 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
481 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
482 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
483 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
484 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
485 /* Pineview only supports single-channel mode. */
486 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
487 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
488 .find_pll = intel_find_best_PLL,
489 .find_reduced_pll = intel_find_best_reduced_PLL,
490 };
491
492 static const intel_limit_t intel_limits_ironlake_sdvo = {
493 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
494 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
495 .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX },
496 .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX },
497 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
498 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
499 .p = { .min = IRONLAKE_P_SDVO_DAC_MIN, .max = IRONLAKE_P_SDVO_DAC_MAX },
500 .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX },
501 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
502 .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW,
503 .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST },
504 .find_pll = intel_g4x_find_best_PLL,
505 };
506
507 static const intel_limit_t intel_limits_ironlake_lvds = {
508 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
509 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
510 .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX },
511 .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX },
512 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
513 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
514 .p = { .min = IRONLAKE_P_LVDS_MIN, .max = IRONLAKE_P_LVDS_MAX },
515 .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX },
516 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
517 .p2_slow = IRONLAKE_P2_LVDS_SLOW,
518 .p2_fast = IRONLAKE_P2_LVDS_FAST },
519 .find_pll = intel_g4x_find_best_PLL,
520 };
521
522 static const intel_limit_t intel_limits_ironlake_display_port = {
523 .dot = { .min = IRONLAKE_DOT_MIN,
524 .max = IRONLAKE_DOT_MAX },
525 .vco = { .min = IRONLAKE_VCO_MIN,
526 .max = IRONLAKE_VCO_MAX},
527 .n = { .min = IRONLAKE_N_MIN,
528 .max = IRONLAKE_N_MAX },
529 .m = { .min = IRONLAKE_M_MIN,
530 .max = IRONLAKE_M_MAX },
531 .m1 = { .min = IRONLAKE_M1_MIN,
532 .max = IRONLAKE_M1_MAX },
533 .m2 = { .min = IRONLAKE_M2_MIN,
534 .max = IRONLAKE_M2_MAX },
535 .p = { .min = IRONLAKE_P_DISPLAY_PORT_MIN,
536 .max = IRONLAKE_P_DISPLAY_PORT_MAX },
537 .p1 = { .min = IRONLAKE_P1_DISPLAY_PORT_MIN,
538 .max = IRONLAKE_P1_DISPLAY_PORT_MAX},
539 .p2 = { .dot_limit = IRONLAKE_P2_DISPLAY_PORT_LIMIT,
540 .p2_slow = IRONLAKE_P2_DISPLAY_PORT_SLOW,
541 .p2_fast = IRONLAKE_P2_DISPLAY_PORT_FAST },
542 .find_pll = intel_find_pll_ironlake_dp,
543 };
544
545 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
546 {
547 const intel_limit_t *limit;
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
549 limit = &intel_limits_ironlake_lvds;
550 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
551 HAS_eDP)
552 limit = &intel_limits_ironlake_display_port;
553 else
554 limit = &intel_limits_ironlake_sdvo;
555
556 return limit;
557 }
558
559 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
560 {
561 struct drm_device *dev = crtc->dev;
562 struct drm_i915_private *dev_priv = dev->dev_private;
563 const intel_limit_t *limit;
564
565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
566 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
567 LVDS_CLKB_POWER_UP)
568 /* LVDS with dual channel */
569 limit = &intel_limits_g4x_dual_channel_lvds;
570 else
571 /* LVDS with dual channel */
572 limit = &intel_limits_g4x_single_channel_lvds;
573 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
574 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
575 limit = &intel_limits_g4x_hdmi;
576 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
577 limit = &intel_limits_g4x_sdvo;
578 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
579 limit = &intel_limits_g4x_display_port;
580 } else /* The option is for other outputs */
581 limit = &intel_limits_i9xx_sdvo;
582
583 return limit;
584 }
585
586 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
587 {
588 struct drm_device *dev = crtc->dev;
589 const intel_limit_t *limit;
590
591 if (IS_IRONLAKE(dev))
592 limit = intel_ironlake_limit(crtc);
593 else if (IS_G4X(dev)) {
594 limit = intel_g4x_limit(crtc);
595 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
596 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
597 limit = &intel_limits_i9xx_lvds;
598 else
599 limit = &intel_limits_i9xx_sdvo;
600 } else if (IS_PINEVIEW(dev)) {
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
602 limit = &intel_limits_pineview_lvds;
603 else
604 limit = &intel_limits_pineview_sdvo;
605 } else {
606 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
607 limit = &intel_limits_i8xx_lvds;
608 else
609 limit = &intel_limits_i8xx_dvo;
610 }
611 return limit;
612 }
613
614 /* m1 is reserved as 0 in Pineview, n is a ring counter */
615 static void pineview_clock(int refclk, intel_clock_t *clock)
616 {
617 clock->m = clock->m2 + 2;
618 clock->p = clock->p1 * clock->p2;
619 clock->vco = refclk * clock->m / clock->n;
620 clock->dot = clock->vco / clock->p;
621 }
622
623 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
624 {
625 if (IS_PINEVIEW(dev)) {
626 pineview_clock(refclk, clock);
627 return;
628 }
629 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
630 clock->p = clock->p1 * clock->p2;
631 clock->vco = refclk * clock->m / (clock->n + 2);
632 clock->dot = clock->vco / clock->p;
633 }
634
635 /**
636 * Returns whether any output on the specified pipe is of the specified type
637 */
638 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
639 {
640 struct drm_device *dev = crtc->dev;
641 struct drm_mode_config *mode_config = &dev->mode_config;
642 struct drm_connector *l_entry;
643
644 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
645 if (l_entry->encoder &&
646 l_entry->encoder->crtc == crtc) {
647 struct intel_output *intel_output = to_intel_output(l_entry);
648 if (intel_output->type == type)
649 return true;
650 }
651 }
652 return false;
653 }
654
655 struct drm_connector *
656 intel_pipe_get_output (struct drm_crtc *crtc)
657 {
658 struct drm_device *dev = crtc->dev;
659 struct drm_mode_config *mode_config = &dev->mode_config;
660 struct drm_connector *l_entry, *ret = NULL;
661
662 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
663 if (l_entry->encoder &&
664 l_entry->encoder->crtc == crtc) {
665 ret = l_entry;
666 break;
667 }
668 }
669 return ret;
670 }
671
672 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
673 /**
674 * Returns whether the given set of divisors are valid for a given refclk with
675 * the given connectors.
676 */
677
678 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
679 {
680 const intel_limit_t *limit = intel_limit (crtc);
681 struct drm_device *dev = crtc->dev;
682
683 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
684 INTELPllInvalid ("p1 out of range\n");
685 if (clock->p < limit->p.min || limit->p.max < clock->p)
686 INTELPllInvalid ("p out of range\n");
687 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
688 INTELPllInvalid ("m2 out of range\n");
689 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
690 INTELPllInvalid ("m1 out of range\n");
691 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
692 INTELPllInvalid ("m1 <= m2\n");
693 if (clock->m < limit->m.min || limit->m.max < clock->m)
694 INTELPllInvalid ("m out of range\n");
695 if (clock->n < limit->n.min || limit->n.max < clock->n)
696 INTELPllInvalid ("n out of range\n");
697 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
698 INTELPllInvalid ("vco out of range\n");
699 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
700 * connector, etc., rather than just a single range.
701 */
702 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
703 INTELPllInvalid ("dot out of range\n");
704
705 return true;
706 }
707
708 static bool
709 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
710 int target, int refclk, intel_clock_t *best_clock)
711
712 {
713 struct drm_device *dev = crtc->dev;
714 struct drm_i915_private *dev_priv = dev->dev_private;
715 intel_clock_t clock;
716 int err = target;
717
718 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
719 (I915_READ(LVDS)) != 0) {
720 /*
721 * For LVDS, if the panel is on, just rely on its current
722 * settings for dual-channel. We haven't figured out how to
723 * reliably set up different single/dual channel state, if we
724 * even can.
725 */
726 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
727 LVDS_CLKB_POWER_UP)
728 clock.p2 = limit->p2.p2_fast;
729 else
730 clock.p2 = limit->p2.p2_slow;
731 } else {
732 if (target < limit->p2.dot_limit)
733 clock.p2 = limit->p2.p2_slow;
734 else
735 clock.p2 = limit->p2.p2_fast;
736 }
737
738 memset (best_clock, 0, sizeof (*best_clock));
739
740 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
741 clock.m1++) {
742 for (clock.m2 = limit->m2.min;
743 clock.m2 <= limit->m2.max; clock.m2++) {
744 /* m1 is always 0 in Pineview */
745 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
746 break;
747 for (clock.n = limit->n.min;
748 clock.n <= limit->n.max; clock.n++) {
749 for (clock.p1 = limit->p1.min;
750 clock.p1 <= limit->p1.max; clock.p1++) {
751 int this_err;
752
753 intel_clock(dev, refclk, &clock);
754
755 if (!intel_PLL_is_valid(crtc, &clock))
756 continue;
757
758 this_err = abs(clock.dot - target);
759 if (this_err < err) {
760 *best_clock = clock;
761 err = this_err;
762 }
763 }
764 }
765 }
766 }
767
768 return (err != target);
769 }
770
771
772 static bool
773 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
774 int target, int refclk, intel_clock_t *best_clock)
775
776 {
777 struct drm_device *dev = crtc->dev;
778 intel_clock_t clock;
779 int err = target;
780 bool found = false;
781
782 memcpy(&clock, best_clock, sizeof(intel_clock_t));
783
784 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
785 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
786 /* m1 is always 0 in Pineview */
787 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
788 break;
789 for (clock.n = limit->n.min; clock.n <= limit->n.max;
790 clock.n++) {
791 int this_err;
792
793 intel_clock(dev, refclk, &clock);
794
795 if (!intel_PLL_is_valid(crtc, &clock))
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 found = true;
803 }
804 }
805 }
806 }
807
808 return found;
809 }
810
811 static bool
812 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
813 int target, int refclk, intel_clock_t *best_clock)
814 {
815 struct drm_device *dev = crtc->dev;
816 struct drm_i915_private *dev_priv = dev->dev_private;
817 intel_clock_t clock;
818 int max_n;
819 bool found;
820 /* approximately equals target * 0.00488 */
821 int err_most = (target >> 8) + (target >> 10);
822 found = false;
823
824 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
825 int lvds_reg;
826
827 if (IS_IRONLAKE(dev))
828 lvds_reg = PCH_LVDS;
829 else
830 lvds_reg = LVDS;
831 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
832 LVDS_CLKB_POWER_UP)
833 clock.p2 = limit->p2.p2_fast;
834 else
835 clock.p2 = limit->p2.p2_slow;
836 } else {
837 if (target < limit->p2.dot_limit)
838 clock.p2 = limit->p2.p2_slow;
839 else
840 clock.p2 = limit->p2.p2_fast;
841 }
842
843 memset(best_clock, 0, sizeof(*best_clock));
844 max_n = limit->n.max;
845 /* based on hardware requriment prefer smaller n to precision */
846 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
847 /* based on hardware requirment prefere larger m1,m2 */
848 for (clock.m1 = limit->m1.max;
849 clock.m1 >= limit->m1.min; clock.m1--) {
850 for (clock.m2 = limit->m2.max;
851 clock.m2 >= limit->m2.min; clock.m2--) {
852 for (clock.p1 = limit->p1.max;
853 clock.p1 >= limit->p1.min; clock.p1--) {
854 int this_err;
855
856 intel_clock(dev, refclk, &clock);
857 if (!intel_PLL_is_valid(crtc, &clock))
858 continue;
859 this_err = abs(clock.dot - target) ;
860 if (this_err < err_most) {
861 *best_clock = clock;
862 err_most = this_err;
863 max_n = clock.n;
864 found = true;
865 }
866 }
867 }
868 }
869 }
870 return found;
871 }
872
873 static bool
874 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
875 int target, int refclk, intel_clock_t *best_clock)
876 {
877 struct drm_device *dev = crtc->dev;
878 intel_clock_t clock;
879
880 /* return directly when it is eDP */
881 if (HAS_eDP)
882 return true;
883
884 if (target < 200000) {
885 clock.n = 1;
886 clock.p1 = 2;
887 clock.p2 = 10;
888 clock.m1 = 12;
889 clock.m2 = 9;
890 } else {
891 clock.n = 2;
892 clock.p1 = 1;
893 clock.p2 = 10;
894 clock.m1 = 14;
895 clock.m2 = 8;
896 }
897 intel_clock(dev, refclk, &clock);
898 memcpy(best_clock, &clock, sizeof(intel_clock_t));
899 return true;
900 }
901
902 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
903 static bool
904 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
905 int target, int refclk, intel_clock_t *best_clock)
906 {
907 intel_clock_t clock;
908 if (target < 200000) {
909 clock.p1 = 2;
910 clock.p2 = 10;
911 clock.n = 2;
912 clock.m1 = 23;
913 clock.m2 = 8;
914 } else {
915 clock.p1 = 1;
916 clock.p2 = 10;
917 clock.n = 1;
918 clock.m1 = 14;
919 clock.m2 = 2;
920 }
921 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
922 clock.p = (clock.p1 * clock.p2);
923 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
924 clock.vco = 0;
925 memcpy(best_clock, &clock, sizeof(intel_clock_t));
926 return true;
927 }
928
929 void
930 intel_wait_for_vblank(struct drm_device *dev)
931 {
932 /* Wait for 20ms, i.e. one cycle at 50hz. */
933 msleep(20);
934 }
935
936 /* Parameters have changed, update FBC info */
937 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
938 {
939 struct drm_device *dev = crtc->dev;
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 struct drm_framebuffer *fb = crtc->fb;
942 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
943 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945 int plane, i;
946 u32 fbc_ctl, fbc_ctl2;
947
948 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
949
950 if (fb->pitch < dev_priv->cfb_pitch)
951 dev_priv->cfb_pitch = fb->pitch;
952
953 /* FBC_CTL wants 64B units */
954 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
955 dev_priv->cfb_fence = obj_priv->fence_reg;
956 dev_priv->cfb_plane = intel_crtc->plane;
957 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
958
959 /* Clear old tags */
960 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
961 I915_WRITE(FBC_TAG + (i * 4), 0);
962
963 /* Set it up... */
964 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
965 if (obj_priv->tiling_mode != I915_TILING_NONE)
966 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
967 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
968 I915_WRITE(FBC_FENCE_OFF, crtc->y);
969
970 /* enable it... */
971 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
972 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
973 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
974 if (obj_priv->tiling_mode != I915_TILING_NONE)
975 fbc_ctl |= dev_priv->cfb_fence;
976 I915_WRITE(FBC_CONTROL, fbc_ctl);
977
978 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
979 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
980 }
981
982 void i8xx_disable_fbc(struct drm_device *dev)
983 {
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u32 fbc_ctl;
986
987 if (!I915_HAS_FBC(dev))
988 return;
989
990 /* Disable compression */
991 fbc_ctl = I915_READ(FBC_CONTROL);
992 fbc_ctl &= ~FBC_CTL_EN;
993 I915_WRITE(FBC_CONTROL, fbc_ctl);
994
995 /* Wait for compressing bit to clear */
996 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
997 ; /* nothing */
998
999 intel_wait_for_vblank(dev);
1000
1001 DRM_DEBUG_KMS("disabled FBC\n");
1002 }
1003
1004 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1005 {
1006 struct drm_device *dev = crtc->dev;
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008
1009 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1010 }
1011
1012 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1013 {
1014 struct drm_device *dev = crtc->dev;
1015 struct drm_i915_private *dev_priv = dev->dev_private;
1016 struct drm_framebuffer *fb = crtc->fb;
1017 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1018 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1020 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1021 DPFC_CTL_PLANEB);
1022 unsigned long stall_watermark = 200;
1023 u32 dpfc_ctl;
1024
1025 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1026 dev_priv->cfb_fence = obj_priv->fence_reg;
1027 dev_priv->cfb_plane = intel_crtc->plane;
1028
1029 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1030 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1031 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1032 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1033 } else {
1034 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1035 }
1036
1037 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1038 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1039 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1040 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1041 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1042
1043 /* enable it... */
1044 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1045
1046 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1047 }
1048
1049 void g4x_disable_fbc(struct drm_device *dev)
1050 {
1051 struct drm_i915_private *dev_priv = dev->dev_private;
1052 u32 dpfc_ctl;
1053
1054 /* Disable compression */
1055 dpfc_ctl = I915_READ(DPFC_CONTROL);
1056 dpfc_ctl &= ~DPFC_CTL_EN;
1057 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1058 intel_wait_for_vblank(dev);
1059
1060 DRM_DEBUG_KMS("disabled FBC\n");
1061 }
1062
1063 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1064 {
1065 struct drm_device *dev = crtc->dev;
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067
1068 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1069 }
1070
1071 /**
1072 * intel_update_fbc - enable/disable FBC as needed
1073 * @crtc: CRTC to point the compressor at
1074 * @mode: mode in use
1075 *
1076 * Set up the framebuffer compression hardware at mode set time. We
1077 * enable it if possible:
1078 * - plane A only (on pre-965)
1079 * - no pixel mulitply/line duplication
1080 * - no alpha buffer discard
1081 * - no dual wide
1082 * - framebuffer <= 2048 in width, 1536 in height
1083 *
1084 * We can't assume that any compression will take place (worst case),
1085 * so the compressed buffer has to be the same size as the uncompressed
1086 * one. It also must reside (along with the line length buffer) in
1087 * stolen memory.
1088 *
1089 * We need to enable/disable FBC on a global basis.
1090 */
1091 static void intel_update_fbc(struct drm_crtc *crtc,
1092 struct drm_display_mode *mode)
1093 {
1094 struct drm_device *dev = crtc->dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct drm_framebuffer *fb = crtc->fb;
1097 struct intel_framebuffer *intel_fb;
1098 struct drm_i915_gem_object *obj_priv;
1099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1100 int plane = intel_crtc->plane;
1101
1102 if (!i915_powersave)
1103 return;
1104
1105 if (!dev_priv->display.fbc_enabled ||
1106 !dev_priv->display.enable_fbc ||
1107 !dev_priv->display.disable_fbc)
1108 return;
1109
1110 if (!crtc->fb)
1111 return;
1112
1113 intel_fb = to_intel_framebuffer(fb);
1114 obj_priv = intel_fb->obj->driver_private;
1115
1116 /*
1117 * If FBC is already on, we just have to verify that we can
1118 * keep it that way...
1119 * Need to disable if:
1120 * - changing FBC params (stride, fence, mode)
1121 * - new fb is too large to fit in compressed buffer
1122 * - going to an unsupported config (interlace, pixel multiply, etc.)
1123 */
1124 if (intel_fb->obj->size > dev_priv->cfb_size) {
1125 DRM_DEBUG_KMS("framebuffer too large, disabling "
1126 "compression\n");
1127 goto out_disable;
1128 }
1129 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1130 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1131 DRM_DEBUG_KMS("mode incompatible with compression, "
1132 "disabling\n");
1133 goto out_disable;
1134 }
1135 if ((mode->hdisplay > 2048) ||
1136 (mode->vdisplay > 1536)) {
1137 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1138 goto out_disable;
1139 }
1140 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1141 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1142 goto out_disable;
1143 }
1144 if (obj_priv->tiling_mode != I915_TILING_X) {
1145 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1146 goto out_disable;
1147 }
1148
1149 if (dev_priv->display.fbc_enabled(crtc)) {
1150 /* We can re-enable it in this case, but need to update pitch */
1151 if (fb->pitch > dev_priv->cfb_pitch)
1152 dev_priv->display.disable_fbc(dev);
1153 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1154 dev_priv->display.disable_fbc(dev);
1155 if (plane != dev_priv->cfb_plane)
1156 dev_priv->display.disable_fbc(dev);
1157 }
1158
1159 if (!dev_priv->display.fbc_enabled(crtc)) {
1160 /* Now try to turn it back on if possible */
1161 dev_priv->display.enable_fbc(crtc, 500);
1162 }
1163
1164 return;
1165
1166 out_disable:
1167 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1168 /* Multiple disables should be harmless */
1169 if (dev_priv->display.fbc_enabled(crtc))
1170 dev_priv->display.disable_fbc(dev);
1171 }
1172
1173 static int
1174 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1175 {
1176 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1177 u32 alignment;
1178 int ret;
1179
1180 switch (obj_priv->tiling_mode) {
1181 case I915_TILING_NONE:
1182 alignment = 64 * 1024;
1183 break;
1184 case I915_TILING_X:
1185 /* pin() will align the object as required by fence */
1186 alignment = 0;
1187 break;
1188 case I915_TILING_Y:
1189 /* FIXME: Is this true? */
1190 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1191 return -EINVAL;
1192 default:
1193 BUG();
1194 }
1195
1196 ret = i915_gem_object_pin(obj, alignment);
1197 if (ret != 0)
1198 return ret;
1199
1200 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1201 * fence, whereas 965+ only requires a fence if using
1202 * framebuffer compression. For simplicity, we always install
1203 * a fence as the cost is not that onerous.
1204 */
1205 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1206 obj_priv->tiling_mode != I915_TILING_NONE) {
1207 ret = i915_gem_object_get_fence_reg(obj);
1208 if (ret != 0) {
1209 i915_gem_object_unpin(obj);
1210 return ret;
1211 }
1212 }
1213
1214 return 0;
1215 }
1216
1217 static int
1218 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1219 struct drm_framebuffer *old_fb)
1220 {
1221 struct drm_device *dev = crtc->dev;
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 struct drm_i915_master_private *master_priv;
1224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1225 struct intel_framebuffer *intel_fb;
1226 struct drm_i915_gem_object *obj_priv;
1227 struct drm_gem_object *obj;
1228 int pipe = intel_crtc->pipe;
1229 int plane = intel_crtc->plane;
1230 unsigned long Start, Offset;
1231 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1232 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1233 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1234 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1235 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1236 u32 dspcntr;
1237 int ret;
1238
1239 /* no fb bound */
1240 if (!crtc->fb) {
1241 DRM_DEBUG_KMS("No FB bound\n");
1242 return 0;
1243 }
1244
1245 switch (plane) {
1246 case 0:
1247 case 1:
1248 break;
1249 default:
1250 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1251 return -EINVAL;
1252 }
1253
1254 intel_fb = to_intel_framebuffer(crtc->fb);
1255 obj = intel_fb->obj;
1256 obj_priv = obj->driver_private;
1257
1258 mutex_lock(&dev->struct_mutex);
1259 ret = intel_pin_and_fence_fb_obj(dev, obj);
1260 if (ret != 0) {
1261 mutex_unlock(&dev->struct_mutex);
1262 return ret;
1263 }
1264
1265 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1266 if (ret != 0) {
1267 i915_gem_object_unpin(obj);
1268 mutex_unlock(&dev->struct_mutex);
1269 return ret;
1270 }
1271
1272 dspcntr = I915_READ(dspcntr_reg);
1273 /* Mask out pixel format bits in case we change it */
1274 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1275 switch (crtc->fb->bits_per_pixel) {
1276 case 8:
1277 dspcntr |= DISPPLANE_8BPP;
1278 break;
1279 case 16:
1280 if (crtc->fb->depth == 15)
1281 dspcntr |= DISPPLANE_15_16BPP;
1282 else
1283 dspcntr |= DISPPLANE_16BPP;
1284 break;
1285 case 24:
1286 case 32:
1287 if (crtc->fb->depth == 30)
1288 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1289 else
1290 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1291 break;
1292 default:
1293 DRM_ERROR("Unknown color depth\n");
1294 i915_gem_object_unpin(obj);
1295 mutex_unlock(&dev->struct_mutex);
1296 return -EINVAL;
1297 }
1298 if (IS_I965G(dev)) {
1299 if (obj_priv->tiling_mode != I915_TILING_NONE)
1300 dspcntr |= DISPPLANE_TILED;
1301 else
1302 dspcntr &= ~DISPPLANE_TILED;
1303 }
1304
1305 if (IS_IRONLAKE(dev))
1306 /* must disable */
1307 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1308
1309 I915_WRITE(dspcntr_reg, dspcntr);
1310
1311 Start = obj_priv->gtt_offset;
1312 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1313
1314 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1315 I915_WRITE(dspstride, crtc->fb->pitch);
1316 if (IS_I965G(dev)) {
1317 I915_WRITE(dspbase, Offset);
1318 I915_READ(dspbase);
1319 I915_WRITE(dspsurf, Start);
1320 I915_READ(dspsurf);
1321 I915_WRITE(dsptileoff, (y << 16) | x);
1322 } else {
1323 I915_WRITE(dspbase, Start + Offset);
1324 I915_READ(dspbase);
1325 }
1326
1327 if ((IS_I965G(dev) || plane == 0))
1328 intel_update_fbc(crtc, &crtc->mode);
1329
1330 intel_wait_for_vblank(dev);
1331
1332 if (old_fb) {
1333 intel_fb = to_intel_framebuffer(old_fb);
1334 obj_priv = intel_fb->obj->driver_private;
1335 i915_gem_object_unpin(intel_fb->obj);
1336 }
1337 intel_increase_pllclock(crtc, true);
1338
1339 mutex_unlock(&dev->struct_mutex);
1340
1341 if (!dev->primary->master)
1342 return 0;
1343
1344 master_priv = dev->primary->master->driver_priv;
1345 if (!master_priv->sarea_priv)
1346 return 0;
1347
1348 if (pipe) {
1349 master_priv->sarea_priv->pipeB_x = x;
1350 master_priv->sarea_priv->pipeB_y = y;
1351 } else {
1352 master_priv->sarea_priv->pipeA_x = x;
1353 master_priv->sarea_priv->pipeA_y = y;
1354 }
1355
1356 return 0;
1357 }
1358
1359 /* Disable the VGA plane that we never use */
1360 static void i915_disable_vga (struct drm_device *dev)
1361 {
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 u8 sr1;
1364 u32 vga_reg;
1365
1366 if (IS_IRONLAKE(dev))
1367 vga_reg = CPU_VGACNTRL;
1368 else
1369 vga_reg = VGACNTRL;
1370
1371 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1372 return;
1373
1374 I915_WRITE8(VGA_SR_INDEX, 1);
1375 sr1 = I915_READ8(VGA_SR_DATA);
1376 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1377 udelay(100);
1378
1379 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1380 }
1381
1382 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1383 {
1384 struct drm_device *dev = crtc->dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 u32 dpa_ctl;
1387
1388 DRM_DEBUG_KMS("\n");
1389 dpa_ctl = I915_READ(DP_A);
1390 dpa_ctl &= ~DP_PLL_ENABLE;
1391 I915_WRITE(DP_A, dpa_ctl);
1392 }
1393
1394 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1395 {
1396 struct drm_device *dev = crtc->dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398 u32 dpa_ctl;
1399
1400 dpa_ctl = I915_READ(DP_A);
1401 dpa_ctl |= DP_PLL_ENABLE;
1402 I915_WRITE(DP_A, dpa_ctl);
1403 udelay(200);
1404 }
1405
1406
1407 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1408 {
1409 struct drm_device *dev = crtc->dev;
1410 struct drm_i915_private *dev_priv = dev->dev_private;
1411 u32 dpa_ctl;
1412
1413 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1414 dpa_ctl = I915_READ(DP_A);
1415 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1416
1417 if (clock < 200000) {
1418 u32 temp;
1419 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1420 /* workaround for 160Mhz:
1421 1) program 0x4600c bits 15:0 = 0x8124
1422 2) program 0x46010 bit 0 = 1
1423 3) program 0x46034 bit 24 = 1
1424 4) program 0x64000 bit 14 = 1
1425 */
1426 temp = I915_READ(0x4600c);
1427 temp &= 0xffff0000;
1428 I915_WRITE(0x4600c, temp | 0x8124);
1429
1430 temp = I915_READ(0x46010);
1431 I915_WRITE(0x46010, temp | 1);
1432
1433 temp = I915_READ(0x46034);
1434 I915_WRITE(0x46034, temp | (1 << 24));
1435 } else {
1436 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1437 }
1438 I915_WRITE(DP_A, dpa_ctl);
1439
1440 udelay(500);
1441 }
1442
1443 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1444 {
1445 struct drm_device *dev = crtc->dev;
1446 struct drm_i915_private *dev_priv = dev->dev_private;
1447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1448 int pipe = intel_crtc->pipe;
1449 int plane = intel_crtc->plane;
1450 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1451 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1452 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1453 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1454 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1455 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1456 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1457 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1458 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1459 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1460 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1461 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1462 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1463 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1464 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1465 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1466 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1467 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1468 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1469 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1470 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1471 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1472 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1473 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1474 u32 temp;
1475 int tries = 5, j, n;
1476 u32 pipe_bpc;
1477
1478 temp = I915_READ(pipeconf_reg);
1479 pipe_bpc = temp & PIPE_BPC_MASK;
1480
1481 /* XXX: When our outputs are all unaware of DPMS modes other than off
1482 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1483 */
1484 switch (mode) {
1485 case DRM_MODE_DPMS_ON:
1486 case DRM_MODE_DPMS_STANDBY:
1487 case DRM_MODE_DPMS_SUSPEND:
1488 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1489
1490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1491 temp = I915_READ(PCH_LVDS);
1492 if ((temp & LVDS_PORT_EN) == 0) {
1493 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1494 POSTING_READ(PCH_LVDS);
1495 }
1496 }
1497
1498 if (HAS_eDP) {
1499 /* enable eDP PLL */
1500 ironlake_enable_pll_edp(crtc);
1501 } else {
1502 /* enable PCH DPLL */
1503 temp = I915_READ(pch_dpll_reg);
1504 if ((temp & DPLL_VCO_ENABLE) == 0) {
1505 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1506 I915_READ(pch_dpll_reg);
1507 }
1508
1509 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1510 temp = I915_READ(fdi_rx_reg);
1511 /*
1512 * make the BPC in FDI Rx be consistent with that in
1513 * pipeconf reg.
1514 */
1515 temp &= ~(0x7 << 16);
1516 temp |= (pipe_bpc << 11);
1517 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1518 FDI_SEL_PCDCLK |
1519 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1520 I915_READ(fdi_rx_reg);
1521 udelay(200);
1522
1523 /* Enable CPU FDI TX PLL, always on for Ironlake */
1524 temp = I915_READ(fdi_tx_reg);
1525 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1526 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1527 I915_READ(fdi_tx_reg);
1528 udelay(100);
1529 }
1530 }
1531
1532 /* Enable panel fitting for LVDS */
1533 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1534 temp = I915_READ(pf_ctl_reg);
1535 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1536
1537 /* currently full aspect */
1538 I915_WRITE(pf_win_pos, 0);
1539
1540 I915_WRITE(pf_win_size,
1541 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1542 (dev_priv->panel_fixed_mode->vdisplay));
1543 }
1544
1545 /* Enable CPU pipe */
1546 temp = I915_READ(pipeconf_reg);
1547 if ((temp & PIPEACONF_ENABLE) == 0) {
1548 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1549 I915_READ(pipeconf_reg);
1550 udelay(100);
1551 }
1552
1553 /* configure and enable CPU plane */
1554 temp = I915_READ(dspcntr_reg);
1555 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1556 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1557 /* Flush the plane changes */
1558 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1559 }
1560
1561 if (!HAS_eDP) {
1562 /* enable CPU FDI TX and PCH FDI RX */
1563 temp = I915_READ(fdi_tx_reg);
1564 temp |= FDI_TX_ENABLE;
1565 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1566 temp &= ~FDI_LINK_TRAIN_NONE;
1567 temp |= FDI_LINK_TRAIN_PATTERN_1;
1568 I915_WRITE(fdi_tx_reg, temp);
1569 I915_READ(fdi_tx_reg);
1570
1571 temp = I915_READ(fdi_rx_reg);
1572 temp &= ~FDI_LINK_TRAIN_NONE;
1573 temp |= FDI_LINK_TRAIN_PATTERN_1;
1574 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1575 I915_READ(fdi_rx_reg);
1576
1577 udelay(150);
1578
1579 /* Train FDI. */
1580 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1581 for train result */
1582 temp = I915_READ(fdi_rx_imr_reg);
1583 temp &= ~FDI_RX_SYMBOL_LOCK;
1584 temp &= ~FDI_RX_BIT_LOCK;
1585 I915_WRITE(fdi_rx_imr_reg, temp);
1586 I915_READ(fdi_rx_imr_reg);
1587 udelay(150);
1588
1589 temp = I915_READ(fdi_rx_iir_reg);
1590 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1591
1592 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1593 for (j = 0; j < tries; j++) {
1594 temp = I915_READ(fdi_rx_iir_reg);
1595 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1596 temp);
1597 if (temp & FDI_RX_BIT_LOCK)
1598 break;
1599 udelay(200);
1600 }
1601 if (j != tries)
1602 I915_WRITE(fdi_rx_iir_reg,
1603 temp | FDI_RX_BIT_LOCK);
1604 else
1605 DRM_DEBUG_KMS("train 1 fail\n");
1606 } else {
1607 I915_WRITE(fdi_rx_iir_reg,
1608 temp | FDI_RX_BIT_LOCK);
1609 DRM_DEBUG_KMS("train 1 ok 2!\n");
1610 }
1611 temp = I915_READ(fdi_tx_reg);
1612 temp &= ~FDI_LINK_TRAIN_NONE;
1613 temp |= FDI_LINK_TRAIN_PATTERN_2;
1614 I915_WRITE(fdi_tx_reg, temp);
1615
1616 temp = I915_READ(fdi_rx_reg);
1617 temp &= ~FDI_LINK_TRAIN_NONE;
1618 temp |= FDI_LINK_TRAIN_PATTERN_2;
1619 I915_WRITE(fdi_rx_reg, temp);
1620
1621 udelay(150);
1622
1623 temp = I915_READ(fdi_rx_iir_reg);
1624 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1625
1626 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1627 for (j = 0; j < tries; j++) {
1628 temp = I915_READ(fdi_rx_iir_reg);
1629 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1630 temp);
1631 if (temp & FDI_RX_SYMBOL_LOCK)
1632 break;
1633 udelay(200);
1634 }
1635 if (j != tries) {
1636 I915_WRITE(fdi_rx_iir_reg,
1637 temp | FDI_RX_SYMBOL_LOCK);
1638 DRM_DEBUG_KMS("train 2 ok 1!\n");
1639 } else
1640 DRM_DEBUG_KMS("train 2 fail\n");
1641 } else {
1642 I915_WRITE(fdi_rx_iir_reg,
1643 temp | FDI_RX_SYMBOL_LOCK);
1644 DRM_DEBUG_KMS("train 2 ok 2!\n");
1645 }
1646 DRM_DEBUG_KMS("train done\n");
1647
1648 /* set transcoder timing */
1649 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1650 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1651 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1652
1653 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1654 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1655 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1656
1657 /* enable PCH transcoder */
1658 temp = I915_READ(transconf_reg);
1659 /*
1660 * make the BPC in transcoder be consistent with
1661 * that in pipeconf reg.
1662 */
1663 temp &= ~PIPE_BPC_MASK;
1664 temp |= pipe_bpc;
1665 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1666 I915_READ(transconf_reg);
1667
1668 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1669 ;
1670
1671 /* enable normal */
1672
1673 temp = I915_READ(fdi_tx_reg);
1674 temp &= ~FDI_LINK_TRAIN_NONE;
1675 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1676 FDI_TX_ENHANCE_FRAME_ENABLE);
1677 I915_READ(fdi_tx_reg);
1678
1679 temp = I915_READ(fdi_rx_reg);
1680 temp &= ~FDI_LINK_TRAIN_NONE;
1681 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1682 FDI_RX_ENHANCE_FRAME_ENABLE);
1683 I915_READ(fdi_rx_reg);
1684
1685 /* wait one idle pattern time */
1686 udelay(100);
1687
1688 }
1689
1690 intel_crtc_load_lut(crtc);
1691
1692 break;
1693 case DRM_MODE_DPMS_OFF:
1694 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1695
1696 /* Disable display plane */
1697 temp = I915_READ(dspcntr_reg);
1698 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1699 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1700 /* Flush the plane changes */
1701 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1702 I915_READ(dspbase_reg);
1703 }
1704
1705 i915_disable_vga(dev);
1706
1707 /* disable cpu pipe, disable after all planes disabled */
1708 temp = I915_READ(pipeconf_reg);
1709 if ((temp & PIPEACONF_ENABLE) != 0) {
1710 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1711 I915_READ(pipeconf_reg);
1712 n = 0;
1713 /* wait for cpu pipe off, pipe state */
1714 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1715 n++;
1716 if (n < 60) {
1717 udelay(500);
1718 continue;
1719 } else {
1720 DRM_DEBUG_KMS("pipe %d off delay\n",
1721 pipe);
1722 break;
1723 }
1724 }
1725 } else
1726 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1727
1728 udelay(100);
1729
1730 /* Disable PF */
1731 temp = I915_READ(pf_ctl_reg);
1732 if ((temp & PF_ENABLE) != 0) {
1733 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1734 I915_READ(pf_ctl_reg);
1735 }
1736 I915_WRITE(pf_win_size, 0);
1737
1738 /* disable CPU FDI tx and PCH FDI rx */
1739 temp = I915_READ(fdi_tx_reg);
1740 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1741 I915_READ(fdi_tx_reg);
1742
1743 temp = I915_READ(fdi_rx_reg);
1744 /* BPC in FDI rx is consistent with that in pipeconf */
1745 temp &= ~(0x07 << 16);
1746 temp |= (pipe_bpc << 11);
1747 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1748 I915_READ(fdi_rx_reg);
1749
1750 udelay(100);
1751
1752 /* still set train pattern 1 */
1753 temp = I915_READ(fdi_tx_reg);
1754 temp &= ~FDI_LINK_TRAIN_NONE;
1755 temp |= FDI_LINK_TRAIN_PATTERN_1;
1756 I915_WRITE(fdi_tx_reg, temp);
1757
1758 temp = I915_READ(fdi_rx_reg);
1759 temp &= ~FDI_LINK_TRAIN_NONE;
1760 temp |= FDI_LINK_TRAIN_PATTERN_1;
1761 I915_WRITE(fdi_rx_reg, temp);
1762
1763 udelay(100);
1764
1765 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1766 temp = I915_READ(PCH_LVDS);
1767 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1768 I915_READ(PCH_LVDS);
1769 udelay(100);
1770 }
1771
1772 /* disable PCH transcoder */
1773 temp = I915_READ(transconf_reg);
1774 if ((temp & TRANS_ENABLE) != 0) {
1775 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1776 I915_READ(transconf_reg);
1777 n = 0;
1778 /* wait for PCH transcoder off, transcoder state */
1779 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1780 n++;
1781 if (n < 60) {
1782 udelay(500);
1783 continue;
1784 } else {
1785 DRM_DEBUG_KMS("transcoder %d off "
1786 "delay\n", pipe);
1787 break;
1788 }
1789 }
1790 }
1791 temp = I915_READ(transconf_reg);
1792 /* BPC in transcoder is consistent with that in pipeconf */
1793 temp &= ~PIPE_BPC_MASK;
1794 temp |= pipe_bpc;
1795 I915_WRITE(transconf_reg, temp);
1796 I915_READ(transconf_reg);
1797 udelay(100);
1798
1799 /* disable PCH DPLL */
1800 temp = I915_READ(pch_dpll_reg);
1801 if ((temp & DPLL_VCO_ENABLE) != 0) {
1802 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1803 I915_READ(pch_dpll_reg);
1804 }
1805
1806 if (HAS_eDP) {
1807 ironlake_disable_pll_edp(crtc);
1808 }
1809
1810 temp = I915_READ(fdi_rx_reg);
1811 temp &= ~FDI_SEL_PCDCLK;
1812 I915_WRITE(fdi_rx_reg, temp);
1813 I915_READ(fdi_rx_reg);
1814
1815 temp = I915_READ(fdi_rx_reg);
1816 temp &= ~FDI_RX_PLL_ENABLE;
1817 I915_WRITE(fdi_rx_reg, temp);
1818 I915_READ(fdi_rx_reg);
1819
1820 /* Disable CPU FDI TX PLL */
1821 temp = I915_READ(fdi_tx_reg);
1822 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1823 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1824 I915_READ(fdi_tx_reg);
1825 udelay(100);
1826 }
1827
1828 /* Wait for the clocks to turn off. */
1829 udelay(100);
1830 break;
1831 }
1832 }
1833
1834 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1835 {
1836 struct intel_overlay *overlay;
1837 int ret;
1838
1839 if (!enable && intel_crtc->overlay) {
1840 overlay = intel_crtc->overlay;
1841 mutex_lock(&overlay->dev->struct_mutex);
1842 for (;;) {
1843 ret = intel_overlay_switch_off(overlay);
1844 if (ret == 0)
1845 break;
1846
1847 ret = intel_overlay_recover_from_interrupt(overlay, 0);
1848 if (ret != 0) {
1849 /* overlay doesn't react anymore. Usually
1850 * results in a black screen and an unkillable
1851 * X server. */
1852 BUG();
1853 overlay->hw_wedged = HW_WEDGED;
1854 break;
1855 }
1856 }
1857 mutex_unlock(&overlay->dev->struct_mutex);
1858 }
1859 /* Let userspace switch the overlay on again. In most cases userspace
1860 * has to recompute where to put it anyway. */
1861
1862 return;
1863 }
1864
1865 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1866 {
1867 struct drm_device *dev = crtc->dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1870 int pipe = intel_crtc->pipe;
1871 int plane = intel_crtc->plane;
1872 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1873 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1874 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1875 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1876 u32 temp;
1877
1878 /* XXX: When our outputs are all unaware of DPMS modes other than off
1879 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1880 */
1881 switch (mode) {
1882 case DRM_MODE_DPMS_ON:
1883 case DRM_MODE_DPMS_STANDBY:
1884 case DRM_MODE_DPMS_SUSPEND:
1885 intel_update_watermarks(dev);
1886
1887 /* Enable the DPLL */
1888 temp = I915_READ(dpll_reg);
1889 if ((temp & DPLL_VCO_ENABLE) == 0) {
1890 I915_WRITE(dpll_reg, temp);
1891 I915_READ(dpll_reg);
1892 /* Wait for the clocks to stabilize. */
1893 udelay(150);
1894 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1895 I915_READ(dpll_reg);
1896 /* Wait for the clocks to stabilize. */
1897 udelay(150);
1898 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1899 I915_READ(dpll_reg);
1900 /* Wait for the clocks to stabilize. */
1901 udelay(150);
1902 }
1903
1904 /* Enable the pipe */
1905 temp = I915_READ(pipeconf_reg);
1906 if ((temp & PIPEACONF_ENABLE) == 0)
1907 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1908
1909 /* Enable the plane */
1910 temp = I915_READ(dspcntr_reg);
1911 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1912 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1913 /* Flush the plane changes */
1914 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1915 }
1916
1917 intel_crtc_load_lut(crtc);
1918
1919 if ((IS_I965G(dev) || plane == 0))
1920 intel_update_fbc(crtc, &crtc->mode);
1921
1922 /* Give the overlay scaler a chance to enable if it's on this pipe */
1923 intel_crtc_dpms_overlay(intel_crtc, true);
1924 break;
1925 case DRM_MODE_DPMS_OFF:
1926 intel_update_watermarks(dev);
1927
1928 /* Give the overlay scaler a chance to disable if it's on this pipe */
1929 intel_crtc_dpms_overlay(intel_crtc, false);
1930 drm_vblank_off(dev, pipe);
1931
1932 if (dev_priv->cfb_plane == plane &&
1933 dev_priv->display.disable_fbc)
1934 dev_priv->display.disable_fbc(dev);
1935
1936 /* Disable the VGA plane that we never use */
1937 i915_disable_vga(dev);
1938
1939 /* Disable display plane */
1940 temp = I915_READ(dspcntr_reg);
1941 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1942 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1943 /* Flush the plane changes */
1944 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1945 I915_READ(dspbase_reg);
1946 }
1947
1948 if (!IS_I9XX(dev)) {
1949 /* Wait for vblank for the disable to take effect */
1950 intel_wait_for_vblank(dev);
1951 }
1952
1953 /* Next, disable display pipes */
1954 temp = I915_READ(pipeconf_reg);
1955 if ((temp & PIPEACONF_ENABLE) != 0) {
1956 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1957 I915_READ(pipeconf_reg);
1958 }
1959
1960 /* Wait for vblank for the disable to take effect. */
1961 intel_wait_for_vblank(dev);
1962
1963 temp = I915_READ(dpll_reg);
1964 if ((temp & DPLL_VCO_ENABLE) != 0) {
1965 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1966 I915_READ(dpll_reg);
1967 }
1968
1969 /* Wait for the clocks to turn off. */
1970 udelay(150);
1971 break;
1972 }
1973 }
1974
1975 /**
1976 * Sets the power management mode of the pipe and plane.
1977 *
1978 * This code should probably grow support for turning the cursor off and back
1979 * on appropriately at the same time as we're turning the pipe off/on.
1980 */
1981 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1982 {
1983 struct drm_device *dev = crtc->dev;
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1985 struct drm_i915_master_private *master_priv;
1986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1987 int pipe = intel_crtc->pipe;
1988 bool enabled;
1989
1990 dev_priv->display.dpms(crtc, mode);
1991
1992 intel_crtc->dpms_mode = mode;
1993
1994 if (!dev->primary->master)
1995 return;
1996
1997 master_priv = dev->primary->master->driver_priv;
1998 if (!master_priv->sarea_priv)
1999 return;
2000
2001 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2002
2003 switch (pipe) {
2004 case 0:
2005 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2006 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2007 break;
2008 case 1:
2009 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2010 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2011 break;
2012 default:
2013 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2014 break;
2015 }
2016 }
2017
2018 static void intel_crtc_prepare (struct drm_crtc *crtc)
2019 {
2020 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2021 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2022 }
2023
2024 static void intel_crtc_commit (struct drm_crtc *crtc)
2025 {
2026 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2027 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2028 }
2029
2030 void intel_encoder_prepare (struct drm_encoder *encoder)
2031 {
2032 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2033 /* lvds has its own version of prepare see intel_lvds_prepare */
2034 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2035 }
2036
2037 void intel_encoder_commit (struct drm_encoder *encoder)
2038 {
2039 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2040 /* lvds has its own version of commit see intel_lvds_commit */
2041 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2042 }
2043
2044 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2045 struct drm_display_mode *mode,
2046 struct drm_display_mode *adjusted_mode)
2047 {
2048 struct drm_device *dev = crtc->dev;
2049 if (IS_IRONLAKE(dev)) {
2050 /* FDI link clock is fixed at 2.7G */
2051 if (mode->clock * 3 > 27000 * 4)
2052 return MODE_CLOCK_HIGH;
2053 }
2054 return true;
2055 }
2056
2057 static int i945_get_display_clock_speed(struct drm_device *dev)
2058 {
2059 return 400000;
2060 }
2061
2062 static int i915_get_display_clock_speed(struct drm_device *dev)
2063 {
2064 return 333000;
2065 }
2066
2067 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2068 {
2069 return 200000;
2070 }
2071
2072 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2073 {
2074 u16 gcfgc = 0;
2075
2076 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2077
2078 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2079 return 133000;
2080 else {
2081 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2082 case GC_DISPLAY_CLOCK_333_MHZ:
2083 return 333000;
2084 default:
2085 case GC_DISPLAY_CLOCK_190_200_MHZ:
2086 return 190000;
2087 }
2088 }
2089 }
2090
2091 static int i865_get_display_clock_speed(struct drm_device *dev)
2092 {
2093 return 266000;
2094 }
2095
2096 static int i855_get_display_clock_speed(struct drm_device *dev)
2097 {
2098 u16 hpllcc = 0;
2099 /* Assume that the hardware is in the high speed state. This
2100 * should be the default.
2101 */
2102 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2103 case GC_CLOCK_133_200:
2104 case GC_CLOCK_100_200:
2105 return 200000;
2106 case GC_CLOCK_166_250:
2107 return 250000;
2108 case GC_CLOCK_100_133:
2109 return 133000;
2110 }
2111
2112 /* Shouldn't happen */
2113 return 0;
2114 }
2115
2116 static int i830_get_display_clock_speed(struct drm_device *dev)
2117 {
2118 return 133000;
2119 }
2120
2121 /**
2122 * Return the pipe currently connected to the panel fitter,
2123 * or -1 if the panel fitter is not present or not in use
2124 */
2125 int intel_panel_fitter_pipe (struct drm_device *dev)
2126 {
2127 struct drm_i915_private *dev_priv = dev->dev_private;
2128 u32 pfit_control;
2129
2130 /* i830 doesn't have a panel fitter */
2131 if (IS_I830(dev))
2132 return -1;
2133
2134 pfit_control = I915_READ(PFIT_CONTROL);
2135
2136 /* See if the panel fitter is in use */
2137 if ((pfit_control & PFIT_ENABLE) == 0)
2138 return -1;
2139
2140 /* 965 can place panel fitter on either pipe */
2141 if (IS_I965G(dev))
2142 return (pfit_control >> 29) & 0x3;
2143
2144 /* older chips can only use pipe 1 */
2145 return 1;
2146 }
2147
2148 struct fdi_m_n {
2149 u32 tu;
2150 u32 gmch_m;
2151 u32 gmch_n;
2152 u32 link_m;
2153 u32 link_n;
2154 };
2155
2156 static void
2157 fdi_reduce_ratio(u32 *num, u32 *den)
2158 {
2159 while (*num > 0xffffff || *den > 0xffffff) {
2160 *num >>= 1;
2161 *den >>= 1;
2162 }
2163 }
2164
2165 #define DATA_N 0x800000
2166 #define LINK_N 0x80000
2167
2168 static void
2169 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2170 int link_clock, struct fdi_m_n *m_n)
2171 {
2172 u64 temp;
2173
2174 m_n->tu = 64; /* default size */
2175
2176 temp = (u64) DATA_N * pixel_clock;
2177 temp = div_u64(temp, link_clock);
2178 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2179 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2180 m_n->gmch_n = DATA_N;
2181 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2182
2183 temp = (u64) LINK_N * pixel_clock;
2184 m_n->link_m = div_u64(temp, link_clock);
2185 m_n->link_n = LINK_N;
2186 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2187 }
2188
2189
2190 struct intel_watermark_params {
2191 unsigned long fifo_size;
2192 unsigned long max_wm;
2193 unsigned long default_wm;
2194 unsigned long guard_size;
2195 unsigned long cacheline_size;
2196 };
2197
2198 /* Pineview has different values for various configs */
2199 static struct intel_watermark_params pineview_display_wm = {
2200 PINEVIEW_DISPLAY_FIFO,
2201 PINEVIEW_MAX_WM,
2202 PINEVIEW_DFT_WM,
2203 PINEVIEW_GUARD_WM,
2204 PINEVIEW_FIFO_LINE_SIZE
2205 };
2206 static struct intel_watermark_params pineview_display_hplloff_wm = {
2207 PINEVIEW_DISPLAY_FIFO,
2208 PINEVIEW_MAX_WM,
2209 PINEVIEW_DFT_HPLLOFF_WM,
2210 PINEVIEW_GUARD_WM,
2211 PINEVIEW_FIFO_LINE_SIZE
2212 };
2213 static struct intel_watermark_params pineview_cursor_wm = {
2214 PINEVIEW_CURSOR_FIFO,
2215 PINEVIEW_CURSOR_MAX_WM,
2216 PINEVIEW_CURSOR_DFT_WM,
2217 PINEVIEW_CURSOR_GUARD_WM,
2218 PINEVIEW_FIFO_LINE_SIZE,
2219 };
2220 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2221 PINEVIEW_CURSOR_FIFO,
2222 PINEVIEW_CURSOR_MAX_WM,
2223 PINEVIEW_CURSOR_DFT_WM,
2224 PINEVIEW_CURSOR_GUARD_WM,
2225 PINEVIEW_FIFO_LINE_SIZE
2226 };
2227 static struct intel_watermark_params g4x_wm_info = {
2228 G4X_FIFO_SIZE,
2229 G4X_MAX_WM,
2230 G4X_MAX_WM,
2231 2,
2232 G4X_FIFO_LINE_SIZE,
2233 };
2234 static struct intel_watermark_params i945_wm_info = {
2235 I945_FIFO_SIZE,
2236 I915_MAX_WM,
2237 1,
2238 2,
2239 I915_FIFO_LINE_SIZE
2240 };
2241 static struct intel_watermark_params i915_wm_info = {
2242 I915_FIFO_SIZE,
2243 I915_MAX_WM,
2244 1,
2245 2,
2246 I915_FIFO_LINE_SIZE
2247 };
2248 static struct intel_watermark_params i855_wm_info = {
2249 I855GM_FIFO_SIZE,
2250 I915_MAX_WM,
2251 1,
2252 2,
2253 I830_FIFO_LINE_SIZE
2254 };
2255 static struct intel_watermark_params i830_wm_info = {
2256 I830_FIFO_SIZE,
2257 I915_MAX_WM,
2258 1,
2259 2,
2260 I830_FIFO_LINE_SIZE
2261 };
2262
2263 /**
2264 * intel_calculate_wm - calculate watermark level
2265 * @clock_in_khz: pixel clock
2266 * @wm: chip FIFO params
2267 * @pixel_size: display pixel size
2268 * @latency_ns: memory latency for the platform
2269 *
2270 * Calculate the watermark level (the level at which the display plane will
2271 * start fetching from memory again). Each chip has a different display
2272 * FIFO size and allocation, so the caller needs to figure that out and pass
2273 * in the correct intel_watermark_params structure.
2274 *
2275 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2276 * on the pixel size. When it reaches the watermark level, it'll start
2277 * fetching FIFO line sized based chunks from memory until the FIFO fills
2278 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2279 * will occur, and a display engine hang could result.
2280 */
2281 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2282 struct intel_watermark_params *wm,
2283 int pixel_size,
2284 unsigned long latency_ns)
2285 {
2286 long entries_required, wm_size;
2287
2288 /*
2289 * Note: we need to make sure we don't overflow for various clock &
2290 * latency values.
2291 * clocks go from a few thousand to several hundred thousand.
2292 * latency is usually a few thousand
2293 */
2294 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2295 1000;
2296 entries_required /= wm->cacheline_size;
2297
2298 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2299
2300 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2301
2302 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2303
2304 /* Don't promote wm_size to unsigned... */
2305 if (wm_size > (long)wm->max_wm)
2306 wm_size = wm->max_wm;
2307 if (wm_size <= 0)
2308 wm_size = wm->default_wm;
2309 return wm_size;
2310 }
2311
2312 struct cxsr_latency {
2313 int is_desktop;
2314 unsigned long fsb_freq;
2315 unsigned long mem_freq;
2316 unsigned long display_sr;
2317 unsigned long display_hpll_disable;
2318 unsigned long cursor_sr;
2319 unsigned long cursor_hpll_disable;
2320 };
2321
2322 static struct cxsr_latency cxsr_latency_table[] = {
2323 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2324 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2325 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2326
2327 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2328 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2329 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2330
2331 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2332 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2333 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2334
2335 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2336 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2337 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2338
2339 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2340 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2341 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2342
2343 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2344 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2345 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2346 };
2347
2348 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2349 int mem)
2350 {
2351 int i;
2352 struct cxsr_latency *latency;
2353
2354 if (fsb == 0 || mem == 0)
2355 return NULL;
2356
2357 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2358 latency = &cxsr_latency_table[i];
2359 if (is_desktop == latency->is_desktop &&
2360 fsb == latency->fsb_freq && mem == latency->mem_freq)
2361 return latency;
2362 }
2363
2364 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2365
2366 return NULL;
2367 }
2368
2369 static void pineview_disable_cxsr(struct drm_device *dev)
2370 {
2371 struct drm_i915_private *dev_priv = dev->dev_private;
2372 u32 reg;
2373
2374 /* deactivate cxsr */
2375 reg = I915_READ(DSPFW3);
2376 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2377 I915_WRITE(DSPFW3, reg);
2378 DRM_INFO("Big FIFO is disabled\n");
2379 }
2380
2381 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2382 int pixel_size)
2383 {
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2385 u32 reg;
2386 unsigned long wm;
2387 struct cxsr_latency *latency;
2388
2389 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2390 dev_priv->mem_freq);
2391 if (!latency) {
2392 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2393 pineview_disable_cxsr(dev);
2394 return;
2395 }
2396
2397 /* Display SR */
2398 wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2399 latency->display_sr);
2400 reg = I915_READ(DSPFW1);
2401 reg &= 0x7fffff;
2402 reg |= wm << 23;
2403 I915_WRITE(DSPFW1, reg);
2404 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2405
2406 /* cursor SR */
2407 wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2408 latency->cursor_sr);
2409 reg = I915_READ(DSPFW3);
2410 reg &= ~(0x3f << 24);
2411 reg |= (wm & 0x3f) << 24;
2412 I915_WRITE(DSPFW3, reg);
2413
2414 /* Display HPLL off SR */
2415 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2416 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2417 reg = I915_READ(DSPFW3);
2418 reg &= 0xfffffe00;
2419 reg |= wm & 0x1ff;
2420 I915_WRITE(DSPFW3, reg);
2421
2422 /* cursor HPLL off SR */
2423 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2424 latency->cursor_hpll_disable);
2425 reg = I915_READ(DSPFW3);
2426 reg &= ~(0x3f << 16);
2427 reg |= (wm & 0x3f) << 16;
2428 I915_WRITE(DSPFW3, reg);
2429 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2430
2431 /* activate cxsr */
2432 reg = I915_READ(DSPFW3);
2433 reg |= PINEVIEW_SELF_REFRESH_EN;
2434 I915_WRITE(DSPFW3, reg);
2435
2436 DRM_INFO("Big FIFO is enabled\n");
2437
2438 return;
2439 }
2440
2441 /*
2442 * Latency for FIFO fetches is dependent on several factors:
2443 * - memory configuration (speed, channels)
2444 * - chipset
2445 * - current MCH state
2446 * It can be fairly high in some situations, so here we assume a fairly
2447 * pessimal value. It's a tradeoff between extra memory fetches (if we
2448 * set this value too high, the FIFO will fetch frequently to stay full)
2449 * and power consumption (set it too low to save power and we might see
2450 * FIFO underruns and display "flicker").
2451 *
2452 * A value of 5us seems to be a good balance; safe for very low end
2453 * platforms but not overly aggressive on lower latency configs.
2454 */
2455 static const int latency_ns = 5000;
2456
2457 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2458 {
2459 struct drm_i915_private *dev_priv = dev->dev_private;
2460 uint32_t dsparb = I915_READ(DSPARB);
2461 int size;
2462
2463 if (plane == 0)
2464 size = dsparb & 0x7f;
2465 else
2466 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2467 (dsparb & 0x7f);
2468
2469 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2470 plane ? "B" : "A", size);
2471
2472 return size;
2473 }
2474
2475 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2476 {
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 uint32_t dsparb = I915_READ(DSPARB);
2479 int size;
2480
2481 if (plane == 0)
2482 size = dsparb & 0x1ff;
2483 else
2484 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2485 (dsparb & 0x1ff);
2486 size >>= 1; /* Convert to cachelines */
2487
2488 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2489 plane ? "B" : "A", size);
2490
2491 return size;
2492 }
2493
2494 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2495 {
2496 struct drm_i915_private *dev_priv = dev->dev_private;
2497 uint32_t dsparb = I915_READ(DSPARB);
2498 int size;
2499
2500 size = dsparb & 0x7f;
2501 size >>= 2; /* Convert to cachelines */
2502
2503 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2504 plane ? "B" : "A",
2505 size);
2506
2507 return size;
2508 }
2509
2510 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2511 {
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 uint32_t dsparb = I915_READ(DSPARB);
2514 int size;
2515
2516 size = dsparb & 0x7f;
2517 size >>= 1; /* Convert to cachelines */
2518
2519 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2520 plane ? "B" : "A", size);
2521
2522 return size;
2523 }
2524
2525 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2526 int planeb_clock, int sr_hdisplay, int pixel_size)
2527 {
2528 struct drm_i915_private *dev_priv = dev->dev_private;
2529 int total_size, cacheline_size;
2530 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2531 struct intel_watermark_params planea_params, planeb_params;
2532 unsigned long line_time_us;
2533 int sr_clock, sr_entries = 0, entries_required;
2534
2535 /* Create copies of the base settings for each pipe */
2536 planea_params = planeb_params = g4x_wm_info;
2537
2538 /* Grab a couple of global values before we overwrite them */
2539 total_size = planea_params.fifo_size;
2540 cacheline_size = planea_params.cacheline_size;
2541
2542 /*
2543 * Note: we need to make sure we don't overflow for various clock &
2544 * latency values.
2545 * clocks go from a few thousand to several hundred thousand.
2546 * latency is usually a few thousand
2547 */
2548 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2549 1000;
2550 entries_required /= G4X_FIFO_LINE_SIZE;
2551 planea_wm = entries_required + planea_params.guard_size;
2552
2553 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2554 1000;
2555 entries_required /= G4X_FIFO_LINE_SIZE;
2556 planeb_wm = entries_required + planeb_params.guard_size;
2557
2558 cursora_wm = cursorb_wm = 16;
2559 cursor_sr = 32;
2560
2561 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2562
2563 /* Calc sr entries for one plane configs */
2564 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2565 /* self-refresh has much higher latency */
2566 static const int sr_latency_ns = 12000;
2567
2568 sr_clock = planea_clock ? planea_clock : planeb_clock;
2569 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2570
2571 /* Use ns/us then divide to preserve precision */
2572 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2573 pixel_size * sr_hdisplay) / 1000;
2574 sr_entries = roundup(sr_entries / cacheline_size, 1);
2575 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2576 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2577 }
2578
2579 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2580 planea_wm, planeb_wm, sr_entries);
2581
2582 planea_wm &= 0x3f;
2583 planeb_wm &= 0x3f;
2584
2585 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2586 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2587 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2588 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2589 (cursora_wm << DSPFW_CURSORA_SHIFT));
2590 /* HPLL off in SR has some issues on G4x... disable it */
2591 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2592 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2593 }
2594
2595 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2596 int planeb_clock, int sr_hdisplay, int pixel_size)
2597 {
2598 struct drm_i915_private *dev_priv = dev->dev_private;
2599 unsigned long line_time_us;
2600 int sr_clock, sr_entries, srwm = 1;
2601
2602 /* Calc sr entries for one plane configs */
2603 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2604 /* self-refresh has much higher latency */
2605 static const int sr_latency_ns = 12000;
2606
2607 sr_clock = planea_clock ? planea_clock : planeb_clock;
2608 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2609
2610 /* Use ns/us then divide to preserve precision */
2611 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2612 pixel_size * sr_hdisplay) / 1000;
2613 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2614 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2615 srwm = I945_FIFO_SIZE - sr_entries;
2616 if (srwm < 0)
2617 srwm = 1;
2618 srwm &= 0x3f;
2619 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2620 }
2621
2622 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2623 srwm);
2624
2625 /* 965 has limitations... */
2626 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2627 (8 << 0));
2628 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2629 }
2630
2631 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2632 int planeb_clock, int sr_hdisplay, int pixel_size)
2633 {
2634 struct drm_i915_private *dev_priv = dev->dev_private;
2635 uint32_t fwater_lo;
2636 uint32_t fwater_hi;
2637 int total_size, cacheline_size, cwm, srwm = 1;
2638 int planea_wm, planeb_wm;
2639 struct intel_watermark_params planea_params, planeb_params;
2640 unsigned long line_time_us;
2641 int sr_clock, sr_entries = 0;
2642
2643 /* Create copies of the base settings for each pipe */
2644 if (IS_I965GM(dev) || IS_I945GM(dev))
2645 planea_params = planeb_params = i945_wm_info;
2646 else if (IS_I9XX(dev))
2647 planea_params = planeb_params = i915_wm_info;
2648 else
2649 planea_params = planeb_params = i855_wm_info;
2650
2651 /* Grab a couple of global values before we overwrite them */
2652 total_size = planea_params.fifo_size;
2653 cacheline_size = planea_params.cacheline_size;
2654
2655 /* Update per-plane FIFO sizes */
2656 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2657 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2658
2659 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2660 pixel_size, latency_ns);
2661 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2662 pixel_size, latency_ns);
2663 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2664
2665 /*
2666 * Overlay gets an aggressive default since video jitter is bad.
2667 */
2668 cwm = 2;
2669
2670 /* Calc sr entries for one plane configs */
2671 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2672 (!planea_clock || !planeb_clock)) {
2673 /* self-refresh has much higher latency */
2674 static const int sr_latency_ns = 6000;
2675
2676 sr_clock = planea_clock ? planea_clock : planeb_clock;
2677 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2678
2679 /* Use ns/us then divide to preserve precision */
2680 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2681 pixel_size * sr_hdisplay) / 1000;
2682 sr_entries = roundup(sr_entries / cacheline_size, 1);
2683 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2684 srwm = total_size - sr_entries;
2685 if (srwm < 0)
2686 srwm = 1;
2687 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2688 }
2689
2690 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2691 planea_wm, planeb_wm, cwm, srwm);
2692
2693 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2694 fwater_hi = (cwm & 0x1f);
2695
2696 /* Set request length to 8 cachelines per fetch */
2697 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2698 fwater_hi = fwater_hi | (1 << 8);
2699
2700 I915_WRITE(FW_BLC, fwater_lo);
2701 I915_WRITE(FW_BLC2, fwater_hi);
2702 }
2703
2704 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2705 int unused2, int pixel_size)
2706 {
2707 struct drm_i915_private *dev_priv = dev->dev_private;
2708 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2709 int planea_wm;
2710
2711 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2712
2713 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2714 pixel_size, latency_ns);
2715 fwater_lo |= (3<<8) | planea_wm;
2716
2717 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2718
2719 I915_WRITE(FW_BLC, fwater_lo);
2720 }
2721
2722 /**
2723 * intel_update_watermarks - update FIFO watermark values based on current modes
2724 *
2725 * Calculate watermark values for the various WM regs based on current mode
2726 * and plane configuration.
2727 *
2728 * There are several cases to deal with here:
2729 * - normal (i.e. non-self-refresh)
2730 * - self-refresh (SR) mode
2731 * - lines are large relative to FIFO size (buffer can hold up to 2)
2732 * - lines are small relative to FIFO size (buffer can hold more than 2
2733 * lines), so need to account for TLB latency
2734 *
2735 * The normal calculation is:
2736 * watermark = dotclock * bytes per pixel * latency
2737 * where latency is platform & configuration dependent (we assume pessimal
2738 * values here).
2739 *
2740 * The SR calculation is:
2741 * watermark = (trunc(latency/line time)+1) * surface width *
2742 * bytes per pixel
2743 * where
2744 * line time = htotal / dotclock
2745 * and latency is assumed to be high, as above.
2746 *
2747 * The final value programmed to the register should always be rounded up,
2748 * and include an extra 2 entries to account for clock crossings.
2749 *
2750 * We don't use the sprite, so we can ignore that. And on Crestline we have
2751 * to set the non-SR watermarks to 8.
2752 */
2753 static void intel_update_watermarks(struct drm_device *dev)
2754 {
2755 struct drm_i915_private *dev_priv = dev->dev_private;
2756 struct drm_crtc *crtc;
2757 struct intel_crtc *intel_crtc;
2758 int sr_hdisplay = 0;
2759 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2760 int enabled = 0, pixel_size = 0;
2761
2762 if (!dev_priv->display.update_wm)
2763 return;
2764
2765 /* Get the clock config from both planes */
2766 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2767 intel_crtc = to_intel_crtc(crtc);
2768 if (crtc->enabled) {
2769 enabled++;
2770 if (intel_crtc->plane == 0) {
2771 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2772 intel_crtc->pipe, crtc->mode.clock);
2773 planea_clock = crtc->mode.clock;
2774 } else {
2775 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2776 intel_crtc->pipe, crtc->mode.clock);
2777 planeb_clock = crtc->mode.clock;
2778 }
2779 sr_hdisplay = crtc->mode.hdisplay;
2780 sr_clock = crtc->mode.clock;
2781 if (crtc->fb)
2782 pixel_size = crtc->fb->bits_per_pixel / 8;
2783 else
2784 pixel_size = 4; /* by default */
2785 }
2786 }
2787
2788 if (enabled <= 0)
2789 return;
2790
2791 /* Single plane configs can enable self refresh */
2792 if (enabled == 1 && IS_PINEVIEW(dev))
2793 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2794 else if (IS_PINEVIEW(dev))
2795 pineview_disable_cxsr(dev);
2796
2797 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2798 sr_hdisplay, pixel_size);
2799 }
2800
2801 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2802 struct drm_display_mode *mode,
2803 struct drm_display_mode *adjusted_mode,
2804 int x, int y,
2805 struct drm_framebuffer *old_fb)
2806 {
2807 struct drm_device *dev = crtc->dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2810 int pipe = intel_crtc->pipe;
2811 int plane = intel_crtc->plane;
2812 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2813 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2814 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2815 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2816 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2817 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2818 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2819 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2820 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2821 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2822 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2823 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2824 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2825 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2826 int refclk, num_outputs = 0;
2827 intel_clock_t clock, reduced_clock;
2828 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2829 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2830 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2831 bool is_edp = false;
2832 struct drm_mode_config *mode_config = &dev->mode_config;
2833 struct drm_connector *connector;
2834 const intel_limit_t *limit;
2835 int ret;
2836 struct fdi_m_n m_n = {0};
2837 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2838 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2839 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2840 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2841 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2842 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2843 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2844 int lvds_reg = LVDS;
2845 u32 temp;
2846 int sdvo_pixel_multiply;
2847 int target_clock;
2848
2849 drm_vblank_pre_modeset(dev, pipe);
2850
2851 list_for_each_entry(connector, &mode_config->connector_list, head) {
2852 struct intel_output *intel_output = to_intel_output(connector);
2853
2854 if (!connector->encoder || connector->encoder->crtc != crtc)
2855 continue;
2856
2857 switch (intel_output->type) {
2858 case INTEL_OUTPUT_LVDS:
2859 is_lvds = true;
2860 break;
2861 case INTEL_OUTPUT_SDVO:
2862 case INTEL_OUTPUT_HDMI:
2863 is_sdvo = true;
2864 if (intel_output->needs_tv_clock)
2865 is_tv = true;
2866 break;
2867 case INTEL_OUTPUT_DVO:
2868 is_dvo = true;
2869 break;
2870 case INTEL_OUTPUT_TVOUT:
2871 is_tv = true;
2872 break;
2873 case INTEL_OUTPUT_ANALOG:
2874 is_crt = true;
2875 break;
2876 case INTEL_OUTPUT_DISPLAYPORT:
2877 is_dp = true;
2878 break;
2879 case INTEL_OUTPUT_EDP:
2880 is_edp = true;
2881 break;
2882 }
2883
2884 num_outputs++;
2885 }
2886
2887 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2888 refclk = dev_priv->lvds_ssc_freq * 1000;
2889 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2890 refclk / 1000);
2891 } else if (IS_I9XX(dev)) {
2892 refclk = 96000;
2893 if (IS_IRONLAKE(dev))
2894 refclk = 120000; /* 120Mhz refclk */
2895 } else {
2896 refclk = 48000;
2897 }
2898
2899
2900 /*
2901 * Returns a set of divisors for the desired target clock with the given
2902 * refclk, or FALSE. The returned values represent the clock equation:
2903 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2904 */
2905 limit = intel_limit(crtc);
2906 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2907 if (!ok) {
2908 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2909 drm_vblank_post_modeset(dev, pipe);
2910 return -EINVAL;
2911 }
2912
2913 if (is_lvds && limit->find_reduced_pll &&
2914 dev_priv->lvds_downclock_avail) {
2915 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2916 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2917 dev_priv->lvds_downclock,
2918 refclk,
2919 &reduced_clock);
2920 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2921 /*
2922 * If the different P is found, it means that we can't
2923 * switch the display clock by using the FP0/FP1.
2924 * In such case we will disable the LVDS downclock
2925 * feature.
2926 */
2927 DRM_DEBUG_KMS("Different P is found for "
2928 "LVDS clock/downclock\n");
2929 has_reduced_clock = 0;
2930 }
2931 }
2932 /* SDVO TV has fixed PLL values depend on its clock range,
2933 this mirrors vbios setting. */
2934 if (is_sdvo && is_tv) {
2935 if (adjusted_mode->clock >= 100000
2936 && adjusted_mode->clock < 140500) {
2937 clock.p1 = 2;
2938 clock.p2 = 10;
2939 clock.n = 3;
2940 clock.m1 = 16;
2941 clock.m2 = 8;
2942 } else if (adjusted_mode->clock >= 140500
2943 && adjusted_mode->clock <= 200000) {
2944 clock.p1 = 1;
2945 clock.p2 = 10;
2946 clock.n = 6;
2947 clock.m1 = 12;
2948 clock.m2 = 8;
2949 }
2950 }
2951
2952 /* FDI link */
2953 if (IS_IRONLAKE(dev)) {
2954 int lane, link_bw, bpp;
2955 /* eDP doesn't require FDI link, so just set DP M/N
2956 according to current link config */
2957 if (is_edp) {
2958 struct drm_connector *edp;
2959 target_clock = mode->clock;
2960 edp = intel_pipe_get_output(crtc);
2961 intel_edp_link_config(to_intel_output(edp),
2962 &lane, &link_bw);
2963 } else {
2964 /* DP over FDI requires target mode clock
2965 instead of link clock */
2966 if (is_dp)
2967 target_clock = mode->clock;
2968 else
2969 target_clock = adjusted_mode->clock;
2970 lane = 4;
2971 link_bw = 270000;
2972 }
2973
2974 /* determine panel color depth */
2975 temp = I915_READ(pipeconf_reg);
2976 temp &= ~PIPE_BPC_MASK;
2977 if (is_lvds) {
2978 int lvds_reg = I915_READ(PCH_LVDS);
2979 /* the BPC will be 6 if it is 18-bit LVDS panel */
2980 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
2981 temp |= PIPE_8BPC;
2982 else
2983 temp |= PIPE_6BPC;
2984 } else
2985 temp |= PIPE_8BPC;
2986 I915_WRITE(pipeconf_reg, temp);
2987 I915_READ(pipeconf_reg);
2988
2989 switch (temp & PIPE_BPC_MASK) {
2990 case PIPE_8BPC:
2991 bpp = 24;
2992 break;
2993 case PIPE_10BPC:
2994 bpp = 30;
2995 break;
2996 case PIPE_6BPC:
2997 bpp = 18;
2998 break;
2999 case PIPE_12BPC:
3000 bpp = 36;
3001 break;
3002 default:
3003 DRM_ERROR("unknown pipe bpc value\n");
3004 bpp = 24;
3005 }
3006
3007 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3008 }
3009
3010 /* Ironlake: try to setup display ref clock before DPLL
3011 * enabling. This is only under driver's control after
3012 * PCH B stepping, previous chipset stepping should be
3013 * ignoring this setting.
3014 */
3015 if (IS_IRONLAKE(dev)) {
3016 temp = I915_READ(PCH_DREF_CONTROL);
3017 /* Always enable nonspread source */
3018 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3019 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3020 I915_WRITE(PCH_DREF_CONTROL, temp);
3021 POSTING_READ(PCH_DREF_CONTROL);
3022
3023 temp &= ~DREF_SSC_SOURCE_MASK;
3024 temp |= DREF_SSC_SOURCE_ENABLE;
3025 I915_WRITE(PCH_DREF_CONTROL, temp);
3026 POSTING_READ(PCH_DREF_CONTROL);
3027
3028 udelay(200);
3029
3030 if (is_edp) {
3031 if (dev_priv->lvds_use_ssc) {
3032 temp |= DREF_SSC1_ENABLE;
3033 I915_WRITE(PCH_DREF_CONTROL, temp);
3034 POSTING_READ(PCH_DREF_CONTROL);
3035
3036 udelay(200);
3037
3038 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3039 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3040 I915_WRITE(PCH_DREF_CONTROL, temp);
3041 POSTING_READ(PCH_DREF_CONTROL);
3042 } else {
3043 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3044 I915_WRITE(PCH_DREF_CONTROL, temp);
3045 POSTING_READ(PCH_DREF_CONTROL);
3046 }
3047 }
3048 }
3049
3050 if (IS_PINEVIEW(dev)) {
3051 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3052 if (has_reduced_clock)
3053 fp2 = (1 << reduced_clock.n) << 16 |
3054 reduced_clock.m1 << 8 | reduced_clock.m2;
3055 } else {
3056 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3057 if (has_reduced_clock)
3058 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3059 reduced_clock.m2;
3060 }
3061
3062 if (!IS_IRONLAKE(dev))
3063 dpll = DPLL_VGA_MODE_DIS;
3064
3065 if (IS_I9XX(dev)) {
3066 if (is_lvds)
3067 dpll |= DPLLB_MODE_LVDS;
3068 else
3069 dpll |= DPLLB_MODE_DAC_SERIAL;
3070 if (is_sdvo) {
3071 dpll |= DPLL_DVO_HIGH_SPEED;
3072 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3073 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3074 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3075 else if (IS_IRONLAKE(dev))
3076 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3077 }
3078 if (is_dp)
3079 dpll |= DPLL_DVO_HIGH_SPEED;
3080
3081 /* compute bitmask from p1 value */
3082 if (IS_PINEVIEW(dev))
3083 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3084 else {
3085 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3086 /* also FPA1 */
3087 if (IS_IRONLAKE(dev))
3088 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3089 if (IS_G4X(dev) && has_reduced_clock)
3090 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3091 }
3092 switch (clock.p2) {
3093 case 5:
3094 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3095 break;
3096 case 7:
3097 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3098 break;
3099 case 10:
3100 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3101 break;
3102 case 14:
3103 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3104 break;
3105 }
3106 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
3107 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3108 } else {
3109 if (is_lvds) {
3110 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3111 } else {
3112 if (clock.p1 == 2)
3113 dpll |= PLL_P1_DIVIDE_BY_TWO;
3114 else
3115 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3116 if (clock.p2 == 4)
3117 dpll |= PLL_P2_DIVIDE_BY_4;
3118 }
3119 }
3120
3121 if (is_sdvo && is_tv)
3122 dpll |= PLL_REF_INPUT_TVCLKINBC;
3123 else if (is_tv)
3124 /* XXX: just matching BIOS for now */
3125 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3126 dpll |= 3;
3127 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3128 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3129 else
3130 dpll |= PLL_REF_INPUT_DREFCLK;
3131
3132 /* setup pipeconf */
3133 pipeconf = I915_READ(pipeconf_reg);
3134
3135 /* Set up the display plane register */
3136 dspcntr = DISPPLANE_GAMMA_ENABLE;
3137
3138 /* Ironlake's plane is forced to pipe, bit 24 is to
3139 enable color space conversion */
3140 if (!IS_IRONLAKE(dev)) {
3141 if (pipe == 0)
3142 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3143 else
3144 dspcntr |= DISPPLANE_SEL_PIPE_B;
3145 }
3146
3147 if (pipe == 0 && !IS_I965G(dev)) {
3148 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3149 * core speed.
3150 *
3151 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3152 * pipe == 0 check?
3153 */
3154 if (mode->clock >
3155 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3156 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3157 else
3158 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3159 }
3160
3161 dspcntr |= DISPLAY_PLANE_ENABLE;
3162 pipeconf |= PIPEACONF_ENABLE;
3163 dpll |= DPLL_VCO_ENABLE;
3164
3165
3166 /* Disable the panel fitter if it was on our pipe */
3167 if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
3168 I915_WRITE(PFIT_CONTROL, 0);
3169
3170 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3171 drm_mode_debug_printmodeline(mode);
3172
3173 /* assign to Ironlake registers */
3174 if (IS_IRONLAKE(dev)) {
3175 fp_reg = pch_fp_reg;
3176 dpll_reg = pch_dpll_reg;
3177 }
3178
3179 if (is_edp) {
3180 ironlake_disable_pll_edp(crtc);
3181 } else if ((dpll & DPLL_VCO_ENABLE)) {
3182 I915_WRITE(fp_reg, fp);
3183 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3184 I915_READ(dpll_reg);
3185 udelay(150);
3186 }
3187
3188 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3189 * This is an exception to the general rule that mode_set doesn't turn
3190 * things on.
3191 */
3192 if (is_lvds) {
3193 u32 lvds;
3194
3195 if (IS_IRONLAKE(dev))
3196 lvds_reg = PCH_LVDS;
3197
3198 lvds = I915_READ(lvds_reg);
3199 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3200 /* set the corresponsding LVDS_BORDER bit */
3201 lvds |= dev_priv->lvds_border_bits;
3202 /* Set the B0-B3 data pairs corresponding to whether we're going to
3203 * set the DPLLs for dual-channel mode or not.
3204 */
3205 if (clock.p2 == 7)
3206 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3207 else
3208 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3209
3210 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3211 * appropriately here, but we need to look more thoroughly into how
3212 * panels behave in the two modes.
3213 */
3214 /* set the dithering flag */
3215 if (IS_I965G(dev)) {
3216 if (dev_priv->lvds_dither) {
3217 if (IS_IRONLAKE(dev))
3218 pipeconf |= PIPE_ENABLE_DITHER;
3219 else
3220 lvds |= LVDS_ENABLE_DITHER;
3221 } else {
3222 if (IS_IRONLAKE(dev))
3223 pipeconf &= ~PIPE_ENABLE_DITHER;
3224 else
3225 lvds &= ~LVDS_ENABLE_DITHER;
3226 }
3227 }
3228 I915_WRITE(lvds_reg, lvds);
3229 I915_READ(lvds_reg);
3230 }
3231 if (is_dp)
3232 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3233
3234 if (!is_edp) {
3235 I915_WRITE(fp_reg, fp);
3236 I915_WRITE(dpll_reg, dpll);
3237 I915_READ(dpll_reg);
3238 /* Wait for the clocks to stabilize. */
3239 udelay(150);
3240
3241 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
3242 if (is_sdvo) {
3243 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3244 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3245 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3246 } else
3247 I915_WRITE(dpll_md_reg, 0);
3248 } else {
3249 /* write it again -- the BIOS does, after all */
3250 I915_WRITE(dpll_reg, dpll);
3251 }
3252 I915_READ(dpll_reg);
3253 /* Wait for the clocks to stabilize. */
3254 udelay(150);
3255 }
3256
3257 if (is_lvds && has_reduced_clock && i915_powersave) {
3258 I915_WRITE(fp_reg + 4, fp2);
3259 intel_crtc->lowfreq_avail = true;
3260 if (HAS_PIPE_CXSR(dev)) {
3261 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3262 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3263 }
3264 } else {
3265 I915_WRITE(fp_reg + 4, fp);
3266 intel_crtc->lowfreq_avail = false;
3267 if (HAS_PIPE_CXSR(dev)) {
3268 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3269 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3270 }
3271 }
3272
3273 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3274 ((adjusted_mode->crtc_htotal - 1) << 16));
3275 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3276 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3277 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3278 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3279 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3280 ((adjusted_mode->crtc_vtotal - 1) << 16));
3281 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3282 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3283 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3284 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3285 /* pipesrc and dspsize control the size that is scaled from, which should
3286 * always be the user's requested size.
3287 */
3288 if (!IS_IRONLAKE(dev)) {
3289 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3290 (mode->hdisplay - 1));
3291 I915_WRITE(dsppos_reg, 0);
3292 }
3293 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3294
3295 if (IS_IRONLAKE(dev)) {
3296 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3297 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3298 I915_WRITE(link_m1_reg, m_n.link_m);
3299 I915_WRITE(link_n1_reg, m_n.link_n);
3300
3301 if (is_edp) {
3302 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3303 } else {
3304 /* enable FDI RX PLL too */
3305 temp = I915_READ(fdi_rx_reg);
3306 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3307 udelay(200);
3308 }
3309 }
3310
3311 I915_WRITE(pipeconf_reg, pipeconf);
3312 I915_READ(pipeconf_reg);
3313
3314 intel_wait_for_vblank(dev);
3315
3316 if (IS_IRONLAKE(dev)) {
3317 /* enable address swizzle for tiling buffer */
3318 temp = I915_READ(DISP_ARB_CTL);
3319 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3320 }
3321
3322 I915_WRITE(dspcntr_reg, dspcntr);
3323
3324 /* Flush the plane changes */
3325 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3326
3327 if ((IS_I965G(dev) || plane == 0))
3328 intel_update_fbc(crtc, &crtc->mode);
3329
3330 intel_update_watermarks(dev);
3331
3332 drm_vblank_post_modeset(dev, pipe);
3333
3334 return ret;
3335 }
3336
3337 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3338 void intel_crtc_load_lut(struct drm_crtc *crtc)
3339 {
3340 struct drm_device *dev = crtc->dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3343 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3344 int i;
3345
3346 /* The clocks have to be on to load the palette. */
3347 if (!crtc->enabled)
3348 return;
3349
3350 /* use legacy palette for Ironlake */
3351 if (IS_IRONLAKE(dev))
3352 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3353 LGC_PALETTE_B;
3354
3355 for (i = 0; i < 256; i++) {
3356 I915_WRITE(palreg + 4 * i,
3357 (intel_crtc->lut_r[i] << 16) |
3358 (intel_crtc->lut_g[i] << 8) |
3359 intel_crtc->lut_b[i]);
3360 }
3361 }
3362
3363 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3364 struct drm_file *file_priv,
3365 uint32_t handle,
3366 uint32_t width, uint32_t height)
3367 {
3368 struct drm_device *dev = crtc->dev;
3369 struct drm_i915_private *dev_priv = dev->dev_private;
3370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3371 struct drm_gem_object *bo;
3372 struct drm_i915_gem_object *obj_priv;
3373 int pipe = intel_crtc->pipe;
3374 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3375 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3376 uint32_t temp = I915_READ(control);
3377 size_t addr;
3378 int ret;
3379
3380 DRM_DEBUG_KMS("\n");
3381
3382 /* if we want to turn off the cursor ignore width and height */
3383 if (!handle) {
3384 DRM_DEBUG_KMS("cursor off\n");
3385 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3386 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3387 temp |= CURSOR_MODE_DISABLE;
3388 } else {
3389 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3390 }
3391 addr = 0;
3392 bo = NULL;
3393 mutex_lock(&dev->struct_mutex);
3394 goto finish;
3395 }
3396
3397 /* Currently we only support 64x64 cursors */
3398 if (width != 64 || height != 64) {
3399 DRM_ERROR("we currently only support 64x64 cursors\n");
3400 return -EINVAL;
3401 }
3402
3403 bo = drm_gem_object_lookup(dev, file_priv, handle);
3404 if (!bo)
3405 return -ENOENT;
3406
3407 obj_priv = bo->driver_private;
3408
3409 if (bo->size < width * height * 4) {
3410 DRM_ERROR("buffer is to small\n");
3411 ret = -ENOMEM;
3412 goto fail;
3413 }
3414
3415 /* we only need to pin inside GTT if cursor is non-phy */
3416 mutex_lock(&dev->struct_mutex);
3417 if (!dev_priv->info->cursor_needs_physical) {
3418 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3419 if (ret) {
3420 DRM_ERROR("failed to pin cursor bo\n");
3421 goto fail_locked;
3422 }
3423 addr = obj_priv->gtt_offset;
3424 } else {
3425 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3426 if (ret) {
3427 DRM_ERROR("failed to attach phys object\n");
3428 goto fail_locked;
3429 }
3430 addr = obj_priv->phys_obj->handle->busaddr;
3431 }
3432
3433 if (!IS_I9XX(dev))
3434 I915_WRITE(CURSIZE, (height << 12) | width);
3435
3436 /* Hooray for CUR*CNTR differences */
3437 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3438 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3439 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3440 temp |= (pipe << 28); /* Connect to correct pipe */
3441 } else {
3442 temp &= ~(CURSOR_FORMAT_MASK);
3443 temp |= CURSOR_ENABLE;
3444 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3445 }
3446
3447 finish:
3448 I915_WRITE(control, temp);
3449 I915_WRITE(base, addr);
3450
3451 if (intel_crtc->cursor_bo) {
3452 if (dev_priv->info->cursor_needs_physical) {
3453 if (intel_crtc->cursor_bo != bo)
3454 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3455 } else
3456 i915_gem_object_unpin(intel_crtc->cursor_bo);
3457 drm_gem_object_unreference(intel_crtc->cursor_bo);
3458 }
3459
3460 mutex_unlock(&dev->struct_mutex);
3461
3462 intel_crtc->cursor_addr = addr;
3463 intel_crtc->cursor_bo = bo;
3464
3465 return 0;
3466 fail:
3467 mutex_lock(&dev->struct_mutex);
3468 fail_locked:
3469 drm_gem_object_unreference(bo);
3470 mutex_unlock(&dev->struct_mutex);
3471 return ret;
3472 }
3473
3474 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3475 {
3476 struct drm_device *dev = crtc->dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479 struct intel_framebuffer *intel_fb;
3480 int pipe = intel_crtc->pipe;
3481 uint32_t temp = 0;
3482 uint32_t adder;
3483
3484 if (crtc->fb) {
3485 intel_fb = to_intel_framebuffer(crtc->fb);
3486 intel_mark_busy(dev, intel_fb->obj);
3487 }
3488
3489 if (x < 0) {
3490 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3491 x = -x;
3492 }
3493 if (y < 0) {
3494 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3495 y = -y;
3496 }
3497
3498 temp |= x << CURSOR_X_SHIFT;
3499 temp |= y << CURSOR_Y_SHIFT;
3500
3501 adder = intel_crtc->cursor_addr;
3502 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3503 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3504
3505 return 0;
3506 }
3507
3508 /** Sets the color ramps on behalf of RandR */
3509 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3510 u16 blue, int regno)
3511 {
3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513
3514 intel_crtc->lut_r[regno] = red >> 8;
3515 intel_crtc->lut_g[regno] = green >> 8;
3516 intel_crtc->lut_b[regno] = blue >> 8;
3517 }
3518
3519 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3520 u16 *blue, int regno)
3521 {
3522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3523
3524 *red = intel_crtc->lut_r[regno] << 8;
3525 *green = intel_crtc->lut_g[regno] << 8;
3526 *blue = intel_crtc->lut_b[regno] << 8;
3527 }
3528
3529 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3530 u16 *blue, uint32_t size)
3531 {
3532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3533 int i;
3534
3535 if (size != 256)
3536 return;
3537
3538 for (i = 0; i < 256; i++) {
3539 intel_crtc->lut_r[i] = red[i] >> 8;
3540 intel_crtc->lut_g[i] = green[i] >> 8;
3541 intel_crtc->lut_b[i] = blue[i] >> 8;
3542 }
3543
3544 intel_crtc_load_lut(crtc);
3545 }
3546
3547 /**
3548 * Get a pipe with a simple mode set on it for doing load-based monitor
3549 * detection.
3550 *
3551 * It will be up to the load-detect code to adjust the pipe as appropriate for
3552 * its requirements. The pipe will be connected to no other outputs.
3553 *
3554 * Currently this code will only succeed if there is a pipe with no outputs
3555 * configured for it. In the future, it could choose to temporarily disable
3556 * some outputs to free up a pipe for its use.
3557 *
3558 * \return crtc, or NULL if no pipes are available.
3559 */
3560
3561 /* VESA 640x480x72Hz mode to set on the pipe */
3562 static struct drm_display_mode load_detect_mode = {
3563 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3564 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3565 };
3566
3567 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3568 struct drm_display_mode *mode,
3569 int *dpms_mode)
3570 {
3571 struct intel_crtc *intel_crtc;
3572 struct drm_crtc *possible_crtc;
3573 struct drm_crtc *supported_crtc =NULL;
3574 struct drm_encoder *encoder = &intel_output->enc;
3575 struct drm_crtc *crtc = NULL;
3576 struct drm_device *dev = encoder->dev;
3577 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3578 struct drm_crtc_helper_funcs *crtc_funcs;
3579 int i = -1;
3580
3581 /*
3582 * Algorithm gets a little messy:
3583 * - if the connector already has an assigned crtc, use it (but make
3584 * sure it's on first)
3585 * - try to find the first unused crtc that can drive this connector,
3586 * and use that if we find one
3587 * - if there are no unused crtcs available, try to use the first
3588 * one we found that supports the connector
3589 */
3590
3591 /* See if we already have a CRTC for this connector */
3592 if (encoder->crtc) {
3593 crtc = encoder->crtc;
3594 /* Make sure the crtc and connector are running */
3595 intel_crtc = to_intel_crtc(crtc);
3596 *dpms_mode = intel_crtc->dpms_mode;
3597 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3598 crtc_funcs = crtc->helper_private;
3599 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3600 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3601 }
3602 return crtc;
3603 }
3604
3605 /* Find an unused one (if possible) */
3606 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3607 i++;
3608 if (!(encoder->possible_crtcs & (1 << i)))
3609 continue;
3610 if (!possible_crtc->enabled) {
3611 crtc = possible_crtc;
3612 break;
3613 }
3614 if (!supported_crtc)
3615 supported_crtc = possible_crtc;
3616 }
3617
3618 /*
3619 * If we didn't find an unused CRTC, don't use any.
3620 */
3621 if (!crtc) {
3622 return NULL;
3623 }
3624
3625 encoder->crtc = crtc;
3626 intel_output->base.encoder = encoder;
3627 intel_output->load_detect_temp = true;
3628
3629 intel_crtc = to_intel_crtc(crtc);
3630 *dpms_mode = intel_crtc->dpms_mode;
3631
3632 if (!crtc->enabled) {
3633 if (!mode)
3634 mode = &load_detect_mode;
3635 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3636 } else {
3637 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3638 crtc_funcs = crtc->helper_private;
3639 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3640 }
3641
3642 /* Add this connector to the crtc */
3643 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3644 encoder_funcs->commit(encoder);
3645 }
3646 /* let the connector get through one full cycle before testing */
3647 intel_wait_for_vblank(dev);
3648
3649 return crtc;
3650 }
3651
3652 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3653 {
3654 struct drm_encoder *encoder = &intel_output->enc;
3655 struct drm_device *dev = encoder->dev;
3656 struct drm_crtc *crtc = encoder->crtc;
3657 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3658 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3659
3660 if (intel_output->load_detect_temp) {
3661 encoder->crtc = NULL;
3662 intel_output->base.encoder = NULL;
3663 intel_output->load_detect_temp = false;
3664 crtc->enabled = drm_helper_crtc_in_use(crtc);
3665 drm_helper_disable_unused_functions(dev);
3666 }
3667
3668 /* Switch crtc and output back off if necessary */
3669 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3670 if (encoder->crtc == crtc)
3671 encoder_funcs->dpms(encoder, dpms_mode);
3672 crtc_funcs->dpms(crtc, dpms_mode);
3673 }
3674 }
3675
3676 /* Returns the clock of the currently programmed mode of the given pipe. */
3677 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3678 {
3679 struct drm_i915_private *dev_priv = dev->dev_private;
3680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3681 int pipe = intel_crtc->pipe;
3682 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3683 u32 fp;
3684 intel_clock_t clock;
3685
3686 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3687 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3688 else
3689 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3690
3691 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3692 if (IS_PINEVIEW(dev)) {
3693 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3694 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3695 } else {
3696 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3697 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3698 }
3699
3700 if (IS_I9XX(dev)) {
3701 if (IS_PINEVIEW(dev))
3702 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3703 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3704 else
3705 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3706 DPLL_FPA01_P1_POST_DIV_SHIFT);
3707
3708 switch (dpll & DPLL_MODE_MASK) {
3709 case DPLLB_MODE_DAC_SERIAL:
3710 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3711 5 : 10;
3712 break;
3713 case DPLLB_MODE_LVDS:
3714 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3715 7 : 14;
3716 break;
3717 default:
3718 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3719 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3720 return 0;
3721 }
3722
3723 /* XXX: Handle the 100Mhz refclk */
3724 intel_clock(dev, 96000, &clock);
3725 } else {
3726 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3727
3728 if (is_lvds) {
3729 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3730 DPLL_FPA01_P1_POST_DIV_SHIFT);
3731 clock.p2 = 14;
3732
3733 if ((dpll & PLL_REF_INPUT_MASK) ==
3734 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3735 /* XXX: might not be 66MHz */
3736 intel_clock(dev, 66000, &clock);
3737 } else
3738 intel_clock(dev, 48000, &clock);
3739 } else {
3740 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3741 clock.p1 = 2;
3742 else {
3743 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3744 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3745 }
3746 if (dpll & PLL_P2_DIVIDE_BY_4)
3747 clock.p2 = 4;
3748 else
3749 clock.p2 = 2;
3750
3751 intel_clock(dev, 48000, &clock);
3752 }
3753 }
3754
3755 /* XXX: It would be nice to validate the clocks, but we can't reuse
3756 * i830PllIsValid() because it relies on the xf86_config connector
3757 * configuration being accurate, which it isn't necessarily.
3758 */
3759
3760 return clock.dot;
3761 }
3762
3763 /** Returns the currently programmed mode of the given pipe. */
3764 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3765 struct drm_crtc *crtc)
3766 {
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3769 int pipe = intel_crtc->pipe;
3770 struct drm_display_mode *mode;
3771 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3772 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3773 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3774 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3775
3776 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3777 if (!mode)
3778 return NULL;
3779
3780 mode->clock = intel_crtc_clock_get(dev, crtc);
3781 mode->hdisplay = (htot & 0xffff) + 1;
3782 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3783 mode->hsync_start = (hsync & 0xffff) + 1;
3784 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3785 mode->vdisplay = (vtot & 0xffff) + 1;
3786 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3787 mode->vsync_start = (vsync & 0xffff) + 1;
3788 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3789
3790 drm_mode_set_name(mode);
3791 drm_mode_set_crtcinfo(mode, 0);
3792
3793 return mode;
3794 }
3795
3796 #define GPU_IDLE_TIMEOUT 500 /* ms */
3797
3798 /* When this timer fires, we've been idle for awhile */
3799 static void intel_gpu_idle_timer(unsigned long arg)
3800 {
3801 struct drm_device *dev = (struct drm_device *)arg;
3802 drm_i915_private_t *dev_priv = dev->dev_private;
3803
3804 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3805
3806 dev_priv->busy = false;
3807
3808 queue_work(dev_priv->wq, &dev_priv->idle_work);
3809 }
3810
3811 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3812
3813 static void intel_crtc_idle_timer(unsigned long arg)
3814 {
3815 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3816 struct drm_crtc *crtc = &intel_crtc->base;
3817 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3818
3819 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3820
3821 intel_crtc->busy = false;
3822
3823 queue_work(dev_priv->wq, &dev_priv->idle_work);
3824 }
3825
3826 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3827 {
3828 struct drm_device *dev = crtc->dev;
3829 drm_i915_private_t *dev_priv = dev->dev_private;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 int pipe = intel_crtc->pipe;
3832 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3833 int dpll = I915_READ(dpll_reg);
3834
3835 if (IS_IRONLAKE(dev))
3836 return;
3837
3838 if (!dev_priv->lvds_downclock_avail)
3839 return;
3840
3841 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3842 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3843
3844 /* Unlock panel regs */
3845 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3846
3847 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3848 I915_WRITE(dpll_reg, dpll);
3849 dpll = I915_READ(dpll_reg);
3850 intel_wait_for_vblank(dev);
3851 dpll = I915_READ(dpll_reg);
3852 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3853 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3854
3855 /* ...and lock them again */
3856 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3857 }
3858
3859 /* Schedule downclock */
3860 if (schedule)
3861 mod_timer(&intel_crtc->idle_timer, jiffies +
3862 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3863 }
3864
3865 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3866 {
3867 struct drm_device *dev = crtc->dev;
3868 drm_i915_private_t *dev_priv = dev->dev_private;
3869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3870 int pipe = intel_crtc->pipe;
3871 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3872 int dpll = I915_READ(dpll_reg);
3873
3874 if (IS_IRONLAKE(dev))
3875 return;
3876
3877 if (!dev_priv->lvds_downclock_avail)
3878 return;
3879
3880 /*
3881 * Since this is called by a timer, we should never get here in
3882 * the manual case.
3883 */
3884 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3885 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3886
3887 /* Unlock panel regs */
3888 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3889
3890 dpll |= DISPLAY_RATE_SELECT_FPA1;
3891 I915_WRITE(dpll_reg, dpll);
3892 dpll = I915_READ(dpll_reg);
3893 intel_wait_for_vblank(dev);
3894 dpll = I915_READ(dpll_reg);
3895 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3896 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3897
3898 /* ...and lock them again */
3899 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3900 }
3901
3902 }
3903
3904 /**
3905 * intel_idle_update - adjust clocks for idleness
3906 * @work: work struct
3907 *
3908 * Either the GPU or display (or both) went idle. Check the busy status
3909 * here and adjust the CRTC and GPU clocks as necessary.
3910 */
3911 static void intel_idle_update(struct work_struct *work)
3912 {
3913 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3914 idle_work);
3915 struct drm_device *dev = dev_priv->dev;
3916 struct drm_crtc *crtc;
3917 struct intel_crtc *intel_crtc;
3918
3919 if (!i915_powersave)
3920 return;
3921
3922 mutex_lock(&dev->struct_mutex);
3923
3924 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3925 /* Skip inactive CRTCs */
3926 if (!crtc->fb)
3927 continue;
3928
3929 intel_crtc = to_intel_crtc(crtc);
3930 if (!intel_crtc->busy)
3931 intel_decrease_pllclock(crtc);
3932 }
3933
3934 mutex_unlock(&dev->struct_mutex);
3935 }
3936
3937 /**
3938 * intel_mark_busy - mark the GPU and possibly the display busy
3939 * @dev: drm device
3940 * @obj: object we're operating on
3941 *
3942 * Callers can use this function to indicate that the GPU is busy processing
3943 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
3944 * buffer), we'll also mark the display as busy, so we know to increase its
3945 * clock frequency.
3946 */
3947 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3948 {
3949 drm_i915_private_t *dev_priv = dev->dev_private;
3950 struct drm_crtc *crtc = NULL;
3951 struct intel_framebuffer *intel_fb;
3952 struct intel_crtc *intel_crtc;
3953
3954 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3955 return;
3956
3957 if (!dev_priv->busy)
3958 dev_priv->busy = true;
3959 else
3960 mod_timer(&dev_priv->idle_timer, jiffies +
3961 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3962
3963 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3964 if (!crtc->fb)
3965 continue;
3966
3967 intel_crtc = to_intel_crtc(crtc);
3968 intel_fb = to_intel_framebuffer(crtc->fb);
3969 if (intel_fb->obj == obj) {
3970 if (!intel_crtc->busy) {
3971 /* Non-busy -> busy, upclock */
3972 intel_increase_pllclock(crtc, true);
3973 intel_crtc->busy = true;
3974 } else {
3975 /* Busy -> busy, put off timer */
3976 mod_timer(&intel_crtc->idle_timer, jiffies +
3977 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3978 }
3979 }
3980 }
3981 }
3982
3983 static void intel_crtc_destroy(struct drm_crtc *crtc)
3984 {
3985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3986
3987 drm_crtc_cleanup(crtc);
3988 kfree(intel_crtc);
3989 }
3990
3991 struct intel_unpin_work {
3992 struct work_struct work;
3993 struct drm_device *dev;
3994 struct drm_gem_object *obj;
3995 struct drm_pending_vblank_event *event;
3996 int pending;
3997 };
3998
3999 static void intel_unpin_work_fn(struct work_struct *__work)
4000 {
4001 struct intel_unpin_work *work =
4002 container_of(__work, struct intel_unpin_work, work);
4003
4004 mutex_lock(&work->dev->struct_mutex);
4005 i915_gem_object_unpin(work->obj);
4006 drm_gem_object_unreference(work->obj);
4007 mutex_unlock(&work->dev->struct_mutex);
4008 kfree(work);
4009 }
4010
4011 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4012 {
4013 drm_i915_private_t *dev_priv = dev->dev_private;
4014 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4016 struct intel_unpin_work *work;
4017 struct drm_i915_gem_object *obj_priv;
4018 struct drm_pending_vblank_event *e;
4019 struct timeval now;
4020 unsigned long flags;
4021
4022 /* Ignore early vblank irqs */
4023 if (intel_crtc == NULL)
4024 return;
4025
4026 spin_lock_irqsave(&dev->event_lock, flags);
4027 work = intel_crtc->unpin_work;
4028 if (work == NULL || !work->pending) {
4029 spin_unlock_irqrestore(&dev->event_lock, flags);
4030 return;
4031 }
4032
4033 intel_crtc->unpin_work = NULL;
4034 drm_vblank_put(dev, intel_crtc->pipe);
4035
4036 if (work->event) {
4037 e = work->event;
4038 do_gettimeofday(&now);
4039 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4040 e->event.tv_sec = now.tv_sec;
4041 e->event.tv_usec = now.tv_usec;
4042 list_add_tail(&e->base.link,
4043 &e->base.file_priv->event_list);
4044 wake_up_interruptible(&e->base.file_priv->event_wait);
4045 }
4046
4047 spin_unlock_irqrestore(&dev->event_lock, flags);
4048
4049 obj_priv = work->obj->driver_private;
4050 if (atomic_dec_and_test(&obj_priv->pending_flip))
4051 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4052 schedule_work(&work->work);
4053 }
4054
4055 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4056 {
4057 drm_i915_private_t *dev_priv = dev->dev_private;
4058 struct intel_crtc *intel_crtc =
4059 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4060 unsigned long flags;
4061
4062 spin_lock_irqsave(&dev->event_lock, flags);
4063 if (intel_crtc->unpin_work)
4064 intel_crtc->unpin_work->pending = 1;
4065 spin_unlock_irqrestore(&dev->event_lock, flags);
4066 }
4067
4068 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4069 struct drm_framebuffer *fb,
4070 struct drm_pending_vblank_event *event)
4071 {
4072 struct drm_device *dev = crtc->dev;
4073 struct drm_i915_private *dev_priv = dev->dev_private;
4074 struct intel_framebuffer *intel_fb;
4075 struct drm_i915_gem_object *obj_priv;
4076 struct drm_gem_object *obj;
4077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4078 struct intel_unpin_work *work;
4079 unsigned long flags;
4080 int ret;
4081 RING_LOCALS;
4082
4083 work = kzalloc(sizeof *work, GFP_KERNEL);
4084 if (work == NULL)
4085 return -ENOMEM;
4086
4087 mutex_lock(&dev->struct_mutex);
4088
4089 work->event = event;
4090 work->dev = crtc->dev;
4091 intel_fb = to_intel_framebuffer(crtc->fb);
4092 work->obj = intel_fb->obj;
4093 INIT_WORK(&work->work, intel_unpin_work_fn);
4094
4095 /* We borrow the event spin lock for protecting unpin_work */
4096 spin_lock_irqsave(&dev->event_lock, flags);
4097 if (intel_crtc->unpin_work) {
4098 spin_unlock_irqrestore(&dev->event_lock, flags);
4099 kfree(work);
4100 mutex_unlock(&dev->struct_mutex);
4101 return -EBUSY;
4102 }
4103 intel_crtc->unpin_work = work;
4104 spin_unlock_irqrestore(&dev->event_lock, flags);
4105
4106 intel_fb = to_intel_framebuffer(fb);
4107 obj = intel_fb->obj;
4108
4109 ret = intel_pin_and_fence_fb_obj(dev, obj);
4110 if (ret != 0) {
4111 kfree(work);
4112 mutex_unlock(&dev->struct_mutex);
4113 return ret;
4114 }
4115
4116 /* Reference the old fb object for the scheduled work. */
4117 drm_gem_object_reference(work->obj);
4118
4119 crtc->fb = fb;
4120 i915_gem_object_flush_write_domain(obj);
4121 drm_vblank_get(dev, intel_crtc->pipe);
4122 obj_priv = obj->driver_private;
4123 atomic_inc(&obj_priv->pending_flip);
4124
4125 BEGIN_LP_RING(4);
4126 OUT_RING(MI_DISPLAY_FLIP |
4127 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4128 OUT_RING(fb->pitch);
4129 if (IS_I965G(dev)) {
4130 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4131 OUT_RING((fb->width << 16) | fb->height);
4132 } else {
4133 OUT_RING(obj_priv->gtt_offset);
4134 OUT_RING(MI_NOOP);
4135 }
4136 ADVANCE_LP_RING();
4137
4138 mutex_unlock(&dev->struct_mutex);
4139
4140 return 0;
4141 }
4142
4143 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4144 .dpms = intel_crtc_dpms,
4145 .mode_fixup = intel_crtc_mode_fixup,
4146 .mode_set = intel_crtc_mode_set,
4147 .mode_set_base = intel_pipe_set_base,
4148 .prepare = intel_crtc_prepare,
4149 .commit = intel_crtc_commit,
4150 .load_lut = intel_crtc_load_lut,
4151 };
4152
4153 static const struct drm_crtc_funcs intel_crtc_funcs = {
4154 .cursor_set = intel_crtc_cursor_set,
4155 .cursor_move = intel_crtc_cursor_move,
4156 .gamma_set = intel_crtc_gamma_set,
4157 .set_config = drm_crtc_helper_set_config,
4158 .destroy = intel_crtc_destroy,
4159 .page_flip = intel_crtc_page_flip,
4160 };
4161
4162
4163 static void intel_crtc_init(struct drm_device *dev, int pipe)
4164 {
4165 drm_i915_private_t *dev_priv = dev->dev_private;
4166 struct intel_crtc *intel_crtc;
4167 int i;
4168
4169 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4170 if (intel_crtc == NULL)
4171 return;
4172
4173 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4174
4175 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4176 intel_crtc->pipe = pipe;
4177 intel_crtc->plane = pipe;
4178 for (i = 0; i < 256; i++) {
4179 intel_crtc->lut_r[i] = i;
4180 intel_crtc->lut_g[i] = i;
4181 intel_crtc->lut_b[i] = i;
4182 }
4183
4184 /* Swap pipes & planes for FBC on pre-965 */
4185 intel_crtc->pipe = pipe;
4186 intel_crtc->plane = pipe;
4187 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4188 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4189 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4190 }
4191
4192 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4193 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4194 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4195 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4196
4197 intel_crtc->cursor_addr = 0;
4198 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4199 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4200
4201 intel_crtc->busy = false;
4202
4203 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4204 (unsigned long)intel_crtc);
4205 }
4206
4207 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4208 struct drm_file *file_priv)
4209 {
4210 drm_i915_private_t *dev_priv = dev->dev_private;
4211 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4212 struct drm_mode_object *drmmode_obj;
4213 struct intel_crtc *crtc;
4214
4215 if (!dev_priv) {
4216 DRM_ERROR("called with no initialization\n");
4217 return -EINVAL;
4218 }
4219
4220 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4221 DRM_MODE_OBJECT_CRTC);
4222
4223 if (!drmmode_obj) {
4224 DRM_ERROR("no such CRTC id\n");
4225 return -EINVAL;
4226 }
4227
4228 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4229 pipe_from_crtc_id->pipe = crtc->pipe;
4230
4231 return 0;
4232 }
4233
4234 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4235 {
4236 struct drm_crtc *crtc = NULL;
4237
4238 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4240 if (intel_crtc->pipe == pipe)
4241 break;
4242 }
4243 return crtc;
4244 }
4245
4246 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4247 {
4248 int index_mask = 0;
4249 struct drm_connector *connector;
4250 int entry = 0;
4251
4252 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4253 struct intel_output *intel_output = to_intel_output(connector);
4254 if (type_mask & intel_output->clone_mask)
4255 index_mask |= (1 << entry);
4256 entry++;
4257 }
4258 return index_mask;
4259 }
4260
4261
4262 static void intel_setup_outputs(struct drm_device *dev)
4263 {
4264 struct drm_i915_private *dev_priv = dev->dev_private;
4265 struct drm_connector *connector;
4266
4267 intel_crt_init(dev);
4268
4269 /* Set up integrated LVDS */
4270 if (IS_MOBILE(dev) && !IS_I830(dev))
4271 intel_lvds_init(dev);
4272
4273 if (IS_IRONLAKE(dev)) {
4274 int found;
4275
4276 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4277 intel_dp_init(dev, DP_A);
4278
4279 if (I915_READ(HDMIB) & PORT_DETECTED) {
4280 /* check SDVOB */
4281 /* found = intel_sdvo_init(dev, HDMIB); */
4282 found = 0;
4283 if (!found)
4284 intel_hdmi_init(dev, HDMIB);
4285 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4286 intel_dp_init(dev, PCH_DP_B);
4287 }
4288
4289 if (I915_READ(HDMIC) & PORT_DETECTED)
4290 intel_hdmi_init(dev, HDMIC);
4291
4292 if (I915_READ(HDMID) & PORT_DETECTED)
4293 intel_hdmi_init(dev, HDMID);
4294
4295 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4296 intel_dp_init(dev, PCH_DP_C);
4297
4298 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4299 intel_dp_init(dev, PCH_DP_D);
4300
4301 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4302 bool found = false;
4303
4304 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4305 DRM_DEBUG_KMS("probing SDVOB\n");
4306 found = intel_sdvo_init(dev, SDVOB);
4307 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4308 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4309 intel_hdmi_init(dev, SDVOB);
4310 }
4311
4312 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4313 DRM_DEBUG_KMS("probing DP_B\n");
4314 intel_dp_init(dev, DP_B);
4315 }
4316 }
4317
4318 /* Before G4X SDVOC doesn't have its own detect register */
4319
4320 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4321 DRM_DEBUG_KMS("probing SDVOC\n");
4322 found = intel_sdvo_init(dev, SDVOC);
4323 }
4324
4325 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4326
4327 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4328 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4329 intel_hdmi_init(dev, SDVOC);
4330 }
4331 if (SUPPORTS_INTEGRATED_DP(dev)) {
4332 DRM_DEBUG_KMS("probing DP_C\n");
4333 intel_dp_init(dev, DP_C);
4334 }
4335 }
4336
4337 if (SUPPORTS_INTEGRATED_DP(dev) &&
4338 (I915_READ(DP_D) & DP_DETECTED)) {
4339 DRM_DEBUG_KMS("probing DP_D\n");
4340 intel_dp_init(dev, DP_D);
4341 }
4342 } else if (IS_I8XX(dev))
4343 intel_dvo_init(dev);
4344
4345 if (SUPPORTS_TV(dev))
4346 intel_tv_init(dev);
4347
4348 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4349 struct intel_output *intel_output = to_intel_output(connector);
4350 struct drm_encoder *encoder = &intel_output->enc;
4351
4352 encoder->possible_crtcs = intel_output->crtc_mask;
4353 encoder->possible_clones = intel_connector_clones(dev,
4354 intel_output->clone_mask);
4355 }
4356 }
4357
4358 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4359 {
4360 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4361 struct drm_device *dev = fb->dev;
4362
4363 if (fb->fbdev)
4364 intelfb_remove(dev, fb);
4365
4366 drm_framebuffer_cleanup(fb);
4367 mutex_lock(&dev->struct_mutex);
4368 drm_gem_object_unreference(intel_fb->obj);
4369 mutex_unlock(&dev->struct_mutex);
4370
4371 kfree(intel_fb);
4372 }
4373
4374 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4375 struct drm_file *file_priv,
4376 unsigned int *handle)
4377 {
4378 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4379 struct drm_gem_object *object = intel_fb->obj;
4380
4381 return drm_gem_handle_create(file_priv, object, handle);
4382 }
4383
4384 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4385 .destroy = intel_user_framebuffer_destroy,
4386 .create_handle = intel_user_framebuffer_create_handle,
4387 };
4388
4389 int intel_framebuffer_create(struct drm_device *dev,
4390 struct drm_mode_fb_cmd *mode_cmd,
4391 struct drm_framebuffer **fb,
4392 struct drm_gem_object *obj)
4393 {
4394 struct intel_framebuffer *intel_fb;
4395 int ret;
4396
4397 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4398 if (!intel_fb)
4399 return -ENOMEM;
4400
4401 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4402 if (ret) {
4403 DRM_ERROR("framebuffer init failed %d\n", ret);
4404 return ret;
4405 }
4406
4407 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4408
4409 intel_fb->obj = obj;
4410
4411 *fb = &intel_fb->base;
4412
4413 return 0;
4414 }
4415
4416
4417 static struct drm_framebuffer *
4418 intel_user_framebuffer_create(struct drm_device *dev,
4419 struct drm_file *filp,
4420 struct drm_mode_fb_cmd *mode_cmd)
4421 {
4422 struct drm_gem_object *obj;
4423 struct drm_framebuffer *fb;
4424 int ret;
4425
4426 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4427 if (!obj)
4428 return NULL;
4429
4430 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4431 if (ret) {
4432 mutex_lock(&dev->struct_mutex);
4433 drm_gem_object_unreference(obj);
4434 mutex_unlock(&dev->struct_mutex);
4435 return NULL;
4436 }
4437
4438 return fb;
4439 }
4440
4441 static const struct drm_mode_config_funcs intel_mode_funcs = {
4442 .fb_create = intel_user_framebuffer_create,
4443 .fb_changed = intelfb_probe,
4444 };
4445
4446 static struct drm_gem_object *
4447 intel_alloc_power_context(struct drm_device *dev)
4448 {
4449 struct drm_gem_object *pwrctx;
4450 int ret;
4451
4452 pwrctx = drm_gem_object_alloc(dev, 4096);
4453 if (!pwrctx) {
4454 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4455 return NULL;
4456 }
4457
4458 mutex_lock(&dev->struct_mutex);
4459 ret = i915_gem_object_pin(pwrctx, 4096);
4460 if (ret) {
4461 DRM_ERROR("failed to pin power context: %d\n", ret);
4462 goto err_unref;
4463 }
4464
4465 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4466 if (ret) {
4467 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4468 goto err_unpin;
4469 }
4470 mutex_unlock(&dev->struct_mutex);
4471
4472 return pwrctx;
4473
4474 err_unpin:
4475 i915_gem_object_unpin(pwrctx);
4476 err_unref:
4477 drm_gem_object_unreference(pwrctx);
4478 mutex_unlock(&dev->struct_mutex);
4479 return NULL;
4480 }
4481
4482 void intel_init_clock_gating(struct drm_device *dev)
4483 {
4484 struct drm_i915_private *dev_priv = dev->dev_private;
4485
4486 /*
4487 * Disable clock gating reported to work incorrectly according to the
4488 * specs, but enable as much else as we can.
4489 */
4490 if (IS_IRONLAKE(dev)) {
4491 return;
4492 } else if (IS_G4X(dev)) {
4493 uint32_t dspclk_gate;
4494 I915_WRITE(RENCLK_GATE_D1, 0);
4495 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4496 GS_UNIT_CLOCK_GATE_DISABLE |
4497 CL_UNIT_CLOCK_GATE_DISABLE);
4498 I915_WRITE(RAMCLK_GATE_D, 0);
4499 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4500 OVRUNIT_CLOCK_GATE_DISABLE |
4501 OVCUNIT_CLOCK_GATE_DISABLE;
4502 if (IS_GM45(dev))
4503 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4504 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4505 } else if (IS_I965GM(dev)) {
4506 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4507 I915_WRITE(RENCLK_GATE_D2, 0);
4508 I915_WRITE(DSPCLK_GATE_D, 0);
4509 I915_WRITE(RAMCLK_GATE_D, 0);
4510 I915_WRITE16(DEUC, 0);
4511 } else if (IS_I965G(dev)) {
4512 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4513 I965_RCC_CLOCK_GATE_DISABLE |
4514 I965_RCPB_CLOCK_GATE_DISABLE |
4515 I965_ISC_CLOCK_GATE_DISABLE |
4516 I965_FBC_CLOCK_GATE_DISABLE);
4517 I915_WRITE(RENCLK_GATE_D2, 0);
4518 } else if (IS_I9XX(dev)) {
4519 u32 dstate = I915_READ(D_STATE);
4520
4521 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4522 DSTATE_DOT_CLOCK_GATING;
4523 I915_WRITE(D_STATE, dstate);
4524 } else if (IS_I85X(dev) || IS_I865G(dev)) {
4525 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4526 } else if (IS_I830(dev)) {
4527 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4528 }
4529
4530 /*
4531 * GPU can automatically power down the render unit if given a page
4532 * to save state.
4533 */
4534 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4535 struct drm_i915_gem_object *obj_priv = NULL;
4536
4537 if (dev_priv->pwrctx) {
4538 obj_priv = dev_priv->pwrctx->driver_private;
4539 } else {
4540 struct drm_gem_object *pwrctx;
4541
4542 pwrctx = intel_alloc_power_context(dev);
4543 if (pwrctx) {
4544 dev_priv->pwrctx = pwrctx;
4545 obj_priv = pwrctx->driver_private;
4546 }
4547 }
4548
4549 if (obj_priv) {
4550 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4551 I915_WRITE(MCHBAR_RENDER_STANDBY,
4552 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4553 }
4554 }
4555 }
4556
4557 /* Set up chip specific display functions */
4558 static void intel_init_display(struct drm_device *dev)
4559 {
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561
4562 /* We always want a DPMS function */
4563 if (IS_IRONLAKE(dev))
4564 dev_priv->display.dpms = ironlake_crtc_dpms;
4565 else
4566 dev_priv->display.dpms = i9xx_crtc_dpms;
4567
4568 /* Only mobile has FBC, leave pointers NULL for other chips */
4569 if (IS_MOBILE(dev)) {
4570 if (IS_GM45(dev)) {
4571 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4572 dev_priv->display.enable_fbc = g4x_enable_fbc;
4573 dev_priv->display.disable_fbc = g4x_disable_fbc;
4574 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4575 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4576 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4577 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4578 }
4579 /* 855GM needs testing */
4580 }
4581
4582 /* Returns the core display clock speed */
4583 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4584 dev_priv->display.get_display_clock_speed =
4585 i945_get_display_clock_speed;
4586 else if (IS_I915G(dev))
4587 dev_priv->display.get_display_clock_speed =
4588 i915_get_display_clock_speed;
4589 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4590 dev_priv->display.get_display_clock_speed =
4591 i9xx_misc_get_display_clock_speed;
4592 else if (IS_I915GM(dev))
4593 dev_priv->display.get_display_clock_speed =
4594 i915gm_get_display_clock_speed;
4595 else if (IS_I865G(dev))
4596 dev_priv->display.get_display_clock_speed =
4597 i865_get_display_clock_speed;
4598 else if (IS_I85X(dev))
4599 dev_priv->display.get_display_clock_speed =
4600 i855_get_display_clock_speed;
4601 else /* 852, 830 */
4602 dev_priv->display.get_display_clock_speed =
4603 i830_get_display_clock_speed;
4604
4605 /* For FIFO watermark updates */
4606 if (IS_IRONLAKE(dev))
4607 dev_priv->display.update_wm = NULL;
4608 else if (IS_G4X(dev))
4609 dev_priv->display.update_wm = g4x_update_wm;
4610 else if (IS_I965G(dev))
4611 dev_priv->display.update_wm = i965_update_wm;
4612 else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4613 dev_priv->display.update_wm = i9xx_update_wm;
4614 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4615 } else {
4616 if (IS_I85X(dev))
4617 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4618 else if (IS_845G(dev))
4619 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4620 else
4621 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4622 dev_priv->display.update_wm = i830_update_wm;
4623 }
4624 }
4625
4626 void intel_modeset_init(struct drm_device *dev)
4627 {
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629 int num_pipe;
4630 int i;
4631
4632 drm_mode_config_init(dev);
4633
4634 dev->mode_config.min_width = 0;
4635 dev->mode_config.min_height = 0;
4636
4637 dev->mode_config.funcs = (void *)&intel_mode_funcs;
4638
4639 intel_init_display(dev);
4640
4641 if (IS_I965G(dev)) {
4642 dev->mode_config.max_width = 8192;
4643 dev->mode_config.max_height = 8192;
4644 } else if (IS_I9XX(dev)) {
4645 dev->mode_config.max_width = 4096;
4646 dev->mode_config.max_height = 4096;
4647 } else {
4648 dev->mode_config.max_width = 2048;
4649 dev->mode_config.max_height = 2048;
4650 }
4651
4652 /* set memory base */
4653 if (IS_I9XX(dev))
4654 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4655 else
4656 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4657
4658 if (IS_MOBILE(dev) || IS_I9XX(dev))
4659 num_pipe = 2;
4660 else
4661 num_pipe = 1;
4662 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4663 num_pipe, num_pipe > 1 ? "s" : "");
4664
4665 if (IS_I85X(dev))
4666 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4667 else if (IS_I9XX(dev) || IS_G4X(dev))
4668 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4669
4670 for (i = 0; i < num_pipe; i++) {
4671 intel_crtc_init(dev, i);
4672 }
4673
4674 intel_setup_outputs(dev);
4675
4676 intel_init_clock_gating(dev);
4677
4678 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4679 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4680 (unsigned long)dev);
4681
4682 intel_setup_overlay(dev);
4683
4684 if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4685 dev_priv->fsb_freq,
4686 dev_priv->mem_freq))
4687 DRM_INFO("failed to find known CxSR latency "
4688 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4689 dev_priv->fsb_freq, dev_priv->mem_freq);
4690 }
4691
4692 void intel_modeset_cleanup(struct drm_device *dev)
4693 {
4694 struct drm_i915_private *dev_priv = dev->dev_private;
4695 struct drm_crtc *crtc;
4696 struct intel_crtc *intel_crtc;
4697
4698 mutex_lock(&dev->struct_mutex);
4699
4700 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4701 /* Skip inactive CRTCs */
4702 if (!crtc->fb)
4703 continue;
4704
4705 intel_crtc = to_intel_crtc(crtc);
4706 intel_increase_pllclock(crtc, false);
4707 del_timer_sync(&intel_crtc->idle_timer);
4708 }
4709
4710 del_timer_sync(&dev_priv->idle_timer);
4711
4712 if (dev_priv->display.disable_fbc)
4713 dev_priv->display.disable_fbc(dev);
4714
4715 if (dev_priv->pwrctx) {
4716 struct drm_i915_gem_object *obj_priv;
4717
4718 obj_priv = dev_priv->pwrctx->driver_private;
4719 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4720 I915_READ(PWRCTXA);
4721 i915_gem_object_unpin(dev_priv->pwrctx);
4722 drm_gem_object_unreference(dev_priv->pwrctx);
4723 }
4724
4725 mutex_unlock(&dev->struct_mutex);
4726
4727 drm_mode_config_cleanup(dev);
4728 }
4729
4730
4731 /* current intel driver doesn't take advantage of encoders
4732 always give back the encoder for the connector
4733 */
4734 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4735 {
4736 struct intel_output *intel_output = to_intel_output(connector);
4737
4738 return &intel_output->enc;
4739 }
4740
4741 /*
4742 * set vga decode state - true == enable VGA decode
4743 */
4744 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4745 {
4746 struct drm_i915_private *dev_priv = dev->dev_private;
4747 u16 gmch_ctrl;
4748
4749 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4750 if (state)
4751 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4752 else
4753 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4754 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4755 return 0;
4756 }
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