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Merge remote-tracking branch 'airlied/drm-next' into topic/vblank-rework
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait timed out\n");
904 }
905
906 /**
907 * intel_wait_for_vblank - wait for vblank on a given pipe
908 * @dev: drm device
909 * @pipe: pipe to wait for
910 *
911 * Wait for vblank to occur on a given pipe. Needed for various bits of
912 * mode setting code.
913 */
914 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
915 {
916 struct drm_i915_private *dev_priv = dev->dev_private;
917 int pipestat_reg = PIPESTAT(pipe);
918
919 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
920 g4x_wait_for_vblank(dev, pipe);
921 return;
922 }
923
924 /* Clear existing vblank status. Note this will clear any other
925 * sticky status fields as well.
926 *
927 * This races with i915_driver_irq_handler() with the result
928 * that either function could miss a vblank event. Here it is not
929 * fatal, as we will either wait upon the next vblank interrupt or
930 * timeout. Generally speaking intel_wait_for_vblank() is only
931 * called during modeset at which time the GPU should be idle and
932 * should *not* be performing page flips and thus not waiting on
933 * vblanks...
934 * Currently, the result of us stealing a vblank from the irq
935 * handler is that a single frame will be skipped during swapbuffers.
936 */
937 I915_WRITE(pipestat_reg,
938 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
939
940 /* Wait for vblank interrupt bit to set */
941 if (wait_for(I915_READ(pipestat_reg) &
942 PIPE_VBLANK_INTERRUPT_STATUS,
943 50))
944 DRM_DEBUG_KMS("vblank wait timed out\n");
945 }
946
947 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
948 {
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 reg = PIPEDSL(pipe);
951 u32 line1, line2;
952 u32 line_mask;
953
954 if (IS_GEN2(dev))
955 line_mask = DSL_LINEMASK_GEN2;
956 else
957 line_mask = DSL_LINEMASK_GEN3;
958
959 line1 = I915_READ(reg) & line_mask;
960 mdelay(5);
961 line2 = I915_READ(reg) & line_mask;
962
963 return line1 == line2;
964 }
965
966 /*
967 * intel_wait_for_pipe_off - wait for pipe to turn off
968 * @dev: drm device
969 * @pipe: pipe to wait for
970 *
971 * After disabling a pipe, we can't wait for vblank in the usual way,
972 * spinning on the vblank interrupt status bit, since we won't actually
973 * see an interrupt when the pipe is disabled.
974 *
975 * On Gen4 and above:
976 * wait for the pipe register state bit to turn off
977 *
978 * Otherwise:
979 * wait for the display line value to settle (it usually
980 * ends up stopping at the start of the next frame).
981 *
982 */
983 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
984 {
985 struct drm_i915_private *dev_priv = dev->dev_private;
986 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
987 pipe);
988
989 if (INTEL_INFO(dev)->gen >= 4) {
990 int reg = PIPECONF(cpu_transcoder);
991
992 /* Wait for the Pipe State to go off */
993 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
994 100))
995 WARN(1, "pipe_off wait timed out\n");
996 } else {
997 /* Wait for the display line to settle */
998 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
999 WARN(1, "pipe_off wait timed out\n");
1000 }
1001 }
1002
1003 /*
1004 * ibx_digital_port_connected - is the specified port connected?
1005 * @dev_priv: i915 private structure
1006 * @port: the port to test
1007 *
1008 * Returns true if @port is connected, false otherwise.
1009 */
1010 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1011 struct intel_digital_port *port)
1012 {
1013 u32 bit;
1014
1015 if (HAS_PCH_IBX(dev_priv->dev)) {
1016 switch (port->port) {
1017 case PORT_B:
1018 bit = SDE_PORTB_HOTPLUG;
1019 break;
1020 case PORT_C:
1021 bit = SDE_PORTC_HOTPLUG;
1022 break;
1023 case PORT_D:
1024 bit = SDE_PORTD_HOTPLUG;
1025 break;
1026 default:
1027 return true;
1028 }
1029 } else {
1030 switch (port->port) {
1031 case PORT_B:
1032 bit = SDE_PORTB_HOTPLUG_CPT;
1033 break;
1034 case PORT_C:
1035 bit = SDE_PORTC_HOTPLUG_CPT;
1036 break;
1037 case PORT_D:
1038 bit = SDE_PORTD_HOTPLUG_CPT;
1039 break;
1040 default:
1041 return true;
1042 }
1043 }
1044
1045 return I915_READ(SDEISR) & bit;
1046 }
1047
1048 static const char *state_string(bool enabled)
1049 {
1050 return enabled ? "on" : "off";
1051 }
1052
1053 /* Only for pre-ILK configs */
1054 void assert_pll(struct drm_i915_private *dev_priv,
1055 enum pipe pipe, bool state)
1056 {
1057 int reg;
1058 u32 val;
1059 bool cur_state;
1060
1061 reg = DPLL(pipe);
1062 val = I915_READ(reg);
1063 cur_state = !!(val & DPLL_VCO_ENABLE);
1064 WARN(cur_state != state,
1065 "PLL state assertion failure (expected %s, current %s)\n",
1066 state_string(state), state_string(cur_state));
1067 }
1068
1069 /* XXX: the dsi pll is shared between MIPI DSI ports */
1070 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1071 {
1072 u32 val;
1073 bool cur_state;
1074
1075 mutex_lock(&dev_priv->dpio_lock);
1076 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1077 mutex_unlock(&dev_priv->dpio_lock);
1078
1079 cur_state = val & DSI_PLL_VCO_EN;
1080 WARN(cur_state != state,
1081 "DSI PLL state assertion failure (expected %s, current %s)\n",
1082 state_string(state), state_string(cur_state));
1083 }
1084 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1085 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1086
1087 struct intel_shared_dpll *
1088 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1089 {
1090 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1091
1092 if (crtc->config.shared_dpll < 0)
1093 return NULL;
1094
1095 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1096 }
1097
1098 /* For ILK+ */
1099 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1100 struct intel_shared_dpll *pll,
1101 bool state)
1102 {
1103 bool cur_state;
1104 struct intel_dpll_hw_state hw_state;
1105
1106 if (WARN (!pll,
1107 "asserting DPLL %s with no DPLL\n", state_string(state)))
1108 return;
1109
1110 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1111 WARN(cur_state != state,
1112 "%s assertion failure (expected %s, current %s)\n",
1113 pll->name, state_string(state), state_string(cur_state));
1114 }
1115
1116 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1117 enum pipe pipe, bool state)
1118 {
1119 int reg;
1120 u32 val;
1121 bool cur_state;
1122 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1123 pipe);
1124
1125 if (HAS_DDI(dev_priv->dev)) {
1126 /* DDI does not have a specific FDI_TX register */
1127 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1130 } else {
1131 reg = FDI_TX_CTL(pipe);
1132 val = I915_READ(reg);
1133 cur_state = !!(val & FDI_TX_ENABLE);
1134 }
1135 WARN(cur_state != state,
1136 "FDI TX state assertion failure (expected %s, current %s)\n",
1137 state_string(state), state_string(cur_state));
1138 }
1139 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1140 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141
1142 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, bool state)
1144 {
1145 int reg;
1146 u32 val;
1147 bool cur_state;
1148
1149 reg = FDI_RX_CTL(pipe);
1150 val = I915_READ(reg);
1151 cur_state = !!(val & FDI_RX_ENABLE);
1152 WARN(cur_state != state,
1153 "FDI RX state assertion failure (expected %s, current %s)\n",
1154 state_string(state), state_string(cur_state));
1155 }
1156 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158
1159 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161 {
1162 int reg;
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1167 return;
1168
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv->dev))
1171 return;
1172
1173 reg = FDI_TX_CTL(pipe);
1174 val = I915_READ(reg);
1175 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1176 }
1177
1178 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1179 enum pipe pipe, bool state)
1180 {
1181 int reg;
1182 u32 val;
1183 bool cur_state;
1184
1185 reg = FDI_RX_CTL(pipe);
1186 val = I915_READ(reg);
1187 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1188 WARN(cur_state != state,
1189 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
1191 }
1192
1193 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
1195 {
1196 int pp_reg, lvds_reg;
1197 u32 val;
1198 enum pipe panel_pipe = PIPE_A;
1199 bool locked = true;
1200
1201 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1202 pp_reg = PCH_PP_CONTROL;
1203 lvds_reg = PCH_LVDS;
1204 } else {
1205 pp_reg = PP_CONTROL;
1206 lvds_reg = LVDS;
1207 }
1208
1209 val = I915_READ(pp_reg);
1210 if (!(val & PANEL_POWER_ON) ||
1211 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1212 locked = false;
1213
1214 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216
1217 WARN(panel_pipe == pipe && locked,
1218 "panel assertion failure, pipe %c regs locked\n",
1219 pipe_name(pipe));
1220 }
1221
1222 static void assert_cursor(struct drm_i915_private *dev_priv,
1223 enum pipe pipe, bool state)
1224 {
1225 struct drm_device *dev = dev_priv->dev;
1226 bool cur_state;
1227
1228 if (IS_845G(dev) || IS_I865G(dev))
1229 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1230 else
1231 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1232
1233 WARN(cur_state != state,
1234 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1235 pipe_name(pipe), state_string(state), state_string(cur_state));
1236 }
1237 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1238 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1239
1240 void assert_pipe(struct drm_i915_private *dev_priv,
1241 enum pipe pipe, bool state)
1242 {
1243 int reg;
1244 u32 val;
1245 bool cur_state;
1246 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1247 pipe);
1248
1249 /* if we need the pipe A quirk it must be always on */
1250 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1251 state = true;
1252
1253 if (!intel_display_power_enabled(dev_priv,
1254 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1255 cur_state = false;
1256 } else {
1257 reg = PIPECONF(cpu_transcoder);
1258 val = I915_READ(reg);
1259 cur_state = !!(val & PIPECONF_ENABLE);
1260 }
1261
1262 WARN(cur_state != state,
1263 "pipe %c assertion failure (expected %s, current %s)\n",
1264 pipe_name(pipe), state_string(state), state_string(cur_state));
1265 }
1266
1267 static void assert_plane(struct drm_i915_private *dev_priv,
1268 enum plane plane, bool state)
1269 {
1270 int reg;
1271 u32 val;
1272 bool cur_state;
1273
1274 reg = DSPCNTR(plane);
1275 val = I915_READ(reg);
1276 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1277 WARN(cur_state != state,
1278 "plane %c assertion failure (expected %s, current %s)\n",
1279 plane_name(plane), state_string(state), state_string(cur_state));
1280 }
1281
1282 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1283 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1284
1285 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1286 enum pipe pipe)
1287 {
1288 struct drm_device *dev = dev_priv->dev;
1289 int reg, i;
1290 u32 val;
1291 int cur_pipe;
1292
1293 /* Primary planes are fixed to pipes on gen4+ */
1294 if (INTEL_INFO(dev)->gen >= 4) {
1295 reg = DSPCNTR(pipe);
1296 val = I915_READ(reg);
1297 WARN(val & DISPLAY_PLANE_ENABLE,
1298 "plane %c assertion failure, should be disabled but not\n",
1299 plane_name(pipe));
1300 return;
1301 }
1302
1303 /* Need to check both planes against the pipe */
1304 for_each_pipe(i) {
1305 reg = DSPCNTR(i);
1306 val = I915_READ(reg);
1307 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1308 DISPPLANE_SEL_PIPE_SHIFT;
1309 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1310 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1311 plane_name(i), pipe_name(pipe));
1312 }
1313 }
1314
1315 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317 {
1318 struct drm_device *dev = dev_priv->dev;
1319 int reg, sprite;
1320 u32 val;
1321
1322 if (IS_VALLEYVIEW(dev)) {
1323 for_each_sprite(pipe, sprite) {
1324 reg = SPCNTR(pipe, sprite);
1325 val = I915_READ(reg);
1326 WARN(val & SP_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 sprite_name(pipe, sprite), pipe_name(pipe));
1329 }
1330 } else if (INTEL_INFO(dev)->gen >= 7) {
1331 reg = SPRCTL(pipe);
1332 val = I915_READ(reg);
1333 WARN(val & SPRITE_ENABLE,
1334 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1335 plane_name(pipe), pipe_name(pipe));
1336 } else if (INTEL_INFO(dev)->gen >= 5) {
1337 reg = DVSCNTR(pipe);
1338 val = I915_READ(reg);
1339 WARN(val & DVS_ENABLE,
1340 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1341 plane_name(pipe), pipe_name(pipe));
1342 }
1343 }
1344
1345 static void assert_vblank_disabled(struct drm_crtc *crtc)
1346 {
1347 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1348 drm_crtc_vblank_put(crtc);
1349 }
1350
1351 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1352 {
1353 u32 val;
1354 bool enabled;
1355
1356 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1357
1358 val = I915_READ(PCH_DREF_CONTROL);
1359 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1360 DREF_SUPERSPREAD_SOURCE_MASK));
1361 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1362 }
1363
1364 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366 {
1367 int reg;
1368 u32 val;
1369 bool enabled;
1370
1371 reg = PCH_TRANSCONF(pipe);
1372 val = I915_READ(reg);
1373 enabled = !!(val & TRANS_ENABLE);
1374 WARN(enabled,
1375 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1376 pipe_name(pipe));
1377 }
1378
1379 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1380 enum pipe pipe, u32 port_sel, u32 val)
1381 {
1382 if ((val & DP_PORT_EN) == 0)
1383 return false;
1384
1385 if (HAS_PCH_CPT(dev_priv->dev)) {
1386 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1387 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1388 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1389 return false;
1390 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1391 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1392 return false;
1393 } else {
1394 if ((val & DP_PIPE_MASK) != (pipe << 30))
1395 return false;
1396 }
1397 return true;
1398 }
1399
1400 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, u32 val)
1402 {
1403 if ((val & SDVO_ENABLE) == 0)
1404 return false;
1405
1406 if (HAS_PCH_CPT(dev_priv->dev)) {
1407 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1408 return false;
1409 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1410 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1411 return false;
1412 } else {
1413 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1414 return false;
1415 }
1416 return true;
1417 }
1418
1419 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1421 {
1422 if ((val & LVDS_PORT_EN) == 0)
1423 return false;
1424
1425 if (HAS_PCH_CPT(dev_priv->dev)) {
1426 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1427 return false;
1428 } else {
1429 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1430 return false;
1431 }
1432 return true;
1433 }
1434
1435 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1436 enum pipe pipe, u32 val)
1437 {
1438 if ((val & ADPA_DAC_ENABLE) == 0)
1439 return false;
1440 if (HAS_PCH_CPT(dev_priv->dev)) {
1441 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1442 return false;
1443 } else {
1444 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1445 return false;
1446 }
1447 return true;
1448 }
1449
1450 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg, u32 port_sel)
1452 {
1453 u32 val = I915_READ(reg);
1454 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1455 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1457
1458 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1459 && (val & DP_PIPEB_SELECT),
1460 "IBX PCH dp port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe, int reg)
1465 {
1466 u32 val = I915_READ(reg);
1467 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1468 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1469 reg, pipe_name(pipe));
1470
1471 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1472 && (val & SDVO_PIPE_B_SELECT),
1473 "IBX PCH hdmi port still using transcoder B\n");
1474 }
1475
1476 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe)
1478 {
1479 int reg;
1480 u32 val;
1481
1482 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1483 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1484 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1485
1486 reg = PCH_ADPA;
1487 val = I915_READ(reg);
1488 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1489 "PCH VGA enabled on transcoder %c, should be disabled\n",
1490 pipe_name(pipe));
1491
1492 reg = PCH_LVDS;
1493 val = I915_READ(reg);
1494 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1495 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1496 pipe_name(pipe));
1497
1498 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1499 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1500 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1501 }
1502
1503 static void intel_init_dpio(struct drm_device *dev)
1504 {
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506
1507 if (!IS_VALLEYVIEW(dev))
1508 return;
1509
1510 /*
1511 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1512 * CHV x1 PHY (DP/HDMI D)
1513 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1514 */
1515 if (IS_CHERRYVIEW(dev)) {
1516 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1517 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1518 } else {
1519 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1520 }
1521 }
1522
1523 static void vlv_enable_pll(struct intel_crtc *crtc)
1524 {
1525 struct drm_device *dev = crtc->base.dev;
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527 int reg = DPLL(crtc->pipe);
1528 u32 dpll = crtc->config.dpll_hw_state.dpll;
1529
1530 assert_pipe_disabled(dev_priv, crtc->pipe);
1531
1532 /* No really, not for ILK+ */
1533 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1534
1535 /* PLL is protected by panel, make sure we can write it */
1536 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1537 assert_panel_unlocked(dev_priv, crtc->pipe);
1538
1539 I915_WRITE(reg, dpll);
1540 POSTING_READ(reg);
1541 udelay(150);
1542
1543 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1544 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1545
1546 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1547 POSTING_READ(DPLL_MD(crtc->pipe));
1548
1549 /* We do this three times for luck */
1550 I915_WRITE(reg, dpll);
1551 POSTING_READ(reg);
1552 udelay(150); /* wait for warmup */
1553 I915_WRITE(reg, dpll);
1554 POSTING_READ(reg);
1555 udelay(150); /* wait for warmup */
1556 I915_WRITE(reg, dpll);
1557 POSTING_READ(reg);
1558 udelay(150); /* wait for warmup */
1559 }
1560
1561 static void chv_enable_pll(struct intel_crtc *crtc)
1562 {
1563 struct drm_device *dev = crtc->base.dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 int pipe = crtc->pipe;
1566 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1567 u32 tmp;
1568
1569 assert_pipe_disabled(dev_priv, crtc->pipe);
1570
1571 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1572
1573 mutex_lock(&dev_priv->dpio_lock);
1574
1575 /* Enable back the 10bit clock to display controller */
1576 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1577 tmp |= DPIO_DCLKP_EN;
1578 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1579
1580 /*
1581 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1582 */
1583 udelay(1);
1584
1585 /* Enable PLL */
1586 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1587
1588 /* Check PLL is locked */
1589 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1590 DRM_ERROR("PLL %d failed to lock\n", pipe);
1591
1592 /* not sure when this should be written */
1593 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1594 POSTING_READ(DPLL_MD(pipe));
1595
1596 mutex_unlock(&dev_priv->dpio_lock);
1597 }
1598
1599 static void i9xx_enable_pll(struct intel_crtc *crtc)
1600 {
1601 struct drm_device *dev = crtc->base.dev;
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 int reg = DPLL(crtc->pipe);
1604 u32 dpll = crtc->config.dpll_hw_state.dpll;
1605
1606 assert_pipe_disabled(dev_priv, crtc->pipe);
1607
1608 /* No really, not for ILK+ */
1609 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1610
1611 /* PLL is protected by panel, make sure we can write it */
1612 if (IS_MOBILE(dev) && !IS_I830(dev))
1613 assert_panel_unlocked(dev_priv, crtc->pipe);
1614
1615 I915_WRITE(reg, dpll);
1616
1617 /* Wait for the clocks to stabilize. */
1618 POSTING_READ(reg);
1619 udelay(150);
1620
1621 if (INTEL_INFO(dev)->gen >= 4) {
1622 I915_WRITE(DPLL_MD(crtc->pipe),
1623 crtc->config.dpll_hw_state.dpll_md);
1624 } else {
1625 /* The pixel multiplier can only be updated once the
1626 * DPLL is enabled and the clocks are stable.
1627 *
1628 * So write it again.
1629 */
1630 I915_WRITE(reg, dpll);
1631 }
1632
1633 /* We do this three times for luck */
1634 I915_WRITE(reg, dpll);
1635 POSTING_READ(reg);
1636 udelay(150); /* wait for warmup */
1637 I915_WRITE(reg, dpll);
1638 POSTING_READ(reg);
1639 udelay(150); /* wait for warmup */
1640 I915_WRITE(reg, dpll);
1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
1643 }
1644
1645 /**
1646 * i9xx_disable_pll - disable a PLL
1647 * @dev_priv: i915 private structure
1648 * @pipe: pipe PLL to disable
1649 *
1650 * Disable the PLL for @pipe, making sure the pipe is off first.
1651 *
1652 * Note! This is for pre-ILK only.
1653 */
1654 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1655 {
1656 /* Don't disable pipe A or pipe A PLLs if needed */
1657 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1658 return;
1659
1660 /* Make sure the pipe isn't still relying on us */
1661 assert_pipe_disabled(dev_priv, pipe);
1662
1663 I915_WRITE(DPLL(pipe), 0);
1664 POSTING_READ(DPLL(pipe));
1665 }
1666
1667 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1668 {
1669 u32 val = 0;
1670
1671 /* Make sure the pipe isn't still relying on us */
1672 assert_pipe_disabled(dev_priv, pipe);
1673
1674 /*
1675 * Leave integrated clock source and reference clock enabled for pipe B.
1676 * The latter is needed for VGA hotplug / manual detection.
1677 */
1678 if (pipe == PIPE_B)
1679 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1680 I915_WRITE(DPLL(pipe), val);
1681 POSTING_READ(DPLL(pipe));
1682
1683 }
1684
1685 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1686 {
1687 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1688 u32 val;
1689
1690 /* Make sure the pipe isn't still relying on us */
1691 assert_pipe_disabled(dev_priv, pipe);
1692
1693 /* Set PLL en = 0 */
1694 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1695 if (pipe != PIPE_A)
1696 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1697 I915_WRITE(DPLL(pipe), val);
1698 POSTING_READ(DPLL(pipe));
1699
1700 mutex_lock(&dev_priv->dpio_lock);
1701
1702 /* Disable 10bit clock to display controller */
1703 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1704 val &= ~DPIO_DCLKP_EN;
1705 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1706
1707 /* disable left/right clock distribution */
1708 if (pipe != PIPE_B) {
1709 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1710 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1711 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1712 } else {
1713 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1714 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1715 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1716 }
1717
1718 mutex_unlock(&dev_priv->dpio_lock);
1719 }
1720
1721 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1722 struct intel_digital_port *dport)
1723 {
1724 u32 port_mask;
1725 int dpll_reg;
1726
1727 switch (dport->port) {
1728 case PORT_B:
1729 port_mask = DPLL_PORTB_READY_MASK;
1730 dpll_reg = DPLL(0);
1731 break;
1732 case PORT_C:
1733 port_mask = DPLL_PORTC_READY_MASK;
1734 dpll_reg = DPLL(0);
1735 break;
1736 case PORT_D:
1737 port_mask = DPLL_PORTD_READY_MASK;
1738 dpll_reg = DPIO_PHY_STATUS;
1739 break;
1740 default:
1741 BUG();
1742 }
1743
1744 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1745 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1746 port_name(dport->port), I915_READ(dpll_reg));
1747 }
1748
1749 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1750 {
1751 struct drm_device *dev = crtc->base.dev;
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1754
1755 if (WARN_ON(pll == NULL))
1756 return;
1757
1758 WARN_ON(!pll->refcount);
1759 if (pll->active == 0) {
1760 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1761 WARN_ON(pll->on);
1762 assert_shared_dpll_disabled(dev_priv, pll);
1763
1764 pll->mode_set(dev_priv, pll);
1765 }
1766 }
1767
1768 /**
1769 * intel_enable_shared_dpll - enable PCH PLL
1770 * @dev_priv: i915 private structure
1771 * @pipe: pipe PLL to enable
1772 *
1773 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1774 * drives the transcoder clock.
1775 */
1776 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1777 {
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 if (WARN_ON(pll->refcount == 0))
1786 return;
1787
1788 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1789 pll->name, pll->active, pll->on,
1790 crtc->base.base.id);
1791
1792 if (pll->active++) {
1793 WARN_ON(!pll->on);
1794 assert_shared_dpll_enabled(dev_priv, pll);
1795 return;
1796 }
1797 WARN_ON(pll->on);
1798
1799 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1800
1801 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1802 pll->enable(dev_priv, pll);
1803 pll->on = true;
1804 }
1805
1806 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1807 {
1808 struct drm_device *dev = crtc->base.dev;
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1811
1812 /* PCH only available on ILK+ */
1813 BUG_ON(INTEL_INFO(dev)->gen < 5);
1814 if (WARN_ON(pll == NULL))
1815 return;
1816
1817 if (WARN_ON(pll->refcount == 0))
1818 return;
1819
1820 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1821 pll->name, pll->active, pll->on,
1822 crtc->base.base.id);
1823
1824 if (WARN_ON(pll->active == 0)) {
1825 assert_shared_dpll_disabled(dev_priv, pll);
1826 return;
1827 }
1828
1829 assert_shared_dpll_enabled(dev_priv, pll);
1830 WARN_ON(!pll->on);
1831 if (--pll->active)
1832 return;
1833
1834 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1835 pll->disable(dev_priv, pll);
1836 pll->on = false;
1837
1838 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1839 }
1840
1841 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1842 enum pipe pipe)
1843 {
1844 struct drm_device *dev = dev_priv->dev;
1845 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1847 uint32_t reg, val, pipeconf_val;
1848
1849 /* PCH only available on ILK+ */
1850 BUG_ON(INTEL_INFO(dev)->gen < 5);
1851
1852 /* Make sure PCH DPLL is enabled */
1853 assert_shared_dpll_enabled(dev_priv,
1854 intel_crtc_to_shared_dpll(intel_crtc));
1855
1856 /* FDI must be feeding us bits for PCH ports */
1857 assert_fdi_tx_enabled(dev_priv, pipe);
1858 assert_fdi_rx_enabled(dev_priv, pipe);
1859
1860 if (HAS_PCH_CPT(dev)) {
1861 /* Workaround: Set the timing override bit before enabling the
1862 * pch transcoder. */
1863 reg = TRANS_CHICKEN2(pipe);
1864 val = I915_READ(reg);
1865 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1866 I915_WRITE(reg, val);
1867 }
1868
1869 reg = PCH_TRANSCONF(pipe);
1870 val = I915_READ(reg);
1871 pipeconf_val = I915_READ(PIPECONF(pipe));
1872
1873 if (HAS_PCH_IBX(dev_priv->dev)) {
1874 /*
1875 * make the BPC in transcoder be consistent with
1876 * that in pipeconf reg.
1877 */
1878 val &= ~PIPECONF_BPC_MASK;
1879 val |= pipeconf_val & PIPECONF_BPC_MASK;
1880 }
1881
1882 val &= ~TRANS_INTERLACE_MASK;
1883 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1884 if (HAS_PCH_IBX(dev_priv->dev) &&
1885 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1886 val |= TRANS_LEGACY_INTERLACED_ILK;
1887 else
1888 val |= TRANS_INTERLACED;
1889 else
1890 val |= TRANS_PROGRESSIVE;
1891
1892 I915_WRITE(reg, val | TRANS_ENABLE);
1893 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1894 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1895 }
1896
1897 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1898 enum transcoder cpu_transcoder)
1899 {
1900 u32 val, pipeconf_val;
1901
1902 /* PCH only available on ILK+ */
1903 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1904
1905 /* FDI must be feeding us bits for PCH ports */
1906 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1907 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1908
1909 /* Workaround: set timing override bit. */
1910 val = I915_READ(_TRANSA_CHICKEN2);
1911 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1912 I915_WRITE(_TRANSA_CHICKEN2, val);
1913
1914 val = TRANS_ENABLE;
1915 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1916
1917 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1918 PIPECONF_INTERLACED_ILK)
1919 val |= TRANS_INTERLACED;
1920 else
1921 val |= TRANS_PROGRESSIVE;
1922
1923 I915_WRITE(LPT_TRANSCONF, val);
1924 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1925 DRM_ERROR("Failed to enable PCH transcoder\n");
1926 }
1927
1928 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1929 enum pipe pipe)
1930 {
1931 struct drm_device *dev = dev_priv->dev;
1932 uint32_t reg, val;
1933
1934 /* FDI relies on the transcoder */
1935 assert_fdi_tx_disabled(dev_priv, pipe);
1936 assert_fdi_rx_disabled(dev_priv, pipe);
1937
1938 /* Ports must be off as well */
1939 assert_pch_ports_disabled(dev_priv, pipe);
1940
1941 reg = PCH_TRANSCONF(pipe);
1942 val = I915_READ(reg);
1943 val &= ~TRANS_ENABLE;
1944 I915_WRITE(reg, val);
1945 /* wait for PCH transcoder off, transcoder state */
1946 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1947 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1948
1949 if (!HAS_PCH_IBX(dev)) {
1950 /* Workaround: Clear the timing override chicken bit again. */
1951 reg = TRANS_CHICKEN2(pipe);
1952 val = I915_READ(reg);
1953 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1954 I915_WRITE(reg, val);
1955 }
1956 }
1957
1958 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1959 {
1960 u32 val;
1961
1962 val = I915_READ(LPT_TRANSCONF);
1963 val &= ~TRANS_ENABLE;
1964 I915_WRITE(LPT_TRANSCONF, val);
1965 /* wait for PCH transcoder off, transcoder state */
1966 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1967 DRM_ERROR("Failed to disable PCH transcoder\n");
1968
1969 /* Workaround: clear timing override bit. */
1970 val = I915_READ(_TRANSA_CHICKEN2);
1971 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1972 I915_WRITE(_TRANSA_CHICKEN2, val);
1973 }
1974
1975 /**
1976 * intel_enable_pipe - enable a pipe, asserting requirements
1977 * @crtc: crtc responsible for the pipe
1978 *
1979 * Enable @crtc's pipe, making sure that various hardware specific requirements
1980 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1981 */
1982 static void intel_enable_pipe(struct intel_crtc *crtc)
1983 {
1984 struct drm_device *dev = crtc->base.dev;
1985 struct drm_i915_private *dev_priv = dev->dev_private;
1986 enum pipe pipe = crtc->pipe;
1987 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1988 pipe);
1989 enum pipe pch_transcoder;
1990 int reg;
1991 u32 val;
1992
1993 assert_planes_disabled(dev_priv, pipe);
1994 assert_cursor_disabled(dev_priv, pipe);
1995 assert_sprites_disabled(dev_priv, pipe);
1996
1997 if (HAS_PCH_LPT(dev_priv->dev))
1998 pch_transcoder = TRANSCODER_A;
1999 else
2000 pch_transcoder = pipe;
2001
2002 /*
2003 * A pipe without a PLL won't actually be able to drive bits from
2004 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2005 * need the check.
2006 */
2007 if (!HAS_PCH_SPLIT(dev_priv->dev))
2008 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2009 assert_dsi_pll_enabled(dev_priv);
2010 else
2011 assert_pll_enabled(dev_priv, pipe);
2012 else {
2013 if (crtc->config.has_pch_encoder) {
2014 /* if driving the PCH, we need FDI enabled */
2015 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2016 assert_fdi_tx_pll_enabled(dev_priv,
2017 (enum pipe) cpu_transcoder);
2018 }
2019 /* FIXME: assert CPU port conditions for SNB+ */
2020 }
2021
2022 reg = PIPECONF(cpu_transcoder);
2023 val = I915_READ(reg);
2024 if (val & PIPECONF_ENABLE) {
2025 WARN_ON(!(pipe == PIPE_A &&
2026 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2027 return;
2028 }
2029
2030 I915_WRITE(reg, val | PIPECONF_ENABLE);
2031 POSTING_READ(reg);
2032 }
2033
2034 /**
2035 * intel_disable_pipe - disable a pipe, asserting requirements
2036 * @dev_priv: i915 private structure
2037 * @pipe: pipe to disable
2038 *
2039 * Disable @pipe, making sure that various hardware specific requirements
2040 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2041 *
2042 * @pipe should be %PIPE_A or %PIPE_B.
2043 *
2044 * Will wait until the pipe has shut down before returning.
2045 */
2046 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2047 enum pipe pipe)
2048 {
2049 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2050 pipe);
2051 int reg;
2052 u32 val;
2053
2054 /*
2055 * Make sure planes won't keep trying to pump pixels to us,
2056 * or we might hang the display.
2057 */
2058 assert_planes_disabled(dev_priv, pipe);
2059 assert_cursor_disabled(dev_priv, pipe);
2060 assert_sprites_disabled(dev_priv, pipe);
2061
2062 /* Don't disable pipe A or pipe A PLLs if needed */
2063 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2064 return;
2065
2066 reg = PIPECONF(cpu_transcoder);
2067 val = I915_READ(reg);
2068 if ((val & PIPECONF_ENABLE) == 0)
2069 return;
2070
2071 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2072 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2073 }
2074
2075 /*
2076 * Plane regs are double buffered, going from enabled->disabled needs a
2077 * trigger in order to latch. The display address reg provides this.
2078 */
2079 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2080 enum plane plane)
2081 {
2082 struct drm_device *dev = dev_priv->dev;
2083 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2084
2085 I915_WRITE(reg, I915_READ(reg));
2086 POSTING_READ(reg);
2087 }
2088
2089 /**
2090 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2091 * @plane: plane to be enabled
2092 * @crtc: crtc for the plane
2093 *
2094 * Enable @plane on @crtc, making sure that the pipe is running first.
2095 */
2096 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2097 struct drm_crtc *crtc)
2098 {
2099 struct drm_device *dev = plane->dev;
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2102
2103 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2104 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2105
2106 if (intel_crtc->primary_enabled)
2107 return;
2108
2109 intel_crtc->primary_enabled = true;
2110
2111 dev_priv->display.update_primary_plane(crtc, plane->fb,
2112 crtc->x, crtc->y);
2113
2114 /*
2115 * BDW signals flip done immediately if the plane
2116 * is disabled, even if the plane enable is already
2117 * armed to occur at the next vblank :(
2118 */
2119 if (IS_BROADWELL(dev))
2120 intel_wait_for_vblank(dev, intel_crtc->pipe);
2121 }
2122
2123 /**
2124 * intel_disable_primary_hw_plane - disable the primary hardware plane
2125 * @plane: plane to be disabled
2126 * @crtc: crtc for the plane
2127 *
2128 * Disable @plane on @crtc, making sure that the pipe is running first.
2129 */
2130 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2132 {
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2138
2139 if (!intel_crtc->primary_enabled)
2140 return;
2141
2142 intel_crtc->primary_enabled = false;
2143
2144 dev_priv->display.update_primary_plane(crtc, plane->fb,
2145 crtc->x, crtc->y);
2146 }
2147
2148 static bool need_vtd_wa(struct drm_device *dev)
2149 {
2150 #ifdef CONFIG_INTEL_IOMMU
2151 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2152 return true;
2153 #endif
2154 return false;
2155 }
2156
2157 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2158 {
2159 int tile_height;
2160
2161 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2162 return ALIGN(height, tile_height);
2163 }
2164
2165 int
2166 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2167 struct drm_i915_gem_object *obj,
2168 struct intel_engine_cs *pipelined)
2169 {
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 u32 alignment;
2172 int ret;
2173
2174 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2175
2176 switch (obj->tiling_mode) {
2177 case I915_TILING_NONE:
2178 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2179 alignment = 128 * 1024;
2180 else if (INTEL_INFO(dev)->gen >= 4)
2181 alignment = 4 * 1024;
2182 else
2183 alignment = 64 * 1024;
2184 break;
2185 case I915_TILING_X:
2186 /* pin() will align the object as required by fence */
2187 alignment = 0;
2188 break;
2189 case I915_TILING_Y:
2190 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2191 return -EINVAL;
2192 default:
2193 BUG();
2194 }
2195
2196 /* Note that the w/a also requires 64 PTE of padding following the
2197 * bo. We currently fill all unused PTE with the shadow page and so
2198 * we should always have valid PTE following the scanout preventing
2199 * the VT-d warning.
2200 */
2201 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2202 alignment = 256 * 1024;
2203
2204 dev_priv->mm.interruptible = false;
2205 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2206 if (ret)
2207 goto err_interruptible;
2208
2209 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2210 * fence, whereas 965+ only requires a fence if using
2211 * framebuffer compression. For simplicity, we always install
2212 * a fence as the cost is not that onerous.
2213 */
2214 ret = i915_gem_object_get_fence(obj);
2215 if (ret)
2216 goto err_unpin;
2217
2218 i915_gem_object_pin_fence(obj);
2219
2220 dev_priv->mm.interruptible = true;
2221 return 0;
2222
2223 err_unpin:
2224 i915_gem_object_unpin_from_display_plane(obj);
2225 err_interruptible:
2226 dev_priv->mm.interruptible = true;
2227 return ret;
2228 }
2229
2230 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2231 {
2232 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2233
2234 i915_gem_object_unpin_fence(obj);
2235 i915_gem_object_unpin_from_display_plane(obj);
2236 }
2237
2238 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2239 * is assumed to be a power-of-two. */
2240 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2241 unsigned int tiling_mode,
2242 unsigned int cpp,
2243 unsigned int pitch)
2244 {
2245 if (tiling_mode != I915_TILING_NONE) {
2246 unsigned int tile_rows, tiles;
2247
2248 tile_rows = *y / 8;
2249 *y %= 8;
2250
2251 tiles = *x / (512/cpp);
2252 *x %= 512/cpp;
2253
2254 return tile_rows * pitch * 8 + tiles * 4096;
2255 } else {
2256 unsigned int offset;
2257
2258 offset = *y * pitch + *x * cpp;
2259 *y = 0;
2260 *x = (offset & 4095) / cpp;
2261 return offset & -4096;
2262 }
2263 }
2264
2265 int intel_format_to_fourcc(int format)
2266 {
2267 switch (format) {
2268 case DISPPLANE_8BPP:
2269 return DRM_FORMAT_C8;
2270 case DISPPLANE_BGRX555:
2271 return DRM_FORMAT_XRGB1555;
2272 case DISPPLANE_BGRX565:
2273 return DRM_FORMAT_RGB565;
2274 default:
2275 case DISPPLANE_BGRX888:
2276 return DRM_FORMAT_XRGB8888;
2277 case DISPPLANE_RGBX888:
2278 return DRM_FORMAT_XBGR8888;
2279 case DISPPLANE_BGRX101010:
2280 return DRM_FORMAT_XRGB2101010;
2281 case DISPPLANE_RGBX101010:
2282 return DRM_FORMAT_XBGR2101010;
2283 }
2284 }
2285
2286 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2287 struct intel_plane_config *plane_config)
2288 {
2289 struct drm_device *dev = crtc->base.dev;
2290 struct drm_i915_gem_object *obj = NULL;
2291 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2292 u32 base = plane_config->base;
2293
2294 if (plane_config->size == 0)
2295 return false;
2296
2297 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2298 plane_config->size);
2299 if (!obj)
2300 return false;
2301
2302 if (plane_config->tiled) {
2303 obj->tiling_mode = I915_TILING_X;
2304 obj->stride = crtc->base.primary->fb->pitches[0];
2305 }
2306
2307 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2308 mode_cmd.width = crtc->base.primary->fb->width;
2309 mode_cmd.height = crtc->base.primary->fb->height;
2310 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2311
2312 mutex_lock(&dev->struct_mutex);
2313
2314 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2315 &mode_cmd, obj)) {
2316 DRM_DEBUG_KMS("intel fb init failed\n");
2317 goto out_unref_obj;
2318 }
2319
2320 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2321 mutex_unlock(&dev->struct_mutex);
2322
2323 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2324 return true;
2325
2326 out_unref_obj:
2327 drm_gem_object_unreference(&obj->base);
2328 mutex_unlock(&dev->struct_mutex);
2329 return false;
2330 }
2331
2332 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2333 struct intel_plane_config *plane_config)
2334 {
2335 struct drm_device *dev = intel_crtc->base.dev;
2336 struct drm_crtc *c;
2337 struct intel_crtc *i;
2338 struct drm_i915_gem_object *obj;
2339
2340 if (!intel_crtc->base.primary->fb)
2341 return;
2342
2343 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2344 return;
2345
2346 kfree(intel_crtc->base.primary->fb);
2347 intel_crtc->base.primary->fb = NULL;
2348
2349 /*
2350 * Failed to alloc the obj, check to see if we should share
2351 * an fb with another CRTC instead
2352 */
2353 for_each_crtc(dev, c) {
2354 i = to_intel_crtc(c);
2355
2356 if (c == &intel_crtc->base)
2357 continue;
2358
2359 if (!i->active)
2360 continue;
2361
2362 obj = intel_fb_obj(c->primary->fb);
2363 if (obj == NULL)
2364 continue;
2365
2366 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2367 drm_framebuffer_reference(c->primary->fb);
2368 intel_crtc->base.primary->fb = c->primary->fb;
2369 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2370 break;
2371 }
2372 }
2373 }
2374
2375 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2376 struct drm_framebuffer *fb,
2377 int x, int y)
2378 {
2379 struct drm_device *dev = crtc->dev;
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2382 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2383 int plane = intel_crtc->plane;
2384 unsigned long linear_offset;
2385 u32 dspcntr;
2386 u32 reg = DSPCNTR(plane);
2387
2388 if (!intel_crtc->primary_enabled) {
2389 I915_WRITE(reg, 0);
2390 if (INTEL_INFO(dev)->gen >= 4)
2391 I915_WRITE(DSPSURF(plane), 0);
2392 else
2393 I915_WRITE(DSPADDR(plane), 0);
2394 POSTING_READ(reg);
2395 return;
2396 }
2397
2398 dspcntr = DISPPLANE_GAMMA_ENABLE;
2399
2400 dspcntr |= DISPLAY_PLANE_ENABLE;
2401
2402 if (INTEL_INFO(dev)->gen < 4) {
2403 if (intel_crtc->pipe == PIPE_B)
2404 dspcntr |= DISPPLANE_SEL_PIPE_B;
2405
2406 /* pipesrc and dspsize control the size that is scaled from,
2407 * which should always be the user's requested size.
2408 */
2409 I915_WRITE(DSPSIZE(plane),
2410 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2411 (intel_crtc->config.pipe_src_w - 1));
2412 I915_WRITE(DSPPOS(plane), 0);
2413 }
2414
2415 switch (fb->pixel_format) {
2416 case DRM_FORMAT_C8:
2417 dspcntr |= DISPPLANE_8BPP;
2418 break;
2419 case DRM_FORMAT_XRGB1555:
2420 case DRM_FORMAT_ARGB1555:
2421 dspcntr |= DISPPLANE_BGRX555;
2422 break;
2423 case DRM_FORMAT_RGB565:
2424 dspcntr |= DISPPLANE_BGRX565;
2425 break;
2426 case DRM_FORMAT_XRGB8888:
2427 case DRM_FORMAT_ARGB8888:
2428 dspcntr |= DISPPLANE_BGRX888;
2429 break;
2430 case DRM_FORMAT_XBGR8888:
2431 case DRM_FORMAT_ABGR8888:
2432 dspcntr |= DISPPLANE_RGBX888;
2433 break;
2434 case DRM_FORMAT_XRGB2101010:
2435 case DRM_FORMAT_ARGB2101010:
2436 dspcntr |= DISPPLANE_BGRX101010;
2437 break;
2438 case DRM_FORMAT_XBGR2101010:
2439 case DRM_FORMAT_ABGR2101010:
2440 dspcntr |= DISPPLANE_RGBX101010;
2441 break;
2442 default:
2443 BUG();
2444 }
2445
2446 if (INTEL_INFO(dev)->gen >= 4 &&
2447 obj->tiling_mode != I915_TILING_NONE)
2448 dspcntr |= DISPPLANE_TILED;
2449
2450 if (IS_G4X(dev))
2451 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2452
2453 I915_WRITE(reg, dspcntr);
2454
2455 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2456
2457 if (INTEL_INFO(dev)->gen >= 4) {
2458 intel_crtc->dspaddr_offset =
2459 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2460 fb->bits_per_pixel / 8,
2461 fb->pitches[0]);
2462 linear_offset -= intel_crtc->dspaddr_offset;
2463 } else {
2464 intel_crtc->dspaddr_offset = linear_offset;
2465 }
2466
2467 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2468 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2469 fb->pitches[0]);
2470 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2471 if (INTEL_INFO(dev)->gen >= 4) {
2472 I915_WRITE(DSPSURF(plane),
2473 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2474 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2475 I915_WRITE(DSPLINOFF(plane), linear_offset);
2476 } else
2477 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2478 POSTING_READ(reg);
2479 }
2480
2481 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2482 struct drm_framebuffer *fb,
2483 int x, int y)
2484 {
2485 struct drm_device *dev = crtc->dev;
2486 struct drm_i915_private *dev_priv = dev->dev_private;
2487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2488 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2489 int plane = intel_crtc->plane;
2490 unsigned long linear_offset;
2491 u32 dspcntr;
2492 u32 reg = DSPCNTR(plane);
2493
2494 if (!intel_crtc->primary_enabled) {
2495 I915_WRITE(reg, 0);
2496 I915_WRITE(DSPSURF(plane), 0);
2497 POSTING_READ(reg);
2498 return;
2499 }
2500
2501 dspcntr = DISPPLANE_GAMMA_ENABLE;
2502
2503 dspcntr |= DISPLAY_PLANE_ENABLE;
2504
2505 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2506 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2507
2508 switch (fb->pixel_format) {
2509 case DRM_FORMAT_C8:
2510 dspcntr |= DISPPLANE_8BPP;
2511 break;
2512 case DRM_FORMAT_RGB565:
2513 dspcntr |= DISPPLANE_BGRX565;
2514 break;
2515 case DRM_FORMAT_XRGB8888:
2516 case DRM_FORMAT_ARGB8888:
2517 dspcntr |= DISPPLANE_BGRX888;
2518 break;
2519 case DRM_FORMAT_XBGR8888:
2520 case DRM_FORMAT_ABGR8888:
2521 dspcntr |= DISPPLANE_RGBX888;
2522 break;
2523 case DRM_FORMAT_XRGB2101010:
2524 case DRM_FORMAT_ARGB2101010:
2525 dspcntr |= DISPPLANE_BGRX101010;
2526 break;
2527 case DRM_FORMAT_XBGR2101010:
2528 case DRM_FORMAT_ABGR2101010:
2529 dspcntr |= DISPPLANE_RGBX101010;
2530 break;
2531 default:
2532 BUG();
2533 }
2534
2535 if (obj->tiling_mode != I915_TILING_NONE)
2536 dspcntr |= DISPPLANE_TILED;
2537
2538 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2539 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2540
2541 I915_WRITE(reg, dspcntr);
2542
2543 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2544 intel_crtc->dspaddr_offset =
2545 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2546 fb->bits_per_pixel / 8,
2547 fb->pitches[0]);
2548 linear_offset -= intel_crtc->dspaddr_offset;
2549
2550 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2551 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2552 fb->pitches[0]);
2553 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2554 I915_WRITE(DSPSURF(plane),
2555 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2556 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2557 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2558 } else {
2559 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2560 I915_WRITE(DSPLINOFF(plane), linear_offset);
2561 }
2562 POSTING_READ(reg);
2563 }
2564
2565 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2566 static int
2567 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2568 int x, int y, enum mode_set_atomic state)
2569 {
2570 struct drm_device *dev = crtc->dev;
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572
2573 if (dev_priv->display.disable_fbc)
2574 dev_priv->display.disable_fbc(dev);
2575 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2576
2577 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2578
2579 return 0;
2580 }
2581
2582 void intel_display_handle_reset(struct drm_device *dev)
2583 {
2584 struct drm_i915_private *dev_priv = dev->dev_private;
2585 struct drm_crtc *crtc;
2586
2587 /*
2588 * Flips in the rings have been nuked by the reset,
2589 * so complete all pending flips so that user space
2590 * will get its events and not get stuck.
2591 *
2592 * Also update the base address of all primary
2593 * planes to the the last fb to make sure we're
2594 * showing the correct fb after a reset.
2595 *
2596 * Need to make two loops over the crtcs so that we
2597 * don't try to grab a crtc mutex before the
2598 * pending_flip_queue really got woken up.
2599 */
2600
2601 for_each_crtc(dev, crtc) {
2602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2603 enum plane plane = intel_crtc->plane;
2604
2605 intel_prepare_page_flip(dev, plane);
2606 intel_finish_page_flip_plane(dev, plane);
2607 }
2608
2609 for_each_crtc(dev, crtc) {
2610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2611
2612 drm_modeset_lock(&crtc->mutex, NULL);
2613 /*
2614 * FIXME: Once we have proper support for primary planes (and
2615 * disabling them without disabling the entire crtc) allow again
2616 * a NULL crtc->primary->fb.
2617 */
2618 if (intel_crtc->active && crtc->primary->fb)
2619 dev_priv->display.update_primary_plane(crtc,
2620 crtc->primary->fb,
2621 crtc->x,
2622 crtc->y);
2623 drm_modeset_unlock(&crtc->mutex);
2624 }
2625 }
2626
2627 static int
2628 intel_finish_fb(struct drm_framebuffer *old_fb)
2629 {
2630 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2631 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2632 bool was_interruptible = dev_priv->mm.interruptible;
2633 int ret;
2634
2635 /* Big Hammer, we also need to ensure that any pending
2636 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2637 * current scanout is retired before unpinning the old
2638 * framebuffer.
2639 *
2640 * This should only fail upon a hung GPU, in which case we
2641 * can safely continue.
2642 */
2643 dev_priv->mm.interruptible = false;
2644 ret = i915_gem_object_finish_gpu(obj);
2645 dev_priv->mm.interruptible = was_interruptible;
2646
2647 return ret;
2648 }
2649
2650 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2651 {
2652 struct drm_device *dev = crtc->dev;
2653 struct drm_i915_private *dev_priv = dev->dev_private;
2654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2655 unsigned long flags;
2656 bool pending;
2657
2658 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2659 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2660 return false;
2661
2662 spin_lock_irqsave(&dev->event_lock, flags);
2663 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2664 spin_unlock_irqrestore(&dev->event_lock, flags);
2665
2666 return pending;
2667 }
2668
2669 static int
2670 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2671 struct drm_framebuffer *fb)
2672 {
2673 struct drm_device *dev = crtc->dev;
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2676 enum pipe pipe = intel_crtc->pipe;
2677 struct drm_framebuffer *old_fb = crtc->primary->fb;
2678 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2679 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2680 int ret;
2681
2682 if (intel_crtc_has_pending_flip(crtc)) {
2683 DRM_ERROR("pipe is still busy with an old pageflip\n");
2684 return -EBUSY;
2685 }
2686
2687 /* no fb bound */
2688 if (!fb) {
2689 DRM_ERROR("No FB bound\n");
2690 return 0;
2691 }
2692
2693 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2694 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2695 plane_name(intel_crtc->plane),
2696 INTEL_INFO(dev)->num_pipes);
2697 return -EINVAL;
2698 }
2699
2700 mutex_lock(&dev->struct_mutex);
2701 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2702 if (ret == 0)
2703 i915_gem_track_fb(old_obj, obj,
2704 INTEL_FRONTBUFFER_PRIMARY(pipe));
2705 mutex_unlock(&dev->struct_mutex);
2706 if (ret != 0) {
2707 DRM_ERROR("pin & fence failed\n");
2708 return ret;
2709 }
2710
2711 /*
2712 * Update pipe size and adjust fitter if needed: the reason for this is
2713 * that in compute_mode_changes we check the native mode (not the pfit
2714 * mode) to see if we can flip rather than do a full mode set. In the
2715 * fastboot case, we'll flip, but if we don't update the pipesrc and
2716 * pfit state, we'll end up with a big fb scanned out into the wrong
2717 * sized surface.
2718 *
2719 * To fix this properly, we need to hoist the checks up into
2720 * compute_mode_changes (or above), check the actual pfit state and
2721 * whether the platform allows pfit disable with pipe active, and only
2722 * then update the pipesrc and pfit state, even on the flip path.
2723 */
2724 if (i915.fastboot) {
2725 const struct drm_display_mode *adjusted_mode =
2726 &intel_crtc->config.adjusted_mode;
2727
2728 I915_WRITE(PIPESRC(intel_crtc->pipe),
2729 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2730 (adjusted_mode->crtc_vdisplay - 1));
2731 if (!intel_crtc->config.pch_pfit.enabled &&
2732 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2733 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2734 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2735 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2736 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2737 }
2738 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2739 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2740 }
2741
2742 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2743
2744 if (intel_crtc->active)
2745 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2746
2747 crtc->primary->fb = fb;
2748 crtc->x = x;
2749 crtc->y = y;
2750
2751 if (old_fb) {
2752 if (intel_crtc->active && old_fb != fb)
2753 intel_wait_for_vblank(dev, intel_crtc->pipe);
2754 mutex_lock(&dev->struct_mutex);
2755 intel_unpin_fb_obj(old_obj);
2756 mutex_unlock(&dev->struct_mutex);
2757 }
2758
2759 mutex_lock(&dev->struct_mutex);
2760 intel_update_fbc(dev);
2761 mutex_unlock(&dev->struct_mutex);
2762
2763 return 0;
2764 }
2765
2766 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2767 {
2768 struct drm_device *dev = crtc->dev;
2769 struct drm_i915_private *dev_priv = dev->dev_private;
2770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2771 int pipe = intel_crtc->pipe;
2772 u32 reg, temp;
2773
2774 /* enable normal train */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if (IS_IVYBRIDGE(dev)) {
2778 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2779 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2780 } else {
2781 temp &= ~FDI_LINK_TRAIN_NONE;
2782 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2783 }
2784 I915_WRITE(reg, temp);
2785
2786 reg = FDI_RX_CTL(pipe);
2787 temp = I915_READ(reg);
2788 if (HAS_PCH_CPT(dev)) {
2789 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2790 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2791 } else {
2792 temp &= ~FDI_LINK_TRAIN_NONE;
2793 temp |= FDI_LINK_TRAIN_NONE;
2794 }
2795 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2796
2797 /* wait one idle pattern time */
2798 POSTING_READ(reg);
2799 udelay(1000);
2800
2801 /* IVB wants error correction enabled */
2802 if (IS_IVYBRIDGE(dev))
2803 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2804 FDI_FE_ERRC_ENABLE);
2805 }
2806
2807 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2808 {
2809 return crtc->base.enabled && crtc->active &&
2810 crtc->config.has_pch_encoder;
2811 }
2812
2813 static void ivb_modeset_global_resources(struct drm_device *dev)
2814 {
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *pipe_B_crtc =
2817 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2818 struct intel_crtc *pipe_C_crtc =
2819 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2820 uint32_t temp;
2821
2822 /*
2823 * When everything is off disable fdi C so that we could enable fdi B
2824 * with all lanes. Note that we don't care about enabled pipes without
2825 * an enabled pch encoder.
2826 */
2827 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2828 !pipe_has_enabled_pch(pipe_C_crtc)) {
2829 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2830 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2831
2832 temp = I915_READ(SOUTH_CHICKEN1);
2833 temp &= ~FDI_BC_BIFURCATION_SELECT;
2834 DRM_DEBUG_KMS("disabling fdi C rx\n");
2835 I915_WRITE(SOUTH_CHICKEN1, temp);
2836 }
2837 }
2838
2839 /* The FDI link training functions for ILK/Ibexpeak. */
2840 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2841 {
2842 struct drm_device *dev = crtc->dev;
2843 struct drm_i915_private *dev_priv = dev->dev_private;
2844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2845 int pipe = intel_crtc->pipe;
2846 u32 reg, temp, tries;
2847
2848 /* FDI needs bits from pipe first */
2849 assert_pipe_enabled(dev_priv, pipe);
2850
2851 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2852 for train result */
2853 reg = FDI_RX_IMR(pipe);
2854 temp = I915_READ(reg);
2855 temp &= ~FDI_RX_SYMBOL_LOCK;
2856 temp &= ~FDI_RX_BIT_LOCK;
2857 I915_WRITE(reg, temp);
2858 I915_READ(reg);
2859 udelay(150);
2860
2861 /* enable CPU FDI TX and PCH FDI RX */
2862 reg = FDI_TX_CTL(pipe);
2863 temp = I915_READ(reg);
2864 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2865 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2866 temp &= ~FDI_LINK_TRAIN_NONE;
2867 temp |= FDI_LINK_TRAIN_PATTERN_1;
2868 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2869
2870 reg = FDI_RX_CTL(pipe);
2871 temp = I915_READ(reg);
2872 temp &= ~FDI_LINK_TRAIN_NONE;
2873 temp |= FDI_LINK_TRAIN_PATTERN_1;
2874 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2875
2876 POSTING_READ(reg);
2877 udelay(150);
2878
2879 /* Ironlake workaround, enable clock pointer after FDI enable*/
2880 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2881 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2882 FDI_RX_PHASE_SYNC_POINTER_EN);
2883
2884 reg = FDI_RX_IIR(pipe);
2885 for (tries = 0; tries < 5; tries++) {
2886 temp = I915_READ(reg);
2887 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2888
2889 if ((temp & FDI_RX_BIT_LOCK)) {
2890 DRM_DEBUG_KMS("FDI train 1 done.\n");
2891 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2892 break;
2893 }
2894 }
2895 if (tries == 5)
2896 DRM_ERROR("FDI train 1 fail!\n");
2897
2898 /* Train 2 */
2899 reg = FDI_TX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 temp &= ~FDI_LINK_TRAIN_NONE;
2902 temp |= FDI_LINK_TRAIN_PATTERN_2;
2903 I915_WRITE(reg, temp);
2904
2905 reg = FDI_RX_CTL(pipe);
2906 temp = I915_READ(reg);
2907 temp &= ~FDI_LINK_TRAIN_NONE;
2908 temp |= FDI_LINK_TRAIN_PATTERN_2;
2909 I915_WRITE(reg, temp);
2910
2911 POSTING_READ(reg);
2912 udelay(150);
2913
2914 reg = FDI_RX_IIR(pipe);
2915 for (tries = 0; tries < 5; tries++) {
2916 temp = I915_READ(reg);
2917 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2918
2919 if (temp & FDI_RX_SYMBOL_LOCK) {
2920 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2921 DRM_DEBUG_KMS("FDI train 2 done.\n");
2922 break;
2923 }
2924 }
2925 if (tries == 5)
2926 DRM_ERROR("FDI train 2 fail!\n");
2927
2928 DRM_DEBUG_KMS("FDI train done\n");
2929
2930 }
2931
2932 static const int snb_b_fdi_train_param[] = {
2933 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2934 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2935 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2936 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2937 };
2938
2939 /* The FDI link training functions for SNB/Cougarpoint. */
2940 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2941 {
2942 struct drm_device *dev = crtc->dev;
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2945 int pipe = intel_crtc->pipe;
2946 u32 reg, temp, i, retry;
2947
2948 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2949 for train result */
2950 reg = FDI_RX_IMR(pipe);
2951 temp = I915_READ(reg);
2952 temp &= ~FDI_RX_SYMBOL_LOCK;
2953 temp &= ~FDI_RX_BIT_LOCK;
2954 I915_WRITE(reg, temp);
2955
2956 POSTING_READ(reg);
2957 udelay(150);
2958
2959 /* enable CPU FDI TX and PCH FDI RX */
2960 reg = FDI_TX_CTL(pipe);
2961 temp = I915_READ(reg);
2962 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2963 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2964 temp &= ~FDI_LINK_TRAIN_NONE;
2965 temp |= FDI_LINK_TRAIN_PATTERN_1;
2966 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2967 /* SNB-B */
2968 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2969 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2970
2971 I915_WRITE(FDI_RX_MISC(pipe),
2972 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2973
2974 reg = FDI_RX_CTL(pipe);
2975 temp = I915_READ(reg);
2976 if (HAS_PCH_CPT(dev)) {
2977 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2978 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2979 } else {
2980 temp &= ~FDI_LINK_TRAIN_NONE;
2981 temp |= FDI_LINK_TRAIN_PATTERN_1;
2982 }
2983 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2984
2985 POSTING_READ(reg);
2986 udelay(150);
2987
2988 for (i = 0; i < 4; i++) {
2989 reg = FDI_TX_CTL(pipe);
2990 temp = I915_READ(reg);
2991 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2992 temp |= snb_b_fdi_train_param[i];
2993 I915_WRITE(reg, temp);
2994
2995 POSTING_READ(reg);
2996 udelay(500);
2997
2998 for (retry = 0; retry < 5; retry++) {
2999 reg = FDI_RX_IIR(pipe);
3000 temp = I915_READ(reg);
3001 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3002 if (temp & FDI_RX_BIT_LOCK) {
3003 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3004 DRM_DEBUG_KMS("FDI train 1 done.\n");
3005 break;
3006 }
3007 udelay(50);
3008 }
3009 if (retry < 5)
3010 break;
3011 }
3012 if (i == 4)
3013 DRM_ERROR("FDI train 1 fail!\n");
3014
3015 /* Train 2 */
3016 reg = FDI_TX_CTL(pipe);
3017 temp = I915_READ(reg);
3018 temp &= ~FDI_LINK_TRAIN_NONE;
3019 temp |= FDI_LINK_TRAIN_PATTERN_2;
3020 if (IS_GEN6(dev)) {
3021 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3022 /* SNB-B */
3023 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3024 }
3025 I915_WRITE(reg, temp);
3026
3027 reg = FDI_RX_CTL(pipe);
3028 temp = I915_READ(reg);
3029 if (HAS_PCH_CPT(dev)) {
3030 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3031 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3032 } else {
3033 temp &= ~FDI_LINK_TRAIN_NONE;
3034 temp |= FDI_LINK_TRAIN_PATTERN_2;
3035 }
3036 I915_WRITE(reg, temp);
3037
3038 POSTING_READ(reg);
3039 udelay(150);
3040
3041 for (i = 0; i < 4; i++) {
3042 reg = FDI_TX_CTL(pipe);
3043 temp = I915_READ(reg);
3044 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3045 temp |= snb_b_fdi_train_param[i];
3046 I915_WRITE(reg, temp);
3047
3048 POSTING_READ(reg);
3049 udelay(500);
3050
3051 for (retry = 0; retry < 5; retry++) {
3052 reg = FDI_RX_IIR(pipe);
3053 temp = I915_READ(reg);
3054 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3055 if (temp & FDI_RX_SYMBOL_LOCK) {
3056 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3057 DRM_DEBUG_KMS("FDI train 2 done.\n");
3058 break;
3059 }
3060 udelay(50);
3061 }
3062 if (retry < 5)
3063 break;
3064 }
3065 if (i == 4)
3066 DRM_ERROR("FDI train 2 fail!\n");
3067
3068 DRM_DEBUG_KMS("FDI train done.\n");
3069 }
3070
3071 /* Manual link training for Ivy Bridge A0 parts */
3072 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3073 {
3074 struct drm_device *dev = crtc->dev;
3075 struct drm_i915_private *dev_priv = dev->dev_private;
3076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3077 int pipe = intel_crtc->pipe;
3078 u32 reg, temp, i, j;
3079
3080 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3081 for train result */
3082 reg = FDI_RX_IMR(pipe);
3083 temp = I915_READ(reg);
3084 temp &= ~FDI_RX_SYMBOL_LOCK;
3085 temp &= ~FDI_RX_BIT_LOCK;
3086 I915_WRITE(reg, temp);
3087
3088 POSTING_READ(reg);
3089 udelay(150);
3090
3091 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3092 I915_READ(FDI_RX_IIR(pipe)));
3093
3094 /* Try each vswing and preemphasis setting twice before moving on */
3095 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3096 /* disable first in case we need to retry */
3097 reg = FDI_TX_CTL(pipe);
3098 temp = I915_READ(reg);
3099 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3100 temp &= ~FDI_TX_ENABLE;
3101 I915_WRITE(reg, temp);
3102
3103 reg = FDI_RX_CTL(pipe);
3104 temp = I915_READ(reg);
3105 temp &= ~FDI_LINK_TRAIN_AUTO;
3106 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3107 temp &= ~FDI_RX_ENABLE;
3108 I915_WRITE(reg, temp);
3109
3110 /* enable CPU FDI TX and PCH FDI RX */
3111 reg = FDI_TX_CTL(pipe);
3112 temp = I915_READ(reg);
3113 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3114 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3115 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3116 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3117 temp |= snb_b_fdi_train_param[j/2];
3118 temp |= FDI_COMPOSITE_SYNC;
3119 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3120
3121 I915_WRITE(FDI_RX_MISC(pipe),
3122 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3123
3124 reg = FDI_RX_CTL(pipe);
3125 temp = I915_READ(reg);
3126 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3127 temp |= FDI_COMPOSITE_SYNC;
3128 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3129
3130 POSTING_READ(reg);
3131 udelay(1); /* should be 0.5us */
3132
3133 for (i = 0; i < 4; i++) {
3134 reg = FDI_RX_IIR(pipe);
3135 temp = I915_READ(reg);
3136 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3137
3138 if (temp & FDI_RX_BIT_LOCK ||
3139 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3140 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3141 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3142 i);
3143 break;
3144 }
3145 udelay(1); /* should be 0.5us */
3146 }
3147 if (i == 4) {
3148 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3149 continue;
3150 }
3151
3152 /* Train 2 */
3153 reg = FDI_TX_CTL(pipe);
3154 temp = I915_READ(reg);
3155 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3156 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3157 I915_WRITE(reg, temp);
3158
3159 reg = FDI_RX_CTL(pipe);
3160 temp = I915_READ(reg);
3161 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3162 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3163 I915_WRITE(reg, temp);
3164
3165 POSTING_READ(reg);
3166 udelay(2); /* should be 1.5us */
3167
3168 for (i = 0; i < 4; i++) {
3169 reg = FDI_RX_IIR(pipe);
3170 temp = I915_READ(reg);
3171 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3172
3173 if (temp & FDI_RX_SYMBOL_LOCK ||
3174 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3175 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3176 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3177 i);
3178 goto train_done;
3179 }
3180 udelay(2); /* should be 1.5us */
3181 }
3182 if (i == 4)
3183 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3184 }
3185
3186 train_done:
3187 DRM_DEBUG_KMS("FDI train done.\n");
3188 }
3189
3190 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3191 {
3192 struct drm_device *dev = intel_crtc->base.dev;
3193 struct drm_i915_private *dev_priv = dev->dev_private;
3194 int pipe = intel_crtc->pipe;
3195 u32 reg, temp;
3196
3197
3198 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3199 reg = FDI_RX_CTL(pipe);
3200 temp = I915_READ(reg);
3201 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3202 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3203 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3204 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3205
3206 POSTING_READ(reg);
3207 udelay(200);
3208
3209 /* Switch from Rawclk to PCDclk */
3210 temp = I915_READ(reg);
3211 I915_WRITE(reg, temp | FDI_PCDCLK);
3212
3213 POSTING_READ(reg);
3214 udelay(200);
3215
3216 /* Enable CPU FDI TX PLL, always on for Ironlake */
3217 reg = FDI_TX_CTL(pipe);
3218 temp = I915_READ(reg);
3219 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3220 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3221
3222 POSTING_READ(reg);
3223 udelay(100);
3224 }
3225 }
3226
3227 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3228 {
3229 struct drm_device *dev = intel_crtc->base.dev;
3230 struct drm_i915_private *dev_priv = dev->dev_private;
3231 int pipe = intel_crtc->pipe;
3232 u32 reg, temp;
3233
3234 /* Switch from PCDclk to Rawclk */
3235 reg = FDI_RX_CTL(pipe);
3236 temp = I915_READ(reg);
3237 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3238
3239 /* Disable CPU FDI TX PLL */
3240 reg = FDI_TX_CTL(pipe);
3241 temp = I915_READ(reg);
3242 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3243
3244 POSTING_READ(reg);
3245 udelay(100);
3246
3247 reg = FDI_RX_CTL(pipe);
3248 temp = I915_READ(reg);
3249 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3250
3251 /* Wait for the clocks to turn off. */
3252 POSTING_READ(reg);
3253 udelay(100);
3254 }
3255
3256 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3257 {
3258 struct drm_device *dev = crtc->dev;
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3261 int pipe = intel_crtc->pipe;
3262 u32 reg, temp;
3263
3264 /* disable CPU FDI tx and PCH FDI rx */
3265 reg = FDI_TX_CTL(pipe);
3266 temp = I915_READ(reg);
3267 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3268 POSTING_READ(reg);
3269
3270 reg = FDI_RX_CTL(pipe);
3271 temp = I915_READ(reg);
3272 temp &= ~(0x7 << 16);
3273 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3274 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3275
3276 POSTING_READ(reg);
3277 udelay(100);
3278
3279 /* Ironlake workaround, disable clock pointer after downing FDI */
3280 if (HAS_PCH_IBX(dev))
3281 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3282
3283 /* still set train pattern 1 */
3284 reg = FDI_TX_CTL(pipe);
3285 temp = I915_READ(reg);
3286 temp &= ~FDI_LINK_TRAIN_NONE;
3287 temp |= FDI_LINK_TRAIN_PATTERN_1;
3288 I915_WRITE(reg, temp);
3289
3290 reg = FDI_RX_CTL(pipe);
3291 temp = I915_READ(reg);
3292 if (HAS_PCH_CPT(dev)) {
3293 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3294 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3295 } else {
3296 temp &= ~FDI_LINK_TRAIN_NONE;
3297 temp |= FDI_LINK_TRAIN_PATTERN_1;
3298 }
3299 /* BPC in FDI rx is consistent with that in PIPECONF */
3300 temp &= ~(0x07 << 16);
3301 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3302 I915_WRITE(reg, temp);
3303
3304 POSTING_READ(reg);
3305 udelay(100);
3306 }
3307
3308 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3309 {
3310 struct intel_crtc *crtc;
3311
3312 /* Note that we don't need to be called with mode_config.lock here
3313 * as our list of CRTC objects is static for the lifetime of the
3314 * device and so cannot disappear as we iterate. Similarly, we can
3315 * happily treat the predicates as racy, atomic checks as userspace
3316 * cannot claim and pin a new fb without at least acquring the
3317 * struct_mutex and so serialising with us.
3318 */
3319 for_each_intel_crtc(dev, crtc) {
3320 if (atomic_read(&crtc->unpin_work_count) == 0)
3321 continue;
3322
3323 if (crtc->unpin_work)
3324 intel_wait_for_vblank(dev, crtc->pipe);
3325
3326 return true;
3327 }
3328
3329 return false;
3330 }
3331
3332 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3333 {
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336
3337 if (crtc->primary->fb == NULL)
3338 return;
3339
3340 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3341
3342 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3343 !intel_crtc_has_pending_flip(crtc),
3344 60*HZ) == 0);
3345
3346 mutex_lock(&dev->struct_mutex);
3347 intel_finish_fb(crtc->primary->fb);
3348 mutex_unlock(&dev->struct_mutex);
3349 }
3350
3351 /* Program iCLKIP clock to the desired frequency */
3352 static void lpt_program_iclkip(struct drm_crtc *crtc)
3353 {
3354 struct drm_device *dev = crtc->dev;
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3357 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3358 u32 temp;
3359
3360 mutex_lock(&dev_priv->dpio_lock);
3361
3362 /* It is necessary to ungate the pixclk gate prior to programming
3363 * the divisors, and gate it back when it is done.
3364 */
3365 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3366
3367 /* Disable SSCCTL */
3368 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3369 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3370 SBI_SSCCTL_DISABLE,
3371 SBI_ICLK);
3372
3373 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3374 if (clock == 20000) {
3375 auxdiv = 1;
3376 divsel = 0x41;
3377 phaseinc = 0x20;
3378 } else {
3379 /* The iCLK virtual clock root frequency is in MHz,
3380 * but the adjusted_mode->crtc_clock in in KHz. To get the
3381 * divisors, it is necessary to divide one by another, so we
3382 * convert the virtual clock precision to KHz here for higher
3383 * precision.
3384 */
3385 u32 iclk_virtual_root_freq = 172800 * 1000;
3386 u32 iclk_pi_range = 64;
3387 u32 desired_divisor, msb_divisor_value, pi_value;
3388
3389 desired_divisor = (iclk_virtual_root_freq / clock);
3390 msb_divisor_value = desired_divisor / iclk_pi_range;
3391 pi_value = desired_divisor % iclk_pi_range;
3392
3393 auxdiv = 0;
3394 divsel = msb_divisor_value - 2;
3395 phaseinc = pi_value;
3396 }
3397
3398 /* This should not happen with any sane values */
3399 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3400 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3401 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3402 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3403
3404 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3405 clock,
3406 auxdiv,
3407 divsel,
3408 phasedir,
3409 phaseinc);
3410
3411 /* Program SSCDIVINTPHASE6 */
3412 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3413 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3414 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3415 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3416 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3417 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3418 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3419 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3420
3421 /* Program SSCAUXDIV */
3422 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3423 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3424 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3425 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3426
3427 /* Enable modulator and associated divider */
3428 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3429 temp &= ~SBI_SSCCTL_DISABLE;
3430 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3431
3432 /* Wait for initialization time */
3433 udelay(24);
3434
3435 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3436
3437 mutex_unlock(&dev_priv->dpio_lock);
3438 }
3439
3440 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3441 enum pipe pch_transcoder)
3442 {
3443 struct drm_device *dev = crtc->base.dev;
3444 struct drm_i915_private *dev_priv = dev->dev_private;
3445 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3446
3447 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3448 I915_READ(HTOTAL(cpu_transcoder)));
3449 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3450 I915_READ(HBLANK(cpu_transcoder)));
3451 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3452 I915_READ(HSYNC(cpu_transcoder)));
3453
3454 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3455 I915_READ(VTOTAL(cpu_transcoder)));
3456 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3457 I915_READ(VBLANK(cpu_transcoder)));
3458 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3459 I915_READ(VSYNC(cpu_transcoder)));
3460 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3461 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3462 }
3463
3464 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3465 {
3466 struct drm_i915_private *dev_priv = dev->dev_private;
3467 uint32_t temp;
3468
3469 temp = I915_READ(SOUTH_CHICKEN1);
3470 if (temp & FDI_BC_BIFURCATION_SELECT)
3471 return;
3472
3473 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3474 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3475
3476 temp |= FDI_BC_BIFURCATION_SELECT;
3477 DRM_DEBUG_KMS("enabling fdi C rx\n");
3478 I915_WRITE(SOUTH_CHICKEN1, temp);
3479 POSTING_READ(SOUTH_CHICKEN1);
3480 }
3481
3482 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3483 {
3484 struct drm_device *dev = intel_crtc->base.dev;
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486
3487 switch (intel_crtc->pipe) {
3488 case PIPE_A:
3489 break;
3490 case PIPE_B:
3491 if (intel_crtc->config.fdi_lanes > 2)
3492 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3493 else
3494 cpt_enable_fdi_bc_bifurcation(dev);
3495
3496 break;
3497 case PIPE_C:
3498 cpt_enable_fdi_bc_bifurcation(dev);
3499
3500 break;
3501 default:
3502 BUG();
3503 }
3504 }
3505
3506 /*
3507 * Enable PCH resources required for PCH ports:
3508 * - PCH PLLs
3509 * - FDI training & RX/TX
3510 * - update transcoder timings
3511 * - DP transcoding bits
3512 * - transcoder
3513 */
3514 static void ironlake_pch_enable(struct drm_crtc *crtc)
3515 {
3516 struct drm_device *dev = crtc->dev;
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3519 int pipe = intel_crtc->pipe;
3520 u32 reg, temp;
3521
3522 assert_pch_transcoder_disabled(dev_priv, pipe);
3523
3524 if (IS_IVYBRIDGE(dev))
3525 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3526
3527 /* Write the TU size bits before fdi link training, so that error
3528 * detection works. */
3529 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3530 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3531
3532 /* For PCH output, training FDI link */
3533 dev_priv->display.fdi_link_train(crtc);
3534
3535 /* We need to program the right clock selection before writing the pixel
3536 * mutliplier into the DPLL. */
3537 if (HAS_PCH_CPT(dev)) {
3538 u32 sel;
3539
3540 temp = I915_READ(PCH_DPLL_SEL);
3541 temp |= TRANS_DPLL_ENABLE(pipe);
3542 sel = TRANS_DPLLB_SEL(pipe);
3543 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3544 temp |= sel;
3545 else
3546 temp &= ~sel;
3547 I915_WRITE(PCH_DPLL_SEL, temp);
3548 }
3549
3550 /* XXX: pch pll's can be enabled any time before we enable the PCH
3551 * transcoder, and we actually should do this to not upset any PCH
3552 * transcoder that already use the clock when we share it.
3553 *
3554 * Note that enable_shared_dpll tries to do the right thing, but
3555 * get_shared_dpll unconditionally resets the pll - we need that to have
3556 * the right LVDS enable sequence. */
3557 intel_enable_shared_dpll(intel_crtc);
3558
3559 /* set transcoder timing, panel must allow it */
3560 assert_panel_unlocked(dev_priv, pipe);
3561 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3562
3563 intel_fdi_normal_train(crtc);
3564
3565 /* For PCH DP, enable TRANS_DP_CTL */
3566 if (HAS_PCH_CPT(dev) &&
3567 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3568 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3569 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3570 reg = TRANS_DP_CTL(pipe);
3571 temp = I915_READ(reg);
3572 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3573 TRANS_DP_SYNC_MASK |
3574 TRANS_DP_BPC_MASK);
3575 temp |= (TRANS_DP_OUTPUT_ENABLE |
3576 TRANS_DP_ENH_FRAMING);
3577 temp |= bpc << 9; /* same format but at 11:9 */
3578
3579 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3580 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3581 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3582 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3583
3584 switch (intel_trans_dp_port_sel(crtc)) {
3585 case PCH_DP_B:
3586 temp |= TRANS_DP_PORT_SEL_B;
3587 break;
3588 case PCH_DP_C:
3589 temp |= TRANS_DP_PORT_SEL_C;
3590 break;
3591 case PCH_DP_D:
3592 temp |= TRANS_DP_PORT_SEL_D;
3593 break;
3594 default:
3595 BUG();
3596 }
3597
3598 I915_WRITE(reg, temp);
3599 }
3600
3601 ironlake_enable_pch_transcoder(dev_priv, pipe);
3602 }
3603
3604 static void lpt_pch_enable(struct drm_crtc *crtc)
3605 {
3606 struct drm_device *dev = crtc->dev;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3610
3611 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3612
3613 lpt_program_iclkip(crtc);
3614
3615 /* Set transcoder timing. */
3616 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3617
3618 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3619 }
3620
3621 void intel_put_shared_dpll(struct intel_crtc *crtc)
3622 {
3623 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3624
3625 if (pll == NULL)
3626 return;
3627
3628 if (pll->refcount == 0) {
3629 WARN(1, "bad %s refcount\n", pll->name);
3630 return;
3631 }
3632
3633 if (--pll->refcount == 0) {
3634 WARN_ON(pll->on);
3635 WARN_ON(pll->active);
3636 }
3637
3638 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3639 }
3640
3641 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3642 {
3643 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3644 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3645 enum intel_dpll_id i;
3646
3647 if (pll) {
3648 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3649 crtc->base.base.id, pll->name);
3650 intel_put_shared_dpll(crtc);
3651 }
3652
3653 if (HAS_PCH_IBX(dev_priv->dev)) {
3654 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3655 i = (enum intel_dpll_id) crtc->pipe;
3656 pll = &dev_priv->shared_dplls[i];
3657
3658 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3659 crtc->base.base.id, pll->name);
3660
3661 WARN_ON(pll->refcount);
3662
3663 goto found;
3664 }
3665
3666 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3667 pll = &dev_priv->shared_dplls[i];
3668
3669 /* Only want to check enabled timings first */
3670 if (pll->refcount == 0)
3671 continue;
3672
3673 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3674 sizeof(pll->hw_state)) == 0) {
3675 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3676 crtc->base.base.id,
3677 pll->name, pll->refcount, pll->active);
3678
3679 goto found;
3680 }
3681 }
3682
3683 /* Ok no matching timings, maybe there's a free one? */
3684 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3685 pll = &dev_priv->shared_dplls[i];
3686 if (pll->refcount == 0) {
3687 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3688 crtc->base.base.id, pll->name);
3689 goto found;
3690 }
3691 }
3692
3693 return NULL;
3694
3695 found:
3696 if (pll->refcount == 0)
3697 pll->hw_state = crtc->config.dpll_hw_state;
3698
3699 crtc->config.shared_dpll = i;
3700 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3701 pipe_name(crtc->pipe));
3702
3703 pll->refcount++;
3704
3705 return pll;
3706 }
3707
3708 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3709 {
3710 struct drm_i915_private *dev_priv = dev->dev_private;
3711 int dslreg = PIPEDSL(pipe);
3712 u32 temp;
3713
3714 temp = I915_READ(dslreg);
3715 udelay(500);
3716 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3717 if (wait_for(I915_READ(dslreg) != temp, 5))
3718 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3719 }
3720 }
3721
3722 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3723 {
3724 struct drm_device *dev = crtc->base.dev;
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 int pipe = crtc->pipe;
3727
3728 if (crtc->config.pch_pfit.enabled) {
3729 /* Force use of hard-coded filter coefficients
3730 * as some pre-programmed values are broken,
3731 * e.g. x201.
3732 */
3733 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3734 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3735 PF_PIPE_SEL_IVB(pipe));
3736 else
3737 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3738 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3739 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3740 }
3741 }
3742
3743 static void intel_enable_planes(struct drm_crtc *crtc)
3744 {
3745 struct drm_device *dev = crtc->dev;
3746 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3747 struct drm_plane *plane;
3748 struct intel_plane *intel_plane;
3749
3750 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3751 intel_plane = to_intel_plane(plane);
3752 if (intel_plane->pipe == pipe)
3753 intel_plane_restore(&intel_plane->base);
3754 }
3755 }
3756
3757 static void intel_disable_planes(struct drm_crtc *crtc)
3758 {
3759 struct drm_device *dev = crtc->dev;
3760 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3761 struct drm_plane *plane;
3762 struct intel_plane *intel_plane;
3763
3764 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3765 intel_plane = to_intel_plane(plane);
3766 if (intel_plane->pipe == pipe)
3767 intel_plane_disable(&intel_plane->base);
3768 }
3769 }
3770
3771 void hsw_enable_ips(struct intel_crtc *crtc)
3772 {
3773 struct drm_device *dev = crtc->base.dev;
3774 struct drm_i915_private *dev_priv = dev->dev_private;
3775
3776 if (!crtc->config.ips_enabled)
3777 return;
3778
3779 /* We can only enable IPS after we enable a plane and wait for a vblank */
3780 intel_wait_for_vblank(dev, crtc->pipe);
3781
3782 assert_plane_enabled(dev_priv, crtc->plane);
3783 if (IS_BROADWELL(dev)) {
3784 mutex_lock(&dev_priv->rps.hw_lock);
3785 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3786 mutex_unlock(&dev_priv->rps.hw_lock);
3787 /* Quoting Art Runyan: "its not safe to expect any particular
3788 * value in IPS_CTL bit 31 after enabling IPS through the
3789 * mailbox." Moreover, the mailbox may return a bogus state,
3790 * so we need to just enable it and continue on.
3791 */
3792 } else {
3793 I915_WRITE(IPS_CTL, IPS_ENABLE);
3794 /* The bit only becomes 1 in the next vblank, so this wait here
3795 * is essentially intel_wait_for_vblank. If we don't have this
3796 * and don't wait for vblanks until the end of crtc_enable, then
3797 * the HW state readout code will complain that the expected
3798 * IPS_CTL value is not the one we read. */
3799 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3800 DRM_ERROR("Timed out waiting for IPS enable\n");
3801 }
3802 }
3803
3804 void hsw_disable_ips(struct intel_crtc *crtc)
3805 {
3806 struct drm_device *dev = crtc->base.dev;
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808
3809 if (!crtc->config.ips_enabled)
3810 return;
3811
3812 assert_plane_enabled(dev_priv, crtc->plane);
3813 if (IS_BROADWELL(dev)) {
3814 mutex_lock(&dev_priv->rps.hw_lock);
3815 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3816 mutex_unlock(&dev_priv->rps.hw_lock);
3817 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3818 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3819 DRM_ERROR("Timed out waiting for IPS disable\n");
3820 } else {
3821 I915_WRITE(IPS_CTL, 0);
3822 POSTING_READ(IPS_CTL);
3823 }
3824
3825 /* We need to wait for a vblank before we can disable the plane. */
3826 intel_wait_for_vblank(dev, crtc->pipe);
3827 }
3828
3829 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3830 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3831 {
3832 struct drm_device *dev = crtc->dev;
3833 struct drm_i915_private *dev_priv = dev->dev_private;
3834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3835 enum pipe pipe = intel_crtc->pipe;
3836 int palreg = PALETTE(pipe);
3837 int i;
3838 bool reenable_ips = false;
3839
3840 /* The clocks have to be on to load the palette. */
3841 if (!crtc->enabled || !intel_crtc->active)
3842 return;
3843
3844 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3845 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3846 assert_dsi_pll_enabled(dev_priv);
3847 else
3848 assert_pll_enabled(dev_priv, pipe);
3849 }
3850
3851 /* use legacy palette for Ironlake */
3852 if (!HAS_GMCH_DISPLAY(dev))
3853 palreg = LGC_PALETTE(pipe);
3854
3855 /* Workaround : Do not read or write the pipe palette/gamma data while
3856 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3857 */
3858 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3859 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3860 GAMMA_MODE_MODE_SPLIT)) {
3861 hsw_disable_ips(intel_crtc);
3862 reenable_ips = true;
3863 }
3864
3865 for (i = 0; i < 256; i++) {
3866 I915_WRITE(palreg + 4 * i,
3867 (intel_crtc->lut_r[i] << 16) |
3868 (intel_crtc->lut_g[i] << 8) |
3869 intel_crtc->lut_b[i]);
3870 }
3871
3872 if (reenable_ips)
3873 hsw_enable_ips(intel_crtc);
3874 }
3875
3876 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3877 {
3878 if (!enable && intel_crtc->overlay) {
3879 struct drm_device *dev = intel_crtc->base.dev;
3880 struct drm_i915_private *dev_priv = dev->dev_private;
3881
3882 mutex_lock(&dev->struct_mutex);
3883 dev_priv->mm.interruptible = false;
3884 (void) intel_overlay_switch_off(intel_crtc->overlay);
3885 dev_priv->mm.interruptible = true;
3886 mutex_unlock(&dev->struct_mutex);
3887 }
3888
3889 /* Let userspace switch the overlay on again. In most cases userspace
3890 * has to recompute where to put it anyway.
3891 */
3892 }
3893
3894 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3895 {
3896 struct drm_device *dev = crtc->dev;
3897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3898 int pipe = intel_crtc->pipe;
3899
3900 assert_vblank_disabled(crtc);
3901
3902 drm_vblank_on(dev, pipe);
3903
3904 intel_enable_primary_hw_plane(crtc->primary, crtc);
3905 intel_enable_planes(crtc);
3906 intel_crtc_update_cursor(crtc, true);
3907 intel_crtc_dpms_overlay(intel_crtc, true);
3908
3909 hsw_enable_ips(intel_crtc);
3910
3911 mutex_lock(&dev->struct_mutex);
3912 intel_update_fbc(dev);
3913 mutex_unlock(&dev->struct_mutex);
3914
3915 /*
3916 * FIXME: Once we grow proper nuclear flip support out of this we need
3917 * to compute the mask of flip planes precisely. For the time being
3918 * consider this a flip from a NULL plane.
3919 */
3920 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3921 }
3922
3923 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3924 {
3925 struct drm_device *dev = crtc->dev;
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3928 int pipe = intel_crtc->pipe;
3929 int plane = intel_crtc->plane;
3930
3931 intel_crtc_wait_for_pending_flips(crtc);
3932
3933 if (dev_priv->fbc.plane == plane)
3934 intel_disable_fbc(dev);
3935
3936 hsw_disable_ips(intel_crtc);
3937
3938 intel_crtc_dpms_overlay(intel_crtc, false);
3939 intel_crtc_update_cursor(crtc, false);
3940 intel_disable_planes(crtc);
3941 intel_disable_primary_hw_plane(crtc->primary, crtc);
3942
3943 /*
3944 * FIXME: Once we grow proper nuclear flip support out of this we need
3945 * to compute the mask of flip planes precisely. For the time being
3946 * consider this a flip to a NULL plane.
3947 */
3948 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3949
3950 drm_vblank_off(dev, pipe);
3951
3952 assert_vblank_disabled(crtc);
3953 }
3954
3955 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3956 {
3957 struct drm_device *dev = crtc->dev;
3958 struct drm_i915_private *dev_priv = dev->dev_private;
3959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3960 struct intel_encoder *encoder;
3961 int pipe = intel_crtc->pipe;
3962
3963 WARN_ON(!crtc->enabled);
3964
3965 if (intel_crtc->active)
3966 return;
3967
3968 if (intel_crtc->config.has_pch_encoder)
3969 intel_prepare_shared_dpll(intel_crtc);
3970
3971 if (intel_crtc->config.has_dp_encoder)
3972 intel_dp_set_m_n(intel_crtc);
3973
3974 intel_set_pipe_timings(intel_crtc);
3975
3976 if (intel_crtc->config.has_pch_encoder) {
3977 intel_cpu_transcoder_set_m_n(intel_crtc,
3978 &intel_crtc->config.fdi_m_n, NULL);
3979 }
3980
3981 ironlake_set_pipeconf(crtc);
3982
3983 intel_crtc->active = true;
3984
3985 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3986 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3987
3988 for_each_encoder_on_crtc(dev, crtc, encoder)
3989 if (encoder->pre_enable)
3990 encoder->pre_enable(encoder);
3991
3992 if (intel_crtc->config.has_pch_encoder) {
3993 /* Note: FDI PLL enabling _must_ be done before we enable the
3994 * cpu pipes, hence this is separate from all the other fdi/pch
3995 * enabling. */
3996 ironlake_fdi_pll_enable(intel_crtc);
3997 } else {
3998 assert_fdi_tx_disabled(dev_priv, pipe);
3999 assert_fdi_rx_disabled(dev_priv, pipe);
4000 }
4001
4002 ironlake_pfit_enable(intel_crtc);
4003
4004 /*
4005 * On ILK+ LUT must be loaded before the pipe is running but with
4006 * clocks enabled
4007 */
4008 intel_crtc_load_lut(crtc);
4009
4010 intel_update_watermarks(crtc);
4011 intel_enable_pipe(intel_crtc);
4012
4013 if (intel_crtc->config.has_pch_encoder)
4014 ironlake_pch_enable(crtc);
4015
4016 for_each_encoder_on_crtc(dev, crtc, encoder)
4017 encoder->enable(encoder);
4018
4019 if (HAS_PCH_CPT(dev))
4020 cpt_verify_modeset(dev, intel_crtc->pipe);
4021
4022 intel_crtc_enable_planes(crtc);
4023 }
4024
4025 /* IPS only exists on ULT machines and is tied to pipe A. */
4026 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4027 {
4028 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4029 }
4030
4031 /*
4032 * This implements the workaround described in the "notes" section of the mode
4033 * set sequence documentation. When going from no pipes or single pipe to
4034 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4035 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4036 */
4037 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4038 {
4039 struct drm_device *dev = crtc->base.dev;
4040 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4041
4042 /* We want to get the other_active_crtc only if there's only 1 other
4043 * active crtc. */
4044 for_each_intel_crtc(dev, crtc_it) {
4045 if (!crtc_it->active || crtc_it == crtc)
4046 continue;
4047
4048 if (other_active_crtc)
4049 return;
4050
4051 other_active_crtc = crtc_it;
4052 }
4053 if (!other_active_crtc)
4054 return;
4055
4056 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4057 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4058 }
4059
4060 static void haswell_crtc_enable(struct drm_crtc *crtc)
4061 {
4062 struct drm_device *dev = crtc->dev;
4063 struct drm_i915_private *dev_priv = dev->dev_private;
4064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4065 struct intel_encoder *encoder;
4066 int pipe = intel_crtc->pipe;
4067
4068 WARN_ON(!crtc->enabled);
4069
4070 if (intel_crtc->active)
4071 return;
4072
4073 if (intel_crtc_to_shared_dpll(intel_crtc))
4074 intel_enable_shared_dpll(intel_crtc);
4075
4076 if (intel_crtc->config.has_dp_encoder)
4077 intel_dp_set_m_n(intel_crtc);
4078
4079 intel_set_pipe_timings(intel_crtc);
4080
4081 if (intel_crtc->config.has_pch_encoder) {
4082 intel_cpu_transcoder_set_m_n(intel_crtc,
4083 &intel_crtc->config.fdi_m_n, NULL);
4084 }
4085
4086 haswell_set_pipeconf(crtc);
4087
4088 intel_set_pipe_csc(crtc);
4089
4090 intel_crtc->active = true;
4091
4092 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4093 for_each_encoder_on_crtc(dev, crtc, encoder)
4094 if (encoder->pre_enable)
4095 encoder->pre_enable(encoder);
4096
4097 if (intel_crtc->config.has_pch_encoder) {
4098 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4099 dev_priv->display.fdi_link_train(crtc);
4100 }
4101
4102 intel_ddi_enable_pipe_clock(intel_crtc);
4103
4104 ironlake_pfit_enable(intel_crtc);
4105
4106 /*
4107 * On ILK+ LUT must be loaded before the pipe is running but with
4108 * clocks enabled
4109 */
4110 intel_crtc_load_lut(crtc);
4111
4112 intel_ddi_set_pipe_settings(crtc);
4113 intel_ddi_enable_transcoder_func(crtc);
4114
4115 intel_update_watermarks(crtc);
4116 intel_enable_pipe(intel_crtc);
4117
4118 if (intel_crtc->config.has_pch_encoder)
4119 lpt_pch_enable(crtc);
4120
4121 if (intel_crtc->config.dp_encoder_is_mst)
4122 intel_ddi_set_vc_payload_alloc(crtc, true);
4123
4124 for_each_encoder_on_crtc(dev, crtc, encoder) {
4125 encoder->enable(encoder);
4126 intel_opregion_notify_encoder(encoder, true);
4127 }
4128
4129 /* If we change the relative order between pipe/planes enabling, we need
4130 * to change the workaround. */
4131 haswell_mode_set_planes_workaround(intel_crtc);
4132 intel_crtc_enable_planes(crtc);
4133 }
4134
4135 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4136 {
4137 struct drm_device *dev = crtc->base.dev;
4138 struct drm_i915_private *dev_priv = dev->dev_private;
4139 int pipe = crtc->pipe;
4140
4141 /* To avoid upsetting the power well on haswell only disable the pfit if
4142 * it's in use. The hw state code will make sure we get this right. */
4143 if (crtc->config.pch_pfit.enabled) {
4144 I915_WRITE(PF_CTL(pipe), 0);
4145 I915_WRITE(PF_WIN_POS(pipe), 0);
4146 I915_WRITE(PF_WIN_SZ(pipe), 0);
4147 }
4148 }
4149
4150 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4151 {
4152 struct drm_device *dev = crtc->dev;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4155 struct intel_encoder *encoder;
4156 int pipe = intel_crtc->pipe;
4157 u32 reg, temp;
4158
4159 if (!intel_crtc->active)
4160 return;
4161
4162 intel_crtc_disable_planes(crtc);
4163
4164 for_each_encoder_on_crtc(dev, crtc, encoder)
4165 encoder->disable(encoder);
4166
4167 if (intel_crtc->config.has_pch_encoder)
4168 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4169
4170 intel_disable_pipe(dev_priv, pipe);
4171
4172 if (intel_crtc->config.dp_encoder_is_mst)
4173 intel_ddi_set_vc_payload_alloc(crtc, false);
4174
4175 ironlake_pfit_disable(intel_crtc);
4176
4177 for_each_encoder_on_crtc(dev, crtc, encoder)
4178 if (encoder->post_disable)
4179 encoder->post_disable(encoder);
4180
4181 if (intel_crtc->config.has_pch_encoder) {
4182 ironlake_fdi_disable(crtc);
4183
4184 ironlake_disable_pch_transcoder(dev_priv, pipe);
4185 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4186
4187 if (HAS_PCH_CPT(dev)) {
4188 /* disable TRANS_DP_CTL */
4189 reg = TRANS_DP_CTL(pipe);
4190 temp = I915_READ(reg);
4191 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4192 TRANS_DP_PORT_SEL_MASK);
4193 temp |= TRANS_DP_PORT_SEL_NONE;
4194 I915_WRITE(reg, temp);
4195
4196 /* disable DPLL_SEL */
4197 temp = I915_READ(PCH_DPLL_SEL);
4198 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4199 I915_WRITE(PCH_DPLL_SEL, temp);
4200 }
4201
4202 /* disable PCH DPLL */
4203 intel_disable_shared_dpll(intel_crtc);
4204
4205 ironlake_fdi_pll_disable(intel_crtc);
4206 }
4207
4208 intel_crtc->active = false;
4209 intel_update_watermarks(crtc);
4210
4211 mutex_lock(&dev->struct_mutex);
4212 intel_update_fbc(dev);
4213 mutex_unlock(&dev->struct_mutex);
4214 }
4215
4216 static void haswell_crtc_disable(struct drm_crtc *crtc)
4217 {
4218 struct drm_device *dev = crtc->dev;
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4221 struct intel_encoder *encoder;
4222 int pipe = intel_crtc->pipe;
4223 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4224
4225 if (!intel_crtc->active)
4226 return;
4227
4228 intel_crtc_disable_planes(crtc);
4229
4230 for_each_encoder_on_crtc(dev, crtc, encoder) {
4231 intel_opregion_notify_encoder(encoder, false);
4232 encoder->disable(encoder);
4233 }
4234
4235 if (intel_crtc->config.has_pch_encoder)
4236 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4237 intel_disable_pipe(dev_priv, pipe);
4238
4239 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4240
4241 ironlake_pfit_disable(intel_crtc);
4242
4243 intel_ddi_disable_pipe_clock(intel_crtc);
4244
4245 if (intel_crtc->config.has_pch_encoder) {
4246 lpt_disable_pch_transcoder(dev_priv);
4247 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4248 intel_ddi_fdi_disable(crtc);
4249 }
4250
4251 for_each_encoder_on_crtc(dev, crtc, encoder)
4252 if (encoder->post_disable)
4253 encoder->post_disable(encoder);
4254
4255 intel_crtc->active = false;
4256 intel_update_watermarks(crtc);
4257
4258 mutex_lock(&dev->struct_mutex);
4259 intel_update_fbc(dev);
4260 mutex_unlock(&dev->struct_mutex);
4261
4262 if (intel_crtc_to_shared_dpll(intel_crtc))
4263 intel_disable_shared_dpll(intel_crtc);
4264 }
4265
4266 static void ironlake_crtc_off(struct drm_crtc *crtc)
4267 {
4268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4269 intel_put_shared_dpll(intel_crtc);
4270 }
4271
4272
4273 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4274 {
4275 struct drm_device *dev = crtc->base.dev;
4276 struct drm_i915_private *dev_priv = dev->dev_private;
4277 struct intel_crtc_config *pipe_config = &crtc->config;
4278
4279 if (!crtc->config.gmch_pfit.control)
4280 return;
4281
4282 /*
4283 * The panel fitter should only be adjusted whilst the pipe is disabled,
4284 * according to register description and PRM.
4285 */
4286 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4287 assert_pipe_disabled(dev_priv, crtc->pipe);
4288
4289 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4290 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4291
4292 /* Border color in case we don't scale up to the full screen. Black by
4293 * default, change to something else for debugging. */
4294 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4295 }
4296
4297 static enum intel_display_power_domain port_to_power_domain(enum port port)
4298 {
4299 switch (port) {
4300 case PORT_A:
4301 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4302 case PORT_B:
4303 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4304 case PORT_C:
4305 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4306 case PORT_D:
4307 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4308 default:
4309 WARN_ON_ONCE(1);
4310 return POWER_DOMAIN_PORT_OTHER;
4311 }
4312 }
4313
4314 #define for_each_power_domain(domain, mask) \
4315 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4316 if ((1 << (domain)) & (mask))
4317
4318 enum intel_display_power_domain
4319 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4320 {
4321 struct drm_device *dev = intel_encoder->base.dev;
4322 struct intel_digital_port *intel_dig_port;
4323
4324 switch (intel_encoder->type) {
4325 case INTEL_OUTPUT_UNKNOWN:
4326 /* Only DDI platforms should ever use this output type */
4327 WARN_ON_ONCE(!HAS_DDI(dev));
4328 case INTEL_OUTPUT_DISPLAYPORT:
4329 case INTEL_OUTPUT_HDMI:
4330 case INTEL_OUTPUT_EDP:
4331 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4332 return port_to_power_domain(intel_dig_port->port);
4333 case INTEL_OUTPUT_DP_MST:
4334 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4335 return port_to_power_domain(intel_dig_port->port);
4336 case INTEL_OUTPUT_ANALOG:
4337 return POWER_DOMAIN_PORT_CRT;
4338 case INTEL_OUTPUT_DSI:
4339 return POWER_DOMAIN_PORT_DSI;
4340 default:
4341 return POWER_DOMAIN_PORT_OTHER;
4342 }
4343 }
4344
4345 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4346 {
4347 struct drm_device *dev = crtc->dev;
4348 struct intel_encoder *intel_encoder;
4349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4350 enum pipe pipe = intel_crtc->pipe;
4351 unsigned long mask;
4352 enum transcoder transcoder;
4353
4354 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4355
4356 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4357 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4358 if (intel_crtc->config.pch_pfit.enabled ||
4359 intel_crtc->config.pch_pfit.force_thru)
4360 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4361
4362 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4363 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4364
4365 return mask;
4366 }
4367
4368 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4369 bool enable)
4370 {
4371 if (dev_priv->power_domains.init_power_on == enable)
4372 return;
4373
4374 if (enable)
4375 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4376 else
4377 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4378
4379 dev_priv->power_domains.init_power_on = enable;
4380 }
4381
4382 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4383 {
4384 struct drm_i915_private *dev_priv = dev->dev_private;
4385 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4386 struct intel_crtc *crtc;
4387
4388 /*
4389 * First get all needed power domains, then put all unneeded, to avoid
4390 * any unnecessary toggling of the power wells.
4391 */
4392 for_each_intel_crtc(dev, crtc) {
4393 enum intel_display_power_domain domain;
4394
4395 if (!crtc->base.enabled)
4396 continue;
4397
4398 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4399
4400 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4401 intel_display_power_get(dev_priv, domain);
4402 }
4403
4404 for_each_intel_crtc(dev, crtc) {
4405 enum intel_display_power_domain domain;
4406
4407 for_each_power_domain(domain, crtc->enabled_power_domains)
4408 intel_display_power_put(dev_priv, domain);
4409
4410 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4411 }
4412
4413 intel_display_set_init_power(dev_priv, false);
4414 }
4415
4416 /* returns HPLL frequency in kHz */
4417 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4418 {
4419 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4420
4421 /* Obtain SKU information */
4422 mutex_lock(&dev_priv->dpio_lock);
4423 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4424 CCK_FUSE_HPLL_FREQ_MASK;
4425 mutex_unlock(&dev_priv->dpio_lock);
4426
4427 return vco_freq[hpll_freq] * 1000;
4428 }
4429
4430 static void vlv_update_cdclk(struct drm_device *dev)
4431 {
4432 struct drm_i915_private *dev_priv = dev->dev_private;
4433
4434 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4435 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4436 dev_priv->vlv_cdclk_freq);
4437
4438 /*
4439 * Program the gmbus_freq based on the cdclk frequency.
4440 * BSpec erroneously claims we should aim for 4MHz, but
4441 * in fact 1MHz is the correct frequency.
4442 */
4443 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4444 }
4445
4446 /* Adjust CDclk dividers to allow high res or save power if possible */
4447 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4448 {
4449 struct drm_i915_private *dev_priv = dev->dev_private;
4450 u32 val, cmd;
4451
4452 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4453
4454 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4455 cmd = 2;
4456 else if (cdclk == 266667)
4457 cmd = 1;
4458 else
4459 cmd = 0;
4460
4461 mutex_lock(&dev_priv->rps.hw_lock);
4462 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4463 val &= ~DSPFREQGUAR_MASK;
4464 val |= (cmd << DSPFREQGUAR_SHIFT);
4465 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4466 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4467 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4468 50)) {
4469 DRM_ERROR("timed out waiting for CDclk change\n");
4470 }
4471 mutex_unlock(&dev_priv->rps.hw_lock);
4472
4473 if (cdclk == 400000) {
4474 u32 divider, vco;
4475
4476 vco = valleyview_get_vco(dev_priv);
4477 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4478
4479 mutex_lock(&dev_priv->dpio_lock);
4480 /* adjust cdclk divider */
4481 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4482 val &= ~DISPLAY_FREQUENCY_VALUES;
4483 val |= divider;
4484 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4485
4486 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4487 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4488 50))
4489 DRM_ERROR("timed out waiting for CDclk change\n");
4490 mutex_unlock(&dev_priv->dpio_lock);
4491 }
4492
4493 mutex_lock(&dev_priv->dpio_lock);
4494 /* adjust self-refresh exit latency value */
4495 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4496 val &= ~0x7f;
4497
4498 /*
4499 * For high bandwidth configs, we set a higher latency in the bunit
4500 * so that the core display fetch happens in time to avoid underruns.
4501 */
4502 if (cdclk == 400000)
4503 val |= 4500 / 250; /* 4.5 usec */
4504 else
4505 val |= 3000 / 250; /* 3.0 usec */
4506 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4507 mutex_unlock(&dev_priv->dpio_lock);
4508
4509 vlv_update_cdclk(dev);
4510 }
4511
4512 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4513 {
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 u32 val, cmd;
4516
4517 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4518
4519 switch (cdclk) {
4520 case 400000:
4521 cmd = 3;
4522 break;
4523 case 333333:
4524 case 320000:
4525 cmd = 2;
4526 break;
4527 case 266667:
4528 cmd = 1;
4529 break;
4530 case 200000:
4531 cmd = 0;
4532 break;
4533 default:
4534 WARN_ON(1);
4535 return;
4536 }
4537
4538 mutex_lock(&dev_priv->rps.hw_lock);
4539 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4540 val &= ~DSPFREQGUAR_MASK_CHV;
4541 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4542 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4543 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4544 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4545 50)) {
4546 DRM_ERROR("timed out waiting for CDclk change\n");
4547 }
4548 mutex_unlock(&dev_priv->rps.hw_lock);
4549
4550 vlv_update_cdclk(dev);
4551 }
4552
4553 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4554 int max_pixclk)
4555 {
4556 int vco = valleyview_get_vco(dev_priv);
4557 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4558
4559 /* FIXME: Punit isn't quite ready yet */
4560 if (IS_CHERRYVIEW(dev_priv->dev))
4561 return 400000;
4562
4563 /*
4564 * Really only a few cases to deal with, as only 4 CDclks are supported:
4565 * 200MHz
4566 * 267MHz
4567 * 320/333MHz (depends on HPLL freq)
4568 * 400MHz
4569 * So we check to see whether we're above 90% of the lower bin and
4570 * adjust if needed.
4571 *
4572 * We seem to get an unstable or solid color picture at 200MHz.
4573 * Not sure what's wrong. For now use 200MHz only when all pipes
4574 * are off.
4575 */
4576 if (max_pixclk > freq_320*9/10)
4577 return 400000;
4578 else if (max_pixclk > 266667*9/10)
4579 return freq_320;
4580 else if (max_pixclk > 0)
4581 return 266667;
4582 else
4583 return 200000;
4584 }
4585
4586 /* compute the max pixel clock for new configuration */
4587 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4588 {
4589 struct drm_device *dev = dev_priv->dev;
4590 struct intel_crtc *intel_crtc;
4591 int max_pixclk = 0;
4592
4593 for_each_intel_crtc(dev, intel_crtc) {
4594 if (intel_crtc->new_enabled)
4595 max_pixclk = max(max_pixclk,
4596 intel_crtc->new_config->adjusted_mode.crtc_clock);
4597 }
4598
4599 return max_pixclk;
4600 }
4601
4602 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4603 unsigned *prepare_pipes)
4604 {
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 struct intel_crtc *intel_crtc;
4607 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4608
4609 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4610 dev_priv->vlv_cdclk_freq)
4611 return;
4612
4613 /* disable/enable all currently active pipes while we change cdclk */
4614 for_each_intel_crtc(dev, intel_crtc)
4615 if (intel_crtc->base.enabled)
4616 *prepare_pipes |= (1 << intel_crtc->pipe);
4617 }
4618
4619 static void valleyview_modeset_global_resources(struct drm_device *dev)
4620 {
4621 struct drm_i915_private *dev_priv = dev->dev_private;
4622 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4623 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4624
4625 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4626 if (IS_CHERRYVIEW(dev))
4627 cherryview_set_cdclk(dev, req_cdclk);
4628 else
4629 valleyview_set_cdclk(dev, req_cdclk);
4630 }
4631
4632 modeset_update_crtc_power_domains(dev);
4633 }
4634
4635 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4636 {
4637 struct drm_device *dev = crtc->dev;
4638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4639 struct intel_encoder *encoder;
4640 int pipe = intel_crtc->pipe;
4641 bool is_dsi;
4642
4643 WARN_ON(!crtc->enabled);
4644
4645 if (intel_crtc->active)
4646 return;
4647
4648 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4649
4650 if (!is_dsi) {
4651 if (IS_CHERRYVIEW(dev))
4652 chv_prepare_pll(intel_crtc);
4653 else
4654 vlv_prepare_pll(intel_crtc);
4655 }
4656
4657 if (intel_crtc->config.has_dp_encoder)
4658 intel_dp_set_m_n(intel_crtc);
4659
4660 intel_set_pipe_timings(intel_crtc);
4661
4662 i9xx_set_pipeconf(intel_crtc);
4663
4664 intel_crtc->active = true;
4665
4666 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4667
4668 for_each_encoder_on_crtc(dev, crtc, encoder)
4669 if (encoder->pre_pll_enable)
4670 encoder->pre_pll_enable(encoder);
4671
4672 if (!is_dsi) {
4673 if (IS_CHERRYVIEW(dev))
4674 chv_enable_pll(intel_crtc);
4675 else
4676 vlv_enable_pll(intel_crtc);
4677 }
4678
4679 for_each_encoder_on_crtc(dev, crtc, encoder)
4680 if (encoder->pre_enable)
4681 encoder->pre_enable(encoder);
4682
4683 i9xx_pfit_enable(intel_crtc);
4684
4685 intel_crtc_load_lut(crtc);
4686
4687 intel_update_watermarks(crtc);
4688 intel_enable_pipe(intel_crtc);
4689
4690 for_each_encoder_on_crtc(dev, crtc, encoder)
4691 encoder->enable(encoder);
4692
4693 intel_crtc_enable_planes(crtc);
4694
4695 /* Underruns don't raise interrupts, so check manually. */
4696 i9xx_check_fifo_underruns(dev);
4697 }
4698
4699 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4700 {
4701 struct drm_device *dev = crtc->base.dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703
4704 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4705 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4706 }
4707
4708 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4709 {
4710 struct drm_device *dev = crtc->dev;
4711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712 struct intel_encoder *encoder;
4713 int pipe = intel_crtc->pipe;
4714
4715 WARN_ON(!crtc->enabled);
4716
4717 if (intel_crtc->active)
4718 return;
4719
4720 i9xx_set_pll_dividers(intel_crtc);
4721
4722 if (intel_crtc->config.has_dp_encoder)
4723 intel_dp_set_m_n(intel_crtc);
4724
4725 intel_set_pipe_timings(intel_crtc);
4726
4727 i9xx_set_pipeconf(intel_crtc);
4728
4729 intel_crtc->active = true;
4730
4731 if (!IS_GEN2(dev))
4732 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4733
4734 for_each_encoder_on_crtc(dev, crtc, encoder)
4735 if (encoder->pre_enable)
4736 encoder->pre_enable(encoder);
4737
4738 i9xx_enable_pll(intel_crtc);
4739
4740 i9xx_pfit_enable(intel_crtc);
4741
4742 intel_crtc_load_lut(crtc);
4743
4744 intel_update_watermarks(crtc);
4745 intel_enable_pipe(intel_crtc);
4746
4747 for_each_encoder_on_crtc(dev, crtc, encoder)
4748 encoder->enable(encoder);
4749
4750 intel_crtc_enable_planes(crtc);
4751
4752 /*
4753 * Gen2 reports pipe underruns whenever all planes are disabled.
4754 * So don't enable underrun reporting before at least some planes
4755 * are enabled.
4756 * FIXME: Need to fix the logic to work when we turn off all planes
4757 * but leave the pipe running.
4758 */
4759 if (IS_GEN2(dev))
4760 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4761
4762 /* Underruns don't raise interrupts, so check manually. */
4763 i9xx_check_fifo_underruns(dev);
4764 }
4765
4766 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4767 {
4768 struct drm_device *dev = crtc->base.dev;
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770
4771 if (!crtc->config.gmch_pfit.control)
4772 return;
4773
4774 assert_pipe_disabled(dev_priv, crtc->pipe);
4775
4776 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4777 I915_READ(PFIT_CONTROL));
4778 I915_WRITE(PFIT_CONTROL, 0);
4779 }
4780
4781 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4782 {
4783 struct drm_device *dev = crtc->dev;
4784 struct drm_i915_private *dev_priv = dev->dev_private;
4785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4786 struct intel_encoder *encoder;
4787 int pipe = intel_crtc->pipe;
4788
4789 if (!intel_crtc->active)
4790 return;
4791
4792 /*
4793 * Gen2 reports pipe underruns whenever all planes are disabled.
4794 * So diasble underrun reporting before all the planes get disabled.
4795 * FIXME: Need to fix the logic to work when we turn off all planes
4796 * but leave the pipe running.
4797 */
4798 if (IS_GEN2(dev))
4799 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4800
4801 /*
4802 * Vblank time updates from the shadow to live plane control register
4803 * are blocked if the memory self-refresh mode is active at that
4804 * moment. So to make sure the plane gets truly disabled, disable
4805 * first the self-refresh mode. The self-refresh enable bit in turn
4806 * will be checked/applied by the HW only at the next frame start
4807 * event which is after the vblank start event, so we need to have a
4808 * wait-for-vblank between disabling the plane and the pipe.
4809 */
4810 intel_set_memory_cxsr(dev_priv, false);
4811 intel_crtc_disable_planes(crtc);
4812
4813 for_each_encoder_on_crtc(dev, crtc, encoder)
4814 encoder->disable(encoder);
4815
4816 /*
4817 * On gen2 planes are double buffered but the pipe isn't, so we must
4818 * wait for planes to fully turn off before disabling the pipe.
4819 * We also need to wait on all gmch platforms because of the
4820 * self-refresh mode constraint explained above.
4821 */
4822 intel_wait_for_vblank(dev, pipe);
4823
4824 intel_disable_pipe(dev_priv, pipe);
4825
4826 i9xx_pfit_disable(intel_crtc);
4827
4828 for_each_encoder_on_crtc(dev, crtc, encoder)
4829 if (encoder->post_disable)
4830 encoder->post_disable(encoder);
4831
4832 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4833 if (IS_CHERRYVIEW(dev))
4834 chv_disable_pll(dev_priv, pipe);
4835 else if (IS_VALLEYVIEW(dev))
4836 vlv_disable_pll(dev_priv, pipe);
4837 else
4838 i9xx_disable_pll(dev_priv, pipe);
4839 }
4840
4841 if (!IS_GEN2(dev))
4842 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4843
4844 intel_crtc->active = false;
4845 intel_update_watermarks(crtc);
4846
4847 mutex_lock(&dev->struct_mutex);
4848 intel_update_fbc(dev);
4849 mutex_unlock(&dev->struct_mutex);
4850 }
4851
4852 static void i9xx_crtc_off(struct drm_crtc *crtc)
4853 {
4854 }
4855
4856 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4857 bool enabled)
4858 {
4859 struct drm_device *dev = crtc->dev;
4860 struct drm_i915_master_private *master_priv;
4861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4862 int pipe = intel_crtc->pipe;
4863
4864 if (!dev->primary->master)
4865 return;
4866
4867 master_priv = dev->primary->master->driver_priv;
4868 if (!master_priv->sarea_priv)
4869 return;
4870
4871 switch (pipe) {
4872 case 0:
4873 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4874 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4875 break;
4876 case 1:
4877 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4878 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4879 break;
4880 default:
4881 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4882 break;
4883 }
4884 }
4885
4886 /* Master function to enable/disable CRTC and corresponding power wells */
4887 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4888 {
4889 struct drm_device *dev = crtc->dev;
4890 struct drm_i915_private *dev_priv = dev->dev_private;
4891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4892 enum intel_display_power_domain domain;
4893 unsigned long domains;
4894
4895 if (enable) {
4896 if (!intel_crtc->active) {
4897 domains = get_crtc_power_domains(crtc);
4898 for_each_power_domain(domain, domains)
4899 intel_display_power_get(dev_priv, domain);
4900 intel_crtc->enabled_power_domains = domains;
4901
4902 dev_priv->display.crtc_enable(crtc);
4903 }
4904 } else {
4905 if (intel_crtc->active) {
4906 dev_priv->display.crtc_disable(crtc);
4907
4908 domains = intel_crtc->enabled_power_domains;
4909 for_each_power_domain(domain, domains)
4910 intel_display_power_put(dev_priv, domain);
4911 intel_crtc->enabled_power_domains = 0;
4912 }
4913 }
4914 }
4915
4916 /**
4917 * Sets the power management mode of the pipe and plane.
4918 */
4919 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4920 {
4921 struct drm_device *dev = crtc->dev;
4922 struct intel_encoder *intel_encoder;
4923 bool enable = false;
4924
4925 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4926 enable |= intel_encoder->connectors_active;
4927
4928 intel_crtc_control(crtc, enable);
4929
4930 intel_crtc_update_sarea(crtc, enable);
4931 }
4932
4933 static void intel_crtc_disable(struct drm_crtc *crtc)
4934 {
4935 struct drm_device *dev = crtc->dev;
4936 struct drm_connector *connector;
4937 struct drm_i915_private *dev_priv = dev->dev_private;
4938 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4939 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4940
4941 /* crtc should still be enabled when we disable it. */
4942 WARN_ON(!crtc->enabled);
4943
4944 dev_priv->display.crtc_disable(crtc);
4945 intel_crtc_update_sarea(crtc, false);
4946 dev_priv->display.off(crtc);
4947
4948 if (crtc->primary->fb) {
4949 mutex_lock(&dev->struct_mutex);
4950 intel_unpin_fb_obj(old_obj);
4951 i915_gem_track_fb(old_obj, NULL,
4952 INTEL_FRONTBUFFER_PRIMARY(pipe));
4953 mutex_unlock(&dev->struct_mutex);
4954 crtc->primary->fb = NULL;
4955 }
4956
4957 /* Update computed state. */
4958 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4959 if (!connector->encoder || !connector->encoder->crtc)
4960 continue;
4961
4962 if (connector->encoder->crtc != crtc)
4963 continue;
4964
4965 connector->dpms = DRM_MODE_DPMS_OFF;
4966 to_intel_encoder(connector->encoder)->connectors_active = false;
4967 }
4968 }
4969
4970 void intel_encoder_destroy(struct drm_encoder *encoder)
4971 {
4972 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4973
4974 drm_encoder_cleanup(encoder);
4975 kfree(intel_encoder);
4976 }
4977
4978 /* Simple dpms helper for encoders with just one connector, no cloning and only
4979 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4980 * state of the entire output pipe. */
4981 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4982 {
4983 if (mode == DRM_MODE_DPMS_ON) {
4984 encoder->connectors_active = true;
4985
4986 intel_crtc_update_dpms(encoder->base.crtc);
4987 } else {
4988 encoder->connectors_active = false;
4989
4990 intel_crtc_update_dpms(encoder->base.crtc);
4991 }
4992 }
4993
4994 /* Cross check the actual hw state with our own modeset state tracking (and it's
4995 * internal consistency). */
4996 static void intel_connector_check_state(struct intel_connector *connector)
4997 {
4998 if (connector->get_hw_state(connector)) {
4999 struct intel_encoder *encoder = connector->encoder;
5000 struct drm_crtc *crtc;
5001 bool encoder_enabled;
5002 enum pipe pipe;
5003
5004 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5005 connector->base.base.id,
5006 connector->base.name);
5007
5008 /* there is no real hw state for MST connectors */
5009 if (connector->mst_port)
5010 return;
5011
5012 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5013 "wrong connector dpms state\n");
5014 WARN(connector->base.encoder != &encoder->base,
5015 "active connector not linked to encoder\n");
5016
5017 if (encoder) {
5018 WARN(!encoder->connectors_active,
5019 "encoder->connectors_active not set\n");
5020
5021 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5022 WARN(!encoder_enabled, "encoder not enabled\n");
5023 if (WARN_ON(!encoder->base.crtc))
5024 return;
5025
5026 crtc = encoder->base.crtc;
5027
5028 WARN(!crtc->enabled, "crtc not enabled\n");
5029 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5030 WARN(pipe != to_intel_crtc(crtc)->pipe,
5031 "encoder active on the wrong pipe\n");
5032 }
5033 }
5034 }
5035
5036 /* Even simpler default implementation, if there's really no special case to
5037 * consider. */
5038 void intel_connector_dpms(struct drm_connector *connector, int mode)
5039 {
5040 /* All the simple cases only support two dpms states. */
5041 if (mode != DRM_MODE_DPMS_ON)
5042 mode = DRM_MODE_DPMS_OFF;
5043
5044 if (mode == connector->dpms)
5045 return;
5046
5047 connector->dpms = mode;
5048
5049 /* Only need to change hw state when actually enabled */
5050 if (connector->encoder)
5051 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5052
5053 intel_modeset_check_state(connector->dev);
5054 }
5055
5056 /* Simple connector->get_hw_state implementation for encoders that support only
5057 * one connector and no cloning and hence the encoder state determines the state
5058 * of the connector. */
5059 bool intel_connector_get_hw_state(struct intel_connector *connector)
5060 {
5061 enum pipe pipe = 0;
5062 struct intel_encoder *encoder = connector->encoder;
5063
5064 return encoder->get_hw_state(encoder, &pipe);
5065 }
5066
5067 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5068 struct intel_crtc_config *pipe_config)
5069 {
5070 struct drm_i915_private *dev_priv = dev->dev_private;
5071 struct intel_crtc *pipe_B_crtc =
5072 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5073
5074 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5075 pipe_name(pipe), pipe_config->fdi_lanes);
5076 if (pipe_config->fdi_lanes > 4) {
5077 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5078 pipe_name(pipe), pipe_config->fdi_lanes);
5079 return false;
5080 }
5081
5082 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5083 if (pipe_config->fdi_lanes > 2) {
5084 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5085 pipe_config->fdi_lanes);
5086 return false;
5087 } else {
5088 return true;
5089 }
5090 }
5091
5092 if (INTEL_INFO(dev)->num_pipes == 2)
5093 return true;
5094
5095 /* Ivybridge 3 pipe is really complicated */
5096 switch (pipe) {
5097 case PIPE_A:
5098 return true;
5099 case PIPE_B:
5100 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5101 pipe_config->fdi_lanes > 2) {
5102 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5103 pipe_name(pipe), pipe_config->fdi_lanes);
5104 return false;
5105 }
5106 return true;
5107 case PIPE_C:
5108 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5109 pipe_B_crtc->config.fdi_lanes <= 2) {
5110 if (pipe_config->fdi_lanes > 2) {
5111 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5112 pipe_name(pipe), pipe_config->fdi_lanes);
5113 return false;
5114 }
5115 } else {
5116 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5117 return false;
5118 }
5119 return true;
5120 default:
5121 BUG();
5122 }
5123 }
5124
5125 #define RETRY 1
5126 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5127 struct intel_crtc_config *pipe_config)
5128 {
5129 struct drm_device *dev = intel_crtc->base.dev;
5130 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5131 int lane, link_bw, fdi_dotclock;
5132 bool setup_ok, needs_recompute = false;
5133
5134 retry:
5135 /* FDI is a binary signal running at ~2.7GHz, encoding
5136 * each output octet as 10 bits. The actual frequency
5137 * is stored as a divider into a 100MHz clock, and the
5138 * mode pixel clock is stored in units of 1KHz.
5139 * Hence the bw of each lane in terms of the mode signal
5140 * is:
5141 */
5142 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5143
5144 fdi_dotclock = adjusted_mode->crtc_clock;
5145
5146 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5147 pipe_config->pipe_bpp);
5148
5149 pipe_config->fdi_lanes = lane;
5150
5151 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5152 link_bw, &pipe_config->fdi_m_n);
5153
5154 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5155 intel_crtc->pipe, pipe_config);
5156 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5157 pipe_config->pipe_bpp -= 2*3;
5158 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5159 pipe_config->pipe_bpp);
5160 needs_recompute = true;
5161 pipe_config->bw_constrained = true;
5162
5163 goto retry;
5164 }
5165
5166 if (needs_recompute)
5167 return RETRY;
5168
5169 return setup_ok ? 0 : -EINVAL;
5170 }
5171
5172 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5173 struct intel_crtc_config *pipe_config)
5174 {
5175 pipe_config->ips_enabled = i915.enable_ips &&
5176 hsw_crtc_supports_ips(crtc) &&
5177 pipe_config->pipe_bpp <= 24;
5178 }
5179
5180 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5181 struct intel_crtc_config *pipe_config)
5182 {
5183 struct drm_device *dev = crtc->base.dev;
5184 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5185
5186 /* FIXME should check pixel clock limits on all platforms */
5187 if (INTEL_INFO(dev)->gen < 4) {
5188 struct drm_i915_private *dev_priv = dev->dev_private;
5189 int clock_limit =
5190 dev_priv->display.get_display_clock_speed(dev);
5191
5192 /*
5193 * Enable pixel doubling when the dot clock
5194 * is > 90% of the (display) core speed.
5195 *
5196 * GDG double wide on either pipe,
5197 * otherwise pipe A only.
5198 */
5199 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5200 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5201 clock_limit *= 2;
5202 pipe_config->double_wide = true;
5203 }
5204
5205 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5206 return -EINVAL;
5207 }
5208
5209 /*
5210 * Pipe horizontal size must be even in:
5211 * - DVO ganged mode
5212 * - LVDS dual channel mode
5213 * - Double wide pipe
5214 */
5215 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5216 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5217 pipe_config->pipe_src_w &= ~1;
5218
5219 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5220 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5221 */
5222 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5223 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5224 return -EINVAL;
5225
5226 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5227 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5228 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5229 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5230 * for lvds. */
5231 pipe_config->pipe_bpp = 8*3;
5232 }
5233
5234 if (HAS_IPS(dev))
5235 hsw_compute_ips_config(crtc, pipe_config);
5236
5237 /*
5238 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5239 * old clock survives for now.
5240 */
5241 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5242 pipe_config->shared_dpll = crtc->config.shared_dpll;
5243
5244 if (pipe_config->has_pch_encoder)
5245 return ironlake_fdi_compute_config(crtc, pipe_config);
5246
5247 return 0;
5248 }
5249
5250 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5251 {
5252 struct drm_i915_private *dev_priv = dev->dev_private;
5253 int vco = valleyview_get_vco(dev_priv);
5254 u32 val;
5255 int divider;
5256
5257 /* FIXME: Punit isn't quite ready yet */
5258 if (IS_CHERRYVIEW(dev))
5259 return 400000;
5260
5261 mutex_lock(&dev_priv->dpio_lock);
5262 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5263 mutex_unlock(&dev_priv->dpio_lock);
5264
5265 divider = val & DISPLAY_FREQUENCY_VALUES;
5266
5267 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5268 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5269 "cdclk change in progress\n");
5270
5271 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5272 }
5273
5274 static int i945_get_display_clock_speed(struct drm_device *dev)
5275 {
5276 return 400000;
5277 }
5278
5279 static int i915_get_display_clock_speed(struct drm_device *dev)
5280 {
5281 return 333000;
5282 }
5283
5284 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5285 {
5286 return 200000;
5287 }
5288
5289 static int pnv_get_display_clock_speed(struct drm_device *dev)
5290 {
5291 u16 gcfgc = 0;
5292
5293 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5294
5295 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5296 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5297 return 267000;
5298 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5299 return 333000;
5300 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5301 return 444000;
5302 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5303 return 200000;
5304 default:
5305 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5306 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5307 return 133000;
5308 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5309 return 167000;
5310 }
5311 }
5312
5313 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5314 {
5315 u16 gcfgc = 0;
5316
5317 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5318
5319 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5320 return 133000;
5321 else {
5322 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5323 case GC_DISPLAY_CLOCK_333_MHZ:
5324 return 333000;
5325 default:
5326 case GC_DISPLAY_CLOCK_190_200_MHZ:
5327 return 190000;
5328 }
5329 }
5330 }
5331
5332 static int i865_get_display_clock_speed(struct drm_device *dev)
5333 {
5334 return 266000;
5335 }
5336
5337 static int i855_get_display_clock_speed(struct drm_device *dev)
5338 {
5339 u16 hpllcc = 0;
5340 /* Assume that the hardware is in the high speed state. This
5341 * should be the default.
5342 */
5343 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5344 case GC_CLOCK_133_200:
5345 case GC_CLOCK_100_200:
5346 return 200000;
5347 case GC_CLOCK_166_250:
5348 return 250000;
5349 case GC_CLOCK_100_133:
5350 return 133000;
5351 }
5352
5353 /* Shouldn't happen */
5354 return 0;
5355 }
5356
5357 static int i830_get_display_clock_speed(struct drm_device *dev)
5358 {
5359 return 133000;
5360 }
5361
5362 static void
5363 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5364 {
5365 while (*num > DATA_LINK_M_N_MASK ||
5366 *den > DATA_LINK_M_N_MASK) {
5367 *num >>= 1;
5368 *den >>= 1;
5369 }
5370 }
5371
5372 static void compute_m_n(unsigned int m, unsigned int n,
5373 uint32_t *ret_m, uint32_t *ret_n)
5374 {
5375 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5376 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5377 intel_reduce_m_n_ratio(ret_m, ret_n);
5378 }
5379
5380 void
5381 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5382 int pixel_clock, int link_clock,
5383 struct intel_link_m_n *m_n)
5384 {
5385 m_n->tu = 64;
5386
5387 compute_m_n(bits_per_pixel * pixel_clock,
5388 link_clock * nlanes * 8,
5389 &m_n->gmch_m, &m_n->gmch_n);
5390
5391 compute_m_n(pixel_clock, link_clock,
5392 &m_n->link_m, &m_n->link_n);
5393 }
5394
5395 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5396 {
5397 if (i915.panel_use_ssc >= 0)
5398 return i915.panel_use_ssc != 0;
5399 return dev_priv->vbt.lvds_use_ssc
5400 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5401 }
5402
5403 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5404 {
5405 struct drm_device *dev = crtc->dev;
5406 struct drm_i915_private *dev_priv = dev->dev_private;
5407 int refclk;
5408
5409 if (IS_VALLEYVIEW(dev)) {
5410 refclk = 100000;
5411 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5412 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5413 refclk = dev_priv->vbt.lvds_ssc_freq;
5414 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5415 } else if (!IS_GEN2(dev)) {
5416 refclk = 96000;
5417 } else {
5418 refclk = 48000;
5419 }
5420
5421 return refclk;
5422 }
5423
5424 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5425 {
5426 return (1 << dpll->n) << 16 | dpll->m2;
5427 }
5428
5429 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5430 {
5431 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5432 }
5433
5434 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5435 intel_clock_t *reduced_clock)
5436 {
5437 struct drm_device *dev = crtc->base.dev;
5438 u32 fp, fp2 = 0;
5439
5440 if (IS_PINEVIEW(dev)) {
5441 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5442 if (reduced_clock)
5443 fp2 = pnv_dpll_compute_fp(reduced_clock);
5444 } else {
5445 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5446 if (reduced_clock)
5447 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5448 }
5449
5450 crtc->config.dpll_hw_state.fp0 = fp;
5451
5452 crtc->lowfreq_avail = false;
5453 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5454 reduced_clock && i915.powersave) {
5455 crtc->config.dpll_hw_state.fp1 = fp2;
5456 crtc->lowfreq_avail = true;
5457 } else {
5458 crtc->config.dpll_hw_state.fp1 = fp;
5459 }
5460 }
5461
5462 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5463 pipe)
5464 {
5465 u32 reg_val;
5466
5467 /*
5468 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5469 * and set it to a reasonable value instead.
5470 */
5471 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5472 reg_val &= 0xffffff00;
5473 reg_val |= 0x00000030;
5474 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5475
5476 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5477 reg_val &= 0x8cffffff;
5478 reg_val = 0x8c000000;
5479 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5480
5481 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5482 reg_val &= 0xffffff00;
5483 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5484
5485 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5486 reg_val &= 0x00ffffff;
5487 reg_val |= 0xb0000000;
5488 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5489 }
5490
5491 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5492 struct intel_link_m_n *m_n)
5493 {
5494 struct drm_device *dev = crtc->base.dev;
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496 int pipe = crtc->pipe;
5497
5498 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5499 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5500 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5501 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5502 }
5503
5504 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5505 struct intel_link_m_n *m_n,
5506 struct intel_link_m_n *m2_n2)
5507 {
5508 struct drm_device *dev = crtc->base.dev;
5509 struct drm_i915_private *dev_priv = dev->dev_private;
5510 int pipe = crtc->pipe;
5511 enum transcoder transcoder = crtc->config.cpu_transcoder;
5512
5513 if (INTEL_INFO(dev)->gen >= 5) {
5514 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5515 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5516 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5517 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5518 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5519 * for gen < 8) and if DRRS is supported (to make sure the
5520 * registers are not unnecessarily accessed).
5521 */
5522 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5523 crtc->config.has_drrs) {
5524 I915_WRITE(PIPE_DATA_M2(transcoder),
5525 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5526 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5527 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5528 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5529 }
5530 } else {
5531 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5532 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5533 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5534 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5535 }
5536 }
5537
5538 void intel_dp_set_m_n(struct intel_crtc *crtc)
5539 {
5540 if (crtc->config.has_pch_encoder)
5541 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5542 else
5543 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5544 &crtc->config.dp_m2_n2);
5545 }
5546
5547 static void vlv_update_pll(struct intel_crtc *crtc)
5548 {
5549 u32 dpll, dpll_md;
5550
5551 /*
5552 * Enable DPIO clock input. We should never disable the reference
5553 * clock for pipe B, since VGA hotplug / manual detection depends
5554 * on it.
5555 */
5556 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5557 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5558 /* We should never disable this, set it here for state tracking */
5559 if (crtc->pipe == PIPE_B)
5560 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5561 dpll |= DPLL_VCO_ENABLE;
5562 crtc->config.dpll_hw_state.dpll = dpll;
5563
5564 dpll_md = (crtc->config.pixel_multiplier - 1)
5565 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5566 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5567 }
5568
5569 static void vlv_prepare_pll(struct intel_crtc *crtc)
5570 {
5571 struct drm_device *dev = crtc->base.dev;
5572 struct drm_i915_private *dev_priv = dev->dev_private;
5573 int pipe = crtc->pipe;
5574 u32 mdiv;
5575 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5576 u32 coreclk, reg_val;
5577
5578 mutex_lock(&dev_priv->dpio_lock);
5579
5580 bestn = crtc->config.dpll.n;
5581 bestm1 = crtc->config.dpll.m1;
5582 bestm2 = crtc->config.dpll.m2;
5583 bestp1 = crtc->config.dpll.p1;
5584 bestp2 = crtc->config.dpll.p2;
5585
5586 /* See eDP HDMI DPIO driver vbios notes doc */
5587
5588 /* PLL B needs special handling */
5589 if (pipe == PIPE_B)
5590 vlv_pllb_recal_opamp(dev_priv, pipe);
5591
5592 /* Set up Tx target for periodic Rcomp update */
5593 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5594
5595 /* Disable target IRef on PLL */
5596 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5597 reg_val &= 0x00ffffff;
5598 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5599
5600 /* Disable fast lock */
5601 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5602
5603 /* Set idtafcrecal before PLL is enabled */
5604 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5605 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5606 mdiv |= ((bestn << DPIO_N_SHIFT));
5607 mdiv |= (1 << DPIO_K_SHIFT);
5608
5609 /*
5610 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5611 * but we don't support that).
5612 * Note: don't use the DAC post divider as it seems unstable.
5613 */
5614 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5615 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5616
5617 mdiv |= DPIO_ENABLE_CALIBRATION;
5618 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5619
5620 /* Set HBR and RBR LPF coefficients */
5621 if (crtc->config.port_clock == 162000 ||
5622 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5623 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5624 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5625 0x009f0003);
5626 else
5627 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5628 0x00d0000f);
5629
5630 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5631 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5632 /* Use SSC source */
5633 if (pipe == PIPE_A)
5634 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5635 0x0df40000);
5636 else
5637 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5638 0x0df70000);
5639 } else { /* HDMI or VGA */
5640 /* Use bend source */
5641 if (pipe == PIPE_A)
5642 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5643 0x0df70000);
5644 else
5645 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5646 0x0df40000);
5647 }
5648
5649 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5650 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5651 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5652 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5653 coreclk |= 0x01000000;
5654 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5655
5656 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5657 mutex_unlock(&dev_priv->dpio_lock);
5658 }
5659
5660 static void chv_update_pll(struct intel_crtc *crtc)
5661 {
5662 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5663 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5664 DPLL_VCO_ENABLE;
5665 if (crtc->pipe != PIPE_A)
5666 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5667
5668 crtc->config.dpll_hw_state.dpll_md =
5669 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5670 }
5671
5672 static void chv_prepare_pll(struct intel_crtc *crtc)
5673 {
5674 struct drm_device *dev = crtc->base.dev;
5675 struct drm_i915_private *dev_priv = dev->dev_private;
5676 int pipe = crtc->pipe;
5677 int dpll_reg = DPLL(crtc->pipe);
5678 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5679 u32 loopfilter, intcoeff;
5680 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5681 int refclk;
5682
5683 bestn = crtc->config.dpll.n;
5684 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5685 bestm1 = crtc->config.dpll.m1;
5686 bestm2 = crtc->config.dpll.m2 >> 22;
5687 bestp1 = crtc->config.dpll.p1;
5688 bestp2 = crtc->config.dpll.p2;
5689
5690 /*
5691 * Enable Refclk and SSC
5692 */
5693 I915_WRITE(dpll_reg,
5694 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5695
5696 mutex_lock(&dev_priv->dpio_lock);
5697
5698 /* p1 and p2 divider */
5699 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5700 5 << DPIO_CHV_S1_DIV_SHIFT |
5701 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5702 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5703 1 << DPIO_CHV_K_DIV_SHIFT);
5704
5705 /* Feedback post-divider - m2 */
5706 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5707
5708 /* Feedback refclk divider - n and m1 */
5709 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5710 DPIO_CHV_M1_DIV_BY_2 |
5711 1 << DPIO_CHV_N_DIV_SHIFT);
5712
5713 /* M2 fraction division */
5714 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5715
5716 /* M2 fraction division enable */
5717 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5718 DPIO_CHV_FRAC_DIV_EN |
5719 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5720
5721 /* Loop filter */
5722 refclk = i9xx_get_refclk(&crtc->base, 0);
5723 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5724 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5725 if (refclk == 100000)
5726 intcoeff = 11;
5727 else if (refclk == 38400)
5728 intcoeff = 10;
5729 else
5730 intcoeff = 9;
5731 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5732 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5733
5734 /* AFC Recal */
5735 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5736 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5737 DPIO_AFC_RECAL);
5738
5739 mutex_unlock(&dev_priv->dpio_lock);
5740 }
5741
5742 static void i9xx_update_pll(struct intel_crtc *crtc,
5743 intel_clock_t *reduced_clock,
5744 int num_connectors)
5745 {
5746 struct drm_device *dev = crtc->base.dev;
5747 struct drm_i915_private *dev_priv = dev->dev_private;
5748 u32 dpll;
5749 bool is_sdvo;
5750 struct dpll *clock = &crtc->config.dpll;
5751
5752 i9xx_update_pll_dividers(crtc, reduced_clock);
5753
5754 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5755 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5756
5757 dpll = DPLL_VGA_MODE_DIS;
5758
5759 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5760 dpll |= DPLLB_MODE_LVDS;
5761 else
5762 dpll |= DPLLB_MODE_DAC_SERIAL;
5763
5764 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5765 dpll |= (crtc->config.pixel_multiplier - 1)
5766 << SDVO_MULTIPLIER_SHIFT_HIRES;
5767 }
5768
5769 if (is_sdvo)
5770 dpll |= DPLL_SDVO_HIGH_SPEED;
5771
5772 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5773 dpll |= DPLL_SDVO_HIGH_SPEED;
5774
5775 /* compute bitmask from p1 value */
5776 if (IS_PINEVIEW(dev))
5777 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5778 else {
5779 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5780 if (IS_G4X(dev) && reduced_clock)
5781 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5782 }
5783 switch (clock->p2) {
5784 case 5:
5785 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5786 break;
5787 case 7:
5788 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5789 break;
5790 case 10:
5791 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5792 break;
5793 case 14:
5794 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5795 break;
5796 }
5797 if (INTEL_INFO(dev)->gen >= 4)
5798 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5799
5800 if (crtc->config.sdvo_tv_clock)
5801 dpll |= PLL_REF_INPUT_TVCLKINBC;
5802 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5803 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5804 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5805 else
5806 dpll |= PLL_REF_INPUT_DREFCLK;
5807
5808 dpll |= DPLL_VCO_ENABLE;
5809 crtc->config.dpll_hw_state.dpll = dpll;
5810
5811 if (INTEL_INFO(dev)->gen >= 4) {
5812 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5813 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5814 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5815 }
5816 }
5817
5818 static void i8xx_update_pll(struct intel_crtc *crtc,
5819 intel_clock_t *reduced_clock,
5820 int num_connectors)
5821 {
5822 struct drm_device *dev = crtc->base.dev;
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824 u32 dpll;
5825 struct dpll *clock = &crtc->config.dpll;
5826
5827 i9xx_update_pll_dividers(crtc, reduced_clock);
5828
5829 dpll = DPLL_VGA_MODE_DIS;
5830
5831 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5832 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5833 } else {
5834 if (clock->p1 == 2)
5835 dpll |= PLL_P1_DIVIDE_BY_TWO;
5836 else
5837 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5838 if (clock->p2 == 4)
5839 dpll |= PLL_P2_DIVIDE_BY_4;
5840 }
5841
5842 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5843 dpll |= DPLL_DVO_2X_MODE;
5844
5845 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5846 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5847 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5848 else
5849 dpll |= PLL_REF_INPUT_DREFCLK;
5850
5851 dpll |= DPLL_VCO_ENABLE;
5852 crtc->config.dpll_hw_state.dpll = dpll;
5853 }
5854
5855 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5856 {
5857 struct drm_device *dev = intel_crtc->base.dev;
5858 struct drm_i915_private *dev_priv = dev->dev_private;
5859 enum pipe pipe = intel_crtc->pipe;
5860 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5861 struct drm_display_mode *adjusted_mode =
5862 &intel_crtc->config.adjusted_mode;
5863 uint32_t crtc_vtotal, crtc_vblank_end;
5864 int vsyncshift = 0;
5865
5866 /* We need to be careful not to changed the adjusted mode, for otherwise
5867 * the hw state checker will get angry at the mismatch. */
5868 crtc_vtotal = adjusted_mode->crtc_vtotal;
5869 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5870
5871 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5872 /* the chip adds 2 halflines automatically */
5873 crtc_vtotal -= 1;
5874 crtc_vblank_end -= 1;
5875
5876 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5877 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5878 else
5879 vsyncshift = adjusted_mode->crtc_hsync_start -
5880 adjusted_mode->crtc_htotal / 2;
5881 if (vsyncshift < 0)
5882 vsyncshift += adjusted_mode->crtc_htotal;
5883 }
5884
5885 if (INTEL_INFO(dev)->gen > 3)
5886 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5887
5888 I915_WRITE(HTOTAL(cpu_transcoder),
5889 (adjusted_mode->crtc_hdisplay - 1) |
5890 ((adjusted_mode->crtc_htotal - 1) << 16));
5891 I915_WRITE(HBLANK(cpu_transcoder),
5892 (adjusted_mode->crtc_hblank_start - 1) |
5893 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5894 I915_WRITE(HSYNC(cpu_transcoder),
5895 (adjusted_mode->crtc_hsync_start - 1) |
5896 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5897
5898 I915_WRITE(VTOTAL(cpu_transcoder),
5899 (adjusted_mode->crtc_vdisplay - 1) |
5900 ((crtc_vtotal - 1) << 16));
5901 I915_WRITE(VBLANK(cpu_transcoder),
5902 (adjusted_mode->crtc_vblank_start - 1) |
5903 ((crtc_vblank_end - 1) << 16));
5904 I915_WRITE(VSYNC(cpu_transcoder),
5905 (adjusted_mode->crtc_vsync_start - 1) |
5906 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5907
5908 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5909 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5910 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5911 * bits. */
5912 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5913 (pipe == PIPE_B || pipe == PIPE_C))
5914 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5915
5916 /* pipesrc controls the size that is scaled from, which should
5917 * always be the user's requested size.
5918 */
5919 I915_WRITE(PIPESRC(pipe),
5920 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5921 (intel_crtc->config.pipe_src_h - 1));
5922 }
5923
5924 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5925 struct intel_crtc_config *pipe_config)
5926 {
5927 struct drm_device *dev = crtc->base.dev;
5928 struct drm_i915_private *dev_priv = dev->dev_private;
5929 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5930 uint32_t tmp;
5931
5932 tmp = I915_READ(HTOTAL(cpu_transcoder));
5933 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5934 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5935 tmp = I915_READ(HBLANK(cpu_transcoder));
5936 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5937 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5938 tmp = I915_READ(HSYNC(cpu_transcoder));
5939 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5940 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5941
5942 tmp = I915_READ(VTOTAL(cpu_transcoder));
5943 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5944 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5945 tmp = I915_READ(VBLANK(cpu_transcoder));
5946 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5947 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5948 tmp = I915_READ(VSYNC(cpu_transcoder));
5949 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5950 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5951
5952 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5953 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5954 pipe_config->adjusted_mode.crtc_vtotal += 1;
5955 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5956 }
5957
5958 tmp = I915_READ(PIPESRC(crtc->pipe));
5959 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5960 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5961
5962 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5963 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5964 }
5965
5966 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5967 struct intel_crtc_config *pipe_config)
5968 {
5969 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5970 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5971 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5972 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5973
5974 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5975 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5976 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5977 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5978
5979 mode->flags = pipe_config->adjusted_mode.flags;
5980
5981 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5982 mode->flags |= pipe_config->adjusted_mode.flags;
5983 }
5984
5985 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5986 {
5987 struct drm_device *dev = intel_crtc->base.dev;
5988 struct drm_i915_private *dev_priv = dev->dev_private;
5989 uint32_t pipeconf;
5990
5991 pipeconf = 0;
5992
5993 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5994 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5995 pipeconf |= PIPECONF_ENABLE;
5996
5997 if (intel_crtc->config.double_wide)
5998 pipeconf |= PIPECONF_DOUBLE_WIDE;
5999
6000 /* only g4x and later have fancy bpc/dither controls */
6001 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6002 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6003 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6004 pipeconf |= PIPECONF_DITHER_EN |
6005 PIPECONF_DITHER_TYPE_SP;
6006
6007 switch (intel_crtc->config.pipe_bpp) {
6008 case 18:
6009 pipeconf |= PIPECONF_6BPC;
6010 break;
6011 case 24:
6012 pipeconf |= PIPECONF_8BPC;
6013 break;
6014 case 30:
6015 pipeconf |= PIPECONF_10BPC;
6016 break;
6017 default:
6018 /* Case prevented by intel_choose_pipe_bpp_dither. */
6019 BUG();
6020 }
6021 }
6022
6023 if (HAS_PIPE_CXSR(dev)) {
6024 if (intel_crtc->lowfreq_avail) {
6025 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6026 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6027 } else {
6028 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6029 }
6030 }
6031
6032 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6033 if (INTEL_INFO(dev)->gen < 4 ||
6034 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6035 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6036 else
6037 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6038 } else
6039 pipeconf |= PIPECONF_PROGRESSIVE;
6040
6041 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6042 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6043
6044 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6045 POSTING_READ(PIPECONF(intel_crtc->pipe));
6046 }
6047
6048 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6049 int x, int y,
6050 struct drm_framebuffer *fb)
6051 {
6052 struct drm_device *dev = crtc->dev;
6053 struct drm_i915_private *dev_priv = dev->dev_private;
6054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6055 int refclk, num_connectors = 0;
6056 intel_clock_t clock, reduced_clock;
6057 bool ok, has_reduced_clock = false;
6058 bool is_lvds = false, is_dsi = false;
6059 struct intel_encoder *encoder;
6060 const intel_limit_t *limit;
6061
6062 for_each_encoder_on_crtc(dev, crtc, encoder) {
6063 switch (encoder->type) {
6064 case INTEL_OUTPUT_LVDS:
6065 is_lvds = true;
6066 break;
6067 case INTEL_OUTPUT_DSI:
6068 is_dsi = true;
6069 break;
6070 }
6071
6072 num_connectors++;
6073 }
6074
6075 if (is_dsi)
6076 return 0;
6077
6078 if (!intel_crtc->config.clock_set) {
6079 refclk = i9xx_get_refclk(crtc, num_connectors);
6080
6081 /*
6082 * Returns a set of divisors for the desired target clock with
6083 * the given refclk, or FALSE. The returned values represent
6084 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6085 * 2) / p1 / p2.
6086 */
6087 limit = intel_limit(crtc, refclk);
6088 ok = dev_priv->display.find_dpll(limit, crtc,
6089 intel_crtc->config.port_clock,
6090 refclk, NULL, &clock);
6091 if (!ok) {
6092 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6093 return -EINVAL;
6094 }
6095
6096 if (is_lvds && dev_priv->lvds_downclock_avail) {
6097 /*
6098 * Ensure we match the reduced clock's P to the target
6099 * clock. If the clocks don't match, we can't switch
6100 * the display clock by using the FP0/FP1. In such case
6101 * we will disable the LVDS downclock feature.
6102 */
6103 has_reduced_clock =
6104 dev_priv->display.find_dpll(limit, crtc,
6105 dev_priv->lvds_downclock,
6106 refclk, &clock,
6107 &reduced_clock);
6108 }
6109 /* Compat-code for transition, will disappear. */
6110 intel_crtc->config.dpll.n = clock.n;
6111 intel_crtc->config.dpll.m1 = clock.m1;
6112 intel_crtc->config.dpll.m2 = clock.m2;
6113 intel_crtc->config.dpll.p1 = clock.p1;
6114 intel_crtc->config.dpll.p2 = clock.p2;
6115 }
6116
6117 if (IS_GEN2(dev)) {
6118 i8xx_update_pll(intel_crtc,
6119 has_reduced_clock ? &reduced_clock : NULL,
6120 num_connectors);
6121 } else if (IS_CHERRYVIEW(dev)) {
6122 chv_update_pll(intel_crtc);
6123 } else if (IS_VALLEYVIEW(dev)) {
6124 vlv_update_pll(intel_crtc);
6125 } else {
6126 i9xx_update_pll(intel_crtc,
6127 has_reduced_clock ? &reduced_clock : NULL,
6128 num_connectors);
6129 }
6130
6131 return 0;
6132 }
6133
6134 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6135 struct intel_crtc_config *pipe_config)
6136 {
6137 struct drm_device *dev = crtc->base.dev;
6138 struct drm_i915_private *dev_priv = dev->dev_private;
6139 uint32_t tmp;
6140
6141 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6142 return;
6143
6144 tmp = I915_READ(PFIT_CONTROL);
6145 if (!(tmp & PFIT_ENABLE))
6146 return;
6147
6148 /* Check whether the pfit is attached to our pipe. */
6149 if (INTEL_INFO(dev)->gen < 4) {
6150 if (crtc->pipe != PIPE_B)
6151 return;
6152 } else {
6153 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6154 return;
6155 }
6156
6157 pipe_config->gmch_pfit.control = tmp;
6158 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6159 if (INTEL_INFO(dev)->gen < 5)
6160 pipe_config->gmch_pfit.lvds_border_bits =
6161 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6162 }
6163
6164 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6165 struct intel_crtc_config *pipe_config)
6166 {
6167 struct drm_device *dev = crtc->base.dev;
6168 struct drm_i915_private *dev_priv = dev->dev_private;
6169 int pipe = pipe_config->cpu_transcoder;
6170 intel_clock_t clock;
6171 u32 mdiv;
6172 int refclk = 100000;
6173
6174 /* In case of MIPI DPLL will not even be used */
6175 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6176 return;
6177
6178 mutex_lock(&dev_priv->dpio_lock);
6179 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6180 mutex_unlock(&dev_priv->dpio_lock);
6181
6182 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6183 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6184 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6185 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6186 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6187
6188 vlv_clock(refclk, &clock);
6189
6190 /* clock.dot is the fast clock */
6191 pipe_config->port_clock = clock.dot / 5;
6192 }
6193
6194 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6195 struct intel_plane_config *plane_config)
6196 {
6197 struct drm_device *dev = crtc->base.dev;
6198 struct drm_i915_private *dev_priv = dev->dev_private;
6199 u32 val, base, offset;
6200 int pipe = crtc->pipe, plane = crtc->plane;
6201 int fourcc, pixel_format;
6202 int aligned_height;
6203
6204 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6205 if (!crtc->base.primary->fb) {
6206 DRM_DEBUG_KMS("failed to alloc fb\n");
6207 return;
6208 }
6209
6210 val = I915_READ(DSPCNTR(plane));
6211
6212 if (INTEL_INFO(dev)->gen >= 4)
6213 if (val & DISPPLANE_TILED)
6214 plane_config->tiled = true;
6215
6216 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6217 fourcc = intel_format_to_fourcc(pixel_format);
6218 crtc->base.primary->fb->pixel_format = fourcc;
6219 crtc->base.primary->fb->bits_per_pixel =
6220 drm_format_plane_cpp(fourcc, 0) * 8;
6221
6222 if (INTEL_INFO(dev)->gen >= 4) {
6223 if (plane_config->tiled)
6224 offset = I915_READ(DSPTILEOFF(plane));
6225 else
6226 offset = I915_READ(DSPLINOFF(plane));
6227 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6228 } else {
6229 base = I915_READ(DSPADDR(plane));
6230 }
6231 plane_config->base = base;
6232
6233 val = I915_READ(PIPESRC(pipe));
6234 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6235 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6236
6237 val = I915_READ(DSPSTRIDE(pipe));
6238 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6239
6240 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6241 plane_config->tiled);
6242
6243 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6244 aligned_height);
6245
6246 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6247 pipe, plane, crtc->base.primary->fb->width,
6248 crtc->base.primary->fb->height,
6249 crtc->base.primary->fb->bits_per_pixel, base,
6250 crtc->base.primary->fb->pitches[0],
6251 plane_config->size);
6252
6253 }
6254
6255 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6256 struct intel_crtc_config *pipe_config)
6257 {
6258 struct drm_device *dev = crtc->base.dev;
6259 struct drm_i915_private *dev_priv = dev->dev_private;
6260 int pipe = pipe_config->cpu_transcoder;
6261 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6262 intel_clock_t clock;
6263 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6264 int refclk = 100000;
6265
6266 mutex_lock(&dev_priv->dpio_lock);
6267 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6268 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6269 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6270 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6271 mutex_unlock(&dev_priv->dpio_lock);
6272
6273 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6274 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6275 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6276 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6277 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6278
6279 chv_clock(refclk, &clock);
6280
6281 /* clock.dot is the fast clock */
6282 pipe_config->port_clock = clock.dot / 5;
6283 }
6284
6285 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6286 struct intel_crtc_config *pipe_config)
6287 {
6288 struct drm_device *dev = crtc->base.dev;
6289 struct drm_i915_private *dev_priv = dev->dev_private;
6290 uint32_t tmp;
6291
6292 if (!intel_display_power_enabled(dev_priv,
6293 POWER_DOMAIN_PIPE(crtc->pipe)))
6294 return false;
6295
6296 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6297 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6298
6299 tmp = I915_READ(PIPECONF(crtc->pipe));
6300 if (!(tmp & PIPECONF_ENABLE))
6301 return false;
6302
6303 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6304 switch (tmp & PIPECONF_BPC_MASK) {
6305 case PIPECONF_6BPC:
6306 pipe_config->pipe_bpp = 18;
6307 break;
6308 case PIPECONF_8BPC:
6309 pipe_config->pipe_bpp = 24;
6310 break;
6311 case PIPECONF_10BPC:
6312 pipe_config->pipe_bpp = 30;
6313 break;
6314 default:
6315 break;
6316 }
6317 }
6318
6319 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6320 pipe_config->limited_color_range = true;
6321
6322 if (INTEL_INFO(dev)->gen < 4)
6323 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6324
6325 intel_get_pipe_timings(crtc, pipe_config);
6326
6327 i9xx_get_pfit_config(crtc, pipe_config);
6328
6329 if (INTEL_INFO(dev)->gen >= 4) {
6330 tmp = I915_READ(DPLL_MD(crtc->pipe));
6331 pipe_config->pixel_multiplier =
6332 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6333 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6334 pipe_config->dpll_hw_state.dpll_md = tmp;
6335 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6336 tmp = I915_READ(DPLL(crtc->pipe));
6337 pipe_config->pixel_multiplier =
6338 ((tmp & SDVO_MULTIPLIER_MASK)
6339 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6340 } else {
6341 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6342 * port and will be fixed up in the encoder->get_config
6343 * function. */
6344 pipe_config->pixel_multiplier = 1;
6345 }
6346 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6347 if (!IS_VALLEYVIEW(dev)) {
6348 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6349 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6350 } else {
6351 /* Mask out read-only status bits. */
6352 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6353 DPLL_PORTC_READY_MASK |
6354 DPLL_PORTB_READY_MASK);
6355 }
6356
6357 if (IS_CHERRYVIEW(dev))
6358 chv_crtc_clock_get(crtc, pipe_config);
6359 else if (IS_VALLEYVIEW(dev))
6360 vlv_crtc_clock_get(crtc, pipe_config);
6361 else
6362 i9xx_crtc_clock_get(crtc, pipe_config);
6363
6364 return true;
6365 }
6366
6367 static void ironlake_init_pch_refclk(struct drm_device *dev)
6368 {
6369 struct drm_i915_private *dev_priv = dev->dev_private;
6370 struct intel_encoder *encoder;
6371 u32 val, final;
6372 bool has_lvds = false;
6373 bool has_cpu_edp = false;
6374 bool has_panel = false;
6375 bool has_ck505 = false;
6376 bool can_ssc = false;
6377
6378 /* We need to take the global config into account */
6379 for_each_intel_encoder(dev, encoder) {
6380 switch (encoder->type) {
6381 case INTEL_OUTPUT_LVDS:
6382 has_panel = true;
6383 has_lvds = true;
6384 break;
6385 case INTEL_OUTPUT_EDP:
6386 has_panel = true;
6387 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6388 has_cpu_edp = true;
6389 break;
6390 }
6391 }
6392
6393 if (HAS_PCH_IBX(dev)) {
6394 has_ck505 = dev_priv->vbt.display_clock_mode;
6395 can_ssc = has_ck505;
6396 } else {
6397 has_ck505 = false;
6398 can_ssc = true;
6399 }
6400
6401 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6402 has_panel, has_lvds, has_ck505);
6403
6404 /* Ironlake: try to setup display ref clock before DPLL
6405 * enabling. This is only under driver's control after
6406 * PCH B stepping, previous chipset stepping should be
6407 * ignoring this setting.
6408 */
6409 val = I915_READ(PCH_DREF_CONTROL);
6410
6411 /* As we must carefully and slowly disable/enable each source in turn,
6412 * compute the final state we want first and check if we need to
6413 * make any changes at all.
6414 */
6415 final = val;
6416 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6417 if (has_ck505)
6418 final |= DREF_NONSPREAD_CK505_ENABLE;
6419 else
6420 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6421
6422 final &= ~DREF_SSC_SOURCE_MASK;
6423 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6424 final &= ~DREF_SSC1_ENABLE;
6425
6426 if (has_panel) {
6427 final |= DREF_SSC_SOURCE_ENABLE;
6428
6429 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6430 final |= DREF_SSC1_ENABLE;
6431
6432 if (has_cpu_edp) {
6433 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6434 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6435 else
6436 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6437 } else
6438 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6439 } else {
6440 final |= DREF_SSC_SOURCE_DISABLE;
6441 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6442 }
6443
6444 if (final == val)
6445 return;
6446
6447 /* Always enable nonspread source */
6448 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6449
6450 if (has_ck505)
6451 val |= DREF_NONSPREAD_CK505_ENABLE;
6452 else
6453 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6454
6455 if (has_panel) {
6456 val &= ~DREF_SSC_SOURCE_MASK;
6457 val |= DREF_SSC_SOURCE_ENABLE;
6458
6459 /* SSC must be turned on before enabling the CPU output */
6460 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6461 DRM_DEBUG_KMS("Using SSC on panel\n");
6462 val |= DREF_SSC1_ENABLE;
6463 } else
6464 val &= ~DREF_SSC1_ENABLE;
6465
6466 /* Get SSC going before enabling the outputs */
6467 I915_WRITE(PCH_DREF_CONTROL, val);
6468 POSTING_READ(PCH_DREF_CONTROL);
6469 udelay(200);
6470
6471 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6472
6473 /* Enable CPU source on CPU attached eDP */
6474 if (has_cpu_edp) {
6475 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6476 DRM_DEBUG_KMS("Using SSC on eDP\n");
6477 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6478 } else
6479 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6480 } else
6481 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6482
6483 I915_WRITE(PCH_DREF_CONTROL, val);
6484 POSTING_READ(PCH_DREF_CONTROL);
6485 udelay(200);
6486 } else {
6487 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6488
6489 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6490
6491 /* Turn off CPU output */
6492 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6493
6494 I915_WRITE(PCH_DREF_CONTROL, val);
6495 POSTING_READ(PCH_DREF_CONTROL);
6496 udelay(200);
6497
6498 /* Turn off the SSC source */
6499 val &= ~DREF_SSC_SOURCE_MASK;
6500 val |= DREF_SSC_SOURCE_DISABLE;
6501
6502 /* Turn off SSC1 */
6503 val &= ~DREF_SSC1_ENABLE;
6504
6505 I915_WRITE(PCH_DREF_CONTROL, val);
6506 POSTING_READ(PCH_DREF_CONTROL);
6507 udelay(200);
6508 }
6509
6510 BUG_ON(val != final);
6511 }
6512
6513 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6514 {
6515 uint32_t tmp;
6516
6517 tmp = I915_READ(SOUTH_CHICKEN2);
6518 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6519 I915_WRITE(SOUTH_CHICKEN2, tmp);
6520
6521 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6522 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6523 DRM_ERROR("FDI mPHY reset assert timeout\n");
6524
6525 tmp = I915_READ(SOUTH_CHICKEN2);
6526 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6527 I915_WRITE(SOUTH_CHICKEN2, tmp);
6528
6529 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6530 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6531 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6532 }
6533
6534 /* WaMPhyProgramming:hsw */
6535 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6536 {
6537 uint32_t tmp;
6538
6539 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6540 tmp &= ~(0xFF << 24);
6541 tmp |= (0x12 << 24);
6542 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6543
6544 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6545 tmp |= (1 << 11);
6546 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6547
6548 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6549 tmp |= (1 << 11);
6550 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6551
6552 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6553 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6554 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6555
6556 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6557 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6558 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6559
6560 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6561 tmp &= ~(7 << 13);
6562 tmp |= (5 << 13);
6563 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6564
6565 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6566 tmp &= ~(7 << 13);
6567 tmp |= (5 << 13);
6568 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6569
6570 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6571 tmp &= ~0xFF;
6572 tmp |= 0x1C;
6573 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6574
6575 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6576 tmp &= ~0xFF;
6577 tmp |= 0x1C;
6578 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6579
6580 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6581 tmp &= ~(0xFF << 16);
6582 tmp |= (0x1C << 16);
6583 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6584
6585 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6586 tmp &= ~(0xFF << 16);
6587 tmp |= (0x1C << 16);
6588 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6589
6590 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6591 tmp |= (1 << 27);
6592 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6593
6594 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6595 tmp |= (1 << 27);
6596 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6597
6598 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6599 tmp &= ~(0xF << 28);
6600 tmp |= (4 << 28);
6601 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6602
6603 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6604 tmp &= ~(0xF << 28);
6605 tmp |= (4 << 28);
6606 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6607 }
6608
6609 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6610 * Programming" based on the parameters passed:
6611 * - Sequence to enable CLKOUT_DP
6612 * - Sequence to enable CLKOUT_DP without spread
6613 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6614 */
6615 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6616 bool with_fdi)
6617 {
6618 struct drm_i915_private *dev_priv = dev->dev_private;
6619 uint32_t reg, tmp;
6620
6621 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6622 with_spread = true;
6623 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6624 with_fdi, "LP PCH doesn't have FDI\n"))
6625 with_fdi = false;
6626
6627 mutex_lock(&dev_priv->dpio_lock);
6628
6629 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6630 tmp &= ~SBI_SSCCTL_DISABLE;
6631 tmp |= SBI_SSCCTL_PATHALT;
6632 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6633
6634 udelay(24);
6635
6636 if (with_spread) {
6637 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6638 tmp &= ~SBI_SSCCTL_PATHALT;
6639 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6640
6641 if (with_fdi) {
6642 lpt_reset_fdi_mphy(dev_priv);
6643 lpt_program_fdi_mphy(dev_priv);
6644 }
6645 }
6646
6647 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6648 SBI_GEN0 : SBI_DBUFF0;
6649 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6650 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6651 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6652
6653 mutex_unlock(&dev_priv->dpio_lock);
6654 }
6655
6656 /* Sequence to disable CLKOUT_DP */
6657 static void lpt_disable_clkout_dp(struct drm_device *dev)
6658 {
6659 struct drm_i915_private *dev_priv = dev->dev_private;
6660 uint32_t reg, tmp;
6661
6662 mutex_lock(&dev_priv->dpio_lock);
6663
6664 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6665 SBI_GEN0 : SBI_DBUFF0;
6666 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6667 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6668 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6669
6670 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6671 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6672 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6673 tmp |= SBI_SSCCTL_PATHALT;
6674 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6675 udelay(32);
6676 }
6677 tmp |= SBI_SSCCTL_DISABLE;
6678 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6679 }
6680
6681 mutex_unlock(&dev_priv->dpio_lock);
6682 }
6683
6684 static void lpt_init_pch_refclk(struct drm_device *dev)
6685 {
6686 struct intel_encoder *encoder;
6687 bool has_vga = false;
6688
6689 for_each_intel_encoder(dev, encoder) {
6690 switch (encoder->type) {
6691 case INTEL_OUTPUT_ANALOG:
6692 has_vga = true;
6693 break;
6694 }
6695 }
6696
6697 if (has_vga)
6698 lpt_enable_clkout_dp(dev, true, true);
6699 else
6700 lpt_disable_clkout_dp(dev);
6701 }
6702
6703 /*
6704 * Initialize reference clocks when the driver loads
6705 */
6706 void intel_init_pch_refclk(struct drm_device *dev)
6707 {
6708 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6709 ironlake_init_pch_refclk(dev);
6710 else if (HAS_PCH_LPT(dev))
6711 lpt_init_pch_refclk(dev);
6712 }
6713
6714 static int ironlake_get_refclk(struct drm_crtc *crtc)
6715 {
6716 struct drm_device *dev = crtc->dev;
6717 struct drm_i915_private *dev_priv = dev->dev_private;
6718 struct intel_encoder *encoder;
6719 int num_connectors = 0;
6720 bool is_lvds = false;
6721
6722 for_each_encoder_on_crtc(dev, crtc, encoder) {
6723 switch (encoder->type) {
6724 case INTEL_OUTPUT_LVDS:
6725 is_lvds = true;
6726 break;
6727 }
6728 num_connectors++;
6729 }
6730
6731 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6732 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6733 dev_priv->vbt.lvds_ssc_freq);
6734 return dev_priv->vbt.lvds_ssc_freq;
6735 }
6736
6737 return 120000;
6738 }
6739
6740 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6741 {
6742 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6744 int pipe = intel_crtc->pipe;
6745 uint32_t val;
6746
6747 val = 0;
6748
6749 switch (intel_crtc->config.pipe_bpp) {
6750 case 18:
6751 val |= PIPECONF_6BPC;
6752 break;
6753 case 24:
6754 val |= PIPECONF_8BPC;
6755 break;
6756 case 30:
6757 val |= PIPECONF_10BPC;
6758 break;
6759 case 36:
6760 val |= PIPECONF_12BPC;
6761 break;
6762 default:
6763 /* Case prevented by intel_choose_pipe_bpp_dither. */
6764 BUG();
6765 }
6766
6767 if (intel_crtc->config.dither)
6768 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6769
6770 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6771 val |= PIPECONF_INTERLACED_ILK;
6772 else
6773 val |= PIPECONF_PROGRESSIVE;
6774
6775 if (intel_crtc->config.limited_color_range)
6776 val |= PIPECONF_COLOR_RANGE_SELECT;
6777
6778 I915_WRITE(PIPECONF(pipe), val);
6779 POSTING_READ(PIPECONF(pipe));
6780 }
6781
6782 /*
6783 * Set up the pipe CSC unit.
6784 *
6785 * Currently only full range RGB to limited range RGB conversion
6786 * is supported, but eventually this should handle various
6787 * RGB<->YCbCr scenarios as well.
6788 */
6789 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6790 {
6791 struct drm_device *dev = crtc->dev;
6792 struct drm_i915_private *dev_priv = dev->dev_private;
6793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6794 int pipe = intel_crtc->pipe;
6795 uint16_t coeff = 0x7800; /* 1.0 */
6796
6797 /*
6798 * TODO: Check what kind of values actually come out of the pipe
6799 * with these coeff/postoff values and adjust to get the best
6800 * accuracy. Perhaps we even need to take the bpc value into
6801 * consideration.
6802 */
6803
6804 if (intel_crtc->config.limited_color_range)
6805 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6806
6807 /*
6808 * GY/GU and RY/RU should be the other way around according
6809 * to BSpec, but reality doesn't agree. Just set them up in
6810 * a way that results in the correct picture.
6811 */
6812 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6813 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6814
6815 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6816 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6817
6818 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6819 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6820
6821 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6822 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6823 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6824
6825 if (INTEL_INFO(dev)->gen > 6) {
6826 uint16_t postoff = 0;
6827
6828 if (intel_crtc->config.limited_color_range)
6829 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6830
6831 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6832 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6833 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6834
6835 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6836 } else {
6837 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6838
6839 if (intel_crtc->config.limited_color_range)
6840 mode |= CSC_BLACK_SCREEN_OFFSET;
6841
6842 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6843 }
6844 }
6845
6846 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6847 {
6848 struct drm_device *dev = crtc->dev;
6849 struct drm_i915_private *dev_priv = dev->dev_private;
6850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6851 enum pipe pipe = intel_crtc->pipe;
6852 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6853 uint32_t val;
6854
6855 val = 0;
6856
6857 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6858 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6859
6860 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6861 val |= PIPECONF_INTERLACED_ILK;
6862 else
6863 val |= PIPECONF_PROGRESSIVE;
6864
6865 I915_WRITE(PIPECONF(cpu_transcoder), val);
6866 POSTING_READ(PIPECONF(cpu_transcoder));
6867
6868 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6869 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6870
6871 if (IS_BROADWELL(dev)) {
6872 val = 0;
6873
6874 switch (intel_crtc->config.pipe_bpp) {
6875 case 18:
6876 val |= PIPEMISC_DITHER_6_BPC;
6877 break;
6878 case 24:
6879 val |= PIPEMISC_DITHER_8_BPC;
6880 break;
6881 case 30:
6882 val |= PIPEMISC_DITHER_10_BPC;
6883 break;
6884 case 36:
6885 val |= PIPEMISC_DITHER_12_BPC;
6886 break;
6887 default:
6888 /* Case prevented by pipe_config_set_bpp. */
6889 BUG();
6890 }
6891
6892 if (intel_crtc->config.dither)
6893 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6894
6895 I915_WRITE(PIPEMISC(pipe), val);
6896 }
6897 }
6898
6899 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6900 intel_clock_t *clock,
6901 bool *has_reduced_clock,
6902 intel_clock_t *reduced_clock)
6903 {
6904 struct drm_device *dev = crtc->dev;
6905 struct drm_i915_private *dev_priv = dev->dev_private;
6906 struct intel_encoder *intel_encoder;
6907 int refclk;
6908 const intel_limit_t *limit;
6909 bool ret, is_lvds = false;
6910
6911 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6912 switch (intel_encoder->type) {
6913 case INTEL_OUTPUT_LVDS:
6914 is_lvds = true;
6915 break;
6916 }
6917 }
6918
6919 refclk = ironlake_get_refclk(crtc);
6920
6921 /*
6922 * Returns a set of divisors for the desired target clock with the given
6923 * refclk, or FALSE. The returned values represent the clock equation:
6924 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6925 */
6926 limit = intel_limit(crtc, refclk);
6927 ret = dev_priv->display.find_dpll(limit, crtc,
6928 to_intel_crtc(crtc)->config.port_clock,
6929 refclk, NULL, clock);
6930 if (!ret)
6931 return false;
6932
6933 if (is_lvds && dev_priv->lvds_downclock_avail) {
6934 /*
6935 * Ensure we match the reduced clock's P to the target clock.
6936 * If the clocks don't match, we can't switch the display clock
6937 * by using the FP0/FP1. In such case we will disable the LVDS
6938 * downclock feature.
6939 */
6940 *has_reduced_clock =
6941 dev_priv->display.find_dpll(limit, crtc,
6942 dev_priv->lvds_downclock,
6943 refclk, clock,
6944 reduced_clock);
6945 }
6946
6947 return true;
6948 }
6949
6950 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6951 {
6952 /*
6953 * Account for spread spectrum to avoid
6954 * oversubscribing the link. Max center spread
6955 * is 2.5%; use 5% for safety's sake.
6956 */
6957 u32 bps = target_clock * bpp * 21 / 20;
6958 return DIV_ROUND_UP(bps, link_bw * 8);
6959 }
6960
6961 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6962 {
6963 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6964 }
6965
6966 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6967 u32 *fp,
6968 intel_clock_t *reduced_clock, u32 *fp2)
6969 {
6970 struct drm_crtc *crtc = &intel_crtc->base;
6971 struct drm_device *dev = crtc->dev;
6972 struct drm_i915_private *dev_priv = dev->dev_private;
6973 struct intel_encoder *intel_encoder;
6974 uint32_t dpll;
6975 int factor, num_connectors = 0;
6976 bool is_lvds = false, is_sdvo = false;
6977
6978 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6979 switch (intel_encoder->type) {
6980 case INTEL_OUTPUT_LVDS:
6981 is_lvds = true;
6982 break;
6983 case INTEL_OUTPUT_SDVO:
6984 case INTEL_OUTPUT_HDMI:
6985 is_sdvo = true;
6986 break;
6987 }
6988
6989 num_connectors++;
6990 }
6991
6992 /* Enable autotuning of the PLL clock (if permissible) */
6993 factor = 21;
6994 if (is_lvds) {
6995 if ((intel_panel_use_ssc(dev_priv) &&
6996 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6997 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6998 factor = 25;
6999 } else if (intel_crtc->config.sdvo_tv_clock)
7000 factor = 20;
7001
7002 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7003 *fp |= FP_CB_TUNE;
7004
7005 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7006 *fp2 |= FP_CB_TUNE;
7007
7008 dpll = 0;
7009
7010 if (is_lvds)
7011 dpll |= DPLLB_MODE_LVDS;
7012 else
7013 dpll |= DPLLB_MODE_DAC_SERIAL;
7014
7015 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7016 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7017
7018 if (is_sdvo)
7019 dpll |= DPLL_SDVO_HIGH_SPEED;
7020 if (intel_crtc->config.has_dp_encoder)
7021 dpll |= DPLL_SDVO_HIGH_SPEED;
7022
7023 /* compute bitmask from p1 value */
7024 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7025 /* also FPA1 */
7026 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7027
7028 switch (intel_crtc->config.dpll.p2) {
7029 case 5:
7030 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7031 break;
7032 case 7:
7033 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7034 break;
7035 case 10:
7036 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7037 break;
7038 case 14:
7039 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7040 break;
7041 }
7042
7043 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7044 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7045 else
7046 dpll |= PLL_REF_INPUT_DREFCLK;
7047
7048 return dpll | DPLL_VCO_ENABLE;
7049 }
7050
7051 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7052 int x, int y,
7053 struct drm_framebuffer *fb)
7054 {
7055 struct drm_device *dev = crtc->dev;
7056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7057 int num_connectors = 0;
7058 intel_clock_t clock, reduced_clock;
7059 u32 dpll = 0, fp = 0, fp2 = 0;
7060 bool ok, has_reduced_clock = false;
7061 bool is_lvds = false;
7062 struct intel_encoder *encoder;
7063 struct intel_shared_dpll *pll;
7064
7065 for_each_encoder_on_crtc(dev, crtc, encoder) {
7066 switch (encoder->type) {
7067 case INTEL_OUTPUT_LVDS:
7068 is_lvds = true;
7069 break;
7070 }
7071
7072 num_connectors++;
7073 }
7074
7075 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7076 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7077
7078 ok = ironlake_compute_clocks(crtc, &clock,
7079 &has_reduced_clock, &reduced_clock);
7080 if (!ok && !intel_crtc->config.clock_set) {
7081 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7082 return -EINVAL;
7083 }
7084 /* Compat-code for transition, will disappear. */
7085 if (!intel_crtc->config.clock_set) {
7086 intel_crtc->config.dpll.n = clock.n;
7087 intel_crtc->config.dpll.m1 = clock.m1;
7088 intel_crtc->config.dpll.m2 = clock.m2;
7089 intel_crtc->config.dpll.p1 = clock.p1;
7090 intel_crtc->config.dpll.p2 = clock.p2;
7091 }
7092
7093 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7094 if (intel_crtc->config.has_pch_encoder) {
7095 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7096 if (has_reduced_clock)
7097 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7098
7099 dpll = ironlake_compute_dpll(intel_crtc,
7100 &fp, &reduced_clock,
7101 has_reduced_clock ? &fp2 : NULL);
7102
7103 intel_crtc->config.dpll_hw_state.dpll = dpll;
7104 intel_crtc->config.dpll_hw_state.fp0 = fp;
7105 if (has_reduced_clock)
7106 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7107 else
7108 intel_crtc->config.dpll_hw_state.fp1 = fp;
7109
7110 pll = intel_get_shared_dpll(intel_crtc);
7111 if (pll == NULL) {
7112 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7113 pipe_name(intel_crtc->pipe));
7114 return -EINVAL;
7115 }
7116 } else
7117 intel_put_shared_dpll(intel_crtc);
7118
7119 if (is_lvds && has_reduced_clock && i915.powersave)
7120 intel_crtc->lowfreq_avail = true;
7121 else
7122 intel_crtc->lowfreq_avail = false;
7123
7124 return 0;
7125 }
7126
7127 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7128 struct intel_link_m_n *m_n)
7129 {
7130 struct drm_device *dev = crtc->base.dev;
7131 struct drm_i915_private *dev_priv = dev->dev_private;
7132 enum pipe pipe = crtc->pipe;
7133
7134 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7135 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7136 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7137 & ~TU_SIZE_MASK;
7138 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7139 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7140 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7141 }
7142
7143 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7144 enum transcoder transcoder,
7145 struct intel_link_m_n *m_n,
7146 struct intel_link_m_n *m2_n2)
7147 {
7148 struct drm_device *dev = crtc->base.dev;
7149 struct drm_i915_private *dev_priv = dev->dev_private;
7150 enum pipe pipe = crtc->pipe;
7151
7152 if (INTEL_INFO(dev)->gen >= 5) {
7153 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7154 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7155 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7156 & ~TU_SIZE_MASK;
7157 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7158 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7159 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7160 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7161 * gen < 8) and if DRRS is supported (to make sure the
7162 * registers are not unnecessarily read).
7163 */
7164 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7165 crtc->config.has_drrs) {
7166 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7167 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7168 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7169 & ~TU_SIZE_MASK;
7170 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7171 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7172 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7173 }
7174 } else {
7175 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7176 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7177 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7178 & ~TU_SIZE_MASK;
7179 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7180 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7181 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7182 }
7183 }
7184
7185 void intel_dp_get_m_n(struct intel_crtc *crtc,
7186 struct intel_crtc_config *pipe_config)
7187 {
7188 if (crtc->config.has_pch_encoder)
7189 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7190 else
7191 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7192 &pipe_config->dp_m_n,
7193 &pipe_config->dp_m2_n2);
7194 }
7195
7196 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7197 struct intel_crtc_config *pipe_config)
7198 {
7199 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7200 &pipe_config->fdi_m_n, NULL);
7201 }
7202
7203 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7204 struct intel_crtc_config *pipe_config)
7205 {
7206 struct drm_device *dev = crtc->base.dev;
7207 struct drm_i915_private *dev_priv = dev->dev_private;
7208 uint32_t tmp;
7209
7210 tmp = I915_READ(PF_CTL(crtc->pipe));
7211
7212 if (tmp & PF_ENABLE) {
7213 pipe_config->pch_pfit.enabled = true;
7214 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7215 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7216
7217 /* We currently do not free assignements of panel fitters on
7218 * ivb/hsw (since we don't use the higher upscaling modes which
7219 * differentiates them) so just WARN about this case for now. */
7220 if (IS_GEN7(dev)) {
7221 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7222 PF_PIPE_SEL_IVB(crtc->pipe));
7223 }
7224 }
7225 }
7226
7227 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7228 struct intel_plane_config *plane_config)
7229 {
7230 struct drm_device *dev = crtc->base.dev;
7231 struct drm_i915_private *dev_priv = dev->dev_private;
7232 u32 val, base, offset;
7233 int pipe = crtc->pipe, plane = crtc->plane;
7234 int fourcc, pixel_format;
7235 int aligned_height;
7236
7237 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7238 if (!crtc->base.primary->fb) {
7239 DRM_DEBUG_KMS("failed to alloc fb\n");
7240 return;
7241 }
7242
7243 val = I915_READ(DSPCNTR(plane));
7244
7245 if (INTEL_INFO(dev)->gen >= 4)
7246 if (val & DISPPLANE_TILED)
7247 plane_config->tiled = true;
7248
7249 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7250 fourcc = intel_format_to_fourcc(pixel_format);
7251 crtc->base.primary->fb->pixel_format = fourcc;
7252 crtc->base.primary->fb->bits_per_pixel =
7253 drm_format_plane_cpp(fourcc, 0) * 8;
7254
7255 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7256 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7257 offset = I915_READ(DSPOFFSET(plane));
7258 } else {
7259 if (plane_config->tiled)
7260 offset = I915_READ(DSPTILEOFF(plane));
7261 else
7262 offset = I915_READ(DSPLINOFF(plane));
7263 }
7264 plane_config->base = base;
7265
7266 val = I915_READ(PIPESRC(pipe));
7267 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7268 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7269
7270 val = I915_READ(DSPSTRIDE(pipe));
7271 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7272
7273 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7274 plane_config->tiled);
7275
7276 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7277 aligned_height);
7278
7279 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7280 pipe, plane, crtc->base.primary->fb->width,
7281 crtc->base.primary->fb->height,
7282 crtc->base.primary->fb->bits_per_pixel, base,
7283 crtc->base.primary->fb->pitches[0],
7284 plane_config->size);
7285 }
7286
7287 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7288 struct intel_crtc_config *pipe_config)
7289 {
7290 struct drm_device *dev = crtc->base.dev;
7291 struct drm_i915_private *dev_priv = dev->dev_private;
7292 uint32_t tmp;
7293
7294 if (!intel_display_power_enabled(dev_priv,
7295 POWER_DOMAIN_PIPE(crtc->pipe)))
7296 return false;
7297
7298 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7299 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7300
7301 tmp = I915_READ(PIPECONF(crtc->pipe));
7302 if (!(tmp & PIPECONF_ENABLE))
7303 return false;
7304
7305 switch (tmp & PIPECONF_BPC_MASK) {
7306 case PIPECONF_6BPC:
7307 pipe_config->pipe_bpp = 18;
7308 break;
7309 case PIPECONF_8BPC:
7310 pipe_config->pipe_bpp = 24;
7311 break;
7312 case PIPECONF_10BPC:
7313 pipe_config->pipe_bpp = 30;
7314 break;
7315 case PIPECONF_12BPC:
7316 pipe_config->pipe_bpp = 36;
7317 break;
7318 default:
7319 break;
7320 }
7321
7322 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7323 pipe_config->limited_color_range = true;
7324
7325 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7326 struct intel_shared_dpll *pll;
7327
7328 pipe_config->has_pch_encoder = true;
7329
7330 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7331 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7332 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7333
7334 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7335
7336 if (HAS_PCH_IBX(dev_priv->dev)) {
7337 pipe_config->shared_dpll =
7338 (enum intel_dpll_id) crtc->pipe;
7339 } else {
7340 tmp = I915_READ(PCH_DPLL_SEL);
7341 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7342 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7343 else
7344 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7345 }
7346
7347 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7348
7349 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7350 &pipe_config->dpll_hw_state));
7351
7352 tmp = pipe_config->dpll_hw_state.dpll;
7353 pipe_config->pixel_multiplier =
7354 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7355 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7356
7357 ironlake_pch_clock_get(crtc, pipe_config);
7358 } else {
7359 pipe_config->pixel_multiplier = 1;
7360 }
7361
7362 intel_get_pipe_timings(crtc, pipe_config);
7363
7364 ironlake_get_pfit_config(crtc, pipe_config);
7365
7366 return true;
7367 }
7368
7369 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7370 {
7371 struct drm_device *dev = dev_priv->dev;
7372 struct intel_crtc *crtc;
7373
7374 for_each_intel_crtc(dev, crtc)
7375 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7376 pipe_name(crtc->pipe));
7377
7378 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7379 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7380 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7381 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7382 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7383 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7384 "CPU PWM1 enabled\n");
7385 if (IS_HASWELL(dev))
7386 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7387 "CPU PWM2 enabled\n");
7388 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7389 "PCH PWM1 enabled\n");
7390 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7391 "Utility pin enabled\n");
7392 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7393
7394 /*
7395 * In theory we can still leave IRQs enabled, as long as only the HPD
7396 * interrupts remain enabled. We used to check for that, but since it's
7397 * gen-specific and since we only disable LCPLL after we fully disable
7398 * the interrupts, the check below should be enough.
7399 */
7400 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7401 }
7402
7403 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7404 {
7405 struct drm_device *dev = dev_priv->dev;
7406
7407 if (IS_HASWELL(dev))
7408 return I915_READ(D_COMP_HSW);
7409 else
7410 return I915_READ(D_COMP_BDW);
7411 }
7412
7413 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7414 {
7415 struct drm_device *dev = dev_priv->dev;
7416
7417 if (IS_HASWELL(dev)) {
7418 mutex_lock(&dev_priv->rps.hw_lock);
7419 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7420 val))
7421 DRM_ERROR("Failed to write to D_COMP\n");
7422 mutex_unlock(&dev_priv->rps.hw_lock);
7423 } else {
7424 I915_WRITE(D_COMP_BDW, val);
7425 POSTING_READ(D_COMP_BDW);
7426 }
7427 }
7428
7429 /*
7430 * This function implements pieces of two sequences from BSpec:
7431 * - Sequence for display software to disable LCPLL
7432 * - Sequence for display software to allow package C8+
7433 * The steps implemented here are just the steps that actually touch the LCPLL
7434 * register. Callers should take care of disabling all the display engine
7435 * functions, doing the mode unset, fixing interrupts, etc.
7436 */
7437 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7438 bool switch_to_fclk, bool allow_power_down)
7439 {
7440 uint32_t val;
7441
7442 assert_can_disable_lcpll(dev_priv);
7443
7444 val = I915_READ(LCPLL_CTL);
7445
7446 if (switch_to_fclk) {
7447 val |= LCPLL_CD_SOURCE_FCLK;
7448 I915_WRITE(LCPLL_CTL, val);
7449
7450 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7451 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7452 DRM_ERROR("Switching to FCLK failed\n");
7453
7454 val = I915_READ(LCPLL_CTL);
7455 }
7456
7457 val |= LCPLL_PLL_DISABLE;
7458 I915_WRITE(LCPLL_CTL, val);
7459 POSTING_READ(LCPLL_CTL);
7460
7461 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7462 DRM_ERROR("LCPLL still locked\n");
7463
7464 val = hsw_read_dcomp(dev_priv);
7465 val |= D_COMP_COMP_DISABLE;
7466 hsw_write_dcomp(dev_priv, val);
7467 ndelay(100);
7468
7469 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7470 1))
7471 DRM_ERROR("D_COMP RCOMP still in progress\n");
7472
7473 if (allow_power_down) {
7474 val = I915_READ(LCPLL_CTL);
7475 val |= LCPLL_POWER_DOWN_ALLOW;
7476 I915_WRITE(LCPLL_CTL, val);
7477 POSTING_READ(LCPLL_CTL);
7478 }
7479 }
7480
7481 /*
7482 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7483 * source.
7484 */
7485 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7486 {
7487 uint32_t val;
7488 unsigned long irqflags;
7489
7490 val = I915_READ(LCPLL_CTL);
7491
7492 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7493 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7494 return;
7495
7496 /*
7497 * Make sure we're not on PC8 state before disabling PC8, otherwise
7498 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7499 *
7500 * The other problem is that hsw_restore_lcpll() is called as part of
7501 * the runtime PM resume sequence, so we can't just call
7502 * gen6_gt_force_wake_get() because that function calls
7503 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7504 * while we are on the resume sequence. So to solve this problem we have
7505 * to call special forcewake code that doesn't touch runtime PM and
7506 * doesn't enable the forcewake delayed work.
7507 */
7508 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7509 if (dev_priv->uncore.forcewake_count++ == 0)
7510 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7511 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7512
7513 if (val & LCPLL_POWER_DOWN_ALLOW) {
7514 val &= ~LCPLL_POWER_DOWN_ALLOW;
7515 I915_WRITE(LCPLL_CTL, val);
7516 POSTING_READ(LCPLL_CTL);
7517 }
7518
7519 val = hsw_read_dcomp(dev_priv);
7520 val |= D_COMP_COMP_FORCE;
7521 val &= ~D_COMP_COMP_DISABLE;
7522 hsw_write_dcomp(dev_priv, val);
7523
7524 val = I915_READ(LCPLL_CTL);
7525 val &= ~LCPLL_PLL_DISABLE;
7526 I915_WRITE(LCPLL_CTL, val);
7527
7528 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7529 DRM_ERROR("LCPLL not locked yet\n");
7530
7531 if (val & LCPLL_CD_SOURCE_FCLK) {
7532 val = I915_READ(LCPLL_CTL);
7533 val &= ~LCPLL_CD_SOURCE_FCLK;
7534 I915_WRITE(LCPLL_CTL, val);
7535
7536 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7537 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7538 DRM_ERROR("Switching back to LCPLL failed\n");
7539 }
7540
7541 /* See the big comment above. */
7542 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7543 if (--dev_priv->uncore.forcewake_count == 0)
7544 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7545 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7546 }
7547
7548 /*
7549 * Package states C8 and deeper are really deep PC states that can only be
7550 * reached when all the devices on the system allow it, so even if the graphics
7551 * device allows PC8+, it doesn't mean the system will actually get to these
7552 * states. Our driver only allows PC8+ when going into runtime PM.
7553 *
7554 * The requirements for PC8+ are that all the outputs are disabled, the power
7555 * well is disabled and most interrupts are disabled, and these are also
7556 * requirements for runtime PM. When these conditions are met, we manually do
7557 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7558 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7559 * hang the machine.
7560 *
7561 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7562 * the state of some registers, so when we come back from PC8+ we need to
7563 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7564 * need to take care of the registers kept by RC6. Notice that this happens even
7565 * if we don't put the device in PCI D3 state (which is what currently happens
7566 * because of the runtime PM support).
7567 *
7568 * For more, read "Display Sequences for Package C8" on the hardware
7569 * documentation.
7570 */
7571 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7572 {
7573 struct drm_device *dev = dev_priv->dev;
7574 uint32_t val;
7575
7576 DRM_DEBUG_KMS("Enabling package C8+\n");
7577
7578 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7579 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7580 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7581 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7582 }
7583
7584 lpt_disable_clkout_dp(dev);
7585 hsw_disable_lcpll(dev_priv, true, true);
7586 }
7587
7588 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7589 {
7590 struct drm_device *dev = dev_priv->dev;
7591 uint32_t val;
7592
7593 DRM_DEBUG_KMS("Disabling package C8+\n");
7594
7595 hsw_restore_lcpll(dev_priv);
7596 lpt_init_pch_refclk(dev);
7597
7598 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7599 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7600 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7601 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7602 }
7603
7604 intel_prepare_ddi(dev);
7605 }
7606
7607 static void snb_modeset_global_resources(struct drm_device *dev)
7608 {
7609 modeset_update_crtc_power_domains(dev);
7610 }
7611
7612 static void haswell_modeset_global_resources(struct drm_device *dev)
7613 {
7614 modeset_update_crtc_power_domains(dev);
7615 }
7616
7617 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7618 int x, int y,
7619 struct drm_framebuffer *fb)
7620 {
7621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7622
7623 if (!intel_ddi_pll_select(intel_crtc))
7624 return -EINVAL;
7625
7626 intel_crtc->lowfreq_avail = false;
7627
7628 return 0;
7629 }
7630
7631 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7632 enum port port,
7633 struct intel_crtc_config *pipe_config)
7634 {
7635 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7636
7637 switch (pipe_config->ddi_pll_sel) {
7638 case PORT_CLK_SEL_WRPLL1:
7639 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7640 break;
7641 case PORT_CLK_SEL_WRPLL2:
7642 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7643 break;
7644 }
7645 }
7646
7647 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7648 struct intel_crtc_config *pipe_config)
7649 {
7650 struct drm_device *dev = crtc->base.dev;
7651 struct drm_i915_private *dev_priv = dev->dev_private;
7652 struct intel_shared_dpll *pll;
7653 enum port port;
7654 uint32_t tmp;
7655
7656 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7657
7658 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7659
7660 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7661
7662 if (pipe_config->shared_dpll >= 0) {
7663 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7664
7665 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7666 &pipe_config->dpll_hw_state));
7667 }
7668
7669 /*
7670 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7671 * DDI E. So just check whether this pipe is wired to DDI E and whether
7672 * the PCH transcoder is on.
7673 */
7674 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7675 pipe_config->has_pch_encoder = true;
7676
7677 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7678 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7679 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7680
7681 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7682 }
7683 }
7684
7685 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7686 struct intel_crtc_config *pipe_config)
7687 {
7688 struct drm_device *dev = crtc->base.dev;
7689 struct drm_i915_private *dev_priv = dev->dev_private;
7690 enum intel_display_power_domain pfit_domain;
7691 uint32_t tmp;
7692
7693 if (!intel_display_power_enabled(dev_priv,
7694 POWER_DOMAIN_PIPE(crtc->pipe)))
7695 return false;
7696
7697 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7698 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7699
7700 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7701 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7702 enum pipe trans_edp_pipe;
7703 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7704 default:
7705 WARN(1, "unknown pipe linked to edp transcoder\n");
7706 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7707 case TRANS_DDI_EDP_INPUT_A_ON:
7708 trans_edp_pipe = PIPE_A;
7709 break;
7710 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7711 trans_edp_pipe = PIPE_B;
7712 break;
7713 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7714 trans_edp_pipe = PIPE_C;
7715 break;
7716 }
7717
7718 if (trans_edp_pipe == crtc->pipe)
7719 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7720 }
7721
7722 if (!intel_display_power_enabled(dev_priv,
7723 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7724 return false;
7725
7726 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7727 if (!(tmp & PIPECONF_ENABLE))
7728 return false;
7729
7730 haswell_get_ddi_port_state(crtc, pipe_config);
7731
7732 intel_get_pipe_timings(crtc, pipe_config);
7733
7734 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7735 if (intel_display_power_enabled(dev_priv, pfit_domain))
7736 ironlake_get_pfit_config(crtc, pipe_config);
7737
7738 if (IS_HASWELL(dev))
7739 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7740 (I915_READ(IPS_CTL) & IPS_ENABLE);
7741
7742 pipe_config->pixel_multiplier = 1;
7743
7744 return true;
7745 }
7746
7747 static struct {
7748 int clock;
7749 u32 config;
7750 } hdmi_audio_clock[] = {
7751 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7752 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7753 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7754 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7755 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7756 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7757 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7758 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7759 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7760 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7761 };
7762
7763 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7764 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7765 {
7766 int i;
7767
7768 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7769 if (mode->clock == hdmi_audio_clock[i].clock)
7770 break;
7771 }
7772
7773 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7774 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7775 i = 1;
7776 }
7777
7778 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7779 hdmi_audio_clock[i].clock,
7780 hdmi_audio_clock[i].config);
7781
7782 return hdmi_audio_clock[i].config;
7783 }
7784
7785 static bool intel_eld_uptodate(struct drm_connector *connector,
7786 int reg_eldv, uint32_t bits_eldv,
7787 int reg_elda, uint32_t bits_elda,
7788 int reg_edid)
7789 {
7790 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7791 uint8_t *eld = connector->eld;
7792 uint32_t i;
7793
7794 i = I915_READ(reg_eldv);
7795 i &= bits_eldv;
7796
7797 if (!eld[0])
7798 return !i;
7799
7800 if (!i)
7801 return false;
7802
7803 i = I915_READ(reg_elda);
7804 i &= ~bits_elda;
7805 I915_WRITE(reg_elda, i);
7806
7807 for (i = 0; i < eld[2]; i++)
7808 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7809 return false;
7810
7811 return true;
7812 }
7813
7814 static void g4x_write_eld(struct drm_connector *connector,
7815 struct drm_crtc *crtc,
7816 struct drm_display_mode *mode)
7817 {
7818 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7819 uint8_t *eld = connector->eld;
7820 uint32_t eldv;
7821 uint32_t len;
7822 uint32_t i;
7823
7824 i = I915_READ(G4X_AUD_VID_DID);
7825
7826 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7827 eldv = G4X_ELDV_DEVCL_DEVBLC;
7828 else
7829 eldv = G4X_ELDV_DEVCTG;
7830
7831 if (intel_eld_uptodate(connector,
7832 G4X_AUD_CNTL_ST, eldv,
7833 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7834 G4X_HDMIW_HDMIEDID))
7835 return;
7836
7837 i = I915_READ(G4X_AUD_CNTL_ST);
7838 i &= ~(eldv | G4X_ELD_ADDR);
7839 len = (i >> 9) & 0x1f; /* ELD buffer size */
7840 I915_WRITE(G4X_AUD_CNTL_ST, i);
7841
7842 if (!eld[0])
7843 return;
7844
7845 len = min_t(uint8_t, eld[2], len);
7846 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7847 for (i = 0; i < len; i++)
7848 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7849
7850 i = I915_READ(G4X_AUD_CNTL_ST);
7851 i |= eldv;
7852 I915_WRITE(G4X_AUD_CNTL_ST, i);
7853 }
7854
7855 static void haswell_write_eld(struct drm_connector *connector,
7856 struct drm_crtc *crtc,
7857 struct drm_display_mode *mode)
7858 {
7859 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7860 uint8_t *eld = connector->eld;
7861 uint32_t eldv;
7862 uint32_t i;
7863 int len;
7864 int pipe = to_intel_crtc(crtc)->pipe;
7865 int tmp;
7866
7867 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7868 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7869 int aud_config = HSW_AUD_CFG(pipe);
7870 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7871
7872 /* Audio output enable */
7873 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7874 tmp = I915_READ(aud_cntrl_st2);
7875 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7876 I915_WRITE(aud_cntrl_st2, tmp);
7877 POSTING_READ(aud_cntrl_st2);
7878
7879 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7880
7881 /* Set ELD valid state */
7882 tmp = I915_READ(aud_cntrl_st2);
7883 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7884 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7885 I915_WRITE(aud_cntrl_st2, tmp);
7886 tmp = I915_READ(aud_cntrl_st2);
7887 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7888
7889 /* Enable HDMI mode */
7890 tmp = I915_READ(aud_config);
7891 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7892 /* clear N_programing_enable and N_value_index */
7893 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7894 I915_WRITE(aud_config, tmp);
7895
7896 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7897
7898 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7899
7900 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7901 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7902 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7903 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7904 } else {
7905 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7906 }
7907
7908 if (intel_eld_uptodate(connector,
7909 aud_cntrl_st2, eldv,
7910 aud_cntl_st, IBX_ELD_ADDRESS,
7911 hdmiw_hdmiedid))
7912 return;
7913
7914 i = I915_READ(aud_cntrl_st2);
7915 i &= ~eldv;
7916 I915_WRITE(aud_cntrl_st2, i);
7917
7918 if (!eld[0])
7919 return;
7920
7921 i = I915_READ(aud_cntl_st);
7922 i &= ~IBX_ELD_ADDRESS;
7923 I915_WRITE(aud_cntl_st, i);
7924 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7925 DRM_DEBUG_DRIVER("port num:%d\n", i);
7926
7927 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7928 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7929 for (i = 0; i < len; i++)
7930 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7931
7932 i = I915_READ(aud_cntrl_st2);
7933 i |= eldv;
7934 I915_WRITE(aud_cntrl_st2, i);
7935
7936 }
7937
7938 static void ironlake_write_eld(struct drm_connector *connector,
7939 struct drm_crtc *crtc,
7940 struct drm_display_mode *mode)
7941 {
7942 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7943 uint8_t *eld = connector->eld;
7944 uint32_t eldv;
7945 uint32_t i;
7946 int len;
7947 int hdmiw_hdmiedid;
7948 int aud_config;
7949 int aud_cntl_st;
7950 int aud_cntrl_st2;
7951 int pipe = to_intel_crtc(crtc)->pipe;
7952
7953 if (HAS_PCH_IBX(connector->dev)) {
7954 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7955 aud_config = IBX_AUD_CFG(pipe);
7956 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7957 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7958 } else if (IS_VALLEYVIEW(connector->dev)) {
7959 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7960 aud_config = VLV_AUD_CFG(pipe);
7961 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7962 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7963 } else {
7964 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7965 aud_config = CPT_AUD_CFG(pipe);
7966 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7967 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7968 }
7969
7970 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7971
7972 if (IS_VALLEYVIEW(connector->dev)) {
7973 struct intel_encoder *intel_encoder;
7974 struct intel_digital_port *intel_dig_port;
7975
7976 intel_encoder = intel_attached_encoder(connector);
7977 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7978 i = intel_dig_port->port;
7979 } else {
7980 i = I915_READ(aud_cntl_st);
7981 i = (i >> 29) & DIP_PORT_SEL_MASK;
7982 /* DIP_Port_Select, 0x1 = PortB */
7983 }
7984
7985 if (!i) {
7986 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7987 /* operate blindly on all ports */
7988 eldv = IBX_ELD_VALIDB;
7989 eldv |= IBX_ELD_VALIDB << 4;
7990 eldv |= IBX_ELD_VALIDB << 8;
7991 } else {
7992 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7993 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7994 }
7995
7996 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7997 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7998 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7999 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8000 } else {
8001 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8002 }
8003
8004 if (intel_eld_uptodate(connector,
8005 aud_cntrl_st2, eldv,
8006 aud_cntl_st, IBX_ELD_ADDRESS,
8007 hdmiw_hdmiedid))
8008 return;
8009
8010 i = I915_READ(aud_cntrl_st2);
8011 i &= ~eldv;
8012 I915_WRITE(aud_cntrl_st2, i);
8013
8014 if (!eld[0])
8015 return;
8016
8017 i = I915_READ(aud_cntl_st);
8018 i &= ~IBX_ELD_ADDRESS;
8019 I915_WRITE(aud_cntl_st, i);
8020
8021 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8022 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8023 for (i = 0; i < len; i++)
8024 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8025
8026 i = I915_READ(aud_cntrl_st2);
8027 i |= eldv;
8028 I915_WRITE(aud_cntrl_st2, i);
8029 }
8030
8031 void intel_write_eld(struct drm_encoder *encoder,
8032 struct drm_display_mode *mode)
8033 {
8034 struct drm_crtc *crtc = encoder->crtc;
8035 struct drm_connector *connector;
8036 struct drm_device *dev = encoder->dev;
8037 struct drm_i915_private *dev_priv = dev->dev_private;
8038
8039 connector = drm_select_eld(encoder, mode);
8040 if (!connector)
8041 return;
8042
8043 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8044 connector->base.id,
8045 connector->name,
8046 connector->encoder->base.id,
8047 connector->encoder->name);
8048
8049 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8050
8051 if (dev_priv->display.write_eld)
8052 dev_priv->display.write_eld(connector, crtc, mode);
8053 }
8054
8055 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8056 {
8057 struct drm_device *dev = crtc->dev;
8058 struct drm_i915_private *dev_priv = dev->dev_private;
8059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8060 uint32_t cntl = 0, size = 0;
8061
8062 if (base) {
8063 unsigned int width = intel_crtc->cursor_width;
8064 unsigned int height = intel_crtc->cursor_height;
8065 unsigned int stride = roundup_pow_of_two(width) * 4;
8066
8067 switch (stride) {
8068 default:
8069 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8070 width, stride);
8071 stride = 256;
8072 /* fallthrough */
8073 case 256:
8074 case 512:
8075 case 1024:
8076 case 2048:
8077 break;
8078 }
8079
8080 cntl |= CURSOR_ENABLE |
8081 CURSOR_GAMMA_ENABLE |
8082 CURSOR_FORMAT_ARGB |
8083 CURSOR_STRIDE(stride);
8084
8085 size = (height << 12) | width;
8086 }
8087
8088 if (intel_crtc->cursor_cntl != 0 &&
8089 (intel_crtc->cursor_base != base ||
8090 intel_crtc->cursor_size != size ||
8091 intel_crtc->cursor_cntl != cntl)) {
8092 /* On these chipsets we can only modify the base/size/stride
8093 * whilst the cursor is disabled.
8094 */
8095 I915_WRITE(_CURACNTR, 0);
8096 POSTING_READ(_CURACNTR);
8097 intel_crtc->cursor_cntl = 0;
8098 }
8099
8100 if (intel_crtc->cursor_base != base)
8101 I915_WRITE(_CURABASE, base);
8102
8103 if (intel_crtc->cursor_size != size) {
8104 I915_WRITE(CURSIZE, size);
8105 intel_crtc->cursor_size = size;
8106 }
8107
8108 if (intel_crtc->cursor_cntl != cntl) {
8109 I915_WRITE(_CURACNTR, cntl);
8110 POSTING_READ(_CURACNTR);
8111 intel_crtc->cursor_cntl = cntl;
8112 }
8113 }
8114
8115 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8116 {
8117 struct drm_device *dev = crtc->dev;
8118 struct drm_i915_private *dev_priv = dev->dev_private;
8119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8120 int pipe = intel_crtc->pipe;
8121 uint32_t cntl;
8122
8123 cntl = 0;
8124 if (base) {
8125 cntl = MCURSOR_GAMMA_ENABLE;
8126 switch (intel_crtc->cursor_width) {
8127 case 64:
8128 cntl |= CURSOR_MODE_64_ARGB_AX;
8129 break;
8130 case 128:
8131 cntl |= CURSOR_MODE_128_ARGB_AX;
8132 break;
8133 case 256:
8134 cntl |= CURSOR_MODE_256_ARGB_AX;
8135 break;
8136 default:
8137 WARN_ON(1);
8138 return;
8139 }
8140 cntl |= pipe << 28; /* Connect to correct pipe */
8141 }
8142 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8143 cntl |= CURSOR_PIPE_CSC_ENABLE;
8144
8145 if (intel_crtc->cursor_cntl != cntl) {
8146 I915_WRITE(CURCNTR(pipe), cntl);
8147 POSTING_READ(CURCNTR(pipe));
8148 intel_crtc->cursor_cntl = cntl;
8149 }
8150
8151 /* and commit changes on next vblank */
8152 I915_WRITE(CURBASE(pipe), base);
8153 POSTING_READ(CURBASE(pipe));
8154 }
8155
8156 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8157 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8158 bool on)
8159 {
8160 struct drm_device *dev = crtc->dev;
8161 struct drm_i915_private *dev_priv = dev->dev_private;
8162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8163 int pipe = intel_crtc->pipe;
8164 int x = crtc->cursor_x;
8165 int y = crtc->cursor_y;
8166 u32 base = 0, pos = 0;
8167
8168 if (on)
8169 base = intel_crtc->cursor_addr;
8170
8171 if (x >= intel_crtc->config.pipe_src_w)
8172 base = 0;
8173
8174 if (y >= intel_crtc->config.pipe_src_h)
8175 base = 0;
8176
8177 if (x < 0) {
8178 if (x + intel_crtc->cursor_width <= 0)
8179 base = 0;
8180
8181 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8182 x = -x;
8183 }
8184 pos |= x << CURSOR_X_SHIFT;
8185
8186 if (y < 0) {
8187 if (y + intel_crtc->cursor_height <= 0)
8188 base = 0;
8189
8190 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8191 y = -y;
8192 }
8193 pos |= y << CURSOR_Y_SHIFT;
8194
8195 if (base == 0 && intel_crtc->cursor_base == 0)
8196 return;
8197
8198 I915_WRITE(CURPOS(pipe), pos);
8199
8200 if (IS_845G(dev) || IS_I865G(dev))
8201 i845_update_cursor(crtc, base);
8202 else
8203 i9xx_update_cursor(crtc, base);
8204 intel_crtc->cursor_base = base;
8205 }
8206
8207 static bool cursor_size_ok(struct drm_device *dev,
8208 uint32_t width, uint32_t height)
8209 {
8210 if (width == 0 || height == 0)
8211 return false;
8212
8213 /*
8214 * 845g/865g are special in that they are only limited by
8215 * the width of their cursors, the height is arbitrary up to
8216 * the precision of the register. Everything else requires
8217 * square cursors, limited to a few power-of-two sizes.
8218 */
8219 if (IS_845G(dev) || IS_I865G(dev)) {
8220 if ((width & 63) != 0)
8221 return false;
8222
8223 if (width > (IS_845G(dev) ? 64 : 512))
8224 return false;
8225
8226 if (height > 1023)
8227 return false;
8228 } else {
8229 switch (width | height) {
8230 case 256:
8231 case 128:
8232 if (IS_GEN2(dev))
8233 return false;
8234 case 64:
8235 break;
8236 default:
8237 return false;
8238 }
8239 }
8240
8241 return true;
8242 }
8243
8244 /*
8245 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8246 *
8247 * Note that the object's reference will be consumed if the update fails. If
8248 * the update succeeds, the reference of the old object (if any) will be
8249 * consumed.
8250 */
8251 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8252 struct drm_i915_gem_object *obj,
8253 uint32_t width, uint32_t height)
8254 {
8255 struct drm_device *dev = crtc->dev;
8256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8257 enum pipe pipe = intel_crtc->pipe;
8258 unsigned old_width, stride;
8259 uint32_t addr;
8260 int ret;
8261
8262 /* if we want to turn off the cursor ignore width and height */
8263 if (!obj) {
8264 DRM_DEBUG_KMS("cursor off\n");
8265 addr = 0;
8266 obj = NULL;
8267 mutex_lock(&dev->struct_mutex);
8268 goto finish;
8269 }
8270
8271 /* Check for which cursor types we support */
8272 if (!cursor_size_ok(dev, width, height)) {
8273 DRM_DEBUG("Cursor dimension not supported\n");
8274 return -EINVAL;
8275 }
8276
8277 stride = roundup_pow_of_two(width) * 4;
8278 if (obj->base.size < stride * height) {
8279 DRM_DEBUG_KMS("buffer is too small\n");
8280 ret = -ENOMEM;
8281 goto fail;
8282 }
8283
8284 /* we only need to pin inside GTT if cursor is non-phy */
8285 mutex_lock(&dev->struct_mutex);
8286 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8287 unsigned alignment;
8288
8289 if (obj->tiling_mode) {
8290 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8291 ret = -EINVAL;
8292 goto fail_locked;
8293 }
8294
8295 /* Note that the w/a also requires 2 PTE of padding following
8296 * the bo. We currently fill all unused PTE with the shadow
8297 * page and so we should always have valid PTE following the
8298 * cursor preventing the VT-d warning.
8299 */
8300 alignment = 0;
8301 if (need_vtd_wa(dev))
8302 alignment = 64*1024;
8303
8304 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8305 if (ret) {
8306 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8307 goto fail_locked;
8308 }
8309
8310 ret = i915_gem_object_put_fence(obj);
8311 if (ret) {
8312 DRM_DEBUG_KMS("failed to release fence for cursor");
8313 goto fail_unpin;
8314 }
8315
8316 addr = i915_gem_obj_ggtt_offset(obj);
8317 } else {
8318 int align = IS_I830(dev) ? 16 * 1024 : 256;
8319 ret = i915_gem_object_attach_phys(obj, align);
8320 if (ret) {
8321 DRM_DEBUG_KMS("failed to attach phys object\n");
8322 goto fail_locked;
8323 }
8324 addr = obj->phys_handle->busaddr;
8325 }
8326
8327 finish:
8328 if (intel_crtc->cursor_bo) {
8329 if (!INTEL_INFO(dev)->cursor_needs_physical)
8330 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8331 }
8332
8333 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8334 INTEL_FRONTBUFFER_CURSOR(pipe));
8335 mutex_unlock(&dev->struct_mutex);
8336
8337 old_width = intel_crtc->cursor_width;
8338
8339 intel_crtc->cursor_addr = addr;
8340 intel_crtc->cursor_bo = obj;
8341 intel_crtc->cursor_width = width;
8342 intel_crtc->cursor_height = height;
8343
8344 if (intel_crtc->active) {
8345 if (old_width != width)
8346 intel_update_watermarks(crtc);
8347 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8348 }
8349
8350 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8351
8352 return 0;
8353 fail_unpin:
8354 i915_gem_object_unpin_from_display_plane(obj);
8355 fail_locked:
8356 mutex_unlock(&dev->struct_mutex);
8357 fail:
8358 drm_gem_object_unreference_unlocked(&obj->base);
8359 return ret;
8360 }
8361
8362 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8363 u16 *blue, uint32_t start, uint32_t size)
8364 {
8365 int end = (start + size > 256) ? 256 : start + size, i;
8366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8367
8368 for (i = start; i < end; i++) {
8369 intel_crtc->lut_r[i] = red[i] >> 8;
8370 intel_crtc->lut_g[i] = green[i] >> 8;
8371 intel_crtc->lut_b[i] = blue[i] >> 8;
8372 }
8373
8374 intel_crtc_load_lut(crtc);
8375 }
8376
8377 /* VESA 640x480x72Hz mode to set on the pipe */
8378 static struct drm_display_mode load_detect_mode = {
8379 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8380 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8381 };
8382
8383 struct drm_framebuffer *
8384 __intel_framebuffer_create(struct drm_device *dev,
8385 struct drm_mode_fb_cmd2 *mode_cmd,
8386 struct drm_i915_gem_object *obj)
8387 {
8388 struct intel_framebuffer *intel_fb;
8389 int ret;
8390
8391 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8392 if (!intel_fb) {
8393 drm_gem_object_unreference_unlocked(&obj->base);
8394 return ERR_PTR(-ENOMEM);
8395 }
8396
8397 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8398 if (ret)
8399 goto err;
8400
8401 return &intel_fb->base;
8402 err:
8403 drm_gem_object_unreference_unlocked(&obj->base);
8404 kfree(intel_fb);
8405
8406 return ERR_PTR(ret);
8407 }
8408
8409 static struct drm_framebuffer *
8410 intel_framebuffer_create(struct drm_device *dev,
8411 struct drm_mode_fb_cmd2 *mode_cmd,
8412 struct drm_i915_gem_object *obj)
8413 {
8414 struct drm_framebuffer *fb;
8415 int ret;
8416
8417 ret = i915_mutex_lock_interruptible(dev);
8418 if (ret)
8419 return ERR_PTR(ret);
8420 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8421 mutex_unlock(&dev->struct_mutex);
8422
8423 return fb;
8424 }
8425
8426 static u32
8427 intel_framebuffer_pitch_for_width(int width, int bpp)
8428 {
8429 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8430 return ALIGN(pitch, 64);
8431 }
8432
8433 static u32
8434 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8435 {
8436 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8437 return PAGE_ALIGN(pitch * mode->vdisplay);
8438 }
8439
8440 static struct drm_framebuffer *
8441 intel_framebuffer_create_for_mode(struct drm_device *dev,
8442 struct drm_display_mode *mode,
8443 int depth, int bpp)
8444 {
8445 struct drm_i915_gem_object *obj;
8446 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8447
8448 obj = i915_gem_alloc_object(dev,
8449 intel_framebuffer_size_for_mode(mode, bpp));
8450 if (obj == NULL)
8451 return ERR_PTR(-ENOMEM);
8452
8453 mode_cmd.width = mode->hdisplay;
8454 mode_cmd.height = mode->vdisplay;
8455 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8456 bpp);
8457 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8458
8459 return intel_framebuffer_create(dev, &mode_cmd, obj);
8460 }
8461
8462 static struct drm_framebuffer *
8463 mode_fits_in_fbdev(struct drm_device *dev,
8464 struct drm_display_mode *mode)
8465 {
8466 #ifdef CONFIG_DRM_I915_FBDEV
8467 struct drm_i915_private *dev_priv = dev->dev_private;
8468 struct drm_i915_gem_object *obj;
8469 struct drm_framebuffer *fb;
8470
8471 if (!dev_priv->fbdev)
8472 return NULL;
8473
8474 if (!dev_priv->fbdev->fb)
8475 return NULL;
8476
8477 obj = dev_priv->fbdev->fb->obj;
8478 BUG_ON(!obj);
8479
8480 fb = &dev_priv->fbdev->fb->base;
8481 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8482 fb->bits_per_pixel))
8483 return NULL;
8484
8485 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8486 return NULL;
8487
8488 return fb;
8489 #else
8490 return NULL;
8491 #endif
8492 }
8493
8494 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8495 struct drm_display_mode *mode,
8496 struct intel_load_detect_pipe *old,
8497 struct drm_modeset_acquire_ctx *ctx)
8498 {
8499 struct intel_crtc *intel_crtc;
8500 struct intel_encoder *intel_encoder =
8501 intel_attached_encoder(connector);
8502 struct drm_crtc *possible_crtc;
8503 struct drm_encoder *encoder = &intel_encoder->base;
8504 struct drm_crtc *crtc = NULL;
8505 struct drm_device *dev = encoder->dev;
8506 struct drm_framebuffer *fb;
8507 struct drm_mode_config *config = &dev->mode_config;
8508 int ret, i = -1;
8509
8510 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8511 connector->base.id, connector->name,
8512 encoder->base.id, encoder->name);
8513
8514 retry:
8515 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8516 if (ret)
8517 goto fail_unlock;
8518
8519 /*
8520 * Algorithm gets a little messy:
8521 *
8522 * - if the connector already has an assigned crtc, use it (but make
8523 * sure it's on first)
8524 *
8525 * - try to find the first unused crtc that can drive this connector,
8526 * and use that if we find one
8527 */
8528
8529 /* See if we already have a CRTC for this connector */
8530 if (encoder->crtc) {
8531 crtc = encoder->crtc;
8532
8533 ret = drm_modeset_lock(&crtc->mutex, ctx);
8534 if (ret)
8535 goto fail_unlock;
8536
8537 old->dpms_mode = connector->dpms;
8538 old->load_detect_temp = false;
8539
8540 /* Make sure the crtc and connector are running */
8541 if (connector->dpms != DRM_MODE_DPMS_ON)
8542 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8543
8544 return true;
8545 }
8546
8547 /* Find an unused one (if possible) */
8548 for_each_crtc(dev, possible_crtc) {
8549 i++;
8550 if (!(encoder->possible_crtcs & (1 << i)))
8551 continue;
8552 if (possible_crtc->enabled)
8553 continue;
8554 /* This can occur when applying the pipe A quirk on resume. */
8555 if (to_intel_crtc(possible_crtc)->new_enabled)
8556 continue;
8557
8558 crtc = possible_crtc;
8559 break;
8560 }
8561
8562 /*
8563 * If we didn't find an unused CRTC, don't use any.
8564 */
8565 if (!crtc) {
8566 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8567 goto fail_unlock;
8568 }
8569
8570 ret = drm_modeset_lock(&crtc->mutex, ctx);
8571 if (ret)
8572 goto fail_unlock;
8573 intel_encoder->new_crtc = to_intel_crtc(crtc);
8574 to_intel_connector(connector)->new_encoder = intel_encoder;
8575
8576 intel_crtc = to_intel_crtc(crtc);
8577 intel_crtc->new_enabled = true;
8578 intel_crtc->new_config = &intel_crtc->config;
8579 old->dpms_mode = connector->dpms;
8580 old->load_detect_temp = true;
8581 old->release_fb = NULL;
8582
8583 if (!mode)
8584 mode = &load_detect_mode;
8585
8586 /* We need a framebuffer large enough to accommodate all accesses
8587 * that the plane may generate whilst we perform load detection.
8588 * We can not rely on the fbcon either being present (we get called
8589 * during its initialisation to detect all boot displays, or it may
8590 * not even exist) or that it is large enough to satisfy the
8591 * requested mode.
8592 */
8593 fb = mode_fits_in_fbdev(dev, mode);
8594 if (fb == NULL) {
8595 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8596 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8597 old->release_fb = fb;
8598 } else
8599 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8600 if (IS_ERR(fb)) {
8601 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8602 goto fail;
8603 }
8604
8605 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8606 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8607 if (old->release_fb)
8608 old->release_fb->funcs->destroy(old->release_fb);
8609 goto fail;
8610 }
8611
8612 /* let the connector get through one full cycle before testing */
8613 intel_wait_for_vblank(dev, intel_crtc->pipe);
8614 return true;
8615
8616 fail:
8617 intel_crtc->new_enabled = crtc->enabled;
8618 if (intel_crtc->new_enabled)
8619 intel_crtc->new_config = &intel_crtc->config;
8620 else
8621 intel_crtc->new_config = NULL;
8622 fail_unlock:
8623 if (ret == -EDEADLK) {
8624 drm_modeset_backoff(ctx);
8625 goto retry;
8626 }
8627
8628 return false;
8629 }
8630
8631 void intel_release_load_detect_pipe(struct drm_connector *connector,
8632 struct intel_load_detect_pipe *old)
8633 {
8634 struct intel_encoder *intel_encoder =
8635 intel_attached_encoder(connector);
8636 struct drm_encoder *encoder = &intel_encoder->base;
8637 struct drm_crtc *crtc = encoder->crtc;
8638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8639
8640 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8641 connector->base.id, connector->name,
8642 encoder->base.id, encoder->name);
8643
8644 if (old->load_detect_temp) {
8645 to_intel_connector(connector)->new_encoder = NULL;
8646 intel_encoder->new_crtc = NULL;
8647 intel_crtc->new_enabled = false;
8648 intel_crtc->new_config = NULL;
8649 intel_set_mode(crtc, NULL, 0, 0, NULL);
8650
8651 if (old->release_fb) {
8652 drm_framebuffer_unregister_private(old->release_fb);
8653 drm_framebuffer_unreference(old->release_fb);
8654 }
8655
8656 return;
8657 }
8658
8659 /* Switch crtc and encoder back off if necessary */
8660 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8661 connector->funcs->dpms(connector, old->dpms_mode);
8662 }
8663
8664 static int i9xx_pll_refclk(struct drm_device *dev,
8665 const struct intel_crtc_config *pipe_config)
8666 {
8667 struct drm_i915_private *dev_priv = dev->dev_private;
8668 u32 dpll = pipe_config->dpll_hw_state.dpll;
8669
8670 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8671 return dev_priv->vbt.lvds_ssc_freq;
8672 else if (HAS_PCH_SPLIT(dev))
8673 return 120000;
8674 else if (!IS_GEN2(dev))
8675 return 96000;
8676 else
8677 return 48000;
8678 }
8679
8680 /* Returns the clock of the currently programmed mode of the given pipe. */
8681 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8682 struct intel_crtc_config *pipe_config)
8683 {
8684 struct drm_device *dev = crtc->base.dev;
8685 struct drm_i915_private *dev_priv = dev->dev_private;
8686 int pipe = pipe_config->cpu_transcoder;
8687 u32 dpll = pipe_config->dpll_hw_state.dpll;
8688 u32 fp;
8689 intel_clock_t clock;
8690 int refclk = i9xx_pll_refclk(dev, pipe_config);
8691
8692 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8693 fp = pipe_config->dpll_hw_state.fp0;
8694 else
8695 fp = pipe_config->dpll_hw_state.fp1;
8696
8697 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8698 if (IS_PINEVIEW(dev)) {
8699 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8700 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8701 } else {
8702 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8703 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8704 }
8705
8706 if (!IS_GEN2(dev)) {
8707 if (IS_PINEVIEW(dev))
8708 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8709 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8710 else
8711 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8712 DPLL_FPA01_P1_POST_DIV_SHIFT);
8713
8714 switch (dpll & DPLL_MODE_MASK) {
8715 case DPLLB_MODE_DAC_SERIAL:
8716 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8717 5 : 10;
8718 break;
8719 case DPLLB_MODE_LVDS:
8720 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8721 7 : 14;
8722 break;
8723 default:
8724 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8725 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8726 return;
8727 }
8728
8729 if (IS_PINEVIEW(dev))
8730 pineview_clock(refclk, &clock);
8731 else
8732 i9xx_clock(refclk, &clock);
8733 } else {
8734 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8735 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8736
8737 if (is_lvds) {
8738 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8739 DPLL_FPA01_P1_POST_DIV_SHIFT);
8740
8741 if (lvds & LVDS_CLKB_POWER_UP)
8742 clock.p2 = 7;
8743 else
8744 clock.p2 = 14;
8745 } else {
8746 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8747 clock.p1 = 2;
8748 else {
8749 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8750 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8751 }
8752 if (dpll & PLL_P2_DIVIDE_BY_4)
8753 clock.p2 = 4;
8754 else
8755 clock.p2 = 2;
8756 }
8757
8758 i9xx_clock(refclk, &clock);
8759 }
8760
8761 /*
8762 * This value includes pixel_multiplier. We will use
8763 * port_clock to compute adjusted_mode.crtc_clock in the
8764 * encoder's get_config() function.
8765 */
8766 pipe_config->port_clock = clock.dot;
8767 }
8768
8769 int intel_dotclock_calculate(int link_freq,
8770 const struct intel_link_m_n *m_n)
8771 {
8772 /*
8773 * The calculation for the data clock is:
8774 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8775 * But we want to avoid losing precison if possible, so:
8776 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8777 *
8778 * and the link clock is simpler:
8779 * link_clock = (m * link_clock) / n
8780 */
8781
8782 if (!m_n->link_n)
8783 return 0;
8784
8785 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8786 }
8787
8788 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8789 struct intel_crtc_config *pipe_config)
8790 {
8791 struct drm_device *dev = crtc->base.dev;
8792
8793 /* read out port_clock from the DPLL */
8794 i9xx_crtc_clock_get(crtc, pipe_config);
8795
8796 /*
8797 * This value does not include pixel_multiplier.
8798 * We will check that port_clock and adjusted_mode.crtc_clock
8799 * agree once we know their relationship in the encoder's
8800 * get_config() function.
8801 */
8802 pipe_config->adjusted_mode.crtc_clock =
8803 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8804 &pipe_config->fdi_m_n);
8805 }
8806
8807 /** Returns the currently programmed mode of the given pipe. */
8808 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8809 struct drm_crtc *crtc)
8810 {
8811 struct drm_i915_private *dev_priv = dev->dev_private;
8812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8813 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8814 struct drm_display_mode *mode;
8815 struct intel_crtc_config pipe_config;
8816 int htot = I915_READ(HTOTAL(cpu_transcoder));
8817 int hsync = I915_READ(HSYNC(cpu_transcoder));
8818 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8819 int vsync = I915_READ(VSYNC(cpu_transcoder));
8820 enum pipe pipe = intel_crtc->pipe;
8821
8822 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8823 if (!mode)
8824 return NULL;
8825
8826 /*
8827 * Construct a pipe_config sufficient for getting the clock info
8828 * back out of crtc_clock_get.
8829 *
8830 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8831 * to use a real value here instead.
8832 */
8833 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8834 pipe_config.pixel_multiplier = 1;
8835 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8836 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8837 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8838 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8839
8840 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8841 mode->hdisplay = (htot & 0xffff) + 1;
8842 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8843 mode->hsync_start = (hsync & 0xffff) + 1;
8844 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8845 mode->vdisplay = (vtot & 0xffff) + 1;
8846 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8847 mode->vsync_start = (vsync & 0xffff) + 1;
8848 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8849
8850 drm_mode_set_name(mode);
8851
8852 return mode;
8853 }
8854
8855 static void intel_increase_pllclock(struct drm_device *dev,
8856 enum pipe pipe)
8857 {
8858 struct drm_i915_private *dev_priv = dev->dev_private;
8859 int dpll_reg = DPLL(pipe);
8860 int dpll;
8861
8862 if (!HAS_GMCH_DISPLAY(dev))
8863 return;
8864
8865 if (!dev_priv->lvds_downclock_avail)
8866 return;
8867
8868 dpll = I915_READ(dpll_reg);
8869 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8870 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8871
8872 assert_panel_unlocked(dev_priv, pipe);
8873
8874 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8875 I915_WRITE(dpll_reg, dpll);
8876 intel_wait_for_vblank(dev, pipe);
8877
8878 dpll = I915_READ(dpll_reg);
8879 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8880 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8881 }
8882 }
8883
8884 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8885 {
8886 struct drm_device *dev = crtc->dev;
8887 struct drm_i915_private *dev_priv = dev->dev_private;
8888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8889
8890 if (!HAS_GMCH_DISPLAY(dev))
8891 return;
8892
8893 if (!dev_priv->lvds_downclock_avail)
8894 return;
8895
8896 /*
8897 * Since this is called by a timer, we should never get here in
8898 * the manual case.
8899 */
8900 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8901 int pipe = intel_crtc->pipe;
8902 int dpll_reg = DPLL(pipe);
8903 int dpll;
8904
8905 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8906
8907 assert_panel_unlocked(dev_priv, pipe);
8908
8909 dpll = I915_READ(dpll_reg);
8910 dpll |= DISPLAY_RATE_SELECT_FPA1;
8911 I915_WRITE(dpll_reg, dpll);
8912 intel_wait_for_vblank(dev, pipe);
8913 dpll = I915_READ(dpll_reg);
8914 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8915 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8916 }
8917
8918 }
8919
8920 void intel_mark_busy(struct drm_device *dev)
8921 {
8922 struct drm_i915_private *dev_priv = dev->dev_private;
8923
8924 if (dev_priv->mm.busy)
8925 return;
8926
8927 intel_runtime_pm_get(dev_priv);
8928 i915_update_gfx_val(dev_priv);
8929 dev_priv->mm.busy = true;
8930 }
8931
8932 void intel_mark_idle(struct drm_device *dev)
8933 {
8934 struct drm_i915_private *dev_priv = dev->dev_private;
8935 struct drm_crtc *crtc;
8936
8937 if (!dev_priv->mm.busy)
8938 return;
8939
8940 dev_priv->mm.busy = false;
8941
8942 if (!i915.powersave)
8943 goto out;
8944
8945 for_each_crtc(dev, crtc) {
8946 if (!crtc->primary->fb)
8947 continue;
8948
8949 intel_decrease_pllclock(crtc);
8950 }
8951
8952 if (INTEL_INFO(dev)->gen >= 6)
8953 gen6_rps_idle(dev->dev_private);
8954
8955 out:
8956 intel_runtime_pm_put(dev_priv);
8957 }
8958
8959
8960 /**
8961 * intel_mark_fb_busy - mark given planes as busy
8962 * @dev: DRM device
8963 * @frontbuffer_bits: bits for the affected planes
8964 * @ring: optional ring for asynchronous commands
8965 *
8966 * This function gets called every time the screen contents change. It can be
8967 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8968 */
8969 static void intel_mark_fb_busy(struct drm_device *dev,
8970 unsigned frontbuffer_bits,
8971 struct intel_engine_cs *ring)
8972 {
8973 enum pipe pipe;
8974
8975 if (!i915.powersave)
8976 return;
8977
8978 for_each_pipe(pipe) {
8979 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8980 continue;
8981
8982 intel_increase_pllclock(dev, pipe);
8983 if (ring && intel_fbc_enabled(dev))
8984 ring->fbc_dirty = true;
8985 }
8986 }
8987
8988 /**
8989 * intel_fb_obj_invalidate - invalidate frontbuffer object
8990 * @obj: GEM object to invalidate
8991 * @ring: set for asynchronous rendering
8992 *
8993 * This function gets called every time rendering on the given object starts and
8994 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8995 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8996 * until the rendering completes or a flip on this frontbuffer plane is
8997 * scheduled.
8998 */
8999 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9000 struct intel_engine_cs *ring)
9001 {
9002 struct drm_device *dev = obj->base.dev;
9003 struct drm_i915_private *dev_priv = dev->dev_private;
9004
9005 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9006
9007 if (!obj->frontbuffer_bits)
9008 return;
9009
9010 if (ring) {
9011 mutex_lock(&dev_priv->fb_tracking.lock);
9012 dev_priv->fb_tracking.busy_bits
9013 |= obj->frontbuffer_bits;
9014 dev_priv->fb_tracking.flip_bits
9015 &= ~obj->frontbuffer_bits;
9016 mutex_unlock(&dev_priv->fb_tracking.lock);
9017 }
9018
9019 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9020
9021 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9022 }
9023
9024 /**
9025 * intel_frontbuffer_flush - flush frontbuffer
9026 * @dev: DRM device
9027 * @frontbuffer_bits: frontbuffer plane tracking bits
9028 *
9029 * This function gets called every time rendering on the given planes has
9030 * completed and frontbuffer caching can be started again. Flushes will get
9031 * delayed if they're blocked by some oustanding asynchronous rendering.
9032 *
9033 * Can be called without any locks held.
9034 */
9035 void intel_frontbuffer_flush(struct drm_device *dev,
9036 unsigned frontbuffer_bits)
9037 {
9038 struct drm_i915_private *dev_priv = dev->dev_private;
9039
9040 /* Delay flushing when rings are still busy.*/
9041 mutex_lock(&dev_priv->fb_tracking.lock);
9042 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9043 mutex_unlock(&dev_priv->fb_tracking.lock);
9044
9045 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9046
9047 intel_edp_psr_flush(dev, frontbuffer_bits);
9048 }
9049
9050 /**
9051 * intel_fb_obj_flush - flush frontbuffer object
9052 * @obj: GEM object to flush
9053 * @retire: set when retiring asynchronous rendering
9054 *
9055 * This function gets called every time rendering on the given object has
9056 * completed and frontbuffer caching can be started again. If @retire is true
9057 * then any delayed flushes will be unblocked.
9058 */
9059 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9060 bool retire)
9061 {
9062 struct drm_device *dev = obj->base.dev;
9063 struct drm_i915_private *dev_priv = dev->dev_private;
9064 unsigned frontbuffer_bits;
9065
9066 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9067
9068 if (!obj->frontbuffer_bits)
9069 return;
9070
9071 frontbuffer_bits = obj->frontbuffer_bits;
9072
9073 if (retire) {
9074 mutex_lock(&dev_priv->fb_tracking.lock);
9075 /* Filter out new bits since rendering started. */
9076 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9077
9078 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9079 mutex_unlock(&dev_priv->fb_tracking.lock);
9080 }
9081
9082 intel_frontbuffer_flush(dev, frontbuffer_bits);
9083 }
9084
9085 /**
9086 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9087 * @dev: DRM device
9088 * @frontbuffer_bits: frontbuffer plane tracking bits
9089 *
9090 * This function gets called after scheduling a flip on @obj. The actual
9091 * frontbuffer flushing will be delayed until completion is signalled with
9092 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9093 * flush will be cancelled.
9094 *
9095 * Can be called without any locks held.
9096 */
9097 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9098 unsigned frontbuffer_bits)
9099 {
9100 struct drm_i915_private *dev_priv = dev->dev_private;
9101
9102 mutex_lock(&dev_priv->fb_tracking.lock);
9103 dev_priv->fb_tracking.flip_bits
9104 |= frontbuffer_bits;
9105 mutex_unlock(&dev_priv->fb_tracking.lock);
9106 }
9107
9108 /**
9109 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9110 * @dev: DRM device
9111 * @frontbuffer_bits: frontbuffer plane tracking bits
9112 *
9113 * This function gets called after the flip has been latched and will complete
9114 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9115 *
9116 * Can be called without any locks held.
9117 */
9118 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9119 unsigned frontbuffer_bits)
9120 {
9121 struct drm_i915_private *dev_priv = dev->dev_private;
9122
9123 mutex_lock(&dev_priv->fb_tracking.lock);
9124 /* Mask any cancelled flips. */
9125 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9126 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9127 mutex_unlock(&dev_priv->fb_tracking.lock);
9128
9129 intel_frontbuffer_flush(dev, frontbuffer_bits);
9130 }
9131
9132 static void intel_crtc_destroy(struct drm_crtc *crtc)
9133 {
9134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9135 struct drm_device *dev = crtc->dev;
9136 struct intel_unpin_work *work;
9137 unsigned long flags;
9138
9139 spin_lock_irqsave(&dev->event_lock, flags);
9140 work = intel_crtc->unpin_work;
9141 intel_crtc->unpin_work = NULL;
9142 spin_unlock_irqrestore(&dev->event_lock, flags);
9143
9144 if (work) {
9145 cancel_work_sync(&work->work);
9146 kfree(work);
9147 }
9148
9149 drm_crtc_cleanup(crtc);
9150
9151 kfree(intel_crtc);
9152 }
9153
9154 static void intel_unpin_work_fn(struct work_struct *__work)
9155 {
9156 struct intel_unpin_work *work =
9157 container_of(__work, struct intel_unpin_work, work);
9158 struct drm_device *dev = work->crtc->dev;
9159 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9160
9161 mutex_lock(&dev->struct_mutex);
9162 intel_unpin_fb_obj(work->old_fb_obj);
9163 drm_gem_object_unreference(&work->pending_flip_obj->base);
9164 drm_gem_object_unreference(&work->old_fb_obj->base);
9165
9166 intel_update_fbc(dev);
9167 mutex_unlock(&dev->struct_mutex);
9168
9169 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9170
9171 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9172 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9173
9174 kfree(work);
9175 }
9176
9177 static void do_intel_finish_page_flip(struct drm_device *dev,
9178 struct drm_crtc *crtc)
9179 {
9180 struct drm_i915_private *dev_priv = dev->dev_private;
9181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9182 struct intel_unpin_work *work;
9183 unsigned long flags;
9184
9185 /* Ignore early vblank irqs */
9186 if (intel_crtc == NULL)
9187 return;
9188
9189 spin_lock_irqsave(&dev->event_lock, flags);
9190 work = intel_crtc->unpin_work;
9191
9192 /* Ensure we don't miss a work->pending update ... */
9193 smp_rmb();
9194
9195 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9196 spin_unlock_irqrestore(&dev->event_lock, flags);
9197 return;
9198 }
9199
9200 /* and that the unpin work is consistent wrt ->pending. */
9201 smp_rmb();
9202
9203 intel_crtc->unpin_work = NULL;
9204
9205 if (work->event)
9206 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9207
9208 drm_crtc_vblank_put(crtc);
9209
9210 spin_unlock_irqrestore(&dev->event_lock, flags);
9211
9212 wake_up_all(&dev_priv->pending_flip_queue);
9213
9214 queue_work(dev_priv->wq, &work->work);
9215
9216 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9217 }
9218
9219 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9220 {
9221 struct drm_i915_private *dev_priv = dev->dev_private;
9222 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9223
9224 do_intel_finish_page_flip(dev, crtc);
9225 }
9226
9227 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9228 {
9229 struct drm_i915_private *dev_priv = dev->dev_private;
9230 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9231
9232 do_intel_finish_page_flip(dev, crtc);
9233 }
9234
9235 /* Is 'a' after or equal to 'b'? */
9236 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9237 {
9238 return !((a - b) & 0x80000000);
9239 }
9240
9241 static bool page_flip_finished(struct intel_crtc *crtc)
9242 {
9243 struct drm_device *dev = crtc->base.dev;
9244 struct drm_i915_private *dev_priv = dev->dev_private;
9245
9246 /*
9247 * The relevant registers doen't exist on pre-ctg.
9248 * As the flip done interrupt doesn't trigger for mmio
9249 * flips on gmch platforms, a flip count check isn't
9250 * really needed there. But since ctg has the registers,
9251 * include it in the check anyway.
9252 */
9253 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9254 return true;
9255
9256 /*
9257 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9258 * used the same base address. In that case the mmio flip might
9259 * have completed, but the CS hasn't even executed the flip yet.
9260 *
9261 * A flip count check isn't enough as the CS might have updated
9262 * the base address just after start of vblank, but before we
9263 * managed to process the interrupt. This means we'd complete the
9264 * CS flip too soon.
9265 *
9266 * Combining both checks should get us a good enough result. It may
9267 * still happen that the CS flip has been executed, but has not
9268 * yet actually completed. But in case the base address is the same
9269 * anyway, we don't really care.
9270 */
9271 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9272 crtc->unpin_work->gtt_offset &&
9273 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9274 crtc->unpin_work->flip_count);
9275 }
9276
9277 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9278 {
9279 struct drm_i915_private *dev_priv = dev->dev_private;
9280 struct intel_crtc *intel_crtc =
9281 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9282 unsigned long flags;
9283
9284 /* NB: An MMIO update of the plane base pointer will also
9285 * generate a page-flip completion irq, i.e. every modeset
9286 * is also accompanied by a spurious intel_prepare_page_flip().
9287 */
9288 spin_lock_irqsave(&dev->event_lock, flags);
9289 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9290 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9291 spin_unlock_irqrestore(&dev->event_lock, flags);
9292 }
9293
9294 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9295 {
9296 /* Ensure that the work item is consistent when activating it ... */
9297 smp_wmb();
9298 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9299 /* and that it is marked active as soon as the irq could fire. */
9300 smp_wmb();
9301 }
9302
9303 static int intel_gen2_queue_flip(struct drm_device *dev,
9304 struct drm_crtc *crtc,
9305 struct drm_framebuffer *fb,
9306 struct drm_i915_gem_object *obj,
9307 struct intel_engine_cs *ring,
9308 uint32_t flags)
9309 {
9310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9311 u32 flip_mask;
9312 int ret;
9313
9314 ret = intel_ring_begin(ring, 6);
9315 if (ret)
9316 return ret;
9317
9318 /* Can't queue multiple flips, so wait for the previous
9319 * one to finish before executing the next.
9320 */
9321 if (intel_crtc->plane)
9322 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9323 else
9324 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9325 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9326 intel_ring_emit(ring, MI_NOOP);
9327 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9328 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9329 intel_ring_emit(ring, fb->pitches[0]);
9330 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9331 intel_ring_emit(ring, 0); /* aux display base address, unused */
9332
9333 intel_mark_page_flip_active(intel_crtc);
9334 __intel_ring_advance(ring);
9335 return 0;
9336 }
9337
9338 static int intel_gen3_queue_flip(struct drm_device *dev,
9339 struct drm_crtc *crtc,
9340 struct drm_framebuffer *fb,
9341 struct drm_i915_gem_object *obj,
9342 struct intel_engine_cs *ring,
9343 uint32_t flags)
9344 {
9345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9346 u32 flip_mask;
9347 int ret;
9348
9349 ret = intel_ring_begin(ring, 6);
9350 if (ret)
9351 return ret;
9352
9353 if (intel_crtc->plane)
9354 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9355 else
9356 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9357 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9358 intel_ring_emit(ring, MI_NOOP);
9359 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9360 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9361 intel_ring_emit(ring, fb->pitches[0]);
9362 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9363 intel_ring_emit(ring, MI_NOOP);
9364
9365 intel_mark_page_flip_active(intel_crtc);
9366 __intel_ring_advance(ring);
9367 return 0;
9368 }
9369
9370 static int intel_gen4_queue_flip(struct drm_device *dev,
9371 struct drm_crtc *crtc,
9372 struct drm_framebuffer *fb,
9373 struct drm_i915_gem_object *obj,
9374 struct intel_engine_cs *ring,
9375 uint32_t flags)
9376 {
9377 struct drm_i915_private *dev_priv = dev->dev_private;
9378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9379 uint32_t pf, pipesrc;
9380 int ret;
9381
9382 ret = intel_ring_begin(ring, 4);
9383 if (ret)
9384 return ret;
9385
9386 /* i965+ uses the linear or tiled offsets from the
9387 * Display Registers (which do not change across a page-flip)
9388 * so we need only reprogram the base address.
9389 */
9390 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9391 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9392 intel_ring_emit(ring, fb->pitches[0]);
9393 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9394 obj->tiling_mode);
9395
9396 /* XXX Enabling the panel-fitter across page-flip is so far
9397 * untested on non-native modes, so ignore it for now.
9398 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9399 */
9400 pf = 0;
9401 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9402 intel_ring_emit(ring, pf | pipesrc);
9403
9404 intel_mark_page_flip_active(intel_crtc);
9405 __intel_ring_advance(ring);
9406 return 0;
9407 }
9408
9409 static int intel_gen6_queue_flip(struct drm_device *dev,
9410 struct drm_crtc *crtc,
9411 struct drm_framebuffer *fb,
9412 struct drm_i915_gem_object *obj,
9413 struct intel_engine_cs *ring,
9414 uint32_t flags)
9415 {
9416 struct drm_i915_private *dev_priv = dev->dev_private;
9417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9418 uint32_t pf, pipesrc;
9419 int ret;
9420
9421 ret = intel_ring_begin(ring, 4);
9422 if (ret)
9423 return ret;
9424
9425 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9426 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9427 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9428 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9429
9430 /* Contrary to the suggestions in the documentation,
9431 * "Enable Panel Fitter" does not seem to be required when page
9432 * flipping with a non-native mode, and worse causes a normal
9433 * modeset to fail.
9434 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9435 */
9436 pf = 0;
9437 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9438 intel_ring_emit(ring, pf | pipesrc);
9439
9440 intel_mark_page_flip_active(intel_crtc);
9441 __intel_ring_advance(ring);
9442 return 0;
9443 }
9444
9445 static int intel_gen7_queue_flip(struct drm_device *dev,
9446 struct drm_crtc *crtc,
9447 struct drm_framebuffer *fb,
9448 struct drm_i915_gem_object *obj,
9449 struct intel_engine_cs *ring,
9450 uint32_t flags)
9451 {
9452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9453 uint32_t plane_bit = 0;
9454 int len, ret;
9455
9456 switch (intel_crtc->plane) {
9457 case PLANE_A:
9458 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9459 break;
9460 case PLANE_B:
9461 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9462 break;
9463 case PLANE_C:
9464 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9465 break;
9466 default:
9467 WARN_ONCE(1, "unknown plane in flip command\n");
9468 return -ENODEV;
9469 }
9470
9471 len = 4;
9472 if (ring->id == RCS) {
9473 len += 6;
9474 /*
9475 * On Gen 8, SRM is now taking an extra dword to accommodate
9476 * 48bits addresses, and we need a NOOP for the batch size to
9477 * stay even.
9478 */
9479 if (IS_GEN8(dev))
9480 len += 2;
9481 }
9482
9483 /*
9484 * BSpec MI_DISPLAY_FLIP for IVB:
9485 * "The full packet must be contained within the same cache line."
9486 *
9487 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9488 * cacheline, if we ever start emitting more commands before
9489 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9490 * then do the cacheline alignment, and finally emit the
9491 * MI_DISPLAY_FLIP.
9492 */
9493 ret = intel_ring_cacheline_align(ring);
9494 if (ret)
9495 return ret;
9496
9497 ret = intel_ring_begin(ring, len);
9498 if (ret)
9499 return ret;
9500
9501 /* Unmask the flip-done completion message. Note that the bspec says that
9502 * we should do this for both the BCS and RCS, and that we must not unmask
9503 * more than one flip event at any time (or ensure that one flip message
9504 * can be sent by waiting for flip-done prior to queueing new flips).
9505 * Experimentation says that BCS works despite DERRMR masking all
9506 * flip-done completion events and that unmasking all planes at once
9507 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9508 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9509 */
9510 if (ring->id == RCS) {
9511 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9512 intel_ring_emit(ring, DERRMR);
9513 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9514 DERRMR_PIPEB_PRI_FLIP_DONE |
9515 DERRMR_PIPEC_PRI_FLIP_DONE));
9516 if (IS_GEN8(dev))
9517 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9518 MI_SRM_LRM_GLOBAL_GTT);
9519 else
9520 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9521 MI_SRM_LRM_GLOBAL_GTT);
9522 intel_ring_emit(ring, DERRMR);
9523 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9524 if (IS_GEN8(dev)) {
9525 intel_ring_emit(ring, 0);
9526 intel_ring_emit(ring, MI_NOOP);
9527 }
9528 }
9529
9530 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9531 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9532 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9533 intel_ring_emit(ring, (MI_NOOP));
9534
9535 intel_mark_page_flip_active(intel_crtc);
9536 __intel_ring_advance(ring);
9537 return 0;
9538 }
9539
9540 static bool use_mmio_flip(struct intel_engine_cs *ring,
9541 struct drm_i915_gem_object *obj)
9542 {
9543 /*
9544 * This is not being used for older platforms, because
9545 * non-availability of flip done interrupt forces us to use
9546 * CS flips. Older platforms derive flip done using some clever
9547 * tricks involving the flip_pending status bits and vblank irqs.
9548 * So using MMIO flips there would disrupt this mechanism.
9549 */
9550
9551 if (ring == NULL)
9552 return true;
9553
9554 if (INTEL_INFO(ring->dev)->gen < 5)
9555 return false;
9556
9557 if (i915.use_mmio_flip < 0)
9558 return false;
9559 else if (i915.use_mmio_flip > 0)
9560 return true;
9561 else if (i915.enable_execlists)
9562 return true;
9563 else
9564 return ring != obj->ring;
9565 }
9566
9567 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9568 {
9569 struct drm_device *dev = intel_crtc->base.dev;
9570 struct drm_i915_private *dev_priv = dev->dev_private;
9571 struct intel_framebuffer *intel_fb =
9572 to_intel_framebuffer(intel_crtc->base.primary->fb);
9573 struct drm_i915_gem_object *obj = intel_fb->obj;
9574 u32 dspcntr;
9575 u32 reg;
9576
9577 intel_mark_page_flip_active(intel_crtc);
9578
9579 reg = DSPCNTR(intel_crtc->plane);
9580 dspcntr = I915_READ(reg);
9581
9582 if (INTEL_INFO(dev)->gen >= 4) {
9583 if (obj->tiling_mode != I915_TILING_NONE)
9584 dspcntr |= DISPPLANE_TILED;
9585 else
9586 dspcntr &= ~DISPPLANE_TILED;
9587 }
9588 I915_WRITE(reg, dspcntr);
9589
9590 I915_WRITE(DSPSURF(intel_crtc->plane),
9591 intel_crtc->unpin_work->gtt_offset);
9592 POSTING_READ(DSPSURF(intel_crtc->plane));
9593 }
9594
9595 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9596 {
9597 struct intel_engine_cs *ring;
9598 int ret;
9599
9600 lockdep_assert_held(&obj->base.dev->struct_mutex);
9601
9602 if (!obj->last_write_seqno)
9603 return 0;
9604
9605 ring = obj->ring;
9606
9607 if (i915_seqno_passed(ring->get_seqno(ring, true),
9608 obj->last_write_seqno))
9609 return 0;
9610
9611 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9612 if (ret)
9613 return ret;
9614
9615 if (WARN_ON(!ring->irq_get(ring)))
9616 return 0;
9617
9618 return 1;
9619 }
9620
9621 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9622 {
9623 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9624 struct intel_crtc *intel_crtc;
9625 unsigned long irq_flags;
9626 u32 seqno;
9627
9628 seqno = ring->get_seqno(ring, false);
9629
9630 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9631 for_each_intel_crtc(ring->dev, intel_crtc) {
9632 struct intel_mmio_flip *mmio_flip;
9633
9634 mmio_flip = &intel_crtc->mmio_flip;
9635 if (mmio_flip->seqno == 0)
9636 continue;
9637
9638 if (ring->id != mmio_flip->ring_id)
9639 continue;
9640
9641 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9642 intel_do_mmio_flip(intel_crtc);
9643 mmio_flip->seqno = 0;
9644 ring->irq_put(ring);
9645 }
9646 }
9647 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9648 }
9649
9650 static int intel_queue_mmio_flip(struct drm_device *dev,
9651 struct drm_crtc *crtc,
9652 struct drm_framebuffer *fb,
9653 struct drm_i915_gem_object *obj,
9654 struct intel_engine_cs *ring,
9655 uint32_t flags)
9656 {
9657 struct drm_i915_private *dev_priv = dev->dev_private;
9658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9659 unsigned long irq_flags;
9660 int ret;
9661
9662 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9663 return -EBUSY;
9664
9665 ret = intel_postpone_flip(obj);
9666 if (ret < 0)
9667 return ret;
9668 if (ret == 0) {
9669 intel_do_mmio_flip(intel_crtc);
9670 return 0;
9671 }
9672
9673 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9674 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9675 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9676 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9677
9678 /*
9679 * Double check to catch cases where irq fired before
9680 * mmio flip data was ready
9681 */
9682 intel_notify_mmio_flip(obj->ring);
9683 return 0;
9684 }
9685
9686 static int intel_default_queue_flip(struct drm_device *dev,
9687 struct drm_crtc *crtc,
9688 struct drm_framebuffer *fb,
9689 struct drm_i915_gem_object *obj,
9690 struct intel_engine_cs *ring,
9691 uint32_t flags)
9692 {
9693 return -ENODEV;
9694 }
9695
9696 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9697 struct drm_framebuffer *fb,
9698 struct drm_pending_vblank_event *event,
9699 uint32_t page_flip_flags)
9700 {
9701 struct drm_device *dev = crtc->dev;
9702 struct drm_i915_private *dev_priv = dev->dev_private;
9703 struct drm_framebuffer *old_fb = crtc->primary->fb;
9704 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9706 enum pipe pipe = intel_crtc->pipe;
9707 struct intel_unpin_work *work;
9708 struct intel_engine_cs *ring;
9709 unsigned long flags;
9710 int ret;
9711
9712 /*
9713 * drm_mode_page_flip_ioctl() should already catch this, but double
9714 * check to be safe. In the future we may enable pageflipping from
9715 * a disabled primary plane.
9716 */
9717 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9718 return -EBUSY;
9719
9720 /* Can't change pixel format via MI display flips. */
9721 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9722 return -EINVAL;
9723
9724 /*
9725 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9726 * Note that pitch changes could also affect these register.
9727 */
9728 if (INTEL_INFO(dev)->gen > 3 &&
9729 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9730 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9731 return -EINVAL;
9732
9733 if (i915_terminally_wedged(&dev_priv->gpu_error))
9734 goto out_hang;
9735
9736 work = kzalloc(sizeof(*work), GFP_KERNEL);
9737 if (work == NULL)
9738 return -ENOMEM;
9739
9740 work->event = event;
9741 work->crtc = crtc;
9742 work->old_fb_obj = intel_fb_obj(old_fb);
9743 INIT_WORK(&work->work, intel_unpin_work_fn);
9744
9745 ret = drm_crtc_vblank_get(crtc);
9746 if (ret)
9747 goto free_work;
9748
9749 /* We borrow the event spin lock for protecting unpin_work */
9750 spin_lock_irqsave(&dev->event_lock, flags);
9751 if (intel_crtc->unpin_work) {
9752 spin_unlock_irqrestore(&dev->event_lock, flags);
9753 kfree(work);
9754 drm_crtc_vblank_put(crtc);
9755
9756 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9757 return -EBUSY;
9758 }
9759 intel_crtc->unpin_work = work;
9760 spin_unlock_irqrestore(&dev->event_lock, flags);
9761
9762 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9763 flush_workqueue(dev_priv->wq);
9764
9765 ret = i915_mutex_lock_interruptible(dev);
9766 if (ret)
9767 goto cleanup;
9768
9769 /* Reference the objects for the scheduled work. */
9770 drm_gem_object_reference(&work->old_fb_obj->base);
9771 drm_gem_object_reference(&obj->base);
9772
9773 crtc->primary->fb = fb;
9774
9775 work->pending_flip_obj = obj;
9776
9777 work->enable_stall_check = true;
9778
9779 atomic_inc(&intel_crtc->unpin_work_count);
9780 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9781
9782 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9783 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9784
9785 if (IS_VALLEYVIEW(dev)) {
9786 ring = &dev_priv->ring[BCS];
9787 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9788 /* vlv: DISPLAY_FLIP fails to change tiling */
9789 ring = NULL;
9790 } else if (IS_IVYBRIDGE(dev)) {
9791 ring = &dev_priv->ring[BCS];
9792 } else if (INTEL_INFO(dev)->gen >= 7) {
9793 ring = obj->ring;
9794 if (ring == NULL || ring->id != RCS)
9795 ring = &dev_priv->ring[BCS];
9796 } else {
9797 ring = &dev_priv->ring[RCS];
9798 }
9799
9800 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9801 if (ret)
9802 goto cleanup_pending;
9803
9804 work->gtt_offset =
9805 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9806
9807 if (use_mmio_flip(ring, obj))
9808 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9809 page_flip_flags);
9810 else
9811 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9812 page_flip_flags);
9813 if (ret)
9814 goto cleanup_unpin;
9815
9816 i915_gem_track_fb(work->old_fb_obj, obj,
9817 INTEL_FRONTBUFFER_PRIMARY(pipe));
9818
9819 intel_disable_fbc(dev);
9820 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9821 mutex_unlock(&dev->struct_mutex);
9822
9823 trace_i915_flip_request(intel_crtc->plane, obj);
9824
9825 return 0;
9826
9827 cleanup_unpin:
9828 intel_unpin_fb_obj(obj);
9829 cleanup_pending:
9830 atomic_dec(&intel_crtc->unpin_work_count);
9831 crtc->primary->fb = old_fb;
9832 drm_gem_object_unreference(&work->old_fb_obj->base);
9833 drm_gem_object_unreference(&obj->base);
9834 mutex_unlock(&dev->struct_mutex);
9835
9836 cleanup:
9837 spin_lock_irqsave(&dev->event_lock, flags);
9838 intel_crtc->unpin_work = NULL;
9839 spin_unlock_irqrestore(&dev->event_lock, flags);
9840
9841 drm_crtc_vblank_put(crtc);
9842 free_work:
9843 kfree(work);
9844
9845 if (ret == -EIO) {
9846 out_hang:
9847 intel_crtc_wait_for_pending_flips(crtc);
9848 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9849 if (ret == 0 && event)
9850 drm_send_vblank_event(dev, pipe, event);
9851 }
9852 return ret;
9853 }
9854
9855 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9856 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9857 .load_lut = intel_crtc_load_lut,
9858 };
9859
9860 /**
9861 * intel_modeset_update_staged_output_state
9862 *
9863 * Updates the staged output configuration state, e.g. after we've read out the
9864 * current hw state.
9865 */
9866 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9867 {
9868 struct intel_crtc *crtc;
9869 struct intel_encoder *encoder;
9870 struct intel_connector *connector;
9871
9872 list_for_each_entry(connector, &dev->mode_config.connector_list,
9873 base.head) {
9874 connector->new_encoder =
9875 to_intel_encoder(connector->base.encoder);
9876 }
9877
9878 for_each_intel_encoder(dev, encoder) {
9879 encoder->new_crtc =
9880 to_intel_crtc(encoder->base.crtc);
9881 }
9882
9883 for_each_intel_crtc(dev, crtc) {
9884 crtc->new_enabled = crtc->base.enabled;
9885
9886 if (crtc->new_enabled)
9887 crtc->new_config = &crtc->config;
9888 else
9889 crtc->new_config = NULL;
9890 }
9891 }
9892
9893 /**
9894 * intel_modeset_commit_output_state
9895 *
9896 * This function copies the stage display pipe configuration to the real one.
9897 */
9898 static void intel_modeset_commit_output_state(struct drm_device *dev)
9899 {
9900 struct intel_crtc *crtc;
9901 struct intel_encoder *encoder;
9902 struct intel_connector *connector;
9903
9904 list_for_each_entry(connector, &dev->mode_config.connector_list,
9905 base.head) {
9906 connector->base.encoder = &connector->new_encoder->base;
9907 }
9908
9909 for_each_intel_encoder(dev, encoder) {
9910 encoder->base.crtc = &encoder->new_crtc->base;
9911 }
9912
9913 for_each_intel_crtc(dev, crtc) {
9914 crtc->base.enabled = crtc->new_enabled;
9915 }
9916 }
9917
9918 static void
9919 connected_sink_compute_bpp(struct intel_connector *connector,
9920 struct intel_crtc_config *pipe_config)
9921 {
9922 int bpp = pipe_config->pipe_bpp;
9923
9924 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9925 connector->base.base.id,
9926 connector->base.name);
9927
9928 /* Don't use an invalid EDID bpc value */
9929 if (connector->base.display_info.bpc &&
9930 connector->base.display_info.bpc * 3 < bpp) {
9931 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9932 bpp, connector->base.display_info.bpc*3);
9933 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9934 }
9935
9936 /* Clamp bpp to 8 on screens without EDID 1.4 */
9937 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9938 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9939 bpp);
9940 pipe_config->pipe_bpp = 24;
9941 }
9942 }
9943
9944 static int
9945 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9946 struct drm_framebuffer *fb,
9947 struct intel_crtc_config *pipe_config)
9948 {
9949 struct drm_device *dev = crtc->base.dev;
9950 struct intel_connector *connector;
9951 int bpp;
9952
9953 switch (fb->pixel_format) {
9954 case DRM_FORMAT_C8:
9955 bpp = 8*3; /* since we go through a colormap */
9956 break;
9957 case DRM_FORMAT_XRGB1555:
9958 case DRM_FORMAT_ARGB1555:
9959 /* checked in intel_framebuffer_init already */
9960 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9961 return -EINVAL;
9962 case DRM_FORMAT_RGB565:
9963 bpp = 6*3; /* min is 18bpp */
9964 break;
9965 case DRM_FORMAT_XBGR8888:
9966 case DRM_FORMAT_ABGR8888:
9967 /* checked in intel_framebuffer_init already */
9968 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9969 return -EINVAL;
9970 case DRM_FORMAT_XRGB8888:
9971 case DRM_FORMAT_ARGB8888:
9972 bpp = 8*3;
9973 break;
9974 case DRM_FORMAT_XRGB2101010:
9975 case DRM_FORMAT_ARGB2101010:
9976 case DRM_FORMAT_XBGR2101010:
9977 case DRM_FORMAT_ABGR2101010:
9978 /* checked in intel_framebuffer_init already */
9979 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9980 return -EINVAL;
9981 bpp = 10*3;
9982 break;
9983 /* TODO: gen4+ supports 16 bpc floating point, too. */
9984 default:
9985 DRM_DEBUG_KMS("unsupported depth\n");
9986 return -EINVAL;
9987 }
9988
9989 pipe_config->pipe_bpp = bpp;
9990
9991 /* Clamp display bpp to EDID value */
9992 list_for_each_entry(connector, &dev->mode_config.connector_list,
9993 base.head) {
9994 if (!connector->new_encoder ||
9995 connector->new_encoder->new_crtc != crtc)
9996 continue;
9997
9998 connected_sink_compute_bpp(connector, pipe_config);
9999 }
10000
10001 return bpp;
10002 }
10003
10004 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10005 {
10006 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10007 "type: 0x%x flags: 0x%x\n",
10008 mode->crtc_clock,
10009 mode->crtc_hdisplay, mode->crtc_hsync_start,
10010 mode->crtc_hsync_end, mode->crtc_htotal,
10011 mode->crtc_vdisplay, mode->crtc_vsync_start,
10012 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10013 }
10014
10015 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10016 struct intel_crtc_config *pipe_config,
10017 const char *context)
10018 {
10019 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10020 context, pipe_name(crtc->pipe));
10021
10022 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10023 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10024 pipe_config->pipe_bpp, pipe_config->dither);
10025 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10026 pipe_config->has_pch_encoder,
10027 pipe_config->fdi_lanes,
10028 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10029 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10030 pipe_config->fdi_m_n.tu);
10031 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10032 pipe_config->has_dp_encoder,
10033 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10034 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10035 pipe_config->dp_m_n.tu);
10036
10037 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10038 pipe_config->has_dp_encoder,
10039 pipe_config->dp_m2_n2.gmch_m,
10040 pipe_config->dp_m2_n2.gmch_n,
10041 pipe_config->dp_m2_n2.link_m,
10042 pipe_config->dp_m2_n2.link_n,
10043 pipe_config->dp_m2_n2.tu);
10044
10045 DRM_DEBUG_KMS("requested mode:\n");
10046 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10047 DRM_DEBUG_KMS("adjusted mode:\n");
10048 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10049 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10050 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10051 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10052 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10053 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10054 pipe_config->gmch_pfit.control,
10055 pipe_config->gmch_pfit.pgm_ratios,
10056 pipe_config->gmch_pfit.lvds_border_bits);
10057 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10058 pipe_config->pch_pfit.pos,
10059 pipe_config->pch_pfit.size,
10060 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10061 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10062 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10063 }
10064
10065 static bool encoders_cloneable(const struct intel_encoder *a,
10066 const struct intel_encoder *b)
10067 {
10068 /* masks could be asymmetric, so check both ways */
10069 return a == b || (a->cloneable & (1 << b->type) &&
10070 b->cloneable & (1 << a->type));
10071 }
10072
10073 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10074 struct intel_encoder *encoder)
10075 {
10076 struct drm_device *dev = crtc->base.dev;
10077 struct intel_encoder *source_encoder;
10078
10079 for_each_intel_encoder(dev, source_encoder) {
10080 if (source_encoder->new_crtc != crtc)
10081 continue;
10082
10083 if (!encoders_cloneable(encoder, source_encoder))
10084 return false;
10085 }
10086
10087 return true;
10088 }
10089
10090 static bool check_encoder_cloning(struct intel_crtc *crtc)
10091 {
10092 struct drm_device *dev = crtc->base.dev;
10093 struct intel_encoder *encoder;
10094
10095 for_each_intel_encoder(dev, encoder) {
10096 if (encoder->new_crtc != crtc)
10097 continue;
10098
10099 if (!check_single_encoder_cloning(crtc, encoder))
10100 return false;
10101 }
10102
10103 return true;
10104 }
10105
10106 static struct intel_crtc_config *
10107 intel_modeset_pipe_config(struct drm_crtc *crtc,
10108 struct drm_framebuffer *fb,
10109 struct drm_display_mode *mode)
10110 {
10111 struct drm_device *dev = crtc->dev;
10112 struct intel_encoder *encoder;
10113 struct intel_crtc_config *pipe_config;
10114 int plane_bpp, ret = -EINVAL;
10115 bool retry = true;
10116
10117 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10118 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10119 return ERR_PTR(-EINVAL);
10120 }
10121
10122 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10123 if (!pipe_config)
10124 return ERR_PTR(-ENOMEM);
10125
10126 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10127 drm_mode_copy(&pipe_config->requested_mode, mode);
10128
10129 pipe_config->cpu_transcoder =
10130 (enum transcoder) to_intel_crtc(crtc)->pipe;
10131 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10132
10133 /*
10134 * Sanitize sync polarity flags based on requested ones. If neither
10135 * positive or negative polarity is requested, treat this as meaning
10136 * negative polarity.
10137 */
10138 if (!(pipe_config->adjusted_mode.flags &
10139 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10140 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10141
10142 if (!(pipe_config->adjusted_mode.flags &
10143 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10144 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10145
10146 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10147 * plane pixel format and any sink constraints into account. Returns the
10148 * source plane bpp so that dithering can be selected on mismatches
10149 * after encoders and crtc also have had their say. */
10150 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10151 fb, pipe_config);
10152 if (plane_bpp < 0)
10153 goto fail;
10154
10155 /*
10156 * Determine the real pipe dimensions. Note that stereo modes can
10157 * increase the actual pipe size due to the frame doubling and
10158 * insertion of additional space for blanks between the frame. This
10159 * is stored in the crtc timings. We use the requested mode to do this
10160 * computation to clearly distinguish it from the adjusted mode, which
10161 * can be changed by the connectors in the below retry loop.
10162 */
10163 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10164 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10165 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10166
10167 encoder_retry:
10168 /* Ensure the port clock defaults are reset when retrying. */
10169 pipe_config->port_clock = 0;
10170 pipe_config->pixel_multiplier = 1;
10171
10172 /* Fill in default crtc timings, allow encoders to overwrite them. */
10173 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10174
10175 /* Pass our mode to the connectors and the CRTC to give them a chance to
10176 * adjust it according to limitations or connector properties, and also
10177 * a chance to reject the mode entirely.
10178 */
10179 for_each_intel_encoder(dev, encoder) {
10180
10181 if (&encoder->new_crtc->base != crtc)
10182 continue;
10183
10184 if (!(encoder->compute_config(encoder, pipe_config))) {
10185 DRM_DEBUG_KMS("Encoder config failure\n");
10186 goto fail;
10187 }
10188 }
10189
10190 /* Set default port clock if not overwritten by the encoder. Needs to be
10191 * done afterwards in case the encoder adjusts the mode. */
10192 if (!pipe_config->port_clock)
10193 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10194 * pipe_config->pixel_multiplier;
10195
10196 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10197 if (ret < 0) {
10198 DRM_DEBUG_KMS("CRTC fixup failed\n");
10199 goto fail;
10200 }
10201
10202 if (ret == RETRY) {
10203 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10204 ret = -EINVAL;
10205 goto fail;
10206 }
10207
10208 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10209 retry = false;
10210 goto encoder_retry;
10211 }
10212
10213 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10214 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10215 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10216
10217 return pipe_config;
10218 fail:
10219 kfree(pipe_config);
10220 return ERR_PTR(ret);
10221 }
10222
10223 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10224 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10225 static void
10226 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10227 unsigned *prepare_pipes, unsigned *disable_pipes)
10228 {
10229 struct intel_crtc *intel_crtc;
10230 struct drm_device *dev = crtc->dev;
10231 struct intel_encoder *encoder;
10232 struct intel_connector *connector;
10233 struct drm_crtc *tmp_crtc;
10234
10235 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10236
10237 /* Check which crtcs have changed outputs connected to them, these need
10238 * to be part of the prepare_pipes mask. We don't (yet) support global
10239 * modeset across multiple crtcs, so modeset_pipes will only have one
10240 * bit set at most. */
10241 list_for_each_entry(connector, &dev->mode_config.connector_list,
10242 base.head) {
10243 if (connector->base.encoder == &connector->new_encoder->base)
10244 continue;
10245
10246 if (connector->base.encoder) {
10247 tmp_crtc = connector->base.encoder->crtc;
10248
10249 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10250 }
10251
10252 if (connector->new_encoder)
10253 *prepare_pipes |=
10254 1 << connector->new_encoder->new_crtc->pipe;
10255 }
10256
10257 for_each_intel_encoder(dev, encoder) {
10258 if (encoder->base.crtc == &encoder->new_crtc->base)
10259 continue;
10260
10261 if (encoder->base.crtc) {
10262 tmp_crtc = encoder->base.crtc;
10263
10264 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10265 }
10266
10267 if (encoder->new_crtc)
10268 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10269 }
10270
10271 /* Check for pipes that will be enabled/disabled ... */
10272 for_each_intel_crtc(dev, intel_crtc) {
10273 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10274 continue;
10275
10276 if (!intel_crtc->new_enabled)
10277 *disable_pipes |= 1 << intel_crtc->pipe;
10278 else
10279 *prepare_pipes |= 1 << intel_crtc->pipe;
10280 }
10281
10282
10283 /* set_mode is also used to update properties on life display pipes. */
10284 intel_crtc = to_intel_crtc(crtc);
10285 if (intel_crtc->new_enabled)
10286 *prepare_pipes |= 1 << intel_crtc->pipe;
10287
10288 /*
10289 * For simplicity do a full modeset on any pipe where the output routing
10290 * changed. We could be more clever, but that would require us to be
10291 * more careful with calling the relevant encoder->mode_set functions.
10292 */
10293 if (*prepare_pipes)
10294 *modeset_pipes = *prepare_pipes;
10295
10296 /* ... and mask these out. */
10297 *modeset_pipes &= ~(*disable_pipes);
10298 *prepare_pipes &= ~(*disable_pipes);
10299
10300 /*
10301 * HACK: We don't (yet) fully support global modesets. intel_set_config
10302 * obies this rule, but the modeset restore mode of
10303 * intel_modeset_setup_hw_state does not.
10304 */
10305 *modeset_pipes &= 1 << intel_crtc->pipe;
10306 *prepare_pipes &= 1 << intel_crtc->pipe;
10307
10308 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10309 *modeset_pipes, *prepare_pipes, *disable_pipes);
10310 }
10311
10312 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10313 {
10314 struct drm_encoder *encoder;
10315 struct drm_device *dev = crtc->dev;
10316
10317 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10318 if (encoder->crtc == crtc)
10319 return true;
10320
10321 return false;
10322 }
10323
10324 static void
10325 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10326 {
10327 struct intel_encoder *intel_encoder;
10328 struct intel_crtc *intel_crtc;
10329 struct drm_connector *connector;
10330
10331 for_each_intel_encoder(dev, intel_encoder) {
10332 if (!intel_encoder->base.crtc)
10333 continue;
10334
10335 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10336
10337 if (prepare_pipes & (1 << intel_crtc->pipe))
10338 intel_encoder->connectors_active = false;
10339 }
10340
10341 intel_modeset_commit_output_state(dev);
10342
10343 /* Double check state. */
10344 for_each_intel_crtc(dev, intel_crtc) {
10345 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10346 WARN_ON(intel_crtc->new_config &&
10347 intel_crtc->new_config != &intel_crtc->config);
10348 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10349 }
10350
10351 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10352 if (!connector->encoder || !connector->encoder->crtc)
10353 continue;
10354
10355 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10356
10357 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10358 struct drm_property *dpms_property =
10359 dev->mode_config.dpms_property;
10360
10361 connector->dpms = DRM_MODE_DPMS_ON;
10362 drm_object_property_set_value(&connector->base,
10363 dpms_property,
10364 DRM_MODE_DPMS_ON);
10365
10366 intel_encoder = to_intel_encoder(connector->encoder);
10367 intel_encoder->connectors_active = true;
10368 }
10369 }
10370
10371 }
10372
10373 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10374 {
10375 int diff;
10376
10377 if (clock1 == clock2)
10378 return true;
10379
10380 if (!clock1 || !clock2)
10381 return false;
10382
10383 diff = abs(clock1 - clock2);
10384
10385 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10386 return true;
10387
10388 return false;
10389 }
10390
10391 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10392 list_for_each_entry((intel_crtc), \
10393 &(dev)->mode_config.crtc_list, \
10394 base.head) \
10395 if (mask & (1 <<(intel_crtc)->pipe))
10396
10397 static bool
10398 intel_pipe_config_compare(struct drm_device *dev,
10399 struct intel_crtc_config *current_config,
10400 struct intel_crtc_config *pipe_config)
10401 {
10402 #define PIPE_CONF_CHECK_X(name) \
10403 if (current_config->name != pipe_config->name) { \
10404 DRM_ERROR("mismatch in " #name " " \
10405 "(expected 0x%08x, found 0x%08x)\n", \
10406 current_config->name, \
10407 pipe_config->name); \
10408 return false; \
10409 }
10410
10411 #define PIPE_CONF_CHECK_I(name) \
10412 if (current_config->name != pipe_config->name) { \
10413 DRM_ERROR("mismatch in " #name " " \
10414 "(expected %i, found %i)\n", \
10415 current_config->name, \
10416 pipe_config->name); \
10417 return false; \
10418 }
10419
10420 /* This is required for BDW+ where there is only one set of registers for
10421 * switching between high and low RR.
10422 * This macro can be used whenever a comparison has to be made between one
10423 * hw state and multiple sw state variables.
10424 */
10425 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10426 if ((current_config->name != pipe_config->name) && \
10427 (current_config->alt_name != pipe_config->name)) { \
10428 DRM_ERROR("mismatch in " #name " " \
10429 "(expected %i or %i, found %i)\n", \
10430 current_config->name, \
10431 current_config->alt_name, \
10432 pipe_config->name); \
10433 return false; \
10434 }
10435
10436 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10437 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10438 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10439 "(expected %i, found %i)\n", \
10440 current_config->name & (mask), \
10441 pipe_config->name & (mask)); \
10442 return false; \
10443 }
10444
10445 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10446 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10447 DRM_ERROR("mismatch in " #name " " \
10448 "(expected %i, found %i)\n", \
10449 current_config->name, \
10450 pipe_config->name); \
10451 return false; \
10452 }
10453
10454 #define PIPE_CONF_QUIRK(quirk) \
10455 ((current_config->quirks | pipe_config->quirks) & (quirk))
10456
10457 PIPE_CONF_CHECK_I(cpu_transcoder);
10458
10459 PIPE_CONF_CHECK_I(has_pch_encoder);
10460 PIPE_CONF_CHECK_I(fdi_lanes);
10461 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10462 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10463 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10464 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10465 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10466
10467 PIPE_CONF_CHECK_I(has_dp_encoder);
10468
10469 if (INTEL_INFO(dev)->gen < 8) {
10470 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10471 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10472 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10473 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10474 PIPE_CONF_CHECK_I(dp_m_n.tu);
10475
10476 if (current_config->has_drrs) {
10477 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10478 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10479 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10480 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10481 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10482 }
10483 } else {
10484 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10485 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10486 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10487 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10488 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10489 }
10490
10491 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10492 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10493 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10494 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10495 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10496 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10497
10498 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10499 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10500 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10501 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10502 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10503 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10504
10505 PIPE_CONF_CHECK_I(pixel_multiplier);
10506 PIPE_CONF_CHECK_I(has_hdmi_sink);
10507 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10508 IS_VALLEYVIEW(dev))
10509 PIPE_CONF_CHECK_I(limited_color_range);
10510
10511 PIPE_CONF_CHECK_I(has_audio);
10512
10513 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10514 DRM_MODE_FLAG_INTERLACE);
10515
10516 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10517 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10518 DRM_MODE_FLAG_PHSYNC);
10519 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10520 DRM_MODE_FLAG_NHSYNC);
10521 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10522 DRM_MODE_FLAG_PVSYNC);
10523 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10524 DRM_MODE_FLAG_NVSYNC);
10525 }
10526
10527 PIPE_CONF_CHECK_I(pipe_src_w);
10528 PIPE_CONF_CHECK_I(pipe_src_h);
10529
10530 /*
10531 * FIXME: BIOS likes to set up a cloned config with lvds+external
10532 * screen. Since we don't yet re-compute the pipe config when moving
10533 * just the lvds port away to another pipe the sw tracking won't match.
10534 *
10535 * Proper atomic modesets with recomputed global state will fix this.
10536 * Until then just don't check gmch state for inherited modes.
10537 */
10538 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10539 PIPE_CONF_CHECK_I(gmch_pfit.control);
10540 /* pfit ratios are autocomputed by the hw on gen4+ */
10541 if (INTEL_INFO(dev)->gen < 4)
10542 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10543 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10544 }
10545
10546 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10547 if (current_config->pch_pfit.enabled) {
10548 PIPE_CONF_CHECK_I(pch_pfit.pos);
10549 PIPE_CONF_CHECK_I(pch_pfit.size);
10550 }
10551
10552 /* BDW+ don't expose a synchronous way to read the state */
10553 if (IS_HASWELL(dev))
10554 PIPE_CONF_CHECK_I(ips_enabled);
10555
10556 PIPE_CONF_CHECK_I(double_wide);
10557
10558 PIPE_CONF_CHECK_X(ddi_pll_sel);
10559
10560 PIPE_CONF_CHECK_I(shared_dpll);
10561 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10562 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10563 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10564 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10565 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10566
10567 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10568 PIPE_CONF_CHECK_I(pipe_bpp);
10569
10570 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10571 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10572
10573 #undef PIPE_CONF_CHECK_X
10574 #undef PIPE_CONF_CHECK_I
10575 #undef PIPE_CONF_CHECK_I_ALT
10576 #undef PIPE_CONF_CHECK_FLAGS
10577 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10578 #undef PIPE_CONF_QUIRK
10579
10580 return true;
10581 }
10582
10583 static void
10584 check_connector_state(struct drm_device *dev)
10585 {
10586 struct intel_connector *connector;
10587
10588 list_for_each_entry(connector, &dev->mode_config.connector_list,
10589 base.head) {
10590 /* This also checks the encoder/connector hw state with the
10591 * ->get_hw_state callbacks. */
10592 intel_connector_check_state(connector);
10593
10594 WARN(&connector->new_encoder->base != connector->base.encoder,
10595 "connector's staged encoder doesn't match current encoder\n");
10596 }
10597 }
10598
10599 static void
10600 check_encoder_state(struct drm_device *dev)
10601 {
10602 struct intel_encoder *encoder;
10603 struct intel_connector *connector;
10604
10605 for_each_intel_encoder(dev, encoder) {
10606 bool enabled = false;
10607 bool active = false;
10608 enum pipe pipe, tracked_pipe;
10609
10610 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10611 encoder->base.base.id,
10612 encoder->base.name);
10613
10614 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10615 "encoder's stage crtc doesn't match current crtc\n");
10616 WARN(encoder->connectors_active && !encoder->base.crtc,
10617 "encoder's active_connectors set, but no crtc\n");
10618
10619 list_for_each_entry(connector, &dev->mode_config.connector_list,
10620 base.head) {
10621 if (connector->base.encoder != &encoder->base)
10622 continue;
10623 enabled = true;
10624 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10625 active = true;
10626 }
10627 /*
10628 * for MST connectors if we unplug the connector is gone
10629 * away but the encoder is still connected to a crtc
10630 * until a modeset happens in response to the hotplug.
10631 */
10632 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10633 continue;
10634
10635 WARN(!!encoder->base.crtc != enabled,
10636 "encoder's enabled state mismatch "
10637 "(expected %i, found %i)\n",
10638 !!encoder->base.crtc, enabled);
10639 WARN(active && !encoder->base.crtc,
10640 "active encoder with no crtc\n");
10641
10642 WARN(encoder->connectors_active != active,
10643 "encoder's computed active state doesn't match tracked active state "
10644 "(expected %i, found %i)\n", active, encoder->connectors_active);
10645
10646 active = encoder->get_hw_state(encoder, &pipe);
10647 WARN(active != encoder->connectors_active,
10648 "encoder's hw state doesn't match sw tracking "
10649 "(expected %i, found %i)\n",
10650 encoder->connectors_active, active);
10651
10652 if (!encoder->base.crtc)
10653 continue;
10654
10655 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10656 WARN(active && pipe != tracked_pipe,
10657 "active encoder's pipe doesn't match"
10658 "(expected %i, found %i)\n",
10659 tracked_pipe, pipe);
10660
10661 }
10662 }
10663
10664 static void
10665 check_crtc_state(struct drm_device *dev)
10666 {
10667 struct drm_i915_private *dev_priv = dev->dev_private;
10668 struct intel_crtc *crtc;
10669 struct intel_encoder *encoder;
10670 struct intel_crtc_config pipe_config;
10671
10672 for_each_intel_crtc(dev, crtc) {
10673 bool enabled = false;
10674 bool active = false;
10675
10676 memset(&pipe_config, 0, sizeof(pipe_config));
10677
10678 DRM_DEBUG_KMS("[CRTC:%d]\n",
10679 crtc->base.base.id);
10680
10681 WARN(crtc->active && !crtc->base.enabled,
10682 "active crtc, but not enabled in sw tracking\n");
10683
10684 for_each_intel_encoder(dev, encoder) {
10685 if (encoder->base.crtc != &crtc->base)
10686 continue;
10687 enabled = true;
10688 if (encoder->connectors_active)
10689 active = true;
10690 }
10691
10692 WARN(active != crtc->active,
10693 "crtc's computed active state doesn't match tracked active state "
10694 "(expected %i, found %i)\n", active, crtc->active);
10695 WARN(enabled != crtc->base.enabled,
10696 "crtc's computed enabled state doesn't match tracked enabled state "
10697 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10698
10699 active = dev_priv->display.get_pipe_config(crtc,
10700 &pipe_config);
10701
10702 /* hw state is inconsistent with the pipe A quirk */
10703 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10704 active = crtc->active;
10705
10706 for_each_intel_encoder(dev, encoder) {
10707 enum pipe pipe;
10708 if (encoder->base.crtc != &crtc->base)
10709 continue;
10710 if (encoder->get_hw_state(encoder, &pipe))
10711 encoder->get_config(encoder, &pipe_config);
10712 }
10713
10714 WARN(crtc->active != active,
10715 "crtc active state doesn't match with hw state "
10716 "(expected %i, found %i)\n", crtc->active, active);
10717
10718 if (active &&
10719 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10720 WARN(1, "pipe state doesn't match!\n");
10721 intel_dump_pipe_config(crtc, &pipe_config,
10722 "[hw state]");
10723 intel_dump_pipe_config(crtc, &crtc->config,
10724 "[sw state]");
10725 }
10726 }
10727 }
10728
10729 static void
10730 check_shared_dpll_state(struct drm_device *dev)
10731 {
10732 struct drm_i915_private *dev_priv = dev->dev_private;
10733 struct intel_crtc *crtc;
10734 struct intel_dpll_hw_state dpll_hw_state;
10735 int i;
10736
10737 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10738 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10739 int enabled_crtcs = 0, active_crtcs = 0;
10740 bool active;
10741
10742 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10743
10744 DRM_DEBUG_KMS("%s\n", pll->name);
10745
10746 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10747
10748 WARN(pll->active > pll->refcount,
10749 "more active pll users than references: %i vs %i\n",
10750 pll->active, pll->refcount);
10751 WARN(pll->active && !pll->on,
10752 "pll in active use but not on in sw tracking\n");
10753 WARN(pll->on && !pll->active,
10754 "pll in on but not on in use in sw tracking\n");
10755 WARN(pll->on != active,
10756 "pll on state mismatch (expected %i, found %i)\n",
10757 pll->on, active);
10758
10759 for_each_intel_crtc(dev, crtc) {
10760 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10761 enabled_crtcs++;
10762 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10763 active_crtcs++;
10764 }
10765 WARN(pll->active != active_crtcs,
10766 "pll active crtcs mismatch (expected %i, found %i)\n",
10767 pll->active, active_crtcs);
10768 WARN(pll->refcount != enabled_crtcs,
10769 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10770 pll->refcount, enabled_crtcs);
10771
10772 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10773 sizeof(dpll_hw_state)),
10774 "pll hw state mismatch\n");
10775 }
10776 }
10777
10778 void
10779 intel_modeset_check_state(struct drm_device *dev)
10780 {
10781 check_connector_state(dev);
10782 check_encoder_state(dev);
10783 check_crtc_state(dev);
10784 check_shared_dpll_state(dev);
10785 }
10786
10787 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10788 int dotclock)
10789 {
10790 /*
10791 * FDI already provided one idea for the dotclock.
10792 * Yell if the encoder disagrees.
10793 */
10794 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10795 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10796 pipe_config->adjusted_mode.crtc_clock, dotclock);
10797 }
10798
10799 static void update_scanline_offset(struct intel_crtc *crtc)
10800 {
10801 struct drm_device *dev = crtc->base.dev;
10802
10803 /*
10804 * The scanline counter increments at the leading edge of hsync.
10805 *
10806 * On most platforms it starts counting from vtotal-1 on the
10807 * first active line. That means the scanline counter value is
10808 * always one less than what we would expect. Ie. just after
10809 * start of vblank, which also occurs at start of hsync (on the
10810 * last active line), the scanline counter will read vblank_start-1.
10811 *
10812 * On gen2 the scanline counter starts counting from 1 instead
10813 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10814 * to keep the value positive), instead of adding one.
10815 *
10816 * On HSW+ the behaviour of the scanline counter depends on the output
10817 * type. For DP ports it behaves like most other platforms, but on HDMI
10818 * there's an extra 1 line difference. So we need to add two instead of
10819 * one to the value.
10820 */
10821 if (IS_GEN2(dev)) {
10822 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10823 int vtotal;
10824
10825 vtotal = mode->crtc_vtotal;
10826 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10827 vtotal /= 2;
10828
10829 crtc->scanline_offset = vtotal - 1;
10830 } else if (HAS_DDI(dev) &&
10831 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10832 crtc->scanline_offset = 2;
10833 } else
10834 crtc->scanline_offset = 1;
10835 }
10836
10837 static int __intel_set_mode(struct drm_crtc *crtc,
10838 struct drm_display_mode *mode,
10839 int x, int y, struct drm_framebuffer *fb)
10840 {
10841 struct drm_device *dev = crtc->dev;
10842 struct drm_i915_private *dev_priv = dev->dev_private;
10843 struct drm_display_mode *saved_mode;
10844 struct intel_crtc_config *pipe_config = NULL;
10845 struct intel_crtc *intel_crtc;
10846 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10847 int ret = 0;
10848
10849 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10850 if (!saved_mode)
10851 return -ENOMEM;
10852
10853 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10854 &prepare_pipes, &disable_pipes);
10855
10856 *saved_mode = crtc->mode;
10857
10858 /* Hack: Because we don't (yet) support global modeset on multiple
10859 * crtcs, we don't keep track of the new mode for more than one crtc.
10860 * Hence simply check whether any bit is set in modeset_pipes in all the
10861 * pieces of code that are not yet converted to deal with mutliple crtcs
10862 * changing their mode at the same time. */
10863 if (modeset_pipes) {
10864 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10865 if (IS_ERR(pipe_config)) {
10866 ret = PTR_ERR(pipe_config);
10867 pipe_config = NULL;
10868
10869 goto out;
10870 }
10871 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10872 "[modeset]");
10873 to_intel_crtc(crtc)->new_config = pipe_config;
10874 }
10875
10876 /*
10877 * See if the config requires any additional preparation, e.g.
10878 * to adjust global state with pipes off. We need to do this
10879 * here so we can get the modeset_pipe updated config for the new
10880 * mode set on this crtc. For other crtcs we need to use the
10881 * adjusted_mode bits in the crtc directly.
10882 */
10883 if (IS_VALLEYVIEW(dev)) {
10884 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10885
10886 /* may have added more to prepare_pipes than we should */
10887 prepare_pipes &= ~disable_pipes;
10888 }
10889
10890 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10891 intel_crtc_disable(&intel_crtc->base);
10892
10893 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10894 if (intel_crtc->base.enabled)
10895 dev_priv->display.crtc_disable(&intel_crtc->base);
10896 }
10897
10898 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10899 * to set it here already despite that we pass it down the callchain.
10900 */
10901 if (modeset_pipes) {
10902 crtc->mode = *mode;
10903 /* mode_set/enable/disable functions rely on a correct pipe
10904 * config. */
10905 to_intel_crtc(crtc)->config = *pipe_config;
10906 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10907
10908 /*
10909 * Calculate and store various constants which
10910 * are later needed by vblank and swap-completion
10911 * timestamping. They are derived from true hwmode.
10912 */
10913 drm_calc_timestamping_constants(crtc,
10914 &pipe_config->adjusted_mode);
10915 }
10916
10917 /* Only after disabling all output pipelines that will be changed can we
10918 * update the the output configuration. */
10919 intel_modeset_update_state(dev, prepare_pipes);
10920
10921 if (dev_priv->display.modeset_global_resources)
10922 dev_priv->display.modeset_global_resources(dev);
10923
10924 /* Set up the DPLL and any encoders state that needs to adjust or depend
10925 * on the DPLL.
10926 */
10927 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10928 struct drm_framebuffer *old_fb = crtc->primary->fb;
10929 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10930 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10931
10932 mutex_lock(&dev->struct_mutex);
10933 ret = intel_pin_and_fence_fb_obj(dev,
10934 obj,
10935 NULL);
10936 if (ret != 0) {
10937 DRM_ERROR("pin & fence failed\n");
10938 mutex_unlock(&dev->struct_mutex);
10939 goto done;
10940 }
10941 if (old_fb)
10942 intel_unpin_fb_obj(old_obj);
10943 i915_gem_track_fb(old_obj, obj,
10944 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10945 mutex_unlock(&dev->struct_mutex);
10946
10947 crtc->primary->fb = fb;
10948 crtc->x = x;
10949 crtc->y = y;
10950
10951 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10952 x, y, fb);
10953 if (ret)
10954 goto done;
10955 }
10956
10957 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10958 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10959 update_scanline_offset(intel_crtc);
10960
10961 dev_priv->display.crtc_enable(&intel_crtc->base);
10962 }
10963
10964 /* FIXME: add subpixel order */
10965 done:
10966 if (ret && crtc->enabled)
10967 crtc->mode = *saved_mode;
10968
10969 out:
10970 kfree(pipe_config);
10971 kfree(saved_mode);
10972 return ret;
10973 }
10974
10975 static int intel_set_mode(struct drm_crtc *crtc,
10976 struct drm_display_mode *mode,
10977 int x, int y, struct drm_framebuffer *fb)
10978 {
10979 int ret;
10980
10981 ret = __intel_set_mode(crtc, mode, x, y, fb);
10982
10983 if (ret == 0)
10984 intel_modeset_check_state(crtc->dev);
10985
10986 return ret;
10987 }
10988
10989 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10990 {
10991 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10992 }
10993
10994 #undef for_each_intel_crtc_masked
10995
10996 static void intel_set_config_free(struct intel_set_config *config)
10997 {
10998 if (!config)
10999 return;
11000
11001 kfree(config->save_connector_encoders);
11002 kfree(config->save_encoder_crtcs);
11003 kfree(config->save_crtc_enabled);
11004 kfree(config);
11005 }
11006
11007 static int intel_set_config_save_state(struct drm_device *dev,
11008 struct intel_set_config *config)
11009 {
11010 struct drm_crtc *crtc;
11011 struct drm_encoder *encoder;
11012 struct drm_connector *connector;
11013 int count;
11014
11015 config->save_crtc_enabled =
11016 kcalloc(dev->mode_config.num_crtc,
11017 sizeof(bool), GFP_KERNEL);
11018 if (!config->save_crtc_enabled)
11019 return -ENOMEM;
11020
11021 config->save_encoder_crtcs =
11022 kcalloc(dev->mode_config.num_encoder,
11023 sizeof(struct drm_crtc *), GFP_KERNEL);
11024 if (!config->save_encoder_crtcs)
11025 return -ENOMEM;
11026
11027 config->save_connector_encoders =
11028 kcalloc(dev->mode_config.num_connector,
11029 sizeof(struct drm_encoder *), GFP_KERNEL);
11030 if (!config->save_connector_encoders)
11031 return -ENOMEM;
11032
11033 /* Copy data. Note that driver private data is not affected.
11034 * Should anything bad happen only the expected state is
11035 * restored, not the drivers personal bookkeeping.
11036 */
11037 count = 0;
11038 for_each_crtc(dev, crtc) {
11039 config->save_crtc_enabled[count++] = crtc->enabled;
11040 }
11041
11042 count = 0;
11043 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11044 config->save_encoder_crtcs[count++] = encoder->crtc;
11045 }
11046
11047 count = 0;
11048 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11049 config->save_connector_encoders[count++] = connector->encoder;
11050 }
11051
11052 return 0;
11053 }
11054
11055 static void intel_set_config_restore_state(struct drm_device *dev,
11056 struct intel_set_config *config)
11057 {
11058 struct intel_crtc *crtc;
11059 struct intel_encoder *encoder;
11060 struct intel_connector *connector;
11061 int count;
11062
11063 count = 0;
11064 for_each_intel_crtc(dev, crtc) {
11065 crtc->new_enabled = config->save_crtc_enabled[count++];
11066
11067 if (crtc->new_enabled)
11068 crtc->new_config = &crtc->config;
11069 else
11070 crtc->new_config = NULL;
11071 }
11072
11073 count = 0;
11074 for_each_intel_encoder(dev, encoder) {
11075 encoder->new_crtc =
11076 to_intel_crtc(config->save_encoder_crtcs[count++]);
11077 }
11078
11079 count = 0;
11080 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11081 connector->new_encoder =
11082 to_intel_encoder(config->save_connector_encoders[count++]);
11083 }
11084 }
11085
11086 static bool
11087 is_crtc_connector_off(struct drm_mode_set *set)
11088 {
11089 int i;
11090
11091 if (set->num_connectors == 0)
11092 return false;
11093
11094 if (WARN_ON(set->connectors == NULL))
11095 return false;
11096
11097 for (i = 0; i < set->num_connectors; i++)
11098 if (set->connectors[i]->encoder &&
11099 set->connectors[i]->encoder->crtc == set->crtc &&
11100 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11101 return true;
11102
11103 return false;
11104 }
11105
11106 static void
11107 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11108 struct intel_set_config *config)
11109 {
11110
11111 /* We should be able to check here if the fb has the same properties
11112 * and then just flip_or_move it */
11113 if (is_crtc_connector_off(set)) {
11114 config->mode_changed = true;
11115 } else if (set->crtc->primary->fb != set->fb) {
11116 /*
11117 * If we have no fb, we can only flip as long as the crtc is
11118 * active, otherwise we need a full mode set. The crtc may
11119 * be active if we've only disabled the primary plane, or
11120 * in fastboot situations.
11121 */
11122 if (set->crtc->primary->fb == NULL) {
11123 struct intel_crtc *intel_crtc =
11124 to_intel_crtc(set->crtc);
11125
11126 if (intel_crtc->active) {
11127 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11128 config->fb_changed = true;
11129 } else {
11130 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11131 config->mode_changed = true;
11132 }
11133 } else if (set->fb == NULL) {
11134 config->mode_changed = true;
11135 } else if (set->fb->pixel_format !=
11136 set->crtc->primary->fb->pixel_format) {
11137 config->mode_changed = true;
11138 } else {
11139 config->fb_changed = true;
11140 }
11141 }
11142
11143 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11144 config->fb_changed = true;
11145
11146 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11147 DRM_DEBUG_KMS("modes are different, full mode set\n");
11148 drm_mode_debug_printmodeline(&set->crtc->mode);
11149 drm_mode_debug_printmodeline(set->mode);
11150 config->mode_changed = true;
11151 }
11152
11153 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11154 set->crtc->base.id, config->mode_changed, config->fb_changed);
11155 }
11156
11157 static int
11158 intel_modeset_stage_output_state(struct drm_device *dev,
11159 struct drm_mode_set *set,
11160 struct intel_set_config *config)
11161 {
11162 struct intel_connector *connector;
11163 struct intel_encoder *encoder;
11164 struct intel_crtc *crtc;
11165 int ro;
11166
11167 /* The upper layers ensure that we either disable a crtc or have a list
11168 * of connectors. For paranoia, double-check this. */
11169 WARN_ON(!set->fb && (set->num_connectors != 0));
11170 WARN_ON(set->fb && (set->num_connectors == 0));
11171
11172 list_for_each_entry(connector, &dev->mode_config.connector_list,
11173 base.head) {
11174 /* Otherwise traverse passed in connector list and get encoders
11175 * for them. */
11176 for (ro = 0; ro < set->num_connectors; ro++) {
11177 if (set->connectors[ro] == &connector->base) {
11178 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11179 break;
11180 }
11181 }
11182
11183 /* If we disable the crtc, disable all its connectors. Also, if
11184 * the connector is on the changing crtc but not on the new
11185 * connector list, disable it. */
11186 if ((!set->fb || ro == set->num_connectors) &&
11187 connector->base.encoder &&
11188 connector->base.encoder->crtc == set->crtc) {
11189 connector->new_encoder = NULL;
11190
11191 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11192 connector->base.base.id,
11193 connector->base.name);
11194 }
11195
11196
11197 if (&connector->new_encoder->base != connector->base.encoder) {
11198 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11199 config->mode_changed = true;
11200 }
11201 }
11202 /* connector->new_encoder is now updated for all connectors. */
11203
11204 /* Update crtc of enabled connectors. */
11205 list_for_each_entry(connector, &dev->mode_config.connector_list,
11206 base.head) {
11207 struct drm_crtc *new_crtc;
11208
11209 if (!connector->new_encoder)
11210 continue;
11211
11212 new_crtc = connector->new_encoder->base.crtc;
11213
11214 for (ro = 0; ro < set->num_connectors; ro++) {
11215 if (set->connectors[ro] == &connector->base)
11216 new_crtc = set->crtc;
11217 }
11218
11219 /* Make sure the new CRTC will work with the encoder */
11220 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11221 new_crtc)) {
11222 return -EINVAL;
11223 }
11224 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11225
11226 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11227 connector->base.base.id,
11228 connector->base.name,
11229 new_crtc->base.id);
11230 }
11231
11232 /* Check for any encoders that needs to be disabled. */
11233 for_each_intel_encoder(dev, encoder) {
11234 int num_connectors = 0;
11235 list_for_each_entry(connector,
11236 &dev->mode_config.connector_list,
11237 base.head) {
11238 if (connector->new_encoder == encoder) {
11239 WARN_ON(!connector->new_encoder->new_crtc);
11240 num_connectors++;
11241 }
11242 }
11243
11244 if (num_connectors == 0)
11245 encoder->new_crtc = NULL;
11246 else if (num_connectors > 1)
11247 return -EINVAL;
11248
11249 /* Only now check for crtc changes so we don't miss encoders
11250 * that will be disabled. */
11251 if (&encoder->new_crtc->base != encoder->base.crtc) {
11252 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11253 config->mode_changed = true;
11254 }
11255 }
11256 /* Now we've also updated encoder->new_crtc for all encoders. */
11257 list_for_each_entry(connector, &dev->mode_config.connector_list,
11258 base.head) {
11259 if (connector->new_encoder)
11260 if (connector->new_encoder != connector->encoder)
11261 connector->encoder = connector->new_encoder;
11262 }
11263 for_each_intel_crtc(dev, crtc) {
11264 crtc->new_enabled = false;
11265
11266 for_each_intel_encoder(dev, encoder) {
11267 if (encoder->new_crtc == crtc) {
11268 crtc->new_enabled = true;
11269 break;
11270 }
11271 }
11272
11273 if (crtc->new_enabled != crtc->base.enabled) {
11274 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11275 crtc->new_enabled ? "en" : "dis");
11276 config->mode_changed = true;
11277 }
11278
11279 if (crtc->new_enabled)
11280 crtc->new_config = &crtc->config;
11281 else
11282 crtc->new_config = NULL;
11283 }
11284
11285 return 0;
11286 }
11287
11288 static void disable_crtc_nofb(struct intel_crtc *crtc)
11289 {
11290 struct drm_device *dev = crtc->base.dev;
11291 struct intel_encoder *encoder;
11292 struct intel_connector *connector;
11293
11294 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11295 pipe_name(crtc->pipe));
11296
11297 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11298 if (connector->new_encoder &&
11299 connector->new_encoder->new_crtc == crtc)
11300 connector->new_encoder = NULL;
11301 }
11302
11303 for_each_intel_encoder(dev, encoder) {
11304 if (encoder->new_crtc == crtc)
11305 encoder->new_crtc = NULL;
11306 }
11307
11308 crtc->new_enabled = false;
11309 crtc->new_config = NULL;
11310 }
11311
11312 static int intel_crtc_set_config(struct drm_mode_set *set)
11313 {
11314 struct drm_device *dev;
11315 struct drm_mode_set save_set;
11316 struct intel_set_config *config;
11317 int ret;
11318
11319 BUG_ON(!set);
11320 BUG_ON(!set->crtc);
11321 BUG_ON(!set->crtc->helper_private);
11322
11323 /* Enforce sane interface api - has been abused by the fb helper. */
11324 BUG_ON(!set->mode && set->fb);
11325 BUG_ON(set->fb && set->num_connectors == 0);
11326
11327 if (set->fb) {
11328 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11329 set->crtc->base.id, set->fb->base.id,
11330 (int)set->num_connectors, set->x, set->y);
11331 } else {
11332 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11333 }
11334
11335 dev = set->crtc->dev;
11336
11337 ret = -ENOMEM;
11338 config = kzalloc(sizeof(*config), GFP_KERNEL);
11339 if (!config)
11340 goto out_config;
11341
11342 ret = intel_set_config_save_state(dev, config);
11343 if (ret)
11344 goto out_config;
11345
11346 save_set.crtc = set->crtc;
11347 save_set.mode = &set->crtc->mode;
11348 save_set.x = set->crtc->x;
11349 save_set.y = set->crtc->y;
11350 save_set.fb = set->crtc->primary->fb;
11351
11352 /* Compute whether we need a full modeset, only an fb base update or no
11353 * change at all. In the future we might also check whether only the
11354 * mode changed, e.g. for LVDS where we only change the panel fitter in
11355 * such cases. */
11356 intel_set_config_compute_mode_changes(set, config);
11357
11358 ret = intel_modeset_stage_output_state(dev, set, config);
11359 if (ret)
11360 goto fail;
11361
11362 if (config->mode_changed) {
11363 ret = intel_set_mode(set->crtc, set->mode,
11364 set->x, set->y, set->fb);
11365 } else if (config->fb_changed) {
11366 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11367
11368 intel_crtc_wait_for_pending_flips(set->crtc);
11369
11370 ret = intel_pipe_set_base(set->crtc,
11371 set->x, set->y, set->fb);
11372
11373 /*
11374 * We need to make sure the primary plane is re-enabled if it
11375 * has previously been turned off.
11376 */
11377 if (!intel_crtc->primary_enabled && ret == 0) {
11378 WARN_ON(!intel_crtc->active);
11379 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11380 }
11381
11382 /*
11383 * In the fastboot case this may be our only check of the
11384 * state after boot. It would be better to only do it on
11385 * the first update, but we don't have a nice way of doing that
11386 * (and really, set_config isn't used much for high freq page
11387 * flipping, so increasing its cost here shouldn't be a big
11388 * deal).
11389 */
11390 if (i915.fastboot && ret == 0)
11391 intel_modeset_check_state(set->crtc->dev);
11392 }
11393
11394 if (ret) {
11395 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11396 set->crtc->base.id, ret);
11397 fail:
11398 intel_set_config_restore_state(dev, config);
11399
11400 /*
11401 * HACK: if the pipe was on, but we didn't have a framebuffer,
11402 * force the pipe off to avoid oopsing in the modeset code
11403 * due to fb==NULL. This should only happen during boot since
11404 * we don't yet reconstruct the FB from the hardware state.
11405 */
11406 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11407 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11408
11409 /* Try to restore the config */
11410 if (config->mode_changed &&
11411 intel_set_mode(save_set.crtc, save_set.mode,
11412 save_set.x, save_set.y, save_set.fb))
11413 DRM_ERROR("failed to restore config after modeset failure\n");
11414 }
11415
11416 out_config:
11417 intel_set_config_free(config);
11418 return ret;
11419 }
11420
11421 static const struct drm_crtc_funcs intel_crtc_funcs = {
11422 .gamma_set = intel_crtc_gamma_set,
11423 .set_config = intel_crtc_set_config,
11424 .destroy = intel_crtc_destroy,
11425 .page_flip = intel_crtc_page_flip,
11426 };
11427
11428 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11429 struct intel_shared_dpll *pll,
11430 struct intel_dpll_hw_state *hw_state)
11431 {
11432 uint32_t val;
11433
11434 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11435 return false;
11436
11437 val = I915_READ(PCH_DPLL(pll->id));
11438 hw_state->dpll = val;
11439 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11440 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11441
11442 return val & DPLL_VCO_ENABLE;
11443 }
11444
11445 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11446 struct intel_shared_dpll *pll)
11447 {
11448 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11449 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11450 }
11451
11452 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11453 struct intel_shared_dpll *pll)
11454 {
11455 /* PCH refclock must be enabled first */
11456 ibx_assert_pch_refclk_enabled(dev_priv);
11457
11458 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11459
11460 /* Wait for the clocks to stabilize. */
11461 POSTING_READ(PCH_DPLL(pll->id));
11462 udelay(150);
11463
11464 /* The pixel multiplier can only be updated once the
11465 * DPLL is enabled and the clocks are stable.
11466 *
11467 * So write it again.
11468 */
11469 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11470 POSTING_READ(PCH_DPLL(pll->id));
11471 udelay(200);
11472 }
11473
11474 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11475 struct intel_shared_dpll *pll)
11476 {
11477 struct drm_device *dev = dev_priv->dev;
11478 struct intel_crtc *crtc;
11479
11480 /* Make sure no transcoder isn't still depending on us. */
11481 for_each_intel_crtc(dev, crtc) {
11482 if (intel_crtc_to_shared_dpll(crtc) == pll)
11483 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11484 }
11485
11486 I915_WRITE(PCH_DPLL(pll->id), 0);
11487 POSTING_READ(PCH_DPLL(pll->id));
11488 udelay(200);
11489 }
11490
11491 static char *ibx_pch_dpll_names[] = {
11492 "PCH DPLL A",
11493 "PCH DPLL B",
11494 };
11495
11496 static void ibx_pch_dpll_init(struct drm_device *dev)
11497 {
11498 struct drm_i915_private *dev_priv = dev->dev_private;
11499 int i;
11500
11501 dev_priv->num_shared_dpll = 2;
11502
11503 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11504 dev_priv->shared_dplls[i].id = i;
11505 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11506 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11507 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11508 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11509 dev_priv->shared_dplls[i].get_hw_state =
11510 ibx_pch_dpll_get_hw_state;
11511 }
11512 }
11513
11514 static void intel_shared_dpll_init(struct drm_device *dev)
11515 {
11516 struct drm_i915_private *dev_priv = dev->dev_private;
11517
11518 if (HAS_DDI(dev))
11519 intel_ddi_pll_init(dev);
11520 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11521 ibx_pch_dpll_init(dev);
11522 else
11523 dev_priv->num_shared_dpll = 0;
11524
11525 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11526 }
11527
11528 static int
11529 intel_primary_plane_disable(struct drm_plane *plane)
11530 {
11531 struct drm_device *dev = plane->dev;
11532 struct intel_crtc *intel_crtc;
11533
11534 if (!plane->fb)
11535 return 0;
11536
11537 BUG_ON(!plane->crtc);
11538
11539 intel_crtc = to_intel_crtc(plane->crtc);
11540
11541 /*
11542 * Even though we checked plane->fb above, it's still possible that
11543 * the primary plane has been implicitly disabled because the crtc
11544 * coordinates given weren't visible, or because we detected
11545 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11546 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11547 * In either case, we need to unpin the FB and let the fb pointer get
11548 * updated, but otherwise we don't need to touch the hardware.
11549 */
11550 if (!intel_crtc->primary_enabled)
11551 goto disable_unpin;
11552
11553 intel_crtc_wait_for_pending_flips(plane->crtc);
11554 intel_disable_primary_hw_plane(plane, plane->crtc);
11555
11556 disable_unpin:
11557 mutex_lock(&dev->struct_mutex);
11558 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11559 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11560 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11561 mutex_unlock(&dev->struct_mutex);
11562 plane->fb = NULL;
11563
11564 return 0;
11565 }
11566
11567 static int
11568 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11569 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11570 unsigned int crtc_w, unsigned int crtc_h,
11571 uint32_t src_x, uint32_t src_y,
11572 uint32_t src_w, uint32_t src_h)
11573 {
11574 struct drm_device *dev = crtc->dev;
11575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11576 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11577 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11578 struct drm_rect dest = {
11579 /* integer pixels */
11580 .x1 = crtc_x,
11581 .y1 = crtc_y,
11582 .x2 = crtc_x + crtc_w,
11583 .y2 = crtc_y + crtc_h,
11584 };
11585 struct drm_rect src = {
11586 /* 16.16 fixed point */
11587 .x1 = src_x,
11588 .y1 = src_y,
11589 .x2 = src_x + src_w,
11590 .y2 = src_y + src_h,
11591 };
11592 const struct drm_rect clip = {
11593 /* integer pixels */
11594 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11595 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11596 };
11597 bool visible;
11598 int ret;
11599
11600 ret = drm_plane_helper_check_update(plane, crtc, fb,
11601 &src, &dest, &clip,
11602 DRM_PLANE_HELPER_NO_SCALING,
11603 DRM_PLANE_HELPER_NO_SCALING,
11604 false, true, &visible);
11605
11606 if (ret)
11607 return ret;
11608
11609 /*
11610 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11611 * updating the fb pointer, and returning without touching the
11612 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11613 * turn on the display with all planes setup as desired.
11614 */
11615 if (!crtc->enabled) {
11616 mutex_lock(&dev->struct_mutex);
11617
11618 /*
11619 * If we already called setplane while the crtc was disabled,
11620 * we may have an fb pinned; unpin it.
11621 */
11622 if (plane->fb)
11623 intel_unpin_fb_obj(old_obj);
11624
11625 i915_gem_track_fb(old_obj, obj,
11626 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11627
11628 /* Pin and return without programming hardware */
11629 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11630 mutex_unlock(&dev->struct_mutex);
11631
11632 return ret;
11633 }
11634
11635 intel_crtc_wait_for_pending_flips(crtc);
11636
11637 /*
11638 * If clipping results in a non-visible primary plane, we'll disable
11639 * the primary plane. Note that this is a bit different than what
11640 * happens if userspace explicitly disables the plane by passing fb=0
11641 * because plane->fb still gets set and pinned.
11642 */
11643 if (!visible) {
11644 mutex_lock(&dev->struct_mutex);
11645
11646 /*
11647 * Try to pin the new fb first so that we can bail out if we
11648 * fail.
11649 */
11650 if (plane->fb != fb) {
11651 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11652 if (ret) {
11653 mutex_unlock(&dev->struct_mutex);
11654 return ret;
11655 }
11656 }
11657
11658 i915_gem_track_fb(old_obj, obj,
11659 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11660
11661 if (intel_crtc->primary_enabled)
11662 intel_disable_primary_hw_plane(plane, crtc);
11663
11664
11665 if (plane->fb != fb)
11666 if (plane->fb)
11667 intel_unpin_fb_obj(old_obj);
11668
11669 mutex_unlock(&dev->struct_mutex);
11670
11671 return 0;
11672 }
11673
11674 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11675 if (ret)
11676 return ret;
11677
11678 if (!intel_crtc->primary_enabled)
11679 intel_enable_primary_hw_plane(plane, crtc);
11680
11681 return 0;
11682 }
11683
11684 /* Common destruction function for both primary and cursor planes */
11685 static void intel_plane_destroy(struct drm_plane *plane)
11686 {
11687 struct intel_plane *intel_plane = to_intel_plane(plane);
11688 drm_plane_cleanup(plane);
11689 kfree(intel_plane);
11690 }
11691
11692 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11693 .update_plane = intel_primary_plane_setplane,
11694 .disable_plane = intel_primary_plane_disable,
11695 .destroy = intel_plane_destroy,
11696 };
11697
11698 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11699 int pipe)
11700 {
11701 struct intel_plane *primary;
11702 const uint32_t *intel_primary_formats;
11703 int num_formats;
11704
11705 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11706 if (primary == NULL)
11707 return NULL;
11708
11709 primary->can_scale = false;
11710 primary->max_downscale = 1;
11711 primary->pipe = pipe;
11712 primary->plane = pipe;
11713 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11714 primary->plane = !pipe;
11715
11716 if (INTEL_INFO(dev)->gen <= 3) {
11717 intel_primary_formats = intel_primary_formats_gen2;
11718 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11719 } else {
11720 intel_primary_formats = intel_primary_formats_gen4;
11721 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11722 }
11723
11724 drm_universal_plane_init(dev, &primary->base, 0,
11725 &intel_primary_plane_funcs,
11726 intel_primary_formats, num_formats,
11727 DRM_PLANE_TYPE_PRIMARY);
11728 return &primary->base;
11729 }
11730
11731 static int
11732 intel_cursor_plane_disable(struct drm_plane *plane)
11733 {
11734 if (!plane->fb)
11735 return 0;
11736
11737 BUG_ON(!plane->crtc);
11738
11739 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11740 }
11741
11742 static int
11743 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11744 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11745 unsigned int crtc_w, unsigned int crtc_h,
11746 uint32_t src_x, uint32_t src_y,
11747 uint32_t src_w, uint32_t src_h)
11748 {
11749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11750 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11751 struct drm_i915_gem_object *obj = intel_fb->obj;
11752 struct drm_rect dest = {
11753 /* integer pixels */
11754 .x1 = crtc_x,
11755 .y1 = crtc_y,
11756 .x2 = crtc_x + crtc_w,
11757 .y2 = crtc_y + crtc_h,
11758 };
11759 struct drm_rect src = {
11760 /* 16.16 fixed point */
11761 .x1 = src_x,
11762 .y1 = src_y,
11763 .x2 = src_x + src_w,
11764 .y2 = src_y + src_h,
11765 };
11766 const struct drm_rect clip = {
11767 /* integer pixels */
11768 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11769 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11770 };
11771 bool visible;
11772 int ret;
11773
11774 ret = drm_plane_helper_check_update(plane, crtc, fb,
11775 &src, &dest, &clip,
11776 DRM_PLANE_HELPER_NO_SCALING,
11777 DRM_PLANE_HELPER_NO_SCALING,
11778 true, true, &visible);
11779 if (ret)
11780 return ret;
11781
11782 crtc->cursor_x = crtc_x;
11783 crtc->cursor_y = crtc_y;
11784 if (fb != crtc->cursor->fb) {
11785 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11786 } else {
11787 intel_crtc_update_cursor(crtc, visible);
11788
11789 intel_frontbuffer_flip(crtc->dev,
11790 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11791
11792 return 0;
11793 }
11794 }
11795 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11796 .update_plane = intel_cursor_plane_update,
11797 .disable_plane = intel_cursor_plane_disable,
11798 .destroy = intel_plane_destroy,
11799 };
11800
11801 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11802 int pipe)
11803 {
11804 struct intel_plane *cursor;
11805
11806 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11807 if (cursor == NULL)
11808 return NULL;
11809
11810 cursor->can_scale = false;
11811 cursor->max_downscale = 1;
11812 cursor->pipe = pipe;
11813 cursor->plane = pipe;
11814
11815 drm_universal_plane_init(dev, &cursor->base, 0,
11816 &intel_cursor_plane_funcs,
11817 intel_cursor_formats,
11818 ARRAY_SIZE(intel_cursor_formats),
11819 DRM_PLANE_TYPE_CURSOR);
11820 return &cursor->base;
11821 }
11822
11823 static void intel_crtc_init(struct drm_device *dev, int pipe)
11824 {
11825 struct drm_i915_private *dev_priv = dev->dev_private;
11826 struct intel_crtc *intel_crtc;
11827 struct drm_plane *primary = NULL;
11828 struct drm_plane *cursor = NULL;
11829 int i, ret;
11830
11831 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11832 if (intel_crtc == NULL)
11833 return;
11834
11835 primary = intel_primary_plane_create(dev, pipe);
11836 if (!primary)
11837 goto fail;
11838
11839 cursor = intel_cursor_plane_create(dev, pipe);
11840 if (!cursor)
11841 goto fail;
11842
11843 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11844 cursor, &intel_crtc_funcs);
11845 if (ret)
11846 goto fail;
11847
11848 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11849 for (i = 0; i < 256; i++) {
11850 intel_crtc->lut_r[i] = i;
11851 intel_crtc->lut_g[i] = i;
11852 intel_crtc->lut_b[i] = i;
11853 }
11854
11855 /*
11856 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11857 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11858 */
11859 intel_crtc->pipe = pipe;
11860 intel_crtc->plane = pipe;
11861 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11862 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11863 intel_crtc->plane = !pipe;
11864 }
11865
11866 intel_crtc->cursor_base = ~0;
11867 intel_crtc->cursor_cntl = ~0;
11868 intel_crtc->cursor_size = ~0;
11869
11870 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11871 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11872 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11873 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11874
11875 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11876
11877 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11878 return;
11879
11880 fail:
11881 if (primary)
11882 drm_plane_cleanup(primary);
11883 if (cursor)
11884 drm_plane_cleanup(cursor);
11885 kfree(intel_crtc);
11886 }
11887
11888 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11889 {
11890 struct drm_encoder *encoder = connector->base.encoder;
11891 struct drm_device *dev = connector->base.dev;
11892
11893 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11894
11895 if (!encoder)
11896 return INVALID_PIPE;
11897
11898 return to_intel_crtc(encoder->crtc)->pipe;
11899 }
11900
11901 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11902 struct drm_file *file)
11903 {
11904 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11905 struct drm_crtc *drmmode_crtc;
11906 struct intel_crtc *crtc;
11907
11908 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11909 return -ENODEV;
11910
11911 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11912
11913 if (!drmmode_crtc) {
11914 DRM_ERROR("no such CRTC id\n");
11915 return -ENOENT;
11916 }
11917
11918 crtc = to_intel_crtc(drmmode_crtc);
11919 pipe_from_crtc_id->pipe = crtc->pipe;
11920
11921 return 0;
11922 }
11923
11924 static int intel_encoder_clones(struct intel_encoder *encoder)
11925 {
11926 struct drm_device *dev = encoder->base.dev;
11927 struct intel_encoder *source_encoder;
11928 int index_mask = 0;
11929 int entry = 0;
11930
11931 for_each_intel_encoder(dev, source_encoder) {
11932 if (encoders_cloneable(encoder, source_encoder))
11933 index_mask |= (1 << entry);
11934
11935 entry++;
11936 }
11937
11938 return index_mask;
11939 }
11940
11941 static bool has_edp_a(struct drm_device *dev)
11942 {
11943 struct drm_i915_private *dev_priv = dev->dev_private;
11944
11945 if (!IS_MOBILE(dev))
11946 return false;
11947
11948 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11949 return false;
11950
11951 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11952 return false;
11953
11954 return true;
11955 }
11956
11957 const char *intel_output_name(int output)
11958 {
11959 static const char *names[] = {
11960 [INTEL_OUTPUT_UNUSED] = "Unused",
11961 [INTEL_OUTPUT_ANALOG] = "Analog",
11962 [INTEL_OUTPUT_DVO] = "DVO",
11963 [INTEL_OUTPUT_SDVO] = "SDVO",
11964 [INTEL_OUTPUT_LVDS] = "LVDS",
11965 [INTEL_OUTPUT_TVOUT] = "TV",
11966 [INTEL_OUTPUT_HDMI] = "HDMI",
11967 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11968 [INTEL_OUTPUT_EDP] = "eDP",
11969 [INTEL_OUTPUT_DSI] = "DSI",
11970 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11971 };
11972
11973 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11974 return "Invalid";
11975
11976 return names[output];
11977 }
11978
11979 static bool intel_crt_present(struct drm_device *dev)
11980 {
11981 struct drm_i915_private *dev_priv = dev->dev_private;
11982
11983 if (IS_ULT(dev))
11984 return false;
11985
11986 if (IS_CHERRYVIEW(dev))
11987 return false;
11988
11989 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11990 return false;
11991
11992 return true;
11993 }
11994
11995 static void intel_setup_outputs(struct drm_device *dev)
11996 {
11997 struct drm_i915_private *dev_priv = dev->dev_private;
11998 struct intel_encoder *encoder;
11999 bool dpd_is_edp = false;
12000
12001 intel_lvds_init(dev);
12002
12003 if (intel_crt_present(dev))
12004 intel_crt_init(dev);
12005
12006 if (HAS_DDI(dev)) {
12007 int found;
12008
12009 /* Haswell uses DDI functions to detect digital outputs */
12010 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12011 /* DDI A only supports eDP */
12012 if (found)
12013 intel_ddi_init(dev, PORT_A);
12014
12015 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12016 * register */
12017 found = I915_READ(SFUSE_STRAP);
12018
12019 if (found & SFUSE_STRAP_DDIB_DETECTED)
12020 intel_ddi_init(dev, PORT_B);
12021 if (found & SFUSE_STRAP_DDIC_DETECTED)
12022 intel_ddi_init(dev, PORT_C);
12023 if (found & SFUSE_STRAP_DDID_DETECTED)
12024 intel_ddi_init(dev, PORT_D);
12025 } else if (HAS_PCH_SPLIT(dev)) {
12026 int found;
12027 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12028
12029 if (has_edp_a(dev))
12030 intel_dp_init(dev, DP_A, PORT_A);
12031
12032 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12033 /* PCH SDVOB multiplex with HDMIB */
12034 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12035 if (!found)
12036 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12037 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12038 intel_dp_init(dev, PCH_DP_B, PORT_B);
12039 }
12040
12041 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12042 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12043
12044 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12045 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12046
12047 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12048 intel_dp_init(dev, PCH_DP_C, PORT_C);
12049
12050 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12051 intel_dp_init(dev, PCH_DP_D, PORT_D);
12052 } else if (IS_VALLEYVIEW(dev)) {
12053 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12054 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12055 PORT_B);
12056 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12057 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12058 }
12059
12060 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12061 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12062 PORT_C);
12063 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12064 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12065 }
12066
12067 if (IS_CHERRYVIEW(dev)) {
12068 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12069 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12070 PORT_D);
12071 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12072 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12073 }
12074 }
12075
12076 intel_dsi_init(dev);
12077 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12078 bool found = false;
12079
12080 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12081 DRM_DEBUG_KMS("probing SDVOB\n");
12082 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12083 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12084 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12085 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12086 }
12087
12088 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12089 intel_dp_init(dev, DP_B, PORT_B);
12090 }
12091
12092 /* Before G4X SDVOC doesn't have its own detect register */
12093
12094 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12095 DRM_DEBUG_KMS("probing SDVOC\n");
12096 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12097 }
12098
12099 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12100
12101 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12102 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12103 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12104 }
12105 if (SUPPORTS_INTEGRATED_DP(dev))
12106 intel_dp_init(dev, DP_C, PORT_C);
12107 }
12108
12109 if (SUPPORTS_INTEGRATED_DP(dev) &&
12110 (I915_READ(DP_D) & DP_DETECTED))
12111 intel_dp_init(dev, DP_D, PORT_D);
12112 } else if (IS_GEN2(dev))
12113 intel_dvo_init(dev);
12114
12115 if (SUPPORTS_TV(dev))
12116 intel_tv_init(dev);
12117
12118 intel_edp_psr_init(dev);
12119
12120 for_each_intel_encoder(dev, encoder) {
12121 encoder->base.possible_crtcs = encoder->crtc_mask;
12122 encoder->base.possible_clones =
12123 intel_encoder_clones(encoder);
12124 }
12125
12126 intel_init_pch_refclk(dev);
12127
12128 drm_helper_move_panel_connectors_to_head(dev);
12129 }
12130
12131 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12132 {
12133 struct drm_device *dev = fb->dev;
12134 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12135
12136 drm_framebuffer_cleanup(fb);
12137 mutex_lock(&dev->struct_mutex);
12138 WARN_ON(!intel_fb->obj->framebuffer_references--);
12139 drm_gem_object_unreference(&intel_fb->obj->base);
12140 mutex_unlock(&dev->struct_mutex);
12141 kfree(intel_fb);
12142 }
12143
12144 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12145 struct drm_file *file,
12146 unsigned int *handle)
12147 {
12148 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12149 struct drm_i915_gem_object *obj = intel_fb->obj;
12150
12151 return drm_gem_handle_create(file, &obj->base, handle);
12152 }
12153
12154 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12155 .destroy = intel_user_framebuffer_destroy,
12156 .create_handle = intel_user_framebuffer_create_handle,
12157 };
12158
12159 static int intel_framebuffer_init(struct drm_device *dev,
12160 struct intel_framebuffer *intel_fb,
12161 struct drm_mode_fb_cmd2 *mode_cmd,
12162 struct drm_i915_gem_object *obj)
12163 {
12164 int aligned_height;
12165 int pitch_limit;
12166 int ret;
12167
12168 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12169
12170 if (obj->tiling_mode == I915_TILING_Y) {
12171 DRM_DEBUG("hardware does not support tiling Y\n");
12172 return -EINVAL;
12173 }
12174
12175 if (mode_cmd->pitches[0] & 63) {
12176 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12177 mode_cmd->pitches[0]);
12178 return -EINVAL;
12179 }
12180
12181 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12182 pitch_limit = 32*1024;
12183 } else if (INTEL_INFO(dev)->gen >= 4) {
12184 if (obj->tiling_mode)
12185 pitch_limit = 16*1024;
12186 else
12187 pitch_limit = 32*1024;
12188 } else if (INTEL_INFO(dev)->gen >= 3) {
12189 if (obj->tiling_mode)
12190 pitch_limit = 8*1024;
12191 else
12192 pitch_limit = 16*1024;
12193 } else
12194 /* XXX DSPC is limited to 4k tiled */
12195 pitch_limit = 8*1024;
12196
12197 if (mode_cmd->pitches[0] > pitch_limit) {
12198 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12199 obj->tiling_mode ? "tiled" : "linear",
12200 mode_cmd->pitches[0], pitch_limit);
12201 return -EINVAL;
12202 }
12203
12204 if (obj->tiling_mode != I915_TILING_NONE &&
12205 mode_cmd->pitches[0] != obj->stride) {
12206 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12207 mode_cmd->pitches[0], obj->stride);
12208 return -EINVAL;
12209 }
12210
12211 /* Reject formats not supported by any plane early. */
12212 switch (mode_cmd->pixel_format) {
12213 case DRM_FORMAT_C8:
12214 case DRM_FORMAT_RGB565:
12215 case DRM_FORMAT_XRGB8888:
12216 case DRM_FORMAT_ARGB8888:
12217 break;
12218 case DRM_FORMAT_XRGB1555:
12219 case DRM_FORMAT_ARGB1555:
12220 if (INTEL_INFO(dev)->gen > 3) {
12221 DRM_DEBUG("unsupported pixel format: %s\n",
12222 drm_get_format_name(mode_cmd->pixel_format));
12223 return -EINVAL;
12224 }
12225 break;
12226 case DRM_FORMAT_XBGR8888:
12227 case DRM_FORMAT_ABGR8888:
12228 case DRM_FORMAT_XRGB2101010:
12229 case DRM_FORMAT_ARGB2101010:
12230 case DRM_FORMAT_XBGR2101010:
12231 case DRM_FORMAT_ABGR2101010:
12232 if (INTEL_INFO(dev)->gen < 4) {
12233 DRM_DEBUG("unsupported pixel format: %s\n",
12234 drm_get_format_name(mode_cmd->pixel_format));
12235 return -EINVAL;
12236 }
12237 break;
12238 case DRM_FORMAT_YUYV:
12239 case DRM_FORMAT_UYVY:
12240 case DRM_FORMAT_YVYU:
12241 case DRM_FORMAT_VYUY:
12242 if (INTEL_INFO(dev)->gen < 5) {
12243 DRM_DEBUG("unsupported pixel format: %s\n",
12244 drm_get_format_name(mode_cmd->pixel_format));
12245 return -EINVAL;
12246 }
12247 break;
12248 default:
12249 DRM_DEBUG("unsupported pixel format: %s\n",
12250 drm_get_format_name(mode_cmd->pixel_format));
12251 return -EINVAL;
12252 }
12253
12254 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12255 if (mode_cmd->offsets[0] != 0)
12256 return -EINVAL;
12257
12258 aligned_height = intel_align_height(dev, mode_cmd->height,
12259 obj->tiling_mode);
12260 /* FIXME drm helper for size checks (especially planar formats)? */
12261 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12262 return -EINVAL;
12263
12264 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12265 intel_fb->obj = obj;
12266 intel_fb->obj->framebuffer_references++;
12267
12268 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12269 if (ret) {
12270 DRM_ERROR("framebuffer init failed %d\n", ret);
12271 return ret;
12272 }
12273
12274 return 0;
12275 }
12276
12277 static struct drm_framebuffer *
12278 intel_user_framebuffer_create(struct drm_device *dev,
12279 struct drm_file *filp,
12280 struct drm_mode_fb_cmd2 *mode_cmd)
12281 {
12282 struct drm_i915_gem_object *obj;
12283
12284 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12285 mode_cmd->handles[0]));
12286 if (&obj->base == NULL)
12287 return ERR_PTR(-ENOENT);
12288
12289 return intel_framebuffer_create(dev, mode_cmd, obj);
12290 }
12291
12292 #ifndef CONFIG_DRM_I915_FBDEV
12293 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12294 {
12295 }
12296 #endif
12297
12298 static const struct drm_mode_config_funcs intel_mode_funcs = {
12299 .fb_create = intel_user_framebuffer_create,
12300 .output_poll_changed = intel_fbdev_output_poll_changed,
12301 };
12302
12303 /* Set up chip specific display functions */
12304 static void intel_init_display(struct drm_device *dev)
12305 {
12306 struct drm_i915_private *dev_priv = dev->dev_private;
12307
12308 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12309 dev_priv->display.find_dpll = g4x_find_best_dpll;
12310 else if (IS_CHERRYVIEW(dev))
12311 dev_priv->display.find_dpll = chv_find_best_dpll;
12312 else if (IS_VALLEYVIEW(dev))
12313 dev_priv->display.find_dpll = vlv_find_best_dpll;
12314 else if (IS_PINEVIEW(dev))
12315 dev_priv->display.find_dpll = pnv_find_best_dpll;
12316 else
12317 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12318
12319 if (HAS_DDI(dev)) {
12320 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12321 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12322 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12323 dev_priv->display.crtc_enable = haswell_crtc_enable;
12324 dev_priv->display.crtc_disable = haswell_crtc_disable;
12325 dev_priv->display.off = ironlake_crtc_off;
12326 dev_priv->display.update_primary_plane =
12327 ironlake_update_primary_plane;
12328 } else if (HAS_PCH_SPLIT(dev)) {
12329 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12330 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12331 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12332 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12333 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12334 dev_priv->display.off = ironlake_crtc_off;
12335 dev_priv->display.update_primary_plane =
12336 ironlake_update_primary_plane;
12337 } else if (IS_VALLEYVIEW(dev)) {
12338 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12339 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12340 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12341 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12342 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12343 dev_priv->display.off = i9xx_crtc_off;
12344 dev_priv->display.update_primary_plane =
12345 i9xx_update_primary_plane;
12346 } else {
12347 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12348 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12349 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12350 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12351 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12352 dev_priv->display.off = i9xx_crtc_off;
12353 dev_priv->display.update_primary_plane =
12354 i9xx_update_primary_plane;
12355 }
12356
12357 /* Returns the core display clock speed */
12358 if (IS_VALLEYVIEW(dev))
12359 dev_priv->display.get_display_clock_speed =
12360 valleyview_get_display_clock_speed;
12361 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12362 dev_priv->display.get_display_clock_speed =
12363 i945_get_display_clock_speed;
12364 else if (IS_I915G(dev))
12365 dev_priv->display.get_display_clock_speed =
12366 i915_get_display_clock_speed;
12367 else if (IS_I945GM(dev) || IS_845G(dev))
12368 dev_priv->display.get_display_clock_speed =
12369 i9xx_misc_get_display_clock_speed;
12370 else if (IS_PINEVIEW(dev))
12371 dev_priv->display.get_display_clock_speed =
12372 pnv_get_display_clock_speed;
12373 else if (IS_I915GM(dev))
12374 dev_priv->display.get_display_clock_speed =
12375 i915gm_get_display_clock_speed;
12376 else if (IS_I865G(dev))
12377 dev_priv->display.get_display_clock_speed =
12378 i865_get_display_clock_speed;
12379 else if (IS_I85X(dev))
12380 dev_priv->display.get_display_clock_speed =
12381 i855_get_display_clock_speed;
12382 else /* 852, 830 */
12383 dev_priv->display.get_display_clock_speed =
12384 i830_get_display_clock_speed;
12385
12386 if (IS_G4X(dev)) {
12387 dev_priv->display.write_eld = g4x_write_eld;
12388 } else if (IS_GEN5(dev)) {
12389 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12390 dev_priv->display.write_eld = ironlake_write_eld;
12391 } else if (IS_GEN6(dev)) {
12392 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12393 dev_priv->display.write_eld = ironlake_write_eld;
12394 dev_priv->display.modeset_global_resources =
12395 snb_modeset_global_resources;
12396 } else if (IS_IVYBRIDGE(dev)) {
12397 /* FIXME: detect B0+ stepping and use auto training */
12398 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12399 dev_priv->display.write_eld = ironlake_write_eld;
12400 dev_priv->display.modeset_global_resources =
12401 ivb_modeset_global_resources;
12402 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12403 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12404 dev_priv->display.write_eld = haswell_write_eld;
12405 dev_priv->display.modeset_global_resources =
12406 haswell_modeset_global_resources;
12407 } else if (IS_VALLEYVIEW(dev)) {
12408 dev_priv->display.modeset_global_resources =
12409 valleyview_modeset_global_resources;
12410 dev_priv->display.write_eld = ironlake_write_eld;
12411 }
12412
12413 /* Default just returns -ENODEV to indicate unsupported */
12414 dev_priv->display.queue_flip = intel_default_queue_flip;
12415
12416 switch (INTEL_INFO(dev)->gen) {
12417 case 2:
12418 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12419 break;
12420
12421 case 3:
12422 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12423 break;
12424
12425 case 4:
12426 case 5:
12427 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12428 break;
12429
12430 case 6:
12431 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12432 break;
12433 case 7:
12434 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12435 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12436 break;
12437 }
12438
12439 intel_panel_init_backlight_funcs(dev);
12440 }
12441
12442 /*
12443 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12444 * resume, or other times. This quirk makes sure that's the case for
12445 * affected systems.
12446 */
12447 static void quirk_pipea_force(struct drm_device *dev)
12448 {
12449 struct drm_i915_private *dev_priv = dev->dev_private;
12450
12451 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12452 DRM_INFO("applying pipe a force quirk\n");
12453 }
12454
12455 /*
12456 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12457 */
12458 static void quirk_ssc_force_disable(struct drm_device *dev)
12459 {
12460 struct drm_i915_private *dev_priv = dev->dev_private;
12461 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12462 DRM_INFO("applying lvds SSC disable quirk\n");
12463 }
12464
12465 /*
12466 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12467 * brightness value
12468 */
12469 static void quirk_invert_brightness(struct drm_device *dev)
12470 {
12471 struct drm_i915_private *dev_priv = dev->dev_private;
12472 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12473 DRM_INFO("applying inverted panel brightness quirk\n");
12474 }
12475
12476 /* Some VBT's incorrectly indicate no backlight is present */
12477 static void quirk_backlight_present(struct drm_device *dev)
12478 {
12479 struct drm_i915_private *dev_priv = dev->dev_private;
12480 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12481 DRM_INFO("applying backlight present quirk\n");
12482 }
12483
12484 struct intel_quirk {
12485 int device;
12486 int subsystem_vendor;
12487 int subsystem_device;
12488 void (*hook)(struct drm_device *dev);
12489 };
12490
12491 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12492 struct intel_dmi_quirk {
12493 void (*hook)(struct drm_device *dev);
12494 const struct dmi_system_id (*dmi_id_list)[];
12495 };
12496
12497 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12498 {
12499 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12500 return 1;
12501 }
12502
12503 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12504 {
12505 .dmi_id_list = &(const struct dmi_system_id[]) {
12506 {
12507 .callback = intel_dmi_reverse_brightness,
12508 .ident = "NCR Corporation",
12509 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12510 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12511 },
12512 },
12513 { } /* terminating entry */
12514 },
12515 .hook = quirk_invert_brightness,
12516 },
12517 };
12518
12519 static struct intel_quirk intel_quirks[] = {
12520 /* HP Mini needs pipe A force quirk (LP: #322104) */
12521 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12522
12523 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12524 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12525
12526 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12527 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12528
12529 /* Lenovo U160 cannot use SSC on LVDS */
12530 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12531
12532 /* Sony Vaio Y cannot use SSC on LVDS */
12533 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12534
12535 /* Acer Aspire 5734Z must invert backlight brightness */
12536 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12537
12538 /* Acer/eMachines G725 */
12539 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12540
12541 /* Acer/eMachines e725 */
12542 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12543
12544 /* Acer/Packard Bell NCL20 */
12545 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12546
12547 /* Acer Aspire 4736Z */
12548 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12549
12550 /* Acer Aspire 5336 */
12551 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12552
12553 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12554 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12555
12556 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12557 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12558
12559 /* HP Chromebook 14 (Celeron 2955U) */
12560 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12561 };
12562
12563 static void intel_init_quirks(struct drm_device *dev)
12564 {
12565 struct pci_dev *d = dev->pdev;
12566 int i;
12567
12568 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12569 struct intel_quirk *q = &intel_quirks[i];
12570
12571 if (d->device == q->device &&
12572 (d->subsystem_vendor == q->subsystem_vendor ||
12573 q->subsystem_vendor == PCI_ANY_ID) &&
12574 (d->subsystem_device == q->subsystem_device ||
12575 q->subsystem_device == PCI_ANY_ID))
12576 q->hook(dev);
12577 }
12578 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12579 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12580 intel_dmi_quirks[i].hook(dev);
12581 }
12582 }
12583
12584 /* Disable the VGA plane that we never use */
12585 static void i915_disable_vga(struct drm_device *dev)
12586 {
12587 struct drm_i915_private *dev_priv = dev->dev_private;
12588 u8 sr1;
12589 u32 vga_reg = i915_vgacntrl_reg(dev);
12590
12591 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12592 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12593 outb(SR01, VGA_SR_INDEX);
12594 sr1 = inb(VGA_SR_DATA);
12595 outb(sr1 | 1<<5, VGA_SR_DATA);
12596 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12597 udelay(300);
12598
12599 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12600 POSTING_READ(vga_reg);
12601 }
12602
12603 void intel_modeset_init_hw(struct drm_device *dev)
12604 {
12605 intel_prepare_ddi(dev);
12606
12607 if (IS_VALLEYVIEW(dev))
12608 vlv_update_cdclk(dev);
12609
12610 intel_init_clock_gating(dev);
12611
12612 intel_enable_gt_powersave(dev);
12613 }
12614
12615 void intel_modeset_suspend_hw(struct drm_device *dev)
12616 {
12617 intel_suspend_hw(dev);
12618 }
12619
12620 void intel_modeset_init(struct drm_device *dev)
12621 {
12622 struct drm_i915_private *dev_priv = dev->dev_private;
12623 int sprite, ret;
12624 enum pipe pipe;
12625 struct intel_crtc *crtc;
12626
12627 drm_mode_config_init(dev);
12628
12629 dev->mode_config.min_width = 0;
12630 dev->mode_config.min_height = 0;
12631
12632 dev->mode_config.preferred_depth = 24;
12633 dev->mode_config.prefer_shadow = 1;
12634
12635 dev->mode_config.funcs = &intel_mode_funcs;
12636
12637 intel_init_quirks(dev);
12638
12639 intel_init_pm(dev);
12640
12641 if (INTEL_INFO(dev)->num_pipes == 0)
12642 return;
12643
12644 intel_init_display(dev);
12645
12646 if (IS_GEN2(dev)) {
12647 dev->mode_config.max_width = 2048;
12648 dev->mode_config.max_height = 2048;
12649 } else if (IS_GEN3(dev)) {
12650 dev->mode_config.max_width = 4096;
12651 dev->mode_config.max_height = 4096;
12652 } else {
12653 dev->mode_config.max_width = 8192;
12654 dev->mode_config.max_height = 8192;
12655 }
12656
12657 if (IS_845G(dev) || IS_I865G(dev)) {
12658 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12659 dev->mode_config.cursor_height = 1023;
12660 } else if (IS_GEN2(dev)) {
12661 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12662 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12663 } else {
12664 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12665 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12666 }
12667
12668 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12669
12670 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12671 INTEL_INFO(dev)->num_pipes,
12672 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12673
12674 for_each_pipe(pipe) {
12675 intel_crtc_init(dev, pipe);
12676 for_each_sprite(pipe, sprite) {
12677 ret = intel_plane_init(dev, pipe, sprite);
12678 if (ret)
12679 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12680 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12681 }
12682 }
12683
12684 intel_init_dpio(dev);
12685
12686 intel_shared_dpll_init(dev);
12687
12688 /* Just disable it once at startup */
12689 i915_disable_vga(dev);
12690 intel_setup_outputs(dev);
12691
12692 /* Just in case the BIOS is doing something questionable. */
12693 intel_disable_fbc(dev);
12694
12695 drm_modeset_lock_all(dev);
12696 intel_modeset_setup_hw_state(dev, false);
12697 drm_modeset_unlock_all(dev);
12698
12699 for_each_intel_crtc(dev, crtc) {
12700 if (!crtc->active)
12701 continue;
12702
12703 /*
12704 * Note that reserving the BIOS fb up front prevents us
12705 * from stuffing other stolen allocations like the ring
12706 * on top. This prevents some ugliness at boot time, and
12707 * can even allow for smooth boot transitions if the BIOS
12708 * fb is large enough for the active pipe configuration.
12709 */
12710 if (dev_priv->display.get_plane_config) {
12711 dev_priv->display.get_plane_config(crtc,
12712 &crtc->plane_config);
12713 /*
12714 * If the fb is shared between multiple heads, we'll
12715 * just get the first one.
12716 */
12717 intel_find_plane_obj(crtc, &crtc->plane_config);
12718 }
12719 }
12720 }
12721
12722 static void intel_enable_pipe_a(struct drm_device *dev)
12723 {
12724 struct intel_connector *connector;
12725 struct drm_connector *crt = NULL;
12726 struct intel_load_detect_pipe load_detect_temp;
12727 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12728
12729 /* We can't just switch on the pipe A, we need to set things up with a
12730 * proper mode and output configuration. As a gross hack, enable pipe A
12731 * by enabling the load detect pipe once. */
12732 list_for_each_entry(connector,
12733 &dev->mode_config.connector_list,
12734 base.head) {
12735 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12736 crt = &connector->base;
12737 break;
12738 }
12739 }
12740
12741 if (!crt)
12742 return;
12743
12744 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12745 intel_release_load_detect_pipe(crt, &load_detect_temp);
12746 }
12747
12748 static bool
12749 intel_check_plane_mapping(struct intel_crtc *crtc)
12750 {
12751 struct drm_device *dev = crtc->base.dev;
12752 struct drm_i915_private *dev_priv = dev->dev_private;
12753 u32 reg, val;
12754
12755 if (INTEL_INFO(dev)->num_pipes == 1)
12756 return true;
12757
12758 reg = DSPCNTR(!crtc->plane);
12759 val = I915_READ(reg);
12760
12761 if ((val & DISPLAY_PLANE_ENABLE) &&
12762 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12763 return false;
12764
12765 return true;
12766 }
12767
12768 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12769 {
12770 struct drm_device *dev = crtc->base.dev;
12771 struct drm_i915_private *dev_priv = dev->dev_private;
12772 u32 reg;
12773
12774 /* Clear any frame start delays used for debugging left by the BIOS */
12775 reg = PIPECONF(crtc->config.cpu_transcoder);
12776 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12777
12778 /* restore vblank interrupts to correct state */
12779 if (crtc->active) {
12780 update_scanline_offset(crtc);
12781 drm_vblank_on(dev, crtc->pipe);
12782 } else
12783 drm_vblank_off(dev, crtc->pipe);
12784
12785 /* We need to sanitize the plane -> pipe mapping first because this will
12786 * disable the crtc (and hence change the state) if it is wrong. Note
12787 * that gen4+ has a fixed plane -> pipe mapping. */
12788 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12789 struct intel_connector *connector;
12790 bool plane;
12791
12792 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12793 crtc->base.base.id);
12794
12795 /* Pipe has the wrong plane attached and the plane is active.
12796 * Temporarily change the plane mapping and disable everything
12797 * ... */
12798 plane = crtc->plane;
12799 crtc->plane = !plane;
12800 crtc->primary_enabled = true;
12801 dev_priv->display.crtc_disable(&crtc->base);
12802 crtc->plane = plane;
12803
12804 /* ... and break all links. */
12805 list_for_each_entry(connector, &dev->mode_config.connector_list,
12806 base.head) {
12807 if (connector->encoder->base.crtc != &crtc->base)
12808 continue;
12809
12810 connector->base.dpms = DRM_MODE_DPMS_OFF;
12811 connector->base.encoder = NULL;
12812 }
12813 /* multiple connectors may have the same encoder:
12814 * handle them and break crtc link separately */
12815 list_for_each_entry(connector, &dev->mode_config.connector_list,
12816 base.head)
12817 if (connector->encoder->base.crtc == &crtc->base) {
12818 connector->encoder->base.crtc = NULL;
12819 connector->encoder->connectors_active = false;
12820 }
12821
12822 WARN_ON(crtc->active);
12823 crtc->base.enabled = false;
12824 }
12825
12826 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12827 crtc->pipe == PIPE_A && !crtc->active) {
12828 /* BIOS forgot to enable pipe A, this mostly happens after
12829 * resume. Force-enable the pipe to fix this, the update_dpms
12830 * call below we restore the pipe to the right state, but leave
12831 * the required bits on. */
12832 intel_enable_pipe_a(dev);
12833 }
12834
12835 /* Adjust the state of the output pipe according to whether we
12836 * have active connectors/encoders. */
12837 intel_crtc_update_dpms(&crtc->base);
12838
12839 if (crtc->active != crtc->base.enabled) {
12840 struct intel_encoder *encoder;
12841
12842 /* This can happen either due to bugs in the get_hw_state
12843 * functions or because the pipe is force-enabled due to the
12844 * pipe A quirk. */
12845 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12846 crtc->base.base.id,
12847 crtc->base.enabled ? "enabled" : "disabled",
12848 crtc->active ? "enabled" : "disabled");
12849
12850 crtc->base.enabled = crtc->active;
12851
12852 /* Because we only establish the connector -> encoder ->
12853 * crtc links if something is active, this means the
12854 * crtc is now deactivated. Break the links. connector
12855 * -> encoder links are only establish when things are
12856 * actually up, hence no need to break them. */
12857 WARN_ON(crtc->active);
12858
12859 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12860 WARN_ON(encoder->connectors_active);
12861 encoder->base.crtc = NULL;
12862 }
12863 }
12864
12865 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12866 /*
12867 * We start out with underrun reporting disabled to avoid races.
12868 * For correct bookkeeping mark this on active crtcs.
12869 *
12870 * Also on gmch platforms we dont have any hardware bits to
12871 * disable the underrun reporting. Which means we need to start
12872 * out with underrun reporting disabled also on inactive pipes,
12873 * since otherwise we'll complain about the garbage we read when
12874 * e.g. coming up after runtime pm.
12875 *
12876 * No protection against concurrent access is required - at
12877 * worst a fifo underrun happens which also sets this to false.
12878 */
12879 crtc->cpu_fifo_underrun_disabled = true;
12880 crtc->pch_fifo_underrun_disabled = true;
12881 }
12882 }
12883
12884 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12885 {
12886 struct intel_connector *connector;
12887 struct drm_device *dev = encoder->base.dev;
12888
12889 /* We need to check both for a crtc link (meaning that the
12890 * encoder is active and trying to read from a pipe) and the
12891 * pipe itself being active. */
12892 bool has_active_crtc = encoder->base.crtc &&
12893 to_intel_crtc(encoder->base.crtc)->active;
12894
12895 if (encoder->connectors_active && !has_active_crtc) {
12896 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12897 encoder->base.base.id,
12898 encoder->base.name);
12899
12900 /* Connector is active, but has no active pipe. This is
12901 * fallout from our resume register restoring. Disable
12902 * the encoder manually again. */
12903 if (encoder->base.crtc) {
12904 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12905 encoder->base.base.id,
12906 encoder->base.name);
12907 encoder->disable(encoder);
12908 if (encoder->post_disable)
12909 encoder->post_disable(encoder);
12910 }
12911 encoder->base.crtc = NULL;
12912 encoder->connectors_active = false;
12913
12914 /* Inconsistent output/port/pipe state happens presumably due to
12915 * a bug in one of the get_hw_state functions. Or someplace else
12916 * in our code, like the register restore mess on resume. Clamp
12917 * things to off as a safer default. */
12918 list_for_each_entry(connector,
12919 &dev->mode_config.connector_list,
12920 base.head) {
12921 if (connector->encoder != encoder)
12922 continue;
12923 connector->base.dpms = DRM_MODE_DPMS_OFF;
12924 connector->base.encoder = NULL;
12925 }
12926 }
12927 /* Enabled encoders without active connectors will be fixed in
12928 * the crtc fixup. */
12929 }
12930
12931 void i915_redisable_vga_power_on(struct drm_device *dev)
12932 {
12933 struct drm_i915_private *dev_priv = dev->dev_private;
12934 u32 vga_reg = i915_vgacntrl_reg(dev);
12935
12936 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12937 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12938 i915_disable_vga(dev);
12939 }
12940 }
12941
12942 void i915_redisable_vga(struct drm_device *dev)
12943 {
12944 struct drm_i915_private *dev_priv = dev->dev_private;
12945
12946 /* This function can be called both from intel_modeset_setup_hw_state or
12947 * at a very early point in our resume sequence, where the power well
12948 * structures are not yet restored. Since this function is at a very
12949 * paranoid "someone might have enabled VGA while we were not looking"
12950 * level, just check if the power well is enabled instead of trying to
12951 * follow the "don't touch the power well if we don't need it" policy
12952 * the rest of the driver uses. */
12953 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12954 return;
12955
12956 i915_redisable_vga_power_on(dev);
12957 }
12958
12959 static bool primary_get_hw_state(struct intel_crtc *crtc)
12960 {
12961 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12962
12963 if (!crtc->active)
12964 return false;
12965
12966 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12967 }
12968
12969 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12970 {
12971 struct drm_i915_private *dev_priv = dev->dev_private;
12972 enum pipe pipe;
12973 struct intel_crtc *crtc;
12974 struct intel_encoder *encoder;
12975 struct intel_connector *connector;
12976 int i;
12977
12978 for_each_intel_crtc(dev, crtc) {
12979 memset(&crtc->config, 0, sizeof(crtc->config));
12980
12981 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12982
12983 crtc->active = dev_priv->display.get_pipe_config(crtc,
12984 &crtc->config);
12985
12986 crtc->base.enabled = crtc->active;
12987 crtc->primary_enabled = primary_get_hw_state(crtc);
12988
12989 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12990 crtc->base.base.id,
12991 crtc->active ? "enabled" : "disabled");
12992 }
12993
12994 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12995 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12996
12997 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12998 pll->active = 0;
12999 for_each_intel_crtc(dev, crtc) {
13000 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13001 pll->active++;
13002 }
13003 pll->refcount = pll->active;
13004
13005 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13006 pll->name, pll->refcount, pll->on);
13007
13008 if (pll->refcount)
13009 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13010 }
13011
13012 for_each_intel_encoder(dev, encoder) {
13013 pipe = 0;
13014
13015 if (encoder->get_hw_state(encoder, &pipe)) {
13016 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13017 encoder->base.crtc = &crtc->base;
13018 encoder->get_config(encoder, &crtc->config);
13019 } else {
13020 encoder->base.crtc = NULL;
13021 }
13022
13023 encoder->connectors_active = false;
13024 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13025 encoder->base.base.id,
13026 encoder->base.name,
13027 encoder->base.crtc ? "enabled" : "disabled",
13028 pipe_name(pipe));
13029 }
13030
13031 list_for_each_entry(connector, &dev->mode_config.connector_list,
13032 base.head) {
13033 if (connector->get_hw_state(connector)) {
13034 connector->base.dpms = DRM_MODE_DPMS_ON;
13035 connector->encoder->connectors_active = true;
13036 connector->base.encoder = &connector->encoder->base;
13037 } else {
13038 connector->base.dpms = DRM_MODE_DPMS_OFF;
13039 connector->base.encoder = NULL;
13040 }
13041 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13042 connector->base.base.id,
13043 connector->base.name,
13044 connector->base.encoder ? "enabled" : "disabled");
13045 }
13046 }
13047
13048 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13049 * and i915 state tracking structures. */
13050 void intel_modeset_setup_hw_state(struct drm_device *dev,
13051 bool force_restore)
13052 {
13053 struct drm_i915_private *dev_priv = dev->dev_private;
13054 enum pipe pipe;
13055 struct intel_crtc *crtc;
13056 struct intel_encoder *encoder;
13057 int i;
13058
13059 intel_modeset_readout_hw_state(dev);
13060
13061 /*
13062 * Now that we have the config, copy it to each CRTC struct
13063 * Note that this could go away if we move to using crtc_config
13064 * checking everywhere.
13065 */
13066 for_each_intel_crtc(dev, crtc) {
13067 if (crtc->active && i915.fastboot) {
13068 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13069 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13070 crtc->base.base.id);
13071 drm_mode_debug_printmodeline(&crtc->base.mode);
13072 }
13073 }
13074
13075 /* HW state is read out, now we need to sanitize this mess. */
13076 for_each_intel_encoder(dev, encoder) {
13077 intel_sanitize_encoder(encoder);
13078 }
13079
13080 for_each_pipe(pipe) {
13081 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13082 intel_sanitize_crtc(crtc);
13083 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13084 }
13085
13086 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13087 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13088
13089 if (!pll->on || pll->active)
13090 continue;
13091
13092 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13093
13094 pll->disable(dev_priv, pll);
13095 pll->on = false;
13096 }
13097
13098 if (HAS_PCH_SPLIT(dev))
13099 ilk_wm_get_hw_state(dev);
13100
13101 if (force_restore) {
13102 i915_redisable_vga(dev);
13103
13104 /*
13105 * We need to use raw interfaces for restoring state to avoid
13106 * checking (bogus) intermediate states.
13107 */
13108 for_each_pipe(pipe) {
13109 struct drm_crtc *crtc =
13110 dev_priv->pipe_to_crtc_mapping[pipe];
13111
13112 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13113 crtc->primary->fb);
13114 }
13115 } else {
13116 intel_modeset_update_staged_output_state(dev);
13117 }
13118
13119 intel_modeset_check_state(dev);
13120 }
13121
13122 void intel_modeset_gem_init(struct drm_device *dev)
13123 {
13124 struct drm_crtc *c;
13125 struct drm_i915_gem_object *obj;
13126
13127 mutex_lock(&dev->struct_mutex);
13128 intel_init_gt_powersave(dev);
13129 mutex_unlock(&dev->struct_mutex);
13130
13131 intel_modeset_init_hw(dev);
13132
13133 intel_setup_overlay(dev);
13134
13135 /*
13136 * Make sure any fbs we allocated at startup are properly
13137 * pinned & fenced. When we do the allocation it's too early
13138 * for this.
13139 */
13140 mutex_lock(&dev->struct_mutex);
13141 for_each_crtc(dev, c) {
13142 obj = intel_fb_obj(c->primary->fb);
13143 if (obj == NULL)
13144 continue;
13145
13146 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13147 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13148 to_intel_crtc(c)->pipe);
13149 drm_framebuffer_unreference(c->primary->fb);
13150 c->primary->fb = NULL;
13151 }
13152 }
13153 mutex_unlock(&dev->struct_mutex);
13154 }
13155
13156 void intel_connector_unregister(struct intel_connector *intel_connector)
13157 {
13158 struct drm_connector *connector = &intel_connector->base;
13159
13160 intel_panel_destroy_backlight(connector);
13161 drm_connector_unregister(connector);
13162 }
13163
13164 void intel_modeset_cleanup(struct drm_device *dev)
13165 {
13166 struct drm_i915_private *dev_priv = dev->dev_private;
13167 struct drm_connector *connector;
13168
13169 /*
13170 * Interrupts and polling as the first thing to avoid creating havoc.
13171 * Too much stuff here (turning of rps, connectors, ...) would
13172 * experience fancy races otherwise.
13173 */
13174 drm_irq_uninstall(dev);
13175 intel_hpd_cancel_work(dev_priv);
13176 dev_priv->pm._irqs_disabled = true;
13177
13178 /*
13179 * Due to the hpd irq storm handling the hotplug work can re-arm the
13180 * poll handlers. Hence disable polling after hpd handling is shut down.
13181 */
13182 drm_kms_helper_poll_fini(dev);
13183
13184 mutex_lock(&dev->struct_mutex);
13185
13186 intel_unregister_dsm_handler();
13187
13188 intel_disable_fbc(dev);
13189
13190 intel_disable_gt_powersave(dev);
13191
13192 ironlake_teardown_rc6(dev);
13193
13194 mutex_unlock(&dev->struct_mutex);
13195
13196 /* flush any delayed tasks or pending work */
13197 flush_scheduled_work();
13198
13199 /* destroy the backlight and sysfs files before encoders/connectors */
13200 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13201 struct intel_connector *intel_connector;
13202
13203 intel_connector = to_intel_connector(connector);
13204 intel_connector->unregister(intel_connector);
13205 }
13206
13207 drm_mode_config_cleanup(dev);
13208
13209 intel_cleanup_overlay(dev);
13210
13211 mutex_lock(&dev->struct_mutex);
13212 intel_cleanup_gt_powersave(dev);
13213 mutex_unlock(&dev->struct_mutex);
13214 }
13215
13216 /*
13217 * Return which encoder is currently attached for connector.
13218 */
13219 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13220 {
13221 return &intel_attached_encoder(connector)->base;
13222 }
13223
13224 void intel_connector_attach_encoder(struct intel_connector *connector,
13225 struct intel_encoder *encoder)
13226 {
13227 connector->encoder = encoder;
13228 drm_mode_connector_attach_encoder(&connector->base,
13229 &encoder->base);
13230 }
13231
13232 /*
13233 * set vga decode state - true == enable VGA decode
13234 */
13235 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13236 {
13237 struct drm_i915_private *dev_priv = dev->dev_private;
13238 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13239 u16 gmch_ctrl;
13240
13241 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13242 DRM_ERROR("failed to read control word\n");
13243 return -EIO;
13244 }
13245
13246 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13247 return 0;
13248
13249 if (state)
13250 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13251 else
13252 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13253
13254 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13255 DRM_ERROR("failed to write control word\n");
13256 return -EIO;
13257 }
13258
13259 return 0;
13260 }
13261
13262 struct intel_display_error_state {
13263
13264 u32 power_well_driver;
13265
13266 int num_transcoders;
13267
13268 struct intel_cursor_error_state {
13269 u32 control;
13270 u32 position;
13271 u32 base;
13272 u32 size;
13273 } cursor[I915_MAX_PIPES];
13274
13275 struct intel_pipe_error_state {
13276 bool power_domain_on;
13277 u32 source;
13278 u32 stat;
13279 } pipe[I915_MAX_PIPES];
13280
13281 struct intel_plane_error_state {
13282 u32 control;
13283 u32 stride;
13284 u32 size;
13285 u32 pos;
13286 u32 addr;
13287 u32 surface;
13288 u32 tile_offset;
13289 } plane[I915_MAX_PIPES];
13290
13291 struct intel_transcoder_error_state {
13292 bool power_domain_on;
13293 enum transcoder cpu_transcoder;
13294
13295 u32 conf;
13296
13297 u32 htotal;
13298 u32 hblank;
13299 u32 hsync;
13300 u32 vtotal;
13301 u32 vblank;
13302 u32 vsync;
13303 } transcoder[4];
13304 };
13305
13306 struct intel_display_error_state *
13307 intel_display_capture_error_state(struct drm_device *dev)
13308 {
13309 struct drm_i915_private *dev_priv = dev->dev_private;
13310 struct intel_display_error_state *error;
13311 int transcoders[] = {
13312 TRANSCODER_A,
13313 TRANSCODER_B,
13314 TRANSCODER_C,
13315 TRANSCODER_EDP,
13316 };
13317 int i;
13318
13319 if (INTEL_INFO(dev)->num_pipes == 0)
13320 return NULL;
13321
13322 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13323 if (error == NULL)
13324 return NULL;
13325
13326 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13327 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13328
13329 for_each_pipe(i) {
13330 error->pipe[i].power_domain_on =
13331 intel_display_power_enabled_unlocked(dev_priv,
13332 POWER_DOMAIN_PIPE(i));
13333 if (!error->pipe[i].power_domain_on)
13334 continue;
13335
13336 error->cursor[i].control = I915_READ(CURCNTR(i));
13337 error->cursor[i].position = I915_READ(CURPOS(i));
13338 error->cursor[i].base = I915_READ(CURBASE(i));
13339
13340 error->plane[i].control = I915_READ(DSPCNTR(i));
13341 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13342 if (INTEL_INFO(dev)->gen <= 3) {
13343 error->plane[i].size = I915_READ(DSPSIZE(i));
13344 error->plane[i].pos = I915_READ(DSPPOS(i));
13345 }
13346 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13347 error->plane[i].addr = I915_READ(DSPADDR(i));
13348 if (INTEL_INFO(dev)->gen >= 4) {
13349 error->plane[i].surface = I915_READ(DSPSURF(i));
13350 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13351 }
13352
13353 error->pipe[i].source = I915_READ(PIPESRC(i));
13354
13355 if (HAS_GMCH_DISPLAY(dev))
13356 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13357 }
13358
13359 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13360 if (HAS_DDI(dev_priv->dev))
13361 error->num_transcoders++; /* Account for eDP. */
13362
13363 for (i = 0; i < error->num_transcoders; i++) {
13364 enum transcoder cpu_transcoder = transcoders[i];
13365
13366 error->transcoder[i].power_domain_on =
13367 intel_display_power_enabled_unlocked(dev_priv,
13368 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13369 if (!error->transcoder[i].power_domain_on)
13370 continue;
13371
13372 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13373
13374 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13375 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13376 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13377 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13378 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13379 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13380 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13381 }
13382
13383 return error;
13384 }
13385
13386 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13387
13388 void
13389 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13390 struct drm_device *dev,
13391 struct intel_display_error_state *error)
13392 {
13393 int i;
13394
13395 if (!error)
13396 return;
13397
13398 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13399 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13400 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13401 error->power_well_driver);
13402 for_each_pipe(i) {
13403 err_printf(m, "Pipe [%d]:\n", i);
13404 err_printf(m, " Power: %s\n",
13405 error->pipe[i].power_domain_on ? "on" : "off");
13406 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13407 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13408
13409 err_printf(m, "Plane [%d]:\n", i);
13410 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13411 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13412 if (INTEL_INFO(dev)->gen <= 3) {
13413 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13414 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13415 }
13416 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13417 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13418 if (INTEL_INFO(dev)->gen >= 4) {
13419 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13420 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13421 }
13422
13423 err_printf(m, "Cursor [%d]:\n", i);
13424 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13425 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13426 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13427 }
13428
13429 for (i = 0; i < error->num_transcoders; i++) {
13430 err_printf(m, "CPU transcoder: %c\n",
13431 transcoder_name(error->transcoder[i].cpu_transcoder));
13432 err_printf(m, " Power: %s\n",
13433 error->transcoder[i].power_domain_on ? "on" : "off");
13434 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13435 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13436 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13437 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13438 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13439 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13440 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13441 }
13442 }
13443
13444 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13445 {
13446 struct intel_crtc *crtc;
13447
13448 for_each_intel_crtc(dev, crtc) {
13449 struct intel_unpin_work *work;
13450 unsigned long irqflags;
13451
13452 spin_lock_irqsave(&dev->event_lock, irqflags);
13453
13454 work = crtc->unpin_work;
13455
13456 if (work && work->event &&
13457 work->event->base.file_priv == file) {
13458 kfree(work->event);
13459 work->event = NULL;
13460 }
13461
13462 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13463 }
13464 }
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