2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t
;
72 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
85 * Returns true on success, false on failure.
87 bool (*find_pll
)(const intel_limit_t
*limit
,
88 struct drm_crtc
*crtc
,
89 int target
, int refclk
,
90 intel_clock_t
*match_clock
,
91 intel_clock_t
*best_clock
);
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
98 intel_pch_rawclk(struct drm_device
*dev
)
100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
102 WARN_ON(!HAS_PCH_SPLIT(dev
));
104 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
108 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
109 int target
, int refclk
, intel_clock_t
*match_clock
,
110 intel_clock_t
*best_clock
);
112 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
113 int target
, int refclk
, intel_clock_t
*match_clock
,
114 intel_clock_t
*best_clock
);
117 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
118 int target
, int refclk
, intel_clock_t
*match_clock
,
119 intel_clock_t
*best_clock
);
121 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
122 int target
, int refclk
, intel_clock_t
*match_clock
,
123 intel_clock_t
*best_clock
);
126 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
127 int target
, int refclk
, intel_clock_t
*match_clock
,
128 intel_clock_t
*best_clock
);
130 static inline u32
/* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device
*dev
)
134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
135 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
140 static const intel_limit_t intel_limits_i8xx_dvo
= {
141 .dot
= { .min
= 25000, .max
= 350000 },
142 .vco
= { .min
= 930000, .max
= 1400000 },
143 .n
= { .min
= 3, .max
= 16 },
144 .m
= { .min
= 96, .max
= 140 },
145 .m1
= { .min
= 18, .max
= 26 },
146 .m2
= { .min
= 6, .max
= 16 },
147 .p
= { .min
= 4, .max
= 128 },
148 .p1
= { .min
= 2, .max
= 33 },
149 .p2
= { .dot_limit
= 165000,
150 .p2_slow
= 4, .p2_fast
= 2 },
151 .find_pll
= intel_find_best_PLL
,
154 static const intel_limit_t intel_limits_i8xx_lvds
= {
155 .dot
= { .min
= 25000, .max
= 350000 },
156 .vco
= { .min
= 930000, .max
= 1400000 },
157 .n
= { .min
= 3, .max
= 16 },
158 .m
= { .min
= 96, .max
= 140 },
159 .m1
= { .min
= 18, .max
= 26 },
160 .m2
= { .min
= 6, .max
= 16 },
161 .p
= { .min
= 4, .max
= 128 },
162 .p1
= { .min
= 1, .max
= 6 },
163 .p2
= { .dot_limit
= 165000,
164 .p2_slow
= 14, .p2_fast
= 7 },
165 .find_pll
= intel_find_best_PLL
,
168 static const intel_limit_t intel_limits_i9xx_sdvo
= {
169 .dot
= { .min
= 20000, .max
= 400000 },
170 .vco
= { .min
= 1400000, .max
= 2800000 },
171 .n
= { .min
= 1, .max
= 6 },
172 .m
= { .min
= 70, .max
= 120 },
173 .m1
= { .min
= 8, .max
= 18 },
174 .m2
= { .min
= 3, .max
= 7 },
175 .p
= { .min
= 5, .max
= 80 },
176 .p1
= { .min
= 1, .max
= 8 },
177 .p2
= { .dot_limit
= 200000,
178 .p2_slow
= 10, .p2_fast
= 5 },
179 .find_pll
= intel_find_best_PLL
,
182 static const intel_limit_t intel_limits_i9xx_lvds
= {
183 .dot
= { .min
= 20000, .max
= 400000 },
184 .vco
= { .min
= 1400000, .max
= 2800000 },
185 .n
= { .min
= 1, .max
= 6 },
186 .m
= { .min
= 70, .max
= 120 },
187 .m1
= { .min
= 8, .max
= 18 },
188 .m2
= { .min
= 3, .max
= 7 },
189 .p
= { .min
= 7, .max
= 98 },
190 .p1
= { .min
= 1, .max
= 8 },
191 .p2
= { .dot_limit
= 112000,
192 .p2_slow
= 14, .p2_fast
= 7 },
193 .find_pll
= intel_find_best_PLL
,
197 static const intel_limit_t intel_limits_g4x_sdvo
= {
198 .dot
= { .min
= 25000, .max
= 270000 },
199 .vco
= { .min
= 1750000, .max
= 3500000},
200 .n
= { .min
= 1, .max
= 4 },
201 .m
= { .min
= 104, .max
= 138 },
202 .m1
= { .min
= 17, .max
= 23 },
203 .m2
= { .min
= 5, .max
= 11 },
204 .p
= { .min
= 10, .max
= 30 },
205 .p1
= { .min
= 1, .max
= 3},
206 .p2
= { .dot_limit
= 270000,
210 .find_pll
= intel_g4x_find_best_PLL
,
213 static const intel_limit_t intel_limits_g4x_hdmi
= {
214 .dot
= { .min
= 22000, .max
= 400000 },
215 .vco
= { .min
= 1750000, .max
= 3500000},
216 .n
= { .min
= 1, .max
= 4 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 16, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 5, .max
= 80 },
221 .p1
= { .min
= 1, .max
= 8},
222 .p2
= { .dot_limit
= 165000,
223 .p2_slow
= 10, .p2_fast
= 5 },
224 .find_pll
= intel_g4x_find_best_PLL
,
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
228 .dot
= { .min
= 20000, .max
= 115000 },
229 .vco
= { .min
= 1750000, .max
= 3500000 },
230 .n
= { .min
= 1, .max
= 3 },
231 .m
= { .min
= 104, .max
= 138 },
232 .m1
= { .min
= 17, .max
= 23 },
233 .m2
= { .min
= 5, .max
= 11 },
234 .p
= { .min
= 28, .max
= 112 },
235 .p1
= { .min
= 2, .max
= 8 },
236 .p2
= { .dot_limit
= 0,
237 .p2_slow
= 14, .p2_fast
= 14
239 .find_pll
= intel_g4x_find_best_PLL
,
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
243 .dot
= { .min
= 80000, .max
= 224000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 14, .max
= 42 },
250 .p1
= { .min
= 2, .max
= 6 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 7, .p2_fast
= 7
254 .find_pll
= intel_g4x_find_best_PLL
,
257 static const intel_limit_t intel_limits_g4x_display_port
= {
258 .dot
= { .min
= 161670, .max
= 227000 },
259 .vco
= { .min
= 1750000, .max
= 3500000},
260 .n
= { .min
= 1, .max
= 2 },
261 .m
= { .min
= 97, .max
= 108 },
262 .m1
= { .min
= 0x10, .max
= 0x12 },
263 .m2
= { .min
= 0x05, .max
= 0x06 },
264 .p
= { .min
= 10, .max
= 20 },
265 .p1
= { .min
= 1, .max
= 2},
266 .p2
= { .dot_limit
= 0,
267 .p2_slow
= 10, .p2_fast
= 10 },
268 .find_pll
= intel_find_pll_g4x_dp
,
271 static const intel_limit_t intel_limits_pineview_sdvo
= {
272 .dot
= { .min
= 20000, .max
= 400000},
273 .vco
= { .min
= 1700000, .max
= 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n
= { .min
= 3, .max
= 6 },
276 .m
= { .min
= 2, .max
= 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1
= { .min
= 0, .max
= 0 },
279 .m2
= { .min
= 0, .max
= 254 },
280 .p
= { .min
= 5, .max
= 80 },
281 .p1
= { .min
= 1, .max
= 8 },
282 .p2
= { .dot_limit
= 200000,
283 .p2_slow
= 10, .p2_fast
= 5 },
284 .find_pll
= intel_find_best_PLL
,
287 static const intel_limit_t intel_limits_pineview_lvds
= {
288 .dot
= { .min
= 20000, .max
= 400000 },
289 .vco
= { .min
= 1700000, .max
= 3500000 },
290 .n
= { .min
= 3, .max
= 6 },
291 .m
= { .min
= 2, .max
= 256 },
292 .m1
= { .min
= 0, .max
= 0 },
293 .m2
= { .min
= 0, .max
= 254 },
294 .p
= { .min
= 7, .max
= 112 },
295 .p1
= { .min
= 1, .max
= 8 },
296 .p2
= { .dot_limit
= 112000,
297 .p2_slow
= 14, .p2_fast
= 14 },
298 .find_pll
= intel_find_best_PLL
,
301 /* Ironlake / Sandybridge
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
306 static const intel_limit_t intel_limits_ironlake_dac
= {
307 .dot
= { .min
= 25000, .max
= 350000 },
308 .vco
= { .min
= 1760000, .max
= 3510000 },
309 .n
= { .min
= 1, .max
= 5 },
310 .m
= { .min
= 79, .max
= 127 },
311 .m1
= { .min
= 12, .max
= 22 },
312 .m2
= { .min
= 5, .max
= 9 },
313 .p
= { .min
= 5, .max
= 80 },
314 .p1
= { .min
= 1, .max
= 8 },
315 .p2
= { .dot_limit
= 225000,
316 .p2_slow
= 10, .p2_fast
= 5 },
317 .find_pll
= intel_g4x_find_best_PLL
,
320 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
321 .dot
= { .min
= 25000, .max
= 350000 },
322 .vco
= { .min
= 1760000, .max
= 3510000 },
323 .n
= { .min
= 1, .max
= 3 },
324 .m
= { .min
= 79, .max
= 118 },
325 .m1
= { .min
= 12, .max
= 22 },
326 .m2
= { .min
= 5, .max
= 9 },
327 .p
= { .min
= 28, .max
= 112 },
328 .p1
= { .min
= 2, .max
= 8 },
329 .p2
= { .dot_limit
= 225000,
330 .p2_slow
= 14, .p2_fast
= 14 },
331 .find_pll
= intel_g4x_find_best_PLL
,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
335 .dot
= { .min
= 25000, .max
= 350000 },
336 .vco
= { .min
= 1760000, .max
= 3510000 },
337 .n
= { .min
= 1, .max
= 3 },
338 .m
= { .min
= 79, .max
= 127 },
339 .m1
= { .min
= 12, .max
= 22 },
340 .m2
= { .min
= 5, .max
= 9 },
341 .p
= { .min
= 14, .max
= 56 },
342 .p1
= { .min
= 2, .max
= 8 },
343 .p2
= { .dot_limit
= 225000,
344 .p2_slow
= 7, .p2_fast
= 7 },
345 .find_pll
= intel_g4x_find_best_PLL
,
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
350 .dot
= { .min
= 25000, .max
= 350000 },
351 .vco
= { .min
= 1760000, .max
= 3510000 },
352 .n
= { .min
= 1, .max
= 2 },
353 .m
= { .min
= 79, .max
= 126 },
354 .m1
= { .min
= 12, .max
= 22 },
355 .m2
= { .min
= 5, .max
= 9 },
356 .p
= { .min
= 28, .max
= 112 },
357 .p1
= { .min
= 2, .max
= 8 },
358 .p2
= { .dot_limit
= 225000,
359 .p2_slow
= 14, .p2_fast
= 14 },
360 .find_pll
= intel_g4x_find_best_PLL
,
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
364 .dot
= { .min
= 25000, .max
= 350000 },
365 .vco
= { .min
= 1760000, .max
= 3510000 },
366 .n
= { .min
= 1, .max
= 3 },
367 .m
= { .min
= 79, .max
= 126 },
368 .m1
= { .min
= 12, .max
= 22 },
369 .m2
= { .min
= 5, .max
= 9 },
370 .p
= { .min
= 14, .max
= 42 },
371 .p1
= { .min
= 2, .max
= 6 },
372 .p2
= { .dot_limit
= 225000,
373 .p2_slow
= 7, .p2_fast
= 7 },
374 .find_pll
= intel_g4x_find_best_PLL
,
377 static const intel_limit_t intel_limits_ironlake_display_port
= {
378 .dot
= { .min
= 25000, .max
= 350000 },
379 .vco
= { .min
= 1760000, .max
= 3510000},
380 .n
= { .min
= 1, .max
= 2 },
381 .m
= { .min
= 81, .max
= 90 },
382 .m1
= { .min
= 12, .max
= 22 },
383 .m2
= { .min
= 5, .max
= 9 },
384 .p
= { .min
= 10, .max
= 20 },
385 .p1
= { .min
= 1, .max
= 2},
386 .p2
= { .dot_limit
= 0,
387 .p2_slow
= 10, .p2_fast
= 10 },
388 .find_pll
= intel_find_pll_ironlake_dp
,
391 static const intel_limit_t intel_limits_vlv_dac
= {
392 .dot
= { .min
= 25000, .max
= 270000 },
393 .vco
= { .min
= 4000000, .max
= 6000000 },
394 .n
= { .min
= 1, .max
= 7 },
395 .m
= { .min
= 22, .max
= 450 }, /* guess */
396 .m1
= { .min
= 2, .max
= 3 },
397 .m2
= { .min
= 11, .max
= 156 },
398 .p
= { .min
= 10, .max
= 30 },
399 .p1
= { .min
= 2, .max
= 3 },
400 .p2
= { .dot_limit
= 270000,
401 .p2_slow
= 2, .p2_fast
= 20 },
402 .find_pll
= intel_vlv_find_best_pll
,
405 static const intel_limit_t intel_limits_vlv_hdmi
= {
406 .dot
= { .min
= 20000, .max
= 165000 },
407 .vco
= { .min
= 4000000, .max
= 5994000},
408 .n
= { .min
= 1, .max
= 7 },
409 .m
= { .min
= 60, .max
= 300 }, /* guess */
410 .m1
= { .min
= 2, .max
= 3 },
411 .m2
= { .min
= 11, .max
= 156 },
412 .p
= { .min
= 10, .max
= 30 },
413 .p1
= { .min
= 2, .max
= 3 },
414 .p2
= { .dot_limit
= 270000,
415 .p2_slow
= 2, .p2_fast
= 20 },
416 .find_pll
= intel_vlv_find_best_pll
,
419 static const intel_limit_t intel_limits_vlv_dp
= {
420 .dot
= { .min
= 25000, .max
= 270000 },
421 .vco
= { .min
= 4000000, .max
= 6000000 },
422 .n
= { .min
= 1, .max
= 7 },
423 .m
= { .min
= 22, .max
= 450 },
424 .m1
= { .min
= 2, .max
= 3 },
425 .m2
= { .min
= 11, .max
= 156 },
426 .p
= { .min
= 10, .max
= 30 },
427 .p1
= { .min
= 2, .max
= 3 },
428 .p2
= { .dot_limit
= 270000,
429 .p2_slow
= 2, .p2_fast
= 20 },
430 .find_pll
= intel_vlv_find_best_pll
,
433 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
435 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
442 I915_WRITE(DPIO_REG
, reg
);
443 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
450 return I915_READ(DPIO_DATA
);
453 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
456 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
463 I915_WRITE(DPIO_DATA
, val
);
464 I915_WRITE(DPIO_REG
, reg
);
465 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
471 static void vlv_init_dpio(struct drm_device
*dev
)
473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL
, 0);
477 POSTING_READ(DPIO_CTL
);
478 I915_WRITE(DPIO_CTL
, 1);
479 POSTING_READ(DPIO_CTL
);
482 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
485 struct drm_device
*dev
= crtc
->dev
;
486 const intel_limit_t
*limit
;
488 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
489 if (intel_is_dual_link_lvds(dev
)) {
490 if (refclk
== 100000)
491 limit
= &intel_limits_ironlake_dual_lvds_100m
;
493 limit
= &intel_limits_ironlake_dual_lvds
;
495 if (refclk
== 100000)
496 limit
= &intel_limits_ironlake_single_lvds_100m
;
498 limit
= &intel_limits_ironlake_single_lvds
;
500 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
501 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
502 limit
= &intel_limits_ironlake_display_port
;
504 limit
= &intel_limits_ironlake_dac
;
509 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
511 struct drm_device
*dev
= crtc
->dev
;
512 const intel_limit_t
*limit
;
514 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
515 if (intel_is_dual_link_lvds(dev
))
516 limit
= &intel_limits_g4x_dual_channel_lvds
;
518 limit
= &intel_limits_g4x_single_channel_lvds
;
519 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
520 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
521 limit
= &intel_limits_g4x_hdmi
;
522 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
523 limit
= &intel_limits_g4x_sdvo
;
524 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
525 limit
= &intel_limits_g4x_display_port
;
526 } else /* The option is for other outputs */
527 limit
= &intel_limits_i9xx_sdvo
;
532 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
534 struct drm_device
*dev
= crtc
->dev
;
535 const intel_limit_t
*limit
;
537 if (HAS_PCH_SPLIT(dev
))
538 limit
= intel_ironlake_limit(crtc
, refclk
);
539 else if (IS_G4X(dev
)) {
540 limit
= intel_g4x_limit(crtc
);
541 } else if (IS_PINEVIEW(dev
)) {
542 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
543 limit
= &intel_limits_pineview_lvds
;
545 limit
= &intel_limits_pineview_sdvo
;
546 } else if (IS_VALLEYVIEW(dev
)) {
547 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
548 limit
= &intel_limits_vlv_dac
;
549 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
550 limit
= &intel_limits_vlv_hdmi
;
552 limit
= &intel_limits_vlv_dp
;
553 } else if (!IS_GEN2(dev
)) {
554 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
555 limit
= &intel_limits_i9xx_lvds
;
557 limit
= &intel_limits_i9xx_sdvo
;
559 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
560 limit
= &intel_limits_i8xx_lvds
;
562 limit
= &intel_limits_i8xx_dvo
;
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
570 clock
->m
= clock
->m2
+ 2;
571 clock
->p
= clock
->p1
* clock
->p2
;
572 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
573 clock
->dot
= clock
->vco
/ clock
->p
;
576 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
578 if (IS_PINEVIEW(dev
)) {
579 pineview_clock(refclk
, clock
);
582 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
583 clock
->p
= clock
->p1
* clock
->p2
;
584 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
585 clock
->dot
= clock
->vco
/ clock
->p
;
589 * Returns whether any output on the specified pipe is of the specified type
591 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
593 struct drm_device
*dev
= crtc
->dev
;
594 struct intel_encoder
*encoder
;
596 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
597 if (encoder
->type
== type
)
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
609 static bool intel_PLL_is_valid(struct drm_device
*dev
,
610 const intel_limit_t
*limit
,
611 const intel_clock_t
*clock
)
613 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
616 INTELPllInvalid("p out of range\n");
617 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
624 INTELPllInvalid("m out of range\n");
625 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
626 INTELPllInvalid("n out of range\n");
627 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
632 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
633 INTELPllInvalid("dot out of range\n");
639 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
640 int target
, int refclk
, intel_clock_t
*match_clock
,
641 intel_clock_t
*best_clock
)
644 struct drm_device
*dev
= crtc
->dev
;
648 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
654 if (intel_is_dual_link_lvds(dev
))
655 clock
.p2
= limit
->p2
.p2_fast
;
657 clock
.p2
= limit
->p2
.p2_slow
;
659 if (target
< limit
->p2
.dot_limit
)
660 clock
.p2
= limit
->p2
.p2_slow
;
662 clock
.p2
= limit
->p2
.p2_fast
;
665 memset(best_clock
, 0, sizeof(*best_clock
));
667 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
669 for (clock
.m2
= limit
->m2
.min
;
670 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
671 /* m1 is always 0 in Pineview */
672 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
674 for (clock
.n
= limit
->n
.min
;
675 clock
.n
<= limit
->n
.max
; clock
.n
++) {
676 for (clock
.p1
= limit
->p1
.min
;
677 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
680 intel_clock(dev
, refclk
, &clock
);
681 if (!intel_PLL_is_valid(dev
, limit
,
685 clock
.p
!= match_clock
->p
)
688 this_err
= abs(clock
.dot
- target
);
689 if (this_err
< err
) {
698 return (err
!= target
);
702 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
703 int target
, int refclk
, intel_clock_t
*match_clock
,
704 intel_clock_t
*best_clock
)
706 struct drm_device
*dev
= crtc
->dev
;
710 /* approximately equals target * 0.00585 */
711 int err_most
= (target
>> 8) + (target
>> 9);
714 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (HAS_PCH_SPLIT(dev
))
721 if (intel_is_dual_link_lvds(dev
))
722 clock
.p2
= limit
->p2
.p2_fast
;
724 clock
.p2
= limit
->p2
.p2_slow
;
726 if (target
< limit
->p2
.dot_limit
)
727 clock
.p2
= limit
->p2
.p2_slow
;
729 clock
.p2
= limit
->p2
.p2_fast
;
732 memset(best_clock
, 0, sizeof(*best_clock
));
733 max_n
= limit
->n
.max
;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock
.m1
= limit
->m1
.max
;
738 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
739 for (clock
.m2
= limit
->m2
.max
;
740 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
741 for (clock
.p1
= limit
->p1
.max
;
742 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
745 intel_clock(dev
, refclk
, &clock
);
746 if (!intel_PLL_is_valid(dev
, limit
,
750 clock
.p
!= match_clock
->p
)
753 this_err
= abs(clock
.dot
- target
);
754 if (this_err
< err_most
) {
768 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
769 int target
, int refclk
, intel_clock_t
*match_clock
,
770 intel_clock_t
*best_clock
)
772 struct drm_device
*dev
= crtc
->dev
;
775 if (target
< 200000) {
788 intel_clock(dev
, refclk
, &clock
);
789 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
795 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
796 int target
, int refclk
, intel_clock_t
*match_clock
,
797 intel_clock_t
*best_clock
)
800 if (target
< 200000) {
813 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
814 clock
.p
= (clock
.p1
* clock
.p2
);
815 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
817 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
821 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
822 int target
, int refclk
, intel_clock_t
*match_clock
,
823 intel_clock_t
*best_clock
)
825 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
827 u32 updrate
, minupdate
, fracbits
, p
;
828 unsigned long bestppm
, ppm
, absppm
;
832 dotclk
= target
* 1000;
835 fastclk
= dotclk
/ (2*100);
839 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
840 bestm1
= bestm2
= bestp1
= bestp2
= 0;
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
844 updrate
= refclk
/ n
;
845 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
846 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
852 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
853 refclk
) / (2*refclk
));
856 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
857 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
858 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
859 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
863 if (absppm
< bestppm
- 10) {
880 best_clock
->n
= bestn
;
881 best_clock
->m1
= bestm1
;
882 best_clock
->m2
= bestm2
;
883 best_clock
->p1
= bestp1
;
884 best_clock
->p2
= bestp2
;
889 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
892 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
893 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
895 return intel_crtc
->cpu_transcoder
;
898 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
903 frame
= I915_READ(frame_reg
);
905 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
910 * intel_wait_for_vblank - wait for vblank on a given pipe
912 * @pipe: pipe to wait for
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
917 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
920 int pipestat_reg
= PIPESTAT(pipe
);
922 if (INTEL_INFO(dev
)->gen
>= 5) {
923 ironlake_wait_for_vblank(dev
, pipe
);
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
940 I915_WRITE(pipestat_reg
,
941 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg
) &
945 PIPE_VBLANK_INTERRUPT_STATUS
,
947 DRM_DEBUG_KMS("vblank wait timed out\n");
951 * intel_wait_for_pipe_off - wait for pipe to turn off
953 * @pipe: pipe to wait for
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
960 * wait for the pipe register state bit to turn off
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
967 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
970 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
973 if (INTEL_INFO(dev
)->gen
>= 4) {
974 int reg
= PIPECONF(cpu_transcoder
);
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
979 WARN(1, "pipe_off wait timed out\n");
981 u32 last_line
, line_mask
;
982 int reg
= PIPEDSL(pipe
);
983 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
986 line_mask
= DSL_LINEMASK_GEN2
;
988 line_mask
= DSL_LINEMASK_GEN3
;
990 /* Wait for the display line to settle */
992 last_line
= I915_READ(reg
) & line_mask
;
994 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
995 time_after(timeout
, jiffies
));
996 if (time_after(jiffies
, timeout
))
997 WARN(1, "pipe_off wait timed out\n");
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1006 * Returns true if @port is connected, false otherwise.
1008 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1009 struct intel_digital_port
*port
)
1013 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1014 switch(port
->port
) {
1016 bit
= SDE_PORTB_HOTPLUG
;
1019 bit
= SDE_PORTC_HOTPLUG
;
1022 bit
= SDE_PORTD_HOTPLUG
;
1028 switch(port
->port
) {
1030 bit
= SDE_PORTB_HOTPLUG_CPT
;
1033 bit
= SDE_PORTC_HOTPLUG_CPT
;
1036 bit
= SDE_PORTD_HOTPLUG_CPT
;
1043 return I915_READ(SDEISR
) & bit
;
1046 static const char *state_string(bool enabled
)
1048 return enabled
? "on" : "off";
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private
*dev_priv
,
1053 enum pipe pipe
, bool state
)
1060 val
= I915_READ(reg
);
1061 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1062 WARN(cur_state
!= state
,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state
), state_string(cur_state
));
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1070 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1071 struct intel_pch_pll
*pll
,
1072 struct intel_crtc
*crtc
,
1078 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1087 val
= I915_READ(pll
->pll_reg
);
1088 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1089 WARN(cur_state
!= state
,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1097 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1098 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1099 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state
, crtc
->pipe
, pch_dpll
)) {
1102 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1103 WARN(cur_state
!= state
,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll
->pll_reg
== _PCH_DPLL_B
,
1106 state_string(state
),
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1115 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1116 enum pipe pipe
, bool state
)
1121 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1124 if (HAS_DDI(dev_priv
->dev
)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1130 reg
= FDI_TX_CTL(pipe
);
1131 val
= I915_READ(reg
);
1132 cur_state
= !!(val
& FDI_TX_ENABLE
);
1134 WARN(cur_state
!= state
,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state
), state_string(cur_state
));
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1142 enum pipe pipe
, bool state
)
1148 reg
= FDI_RX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 cur_state
= !!(val
& FDI_RX_ENABLE
);
1151 WARN(cur_state
!= state
,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state
), state_string(cur_state
));
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv
->info
->gen
== 5)
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv
->dev
))
1172 reg
= FDI_TX_CTL(pipe
);
1173 val
= I915_READ(reg
);
1174 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1183 reg
= FDI_RX_CTL(pipe
);
1184 val
= I915_READ(reg
);
1185 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1191 int pp_reg
, lvds_reg
;
1193 enum pipe panel_pipe
= PIPE_A
;
1196 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1197 pp_reg
= PCH_PP_CONTROL
;
1198 lvds_reg
= PCH_LVDS
;
1200 pp_reg
= PP_CONTROL
;
1204 val
= I915_READ(pp_reg
);
1205 if (!(val
& PANEL_POWER_ON
) ||
1206 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1209 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1210 panel_pipe
= PIPE_B
;
1212 WARN(panel_pipe
== pipe
&& locked
,
1213 "panel assertion failure, pipe %c regs locked\n",
1217 void assert_pipe(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
)
1223 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1230 if (IS_HASWELL(dev_priv
->dev
) && cpu_transcoder
!= TRANSCODER_EDP
&&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_ENABLE
)) {
1234 reg
= PIPECONF(cpu_transcoder
);
1235 val
= I915_READ(reg
);
1236 cur_state
= !!(val
& PIPECONF_ENABLE
);
1239 WARN(cur_state
!= state
,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1244 static void assert_plane(struct drm_i915_private
*dev_priv
,
1245 enum plane plane
, bool state
)
1251 reg
= DSPCNTR(plane
);
1252 val
= I915_READ(reg
);
1253 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1254 WARN(cur_state
!= state
,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane
), state_string(state
), state_string(cur_state
));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1271 reg
= DSPCNTR(pipe
);
1272 val
= I915_READ(reg
);
1273 WARN((val
& DISPLAY_PLANE_ENABLE
),
1274 "plane %c assertion failure, should be disabled but not\n",
1279 /* Need to check both planes against the pipe */
1280 for (i
= 0; i
< 2; i
++) {
1282 val
= I915_READ(reg
);
1283 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1284 DISPPLANE_SEL_PIPE_SHIFT
;
1285 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i
), pipe_name(pipe
));
1291 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1296 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1301 val
= I915_READ(PCH_DREF_CONTROL
);
1302 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1303 DREF_SUPERSPREAD_SOURCE_MASK
));
1304 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1307 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1314 reg
= TRANSCONF(pipe
);
1315 val
= I915_READ(reg
);
1316 enabled
= !!(val
& TRANS_ENABLE
);
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1322 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1323 enum pipe pipe
, u32 port_sel
, u32 val
)
1325 if ((val
& DP_PORT_EN
) == 0)
1328 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1329 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1330 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1331 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1334 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1340 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1341 enum pipe pipe
, u32 val
)
1343 if ((val
& PORT_ENABLE
) == 0)
1346 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1347 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1350 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1356 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1357 enum pipe pipe
, u32 val
)
1359 if ((val
& LVDS_PORT_EN
) == 0)
1362 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1363 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1366 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1372 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1373 enum pipe pipe
, u32 val
)
1375 if ((val
& ADPA_DAC_ENABLE
) == 0)
1377 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1378 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1381 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1387 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1388 enum pipe pipe
, int reg
, u32 port_sel
)
1390 u32 val
= I915_READ(reg
);
1391 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1393 reg
, pipe_name(pipe
));
1395 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1396 && (val
& DP_PIPEB_SELECT
),
1397 "IBX PCH dp port still using transcoder B\n");
1400 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1401 enum pipe pipe
, int reg
)
1403 u32 val
= I915_READ(reg
);
1404 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1406 reg
, pipe_name(pipe
));
1408 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& PORT_ENABLE
) == 0
1409 && (val
& SDVO_PIPE_B_SELECT
),
1410 "IBX PCH hdmi port still using transcoder B\n");
1413 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1419 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1420 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1421 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1424 val
= I915_READ(reg
);
1425 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
1430 val
= I915_READ(reg
);
1431 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1435 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1436 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1437 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1449 * Note! This is for pre-ILK only.
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1453 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1458 /* No really, not for ILK+ */
1459 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1463 assert_panel_unlocked(dev_priv
, pipe
);
1466 val
= I915_READ(reg
);
1467 val
|= DPLL_VCO_ENABLE
;
1469 /* We do this three times for luck */
1470 I915_WRITE(reg
, val
);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg
, val
);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg
, val
);
1478 udelay(150); /* wait for warmup */
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1488 * Note! This is for pre-ILK only.
1490 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv
, pipe
);
1503 val
= I915_READ(reg
);
1504 val
&= ~DPLL_VCO_ENABLE
;
1505 I915_WRITE(reg
, val
);
1511 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
1512 enum intel_sbi_destination destination
)
1516 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1518 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
1524 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1525 I915_WRITE(SBI_DATA
, value
);
1527 if (destination
== SBI_ICLK
)
1528 tmp
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRWR
;
1530 tmp
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IOWR
;
1531 I915_WRITE(SBI_CTL_STAT
, SBI_BUSY
| tmp
);
1533 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1541 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
1542 enum intel_sbi_destination destination
)
1545 WARN_ON(!mutex_is_locked(&dev_priv
->dpio_lock
));
1547 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
1553 I915_WRITE(SBI_ADDR
, (reg
<< 16));
1555 if (destination
== SBI_ICLK
)
1556 value
= SBI_CTL_DEST_ICLK
| SBI_CTL_OP_CRRD
;
1558 value
= SBI_CTL_DEST_MPHY
| SBI_CTL_OP_IORD
;
1559 I915_WRITE(SBI_CTL_STAT
, value
| SBI_BUSY
);
1561 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1567 return I915_READ(SBI_DATA
);
1571 * ironlake_enable_pch_pll - enable PCH PLL
1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1578 static void ironlake_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1580 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1581 struct intel_pch_pll
*pll
;
1585 /* PCH PLLs only available on ILK, SNB and IVB */
1586 BUG_ON(dev_priv
->info
->gen
< 5);
1587 pll
= intel_crtc
->pch_pll
;
1591 if (WARN_ON(pll
->refcount
== 0))
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll
->pll_reg
, pll
->active
, pll
->on
,
1596 intel_crtc
->base
.base
.id
);
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv
);
1601 if (pll
->active
++ && pll
->on
) {
1602 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1609 val
= I915_READ(reg
);
1610 val
|= DPLL_VCO_ENABLE
;
1611 I915_WRITE(reg
, val
);
1618 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1620 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1621 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv
->info
->gen
< 5);
1630 if (WARN_ON(pll
->refcount
== 0))
1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll
->pll_reg
, pll
->active
, pll
->on
,
1635 intel_crtc
->base
.base
.id
);
1637 if (WARN_ON(pll
->active
== 0)) {
1638 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1642 if (--pll
->active
) {
1643 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1653 val
= I915_READ(reg
);
1654 val
&= ~DPLL_VCO_ENABLE
;
1655 I915_WRITE(reg
, val
);
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1665 struct drm_device
*dev
= dev_priv
->dev
;
1666 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1667 uint32_t reg
, val
, pipeconf_val
;
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv
->info
->gen
< 5);
1672 /* Make sure PCH DPLL is enabled */
1673 assert_pch_pll_enabled(dev_priv
,
1674 to_intel_crtc(crtc
)->pch_pll
,
1675 to_intel_crtc(crtc
));
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv
, pipe
);
1679 assert_fdi_rx_enabled(dev_priv
, pipe
);
1681 if (HAS_PCH_CPT(dev
)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg
= TRANS_CHICKEN2(pipe
);
1685 val
= I915_READ(reg
);
1686 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1687 I915_WRITE(reg
, val
);
1690 reg
= TRANSCONF(pipe
);
1691 val
= I915_READ(reg
);
1692 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1694 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1699 val
&= ~PIPECONF_BPC_MASK
;
1700 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1703 val
&= ~TRANS_INTERLACE_MASK
;
1704 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1705 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1706 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1707 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1709 val
|= TRANS_INTERLACED
;
1711 val
|= TRANS_PROGRESSIVE
;
1713 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1714 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1719 enum transcoder cpu_transcoder
)
1721 u32 val
, pipeconf_val
;
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv
->info
->gen
< 5);
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1728 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1730 /* Workaround: set timing override bit. */
1731 val
= I915_READ(_TRANSA_CHICKEN2
);
1732 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1733 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1736 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1738 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1739 PIPECONF_INTERLACED_ILK
)
1740 val
|= TRANS_INTERLACED
;
1742 val
|= TRANS_PROGRESSIVE
;
1744 I915_WRITE(TRANSCONF(TRANSCODER_A
), val
);
1745 if (wait_for(I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1752 struct drm_device
*dev
= dev_priv
->dev
;
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv
, pipe
);
1757 assert_fdi_rx_disabled(dev_priv
, pipe
);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv
, pipe
);
1762 reg
= TRANSCONF(pipe
);
1763 val
= I915_READ(reg
);
1764 val
&= ~TRANS_ENABLE
;
1765 I915_WRITE(reg
, val
);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1768 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1770 if (!HAS_PCH_IBX(dev
)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg
= TRANS_CHICKEN2(pipe
);
1773 val
= I915_READ(reg
);
1774 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1775 I915_WRITE(reg
, val
);
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1783 val
= I915_READ(_TRANSACONF
);
1784 val
&= ~TRANS_ENABLE
;
1785 I915_WRITE(_TRANSACONF
, val
);
1786 /* wait for PCH transcoder off, transcoder state */
1787 if (wait_for((I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
1790 /* Workaround: clear timing override bit. */
1791 val
= I915_READ(_TRANSA_CHICKEN2
);
1792 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1793 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1797 * intel_enable_pipe - enable a pipe, asserting requirements
1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1805 * @pipe should be %PIPE_A or %PIPE_B.
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1810 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1813 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1815 enum pipe pch_transcoder
;
1819 if (HAS_PCH_LPT(dev_priv
->dev
))
1820 pch_transcoder
= TRANSCODER_A
;
1822 pch_transcoder
= pipe
;
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1829 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1830 assert_pll_enabled(dev_priv
, pipe
);
1833 /* if driving the PCH, we need FDI enabled */
1834 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1835 assert_fdi_tx_pll_enabled(dev_priv
,
1836 (enum pipe
) cpu_transcoder
);
1838 /* FIXME: assert CPU port conditions for SNB+ */
1841 reg
= PIPECONF(cpu_transcoder
);
1842 val
= I915_READ(reg
);
1843 if (val
& PIPECONF_ENABLE
)
1846 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1847 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1851 * intel_disable_pipe - disable a pipe, asserting requirements
1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1858 * @pipe should be %PIPE_A or %PIPE_B.
1860 * Will wait until the pipe has shut down before returning.
1862 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1865 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1874 assert_planes_disabled(dev_priv
, pipe
);
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1880 reg
= PIPECONF(cpu_transcoder
);
1881 val
= I915_READ(reg
);
1882 if ((val
& PIPECONF_ENABLE
) == 0)
1885 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1886 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1893 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1896 if (dev_priv
->info
->gen
>= 4)
1897 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1899 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1910 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1911 enum plane plane
, enum pipe pipe
)
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv
, pipe
);
1919 reg
= DSPCNTR(plane
);
1920 val
= I915_READ(reg
);
1921 if (val
& DISPLAY_PLANE_ENABLE
)
1924 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1925 intel_flush_display_plane(dev_priv
, plane
);
1926 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1935 * Disable @plane; should be an independent operation.
1937 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1938 enum plane plane
, enum pipe pipe
)
1943 reg
= DSPCNTR(plane
);
1944 val
= I915_READ(reg
);
1945 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1948 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1949 intel_flush_display_plane(dev_priv
, plane
);
1950 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1954 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1955 struct drm_i915_gem_object
*obj
,
1956 struct intel_ring_buffer
*pipelined
)
1958 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1962 switch (obj
->tiling_mode
) {
1963 case I915_TILING_NONE
:
1964 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1965 alignment
= 128 * 1024;
1966 else if (INTEL_INFO(dev
)->gen
>= 4)
1967 alignment
= 4 * 1024;
1969 alignment
= 64 * 1024;
1972 /* pin() will align the object as required by fence */
1976 /* FIXME: Is this true? */
1977 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1983 dev_priv
->mm
.interruptible
= false;
1984 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1986 goto err_interruptible
;
1988 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1989 * fence, whereas 965+ only requires a fence if using
1990 * framebuffer compression. For simplicity, we always install
1991 * a fence as the cost is not that onerous.
1993 ret
= i915_gem_object_get_fence(obj
);
1997 i915_gem_object_pin_fence(obj
);
1999 dev_priv
->mm
.interruptible
= true;
2003 i915_gem_object_unpin(obj
);
2005 dev_priv
->mm
.interruptible
= true;
2009 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2011 i915_gem_object_unpin_fence(obj
);
2012 i915_gem_object_unpin(obj
);
2015 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2016 * is assumed to be a power-of-two. */
2017 unsigned long intel_gen4_compute_offset_xtiled(int *x
, int *y
,
2021 int tile_rows
, tiles
;
2025 tiles
= *x
/ (512/bpp
);
2028 return tile_rows
* pitch
* 8 + tiles
* 4096;
2031 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2034 struct drm_device
*dev
= crtc
->dev
;
2035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2036 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2037 struct intel_framebuffer
*intel_fb
;
2038 struct drm_i915_gem_object
*obj
;
2039 int plane
= intel_crtc
->plane
;
2040 unsigned long linear_offset
;
2049 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2053 intel_fb
= to_intel_framebuffer(fb
);
2054 obj
= intel_fb
->obj
;
2056 reg
= DSPCNTR(plane
);
2057 dspcntr
= I915_READ(reg
);
2058 /* Mask out pixel format bits in case we change it */
2059 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2060 switch (fb
->pixel_format
) {
2062 dspcntr
|= DISPPLANE_8BPP
;
2064 case DRM_FORMAT_XRGB1555
:
2065 case DRM_FORMAT_ARGB1555
:
2066 dspcntr
|= DISPPLANE_BGRX555
;
2068 case DRM_FORMAT_RGB565
:
2069 dspcntr
|= DISPPLANE_BGRX565
;
2071 case DRM_FORMAT_XRGB8888
:
2072 case DRM_FORMAT_ARGB8888
:
2073 dspcntr
|= DISPPLANE_BGRX888
;
2075 case DRM_FORMAT_XBGR8888
:
2076 case DRM_FORMAT_ABGR8888
:
2077 dspcntr
|= DISPPLANE_RGBX888
;
2079 case DRM_FORMAT_XRGB2101010
:
2080 case DRM_FORMAT_ARGB2101010
:
2081 dspcntr
|= DISPPLANE_BGRX101010
;
2083 case DRM_FORMAT_XBGR2101010
:
2084 case DRM_FORMAT_ABGR2101010
:
2085 dspcntr
|= DISPPLANE_RGBX101010
;
2088 DRM_ERROR("Unknown pixel format 0x%08x\n", fb
->pixel_format
);
2092 if (INTEL_INFO(dev
)->gen
>= 4) {
2093 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2094 dspcntr
|= DISPPLANE_TILED
;
2096 dspcntr
&= ~DISPPLANE_TILED
;
2099 I915_WRITE(reg
, dspcntr
);
2101 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2103 if (INTEL_INFO(dev
)->gen
>= 4) {
2104 intel_crtc
->dspaddr_offset
=
2105 intel_gen4_compute_offset_xtiled(&x
, &y
,
2106 fb
->bits_per_pixel
/ 8,
2108 linear_offset
-= intel_crtc
->dspaddr_offset
;
2110 intel_crtc
->dspaddr_offset
= linear_offset
;
2113 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2114 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2115 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2116 if (INTEL_INFO(dev
)->gen
>= 4) {
2117 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2118 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2119 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2120 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2122 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2128 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2129 struct drm_framebuffer
*fb
, int x
, int y
)
2131 struct drm_device
*dev
= crtc
->dev
;
2132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2133 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2134 struct intel_framebuffer
*intel_fb
;
2135 struct drm_i915_gem_object
*obj
;
2136 int plane
= intel_crtc
->plane
;
2137 unsigned long linear_offset
;
2147 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2151 intel_fb
= to_intel_framebuffer(fb
);
2152 obj
= intel_fb
->obj
;
2154 reg
= DSPCNTR(plane
);
2155 dspcntr
= I915_READ(reg
);
2156 /* Mask out pixel format bits in case we change it */
2157 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2158 switch (fb
->pixel_format
) {
2160 dspcntr
|= DISPPLANE_8BPP
;
2162 case DRM_FORMAT_RGB565
:
2163 dspcntr
|= DISPPLANE_BGRX565
;
2165 case DRM_FORMAT_XRGB8888
:
2166 case DRM_FORMAT_ARGB8888
:
2167 dspcntr
|= DISPPLANE_BGRX888
;
2169 case DRM_FORMAT_XBGR8888
:
2170 case DRM_FORMAT_ABGR8888
:
2171 dspcntr
|= DISPPLANE_RGBX888
;
2173 case DRM_FORMAT_XRGB2101010
:
2174 case DRM_FORMAT_ARGB2101010
:
2175 dspcntr
|= DISPPLANE_BGRX101010
;
2177 case DRM_FORMAT_XBGR2101010
:
2178 case DRM_FORMAT_ABGR2101010
:
2179 dspcntr
|= DISPPLANE_RGBX101010
;
2182 DRM_ERROR("Unknown pixel format 0x%08x\n", fb
->pixel_format
);
2186 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2187 dspcntr
|= DISPPLANE_TILED
;
2189 dspcntr
&= ~DISPPLANE_TILED
;
2192 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2194 I915_WRITE(reg
, dspcntr
);
2196 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2197 intel_crtc
->dspaddr_offset
=
2198 intel_gen4_compute_offset_xtiled(&x
, &y
,
2199 fb
->bits_per_pixel
/ 8,
2201 linear_offset
-= intel_crtc
->dspaddr_offset
;
2203 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2204 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2205 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2206 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2207 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2208 if (IS_HASWELL(dev
)) {
2209 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2211 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2212 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2219 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2221 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2222 int x
, int y
, enum mode_set_atomic state
)
2224 struct drm_device
*dev
= crtc
->dev
;
2225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2227 if (dev_priv
->display
.disable_fbc
)
2228 dev_priv
->display
.disable_fbc(dev
);
2229 intel_increase_pllclock(crtc
);
2231 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2234 void intel_display_handle_reset(struct drm_device
*dev
)
2236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2237 struct drm_crtc
*crtc
;
2240 * Flips in the rings have been nuked by the reset,
2241 * so complete all pending flips so that user space
2242 * will get its events and not get stuck.
2244 * Also update the base address of all primary
2245 * planes to the the last fb to make sure we're
2246 * showing the correct fb after a reset.
2248 * Need to make two loops over the crtcs so that we
2249 * don't try to grab a crtc mutex before the
2250 * pending_flip_queue really got woken up.
2253 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2254 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2255 enum plane plane
= intel_crtc
->plane
;
2257 intel_prepare_page_flip(dev
, plane
);
2258 intel_finish_page_flip_plane(dev
, plane
);
2261 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2262 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2264 mutex_lock(&crtc
->mutex
);
2265 if (intel_crtc
->active
)
2266 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2268 mutex_unlock(&crtc
->mutex
);
2273 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2275 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2276 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2277 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2280 /* Big Hammer, we also need to ensure that any pending
2281 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2282 * current scanout is retired before unpinning the old
2285 * This should only fail upon a hung GPU, in which case we
2286 * can safely continue.
2288 dev_priv
->mm
.interruptible
= false;
2289 ret
= i915_gem_object_finish_gpu(obj
);
2290 dev_priv
->mm
.interruptible
= was_interruptible
;
2295 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2297 struct drm_device
*dev
= crtc
->dev
;
2298 struct drm_i915_master_private
*master_priv
;
2299 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2301 if (!dev
->primary
->master
)
2304 master_priv
= dev
->primary
->master
->driver_priv
;
2305 if (!master_priv
->sarea_priv
)
2308 switch (intel_crtc
->pipe
) {
2310 master_priv
->sarea_priv
->pipeA_x
= x
;
2311 master_priv
->sarea_priv
->pipeA_y
= y
;
2314 master_priv
->sarea_priv
->pipeB_x
= x
;
2315 master_priv
->sarea_priv
->pipeB_y
= y
;
2323 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2324 struct drm_framebuffer
*fb
)
2326 struct drm_device
*dev
= crtc
->dev
;
2327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2328 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2329 struct drm_framebuffer
*old_fb
;
2334 DRM_ERROR("No FB bound\n");
2338 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2339 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2341 dev_priv
->num_pipe
);
2345 mutex_lock(&dev
->struct_mutex
);
2346 ret
= intel_pin_and_fence_fb_obj(dev
,
2347 to_intel_framebuffer(fb
)->obj
,
2350 mutex_unlock(&dev
->struct_mutex
);
2351 DRM_ERROR("pin & fence failed\n");
2355 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2357 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2358 mutex_unlock(&dev
->struct_mutex
);
2359 DRM_ERROR("failed to update base address\n");
2369 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2370 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2373 intel_update_fbc(dev
);
2374 mutex_unlock(&dev
->struct_mutex
);
2376 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2381 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2383 struct drm_device
*dev
= crtc
->dev
;
2384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2385 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2386 int pipe
= intel_crtc
->pipe
;
2389 /* enable normal train */
2390 reg
= FDI_TX_CTL(pipe
);
2391 temp
= I915_READ(reg
);
2392 if (IS_IVYBRIDGE(dev
)) {
2393 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2394 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2396 temp
&= ~FDI_LINK_TRAIN_NONE
;
2397 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2399 I915_WRITE(reg
, temp
);
2401 reg
= FDI_RX_CTL(pipe
);
2402 temp
= I915_READ(reg
);
2403 if (HAS_PCH_CPT(dev
)) {
2404 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2405 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2407 temp
&= ~FDI_LINK_TRAIN_NONE
;
2408 temp
|= FDI_LINK_TRAIN_NONE
;
2410 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2412 /* wait one idle pattern time */
2416 /* IVB wants error correction enabled */
2417 if (IS_IVYBRIDGE(dev
))
2418 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2419 FDI_FE_ERRC_ENABLE
);
2422 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2425 struct intel_crtc
*pipe_B_crtc
=
2426 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2427 struct intel_crtc
*pipe_C_crtc
=
2428 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2431 /* When everything is off disable fdi C so that we could enable fdi B
2432 * with all lanes. XXX: This misses the case where a pipe is not using
2433 * any pch resources and so doesn't need any fdi lanes. */
2434 if (!pipe_B_crtc
->base
.enabled
&& !pipe_C_crtc
->base
.enabled
) {
2435 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2436 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2438 temp
= I915_READ(SOUTH_CHICKEN1
);
2439 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2440 DRM_DEBUG_KMS("disabling fdi C rx\n");
2441 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2445 /* The FDI link training functions for ILK/Ibexpeak. */
2446 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2448 struct drm_device
*dev
= crtc
->dev
;
2449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2450 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2451 int pipe
= intel_crtc
->pipe
;
2452 int plane
= intel_crtc
->plane
;
2453 u32 reg
, temp
, tries
;
2455 /* FDI needs bits from pipe & plane first */
2456 assert_pipe_enabled(dev_priv
, pipe
);
2457 assert_plane_enabled(dev_priv
, plane
);
2459 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2461 reg
= FDI_RX_IMR(pipe
);
2462 temp
= I915_READ(reg
);
2463 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2464 temp
&= ~FDI_RX_BIT_LOCK
;
2465 I915_WRITE(reg
, temp
);
2469 /* enable CPU FDI TX and PCH FDI RX */
2470 reg
= FDI_TX_CTL(pipe
);
2471 temp
= I915_READ(reg
);
2473 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2474 temp
&= ~FDI_LINK_TRAIN_NONE
;
2475 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2476 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2478 reg
= FDI_RX_CTL(pipe
);
2479 temp
= I915_READ(reg
);
2480 temp
&= ~FDI_LINK_TRAIN_NONE
;
2481 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2482 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2487 /* Ironlake workaround, enable clock pointer after FDI enable*/
2488 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2489 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2490 FDI_RX_PHASE_SYNC_POINTER_EN
);
2492 reg
= FDI_RX_IIR(pipe
);
2493 for (tries
= 0; tries
< 5; tries
++) {
2494 temp
= I915_READ(reg
);
2495 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2497 if ((temp
& FDI_RX_BIT_LOCK
)) {
2498 DRM_DEBUG_KMS("FDI train 1 done.\n");
2499 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2504 DRM_ERROR("FDI train 1 fail!\n");
2507 reg
= FDI_TX_CTL(pipe
);
2508 temp
= I915_READ(reg
);
2509 temp
&= ~FDI_LINK_TRAIN_NONE
;
2510 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2511 I915_WRITE(reg
, temp
);
2513 reg
= FDI_RX_CTL(pipe
);
2514 temp
= I915_READ(reg
);
2515 temp
&= ~FDI_LINK_TRAIN_NONE
;
2516 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2517 I915_WRITE(reg
, temp
);
2522 reg
= FDI_RX_IIR(pipe
);
2523 for (tries
= 0; tries
< 5; tries
++) {
2524 temp
= I915_READ(reg
);
2525 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2527 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2528 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2529 DRM_DEBUG_KMS("FDI train 2 done.\n");
2534 DRM_ERROR("FDI train 2 fail!\n");
2536 DRM_DEBUG_KMS("FDI train done\n");
2540 static const int snb_b_fdi_train_param
[] = {
2541 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2542 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2543 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2544 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2547 /* The FDI link training functions for SNB/Cougarpoint. */
2548 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2550 struct drm_device
*dev
= crtc
->dev
;
2551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2552 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2553 int pipe
= intel_crtc
->pipe
;
2554 u32 reg
, temp
, i
, retry
;
2556 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2558 reg
= FDI_RX_IMR(pipe
);
2559 temp
= I915_READ(reg
);
2560 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2561 temp
&= ~FDI_RX_BIT_LOCK
;
2562 I915_WRITE(reg
, temp
);
2567 /* enable CPU FDI TX and PCH FDI RX */
2568 reg
= FDI_TX_CTL(pipe
);
2569 temp
= I915_READ(reg
);
2571 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2572 temp
&= ~FDI_LINK_TRAIN_NONE
;
2573 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2574 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2576 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2577 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2579 I915_WRITE(FDI_RX_MISC(pipe
),
2580 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2582 reg
= FDI_RX_CTL(pipe
);
2583 temp
= I915_READ(reg
);
2584 if (HAS_PCH_CPT(dev
)) {
2585 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2586 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2588 temp
&= ~FDI_LINK_TRAIN_NONE
;
2589 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2591 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2596 for (i
= 0; i
< 4; i
++) {
2597 reg
= FDI_TX_CTL(pipe
);
2598 temp
= I915_READ(reg
);
2599 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2600 temp
|= snb_b_fdi_train_param
[i
];
2601 I915_WRITE(reg
, temp
);
2606 for (retry
= 0; retry
< 5; retry
++) {
2607 reg
= FDI_RX_IIR(pipe
);
2608 temp
= I915_READ(reg
);
2609 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2610 if (temp
& FDI_RX_BIT_LOCK
) {
2611 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2612 DRM_DEBUG_KMS("FDI train 1 done.\n");
2621 DRM_ERROR("FDI train 1 fail!\n");
2624 reg
= FDI_TX_CTL(pipe
);
2625 temp
= I915_READ(reg
);
2626 temp
&= ~FDI_LINK_TRAIN_NONE
;
2627 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2629 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2631 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2633 I915_WRITE(reg
, temp
);
2635 reg
= FDI_RX_CTL(pipe
);
2636 temp
= I915_READ(reg
);
2637 if (HAS_PCH_CPT(dev
)) {
2638 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2639 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2641 temp
&= ~FDI_LINK_TRAIN_NONE
;
2642 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2644 I915_WRITE(reg
, temp
);
2649 for (i
= 0; i
< 4; i
++) {
2650 reg
= FDI_TX_CTL(pipe
);
2651 temp
= I915_READ(reg
);
2652 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2653 temp
|= snb_b_fdi_train_param
[i
];
2654 I915_WRITE(reg
, temp
);
2659 for (retry
= 0; retry
< 5; retry
++) {
2660 reg
= FDI_RX_IIR(pipe
);
2661 temp
= I915_READ(reg
);
2662 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2663 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2664 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2665 DRM_DEBUG_KMS("FDI train 2 done.\n");
2674 DRM_ERROR("FDI train 2 fail!\n");
2676 DRM_DEBUG_KMS("FDI train done.\n");
2679 /* Manual link training for Ivy Bridge A0 parts */
2680 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2682 struct drm_device
*dev
= crtc
->dev
;
2683 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2684 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2685 int pipe
= intel_crtc
->pipe
;
2688 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2690 reg
= FDI_RX_IMR(pipe
);
2691 temp
= I915_READ(reg
);
2692 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2693 temp
&= ~FDI_RX_BIT_LOCK
;
2694 I915_WRITE(reg
, temp
);
2699 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2700 I915_READ(FDI_RX_IIR(pipe
)));
2702 /* enable CPU FDI TX and PCH FDI RX */
2703 reg
= FDI_TX_CTL(pipe
);
2704 temp
= I915_READ(reg
);
2706 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2707 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2708 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2709 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2710 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2711 temp
|= FDI_COMPOSITE_SYNC
;
2712 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2714 I915_WRITE(FDI_RX_MISC(pipe
),
2715 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2717 reg
= FDI_RX_CTL(pipe
);
2718 temp
= I915_READ(reg
);
2719 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2720 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2721 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2722 temp
|= FDI_COMPOSITE_SYNC
;
2723 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2728 for (i
= 0; i
< 4; i
++) {
2729 reg
= FDI_TX_CTL(pipe
);
2730 temp
= I915_READ(reg
);
2731 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2732 temp
|= snb_b_fdi_train_param
[i
];
2733 I915_WRITE(reg
, temp
);
2738 reg
= FDI_RX_IIR(pipe
);
2739 temp
= I915_READ(reg
);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2742 if (temp
& FDI_RX_BIT_LOCK
||
2743 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2744 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2745 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2750 DRM_ERROR("FDI train 1 fail!\n");
2753 reg
= FDI_TX_CTL(pipe
);
2754 temp
= I915_READ(reg
);
2755 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2756 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2757 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2758 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2759 I915_WRITE(reg
, temp
);
2761 reg
= FDI_RX_CTL(pipe
);
2762 temp
= I915_READ(reg
);
2763 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2764 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2765 I915_WRITE(reg
, temp
);
2770 for (i
= 0; i
< 4; i
++) {
2771 reg
= FDI_TX_CTL(pipe
);
2772 temp
= I915_READ(reg
);
2773 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2774 temp
|= snb_b_fdi_train_param
[i
];
2775 I915_WRITE(reg
, temp
);
2780 reg
= FDI_RX_IIR(pipe
);
2781 temp
= I915_READ(reg
);
2782 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2784 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2785 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2786 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2791 DRM_ERROR("FDI train 2 fail!\n");
2793 DRM_DEBUG_KMS("FDI train done.\n");
2796 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2798 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2800 int pipe
= intel_crtc
->pipe
;
2804 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2805 reg
= FDI_RX_CTL(pipe
);
2806 temp
= I915_READ(reg
);
2807 temp
&= ~((0x7 << 19) | (0x7 << 16));
2808 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2809 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2810 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2815 /* Switch from Rawclk to PCDclk */
2816 temp
= I915_READ(reg
);
2817 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2822 /* Enable CPU FDI TX PLL, always on for Ironlake */
2823 reg
= FDI_TX_CTL(pipe
);
2824 temp
= I915_READ(reg
);
2825 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2826 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2833 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2835 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2837 int pipe
= intel_crtc
->pipe
;
2840 /* Switch from PCDclk to Rawclk */
2841 reg
= FDI_RX_CTL(pipe
);
2842 temp
= I915_READ(reg
);
2843 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2845 /* Disable CPU FDI TX PLL */
2846 reg
= FDI_TX_CTL(pipe
);
2847 temp
= I915_READ(reg
);
2848 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2853 reg
= FDI_RX_CTL(pipe
);
2854 temp
= I915_READ(reg
);
2855 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2857 /* Wait for the clocks to turn off. */
2862 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2864 struct drm_device
*dev
= crtc
->dev
;
2865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2866 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2867 int pipe
= intel_crtc
->pipe
;
2870 /* disable CPU FDI tx and PCH FDI rx */
2871 reg
= FDI_TX_CTL(pipe
);
2872 temp
= I915_READ(reg
);
2873 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2876 reg
= FDI_RX_CTL(pipe
);
2877 temp
= I915_READ(reg
);
2878 temp
&= ~(0x7 << 16);
2879 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2880 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2885 /* Ironlake workaround, disable clock pointer after downing FDI */
2886 if (HAS_PCH_IBX(dev
)) {
2887 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2890 /* still set train pattern 1 */
2891 reg
= FDI_TX_CTL(pipe
);
2892 temp
= I915_READ(reg
);
2893 temp
&= ~FDI_LINK_TRAIN_NONE
;
2894 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2895 I915_WRITE(reg
, temp
);
2897 reg
= FDI_RX_CTL(pipe
);
2898 temp
= I915_READ(reg
);
2899 if (HAS_PCH_CPT(dev
)) {
2900 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2901 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2903 temp
&= ~FDI_LINK_TRAIN_NONE
;
2904 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2906 /* BPC in FDI rx is consistent with that in PIPECONF */
2907 temp
&= ~(0x07 << 16);
2908 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2909 I915_WRITE(reg
, temp
);
2915 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2917 struct drm_device
*dev
= crtc
->dev
;
2918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2919 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2920 unsigned long flags
;
2923 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2924 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2927 spin_lock_irqsave(&dev
->event_lock
, flags
);
2928 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2929 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2934 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2936 struct drm_device
*dev
= crtc
->dev
;
2937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2939 if (crtc
->fb
== NULL
)
2942 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2944 wait_event(dev_priv
->pending_flip_queue
,
2945 !intel_crtc_has_pending_flip(crtc
));
2947 mutex_lock(&dev
->struct_mutex
);
2948 intel_finish_fb(crtc
->fb
);
2949 mutex_unlock(&dev
->struct_mutex
);
2952 static bool ironlake_crtc_driving_pch(struct drm_crtc
*crtc
)
2954 struct drm_device
*dev
= crtc
->dev
;
2955 struct intel_encoder
*intel_encoder
;
2958 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2959 * must be driven by its own crtc; no sharing is possible.
2961 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2962 switch (intel_encoder
->type
) {
2963 case INTEL_OUTPUT_EDP
:
2964 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
2973 static bool haswell_crtc_driving_pch(struct drm_crtc
*crtc
)
2975 return intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
);
2978 /* Program iCLKIP clock to the desired frequency */
2979 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2981 struct drm_device
*dev
= crtc
->dev
;
2982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2983 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2986 mutex_lock(&dev_priv
->dpio_lock
);
2988 /* It is necessary to ungate the pixclk gate prior to programming
2989 * the divisors, and gate it back when it is done.
2991 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2993 /* Disable SSCCTL */
2994 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2995 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2999 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3000 if (crtc
->mode
.clock
== 20000) {
3005 /* The iCLK virtual clock root frequency is in MHz,
3006 * but the crtc->mode.clock in in KHz. To get the divisors,
3007 * it is necessary to divide one by another, so we
3008 * convert the virtual clock precision to KHz here for higher
3011 u32 iclk_virtual_root_freq
= 172800 * 1000;
3012 u32 iclk_pi_range
= 64;
3013 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3015 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
3016 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3017 pi_value
= desired_divisor
% iclk_pi_range
;
3020 divsel
= msb_divisor_value
- 2;
3021 phaseinc
= pi_value
;
3024 /* This should not happen with any sane values */
3025 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3026 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3027 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3028 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3030 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3037 /* Program SSCDIVINTPHASE6 */
3038 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3039 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3040 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3041 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3042 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3043 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3044 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3045 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3047 /* Program SSCAUXDIV */
3048 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3049 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3050 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3051 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3053 /* Enable modulator and associated divider */
3054 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3055 temp
&= ~SBI_SSCCTL_DISABLE
;
3056 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3058 /* Wait for initialization time */
3061 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3063 mutex_unlock(&dev_priv
->dpio_lock
);
3067 * Enable PCH resources required for PCH ports:
3069 * - FDI training & RX/TX
3070 * - update transcoder timings
3071 * - DP transcoding bits
3074 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3076 struct drm_device
*dev
= crtc
->dev
;
3077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3078 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3079 int pipe
= intel_crtc
->pipe
;
3082 assert_transcoder_disabled(dev_priv
, pipe
);
3084 /* Write the TU size bits before fdi link training, so that error
3085 * detection works. */
3086 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3087 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3089 /* For PCH output, training FDI link */
3090 dev_priv
->display
.fdi_link_train(crtc
);
3092 /* XXX: pch pll's can be enabled any time before we enable the PCH
3093 * transcoder, and we actually should do this to not upset any PCH
3094 * transcoder that already use the clock when we share it.
3096 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3097 * unconditionally resets the pll - we need that to have the right LVDS
3098 * enable sequence. */
3099 ironlake_enable_pch_pll(intel_crtc
);
3101 if (HAS_PCH_CPT(dev
)) {
3104 temp
= I915_READ(PCH_DPLL_SEL
);
3108 temp
|= TRANSA_DPLL_ENABLE
;
3109 sel
= TRANSA_DPLLB_SEL
;
3112 temp
|= TRANSB_DPLL_ENABLE
;
3113 sel
= TRANSB_DPLLB_SEL
;
3116 temp
|= TRANSC_DPLL_ENABLE
;
3117 sel
= TRANSC_DPLLB_SEL
;
3120 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3124 I915_WRITE(PCH_DPLL_SEL
, temp
);
3127 /* set transcoder timing, panel must allow it */
3128 assert_panel_unlocked(dev_priv
, pipe
);
3129 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3130 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3131 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3133 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3134 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3135 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3136 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3138 intel_fdi_normal_train(crtc
);
3140 /* For PCH DP, enable TRANS_DP_CTL */
3141 if (HAS_PCH_CPT(dev
) &&
3142 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3143 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3144 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3145 reg
= TRANS_DP_CTL(pipe
);
3146 temp
= I915_READ(reg
);
3147 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3148 TRANS_DP_SYNC_MASK
|
3150 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3151 TRANS_DP_ENH_FRAMING
);
3152 temp
|= bpc
<< 9; /* same format but at 11:9 */
3154 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3155 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3156 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3157 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3159 switch (intel_trans_dp_port_sel(crtc
)) {
3161 temp
|= TRANS_DP_PORT_SEL_B
;
3164 temp
|= TRANS_DP_PORT_SEL_C
;
3167 temp
|= TRANS_DP_PORT_SEL_D
;
3173 I915_WRITE(reg
, temp
);
3176 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3179 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3181 struct drm_device
*dev
= crtc
->dev
;
3182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3183 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3184 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3186 assert_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3188 lpt_program_iclkip(crtc
);
3190 /* Set transcoder timing. */
3191 I915_WRITE(_TRANS_HTOTAL_A
, I915_READ(HTOTAL(cpu_transcoder
)));
3192 I915_WRITE(_TRANS_HBLANK_A
, I915_READ(HBLANK(cpu_transcoder
)));
3193 I915_WRITE(_TRANS_HSYNC_A
, I915_READ(HSYNC(cpu_transcoder
)));
3195 I915_WRITE(_TRANS_VTOTAL_A
, I915_READ(VTOTAL(cpu_transcoder
)));
3196 I915_WRITE(_TRANS_VBLANK_A
, I915_READ(VBLANK(cpu_transcoder
)));
3197 I915_WRITE(_TRANS_VSYNC_A
, I915_READ(VSYNC(cpu_transcoder
)));
3198 I915_WRITE(_TRANS_VSYNCSHIFT_A
, I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3200 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3203 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3205 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3210 if (pll
->refcount
== 0) {
3211 WARN(1, "bad PCH PLL refcount\n");
3216 intel_crtc
->pch_pll
= NULL
;
3219 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3221 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3222 struct intel_pch_pll
*pll
;
3225 pll
= intel_crtc
->pch_pll
;
3227 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3228 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3232 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3233 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3234 i
= intel_crtc
->pipe
;
3235 pll
= &dev_priv
->pch_plls
[i
];
3237 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3238 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3243 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3244 pll
= &dev_priv
->pch_plls
[i
];
3246 /* Only want to check enabled timings first */
3247 if (pll
->refcount
== 0)
3250 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3251 fp
== I915_READ(pll
->fp0_reg
)) {
3252 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3253 intel_crtc
->base
.base
.id
,
3254 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3260 /* Ok no matching timings, maybe there's a free one? */
3261 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3262 pll
= &dev_priv
->pch_plls
[i
];
3263 if (pll
->refcount
== 0) {
3264 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3265 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3273 intel_crtc
->pch_pll
= pll
;
3275 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3276 prepare
: /* separate function? */
3277 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3279 /* Wait for the clocks to stabilize before rewriting the regs */
3280 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3281 POSTING_READ(pll
->pll_reg
);
3284 I915_WRITE(pll
->fp0_reg
, fp
);
3285 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3290 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3293 int dslreg
= PIPEDSL(pipe
);
3296 temp
= I915_READ(dslreg
);
3298 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3299 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3300 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3304 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3306 struct drm_device
*dev
= crtc
->dev
;
3307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3309 struct intel_encoder
*encoder
;
3310 int pipe
= intel_crtc
->pipe
;
3311 int plane
= intel_crtc
->plane
;
3315 WARN_ON(!crtc
->enabled
);
3317 if (intel_crtc
->active
)
3320 intel_crtc
->active
= true;
3321 intel_update_watermarks(dev
);
3323 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3324 temp
= I915_READ(PCH_LVDS
);
3325 if ((temp
& LVDS_PORT_EN
) == 0)
3326 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3329 is_pch_port
= ironlake_crtc_driving_pch(crtc
);
3332 /* Note: FDI PLL enabling _must_ be done before we enable the
3333 * cpu pipes, hence this is separate from all the other fdi/pch
3335 ironlake_fdi_pll_enable(intel_crtc
);
3337 assert_fdi_tx_disabled(dev_priv
, pipe
);
3338 assert_fdi_rx_disabled(dev_priv
, pipe
);
3341 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3342 if (encoder
->pre_enable
)
3343 encoder
->pre_enable(encoder
);
3345 /* Enable panel fitting for LVDS */
3346 if (dev_priv
->pch_pf_size
&&
3347 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3348 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3349 /* Force use of hard-coded filter coefficients
3350 * as some pre-programmed values are broken,
3353 if (IS_IVYBRIDGE(dev
))
3354 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3355 PF_PIPE_SEL_IVB(pipe
));
3357 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3358 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3359 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3363 * On ILK+ LUT must be loaded before the pipe is running but with
3366 intel_crtc_load_lut(crtc
);
3368 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3369 intel_enable_plane(dev_priv
, plane
, pipe
);
3372 ironlake_pch_enable(crtc
);
3374 mutex_lock(&dev
->struct_mutex
);
3375 intel_update_fbc(dev
);
3376 mutex_unlock(&dev
->struct_mutex
);
3378 intel_crtc_update_cursor(crtc
, true);
3380 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3381 encoder
->enable(encoder
);
3383 if (HAS_PCH_CPT(dev
))
3384 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3387 * There seems to be a race in PCH platform hw (at least on some
3388 * outputs) where an enabled pipe still completes any pageflip right
3389 * away (as if the pipe is off) instead of waiting for vblank. As soon
3390 * as the first vblank happend, everything works as expected. Hence just
3391 * wait for one vblank before returning to avoid strange things
3394 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3397 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3399 struct drm_device
*dev
= crtc
->dev
;
3400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3401 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3402 struct intel_encoder
*encoder
;
3403 int pipe
= intel_crtc
->pipe
;
3404 int plane
= intel_crtc
->plane
;
3407 WARN_ON(!crtc
->enabled
);
3409 if (intel_crtc
->active
)
3412 intel_crtc
->active
= true;
3413 intel_update_watermarks(dev
);
3415 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3418 dev_priv
->display
.fdi_link_train(crtc
);
3420 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3421 if (encoder
->pre_enable
)
3422 encoder
->pre_enable(encoder
);
3424 intel_ddi_enable_pipe_clock(intel_crtc
);
3426 /* Enable panel fitting for eDP */
3427 if (dev_priv
->pch_pf_size
&&
3428 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3429 /* Force use of hard-coded filter coefficients
3430 * as some pre-programmed values are broken,
3433 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3434 PF_PIPE_SEL_IVB(pipe
));
3435 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3436 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3440 * On ILK+ LUT must be loaded before the pipe is running but with
3443 intel_crtc_load_lut(crtc
);
3445 intel_ddi_set_pipe_settings(crtc
);
3446 intel_ddi_enable_pipe_func(crtc
);
3448 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3449 intel_enable_plane(dev_priv
, plane
, pipe
);
3452 lpt_pch_enable(crtc
);
3454 mutex_lock(&dev
->struct_mutex
);
3455 intel_update_fbc(dev
);
3456 mutex_unlock(&dev
->struct_mutex
);
3458 intel_crtc_update_cursor(crtc
, true);
3460 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3461 encoder
->enable(encoder
);
3464 * There seems to be a race in PCH platform hw (at least on some
3465 * outputs) where an enabled pipe still completes any pageflip right
3466 * away (as if the pipe is off) instead of waiting for vblank. As soon
3467 * as the first vblank happend, everything works as expected. Hence just
3468 * wait for one vblank before returning to avoid strange things
3471 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3474 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3476 struct drm_device
*dev
= crtc
->dev
;
3477 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3478 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3479 struct intel_encoder
*encoder
;
3480 int pipe
= intel_crtc
->pipe
;
3481 int plane
= intel_crtc
->plane
;
3485 if (!intel_crtc
->active
)
3488 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3489 encoder
->disable(encoder
);
3491 intel_crtc_wait_for_pending_flips(crtc
);
3492 drm_vblank_off(dev
, pipe
);
3493 intel_crtc_update_cursor(crtc
, false);
3495 intel_disable_plane(dev_priv
, plane
, pipe
);
3497 if (dev_priv
->cfb_plane
== plane
)
3498 intel_disable_fbc(dev
);
3500 intel_disable_pipe(dev_priv
, pipe
);
3503 I915_WRITE(PF_CTL(pipe
), 0);
3504 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3506 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3507 if (encoder
->post_disable
)
3508 encoder
->post_disable(encoder
);
3510 ironlake_fdi_disable(crtc
);
3512 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3514 if (HAS_PCH_CPT(dev
)) {
3515 /* disable TRANS_DP_CTL */
3516 reg
= TRANS_DP_CTL(pipe
);
3517 temp
= I915_READ(reg
);
3518 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3519 temp
|= TRANS_DP_PORT_SEL_NONE
;
3520 I915_WRITE(reg
, temp
);
3522 /* disable DPLL_SEL */
3523 temp
= I915_READ(PCH_DPLL_SEL
);
3526 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3529 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3532 /* C shares PLL A or B */
3533 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3538 I915_WRITE(PCH_DPLL_SEL
, temp
);
3541 /* disable PCH DPLL */
3542 intel_disable_pch_pll(intel_crtc
);
3544 ironlake_fdi_pll_disable(intel_crtc
);
3546 intel_crtc
->active
= false;
3547 intel_update_watermarks(dev
);
3549 mutex_lock(&dev
->struct_mutex
);
3550 intel_update_fbc(dev
);
3551 mutex_unlock(&dev
->struct_mutex
);
3554 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3556 struct drm_device
*dev
= crtc
->dev
;
3557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3558 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3559 struct intel_encoder
*encoder
;
3560 int pipe
= intel_crtc
->pipe
;
3561 int plane
= intel_crtc
->plane
;
3562 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3565 if (!intel_crtc
->active
)
3568 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3570 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3571 encoder
->disable(encoder
);
3573 intel_crtc_wait_for_pending_flips(crtc
);
3574 drm_vblank_off(dev
, pipe
);
3575 intel_crtc_update_cursor(crtc
, false);
3577 intel_disable_plane(dev_priv
, plane
, pipe
);
3579 if (dev_priv
->cfb_plane
== plane
)
3580 intel_disable_fbc(dev
);
3582 intel_disable_pipe(dev_priv
, pipe
);
3584 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3587 I915_WRITE(PF_CTL(pipe
), 0);
3588 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3590 intel_ddi_disable_pipe_clock(intel_crtc
);
3592 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3593 if (encoder
->post_disable
)
3594 encoder
->post_disable(encoder
);
3597 lpt_disable_pch_transcoder(dev_priv
);
3598 intel_ddi_fdi_disable(crtc
);
3601 intel_crtc
->active
= false;
3602 intel_update_watermarks(dev
);
3604 mutex_lock(&dev
->struct_mutex
);
3605 intel_update_fbc(dev
);
3606 mutex_unlock(&dev
->struct_mutex
);
3609 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3611 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3612 intel_put_pch_pll(intel_crtc
);
3615 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3617 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3619 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3620 * start using it. */
3621 intel_crtc
->cpu_transcoder
= (enum transcoder
) intel_crtc
->pipe
;
3623 intel_ddi_put_crtc_pll(crtc
);
3626 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3628 if (!enable
&& intel_crtc
->overlay
) {
3629 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3632 mutex_lock(&dev
->struct_mutex
);
3633 dev_priv
->mm
.interruptible
= false;
3634 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3635 dev_priv
->mm
.interruptible
= true;
3636 mutex_unlock(&dev
->struct_mutex
);
3639 /* Let userspace switch the overlay on again. In most cases userspace
3640 * has to recompute where to put it anyway.
3644 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3646 struct drm_device
*dev
= crtc
->dev
;
3647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3648 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3649 struct intel_encoder
*encoder
;
3650 int pipe
= intel_crtc
->pipe
;
3651 int plane
= intel_crtc
->plane
;
3653 WARN_ON(!crtc
->enabled
);
3655 if (intel_crtc
->active
)
3658 intel_crtc
->active
= true;
3659 intel_update_watermarks(dev
);
3661 intel_enable_pll(dev_priv
, pipe
);
3663 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3664 if (encoder
->pre_enable
)
3665 encoder
->pre_enable(encoder
);
3667 intel_enable_pipe(dev_priv
, pipe
, false);
3668 intel_enable_plane(dev_priv
, plane
, pipe
);
3670 intel_crtc_load_lut(crtc
);
3671 intel_update_fbc(dev
);
3673 /* Give the overlay scaler a chance to enable if it's on this pipe */
3674 intel_crtc_dpms_overlay(intel_crtc
, true);
3675 intel_crtc_update_cursor(crtc
, true);
3677 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3678 encoder
->enable(encoder
);
3681 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3683 struct drm_device
*dev
= crtc
->dev
;
3684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3685 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3686 struct intel_encoder
*encoder
;
3687 int pipe
= intel_crtc
->pipe
;
3688 int plane
= intel_crtc
->plane
;
3692 if (!intel_crtc
->active
)
3695 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3696 encoder
->disable(encoder
);
3698 /* Give the overlay scaler a chance to disable if it's on this pipe */
3699 intel_crtc_wait_for_pending_flips(crtc
);
3700 drm_vblank_off(dev
, pipe
);
3701 intel_crtc_dpms_overlay(intel_crtc
, false);
3702 intel_crtc_update_cursor(crtc
, false);
3704 if (dev_priv
->cfb_plane
== plane
)
3705 intel_disable_fbc(dev
);
3707 intel_disable_plane(dev_priv
, plane
, pipe
);
3708 intel_disable_pipe(dev_priv
, pipe
);
3710 /* Disable pannel fitter if it is on this pipe. */
3711 pctl
= I915_READ(PFIT_CONTROL
);
3712 if ((pctl
& PFIT_ENABLE
) &&
3713 ((pctl
& PFIT_PIPE_MASK
) >> PFIT_PIPE_SHIFT
) == pipe
)
3714 I915_WRITE(PFIT_CONTROL
, 0);
3716 intel_disable_pll(dev_priv
, pipe
);
3718 intel_crtc
->active
= false;
3719 intel_update_fbc(dev
);
3720 intel_update_watermarks(dev
);
3723 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3727 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3730 struct drm_device
*dev
= crtc
->dev
;
3731 struct drm_i915_master_private
*master_priv
;
3732 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3733 int pipe
= intel_crtc
->pipe
;
3735 if (!dev
->primary
->master
)
3738 master_priv
= dev
->primary
->master
->driver_priv
;
3739 if (!master_priv
->sarea_priv
)
3744 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3745 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3748 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3749 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3752 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3758 * Sets the power management mode of the pipe and plane.
3760 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3762 struct drm_device
*dev
= crtc
->dev
;
3763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3764 struct intel_encoder
*intel_encoder
;
3765 bool enable
= false;
3767 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3768 enable
|= intel_encoder
->connectors_active
;
3771 dev_priv
->display
.crtc_enable(crtc
);
3773 dev_priv
->display
.crtc_disable(crtc
);
3775 intel_crtc_update_sarea(crtc
, enable
);
3778 static void intel_crtc_noop(struct drm_crtc
*crtc
)
3782 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3784 struct drm_device
*dev
= crtc
->dev
;
3785 struct drm_connector
*connector
;
3786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3787 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3789 /* crtc should still be enabled when we disable it. */
3790 WARN_ON(!crtc
->enabled
);
3792 intel_crtc
->eld_vld
= false;
3793 dev_priv
->display
.crtc_disable(crtc
);
3794 intel_crtc_update_sarea(crtc
, false);
3795 dev_priv
->display
.off(crtc
);
3797 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3798 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3801 mutex_lock(&dev
->struct_mutex
);
3802 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3803 mutex_unlock(&dev
->struct_mutex
);
3807 /* Update computed state. */
3808 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3809 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3812 if (connector
->encoder
->crtc
!= crtc
)
3815 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3816 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3820 void intel_modeset_disable(struct drm_device
*dev
)
3822 struct drm_crtc
*crtc
;
3824 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3826 intel_crtc_disable(crtc
);
3830 void intel_encoder_noop(struct drm_encoder
*encoder
)
3834 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3836 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3838 drm_encoder_cleanup(encoder
);
3839 kfree(intel_encoder
);
3842 /* Simple dpms helper for encodres with just one connector, no cloning and only
3843 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3844 * state of the entire output pipe. */
3845 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3847 if (mode
== DRM_MODE_DPMS_ON
) {
3848 encoder
->connectors_active
= true;
3850 intel_crtc_update_dpms(encoder
->base
.crtc
);
3852 encoder
->connectors_active
= false;
3854 intel_crtc_update_dpms(encoder
->base
.crtc
);
3858 /* Cross check the actual hw state with our own modeset state tracking (and it's
3859 * internal consistency). */
3860 static void intel_connector_check_state(struct intel_connector
*connector
)
3862 if (connector
->get_hw_state(connector
)) {
3863 struct intel_encoder
*encoder
= connector
->encoder
;
3864 struct drm_crtc
*crtc
;
3865 bool encoder_enabled
;
3868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3869 connector
->base
.base
.id
,
3870 drm_get_connector_name(&connector
->base
));
3872 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3873 "wrong connector dpms state\n");
3874 WARN(connector
->base
.encoder
!= &encoder
->base
,
3875 "active connector not linked to encoder\n");
3876 WARN(!encoder
->connectors_active
,
3877 "encoder->connectors_active not set\n");
3879 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3880 WARN(!encoder_enabled
, "encoder not enabled\n");
3881 if (WARN_ON(!encoder
->base
.crtc
))
3884 crtc
= encoder
->base
.crtc
;
3886 WARN(!crtc
->enabled
, "crtc not enabled\n");
3887 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3888 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3889 "encoder active on the wrong pipe\n");
3893 /* Even simpler default implementation, if there's really no special case to
3895 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3897 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3899 /* All the simple cases only support two dpms states. */
3900 if (mode
!= DRM_MODE_DPMS_ON
)
3901 mode
= DRM_MODE_DPMS_OFF
;
3903 if (mode
== connector
->dpms
)
3906 connector
->dpms
= mode
;
3908 /* Only need to change hw state when actually enabled */
3909 if (encoder
->base
.crtc
)
3910 intel_encoder_dpms(encoder
, mode
);
3912 WARN_ON(encoder
->connectors_active
!= false);
3914 intel_modeset_check_state(connector
->dev
);
3917 /* Simple connector->get_hw_state implementation for encoders that support only
3918 * one connector and no cloning and hence the encoder state determines the state
3919 * of the connector. */
3920 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3923 struct intel_encoder
*encoder
= connector
->encoder
;
3925 return encoder
->get_hw_state(encoder
, &pipe
);
3928 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3929 const struct drm_display_mode
*mode
,
3930 struct drm_display_mode
*adjusted_mode
)
3932 struct drm_device
*dev
= crtc
->dev
;
3934 if (HAS_PCH_SPLIT(dev
)) {
3935 /* FDI link clock is fixed at 2.7G */
3936 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3940 /* All interlaced capable intel hw wants timings in frames. Note though
3941 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3942 * timings, so we need to be careful not to clobber these.*/
3943 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3944 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3946 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3947 * with a hsync front porch of 0.
3949 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3950 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3956 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3958 return 400000; /* FIXME */
3961 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3966 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3971 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3976 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3980 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3982 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3985 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3986 case GC_DISPLAY_CLOCK_333_MHZ
:
3989 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3995 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4000 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4003 /* Assume that the hardware is in the high speed state. This
4004 * should be the default.
4006 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4007 case GC_CLOCK_133_200
:
4008 case GC_CLOCK_100_200
:
4010 case GC_CLOCK_166_250
:
4012 case GC_CLOCK_100_133
:
4016 /* Shouldn't happen */
4020 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4026 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
4028 while (*num
> 0xffffff || *den
> 0xffffff) {
4035 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4036 int pixel_clock
, int link_clock
,
4037 struct intel_link_m_n
*m_n
)
4040 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
4041 m_n
->gmch_n
= link_clock
* nlanes
* 8;
4042 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
4043 m_n
->link_m
= pixel_clock
;
4044 m_n
->link_n
= link_clock
;
4045 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
4048 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4050 if (i915_panel_use_ssc
>= 0)
4051 return i915_panel_use_ssc
!= 0;
4052 return dev_priv
->lvds_use_ssc
4053 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4057 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4058 * @crtc: CRTC structure
4059 * @mode: requested mode
4061 * A pipe may be connected to one or more outputs. Based on the depth of the
4062 * attached framebuffer, choose a good color depth to use on the pipe.
4064 * If possible, match the pipe depth to the fb depth. In some cases, this
4065 * isn't ideal, because the connected output supports a lesser or restricted
4066 * set of depths. Resolve that here:
4067 * LVDS typically supports only 6bpc, so clamp down in that case
4068 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4069 * Displays may support a restricted set as well, check EDID and clamp as
4071 * DP may want to dither down to 6bpc to fit larger modes
4074 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4075 * true if they don't match).
4077 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
4078 struct drm_framebuffer
*fb
,
4079 unsigned int *pipe_bpp
,
4080 struct drm_display_mode
*mode
)
4082 struct drm_device
*dev
= crtc
->dev
;
4083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4084 struct drm_connector
*connector
;
4085 struct intel_encoder
*intel_encoder
;
4086 unsigned int display_bpc
= UINT_MAX
, bpc
;
4088 /* Walk the encoders & connectors on this crtc, get min bpc */
4089 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4091 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
4092 unsigned int lvds_bpc
;
4094 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
4100 if (lvds_bpc
< display_bpc
) {
4101 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
4102 display_bpc
= lvds_bpc
;
4107 /* Not one of the known troublemakers, check the EDID */
4108 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
4110 if (connector
->encoder
!= &intel_encoder
->base
)
4113 /* Don't use an invalid EDID bpc value */
4114 if (connector
->display_info
.bpc
&&
4115 connector
->display_info
.bpc
< display_bpc
) {
4116 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
4117 display_bpc
= connector
->display_info
.bpc
;
4121 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
4122 /* Use VBT settings if we have an eDP panel */
4123 unsigned int edp_bpc
= dev_priv
->edp
.bpp
/ 3;
4125 if (edp_bpc
&& edp_bpc
< display_bpc
) {
4126 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc
, edp_bpc
);
4127 display_bpc
= edp_bpc
;
4133 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4134 * through, clamp it down. (Note: >12bpc will be caught below.)
4136 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
4137 if (display_bpc
> 8 && display_bpc
< 12) {
4138 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4141 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4147 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4148 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4153 * We could just drive the pipe at the highest bpc all the time and
4154 * enable dithering as needed, but that costs bandwidth. So choose
4155 * the minimum value that expresses the full color range of the fb but
4156 * also stays within the max display bpc discovered above.
4159 switch (fb
->depth
) {
4161 bpc
= 8; /* since we go through a colormap */
4165 bpc
= 6; /* min is 18bpp */
4177 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4178 bpc
= min((unsigned int)8, display_bpc
);
4182 display_bpc
= min(display_bpc
, bpc
);
4184 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4187 *pipe_bpp
= display_bpc
* 3;
4189 return display_bpc
!= bpc
;
4192 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4194 struct drm_device
*dev
= crtc
->dev
;
4195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4196 int refclk
= 27000; /* for DP & HDMI */
4198 return 100000; /* only one validated so far */
4200 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4202 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4203 if (intel_panel_use_ssc(dev_priv
))
4207 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4214 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4216 struct drm_device
*dev
= crtc
->dev
;
4217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4220 if (IS_VALLEYVIEW(dev
)) {
4221 refclk
= vlv_get_refclk(crtc
);
4222 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4223 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4224 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4225 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4227 } else if (!IS_GEN2(dev
)) {
4236 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
4237 intel_clock_t
*clock
)
4239 /* SDVO TV has fixed PLL values depend on its clock range,
4240 this mirrors vbios setting. */
4241 if (adjusted_mode
->clock
>= 100000
4242 && adjusted_mode
->clock
< 140500) {
4248 } else if (adjusted_mode
->clock
>= 140500
4249 && adjusted_mode
->clock
<= 200000) {
4258 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
4259 intel_clock_t
*clock
,
4260 intel_clock_t
*reduced_clock
)
4262 struct drm_device
*dev
= crtc
->dev
;
4263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4264 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4265 int pipe
= intel_crtc
->pipe
;
4268 if (IS_PINEVIEW(dev
)) {
4269 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
4271 fp2
= (1 << reduced_clock
->n
) << 16 |
4272 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
4274 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
4276 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
4280 I915_WRITE(FP0(pipe
), fp
);
4282 intel_crtc
->lowfreq_avail
= false;
4283 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4284 reduced_clock
&& i915_powersave
) {
4285 I915_WRITE(FP1(pipe
), fp2
);
4286 intel_crtc
->lowfreq_avail
= true;
4288 I915_WRITE(FP1(pipe
), fp
);
4292 static void vlv_update_pll(struct drm_crtc
*crtc
,
4293 struct drm_display_mode
*mode
,
4294 struct drm_display_mode
*adjusted_mode
,
4295 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4298 struct drm_device
*dev
= crtc
->dev
;
4299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4300 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4301 int pipe
= intel_crtc
->pipe
;
4302 u32 dpll
, mdiv
, pdiv
;
4303 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4307 mutex_lock(&dev_priv
->dpio_lock
);
4309 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4310 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4312 dpll
= DPLL_VGA_MODE_DIS
;
4313 dpll
|= DPLL_EXT_BUFFER_ENABLE_VLV
;
4314 dpll
|= DPLL_REFA_CLK_ENABLE_VLV
;
4315 dpll
|= DPLL_INTEGRATED_CLOCK_VLV
;
4317 I915_WRITE(DPLL(pipe
), dpll
);
4318 POSTING_READ(DPLL(pipe
));
4327 * In Valleyview PLL and program lane counter registers are exposed
4328 * through DPIO interface
4330 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4331 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4332 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4333 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4334 mdiv
|= (1 << DPIO_K_SHIFT
);
4335 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4336 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4338 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4340 pdiv
= (1 << DPIO_REFSEL_OVERRIDE
) | (5 << DPIO_PLL_MODESEL_SHIFT
) |
4341 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4342 (7 << DPIO_PLL_REFCLK_SEL_SHIFT
) | (8 << DPIO_DRIVER_CTL_SHIFT
) |
4343 (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4344 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4346 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x005f003b);
4348 dpll
|= DPLL_VCO_ENABLE
;
4349 I915_WRITE(DPLL(pipe
), dpll
);
4350 POSTING_READ(DPLL(pipe
));
4351 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4352 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4354 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x620);
4356 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4357 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4359 I915_WRITE(DPLL(pipe
), dpll
);
4361 /* Wait for the clocks to stabilize. */
4362 POSTING_READ(DPLL(pipe
));
4367 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4369 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4373 I915_WRITE(DPLL_MD(pipe
), temp
);
4374 POSTING_READ(DPLL_MD(pipe
));
4376 /* Now program lane control registers */
4377 if(intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)
4378 || intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
4383 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL1
, temp
);
4385 if(intel_pipe_has_type(crtc
,INTEL_OUTPUT_EDP
))
4390 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL2
, temp
);
4393 mutex_unlock(&dev_priv
->dpio_lock
);
4396 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4397 struct drm_display_mode
*mode
,
4398 struct drm_display_mode
*adjusted_mode
,
4399 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4402 struct drm_device
*dev
= crtc
->dev
;
4403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4404 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4405 struct intel_encoder
*encoder
;
4406 int pipe
= intel_crtc
->pipe
;
4410 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4412 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4413 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4415 dpll
= DPLL_VGA_MODE_DIS
;
4417 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4418 dpll
|= DPLLB_MODE_LVDS
;
4420 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4422 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4423 if (pixel_multiplier
> 1) {
4424 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4425 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4427 dpll
|= DPLL_DVO_HIGH_SPEED
;
4429 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4430 dpll
|= DPLL_DVO_HIGH_SPEED
;
4432 /* compute bitmask from p1 value */
4433 if (IS_PINEVIEW(dev
))
4434 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4436 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4437 if (IS_G4X(dev
) && reduced_clock
)
4438 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4440 switch (clock
->p2
) {
4442 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4445 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4448 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4451 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4454 if (INTEL_INFO(dev
)->gen
>= 4)
4455 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4457 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4458 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4459 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4460 /* XXX: just matching BIOS for now */
4461 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4463 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4464 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4465 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4467 dpll
|= PLL_REF_INPUT_DREFCLK
;
4469 dpll
|= DPLL_VCO_ENABLE
;
4470 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4471 POSTING_READ(DPLL(pipe
));
4474 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4475 if (encoder
->pre_pll_enable
)
4476 encoder
->pre_pll_enable(encoder
);
4478 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4479 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4481 I915_WRITE(DPLL(pipe
), dpll
);
4483 /* Wait for the clocks to stabilize. */
4484 POSTING_READ(DPLL(pipe
));
4487 if (INTEL_INFO(dev
)->gen
>= 4) {
4490 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4492 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4496 I915_WRITE(DPLL_MD(pipe
), temp
);
4498 /* The pixel multiplier can only be updated once the
4499 * DPLL is enabled and the clocks are stable.
4501 * So write it again.
4503 I915_WRITE(DPLL(pipe
), dpll
);
4507 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4508 struct drm_display_mode
*adjusted_mode
,
4509 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4512 struct drm_device
*dev
= crtc
->dev
;
4513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4514 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4515 struct intel_encoder
*encoder
;
4516 int pipe
= intel_crtc
->pipe
;
4519 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4521 dpll
= DPLL_VGA_MODE_DIS
;
4523 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4524 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4527 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4529 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4531 dpll
|= PLL_P2_DIVIDE_BY_4
;
4534 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4535 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4536 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4538 dpll
|= PLL_REF_INPUT_DREFCLK
;
4540 dpll
|= DPLL_VCO_ENABLE
;
4541 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4542 POSTING_READ(DPLL(pipe
));
4545 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4546 if (encoder
->pre_pll_enable
)
4547 encoder
->pre_pll_enable(encoder
);
4549 I915_WRITE(DPLL(pipe
), dpll
);
4551 /* Wait for the clocks to stabilize. */
4552 POSTING_READ(DPLL(pipe
));
4555 /* The pixel multiplier can only be updated once the
4556 * DPLL is enabled and the clocks are stable.
4558 * So write it again.
4560 I915_WRITE(DPLL(pipe
), dpll
);
4563 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4564 struct drm_display_mode
*mode
,
4565 struct drm_display_mode
*adjusted_mode
)
4567 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4569 enum pipe pipe
= intel_crtc
->pipe
;
4570 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
4571 uint32_t vsyncshift
;
4573 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4574 /* the chip adds 2 halflines automatically */
4575 adjusted_mode
->crtc_vtotal
-= 1;
4576 adjusted_mode
->crtc_vblank_end
-= 1;
4577 vsyncshift
= adjusted_mode
->crtc_hsync_start
4578 - adjusted_mode
->crtc_htotal
/ 2;
4583 if (INTEL_INFO(dev
)->gen
> 3)
4584 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4586 I915_WRITE(HTOTAL(cpu_transcoder
),
4587 (adjusted_mode
->crtc_hdisplay
- 1) |
4588 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4589 I915_WRITE(HBLANK(cpu_transcoder
),
4590 (adjusted_mode
->crtc_hblank_start
- 1) |
4591 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4592 I915_WRITE(HSYNC(cpu_transcoder
),
4593 (adjusted_mode
->crtc_hsync_start
- 1) |
4594 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4596 I915_WRITE(VTOTAL(cpu_transcoder
),
4597 (adjusted_mode
->crtc_vdisplay
- 1) |
4598 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4599 I915_WRITE(VBLANK(cpu_transcoder
),
4600 (adjusted_mode
->crtc_vblank_start
- 1) |
4601 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4602 I915_WRITE(VSYNC(cpu_transcoder
),
4603 (adjusted_mode
->crtc_vsync_start
- 1) |
4604 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4606 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4607 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4608 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4610 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4611 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4612 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4614 /* pipesrc controls the size that is scaled from, which should
4615 * always be the user's requested size.
4617 I915_WRITE(PIPESRC(pipe
),
4618 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4621 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4622 struct drm_display_mode
*mode
,
4623 struct drm_display_mode
*adjusted_mode
,
4625 struct drm_framebuffer
*fb
)
4627 struct drm_device
*dev
= crtc
->dev
;
4628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4629 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4630 int pipe
= intel_crtc
->pipe
;
4631 int plane
= intel_crtc
->plane
;
4632 int refclk
, num_connectors
= 0;
4633 intel_clock_t clock
, reduced_clock
;
4634 u32 dspcntr
, pipeconf
;
4635 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4636 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4637 struct intel_encoder
*encoder
;
4638 const intel_limit_t
*limit
;
4641 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4642 switch (encoder
->type
) {
4643 case INTEL_OUTPUT_LVDS
:
4646 case INTEL_OUTPUT_SDVO
:
4647 case INTEL_OUTPUT_HDMI
:
4649 if (encoder
->needs_tv_clock
)
4652 case INTEL_OUTPUT_TVOUT
:
4655 case INTEL_OUTPUT_DISPLAYPORT
:
4663 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4666 * Returns a set of divisors for the desired target clock with the given
4667 * refclk, or FALSE. The returned values represent the clock equation:
4668 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4670 limit
= intel_limit(crtc
, refclk
);
4671 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4674 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4678 /* Ensure that the cursor is valid for the new mode before changing... */
4679 intel_crtc_update_cursor(crtc
, true);
4681 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4683 * Ensure we match the reduced clock's P to the target clock.
4684 * If the clocks don't match, we can't switch the display clock
4685 * by using the FP0/FP1. In such case we will disable the LVDS
4686 * downclock feature.
4688 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4689 dev_priv
->lvds_downclock
,
4695 if (is_sdvo
&& is_tv
)
4696 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4699 i8xx_update_pll(crtc
, adjusted_mode
, &clock
,
4700 has_reduced_clock
? &reduced_clock
: NULL
,
4702 else if (IS_VALLEYVIEW(dev
))
4703 vlv_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4704 has_reduced_clock
? &reduced_clock
: NULL
,
4707 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4708 has_reduced_clock
? &reduced_clock
: NULL
,
4711 /* setup pipeconf */
4712 pipeconf
= I915_READ(PIPECONF(pipe
));
4714 /* Set up the display plane register */
4715 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4718 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4720 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4722 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4723 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4726 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4730 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4731 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4733 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4736 /* default to 8bpc */
4737 pipeconf
&= ~(PIPECONF_BPC_MASK
| PIPECONF_DITHER_EN
);
4739 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4740 pipeconf
|= PIPECONF_6BPC
|
4741 PIPECONF_DITHER_EN
|
4742 PIPECONF_DITHER_TYPE_SP
;
4746 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4747 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4748 pipeconf
|= PIPECONF_6BPC
|
4750 I965_PIPECONF_ACTIVE
;
4754 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4755 drm_mode_debug_printmodeline(mode
);
4757 if (HAS_PIPE_CXSR(dev
)) {
4758 if (intel_crtc
->lowfreq_avail
) {
4759 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4760 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4762 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4763 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4767 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4768 if (!IS_GEN2(dev
) &&
4769 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4770 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4772 pipeconf
|= PIPECONF_PROGRESSIVE
;
4774 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4776 /* pipesrc and dspsize control the size that is scaled from,
4777 * which should always be the user's requested size.
4779 I915_WRITE(DSPSIZE(plane
),
4780 ((mode
->vdisplay
- 1) << 16) |
4781 (mode
->hdisplay
- 1));
4782 I915_WRITE(DSPPOS(plane
), 0);
4784 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4785 POSTING_READ(PIPECONF(pipe
));
4786 intel_enable_pipe(dev_priv
, pipe
, false);
4788 intel_wait_for_vblank(dev
, pipe
);
4790 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4791 POSTING_READ(DSPCNTR(plane
));
4793 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4795 intel_update_watermarks(dev
);
4800 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
4802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4803 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4804 struct intel_encoder
*encoder
;
4806 bool has_lvds
= false;
4807 bool has_cpu_edp
= false;
4808 bool has_pch_edp
= false;
4809 bool has_panel
= false;
4810 bool has_ck505
= false;
4811 bool can_ssc
= false;
4813 /* We need to take the global config into account */
4814 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4816 switch (encoder
->type
) {
4817 case INTEL_OUTPUT_LVDS
:
4821 case INTEL_OUTPUT_EDP
:
4823 if (intel_encoder_is_pch_edp(&encoder
->base
))
4831 if (HAS_PCH_IBX(dev
)) {
4832 has_ck505
= dev_priv
->display_clock_mode
;
4833 can_ssc
= has_ck505
;
4839 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4840 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4843 /* Ironlake: try to setup display ref clock before DPLL
4844 * enabling. This is only under driver's control after
4845 * PCH B stepping, previous chipset stepping should be
4846 * ignoring this setting.
4848 temp
= I915_READ(PCH_DREF_CONTROL
);
4849 /* Always enable nonspread source */
4850 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4853 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4855 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4858 temp
&= ~DREF_SSC_SOURCE_MASK
;
4859 temp
|= DREF_SSC_SOURCE_ENABLE
;
4861 /* SSC must be turned on before enabling the CPU output */
4862 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4863 DRM_DEBUG_KMS("Using SSC on panel\n");
4864 temp
|= DREF_SSC1_ENABLE
;
4866 temp
&= ~DREF_SSC1_ENABLE
;
4868 /* Get SSC going before enabling the outputs */
4869 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4870 POSTING_READ(PCH_DREF_CONTROL
);
4873 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4875 /* Enable CPU source on CPU attached eDP */
4877 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4878 DRM_DEBUG_KMS("Using SSC on eDP\n");
4879 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4882 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4884 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4886 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4887 POSTING_READ(PCH_DREF_CONTROL
);
4890 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4892 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4894 /* Turn off CPU output */
4895 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4897 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4898 POSTING_READ(PCH_DREF_CONTROL
);
4901 /* Turn off the SSC source */
4902 temp
&= ~DREF_SSC_SOURCE_MASK
;
4903 temp
|= DREF_SSC_SOURCE_DISABLE
;
4906 temp
&= ~ DREF_SSC1_ENABLE
;
4908 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4909 POSTING_READ(PCH_DREF_CONTROL
);
4914 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4915 static void lpt_init_pch_refclk(struct drm_device
*dev
)
4917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4918 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4919 struct intel_encoder
*encoder
;
4920 bool has_vga
= false;
4921 bool is_sdv
= false;
4924 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4925 switch (encoder
->type
) {
4926 case INTEL_OUTPUT_ANALOG
:
4935 mutex_lock(&dev_priv
->dpio_lock
);
4937 /* XXX: Rip out SDV support once Haswell ships for real. */
4938 if (IS_HASWELL(dev
) && (dev
->pci_device
& 0xFF00) == 0x0C00)
4941 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4942 tmp
&= ~SBI_SSCCTL_DISABLE
;
4943 tmp
|= SBI_SSCCTL_PATHALT
;
4944 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4948 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
4949 tmp
&= ~SBI_SSCCTL_PATHALT
;
4950 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
4953 tmp
= I915_READ(SOUTH_CHICKEN2
);
4954 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
4955 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4957 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
4958 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
4959 DRM_ERROR("FDI mPHY reset assert timeout\n");
4961 tmp
= I915_READ(SOUTH_CHICKEN2
);
4962 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
4963 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
4965 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
4966 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0,
4968 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4971 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
4972 tmp
&= ~(0xFF << 24);
4973 tmp
|= (0x12 << 24);
4974 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
4977 tmp
= intel_sbi_read(dev_priv
, 0x808C, SBI_MPHY
);
4979 tmp
|= (1 << 6) | (1 << 0);
4980 intel_sbi_write(dev_priv
, 0x808C, tmp
, SBI_MPHY
);
4984 tmp
= intel_sbi_read(dev_priv
, 0x800C, SBI_MPHY
);
4986 intel_sbi_write(dev_priv
, 0x800C, tmp
, SBI_MPHY
);
4989 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
4991 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
4993 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
4995 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
4998 tmp
= intel_sbi_read(dev_priv
, 0x2038, SBI_MPHY
);
4999 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5000 intel_sbi_write(dev_priv
, 0x2038, tmp
, SBI_MPHY
);
5002 tmp
= intel_sbi_read(dev_priv
, 0x2138, SBI_MPHY
);
5003 tmp
|= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5004 intel_sbi_write(dev_priv
, 0x2138, tmp
, SBI_MPHY
);
5006 tmp
= intel_sbi_read(dev_priv
, 0x203C, SBI_MPHY
);
5008 intel_sbi_write(dev_priv
, 0x203C, tmp
, SBI_MPHY
);
5010 tmp
= intel_sbi_read(dev_priv
, 0x213C, SBI_MPHY
);
5012 intel_sbi_write(dev_priv
, 0x213C, tmp
, SBI_MPHY
);
5015 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5016 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5017 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5019 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5020 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5021 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5024 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5027 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5029 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5032 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5035 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5038 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5040 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5043 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5045 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5046 tmp
&= ~(0xFF << 16);
5047 tmp
|= (0x1C << 16);
5048 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5050 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5051 tmp
&= ~(0xFF << 16);
5052 tmp
|= (0x1C << 16);
5053 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5056 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5058 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5060 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5062 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5064 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5065 tmp
&= ~(0xF << 28);
5067 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5069 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5070 tmp
&= ~(0xF << 28);
5072 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5075 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5076 tmp
= intel_sbi_read(dev_priv
, SBI_DBUFF0
, SBI_ICLK
);
5077 tmp
|= SBI_DBUFF0_ENABLE
;
5078 intel_sbi_write(dev_priv
, SBI_DBUFF0
, tmp
, SBI_ICLK
);
5080 mutex_unlock(&dev_priv
->dpio_lock
);
5084 * Initialize reference clocks when the driver loads
5086 void intel_init_pch_refclk(struct drm_device
*dev
)
5088 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5089 ironlake_init_pch_refclk(dev
);
5090 else if (HAS_PCH_LPT(dev
))
5091 lpt_init_pch_refclk(dev
);
5094 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5096 struct drm_device
*dev
= crtc
->dev
;
5097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5098 struct intel_encoder
*encoder
;
5099 struct intel_encoder
*edp_encoder
= NULL
;
5100 int num_connectors
= 0;
5101 bool is_lvds
= false;
5103 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5104 switch (encoder
->type
) {
5105 case INTEL_OUTPUT_LVDS
:
5108 case INTEL_OUTPUT_EDP
:
5109 edp_encoder
= encoder
;
5115 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5116 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5117 dev_priv
->lvds_ssc_freq
);
5118 return dev_priv
->lvds_ssc_freq
* 1000;
5124 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
5125 struct drm_display_mode
*adjusted_mode
,
5128 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5129 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5130 int pipe
= intel_crtc
->pipe
;
5133 val
= I915_READ(PIPECONF(pipe
));
5135 val
&= ~PIPECONF_BPC_MASK
;
5136 switch (intel_crtc
->bpp
) {
5138 val
|= PIPECONF_6BPC
;
5141 val
|= PIPECONF_8BPC
;
5144 val
|= PIPECONF_10BPC
;
5147 val
|= PIPECONF_12BPC
;
5150 /* Case prevented by intel_choose_pipe_bpp_dither. */
5154 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5156 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5158 val
&= ~PIPECONF_INTERLACE_MASK
;
5159 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5160 val
|= PIPECONF_INTERLACED_ILK
;
5162 val
|= PIPECONF_PROGRESSIVE
;
5164 if (adjusted_mode
->private_flags
& INTEL_MODE_LIMITED_COLOR_RANGE
)
5165 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5167 val
&= ~PIPECONF_COLOR_RANGE_SELECT
;
5169 I915_WRITE(PIPECONF(pipe
), val
);
5170 POSTING_READ(PIPECONF(pipe
));
5174 * Set up the pipe CSC unit.
5176 * Currently only full range RGB to limited range RGB conversion
5177 * is supported, but eventually this should handle various
5178 * RGB<->YCbCr scenarios as well.
5180 static void intel_set_pipe_csc(struct drm_crtc
*crtc
,
5181 const struct drm_display_mode
*adjusted_mode
)
5183 struct drm_device
*dev
= crtc
->dev
;
5184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5185 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5186 int pipe
= intel_crtc
->pipe
;
5187 uint16_t coeff
= 0x7800; /* 1.0 */
5190 * TODO: Check what kind of values actually come out of the pipe
5191 * with these coeff/postoff values and adjust to get the best
5192 * accuracy. Perhaps we even need to take the bpc value into
5196 if (adjusted_mode
->private_flags
& INTEL_MODE_LIMITED_COLOR_RANGE
)
5197 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5200 * GY/GU and RY/RU should be the other way around according
5201 * to BSpec, but reality doesn't agree. Just set them up in
5202 * a way that results in the correct picture.
5204 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5205 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5207 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5208 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5210 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5211 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5213 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5214 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5215 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5217 if (INTEL_INFO(dev
)->gen
> 6) {
5218 uint16_t postoff
= 0;
5220 if (adjusted_mode
->private_flags
& INTEL_MODE_LIMITED_COLOR_RANGE
)
5221 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5223 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5224 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5225 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5227 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5229 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5231 if (adjusted_mode
->private_flags
& INTEL_MODE_LIMITED_COLOR_RANGE
)
5232 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5234 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5238 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
5239 struct drm_display_mode
*adjusted_mode
,
5242 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5243 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5244 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5247 val
= I915_READ(PIPECONF(cpu_transcoder
));
5249 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5251 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5253 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
5254 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5255 val
|= PIPECONF_INTERLACED_ILK
;
5257 val
|= PIPECONF_PROGRESSIVE
;
5259 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5260 POSTING_READ(PIPECONF(cpu_transcoder
));
5263 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5264 struct drm_display_mode
*adjusted_mode
,
5265 intel_clock_t
*clock
,
5266 bool *has_reduced_clock
,
5267 intel_clock_t
*reduced_clock
)
5269 struct drm_device
*dev
= crtc
->dev
;
5270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5271 struct intel_encoder
*intel_encoder
;
5273 const intel_limit_t
*limit
;
5274 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
5276 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5277 switch (intel_encoder
->type
) {
5278 case INTEL_OUTPUT_LVDS
:
5281 case INTEL_OUTPUT_SDVO
:
5282 case INTEL_OUTPUT_HDMI
:
5284 if (intel_encoder
->needs_tv_clock
)
5287 case INTEL_OUTPUT_TVOUT
:
5293 refclk
= ironlake_get_refclk(crtc
);
5296 * Returns a set of divisors for the desired target clock with the given
5297 * refclk, or FALSE. The returned values represent the clock equation:
5298 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5300 limit
= intel_limit(crtc
, refclk
);
5301 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5306 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5308 * Ensure we match the reduced clock's P to the target clock.
5309 * If the clocks don't match, we can't switch the display clock
5310 * by using the FP0/FP1. In such case we will disable the LVDS
5311 * downclock feature.
5313 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5314 dev_priv
->lvds_downclock
,
5320 if (is_sdvo
&& is_tv
)
5321 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, clock
);
5326 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5331 temp
= I915_READ(SOUTH_CHICKEN1
);
5332 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5335 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5336 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5338 temp
|= FDI_BC_BIFURCATION_SELECT
;
5339 DRM_DEBUG_KMS("enabling fdi C rx\n");
5340 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5341 POSTING_READ(SOUTH_CHICKEN1
);
5344 static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc
)
5346 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5348 struct intel_crtc
*pipe_B_crtc
=
5349 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5351 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5352 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5353 if (intel_crtc
->fdi_lanes
> 4) {
5354 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5355 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5356 /* Clamp lanes to avoid programming the hw with bogus values. */
5357 intel_crtc
->fdi_lanes
= 4;
5362 if (dev_priv
->num_pipe
== 2)
5365 switch (intel_crtc
->pipe
) {
5369 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5370 intel_crtc
->fdi_lanes
> 2) {
5371 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5372 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5373 /* Clamp lanes to avoid programming the hw with bogus values. */
5374 intel_crtc
->fdi_lanes
= 2;
5379 if (intel_crtc
->fdi_lanes
> 2)
5380 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5382 cpt_enable_fdi_bc_bifurcation(dev
);
5386 if (!pipe_B_crtc
->base
.enabled
|| pipe_B_crtc
->fdi_lanes
<= 2) {
5387 if (intel_crtc
->fdi_lanes
> 2) {
5388 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5389 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5390 /* Clamp lanes to avoid programming the hw with bogus values. */
5391 intel_crtc
->fdi_lanes
= 2;
5396 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5400 cpt_enable_fdi_bc_bifurcation(dev
);
5408 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5411 * Account for spread spectrum to avoid
5412 * oversubscribing the link. Max center spread
5413 * is 2.5%; use 5% for safety's sake.
5415 u32 bps
= target_clock
* bpp
* 21 / 20;
5416 return bps
/ (link_bw
* 8) + 1;
5419 static void ironlake_set_m_n(struct drm_crtc
*crtc
,
5420 struct drm_display_mode
*mode
,
5421 struct drm_display_mode
*adjusted_mode
)
5423 struct drm_device
*dev
= crtc
->dev
;
5424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5425 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5426 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5427 struct intel_encoder
*intel_encoder
, *edp_encoder
= NULL
;
5428 struct intel_link_m_n m_n
= {0};
5429 int target_clock
, pixel_multiplier
, lane
, link_bw
;
5430 bool is_dp
= false, is_cpu_edp
= false;
5432 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5433 switch (intel_encoder
->type
) {
5434 case INTEL_OUTPUT_DISPLAYPORT
:
5437 case INTEL_OUTPUT_EDP
:
5439 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5441 edp_encoder
= intel_encoder
;
5447 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5449 /* CPU eDP doesn't require FDI link, so just set DP M/N
5450 according to current link config */
5452 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
5454 /* FDI is a binary signal running at ~2.7GHz, encoding
5455 * each output octet as 10 bits. The actual frequency
5456 * is stored as a divider into a 100MHz clock, and the
5457 * mode pixel clock is stored in units of 1KHz.
5458 * Hence the bw of each lane in terms of the mode signal
5461 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5464 /* [e]DP over FDI requires target mode clock instead of link clock. */
5466 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
5468 target_clock
= mode
->clock
;
5470 target_clock
= adjusted_mode
->clock
;
5473 lane
= ironlake_get_lanes_required(target_clock
, link_bw
,
5476 intel_crtc
->fdi_lanes
= lane
;
5478 if (pixel_multiplier
> 1)
5479 link_bw
*= pixel_multiplier
;
5480 intel_link_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
, &m_n
);
5482 I915_WRITE(PIPE_DATA_M1(cpu_transcoder
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
5483 I915_WRITE(PIPE_DATA_N1(cpu_transcoder
), m_n
.gmch_n
);
5484 I915_WRITE(PIPE_LINK_M1(cpu_transcoder
), m_n
.link_m
);
5485 I915_WRITE(PIPE_LINK_N1(cpu_transcoder
), m_n
.link_n
);
5488 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5489 struct drm_display_mode
*adjusted_mode
,
5490 intel_clock_t
*clock
, u32 fp
)
5492 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5493 struct drm_device
*dev
= crtc
->dev
;
5494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5495 struct intel_encoder
*intel_encoder
;
5497 int factor
, pixel_multiplier
, num_connectors
= 0;
5498 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5499 bool is_dp
= false, is_cpu_edp
= false;
5501 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5502 switch (intel_encoder
->type
) {
5503 case INTEL_OUTPUT_LVDS
:
5506 case INTEL_OUTPUT_SDVO
:
5507 case INTEL_OUTPUT_HDMI
:
5509 if (intel_encoder
->needs_tv_clock
)
5512 case INTEL_OUTPUT_TVOUT
:
5515 case INTEL_OUTPUT_DISPLAYPORT
:
5518 case INTEL_OUTPUT_EDP
:
5520 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5528 /* Enable autotuning of the PLL clock (if permissible) */
5531 if ((intel_panel_use_ssc(dev_priv
) &&
5532 dev_priv
->lvds_ssc_freq
== 100) ||
5533 intel_is_dual_link_lvds(dev
))
5535 } else if (is_sdvo
&& is_tv
)
5538 if (clock
->m
< factor
* clock
->n
)
5544 dpll
|= DPLLB_MODE_LVDS
;
5546 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5548 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5549 if (pixel_multiplier
> 1) {
5550 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5552 dpll
|= DPLL_DVO_HIGH_SPEED
;
5554 if (is_dp
&& !is_cpu_edp
)
5555 dpll
|= DPLL_DVO_HIGH_SPEED
;
5557 /* compute bitmask from p1 value */
5558 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5560 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5562 switch (clock
->p2
) {
5564 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5567 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5570 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5573 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5577 if (is_sdvo
&& is_tv
)
5578 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5580 /* XXX: just matching BIOS for now */
5581 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5583 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5584 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5586 dpll
|= PLL_REF_INPUT_DREFCLK
;
5591 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5592 struct drm_display_mode
*mode
,
5593 struct drm_display_mode
*adjusted_mode
,
5595 struct drm_framebuffer
*fb
)
5597 struct drm_device
*dev
= crtc
->dev
;
5598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5599 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5600 int pipe
= intel_crtc
->pipe
;
5601 int plane
= intel_crtc
->plane
;
5602 int num_connectors
= 0;
5603 intel_clock_t clock
, reduced_clock
;
5604 u32 dpll
, fp
= 0, fp2
= 0;
5605 bool ok
, has_reduced_clock
= false;
5606 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
5607 struct intel_encoder
*encoder
;
5609 bool dither
, fdi_config_ok
;
5611 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5612 switch (encoder
->type
) {
5613 case INTEL_OUTPUT_LVDS
:
5616 case INTEL_OUTPUT_DISPLAYPORT
:
5619 case INTEL_OUTPUT_EDP
:
5621 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5629 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5630 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5632 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5633 &has_reduced_clock
, &reduced_clock
);
5635 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5639 /* Ensure that the cursor is valid for the new mode before changing... */
5640 intel_crtc_update_cursor(crtc
, true);
5642 /* determine panel color depth */
5643 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5645 if (is_lvds
&& dev_priv
->lvds_dither
)
5648 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5649 if (has_reduced_clock
)
5650 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5653 dpll
= ironlake_compute_dpll(intel_crtc
, adjusted_mode
, &clock
, fp
);
5655 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5656 drm_mode_debug_printmodeline(mode
);
5658 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5660 struct intel_pch_pll
*pll
;
5662 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5664 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5669 intel_put_pch_pll(intel_crtc
);
5671 if (is_dp
&& !is_cpu_edp
)
5672 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5674 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5675 if (encoder
->pre_pll_enable
)
5676 encoder
->pre_pll_enable(encoder
);
5678 if (intel_crtc
->pch_pll
) {
5679 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5681 /* Wait for the clocks to stabilize. */
5682 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5685 /* The pixel multiplier can only be updated once the
5686 * DPLL is enabled and the clocks are stable.
5688 * So write it again.
5690 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5693 intel_crtc
->lowfreq_avail
= false;
5694 if (intel_crtc
->pch_pll
) {
5695 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5696 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5697 intel_crtc
->lowfreq_avail
= true;
5699 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5703 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5705 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5706 * ironlake_check_fdi_lanes. */
5707 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5709 fdi_config_ok
= ironlake_check_fdi_lanes(intel_crtc
);
5711 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5713 intel_wait_for_vblank(dev
, pipe
);
5715 /* Set up the display plane register */
5716 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5717 POSTING_READ(DSPCNTR(plane
));
5719 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5721 intel_update_watermarks(dev
);
5723 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5725 return fdi_config_ok
? ret
: -EINVAL
;
5728 static void haswell_modeset_global_resources(struct drm_device
*dev
)
5730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5731 bool enable
= false;
5732 struct intel_crtc
*crtc
;
5733 struct intel_encoder
*encoder
;
5735 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
5736 if (crtc
->pipe
!= PIPE_A
&& crtc
->base
.enabled
)
5738 /* XXX: Should check for edp transcoder here, but thanks to init
5739 * sequence that's not yet available. Just in case desktop eDP
5740 * on PORT D is possible on haswell, too. */
5743 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
5745 if (encoder
->type
!= INTEL_OUTPUT_EDP
&&
5746 encoder
->connectors_active
)
5750 /* Even the eDP panel fitter is outside the always-on well. */
5751 if (dev_priv
->pch_pf_size
)
5754 intel_set_power_well(dev
, enable
);
5757 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5758 struct drm_display_mode
*mode
,
5759 struct drm_display_mode
*adjusted_mode
,
5761 struct drm_framebuffer
*fb
)
5763 struct drm_device
*dev
= crtc
->dev
;
5764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5765 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5766 int pipe
= intel_crtc
->pipe
;
5767 int plane
= intel_crtc
->plane
;
5768 int num_connectors
= 0;
5769 bool is_dp
= false, is_cpu_edp
= false;
5770 struct intel_encoder
*encoder
;
5774 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5775 switch (encoder
->type
) {
5776 case INTEL_OUTPUT_DISPLAYPORT
:
5779 case INTEL_OUTPUT_EDP
:
5781 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5789 /* We are not sure yet this won't happen. */
5790 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5791 INTEL_PCH_TYPE(dev
));
5793 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5794 num_connectors
, pipe_name(pipe
));
5796 WARN_ON(I915_READ(PIPECONF(intel_crtc
->cpu_transcoder
)) &
5797 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5799 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5801 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5804 /* Ensure that the cursor is valid for the new mode before changing... */
5805 intel_crtc_update_cursor(crtc
, true);
5807 /* determine panel color depth */
5808 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5811 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5812 drm_mode_debug_printmodeline(mode
);
5814 if (is_dp
&& !is_cpu_edp
)
5815 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5817 intel_crtc
->lowfreq_avail
= false;
5819 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5821 if (!is_dp
|| is_cpu_edp
)
5822 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5824 haswell_set_pipeconf(crtc
, adjusted_mode
, dither
);
5826 intel_set_pipe_csc(crtc
, adjusted_mode
);
5828 /* Set up the display plane register */
5829 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
5830 POSTING_READ(DSPCNTR(plane
));
5832 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5834 intel_update_watermarks(dev
);
5836 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5841 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5842 struct drm_display_mode
*mode
,
5843 struct drm_display_mode
*adjusted_mode
,
5845 struct drm_framebuffer
*fb
)
5847 struct drm_device
*dev
= crtc
->dev
;
5848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5849 struct drm_encoder_helper_funcs
*encoder_funcs
;
5850 struct intel_encoder
*encoder
;
5851 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5852 int pipe
= intel_crtc
->pipe
;
5855 if (IS_HASWELL(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
5856 intel_crtc
->cpu_transcoder
= TRANSCODER_EDP
;
5858 intel_crtc
->cpu_transcoder
= pipe
;
5860 drm_vblank_pre_modeset(dev
, pipe
);
5862 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
5864 drm_vblank_post_modeset(dev
, pipe
);
5869 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5870 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5871 encoder
->base
.base
.id
,
5872 drm_get_encoder_name(&encoder
->base
),
5873 mode
->base
.id
, mode
->name
);
5874 encoder_funcs
= encoder
->base
.helper_private
;
5875 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
5881 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5882 int reg_eldv
, uint32_t bits_eldv
,
5883 int reg_elda
, uint32_t bits_elda
,
5886 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5887 uint8_t *eld
= connector
->eld
;
5890 i
= I915_READ(reg_eldv
);
5899 i
= I915_READ(reg_elda
);
5901 I915_WRITE(reg_elda
, i
);
5903 for (i
= 0; i
< eld
[2]; i
++)
5904 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5910 static void g4x_write_eld(struct drm_connector
*connector
,
5911 struct drm_crtc
*crtc
)
5913 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5914 uint8_t *eld
= connector
->eld
;
5919 i
= I915_READ(G4X_AUD_VID_DID
);
5921 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5922 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5924 eldv
= G4X_ELDV_DEVCTG
;
5926 if (intel_eld_uptodate(connector
,
5927 G4X_AUD_CNTL_ST
, eldv
,
5928 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5929 G4X_HDMIW_HDMIEDID
))
5932 i
= I915_READ(G4X_AUD_CNTL_ST
);
5933 i
&= ~(eldv
| G4X_ELD_ADDR
);
5934 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5935 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5940 len
= min_t(uint8_t, eld
[2], len
);
5941 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5942 for (i
= 0; i
< len
; i
++)
5943 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5945 i
= I915_READ(G4X_AUD_CNTL_ST
);
5947 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5950 static void haswell_write_eld(struct drm_connector
*connector
,
5951 struct drm_crtc
*crtc
)
5953 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5954 uint8_t *eld
= connector
->eld
;
5955 struct drm_device
*dev
= crtc
->dev
;
5956 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5960 int pipe
= to_intel_crtc(crtc
)->pipe
;
5963 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
5964 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
5965 int aud_config
= HSW_AUD_CFG(pipe
);
5966 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
5969 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5971 /* Audio output enable */
5972 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5973 tmp
= I915_READ(aud_cntrl_st2
);
5974 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
5975 I915_WRITE(aud_cntrl_st2
, tmp
);
5977 /* Wait for 1 vertical blank */
5978 intel_wait_for_vblank(dev
, pipe
);
5980 /* Set ELD valid state */
5981 tmp
= I915_READ(aud_cntrl_st2
);
5982 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
5983 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
5984 I915_WRITE(aud_cntrl_st2
, tmp
);
5985 tmp
= I915_READ(aud_cntrl_st2
);
5986 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
5988 /* Enable HDMI mode */
5989 tmp
= I915_READ(aud_config
);
5990 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
5991 /* clear N_programing_enable and N_value_index */
5992 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
5993 I915_WRITE(aud_config
, tmp
);
5995 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5997 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
5998 intel_crtc
->eld_vld
= true;
6000 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6001 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6002 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6003 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6005 I915_WRITE(aud_config
, 0);
6007 if (intel_eld_uptodate(connector
,
6008 aud_cntrl_st2
, eldv
,
6009 aud_cntl_st
, IBX_ELD_ADDRESS
,
6013 i
= I915_READ(aud_cntrl_st2
);
6015 I915_WRITE(aud_cntrl_st2
, i
);
6020 i
= I915_READ(aud_cntl_st
);
6021 i
&= ~IBX_ELD_ADDRESS
;
6022 I915_WRITE(aud_cntl_st
, i
);
6023 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6024 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6026 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6027 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6028 for (i
= 0; i
< len
; i
++)
6029 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6031 i
= I915_READ(aud_cntrl_st2
);
6033 I915_WRITE(aud_cntrl_st2
, i
);
6037 static void ironlake_write_eld(struct drm_connector
*connector
,
6038 struct drm_crtc
*crtc
)
6040 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6041 uint8_t *eld
= connector
->eld
;
6049 int pipe
= to_intel_crtc(crtc
)->pipe
;
6051 if (HAS_PCH_IBX(connector
->dev
)) {
6052 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6053 aud_config
= IBX_AUD_CFG(pipe
);
6054 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6055 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6057 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6058 aud_config
= CPT_AUD_CFG(pipe
);
6059 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6060 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6063 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6065 i
= I915_READ(aud_cntl_st
);
6066 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6068 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6069 /* operate blindly on all ports */
6070 eldv
= IBX_ELD_VALIDB
;
6071 eldv
|= IBX_ELD_VALIDB
<< 4;
6072 eldv
|= IBX_ELD_VALIDB
<< 8;
6074 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
6075 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6078 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6079 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6080 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6081 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6083 I915_WRITE(aud_config
, 0);
6085 if (intel_eld_uptodate(connector
,
6086 aud_cntrl_st2
, eldv
,
6087 aud_cntl_st
, IBX_ELD_ADDRESS
,
6091 i
= I915_READ(aud_cntrl_st2
);
6093 I915_WRITE(aud_cntrl_st2
, i
);
6098 i
= I915_READ(aud_cntl_st
);
6099 i
&= ~IBX_ELD_ADDRESS
;
6100 I915_WRITE(aud_cntl_st
, i
);
6102 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6103 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6104 for (i
= 0; i
< len
; i
++)
6105 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6107 i
= I915_READ(aud_cntrl_st2
);
6109 I915_WRITE(aud_cntrl_st2
, i
);
6112 void intel_write_eld(struct drm_encoder
*encoder
,
6113 struct drm_display_mode
*mode
)
6115 struct drm_crtc
*crtc
= encoder
->crtc
;
6116 struct drm_connector
*connector
;
6117 struct drm_device
*dev
= encoder
->dev
;
6118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6120 connector
= drm_select_eld(encoder
, mode
);
6124 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6126 drm_get_connector_name(connector
),
6127 connector
->encoder
->base
.id
,
6128 drm_get_encoder_name(connector
->encoder
));
6130 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6132 if (dev_priv
->display
.write_eld
)
6133 dev_priv
->display
.write_eld(connector
, crtc
);
6136 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6137 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6139 struct drm_device
*dev
= crtc
->dev
;
6140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6141 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6142 int palreg
= PALETTE(intel_crtc
->pipe
);
6145 /* The clocks have to be on to load the palette. */
6146 if (!crtc
->enabled
|| !intel_crtc
->active
)
6149 /* use legacy palette for Ironlake */
6150 if (HAS_PCH_SPLIT(dev
))
6151 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
6153 for (i
= 0; i
< 256; i
++) {
6154 I915_WRITE(palreg
+ 4 * i
,
6155 (intel_crtc
->lut_r
[i
] << 16) |
6156 (intel_crtc
->lut_g
[i
] << 8) |
6157 intel_crtc
->lut_b
[i
]);
6161 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6163 struct drm_device
*dev
= crtc
->dev
;
6164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6165 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6166 bool visible
= base
!= 0;
6169 if (intel_crtc
->cursor_visible
== visible
)
6172 cntl
= I915_READ(_CURACNTR
);
6174 /* On these chipsets we can only modify the base whilst
6175 * the cursor is disabled.
6177 I915_WRITE(_CURABASE
, base
);
6179 cntl
&= ~(CURSOR_FORMAT_MASK
);
6180 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6181 cntl
|= CURSOR_ENABLE
|
6182 CURSOR_GAMMA_ENABLE
|
6185 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6186 I915_WRITE(_CURACNTR
, cntl
);
6188 intel_crtc
->cursor_visible
= visible
;
6191 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6193 struct drm_device
*dev
= crtc
->dev
;
6194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6195 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6196 int pipe
= intel_crtc
->pipe
;
6197 bool visible
= base
!= 0;
6199 if (intel_crtc
->cursor_visible
!= visible
) {
6200 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6202 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6203 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6204 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6206 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6207 cntl
|= CURSOR_MODE_DISABLE
;
6209 I915_WRITE(CURCNTR(pipe
), cntl
);
6211 intel_crtc
->cursor_visible
= visible
;
6213 /* and commit changes on next vblank */
6214 I915_WRITE(CURBASE(pipe
), base
);
6217 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6219 struct drm_device
*dev
= crtc
->dev
;
6220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6221 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6222 int pipe
= intel_crtc
->pipe
;
6223 bool visible
= base
!= 0;
6225 if (intel_crtc
->cursor_visible
!= visible
) {
6226 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6228 cntl
&= ~CURSOR_MODE
;
6229 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6231 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6232 cntl
|= CURSOR_MODE_DISABLE
;
6234 if (IS_HASWELL(dev
))
6235 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6236 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6238 intel_crtc
->cursor_visible
= visible
;
6240 /* and commit changes on next vblank */
6241 I915_WRITE(CURBASE_IVB(pipe
), base
);
6244 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6245 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6248 struct drm_device
*dev
= crtc
->dev
;
6249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6250 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6251 int pipe
= intel_crtc
->pipe
;
6252 int x
= intel_crtc
->cursor_x
;
6253 int y
= intel_crtc
->cursor_y
;
6259 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6260 base
= intel_crtc
->cursor_addr
;
6261 if (x
> (int) crtc
->fb
->width
)
6264 if (y
> (int) crtc
->fb
->height
)
6270 if (x
+ intel_crtc
->cursor_width
< 0)
6273 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6276 pos
|= x
<< CURSOR_X_SHIFT
;
6279 if (y
+ intel_crtc
->cursor_height
< 0)
6282 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6285 pos
|= y
<< CURSOR_Y_SHIFT
;
6287 visible
= base
!= 0;
6288 if (!visible
&& !intel_crtc
->cursor_visible
)
6291 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6292 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6293 ivb_update_cursor(crtc
, base
);
6295 I915_WRITE(CURPOS(pipe
), pos
);
6296 if (IS_845G(dev
) || IS_I865G(dev
))
6297 i845_update_cursor(crtc
, base
);
6299 i9xx_update_cursor(crtc
, base
);
6303 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6304 struct drm_file
*file
,
6306 uint32_t width
, uint32_t height
)
6308 struct drm_device
*dev
= crtc
->dev
;
6309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6311 struct drm_i915_gem_object
*obj
;
6315 /* if we want to turn off the cursor ignore width and height */
6317 DRM_DEBUG_KMS("cursor off\n");
6320 mutex_lock(&dev
->struct_mutex
);
6324 /* Currently we only support 64x64 cursors */
6325 if (width
!= 64 || height
!= 64) {
6326 DRM_ERROR("we currently only support 64x64 cursors\n");
6330 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6331 if (&obj
->base
== NULL
)
6334 if (obj
->base
.size
< width
* height
* 4) {
6335 DRM_ERROR("buffer is to small\n");
6340 /* we only need to pin inside GTT if cursor is non-phy */
6341 mutex_lock(&dev
->struct_mutex
);
6342 if (!dev_priv
->info
->cursor_needs_physical
) {
6343 if (obj
->tiling_mode
) {
6344 DRM_ERROR("cursor cannot be tiled\n");
6349 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
6351 DRM_ERROR("failed to move cursor bo into the GTT\n");
6355 ret
= i915_gem_object_put_fence(obj
);
6357 DRM_ERROR("failed to release fence for cursor");
6361 addr
= obj
->gtt_offset
;
6363 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6364 ret
= i915_gem_attach_phys_object(dev
, obj
,
6365 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6368 DRM_ERROR("failed to attach phys object\n");
6371 addr
= obj
->phys_obj
->handle
->busaddr
;
6375 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6378 if (intel_crtc
->cursor_bo
) {
6379 if (dev_priv
->info
->cursor_needs_physical
) {
6380 if (intel_crtc
->cursor_bo
!= obj
)
6381 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6383 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6384 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6387 mutex_unlock(&dev
->struct_mutex
);
6389 intel_crtc
->cursor_addr
= addr
;
6390 intel_crtc
->cursor_bo
= obj
;
6391 intel_crtc
->cursor_width
= width
;
6392 intel_crtc
->cursor_height
= height
;
6394 intel_crtc_update_cursor(crtc
, true);
6398 i915_gem_object_unpin(obj
);
6400 mutex_unlock(&dev
->struct_mutex
);
6402 drm_gem_object_unreference_unlocked(&obj
->base
);
6406 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6408 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6410 intel_crtc
->cursor_x
= x
;
6411 intel_crtc
->cursor_y
= y
;
6413 intel_crtc_update_cursor(crtc
, true);
6418 /** Sets the color ramps on behalf of RandR */
6419 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6420 u16 blue
, int regno
)
6422 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6424 intel_crtc
->lut_r
[regno
] = red
>> 8;
6425 intel_crtc
->lut_g
[regno
] = green
>> 8;
6426 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6429 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6430 u16
*blue
, int regno
)
6432 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6434 *red
= intel_crtc
->lut_r
[regno
] << 8;
6435 *green
= intel_crtc
->lut_g
[regno
] << 8;
6436 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6439 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6440 u16
*blue
, uint32_t start
, uint32_t size
)
6442 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6443 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6445 for (i
= start
; i
< end
; i
++) {
6446 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6447 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6448 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6451 intel_crtc_load_lut(crtc
);
6454 /* VESA 640x480x72Hz mode to set on the pipe */
6455 static struct drm_display_mode load_detect_mode
= {
6456 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6457 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6460 static struct drm_framebuffer
*
6461 intel_framebuffer_create(struct drm_device
*dev
,
6462 struct drm_mode_fb_cmd2
*mode_cmd
,
6463 struct drm_i915_gem_object
*obj
)
6465 struct intel_framebuffer
*intel_fb
;
6468 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6470 drm_gem_object_unreference_unlocked(&obj
->base
);
6471 return ERR_PTR(-ENOMEM
);
6474 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6476 drm_gem_object_unreference_unlocked(&obj
->base
);
6478 return ERR_PTR(ret
);
6481 return &intel_fb
->base
;
6485 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6487 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6488 return ALIGN(pitch
, 64);
6492 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6494 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6495 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6498 static struct drm_framebuffer
*
6499 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6500 struct drm_display_mode
*mode
,
6503 struct drm_i915_gem_object
*obj
;
6504 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6506 obj
= i915_gem_alloc_object(dev
,
6507 intel_framebuffer_size_for_mode(mode
, bpp
));
6509 return ERR_PTR(-ENOMEM
);
6511 mode_cmd
.width
= mode
->hdisplay
;
6512 mode_cmd
.height
= mode
->vdisplay
;
6513 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6515 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6517 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6520 static struct drm_framebuffer
*
6521 mode_fits_in_fbdev(struct drm_device
*dev
,
6522 struct drm_display_mode
*mode
)
6524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6525 struct drm_i915_gem_object
*obj
;
6526 struct drm_framebuffer
*fb
;
6528 if (dev_priv
->fbdev
== NULL
)
6531 obj
= dev_priv
->fbdev
->ifb
.obj
;
6535 fb
= &dev_priv
->fbdev
->ifb
.base
;
6536 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6537 fb
->bits_per_pixel
))
6540 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6546 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6547 struct drm_display_mode
*mode
,
6548 struct intel_load_detect_pipe
*old
)
6550 struct intel_crtc
*intel_crtc
;
6551 struct intel_encoder
*intel_encoder
=
6552 intel_attached_encoder(connector
);
6553 struct drm_crtc
*possible_crtc
;
6554 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6555 struct drm_crtc
*crtc
= NULL
;
6556 struct drm_device
*dev
= encoder
->dev
;
6557 struct drm_framebuffer
*fb
;
6560 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6561 connector
->base
.id
, drm_get_connector_name(connector
),
6562 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6565 * Algorithm gets a little messy:
6567 * - if the connector already has an assigned crtc, use it (but make
6568 * sure it's on first)
6570 * - try to find the first unused crtc that can drive this connector,
6571 * and use that if we find one
6574 /* See if we already have a CRTC for this connector */
6575 if (encoder
->crtc
) {
6576 crtc
= encoder
->crtc
;
6578 mutex_lock(&crtc
->mutex
);
6580 old
->dpms_mode
= connector
->dpms
;
6581 old
->load_detect_temp
= false;
6583 /* Make sure the crtc and connector are running */
6584 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6585 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6590 /* Find an unused one (if possible) */
6591 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6593 if (!(encoder
->possible_crtcs
& (1 << i
)))
6595 if (!possible_crtc
->enabled
) {
6596 crtc
= possible_crtc
;
6602 * If we didn't find an unused CRTC, don't use any.
6605 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6609 mutex_lock(&crtc
->mutex
);
6610 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6611 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6613 intel_crtc
= to_intel_crtc(crtc
);
6614 old
->dpms_mode
= connector
->dpms
;
6615 old
->load_detect_temp
= true;
6616 old
->release_fb
= NULL
;
6619 mode
= &load_detect_mode
;
6621 /* We need a framebuffer large enough to accommodate all accesses
6622 * that the plane may generate whilst we perform load detection.
6623 * We can not rely on the fbcon either being present (we get called
6624 * during its initialisation to detect all boot displays, or it may
6625 * not even exist) or that it is large enough to satisfy the
6628 fb
= mode_fits_in_fbdev(dev
, mode
);
6630 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6631 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6632 old
->release_fb
= fb
;
6634 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6636 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6637 mutex_unlock(&crtc
->mutex
);
6641 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6642 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6643 if (old
->release_fb
)
6644 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6645 mutex_unlock(&crtc
->mutex
);
6649 /* let the connector get through one full cycle before testing */
6650 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6654 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6655 struct intel_load_detect_pipe
*old
)
6657 struct intel_encoder
*intel_encoder
=
6658 intel_attached_encoder(connector
);
6659 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6660 struct drm_crtc
*crtc
= encoder
->crtc
;
6662 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6663 connector
->base
.id
, drm_get_connector_name(connector
),
6664 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6666 if (old
->load_detect_temp
) {
6667 to_intel_connector(connector
)->new_encoder
= NULL
;
6668 intel_encoder
->new_crtc
= NULL
;
6669 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6671 if (old
->release_fb
) {
6672 drm_framebuffer_unregister_private(old
->release_fb
);
6673 drm_framebuffer_unreference(old
->release_fb
);
6676 mutex_unlock(&crtc
->mutex
);
6680 /* Switch crtc and encoder back off if necessary */
6681 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6682 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6684 mutex_unlock(&crtc
->mutex
);
6687 /* Returns the clock of the currently programmed mode of the given pipe. */
6688 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6691 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6692 int pipe
= intel_crtc
->pipe
;
6693 u32 dpll
= I915_READ(DPLL(pipe
));
6695 intel_clock_t clock
;
6697 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6698 fp
= I915_READ(FP0(pipe
));
6700 fp
= I915_READ(FP1(pipe
));
6702 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6703 if (IS_PINEVIEW(dev
)) {
6704 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6705 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6707 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6708 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6711 if (!IS_GEN2(dev
)) {
6712 if (IS_PINEVIEW(dev
))
6713 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6714 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6716 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6717 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6719 switch (dpll
& DPLL_MODE_MASK
) {
6720 case DPLLB_MODE_DAC_SERIAL
:
6721 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6724 case DPLLB_MODE_LVDS
:
6725 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6729 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6730 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6734 /* XXX: Handle the 100Mhz refclk */
6735 intel_clock(dev
, 96000, &clock
);
6737 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6740 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6741 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6744 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6745 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6746 /* XXX: might not be 66MHz */
6747 intel_clock(dev
, 66000, &clock
);
6749 intel_clock(dev
, 48000, &clock
);
6751 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6754 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6755 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6757 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6762 intel_clock(dev
, 48000, &clock
);
6766 /* XXX: It would be nice to validate the clocks, but we can't reuse
6767 * i830PllIsValid() because it relies on the xf86_config connector
6768 * configuration being accurate, which it isn't necessarily.
6774 /** Returns the currently programmed mode of the given pipe. */
6775 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6776 struct drm_crtc
*crtc
)
6778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6779 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6780 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
6781 struct drm_display_mode
*mode
;
6782 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6783 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6784 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6785 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6787 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6791 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6792 mode
->hdisplay
= (htot
& 0xffff) + 1;
6793 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6794 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6795 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6796 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6797 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6798 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6799 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6801 drm_mode_set_name(mode
);
6806 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6808 struct drm_device
*dev
= crtc
->dev
;
6809 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6810 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6811 int pipe
= intel_crtc
->pipe
;
6812 int dpll_reg
= DPLL(pipe
);
6815 if (HAS_PCH_SPLIT(dev
))
6818 if (!dev_priv
->lvds_downclock_avail
)
6821 dpll
= I915_READ(dpll_reg
);
6822 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6823 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6825 assert_panel_unlocked(dev_priv
, pipe
);
6827 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6828 I915_WRITE(dpll_reg
, dpll
);
6829 intel_wait_for_vblank(dev
, pipe
);
6831 dpll
= I915_READ(dpll_reg
);
6832 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6833 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6837 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6839 struct drm_device
*dev
= crtc
->dev
;
6840 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6841 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6843 if (HAS_PCH_SPLIT(dev
))
6846 if (!dev_priv
->lvds_downclock_avail
)
6850 * Since this is called by a timer, we should never get here in
6853 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6854 int pipe
= intel_crtc
->pipe
;
6855 int dpll_reg
= DPLL(pipe
);
6858 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6860 assert_panel_unlocked(dev_priv
, pipe
);
6862 dpll
= I915_READ(dpll_reg
);
6863 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6864 I915_WRITE(dpll_reg
, dpll
);
6865 intel_wait_for_vblank(dev
, pipe
);
6866 dpll
= I915_READ(dpll_reg
);
6867 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6868 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6873 void intel_mark_busy(struct drm_device
*dev
)
6875 i915_update_gfx_val(dev
->dev_private
);
6878 void intel_mark_idle(struct drm_device
*dev
)
6880 struct drm_crtc
*crtc
;
6882 if (!i915_powersave
)
6885 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6889 intel_decrease_pllclock(crtc
);
6893 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6895 struct drm_device
*dev
= obj
->base
.dev
;
6896 struct drm_crtc
*crtc
;
6898 if (!i915_powersave
)
6901 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6905 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6906 intel_increase_pllclock(crtc
);
6910 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6912 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6913 struct drm_device
*dev
= crtc
->dev
;
6914 struct intel_unpin_work
*work
;
6915 unsigned long flags
;
6917 spin_lock_irqsave(&dev
->event_lock
, flags
);
6918 work
= intel_crtc
->unpin_work
;
6919 intel_crtc
->unpin_work
= NULL
;
6920 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6923 cancel_work_sync(&work
->work
);
6927 drm_crtc_cleanup(crtc
);
6932 static void intel_unpin_work_fn(struct work_struct
*__work
)
6934 struct intel_unpin_work
*work
=
6935 container_of(__work
, struct intel_unpin_work
, work
);
6936 struct drm_device
*dev
= work
->crtc
->dev
;
6938 mutex_lock(&dev
->struct_mutex
);
6939 intel_unpin_fb_obj(work
->old_fb_obj
);
6940 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6941 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6943 intel_update_fbc(dev
);
6944 mutex_unlock(&dev
->struct_mutex
);
6946 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
6947 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
6952 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6953 struct drm_crtc
*crtc
)
6955 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6956 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6957 struct intel_unpin_work
*work
;
6958 unsigned long flags
;
6960 /* Ignore early vblank irqs */
6961 if (intel_crtc
== NULL
)
6964 spin_lock_irqsave(&dev
->event_lock
, flags
);
6965 work
= intel_crtc
->unpin_work
;
6967 /* Ensure we don't miss a work->pending update ... */
6970 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
6971 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6975 /* and that the unpin work is consistent wrt ->pending. */
6978 intel_crtc
->unpin_work
= NULL
;
6981 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
6983 drm_vblank_put(dev
, intel_crtc
->pipe
);
6985 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6987 wake_up_all(&dev_priv
->pending_flip_queue
);
6989 queue_work(dev_priv
->wq
, &work
->work
);
6991 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6994 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6996 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6997 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6999 do_intel_finish_page_flip(dev
, crtc
);
7002 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7004 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7005 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7007 do_intel_finish_page_flip(dev
, crtc
);
7010 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7012 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7013 struct intel_crtc
*intel_crtc
=
7014 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7015 unsigned long flags
;
7017 /* NB: An MMIO update of the plane base pointer will also
7018 * generate a page-flip completion irq, i.e. every modeset
7019 * is also accompanied by a spurious intel_prepare_page_flip().
7021 spin_lock_irqsave(&dev
->event_lock
, flags
);
7022 if (intel_crtc
->unpin_work
)
7023 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7024 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7027 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7029 /* Ensure that the work item is consistent when activating it ... */
7031 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7032 /* and that it is marked active as soon as the irq could fire. */
7036 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7037 struct drm_crtc
*crtc
,
7038 struct drm_framebuffer
*fb
,
7039 struct drm_i915_gem_object
*obj
)
7041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7042 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7044 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7047 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7051 ret
= intel_ring_begin(ring
, 6);
7055 /* Can't queue multiple flips, so wait for the previous
7056 * one to finish before executing the next.
7058 if (intel_crtc
->plane
)
7059 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7061 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7062 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7063 intel_ring_emit(ring
, MI_NOOP
);
7064 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7065 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7066 intel_ring_emit(ring
, fb
->pitches
[0]);
7067 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7068 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7070 intel_mark_page_flip_active(intel_crtc
);
7071 intel_ring_advance(ring
);
7075 intel_unpin_fb_obj(obj
);
7080 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7081 struct drm_crtc
*crtc
,
7082 struct drm_framebuffer
*fb
,
7083 struct drm_i915_gem_object
*obj
)
7085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7086 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7088 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7091 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7095 ret
= intel_ring_begin(ring
, 6);
7099 if (intel_crtc
->plane
)
7100 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7102 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7103 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7104 intel_ring_emit(ring
, MI_NOOP
);
7105 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7106 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7107 intel_ring_emit(ring
, fb
->pitches
[0]);
7108 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7109 intel_ring_emit(ring
, MI_NOOP
);
7111 intel_mark_page_flip_active(intel_crtc
);
7112 intel_ring_advance(ring
);
7116 intel_unpin_fb_obj(obj
);
7121 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7122 struct drm_crtc
*crtc
,
7123 struct drm_framebuffer
*fb
,
7124 struct drm_i915_gem_object
*obj
)
7126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7127 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7128 uint32_t pf
, pipesrc
;
7129 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7132 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7136 ret
= intel_ring_begin(ring
, 4);
7140 /* i965+ uses the linear or tiled offsets from the
7141 * Display Registers (which do not change across a page-flip)
7142 * so we need only reprogram the base address.
7144 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7145 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7146 intel_ring_emit(ring
, fb
->pitches
[0]);
7147 intel_ring_emit(ring
,
7148 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
7151 /* XXX Enabling the panel-fitter across page-flip is so far
7152 * untested on non-native modes, so ignore it for now.
7153 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7156 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7157 intel_ring_emit(ring
, pf
| pipesrc
);
7159 intel_mark_page_flip_active(intel_crtc
);
7160 intel_ring_advance(ring
);
7164 intel_unpin_fb_obj(obj
);
7169 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7170 struct drm_crtc
*crtc
,
7171 struct drm_framebuffer
*fb
,
7172 struct drm_i915_gem_object
*obj
)
7174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7175 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7176 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7177 uint32_t pf
, pipesrc
;
7180 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7184 ret
= intel_ring_begin(ring
, 4);
7188 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7189 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7190 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7191 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7193 /* Contrary to the suggestions in the documentation,
7194 * "Enable Panel Fitter" does not seem to be required when page
7195 * flipping with a non-native mode, and worse causes a normal
7197 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7200 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7201 intel_ring_emit(ring
, pf
| pipesrc
);
7203 intel_mark_page_flip_active(intel_crtc
);
7204 intel_ring_advance(ring
);
7208 intel_unpin_fb_obj(obj
);
7214 * On gen7 we currently use the blit ring because (in early silicon at least)
7215 * the render ring doesn't give us interrpts for page flip completion, which
7216 * means clients will hang after the first flip is queued. Fortunately the
7217 * blit ring generates interrupts properly, so use it instead.
7219 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7220 struct drm_crtc
*crtc
,
7221 struct drm_framebuffer
*fb
,
7222 struct drm_i915_gem_object
*obj
)
7224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7225 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7226 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7227 uint32_t plane_bit
= 0;
7230 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7234 switch(intel_crtc
->plane
) {
7236 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7239 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7242 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7245 WARN_ONCE(1, "unknown plane in flip command\n");
7250 ret
= intel_ring_begin(ring
, 4);
7254 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7255 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7256 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7257 intel_ring_emit(ring
, (MI_NOOP
));
7259 intel_mark_page_flip_active(intel_crtc
);
7260 intel_ring_advance(ring
);
7264 intel_unpin_fb_obj(obj
);
7269 static int intel_default_queue_flip(struct drm_device
*dev
,
7270 struct drm_crtc
*crtc
,
7271 struct drm_framebuffer
*fb
,
7272 struct drm_i915_gem_object
*obj
)
7277 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7278 struct drm_framebuffer
*fb
,
7279 struct drm_pending_vblank_event
*event
)
7281 struct drm_device
*dev
= crtc
->dev
;
7282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7283 struct intel_framebuffer
*intel_fb
;
7284 struct drm_i915_gem_object
*obj
;
7285 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7286 struct intel_unpin_work
*work
;
7287 unsigned long flags
;
7290 /* Can't change pixel format via MI display flips. */
7291 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7295 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7296 * Note that pitch changes could also affect these register.
7298 if (INTEL_INFO(dev
)->gen
> 3 &&
7299 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7300 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7303 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7307 work
->event
= event
;
7309 intel_fb
= to_intel_framebuffer(crtc
->fb
);
7310 work
->old_fb_obj
= intel_fb
->obj
;
7311 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7313 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7317 /* We borrow the event spin lock for protecting unpin_work */
7318 spin_lock_irqsave(&dev
->event_lock
, flags
);
7319 if (intel_crtc
->unpin_work
) {
7320 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7322 drm_vblank_put(dev
, intel_crtc
->pipe
);
7324 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7327 intel_crtc
->unpin_work
= work
;
7328 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7330 intel_fb
= to_intel_framebuffer(fb
);
7331 obj
= intel_fb
->obj
;
7333 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7334 flush_workqueue(dev_priv
->wq
);
7336 ret
= i915_mutex_lock_interruptible(dev
);
7340 /* Reference the objects for the scheduled work. */
7341 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7342 drm_gem_object_reference(&obj
->base
);
7346 work
->pending_flip_obj
= obj
;
7348 work
->enable_stall_check
= true;
7350 atomic_inc(&intel_crtc
->unpin_work_count
);
7351 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
7353 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7355 goto cleanup_pending
;
7357 intel_disable_fbc(dev
);
7358 intel_mark_fb_busy(obj
);
7359 mutex_unlock(&dev
->struct_mutex
);
7361 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7366 atomic_dec(&intel_crtc
->unpin_work_count
);
7367 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7368 drm_gem_object_unreference(&obj
->base
);
7369 mutex_unlock(&dev
->struct_mutex
);
7372 spin_lock_irqsave(&dev
->event_lock
, flags
);
7373 intel_crtc
->unpin_work
= NULL
;
7374 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7376 drm_vblank_put(dev
, intel_crtc
->pipe
);
7383 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7384 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7385 .load_lut
= intel_crtc_load_lut
,
7386 .disable
= intel_crtc_noop
,
7389 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7391 struct intel_encoder
*other_encoder
;
7392 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7397 list_for_each_entry(other_encoder
,
7398 &crtc
->dev
->mode_config
.encoder_list
,
7401 if (&other_encoder
->new_crtc
->base
!= crtc
||
7402 encoder
== other_encoder
)
7411 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7412 struct drm_crtc
*crtc
)
7414 struct drm_device
*dev
;
7415 struct drm_crtc
*tmp
;
7418 WARN(!crtc
, "checking null crtc?\n");
7422 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7428 if (encoder
->possible_crtcs
& crtc_mask
)
7434 * intel_modeset_update_staged_output_state
7436 * Updates the staged output configuration state, e.g. after we've read out the
7439 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7441 struct intel_encoder
*encoder
;
7442 struct intel_connector
*connector
;
7444 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7446 connector
->new_encoder
=
7447 to_intel_encoder(connector
->base
.encoder
);
7450 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7453 to_intel_crtc(encoder
->base
.crtc
);
7458 * intel_modeset_commit_output_state
7460 * This function copies the stage display pipe configuration to the real one.
7462 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7464 struct intel_encoder
*encoder
;
7465 struct intel_connector
*connector
;
7467 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7469 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7472 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7474 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7478 static struct drm_display_mode
*
7479 intel_modeset_adjusted_mode(struct drm_crtc
*crtc
,
7480 struct drm_display_mode
*mode
)
7482 struct drm_device
*dev
= crtc
->dev
;
7483 struct drm_display_mode
*adjusted_mode
;
7484 struct drm_encoder_helper_funcs
*encoder_funcs
;
7485 struct intel_encoder
*encoder
;
7487 adjusted_mode
= drm_mode_duplicate(dev
, mode
);
7489 return ERR_PTR(-ENOMEM
);
7491 /* Pass our mode to the connectors and the CRTC to give them a chance to
7492 * adjust it according to limitations or connector properties, and also
7493 * a chance to reject the mode entirely.
7495 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7498 if (&encoder
->new_crtc
->base
!= crtc
)
7500 encoder_funcs
= encoder
->base
.helper_private
;
7501 if (!(encoder_funcs
->mode_fixup(&encoder
->base
, mode
,
7503 DRM_DEBUG_KMS("Encoder fixup failed\n");
7508 if (!(intel_crtc_mode_fixup(crtc
, mode
, adjusted_mode
))) {
7509 DRM_DEBUG_KMS("CRTC fixup failed\n");
7512 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7514 return adjusted_mode
;
7516 drm_mode_destroy(dev
, adjusted_mode
);
7517 return ERR_PTR(-EINVAL
);
7520 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7521 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7523 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7524 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7526 struct intel_crtc
*intel_crtc
;
7527 struct drm_device
*dev
= crtc
->dev
;
7528 struct intel_encoder
*encoder
;
7529 struct intel_connector
*connector
;
7530 struct drm_crtc
*tmp_crtc
;
7532 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7534 /* Check which crtcs have changed outputs connected to them, these need
7535 * to be part of the prepare_pipes mask. We don't (yet) support global
7536 * modeset across multiple crtcs, so modeset_pipes will only have one
7537 * bit set at most. */
7538 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7540 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7543 if (connector
->base
.encoder
) {
7544 tmp_crtc
= connector
->base
.encoder
->crtc
;
7546 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7549 if (connector
->new_encoder
)
7551 1 << connector
->new_encoder
->new_crtc
->pipe
;
7554 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7556 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7559 if (encoder
->base
.crtc
) {
7560 tmp_crtc
= encoder
->base
.crtc
;
7562 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7565 if (encoder
->new_crtc
)
7566 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7569 /* Check for any pipes that will be fully disabled ... */
7570 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7574 /* Don't try to disable disabled crtcs. */
7575 if (!intel_crtc
->base
.enabled
)
7578 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7580 if (encoder
->new_crtc
== intel_crtc
)
7585 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7589 /* set_mode is also used to update properties on life display pipes. */
7590 intel_crtc
= to_intel_crtc(crtc
);
7592 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7594 /* We only support modeset on one single crtc, hence we need to do that
7595 * only for the passed in crtc iff we change anything else than just
7598 * This is actually not true, to be fully compatible with the old crtc
7599 * helper we automatically disable _any_ output (i.e. doesn't need to be
7600 * connected to the crtc we're modesetting on) if it's disconnected.
7601 * Which is a rather nutty api (since changed the output configuration
7602 * without userspace's explicit request can lead to confusion), but
7603 * alas. Hence we currently need to modeset on all pipes we prepare. */
7605 *modeset_pipes
= *prepare_pipes
;
7607 /* ... and mask these out. */
7608 *modeset_pipes
&= ~(*disable_pipes
);
7609 *prepare_pipes
&= ~(*disable_pipes
);
7612 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7614 struct drm_encoder
*encoder
;
7615 struct drm_device
*dev
= crtc
->dev
;
7617 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7618 if (encoder
->crtc
== crtc
)
7625 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7627 struct intel_encoder
*intel_encoder
;
7628 struct intel_crtc
*intel_crtc
;
7629 struct drm_connector
*connector
;
7631 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7633 if (!intel_encoder
->base
.crtc
)
7636 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7638 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7639 intel_encoder
->connectors_active
= false;
7642 intel_modeset_commit_output_state(dev
);
7644 /* Update computed state. */
7645 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7647 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7650 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7651 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7654 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7656 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7657 struct drm_property
*dpms_property
=
7658 dev
->mode_config
.dpms_property
;
7660 connector
->dpms
= DRM_MODE_DPMS_ON
;
7661 drm_object_property_set_value(&connector
->base
,
7665 intel_encoder
= to_intel_encoder(connector
->encoder
);
7666 intel_encoder
->connectors_active
= true;
7672 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7673 list_for_each_entry((intel_crtc), \
7674 &(dev)->mode_config.crtc_list, \
7676 if (mask & (1 <<(intel_crtc)->pipe)) \
7679 intel_modeset_check_state(struct drm_device
*dev
)
7681 struct intel_crtc
*crtc
;
7682 struct intel_encoder
*encoder
;
7683 struct intel_connector
*connector
;
7685 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7687 /* This also checks the encoder/connector hw state with the
7688 * ->get_hw_state callbacks. */
7689 intel_connector_check_state(connector
);
7691 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7692 "connector's staged encoder doesn't match current encoder\n");
7695 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7697 bool enabled
= false;
7698 bool active
= false;
7699 enum pipe pipe
, tracked_pipe
;
7701 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7702 encoder
->base
.base
.id
,
7703 drm_get_encoder_name(&encoder
->base
));
7705 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7706 "encoder's stage crtc doesn't match current crtc\n");
7707 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7708 "encoder's active_connectors set, but no crtc\n");
7710 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7712 if (connector
->base
.encoder
!= &encoder
->base
)
7715 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7718 WARN(!!encoder
->base
.crtc
!= enabled
,
7719 "encoder's enabled state mismatch "
7720 "(expected %i, found %i)\n",
7721 !!encoder
->base
.crtc
, enabled
);
7722 WARN(active
&& !encoder
->base
.crtc
,
7723 "active encoder with no crtc\n");
7725 WARN(encoder
->connectors_active
!= active
,
7726 "encoder's computed active state doesn't match tracked active state "
7727 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7729 active
= encoder
->get_hw_state(encoder
, &pipe
);
7730 WARN(active
!= encoder
->connectors_active
,
7731 "encoder's hw state doesn't match sw tracking "
7732 "(expected %i, found %i)\n",
7733 encoder
->connectors_active
, active
);
7735 if (!encoder
->base
.crtc
)
7738 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7739 WARN(active
&& pipe
!= tracked_pipe
,
7740 "active encoder's pipe doesn't match"
7741 "(expected %i, found %i)\n",
7742 tracked_pipe
, pipe
);
7746 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7748 bool enabled
= false;
7749 bool active
= false;
7751 DRM_DEBUG_KMS("[CRTC:%d]\n",
7752 crtc
->base
.base
.id
);
7754 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7755 "active crtc, but not enabled in sw tracking\n");
7757 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7759 if (encoder
->base
.crtc
!= &crtc
->base
)
7762 if (encoder
->connectors_active
)
7765 WARN(active
!= crtc
->active
,
7766 "crtc's computed active state doesn't match tracked active state "
7767 "(expected %i, found %i)\n", active
, crtc
->active
);
7768 WARN(enabled
!= crtc
->base
.enabled
,
7769 "crtc's computed enabled state doesn't match tracked enabled state "
7770 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7772 assert_pipe(dev
->dev_private
, crtc
->pipe
, crtc
->active
);
7776 int intel_set_mode(struct drm_crtc
*crtc
,
7777 struct drm_display_mode
*mode
,
7778 int x
, int y
, struct drm_framebuffer
*fb
)
7780 struct drm_device
*dev
= crtc
->dev
;
7781 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7782 struct drm_display_mode
*adjusted_mode
, *saved_mode
, *saved_hwmode
;
7783 struct intel_crtc
*intel_crtc
;
7784 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7787 saved_mode
= kmalloc(2 * sizeof(*saved_mode
), GFP_KERNEL
);
7790 saved_hwmode
= saved_mode
+ 1;
7792 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7793 &prepare_pipes
, &disable_pipes
);
7795 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7796 modeset_pipes
, prepare_pipes
, disable_pipes
);
7798 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7799 intel_crtc_disable(&intel_crtc
->base
);
7801 *saved_hwmode
= crtc
->hwmode
;
7802 *saved_mode
= crtc
->mode
;
7804 /* Hack: Because we don't (yet) support global modeset on multiple
7805 * crtcs, we don't keep track of the new mode for more than one crtc.
7806 * Hence simply check whether any bit is set in modeset_pipes in all the
7807 * pieces of code that are not yet converted to deal with mutliple crtcs
7808 * changing their mode at the same time. */
7809 adjusted_mode
= NULL
;
7810 if (modeset_pipes
) {
7811 adjusted_mode
= intel_modeset_adjusted_mode(crtc
, mode
);
7812 if (IS_ERR(adjusted_mode
)) {
7813 ret
= PTR_ERR(adjusted_mode
);
7818 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7819 if (intel_crtc
->base
.enabled
)
7820 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7823 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7824 * to set it here already despite that we pass it down the callchain.
7829 /* Only after disabling all output pipelines that will be changed can we
7830 * update the the output configuration. */
7831 intel_modeset_update_state(dev
, prepare_pipes
);
7833 if (dev_priv
->display
.modeset_global_resources
)
7834 dev_priv
->display
.modeset_global_resources(dev
);
7836 /* Set up the DPLL and any encoders state that needs to adjust or depend
7839 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
7840 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
7841 mode
, adjusted_mode
,
7847 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7848 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
7849 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
7851 if (modeset_pipes
) {
7852 /* Store real post-adjustment hardware mode. */
7853 crtc
->hwmode
= *adjusted_mode
;
7855 /* Calculate and store various constants which
7856 * are later needed by vblank and swap-completion
7857 * timestamping. They are derived from true hwmode.
7859 drm_calc_timestamping_constants(crtc
);
7862 /* FIXME: add subpixel order */
7864 drm_mode_destroy(dev
, adjusted_mode
);
7865 if (ret
&& crtc
->enabled
) {
7866 crtc
->hwmode
= *saved_hwmode
;
7867 crtc
->mode
= *saved_mode
;
7869 intel_modeset_check_state(dev
);
7877 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
7879 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
7882 #undef for_each_intel_crtc_masked
7884 static void intel_set_config_free(struct intel_set_config
*config
)
7889 kfree(config
->save_connector_encoders
);
7890 kfree(config
->save_encoder_crtcs
);
7894 static int intel_set_config_save_state(struct drm_device
*dev
,
7895 struct intel_set_config
*config
)
7897 struct drm_encoder
*encoder
;
7898 struct drm_connector
*connector
;
7901 config
->save_encoder_crtcs
=
7902 kcalloc(dev
->mode_config
.num_encoder
,
7903 sizeof(struct drm_crtc
*), GFP_KERNEL
);
7904 if (!config
->save_encoder_crtcs
)
7907 config
->save_connector_encoders
=
7908 kcalloc(dev
->mode_config
.num_connector
,
7909 sizeof(struct drm_encoder
*), GFP_KERNEL
);
7910 if (!config
->save_connector_encoders
)
7913 /* Copy data. Note that driver private data is not affected.
7914 * Should anything bad happen only the expected state is
7915 * restored, not the drivers personal bookkeeping.
7918 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7919 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
7923 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7924 config
->save_connector_encoders
[count
++] = connector
->encoder
;
7930 static void intel_set_config_restore_state(struct drm_device
*dev
,
7931 struct intel_set_config
*config
)
7933 struct intel_encoder
*encoder
;
7934 struct intel_connector
*connector
;
7938 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7940 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
7944 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
7945 connector
->new_encoder
=
7946 to_intel_encoder(config
->save_connector_encoders
[count
++]);
7951 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
7952 struct intel_set_config
*config
)
7955 /* We should be able to check here if the fb has the same properties
7956 * and then just flip_or_move it */
7957 if (set
->crtc
->fb
!= set
->fb
) {
7958 /* If we have no fb then treat it as a full mode set */
7959 if (set
->crtc
->fb
== NULL
) {
7960 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7961 config
->mode_changed
= true;
7962 } else if (set
->fb
== NULL
) {
7963 config
->mode_changed
= true;
7964 } else if (set
->fb
->depth
!= set
->crtc
->fb
->depth
) {
7965 config
->mode_changed
= true;
7966 } else if (set
->fb
->bits_per_pixel
!=
7967 set
->crtc
->fb
->bits_per_pixel
) {
7968 config
->mode_changed
= true;
7970 config
->fb_changed
= true;
7973 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
7974 config
->fb_changed
= true;
7976 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
7977 DRM_DEBUG_KMS("modes are different, full mode set\n");
7978 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
7979 drm_mode_debug_printmodeline(set
->mode
);
7980 config
->mode_changed
= true;
7985 intel_modeset_stage_output_state(struct drm_device
*dev
,
7986 struct drm_mode_set
*set
,
7987 struct intel_set_config
*config
)
7989 struct drm_crtc
*new_crtc
;
7990 struct intel_connector
*connector
;
7991 struct intel_encoder
*encoder
;
7994 /* The upper layers ensure that we either disable a crtc or have a list
7995 * of connectors. For paranoia, double-check this. */
7996 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
7997 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
8000 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8002 /* Otherwise traverse passed in connector list and get encoders
8004 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8005 if (set
->connectors
[ro
] == &connector
->base
) {
8006 connector
->new_encoder
= connector
->encoder
;
8011 /* If we disable the crtc, disable all its connectors. Also, if
8012 * the connector is on the changing crtc but not on the new
8013 * connector list, disable it. */
8014 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
8015 connector
->base
.encoder
&&
8016 connector
->base
.encoder
->crtc
== set
->crtc
) {
8017 connector
->new_encoder
= NULL
;
8019 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8020 connector
->base
.base
.id
,
8021 drm_get_connector_name(&connector
->base
));
8025 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
8026 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8027 config
->mode_changed
= true;
8030 /* connector->new_encoder is now updated for all connectors. */
8032 /* Update crtc of enabled connectors. */
8034 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8036 if (!connector
->new_encoder
)
8039 new_crtc
= connector
->new_encoder
->base
.crtc
;
8041 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
8042 if (set
->connectors
[ro
] == &connector
->base
)
8043 new_crtc
= set
->crtc
;
8046 /* Make sure the new CRTC will work with the encoder */
8047 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
8051 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
8053 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8054 connector
->base
.base
.id
,
8055 drm_get_connector_name(&connector
->base
),
8059 /* Check for any encoders that needs to be disabled. */
8060 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8062 list_for_each_entry(connector
,
8063 &dev
->mode_config
.connector_list
,
8065 if (connector
->new_encoder
== encoder
) {
8066 WARN_ON(!connector
->new_encoder
->new_crtc
);
8071 encoder
->new_crtc
= NULL
;
8073 /* Only now check for crtc changes so we don't miss encoders
8074 * that will be disabled. */
8075 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8076 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8077 config
->mode_changed
= true;
8080 /* Now we've also updated encoder->new_crtc for all encoders. */
8085 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8087 struct drm_device
*dev
;
8088 struct drm_mode_set save_set
;
8089 struct intel_set_config
*config
;
8094 BUG_ON(!set
->crtc
->helper_private
);
8099 /* The fb helper likes to play gross jokes with ->mode_set_config.
8100 * Unfortunately the crtc helper doesn't do much at all for this case,
8101 * so we have to cope with this madness until the fb helper is fixed up. */
8102 if (set
->fb
&& set
->num_connectors
== 0)
8106 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8107 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8108 (int)set
->num_connectors
, set
->x
, set
->y
);
8110 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8113 dev
= set
->crtc
->dev
;
8116 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8120 ret
= intel_set_config_save_state(dev
, config
);
8124 save_set
.crtc
= set
->crtc
;
8125 save_set
.mode
= &set
->crtc
->mode
;
8126 save_set
.x
= set
->crtc
->x
;
8127 save_set
.y
= set
->crtc
->y
;
8128 save_set
.fb
= set
->crtc
->fb
;
8130 /* Compute whether we need a full modeset, only an fb base update or no
8131 * change at all. In the future we might also check whether only the
8132 * mode changed, e.g. for LVDS where we only change the panel fitter in
8134 intel_set_config_compute_mode_changes(set
, config
);
8136 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8140 if (config
->mode_changed
) {
8142 DRM_DEBUG_KMS("attempting to set mode from"
8144 drm_mode_debug_printmodeline(set
->mode
);
8147 ret
= intel_set_mode(set
->crtc
, set
->mode
,
8148 set
->x
, set
->y
, set
->fb
);
8150 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8151 set
->crtc
->base
.id
, ret
);
8154 } else if (config
->fb_changed
) {
8155 intel_crtc_wait_for_pending_flips(set
->crtc
);
8157 ret
= intel_pipe_set_base(set
->crtc
,
8158 set
->x
, set
->y
, set
->fb
);
8161 intel_set_config_free(config
);
8166 intel_set_config_restore_state(dev
, config
);
8168 /* Try to restore the config */
8169 if (config
->mode_changed
&&
8170 intel_set_mode(save_set
.crtc
, save_set
.mode
,
8171 save_set
.x
, save_set
.y
, save_set
.fb
))
8172 DRM_ERROR("failed to restore config after modeset failure\n");
8175 intel_set_config_free(config
);
8179 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8180 .cursor_set
= intel_crtc_cursor_set
,
8181 .cursor_move
= intel_crtc_cursor_move
,
8182 .gamma_set
= intel_crtc_gamma_set
,
8183 .set_config
= intel_crtc_set_config
,
8184 .destroy
= intel_crtc_destroy
,
8185 .page_flip
= intel_crtc_page_flip
,
8188 static void intel_cpu_pll_init(struct drm_device
*dev
)
8191 intel_ddi_pll_init(dev
);
8194 static void intel_pch_pll_init(struct drm_device
*dev
)
8196 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8199 if (dev_priv
->num_pch_pll
== 0) {
8200 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8204 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
8205 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
8206 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
8207 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
8211 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8213 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8214 struct intel_crtc
*intel_crtc
;
8217 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8218 if (intel_crtc
== NULL
)
8221 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8223 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8224 for (i
= 0; i
< 256; i
++) {
8225 intel_crtc
->lut_r
[i
] = i
;
8226 intel_crtc
->lut_g
[i
] = i
;
8227 intel_crtc
->lut_b
[i
] = i
;
8230 /* Swap pipes & planes for FBC on pre-965 */
8231 intel_crtc
->pipe
= pipe
;
8232 intel_crtc
->plane
= pipe
;
8233 intel_crtc
->cpu_transcoder
= pipe
;
8234 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8235 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8236 intel_crtc
->plane
= !pipe
;
8239 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8240 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8241 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8242 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8244 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
8246 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8249 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8250 struct drm_file
*file
)
8252 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8253 struct drm_mode_object
*drmmode_obj
;
8254 struct intel_crtc
*crtc
;
8256 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8259 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8260 DRM_MODE_OBJECT_CRTC
);
8263 DRM_ERROR("no such CRTC id\n");
8267 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8268 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8273 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8275 struct drm_device
*dev
= encoder
->base
.dev
;
8276 struct intel_encoder
*source_encoder
;
8280 list_for_each_entry(source_encoder
,
8281 &dev
->mode_config
.encoder_list
, base
.head
) {
8283 if (encoder
== source_encoder
)
8284 index_mask
|= (1 << entry
);
8286 /* Intel hw has only one MUX where enocoders could be cloned. */
8287 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8288 index_mask
|= (1 << entry
);
8296 static bool has_edp_a(struct drm_device
*dev
)
8298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8300 if (!IS_MOBILE(dev
))
8303 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8307 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8313 static void intel_setup_outputs(struct drm_device
*dev
)
8315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8316 struct intel_encoder
*encoder
;
8317 bool dpd_is_edp
= false;
8320 has_lvds
= intel_lvds_init(dev
);
8321 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8322 /* disable the panel fitter on everything but LVDS */
8323 I915_WRITE(PFIT_CONTROL
, 0);
8326 if (!(HAS_DDI(dev
) && (I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)))
8327 intel_crt_init(dev
);
8332 /* Haswell uses DDI functions to detect digital outputs */
8333 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8334 /* DDI A only supports eDP */
8336 intel_ddi_init(dev
, PORT_A
);
8338 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8340 found
= I915_READ(SFUSE_STRAP
);
8342 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8343 intel_ddi_init(dev
, PORT_B
);
8344 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8345 intel_ddi_init(dev
, PORT_C
);
8346 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8347 intel_ddi_init(dev
, PORT_D
);
8348 } else if (HAS_PCH_SPLIT(dev
)) {
8350 dpd_is_edp
= intel_dpd_is_edp(dev
);
8353 intel_dp_init(dev
, DP_A
, PORT_A
);
8355 if (I915_READ(PCH_HDMIB
) & PORT_DETECTED
) {
8356 /* PCH SDVOB multiplex with HDMIB */
8357 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8359 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
8360 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8361 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8364 if (I915_READ(PCH_HDMIC
) & PORT_DETECTED
)
8365 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
8367 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & PORT_DETECTED
)
8368 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
8370 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8371 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8373 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
8374 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8375 } else if (IS_VALLEYVIEW(dev
)) {
8376 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8377 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
8378 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
8380 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & PORT_DETECTED
) {
8381 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
8383 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
8384 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
8387 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & PORT_DETECTED
)
8388 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
8391 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8394 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8395 DRM_DEBUG_KMS("probing SDVOB\n");
8396 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
8397 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8398 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8399 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
8402 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8403 DRM_DEBUG_KMS("probing DP_B\n");
8404 intel_dp_init(dev
, DP_B
, PORT_B
);
8408 /* Before G4X SDVOC doesn't have its own detect register */
8410 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
8411 DRM_DEBUG_KMS("probing SDVOC\n");
8412 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
8415 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
8417 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8418 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8419 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
8421 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8422 DRM_DEBUG_KMS("probing DP_C\n");
8423 intel_dp_init(dev
, DP_C
, PORT_C
);
8427 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8428 (I915_READ(DP_D
) & DP_DETECTED
)) {
8429 DRM_DEBUG_KMS("probing DP_D\n");
8430 intel_dp_init(dev
, DP_D
, PORT_D
);
8432 } else if (IS_GEN2(dev
))
8433 intel_dvo_init(dev
);
8435 if (SUPPORTS_TV(dev
))
8438 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8439 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8440 encoder
->base
.possible_clones
=
8441 intel_encoder_clones(encoder
);
8444 intel_init_pch_refclk(dev
);
8446 drm_helper_move_panel_connectors_to_head(dev
);
8449 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8451 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8453 drm_framebuffer_cleanup(fb
);
8454 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8459 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8460 struct drm_file
*file
,
8461 unsigned int *handle
)
8463 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8464 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8466 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8469 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8470 .destroy
= intel_user_framebuffer_destroy
,
8471 .create_handle
= intel_user_framebuffer_create_handle
,
8474 int intel_framebuffer_init(struct drm_device
*dev
,
8475 struct intel_framebuffer
*intel_fb
,
8476 struct drm_mode_fb_cmd2
*mode_cmd
,
8477 struct drm_i915_gem_object
*obj
)
8481 if (obj
->tiling_mode
== I915_TILING_Y
) {
8482 DRM_DEBUG("hardware does not support tiling Y\n");
8486 if (mode_cmd
->pitches
[0] & 63) {
8487 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8488 mode_cmd
->pitches
[0]);
8492 /* FIXME <= Gen4 stride limits are bit unclear */
8493 if (mode_cmd
->pitches
[0] > 32768) {
8494 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8495 mode_cmd
->pitches
[0]);
8499 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
8500 mode_cmd
->pitches
[0] != obj
->stride
) {
8501 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8502 mode_cmd
->pitches
[0], obj
->stride
);
8506 /* Reject formats not supported by any plane early. */
8507 switch (mode_cmd
->pixel_format
) {
8509 case DRM_FORMAT_RGB565
:
8510 case DRM_FORMAT_XRGB8888
:
8511 case DRM_FORMAT_ARGB8888
:
8513 case DRM_FORMAT_XRGB1555
:
8514 case DRM_FORMAT_ARGB1555
:
8515 if (INTEL_INFO(dev
)->gen
> 3) {
8516 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8520 case DRM_FORMAT_XBGR8888
:
8521 case DRM_FORMAT_ABGR8888
:
8522 case DRM_FORMAT_XRGB2101010
:
8523 case DRM_FORMAT_ARGB2101010
:
8524 case DRM_FORMAT_XBGR2101010
:
8525 case DRM_FORMAT_ABGR2101010
:
8526 if (INTEL_INFO(dev
)->gen
< 4) {
8527 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8531 case DRM_FORMAT_YUYV
:
8532 case DRM_FORMAT_UYVY
:
8533 case DRM_FORMAT_YVYU
:
8534 case DRM_FORMAT_VYUY
:
8535 if (INTEL_INFO(dev
)->gen
< 5) {
8536 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd
->pixel_format
);
8541 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd
->pixel_format
);
8545 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8546 if (mode_cmd
->offsets
[0] != 0)
8549 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8550 intel_fb
->obj
= obj
;
8552 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8554 DRM_ERROR("framebuffer init failed %d\n", ret
);
8561 static struct drm_framebuffer
*
8562 intel_user_framebuffer_create(struct drm_device
*dev
,
8563 struct drm_file
*filp
,
8564 struct drm_mode_fb_cmd2
*mode_cmd
)
8566 struct drm_i915_gem_object
*obj
;
8568 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8569 mode_cmd
->handles
[0]));
8570 if (&obj
->base
== NULL
)
8571 return ERR_PTR(-ENOENT
);
8573 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8576 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8577 .fb_create
= intel_user_framebuffer_create
,
8578 .output_poll_changed
= intel_fb_output_poll_changed
,
8581 /* Set up chip specific display functions */
8582 static void intel_init_display(struct drm_device
*dev
)
8584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8586 /* We always want a DPMS function */
8588 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8589 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8590 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8591 dev_priv
->display
.off
= haswell_crtc_off
;
8592 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8593 } else if (HAS_PCH_SPLIT(dev
)) {
8594 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8595 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8596 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8597 dev_priv
->display
.off
= ironlake_crtc_off
;
8598 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8600 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8601 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8602 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8603 dev_priv
->display
.off
= i9xx_crtc_off
;
8604 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8607 /* Returns the core display clock speed */
8608 if (IS_VALLEYVIEW(dev
))
8609 dev_priv
->display
.get_display_clock_speed
=
8610 valleyview_get_display_clock_speed
;
8611 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8612 dev_priv
->display
.get_display_clock_speed
=
8613 i945_get_display_clock_speed
;
8614 else if (IS_I915G(dev
))
8615 dev_priv
->display
.get_display_clock_speed
=
8616 i915_get_display_clock_speed
;
8617 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8618 dev_priv
->display
.get_display_clock_speed
=
8619 i9xx_misc_get_display_clock_speed
;
8620 else if (IS_I915GM(dev
))
8621 dev_priv
->display
.get_display_clock_speed
=
8622 i915gm_get_display_clock_speed
;
8623 else if (IS_I865G(dev
))
8624 dev_priv
->display
.get_display_clock_speed
=
8625 i865_get_display_clock_speed
;
8626 else if (IS_I85X(dev
))
8627 dev_priv
->display
.get_display_clock_speed
=
8628 i855_get_display_clock_speed
;
8630 dev_priv
->display
.get_display_clock_speed
=
8631 i830_get_display_clock_speed
;
8633 if (HAS_PCH_SPLIT(dev
)) {
8635 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8636 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8637 } else if (IS_GEN6(dev
)) {
8638 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8639 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8640 } else if (IS_IVYBRIDGE(dev
)) {
8641 /* FIXME: detect B0+ stepping and use auto training */
8642 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8643 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8644 dev_priv
->display
.modeset_global_resources
=
8645 ivb_modeset_global_resources
;
8646 } else if (IS_HASWELL(dev
)) {
8647 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8648 dev_priv
->display
.write_eld
= haswell_write_eld
;
8649 dev_priv
->display
.modeset_global_resources
=
8650 haswell_modeset_global_resources
;
8652 } else if (IS_G4X(dev
)) {
8653 dev_priv
->display
.write_eld
= g4x_write_eld
;
8656 /* Default just returns -ENODEV to indicate unsupported */
8657 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8659 switch (INTEL_INFO(dev
)->gen
) {
8661 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8665 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8670 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8674 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8677 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8683 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8684 * resume, or other times. This quirk makes sure that's the case for
8687 static void quirk_pipea_force(struct drm_device
*dev
)
8689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8691 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8692 DRM_INFO("applying pipe a force quirk\n");
8696 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8698 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8701 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
8702 DRM_INFO("applying lvds SSC disable quirk\n");
8706 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8709 static void quirk_invert_brightness(struct drm_device
*dev
)
8711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8712 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
8713 DRM_INFO("applying inverted panel brightness quirk\n");
8716 struct intel_quirk
{
8718 int subsystem_vendor
;
8719 int subsystem_device
;
8720 void (*hook
)(struct drm_device
*dev
);
8723 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8724 struct intel_dmi_quirk
{
8725 void (*hook
)(struct drm_device
*dev
);
8726 const struct dmi_system_id (*dmi_id_list
)[];
8729 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
8731 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
8735 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
8737 .dmi_id_list
= &(const struct dmi_system_id
[]) {
8739 .callback
= intel_dmi_reverse_brightness
,
8740 .ident
= "NCR Corporation",
8741 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
8742 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
8745 { } /* terminating entry */
8747 .hook
= quirk_invert_brightness
,
8751 static struct intel_quirk intel_quirks
[] = {
8752 /* HP Mini needs pipe A force quirk (LP: #322104) */
8753 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
8755 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8756 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
8758 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8759 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
8761 /* 830/845 need to leave pipe A & dpll A up */
8762 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8763 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8765 /* Lenovo U160 cannot use SSC on LVDS */
8766 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
8768 /* Sony Vaio Y cannot use SSC on LVDS */
8769 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
8771 /* Acer Aspire 5734Z must invert backlight brightness */
8772 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
8774 /* Acer/eMachines G725 */
8775 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
8777 /* Acer/eMachines e725 */
8778 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
8780 /* Acer/Packard Bell NCL20 */
8781 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
8783 /* Acer Aspire 4736Z */
8784 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
8787 static void intel_init_quirks(struct drm_device
*dev
)
8789 struct pci_dev
*d
= dev
->pdev
;
8792 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8793 struct intel_quirk
*q
= &intel_quirks
[i
];
8795 if (d
->device
== q
->device
&&
8796 (d
->subsystem_vendor
== q
->subsystem_vendor
||
8797 q
->subsystem_vendor
== PCI_ANY_ID
) &&
8798 (d
->subsystem_device
== q
->subsystem_device
||
8799 q
->subsystem_device
== PCI_ANY_ID
))
8802 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
8803 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
8804 intel_dmi_quirks
[i
].hook(dev
);
8808 /* Disable the VGA plane that we never use */
8809 static void i915_disable_vga(struct drm_device
*dev
)
8811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8813 u32 vga_reg
= i915_vgacntrl_reg(dev
);
8815 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8816 outb(SR01
, VGA_SR_INDEX
);
8817 sr1
= inb(VGA_SR_DATA
);
8818 outb(sr1
| 1<<5, VGA_SR_DATA
);
8819 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8822 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
8823 POSTING_READ(vga_reg
);
8826 void intel_modeset_init_hw(struct drm_device
*dev
)
8828 intel_init_power_well(dev
);
8830 intel_prepare_ddi(dev
);
8832 intel_init_clock_gating(dev
);
8834 mutex_lock(&dev
->struct_mutex
);
8835 intel_enable_gt_powersave(dev
);
8836 mutex_unlock(&dev
->struct_mutex
);
8839 void intel_modeset_init(struct drm_device
*dev
)
8841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8844 drm_mode_config_init(dev
);
8846 dev
->mode_config
.min_width
= 0;
8847 dev
->mode_config
.min_height
= 0;
8849 dev
->mode_config
.preferred_depth
= 24;
8850 dev
->mode_config
.prefer_shadow
= 1;
8852 dev
->mode_config
.funcs
= &intel_mode_funcs
;
8854 intel_init_quirks(dev
);
8858 intel_init_display(dev
);
8861 dev
->mode_config
.max_width
= 2048;
8862 dev
->mode_config
.max_height
= 2048;
8863 } else if (IS_GEN3(dev
)) {
8864 dev
->mode_config
.max_width
= 4096;
8865 dev
->mode_config
.max_height
= 4096;
8867 dev
->mode_config
.max_width
= 8192;
8868 dev
->mode_config
.max_height
= 8192;
8870 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
8872 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8873 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
8875 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
8876 intel_crtc_init(dev
, i
);
8877 ret
= intel_plane_init(dev
, i
);
8879 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
8882 intel_cpu_pll_init(dev
);
8883 intel_pch_pll_init(dev
);
8885 /* Just disable it once at startup */
8886 i915_disable_vga(dev
);
8887 intel_setup_outputs(dev
);
8889 /* Just in case the BIOS is doing something questionable. */
8890 intel_disable_fbc(dev
);
8894 intel_connector_break_all_links(struct intel_connector
*connector
)
8896 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8897 connector
->base
.encoder
= NULL
;
8898 connector
->encoder
->connectors_active
= false;
8899 connector
->encoder
->base
.crtc
= NULL
;
8902 static void intel_enable_pipe_a(struct drm_device
*dev
)
8904 struct intel_connector
*connector
;
8905 struct drm_connector
*crt
= NULL
;
8906 struct intel_load_detect_pipe load_detect_temp
;
8908 /* We can't just switch on the pipe A, we need to set things up with a
8909 * proper mode and output configuration. As a gross hack, enable pipe A
8910 * by enabling the load detect pipe once. */
8911 list_for_each_entry(connector
,
8912 &dev
->mode_config
.connector_list
,
8914 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
8915 crt
= &connector
->base
;
8923 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
8924 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
8930 intel_check_plane_mapping(struct intel_crtc
*crtc
)
8932 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
8935 if (dev_priv
->num_pipe
== 1)
8938 reg
= DSPCNTR(!crtc
->plane
);
8939 val
= I915_READ(reg
);
8941 if ((val
& DISPLAY_PLANE_ENABLE
) &&
8942 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
8948 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
8950 struct drm_device
*dev
= crtc
->base
.dev
;
8951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8954 /* Clear any frame start delays used for debugging left by the BIOS */
8955 reg
= PIPECONF(crtc
->cpu_transcoder
);
8956 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
8958 /* We need to sanitize the plane -> pipe mapping first because this will
8959 * disable the crtc (and hence change the state) if it is wrong. Note
8960 * that gen4+ has a fixed plane -> pipe mapping. */
8961 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
8962 struct intel_connector
*connector
;
8965 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8966 crtc
->base
.base
.id
);
8968 /* Pipe has the wrong plane attached and the plane is active.
8969 * Temporarily change the plane mapping and disable everything
8971 plane
= crtc
->plane
;
8972 crtc
->plane
= !plane
;
8973 dev_priv
->display
.crtc_disable(&crtc
->base
);
8974 crtc
->plane
= plane
;
8976 /* ... and break all links. */
8977 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8979 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
8982 intel_connector_break_all_links(connector
);
8985 WARN_ON(crtc
->active
);
8986 crtc
->base
.enabled
= false;
8989 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
8990 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
8991 /* BIOS forgot to enable pipe A, this mostly happens after
8992 * resume. Force-enable the pipe to fix this, the update_dpms
8993 * call below we restore the pipe to the right state, but leave
8994 * the required bits on. */
8995 intel_enable_pipe_a(dev
);
8998 /* Adjust the state of the output pipe according to whether we
8999 * have active connectors/encoders. */
9000 intel_crtc_update_dpms(&crtc
->base
);
9002 if (crtc
->active
!= crtc
->base
.enabled
) {
9003 struct intel_encoder
*encoder
;
9005 /* This can happen either due to bugs in the get_hw_state
9006 * functions or because the pipe is force-enabled due to the
9008 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9010 crtc
->base
.enabled
? "enabled" : "disabled",
9011 crtc
->active
? "enabled" : "disabled");
9013 crtc
->base
.enabled
= crtc
->active
;
9015 /* Because we only establish the connector -> encoder ->
9016 * crtc links if something is active, this means the
9017 * crtc is now deactivated. Break the links. connector
9018 * -> encoder links are only establish when things are
9019 * actually up, hence no need to break them. */
9020 WARN_ON(crtc
->active
);
9022 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
9023 WARN_ON(encoder
->connectors_active
);
9024 encoder
->base
.crtc
= NULL
;
9029 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
9031 struct intel_connector
*connector
;
9032 struct drm_device
*dev
= encoder
->base
.dev
;
9034 /* We need to check both for a crtc link (meaning that the
9035 * encoder is active and trying to read from a pipe) and the
9036 * pipe itself being active. */
9037 bool has_active_crtc
= encoder
->base
.crtc
&&
9038 to_intel_crtc(encoder
->base
.crtc
)->active
;
9040 if (encoder
->connectors_active
&& !has_active_crtc
) {
9041 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9042 encoder
->base
.base
.id
,
9043 drm_get_encoder_name(&encoder
->base
));
9045 /* Connector is active, but has no active pipe. This is
9046 * fallout from our resume register restoring. Disable
9047 * the encoder manually again. */
9048 if (encoder
->base
.crtc
) {
9049 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9050 encoder
->base
.base
.id
,
9051 drm_get_encoder_name(&encoder
->base
));
9052 encoder
->disable(encoder
);
9055 /* Inconsistent output/port/pipe state happens presumably due to
9056 * a bug in one of the get_hw_state functions. Or someplace else
9057 * in our code, like the register restore mess on resume. Clamp
9058 * things to off as a safer default. */
9059 list_for_each_entry(connector
,
9060 &dev
->mode_config
.connector_list
,
9062 if (connector
->encoder
!= encoder
)
9065 intel_connector_break_all_links(connector
);
9068 /* Enabled encoders without active connectors will be fixed in
9069 * the crtc fixup. */
9072 void i915_redisable_vga(struct drm_device
*dev
)
9074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9075 u32 vga_reg
= i915_vgacntrl_reg(dev
);
9077 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
9078 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9079 i915_disable_vga(dev
);
9083 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9084 * and i915 state tracking structures. */
9085 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
9088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9091 struct intel_crtc
*crtc
;
9092 struct intel_encoder
*encoder
;
9093 struct intel_connector
*connector
;
9096 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9098 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9099 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9100 case TRANS_DDI_EDP_INPUT_A_ON
:
9101 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9104 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9107 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9112 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9113 crtc
->cpu_transcoder
= TRANSCODER_EDP
;
9115 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9120 for_each_pipe(pipe
) {
9121 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9123 tmp
= I915_READ(PIPECONF(crtc
->cpu_transcoder
));
9124 if (tmp
& PIPECONF_ENABLE
)
9125 crtc
->active
= true;
9127 crtc
->active
= false;
9129 crtc
->base
.enabled
= crtc
->active
;
9131 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9133 crtc
->active
? "enabled" : "disabled");
9137 intel_ddi_setup_hw_pll_state(dev
);
9139 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9143 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9144 encoder
->base
.crtc
=
9145 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9147 encoder
->base
.crtc
= NULL
;
9150 encoder
->connectors_active
= false;
9151 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9152 encoder
->base
.base
.id
,
9153 drm_get_encoder_name(&encoder
->base
),
9154 encoder
->base
.crtc
? "enabled" : "disabled",
9158 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9160 if (connector
->get_hw_state(connector
)) {
9161 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
9162 connector
->encoder
->connectors_active
= true;
9163 connector
->base
.encoder
= &connector
->encoder
->base
;
9165 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9166 connector
->base
.encoder
= NULL
;
9168 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9169 connector
->base
.base
.id
,
9170 drm_get_connector_name(&connector
->base
),
9171 connector
->base
.encoder
? "enabled" : "disabled");
9174 /* HW state is read out, now we need to sanitize this mess. */
9175 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9177 intel_sanitize_encoder(encoder
);
9180 for_each_pipe(pipe
) {
9181 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9182 intel_sanitize_crtc(crtc
);
9185 if (force_restore
) {
9186 for_each_pipe(pipe
) {
9187 intel_crtc_restore_mode(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9190 i915_redisable_vga(dev
);
9192 intel_modeset_update_staged_output_state(dev
);
9195 intel_modeset_check_state(dev
);
9197 drm_mode_config_reset(dev
);
9200 void intel_modeset_gem_init(struct drm_device
*dev
)
9202 intel_modeset_init_hw(dev
);
9204 intel_setup_overlay(dev
);
9206 intel_modeset_setup_hw_state(dev
, false);
9209 void intel_modeset_cleanup(struct drm_device
*dev
)
9211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9212 struct drm_crtc
*crtc
;
9213 struct intel_crtc
*intel_crtc
;
9215 drm_kms_helper_poll_fini(dev
);
9216 mutex_lock(&dev
->struct_mutex
);
9218 intel_unregister_dsm_handler();
9221 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9222 /* Skip inactive CRTCs */
9226 intel_crtc
= to_intel_crtc(crtc
);
9227 intel_increase_pllclock(crtc
);
9230 intel_disable_fbc(dev
);
9232 intel_disable_gt_powersave(dev
);
9234 ironlake_teardown_rc6(dev
);
9236 if (IS_VALLEYVIEW(dev
))
9239 mutex_unlock(&dev
->struct_mutex
);
9241 /* Disable the irq before mode object teardown, for the irq might
9242 * enqueue unpin/hotplug work. */
9243 drm_irq_uninstall(dev
);
9244 cancel_work_sync(&dev_priv
->hotplug_work
);
9245 cancel_work_sync(&dev_priv
->rps
.work
);
9247 /* flush any delayed tasks or pending work */
9248 flush_scheduled_work();
9250 drm_mode_config_cleanup(dev
);
9252 intel_cleanup_overlay(dev
);
9256 * Return which encoder is currently attached for connector.
9258 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9260 return &intel_attached_encoder(connector
)->base
;
9263 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9264 struct intel_encoder
*encoder
)
9266 connector
->encoder
= encoder
;
9267 drm_mode_connector_attach_encoder(&connector
->base
,
9272 * set vga decode state - true == enable VGA decode
9274 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9279 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9281 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9283 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9284 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9288 #ifdef CONFIG_DEBUG_FS
9289 #include <linux/seq_file.h>
9291 struct intel_display_error_state
{
9292 struct intel_cursor_error_state
{
9297 } cursor
[I915_MAX_PIPES
];
9299 struct intel_pipe_error_state
{
9309 } pipe
[I915_MAX_PIPES
];
9311 struct intel_plane_error_state
{
9319 } plane
[I915_MAX_PIPES
];
9322 struct intel_display_error_state
*
9323 intel_display_capture_error_state(struct drm_device
*dev
)
9325 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9326 struct intel_display_error_state
*error
;
9327 enum transcoder cpu_transcoder
;
9330 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9335 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9337 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9338 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9339 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9341 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9342 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9343 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9344 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9345 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9346 if (INTEL_INFO(dev
)->gen
>= 4) {
9347 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9348 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9351 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9352 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9353 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9354 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9355 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9356 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9357 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9358 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9365 intel_display_print_error_state(struct seq_file
*m
,
9366 struct drm_device
*dev
,
9367 struct intel_display_error_state
*error
)
9369 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9372 seq_printf(m
, "Num Pipes: %d\n", dev_priv
->num_pipe
);
9374 seq_printf(m
, "Pipe [%d]:\n", i
);
9375 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9376 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9377 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9378 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9379 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9380 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9381 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9382 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9384 seq_printf(m
, "Plane [%d]:\n", i
);
9385 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9386 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9387 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9388 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9389 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9390 if (INTEL_INFO(dev
)->gen
>= 4) {
9391 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9392 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9395 seq_printf(m
, "Cursor [%d]:\n", i
);
9396 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9397 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9398 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);