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Merge tag 'drm-intel-next-2017-11-17-1' of git://anongit.freedesktop.org/drm/drm...
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54 DRM_FORMAT_C8,
55 DRM_FORMAT_RGB565,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_XRGB8888,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB8888,
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 };
69
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
74 };
75
76 static const uint32_t skl_primary_formats[] = {
77 DRM_FORMAT_C8,
78 DRM_FORMAT_RGB565,
79 DRM_FORMAT_XRGB8888,
80 DRM_FORMAT_XBGR8888,
81 DRM_FORMAT_ARGB8888,
82 DRM_FORMAT_ABGR8888,
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
85 DRM_FORMAT_YUYV,
86 DRM_FORMAT_YVYU,
87 DRM_FORMAT_UYVY,
88 DRM_FORMAT_VYUY,
89 };
90
91 static const uint64_t skl_format_modifiers_noccs[] = {
92 I915_FORMAT_MOD_Yf_TILED,
93 I915_FORMAT_MOD_Y_TILED,
94 I915_FORMAT_MOD_X_TILED,
95 DRM_FORMAT_MOD_LINEAR,
96 DRM_FORMAT_MOD_INVALID
97 };
98
99 static const uint64_t skl_format_modifiers_ccs[] = {
100 I915_FORMAT_MOD_Yf_TILED_CCS,
101 I915_FORMAT_MOD_Y_TILED_CCS,
102 I915_FORMAT_MOD_Yf_TILED,
103 I915_FORMAT_MOD_Y_TILED,
104 I915_FORMAT_MOD_X_TILED,
105 DRM_FORMAT_MOD_LINEAR,
106 DRM_FORMAT_MOD_INVALID
107 };
108
109 /* Cursor formats */
110 static const uint32_t intel_cursor_formats[] = {
111 DRM_FORMAT_ARGB8888,
112 };
113
114 static const uint64_t cursor_format_modifiers[] = {
115 DRM_FORMAT_MOD_LINEAR,
116 DRM_FORMAT_MOD_INVALID
117 };
118
119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
120 struct intel_crtc_state *pipe_config);
121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
122 struct intel_crtc_state *pipe_config);
123
124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
125 struct drm_i915_gem_object *obj,
126 struct drm_mode_fb_cmd2 *mode_cmd);
127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
131 struct intel_link_m_n *m_n,
132 struct intel_link_m_n *m2_n2);
133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
136 static void vlv_prepare_pll(struct intel_crtc *crtc,
137 const struct intel_crtc_state *pipe_config);
138 static void chv_prepare_pll(struct intel_crtc *crtc,
139 const struct intel_crtc_state *pipe_config);
140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
143 struct intel_crtc_state *crtc_state);
144 static void skylake_pfit_enable(struct intel_crtc *crtc);
145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
148 struct drm_modeset_acquire_ctx *ctx);
149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
150
151 struct intel_limit {
152 struct {
153 int min, max;
154 } dot, vco, n, m, m1, m2, p, p1;
155
156 struct {
157 int dot_limit;
158 int p2_slow, p2_fast;
159 } p2;
160 };
161
162 /* returns HPLL frequency in kHz */
163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
164 {
165 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
166
167 /* Obtain SKU information */
168 mutex_lock(&dev_priv->sb_lock);
169 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
170 CCK_FUSE_HPLL_FREQ_MASK;
171 mutex_unlock(&dev_priv->sb_lock);
172
173 return vco_freq[hpll_freq] * 1000;
174 }
175
176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
177 const char *name, u32 reg, int ref_freq)
178 {
179 u32 val;
180 int divider;
181
182 mutex_lock(&dev_priv->sb_lock);
183 val = vlv_cck_read(dev_priv, reg);
184 mutex_unlock(&dev_priv->sb_lock);
185
186 divider = val & CCK_FREQUENCY_VALUES;
187
188 WARN((val & CCK_FREQUENCY_STATUS) !=
189 (divider << CCK_FREQUENCY_STATUS_SHIFT),
190 "%s change in progress\n", name);
191
192 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
193 }
194
195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
196 const char *name, u32 reg)
197 {
198 if (dev_priv->hpll_freq == 0)
199 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
200
201 return vlv_get_cck_clock(dev_priv, name, reg,
202 dev_priv->hpll_freq);
203 }
204
205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
206 {
207 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
208 return;
209
210 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
211 CCK_CZ_CLOCK_CONTROL);
212
213 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
214 }
215
216 static inline u32 /* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
218 const struct intel_crtc_state *pipe_config)
219 {
220 if (HAS_DDI(dev_priv))
221 return pipe_config->port_clock; /* SPLL */
222 else
223 return dev_priv->fdi_pll_freq;
224 }
225
226 static const struct intel_limit intel_limits_i8xx_dac = {
227 .dot = { .min = 25000, .max = 350000 },
228 .vco = { .min = 908000, .max = 1512000 },
229 .n = { .min = 2, .max = 16 },
230 .m = { .min = 96, .max = 140 },
231 .m1 = { .min = 18, .max = 26 },
232 .m2 = { .min = 6, .max = 16 },
233 .p = { .min = 4, .max = 128 },
234 .p1 = { .min = 2, .max = 33 },
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 4, .p2_fast = 2 },
237 };
238
239 static const struct intel_limit intel_limits_i8xx_dvo = {
240 .dot = { .min = 25000, .max = 350000 },
241 .vco = { .min = 908000, .max = 1512000 },
242 .n = { .min = 2, .max = 16 },
243 .m = { .min = 96, .max = 140 },
244 .m1 = { .min = 18, .max = 26 },
245 .m2 = { .min = 6, .max = 16 },
246 .p = { .min = 4, .max = 128 },
247 .p1 = { .min = 2, .max = 33 },
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 4, .p2_fast = 4 },
250 };
251
252 static const struct intel_limit intel_limits_i8xx_lvds = {
253 .dot = { .min = 25000, .max = 350000 },
254 .vco = { .min = 908000, .max = 1512000 },
255 .n = { .min = 2, .max = 16 },
256 .m = { .min = 96, .max = 140 },
257 .m1 = { .min = 18, .max = 26 },
258 .m2 = { .min = 6, .max = 16 },
259 .p = { .min = 4, .max = 128 },
260 .p1 = { .min = 1, .max = 6 },
261 .p2 = { .dot_limit = 165000,
262 .p2_slow = 14, .p2_fast = 7 },
263 };
264
265 static const struct intel_limit intel_limits_i9xx_sdvo = {
266 .dot = { .min = 20000, .max = 400000 },
267 .vco = { .min = 1400000, .max = 2800000 },
268 .n = { .min = 1, .max = 6 },
269 .m = { .min = 70, .max = 120 },
270 .m1 = { .min = 8, .max = 18 },
271 .m2 = { .min = 3, .max = 7 },
272 .p = { .min = 5, .max = 80 },
273 .p1 = { .min = 1, .max = 8 },
274 .p2 = { .dot_limit = 200000,
275 .p2_slow = 10, .p2_fast = 5 },
276 };
277
278 static const struct intel_limit intel_limits_i9xx_lvds = {
279 .dot = { .min = 20000, .max = 400000 },
280 .vco = { .min = 1400000, .max = 2800000 },
281 .n = { .min = 1, .max = 6 },
282 .m = { .min = 70, .max = 120 },
283 .m1 = { .min = 8, .max = 18 },
284 .m2 = { .min = 3, .max = 7 },
285 .p = { .min = 7, .max = 98 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 112000,
288 .p2_slow = 14, .p2_fast = 7 },
289 };
290
291
292 static const struct intel_limit intel_limits_g4x_sdvo = {
293 .dot = { .min = 25000, .max = 270000 },
294 .vco = { .min = 1750000, .max = 3500000},
295 .n = { .min = 1, .max = 4 },
296 .m = { .min = 104, .max = 138 },
297 .m1 = { .min = 17, .max = 23 },
298 .m2 = { .min = 5, .max = 11 },
299 .p = { .min = 10, .max = 30 },
300 .p1 = { .min = 1, .max = 3},
301 .p2 = { .dot_limit = 270000,
302 .p2_slow = 10,
303 .p2_fast = 10
304 },
305 };
306
307 static const struct intel_limit intel_limits_g4x_hdmi = {
308 .dot = { .min = 22000, .max = 400000 },
309 .vco = { .min = 1750000, .max = 3500000},
310 .n = { .min = 1, .max = 4 },
311 .m = { .min = 104, .max = 138 },
312 .m1 = { .min = 16, .max = 23 },
313 .m2 = { .min = 5, .max = 11 },
314 .p = { .min = 5, .max = 80 },
315 .p1 = { .min = 1, .max = 8},
316 .p2 = { .dot_limit = 165000,
317 .p2_slow = 10, .p2_fast = 5 },
318 };
319
320 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
321 .dot = { .min = 20000, .max = 115000 },
322 .vco = { .min = 1750000, .max = 3500000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 104, .max = 138 },
325 .m1 = { .min = 17, .max = 23 },
326 .m2 = { .min = 5, .max = 11 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 0,
330 .p2_slow = 14, .p2_fast = 14
331 },
332 };
333
334 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
335 .dot = { .min = 80000, .max = 224000 },
336 .vco = { .min = 1750000, .max = 3500000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 104, .max = 138 },
339 .m1 = { .min = 17, .max = 23 },
340 .m2 = { .min = 5, .max = 11 },
341 .p = { .min = 14, .max = 42 },
342 .p1 = { .min = 2, .max = 6 },
343 .p2 = { .dot_limit = 0,
344 .p2_slow = 7, .p2_fast = 7
345 },
346 };
347
348 static const struct intel_limit intel_limits_pineview_sdvo = {
349 .dot = { .min = 20000, .max = 400000},
350 .vco = { .min = 1700000, .max = 3500000 },
351 /* Pineview's Ncounter is a ring counter */
352 .n = { .min = 3, .max = 6 },
353 .m = { .min = 2, .max = 256 },
354 /* Pineview only has one combined m divider, which we treat as m2. */
355 .m1 = { .min = 0, .max = 0 },
356 .m2 = { .min = 0, .max = 254 },
357 .p = { .min = 5, .max = 80 },
358 .p1 = { .min = 1, .max = 8 },
359 .p2 = { .dot_limit = 200000,
360 .p2_slow = 10, .p2_fast = 5 },
361 };
362
363 static const struct intel_limit intel_limits_pineview_lvds = {
364 .dot = { .min = 20000, .max = 400000 },
365 .vco = { .min = 1700000, .max = 3500000 },
366 .n = { .min = 3, .max = 6 },
367 .m = { .min = 2, .max = 256 },
368 .m1 = { .min = 0, .max = 0 },
369 .m2 = { .min = 0, .max = 254 },
370 .p = { .min = 7, .max = 112 },
371 .p1 = { .min = 1, .max = 8 },
372 .p2 = { .dot_limit = 112000,
373 .p2_slow = 14, .p2_fast = 14 },
374 };
375
376 /* Ironlake / Sandybridge
377 *
378 * We calculate clock using (register_value + 2) for N/M1/M2, so here
379 * the range value for them is (actual_value - 2).
380 */
381 static const struct intel_limit intel_limits_ironlake_dac = {
382 .dot = { .min = 25000, .max = 350000 },
383 .vco = { .min = 1760000, .max = 3510000 },
384 .n = { .min = 1, .max = 5 },
385 .m = { .min = 79, .max = 127 },
386 .m1 = { .min = 12, .max = 22 },
387 .m2 = { .min = 5, .max = 9 },
388 .p = { .min = 5, .max = 80 },
389 .p1 = { .min = 1, .max = 8 },
390 .p2 = { .dot_limit = 225000,
391 .p2_slow = 10, .p2_fast = 5 },
392 };
393
394 static const struct intel_limit intel_limits_ironlake_single_lvds = {
395 .dot = { .min = 25000, .max = 350000 },
396 .vco = { .min = 1760000, .max = 3510000 },
397 .n = { .min = 1, .max = 3 },
398 .m = { .min = 79, .max = 118 },
399 .m1 = { .min = 12, .max = 22 },
400 .m2 = { .min = 5, .max = 9 },
401 .p = { .min = 28, .max = 112 },
402 .p1 = { .min = 2, .max = 8 },
403 .p2 = { .dot_limit = 225000,
404 .p2_slow = 14, .p2_fast = 14 },
405 };
406
407 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
408 .dot = { .min = 25000, .max = 350000 },
409 .vco = { .min = 1760000, .max = 3510000 },
410 .n = { .min = 1, .max = 3 },
411 .m = { .min = 79, .max = 127 },
412 .m1 = { .min = 12, .max = 22 },
413 .m2 = { .min = 5, .max = 9 },
414 .p = { .min = 14, .max = 56 },
415 .p1 = { .min = 2, .max = 8 },
416 .p2 = { .dot_limit = 225000,
417 .p2_slow = 7, .p2_fast = 7 },
418 };
419
420 /* LVDS 100mhz refclk limits. */
421 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
422 .dot = { .min = 25000, .max = 350000 },
423 .vco = { .min = 1760000, .max = 3510000 },
424 .n = { .min = 1, .max = 2 },
425 .m = { .min = 79, .max = 126 },
426 .m1 = { .min = 12, .max = 22 },
427 .m2 = { .min = 5, .max = 9 },
428 .p = { .min = 28, .max = 112 },
429 .p1 = { .min = 2, .max = 8 },
430 .p2 = { .dot_limit = 225000,
431 .p2_slow = 14, .p2_fast = 14 },
432 };
433
434 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
435 .dot = { .min = 25000, .max = 350000 },
436 .vco = { .min = 1760000, .max = 3510000 },
437 .n = { .min = 1, .max = 3 },
438 .m = { .min = 79, .max = 126 },
439 .m1 = { .min = 12, .max = 22 },
440 .m2 = { .min = 5, .max = 9 },
441 .p = { .min = 14, .max = 42 },
442 .p1 = { .min = 2, .max = 6 },
443 .p2 = { .dot_limit = 225000,
444 .p2_slow = 7, .p2_fast = 7 },
445 };
446
447 static const struct intel_limit intel_limits_vlv = {
448 /*
449 * These are the data rate limits (measured in fast clocks)
450 * since those are the strictest limits we have. The fast
451 * clock and actual rate limits are more relaxed, so checking
452 * them would make no difference.
453 */
454 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
455 .vco = { .min = 4000000, .max = 6000000 },
456 .n = { .min = 1, .max = 7 },
457 .m1 = { .min = 2, .max = 3 },
458 .m2 = { .min = 11, .max = 156 },
459 .p1 = { .min = 2, .max = 3 },
460 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
461 };
462
463 static const struct intel_limit intel_limits_chv = {
464 /*
465 * These are the data rate limits (measured in fast clocks)
466 * since those are the strictest limits we have. The fast
467 * clock and actual rate limits are more relaxed, so checking
468 * them would make no difference.
469 */
470 .dot = { .min = 25000 * 5, .max = 540000 * 5},
471 .vco = { .min = 4800000, .max = 6480000 },
472 .n = { .min = 1, .max = 1 },
473 .m1 = { .min = 2, .max = 2 },
474 .m2 = { .min = 24 << 22, .max = 175 << 22 },
475 .p1 = { .min = 2, .max = 4 },
476 .p2 = { .p2_slow = 1, .p2_fast = 14 },
477 };
478
479 static const struct intel_limit intel_limits_bxt = {
480 /* FIXME: find real dot limits */
481 .dot = { .min = 0, .max = INT_MAX },
482 .vco = { .min = 4800000, .max = 6700000 },
483 .n = { .min = 1, .max = 1 },
484 .m1 = { .min = 2, .max = 2 },
485 /* FIXME: find real m2 limits */
486 .m2 = { .min = 2 << 22, .max = 255 << 22 },
487 .p1 = { .min = 2, .max = 4 },
488 .p2 = { .p2_slow = 1, .p2_fast = 20 },
489 };
490
491 static bool
492 needs_modeset(struct drm_crtc_state *state)
493 {
494 return drm_atomic_crtc_needs_modeset(state);
495 }
496
497 /*
498 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
499 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
500 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
501 * The helpers' return value is the rate of the clock that is fed to the
502 * display engine's pipe which can be the above fast dot clock rate or a
503 * divided-down version of it.
504 */
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return 0;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514
515 return clock->dot;
516 }
517
518 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
519 {
520 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
521 }
522
523 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
524 {
525 clock->m = i9xx_dpll_compute_m(clock);
526 clock->p = clock->p1 * clock->p2;
527 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
528 return 0;
529 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531
532 return clock->dot;
533 }
534
535 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
536 {
537 clock->m = clock->m1 * clock->m2;
538 clock->p = clock->p1 * clock->p2;
539 if (WARN_ON(clock->n == 0 || clock->p == 0))
540 return 0;
541 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
542 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
543
544 return clock->dot / 5;
545 }
546
547 int chv_calc_dpll_params(int refclk, struct dpll *clock)
548 {
549 clock->m = clock->m1 * clock->m2;
550 clock->p = clock->p1 * clock->p2;
551 if (WARN_ON(clock->n == 0 || clock->p == 0))
552 return 0;
553 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
554 clock->n << 22);
555 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
556
557 return clock->dot / 5;
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
567 const struct intel_limit *limit,
568 const struct dpll *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
580 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
583
584 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
585 !IS_GEN9_LP(dev_priv)) {
586 if (clock->p < limit->p.min || limit->p.max < clock->p)
587 INTELPllInvalid("p out of range\n");
588 if (clock->m < limit->m.min || limit->m.max < clock->m)
589 INTELPllInvalid("m out of range\n");
590 }
591
592 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
593 INTELPllInvalid("vco out of range\n");
594 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
595 * connector, etc., rather than just a single range.
596 */
597 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
598 INTELPllInvalid("dot out of range\n");
599
600 return true;
601 }
602
603 static int
604 i9xx_select_p2_div(const struct intel_limit *limit,
605 const struct intel_crtc_state *crtc_state,
606 int target)
607 {
608 struct drm_device *dev = crtc_state->base.crtc->dev;
609
610 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 return limit->p2.p2_fast;
618 else
619 return limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 return limit->p2.p2_slow;
623 else
624 return limit->p2.p2_fast;
625 }
626 }
627
628 /*
629 * Returns a set of divisors for the desired target clock with the given
630 * refclk, or FALSE. The returned values represent the clock equation:
631 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
632 *
633 * Target and reference clocks are specified in kHz.
634 *
635 * If match_clock is provided, then best_clock P divider must match the P
636 * divider from @match_clock used for LVDS downclocking.
637 */
638 static bool
639 i9xx_find_best_dpll(const struct intel_limit *limit,
640 struct intel_crtc_state *crtc_state,
641 int target, int refclk, struct dpll *match_clock,
642 struct dpll *best_clock)
643 {
644 struct drm_device *dev = crtc_state->base.crtc->dev;
645 struct dpll clock;
646 int err = target;
647
648 memset(best_clock, 0, sizeof(*best_clock));
649
650 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
651
652 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
653 clock.m1++) {
654 for (clock.m2 = limit->m2.min;
655 clock.m2 <= limit->m2.max; clock.m2++) {
656 if (clock.m2 >= clock.m1)
657 break;
658 for (clock.n = limit->n.min;
659 clock.n <= limit->n.max; clock.n++) {
660 for (clock.p1 = limit->p1.min;
661 clock.p1 <= limit->p1.max; clock.p1++) {
662 int this_err;
663
664 i9xx_calc_dpll_params(refclk, &clock);
665 if (!intel_PLL_is_valid(to_i915(dev),
666 limit,
667 &clock))
668 continue;
669 if (match_clock &&
670 clock.p != match_clock->p)
671 continue;
672
673 this_err = abs(clock.dot - target);
674 if (this_err < err) {
675 *best_clock = clock;
676 err = this_err;
677 }
678 }
679 }
680 }
681 }
682
683 return (err != target);
684 }
685
686 /*
687 * Returns a set of divisors for the desired target clock with the given
688 * refclk, or FALSE. The returned values represent the clock equation:
689 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
690 *
691 * Target and reference clocks are specified in kHz.
692 *
693 * If match_clock is provided, then best_clock P divider must match the P
694 * divider from @match_clock used for LVDS downclocking.
695 */
696 static bool
697 pnv_find_best_dpll(const struct intel_limit *limit,
698 struct intel_crtc_state *crtc_state,
699 int target, int refclk, struct dpll *match_clock,
700 struct dpll *best_clock)
701 {
702 struct drm_device *dev = crtc_state->base.crtc->dev;
703 struct dpll clock;
704 int err = target;
705
706 memset(best_clock, 0, sizeof(*best_clock));
707
708 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
709
710 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
711 clock.m1++) {
712 for (clock.m2 = limit->m2.min;
713 clock.m2 <= limit->m2.max; clock.m2++) {
714 for (clock.n = limit->n.min;
715 clock.n <= limit->n.max; clock.n++) {
716 for (clock.p1 = limit->p1.min;
717 clock.p1 <= limit->p1.max; clock.p1++) {
718 int this_err;
719
720 pnv_calc_dpll_params(refclk, &clock);
721 if (!intel_PLL_is_valid(to_i915(dev),
722 limit,
723 &clock))
724 continue;
725 if (match_clock &&
726 clock.p != match_clock->p)
727 continue;
728
729 this_err = abs(clock.dot - target);
730 if (this_err < err) {
731 *best_clock = clock;
732 err = this_err;
733 }
734 }
735 }
736 }
737 }
738
739 return (err != target);
740 }
741
742 /*
743 * Returns a set of divisors for the desired target clock with the given
744 * refclk, or FALSE. The returned values represent the clock equation:
745 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
746 *
747 * Target and reference clocks are specified in kHz.
748 *
749 * If match_clock is provided, then best_clock P divider must match the P
750 * divider from @match_clock used for LVDS downclocking.
751 */
752 static bool
753 g4x_find_best_dpll(const struct intel_limit *limit,
754 struct intel_crtc_state *crtc_state,
755 int target, int refclk, struct dpll *match_clock,
756 struct dpll *best_clock)
757 {
758 struct drm_device *dev = crtc_state->base.crtc->dev;
759 struct dpll clock;
760 int max_n;
761 bool found = false;
762 /* approximately equals target * 0.00585 */
763 int err_most = (target >> 8) + (target >> 9);
764
765 memset(best_clock, 0, sizeof(*best_clock));
766
767 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
768
769 max_n = limit->n.max;
770 /* based on hardware requirement, prefer smaller n to precision */
771 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
772 /* based on hardware requirement, prefere larger m1,m2 */
773 for (clock.m1 = limit->m1.max;
774 clock.m1 >= limit->m1.min; clock.m1--) {
775 for (clock.m2 = limit->m2.max;
776 clock.m2 >= limit->m2.min; clock.m2--) {
777 for (clock.p1 = limit->p1.max;
778 clock.p1 >= limit->p1.min; clock.p1--) {
779 int this_err;
780
781 i9xx_calc_dpll_params(refclk, &clock);
782 if (!intel_PLL_is_valid(to_i915(dev),
783 limit,
784 &clock))
785 continue;
786
787 this_err = abs(clock.dot - target);
788 if (this_err < err_most) {
789 *best_clock = clock;
790 err_most = this_err;
791 max_n = clock.n;
792 found = true;
793 }
794 }
795 }
796 }
797 }
798 return found;
799 }
800
801 /*
802 * Check if the calculated PLL configuration is more optimal compared to the
803 * best configuration and error found so far. Return the calculated error.
804 */
805 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
806 const struct dpll *calculated_clock,
807 const struct dpll *best_clock,
808 unsigned int best_error_ppm,
809 unsigned int *error_ppm)
810 {
811 /*
812 * For CHV ignore the error and consider only the P value.
813 * Prefer a bigger P value based on HW requirements.
814 */
815 if (IS_CHERRYVIEW(to_i915(dev))) {
816 *error_ppm = 0;
817
818 return calculated_clock->p > best_clock->p;
819 }
820
821 if (WARN_ON_ONCE(!target_freq))
822 return false;
823
824 *error_ppm = div_u64(1000000ULL *
825 abs(target_freq - calculated_clock->dot),
826 target_freq);
827 /*
828 * Prefer a better P value over a better (smaller) error if the error
829 * is small. Ensure this preference for future configurations too by
830 * setting the error to 0.
831 */
832 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
833 *error_ppm = 0;
834
835 return true;
836 }
837
838 return *error_ppm + 10 < best_error_ppm;
839 }
840
841 /*
842 * Returns a set of divisors for the desired target clock with the given
843 * refclk, or FALSE. The returned values represent the clock equation:
844 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
845 */
846 static bool
847 vlv_find_best_dpll(const struct intel_limit *limit,
848 struct intel_crtc_state *crtc_state,
849 int target, int refclk, struct dpll *match_clock,
850 struct dpll *best_clock)
851 {
852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
853 struct drm_device *dev = crtc->base.dev;
854 struct dpll clock;
855 unsigned int bestppm = 1000000;
856 /* min update 19.2 MHz */
857 int max_n = min(limit->n.max, refclk / 19200);
858 bool found = false;
859
860 target *= 5; /* fast clock */
861
862 memset(best_clock, 0, sizeof(*best_clock));
863
864 /* based on hardware requirement, prefer smaller n to precision */
865 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
866 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
867 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
868 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
869 clock.p = clock.p1 * clock.p2;
870 /* based on hardware requirement, prefer bigger m1,m2 values */
871 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
872 unsigned int ppm;
873
874 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
875 refclk * clock.m1);
876
877 vlv_calc_dpll_params(refclk, &clock);
878
879 if (!intel_PLL_is_valid(to_i915(dev),
880 limit,
881 &clock))
882 continue;
883
884 if (!vlv_PLL_is_optimal(dev, target,
885 &clock,
886 best_clock,
887 bestppm, &ppm))
888 continue;
889
890 *best_clock = clock;
891 bestppm = ppm;
892 found = true;
893 }
894 }
895 }
896 }
897
898 return found;
899 }
900
901 /*
902 * Returns a set of divisors for the desired target clock with the given
903 * refclk, or FALSE. The returned values represent the clock equation:
904 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
905 */
906 static bool
907 chv_find_best_dpll(const struct intel_limit *limit,
908 struct intel_crtc_state *crtc_state,
909 int target, int refclk, struct dpll *match_clock,
910 struct dpll *best_clock)
911 {
912 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
913 struct drm_device *dev = crtc->base.dev;
914 unsigned int best_error_ppm;
915 struct dpll clock;
916 uint64_t m2;
917 int found = false;
918
919 memset(best_clock, 0, sizeof(*best_clock));
920 best_error_ppm = 1000000;
921
922 /*
923 * Based on hardware doc, the n always set to 1, and m1 always
924 * set to 2. If requires to support 200Mhz refclk, we need to
925 * revisit this because n may not 1 anymore.
926 */
927 clock.n = 1, clock.m1 = 2;
928 target *= 5; /* fast clock */
929
930 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
931 for (clock.p2 = limit->p2.p2_fast;
932 clock.p2 >= limit->p2.p2_slow;
933 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
934 unsigned int error_ppm;
935
936 clock.p = clock.p1 * clock.p2;
937
938 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
939 clock.n) << 22, refclk * clock.m1);
940
941 if (m2 > INT_MAX/clock.m1)
942 continue;
943
944 clock.m2 = m2;
945
946 chv_calc_dpll_params(refclk, &clock);
947
948 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
949 continue;
950
951 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
952 best_error_ppm, &error_ppm))
953 continue;
954
955 *best_clock = clock;
956 best_error_ppm = error_ppm;
957 found = true;
958 }
959 }
960
961 return found;
962 }
963
964 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
965 struct dpll *best_clock)
966 {
967 int refclk = 100000;
968 const struct intel_limit *limit = &intel_limits_bxt;
969
970 return chv_find_best_dpll(limit, crtc_state,
971 target_clock, refclk, NULL, best_clock);
972 }
973
974 bool intel_crtc_active(struct intel_crtc *crtc)
975 {
976 /* Be paranoid as we can arrive here with only partial
977 * state retrieved from the hardware during setup.
978 *
979 * We can ditch the adjusted_mode.crtc_clock check as soon
980 * as Haswell has gained clock readout/fastboot support.
981 *
982 * We can ditch the crtc->primary->fb check as soon as we can
983 * properly reconstruct framebuffers.
984 *
985 * FIXME: The intel_crtc->active here should be switched to
986 * crtc->state->active once we have proper CRTC states wired up
987 * for atomic.
988 */
989 return crtc->active && crtc->base.primary->state->fb &&
990 crtc->config->base.adjusted_mode.crtc_clock;
991 }
992
993 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
994 enum pipe pipe)
995 {
996 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
997
998 return crtc->config->cpu_transcoder;
999 }
1000
1001 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1002 {
1003 i915_reg_t reg = PIPEDSL(pipe);
1004 u32 line1, line2;
1005 u32 line_mask;
1006
1007 if (IS_GEN2(dev_priv))
1008 line_mask = DSL_LINEMASK_GEN2;
1009 else
1010 line_mask = DSL_LINEMASK_GEN3;
1011
1012 line1 = I915_READ(reg) & line_mask;
1013 msleep(5);
1014 line2 = I915_READ(reg) & line_mask;
1015
1016 return line1 == line2;
1017 }
1018
1019 /*
1020 * intel_wait_for_pipe_off - wait for pipe to turn off
1021 * @crtc: crtc whose pipe to wait for
1022 *
1023 * After disabling a pipe, we can't wait for vblank in the usual way,
1024 * spinning on the vblank interrupt status bit, since we won't actually
1025 * see an interrupt when the pipe is disabled.
1026 *
1027 * On Gen4 and above:
1028 * wait for the pipe register state bit to turn off
1029 *
1030 * Otherwise:
1031 * wait for the display line value to settle (it usually
1032 * ends up stopping at the start of the next frame).
1033 *
1034 */
1035 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1036 {
1037 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1038 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1039 enum pipe pipe = crtc->pipe;
1040
1041 if (INTEL_GEN(dev_priv) >= 4) {
1042 i915_reg_t reg = PIPECONF(cpu_transcoder);
1043
1044 /* Wait for the Pipe State to go off */
1045 if (intel_wait_for_register(dev_priv,
1046 reg, I965_PIPECONF_ACTIVE, 0,
1047 100))
1048 WARN(1, "pipe_off wait timed out\n");
1049 } else {
1050 /* Wait for the display line to settle */
1051 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1052 WARN(1, "pipe_off wait timed out\n");
1053 }
1054 }
1055
1056 /* Only for pre-ILK configs */
1057 void assert_pll(struct drm_i915_private *dev_priv,
1058 enum pipe pipe, bool state)
1059 {
1060 u32 val;
1061 bool cur_state;
1062
1063 val = I915_READ(DPLL(pipe));
1064 cur_state = !!(val & DPLL_VCO_ENABLE);
1065 I915_STATE_WARN(cur_state != state,
1066 "PLL state assertion failure (expected %s, current %s)\n",
1067 onoff(state), onoff(cur_state));
1068 }
1069
1070 /* XXX: the dsi pll is shared between MIPI DSI ports */
1071 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1072 {
1073 u32 val;
1074 bool cur_state;
1075
1076 mutex_lock(&dev_priv->sb_lock);
1077 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1078 mutex_unlock(&dev_priv->sb_lock);
1079
1080 cur_state = val & DSI_PLL_VCO_EN;
1081 I915_STATE_WARN(cur_state != state,
1082 "DSI PLL state assertion failure (expected %s, current %s)\n",
1083 onoff(state), onoff(cur_state));
1084 }
1085
1086 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1087 enum pipe pipe, bool state)
1088 {
1089 bool cur_state;
1090 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1091 pipe);
1092
1093 if (HAS_DDI(dev_priv)) {
1094 /* DDI does not have a specific FDI_TX register */
1095 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1096 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1097 } else {
1098 u32 val = I915_READ(FDI_TX_CTL(pipe));
1099 cur_state = !!(val & FDI_TX_ENABLE);
1100 }
1101 I915_STATE_WARN(cur_state != state,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 onoff(state), onoff(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1110 {
1111 u32 val;
1112 bool cur_state;
1113
1114 val = I915_READ(FDI_RX_CTL(pipe));
1115 cur_state = !!(val & FDI_RX_ENABLE);
1116 I915_STATE_WARN(cur_state != state,
1117 "FDI RX state assertion failure (expected %s, current %s)\n",
1118 onoff(state), onoff(cur_state));
1119 }
1120 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1121 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122
1123 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1124 enum pipe pipe)
1125 {
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
1129 if (IS_GEN5(dev_priv))
1130 return;
1131
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv))
1134 return;
1135
1136 val = I915_READ(FDI_TX_CTL(pipe));
1137 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1138 }
1139
1140 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1141 enum pipe pipe, bool state)
1142 {
1143 u32 val;
1144 bool cur_state;
1145
1146 val = I915_READ(FDI_RX_CTL(pipe));
1147 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1148 I915_STATE_WARN(cur_state != state,
1149 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1150 onoff(state), onoff(cur_state));
1151 }
1152
1153 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1154 {
1155 i915_reg_t pp_reg;
1156 u32 val;
1157 enum pipe panel_pipe = PIPE_A;
1158 bool locked = true;
1159
1160 if (WARN_ON(HAS_DDI(dev_priv)))
1161 return;
1162
1163 if (HAS_PCH_SPLIT(dev_priv)) {
1164 u32 port_sel;
1165
1166 pp_reg = PP_CONTROL(0);
1167 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1168
1169 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1170 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1171 panel_pipe = PIPE_B;
1172 /* XXX: else fix for eDP */
1173 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1174 /* presumably write lock depends on pipe, not port select */
1175 pp_reg = PP_CONTROL(pipe);
1176 panel_pipe = pipe;
1177 } else {
1178 pp_reg = PP_CONTROL(0);
1179 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1180 panel_pipe = PIPE_B;
1181 }
1182
1183 val = I915_READ(pp_reg);
1184 if (!(val & PANEL_POWER_ON) ||
1185 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1186 locked = false;
1187
1188 I915_STATE_WARN(panel_pipe == pipe && locked,
1189 "panel assertion failure, pipe %c regs locked\n",
1190 pipe_name(pipe));
1191 }
1192
1193 static void assert_cursor(struct drm_i915_private *dev_priv,
1194 enum pipe pipe, bool state)
1195 {
1196 bool cur_state;
1197
1198 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1199 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1200 else
1201 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1202
1203 I915_STATE_WARN(cur_state != state,
1204 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1205 pipe_name(pipe), onoff(state), onoff(cur_state));
1206 }
1207 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1208 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1209
1210 void assert_pipe(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212 {
1213 bool cur_state;
1214 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1215 pipe);
1216 enum intel_display_power_domain power_domain;
1217
1218 /* we keep both pipes enabled on 830 */
1219 if (IS_I830(dev_priv))
1220 state = true;
1221
1222 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1223 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1224 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1225 cur_state = !!(val & PIPECONF_ENABLE);
1226
1227 intel_display_power_put(dev_priv, power_domain);
1228 } else {
1229 cur_state = false;
1230 }
1231
1232 I915_STATE_WARN(cur_state != state,
1233 "pipe %c assertion failure (expected %s, current %s)\n",
1234 pipe_name(pipe), onoff(state), onoff(cur_state));
1235 }
1236
1237 static void assert_plane(struct drm_i915_private *dev_priv,
1238 enum plane plane, bool state)
1239 {
1240 u32 val;
1241 bool cur_state;
1242
1243 val = I915_READ(DSPCNTR(plane));
1244 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1245 I915_STATE_WARN(cur_state != state,
1246 "plane %c assertion failure (expected %s, current %s)\n",
1247 plane_name(plane), onoff(state), onoff(cur_state));
1248 }
1249
1250 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1251 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1252
1253 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1254 enum pipe pipe)
1255 {
1256 int i;
1257
1258 /* Primary planes are fixed to pipes on gen4+ */
1259 if (INTEL_GEN(dev_priv) >= 4) {
1260 u32 val = I915_READ(DSPCNTR(pipe));
1261 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1262 "plane %c assertion failure, should be disabled but not\n",
1263 plane_name(pipe));
1264 return;
1265 }
1266
1267 /* Need to check both planes against the pipe */
1268 for_each_pipe(dev_priv, i) {
1269 u32 val = I915_READ(DSPCNTR(i));
1270 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
1275 }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe)
1280 {
1281 int sprite;
1282
1283 if (INTEL_GEN(dev_priv) >= 9) {
1284 for_each_sprite(dev_priv, pipe, sprite) {
1285 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1286 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1287 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1288 sprite, pipe_name(pipe));
1289 }
1290 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1291 for_each_sprite(dev_priv, pipe, sprite) {
1292 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1293 I915_STATE_WARN(val & SP_ENABLE,
1294 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1295 sprite_name(pipe, sprite), pipe_name(pipe));
1296 }
1297 } else if (INTEL_GEN(dev_priv) >= 7) {
1298 u32 val = I915_READ(SPRCTL(pipe));
1299 I915_STATE_WARN(val & SPRITE_ENABLE,
1300 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1301 plane_name(pipe), pipe_name(pipe));
1302 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1303 u32 val = I915_READ(DVSCNTR(pipe));
1304 I915_STATE_WARN(val & DVS_ENABLE,
1305 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1306 plane_name(pipe), pipe_name(pipe));
1307 }
1308 }
1309
1310 static void assert_vblank_disabled(struct drm_crtc *crtc)
1311 {
1312 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1313 drm_crtc_vblank_put(crtc);
1314 }
1315
1316 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318 {
1319 u32 val;
1320 bool enabled;
1321
1322 val = I915_READ(PCH_TRANSCONF(pipe));
1323 enabled = !!(val & TRANS_ENABLE);
1324 I915_STATE_WARN(enabled,
1325 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326 pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330 enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332 if ((val & DP_PORT_EN) == 0)
1333 return false;
1334
1335 if (HAS_PCH_CPT(dev_priv)) {
1336 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1337 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1338 return false;
1339 } else if (IS_CHERRYVIEW(dev_priv)) {
1340 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351 {
1352 if ((val & SDVO_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv)) {
1356 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1357 return false;
1358 } else if (IS_CHERRYVIEW(dev_priv)) {
1359 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1360 return false;
1361 } else {
1362 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1363 return false;
1364 }
1365 return true;
1366 }
1367
1368 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe, u32 val)
1370 {
1371 if ((val & LVDS_PORT_EN) == 0)
1372 return false;
1373
1374 if (HAS_PCH_CPT(dev_priv)) {
1375 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1376 return false;
1377 } else {
1378 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1379 return false;
1380 }
1381 return true;
1382 }
1383
1384 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, u32 val)
1386 {
1387 if ((val & ADPA_DAC_ENABLE) == 0)
1388 return false;
1389 if (HAS_PCH_CPT(dev_priv)) {
1390 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1391 return false;
1392 } else {
1393 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1394 return false;
1395 }
1396 return true;
1397 }
1398
1399 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1400 enum pipe pipe, i915_reg_t reg,
1401 u32 port_sel)
1402 {
1403 u32 val = I915_READ(reg);
1404 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406 i915_mmio_reg_offset(reg), pipe_name(pipe));
1407
1408 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1409 && (val & DP_PIPEB_SELECT),
1410 "IBX PCH dp port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe, i915_reg_t reg)
1415 {
1416 u32 val = I915_READ(reg);
1417 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419 i915_mmio_reg_offset(reg), pipe_name(pipe));
1420
1421 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1422 && (val & SDVO_PIPE_B_SELECT),
1423 "IBX PCH hdmi port still using transcoder B\n");
1424 }
1425
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1427 enum pipe pipe)
1428 {
1429 u32 val;
1430
1431 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1432 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1433 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1434
1435 val = I915_READ(PCH_ADPA);
1436 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1437 "PCH VGA enabled on transcoder %c, should be disabled\n",
1438 pipe_name(pipe));
1439
1440 val = I915_READ(PCH_LVDS);
1441 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1442 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1443 pipe_name(pipe));
1444
1445 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1447 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1448 }
1449
1450 static void _vlv_enable_pll(struct intel_crtc *crtc,
1451 const struct intel_crtc_state *pipe_config)
1452 {
1453 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1454 enum pipe pipe = crtc->pipe;
1455
1456 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457 POSTING_READ(DPLL(pipe));
1458 udelay(150);
1459
1460 if (intel_wait_for_register(dev_priv,
1461 DPLL(pipe),
1462 DPLL_LOCK_VLV,
1463 DPLL_LOCK_VLV,
1464 1))
1465 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1466 }
1467
1468 static void vlv_enable_pll(struct intel_crtc *crtc,
1469 const struct intel_crtc_state *pipe_config)
1470 {
1471 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1472 enum pipe pipe = crtc->pipe;
1473
1474 assert_pipe_disabled(dev_priv, pipe);
1475
1476 /* PLL is protected by panel, make sure we can write it */
1477 assert_panel_unlocked(dev_priv, pipe);
1478
1479 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1480 _vlv_enable_pll(crtc, pipe_config);
1481
1482 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1483 POSTING_READ(DPLL_MD(pipe));
1484 }
1485
1486
1487 static void _chv_enable_pll(struct intel_crtc *crtc,
1488 const struct intel_crtc_state *pipe_config)
1489 {
1490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1491 enum pipe pipe = crtc->pipe;
1492 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1493 u32 tmp;
1494
1495 mutex_lock(&dev_priv->sb_lock);
1496
1497 /* Enable back the 10bit clock to display controller */
1498 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1499 tmp |= DPIO_DCLKP_EN;
1500 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1501
1502 mutex_unlock(&dev_priv->sb_lock);
1503
1504 /*
1505 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1506 */
1507 udelay(1);
1508
1509 /* Enable PLL */
1510 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1511
1512 /* Check PLL is locked */
1513 if (intel_wait_for_register(dev_priv,
1514 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1515 1))
1516 DRM_ERROR("PLL %d failed to lock\n", pipe);
1517 }
1518
1519 static void chv_enable_pll(struct intel_crtc *crtc,
1520 const struct intel_crtc_state *pipe_config)
1521 {
1522 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1523 enum pipe pipe = crtc->pipe;
1524
1525 assert_pipe_disabled(dev_priv, pipe);
1526
1527 /* PLL is protected by panel, make sure we can write it */
1528 assert_panel_unlocked(dev_priv, pipe);
1529
1530 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1531 _chv_enable_pll(crtc, pipe_config);
1532
1533 if (pipe != PIPE_A) {
1534 /*
1535 * WaPixelRepeatModeFixForC0:chv
1536 *
1537 * DPLLCMD is AWOL. Use chicken bits to propagate
1538 * the value from DPLLBMD to either pipe B or C.
1539 */
1540 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1541 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1542 I915_WRITE(CBR4_VLV, 0);
1543 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1544
1545 /*
1546 * DPLLB VGA mode also seems to cause problems.
1547 * We should always have it disabled.
1548 */
1549 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1550 } else {
1551 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1552 POSTING_READ(DPLL_MD(pipe));
1553 }
1554 }
1555
1556 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1557 {
1558 struct intel_crtc *crtc;
1559 int count = 0;
1560
1561 for_each_intel_crtc(&dev_priv->drm, crtc) {
1562 count += crtc->base.state->active &&
1563 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1564 }
1565
1566 return count;
1567 }
1568
1569 static void i9xx_enable_pll(struct intel_crtc *crtc,
1570 const struct intel_crtc_state *crtc_state)
1571 {
1572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1573 i915_reg_t reg = DPLL(crtc->pipe);
1574 u32 dpll = crtc_state->dpll_hw_state.dpll;
1575 int i;
1576
1577 assert_pipe_disabled(dev_priv, crtc->pipe);
1578
1579 /* PLL is protected by panel, make sure we can write it */
1580 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1581 assert_panel_unlocked(dev_priv, crtc->pipe);
1582
1583 /* Enable DVO 2x clock on both PLLs if necessary */
1584 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1585 /*
1586 * It appears to be important that we don't enable this
1587 * for the current pipe before otherwise configuring the
1588 * PLL. No idea how this should be handled if multiple
1589 * DVO outputs are enabled simultaneosly.
1590 */
1591 dpll |= DPLL_DVO_2X_MODE;
1592 I915_WRITE(DPLL(!crtc->pipe),
1593 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1594 }
1595
1596 /*
1597 * Apparently we need to have VGA mode enabled prior to changing
1598 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1599 * dividers, even though the register value does change.
1600 */
1601 I915_WRITE(reg, 0);
1602
1603 I915_WRITE(reg, dpll);
1604
1605 /* Wait for the clocks to stabilize. */
1606 POSTING_READ(reg);
1607 udelay(150);
1608
1609 if (INTEL_GEN(dev_priv) >= 4) {
1610 I915_WRITE(DPLL_MD(crtc->pipe),
1611 crtc_state->dpll_hw_state.dpll_md);
1612 } else {
1613 /* The pixel multiplier can only be updated once the
1614 * DPLL is enabled and the clocks are stable.
1615 *
1616 * So write it again.
1617 */
1618 I915_WRITE(reg, dpll);
1619 }
1620
1621 /* We do this three times for luck */
1622 for (i = 0; i < 3; i++) {
1623 I915_WRITE(reg, dpll);
1624 POSTING_READ(reg);
1625 udelay(150); /* wait for warmup */
1626 }
1627 }
1628
1629 static void i9xx_disable_pll(struct intel_crtc *crtc)
1630 {
1631 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1632 enum pipe pipe = crtc->pipe;
1633
1634 /* Disable DVO 2x clock on both PLLs if necessary */
1635 if (IS_I830(dev_priv) &&
1636 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1637 !intel_num_dvo_pipes(dev_priv)) {
1638 I915_WRITE(DPLL(PIPE_B),
1639 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1640 I915_WRITE(DPLL(PIPE_A),
1641 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1642 }
1643
1644 /* Don't disable pipe or pipe PLLs if needed */
1645 if (IS_I830(dev_priv))
1646 return;
1647
1648 /* Make sure the pipe isn't still relying on us */
1649 assert_pipe_disabled(dev_priv, pipe);
1650
1651 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1652 POSTING_READ(DPLL(pipe));
1653 }
1654
1655 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1656 {
1657 u32 val;
1658
1659 /* Make sure the pipe isn't still relying on us */
1660 assert_pipe_disabled(dev_priv, pipe);
1661
1662 val = DPLL_INTEGRATED_REF_CLK_VLV |
1663 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1664 if (pipe != PIPE_A)
1665 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1666
1667 I915_WRITE(DPLL(pipe), val);
1668 POSTING_READ(DPLL(pipe));
1669 }
1670
1671 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1672 {
1673 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1674 u32 val;
1675
1676 /* Make sure the pipe isn't still relying on us */
1677 assert_pipe_disabled(dev_priv, pipe);
1678
1679 val = DPLL_SSC_REF_CLK_CHV |
1680 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1681 if (pipe != PIPE_A)
1682 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1683
1684 I915_WRITE(DPLL(pipe), val);
1685 POSTING_READ(DPLL(pipe));
1686
1687 mutex_lock(&dev_priv->sb_lock);
1688
1689 /* Disable 10bit clock to display controller */
1690 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1691 val &= ~DPIO_DCLKP_EN;
1692 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1693
1694 mutex_unlock(&dev_priv->sb_lock);
1695 }
1696
1697 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1698 struct intel_digital_port *dport,
1699 unsigned int expected_mask)
1700 {
1701 u32 port_mask;
1702 i915_reg_t dpll_reg;
1703
1704 switch (dport->base.port) {
1705 case PORT_B:
1706 port_mask = DPLL_PORTB_READY_MASK;
1707 dpll_reg = DPLL(0);
1708 break;
1709 case PORT_C:
1710 port_mask = DPLL_PORTC_READY_MASK;
1711 dpll_reg = DPLL(0);
1712 expected_mask <<= 4;
1713 break;
1714 case PORT_D:
1715 port_mask = DPLL_PORTD_READY_MASK;
1716 dpll_reg = DPIO_PHY_STATUS;
1717 break;
1718 default:
1719 BUG();
1720 }
1721
1722 if (intel_wait_for_register(dev_priv,
1723 dpll_reg, port_mask, expected_mask,
1724 1000))
1725 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1726 port_name(dport->base.port),
1727 I915_READ(dpll_reg) & port_mask, expected_mask);
1728 }
1729
1730 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1731 enum pipe pipe)
1732 {
1733 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1734 pipe);
1735 i915_reg_t reg;
1736 uint32_t val, pipeconf_val;
1737
1738 /* Make sure PCH DPLL is enabled */
1739 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1740
1741 /* FDI must be feeding us bits for PCH ports */
1742 assert_fdi_tx_enabled(dev_priv, pipe);
1743 assert_fdi_rx_enabled(dev_priv, pipe);
1744
1745 if (HAS_PCH_CPT(dev_priv)) {
1746 /* Workaround: Set the timing override bit before enabling the
1747 * pch transcoder. */
1748 reg = TRANS_CHICKEN2(pipe);
1749 val = I915_READ(reg);
1750 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1751 I915_WRITE(reg, val);
1752 }
1753
1754 reg = PCH_TRANSCONF(pipe);
1755 val = I915_READ(reg);
1756 pipeconf_val = I915_READ(PIPECONF(pipe));
1757
1758 if (HAS_PCH_IBX(dev_priv)) {
1759 /*
1760 * Make the BPC in transcoder be consistent with
1761 * that in pipeconf reg. For HDMI we must use 8bpc
1762 * here for both 8bpc and 12bpc.
1763 */
1764 val &= ~PIPECONF_BPC_MASK;
1765 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1766 val |= PIPECONF_8BPC;
1767 else
1768 val |= pipeconf_val & PIPECONF_BPC_MASK;
1769 }
1770
1771 val &= ~TRANS_INTERLACE_MASK;
1772 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1773 if (HAS_PCH_IBX(dev_priv) &&
1774 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1775 val |= TRANS_LEGACY_INTERLACED_ILK;
1776 else
1777 val |= TRANS_INTERLACED;
1778 else
1779 val |= TRANS_PROGRESSIVE;
1780
1781 I915_WRITE(reg, val | TRANS_ENABLE);
1782 if (intel_wait_for_register(dev_priv,
1783 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1784 100))
1785 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1786 }
1787
1788 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1789 enum transcoder cpu_transcoder)
1790 {
1791 u32 val, pipeconf_val;
1792
1793 /* FDI must be feeding us bits for PCH ports */
1794 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1795 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1796
1797 /* Workaround: set timing override bit. */
1798 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1799 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1801
1802 val = TRANS_ENABLE;
1803 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1804
1805 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1806 PIPECONF_INTERLACED_ILK)
1807 val |= TRANS_INTERLACED;
1808 else
1809 val |= TRANS_PROGRESSIVE;
1810
1811 I915_WRITE(LPT_TRANSCONF, val);
1812 if (intel_wait_for_register(dev_priv,
1813 LPT_TRANSCONF,
1814 TRANS_STATE_ENABLE,
1815 TRANS_STATE_ENABLE,
1816 100))
1817 DRM_ERROR("Failed to enable PCH transcoder\n");
1818 }
1819
1820 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1821 enum pipe pipe)
1822 {
1823 i915_reg_t reg;
1824 uint32_t val;
1825
1826 /* FDI relies on the transcoder */
1827 assert_fdi_tx_disabled(dev_priv, pipe);
1828 assert_fdi_rx_disabled(dev_priv, pipe);
1829
1830 /* Ports must be off as well */
1831 assert_pch_ports_disabled(dev_priv, pipe);
1832
1833 reg = PCH_TRANSCONF(pipe);
1834 val = I915_READ(reg);
1835 val &= ~TRANS_ENABLE;
1836 I915_WRITE(reg, val);
1837 /* wait for PCH transcoder off, transcoder state */
1838 if (intel_wait_for_register(dev_priv,
1839 reg, TRANS_STATE_ENABLE, 0,
1840 50))
1841 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1842
1843 if (HAS_PCH_CPT(dev_priv)) {
1844 /* Workaround: Clear the timing override chicken bit again. */
1845 reg = TRANS_CHICKEN2(pipe);
1846 val = I915_READ(reg);
1847 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1848 I915_WRITE(reg, val);
1849 }
1850 }
1851
1852 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1853 {
1854 u32 val;
1855
1856 val = I915_READ(LPT_TRANSCONF);
1857 val &= ~TRANS_ENABLE;
1858 I915_WRITE(LPT_TRANSCONF, val);
1859 /* wait for PCH transcoder off, transcoder state */
1860 if (intel_wait_for_register(dev_priv,
1861 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1862 50))
1863 DRM_ERROR("Failed to disable PCH transcoder\n");
1864
1865 /* Workaround: clear timing override bit. */
1866 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1867 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1868 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1869 }
1870
1871 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1872 {
1873 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1874
1875 if (HAS_PCH_LPT(dev_priv))
1876 return PIPE_A;
1877 else
1878 return crtc->pipe;
1879 }
1880
1881 /**
1882 * intel_enable_pipe - enable a pipe, asserting requirements
1883 * @crtc: crtc responsible for the pipe
1884 *
1885 * Enable @crtc's pipe, making sure that various hardware specific requirements
1886 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1887 */
1888 static void intel_enable_pipe(struct intel_crtc *crtc)
1889 {
1890 struct drm_device *dev = crtc->base.dev;
1891 struct drm_i915_private *dev_priv = to_i915(dev);
1892 enum pipe pipe = crtc->pipe;
1893 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1894 i915_reg_t reg;
1895 u32 val;
1896
1897 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1898
1899 assert_planes_disabled(dev_priv, pipe);
1900 assert_cursor_disabled(dev_priv, pipe);
1901 assert_sprites_disabled(dev_priv, pipe);
1902
1903 /*
1904 * A pipe without a PLL won't actually be able to drive bits from
1905 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1906 * need the check.
1907 */
1908 if (HAS_GMCH_DISPLAY(dev_priv)) {
1909 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1910 assert_dsi_pll_enabled(dev_priv);
1911 else
1912 assert_pll_enabled(dev_priv, pipe);
1913 } else {
1914 if (crtc->config->has_pch_encoder) {
1915 /* if driving the PCH, we need FDI enabled */
1916 assert_fdi_rx_pll_enabled(dev_priv,
1917 intel_crtc_pch_transcoder(crtc));
1918 assert_fdi_tx_pll_enabled(dev_priv,
1919 (enum pipe) cpu_transcoder);
1920 }
1921 /* FIXME: assert CPU port conditions for SNB+ */
1922 }
1923
1924 reg = PIPECONF(cpu_transcoder);
1925 val = I915_READ(reg);
1926 if (val & PIPECONF_ENABLE) {
1927 /* we keep both pipes enabled on 830 */
1928 WARN_ON(!IS_I830(dev_priv));
1929 return;
1930 }
1931
1932 I915_WRITE(reg, val | PIPECONF_ENABLE);
1933 POSTING_READ(reg);
1934
1935 /*
1936 * Until the pipe starts DSL will read as 0, which would cause
1937 * an apparent vblank timestamp jump, which messes up also the
1938 * frame count when it's derived from the timestamps. So let's
1939 * wait for the pipe to start properly before we call
1940 * drm_crtc_vblank_on()
1941 */
1942 if (dev->max_vblank_count == 0 &&
1943 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1944 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1945 }
1946
1947 /**
1948 * intel_disable_pipe - disable a pipe, asserting requirements
1949 * @crtc: crtc whose pipes is to be disabled
1950 *
1951 * Disable the pipe of @crtc, making sure that various hardware
1952 * specific requirements are met, if applicable, e.g. plane
1953 * disabled, panel fitter off, etc.
1954 *
1955 * Will wait until the pipe has shut down before returning.
1956 */
1957 static void intel_disable_pipe(struct intel_crtc *crtc)
1958 {
1959 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1960 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1961 enum pipe pipe = crtc->pipe;
1962 i915_reg_t reg;
1963 u32 val;
1964
1965 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1966
1967 /*
1968 * Make sure planes won't keep trying to pump pixels to us,
1969 * or we might hang the display.
1970 */
1971 assert_planes_disabled(dev_priv, pipe);
1972 assert_cursor_disabled(dev_priv, pipe);
1973 assert_sprites_disabled(dev_priv, pipe);
1974
1975 reg = PIPECONF(cpu_transcoder);
1976 val = I915_READ(reg);
1977 if ((val & PIPECONF_ENABLE) == 0)
1978 return;
1979
1980 /*
1981 * Double wide has implications for planes
1982 * so best keep it disabled when not needed.
1983 */
1984 if (crtc->config->double_wide)
1985 val &= ~PIPECONF_DOUBLE_WIDE;
1986
1987 /* Don't disable pipe or pipe PLLs if needed */
1988 if (!IS_I830(dev_priv))
1989 val &= ~PIPECONF_ENABLE;
1990
1991 I915_WRITE(reg, val);
1992 if ((val & PIPECONF_ENABLE) == 0)
1993 intel_wait_for_pipe_off(crtc);
1994 }
1995
1996 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1997 {
1998 return IS_GEN2(dev_priv) ? 2048 : 4096;
1999 }
2000
2001 static unsigned int
2002 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2003 {
2004 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2005 unsigned int cpp = fb->format->cpp[plane];
2006
2007 switch (fb->modifier) {
2008 case DRM_FORMAT_MOD_LINEAR:
2009 return cpp;
2010 case I915_FORMAT_MOD_X_TILED:
2011 if (IS_GEN2(dev_priv))
2012 return 128;
2013 else
2014 return 512;
2015 case I915_FORMAT_MOD_Y_TILED_CCS:
2016 if (plane == 1)
2017 return 128;
2018 /* fall through */
2019 case I915_FORMAT_MOD_Y_TILED:
2020 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2021 return 128;
2022 else
2023 return 512;
2024 case I915_FORMAT_MOD_Yf_TILED_CCS:
2025 if (plane == 1)
2026 return 128;
2027 /* fall through */
2028 case I915_FORMAT_MOD_Yf_TILED:
2029 switch (cpp) {
2030 case 1:
2031 return 64;
2032 case 2:
2033 case 4:
2034 return 128;
2035 case 8:
2036 case 16:
2037 return 256;
2038 default:
2039 MISSING_CASE(cpp);
2040 return cpp;
2041 }
2042 break;
2043 default:
2044 MISSING_CASE(fb->modifier);
2045 return cpp;
2046 }
2047 }
2048
2049 static unsigned int
2050 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2051 {
2052 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2053 return 1;
2054 else
2055 return intel_tile_size(to_i915(fb->dev)) /
2056 intel_tile_width_bytes(fb, plane);
2057 }
2058
2059 /* Return the tile dimensions in pixel units */
2060 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2061 unsigned int *tile_width,
2062 unsigned int *tile_height)
2063 {
2064 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2065 unsigned int cpp = fb->format->cpp[plane];
2066
2067 *tile_width = tile_width_bytes / cpp;
2068 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2069 }
2070
2071 unsigned int
2072 intel_fb_align_height(const struct drm_framebuffer *fb,
2073 int plane, unsigned int height)
2074 {
2075 unsigned int tile_height = intel_tile_height(fb, plane);
2076
2077 return ALIGN(height, tile_height);
2078 }
2079
2080 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2081 {
2082 unsigned int size = 0;
2083 int i;
2084
2085 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2086 size += rot_info->plane[i].width * rot_info->plane[i].height;
2087
2088 return size;
2089 }
2090
2091 static void
2092 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2093 const struct drm_framebuffer *fb,
2094 unsigned int rotation)
2095 {
2096 view->type = I915_GGTT_VIEW_NORMAL;
2097 if (drm_rotation_90_or_270(rotation)) {
2098 view->type = I915_GGTT_VIEW_ROTATED;
2099 view->rotated = to_intel_framebuffer(fb)->rot_info;
2100 }
2101 }
2102
2103 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2104 {
2105 if (IS_I830(dev_priv))
2106 return 16 * 1024;
2107 else if (IS_I85X(dev_priv))
2108 return 256;
2109 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2110 return 32;
2111 else
2112 return 4 * 1024;
2113 }
2114
2115 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2116 {
2117 if (INTEL_INFO(dev_priv)->gen >= 9)
2118 return 256 * 1024;
2119 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2120 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2121 return 128 * 1024;
2122 else if (INTEL_INFO(dev_priv)->gen >= 4)
2123 return 4 * 1024;
2124 else
2125 return 0;
2126 }
2127
2128 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2129 int plane)
2130 {
2131 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2132
2133 /* AUX_DIST needs only 4K alignment */
2134 if (plane == 1)
2135 return 4096;
2136
2137 switch (fb->modifier) {
2138 case DRM_FORMAT_MOD_LINEAR:
2139 return intel_linear_alignment(dev_priv);
2140 case I915_FORMAT_MOD_X_TILED:
2141 if (INTEL_GEN(dev_priv) >= 9)
2142 return 256 * 1024;
2143 return 0;
2144 case I915_FORMAT_MOD_Y_TILED_CCS:
2145 case I915_FORMAT_MOD_Yf_TILED_CCS:
2146 case I915_FORMAT_MOD_Y_TILED:
2147 case I915_FORMAT_MOD_Yf_TILED:
2148 return 1 * 1024 * 1024;
2149 default:
2150 MISSING_CASE(fb->modifier);
2151 return 0;
2152 }
2153 }
2154
2155 struct i915_vma *
2156 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2157 {
2158 struct drm_device *dev = fb->dev;
2159 struct drm_i915_private *dev_priv = to_i915(dev);
2160 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2161 struct i915_ggtt_view view;
2162 struct i915_vma *vma;
2163 u32 alignment;
2164
2165 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2166
2167 alignment = intel_surf_alignment(fb, 0);
2168
2169 intel_fill_fb_ggtt_view(&view, fb, rotation);
2170
2171 /* Note that the w/a also requires 64 PTE of padding following the
2172 * bo. We currently fill all unused PTE with the shadow page and so
2173 * we should always have valid PTE following the scanout preventing
2174 * the VT-d warning.
2175 */
2176 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2177 alignment = 256 * 1024;
2178
2179 /*
2180 * Global gtt pte registers are special registers which actually forward
2181 * writes to a chunk of system memory. Which means that there is no risk
2182 * that the register values disappear as soon as we call
2183 * intel_runtime_pm_put(), so it is correct to wrap only the
2184 * pin/unpin/fence and not more.
2185 */
2186 intel_runtime_pm_get(dev_priv);
2187
2188 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2189
2190 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2191 if (IS_ERR(vma))
2192 goto err;
2193
2194 if (i915_vma_is_map_and_fenceable(vma)) {
2195 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2196 * fence, whereas 965+ only requires a fence if using
2197 * framebuffer compression. For simplicity, we always, when
2198 * possible, install a fence as the cost is not that onerous.
2199 *
2200 * If we fail to fence the tiled scanout, then either the
2201 * modeset will reject the change (which is highly unlikely as
2202 * the affected systems, all but one, do not have unmappable
2203 * space) or we will not be able to enable full powersaving
2204 * techniques (also likely not to apply due to various limits
2205 * FBC and the like impose on the size of the buffer, which
2206 * presumably we violated anyway with this unmappable buffer).
2207 * Anyway, it is presumably better to stumble onwards with
2208 * something and try to run the system in a "less than optimal"
2209 * mode that matches the user configuration.
2210 */
2211 i915_vma_pin_fence(vma);
2212 }
2213
2214 i915_vma_get(vma);
2215 err:
2216 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2217
2218 intel_runtime_pm_put(dev_priv);
2219 return vma;
2220 }
2221
2222 void intel_unpin_fb_vma(struct i915_vma *vma)
2223 {
2224 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2225
2226 i915_vma_unpin_fence(vma);
2227 i915_gem_object_unpin_from_display_plane(vma);
2228 i915_vma_put(vma);
2229 }
2230
2231 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2232 unsigned int rotation)
2233 {
2234 if (drm_rotation_90_or_270(rotation))
2235 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2236 else
2237 return fb->pitches[plane];
2238 }
2239
2240 /*
2241 * Convert the x/y offsets into a linear offset.
2242 * Only valid with 0/180 degree rotation, which is fine since linear
2243 * offset is only used with linear buffers on pre-hsw and tiled buffers
2244 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2245 */
2246 u32 intel_fb_xy_to_linear(int x, int y,
2247 const struct intel_plane_state *state,
2248 int plane)
2249 {
2250 const struct drm_framebuffer *fb = state->base.fb;
2251 unsigned int cpp = fb->format->cpp[plane];
2252 unsigned int pitch = fb->pitches[plane];
2253
2254 return y * pitch + x * cpp;
2255 }
2256
2257 /*
2258 * Add the x/y offsets derived from fb->offsets[] to the user
2259 * specified plane src x/y offsets. The resulting x/y offsets
2260 * specify the start of scanout from the beginning of the gtt mapping.
2261 */
2262 void intel_add_fb_offsets(int *x, int *y,
2263 const struct intel_plane_state *state,
2264 int plane)
2265
2266 {
2267 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2268 unsigned int rotation = state->base.rotation;
2269
2270 if (drm_rotation_90_or_270(rotation)) {
2271 *x += intel_fb->rotated[plane].x;
2272 *y += intel_fb->rotated[plane].y;
2273 } else {
2274 *x += intel_fb->normal[plane].x;
2275 *y += intel_fb->normal[plane].y;
2276 }
2277 }
2278
2279 static u32 __intel_adjust_tile_offset(int *x, int *y,
2280 unsigned int tile_width,
2281 unsigned int tile_height,
2282 unsigned int tile_size,
2283 unsigned int pitch_tiles,
2284 u32 old_offset,
2285 u32 new_offset)
2286 {
2287 unsigned int pitch_pixels = pitch_tiles * tile_width;
2288 unsigned int tiles;
2289
2290 WARN_ON(old_offset & (tile_size - 1));
2291 WARN_ON(new_offset & (tile_size - 1));
2292 WARN_ON(new_offset > old_offset);
2293
2294 tiles = (old_offset - new_offset) / tile_size;
2295
2296 *y += tiles / pitch_tiles * tile_height;
2297 *x += tiles % pitch_tiles * tile_width;
2298
2299 /* minimize x in case it got needlessly big */
2300 *y += *x / pitch_pixels * tile_height;
2301 *x %= pitch_pixels;
2302
2303 return new_offset;
2304 }
2305
2306 static u32 _intel_adjust_tile_offset(int *x, int *y,
2307 const struct drm_framebuffer *fb, int plane,
2308 unsigned int rotation,
2309 u32 old_offset, u32 new_offset)
2310 {
2311 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2312 unsigned int cpp = fb->format->cpp[plane];
2313 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2314
2315 WARN_ON(new_offset > old_offset);
2316
2317 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2318 unsigned int tile_size, tile_width, tile_height;
2319 unsigned int pitch_tiles;
2320
2321 tile_size = intel_tile_size(dev_priv);
2322 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2323
2324 if (drm_rotation_90_or_270(rotation)) {
2325 pitch_tiles = pitch / tile_height;
2326 swap(tile_width, tile_height);
2327 } else {
2328 pitch_tiles = pitch / (tile_width * cpp);
2329 }
2330
2331 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2332 tile_size, pitch_tiles,
2333 old_offset, new_offset);
2334 } else {
2335 old_offset += *y * pitch + *x * cpp;
2336
2337 *y = (old_offset - new_offset) / pitch;
2338 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2339 }
2340
2341 return new_offset;
2342 }
2343
2344 /*
2345 * Adjust the tile offset by moving the difference into
2346 * the x/y offsets.
2347 */
2348 static u32 intel_adjust_tile_offset(int *x, int *y,
2349 const struct intel_plane_state *state, int plane,
2350 u32 old_offset, u32 new_offset)
2351 {
2352 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2353 state->base.rotation,
2354 old_offset, new_offset);
2355 }
2356
2357 /*
2358 * Computes the linear offset to the base tile and adjusts
2359 * x, y. bytes per pixel is assumed to be a power-of-two.
2360 *
2361 * In the 90/270 rotated case, x and y are assumed
2362 * to be already rotated to match the rotated GTT view, and
2363 * pitch is the tile_height aligned framebuffer height.
2364 *
2365 * This function is used when computing the derived information
2366 * under intel_framebuffer, so using any of that information
2367 * here is not allowed. Anything under drm_framebuffer can be
2368 * used. This is why the user has to pass in the pitch since it
2369 * is specified in the rotated orientation.
2370 */
2371 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2372 int *x, int *y,
2373 const struct drm_framebuffer *fb, int plane,
2374 unsigned int pitch,
2375 unsigned int rotation,
2376 u32 alignment)
2377 {
2378 uint64_t fb_modifier = fb->modifier;
2379 unsigned int cpp = fb->format->cpp[plane];
2380 u32 offset, offset_aligned;
2381
2382 if (alignment)
2383 alignment--;
2384
2385 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2386 unsigned int tile_size, tile_width, tile_height;
2387 unsigned int tile_rows, tiles, pitch_tiles;
2388
2389 tile_size = intel_tile_size(dev_priv);
2390 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2391
2392 if (drm_rotation_90_or_270(rotation)) {
2393 pitch_tiles = pitch / tile_height;
2394 swap(tile_width, tile_height);
2395 } else {
2396 pitch_tiles = pitch / (tile_width * cpp);
2397 }
2398
2399 tile_rows = *y / tile_height;
2400 *y %= tile_height;
2401
2402 tiles = *x / tile_width;
2403 *x %= tile_width;
2404
2405 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2406 offset_aligned = offset & ~alignment;
2407
2408 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2409 tile_size, pitch_tiles,
2410 offset, offset_aligned);
2411 } else {
2412 offset = *y * pitch + *x * cpp;
2413 offset_aligned = offset & ~alignment;
2414
2415 *y = (offset & alignment) / pitch;
2416 *x = ((offset & alignment) - *y * pitch) / cpp;
2417 }
2418
2419 return offset_aligned;
2420 }
2421
2422 u32 intel_compute_tile_offset(int *x, int *y,
2423 const struct intel_plane_state *state,
2424 int plane)
2425 {
2426 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2427 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2428 const struct drm_framebuffer *fb = state->base.fb;
2429 unsigned int rotation = state->base.rotation;
2430 int pitch = intel_fb_pitch(fb, plane, rotation);
2431 u32 alignment;
2432
2433 if (intel_plane->id == PLANE_CURSOR)
2434 alignment = intel_cursor_alignment(dev_priv);
2435 else
2436 alignment = intel_surf_alignment(fb, plane);
2437
2438 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2439 rotation, alignment);
2440 }
2441
2442 /* Convert the fb->offset[] into x/y offsets */
2443 static int intel_fb_offset_to_xy(int *x, int *y,
2444 const struct drm_framebuffer *fb, int plane)
2445 {
2446 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2447
2448 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2449 fb->offsets[plane] % intel_tile_size(dev_priv))
2450 return -EINVAL;
2451
2452 *x = 0;
2453 *y = 0;
2454
2455 _intel_adjust_tile_offset(x, y,
2456 fb, plane, DRM_MODE_ROTATE_0,
2457 fb->offsets[plane], 0);
2458
2459 return 0;
2460 }
2461
2462 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2463 {
2464 switch (fb_modifier) {
2465 case I915_FORMAT_MOD_X_TILED:
2466 return I915_TILING_X;
2467 case I915_FORMAT_MOD_Y_TILED:
2468 case I915_FORMAT_MOD_Y_TILED_CCS:
2469 return I915_TILING_Y;
2470 default:
2471 return I915_TILING_NONE;
2472 }
2473 }
2474
2475 static const struct drm_format_info ccs_formats[] = {
2476 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2477 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2478 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2479 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2480 };
2481
2482 static const struct drm_format_info *
2483 lookup_format_info(const struct drm_format_info formats[],
2484 int num_formats, u32 format)
2485 {
2486 int i;
2487
2488 for (i = 0; i < num_formats; i++) {
2489 if (formats[i].format == format)
2490 return &formats[i];
2491 }
2492
2493 return NULL;
2494 }
2495
2496 static const struct drm_format_info *
2497 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2498 {
2499 switch (cmd->modifier[0]) {
2500 case I915_FORMAT_MOD_Y_TILED_CCS:
2501 case I915_FORMAT_MOD_Yf_TILED_CCS:
2502 return lookup_format_info(ccs_formats,
2503 ARRAY_SIZE(ccs_formats),
2504 cmd->pixel_format);
2505 default:
2506 return NULL;
2507 }
2508 }
2509
2510 static int
2511 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2512 struct drm_framebuffer *fb)
2513 {
2514 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2515 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2516 u32 gtt_offset_rotated = 0;
2517 unsigned int max_size = 0;
2518 int i, num_planes = fb->format->num_planes;
2519 unsigned int tile_size = intel_tile_size(dev_priv);
2520
2521 for (i = 0; i < num_planes; i++) {
2522 unsigned int width, height;
2523 unsigned int cpp, size;
2524 u32 offset;
2525 int x, y;
2526 int ret;
2527
2528 cpp = fb->format->cpp[i];
2529 width = drm_framebuffer_plane_width(fb->width, fb, i);
2530 height = drm_framebuffer_plane_height(fb->height, fb, i);
2531
2532 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2533 if (ret) {
2534 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2535 i, fb->offsets[i]);
2536 return ret;
2537 }
2538
2539 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2540 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2541 int hsub = fb->format->hsub;
2542 int vsub = fb->format->vsub;
2543 int tile_width, tile_height;
2544 int main_x, main_y;
2545 int ccs_x, ccs_y;
2546
2547 intel_tile_dims(fb, i, &tile_width, &tile_height);
2548 tile_width *= hsub;
2549 tile_height *= vsub;
2550
2551 ccs_x = (x * hsub) % tile_width;
2552 ccs_y = (y * vsub) % tile_height;
2553 main_x = intel_fb->normal[0].x % tile_width;
2554 main_y = intel_fb->normal[0].y % tile_height;
2555
2556 /*
2557 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2558 * x/y offsets must match between CCS and the main surface.
2559 */
2560 if (main_x != ccs_x || main_y != ccs_y) {
2561 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2562 main_x, main_y,
2563 ccs_x, ccs_y,
2564 intel_fb->normal[0].x,
2565 intel_fb->normal[0].y,
2566 x, y);
2567 return -EINVAL;
2568 }
2569 }
2570
2571 /*
2572 * The fence (if used) is aligned to the start of the object
2573 * so having the framebuffer wrap around across the edge of the
2574 * fenced region doesn't really work. We have no API to configure
2575 * the fence start offset within the object (nor could we probably
2576 * on gen2/3). So it's just easier if we just require that the
2577 * fb layout agrees with the fence layout. We already check that the
2578 * fb stride matches the fence stride elsewhere.
2579 */
2580 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2581 (x + width) * cpp > fb->pitches[i]) {
2582 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2583 i, fb->offsets[i]);
2584 return -EINVAL;
2585 }
2586
2587 /*
2588 * First pixel of the framebuffer from
2589 * the start of the normal gtt mapping.
2590 */
2591 intel_fb->normal[i].x = x;
2592 intel_fb->normal[i].y = y;
2593
2594 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2595 fb, i, fb->pitches[i],
2596 DRM_MODE_ROTATE_0, tile_size);
2597 offset /= tile_size;
2598
2599 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2600 unsigned int tile_width, tile_height;
2601 unsigned int pitch_tiles;
2602 struct drm_rect r;
2603
2604 intel_tile_dims(fb, i, &tile_width, &tile_height);
2605
2606 rot_info->plane[i].offset = offset;
2607 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2608 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2609 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2610
2611 intel_fb->rotated[i].pitch =
2612 rot_info->plane[i].height * tile_height;
2613
2614 /* how many tiles does this plane need */
2615 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2616 /*
2617 * If the plane isn't horizontally tile aligned,
2618 * we need one more tile.
2619 */
2620 if (x != 0)
2621 size++;
2622
2623 /* rotate the x/y offsets to match the GTT view */
2624 r.x1 = x;
2625 r.y1 = y;
2626 r.x2 = x + width;
2627 r.y2 = y + height;
2628 drm_rect_rotate(&r,
2629 rot_info->plane[i].width * tile_width,
2630 rot_info->plane[i].height * tile_height,
2631 DRM_MODE_ROTATE_270);
2632 x = r.x1;
2633 y = r.y1;
2634
2635 /* rotate the tile dimensions to match the GTT view */
2636 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2637 swap(tile_width, tile_height);
2638
2639 /*
2640 * We only keep the x/y offsets, so push all of the
2641 * gtt offset into the x/y offsets.
2642 */
2643 __intel_adjust_tile_offset(&x, &y,
2644 tile_width, tile_height,
2645 tile_size, pitch_tiles,
2646 gtt_offset_rotated * tile_size, 0);
2647
2648 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2649
2650 /*
2651 * First pixel of the framebuffer from
2652 * the start of the rotated gtt mapping.
2653 */
2654 intel_fb->rotated[i].x = x;
2655 intel_fb->rotated[i].y = y;
2656 } else {
2657 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2658 x * cpp, tile_size);
2659 }
2660
2661 /* how many tiles in total needed in the bo */
2662 max_size = max(max_size, offset + size);
2663 }
2664
2665 if (max_size * tile_size > intel_fb->obj->base.size) {
2666 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2667 max_size * tile_size, intel_fb->obj->base.size);
2668 return -EINVAL;
2669 }
2670
2671 return 0;
2672 }
2673
2674 static int i9xx_format_to_fourcc(int format)
2675 {
2676 switch (format) {
2677 case DISPPLANE_8BPP:
2678 return DRM_FORMAT_C8;
2679 case DISPPLANE_BGRX555:
2680 return DRM_FORMAT_XRGB1555;
2681 case DISPPLANE_BGRX565:
2682 return DRM_FORMAT_RGB565;
2683 default:
2684 case DISPPLANE_BGRX888:
2685 return DRM_FORMAT_XRGB8888;
2686 case DISPPLANE_RGBX888:
2687 return DRM_FORMAT_XBGR8888;
2688 case DISPPLANE_BGRX101010:
2689 return DRM_FORMAT_XRGB2101010;
2690 case DISPPLANE_RGBX101010:
2691 return DRM_FORMAT_XBGR2101010;
2692 }
2693 }
2694
2695 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2696 {
2697 switch (format) {
2698 case PLANE_CTL_FORMAT_RGB_565:
2699 return DRM_FORMAT_RGB565;
2700 default:
2701 case PLANE_CTL_FORMAT_XRGB_8888:
2702 if (rgb_order) {
2703 if (alpha)
2704 return DRM_FORMAT_ABGR8888;
2705 else
2706 return DRM_FORMAT_XBGR8888;
2707 } else {
2708 if (alpha)
2709 return DRM_FORMAT_ARGB8888;
2710 else
2711 return DRM_FORMAT_XRGB8888;
2712 }
2713 case PLANE_CTL_FORMAT_XRGB_2101010:
2714 if (rgb_order)
2715 return DRM_FORMAT_XBGR2101010;
2716 else
2717 return DRM_FORMAT_XRGB2101010;
2718 }
2719 }
2720
2721 static bool
2722 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2723 struct intel_initial_plane_config *plane_config)
2724 {
2725 struct drm_device *dev = crtc->base.dev;
2726 struct drm_i915_private *dev_priv = to_i915(dev);
2727 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2728 struct drm_i915_gem_object *obj = NULL;
2729 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2730 struct drm_framebuffer *fb = &plane_config->fb->base;
2731 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2732 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2733 PAGE_SIZE);
2734
2735 size_aligned -= base_aligned;
2736
2737 if (plane_config->size == 0)
2738 return false;
2739
2740 /* If the FB is too big, just don't use it since fbdev is not very
2741 * important and we should probably use that space with FBC or other
2742 * features. */
2743 if (size_aligned * 2 > ggtt->stolen_usable_size)
2744 return false;
2745
2746 mutex_lock(&dev->struct_mutex);
2747 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2748 base_aligned,
2749 base_aligned,
2750 size_aligned);
2751 mutex_unlock(&dev->struct_mutex);
2752 if (!obj)
2753 return false;
2754
2755 if (plane_config->tiling == I915_TILING_X)
2756 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2757
2758 mode_cmd.pixel_format = fb->format->format;
2759 mode_cmd.width = fb->width;
2760 mode_cmd.height = fb->height;
2761 mode_cmd.pitches[0] = fb->pitches[0];
2762 mode_cmd.modifier[0] = fb->modifier;
2763 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2764
2765 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2766 DRM_DEBUG_KMS("intel fb init failed\n");
2767 goto out_unref_obj;
2768 }
2769
2770
2771 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2772 return true;
2773
2774 out_unref_obj:
2775 i915_gem_object_put(obj);
2776 return false;
2777 }
2778
2779 static void
2780 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2781 struct intel_plane_state *plane_state,
2782 bool visible)
2783 {
2784 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2785
2786 plane_state->base.visible = visible;
2787
2788 /* FIXME pre-g4x don't work like this */
2789 if (visible) {
2790 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2791 crtc_state->active_planes |= BIT(plane->id);
2792 } else {
2793 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2794 crtc_state->active_planes &= ~BIT(plane->id);
2795 }
2796
2797 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2798 crtc_state->base.crtc->name,
2799 crtc_state->active_planes);
2800 }
2801
2802 static void
2803 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2804 struct intel_initial_plane_config *plane_config)
2805 {
2806 struct drm_device *dev = intel_crtc->base.dev;
2807 struct drm_i915_private *dev_priv = to_i915(dev);
2808 struct drm_crtc *c;
2809 struct drm_i915_gem_object *obj;
2810 struct drm_plane *primary = intel_crtc->base.primary;
2811 struct drm_plane_state *plane_state = primary->state;
2812 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2813 struct intel_plane *intel_plane = to_intel_plane(primary);
2814 struct intel_plane_state *intel_state =
2815 to_intel_plane_state(plane_state);
2816 struct drm_framebuffer *fb;
2817
2818 if (!plane_config->fb)
2819 return;
2820
2821 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2822 fb = &plane_config->fb->base;
2823 goto valid_fb;
2824 }
2825
2826 kfree(plane_config->fb);
2827
2828 /*
2829 * Failed to alloc the obj, check to see if we should share
2830 * an fb with another CRTC instead
2831 */
2832 for_each_crtc(dev, c) {
2833 struct intel_plane_state *state;
2834
2835 if (c == &intel_crtc->base)
2836 continue;
2837
2838 if (!to_intel_crtc(c)->active)
2839 continue;
2840
2841 state = to_intel_plane_state(c->primary->state);
2842 if (!state->vma)
2843 continue;
2844
2845 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2846 fb = c->primary->fb;
2847 drm_framebuffer_get(fb);
2848 goto valid_fb;
2849 }
2850 }
2851
2852 /*
2853 * We've failed to reconstruct the BIOS FB. Current display state
2854 * indicates that the primary plane is visible, but has a NULL FB,
2855 * which will lead to problems later if we don't fix it up. The
2856 * simplest solution is to just disable the primary plane now and
2857 * pretend the BIOS never had it enabled.
2858 */
2859 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2860 to_intel_plane_state(plane_state),
2861 false);
2862 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2863 trace_intel_disable_plane(primary, intel_crtc);
2864 intel_plane->disable_plane(intel_plane, intel_crtc);
2865
2866 return;
2867
2868 valid_fb:
2869 mutex_lock(&dev->struct_mutex);
2870 intel_state->vma =
2871 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2872 mutex_unlock(&dev->struct_mutex);
2873 if (IS_ERR(intel_state->vma)) {
2874 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2875 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2876
2877 intel_state->vma = NULL;
2878 drm_framebuffer_put(fb);
2879 return;
2880 }
2881
2882 plane_state->src_x = 0;
2883 plane_state->src_y = 0;
2884 plane_state->src_w = fb->width << 16;
2885 plane_state->src_h = fb->height << 16;
2886
2887 plane_state->crtc_x = 0;
2888 plane_state->crtc_y = 0;
2889 plane_state->crtc_w = fb->width;
2890 plane_state->crtc_h = fb->height;
2891
2892 intel_state->base.src = drm_plane_state_src(plane_state);
2893 intel_state->base.dst = drm_plane_state_dest(plane_state);
2894
2895 obj = intel_fb_obj(fb);
2896 if (i915_gem_object_is_tiled(obj))
2897 dev_priv->preserve_bios_swizzle = true;
2898
2899 drm_framebuffer_get(fb);
2900 primary->fb = primary->state->fb = fb;
2901 primary->crtc = primary->state->crtc = &intel_crtc->base;
2902
2903 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2904 to_intel_plane_state(plane_state),
2905 true);
2906
2907 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2908 &obj->frontbuffer_bits);
2909 }
2910
2911 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2912 unsigned int rotation)
2913 {
2914 int cpp = fb->format->cpp[plane];
2915
2916 switch (fb->modifier) {
2917 case DRM_FORMAT_MOD_LINEAR:
2918 case I915_FORMAT_MOD_X_TILED:
2919 switch (cpp) {
2920 case 8:
2921 return 4096;
2922 case 4:
2923 case 2:
2924 case 1:
2925 return 8192;
2926 default:
2927 MISSING_CASE(cpp);
2928 break;
2929 }
2930 break;
2931 case I915_FORMAT_MOD_Y_TILED_CCS:
2932 case I915_FORMAT_MOD_Yf_TILED_CCS:
2933 /* FIXME AUX plane? */
2934 case I915_FORMAT_MOD_Y_TILED:
2935 case I915_FORMAT_MOD_Yf_TILED:
2936 switch (cpp) {
2937 case 8:
2938 return 2048;
2939 case 4:
2940 return 4096;
2941 case 2:
2942 case 1:
2943 return 8192;
2944 default:
2945 MISSING_CASE(cpp);
2946 break;
2947 }
2948 break;
2949 default:
2950 MISSING_CASE(fb->modifier);
2951 }
2952
2953 return 2048;
2954 }
2955
2956 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2957 int main_x, int main_y, u32 main_offset)
2958 {
2959 const struct drm_framebuffer *fb = plane_state->base.fb;
2960 int hsub = fb->format->hsub;
2961 int vsub = fb->format->vsub;
2962 int aux_x = plane_state->aux.x;
2963 int aux_y = plane_state->aux.y;
2964 u32 aux_offset = plane_state->aux.offset;
2965 u32 alignment = intel_surf_alignment(fb, 1);
2966
2967 while (aux_offset >= main_offset && aux_y <= main_y) {
2968 int x, y;
2969
2970 if (aux_x == main_x && aux_y == main_y)
2971 break;
2972
2973 if (aux_offset == 0)
2974 break;
2975
2976 x = aux_x / hsub;
2977 y = aux_y / vsub;
2978 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2979 aux_offset, aux_offset - alignment);
2980 aux_x = x * hsub + aux_x % hsub;
2981 aux_y = y * vsub + aux_y % vsub;
2982 }
2983
2984 if (aux_x != main_x || aux_y != main_y)
2985 return false;
2986
2987 plane_state->aux.offset = aux_offset;
2988 plane_state->aux.x = aux_x;
2989 plane_state->aux.y = aux_y;
2990
2991 return true;
2992 }
2993
2994 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2995 {
2996 const struct drm_framebuffer *fb = plane_state->base.fb;
2997 unsigned int rotation = plane_state->base.rotation;
2998 int x = plane_state->base.src.x1 >> 16;
2999 int y = plane_state->base.src.y1 >> 16;
3000 int w = drm_rect_width(&plane_state->base.src) >> 16;
3001 int h = drm_rect_height(&plane_state->base.src) >> 16;
3002 int max_width = skl_max_plane_width(fb, 0, rotation);
3003 int max_height = 4096;
3004 u32 alignment, offset, aux_offset = plane_state->aux.offset;
3005
3006 if (w > max_width || h > max_height) {
3007 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3008 w, h, max_width, max_height);
3009 return -EINVAL;
3010 }
3011
3012 intel_add_fb_offsets(&x, &y, plane_state, 0);
3013 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3014 alignment = intel_surf_alignment(fb, 0);
3015
3016 /*
3017 * AUX surface offset is specified as the distance from the
3018 * main surface offset, and it must be non-negative. Make
3019 * sure that is what we will get.
3020 */
3021 if (offset > aux_offset)
3022 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3023 offset, aux_offset & ~(alignment - 1));
3024
3025 /*
3026 * When using an X-tiled surface, the plane blows up
3027 * if the x offset + width exceed the stride.
3028 *
3029 * TODO: linear and Y-tiled seem fine, Yf untested,
3030 */
3031 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3032 int cpp = fb->format->cpp[0];
3033
3034 while ((x + w) * cpp > fb->pitches[0]) {
3035 if (offset == 0) {
3036 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3037 return -EINVAL;
3038 }
3039
3040 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3041 offset, offset - alignment);
3042 }
3043 }
3044
3045 /*
3046 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3047 * they match with the main surface x/y offsets.
3048 */
3049 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3050 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3051 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3052 if (offset == 0)
3053 break;
3054
3055 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3056 offset, offset - alignment);
3057 }
3058
3059 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3060 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3061 return -EINVAL;
3062 }
3063 }
3064
3065 plane_state->main.offset = offset;
3066 plane_state->main.x = x;
3067 plane_state->main.y = y;
3068
3069 return 0;
3070 }
3071
3072 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3073 {
3074 const struct drm_framebuffer *fb = plane_state->base.fb;
3075 unsigned int rotation = plane_state->base.rotation;
3076 int max_width = skl_max_plane_width(fb, 1, rotation);
3077 int max_height = 4096;
3078 int x = plane_state->base.src.x1 >> 17;
3079 int y = plane_state->base.src.y1 >> 17;
3080 int w = drm_rect_width(&plane_state->base.src) >> 17;
3081 int h = drm_rect_height(&plane_state->base.src) >> 17;
3082 u32 offset;
3083
3084 intel_add_fb_offsets(&x, &y, plane_state, 1);
3085 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3086
3087 /* FIXME not quite sure how/if these apply to the chroma plane */
3088 if (w > max_width || h > max_height) {
3089 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3090 w, h, max_width, max_height);
3091 return -EINVAL;
3092 }
3093
3094 plane_state->aux.offset = offset;
3095 plane_state->aux.x = x;
3096 plane_state->aux.y = y;
3097
3098 return 0;
3099 }
3100
3101 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3102 {
3103 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3104 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3105 const struct drm_framebuffer *fb = plane_state->base.fb;
3106 int src_x = plane_state->base.src.x1 >> 16;
3107 int src_y = plane_state->base.src.y1 >> 16;
3108 int hsub = fb->format->hsub;
3109 int vsub = fb->format->vsub;
3110 int x = src_x / hsub;
3111 int y = src_y / vsub;
3112 u32 offset;
3113
3114 switch (plane->id) {
3115 case PLANE_PRIMARY:
3116 case PLANE_SPRITE0:
3117 break;
3118 default:
3119 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3120 return -EINVAL;
3121 }
3122
3123 if (crtc->pipe == PIPE_C) {
3124 DRM_DEBUG_KMS("No RC support on pipe C\n");
3125 return -EINVAL;
3126 }
3127
3128 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3129 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3130 plane_state->base.rotation);
3131 return -EINVAL;
3132 }
3133
3134 intel_add_fb_offsets(&x, &y, plane_state, 1);
3135 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3136
3137 plane_state->aux.offset = offset;
3138 plane_state->aux.x = x * hsub + src_x % hsub;
3139 plane_state->aux.y = y * vsub + src_y % vsub;
3140
3141 return 0;
3142 }
3143
3144 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3145 {
3146 const struct drm_framebuffer *fb = plane_state->base.fb;
3147 unsigned int rotation = plane_state->base.rotation;
3148 int ret;
3149
3150 if (!plane_state->base.visible)
3151 return 0;
3152
3153 /* Rotate src coordinates to match rotated GTT view */
3154 if (drm_rotation_90_or_270(rotation))
3155 drm_rect_rotate(&plane_state->base.src,
3156 fb->width << 16, fb->height << 16,
3157 DRM_MODE_ROTATE_270);
3158
3159 /*
3160 * Handle the AUX surface first since
3161 * the main surface setup depends on it.
3162 */
3163 if (fb->format->format == DRM_FORMAT_NV12) {
3164 ret = skl_check_nv12_aux_surface(plane_state);
3165 if (ret)
3166 return ret;
3167 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3168 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3169 ret = skl_check_ccs_aux_surface(plane_state);
3170 if (ret)
3171 return ret;
3172 } else {
3173 plane_state->aux.offset = ~0xfff;
3174 plane_state->aux.x = 0;
3175 plane_state->aux.y = 0;
3176 }
3177
3178 ret = skl_check_main_surface(plane_state);
3179 if (ret)
3180 return ret;
3181
3182 return 0;
3183 }
3184
3185 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3186 const struct intel_plane_state *plane_state)
3187 {
3188 struct drm_i915_private *dev_priv =
3189 to_i915(plane_state->base.plane->dev);
3190 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3191 const struct drm_framebuffer *fb = plane_state->base.fb;
3192 unsigned int rotation = plane_state->base.rotation;
3193 u32 dspcntr;
3194
3195 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3196
3197 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3198 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3199 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3200
3201 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3202 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3203
3204 if (INTEL_GEN(dev_priv) < 4)
3205 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3206
3207 switch (fb->format->format) {
3208 case DRM_FORMAT_C8:
3209 dspcntr |= DISPPLANE_8BPP;
3210 break;
3211 case DRM_FORMAT_XRGB1555:
3212 dspcntr |= DISPPLANE_BGRX555;
3213 break;
3214 case DRM_FORMAT_RGB565:
3215 dspcntr |= DISPPLANE_BGRX565;
3216 break;
3217 case DRM_FORMAT_XRGB8888:
3218 dspcntr |= DISPPLANE_BGRX888;
3219 break;
3220 case DRM_FORMAT_XBGR8888:
3221 dspcntr |= DISPPLANE_RGBX888;
3222 break;
3223 case DRM_FORMAT_XRGB2101010:
3224 dspcntr |= DISPPLANE_BGRX101010;
3225 break;
3226 case DRM_FORMAT_XBGR2101010:
3227 dspcntr |= DISPPLANE_RGBX101010;
3228 break;
3229 default:
3230 MISSING_CASE(fb->format->format);
3231 return 0;
3232 }
3233
3234 if (INTEL_GEN(dev_priv) >= 4 &&
3235 fb->modifier == I915_FORMAT_MOD_X_TILED)
3236 dspcntr |= DISPPLANE_TILED;
3237
3238 if (rotation & DRM_MODE_ROTATE_180)
3239 dspcntr |= DISPPLANE_ROTATE_180;
3240
3241 if (rotation & DRM_MODE_REFLECT_X)
3242 dspcntr |= DISPPLANE_MIRROR;
3243
3244 return dspcntr;
3245 }
3246
3247 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3248 {
3249 struct drm_i915_private *dev_priv =
3250 to_i915(plane_state->base.plane->dev);
3251 int src_x = plane_state->base.src.x1 >> 16;
3252 int src_y = plane_state->base.src.y1 >> 16;
3253 u32 offset;
3254
3255 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3256
3257 if (INTEL_GEN(dev_priv) >= 4)
3258 offset = intel_compute_tile_offset(&src_x, &src_y,
3259 plane_state, 0);
3260 else
3261 offset = 0;
3262
3263 /* HSW/BDW do this automagically in hardware */
3264 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3265 unsigned int rotation = plane_state->base.rotation;
3266 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3267 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3268
3269 if (rotation & DRM_MODE_ROTATE_180) {
3270 src_x += src_w - 1;
3271 src_y += src_h - 1;
3272 } else if (rotation & DRM_MODE_REFLECT_X) {
3273 src_x += src_w - 1;
3274 }
3275 }
3276
3277 plane_state->main.offset = offset;
3278 plane_state->main.x = src_x;
3279 plane_state->main.y = src_y;
3280
3281 return 0;
3282 }
3283
3284 static void i9xx_update_primary_plane(struct intel_plane *primary,
3285 const struct intel_crtc_state *crtc_state,
3286 const struct intel_plane_state *plane_state)
3287 {
3288 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3289 const struct drm_framebuffer *fb = plane_state->base.fb;
3290 enum plane plane = primary->plane;
3291 u32 linear_offset;
3292 u32 dspcntr = plane_state->ctl;
3293 i915_reg_t reg = DSPCNTR(plane);
3294 int x = plane_state->main.x;
3295 int y = plane_state->main.y;
3296 unsigned long irqflags;
3297 u32 dspaddr_offset;
3298
3299 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3300
3301 if (INTEL_GEN(dev_priv) >= 4)
3302 dspaddr_offset = plane_state->main.offset;
3303 else
3304 dspaddr_offset = linear_offset;
3305
3306 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3307
3308 if (INTEL_GEN(dev_priv) < 4) {
3309 /* pipesrc and dspsize control the size that is scaled from,
3310 * which should always be the user's requested size.
3311 */
3312 I915_WRITE_FW(DSPSIZE(plane),
3313 ((crtc_state->pipe_src_h - 1) << 16) |
3314 (crtc_state->pipe_src_w - 1));
3315 I915_WRITE_FW(DSPPOS(plane), 0);
3316 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3317 I915_WRITE_FW(PRIMSIZE(plane),
3318 ((crtc_state->pipe_src_h - 1) << 16) |
3319 (crtc_state->pipe_src_w - 1));
3320 I915_WRITE_FW(PRIMPOS(plane), 0);
3321 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3322 }
3323
3324 I915_WRITE_FW(reg, dspcntr);
3325
3326 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3327 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3328 I915_WRITE_FW(DSPSURF(plane),
3329 intel_plane_ggtt_offset(plane_state) +
3330 dspaddr_offset);
3331 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3332 } else if (INTEL_GEN(dev_priv) >= 4) {
3333 I915_WRITE_FW(DSPSURF(plane),
3334 intel_plane_ggtt_offset(plane_state) +
3335 dspaddr_offset);
3336 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3337 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3338 } else {
3339 I915_WRITE_FW(DSPADDR(plane),
3340 intel_plane_ggtt_offset(plane_state) +
3341 dspaddr_offset);
3342 }
3343 POSTING_READ_FW(reg);
3344
3345 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3346 }
3347
3348 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3349 struct intel_crtc *crtc)
3350 {
3351 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3352 enum plane plane = primary->plane;
3353 unsigned long irqflags;
3354
3355 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3356
3357 I915_WRITE_FW(DSPCNTR(plane), 0);
3358 if (INTEL_INFO(dev_priv)->gen >= 4)
3359 I915_WRITE_FW(DSPSURF(plane), 0);
3360 else
3361 I915_WRITE_FW(DSPADDR(plane), 0);
3362 POSTING_READ_FW(DSPCNTR(plane));
3363
3364 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3365 }
3366
3367 static u32
3368 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3369 {
3370 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3371 return 64;
3372 else
3373 return intel_tile_width_bytes(fb, plane);
3374 }
3375
3376 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3377 {
3378 struct drm_device *dev = intel_crtc->base.dev;
3379 struct drm_i915_private *dev_priv = to_i915(dev);
3380
3381 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3382 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3383 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3384 }
3385
3386 /*
3387 * This function detaches (aka. unbinds) unused scalers in hardware
3388 */
3389 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3390 {
3391 struct intel_crtc_scaler_state *scaler_state;
3392 int i;
3393
3394 scaler_state = &intel_crtc->config->scaler_state;
3395
3396 /* loop through and disable scalers that aren't in use */
3397 for (i = 0; i < intel_crtc->num_scalers; i++) {
3398 if (!scaler_state->scalers[i].in_use)
3399 skl_detach_scaler(intel_crtc, i);
3400 }
3401 }
3402
3403 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3404 unsigned int rotation)
3405 {
3406 u32 stride;
3407
3408 if (plane >= fb->format->num_planes)
3409 return 0;
3410
3411 stride = intel_fb_pitch(fb, plane, rotation);
3412
3413 /*
3414 * The stride is either expressed as a multiple of 64 bytes chunks for
3415 * linear buffers or in number of tiles for tiled buffers.
3416 */
3417 if (drm_rotation_90_or_270(rotation))
3418 stride /= intel_tile_height(fb, plane);
3419 else
3420 stride /= intel_fb_stride_alignment(fb, plane);
3421
3422 return stride;
3423 }
3424
3425 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3426 {
3427 switch (pixel_format) {
3428 case DRM_FORMAT_C8:
3429 return PLANE_CTL_FORMAT_INDEXED;
3430 case DRM_FORMAT_RGB565:
3431 return PLANE_CTL_FORMAT_RGB_565;
3432 case DRM_FORMAT_XBGR8888:
3433 case DRM_FORMAT_ABGR8888:
3434 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3435 case DRM_FORMAT_XRGB8888:
3436 case DRM_FORMAT_ARGB8888:
3437 return PLANE_CTL_FORMAT_XRGB_8888;
3438 case DRM_FORMAT_XRGB2101010:
3439 return PLANE_CTL_FORMAT_XRGB_2101010;
3440 case DRM_FORMAT_XBGR2101010:
3441 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3442 case DRM_FORMAT_YUYV:
3443 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3444 case DRM_FORMAT_YVYU:
3445 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3446 case DRM_FORMAT_UYVY:
3447 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3448 case DRM_FORMAT_VYUY:
3449 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3450 default:
3451 MISSING_CASE(pixel_format);
3452 }
3453
3454 return 0;
3455 }
3456
3457 /*
3458 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3459 * to be already pre-multiplied. We need to add a knob (or a different
3460 * DRM_FORMAT) for user-space to configure that.
3461 */
3462 static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3463 {
3464 switch (pixel_format) {
3465 case DRM_FORMAT_ABGR8888:
3466 case DRM_FORMAT_ARGB8888:
3467 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3468 default:
3469 return PLANE_CTL_ALPHA_DISABLE;
3470 }
3471 }
3472
3473 static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
3474 {
3475 switch (pixel_format) {
3476 case DRM_FORMAT_ABGR8888:
3477 case DRM_FORMAT_ARGB8888:
3478 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3479 default:
3480 return PLANE_COLOR_ALPHA_DISABLE;
3481 }
3482 }
3483
3484 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3485 {
3486 switch (fb_modifier) {
3487 case DRM_FORMAT_MOD_LINEAR:
3488 break;
3489 case I915_FORMAT_MOD_X_TILED:
3490 return PLANE_CTL_TILED_X;
3491 case I915_FORMAT_MOD_Y_TILED:
3492 return PLANE_CTL_TILED_Y;
3493 case I915_FORMAT_MOD_Y_TILED_CCS:
3494 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3495 case I915_FORMAT_MOD_Yf_TILED:
3496 return PLANE_CTL_TILED_YF;
3497 case I915_FORMAT_MOD_Yf_TILED_CCS:
3498 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3499 default:
3500 MISSING_CASE(fb_modifier);
3501 }
3502
3503 return 0;
3504 }
3505
3506 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3507 {
3508 switch (rotation) {
3509 case DRM_MODE_ROTATE_0:
3510 break;
3511 /*
3512 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3513 * while i915 HW rotation is clockwise, thats why this swapping.
3514 */
3515 case DRM_MODE_ROTATE_90:
3516 return PLANE_CTL_ROTATE_270;
3517 case DRM_MODE_ROTATE_180:
3518 return PLANE_CTL_ROTATE_180;
3519 case DRM_MODE_ROTATE_270:
3520 return PLANE_CTL_ROTATE_90;
3521 default:
3522 MISSING_CASE(rotation);
3523 }
3524
3525 return 0;
3526 }
3527
3528 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3529 const struct intel_plane_state *plane_state)
3530 {
3531 struct drm_i915_private *dev_priv =
3532 to_i915(plane_state->base.plane->dev);
3533 const struct drm_framebuffer *fb = plane_state->base.fb;
3534 unsigned int rotation = plane_state->base.rotation;
3535 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3536 u32 plane_ctl;
3537
3538 plane_ctl = PLANE_CTL_ENABLE;
3539
3540 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3541 plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
3542 plane_ctl |=
3543 PLANE_CTL_PIPE_GAMMA_ENABLE |
3544 PLANE_CTL_PIPE_CSC_ENABLE |
3545 PLANE_CTL_PLANE_GAMMA_DISABLE;
3546 }
3547
3548 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3549 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3550 plane_ctl |= skl_plane_ctl_rotation(rotation);
3551
3552 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3553 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3554 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3555 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3556
3557 return plane_ctl;
3558 }
3559
3560 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3561 const struct intel_plane_state *plane_state)
3562 {
3563 const struct drm_framebuffer *fb = plane_state->base.fb;
3564 u32 plane_color_ctl = 0;
3565
3566 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3567 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3568 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3569 plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3570
3571 return plane_color_ctl;
3572 }
3573
3574 static int
3575 __intel_display_resume(struct drm_device *dev,
3576 struct drm_atomic_state *state,
3577 struct drm_modeset_acquire_ctx *ctx)
3578 {
3579 struct drm_crtc_state *crtc_state;
3580 struct drm_crtc *crtc;
3581 int i, ret;
3582
3583 intel_modeset_setup_hw_state(dev, ctx);
3584 i915_redisable_vga(to_i915(dev));
3585
3586 if (!state)
3587 return 0;
3588
3589 /*
3590 * We've duplicated the state, pointers to the old state are invalid.
3591 *
3592 * Don't attempt to use the old state until we commit the duplicated state.
3593 */
3594 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3595 /*
3596 * Force recalculation even if we restore
3597 * current state. With fast modeset this may not result
3598 * in a modeset when the state is compatible.
3599 */
3600 crtc_state->mode_changed = true;
3601 }
3602
3603 /* ignore any reset values/BIOS leftovers in the WM registers */
3604 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3605 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3606
3607 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3608
3609 WARN_ON(ret == -EDEADLK);
3610 return ret;
3611 }
3612
3613 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3614 {
3615 return intel_has_gpu_reset(dev_priv) &&
3616 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3617 }
3618
3619 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3620 {
3621 struct drm_device *dev = &dev_priv->drm;
3622 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3623 struct drm_atomic_state *state;
3624 int ret;
3625
3626
3627 /* reset doesn't touch the display */
3628 if (!i915_modparams.force_reset_modeset_test &&
3629 !gpu_reset_clobbers_display(dev_priv))
3630 return;
3631
3632 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3633 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3634 wake_up_all(&dev_priv->gpu_error.wait_queue);
3635
3636 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3637 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3638 i915_gem_set_wedged(dev_priv);
3639 }
3640
3641 /*
3642 * Need mode_config.mutex so that we don't
3643 * trample ongoing ->detect() and whatnot.
3644 */
3645 mutex_lock(&dev->mode_config.mutex);
3646 drm_modeset_acquire_init(ctx, 0);
3647 while (1) {
3648 ret = drm_modeset_lock_all_ctx(dev, ctx);
3649 if (ret != -EDEADLK)
3650 break;
3651
3652 drm_modeset_backoff(ctx);
3653 }
3654 /*
3655 * Disabling the crtcs gracefully seems nicer. Also the
3656 * g33 docs say we should at least disable all the planes.
3657 */
3658 state = drm_atomic_helper_duplicate_state(dev, ctx);
3659 if (IS_ERR(state)) {
3660 ret = PTR_ERR(state);
3661 DRM_ERROR("Duplicating state failed with %i\n", ret);
3662 return;
3663 }
3664
3665 ret = drm_atomic_helper_disable_all(dev, ctx);
3666 if (ret) {
3667 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3668 drm_atomic_state_put(state);
3669 return;
3670 }
3671
3672 dev_priv->modeset_restore_state = state;
3673 state->acquire_ctx = ctx;
3674 }
3675
3676 void intel_finish_reset(struct drm_i915_private *dev_priv)
3677 {
3678 struct drm_device *dev = &dev_priv->drm;
3679 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3680 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3681 int ret;
3682
3683 /* reset doesn't touch the display */
3684 if (!i915_modparams.force_reset_modeset_test &&
3685 !gpu_reset_clobbers_display(dev_priv))
3686 return;
3687
3688 if (!state)
3689 goto unlock;
3690
3691 dev_priv->modeset_restore_state = NULL;
3692
3693 /* reset doesn't touch the display */
3694 if (!gpu_reset_clobbers_display(dev_priv)) {
3695 /* for testing only restore the display */
3696 ret = __intel_display_resume(dev, state, ctx);
3697 if (ret)
3698 DRM_ERROR("Restoring old state failed with %i\n", ret);
3699 } else {
3700 /*
3701 * The display has been reset as well,
3702 * so need a full re-initialization.
3703 */
3704 intel_runtime_pm_disable_interrupts(dev_priv);
3705 intel_runtime_pm_enable_interrupts(dev_priv);
3706
3707 intel_pps_unlock_regs_wa(dev_priv);
3708 intel_modeset_init_hw(dev);
3709 intel_init_clock_gating(dev_priv);
3710
3711 spin_lock_irq(&dev_priv->irq_lock);
3712 if (dev_priv->display.hpd_irq_setup)
3713 dev_priv->display.hpd_irq_setup(dev_priv);
3714 spin_unlock_irq(&dev_priv->irq_lock);
3715
3716 ret = __intel_display_resume(dev, state, ctx);
3717 if (ret)
3718 DRM_ERROR("Restoring old state failed with %i\n", ret);
3719
3720 intel_hpd_init(dev_priv);
3721 }
3722
3723 drm_atomic_state_put(state);
3724 unlock:
3725 drm_modeset_drop_locks(ctx);
3726 drm_modeset_acquire_fini(ctx);
3727 mutex_unlock(&dev->mode_config.mutex);
3728
3729 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3730 }
3731
3732 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3733 const struct intel_crtc_state *new_crtc_state)
3734 {
3735 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3736 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3737
3738 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3739 crtc->base.mode = new_crtc_state->base.mode;
3740
3741 /*
3742 * Update pipe size and adjust fitter if needed: the reason for this is
3743 * that in compute_mode_changes we check the native mode (not the pfit
3744 * mode) to see if we can flip rather than do a full mode set. In the
3745 * fastboot case, we'll flip, but if we don't update the pipesrc and
3746 * pfit state, we'll end up with a big fb scanned out into the wrong
3747 * sized surface.
3748 */
3749
3750 I915_WRITE(PIPESRC(crtc->pipe),
3751 ((new_crtc_state->pipe_src_w - 1) << 16) |
3752 (new_crtc_state->pipe_src_h - 1));
3753
3754 /* on skylake this is done by detaching scalers */
3755 if (INTEL_GEN(dev_priv) >= 9) {
3756 skl_detach_scalers(crtc);
3757
3758 if (new_crtc_state->pch_pfit.enabled)
3759 skylake_pfit_enable(crtc);
3760 } else if (HAS_PCH_SPLIT(dev_priv)) {
3761 if (new_crtc_state->pch_pfit.enabled)
3762 ironlake_pfit_enable(crtc);
3763 else if (old_crtc_state->pch_pfit.enabled)
3764 ironlake_pfit_disable(crtc, true);
3765 }
3766 }
3767
3768 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3769 {
3770 struct drm_device *dev = crtc->base.dev;
3771 struct drm_i915_private *dev_priv = to_i915(dev);
3772 int pipe = crtc->pipe;
3773 i915_reg_t reg;
3774 u32 temp;
3775
3776 /* enable normal train */
3777 reg = FDI_TX_CTL(pipe);
3778 temp = I915_READ(reg);
3779 if (IS_IVYBRIDGE(dev_priv)) {
3780 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3781 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3782 } else {
3783 temp &= ~FDI_LINK_TRAIN_NONE;
3784 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3785 }
3786 I915_WRITE(reg, temp);
3787
3788 reg = FDI_RX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 if (HAS_PCH_CPT(dev_priv)) {
3791 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3792 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3793 } else {
3794 temp &= ~FDI_LINK_TRAIN_NONE;
3795 temp |= FDI_LINK_TRAIN_NONE;
3796 }
3797 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3798
3799 /* wait one idle pattern time */
3800 POSTING_READ(reg);
3801 udelay(1000);
3802
3803 /* IVB wants error correction enabled */
3804 if (IS_IVYBRIDGE(dev_priv))
3805 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3806 FDI_FE_ERRC_ENABLE);
3807 }
3808
3809 /* The FDI link training functions for ILK/Ibexpeak. */
3810 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3811 const struct intel_crtc_state *crtc_state)
3812 {
3813 struct drm_device *dev = crtc->base.dev;
3814 struct drm_i915_private *dev_priv = to_i915(dev);
3815 int pipe = crtc->pipe;
3816 i915_reg_t reg;
3817 u32 temp, tries;
3818
3819 /* FDI needs bits from pipe first */
3820 assert_pipe_enabled(dev_priv, pipe);
3821
3822 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3823 for train result */
3824 reg = FDI_RX_IMR(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~FDI_RX_SYMBOL_LOCK;
3827 temp &= ~FDI_RX_BIT_LOCK;
3828 I915_WRITE(reg, temp);
3829 I915_READ(reg);
3830 udelay(150);
3831
3832 /* enable CPU FDI TX and PCH FDI RX */
3833 reg = FDI_TX_CTL(pipe);
3834 temp = I915_READ(reg);
3835 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3836 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3837 temp &= ~FDI_LINK_TRAIN_NONE;
3838 temp |= FDI_LINK_TRAIN_PATTERN_1;
3839 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3840
3841 reg = FDI_RX_CTL(pipe);
3842 temp = I915_READ(reg);
3843 temp &= ~FDI_LINK_TRAIN_NONE;
3844 temp |= FDI_LINK_TRAIN_PATTERN_1;
3845 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3846
3847 POSTING_READ(reg);
3848 udelay(150);
3849
3850 /* Ironlake workaround, enable clock pointer after FDI enable*/
3851 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3852 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3853 FDI_RX_PHASE_SYNC_POINTER_EN);
3854
3855 reg = FDI_RX_IIR(pipe);
3856 for (tries = 0; tries < 5; tries++) {
3857 temp = I915_READ(reg);
3858 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3859
3860 if ((temp & FDI_RX_BIT_LOCK)) {
3861 DRM_DEBUG_KMS("FDI train 1 done.\n");
3862 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3863 break;
3864 }
3865 }
3866 if (tries == 5)
3867 DRM_ERROR("FDI train 1 fail!\n");
3868
3869 /* Train 2 */
3870 reg = FDI_TX_CTL(pipe);
3871 temp = I915_READ(reg);
3872 temp &= ~FDI_LINK_TRAIN_NONE;
3873 temp |= FDI_LINK_TRAIN_PATTERN_2;
3874 I915_WRITE(reg, temp);
3875
3876 reg = FDI_RX_CTL(pipe);
3877 temp = I915_READ(reg);
3878 temp &= ~FDI_LINK_TRAIN_NONE;
3879 temp |= FDI_LINK_TRAIN_PATTERN_2;
3880 I915_WRITE(reg, temp);
3881
3882 POSTING_READ(reg);
3883 udelay(150);
3884
3885 reg = FDI_RX_IIR(pipe);
3886 for (tries = 0; tries < 5; tries++) {
3887 temp = I915_READ(reg);
3888 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3889
3890 if (temp & FDI_RX_SYMBOL_LOCK) {
3891 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3892 DRM_DEBUG_KMS("FDI train 2 done.\n");
3893 break;
3894 }
3895 }
3896 if (tries == 5)
3897 DRM_ERROR("FDI train 2 fail!\n");
3898
3899 DRM_DEBUG_KMS("FDI train done\n");
3900
3901 }
3902
3903 static const int snb_b_fdi_train_param[] = {
3904 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3905 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3906 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3907 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3908 };
3909
3910 /* The FDI link training functions for SNB/Cougarpoint. */
3911 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3912 const struct intel_crtc_state *crtc_state)
3913 {
3914 struct drm_device *dev = crtc->base.dev;
3915 struct drm_i915_private *dev_priv = to_i915(dev);
3916 int pipe = crtc->pipe;
3917 i915_reg_t reg;
3918 u32 temp, i, retry;
3919
3920 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3921 for train result */
3922 reg = FDI_RX_IMR(pipe);
3923 temp = I915_READ(reg);
3924 temp &= ~FDI_RX_SYMBOL_LOCK;
3925 temp &= ~FDI_RX_BIT_LOCK;
3926 I915_WRITE(reg, temp);
3927
3928 POSTING_READ(reg);
3929 udelay(150);
3930
3931 /* enable CPU FDI TX and PCH FDI RX */
3932 reg = FDI_TX_CTL(pipe);
3933 temp = I915_READ(reg);
3934 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3935 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3936 temp &= ~FDI_LINK_TRAIN_NONE;
3937 temp |= FDI_LINK_TRAIN_PATTERN_1;
3938 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3939 /* SNB-B */
3940 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3941 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3942
3943 I915_WRITE(FDI_RX_MISC(pipe),
3944 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3945
3946 reg = FDI_RX_CTL(pipe);
3947 temp = I915_READ(reg);
3948 if (HAS_PCH_CPT(dev_priv)) {
3949 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3950 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3951 } else {
3952 temp &= ~FDI_LINK_TRAIN_NONE;
3953 temp |= FDI_LINK_TRAIN_PATTERN_1;
3954 }
3955 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3956
3957 POSTING_READ(reg);
3958 udelay(150);
3959
3960 for (i = 0; i < 4; i++) {
3961 reg = FDI_TX_CTL(pipe);
3962 temp = I915_READ(reg);
3963 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3964 temp |= snb_b_fdi_train_param[i];
3965 I915_WRITE(reg, temp);
3966
3967 POSTING_READ(reg);
3968 udelay(500);
3969
3970 for (retry = 0; retry < 5; retry++) {
3971 reg = FDI_RX_IIR(pipe);
3972 temp = I915_READ(reg);
3973 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3974 if (temp & FDI_RX_BIT_LOCK) {
3975 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3976 DRM_DEBUG_KMS("FDI train 1 done.\n");
3977 break;
3978 }
3979 udelay(50);
3980 }
3981 if (retry < 5)
3982 break;
3983 }
3984 if (i == 4)
3985 DRM_ERROR("FDI train 1 fail!\n");
3986
3987 /* Train 2 */
3988 reg = FDI_TX_CTL(pipe);
3989 temp = I915_READ(reg);
3990 temp &= ~FDI_LINK_TRAIN_NONE;
3991 temp |= FDI_LINK_TRAIN_PATTERN_2;
3992 if (IS_GEN6(dev_priv)) {
3993 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3994 /* SNB-B */
3995 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3996 }
3997 I915_WRITE(reg, temp);
3998
3999 reg = FDI_RX_CTL(pipe);
4000 temp = I915_READ(reg);
4001 if (HAS_PCH_CPT(dev_priv)) {
4002 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4003 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4004 } else {
4005 temp &= ~FDI_LINK_TRAIN_NONE;
4006 temp |= FDI_LINK_TRAIN_PATTERN_2;
4007 }
4008 I915_WRITE(reg, temp);
4009
4010 POSTING_READ(reg);
4011 udelay(150);
4012
4013 for (i = 0; i < 4; i++) {
4014 reg = FDI_TX_CTL(pipe);
4015 temp = I915_READ(reg);
4016 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4017 temp |= snb_b_fdi_train_param[i];
4018 I915_WRITE(reg, temp);
4019
4020 POSTING_READ(reg);
4021 udelay(500);
4022
4023 for (retry = 0; retry < 5; retry++) {
4024 reg = FDI_RX_IIR(pipe);
4025 temp = I915_READ(reg);
4026 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4027 if (temp & FDI_RX_SYMBOL_LOCK) {
4028 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4029 DRM_DEBUG_KMS("FDI train 2 done.\n");
4030 break;
4031 }
4032 udelay(50);
4033 }
4034 if (retry < 5)
4035 break;
4036 }
4037 if (i == 4)
4038 DRM_ERROR("FDI train 2 fail!\n");
4039
4040 DRM_DEBUG_KMS("FDI train done.\n");
4041 }
4042
4043 /* Manual link training for Ivy Bridge A0 parts */
4044 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4045 const struct intel_crtc_state *crtc_state)
4046 {
4047 struct drm_device *dev = crtc->base.dev;
4048 struct drm_i915_private *dev_priv = to_i915(dev);
4049 int pipe = crtc->pipe;
4050 i915_reg_t reg;
4051 u32 temp, i, j;
4052
4053 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4054 for train result */
4055 reg = FDI_RX_IMR(pipe);
4056 temp = I915_READ(reg);
4057 temp &= ~FDI_RX_SYMBOL_LOCK;
4058 temp &= ~FDI_RX_BIT_LOCK;
4059 I915_WRITE(reg, temp);
4060
4061 POSTING_READ(reg);
4062 udelay(150);
4063
4064 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4065 I915_READ(FDI_RX_IIR(pipe)));
4066
4067 /* Try each vswing and preemphasis setting twice before moving on */
4068 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4069 /* disable first in case we need to retry */
4070 reg = FDI_TX_CTL(pipe);
4071 temp = I915_READ(reg);
4072 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4073 temp &= ~FDI_TX_ENABLE;
4074 I915_WRITE(reg, temp);
4075
4076 reg = FDI_RX_CTL(pipe);
4077 temp = I915_READ(reg);
4078 temp &= ~FDI_LINK_TRAIN_AUTO;
4079 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4080 temp &= ~FDI_RX_ENABLE;
4081 I915_WRITE(reg, temp);
4082
4083 /* enable CPU FDI TX and PCH FDI RX */
4084 reg = FDI_TX_CTL(pipe);
4085 temp = I915_READ(reg);
4086 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4087 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4088 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4089 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4090 temp |= snb_b_fdi_train_param[j/2];
4091 temp |= FDI_COMPOSITE_SYNC;
4092 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4093
4094 I915_WRITE(FDI_RX_MISC(pipe),
4095 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4096
4097 reg = FDI_RX_CTL(pipe);
4098 temp = I915_READ(reg);
4099 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4100 temp |= FDI_COMPOSITE_SYNC;
4101 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4102
4103 POSTING_READ(reg);
4104 udelay(1); /* should be 0.5us */
4105
4106 for (i = 0; i < 4; i++) {
4107 reg = FDI_RX_IIR(pipe);
4108 temp = I915_READ(reg);
4109 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4110
4111 if (temp & FDI_RX_BIT_LOCK ||
4112 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4113 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4114 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4115 i);
4116 break;
4117 }
4118 udelay(1); /* should be 0.5us */
4119 }
4120 if (i == 4) {
4121 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4122 continue;
4123 }
4124
4125 /* Train 2 */
4126 reg = FDI_TX_CTL(pipe);
4127 temp = I915_READ(reg);
4128 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4129 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4130 I915_WRITE(reg, temp);
4131
4132 reg = FDI_RX_CTL(pipe);
4133 temp = I915_READ(reg);
4134 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4135 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4136 I915_WRITE(reg, temp);
4137
4138 POSTING_READ(reg);
4139 udelay(2); /* should be 1.5us */
4140
4141 for (i = 0; i < 4; i++) {
4142 reg = FDI_RX_IIR(pipe);
4143 temp = I915_READ(reg);
4144 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4145
4146 if (temp & FDI_RX_SYMBOL_LOCK ||
4147 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4148 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4149 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4150 i);
4151 goto train_done;
4152 }
4153 udelay(2); /* should be 1.5us */
4154 }
4155 if (i == 4)
4156 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4157 }
4158
4159 train_done:
4160 DRM_DEBUG_KMS("FDI train done.\n");
4161 }
4162
4163 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4164 {
4165 struct drm_device *dev = intel_crtc->base.dev;
4166 struct drm_i915_private *dev_priv = to_i915(dev);
4167 int pipe = intel_crtc->pipe;
4168 i915_reg_t reg;
4169 u32 temp;
4170
4171 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4172 reg = FDI_RX_CTL(pipe);
4173 temp = I915_READ(reg);
4174 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4175 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4176 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4177 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4178
4179 POSTING_READ(reg);
4180 udelay(200);
4181
4182 /* Switch from Rawclk to PCDclk */
4183 temp = I915_READ(reg);
4184 I915_WRITE(reg, temp | FDI_PCDCLK);
4185
4186 POSTING_READ(reg);
4187 udelay(200);
4188
4189 /* Enable CPU FDI TX PLL, always on for Ironlake */
4190 reg = FDI_TX_CTL(pipe);
4191 temp = I915_READ(reg);
4192 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4193 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4194
4195 POSTING_READ(reg);
4196 udelay(100);
4197 }
4198 }
4199
4200 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4201 {
4202 struct drm_device *dev = intel_crtc->base.dev;
4203 struct drm_i915_private *dev_priv = to_i915(dev);
4204 int pipe = intel_crtc->pipe;
4205 i915_reg_t reg;
4206 u32 temp;
4207
4208 /* Switch from PCDclk to Rawclk */
4209 reg = FDI_RX_CTL(pipe);
4210 temp = I915_READ(reg);
4211 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4212
4213 /* Disable CPU FDI TX PLL */
4214 reg = FDI_TX_CTL(pipe);
4215 temp = I915_READ(reg);
4216 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4217
4218 POSTING_READ(reg);
4219 udelay(100);
4220
4221 reg = FDI_RX_CTL(pipe);
4222 temp = I915_READ(reg);
4223 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4224
4225 /* Wait for the clocks to turn off. */
4226 POSTING_READ(reg);
4227 udelay(100);
4228 }
4229
4230 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4231 {
4232 struct drm_device *dev = crtc->dev;
4233 struct drm_i915_private *dev_priv = to_i915(dev);
4234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4235 int pipe = intel_crtc->pipe;
4236 i915_reg_t reg;
4237 u32 temp;
4238
4239 /* disable CPU FDI tx and PCH FDI rx */
4240 reg = FDI_TX_CTL(pipe);
4241 temp = I915_READ(reg);
4242 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4243 POSTING_READ(reg);
4244
4245 reg = FDI_RX_CTL(pipe);
4246 temp = I915_READ(reg);
4247 temp &= ~(0x7 << 16);
4248 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4249 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4250
4251 POSTING_READ(reg);
4252 udelay(100);
4253
4254 /* Ironlake workaround, disable clock pointer after downing FDI */
4255 if (HAS_PCH_IBX(dev_priv))
4256 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4257
4258 /* still set train pattern 1 */
4259 reg = FDI_TX_CTL(pipe);
4260 temp = I915_READ(reg);
4261 temp &= ~FDI_LINK_TRAIN_NONE;
4262 temp |= FDI_LINK_TRAIN_PATTERN_1;
4263 I915_WRITE(reg, temp);
4264
4265 reg = FDI_RX_CTL(pipe);
4266 temp = I915_READ(reg);
4267 if (HAS_PCH_CPT(dev_priv)) {
4268 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4269 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4270 } else {
4271 temp &= ~FDI_LINK_TRAIN_NONE;
4272 temp |= FDI_LINK_TRAIN_PATTERN_1;
4273 }
4274 /* BPC in FDI rx is consistent with that in PIPECONF */
4275 temp &= ~(0x07 << 16);
4276 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4277 I915_WRITE(reg, temp);
4278
4279 POSTING_READ(reg);
4280 udelay(100);
4281 }
4282
4283 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4284 {
4285 struct drm_crtc *crtc;
4286 bool cleanup_done;
4287
4288 drm_for_each_crtc(crtc, &dev_priv->drm) {
4289 struct drm_crtc_commit *commit;
4290 spin_lock(&crtc->commit_lock);
4291 commit = list_first_entry_or_null(&crtc->commit_list,
4292 struct drm_crtc_commit, commit_entry);
4293 cleanup_done = commit ?
4294 try_wait_for_completion(&commit->cleanup_done) : true;
4295 spin_unlock(&crtc->commit_lock);
4296
4297 if (cleanup_done)
4298 continue;
4299
4300 drm_crtc_wait_one_vblank(crtc);
4301
4302 return true;
4303 }
4304
4305 return false;
4306 }
4307
4308 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4309 {
4310 u32 temp;
4311
4312 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4313
4314 mutex_lock(&dev_priv->sb_lock);
4315
4316 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4317 temp |= SBI_SSCCTL_DISABLE;
4318 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4319
4320 mutex_unlock(&dev_priv->sb_lock);
4321 }
4322
4323 /* Program iCLKIP clock to the desired frequency */
4324 static void lpt_program_iclkip(struct intel_crtc *crtc)
4325 {
4326 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4327 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4328 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4329 u32 temp;
4330
4331 lpt_disable_iclkip(dev_priv);
4332
4333 /* The iCLK virtual clock root frequency is in MHz,
4334 * but the adjusted_mode->crtc_clock in in KHz. To get the
4335 * divisors, it is necessary to divide one by another, so we
4336 * convert the virtual clock precision to KHz here for higher
4337 * precision.
4338 */
4339 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4340 u32 iclk_virtual_root_freq = 172800 * 1000;
4341 u32 iclk_pi_range = 64;
4342 u32 desired_divisor;
4343
4344 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4345 clock << auxdiv);
4346 divsel = (desired_divisor / iclk_pi_range) - 2;
4347 phaseinc = desired_divisor % iclk_pi_range;
4348
4349 /*
4350 * Near 20MHz is a corner case which is
4351 * out of range for the 7-bit divisor
4352 */
4353 if (divsel <= 0x7f)
4354 break;
4355 }
4356
4357 /* This should not happen with any sane values */
4358 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4359 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4360 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4361 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4362
4363 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4364 clock,
4365 auxdiv,
4366 divsel,
4367 phasedir,
4368 phaseinc);
4369
4370 mutex_lock(&dev_priv->sb_lock);
4371
4372 /* Program SSCDIVINTPHASE6 */
4373 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4374 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4375 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4376 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4377 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4378 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4379 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4380 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4381
4382 /* Program SSCAUXDIV */
4383 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4384 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4385 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4386 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4387
4388 /* Enable modulator and associated divider */
4389 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4390 temp &= ~SBI_SSCCTL_DISABLE;
4391 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4392
4393 mutex_unlock(&dev_priv->sb_lock);
4394
4395 /* Wait for initialization time */
4396 udelay(24);
4397
4398 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4399 }
4400
4401 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4402 {
4403 u32 divsel, phaseinc, auxdiv;
4404 u32 iclk_virtual_root_freq = 172800 * 1000;
4405 u32 iclk_pi_range = 64;
4406 u32 desired_divisor;
4407 u32 temp;
4408
4409 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4410 return 0;
4411
4412 mutex_lock(&dev_priv->sb_lock);
4413
4414 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4415 if (temp & SBI_SSCCTL_DISABLE) {
4416 mutex_unlock(&dev_priv->sb_lock);
4417 return 0;
4418 }
4419
4420 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4421 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4422 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4423 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4424 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4425
4426 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4427 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4428 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4429
4430 mutex_unlock(&dev_priv->sb_lock);
4431
4432 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4433
4434 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4435 desired_divisor << auxdiv);
4436 }
4437
4438 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4439 enum pipe pch_transcoder)
4440 {
4441 struct drm_device *dev = crtc->base.dev;
4442 struct drm_i915_private *dev_priv = to_i915(dev);
4443 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4444
4445 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4446 I915_READ(HTOTAL(cpu_transcoder)));
4447 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4448 I915_READ(HBLANK(cpu_transcoder)));
4449 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4450 I915_READ(HSYNC(cpu_transcoder)));
4451
4452 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4453 I915_READ(VTOTAL(cpu_transcoder)));
4454 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4455 I915_READ(VBLANK(cpu_transcoder)));
4456 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4457 I915_READ(VSYNC(cpu_transcoder)));
4458 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4459 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4460 }
4461
4462 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4463 {
4464 struct drm_i915_private *dev_priv = to_i915(dev);
4465 uint32_t temp;
4466
4467 temp = I915_READ(SOUTH_CHICKEN1);
4468 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4469 return;
4470
4471 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4472 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4473
4474 temp &= ~FDI_BC_BIFURCATION_SELECT;
4475 if (enable)
4476 temp |= FDI_BC_BIFURCATION_SELECT;
4477
4478 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4479 I915_WRITE(SOUTH_CHICKEN1, temp);
4480 POSTING_READ(SOUTH_CHICKEN1);
4481 }
4482
4483 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4484 {
4485 struct drm_device *dev = intel_crtc->base.dev;
4486
4487 switch (intel_crtc->pipe) {
4488 case PIPE_A:
4489 break;
4490 case PIPE_B:
4491 if (intel_crtc->config->fdi_lanes > 2)
4492 cpt_set_fdi_bc_bifurcation(dev, false);
4493 else
4494 cpt_set_fdi_bc_bifurcation(dev, true);
4495
4496 break;
4497 case PIPE_C:
4498 cpt_set_fdi_bc_bifurcation(dev, true);
4499
4500 break;
4501 default:
4502 BUG();
4503 }
4504 }
4505
4506 /* Return which DP Port should be selected for Transcoder DP control */
4507 static enum port
4508 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4509 {
4510 struct drm_device *dev = crtc->base.dev;
4511 struct intel_encoder *encoder;
4512
4513 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4514 if (encoder->type == INTEL_OUTPUT_DP ||
4515 encoder->type == INTEL_OUTPUT_EDP)
4516 return encoder->port;
4517 }
4518
4519 return -1;
4520 }
4521
4522 /*
4523 * Enable PCH resources required for PCH ports:
4524 * - PCH PLLs
4525 * - FDI training & RX/TX
4526 * - update transcoder timings
4527 * - DP transcoding bits
4528 * - transcoder
4529 */
4530 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4531 {
4532 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4533 struct drm_device *dev = crtc->base.dev;
4534 struct drm_i915_private *dev_priv = to_i915(dev);
4535 int pipe = crtc->pipe;
4536 u32 temp;
4537
4538 assert_pch_transcoder_disabled(dev_priv, pipe);
4539
4540 if (IS_IVYBRIDGE(dev_priv))
4541 ivybridge_update_fdi_bc_bifurcation(crtc);
4542
4543 /* Write the TU size bits before fdi link training, so that error
4544 * detection works. */
4545 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4546 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4547
4548 /* For PCH output, training FDI link */
4549 dev_priv->display.fdi_link_train(crtc, crtc_state);
4550
4551 /* We need to program the right clock selection before writing the pixel
4552 * mutliplier into the DPLL. */
4553 if (HAS_PCH_CPT(dev_priv)) {
4554 u32 sel;
4555
4556 temp = I915_READ(PCH_DPLL_SEL);
4557 temp |= TRANS_DPLL_ENABLE(pipe);
4558 sel = TRANS_DPLLB_SEL(pipe);
4559 if (crtc_state->shared_dpll ==
4560 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4561 temp |= sel;
4562 else
4563 temp &= ~sel;
4564 I915_WRITE(PCH_DPLL_SEL, temp);
4565 }
4566
4567 /* XXX: pch pll's can be enabled any time before we enable the PCH
4568 * transcoder, and we actually should do this to not upset any PCH
4569 * transcoder that already use the clock when we share it.
4570 *
4571 * Note that enable_shared_dpll tries to do the right thing, but
4572 * get_shared_dpll unconditionally resets the pll - we need that to have
4573 * the right LVDS enable sequence. */
4574 intel_enable_shared_dpll(crtc);
4575
4576 /* set transcoder timing, panel must allow it */
4577 assert_panel_unlocked(dev_priv, pipe);
4578 ironlake_pch_transcoder_set_timings(crtc, pipe);
4579
4580 intel_fdi_normal_train(crtc);
4581
4582 /* For PCH DP, enable TRANS_DP_CTL */
4583 if (HAS_PCH_CPT(dev_priv) &&
4584 intel_crtc_has_dp_encoder(crtc_state)) {
4585 const struct drm_display_mode *adjusted_mode =
4586 &crtc_state->base.adjusted_mode;
4587 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4588 i915_reg_t reg = TRANS_DP_CTL(pipe);
4589 temp = I915_READ(reg);
4590 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4591 TRANS_DP_SYNC_MASK |
4592 TRANS_DP_BPC_MASK);
4593 temp |= TRANS_DP_OUTPUT_ENABLE;
4594 temp |= bpc << 9; /* same format but at 11:9 */
4595
4596 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4597 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4598 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4599 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4600
4601 switch (intel_trans_dp_port_sel(crtc)) {
4602 case PORT_B:
4603 temp |= TRANS_DP_PORT_SEL_B;
4604 break;
4605 case PORT_C:
4606 temp |= TRANS_DP_PORT_SEL_C;
4607 break;
4608 case PORT_D:
4609 temp |= TRANS_DP_PORT_SEL_D;
4610 break;
4611 default:
4612 BUG();
4613 }
4614
4615 I915_WRITE(reg, temp);
4616 }
4617
4618 ironlake_enable_pch_transcoder(dev_priv, pipe);
4619 }
4620
4621 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4622 {
4623 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4624 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4625 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4626
4627 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4628
4629 lpt_program_iclkip(crtc);
4630
4631 /* Set transcoder timing. */
4632 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4633
4634 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4635 }
4636
4637 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4638 {
4639 struct drm_i915_private *dev_priv = to_i915(dev);
4640 i915_reg_t dslreg = PIPEDSL(pipe);
4641 u32 temp;
4642
4643 temp = I915_READ(dslreg);
4644 udelay(500);
4645 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4646 if (wait_for(I915_READ(dslreg) != temp, 5))
4647 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4648 }
4649 }
4650
4651 static int
4652 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4653 unsigned int scaler_user, int *scaler_id,
4654 int src_w, int src_h, int dst_w, int dst_h)
4655 {
4656 struct intel_crtc_scaler_state *scaler_state =
4657 &crtc_state->scaler_state;
4658 struct intel_crtc *intel_crtc =
4659 to_intel_crtc(crtc_state->base.crtc);
4660 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4661 const struct drm_display_mode *adjusted_mode =
4662 &crtc_state->base.adjusted_mode;
4663 int need_scaling;
4664
4665 /*
4666 * Src coordinates are already rotated by 270 degrees for
4667 * the 90/270 degree plane rotation cases (to match the
4668 * GTT mapping), hence no need to account for rotation here.
4669 */
4670 need_scaling = src_w != dst_w || src_h != dst_h;
4671
4672 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4673 need_scaling = true;
4674
4675 /*
4676 * Scaling/fitting not supported in IF-ID mode in GEN9+
4677 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4678 * Once NV12 is enabled, handle it here while allocating scaler
4679 * for NV12.
4680 */
4681 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4682 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4683 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4684 return -EINVAL;
4685 }
4686
4687 /*
4688 * if plane is being disabled or scaler is no more required or force detach
4689 * - free scaler binded to this plane/crtc
4690 * - in order to do this, update crtc->scaler_usage
4691 *
4692 * Here scaler state in crtc_state is set free so that
4693 * scaler can be assigned to other user. Actual register
4694 * update to free the scaler is done in plane/panel-fit programming.
4695 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4696 */
4697 if (force_detach || !need_scaling) {
4698 if (*scaler_id >= 0) {
4699 scaler_state->scaler_users &= ~(1 << scaler_user);
4700 scaler_state->scalers[*scaler_id].in_use = 0;
4701
4702 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4703 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4704 intel_crtc->pipe, scaler_user, *scaler_id,
4705 scaler_state->scaler_users);
4706 *scaler_id = -1;
4707 }
4708 return 0;
4709 }
4710
4711 /* range checks */
4712 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4713 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4714
4715 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4716 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4717 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4718 "size is out of scaler range\n",
4719 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4720 return -EINVAL;
4721 }
4722
4723 /* mark this plane as a scaler user in crtc_state */
4724 scaler_state->scaler_users |= (1 << scaler_user);
4725 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4726 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4727 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4728 scaler_state->scaler_users);
4729
4730 return 0;
4731 }
4732
4733 /**
4734 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4735 *
4736 * @state: crtc's scaler state
4737 *
4738 * Return
4739 * 0 - scaler_usage updated successfully
4740 * error - requested scaling cannot be supported or other error condition
4741 */
4742 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4743 {
4744 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4745
4746 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4747 &state->scaler_state.scaler_id,
4748 state->pipe_src_w, state->pipe_src_h,
4749 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4750 }
4751
4752 /**
4753 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4754 *
4755 * @state: crtc's scaler state
4756 * @plane_state: atomic plane state to update
4757 *
4758 * Return
4759 * 0 - scaler_usage updated successfully
4760 * error - requested scaling cannot be supported or other error condition
4761 */
4762 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4763 struct intel_plane_state *plane_state)
4764 {
4765
4766 struct intel_plane *intel_plane =
4767 to_intel_plane(plane_state->base.plane);
4768 struct drm_framebuffer *fb = plane_state->base.fb;
4769 int ret;
4770
4771 bool force_detach = !fb || !plane_state->base.visible;
4772
4773 ret = skl_update_scaler(crtc_state, force_detach,
4774 drm_plane_index(&intel_plane->base),
4775 &plane_state->scaler_id,
4776 drm_rect_width(&plane_state->base.src) >> 16,
4777 drm_rect_height(&plane_state->base.src) >> 16,
4778 drm_rect_width(&plane_state->base.dst),
4779 drm_rect_height(&plane_state->base.dst));
4780
4781 if (ret || plane_state->scaler_id < 0)
4782 return ret;
4783
4784 /* check colorkey */
4785 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4786 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4787 intel_plane->base.base.id,
4788 intel_plane->base.name);
4789 return -EINVAL;
4790 }
4791
4792 /* Check src format */
4793 switch (fb->format->format) {
4794 case DRM_FORMAT_RGB565:
4795 case DRM_FORMAT_XBGR8888:
4796 case DRM_FORMAT_XRGB8888:
4797 case DRM_FORMAT_ABGR8888:
4798 case DRM_FORMAT_ARGB8888:
4799 case DRM_FORMAT_XRGB2101010:
4800 case DRM_FORMAT_XBGR2101010:
4801 case DRM_FORMAT_YUYV:
4802 case DRM_FORMAT_YVYU:
4803 case DRM_FORMAT_UYVY:
4804 case DRM_FORMAT_VYUY:
4805 break;
4806 default:
4807 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4808 intel_plane->base.base.id, intel_plane->base.name,
4809 fb->base.id, fb->format->format);
4810 return -EINVAL;
4811 }
4812
4813 return 0;
4814 }
4815
4816 static void skylake_scaler_disable(struct intel_crtc *crtc)
4817 {
4818 int i;
4819
4820 for (i = 0; i < crtc->num_scalers; i++)
4821 skl_detach_scaler(crtc, i);
4822 }
4823
4824 static void skylake_pfit_enable(struct intel_crtc *crtc)
4825 {
4826 struct drm_device *dev = crtc->base.dev;
4827 struct drm_i915_private *dev_priv = to_i915(dev);
4828 int pipe = crtc->pipe;
4829 struct intel_crtc_scaler_state *scaler_state =
4830 &crtc->config->scaler_state;
4831
4832 if (crtc->config->pch_pfit.enabled) {
4833 int id;
4834
4835 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4836 return;
4837
4838 id = scaler_state->scaler_id;
4839 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4840 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4841 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4842 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4843 }
4844 }
4845
4846 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4847 {
4848 struct drm_device *dev = crtc->base.dev;
4849 struct drm_i915_private *dev_priv = to_i915(dev);
4850 int pipe = crtc->pipe;
4851
4852 if (crtc->config->pch_pfit.enabled) {
4853 /* Force use of hard-coded filter coefficients
4854 * as some pre-programmed values are broken,
4855 * e.g. x201.
4856 */
4857 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4858 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4859 PF_PIPE_SEL_IVB(pipe));
4860 else
4861 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4862 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4863 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4864 }
4865 }
4866
4867 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
4868 {
4869 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4870 struct drm_device *dev = crtc->base.dev;
4871 struct drm_i915_private *dev_priv = to_i915(dev);
4872
4873 if (!crtc->config->ips_enabled)
4874 return;
4875
4876 /*
4877 * We can only enable IPS after we enable a plane and wait for a vblank
4878 * This function is called from post_plane_update, which is run after
4879 * a vblank wait.
4880 */
4881
4882 assert_plane_enabled(dev_priv, crtc->plane);
4883 if (IS_BROADWELL(dev_priv)) {
4884 mutex_lock(&dev_priv->pcu_lock);
4885 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4886 IPS_ENABLE | IPS_PCODE_CONTROL));
4887 mutex_unlock(&dev_priv->pcu_lock);
4888 /* Quoting Art Runyan: "its not safe to expect any particular
4889 * value in IPS_CTL bit 31 after enabling IPS through the
4890 * mailbox." Moreover, the mailbox may return a bogus state,
4891 * so we need to just enable it and continue on.
4892 */
4893 } else {
4894 I915_WRITE(IPS_CTL, IPS_ENABLE);
4895 /* The bit only becomes 1 in the next vblank, so this wait here
4896 * is essentially intel_wait_for_vblank. If we don't have this
4897 * and don't wait for vblanks until the end of crtc_enable, then
4898 * the HW state readout code will complain that the expected
4899 * IPS_CTL value is not the one we read. */
4900 if (intel_wait_for_register(dev_priv,
4901 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4902 50))
4903 DRM_ERROR("Timed out waiting for IPS enable\n");
4904 }
4905 }
4906
4907 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
4908 {
4909 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4910 struct drm_device *dev = crtc->base.dev;
4911 struct drm_i915_private *dev_priv = to_i915(dev);
4912
4913 if (!crtc_state->ips_enabled)
4914 return;
4915
4916 assert_plane_enabled(dev_priv, crtc->plane);
4917 if (IS_BROADWELL(dev_priv)) {
4918 mutex_lock(&dev_priv->pcu_lock);
4919 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4920 mutex_unlock(&dev_priv->pcu_lock);
4921 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4922 if (intel_wait_for_register(dev_priv,
4923 IPS_CTL, IPS_ENABLE, 0,
4924 42))
4925 DRM_ERROR("Timed out waiting for IPS disable\n");
4926 } else {
4927 I915_WRITE(IPS_CTL, 0);
4928 POSTING_READ(IPS_CTL);
4929 }
4930
4931 /* We need to wait for a vblank before we can disable the plane. */
4932 intel_wait_for_vblank(dev_priv, crtc->pipe);
4933 }
4934
4935 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4936 {
4937 if (intel_crtc->overlay) {
4938 struct drm_device *dev = intel_crtc->base.dev;
4939
4940 mutex_lock(&dev->struct_mutex);
4941 (void) intel_overlay_switch_off(intel_crtc->overlay);
4942 mutex_unlock(&dev->struct_mutex);
4943 }
4944
4945 /* Let userspace switch the overlay on again. In most cases userspace
4946 * has to recompute where to put it anyway.
4947 */
4948 }
4949
4950 /**
4951 * intel_post_enable_primary - Perform operations after enabling primary plane
4952 * @crtc: the CRTC whose primary plane was just enabled
4953 *
4954 * Performs potentially sleeping operations that must be done after the primary
4955 * plane is enabled, such as updating FBC and IPS. Note that this may be
4956 * called due to an explicit primary plane update, or due to an implicit
4957 * re-enable that is caused when a sprite plane is updated to no longer
4958 * completely hide the primary plane.
4959 */
4960 static void
4961 intel_post_enable_primary(struct drm_crtc *crtc,
4962 const struct intel_crtc_state *new_crtc_state)
4963 {
4964 struct drm_device *dev = crtc->dev;
4965 struct drm_i915_private *dev_priv = to_i915(dev);
4966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4967 int pipe = intel_crtc->pipe;
4968
4969 /*
4970 * FIXME IPS should be fine as long as one plane is
4971 * enabled, but in practice it seems to have problems
4972 * when going from primary only to sprite only and vice
4973 * versa.
4974 */
4975 hsw_enable_ips(new_crtc_state);
4976
4977 /*
4978 * Gen2 reports pipe underruns whenever all planes are disabled.
4979 * So don't enable underrun reporting before at least some planes
4980 * are enabled.
4981 * FIXME: Need to fix the logic to work when we turn off all planes
4982 * but leave the pipe running.
4983 */
4984 if (IS_GEN2(dev_priv))
4985 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4986
4987 /* Underruns don't always raise interrupts, so check manually. */
4988 intel_check_cpu_fifo_underruns(dev_priv);
4989 intel_check_pch_fifo_underruns(dev_priv);
4990 }
4991
4992 /* FIXME move all this to pre_plane_update() with proper state tracking */
4993 static void
4994 intel_pre_disable_primary(struct drm_crtc *crtc,
4995 const struct intel_crtc_state *old_crtc_state)
4996 {
4997 struct drm_device *dev = crtc->dev;
4998 struct drm_i915_private *dev_priv = to_i915(dev);
4999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5000 int pipe = intel_crtc->pipe;
5001
5002 /*
5003 * Gen2 reports pipe underruns whenever all planes are disabled.
5004 * So diasble underrun reporting before all the planes get disabled.
5005 * FIXME: Need to fix the logic to work when we turn off all planes
5006 * but leave the pipe running.
5007 */
5008 if (IS_GEN2(dev_priv))
5009 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5010
5011 /*
5012 * FIXME IPS should be fine as long as one plane is
5013 * enabled, but in practice it seems to have problems
5014 * when going from primary only to sprite only and vice
5015 * versa.
5016 */
5017 hsw_disable_ips(old_crtc_state);
5018 }
5019
5020 /* FIXME get rid of this and use pre_plane_update */
5021 static void
5022 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5023 {
5024 struct drm_device *dev = crtc->dev;
5025 struct drm_i915_private *dev_priv = to_i915(dev);
5026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5027 int pipe = intel_crtc->pipe;
5028
5029 intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state));
5030
5031 /*
5032 * Vblank time updates from the shadow to live plane control register
5033 * are blocked if the memory self-refresh mode is active at that
5034 * moment. So to make sure the plane gets truly disabled, disable
5035 * first the self-refresh mode. The self-refresh enable bit in turn
5036 * will be checked/applied by the HW only at the next frame start
5037 * event which is after the vblank start event, so we need to have a
5038 * wait-for-vblank between disabling the plane and the pipe.
5039 */
5040 if (HAS_GMCH_DISPLAY(dev_priv) &&
5041 intel_set_memory_cxsr(dev_priv, false))
5042 intel_wait_for_vblank(dev_priv, pipe);
5043 }
5044
5045 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5046 {
5047 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5048 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5049 struct intel_crtc_state *pipe_config =
5050 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5051 crtc);
5052 struct drm_plane *primary = crtc->base.primary;
5053 struct drm_plane_state *old_pri_state =
5054 drm_atomic_get_existing_plane_state(old_state, primary);
5055
5056 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5057
5058 if (pipe_config->update_wm_post && pipe_config->base.active)
5059 intel_update_watermarks(crtc);
5060
5061 if (old_pri_state) {
5062 struct intel_plane_state *primary_state =
5063 intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5064 to_intel_plane(primary));
5065 struct intel_plane_state *old_primary_state =
5066 to_intel_plane_state(old_pri_state);
5067
5068 intel_fbc_post_update(crtc);
5069
5070 if (primary_state->base.visible &&
5071 (needs_modeset(&pipe_config->base) ||
5072 !old_primary_state->base.visible))
5073 intel_post_enable_primary(&crtc->base, pipe_config);
5074 }
5075 }
5076
5077 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5078 struct intel_crtc_state *pipe_config)
5079 {
5080 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5081 struct drm_device *dev = crtc->base.dev;
5082 struct drm_i915_private *dev_priv = to_i915(dev);
5083 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5084 struct drm_plane *primary = crtc->base.primary;
5085 struct drm_plane_state *old_pri_state =
5086 drm_atomic_get_existing_plane_state(old_state, primary);
5087 bool modeset = needs_modeset(&pipe_config->base);
5088 struct intel_atomic_state *old_intel_state =
5089 to_intel_atomic_state(old_state);
5090
5091 if (old_pri_state) {
5092 struct intel_plane_state *primary_state =
5093 intel_atomic_get_new_plane_state(old_intel_state,
5094 to_intel_plane(primary));
5095 struct intel_plane_state *old_primary_state =
5096 to_intel_plane_state(old_pri_state);
5097
5098 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5099
5100 if (old_primary_state->base.visible &&
5101 (modeset || !primary_state->base.visible))
5102 intel_pre_disable_primary(&crtc->base, old_crtc_state);
5103 }
5104
5105 /*
5106 * Vblank time updates from the shadow to live plane control register
5107 * are blocked if the memory self-refresh mode is active at that
5108 * moment. So to make sure the plane gets truly disabled, disable
5109 * first the self-refresh mode. The self-refresh enable bit in turn
5110 * will be checked/applied by the HW only at the next frame start
5111 * event which is after the vblank start event, so we need to have a
5112 * wait-for-vblank between disabling the plane and the pipe.
5113 */
5114 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5115 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5116 intel_wait_for_vblank(dev_priv, crtc->pipe);
5117
5118 /*
5119 * IVB workaround: must disable low power watermarks for at least
5120 * one frame before enabling scaling. LP watermarks can be re-enabled
5121 * when scaling is disabled.
5122 *
5123 * WaCxSRDisabledForSpriteScaling:ivb
5124 */
5125 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5126 intel_wait_for_vblank(dev_priv, crtc->pipe);
5127
5128 /*
5129 * If we're doing a modeset, we're done. No need to do any pre-vblank
5130 * watermark programming here.
5131 */
5132 if (needs_modeset(&pipe_config->base))
5133 return;
5134
5135 /*
5136 * For platforms that support atomic watermarks, program the
5137 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5138 * will be the intermediate values that are safe for both pre- and
5139 * post- vblank; when vblank happens, the 'active' values will be set
5140 * to the final 'target' values and we'll do this again to get the
5141 * optimal watermarks. For gen9+ platforms, the values we program here
5142 * will be the final target values which will get automatically latched
5143 * at vblank time; no further programming will be necessary.
5144 *
5145 * If a platform hasn't been transitioned to atomic watermarks yet,
5146 * we'll continue to update watermarks the old way, if flags tell
5147 * us to.
5148 */
5149 if (dev_priv->display.initial_watermarks != NULL)
5150 dev_priv->display.initial_watermarks(old_intel_state,
5151 pipe_config);
5152 else if (pipe_config->update_wm_pre)
5153 intel_update_watermarks(crtc);
5154 }
5155
5156 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5157 {
5158 struct drm_device *dev = crtc->dev;
5159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5160 struct drm_plane *p;
5161 int pipe = intel_crtc->pipe;
5162
5163 intel_crtc_dpms_overlay_disable(intel_crtc);
5164
5165 drm_for_each_plane_mask(p, dev, plane_mask)
5166 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5167
5168 /*
5169 * FIXME: Once we grow proper nuclear flip support out of this we need
5170 * to compute the mask of flip planes precisely. For the time being
5171 * consider this a flip to a NULL plane.
5172 */
5173 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5174 }
5175
5176 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5177 struct intel_crtc_state *crtc_state,
5178 struct drm_atomic_state *old_state)
5179 {
5180 struct drm_connector_state *conn_state;
5181 struct drm_connector *conn;
5182 int i;
5183
5184 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5185 struct intel_encoder *encoder =
5186 to_intel_encoder(conn_state->best_encoder);
5187
5188 if (conn_state->crtc != crtc)
5189 continue;
5190
5191 if (encoder->pre_pll_enable)
5192 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5193 }
5194 }
5195
5196 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5197 struct intel_crtc_state *crtc_state,
5198 struct drm_atomic_state *old_state)
5199 {
5200 struct drm_connector_state *conn_state;
5201 struct drm_connector *conn;
5202 int i;
5203
5204 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5205 struct intel_encoder *encoder =
5206 to_intel_encoder(conn_state->best_encoder);
5207
5208 if (conn_state->crtc != crtc)
5209 continue;
5210
5211 if (encoder->pre_enable)
5212 encoder->pre_enable(encoder, crtc_state, conn_state);
5213 }
5214 }
5215
5216 static void intel_encoders_enable(struct drm_crtc *crtc,
5217 struct intel_crtc_state *crtc_state,
5218 struct drm_atomic_state *old_state)
5219 {
5220 struct drm_connector_state *conn_state;
5221 struct drm_connector *conn;
5222 int i;
5223
5224 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5225 struct intel_encoder *encoder =
5226 to_intel_encoder(conn_state->best_encoder);
5227
5228 if (conn_state->crtc != crtc)
5229 continue;
5230
5231 encoder->enable(encoder, crtc_state, conn_state);
5232 intel_opregion_notify_encoder(encoder, true);
5233 }
5234 }
5235
5236 static void intel_encoders_disable(struct drm_crtc *crtc,
5237 struct intel_crtc_state *old_crtc_state,
5238 struct drm_atomic_state *old_state)
5239 {
5240 struct drm_connector_state *old_conn_state;
5241 struct drm_connector *conn;
5242 int i;
5243
5244 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5245 struct intel_encoder *encoder =
5246 to_intel_encoder(old_conn_state->best_encoder);
5247
5248 if (old_conn_state->crtc != crtc)
5249 continue;
5250
5251 intel_opregion_notify_encoder(encoder, false);
5252 encoder->disable(encoder, old_crtc_state, old_conn_state);
5253 }
5254 }
5255
5256 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5257 struct intel_crtc_state *old_crtc_state,
5258 struct drm_atomic_state *old_state)
5259 {
5260 struct drm_connector_state *old_conn_state;
5261 struct drm_connector *conn;
5262 int i;
5263
5264 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5265 struct intel_encoder *encoder =
5266 to_intel_encoder(old_conn_state->best_encoder);
5267
5268 if (old_conn_state->crtc != crtc)
5269 continue;
5270
5271 if (encoder->post_disable)
5272 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5273 }
5274 }
5275
5276 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5277 struct intel_crtc_state *old_crtc_state,
5278 struct drm_atomic_state *old_state)
5279 {
5280 struct drm_connector_state *old_conn_state;
5281 struct drm_connector *conn;
5282 int i;
5283
5284 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5285 struct intel_encoder *encoder =
5286 to_intel_encoder(old_conn_state->best_encoder);
5287
5288 if (old_conn_state->crtc != crtc)
5289 continue;
5290
5291 if (encoder->post_pll_disable)
5292 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5293 }
5294 }
5295
5296 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5297 struct drm_atomic_state *old_state)
5298 {
5299 struct drm_crtc *crtc = pipe_config->base.crtc;
5300 struct drm_device *dev = crtc->dev;
5301 struct drm_i915_private *dev_priv = to_i915(dev);
5302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5303 int pipe = intel_crtc->pipe;
5304 struct intel_atomic_state *old_intel_state =
5305 to_intel_atomic_state(old_state);
5306
5307 if (WARN_ON(intel_crtc->active))
5308 return;
5309
5310 /*
5311 * Sometimes spurious CPU pipe underruns happen during FDI
5312 * training, at least with VGA+HDMI cloning. Suppress them.
5313 *
5314 * On ILK we get an occasional spurious CPU pipe underruns
5315 * between eDP port A enable and vdd enable. Also PCH port
5316 * enable seems to result in the occasional CPU pipe underrun.
5317 *
5318 * Spurious PCH underruns also occur during PCH enabling.
5319 */
5320 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5321 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5322 if (intel_crtc->config->has_pch_encoder)
5323 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5324
5325 if (intel_crtc->config->has_pch_encoder)
5326 intel_prepare_shared_dpll(intel_crtc);
5327
5328 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5329 intel_dp_set_m_n(intel_crtc, M1_N1);
5330
5331 intel_set_pipe_timings(intel_crtc);
5332 intel_set_pipe_src_size(intel_crtc);
5333
5334 if (intel_crtc->config->has_pch_encoder) {
5335 intel_cpu_transcoder_set_m_n(intel_crtc,
5336 &intel_crtc->config->fdi_m_n, NULL);
5337 }
5338
5339 ironlake_set_pipeconf(crtc);
5340
5341 intel_crtc->active = true;
5342
5343 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5344
5345 if (intel_crtc->config->has_pch_encoder) {
5346 /* Note: FDI PLL enabling _must_ be done before we enable the
5347 * cpu pipes, hence this is separate from all the other fdi/pch
5348 * enabling. */
5349 ironlake_fdi_pll_enable(intel_crtc);
5350 } else {
5351 assert_fdi_tx_disabled(dev_priv, pipe);
5352 assert_fdi_rx_disabled(dev_priv, pipe);
5353 }
5354
5355 ironlake_pfit_enable(intel_crtc);
5356
5357 /*
5358 * On ILK+ LUT must be loaded before the pipe is running but with
5359 * clocks enabled
5360 */
5361 intel_color_load_luts(&pipe_config->base);
5362
5363 if (dev_priv->display.initial_watermarks != NULL)
5364 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5365 intel_enable_pipe(intel_crtc);
5366
5367 if (intel_crtc->config->has_pch_encoder)
5368 ironlake_pch_enable(pipe_config);
5369
5370 assert_vblank_disabled(crtc);
5371 drm_crtc_vblank_on(crtc);
5372
5373 intel_encoders_enable(crtc, pipe_config, old_state);
5374
5375 if (HAS_PCH_CPT(dev_priv))
5376 cpt_verify_modeset(dev, intel_crtc->pipe);
5377
5378 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5379 if (intel_crtc->config->has_pch_encoder)
5380 intel_wait_for_vblank(dev_priv, pipe);
5381 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5382 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5383 }
5384
5385 /* IPS only exists on ULT machines and is tied to pipe A. */
5386 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5387 {
5388 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5389 }
5390
5391 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5392 enum pipe pipe, bool apply)
5393 {
5394 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5395 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5396
5397 if (apply)
5398 val |= mask;
5399 else
5400 val &= ~mask;
5401
5402 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5403 }
5404
5405 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5406 struct drm_atomic_state *old_state)
5407 {
5408 struct drm_crtc *crtc = pipe_config->base.crtc;
5409 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5411 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5412 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5413 struct intel_atomic_state *old_intel_state =
5414 to_intel_atomic_state(old_state);
5415 bool psl_clkgate_wa;
5416
5417 if (WARN_ON(intel_crtc->active))
5418 return;
5419
5420 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5421
5422 if (intel_crtc->config->shared_dpll)
5423 intel_enable_shared_dpll(intel_crtc);
5424
5425 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5426 intel_dp_set_m_n(intel_crtc, M1_N1);
5427
5428 if (!transcoder_is_dsi(cpu_transcoder))
5429 intel_set_pipe_timings(intel_crtc);
5430
5431 intel_set_pipe_src_size(intel_crtc);
5432
5433 if (cpu_transcoder != TRANSCODER_EDP &&
5434 !transcoder_is_dsi(cpu_transcoder)) {
5435 I915_WRITE(PIPE_MULT(cpu_transcoder),
5436 intel_crtc->config->pixel_multiplier - 1);
5437 }
5438
5439 if (intel_crtc->config->has_pch_encoder) {
5440 intel_cpu_transcoder_set_m_n(intel_crtc,
5441 &intel_crtc->config->fdi_m_n, NULL);
5442 }
5443
5444 if (!transcoder_is_dsi(cpu_transcoder))
5445 haswell_set_pipeconf(crtc);
5446
5447 haswell_set_pipemisc(crtc);
5448
5449 intel_color_set_csc(&pipe_config->base);
5450
5451 intel_crtc->active = true;
5452
5453 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5454
5455 if (!transcoder_is_dsi(cpu_transcoder))
5456 intel_ddi_enable_pipe_clock(pipe_config);
5457
5458 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5459 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5460 intel_crtc->config->pch_pfit.enabled;
5461 if (psl_clkgate_wa)
5462 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5463
5464 if (INTEL_GEN(dev_priv) >= 9)
5465 skylake_pfit_enable(intel_crtc);
5466 else
5467 ironlake_pfit_enable(intel_crtc);
5468
5469 /*
5470 * On ILK+ LUT must be loaded before the pipe is running but with
5471 * clocks enabled
5472 */
5473 intel_color_load_luts(&pipe_config->base);
5474
5475 intel_ddi_set_pipe_settings(pipe_config);
5476 if (!transcoder_is_dsi(cpu_transcoder))
5477 intel_ddi_enable_transcoder_func(pipe_config);
5478
5479 if (dev_priv->display.initial_watermarks != NULL)
5480 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5481
5482 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5483 if (!transcoder_is_dsi(cpu_transcoder))
5484 intel_enable_pipe(intel_crtc);
5485
5486 if (intel_crtc->config->has_pch_encoder)
5487 lpt_pch_enable(pipe_config);
5488
5489 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5490 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5491
5492 assert_vblank_disabled(crtc);
5493 drm_crtc_vblank_on(crtc);
5494
5495 intel_encoders_enable(crtc, pipe_config, old_state);
5496
5497 if (psl_clkgate_wa) {
5498 intel_wait_for_vblank(dev_priv, pipe);
5499 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5500 }
5501
5502 /* If we change the relative order between pipe/planes enabling, we need
5503 * to change the workaround. */
5504 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5505 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5506 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5507 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5508 }
5509 }
5510
5511 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5512 {
5513 struct drm_device *dev = crtc->base.dev;
5514 struct drm_i915_private *dev_priv = to_i915(dev);
5515 int pipe = crtc->pipe;
5516
5517 /* To avoid upsetting the power well on haswell only disable the pfit if
5518 * it's in use. The hw state code will make sure we get this right. */
5519 if (force || crtc->config->pch_pfit.enabled) {
5520 I915_WRITE(PF_CTL(pipe), 0);
5521 I915_WRITE(PF_WIN_POS(pipe), 0);
5522 I915_WRITE(PF_WIN_SZ(pipe), 0);
5523 }
5524 }
5525
5526 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5527 struct drm_atomic_state *old_state)
5528 {
5529 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5530 struct drm_device *dev = crtc->dev;
5531 struct drm_i915_private *dev_priv = to_i915(dev);
5532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5533 int pipe = intel_crtc->pipe;
5534
5535 /*
5536 * Sometimes spurious CPU pipe underruns happen when the
5537 * pipe is already disabled, but FDI RX/TX is still enabled.
5538 * Happens at least with VGA+HDMI cloning. Suppress them.
5539 */
5540 if (intel_crtc->config->has_pch_encoder) {
5541 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5542 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5543 }
5544
5545 intel_encoders_disable(crtc, old_crtc_state, old_state);
5546
5547 drm_crtc_vblank_off(crtc);
5548 assert_vblank_disabled(crtc);
5549
5550 intel_disable_pipe(intel_crtc);
5551
5552 ironlake_pfit_disable(intel_crtc, false);
5553
5554 if (intel_crtc->config->has_pch_encoder)
5555 ironlake_fdi_disable(crtc);
5556
5557 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5558
5559 if (intel_crtc->config->has_pch_encoder) {
5560 ironlake_disable_pch_transcoder(dev_priv, pipe);
5561
5562 if (HAS_PCH_CPT(dev_priv)) {
5563 i915_reg_t reg;
5564 u32 temp;
5565
5566 /* disable TRANS_DP_CTL */
5567 reg = TRANS_DP_CTL(pipe);
5568 temp = I915_READ(reg);
5569 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5570 TRANS_DP_PORT_SEL_MASK);
5571 temp |= TRANS_DP_PORT_SEL_NONE;
5572 I915_WRITE(reg, temp);
5573
5574 /* disable DPLL_SEL */
5575 temp = I915_READ(PCH_DPLL_SEL);
5576 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5577 I915_WRITE(PCH_DPLL_SEL, temp);
5578 }
5579
5580 ironlake_fdi_pll_disable(intel_crtc);
5581 }
5582
5583 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5584 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5585 }
5586
5587 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5588 struct drm_atomic_state *old_state)
5589 {
5590 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5591 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5593 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5594
5595 intel_encoders_disable(crtc, old_crtc_state, old_state);
5596
5597 drm_crtc_vblank_off(crtc);
5598 assert_vblank_disabled(crtc);
5599
5600 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5601 if (!transcoder_is_dsi(cpu_transcoder))
5602 intel_disable_pipe(intel_crtc);
5603
5604 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5605 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5606
5607 if (!transcoder_is_dsi(cpu_transcoder))
5608 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5609
5610 if (INTEL_GEN(dev_priv) >= 9)
5611 skylake_scaler_disable(intel_crtc);
5612 else
5613 ironlake_pfit_disable(intel_crtc, false);
5614
5615 if (!transcoder_is_dsi(cpu_transcoder))
5616 intel_ddi_disable_pipe_clock(intel_crtc->config);
5617
5618 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5619 }
5620
5621 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5622 {
5623 struct drm_device *dev = crtc->base.dev;
5624 struct drm_i915_private *dev_priv = to_i915(dev);
5625 struct intel_crtc_state *pipe_config = crtc->config;
5626
5627 if (!pipe_config->gmch_pfit.control)
5628 return;
5629
5630 /*
5631 * The panel fitter should only be adjusted whilst the pipe is disabled,
5632 * according to register description and PRM.
5633 */
5634 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5635 assert_pipe_disabled(dev_priv, crtc->pipe);
5636
5637 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5638 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5639
5640 /* Border color in case we don't scale up to the full screen. Black by
5641 * default, change to something else for debugging. */
5642 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5643 }
5644
5645 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5646 {
5647 switch (port) {
5648 case PORT_A:
5649 return POWER_DOMAIN_PORT_DDI_A_LANES;
5650 case PORT_B:
5651 return POWER_DOMAIN_PORT_DDI_B_LANES;
5652 case PORT_C:
5653 return POWER_DOMAIN_PORT_DDI_C_LANES;
5654 case PORT_D:
5655 return POWER_DOMAIN_PORT_DDI_D_LANES;
5656 case PORT_E:
5657 return POWER_DOMAIN_PORT_DDI_E_LANES;
5658 default:
5659 MISSING_CASE(port);
5660 return POWER_DOMAIN_PORT_OTHER;
5661 }
5662 }
5663
5664 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5665 struct intel_crtc_state *crtc_state)
5666 {
5667 struct drm_device *dev = crtc->dev;
5668 struct drm_i915_private *dev_priv = to_i915(dev);
5669 struct drm_encoder *encoder;
5670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5671 enum pipe pipe = intel_crtc->pipe;
5672 u64 mask;
5673 enum transcoder transcoder = crtc_state->cpu_transcoder;
5674
5675 if (!crtc_state->base.active)
5676 return 0;
5677
5678 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5679 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5680 if (crtc_state->pch_pfit.enabled ||
5681 crtc_state->pch_pfit.force_thru)
5682 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5683
5684 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5685 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5686
5687 mask |= BIT_ULL(intel_encoder->power_domain);
5688 }
5689
5690 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5691 mask |= BIT(POWER_DOMAIN_AUDIO);
5692
5693 if (crtc_state->shared_dpll)
5694 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5695
5696 return mask;
5697 }
5698
5699 static u64
5700 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5701 struct intel_crtc_state *crtc_state)
5702 {
5703 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5705 enum intel_display_power_domain domain;
5706 u64 domains, new_domains, old_domains;
5707
5708 old_domains = intel_crtc->enabled_power_domains;
5709 intel_crtc->enabled_power_domains = new_domains =
5710 get_crtc_power_domains(crtc, crtc_state);
5711
5712 domains = new_domains & ~old_domains;
5713
5714 for_each_power_domain(domain, domains)
5715 intel_display_power_get(dev_priv, domain);
5716
5717 return old_domains & ~new_domains;
5718 }
5719
5720 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5721 u64 domains)
5722 {
5723 enum intel_display_power_domain domain;
5724
5725 for_each_power_domain(domain, domains)
5726 intel_display_power_put(dev_priv, domain);
5727 }
5728
5729 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5730 struct drm_atomic_state *old_state)
5731 {
5732 struct intel_atomic_state *old_intel_state =
5733 to_intel_atomic_state(old_state);
5734 struct drm_crtc *crtc = pipe_config->base.crtc;
5735 struct drm_device *dev = crtc->dev;
5736 struct drm_i915_private *dev_priv = to_i915(dev);
5737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5738 int pipe = intel_crtc->pipe;
5739
5740 if (WARN_ON(intel_crtc->active))
5741 return;
5742
5743 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5744 intel_dp_set_m_n(intel_crtc, M1_N1);
5745
5746 intel_set_pipe_timings(intel_crtc);
5747 intel_set_pipe_src_size(intel_crtc);
5748
5749 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5750 struct drm_i915_private *dev_priv = to_i915(dev);
5751
5752 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5753 I915_WRITE(CHV_CANVAS(pipe), 0);
5754 }
5755
5756 i9xx_set_pipeconf(intel_crtc);
5757
5758 intel_crtc->active = true;
5759
5760 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5761
5762 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5763
5764 if (IS_CHERRYVIEW(dev_priv)) {
5765 chv_prepare_pll(intel_crtc, intel_crtc->config);
5766 chv_enable_pll(intel_crtc, intel_crtc->config);
5767 } else {
5768 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5769 vlv_enable_pll(intel_crtc, intel_crtc->config);
5770 }
5771
5772 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5773
5774 i9xx_pfit_enable(intel_crtc);
5775
5776 intel_color_load_luts(&pipe_config->base);
5777
5778 dev_priv->display.initial_watermarks(old_intel_state,
5779 pipe_config);
5780 intel_enable_pipe(intel_crtc);
5781
5782 assert_vblank_disabled(crtc);
5783 drm_crtc_vblank_on(crtc);
5784
5785 intel_encoders_enable(crtc, pipe_config, old_state);
5786 }
5787
5788 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5789 {
5790 struct drm_device *dev = crtc->base.dev;
5791 struct drm_i915_private *dev_priv = to_i915(dev);
5792
5793 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5794 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5795 }
5796
5797 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5798 struct drm_atomic_state *old_state)
5799 {
5800 struct intel_atomic_state *old_intel_state =
5801 to_intel_atomic_state(old_state);
5802 struct drm_crtc *crtc = pipe_config->base.crtc;
5803 struct drm_device *dev = crtc->dev;
5804 struct drm_i915_private *dev_priv = to_i915(dev);
5805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5806 enum pipe pipe = intel_crtc->pipe;
5807
5808 if (WARN_ON(intel_crtc->active))
5809 return;
5810
5811 i9xx_set_pll_dividers(intel_crtc);
5812
5813 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5814 intel_dp_set_m_n(intel_crtc, M1_N1);
5815
5816 intel_set_pipe_timings(intel_crtc);
5817 intel_set_pipe_src_size(intel_crtc);
5818
5819 i9xx_set_pipeconf(intel_crtc);
5820
5821 intel_crtc->active = true;
5822
5823 if (!IS_GEN2(dev_priv))
5824 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5825
5826 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5827
5828 i9xx_enable_pll(intel_crtc, pipe_config);
5829
5830 i9xx_pfit_enable(intel_crtc);
5831
5832 intel_color_load_luts(&pipe_config->base);
5833
5834 if (dev_priv->display.initial_watermarks != NULL)
5835 dev_priv->display.initial_watermarks(old_intel_state,
5836 intel_crtc->config);
5837 else
5838 intel_update_watermarks(intel_crtc);
5839 intel_enable_pipe(intel_crtc);
5840
5841 assert_vblank_disabled(crtc);
5842 drm_crtc_vblank_on(crtc);
5843
5844 intel_encoders_enable(crtc, pipe_config, old_state);
5845 }
5846
5847 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5848 {
5849 struct drm_device *dev = crtc->base.dev;
5850 struct drm_i915_private *dev_priv = to_i915(dev);
5851
5852 if (!crtc->config->gmch_pfit.control)
5853 return;
5854
5855 assert_pipe_disabled(dev_priv, crtc->pipe);
5856
5857 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5858 I915_READ(PFIT_CONTROL));
5859 I915_WRITE(PFIT_CONTROL, 0);
5860 }
5861
5862 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5863 struct drm_atomic_state *old_state)
5864 {
5865 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5866 struct drm_device *dev = crtc->dev;
5867 struct drm_i915_private *dev_priv = to_i915(dev);
5868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5869 int pipe = intel_crtc->pipe;
5870
5871 /*
5872 * On gen2 planes are double buffered but the pipe isn't, so we must
5873 * wait for planes to fully turn off before disabling the pipe.
5874 */
5875 if (IS_GEN2(dev_priv))
5876 intel_wait_for_vblank(dev_priv, pipe);
5877
5878 intel_encoders_disable(crtc, old_crtc_state, old_state);
5879
5880 drm_crtc_vblank_off(crtc);
5881 assert_vblank_disabled(crtc);
5882
5883 intel_disable_pipe(intel_crtc);
5884
5885 i9xx_pfit_disable(intel_crtc);
5886
5887 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5888
5889 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5890 if (IS_CHERRYVIEW(dev_priv))
5891 chv_disable_pll(dev_priv, pipe);
5892 else if (IS_VALLEYVIEW(dev_priv))
5893 vlv_disable_pll(dev_priv, pipe);
5894 else
5895 i9xx_disable_pll(intel_crtc);
5896 }
5897
5898 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5899
5900 if (!IS_GEN2(dev_priv))
5901 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5902
5903 if (!dev_priv->display.initial_watermarks)
5904 intel_update_watermarks(intel_crtc);
5905
5906 /* clock the pipe down to 640x480@60 to potentially save power */
5907 if (IS_I830(dev_priv))
5908 i830_enable_pipe(dev_priv, pipe);
5909 }
5910
5911 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5912 struct drm_modeset_acquire_ctx *ctx)
5913 {
5914 struct intel_encoder *encoder;
5915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5916 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5917 enum intel_display_power_domain domain;
5918 u64 domains;
5919 struct drm_atomic_state *state;
5920 struct intel_crtc_state *crtc_state;
5921 int ret;
5922
5923 if (!intel_crtc->active)
5924 return;
5925
5926 if (crtc->primary->state->visible) {
5927 intel_pre_disable_primary_noatomic(crtc);
5928
5929 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5930 crtc->primary->state->visible = false;
5931 }
5932
5933 state = drm_atomic_state_alloc(crtc->dev);
5934 if (!state) {
5935 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5936 crtc->base.id, crtc->name);
5937 return;
5938 }
5939
5940 state->acquire_ctx = ctx;
5941
5942 /* Everything's already locked, -EDEADLK can't happen. */
5943 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5944 ret = drm_atomic_add_affected_connectors(state, crtc);
5945
5946 WARN_ON(IS_ERR(crtc_state) || ret);
5947
5948 dev_priv->display.crtc_disable(crtc_state, state);
5949
5950 drm_atomic_state_put(state);
5951
5952 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5953 crtc->base.id, crtc->name);
5954
5955 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5956 crtc->state->active = false;
5957 intel_crtc->active = false;
5958 crtc->enabled = false;
5959 crtc->state->connector_mask = 0;
5960 crtc->state->encoder_mask = 0;
5961
5962 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5963 encoder->base.crtc = NULL;
5964
5965 intel_fbc_disable(intel_crtc);
5966 intel_update_watermarks(intel_crtc);
5967 intel_disable_shared_dpll(intel_crtc);
5968
5969 domains = intel_crtc->enabled_power_domains;
5970 for_each_power_domain(domain, domains)
5971 intel_display_power_put(dev_priv, domain);
5972 intel_crtc->enabled_power_domains = 0;
5973
5974 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5975 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
5976 dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
5977 }
5978
5979 /*
5980 * turn all crtc's off, but do not adjust state
5981 * This has to be paired with a call to intel_modeset_setup_hw_state.
5982 */
5983 int intel_display_suspend(struct drm_device *dev)
5984 {
5985 struct drm_i915_private *dev_priv = to_i915(dev);
5986 struct drm_atomic_state *state;
5987 int ret;
5988
5989 state = drm_atomic_helper_suspend(dev);
5990 ret = PTR_ERR_OR_ZERO(state);
5991 if (ret)
5992 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5993 else
5994 dev_priv->modeset_restore_state = state;
5995 return ret;
5996 }
5997
5998 void intel_encoder_destroy(struct drm_encoder *encoder)
5999 {
6000 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6001
6002 drm_encoder_cleanup(encoder);
6003 kfree(intel_encoder);
6004 }
6005
6006 /* Cross check the actual hw state with our own modeset state tracking (and it's
6007 * internal consistency). */
6008 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6009 struct drm_connector_state *conn_state)
6010 {
6011 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6012
6013 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6014 connector->base.base.id,
6015 connector->base.name);
6016
6017 if (connector->get_hw_state(connector)) {
6018 struct intel_encoder *encoder = connector->encoder;
6019
6020 I915_STATE_WARN(!crtc_state,
6021 "connector enabled without attached crtc\n");
6022
6023 if (!crtc_state)
6024 return;
6025
6026 I915_STATE_WARN(!crtc_state->active,
6027 "connector is active, but attached crtc isn't\n");
6028
6029 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6030 return;
6031
6032 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6033 "atomic encoder doesn't match attached encoder\n");
6034
6035 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6036 "attached encoder crtc differs from connector crtc\n");
6037 } else {
6038 I915_STATE_WARN(crtc_state && crtc_state->active,
6039 "attached crtc is active, but connector isn't\n");
6040 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6041 "best encoder set without crtc!\n");
6042 }
6043 }
6044
6045 int intel_connector_init(struct intel_connector *connector)
6046 {
6047 struct intel_digital_connector_state *conn_state;
6048
6049 /*
6050 * Allocate enough memory to hold intel_digital_connector_state,
6051 * This might be a few bytes too many, but for connectors that don't
6052 * need it we'll free the state and allocate a smaller one on the first
6053 * succesful commit anyway.
6054 */
6055 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6056 if (!conn_state)
6057 return -ENOMEM;
6058
6059 __drm_atomic_helper_connector_reset(&connector->base,
6060 &conn_state->base);
6061
6062 return 0;
6063 }
6064
6065 struct intel_connector *intel_connector_alloc(void)
6066 {
6067 struct intel_connector *connector;
6068
6069 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6070 if (!connector)
6071 return NULL;
6072
6073 if (intel_connector_init(connector) < 0) {
6074 kfree(connector);
6075 return NULL;
6076 }
6077
6078 return connector;
6079 }
6080
6081 /*
6082 * Free the bits allocated by intel_connector_alloc.
6083 * This should only be used after intel_connector_alloc has returned
6084 * successfully, and before drm_connector_init returns successfully.
6085 * Otherwise the destroy callbacks for the connector and the state should
6086 * take care of proper cleanup/free
6087 */
6088 void intel_connector_free(struct intel_connector *connector)
6089 {
6090 kfree(to_intel_digital_connector_state(connector->base.state));
6091 kfree(connector);
6092 }
6093
6094 /* Simple connector->get_hw_state implementation for encoders that support only
6095 * one connector and no cloning and hence the encoder state determines the state
6096 * of the connector. */
6097 bool intel_connector_get_hw_state(struct intel_connector *connector)
6098 {
6099 enum pipe pipe = 0;
6100 struct intel_encoder *encoder = connector->encoder;
6101
6102 return encoder->get_hw_state(encoder, &pipe);
6103 }
6104
6105 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6106 {
6107 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6108 return crtc_state->fdi_lanes;
6109
6110 return 0;
6111 }
6112
6113 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6114 struct intel_crtc_state *pipe_config)
6115 {
6116 struct drm_i915_private *dev_priv = to_i915(dev);
6117 struct drm_atomic_state *state = pipe_config->base.state;
6118 struct intel_crtc *other_crtc;
6119 struct intel_crtc_state *other_crtc_state;
6120
6121 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6122 pipe_name(pipe), pipe_config->fdi_lanes);
6123 if (pipe_config->fdi_lanes > 4) {
6124 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6125 pipe_name(pipe), pipe_config->fdi_lanes);
6126 return -EINVAL;
6127 }
6128
6129 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6130 if (pipe_config->fdi_lanes > 2) {
6131 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6132 pipe_config->fdi_lanes);
6133 return -EINVAL;
6134 } else {
6135 return 0;
6136 }
6137 }
6138
6139 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6140 return 0;
6141
6142 /* Ivybridge 3 pipe is really complicated */
6143 switch (pipe) {
6144 case PIPE_A:
6145 return 0;
6146 case PIPE_B:
6147 if (pipe_config->fdi_lanes <= 2)
6148 return 0;
6149
6150 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6151 other_crtc_state =
6152 intel_atomic_get_crtc_state(state, other_crtc);
6153 if (IS_ERR(other_crtc_state))
6154 return PTR_ERR(other_crtc_state);
6155
6156 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6157 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6158 pipe_name(pipe), pipe_config->fdi_lanes);
6159 return -EINVAL;
6160 }
6161 return 0;
6162 case PIPE_C:
6163 if (pipe_config->fdi_lanes > 2) {
6164 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6165 pipe_name(pipe), pipe_config->fdi_lanes);
6166 return -EINVAL;
6167 }
6168
6169 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6170 other_crtc_state =
6171 intel_atomic_get_crtc_state(state, other_crtc);
6172 if (IS_ERR(other_crtc_state))
6173 return PTR_ERR(other_crtc_state);
6174
6175 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6176 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6177 return -EINVAL;
6178 }
6179 return 0;
6180 default:
6181 BUG();
6182 }
6183 }
6184
6185 #define RETRY 1
6186 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6187 struct intel_crtc_state *pipe_config)
6188 {
6189 struct drm_device *dev = intel_crtc->base.dev;
6190 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6191 int lane, link_bw, fdi_dotclock, ret;
6192 bool needs_recompute = false;
6193
6194 retry:
6195 /* FDI is a binary signal running at ~2.7GHz, encoding
6196 * each output octet as 10 bits. The actual frequency
6197 * is stored as a divider into a 100MHz clock, and the
6198 * mode pixel clock is stored in units of 1KHz.
6199 * Hence the bw of each lane in terms of the mode signal
6200 * is:
6201 */
6202 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6203
6204 fdi_dotclock = adjusted_mode->crtc_clock;
6205
6206 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6207 pipe_config->pipe_bpp);
6208
6209 pipe_config->fdi_lanes = lane;
6210
6211 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6212 link_bw, &pipe_config->fdi_m_n, false);
6213
6214 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6215 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6216 pipe_config->pipe_bpp -= 2*3;
6217 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6218 pipe_config->pipe_bpp);
6219 needs_recompute = true;
6220 pipe_config->bw_constrained = true;
6221
6222 goto retry;
6223 }
6224
6225 if (needs_recompute)
6226 return RETRY;
6227
6228 return ret;
6229 }
6230
6231 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6232 struct intel_crtc_state *pipe_config)
6233 {
6234 if (pipe_config->ips_force_disable)
6235 return false;
6236
6237 if (pipe_config->pipe_bpp > 24)
6238 return false;
6239
6240 /* HSW can handle pixel rate up to cdclk? */
6241 if (IS_HASWELL(dev_priv))
6242 return true;
6243
6244 /*
6245 * We compare against max which means we must take
6246 * the increased cdclk requirement into account when
6247 * calculating the new cdclk.
6248 *
6249 * Should measure whether using a lower cdclk w/o IPS
6250 */
6251 return pipe_config->pixel_rate <=
6252 dev_priv->max_cdclk_freq * 95 / 100;
6253 }
6254
6255 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6256 struct intel_crtc_state *pipe_config)
6257 {
6258 struct drm_device *dev = crtc->base.dev;
6259 struct drm_i915_private *dev_priv = to_i915(dev);
6260
6261 pipe_config->ips_enabled = i915_modparams.enable_ips &&
6262 hsw_crtc_supports_ips(crtc) &&
6263 pipe_config_supports_ips(dev_priv, pipe_config);
6264 }
6265
6266 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6267 {
6268 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6269
6270 /* GDG double wide on either pipe, otherwise pipe A only */
6271 return INTEL_INFO(dev_priv)->gen < 4 &&
6272 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6273 }
6274
6275 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6276 {
6277 uint32_t pixel_rate;
6278
6279 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6280
6281 /*
6282 * We only use IF-ID interlacing. If we ever use
6283 * PF-ID we'll need to adjust the pixel_rate here.
6284 */
6285
6286 if (pipe_config->pch_pfit.enabled) {
6287 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6288 uint32_t pfit_size = pipe_config->pch_pfit.size;
6289
6290 pipe_w = pipe_config->pipe_src_w;
6291 pipe_h = pipe_config->pipe_src_h;
6292
6293 pfit_w = (pfit_size >> 16) & 0xFFFF;
6294 pfit_h = pfit_size & 0xFFFF;
6295 if (pipe_w < pfit_w)
6296 pipe_w = pfit_w;
6297 if (pipe_h < pfit_h)
6298 pipe_h = pfit_h;
6299
6300 if (WARN_ON(!pfit_w || !pfit_h))
6301 return pixel_rate;
6302
6303 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6304 pfit_w * pfit_h);
6305 }
6306
6307 return pixel_rate;
6308 }
6309
6310 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6311 {
6312 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6313
6314 if (HAS_GMCH_DISPLAY(dev_priv))
6315 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6316 crtc_state->pixel_rate =
6317 crtc_state->base.adjusted_mode.crtc_clock;
6318 else
6319 crtc_state->pixel_rate =
6320 ilk_pipe_pixel_rate(crtc_state);
6321 }
6322
6323 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6324 struct intel_crtc_state *pipe_config)
6325 {
6326 struct drm_device *dev = crtc->base.dev;
6327 struct drm_i915_private *dev_priv = to_i915(dev);
6328 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6329 int clock_limit = dev_priv->max_dotclk_freq;
6330
6331 if (INTEL_GEN(dev_priv) < 4) {
6332 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6333
6334 /*
6335 * Enable double wide mode when the dot clock
6336 * is > 90% of the (display) core speed.
6337 */
6338 if (intel_crtc_supports_double_wide(crtc) &&
6339 adjusted_mode->crtc_clock > clock_limit) {
6340 clock_limit = dev_priv->max_dotclk_freq;
6341 pipe_config->double_wide = true;
6342 }
6343 }
6344
6345 if (adjusted_mode->crtc_clock > clock_limit) {
6346 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6347 adjusted_mode->crtc_clock, clock_limit,
6348 yesno(pipe_config->double_wide));
6349 return -EINVAL;
6350 }
6351
6352 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6353 /*
6354 * There is only one pipe CSC unit per pipe, and we need that
6355 * for output conversion from RGB->YCBCR. So if CTM is already
6356 * applied we can't support YCBCR420 output.
6357 */
6358 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6359 return -EINVAL;
6360 }
6361
6362 /*
6363 * Pipe horizontal size must be even in:
6364 * - DVO ganged mode
6365 * - LVDS dual channel mode
6366 * - Double wide pipe
6367 */
6368 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6369 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6370 pipe_config->pipe_src_w &= ~1;
6371
6372 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6373 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6374 */
6375 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6376 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6377 return -EINVAL;
6378
6379 intel_crtc_compute_pixel_rate(pipe_config);
6380
6381 if (HAS_IPS(dev_priv))
6382 hsw_compute_ips_config(crtc, pipe_config);
6383
6384 if (pipe_config->has_pch_encoder)
6385 return ironlake_fdi_compute_config(crtc, pipe_config);
6386
6387 return 0;
6388 }
6389
6390 static void
6391 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6392 {
6393 while (*num > DATA_LINK_M_N_MASK ||
6394 *den > DATA_LINK_M_N_MASK) {
6395 *num >>= 1;
6396 *den >>= 1;
6397 }
6398 }
6399
6400 static void compute_m_n(unsigned int m, unsigned int n,
6401 uint32_t *ret_m, uint32_t *ret_n,
6402 bool reduce_m_n)
6403 {
6404 /*
6405 * Reduce M/N as much as possible without loss in precision. Several DP
6406 * dongles in particular seem to be fussy about too large *link* M/N
6407 * values. The passed in values are more likely to have the least
6408 * significant bits zero than M after rounding below, so do this first.
6409 */
6410 if (reduce_m_n) {
6411 while ((m & 1) == 0 && (n & 1) == 0) {
6412 m >>= 1;
6413 n >>= 1;
6414 }
6415 }
6416
6417 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6418 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6419 intel_reduce_m_n_ratio(ret_m, ret_n);
6420 }
6421
6422 void
6423 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6424 int pixel_clock, int link_clock,
6425 struct intel_link_m_n *m_n,
6426 bool reduce_m_n)
6427 {
6428 m_n->tu = 64;
6429
6430 compute_m_n(bits_per_pixel * pixel_clock,
6431 link_clock * nlanes * 8,
6432 &m_n->gmch_m, &m_n->gmch_n,
6433 reduce_m_n);
6434
6435 compute_m_n(pixel_clock, link_clock,
6436 &m_n->link_m, &m_n->link_n,
6437 reduce_m_n);
6438 }
6439
6440 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6441 {
6442 if (i915_modparams.panel_use_ssc >= 0)
6443 return i915_modparams.panel_use_ssc != 0;
6444 return dev_priv->vbt.lvds_use_ssc
6445 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6446 }
6447
6448 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6449 {
6450 return (1 << dpll->n) << 16 | dpll->m2;
6451 }
6452
6453 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6454 {
6455 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6456 }
6457
6458 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6459 struct intel_crtc_state *crtc_state,
6460 struct dpll *reduced_clock)
6461 {
6462 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6463 u32 fp, fp2 = 0;
6464
6465 if (IS_PINEVIEW(dev_priv)) {
6466 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6467 if (reduced_clock)
6468 fp2 = pnv_dpll_compute_fp(reduced_clock);
6469 } else {
6470 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6471 if (reduced_clock)
6472 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6473 }
6474
6475 crtc_state->dpll_hw_state.fp0 = fp;
6476
6477 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6478 reduced_clock) {
6479 crtc_state->dpll_hw_state.fp1 = fp2;
6480 } else {
6481 crtc_state->dpll_hw_state.fp1 = fp;
6482 }
6483 }
6484
6485 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6486 pipe)
6487 {
6488 u32 reg_val;
6489
6490 /*
6491 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6492 * and set it to a reasonable value instead.
6493 */
6494 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6495 reg_val &= 0xffffff00;
6496 reg_val |= 0x00000030;
6497 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6498
6499 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6500 reg_val &= 0x00ffffff;
6501 reg_val |= 0x8c000000;
6502 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6503
6504 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6505 reg_val &= 0xffffff00;
6506 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6507
6508 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6509 reg_val &= 0x00ffffff;
6510 reg_val |= 0xb0000000;
6511 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6512 }
6513
6514 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6515 struct intel_link_m_n *m_n)
6516 {
6517 struct drm_device *dev = crtc->base.dev;
6518 struct drm_i915_private *dev_priv = to_i915(dev);
6519 int pipe = crtc->pipe;
6520
6521 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6522 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6523 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6524 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6525 }
6526
6527 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6528 struct intel_link_m_n *m_n,
6529 struct intel_link_m_n *m2_n2)
6530 {
6531 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6532 int pipe = crtc->pipe;
6533 enum transcoder transcoder = crtc->config->cpu_transcoder;
6534
6535 if (INTEL_GEN(dev_priv) >= 5) {
6536 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6537 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6538 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6539 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6540 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6541 * for gen < 8) and if DRRS is supported (to make sure the
6542 * registers are not unnecessarily accessed).
6543 */
6544 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6545 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6546 I915_WRITE(PIPE_DATA_M2(transcoder),
6547 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6548 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6549 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6550 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6551 }
6552 } else {
6553 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6554 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6555 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6556 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6557 }
6558 }
6559
6560 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6561 {
6562 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6563
6564 if (m_n == M1_N1) {
6565 dp_m_n = &crtc->config->dp_m_n;
6566 dp_m2_n2 = &crtc->config->dp_m2_n2;
6567 } else if (m_n == M2_N2) {
6568
6569 /*
6570 * M2_N2 registers are not supported. Hence m2_n2 divider value
6571 * needs to be programmed into M1_N1.
6572 */
6573 dp_m_n = &crtc->config->dp_m2_n2;
6574 } else {
6575 DRM_ERROR("Unsupported divider value\n");
6576 return;
6577 }
6578
6579 if (crtc->config->has_pch_encoder)
6580 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6581 else
6582 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6583 }
6584
6585 static void vlv_compute_dpll(struct intel_crtc *crtc,
6586 struct intel_crtc_state *pipe_config)
6587 {
6588 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6589 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6590 if (crtc->pipe != PIPE_A)
6591 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6592
6593 /* DPLL not used with DSI, but still need the rest set up */
6594 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6595 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6596 DPLL_EXT_BUFFER_ENABLE_VLV;
6597
6598 pipe_config->dpll_hw_state.dpll_md =
6599 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6600 }
6601
6602 static void chv_compute_dpll(struct intel_crtc *crtc,
6603 struct intel_crtc_state *pipe_config)
6604 {
6605 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6606 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6607 if (crtc->pipe != PIPE_A)
6608 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6609
6610 /* DPLL not used with DSI, but still need the rest set up */
6611 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6612 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6613
6614 pipe_config->dpll_hw_state.dpll_md =
6615 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6616 }
6617
6618 static void vlv_prepare_pll(struct intel_crtc *crtc,
6619 const struct intel_crtc_state *pipe_config)
6620 {
6621 struct drm_device *dev = crtc->base.dev;
6622 struct drm_i915_private *dev_priv = to_i915(dev);
6623 enum pipe pipe = crtc->pipe;
6624 u32 mdiv;
6625 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6626 u32 coreclk, reg_val;
6627
6628 /* Enable Refclk */
6629 I915_WRITE(DPLL(pipe),
6630 pipe_config->dpll_hw_state.dpll &
6631 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6632
6633 /* No need to actually set up the DPLL with DSI */
6634 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6635 return;
6636
6637 mutex_lock(&dev_priv->sb_lock);
6638
6639 bestn = pipe_config->dpll.n;
6640 bestm1 = pipe_config->dpll.m1;
6641 bestm2 = pipe_config->dpll.m2;
6642 bestp1 = pipe_config->dpll.p1;
6643 bestp2 = pipe_config->dpll.p2;
6644
6645 /* See eDP HDMI DPIO driver vbios notes doc */
6646
6647 /* PLL B needs special handling */
6648 if (pipe == PIPE_B)
6649 vlv_pllb_recal_opamp(dev_priv, pipe);
6650
6651 /* Set up Tx target for periodic Rcomp update */
6652 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6653
6654 /* Disable target IRef on PLL */
6655 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6656 reg_val &= 0x00ffffff;
6657 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6658
6659 /* Disable fast lock */
6660 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6661
6662 /* Set idtafcrecal before PLL is enabled */
6663 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6664 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6665 mdiv |= ((bestn << DPIO_N_SHIFT));
6666 mdiv |= (1 << DPIO_K_SHIFT);
6667
6668 /*
6669 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6670 * but we don't support that).
6671 * Note: don't use the DAC post divider as it seems unstable.
6672 */
6673 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6674 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6675
6676 mdiv |= DPIO_ENABLE_CALIBRATION;
6677 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6678
6679 /* Set HBR and RBR LPF coefficients */
6680 if (pipe_config->port_clock == 162000 ||
6681 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6682 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6683 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6684 0x009f0003);
6685 else
6686 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6687 0x00d0000f);
6688
6689 if (intel_crtc_has_dp_encoder(pipe_config)) {
6690 /* Use SSC source */
6691 if (pipe == PIPE_A)
6692 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6693 0x0df40000);
6694 else
6695 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6696 0x0df70000);
6697 } else { /* HDMI or VGA */
6698 /* Use bend source */
6699 if (pipe == PIPE_A)
6700 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6701 0x0df70000);
6702 else
6703 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6704 0x0df40000);
6705 }
6706
6707 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6708 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6709 if (intel_crtc_has_dp_encoder(crtc->config))
6710 coreclk |= 0x01000000;
6711 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6712
6713 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6714 mutex_unlock(&dev_priv->sb_lock);
6715 }
6716
6717 static void chv_prepare_pll(struct intel_crtc *crtc,
6718 const struct intel_crtc_state *pipe_config)
6719 {
6720 struct drm_device *dev = crtc->base.dev;
6721 struct drm_i915_private *dev_priv = to_i915(dev);
6722 enum pipe pipe = crtc->pipe;
6723 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6724 u32 loopfilter, tribuf_calcntr;
6725 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6726 u32 dpio_val;
6727 int vco;
6728
6729 /* Enable Refclk and SSC */
6730 I915_WRITE(DPLL(pipe),
6731 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6732
6733 /* No need to actually set up the DPLL with DSI */
6734 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6735 return;
6736
6737 bestn = pipe_config->dpll.n;
6738 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6739 bestm1 = pipe_config->dpll.m1;
6740 bestm2 = pipe_config->dpll.m2 >> 22;
6741 bestp1 = pipe_config->dpll.p1;
6742 bestp2 = pipe_config->dpll.p2;
6743 vco = pipe_config->dpll.vco;
6744 dpio_val = 0;
6745 loopfilter = 0;
6746
6747 mutex_lock(&dev_priv->sb_lock);
6748
6749 /* p1 and p2 divider */
6750 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6751 5 << DPIO_CHV_S1_DIV_SHIFT |
6752 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6753 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6754 1 << DPIO_CHV_K_DIV_SHIFT);
6755
6756 /* Feedback post-divider - m2 */
6757 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6758
6759 /* Feedback refclk divider - n and m1 */
6760 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6761 DPIO_CHV_M1_DIV_BY_2 |
6762 1 << DPIO_CHV_N_DIV_SHIFT);
6763
6764 /* M2 fraction division */
6765 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6766
6767 /* M2 fraction division enable */
6768 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6769 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6770 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6771 if (bestm2_frac)
6772 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6773 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6774
6775 /* Program digital lock detect threshold */
6776 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6777 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6778 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6779 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6780 if (!bestm2_frac)
6781 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6782 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6783
6784 /* Loop filter */
6785 if (vco == 5400000) {
6786 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6787 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6788 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6789 tribuf_calcntr = 0x9;
6790 } else if (vco <= 6200000) {
6791 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6792 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6793 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6794 tribuf_calcntr = 0x9;
6795 } else if (vco <= 6480000) {
6796 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6797 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6798 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6799 tribuf_calcntr = 0x8;
6800 } else {
6801 /* Not supported. Apply the same limits as in the max case */
6802 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6803 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6804 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6805 tribuf_calcntr = 0;
6806 }
6807 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6808
6809 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6810 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6811 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6812 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6813
6814 /* AFC Recal */
6815 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6816 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6817 DPIO_AFC_RECAL);
6818
6819 mutex_unlock(&dev_priv->sb_lock);
6820 }
6821
6822 /**
6823 * vlv_force_pll_on - forcibly enable just the PLL
6824 * @dev_priv: i915 private structure
6825 * @pipe: pipe PLL to enable
6826 * @dpll: PLL configuration
6827 *
6828 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6829 * in cases where we need the PLL enabled even when @pipe is not going to
6830 * be enabled.
6831 */
6832 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6833 const struct dpll *dpll)
6834 {
6835 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6836 struct intel_crtc_state *pipe_config;
6837
6838 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6839 if (!pipe_config)
6840 return -ENOMEM;
6841
6842 pipe_config->base.crtc = &crtc->base;
6843 pipe_config->pixel_multiplier = 1;
6844 pipe_config->dpll = *dpll;
6845
6846 if (IS_CHERRYVIEW(dev_priv)) {
6847 chv_compute_dpll(crtc, pipe_config);
6848 chv_prepare_pll(crtc, pipe_config);
6849 chv_enable_pll(crtc, pipe_config);
6850 } else {
6851 vlv_compute_dpll(crtc, pipe_config);
6852 vlv_prepare_pll(crtc, pipe_config);
6853 vlv_enable_pll(crtc, pipe_config);
6854 }
6855
6856 kfree(pipe_config);
6857
6858 return 0;
6859 }
6860
6861 /**
6862 * vlv_force_pll_off - forcibly disable just the PLL
6863 * @dev_priv: i915 private structure
6864 * @pipe: pipe PLL to disable
6865 *
6866 * Disable the PLL for @pipe. To be used in cases where we need
6867 * the PLL enabled even when @pipe is not going to be enabled.
6868 */
6869 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6870 {
6871 if (IS_CHERRYVIEW(dev_priv))
6872 chv_disable_pll(dev_priv, pipe);
6873 else
6874 vlv_disable_pll(dev_priv, pipe);
6875 }
6876
6877 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6878 struct intel_crtc_state *crtc_state,
6879 struct dpll *reduced_clock)
6880 {
6881 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6882 u32 dpll;
6883 struct dpll *clock = &crtc_state->dpll;
6884
6885 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6886
6887 dpll = DPLL_VGA_MODE_DIS;
6888
6889 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6890 dpll |= DPLLB_MODE_LVDS;
6891 else
6892 dpll |= DPLLB_MODE_DAC_SERIAL;
6893
6894 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6895 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6896 dpll |= (crtc_state->pixel_multiplier - 1)
6897 << SDVO_MULTIPLIER_SHIFT_HIRES;
6898 }
6899
6900 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6901 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6902 dpll |= DPLL_SDVO_HIGH_SPEED;
6903
6904 if (intel_crtc_has_dp_encoder(crtc_state))
6905 dpll |= DPLL_SDVO_HIGH_SPEED;
6906
6907 /* compute bitmask from p1 value */
6908 if (IS_PINEVIEW(dev_priv))
6909 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6910 else {
6911 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6912 if (IS_G4X(dev_priv) && reduced_clock)
6913 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6914 }
6915 switch (clock->p2) {
6916 case 5:
6917 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6918 break;
6919 case 7:
6920 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6921 break;
6922 case 10:
6923 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6924 break;
6925 case 14:
6926 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6927 break;
6928 }
6929 if (INTEL_GEN(dev_priv) >= 4)
6930 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6931
6932 if (crtc_state->sdvo_tv_clock)
6933 dpll |= PLL_REF_INPUT_TVCLKINBC;
6934 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6935 intel_panel_use_ssc(dev_priv))
6936 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6937 else
6938 dpll |= PLL_REF_INPUT_DREFCLK;
6939
6940 dpll |= DPLL_VCO_ENABLE;
6941 crtc_state->dpll_hw_state.dpll = dpll;
6942
6943 if (INTEL_GEN(dev_priv) >= 4) {
6944 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6945 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6946 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6947 }
6948 }
6949
6950 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6951 struct intel_crtc_state *crtc_state,
6952 struct dpll *reduced_clock)
6953 {
6954 struct drm_device *dev = crtc->base.dev;
6955 struct drm_i915_private *dev_priv = to_i915(dev);
6956 u32 dpll;
6957 struct dpll *clock = &crtc_state->dpll;
6958
6959 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6960
6961 dpll = DPLL_VGA_MODE_DIS;
6962
6963 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6964 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6965 } else {
6966 if (clock->p1 == 2)
6967 dpll |= PLL_P1_DIVIDE_BY_TWO;
6968 else
6969 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6970 if (clock->p2 == 4)
6971 dpll |= PLL_P2_DIVIDE_BY_4;
6972 }
6973
6974 if (!IS_I830(dev_priv) &&
6975 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6976 dpll |= DPLL_DVO_2X_MODE;
6977
6978 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6979 intel_panel_use_ssc(dev_priv))
6980 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6981 else
6982 dpll |= PLL_REF_INPUT_DREFCLK;
6983
6984 dpll |= DPLL_VCO_ENABLE;
6985 crtc_state->dpll_hw_state.dpll = dpll;
6986 }
6987
6988 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6989 {
6990 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6991 enum pipe pipe = intel_crtc->pipe;
6992 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6993 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6994 uint32_t crtc_vtotal, crtc_vblank_end;
6995 int vsyncshift = 0;
6996
6997 /* We need to be careful not to changed the adjusted mode, for otherwise
6998 * the hw state checker will get angry at the mismatch. */
6999 crtc_vtotal = adjusted_mode->crtc_vtotal;
7000 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7001
7002 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7003 /* the chip adds 2 halflines automatically */
7004 crtc_vtotal -= 1;
7005 crtc_vblank_end -= 1;
7006
7007 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7008 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7009 else
7010 vsyncshift = adjusted_mode->crtc_hsync_start -
7011 adjusted_mode->crtc_htotal / 2;
7012 if (vsyncshift < 0)
7013 vsyncshift += adjusted_mode->crtc_htotal;
7014 }
7015
7016 if (INTEL_GEN(dev_priv) > 3)
7017 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7018
7019 I915_WRITE(HTOTAL(cpu_transcoder),
7020 (adjusted_mode->crtc_hdisplay - 1) |
7021 ((adjusted_mode->crtc_htotal - 1) << 16));
7022 I915_WRITE(HBLANK(cpu_transcoder),
7023 (adjusted_mode->crtc_hblank_start - 1) |
7024 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7025 I915_WRITE(HSYNC(cpu_transcoder),
7026 (adjusted_mode->crtc_hsync_start - 1) |
7027 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7028
7029 I915_WRITE(VTOTAL(cpu_transcoder),
7030 (adjusted_mode->crtc_vdisplay - 1) |
7031 ((crtc_vtotal - 1) << 16));
7032 I915_WRITE(VBLANK(cpu_transcoder),
7033 (adjusted_mode->crtc_vblank_start - 1) |
7034 ((crtc_vblank_end - 1) << 16));
7035 I915_WRITE(VSYNC(cpu_transcoder),
7036 (adjusted_mode->crtc_vsync_start - 1) |
7037 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7038
7039 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7040 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7041 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7042 * bits. */
7043 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7044 (pipe == PIPE_B || pipe == PIPE_C))
7045 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7046
7047 }
7048
7049 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7050 {
7051 struct drm_device *dev = intel_crtc->base.dev;
7052 struct drm_i915_private *dev_priv = to_i915(dev);
7053 enum pipe pipe = intel_crtc->pipe;
7054
7055 /* pipesrc controls the size that is scaled from, which should
7056 * always be the user's requested size.
7057 */
7058 I915_WRITE(PIPESRC(pipe),
7059 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7060 (intel_crtc->config->pipe_src_h - 1));
7061 }
7062
7063 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7064 struct intel_crtc_state *pipe_config)
7065 {
7066 struct drm_device *dev = crtc->base.dev;
7067 struct drm_i915_private *dev_priv = to_i915(dev);
7068 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7069 uint32_t tmp;
7070
7071 tmp = I915_READ(HTOTAL(cpu_transcoder));
7072 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7073 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7074 tmp = I915_READ(HBLANK(cpu_transcoder));
7075 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7076 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7077 tmp = I915_READ(HSYNC(cpu_transcoder));
7078 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7079 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7080
7081 tmp = I915_READ(VTOTAL(cpu_transcoder));
7082 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7083 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7084 tmp = I915_READ(VBLANK(cpu_transcoder));
7085 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7086 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7087 tmp = I915_READ(VSYNC(cpu_transcoder));
7088 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7089 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7090
7091 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7092 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7093 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7094 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7095 }
7096 }
7097
7098 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7099 struct intel_crtc_state *pipe_config)
7100 {
7101 struct drm_device *dev = crtc->base.dev;
7102 struct drm_i915_private *dev_priv = to_i915(dev);
7103 u32 tmp;
7104
7105 tmp = I915_READ(PIPESRC(crtc->pipe));
7106 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7107 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7108
7109 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7110 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7111 }
7112
7113 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7114 struct intel_crtc_state *pipe_config)
7115 {
7116 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7117 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7118 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7119 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7120
7121 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7122 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7123 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7124 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7125
7126 mode->flags = pipe_config->base.adjusted_mode.flags;
7127 mode->type = DRM_MODE_TYPE_DRIVER;
7128
7129 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7130
7131 mode->hsync = drm_mode_hsync(mode);
7132 mode->vrefresh = drm_mode_vrefresh(mode);
7133 drm_mode_set_name(mode);
7134 }
7135
7136 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7137 {
7138 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7139 uint32_t pipeconf;
7140
7141 pipeconf = 0;
7142
7143 /* we keep both pipes enabled on 830 */
7144 if (IS_I830(dev_priv))
7145 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7146
7147 if (intel_crtc->config->double_wide)
7148 pipeconf |= PIPECONF_DOUBLE_WIDE;
7149
7150 /* only g4x and later have fancy bpc/dither controls */
7151 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7152 IS_CHERRYVIEW(dev_priv)) {
7153 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7154 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7155 pipeconf |= PIPECONF_DITHER_EN |
7156 PIPECONF_DITHER_TYPE_SP;
7157
7158 switch (intel_crtc->config->pipe_bpp) {
7159 case 18:
7160 pipeconf |= PIPECONF_6BPC;
7161 break;
7162 case 24:
7163 pipeconf |= PIPECONF_8BPC;
7164 break;
7165 case 30:
7166 pipeconf |= PIPECONF_10BPC;
7167 break;
7168 default:
7169 /* Case prevented by intel_choose_pipe_bpp_dither. */
7170 BUG();
7171 }
7172 }
7173
7174 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7175 if (INTEL_GEN(dev_priv) < 4 ||
7176 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7177 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7178 else
7179 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7180 } else
7181 pipeconf |= PIPECONF_PROGRESSIVE;
7182
7183 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7184 intel_crtc->config->limited_color_range)
7185 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7186
7187 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7188 POSTING_READ(PIPECONF(intel_crtc->pipe));
7189 }
7190
7191 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7192 struct intel_crtc_state *crtc_state)
7193 {
7194 struct drm_device *dev = crtc->base.dev;
7195 struct drm_i915_private *dev_priv = to_i915(dev);
7196 const struct intel_limit *limit;
7197 int refclk = 48000;
7198
7199 memset(&crtc_state->dpll_hw_state, 0,
7200 sizeof(crtc_state->dpll_hw_state));
7201
7202 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7203 if (intel_panel_use_ssc(dev_priv)) {
7204 refclk = dev_priv->vbt.lvds_ssc_freq;
7205 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7206 }
7207
7208 limit = &intel_limits_i8xx_lvds;
7209 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7210 limit = &intel_limits_i8xx_dvo;
7211 } else {
7212 limit = &intel_limits_i8xx_dac;
7213 }
7214
7215 if (!crtc_state->clock_set &&
7216 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7217 refclk, NULL, &crtc_state->dpll)) {
7218 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7219 return -EINVAL;
7220 }
7221
7222 i8xx_compute_dpll(crtc, crtc_state, NULL);
7223
7224 return 0;
7225 }
7226
7227 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7228 struct intel_crtc_state *crtc_state)
7229 {
7230 struct drm_device *dev = crtc->base.dev;
7231 struct drm_i915_private *dev_priv = to_i915(dev);
7232 const struct intel_limit *limit;
7233 int refclk = 96000;
7234
7235 memset(&crtc_state->dpll_hw_state, 0,
7236 sizeof(crtc_state->dpll_hw_state));
7237
7238 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7239 if (intel_panel_use_ssc(dev_priv)) {
7240 refclk = dev_priv->vbt.lvds_ssc_freq;
7241 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7242 }
7243
7244 if (intel_is_dual_link_lvds(dev))
7245 limit = &intel_limits_g4x_dual_channel_lvds;
7246 else
7247 limit = &intel_limits_g4x_single_channel_lvds;
7248 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7249 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7250 limit = &intel_limits_g4x_hdmi;
7251 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7252 limit = &intel_limits_g4x_sdvo;
7253 } else {
7254 /* The option is for other outputs */
7255 limit = &intel_limits_i9xx_sdvo;
7256 }
7257
7258 if (!crtc_state->clock_set &&
7259 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7260 refclk, NULL, &crtc_state->dpll)) {
7261 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7262 return -EINVAL;
7263 }
7264
7265 i9xx_compute_dpll(crtc, crtc_state, NULL);
7266
7267 return 0;
7268 }
7269
7270 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7271 struct intel_crtc_state *crtc_state)
7272 {
7273 struct drm_device *dev = crtc->base.dev;
7274 struct drm_i915_private *dev_priv = to_i915(dev);
7275 const struct intel_limit *limit;
7276 int refclk = 96000;
7277
7278 memset(&crtc_state->dpll_hw_state, 0,
7279 sizeof(crtc_state->dpll_hw_state));
7280
7281 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7282 if (intel_panel_use_ssc(dev_priv)) {
7283 refclk = dev_priv->vbt.lvds_ssc_freq;
7284 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7285 }
7286
7287 limit = &intel_limits_pineview_lvds;
7288 } else {
7289 limit = &intel_limits_pineview_sdvo;
7290 }
7291
7292 if (!crtc_state->clock_set &&
7293 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7294 refclk, NULL, &crtc_state->dpll)) {
7295 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7296 return -EINVAL;
7297 }
7298
7299 i9xx_compute_dpll(crtc, crtc_state, NULL);
7300
7301 return 0;
7302 }
7303
7304 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7305 struct intel_crtc_state *crtc_state)
7306 {
7307 struct drm_device *dev = crtc->base.dev;
7308 struct drm_i915_private *dev_priv = to_i915(dev);
7309 const struct intel_limit *limit;
7310 int refclk = 96000;
7311
7312 memset(&crtc_state->dpll_hw_state, 0,
7313 sizeof(crtc_state->dpll_hw_state));
7314
7315 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7316 if (intel_panel_use_ssc(dev_priv)) {
7317 refclk = dev_priv->vbt.lvds_ssc_freq;
7318 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7319 }
7320
7321 limit = &intel_limits_i9xx_lvds;
7322 } else {
7323 limit = &intel_limits_i9xx_sdvo;
7324 }
7325
7326 if (!crtc_state->clock_set &&
7327 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7328 refclk, NULL, &crtc_state->dpll)) {
7329 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7330 return -EINVAL;
7331 }
7332
7333 i9xx_compute_dpll(crtc, crtc_state, NULL);
7334
7335 return 0;
7336 }
7337
7338 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7339 struct intel_crtc_state *crtc_state)
7340 {
7341 int refclk = 100000;
7342 const struct intel_limit *limit = &intel_limits_chv;
7343
7344 memset(&crtc_state->dpll_hw_state, 0,
7345 sizeof(crtc_state->dpll_hw_state));
7346
7347 if (!crtc_state->clock_set &&
7348 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7349 refclk, NULL, &crtc_state->dpll)) {
7350 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7351 return -EINVAL;
7352 }
7353
7354 chv_compute_dpll(crtc, crtc_state);
7355
7356 return 0;
7357 }
7358
7359 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7360 struct intel_crtc_state *crtc_state)
7361 {
7362 int refclk = 100000;
7363 const struct intel_limit *limit = &intel_limits_vlv;
7364
7365 memset(&crtc_state->dpll_hw_state, 0,
7366 sizeof(crtc_state->dpll_hw_state));
7367
7368 if (!crtc_state->clock_set &&
7369 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7370 refclk, NULL, &crtc_state->dpll)) {
7371 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7372 return -EINVAL;
7373 }
7374
7375 vlv_compute_dpll(crtc, crtc_state);
7376
7377 return 0;
7378 }
7379
7380 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7381 struct intel_crtc_state *pipe_config)
7382 {
7383 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7384 uint32_t tmp;
7385
7386 if (INTEL_GEN(dev_priv) <= 3 &&
7387 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7388 return;
7389
7390 tmp = I915_READ(PFIT_CONTROL);
7391 if (!(tmp & PFIT_ENABLE))
7392 return;
7393
7394 /* Check whether the pfit is attached to our pipe. */
7395 if (INTEL_GEN(dev_priv) < 4) {
7396 if (crtc->pipe != PIPE_B)
7397 return;
7398 } else {
7399 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7400 return;
7401 }
7402
7403 pipe_config->gmch_pfit.control = tmp;
7404 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7405 }
7406
7407 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7408 struct intel_crtc_state *pipe_config)
7409 {
7410 struct drm_device *dev = crtc->base.dev;
7411 struct drm_i915_private *dev_priv = to_i915(dev);
7412 int pipe = pipe_config->cpu_transcoder;
7413 struct dpll clock;
7414 u32 mdiv;
7415 int refclk = 100000;
7416
7417 /* In case of DSI, DPLL will not be used */
7418 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7419 return;
7420
7421 mutex_lock(&dev_priv->sb_lock);
7422 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7423 mutex_unlock(&dev_priv->sb_lock);
7424
7425 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7426 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7427 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7428 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7429 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7430
7431 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7432 }
7433
7434 static void
7435 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7436 struct intel_initial_plane_config *plane_config)
7437 {
7438 struct drm_device *dev = crtc->base.dev;
7439 struct drm_i915_private *dev_priv = to_i915(dev);
7440 u32 val, base, offset;
7441 int pipe = crtc->pipe, plane = crtc->plane;
7442 int fourcc, pixel_format;
7443 unsigned int aligned_height;
7444 struct drm_framebuffer *fb;
7445 struct intel_framebuffer *intel_fb;
7446
7447 val = I915_READ(DSPCNTR(plane));
7448 if (!(val & DISPLAY_PLANE_ENABLE))
7449 return;
7450
7451 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7452 if (!intel_fb) {
7453 DRM_DEBUG_KMS("failed to alloc fb\n");
7454 return;
7455 }
7456
7457 fb = &intel_fb->base;
7458
7459 fb->dev = dev;
7460
7461 if (INTEL_GEN(dev_priv) >= 4) {
7462 if (val & DISPPLANE_TILED) {
7463 plane_config->tiling = I915_TILING_X;
7464 fb->modifier = I915_FORMAT_MOD_X_TILED;
7465 }
7466 }
7467
7468 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7469 fourcc = i9xx_format_to_fourcc(pixel_format);
7470 fb->format = drm_format_info(fourcc);
7471
7472 if (INTEL_GEN(dev_priv) >= 4) {
7473 if (plane_config->tiling)
7474 offset = I915_READ(DSPTILEOFF(plane));
7475 else
7476 offset = I915_READ(DSPLINOFF(plane));
7477 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7478 } else {
7479 base = I915_READ(DSPADDR(plane));
7480 }
7481 plane_config->base = base;
7482
7483 val = I915_READ(PIPESRC(pipe));
7484 fb->width = ((val >> 16) & 0xfff) + 1;
7485 fb->height = ((val >> 0) & 0xfff) + 1;
7486
7487 val = I915_READ(DSPSTRIDE(pipe));
7488 fb->pitches[0] = val & 0xffffffc0;
7489
7490 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7491
7492 plane_config->size = fb->pitches[0] * aligned_height;
7493
7494 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7495 pipe_name(pipe), plane, fb->width, fb->height,
7496 fb->format->cpp[0] * 8, base, fb->pitches[0],
7497 plane_config->size);
7498
7499 plane_config->fb = intel_fb;
7500 }
7501
7502 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7503 struct intel_crtc_state *pipe_config)
7504 {
7505 struct drm_device *dev = crtc->base.dev;
7506 struct drm_i915_private *dev_priv = to_i915(dev);
7507 int pipe = pipe_config->cpu_transcoder;
7508 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7509 struct dpll clock;
7510 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7511 int refclk = 100000;
7512
7513 /* In case of DSI, DPLL will not be used */
7514 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7515 return;
7516
7517 mutex_lock(&dev_priv->sb_lock);
7518 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7519 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7520 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7521 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7522 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7523 mutex_unlock(&dev_priv->sb_lock);
7524
7525 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7526 clock.m2 = (pll_dw0 & 0xff) << 22;
7527 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7528 clock.m2 |= pll_dw2 & 0x3fffff;
7529 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7530 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7531 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7532
7533 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7534 }
7535
7536 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7537 struct intel_crtc_state *pipe_config)
7538 {
7539 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7540 enum intel_display_power_domain power_domain;
7541 uint32_t tmp;
7542 bool ret;
7543
7544 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7545 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7546 return false;
7547
7548 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7549 pipe_config->shared_dpll = NULL;
7550
7551 ret = false;
7552
7553 tmp = I915_READ(PIPECONF(crtc->pipe));
7554 if (!(tmp & PIPECONF_ENABLE))
7555 goto out;
7556
7557 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7558 IS_CHERRYVIEW(dev_priv)) {
7559 switch (tmp & PIPECONF_BPC_MASK) {
7560 case PIPECONF_6BPC:
7561 pipe_config->pipe_bpp = 18;
7562 break;
7563 case PIPECONF_8BPC:
7564 pipe_config->pipe_bpp = 24;
7565 break;
7566 case PIPECONF_10BPC:
7567 pipe_config->pipe_bpp = 30;
7568 break;
7569 default:
7570 break;
7571 }
7572 }
7573
7574 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7575 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7576 pipe_config->limited_color_range = true;
7577
7578 if (INTEL_GEN(dev_priv) < 4)
7579 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7580
7581 intel_get_pipe_timings(crtc, pipe_config);
7582 intel_get_pipe_src_size(crtc, pipe_config);
7583
7584 i9xx_get_pfit_config(crtc, pipe_config);
7585
7586 if (INTEL_GEN(dev_priv) >= 4) {
7587 /* No way to read it out on pipes B and C */
7588 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7589 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7590 else
7591 tmp = I915_READ(DPLL_MD(crtc->pipe));
7592 pipe_config->pixel_multiplier =
7593 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7594 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7595 pipe_config->dpll_hw_state.dpll_md = tmp;
7596 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7597 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7598 tmp = I915_READ(DPLL(crtc->pipe));
7599 pipe_config->pixel_multiplier =
7600 ((tmp & SDVO_MULTIPLIER_MASK)
7601 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7602 } else {
7603 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7604 * port and will be fixed up in the encoder->get_config
7605 * function. */
7606 pipe_config->pixel_multiplier = 1;
7607 }
7608 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7609 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7610 /*
7611 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7612 * on 830. Filter it out here so that we don't
7613 * report errors due to that.
7614 */
7615 if (IS_I830(dev_priv))
7616 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7617
7618 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7619 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7620 } else {
7621 /* Mask out read-only status bits. */
7622 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7623 DPLL_PORTC_READY_MASK |
7624 DPLL_PORTB_READY_MASK);
7625 }
7626
7627 if (IS_CHERRYVIEW(dev_priv))
7628 chv_crtc_clock_get(crtc, pipe_config);
7629 else if (IS_VALLEYVIEW(dev_priv))
7630 vlv_crtc_clock_get(crtc, pipe_config);
7631 else
7632 i9xx_crtc_clock_get(crtc, pipe_config);
7633
7634 /*
7635 * Normally the dotclock is filled in by the encoder .get_config()
7636 * but in case the pipe is enabled w/o any ports we need a sane
7637 * default.
7638 */
7639 pipe_config->base.adjusted_mode.crtc_clock =
7640 pipe_config->port_clock / pipe_config->pixel_multiplier;
7641
7642 ret = true;
7643
7644 out:
7645 intel_display_power_put(dev_priv, power_domain);
7646
7647 return ret;
7648 }
7649
7650 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7651 {
7652 struct intel_encoder *encoder;
7653 int i;
7654 u32 val, final;
7655 bool has_lvds = false;
7656 bool has_cpu_edp = false;
7657 bool has_panel = false;
7658 bool has_ck505 = false;
7659 bool can_ssc = false;
7660 bool using_ssc_source = false;
7661
7662 /* We need to take the global config into account */
7663 for_each_intel_encoder(&dev_priv->drm, encoder) {
7664 switch (encoder->type) {
7665 case INTEL_OUTPUT_LVDS:
7666 has_panel = true;
7667 has_lvds = true;
7668 break;
7669 case INTEL_OUTPUT_EDP:
7670 has_panel = true;
7671 if (encoder->port == PORT_A)
7672 has_cpu_edp = true;
7673 break;
7674 default:
7675 break;
7676 }
7677 }
7678
7679 if (HAS_PCH_IBX(dev_priv)) {
7680 has_ck505 = dev_priv->vbt.display_clock_mode;
7681 can_ssc = has_ck505;
7682 } else {
7683 has_ck505 = false;
7684 can_ssc = true;
7685 }
7686
7687 /* Check if any DPLLs are using the SSC source */
7688 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7689 u32 temp = I915_READ(PCH_DPLL(i));
7690
7691 if (!(temp & DPLL_VCO_ENABLE))
7692 continue;
7693
7694 if ((temp & PLL_REF_INPUT_MASK) ==
7695 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7696 using_ssc_source = true;
7697 break;
7698 }
7699 }
7700
7701 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7702 has_panel, has_lvds, has_ck505, using_ssc_source);
7703
7704 /* Ironlake: try to setup display ref clock before DPLL
7705 * enabling. This is only under driver's control after
7706 * PCH B stepping, previous chipset stepping should be
7707 * ignoring this setting.
7708 */
7709 val = I915_READ(PCH_DREF_CONTROL);
7710
7711 /* As we must carefully and slowly disable/enable each source in turn,
7712 * compute the final state we want first and check if we need to
7713 * make any changes at all.
7714 */
7715 final = val;
7716 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7717 if (has_ck505)
7718 final |= DREF_NONSPREAD_CK505_ENABLE;
7719 else
7720 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7721
7722 final &= ~DREF_SSC_SOURCE_MASK;
7723 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7724 final &= ~DREF_SSC1_ENABLE;
7725
7726 if (has_panel) {
7727 final |= DREF_SSC_SOURCE_ENABLE;
7728
7729 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7730 final |= DREF_SSC1_ENABLE;
7731
7732 if (has_cpu_edp) {
7733 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7734 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7735 else
7736 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7737 } else
7738 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7739 } else if (using_ssc_source) {
7740 final |= DREF_SSC_SOURCE_ENABLE;
7741 final |= DREF_SSC1_ENABLE;
7742 }
7743
7744 if (final == val)
7745 return;
7746
7747 /* Always enable nonspread source */
7748 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7749
7750 if (has_ck505)
7751 val |= DREF_NONSPREAD_CK505_ENABLE;
7752 else
7753 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7754
7755 if (has_panel) {
7756 val &= ~DREF_SSC_SOURCE_MASK;
7757 val |= DREF_SSC_SOURCE_ENABLE;
7758
7759 /* SSC must be turned on before enabling the CPU output */
7760 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7761 DRM_DEBUG_KMS("Using SSC on panel\n");
7762 val |= DREF_SSC1_ENABLE;
7763 } else
7764 val &= ~DREF_SSC1_ENABLE;
7765
7766 /* Get SSC going before enabling the outputs */
7767 I915_WRITE(PCH_DREF_CONTROL, val);
7768 POSTING_READ(PCH_DREF_CONTROL);
7769 udelay(200);
7770
7771 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7772
7773 /* Enable CPU source on CPU attached eDP */
7774 if (has_cpu_edp) {
7775 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7776 DRM_DEBUG_KMS("Using SSC on eDP\n");
7777 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7778 } else
7779 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7780 } else
7781 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7782
7783 I915_WRITE(PCH_DREF_CONTROL, val);
7784 POSTING_READ(PCH_DREF_CONTROL);
7785 udelay(200);
7786 } else {
7787 DRM_DEBUG_KMS("Disabling CPU source output\n");
7788
7789 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7790
7791 /* Turn off CPU output */
7792 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7793
7794 I915_WRITE(PCH_DREF_CONTROL, val);
7795 POSTING_READ(PCH_DREF_CONTROL);
7796 udelay(200);
7797
7798 if (!using_ssc_source) {
7799 DRM_DEBUG_KMS("Disabling SSC source\n");
7800
7801 /* Turn off the SSC source */
7802 val &= ~DREF_SSC_SOURCE_MASK;
7803 val |= DREF_SSC_SOURCE_DISABLE;
7804
7805 /* Turn off SSC1 */
7806 val &= ~DREF_SSC1_ENABLE;
7807
7808 I915_WRITE(PCH_DREF_CONTROL, val);
7809 POSTING_READ(PCH_DREF_CONTROL);
7810 udelay(200);
7811 }
7812 }
7813
7814 BUG_ON(val != final);
7815 }
7816
7817 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7818 {
7819 uint32_t tmp;
7820
7821 tmp = I915_READ(SOUTH_CHICKEN2);
7822 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7823 I915_WRITE(SOUTH_CHICKEN2, tmp);
7824
7825 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7826 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7827 DRM_ERROR("FDI mPHY reset assert timeout\n");
7828
7829 tmp = I915_READ(SOUTH_CHICKEN2);
7830 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7831 I915_WRITE(SOUTH_CHICKEN2, tmp);
7832
7833 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7834 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7835 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7836 }
7837
7838 /* WaMPhyProgramming:hsw */
7839 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7840 {
7841 uint32_t tmp;
7842
7843 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7844 tmp &= ~(0xFF << 24);
7845 tmp |= (0x12 << 24);
7846 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7847
7848 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7849 tmp |= (1 << 11);
7850 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7851
7852 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7853 tmp |= (1 << 11);
7854 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7855
7856 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7857 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7858 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7859
7860 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7861 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7862 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7863
7864 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7865 tmp &= ~(7 << 13);
7866 tmp |= (5 << 13);
7867 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7868
7869 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7870 tmp &= ~(7 << 13);
7871 tmp |= (5 << 13);
7872 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7873
7874 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7875 tmp &= ~0xFF;
7876 tmp |= 0x1C;
7877 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7878
7879 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7880 tmp &= ~0xFF;
7881 tmp |= 0x1C;
7882 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7883
7884 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7885 tmp &= ~(0xFF << 16);
7886 tmp |= (0x1C << 16);
7887 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7888
7889 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7890 tmp &= ~(0xFF << 16);
7891 tmp |= (0x1C << 16);
7892 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7893
7894 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7895 tmp |= (1 << 27);
7896 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7897
7898 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7899 tmp |= (1 << 27);
7900 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7901
7902 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7903 tmp &= ~(0xF << 28);
7904 tmp |= (4 << 28);
7905 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7906
7907 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7908 tmp &= ~(0xF << 28);
7909 tmp |= (4 << 28);
7910 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7911 }
7912
7913 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7914 * Programming" based on the parameters passed:
7915 * - Sequence to enable CLKOUT_DP
7916 * - Sequence to enable CLKOUT_DP without spread
7917 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7918 */
7919 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7920 bool with_spread, bool with_fdi)
7921 {
7922 uint32_t reg, tmp;
7923
7924 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7925 with_spread = true;
7926 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7927 with_fdi, "LP PCH doesn't have FDI\n"))
7928 with_fdi = false;
7929
7930 mutex_lock(&dev_priv->sb_lock);
7931
7932 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7933 tmp &= ~SBI_SSCCTL_DISABLE;
7934 tmp |= SBI_SSCCTL_PATHALT;
7935 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7936
7937 udelay(24);
7938
7939 if (with_spread) {
7940 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7941 tmp &= ~SBI_SSCCTL_PATHALT;
7942 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7943
7944 if (with_fdi) {
7945 lpt_reset_fdi_mphy(dev_priv);
7946 lpt_program_fdi_mphy(dev_priv);
7947 }
7948 }
7949
7950 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7951 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7952 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7953 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7954
7955 mutex_unlock(&dev_priv->sb_lock);
7956 }
7957
7958 /* Sequence to disable CLKOUT_DP */
7959 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7960 {
7961 uint32_t reg, tmp;
7962
7963 mutex_lock(&dev_priv->sb_lock);
7964
7965 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7966 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7967 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7968 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7969
7970 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7971 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7972 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7973 tmp |= SBI_SSCCTL_PATHALT;
7974 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7975 udelay(32);
7976 }
7977 tmp |= SBI_SSCCTL_DISABLE;
7978 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7979 }
7980
7981 mutex_unlock(&dev_priv->sb_lock);
7982 }
7983
7984 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7985
7986 static const uint16_t sscdivintphase[] = {
7987 [BEND_IDX( 50)] = 0x3B23,
7988 [BEND_IDX( 45)] = 0x3B23,
7989 [BEND_IDX( 40)] = 0x3C23,
7990 [BEND_IDX( 35)] = 0x3C23,
7991 [BEND_IDX( 30)] = 0x3D23,
7992 [BEND_IDX( 25)] = 0x3D23,
7993 [BEND_IDX( 20)] = 0x3E23,
7994 [BEND_IDX( 15)] = 0x3E23,
7995 [BEND_IDX( 10)] = 0x3F23,
7996 [BEND_IDX( 5)] = 0x3F23,
7997 [BEND_IDX( 0)] = 0x0025,
7998 [BEND_IDX( -5)] = 0x0025,
7999 [BEND_IDX(-10)] = 0x0125,
8000 [BEND_IDX(-15)] = 0x0125,
8001 [BEND_IDX(-20)] = 0x0225,
8002 [BEND_IDX(-25)] = 0x0225,
8003 [BEND_IDX(-30)] = 0x0325,
8004 [BEND_IDX(-35)] = 0x0325,
8005 [BEND_IDX(-40)] = 0x0425,
8006 [BEND_IDX(-45)] = 0x0425,
8007 [BEND_IDX(-50)] = 0x0525,
8008 };
8009
8010 /*
8011 * Bend CLKOUT_DP
8012 * steps -50 to 50 inclusive, in steps of 5
8013 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8014 * change in clock period = -(steps / 10) * 5.787 ps
8015 */
8016 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8017 {
8018 uint32_t tmp;
8019 int idx = BEND_IDX(steps);
8020
8021 if (WARN_ON(steps % 5 != 0))
8022 return;
8023
8024 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8025 return;
8026
8027 mutex_lock(&dev_priv->sb_lock);
8028
8029 if (steps % 10 != 0)
8030 tmp = 0xAAAAAAAB;
8031 else
8032 tmp = 0x00000000;
8033 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8034
8035 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8036 tmp &= 0xffff0000;
8037 tmp |= sscdivintphase[idx];
8038 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8039
8040 mutex_unlock(&dev_priv->sb_lock);
8041 }
8042
8043 #undef BEND_IDX
8044
8045 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8046 {
8047 struct intel_encoder *encoder;
8048 bool has_vga = false;
8049
8050 for_each_intel_encoder(&dev_priv->drm, encoder) {
8051 switch (encoder->type) {
8052 case INTEL_OUTPUT_ANALOG:
8053 has_vga = true;
8054 break;
8055 default:
8056 break;
8057 }
8058 }
8059
8060 if (has_vga) {
8061 lpt_bend_clkout_dp(dev_priv, 0);
8062 lpt_enable_clkout_dp(dev_priv, true, true);
8063 } else {
8064 lpt_disable_clkout_dp(dev_priv);
8065 }
8066 }
8067
8068 /*
8069 * Initialize reference clocks when the driver loads
8070 */
8071 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8072 {
8073 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8074 ironlake_init_pch_refclk(dev_priv);
8075 else if (HAS_PCH_LPT(dev_priv))
8076 lpt_init_pch_refclk(dev_priv);
8077 }
8078
8079 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8080 {
8081 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8083 int pipe = intel_crtc->pipe;
8084 uint32_t val;
8085
8086 val = 0;
8087
8088 switch (intel_crtc->config->pipe_bpp) {
8089 case 18:
8090 val |= PIPECONF_6BPC;
8091 break;
8092 case 24:
8093 val |= PIPECONF_8BPC;
8094 break;
8095 case 30:
8096 val |= PIPECONF_10BPC;
8097 break;
8098 case 36:
8099 val |= PIPECONF_12BPC;
8100 break;
8101 default:
8102 /* Case prevented by intel_choose_pipe_bpp_dither. */
8103 BUG();
8104 }
8105
8106 if (intel_crtc->config->dither)
8107 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8108
8109 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8110 val |= PIPECONF_INTERLACED_ILK;
8111 else
8112 val |= PIPECONF_PROGRESSIVE;
8113
8114 if (intel_crtc->config->limited_color_range)
8115 val |= PIPECONF_COLOR_RANGE_SELECT;
8116
8117 I915_WRITE(PIPECONF(pipe), val);
8118 POSTING_READ(PIPECONF(pipe));
8119 }
8120
8121 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8122 {
8123 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8125 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8126 u32 val = 0;
8127
8128 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8129 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8130
8131 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8132 val |= PIPECONF_INTERLACED_ILK;
8133 else
8134 val |= PIPECONF_PROGRESSIVE;
8135
8136 I915_WRITE(PIPECONF(cpu_transcoder), val);
8137 POSTING_READ(PIPECONF(cpu_transcoder));
8138 }
8139
8140 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8141 {
8142 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8144 struct intel_crtc_state *config = intel_crtc->config;
8145
8146 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8147 u32 val = 0;
8148
8149 switch (intel_crtc->config->pipe_bpp) {
8150 case 18:
8151 val |= PIPEMISC_DITHER_6_BPC;
8152 break;
8153 case 24:
8154 val |= PIPEMISC_DITHER_8_BPC;
8155 break;
8156 case 30:
8157 val |= PIPEMISC_DITHER_10_BPC;
8158 break;
8159 case 36:
8160 val |= PIPEMISC_DITHER_12_BPC;
8161 break;
8162 default:
8163 /* Case prevented by pipe_config_set_bpp. */
8164 BUG();
8165 }
8166
8167 if (intel_crtc->config->dither)
8168 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8169
8170 if (config->ycbcr420) {
8171 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8172 PIPEMISC_YUV420_ENABLE |
8173 PIPEMISC_YUV420_MODE_FULL_BLEND;
8174 }
8175
8176 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8177 }
8178 }
8179
8180 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8181 {
8182 /*
8183 * Account for spread spectrum to avoid
8184 * oversubscribing the link. Max center spread
8185 * is 2.5%; use 5% for safety's sake.
8186 */
8187 u32 bps = target_clock * bpp * 21 / 20;
8188 return DIV_ROUND_UP(bps, link_bw * 8);
8189 }
8190
8191 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8192 {
8193 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8194 }
8195
8196 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8197 struct intel_crtc_state *crtc_state,
8198 struct dpll *reduced_clock)
8199 {
8200 struct drm_crtc *crtc = &intel_crtc->base;
8201 struct drm_device *dev = crtc->dev;
8202 struct drm_i915_private *dev_priv = to_i915(dev);
8203 u32 dpll, fp, fp2;
8204 int factor;
8205
8206 /* Enable autotuning of the PLL clock (if permissible) */
8207 factor = 21;
8208 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8209 if ((intel_panel_use_ssc(dev_priv) &&
8210 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8211 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8212 factor = 25;
8213 } else if (crtc_state->sdvo_tv_clock)
8214 factor = 20;
8215
8216 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8217
8218 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8219 fp |= FP_CB_TUNE;
8220
8221 if (reduced_clock) {
8222 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8223
8224 if (reduced_clock->m < factor * reduced_clock->n)
8225 fp2 |= FP_CB_TUNE;
8226 } else {
8227 fp2 = fp;
8228 }
8229
8230 dpll = 0;
8231
8232 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8233 dpll |= DPLLB_MODE_LVDS;
8234 else
8235 dpll |= DPLLB_MODE_DAC_SERIAL;
8236
8237 dpll |= (crtc_state->pixel_multiplier - 1)
8238 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8239
8240 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8241 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8242 dpll |= DPLL_SDVO_HIGH_SPEED;
8243
8244 if (intel_crtc_has_dp_encoder(crtc_state))
8245 dpll |= DPLL_SDVO_HIGH_SPEED;
8246
8247 /*
8248 * The high speed IO clock is only really required for
8249 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8250 * possible to share the DPLL between CRT and HDMI. Enabling
8251 * the clock needlessly does no real harm, except use up a
8252 * bit of power potentially.
8253 *
8254 * We'll limit this to IVB with 3 pipes, since it has only two
8255 * DPLLs and so DPLL sharing is the only way to get three pipes
8256 * driving PCH ports at the same time. On SNB we could do this,
8257 * and potentially avoid enabling the second DPLL, but it's not
8258 * clear if it''s a win or loss power wise. No point in doing
8259 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8260 */
8261 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8262 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8263 dpll |= DPLL_SDVO_HIGH_SPEED;
8264
8265 /* compute bitmask from p1 value */
8266 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8267 /* also FPA1 */
8268 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8269
8270 switch (crtc_state->dpll.p2) {
8271 case 5:
8272 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8273 break;
8274 case 7:
8275 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8276 break;
8277 case 10:
8278 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8279 break;
8280 case 14:
8281 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8282 break;
8283 }
8284
8285 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8286 intel_panel_use_ssc(dev_priv))
8287 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8288 else
8289 dpll |= PLL_REF_INPUT_DREFCLK;
8290
8291 dpll |= DPLL_VCO_ENABLE;
8292
8293 crtc_state->dpll_hw_state.dpll = dpll;
8294 crtc_state->dpll_hw_state.fp0 = fp;
8295 crtc_state->dpll_hw_state.fp1 = fp2;
8296 }
8297
8298 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8299 struct intel_crtc_state *crtc_state)
8300 {
8301 struct drm_device *dev = crtc->base.dev;
8302 struct drm_i915_private *dev_priv = to_i915(dev);
8303 const struct intel_limit *limit;
8304 int refclk = 120000;
8305
8306 memset(&crtc_state->dpll_hw_state, 0,
8307 sizeof(crtc_state->dpll_hw_state));
8308
8309 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8310 if (!crtc_state->has_pch_encoder)
8311 return 0;
8312
8313 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8314 if (intel_panel_use_ssc(dev_priv)) {
8315 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8316 dev_priv->vbt.lvds_ssc_freq);
8317 refclk = dev_priv->vbt.lvds_ssc_freq;
8318 }
8319
8320 if (intel_is_dual_link_lvds(dev)) {
8321 if (refclk == 100000)
8322 limit = &intel_limits_ironlake_dual_lvds_100m;
8323 else
8324 limit = &intel_limits_ironlake_dual_lvds;
8325 } else {
8326 if (refclk == 100000)
8327 limit = &intel_limits_ironlake_single_lvds_100m;
8328 else
8329 limit = &intel_limits_ironlake_single_lvds;
8330 }
8331 } else {
8332 limit = &intel_limits_ironlake_dac;
8333 }
8334
8335 if (!crtc_state->clock_set &&
8336 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8337 refclk, NULL, &crtc_state->dpll)) {
8338 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8339 return -EINVAL;
8340 }
8341
8342 ironlake_compute_dpll(crtc, crtc_state, NULL);
8343
8344 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8345 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8346 pipe_name(crtc->pipe));
8347 return -EINVAL;
8348 }
8349
8350 return 0;
8351 }
8352
8353 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8354 struct intel_link_m_n *m_n)
8355 {
8356 struct drm_device *dev = crtc->base.dev;
8357 struct drm_i915_private *dev_priv = to_i915(dev);
8358 enum pipe pipe = crtc->pipe;
8359
8360 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8361 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8362 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8363 & ~TU_SIZE_MASK;
8364 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8365 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8366 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8367 }
8368
8369 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8370 enum transcoder transcoder,
8371 struct intel_link_m_n *m_n,
8372 struct intel_link_m_n *m2_n2)
8373 {
8374 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8375 enum pipe pipe = crtc->pipe;
8376
8377 if (INTEL_GEN(dev_priv) >= 5) {
8378 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8379 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8380 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8381 & ~TU_SIZE_MASK;
8382 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8383 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8384 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8385 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8386 * gen < 8) and if DRRS is supported (to make sure the
8387 * registers are not unnecessarily read).
8388 */
8389 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8390 crtc->config->has_drrs) {
8391 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8392 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8393 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8394 & ~TU_SIZE_MASK;
8395 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8396 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8397 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8398 }
8399 } else {
8400 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8401 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8402 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8403 & ~TU_SIZE_MASK;
8404 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8405 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8406 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8407 }
8408 }
8409
8410 void intel_dp_get_m_n(struct intel_crtc *crtc,
8411 struct intel_crtc_state *pipe_config)
8412 {
8413 if (pipe_config->has_pch_encoder)
8414 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8415 else
8416 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8417 &pipe_config->dp_m_n,
8418 &pipe_config->dp_m2_n2);
8419 }
8420
8421 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8422 struct intel_crtc_state *pipe_config)
8423 {
8424 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8425 &pipe_config->fdi_m_n, NULL);
8426 }
8427
8428 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8429 struct intel_crtc_state *pipe_config)
8430 {
8431 struct drm_device *dev = crtc->base.dev;
8432 struct drm_i915_private *dev_priv = to_i915(dev);
8433 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8434 uint32_t ps_ctrl = 0;
8435 int id = -1;
8436 int i;
8437
8438 /* find scaler attached to this pipe */
8439 for (i = 0; i < crtc->num_scalers; i++) {
8440 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8441 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8442 id = i;
8443 pipe_config->pch_pfit.enabled = true;
8444 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8445 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8446 break;
8447 }
8448 }
8449
8450 scaler_state->scaler_id = id;
8451 if (id >= 0) {
8452 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8453 } else {
8454 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8455 }
8456 }
8457
8458 static void
8459 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8460 struct intel_initial_plane_config *plane_config)
8461 {
8462 struct drm_device *dev = crtc->base.dev;
8463 struct drm_i915_private *dev_priv = to_i915(dev);
8464 u32 val, base, offset, stride_mult, tiling, alpha;
8465 int pipe = crtc->pipe;
8466 int fourcc, pixel_format;
8467 unsigned int aligned_height;
8468 struct drm_framebuffer *fb;
8469 struct intel_framebuffer *intel_fb;
8470
8471 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8472 if (!intel_fb) {
8473 DRM_DEBUG_KMS("failed to alloc fb\n");
8474 return;
8475 }
8476
8477 fb = &intel_fb->base;
8478
8479 fb->dev = dev;
8480
8481 val = I915_READ(PLANE_CTL(pipe, 0));
8482 if (!(val & PLANE_CTL_ENABLE))
8483 goto error;
8484
8485 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8486
8487 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8488 alpha = I915_READ(PLANE_COLOR_CTL(pipe, 0));
8489 alpha &= PLANE_COLOR_ALPHA_MASK;
8490 } else {
8491 alpha = val & PLANE_CTL_ALPHA_MASK;
8492 }
8493
8494 fourcc = skl_format_to_fourcc(pixel_format,
8495 val & PLANE_CTL_ORDER_RGBX, alpha);
8496 fb->format = drm_format_info(fourcc);
8497
8498 tiling = val & PLANE_CTL_TILED_MASK;
8499 switch (tiling) {
8500 case PLANE_CTL_TILED_LINEAR:
8501 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8502 break;
8503 case PLANE_CTL_TILED_X:
8504 plane_config->tiling = I915_TILING_X;
8505 fb->modifier = I915_FORMAT_MOD_X_TILED;
8506 break;
8507 case PLANE_CTL_TILED_Y:
8508 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8509 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8510 else
8511 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8512 break;
8513 case PLANE_CTL_TILED_YF:
8514 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8515 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8516 else
8517 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8518 break;
8519 default:
8520 MISSING_CASE(tiling);
8521 goto error;
8522 }
8523
8524 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8525 plane_config->base = base;
8526
8527 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8528
8529 val = I915_READ(PLANE_SIZE(pipe, 0));
8530 fb->height = ((val >> 16) & 0xfff) + 1;
8531 fb->width = ((val >> 0) & 0x1fff) + 1;
8532
8533 val = I915_READ(PLANE_STRIDE(pipe, 0));
8534 stride_mult = intel_fb_stride_alignment(fb, 0);
8535 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8536
8537 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8538
8539 plane_config->size = fb->pitches[0] * aligned_height;
8540
8541 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8542 pipe_name(pipe), fb->width, fb->height,
8543 fb->format->cpp[0] * 8, base, fb->pitches[0],
8544 plane_config->size);
8545
8546 plane_config->fb = intel_fb;
8547 return;
8548
8549 error:
8550 kfree(intel_fb);
8551 }
8552
8553 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8554 struct intel_crtc_state *pipe_config)
8555 {
8556 struct drm_device *dev = crtc->base.dev;
8557 struct drm_i915_private *dev_priv = to_i915(dev);
8558 uint32_t tmp;
8559
8560 tmp = I915_READ(PF_CTL(crtc->pipe));
8561
8562 if (tmp & PF_ENABLE) {
8563 pipe_config->pch_pfit.enabled = true;
8564 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8565 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8566
8567 /* We currently do not free assignements of panel fitters on
8568 * ivb/hsw (since we don't use the higher upscaling modes which
8569 * differentiates them) so just WARN about this case for now. */
8570 if (IS_GEN7(dev_priv)) {
8571 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8572 PF_PIPE_SEL_IVB(crtc->pipe));
8573 }
8574 }
8575 }
8576
8577 static void
8578 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8579 struct intel_initial_plane_config *plane_config)
8580 {
8581 struct drm_device *dev = crtc->base.dev;
8582 struct drm_i915_private *dev_priv = to_i915(dev);
8583 u32 val, base, offset;
8584 int pipe = crtc->pipe;
8585 int fourcc, pixel_format;
8586 unsigned int aligned_height;
8587 struct drm_framebuffer *fb;
8588 struct intel_framebuffer *intel_fb;
8589
8590 val = I915_READ(DSPCNTR(pipe));
8591 if (!(val & DISPLAY_PLANE_ENABLE))
8592 return;
8593
8594 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8595 if (!intel_fb) {
8596 DRM_DEBUG_KMS("failed to alloc fb\n");
8597 return;
8598 }
8599
8600 fb = &intel_fb->base;
8601
8602 fb->dev = dev;
8603
8604 if (INTEL_GEN(dev_priv) >= 4) {
8605 if (val & DISPPLANE_TILED) {
8606 plane_config->tiling = I915_TILING_X;
8607 fb->modifier = I915_FORMAT_MOD_X_TILED;
8608 }
8609 }
8610
8611 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8612 fourcc = i9xx_format_to_fourcc(pixel_format);
8613 fb->format = drm_format_info(fourcc);
8614
8615 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8616 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8617 offset = I915_READ(DSPOFFSET(pipe));
8618 } else {
8619 if (plane_config->tiling)
8620 offset = I915_READ(DSPTILEOFF(pipe));
8621 else
8622 offset = I915_READ(DSPLINOFF(pipe));
8623 }
8624 plane_config->base = base;
8625
8626 val = I915_READ(PIPESRC(pipe));
8627 fb->width = ((val >> 16) & 0xfff) + 1;
8628 fb->height = ((val >> 0) & 0xfff) + 1;
8629
8630 val = I915_READ(DSPSTRIDE(pipe));
8631 fb->pitches[0] = val & 0xffffffc0;
8632
8633 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8634
8635 plane_config->size = fb->pitches[0] * aligned_height;
8636
8637 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8638 pipe_name(pipe), fb->width, fb->height,
8639 fb->format->cpp[0] * 8, base, fb->pitches[0],
8640 plane_config->size);
8641
8642 plane_config->fb = intel_fb;
8643 }
8644
8645 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8646 struct intel_crtc_state *pipe_config)
8647 {
8648 struct drm_device *dev = crtc->base.dev;
8649 struct drm_i915_private *dev_priv = to_i915(dev);
8650 enum intel_display_power_domain power_domain;
8651 uint32_t tmp;
8652 bool ret;
8653
8654 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8655 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8656 return false;
8657
8658 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8659 pipe_config->shared_dpll = NULL;
8660
8661 ret = false;
8662 tmp = I915_READ(PIPECONF(crtc->pipe));
8663 if (!(tmp & PIPECONF_ENABLE))
8664 goto out;
8665
8666 switch (tmp & PIPECONF_BPC_MASK) {
8667 case PIPECONF_6BPC:
8668 pipe_config->pipe_bpp = 18;
8669 break;
8670 case PIPECONF_8BPC:
8671 pipe_config->pipe_bpp = 24;
8672 break;
8673 case PIPECONF_10BPC:
8674 pipe_config->pipe_bpp = 30;
8675 break;
8676 case PIPECONF_12BPC:
8677 pipe_config->pipe_bpp = 36;
8678 break;
8679 default:
8680 break;
8681 }
8682
8683 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8684 pipe_config->limited_color_range = true;
8685
8686 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8687 struct intel_shared_dpll *pll;
8688 enum intel_dpll_id pll_id;
8689
8690 pipe_config->has_pch_encoder = true;
8691
8692 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8693 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8694 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8695
8696 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8697
8698 if (HAS_PCH_IBX(dev_priv)) {
8699 /*
8700 * The pipe->pch transcoder and pch transcoder->pll
8701 * mapping is fixed.
8702 */
8703 pll_id = (enum intel_dpll_id) crtc->pipe;
8704 } else {
8705 tmp = I915_READ(PCH_DPLL_SEL);
8706 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8707 pll_id = DPLL_ID_PCH_PLL_B;
8708 else
8709 pll_id= DPLL_ID_PCH_PLL_A;
8710 }
8711
8712 pipe_config->shared_dpll =
8713 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8714 pll = pipe_config->shared_dpll;
8715
8716 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8717 &pipe_config->dpll_hw_state));
8718
8719 tmp = pipe_config->dpll_hw_state.dpll;
8720 pipe_config->pixel_multiplier =
8721 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8722 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8723
8724 ironlake_pch_clock_get(crtc, pipe_config);
8725 } else {
8726 pipe_config->pixel_multiplier = 1;
8727 }
8728
8729 intel_get_pipe_timings(crtc, pipe_config);
8730 intel_get_pipe_src_size(crtc, pipe_config);
8731
8732 ironlake_get_pfit_config(crtc, pipe_config);
8733
8734 ret = true;
8735
8736 out:
8737 intel_display_power_put(dev_priv, power_domain);
8738
8739 return ret;
8740 }
8741
8742 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8743 {
8744 struct drm_device *dev = &dev_priv->drm;
8745 struct intel_crtc *crtc;
8746
8747 for_each_intel_crtc(dev, crtc)
8748 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8749 pipe_name(crtc->pipe));
8750
8751 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8752 "Display power well on\n");
8753 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8754 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8755 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8756 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8757 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8758 "CPU PWM1 enabled\n");
8759 if (IS_HASWELL(dev_priv))
8760 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8761 "CPU PWM2 enabled\n");
8762 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8763 "PCH PWM1 enabled\n");
8764 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8765 "Utility pin enabled\n");
8766 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8767
8768 /*
8769 * In theory we can still leave IRQs enabled, as long as only the HPD
8770 * interrupts remain enabled. We used to check for that, but since it's
8771 * gen-specific and since we only disable LCPLL after we fully disable
8772 * the interrupts, the check below should be enough.
8773 */
8774 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8775 }
8776
8777 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8778 {
8779 if (IS_HASWELL(dev_priv))
8780 return I915_READ(D_COMP_HSW);
8781 else
8782 return I915_READ(D_COMP_BDW);
8783 }
8784
8785 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8786 {
8787 if (IS_HASWELL(dev_priv)) {
8788 mutex_lock(&dev_priv->pcu_lock);
8789 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8790 val))
8791 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8792 mutex_unlock(&dev_priv->pcu_lock);
8793 } else {
8794 I915_WRITE(D_COMP_BDW, val);
8795 POSTING_READ(D_COMP_BDW);
8796 }
8797 }
8798
8799 /*
8800 * This function implements pieces of two sequences from BSpec:
8801 * - Sequence for display software to disable LCPLL
8802 * - Sequence for display software to allow package C8+
8803 * The steps implemented here are just the steps that actually touch the LCPLL
8804 * register. Callers should take care of disabling all the display engine
8805 * functions, doing the mode unset, fixing interrupts, etc.
8806 */
8807 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8808 bool switch_to_fclk, bool allow_power_down)
8809 {
8810 uint32_t val;
8811
8812 assert_can_disable_lcpll(dev_priv);
8813
8814 val = I915_READ(LCPLL_CTL);
8815
8816 if (switch_to_fclk) {
8817 val |= LCPLL_CD_SOURCE_FCLK;
8818 I915_WRITE(LCPLL_CTL, val);
8819
8820 if (wait_for_us(I915_READ(LCPLL_CTL) &
8821 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8822 DRM_ERROR("Switching to FCLK failed\n");
8823
8824 val = I915_READ(LCPLL_CTL);
8825 }
8826
8827 val |= LCPLL_PLL_DISABLE;
8828 I915_WRITE(LCPLL_CTL, val);
8829 POSTING_READ(LCPLL_CTL);
8830
8831 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8832 DRM_ERROR("LCPLL still locked\n");
8833
8834 val = hsw_read_dcomp(dev_priv);
8835 val |= D_COMP_COMP_DISABLE;
8836 hsw_write_dcomp(dev_priv, val);
8837 ndelay(100);
8838
8839 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8840 1))
8841 DRM_ERROR("D_COMP RCOMP still in progress\n");
8842
8843 if (allow_power_down) {
8844 val = I915_READ(LCPLL_CTL);
8845 val |= LCPLL_POWER_DOWN_ALLOW;
8846 I915_WRITE(LCPLL_CTL, val);
8847 POSTING_READ(LCPLL_CTL);
8848 }
8849 }
8850
8851 /*
8852 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8853 * source.
8854 */
8855 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8856 {
8857 uint32_t val;
8858
8859 val = I915_READ(LCPLL_CTL);
8860
8861 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8862 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8863 return;
8864
8865 /*
8866 * Make sure we're not on PC8 state before disabling PC8, otherwise
8867 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8868 */
8869 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8870
8871 if (val & LCPLL_POWER_DOWN_ALLOW) {
8872 val &= ~LCPLL_POWER_DOWN_ALLOW;
8873 I915_WRITE(LCPLL_CTL, val);
8874 POSTING_READ(LCPLL_CTL);
8875 }
8876
8877 val = hsw_read_dcomp(dev_priv);
8878 val |= D_COMP_COMP_FORCE;
8879 val &= ~D_COMP_COMP_DISABLE;
8880 hsw_write_dcomp(dev_priv, val);
8881
8882 val = I915_READ(LCPLL_CTL);
8883 val &= ~LCPLL_PLL_DISABLE;
8884 I915_WRITE(LCPLL_CTL, val);
8885
8886 if (intel_wait_for_register(dev_priv,
8887 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8888 5))
8889 DRM_ERROR("LCPLL not locked yet\n");
8890
8891 if (val & LCPLL_CD_SOURCE_FCLK) {
8892 val = I915_READ(LCPLL_CTL);
8893 val &= ~LCPLL_CD_SOURCE_FCLK;
8894 I915_WRITE(LCPLL_CTL, val);
8895
8896 if (wait_for_us((I915_READ(LCPLL_CTL) &
8897 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8898 DRM_ERROR("Switching back to LCPLL failed\n");
8899 }
8900
8901 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8902
8903 intel_update_cdclk(dev_priv);
8904 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
8905 }
8906
8907 /*
8908 * Package states C8 and deeper are really deep PC states that can only be
8909 * reached when all the devices on the system allow it, so even if the graphics
8910 * device allows PC8+, it doesn't mean the system will actually get to these
8911 * states. Our driver only allows PC8+ when going into runtime PM.
8912 *
8913 * The requirements for PC8+ are that all the outputs are disabled, the power
8914 * well is disabled and most interrupts are disabled, and these are also
8915 * requirements for runtime PM. When these conditions are met, we manually do
8916 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8917 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8918 * hang the machine.
8919 *
8920 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8921 * the state of some registers, so when we come back from PC8+ we need to
8922 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8923 * need to take care of the registers kept by RC6. Notice that this happens even
8924 * if we don't put the device in PCI D3 state (which is what currently happens
8925 * because of the runtime PM support).
8926 *
8927 * For more, read "Display Sequences for Package C8" on the hardware
8928 * documentation.
8929 */
8930 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8931 {
8932 uint32_t val;
8933
8934 DRM_DEBUG_KMS("Enabling package C8+\n");
8935
8936 if (HAS_PCH_LPT_LP(dev_priv)) {
8937 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8938 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8939 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8940 }
8941
8942 lpt_disable_clkout_dp(dev_priv);
8943 hsw_disable_lcpll(dev_priv, true, true);
8944 }
8945
8946 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8947 {
8948 uint32_t val;
8949
8950 DRM_DEBUG_KMS("Disabling package C8+\n");
8951
8952 hsw_restore_lcpll(dev_priv);
8953 lpt_init_pch_refclk(dev_priv);
8954
8955 if (HAS_PCH_LPT_LP(dev_priv)) {
8956 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8957 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8958 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8959 }
8960 }
8961
8962 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8963 struct intel_crtc_state *crtc_state)
8964 {
8965 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8966 struct intel_encoder *encoder =
8967 intel_ddi_get_crtc_new_encoder(crtc_state);
8968
8969 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8970 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8971 pipe_name(crtc->pipe));
8972 return -EINVAL;
8973 }
8974 }
8975
8976 return 0;
8977 }
8978
8979 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8980 enum port port,
8981 struct intel_crtc_state *pipe_config)
8982 {
8983 enum intel_dpll_id id;
8984 u32 temp;
8985
8986 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8987 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
8988
8989 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8990 return;
8991
8992 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8993 }
8994
8995 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8996 enum port port,
8997 struct intel_crtc_state *pipe_config)
8998 {
8999 enum intel_dpll_id id;
9000
9001 switch (port) {
9002 case PORT_A:
9003 id = DPLL_ID_SKL_DPLL0;
9004 break;
9005 case PORT_B:
9006 id = DPLL_ID_SKL_DPLL1;
9007 break;
9008 case PORT_C:
9009 id = DPLL_ID_SKL_DPLL2;
9010 break;
9011 default:
9012 DRM_ERROR("Incorrect port type\n");
9013 return;
9014 }
9015
9016 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9017 }
9018
9019 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9020 enum port port,
9021 struct intel_crtc_state *pipe_config)
9022 {
9023 enum intel_dpll_id id;
9024 u32 temp;
9025
9026 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9027 id = temp >> (port * 3 + 1);
9028
9029 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9030 return;
9031
9032 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9033 }
9034
9035 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9036 enum port port,
9037 struct intel_crtc_state *pipe_config)
9038 {
9039 enum intel_dpll_id id;
9040 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9041
9042 switch (ddi_pll_sel) {
9043 case PORT_CLK_SEL_WRPLL1:
9044 id = DPLL_ID_WRPLL1;
9045 break;
9046 case PORT_CLK_SEL_WRPLL2:
9047 id = DPLL_ID_WRPLL2;
9048 break;
9049 case PORT_CLK_SEL_SPLL:
9050 id = DPLL_ID_SPLL;
9051 break;
9052 case PORT_CLK_SEL_LCPLL_810:
9053 id = DPLL_ID_LCPLL_810;
9054 break;
9055 case PORT_CLK_SEL_LCPLL_1350:
9056 id = DPLL_ID_LCPLL_1350;
9057 break;
9058 case PORT_CLK_SEL_LCPLL_2700:
9059 id = DPLL_ID_LCPLL_2700;
9060 break;
9061 default:
9062 MISSING_CASE(ddi_pll_sel);
9063 /* fall through */
9064 case PORT_CLK_SEL_NONE:
9065 return;
9066 }
9067
9068 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9069 }
9070
9071 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9072 struct intel_crtc_state *pipe_config,
9073 u64 *power_domain_mask)
9074 {
9075 struct drm_device *dev = crtc->base.dev;
9076 struct drm_i915_private *dev_priv = to_i915(dev);
9077 enum intel_display_power_domain power_domain;
9078 u32 tmp;
9079
9080 /*
9081 * The pipe->transcoder mapping is fixed with the exception of the eDP
9082 * transcoder handled below.
9083 */
9084 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9085
9086 /*
9087 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9088 * consistency and less surprising code; it's in always on power).
9089 */
9090 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9091 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9092 enum pipe trans_edp_pipe;
9093 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9094 default:
9095 WARN(1, "unknown pipe linked to edp transcoder\n");
9096 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9097 case TRANS_DDI_EDP_INPUT_A_ON:
9098 trans_edp_pipe = PIPE_A;
9099 break;
9100 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9101 trans_edp_pipe = PIPE_B;
9102 break;
9103 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9104 trans_edp_pipe = PIPE_C;
9105 break;
9106 }
9107
9108 if (trans_edp_pipe == crtc->pipe)
9109 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9110 }
9111
9112 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9113 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9114 return false;
9115 *power_domain_mask |= BIT_ULL(power_domain);
9116
9117 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9118
9119 return tmp & PIPECONF_ENABLE;
9120 }
9121
9122 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9123 struct intel_crtc_state *pipe_config,
9124 u64 *power_domain_mask)
9125 {
9126 struct drm_device *dev = crtc->base.dev;
9127 struct drm_i915_private *dev_priv = to_i915(dev);
9128 enum intel_display_power_domain power_domain;
9129 enum port port;
9130 enum transcoder cpu_transcoder;
9131 u32 tmp;
9132
9133 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9134 if (port == PORT_A)
9135 cpu_transcoder = TRANSCODER_DSI_A;
9136 else
9137 cpu_transcoder = TRANSCODER_DSI_C;
9138
9139 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9140 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9141 continue;
9142 *power_domain_mask |= BIT_ULL(power_domain);
9143
9144 /*
9145 * The PLL needs to be enabled with a valid divider
9146 * configuration, otherwise accessing DSI registers will hang
9147 * the machine. See BSpec North Display Engine
9148 * registers/MIPI[BXT]. We can break out here early, since we
9149 * need the same DSI PLL to be enabled for both DSI ports.
9150 */
9151 if (!intel_dsi_pll_is_enabled(dev_priv))
9152 break;
9153
9154 /* XXX: this works for video mode only */
9155 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9156 if (!(tmp & DPI_ENABLE))
9157 continue;
9158
9159 tmp = I915_READ(MIPI_CTRL(port));
9160 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9161 continue;
9162
9163 pipe_config->cpu_transcoder = cpu_transcoder;
9164 break;
9165 }
9166
9167 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9168 }
9169
9170 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9171 struct intel_crtc_state *pipe_config)
9172 {
9173 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9174 struct intel_shared_dpll *pll;
9175 enum port port;
9176 uint32_t tmp;
9177
9178 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9179
9180 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9181
9182 if (IS_CANNONLAKE(dev_priv))
9183 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9184 else if (IS_GEN9_BC(dev_priv))
9185 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9186 else if (IS_GEN9_LP(dev_priv))
9187 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9188 else
9189 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9190
9191 pll = pipe_config->shared_dpll;
9192 if (pll) {
9193 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9194 &pipe_config->dpll_hw_state));
9195 }
9196
9197 /*
9198 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9199 * DDI E. So just check whether this pipe is wired to DDI E and whether
9200 * the PCH transcoder is on.
9201 */
9202 if (INTEL_GEN(dev_priv) < 9 &&
9203 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9204 pipe_config->has_pch_encoder = true;
9205
9206 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9207 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9208 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9209
9210 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9211 }
9212 }
9213
9214 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9215 struct intel_crtc_state *pipe_config)
9216 {
9217 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9218 enum intel_display_power_domain power_domain;
9219 u64 power_domain_mask;
9220 bool active;
9221
9222 intel_crtc_init_scalers(crtc, pipe_config);
9223
9224 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9225 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9226 return false;
9227 power_domain_mask = BIT_ULL(power_domain);
9228
9229 pipe_config->shared_dpll = NULL;
9230
9231 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9232
9233 if (IS_GEN9_LP(dev_priv) &&
9234 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9235 WARN_ON(active);
9236 active = true;
9237 }
9238
9239 if (!active)
9240 goto out;
9241
9242 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9243 haswell_get_ddi_port_state(crtc, pipe_config);
9244 intel_get_pipe_timings(crtc, pipe_config);
9245 }
9246
9247 intel_get_pipe_src_size(crtc, pipe_config);
9248
9249 pipe_config->gamma_mode =
9250 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9251
9252 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9253 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9254 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9255
9256 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9257 bool blend_mode_420 = tmp &
9258 PIPEMISC_YUV420_MODE_FULL_BLEND;
9259
9260 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9261 if (pipe_config->ycbcr420 != clrspace_yuv ||
9262 pipe_config->ycbcr420 != blend_mode_420)
9263 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9264 } else if (clrspace_yuv) {
9265 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9266 }
9267 }
9268
9269 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9270 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9271 power_domain_mask |= BIT_ULL(power_domain);
9272 if (INTEL_GEN(dev_priv) >= 9)
9273 skylake_get_pfit_config(crtc, pipe_config);
9274 else
9275 ironlake_get_pfit_config(crtc, pipe_config);
9276 }
9277
9278 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9279 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9280 pipe_config->pixel_multiplier =
9281 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9282 } else {
9283 pipe_config->pixel_multiplier = 1;
9284 }
9285
9286 out:
9287 for_each_power_domain(power_domain, power_domain_mask)
9288 intel_display_power_put(dev_priv, power_domain);
9289
9290 return active;
9291 }
9292
9293 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9294 {
9295 struct drm_i915_private *dev_priv =
9296 to_i915(plane_state->base.plane->dev);
9297 const struct drm_framebuffer *fb = plane_state->base.fb;
9298 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9299 u32 base;
9300
9301 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9302 base = obj->phys_handle->busaddr;
9303 else
9304 base = intel_plane_ggtt_offset(plane_state);
9305
9306 base += plane_state->main.offset;
9307
9308 /* ILK+ do this automagically */
9309 if (HAS_GMCH_DISPLAY(dev_priv) &&
9310 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9311 base += (plane_state->base.crtc_h *
9312 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9313
9314 return base;
9315 }
9316
9317 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9318 {
9319 int x = plane_state->base.crtc_x;
9320 int y = plane_state->base.crtc_y;
9321 u32 pos = 0;
9322
9323 if (x < 0) {
9324 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9325 x = -x;
9326 }
9327 pos |= x << CURSOR_X_SHIFT;
9328
9329 if (y < 0) {
9330 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9331 y = -y;
9332 }
9333 pos |= y << CURSOR_Y_SHIFT;
9334
9335 return pos;
9336 }
9337
9338 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9339 {
9340 const struct drm_mode_config *config =
9341 &plane_state->base.plane->dev->mode_config;
9342 int width = plane_state->base.crtc_w;
9343 int height = plane_state->base.crtc_h;
9344
9345 return width > 0 && width <= config->cursor_width &&
9346 height > 0 && height <= config->cursor_height;
9347 }
9348
9349 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9350 struct intel_plane_state *plane_state)
9351 {
9352 const struct drm_framebuffer *fb = plane_state->base.fb;
9353 int src_x, src_y;
9354 u32 offset;
9355 int ret;
9356
9357 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
9358 &crtc_state->base,
9359 &plane_state->clip,
9360 DRM_PLANE_HELPER_NO_SCALING,
9361 DRM_PLANE_HELPER_NO_SCALING,
9362 true, true);
9363 if (ret)
9364 return ret;
9365
9366 if (!fb)
9367 return 0;
9368
9369 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9370 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9371 return -EINVAL;
9372 }
9373
9374 src_x = plane_state->base.src_x >> 16;
9375 src_y = plane_state->base.src_y >> 16;
9376
9377 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9378 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9379
9380 if (src_x != 0 || src_y != 0) {
9381 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9382 return -EINVAL;
9383 }
9384
9385 plane_state->main.offset = offset;
9386
9387 return 0;
9388 }
9389
9390 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9391 const struct intel_plane_state *plane_state)
9392 {
9393 const struct drm_framebuffer *fb = plane_state->base.fb;
9394
9395 return CURSOR_ENABLE |
9396 CURSOR_GAMMA_ENABLE |
9397 CURSOR_FORMAT_ARGB |
9398 CURSOR_STRIDE(fb->pitches[0]);
9399 }
9400
9401 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9402 {
9403 int width = plane_state->base.crtc_w;
9404
9405 /*
9406 * 845g/865g are only limited by the width of their cursors,
9407 * the height is arbitrary up to the precision of the register.
9408 */
9409 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9410 }
9411
9412 static int i845_check_cursor(struct intel_plane *plane,
9413 struct intel_crtc_state *crtc_state,
9414 struct intel_plane_state *plane_state)
9415 {
9416 const struct drm_framebuffer *fb = plane_state->base.fb;
9417 int ret;
9418
9419 ret = intel_check_cursor(crtc_state, plane_state);
9420 if (ret)
9421 return ret;
9422
9423 /* if we want to turn off the cursor ignore width and height */
9424 if (!fb)
9425 return 0;
9426
9427 /* Check for which cursor types we support */
9428 if (!i845_cursor_size_ok(plane_state)) {
9429 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9430 plane_state->base.crtc_w,
9431 plane_state->base.crtc_h);
9432 return -EINVAL;
9433 }
9434
9435 switch (fb->pitches[0]) {
9436 case 256:
9437 case 512:
9438 case 1024:
9439 case 2048:
9440 break;
9441 default:
9442 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9443 fb->pitches[0]);
9444 return -EINVAL;
9445 }
9446
9447 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9448
9449 return 0;
9450 }
9451
9452 static void i845_update_cursor(struct intel_plane *plane,
9453 const struct intel_crtc_state *crtc_state,
9454 const struct intel_plane_state *plane_state)
9455 {
9456 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9457 u32 cntl = 0, base = 0, pos = 0, size = 0;
9458 unsigned long irqflags;
9459
9460 if (plane_state && plane_state->base.visible) {
9461 unsigned int width = plane_state->base.crtc_w;
9462 unsigned int height = plane_state->base.crtc_h;
9463
9464 cntl = plane_state->ctl;
9465 size = (height << 12) | width;
9466
9467 base = intel_cursor_base(plane_state);
9468 pos = intel_cursor_position(plane_state);
9469 }
9470
9471 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9472
9473 /* On these chipsets we can only modify the base/size/stride
9474 * whilst the cursor is disabled.
9475 */
9476 if (plane->cursor.base != base ||
9477 plane->cursor.size != size ||
9478 plane->cursor.cntl != cntl) {
9479 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9480 I915_WRITE_FW(CURBASE(PIPE_A), base);
9481 I915_WRITE_FW(CURSIZE, size);
9482 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9483 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9484
9485 plane->cursor.base = base;
9486 plane->cursor.size = size;
9487 plane->cursor.cntl = cntl;
9488 } else {
9489 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9490 }
9491
9492 POSTING_READ_FW(CURCNTR(PIPE_A));
9493
9494 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9495 }
9496
9497 static void i845_disable_cursor(struct intel_plane *plane,
9498 struct intel_crtc *crtc)
9499 {
9500 i845_update_cursor(plane, NULL, NULL);
9501 }
9502
9503 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9504 const struct intel_plane_state *plane_state)
9505 {
9506 struct drm_i915_private *dev_priv =
9507 to_i915(plane_state->base.plane->dev);
9508 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9509 u32 cntl;
9510
9511 cntl = MCURSOR_GAMMA_ENABLE;
9512
9513 if (HAS_DDI(dev_priv))
9514 cntl |= CURSOR_PIPE_CSC_ENABLE;
9515
9516 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9517
9518 switch (plane_state->base.crtc_w) {
9519 case 64:
9520 cntl |= CURSOR_MODE_64_ARGB_AX;
9521 break;
9522 case 128:
9523 cntl |= CURSOR_MODE_128_ARGB_AX;
9524 break;
9525 case 256:
9526 cntl |= CURSOR_MODE_256_ARGB_AX;
9527 break;
9528 default:
9529 MISSING_CASE(plane_state->base.crtc_w);
9530 return 0;
9531 }
9532
9533 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9534 cntl |= CURSOR_ROTATE_180;
9535
9536 return cntl;
9537 }
9538
9539 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9540 {
9541 struct drm_i915_private *dev_priv =
9542 to_i915(plane_state->base.plane->dev);
9543 int width = plane_state->base.crtc_w;
9544 int height = plane_state->base.crtc_h;
9545
9546 if (!intel_cursor_size_ok(plane_state))
9547 return false;
9548
9549 /* Cursor width is limited to a few power-of-two sizes */
9550 switch (width) {
9551 case 256:
9552 case 128:
9553 case 64:
9554 break;
9555 default:
9556 return false;
9557 }
9558
9559 /*
9560 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9561 * height from 8 lines up to the cursor width, when the
9562 * cursor is not rotated. Everything else requires square
9563 * cursors.
9564 */
9565 if (HAS_CUR_FBC(dev_priv) &&
9566 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9567 if (height < 8 || height > width)
9568 return false;
9569 } else {
9570 if (height != width)
9571 return false;
9572 }
9573
9574 return true;
9575 }
9576
9577 static int i9xx_check_cursor(struct intel_plane *plane,
9578 struct intel_crtc_state *crtc_state,
9579 struct intel_plane_state *plane_state)
9580 {
9581 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9582 const struct drm_framebuffer *fb = plane_state->base.fb;
9583 enum pipe pipe = plane->pipe;
9584 int ret;
9585
9586 ret = intel_check_cursor(crtc_state, plane_state);
9587 if (ret)
9588 return ret;
9589
9590 /* if we want to turn off the cursor ignore width and height */
9591 if (!fb)
9592 return 0;
9593
9594 /* Check for which cursor types we support */
9595 if (!i9xx_cursor_size_ok(plane_state)) {
9596 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9597 plane_state->base.crtc_w,
9598 plane_state->base.crtc_h);
9599 return -EINVAL;
9600 }
9601
9602 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9603 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9604 fb->pitches[0], plane_state->base.crtc_w);
9605 return -EINVAL;
9606 }
9607
9608 /*
9609 * There's something wrong with the cursor on CHV pipe C.
9610 * If it straddles the left edge of the screen then
9611 * moving it away from the edge or disabling it often
9612 * results in a pipe underrun, and often that can lead to
9613 * dead pipe (constant underrun reported, and it scans
9614 * out just a solid color). To recover from that, the
9615 * display power well must be turned off and on again.
9616 * Refuse the put the cursor into that compromised position.
9617 */
9618 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9619 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9620 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9621 return -EINVAL;
9622 }
9623
9624 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9625
9626 return 0;
9627 }
9628
9629 static void i9xx_update_cursor(struct intel_plane *plane,
9630 const struct intel_crtc_state *crtc_state,
9631 const struct intel_plane_state *plane_state)
9632 {
9633 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9634 enum pipe pipe = plane->pipe;
9635 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9636 unsigned long irqflags;
9637
9638 if (plane_state && plane_state->base.visible) {
9639 cntl = plane_state->ctl;
9640
9641 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9642 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9643
9644 base = intel_cursor_base(plane_state);
9645 pos = intel_cursor_position(plane_state);
9646 }
9647
9648 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9649
9650 /*
9651 * On some platforms writing CURCNTR first will also
9652 * cause CURPOS to be armed by the CURBASE write.
9653 * Without the CURCNTR write the CURPOS write would
9654 * arm itself. Thus we always start the full update
9655 * with a CURCNTR write.
9656 *
9657 * On other platforms CURPOS always requires the
9658 * CURBASE write to arm the update. Additonally
9659 * a write to any of the cursor register will cancel
9660 * an already armed cursor update. Thus leaving out
9661 * the CURBASE write after CURPOS could lead to a
9662 * cursor that doesn't appear to move, or even change
9663 * shape. Thus we always write CURBASE.
9664 *
9665 * CURCNTR and CUR_FBC_CTL are always
9666 * armed by the CURBASE write only.
9667 */
9668 if (plane->cursor.base != base ||
9669 plane->cursor.size != fbc_ctl ||
9670 plane->cursor.cntl != cntl) {
9671 I915_WRITE_FW(CURCNTR(pipe), cntl);
9672 if (HAS_CUR_FBC(dev_priv))
9673 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9674 I915_WRITE_FW(CURPOS(pipe), pos);
9675 I915_WRITE_FW(CURBASE(pipe), base);
9676
9677 plane->cursor.base = base;
9678 plane->cursor.size = fbc_ctl;
9679 plane->cursor.cntl = cntl;
9680 } else {
9681 I915_WRITE_FW(CURPOS(pipe), pos);
9682 I915_WRITE_FW(CURBASE(pipe), base);
9683 }
9684
9685 POSTING_READ_FW(CURBASE(pipe));
9686
9687 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9688 }
9689
9690 static void i9xx_disable_cursor(struct intel_plane *plane,
9691 struct intel_crtc *crtc)
9692 {
9693 i9xx_update_cursor(plane, NULL, NULL);
9694 }
9695
9696
9697 /* VESA 640x480x72Hz mode to set on the pipe */
9698 static const struct drm_display_mode load_detect_mode = {
9699 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9700 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9701 };
9702
9703 struct drm_framebuffer *
9704 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9705 struct drm_mode_fb_cmd2 *mode_cmd)
9706 {
9707 struct intel_framebuffer *intel_fb;
9708 int ret;
9709
9710 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9711 if (!intel_fb)
9712 return ERR_PTR(-ENOMEM);
9713
9714 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9715 if (ret)
9716 goto err;
9717
9718 return &intel_fb->base;
9719
9720 err:
9721 kfree(intel_fb);
9722 return ERR_PTR(ret);
9723 }
9724
9725 static u32
9726 intel_framebuffer_pitch_for_width(int width, int bpp)
9727 {
9728 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9729 return ALIGN(pitch, 64);
9730 }
9731
9732 static u32
9733 intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9734 {
9735 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9736 return PAGE_ALIGN(pitch * mode->vdisplay);
9737 }
9738
9739 static struct drm_framebuffer *
9740 intel_framebuffer_create_for_mode(struct drm_device *dev,
9741 const struct drm_display_mode *mode,
9742 int depth, int bpp)
9743 {
9744 struct drm_framebuffer *fb;
9745 struct drm_i915_gem_object *obj;
9746 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9747
9748 obj = i915_gem_object_create(to_i915(dev),
9749 intel_framebuffer_size_for_mode(mode, bpp));
9750 if (IS_ERR(obj))
9751 return ERR_CAST(obj);
9752
9753 mode_cmd.width = mode->hdisplay;
9754 mode_cmd.height = mode->vdisplay;
9755 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9756 bpp);
9757 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9758
9759 fb = intel_framebuffer_create(obj, &mode_cmd);
9760 if (IS_ERR(fb))
9761 i915_gem_object_put(obj);
9762
9763 return fb;
9764 }
9765
9766 static struct drm_framebuffer *
9767 mode_fits_in_fbdev(struct drm_device *dev,
9768 const struct drm_display_mode *mode)
9769 {
9770 #ifdef CONFIG_DRM_FBDEV_EMULATION
9771 struct drm_i915_private *dev_priv = to_i915(dev);
9772 struct drm_i915_gem_object *obj;
9773 struct drm_framebuffer *fb;
9774
9775 if (!dev_priv->fbdev)
9776 return NULL;
9777
9778 if (!dev_priv->fbdev->fb)
9779 return NULL;
9780
9781 obj = dev_priv->fbdev->fb->obj;
9782 BUG_ON(!obj);
9783
9784 fb = &dev_priv->fbdev->fb->base;
9785 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9786 fb->format->cpp[0] * 8))
9787 return NULL;
9788
9789 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9790 return NULL;
9791
9792 drm_framebuffer_get(fb);
9793 return fb;
9794 #else
9795 return NULL;
9796 #endif
9797 }
9798
9799 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9800 struct drm_crtc *crtc,
9801 const struct drm_display_mode *mode,
9802 struct drm_framebuffer *fb,
9803 int x, int y)
9804 {
9805 struct drm_plane_state *plane_state;
9806 int hdisplay, vdisplay;
9807 int ret;
9808
9809 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9810 if (IS_ERR(plane_state))
9811 return PTR_ERR(plane_state);
9812
9813 if (mode)
9814 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9815 else
9816 hdisplay = vdisplay = 0;
9817
9818 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9819 if (ret)
9820 return ret;
9821 drm_atomic_set_fb_for_plane(plane_state, fb);
9822 plane_state->crtc_x = 0;
9823 plane_state->crtc_y = 0;
9824 plane_state->crtc_w = hdisplay;
9825 plane_state->crtc_h = vdisplay;
9826 plane_state->src_x = x << 16;
9827 plane_state->src_y = y << 16;
9828 plane_state->src_w = hdisplay << 16;
9829 plane_state->src_h = vdisplay << 16;
9830
9831 return 0;
9832 }
9833
9834 int intel_get_load_detect_pipe(struct drm_connector *connector,
9835 const struct drm_display_mode *mode,
9836 struct intel_load_detect_pipe *old,
9837 struct drm_modeset_acquire_ctx *ctx)
9838 {
9839 struct intel_crtc *intel_crtc;
9840 struct intel_encoder *intel_encoder =
9841 intel_attached_encoder(connector);
9842 struct drm_crtc *possible_crtc;
9843 struct drm_encoder *encoder = &intel_encoder->base;
9844 struct drm_crtc *crtc = NULL;
9845 struct drm_device *dev = encoder->dev;
9846 struct drm_i915_private *dev_priv = to_i915(dev);
9847 struct drm_framebuffer *fb;
9848 struct drm_mode_config *config = &dev->mode_config;
9849 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9850 struct drm_connector_state *connector_state;
9851 struct intel_crtc_state *crtc_state;
9852 int ret, i = -1;
9853
9854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9855 connector->base.id, connector->name,
9856 encoder->base.id, encoder->name);
9857
9858 old->restore_state = NULL;
9859
9860 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9861
9862 /*
9863 * Algorithm gets a little messy:
9864 *
9865 * - if the connector already has an assigned crtc, use it (but make
9866 * sure it's on first)
9867 *
9868 * - try to find the first unused crtc that can drive this connector,
9869 * and use that if we find one
9870 */
9871
9872 /* See if we already have a CRTC for this connector */
9873 if (connector->state->crtc) {
9874 crtc = connector->state->crtc;
9875
9876 ret = drm_modeset_lock(&crtc->mutex, ctx);
9877 if (ret)
9878 goto fail;
9879
9880 /* Make sure the crtc and connector are running */
9881 goto found;
9882 }
9883
9884 /* Find an unused one (if possible) */
9885 for_each_crtc(dev, possible_crtc) {
9886 i++;
9887 if (!(encoder->possible_crtcs & (1 << i)))
9888 continue;
9889
9890 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9891 if (ret)
9892 goto fail;
9893
9894 if (possible_crtc->state->enable) {
9895 drm_modeset_unlock(&possible_crtc->mutex);
9896 continue;
9897 }
9898
9899 crtc = possible_crtc;
9900 break;
9901 }
9902
9903 /*
9904 * If we didn't find an unused CRTC, don't use any.
9905 */
9906 if (!crtc) {
9907 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9908 ret = -ENODEV;
9909 goto fail;
9910 }
9911
9912 found:
9913 intel_crtc = to_intel_crtc(crtc);
9914
9915 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9916 if (ret)
9917 goto fail;
9918
9919 state = drm_atomic_state_alloc(dev);
9920 restore_state = drm_atomic_state_alloc(dev);
9921 if (!state || !restore_state) {
9922 ret = -ENOMEM;
9923 goto fail;
9924 }
9925
9926 state->acquire_ctx = ctx;
9927 restore_state->acquire_ctx = ctx;
9928
9929 connector_state = drm_atomic_get_connector_state(state, connector);
9930 if (IS_ERR(connector_state)) {
9931 ret = PTR_ERR(connector_state);
9932 goto fail;
9933 }
9934
9935 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9936 if (ret)
9937 goto fail;
9938
9939 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9940 if (IS_ERR(crtc_state)) {
9941 ret = PTR_ERR(crtc_state);
9942 goto fail;
9943 }
9944
9945 crtc_state->base.active = crtc_state->base.enable = true;
9946
9947 if (!mode)
9948 mode = &load_detect_mode;
9949
9950 /* We need a framebuffer large enough to accommodate all accesses
9951 * that the plane may generate whilst we perform load detection.
9952 * We can not rely on the fbcon either being present (we get called
9953 * during its initialisation to detect all boot displays, or it may
9954 * not even exist) or that it is large enough to satisfy the
9955 * requested mode.
9956 */
9957 fb = mode_fits_in_fbdev(dev, mode);
9958 if (fb == NULL) {
9959 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9960 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9961 } else
9962 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9963 if (IS_ERR(fb)) {
9964 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9965 ret = PTR_ERR(fb);
9966 goto fail;
9967 }
9968
9969 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9970 if (ret)
9971 goto fail;
9972
9973 drm_framebuffer_put(fb);
9974
9975 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9976 if (ret)
9977 goto fail;
9978
9979 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9980 if (!ret)
9981 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9982 if (!ret)
9983 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9984 if (ret) {
9985 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9986 goto fail;
9987 }
9988
9989 ret = drm_atomic_commit(state);
9990 if (ret) {
9991 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9992 goto fail;
9993 }
9994
9995 old->restore_state = restore_state;
9996 drm_atomic_state_put(state);
9997
9998 /* let the connector get through one full cycle before testing */
9999 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10000 return true;
10001
10002 fail:
10003 if (state) {
10004 drm_atomic_state_put(state);
10005 state = NULL;
10006 }
10007 if (restore_state) {
10008 drm_atomic_state_put(restore_state);
10009 restore_state = NULL;
10010 }
10011
10012 if (ret == -EDEADLK)
10013 return ret;
10014
10015 return false;
10016 }
10017
10018 void intel_release_load_detect_pipe(struct drm_connector *connector,
10019 struct intel_load_detect_pipe *old,
10020 struct drm_modeset_acquire_ctx *ctx)
10021 {
10022 struct intel_encoder *intel_encoder =
10023 intel_attached_encoder(connector);
10024 struct drm_encoder *encoder = &intel_encoder->base;
10025 struct drm_atomic_state *state = old->restore_state;
10026 int ret;
10027
10028 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10029 connector->base.id, connector->name,
10030 encoder->base.id, encoder->name);
10031
10032 if (!state)
10033 return;
10034
10035 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10036 if (ret)
10037 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10038 drm_atomic_state_put(state);
10039 }
10040
10041 static int i9xx_pll_refclk(struct drm_device *dev,
10042 const struct intel_crtc_state *pipe_config)
10043 {
10044 struct drm_i915_private *dev_priv = to_i915(dev);
10045 u32 dpll = pipe_config->dpll_hw_state.dpll;
10046
10047 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10048 return dev_priv->vbt.lvds_ssc_freq;
10049 else if (HAS_PCH_SPLIT(dev_priv))
10050 return 120000;
10051 else if (!IS_GEN2(dev_priv))
10052 return 96000;
10053 else
10054 return 48000;
10055 }
10056
10057 /* Returns the clock of the currently programmed mode of the given pipe. */
10058 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10059 struct intel_crtc_state *pipe_config)
10060 {
10061 struct drm_device *dev = crtc->base.dev;
10062 struct drm_i915_private *dev_priv = to_i915(dev);
10063 int pipe = pipe_config->cpu_transcoder;
10064 u32 dpll = pipe_config->dpll_hw_state.dpll;
10065 u32 fp;
10066 struct dpll clock;
10067 int port_clock;
10068 int refclk = i9xx_pll_refclk(dev, pipe_config);
10069
10070 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10071 fp = pipe_config->dpll_hw_state.fp0;
10072 else
10073 fp = pipe_config->dpll_hw_state.fp1;
10074
10075 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10076 if (IS_PINEVIEW(dev_priv)) {
10077 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10078 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10079 } else {
10080 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10081 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10082 }
10083
10084 if (!IS_GEN2(dev_priv)) {
10085 if (IS_PINEVIEW(dev_priv))
10086 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10087 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10088 else
10089 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10090 DPLL_FPA01_P1_POST_DIV_SHIFT);
10091
10092 switch (dpll & DPLL_MODE_MASK) {
10093 case DPLLB_MODE_DAC_SERIAL:
10094 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10095 5 : 10;
10096 break;
10097 case DPLLB_MODE_LVDS:
10098 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10099 7 : 14;
10100 break;
10101 default:
10102 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10103 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10104 return;
10105 }
10106
10107 if (IS_PINEVIEW(dev_priv))
10108 port_clock = pnv_calc_dpll_params(refclk, &clock);
10109 else
10110 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10111 } else {
10112 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10113 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10114
10115 if (is_lvds) {
10116 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10117 DPLL_FPA01_P1_POST_DIV_SHIFT);
10118
10119 if (lvds & LVDS_CLKB_POWER_UP)
10120 clock.p2 = 7;
10121 else
10122 clock.p2 = 14;
10123 } else {
10124 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10125 clock.p1 = 2;
10126 else {
10127 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10128 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10129 }
10130 if (dpll & PLL_P2_DIVIDE_BY_4)
10131 clock.p2 = 4;
10132 else
10133 clock.p2 = 2;
10134 }
10135
10136 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10137 }
10138
10139 /*
10140 * This value includes pixel_multiplier. We will use
10141 * port_clock to compute adjusted_mode.crtc_clock in the
10142 * encoder's get_config() function.
10143 */
10144 pipe_config->port_clock = port_clock;
10145 }
10146
10147 int intel_dotclock_calculate(int link_freq,
10148 const struct intel_link_m_n *m_n)
10149 {
10150 /*
10151 * The calculation for the data clock is:
10152 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10153 * But we want to avoid losing precison if possible, so:
10154 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10155 *
10156 * and the link clock is simpler:
10157 * link_clock = (m * link_clock) / n
10158 */
10159
10160 if (!m_n->link_n)
10161 return 0;
10162
10163 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10164 }
10165
10166 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10167 struct intel_crtc_state *pipe_config)
10168 {
10169 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10170
10171 /* read out port_clock from the DPLL */
10172 i9xx_crtc_clock_get(crtc, pipe_config);
10173
10174 /*
10175 * In case there is an active pipe without active ports,
10176 * we may need some idea for the dotclock anyway.
10177 * Calculate one based on the FDI configuration.
10178 */
10179 pipe_config->base.adjusted_mode.crtc_clock =
10180 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10181 &pipe_config->fdi_m_n);
10182 }
10183
10184 /* Returns the currently programmed mode of the given encoder. */
10185 struct drm_display_mode *
10186 intel_encoder_current_mode(struct intel_encoder *encoder)
10187 {
10188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10189 struct intel_crtc_state *crtc_state;
10190 struct drm_display_mode *mode;
10191 struct intel_crtc *crtc;
10192 enum pipe pipe;
10193
10194 if (!encoder->get_hw_state(encoder, &pipe))
10195 return NULL;
10196
10197 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10198
10199 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10200 if (!mode)
10201 return NULL;
10202
10203 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10204 if (!crtc_state) {
10205 kfree(mode);
10206 return NULL;
10207 }
10208
10209 crtc_state->base.crtc = &crtc->base;
10210
10211 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10212 kfree(crtc_state);
10213 kfree(mode);
10214 return NULL;
10215 }
10216
10217 encoder->get_config(encoder, crtc_state);
10218
10219 intel_mode_from_pipe_config(mode, crtc_state);
10220
10221 kfree(crtc_state);
10222
10223 return mode;
10224 }
10225
10226 static void intel_crtc_destroy(struct drm_crtc *crtc)
10227 {
10228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10229
10230 drm_crtc_cleanup(crtc);
10231 kfree(intel_crtc);
10232 }
10233
10234 /**
10235 * intel_wm_need_update - Check whether watermarks need updating
10236 * @plane: drm plane
10237 * @state: new plane state
10238 *
10239 * Check current plane state versus the new one to determine whether
10240 * watermarks need to be recalculated.
10241 *
10242 * Returns true or false.
10243 */
10244 static bool intel_wm_need_update(struct drm_plane *plane,
10245 struct drm_plane_state *state)
10246 {
10247 struct intel_plane_state *new = to_intel_plane_state(state);
10248 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10249
10250 /* Update watermarks on tiling or size changes. */
10251 if (new->base.visible != cur->base.visible)
10252 return true;
10253
10254 if (!cur->base.fb || !new->base.fb)
10255 return false;
10256
10257 if (cur->base.fb->modifier != new->base.fb->modifier ||
10258 cur->base.rotation != new->base.rotation ||
10259 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10260 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10261 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10262 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10263 return true;
10264
10265 return false;
10266 }
10267
10268 static bool needs_scaling(const struct intel_plane_state *state)
10269 {
10270 int src_w = drm_rect_width(&state->base.src) >> 16;
10271 int src_h = drm_rect_height(&state->base.src) >> 16;
10272 int dst_w = drm_rect_width(&state->base.dst);
10273 int dst_h = drm_rect_height(&state->base.dst);
10274
10275 return (src_w != dst_w || src_h != dst_h);
10276 }
10277
10278 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10279 struct drm_crtc_state *crtc_state,
10280 const struct intel_plane_state *old_plane_state,
10281 struct drm_plane_state *plane_state)
10282 {
10283 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10284 struct drm_crtc *crtc = crtc_state->crtc;
10285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10286 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10287 struct drm_device *dev = crtc->dev;
10288 struct drm_i915_private *dev_priv = to_i915(dev);
10289 bool mode_changed = needs_modeset(crtc_state);
10290 bool was_crtc_enabled = old_crtc_state->base.active;
10291 bool is_crtc_enabled = crtc_state->active;
10292 bool turn_off, turn_on, visible, was_visible;
10293 struct drm_framebuffer *fb = plane_state->fb;
10294 int ret;
10295
10296 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10297 ret = skl_update_scaler_plane(
10298 to_intel_crtc_state(crtc_state),
10299 to_intel_plane_state(plane_state));
10300 if (ret)
10301 return ret;
10302 }
10303
10304 was_visible = old_plane_state->base.visible;
10305 visible = plane_state->visible;
10306
10307 if (!was_crtc_enabled && WARN_ON(was_visible))
10308 was_visible = false;
10309
10310 /*
10311 * Visibility is calculated as if the crtc was on, but
10312 * after scaler setup everything depends on it being off
10313 * when the crtc isn't active.
10314 *
10315 * FIXME this is wrong for watermarks. Watermarks should also
10316 * be computed as if the pipe would be active. Perhaps move
10317 * per-plane wm computation to the .check_plane() hook, and
10318 * only combine the results from all planes in the current place?
10319 */
10320 if (!is_crtc_enabled) {
10321 plane_state->visible = visible = false;
10322 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10323 }
10324
10325 if (!was_visible && !visible)
10326 return 0;
10327
10328 if (fb != old_plane_state->base.fb)
10329 pipe_config->fb_changed = true;
10330
10331 turn_off = was_visible && (!visible || mode_changed);
10332 turn_on = visible && (!was_visible || mode_changed);
10333
10334 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10335 intel_crtc->base.base.id, intel_crtc->base.name,
10336 plane->base.base.id, plane->base.name,
10337 fb ? fb->base.id : -1);
10338
10339 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10340 plane->base.base.id, plane->base.name,
10341 was_visible, visible,
10342 turn_off, turn_on, mode_changed);
10343
10344 if (turn_on) {
10345 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10346 pipe_config->update_wm_pre = true;
10347
10348 /* must disable cxsr around plane enable/disable */
10349 if (plane->id != PLANE_CURSOR)
10350 pipe_config->disable_cxsr = true;
10351 } else if (turn_off) {
10352 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10353 pipe_config->update_wm_post = true;
10354
10355 /* must disable cxsr around plane enable/disable */
10356 if (plane->id != PLANE_CURSOR)
10357 pipe_config->disable_cxsr = true;
10358 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10359 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10360 /* FIXME bollocks */
10361 pipe_config->update_wm_pre = true;
10362 pipe_config->update_wm_post = true;
10363 }
10364 }
10365
10366 if (visible || was_visible)
10367 pipe_config->fb_bits |= plane->frontbuffer_bit;
10368
10369 /*
10370 * WaCxSRDisabledForSpriteScaling:ivb
10371 *
10372 * cstate->update_wm was already set above, so this flag will
10373 * take effect when we commit and program watermarks.
10374 */
10375 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10376 needs_scaling(to_intel_plane_state(plane_state)) &&
10377 !needs_scaling(old_plane_state))
10378 pipe_config->disable_lp_wm = true;
10379
10380 return 0;
10381 }
10382
10383 static bool encoders_cloneable(const struct intel_encoder *a,
10384 const struct intel_encoder *b)
10385 {
10386 /* masks could be asymmetric, so check both ways */
10387 return a == b || (a->cloneable & (1 << b->type) &&
10388 b->cloneable & (1 << a->type));
10389 }
10390
10391 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10392 struct intel_crtc *crtc,
10393 struct intel_encoder *encoder)
10394 {
10395 struct intel_encoder *source_encoder;
10396 struct drm_connector *connector;
10397 struct drm_connector_state *connector_state;
10398 int i;
10399
10400 for_each_new_connector_in_state(state, connector, connector_state, i) {
10401 if (connector_state->crtc != &crtc->base)
10402 continue;
10403
10404 source_encoder =
10405 to_intel_encoder(connector_state->best_encoder);
10406 if (!encoders_cloneable(encoder, source_encoder))
10407 return false;
10408 }
10409
10410 return true;
10411 }
10412
10413 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10414 struct drm_crtc_state *crtc_state)
10415 {
10416 struct drm_device *dev = crtc->dev;
10417 struct drm_i915_private *dev_priv = to_i915(dev);
10418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10419 struct intel_crtc_state *pipe_config =
10420 to_intel_crtc_state(crtc_state);
10421 struct drm_atomic_state *state = crtc_state->state;
10422 int ret;
10423 bool mode_changed = needs_modeset(crtc_state);
10424
10425 if (mode_changed && !crtc_state->active)
10426 pipe_config->update_wm_post = true;
10427
10428 if (mode_changed && crtc_state->enable &&
10429 dev_priv->display.crtc_compute_clock &&
10430 !WARN_ON(pipe_config->shared_dpll)) {
10431 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10432 pipe_config);
10433 if (ret)
10434 return ret;
10435 }
10436
10437 if (crtc_state->color_mgmt_changed) {
10438 ret = intel_color_check(crtc, crtc_state);
10439 if (ret)
10440 return ret;
10441
10442 /*
10443 * Changing color management on Intel hardware is
10444 * handled as part of planes update.
10445 */
10446 crtc_state->planes_changed = true;
10447 }
10448
10449 ret = 0;
10450 if (dev_priv->display.compute_pipe_wm) {
10451 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10452 if (ret) {
10453 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10454 return ret;
10455 }
10456 }
10457
10458 if (dev_priv->display.compute_intermediate_wm &&
10459 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10460 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10461 return 0;
10462
10463 /*
10464 * Calculate 'intermediate' watermarks that satisfy both the
10465 * old state and the new state. We can program these
10466 * immediately.
10467 */
10468 ret = dev_priv->display.compute_intermediate_wm(dev,
10469 intel_crtc,
10470 pipe_config);
10471 if (ret) {
10472 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10473 return ret;
10474 }
10475 } else if (dev_priv->display.compute_intermediate_wm) {
10476 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10477 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10478 }
10479
10480 if (INTEL_GEN(dev_priv) >= 9) {
10481 if (mode_changed)
10482 ret = skl_update_scaler_crtc(pipe_config);
10483
10484 if (!ret)
10485 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10486 pipe_config);
10487 if (!ret)
10488 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10489 pipe_config);
10490 }
10491
10492 return ret;
10493 }
10494
10495 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10496 .atomic_begin = intel_begin_crtc_commit,
10497 .atomic_flush = intel_finish_crtc_commit,
10498 .atomic_check = intel_crtc_atomic_check,
10499 };
10500
10501 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10502 {
10503 struct intel_connector *connector;
10504 struct drm_connector_list_iter conn_iter;
10505
10506 drm_connector_list_iter_begin(dev, &conn_iter);
10507 for_each_intel_connector_iter(connector, &conn_iter) {
10508 if (connector->base.state->crtc)
10509 drm_connector_unreference(&connector->base);
10510
10511 if (connector->base.encoder) {
10512 connector->base.state->best_encoder =
10513 connector->base.encoder;
10514 connector->base.state->crtc =
10515 connector->base.encoder->crtc;
10516
10517 drm_connector_reference(&connector->base);
10518 } else {
10519 connector->base.state->best_encoder = NULL;
10520 connector->base.state->crtc = NULL;
10521 }
10522 }
10523 drm_connector_list_iter_end(&conn_iter);
10524 }
10525
10526 static void
10527 connected_sink_compute_bpp(struct intel_connector *connector,
10528 struct intel_crtc_state *pipe_config)
10529 {
10530 const struct drm_display_info *info = &connector->base.display_info;
10531 int bpp = pipe_config->pipe_bpp;
10532
10533 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10534 connector->base.base.id,
10535 connector->base.name);
10536
10537 /* Don't use an invalid EDID bpc value */
10538 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10539 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10540 bpp, info->bpc * 3);
10541 pipe_config->pipe_bpp = info->bpc * 3;
10542 }
10543
10544 /* Clamp bpp to 8 on screens without EDID 1.4 */
10545 if (info->bpc == 0 && bpp > 24) {
10546 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10547 bpp);
10548 pipe_config->pipe_bpp = 24;
10549 }
10550 }
10551
10552 static int
10553 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10554 struct intel_crtc_state *pipe_config)
10555 {
10556 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10557 struct drm_atomic_state *state;
10558 struct drm_connector *connector;
10559 struct drm_connector_state *connector_state;
10560 int bpp, i;
10561
10562 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10563 IS_CHERRYVIEW(dev_priv)))
10564 bpp = 10*3;
10565 else if (INTEL_GEN(dev_priv) >= 5)
10566 bpp = 12*3;
10567 else
10568 bpp = 8*3;
10569
10570
10571 pipe_config->pipe_bpp = bpp;
10572
10573 state = pipe_config->base.state;
10574
10575 /* Clamp display bpp to EDID value */
10576 for_each_new_connector_in_state(state, connector, connector_state, i) {
10577 if (connector_state->crtc != &crtc->base)
10578 continue;
10579
10580 connected_sink_compute_bpp(to_intel_connector(connector),
10581 pipe_config);
10582 }
10583
10584 return bpp;
10585 }
10586
10587 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10588 {
10589 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10590 "type: 0x%x flags: 0x%x\n",
10591 mode->crtc_clock,
10592 mode->crtc_hdisplay, mode->crtc_hsync_start,
10593 mode->crtc_hsync_end, mode->crtc_htotal,
10594 mode->crtc_vdisplay, mode->crtc_vsync_start,
10595 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10596 }
10597
10598 static inline void
10599 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10600 unsigned int lane_count, struct intel_link_m_n *m_n)
10601 {
10602 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10603 id, lane_count,
10604 m_n->gmch_m, m_n->gmch_n,
10605 m_n->link_m, m_n->link_n, m_n->tu);
10606 }
10607
10608 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10609
10610 static const char * const output_type_str[] = {
10611 OUTPUT_TYPE(UNUSED),
10612 OUTPUT_TYPE(ANALOG),
10613 OUTPUT_TYPE(DVO),
10614 OUTPUT_TYPE(SDVO),
10615 OUTPUT_TYPE(LVDS),
10616 OUTPUT_TYPE(TVOUT),
10617 OUTPUT_TYPE(HDMI),
10618 OUTPUT_TYPE(DP),
10619 OUTPUT_TYPE(EDP),
10620 OUTPUT_TYPE(DSI),
10621 OUTPUT_TYPE(DDI),
10622 OUTPUT_TYPE(DP_MST),
10623 };
10624
10625 #undef OUTPUT_TYPE
10626
10627 static void snprintf_output_types(char *buf, size_t len,
10628 unsigned int output_types)
10629 {
10630 char *str = buf;
10631 int i;
10632
10633 str[0] = '\0';
10634
10635 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10636 int r;
10637
10638 if ((output_types & BIT(i)) == 0)
10639 continue;
10640
10641 r = snprintf(str, len, "%s%s",
10642 str != buf ? "," : "", output_type_str[i]);
10643 if (r >= len)
10644 break;
10645 str += r;
10646 len -= r;
10647
10648 output_types &= ~BIT(i);
10649 }
10650
10651 WARN_ON_ONCE(output_types != 0);
10652 }
10653
10654 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10655 struct intel_crtc_state *pipe_config,
10656 const char *context)
10657 {
10658 struct drm_device *dev = crtc->base.dev;
10659 struct drm_i915_private *dev_priv = to_i915(dev);
10660 struct drm_plane *plane;
10661 struct intel_plane *intel_plane;
10662 struct intel_plane_state *state;
10663 struct drm_framebuffer *fb;
10664 char buf[64];
10665
10666 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10667 crtc->base.base.id, crtc->base.name, context);
10668
10669 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10670 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10671 buf, pipe_config->output_types);
10672
10673 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10674 transcoder_name(pipe_config->cpu_transcoder),
10675 pipe_config->pipe_bpp, pipe_config->dither);
10676
10677 if (pipe_config->has_pch_encoder)
10678 intel_dump_m_n_config(pipe_config, "fdi",
10679 pipe_config->fdi_lanes,
10680 &pipe_config->fdi_m_n);
10681
10682 if (pipe_config->ycbcr420)
10683 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10684
10685 if (intel_crtc_has_dp_encoder(pipe_config)) {
10686 intel_dump_m_n_config(pipe_config, "dp m_n",
10687 pipe_config->lane_count, &pipe_config->dp_m_n);
10688 if (pipe_config->has_drrs)
10689 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10690 pipe_config->lane_count,
10691 &pipe_config->dp_m2_n2);
10692 }
10693
10694 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10695 pipe_config->has_audio, pipe_config->has_infoframe);
10696
10697 DRM_DEBUG_KMS("requested mode:\n");
10698 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10699 DRM_DEBUG_KMS("adjusted mode:\n");
10700 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10701 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10702 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10703 pipe_config->port_clock,
10704 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10705 pipe_config->pixel_rate);
10706
10707 if (INTEL_GEN(dev_priv) >= 9)
10708 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10709 crtc->num_scalers,
10710 pipe_config->scaler_state.scaler_users,
10711 pipe_config->scaler_state.scaler_id);
10712
10713 if (HAS_GMCH_DISPLAY(dev_priv))
10714 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10715 pipe_config->gmch_pfit.control,
10716 pipe_config->gmch_pfit.pgm_ratios,
10717 pipe_config->gmch_pfit.lvds_border_bits);
10718 else
10719 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10720 pipe_config->pch_pfit.pos,
10721 pipe_config->pch_pfit.size,
10722 enableddisabled(pipe_config->pch_pfit.enabled));
10723
10724 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10725 pipe_config->ips_enabled, pipe_config->double_wide);
10726
10727 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10728
10729 DRM_DEBUG_KMS("planes on this crtc\n");
10730 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10731 struct drm_format_name_buf format_name;
10732 intel_plane = to_intel_plane(plane);
10733 if (intel_plane->pipe != crtc->pipe)
10734 continue;
10735
10736 state = to_intel_plane_state(plane->state);
10737 fb = state->base.fb;
10738 if (!fb) {
10739 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10740 plane->base.id, plane->name, state->scaler_id);
10741 continue;
10742 }
10743
10744 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10745 plane->base.id, plane->name,
10746 fb->base.id, fb->width, fb->height,
10747 drm_get_format_name(fb->format->format, &format_name));
10748 if (INTEL_GEN(dev_priv) >= 9)
10749 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10750 state->scaler_id,
10751 state->base.src.x1 >> 16,
10752 state->base.src.y1 >> 16,
10753 drm_rect_width(&state->base.src) >> 16,
10754 drm_rect_height(&state->base.src) >> 16,
10755 state->base.dst.x1, state->base.dst.y1,
10756 drm_rect_width(&state->base.dst),
10757 drm_rect_height(&state->base.dst));
10758 }
10759 }
10760
10761 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10762 {
10763 struct drm_device *dev = state->dev;
10764 struct drm_connector *connector;
10765 struct drm_connector_list_iter conn_iter;
10766 unsigned int used_ports = 0;
10767 unsigned int used_mst_ports = 0;
10768
10769 /*
10770 * Walk the connector list instead of the encoder
10771 * list to detect the problem on ddi platforms
10772 * where there's just one encoder per digital port.
10773 */
10774 drm_connector_list_iter_begin(dev, &conn_iter);
10775 drm_for_each_connector_iter(connector, &conn_iter) {
10776 struct drm_connector_state *connector_state;
10777 struct intel_encoder *encoder;
10778
10779 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10780 if (!connector_state)
10781 connector_state = connector->state;
10782
10783 if (!connector_state->best_encoder)
10784 continue;
10785
10786 encoder = to_intel_encoder(connector_state->best_encoder);
10787
10788 WARN_ON(!connector_state->crtc);
10789
10790 switch (encoder->type) {
10791 unsigned int port_mask;
10792 case INTEL_OUTPUT_DDI:
10793 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10794 break;
10795 case INTEL_OUTPUT_DP:
10796 case INTEL_OUTPUT_HDMI:
10797 case INTEL_OUTPUT_EDP:
10798 port_mask = 1 << encoder->port;
10799
10800 /* the same port mustn't appear more than once */
10801 if (used_ports & port_mask)
10802 return false;
10803
10804 used_ports |= port_mask;
10805 break;
10806 case INTEL_OUTPUT_DP_MST:
10807 used_mst_ports |=
10808 1 << encoder->port;
10809 break;
10810 default:
10811 break;
10812 }
10813 }
10814 drm_connector_list_iter_end(&conn_iter);
10815
10816 /* can't mix MST and SST/HDMI on the same port */
10817 if (used_ports & used_mst_ports)
10818 return false;
10819
10820 return true;
10821 }
10822
10823 static void
10824 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10825 {
10826 struct drm_i915_private *dev_priv =
10827 to_i915(crtc_state->base.crtc->dev);
10828 struct intel_crtc_scaler_state scaler_state;
10829 struct intel_dpll_hw_state dpll_hw_state;
10830 struct intel_shared_dpll *shared_dpll;
10831 struct intel_crtc_wm_state wm_state;
10832 bool force_thru, ips_force_disable;
10833
10834 /* FIXME: before the switch to atomic started, a new pipe_config was
10835 * kzalloc'd. Code that depends on any field being zero should be
10836 * fixed, so that the crtc_state can be safely duplicated. For now,
10837 * only fields that are know to not cause problems are preserved. */
10838
10839 scaler_state = crtc_state->scaler_state;
10840 shared_dpll = crtc_state->shared_dpll;
10841 dpll_hw_state = crtc_state->dpll_hw_state;
10842 force_thru = crtc_state->pch_pfit.force_thru;
10843 ips_force_disable = crtc_state->ips_force_disable;
10844 if (IS_G4X(dev_priv) ||
10845 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10846 wm_state = crtc_state->wm;
10847
10848 /* Keep base drm_crtc_state intact, only clear our extended struct */
10849 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10850 memset(&crtc_state->base + 1, 0,
10851 sizeof(*crtc_state) - sizeof(crtc_state->base));
10852
10853 crtc_state->scaler_state = scaler_state;
10854 crtc_state->shared_dpll = shared_dpll;
10855 crtc_state->dpll_hw_state = dpll_hw_state;
10856 crtc_state->pch_pfit.force_thru = force_thru;
10857 crtc_state->ips_force_disable = ips_force_disable;
10858 if (IS_G4X(dev_priv) ||
10859 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10860 crtc_state->wm = wm_state;
10861 }
10862
10863 static int
10864 intel_modeset_pipe_config(struct drm_crtc *crtc,
10865 struct intel_crtc_state *pipe_config)
10866 {
10867 struct drm_atomic_state *state = pipe_config->base.state;
10868 struct intel_encoder *encoder;
10869 struct drm_connector *connector;
10870 struct drm_connector_state *connector_state;
10871 int base_bpp, ret = -EINVAL;
10872 int i;
10873 bool retry = true;
10874
10875 clear_intel_crtc_state(pipe_config);
10876
10877 pipe_config->cpu_transcoder =
10878 (enum transcoder) to_intel_crtc(crtc)->pipe;
10879
10880 /*
10881 * Sanitize sync polarity flags based on requested ones. If neither
10882 * positive or negative polarity is requested, treat this as meaning
10883 * negative polarity.
10884 */
10885 if (!(pipe_config->base.adjusted_mode.flags &
10886 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10887 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10888
10889 if (!(pipe_config->base.adjusted_mode.flags &
10890 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10891 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10892
10893 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10894 pipe_config);
10895 if (base_bpp < 0)
10896 goto fail;
10897
10898 /*
10899 * Determine the real pipe dimensions. Note that stereo modes can
10900 * increase the actual pipe size due to the frame doubling and
10901 * insertion of additional space for blanks between the frame. This
10902 * is stored in the crtc timings. We use the requested mode to do this
10903 * computation to clearly distinguish it from the adjusted mode, which
10904 * can be changed by the connectors in the below retry loop.
10905 */
10906 drm_mode_get_hv_timing(&pipe_config->base.mode,
10907 &pipe_config->pipe_src_w,
10908 &pipe_config->pipe_src_h);
10909
10910 for_each_new_connector_in_state(state, connector, connector_state, i) {
10911 if (connector_state->crtc != crtc)
10912 continue;
10913
10914 encoder = to_intel_encoder(connector_state->best_encoder);
10915
10916 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10917 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10918 goto fail;
10919 }
10920
10921 /*
10922 * Determine output_types before calling the .compute_config()
10923 * hooks so that the hooks can use this information safely.
10924 */
10925 if (encoder->compute_output_type)
10926 pipe_config->output_types |=
10927 BIT(encoder->compute_output_type(encoder, pipe_config,
10928 connector_state));
10929 else
10930 pipe_config->output_types |= BIT(encoder->type);
10931 }
10932
10933 encoder_retry:
10934 /* Ensure the port clock defaults are reset when retrying. */
10935 pipe_config->port_clock = 0;
10936 pipe_config->pixel_multiplier = 1;
10937
10938 /* Fill in default crtc timings, allow encoders to overwrite them. */
10939 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10940 CRTC_STEREO_DOUBLE);
10941
10942 /* Pass our mode to the connectors and the CRTC to give them a chance to
10943 * adjust it according to limitations or connector properties, and also
10944 * a chance to reject the mode entirely.
10945 */
10946 for_each_new_connector_in_state(state, connector, connector_state, i) {
10947 if (connector_state->crtc != crtc)
10948 continue;
10949
10950 encoder = to_intel_encoder(connector_state->best_encoder);
10951
10952 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10953 DRM_DEBUG_KMS("Encoder config failure\n");
10954 goto fail;
10955 }
10956 }
10957
10958 /* Set default port clock if not overwritten by the encoder. Needs to be
10959 * done afterwards in case the encoder adjusts the mode. */
10960 if (!pipe_config->port_clock)
10961 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10962 * pipe_config->pixel_multiplier;
10963
10964 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10965 if (ret < 0) {
10966 DRM_DEBUG_KMS("CRTC fixup failed\n");
10967 goto fail;
10968 }
10969
10970 if (ret == RETRY) {
10971 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10972 ret = -EINVAL;
10973 goto fail;
10974 }
10975
10976 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10977 retry = false;
10978 goto encoder_retry;
10979 }
10980
10981 /* Dithering seems to not pass-through bits correctly when it should, so
10982 * only enable it on 6bpc panels and when its not a compliance
10983 * test requesting 6bpc video pattern.
10984 */
10985 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10986 !pipe_config->dither_force_disable;
10987 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10988 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10989
10990 fail:
10991 return ret;
10992 }
10993
10994 static void
10995 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10996 {
10997 struct drm_crtc *crtc;
10998 struct drm_crtc_state *new_crtc_state;
10999 int i;
11000
11001 /* Double check state. */
11002 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11003 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11004
11005 /*
11006 * Update legacy state to satisfy fbc code. This can
11007 * be removed when fbc uses the atomic state.
11008 */
11009 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11010 struct drm_plane_state *plane_state = crtc->primary->state;
11011
11012 crtc->primary->fb = plane_state->fb;
11013 crtc->x = plane_state->src_x >> 16;
11014 crtc->y = plane_state->src_y >> 16;
11015 }
11016 }
11017 }
11018
11019 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11020 {
11021 int diff;
11022
11023 if (clock1 == clock2)
11024 return true;
11025
11026 if (!clock1 || !clock2)
11027 return false;
11028
11029 diff = abs(clock1 - clock2);
11030
11031 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11032 return true;
11033
11034 return false;
11035 }
11036
11037 static bool
11038 intel_compare_m_n(unsigned int m, unsigned int n,
11039 unsigned int m2, unsigned int n2,
11040 bool exact)
11041 {
11042 if (m == m2 && n == n2)
11043 return true;
11044
11045 if (exact || !m || !n || !m2 || !n2)
11046 return false;
11047
11048 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11049
11050 if (n > n2) {
11051 while (n > n2) {
11052 m2 <<= 1;
11053 n2 <<= 1;
11054 }
11055 } else if (n < n2) {
11056 while (n < n2) {
11057 m <<= 1;
11058 n <<= 1;
11059 }
11060 }
11061
11062 if (n != n2)
11063 return false;
11064
11065 return intel_fuzzy_clock_check(m, m2);
11066 }
11067
11068 static bool
11069 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11070 struct intel_link_m_n *m2_n2,
11071 bool adjust)
11072 {
11073 if (m_n->tu == m2_n2->tu &&
11074 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11075 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11076 intel_compare_m_n(m_n->link_m, m_n->link_n,
11077 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11078 if (adjust)
11079 *m2_n2 = *m_n;
11080
11081 return true;
11082 }
11083
11084 return false;
11085 }
11086
11087 static void __printf(3, 4)
11088 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11089 {
11090 char *level;
11091 unsigned int category;
11092 struct va_format vaf;
11093 va_list args;
11094
11095 if (adjust) {
11096 level = KERN_DEBUG;
11097 category = DRM_UT_KMS;
11098 } else {
11099 level = KERN_ERR;
11100 category = DRM_UT_NONE;
11101 }
11102
11103 va_start(args, format);
11104 vaf.fmt = format;
11105 vaf.va = &args;
11106
11107 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11108
11109 va_end(args);
11110 }
11111
11112 static bool
11113 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11114 struct intel_crtc_state *current_config,
11115 struct intel_crtc_state *pipe_config,
11116 bool adjust)
11117 {
11118 bool ret = true;
11119 bool fixup_inherited = adjust &&
11120 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11121 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11122
11123 #define PIPE_CONF_CHECK_X(name) \
11124 if (current_config->name != pipe_config->name) { \
11125 pipe_config_err(adjust, __stringify(name), \
11126 "(expected 0x%08x, found 0x%08x)\n", \
11127 current_config->name, \
11128 pipe_config->name); \
11129 ret = false; \
11130 }
11131
11132 #define PIPE_CONF_CHECK_I(name) \
11133 if (current_config->name != pipe_config->name) { \
11134 pipe_config_err(adjust, __stringify(name), \
11135 "(expected %i, found %i)\n", \
11136 current_config->name, \
11137 pipe_config->name); \
11138 ret = false; \
11139 }
11140
11141 #define PIPE_CONF_CHECK_BOOL(name) \
11142 if (current_config->name != pipe_config->name) { \
11143 pipe_config_err(adjust, __stringify(name), \
11144 "(expected %s, found %s)\n", \
11145 yesno(current_config->name), \
11146 yesno(pipe_config->name)); \
11147 ret = false; \
11148 }
11149
11150 /*
11151 * Checks state where we only read out the enabling, but not the entire
11152 * state itself (like full infoframes or ELD for audio). These states
11153 * require a full modeset on bootup to fix up.
11154 */
11155 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) \
11156 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11157 PIPE_CONF_CHECK_BOOL(name); \
11158 } else { \
11159 pipe_config_err(adjust, __stringify(name), \
11160 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
11161 yesno(current_config->name), \
11162 yesno(pipe_config->name)); \
11163 ret = false; \
11164 }
11165
11166 #define PIPE_CONF_CHECK_P(name) \
11167 if (current_config->name != pipe_config->name) { \
11168 pipe_config_err(adjust, __stringify(name), \
11169 "(expected %p, found %p)\n", \
11170 current_config->name, \
11171 pipe_config->name); \
11172 ret = false; \
11173 }
11174
11175 #define PIPE_CONF_CHECK_M_N(name) \
11176 if (!intel_compare_link_m_n(&current_config->name, \
11177 &pipe_config->name,\
11178 adjust)) { \
11179 pipe_config_err(adjust, __stringify(name), \
11180 "(expected tu %i gmch %i/%i link %i/%i, " \
11181 "found tu %i, gmch %i/%i link %i/%i)\n", \
11182 current_config->name.tu, \
11183 current_config->name.gmch_m, \
11184 current_config->name.gmch_n, \
11185 current_config->name.link_m, \
11186 current_config->name.link_n, \
11187 pipe_config->name.tu, \
11188 pipe_config->name.gmch_m, \
11189 pipe_config->name.gmch_n, \
11190 pipe_config->name.link_m, \
11191 pipe_config->name.link_n); \
11192 ret = false; \
11193 }
11194
11195 /* This is required for BDW+ where there is only one set of registers for
11196 * switching between high and low RR.
11197 * This macro can be used whenever a comparison has to be made between one
11198 * hw state and multiple sw state variables.
11199 */
11200 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11201 if (!intel_compare_link_m_n(&current_config->name, \
11202 &pipe_config->name, adjust) && \
11203 !intel_compare_link_m_n(&current_config->alt_name, \
11204 &pipe_config->name, adjust)) { \
11205 pipe_config_err(adjust, __stringify(name), \
11206 "(expected tu %i gmch %i/%i link %i/%i, " \
11207 "or tu %i gmch %i/%i link %i/%i, " \
11208 "found tu %i, gmch %i/%i link %i/%i)\n", \
11209 current_config->name.tu, \
11210 current_config->name.gmch_m, \
11211 current_config->name.gmch_n, \
11212 current_config->name.link_m, \
11213 current_config->name.link_n, \
11214 current_config->alt_name.tu, \
11215 current_config->alt_name.gmch_m, \
11216 current_config->alt_name.gmch_n, \
11217 current_config->alt_name.link_m, \
11218 current_config->alt_name.link_n, \
11219 pipe_config->name.tu, \
11220 pipe_config->name.gmch_m, \
11221 pipe_config->name.gmch_n, \
11222 pipe_config->name.link_m, \
11223 pipe_config->name.link_n); \
11224 ret = false; \
11225 }
11226
11227 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11228 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11229 pipe_config_err(adjust, __stringify(name), \
11230 "(%x) (expected %i, found %i)\n", \
11231 (mask), \
11232 current_config->name & (mask), \
11233 pipe_config->name & (mask)); \
11234 ret = false; \
11235 }
11236
11237 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11238 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11239 pipe_config_err(adjust, __stringify(name), \
11240 "(expected %i, found %i)\n", \
11241 current_config->name, \
11242 pipe_config->name); \
11243 ret = false; \
11244 }
11245
11246 #define PIPE_CONF_QUIRK(quirk) \
11247 ((current_config->quirks | pipe_config->quirks) & (quirk))
11248
11249 PIPE_CONF_CHECK_I(cpu_transcoder);
11250
11251 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11252 PIPE_CONF_CHECK_I(fdi_lanes);
11253 PIPE_CONF_CHECK_M_N(fdi_m_n);
11254
11255 PIPE_CONF_CHECK_I(lane_count);
11256 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11257
11258 if (INTEL_GEN(dev_priv) < 8) {
11259 PIPE_CONF_CHECK_M_N(dp_m_n);
11260
11261 if (current_config->has_drrs)
11262 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11263 } else
11264 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11265
11266 PIPE_CONF_CHECK_X(output_types);
11267
11268 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11269 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11270 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11271 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11272 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11273 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11274
11275 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11276 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11277 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11278 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11279 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11280 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11281
11282 PIPE_CONF_CHECK_I(pixel_multiplier);
11283 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11284 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11285 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11286 PIPE_CONF_CHECK_BOOL(limited_color_range);
11287
11288 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11289 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11290 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11291 PIPE_CONF_CHECK_BOOL(ycbcr420);
11292
11293 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11294
11295 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11296 DRM_MODE_FLAG_INTERLACE);
11297
11298 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11299 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11300 DRM_MODE_FLAG_PHSYNC);
11301 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11302 DRM_MODE_FLAG_NHSYNC);
11303 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11304 DRM_MODE_FLAG_PVSYNC);
11305 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11306 DRM_MODE_FLAG_NVSYNC);
11307 }
11308
11309 PIPE_CONF_CHECK_X(gmch_pfit.control);
11310 /* pfit ratios are autocomputed by the hw on gen4+ */
11311 if (INTEL_GEN(dev_priv) < 4)
11312 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11313 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11314
11315 if (!adjust) {
11316 PIPE_CONF_CHECK_I(pipe_src_w);
11317 PIPE_CONF_CHECK_I(pipe_src_h);
11318
11319 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11320 if (current_config->pch_pfit.enabled) {
11321 PIPE_CONF_CHECK_X(pch_pfit.pos);
11322 PIPE_CONF_CHECK_X(pch_pfit.size);
11323 }
11324
11325 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11326 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11327 }
11328
11329 PIPE_CONF_CHECK_BOOL(double_wide);
11330
11331 PIPE_CONF_CHECK_P(shared_dpll);
11332 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11333 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11334 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11335 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11336 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11337 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11338 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11339 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11340 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11341 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11342 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11343 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11344 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11345 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11346 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11347 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11348 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11349 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11350 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11351 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11352 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11353
11354 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11355 PIPE_CONF_CHECK_X(dsi_pll.div);
11356
11357 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11358 PIPE_CONF_CHECK_I(pipe_bpp);
11359
11360 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11361 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11362
11363 PIPE_CONF_CHECK_I(min_voltage_level);
11364
11365 #undef PIPE_CONF_CHECK_X
11366 #undef PIPE_CONF_CHECK_I
11367 #undef PIPE_CONF_CHECK_BOOL
11368 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11369 #undef PIPE_CONF_CHECK_P
11370 #undef PIPE_CONF_CHECK_FLAGS
11371 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11372 #undef PIPE_CONF_QUIRK
11373
11374 return ret;
11375 }
11376
11377 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11378 const struct intel_crtc_state *pipe_config)
11379 {
11380 if (pipe_config->has_pch_encoder) {
11381 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11382 &pipe_config->fdi_m_n);
11383 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11384
11385 /*
11386 * FDI already provided one idea for the dotclock.
11387 * Yell if the encoder disagrees.
11388 */
11389 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11390 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11391 fdi_dotclock, dotclock);
11392 }
11393 }
11394
11395 static void verify_wm_state(struct drm_crtc *crtc,
11396 struct drm_crtc_state *new_state)
11397 {
11398 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11399 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11400 struct skl_pipe_wm hw_wm, *sw_wm;
11401 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11402 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11404 const enum pipe pipe = intel_crtc->pipe;
11405 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11406
11407 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11408 return;
11409
11410 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11411 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11412
11413 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11414 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11415
11416 /* planes */
11417 for_each_universal_plane(dev_priv, pipe, plane) {
11418 hw_plane_wm = &hw_wm.planes[plane];
11419 sw_plane_wm = &sw_wm->planes[plane];
11420
11421 /* Watermarks */
11422 for (level = 0; level <= max_level; level++) {
11423 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11424 &sw_plane_wm->wm[level]))
11425 continue;
11426
11427 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11428 pipe_name(pipe), plane + 1, level,
11429 sw_plane_wm->wm[level].plane_en,
11430 sw_plane_wm->wm[level].plane_res_b,
11431 sw_plane_wm->wm[level].plane_res_l,
11432 hw_plane_wm->wm[level].plane_en,
11433 hw_plane_wm->wm[level].plane_res_b,
11434 hw_plane_wm->wm[level].plane_res_l);
11435 }
11436
11437 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11438 &sw_plane_wm->trans_wm)) {
11439 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11440 pipe_name(pipe), plane + 1,
11441 sw_plane_wm->trans_wm.plane_en,
11442 sw_plane_wm->trans_wm.plane_res_b,
11443 sw_plane_wm->trans_wm.plane_res_l,
11444 hw_plane_wm->trans_wm.plane_en,
11445 hw_plane_wm->trans_wm.plane_res_b,
11446 hw_plane_wm->trans_wm.plane_res_l);
11447 }
11448
11449 /* DDB */
11450 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11451 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11452
11453 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11454 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11455 pipe_name(pipe), plane + 1,
11456 sw_ddb_entry->start, sw_ddb_entry->end,
11457 hw_ddb_entry->start, hw_ddb_entry->end);
11458 }
11459 }
11460
11461 /*
11462 * cursor
11463 * If the cursor plane isn't active, we may not have updated it's ddb
11464 * allocation. In that case since the ddb allocation will be updated
11465 * once the plane becomes visible, we can skip this check
11466 */
11467 if (1) {
11468 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11469 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11470
11471 /* Watermarks */
11472 for (level = 0; level <= max_level; level++) {
11473 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11474 &sw_plane_wm->wm[level]))
11475 continue;
11476
11477 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11478 pipe_name(pipe), level,
11479 sw_plane_wm->wm[level].plane_en,
11480 sw_plane_wm->wm[level].plane_res_b,
11481 sw_plane_wm->wm[level].plane_res_l,
11482 hw_plane_wm->wm[level].plane_en,
11483 hw_plane_wm->wm[level].plane_res_b,
11484 hw_plane_wm->wm[level].plane_res_l);
11485 }
11486
11487 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11488 &sw_plane_wm->trans_wm)) {
11489 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11490 pipe_name(pipe),
11491 sw_plane_wm->trans_wm.plane_en,
11492 sw_plane_wm->trans_wm.plane_res_b,
11493 sw_plane_wm->trans_wm.plane_res_l,
11494 hw_plane_wm->trans_wm.plane_en,
11495 hw_plane_wm->trans_wm.plane_res_b,
11496 hw_plane_wm->trans_wm.plane_res_l);
11497 }
11498
11499 /* DDB */
11500 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11501 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11502
11503 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11504 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11505 pipe_name(pipe),
11506 sw_ddb_entry->start, sw_ddb_entry->end,
11507 hw_ddb_entry->start, hw_ddb_entry->end);
11508 }
11509 }
11510 }
11511
11512 static void
11513 verify_connector_state(struct drm_device *dev,
11514 struct drm_atomic_state *state,
11515 struct drm_crtc *crtc)
11516 {
11517 struct drm_connector *connector;
11518 struct drm_connector_state *new_conn_state;
11519 int i;
11520
11521 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11522 struct drm_encoder *encoder = connector->encoder;
11523 struct drm_crtc_state *crtc_state = NULL;
11524
11525 if (new_conn_state->crtc != crtc)
11526 continue;
11527
11528 if (crtc)
11529 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11530
11531 intel_connector_verify_state(crtc_state, new_conn_state);
11532
11533 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11534 "connector's atomic encoder doesn't match legacy encoder\n");
11535 }
11536 }
11537
11538 static void
11539 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11540 {
11541 struct intel_encoder *encoder;
11542 struct drm_connector *connector;
11543 struct drm_connector_state *old_conn_state, *new_conn_state;
11544 int i;
11545
11546 for_each_intel_encoder(dev, encoder) {
11547 bool enabled = false, found = false;
11548 enum pipe pipe;
11549
11550 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11551 encoder->base.base.id,
11552 encoder->base.name);
11553
11554 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11555 new_conn_state, i) {
11556 if (old_conn_state->best_encoder == &encoder->base)
11557 found = true;
11558
11559 if (new_conn_state->best_encoder != &encoder->base)
11560 continue;
11561 found = enabled = true;
11562
11563 I915_STATE_WARN(new_conn_state->crtc !=
11564 encoder->base.crtc,
11565 "connector's crtc doesn't match encoder crtc\n");
11566 }
11567
11568 if (!found)
11569 continue;
11570
11571 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11572 "encoder's enabled state mismatch "
11573 "(expected %i, found %i)\n",
11574 !!encoder->base.crtc, enabled);
11575
11576 if (!encoder->base.crtc) {
11577 bool active;
11578
11579 active = encoder->get_hw_state(encoder, &pipe);
11580 I915_STATE_WARN(active,
11581 "encoder detached but still enabled on pipe %c.\n",
11582 pipe_name(pipe));
11583 }
11584 }
11585 }
11586
11587 static void
11588 verify_crtc_state(struct drm_crtc *crtc,
11589 struct drm_crtc_state *old_crtc_state,
11590 struct drm_crtc_state *new_crtc_state)
11591 {
11592 struct drm_device *dev = crtc->dev;
11593 struct drm_i915_private *dev_priv = to_i915(dev);
11594 struct intel_encoder *encoder;
11595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11596 struct intel_crtc_state *pipe_config, *sw_config;
11597 struct drm_atomic_state *old_state;
11598 bool active;
11599
11600 old_state = old_crtc_state->state;
11601 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11602 pipe_config = to_intel_crtc_state(old_crtc_state);
11603 memset(pipe_config, 0, sizeof(*pipe_config));
11604 pipe_config->base.crtc = crtc;
11605 pipe_config->base.state = old_state;
11606
11607 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11608
11609 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11610
11611 /* we keep both pipes enabled on 830 */
11612 if (IS_I830(dev_priv))
11613 active = new_crtc_state->active;
11614
11615 I915_STATE_WARN(new_crtc_state->active != active,
11616 "crtc active state doesn't match with hw state "
11617 "(expected %i, found %i)\n", new_crtc_state->active, active);
11618
11619 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11620 "transitional active state does not match atomic hw state "
11621 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11622
11623 for_each_encoder_on_crtc(dev, crtc, encoder) {
11624 enum pipe pipe;
11625
11626 active = encoder->get_hw_state(encoder, &pipe);
11627 I915_STATE_WARN(active != new_crtc_state->active,
11628 "[ENCODER:%i] active %i with crtc active %i\n",
11629 encoder->base.base.id, active, new_crtc_state->active);
11630
11631 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11632 "Encoder connected to wrong pipe %c\n",
11633 pipe_name(pipe));
11634
11635 if (active)
11636 encoder->get_config(encoder, pipe_config);
11637 }
11638
11639 intel_crtc_compute_pixel_rate(pipe_config);
11640
11641 if (!new_crtc_state->active)
11642 return;
11643
11644 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11645
11646 sw_config = to_intel_crtc_state(new_crtc_state);
11647 if (!intel_pipe_config_compare(dev_priv, sw_config,
11648 pipe_config, false)) {
11649 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11650 intel_dump_pipe_config(intel_crtc, pipe_config,
11651 "[hw state]");
11652 intel_dump_pipe_config(intel_crtc, sw_config,
11653 "[sw state]");
11654 }
11655 }
11656
11657 static void
11658 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11659 struct intel_shared_dpll *pll,
11660 struct drm_crtc *crtc,
11661 struct drm_crtc_state *new_state)
11662 {
11663 struct intel_dpll_hw_state dpll_hw_state;
11664 unsigned crtc_mask;
11665 bool active;
11666
11667 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11668
11669 DRM_DEBUG_KMS("%s\n", pll->name);
11670
11671 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11672
11673 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11674 I915_STATE_WARN(!pll->on && pll->active_mask,
11675 "pll in active use but not on in sw tracking\n");
11676 I915_STATE_WARN(pll->on && !pll->active_mask,
11677 "pll is on but not used by any active crtc\n");
11678 I915_STATE_WARN(pll->on != active,
11679 "pll on state mismatch (expected %i, found %i)\n",
11680 pll->on, active);
11681 }
11682
11683 if (!crtc) {
11684 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11685 "more active pll users than references: %x vs %x\n",
11686 pll->active_mask, pll->state.crtc_mask);
11687
11688 return;
11689 }
11690
11691 crtc_mask = 1 << drm_crtc_index(crtc);
11692
11693 if (new_state->active)
11694 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11695 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11696 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11697 else
11698 I915_STATE_WARN(pll->active_mask & crtc_mask,
11699 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11700 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11701
11702 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11703 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11704 crtc_mask, pll->state.crtc_mask);
11705
11706 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11707 &dpll_hw_state,
11708 sizeof(dpll_hw_state)),
11709 "pll hw state mismatch\n");
11710 }
11711
11712 static void
11713 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11714 struct drm_crtc_state *old_crtc_state,
11715 struct drm_crtc_state *new_crtc_state)
11716 {
11717 struct drm_i915_private *dev_priv = to_i915(dev);
11718 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11719 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11720
11721 if (new_state->shared_dpll)
11722 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11723
11724 if (old_state->shared_dpll &&
11725 old_state->shared_dpll != new_state->shared_dpll) {
11726 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11727 struct intel_shared_dpll *pll = old_state->shared_dpll;
11728
11729 I915_STATE_WARN(pll->active_mask & crtc_mask,
11730 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11731 pipe_name(drm_crtc_index(crtc)));
11732 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11733 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11734 pipe_name(drm_crtc_index(crtc)));
11735 }
11736 }
11737
11738 static void
11739 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11740 struct drm_atomic_state *state,
11741 struct drm_crtc_state *old_state,
11742 struct drm_crtc_state *new_state)
11743 {
11744 if (!needs_modeset(new_state) &&
11745 !to_intel_crtc_state(new_state)->update_pipe)
11746 return;
11747
11748 verify_wm_state(crtc, new_state);
11749 verify_connector_state(crtc->dev, state, crtc);
11750 verify_crtc_state(crtc, old_state, new_state);
11751 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11752 }
11753
11754 static void
11755 verify_disabled_dpll_state(struct drm_device *dev)
11756 {
11757 struct drm_i915_private *dev_priv = to_i915(dev);
11758 int i;
11759
11760 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11761 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11762 }
11763
11764 static void
11765 intel_modeset_verify_disabled(struct drm_device *dev,
11766 struct drm_atomic_state *state)
11767 {
11768 verify_encoder_state(dev, state);
11769 verify_connector_state(dev, state, NULL);
11770 verify_disabled_dpll_state(dev);
11771 }
11772
11773 static void update_scanline_offset(struct intel_crtc *crtc)
11774 {
11775 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11776
11777 /*
11778 * The scanline counter increments at the leading edge of hsync.
11779 *
11780 * On most platforms it starts counting from vtotal-1 on the
11781 * first active line. That means the scanline counter value is
11782 * always one less than what we would expect. Ie. just after
11783 * start of vblank, which also occurs at start of hsync (on the
11784 * last active line), the scanline counter will read vblank_start-1.
11785 *
11786 * On gen2 the scanline counter starts counting from 1 instead
11787 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11788 * to keep the value positive), instead of adding one.
11789 *
11790 * On HSW+ the behaviour of the scanline counter depends on the output
11791 * type. For DP ports it behaves like most other platforms, but on HDMI
11792 * there's an extra 1 line difference. So we need to add two instead of
11793 * one to the value.
11794 *
11795 * On VLV/CHV DSI the scanline counter would appear to increment
11796 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11797 * that means we can't tell whether we're in vblank or not while
11798 * we're on that particular line. We must still set scanline_offset
11799 * to 1 so that the vblank timestamps come out correct when we query
11800 * the scanline counter from within the vblank interrupt handler.
11801 * However if queried just before the start of vblank we'll get an
11802 * answer that's slightly in the future.
11803 */
11804 if (IS_GEN2(dev_priv)) {
11805 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11806 int vtotal;
11807
11808 vtotal = adjusted_mode->crtc_vtotal;
11809 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11810 vtotal /= 2;
11811
11812 crtc->scanline_offset = vtotal - 1;
11813 } else if (HAS_DDI(dev_priv) &&
11814 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11815 crtc->scanline_offset = 2;
11816 } else
11817 crtc->scanline_offset = 1;
11818 }
11819
11820 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11821 {
11822 struct drm_device *dev = state->dev;
11823 struct drm_i915_private *dev_priv = to_i915(dev);
11824 struct drm_crtc *crtc;
11825 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11826 int i;
11827
11828 if (!dev_priv->display.crtc_compute_clock)
11829 return;
11830
11831 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11833 struct intel_shared_dpll *old_dpll =
11834 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11835
11836 if (!needs_modeset(new_crtc_state))
11837 continue;
11838
11839 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11840
11841 if (!old_dpll)
11842 continue;
11843
11844 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11845 }
11846 }
11847
11848 /*
11849 * This implements the workaround described in the "notes" section of the mode
11850 * set sequence documentation. When going from no pipes or single pipe to
11851 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11852 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11853 */
11854 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11855 {
11856 struct drm_crtc_state *crtc_state;
11857 struct intel_crtc *intel_crtc;
11858 struct drm_crtc *crtc;
11859 struct intel_crtc_state *first_crtc_state = NULL;
11860 struct intel_crtc_state *other_crtc_state = NULL;
11861 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11862 int i;
11863
11864 /* look at all crtc's that are going to be enabled in during modeset */
11865 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11866 intel_crtc = to_intel_crtc(crtc);
11867
11868 if (!crtc_state->active || !needs_modeset(crtc_state))
11869 continue;
11870
11871 if (first_crtc_state) {
11872 other_crtc_state = to_intel_crtc_state(crtc_state);
11873 break;
11874 } else {
11875 first_crtc_state = to_intel_crtc_state(crtc_state);
11876 first_pipe = intel_crtc->pipe;
11877 }
11878 }
11879
11880 /* No workaround needed? */
11881 if (!first_crtc_state)
11882 return 0;
11883
11884 /* w/a possibly needed, check how many crtc's are already enabled. */
11885 for_each_intel_crtc(state->dev, intel_crtc) {
11886 struct intel_crtc_state *pipe_config;
11887
11888 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11889 if (IS_ERR(pipe_config))
11890 return PTR_ERR(pipe_config);
11891
11892 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11893
11894 if (!pipe_config->base.active ||
11895 needs_modeset(&pipe_config->base))
11896 continue;
11897
11898 /* 2 or more enabled crtcs means no need for w/a */
11899 if (enabled_pipe != INVALID_PIPE)
11900 return 0;
11901
11902 enabled_pipe = intel_crtc->pipe;
11903 }
11904
11905 if (enabled_pipe != INVALID_PIPE)
11906 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11907 else if (other_crtc_state)
11908 other_crtc_state->hsw_workaround_pipe = first_pipe;
11909
11910 return 0;
11911 }
11912
11913 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11914 {
11915 struct drm_crtc *crtc;
11916
11917 /* Add all pipes to the state */
11918 for_each_crtc(state->dev, crtc) {
11919 struct drm_crtc_state *crtc_state;
11920
11921 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11922 if (IS_ERR(crtc_state))
11923 return PTR_ERR(crtc_state);
11924 }
11925
11926 return 0;
11927 }
11928
11929 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11930 {
11931 struct drm_crtc *crtc;
11932
11933 /*
11934 * Add all pipes to the state, and force
11935 * a modeset on all the active ones.
11936 */
11937 for_each_crtc(state->dev, crtc) {
11938 struct drm_crtc_state *crtc_state;
11939 int ret;
11940
11941 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11942 if (IS_ERR(crtc_state))
11943 return PTR_ERR(crtc_state);
11944
11945 if (!crtc_state->active || needs_modeset(crtc_state))
11946 continue;
11947
11948 crtc_state->mode_changed = true;
11949
11950 ret = drm_atomic_add_affected_connectors(state, crtc);
11951 if (ret)
11952 return ret;
11953
11954 ret = drm_atomic_add_affected_planes(state, crtc);
11955 if (ret)
11956 return ret;
11957 }
11958
11959 return 0;
11960 }
11961
11962 static int intel_modeset_checks(struct drm_atomic_state *state)
11963 {
11964 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11965 struct drm_i915_private *dev_priv = to_i915(state->dev);
11966 struct drm_crtc *crtc;
11967 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11968 int ret = 0, i;
11969
11970 if (!check_digital_port_conflicts(state)) {
11971 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11972 return -EINVAL;
11973 }
11974
11975 intel_state->modeset = true;
11976 intel_state->active_crtcs = dev_priv->active_crtcs;
11977 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11978 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11979
11980 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11981 if (new_crtc_state->active)
11982 intel_state->active_crtcs |= 1 << i;
11983 else
11984 intel_state->active_crtcs &= ~(1 << i);
11985
11986 if (old_crtc_state->active != new_crtc_state->active)
11987 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11988 }
11989
11990 /*
11991 * See if the config requires any additional preparation, e.g.
11992 * to adjust global state with pipes off. We need to do this
11993 * here so we can get the modeset_pipe updated config for the new
11994 * mode set on this crtc. For other crtcs we need to use the
11995 * adjusted_mode bits in the crtc directly.
11996 */
11997 if (dev_priv->display.modeset_calc_cdclk) {
11998 ret = dev_priv->display.modeset_calc_cdclk(state);
11999 if (ret < 0)
12000 return ret;
12001
12002 /*
12003 * Writes to dev_priv->cdclk.logical must protected by
12004 * holding all the crtc locks, even if we don't end up
12005 * touching the hardware
12006 */
12007 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
12008 &intel_state->cdclk.logical)) {
12009 ret = intel_lock_all_pipes(state);
12010 if (ret < 0)
12011 return ret;
12012 }
12013
12014 /* All pipes must be switched off while we change the cdclk. */
12015 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
12016 &intel_state->cdclk.actual)) {
12017 ret = intel_modeset_all_pipes(state);
12018 if (ret < 0)
12019 return ret;
12020 }
12021
12022 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12023 intel_state->cdclk.logical.cdclk,
12024 intel_state->cdclk.actual.cdclk);
12025 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
12026 intel_state->cdclk.logical.voltage_level,
12027 intel_state->cdclk.actual.voltage_level);
12028 } else {
12029 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12030 }
12031
12032 intel_modeset_clear_plls(state);
12033
12034 if (IS_HASWELL(dev_priv))
12035 return haswell_mode_set_planes_workaround(state);
12036
12037 return 0;
12038 }
12039
12040 /*
12041 * Handle calculation of various watermark data at the end of the atomic check
12042 * phase. The code here should be run after the per-crtc and per-plane 'check'
12043 * handlers to ensure that all derived state has been updated.
12044 */
12045 static int calc_watermark_data(struct drm_atomic_state *state)
12046 {
12047 struct drm_device *dev = state->dev;
12048 struct drm_i915_private *dev_priv = to_i915(dev);
12049
12050 /* Is there platform-specific watermark information to calculate? */
12051 if (dev_priv->display.compute_global_watermarks)
12052 return dev_priv->display.compute_global_watermarks(state);
12053
12054 return 0;
12055 }
12056
12057 /**
12058 * intel_atomic_check - validate state object
12059 * @dev: drm device
12060 * @state: state to validate
12061 */
12062 static int intel_atomic_check(struct drm_device *dev,
12063 struct drm_atomic_state *state)
12064 {
12065 struct drm_i915_private *dev_priv = to_i915(dev);
12066 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12067 struct drm_crtc *crtc;
12068 struct drm_crtc_state *old_crtc_state, *crtc_state;
12069 int ret, i;
12070 bool any_ms = false;
12071
12072 ret = drm_atomic_helper_check_modeset(dev, state);
12073 if (ret)
12074 return ret;
12075
12076 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12077 struct intel_crtc_state *pipe_config =
12078 to_intel_crtc_state(crtc_state);
12079
12080 /* Catch I915_MODE_FLAG_INHERITED */
12081 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12082 crtc_state->mode_changed = true;
12083
12084 if (!needs_modeset(crtc_state))
12085 continue;
12086
12087 if (!crtc_state->enable) {
12088 any_ms = true;
12089 continue;
12090 }
12091
12092 /* FIXME: For only active_changed we shouldn't need to do any
12093 * state recomputation at all. */
12094
12095 ret = drm_atomic_add_affected_connectors(state, crtc);
12096 if (ret)
12097 return ret;
12098
12099 ret = intel_modeset_pipe_config(crtc, pipe_config);
12100 if (ret) {
12101 intel_dump_pipe_config(to_intel_crtc(crtc),
12102 pipe_config, "[failed]");
12103 return ret;
12104 }
12105
12106 if (i915_modparams.fastboot &&
12107 intel_pipe_config_compare(dev_priv,
12108 to_intel_crtc_state(old_crtc_state),
12109 pipe_config, true)) {
12110 crtc_state->mode_changed = false;
12111 pipe_config->update_pipe = true;
12112 }
12113
12114 if (needs_modeset(crtc_state))
12115 any_ms = true;
12116
12117 ret = drm_atomic_add_affected_planes(state, crtc);
12118 if (ret)
12119 return ret;
12120
12121 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12122 needs_modeset(crtc_state) ?
12123 "[modeset]" : "[fastset]");
12124 }
12125
12126 if (any_ms) {
12127 ret = intel_modeset_checks(state);
12128
12129 if (ret)
12130 return ret;
12131 } else {
12132 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12133 }
12134
12135 ret = drm_atomic_helper_check_planes(dev, state);
12136 if (ret)
12137 return ret;
12138
12139 intel_fbc_choose_crtc(dev_priv, state);
12140 return calc_watermark_data(state);
12141 }
12142
12143 static int intel_atomic_prepare_commit(struct drm_device *dev,
12144 struct drm_atomic_state *state)
12145 {
12146 return drm_atomic_helper_prepare_planes(dev, state);
12147 }
12148
12149 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12150 {
12151 struct drm_device *dev = crtc->base.dev;
12152
12153 if (!dev->max_vblank_count)
12154 return drm_crtc_accurate_vblank_count(&crtc->base);
12155
12156 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12157 }
12158
12159 static void intel_update_crtc(struct drm_crtc *crtc,
12160 struct drm_atomic_state *state,
12161 struct drm_crtc_state *old_crtc_state,
12162 struct drm_crtc_state *new_crtc_state)
12163 {
12164 struct drm_device *dev = crtc->dev;
12165 struct drm_i915_private *dev_priv = to_i915(dev);
12166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12167 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12168 bool modeset = needs_modeset(new_crtc_state);
12169
12170 if (modeset) {
12171 update_scanline_offset(intel_crtc);
12172 dev_priv->display.crtc_enable(pipe_config, state);
12173 } else {
12174 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12175 pipe_config);
12176 }
12177
12178 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12179 intel_fbc_enable(
12180 intel_crtc, pipe_config,
12181 to_intel_plane_state(crtc->primary->state));
12182 }
12183
12184 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12185 }
12186
12187 static void intel_update_crtcs(struct drm_atomic_state *state)
12188 {
12189 struct drm_crtc *crtc;
12190 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12191 int i;
12192
12193 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12194 if (!new_crtc_state->active)
12195 continue;
12196
12197 intel_update_crtc(crtc, state, old_crtc_state,
12198 new_crtc_state);
12199 }
12200 }
12201
12202 static void skl_update_crtcs(struct drm_atomic_state *state)
12203 {
12204 struct drm_i915_private *dev_priv = to_i915(state->dev);
12205 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12206 struct drm_crtc *crtc;
12207 struct intel_crtc *intel_crtc;
12208 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12209 struct intel_crtc_state *cstate;
12210 unsigned int updated = 0;
12211 bool progress;
12212 enum pipe pipe;
12213 int i;
12214
12215 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12216
12217 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12218 /* ignore allocations for crtc's that have been turned off. */
12219 if (new_crtc_state->active)
12220 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12221
12222 /*
12223 * Whenever the number of active pipes changes, we need to make sure we
12224 * update the pipes in the right order so that their ddb allocations
12225 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12226 * cause pipe underruns and other bad stuff.
12227 */
12228 do {
12229 progress = false;
12230
12231 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12232 bool vbl_wait = false;
12233 unsigned int cmask = drm_crtc_mask(crtc);
12234
12235 intel_crtc = to_intel_crtc(crtc);
12236 cstate = to_intel_crtc_state(new_crtc_state);
12237 pipe = intel_crtc->pipe;
12238
12239 if (updated & cmask || !cstate->base.active)
12240 continue;
12241
12242 if (skl_ddb_allocation_overlaps(dev_priv,
12243 entries,
12244 &cstate->wm.skl.ddb,
12245 i))
12246 continue;
12247
12248 updated |= cmask;
12249 entries[i] = &cstate->wm.skl.ddb;
12250
12251 /*
12252 * If this is an already active pipe, it's DDB changed,
12253 * and this isn't the last pipe that needs updating
12254 * then we need to wait for a vblank to pass for the
12255 * new ddb allocation to take effect.
12256 */
12257 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12258 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12259 !new_crtc_state->active_changed &&
12260 intel_state->wm_results.dirty_pipes != updated)
12261 vbl_wait = true;
12262
12263 intel_update_crtc(crtc, state, old_crtc_state,
12264 new_crtc_state);
12265
12266 if (vbl_wait)
12267 intel_wait_for_vblank(dev_priv, pipe);
12268
12269 progress = true;
12270 }
12271 } while (progress);
12272 }
12273
12274 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12275 {
12276 struct intel_atomic_state *state, *next;
12277 struct llist_node *freed;
12278
12279 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12280 llist_for_each_entry_safe(state, next, freed, freed)
12281 drm_atomic_state_put(&state->base);
12282 }
12283
12284 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12285 {
12286 struct drm_i915_private *dev_priv =
12287 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12288
12289 intel_atomic_helper_free_state(dev_priv);
12290 }
12291
12292 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12293 {
12294 struct wait_queue_entry wait_fence, wait_reset;
12295 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12296
12297 init_wait_entry(&wait_fence, 0);
12298 init_wait_entry(&wait_reset, 0);
12299 for (;;) {
12300 prepare_to_wait(&intel_state->commit_ready.wait,
12301 &wait_fence, TASK_UNINTERRUPTIBLE);
12302 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12303 &wait_reset, TASK_UNINTERRUPTIBLE);
12304
12305
12306 if (i915_sw_fence_done(&intel_state->commit_ready)
12307 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12308 break;
12309
12310 schedule();
12311 }
12312 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12313 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12314 }
12315
12316 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12317 {
12318 struct drm_device *dev = state->dev;
12319 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12320 struct drm_i915_private *dev_priv = to_i915(dev);
12321 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12322 struct drm_crtc *crtc;
12323 struct intel_crtc_state *intel_cstate;
12324 u64 put_domains[I915_MAX_PIPES] = {};
12325 int i;
12326
12327 intel_atomic_commit_fence_wait(intel_state);
12328
12329 drm_atomic_helper_wait_for_dependencies(state);
12330
12331 if (intel_state->modeset)
12332 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12333
12334 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12336
12337 if (needs_modeset(new_crtc_state) ||
12338 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12339
12340 put_domains[to_intel_crtc(crtc)->pipe] =
12341 modeset_get_crtc_power_domains(crtc,
12342 to_intel_crtc_state(new_crtc_state));
12343 }
12344
12345 if (!needs_modeset(new_crtc_state))
12346 continue;
12347
12348 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12349 to_intel_crtc_state(new_crtc_state));
12350
12351 if (old_crtc_state->active) {
12352 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12353 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12354 intel_crtc->active = false;
12355 intel_fbc_disable(intel_crtc);
12356 intel_disable_shared_dpll(intel_crtc);
12357
12358 /*
12359 * Underruns don't always raise
12360 * interrupts, so check manually.
12361 */
12362 intel_check_cpu_fifo_underruns(dev_priv);
12363 intel_check_pch_fifo_underruns(dev_priv);
12364
12365 if (!new_crtc_state->active) {
12366 /*
12367 * Make sure we don't call initial_watermarks
12368 * for ILK-style watermark updates.
12369 *
12370 * No clue what this is supposed to achieve.
12371 */
12372 if (INTEL_GEN(dev_priv) >= 9)
12373 dev_priv->display.initial_watermarks(intel_state,
12374 to_intel_crtc_state(new_crtc_state));
12375 }
12376 }
12377 }
12378
12379 /* Only after disabling all output pipelines that will be changed can we
12380 * update the the output configuration. */
12381 intel_modeset_update_crtc_state(state);
12382
12383 if (intel_state->modeset) {
12384 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12385
12386 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12387
12388 /*
12389 * SKL workaround: bspec recommends we disable the SAGV when we
12390 * have more then one pipe enabled
12391 */
12392 if (!intel_can_enable_sagv(state))
12393 intel_disable_sagv(dev_priv);
12394
12395 intel_modeset_verify_disabled(dev, state);
12396 }
12397
12398 /* Complete the events for pipes that have now been disabled */
12399 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12400 bool modeset = needs_modeset(new_crtc_state);
12401
12402 /* Complete events for now disable pipes here. */
12403 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12404 spin_lock_irq(&dev->event_lock);
12405 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12406 spin_unlock_irq(&dev->event_lock);
12407
12408 new_crtc_state->event = NULL;
12409 }
12410 }
12411
12412 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12413 dev_priv->display.update_crtcs(state);
12414
12415 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12416 * already, but still need the state for the delayed optimization. To
12417 * fix this:
12418 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12419 * - schedule that vblank worker _before_ calling hw_done
12420 * - at the start of commit_tail, cancel it _synchrously
12421 * - switch over to the vblank wait helper in the core after that since
12422 * we don't need out special handling any more.
12423 */
12424 drm_atomic_helper_wait_for_flip_done(dev, state);
12425
12426 /*
12427 * Now that the vblank has passed, we can go ahead and program the
12428 * optimal watermarks on platforms that need two-step watermark
12429 * programming.
12430 *
12431 * TODO: Move this (and other cleanup) to an async worker eventually.
12432 */
12433 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12434 intel_cstate = to_intel_crtc_state(new_crtc_state);
12435
12436 if (dev_priv->display.optimize_watermarks)
12437 dev_priv->display.optimize_watermarks(intel_state,
12438 intel_cstate);
12439 }
12440
12441 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12442 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12443
12444 if (put_domains[i])
12445 modeset_put_power_domains(dev_priv, put_domains[i]);
12446
12447 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12448 }
12449
12450 if (intel_state->modeset && intel_can_enable_sagv(state))
12451 intel_enable_sagv(dev_priv);
12452
12453 drm_atomic_helper_commit_hw_done(state);
12454
12455 if (intel_state->modeset) {
12456 /* As one of the primary mmio accessors, KMS has a high
12457 * likelihood of triggering bugs in unclaimed access. After we
12458 * finish modesetting, see if an error has been flagged, and if
12459 * so enable debugging for the next modeset - and hope we catch
12460 * the culprit.
12461 */
12462 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12463 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12464 }
12465
12466 drm_atomic_helper_cleanup_planes(dev, state);
12467
12468 drm_atomic_helper_commit_cleanup_done(state);
12469
12470 drm_atomic_state_put(state);
12471
12472 intel_atomic_helper_free_state(dev_priv);
12473 }
12474
12475 static void intel_atomic_commit_work(struct work_struct *work)
12476 {
12477 struct drm_atomic_state *state =
12478 container_of(work, struct drm_atomic_state, commit_work);
12479
12480 intel_atomic_commit_tail(state);
12481 }
12482
12483 static int __i915_sw_fence_call
12484 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12485 enum i915_sw_fence_notify notify)
12486 {
12487 struct intel_atomic_state *state =
12488 container_of(fence, struct intel_atomic_state, commit_ready);
12489
12490 switch (notify) {
12491 case FENCE_COMPLETE:
12492 /* we do blocking waits in the worker, nothing to do here */
12493 break;
12494 case FENCE_FREE:
12495 {
12496 struct intel_atomic_helper *helper =
12497 &to_i915(state->base.dev)->atomic_helper;
12498
12499 if (llist_add(&state->freed, &helper->free_list))
12500 schedule_work(&helper->free_work);
12501 break;
12502 }
12503 }
12504
12505 return NOTIFY_DONE;
12506 }
12507
12508 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12509 {
12510 struct drm_plane_state *old_plane_state, *new_plane_state;
12511 struct drm_plane *plane;
12512 int i;
12513
12514 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12515 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12516 intel_fb_obj(new_plane_state->fb),
12517 to_intel_plane(plane)->frontbuffer_bit);
12518 }
12519
12520 /**
12521 * intel_atomic_commit - commit validated state object
12522 * @dev: DRM device
12523 * @state: the top-level driver state object
12524 * @nonblock: nonblocking commit
12525 *
12526 * This function commits a top-level state object that has been validated
12527 * with drm_atomic_helper_check().
12528 *
12529 * RETURNS
12530 * Zero for success or -errno.
12531 */
12532 static int intel_atomic_commit(struct drm_device *dev,
12533 struct drm_atomic_state *state,
12534 bool nonblock)
12535 {
12536 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12537 struct drm_i915_private *dev_priv = to_i915(dev);
12538 int ret = 0;
12539
12540 drm_atomic_state_get(state);
12541 i915_sw_fence_init(&intel_state->commit_ready,
12542 intel_atomic_commit_ready);
12543
12544 /*
12545 * The intel_legacy_cursor_update() fast path takes care
12546 * of avoiding the vblank waits for simple cursor
12547 * movement and flips. For cursor on/off and size changes,
12548 * we want to perform the vblank waits so that watermark
12549 * updates happen during the correct frames. Gen9+ have
12550 * double buffered watermarks and so shouldn't need this.
12551 *
12552 * Unset state->legacy_cursor_update before the call to
12553 * drm_atomic_helper_setup_commit() because otherwise
12554 * drm_atomic_helper_wait_for_flip_done() is a noop and
12555 * we get FIFO underruns because we didn't wait
12556 * for vblank.
12557 *
12558 * FIXME doing watermarks and fb cleanup from a vblank worker
12559 * (assuming we had any) would solve these problems.
12560 */
12561 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12562 struct intel_crtc_state *new_crtc_state;
12563 struct intel_crtc *crtc;
12564 int i;
12565
12566 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12567 if (new_crtc_state->wm.need_postvbl_update ||
12568 new_crtc_state->update_wm_post)
12569 state->legacy_cursor_update = false;
12570 }
12571
12572 ret = intel_atomic_prepare_commit(dev, state);
12573 if (ret) {
12574 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12575 i915_sw_fence_commit(&intel_state->commit_ready);
12576 return ret;
12577 }
12578
12579 ret = drm_atomic_helper_setup_commit(state, nonblock);
12580 if (!ret)
12581 ret = drm_atomic_helper_swap_state(state, true);
12582
12583 if (ret) {
12584 i915_sw_fence_commit(&intel_state->commit_ready);
12585
12586 drm_atomic_helper_cleanup_planes(dev, state);
12587 return ret;
12588 }
12589 dev_priv->wm.distrust_bios_wm = false;
12590 intel_shared_dpll_swap_state(state);
12591 intel_atomic_track_fbs(state);
12592
12593 if (intel_state->modeset) {
12594 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12595 sizeof(intel_state->min_cdclk));
12596 memcpy(dev_priv->min_voltage_level,
12597 intel_state->min_voltage_level,
12598 sizeof(intel_state->min_voltage_level));
12599 dev_priv->active_crtcs = intel_state->active_crtcs;
12600 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12601 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12602 }
12603
12604 drm_atomic_state_get(state);
12605 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12606
12607 i915_sw_fence_commit(&intel_state->commit_ready);
12608 if (nonblock)
12609 queue_work(system_unbound_wq, &state->commit_work);
12610 else
12611 intel_atomic_commit_tail(state);
12612
12613
12614 return 0;
12615 }
12616
12617 static const struct drm_crtc_funcs intel_crtc_funcs = {
12618 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12619 .set_config = drm_atomic_helper_set_config,
12620 .destroy = intel_crtc_destroy,
12621 .page_flip = drm_atomic_helper_page_flip,
12622 .atomic_duplicate_state = intel_crtc_duplicate_state,
12623 .atomic_destroy_state = intel_crtc_destroy_state,
12624 .set_crc_source = intel_crtc_set_crc_source,
12625 };
12626
12627 struct wait_rps_boost {
12628 struct wait_queue_entry wait;
12629
12630 struct drm_crtc *crtc;
12631 struct drm_i915_gem_request *request;
12632 };
12633
12634 static int do_rps_boost(struct wait_queue_entry *_wait,
12635 unsigned mode, int sync, void *key)
12636 {
12637 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12638 struct drm_i915_gem_request *rq = wait->request;
12639
12640 gen6_rps_boost(rq, NULL);
12641 i915_gem_request_put(rq);
12642
12643 drm_crtc_vblank_put(wait->crtc);
12644
12645 list_del(&wait->wait.entry);
12646 kfree(wait);
12647 return 1;
12648 }
12649
12650 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12651 struct dma_fence *fence)
12652 {
12653 struct wait_rps_boost *wait;
12654
12655 if (!dma_fence_is_i915(fence))
12656 return;
12657
12658 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12659 return;
12660
12661 if (drm_crtc_vblank_get(crtc))
12662 return;
12663
12664 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12665 if (!wait) {
12666 drm_crtc_vblank_put(crtc);
12667 return;
12668 }
12669
12670 wait->request = to_request(dma_fence_get(fence));
12671 wait->crtc = crtc;
12672
12673 wait->wait.func = do_rps_boost;
12674 wait->wait.flags = 0;
12675
12676 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12677 }
12678
12679 /**
12680 * intel_prepare_plane_fb - Prepare fb for usage on plane
12681 * @plane: drm plane to prepare for
12682 * @fb: framebuffer to prepare for presentation
12683 *
12684 * Prepares a framebuffer for usage on a display plane. Generally this
12685 * involves pinning the underlying object and updating the frontbuffer tracking
12686 * bits. Some older platforms need special physical address handling for
12687 * cursor planes.
12688 *
12689 * Must be called with struct_mutex held.
12690 *
12691 * Returns 0 on success, negative error code on failure.
12692 */
12693 int
12694 intel_prepare_plane_fb(struct drm_plane *plane,
12695 struct drm_plane_state *new_state)
12696 {
12697 struct intel_atomic_state *intel_state =
12698 to_intel_atomic_state(new_state->state);
12699 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12700 struct drm_framebuffer *fb = new_state->fb;
12701 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12702 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12703 int ret;
12704
12705 if (old_obj) {
12706 struct drm_crtc_state *crtc_state =
12707 drm_atomic_get_existing_crtc_state(new_state->state,
12708 plane->state->crtc);
12709
12710 /* Big Hammer, we also need to ensure that any pending
12711 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12712 * current scanout is retired before unpinning the old
12713 * framebuffer. Note that we rely on userspace rendering
12714 * into the buffer attached to the pipe they are waiting
12715 * on. If not, userspace generates a GPU hang with IPEHR
12716 * point to the MI_WAIT_FOR_EVENT.
12717 *
12718 * This should only fail upon a hung GPU, in which case we
12719 * can safely continue.
12720 */
12721 if (needs_modeset(crtc_state)) {
12722 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12723 old_obj->resv, NULL,
12724 false, 0,
12725 GFP_KERNEL);
12726 if (ret < 0)
12727 return ret;
12728 }
12729 }
12730
12731 if (new_state->fence) { /* explicit fencing */
12732 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12733 new_state->fence,
12734 I915_FENCE_TIMEOUT,
12735 GFP_KERNEL);
12736 if (ret < 0)
12737 return ret;
12738 }
12739
12740 if (!obj)
12741 return 0;
12742
12743 ret = i915_gem_object_pin_pages(obj);
12744 if (ret)
12745 return ret;
12746
12747 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12748 if (ret) {
12749 i915_gem_object_unpin_pages(obj);
12750 return ret;
12751 }
12752
12753 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12754 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12755 const int align = intel_cursor_alignment(dev_priv);
12756
12757 ret = i915_gem_object_attach_phys(obj, align);
12758 } else {
12759 struct i915_vma *vma;
12760
12761 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12762 if (!IS_ERR(vma))
12763 to_intel_plane_state(new_state)->vma = vma;
12764 else
12765 ret = PTR_ERR(vma);
12766 }
12767
12768 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12769
12770 mutex_unlock(&dev_priv->drm.struct_mutex);
12771 i915_gem_object_unpin_pages(obj);
12772 if (ret)
12773 return ret;
12774
12775 if (!new_state->fence) { /* implicit fencing */
12776 struct dma_fence *fence;
12777
12778 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12779 obj->resv, NULL,
12780 false, I915_FENCE_TIMEOUT,
12781 GFP_KERNEL);
12782 if (ret < 0)
12783 return ret;
12784
12785 fence = reservation_object_get_excl_rcu(obj->resv);
12786 if (fence) {
12787 add_rps_boost_after_vblank(new_state->crtc, fence);
12788 dma_fence_put(fence);
12789 }
12790 } else {
12791 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12792 }
12793
12794 return 0;
12795 }
12796
12797 /**
12798 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12799 * @plane: drm plane to clean up for
12800 * @fb: old framebuffer that was on plane
12801 *
12802 * Cleans up a framebuffer that has just been removed from a plane.
12803 *
12804 * Must be called with struct_mutex held.
12805 */
12806 void
12807 intel_cleanup_plane_fb(struct drm_plane *plane,
12808 struct drm_plane_state *old_state)
12809 {
12810 struct i915_vma *vma;
12811
12812 /* Should only be called after a successful intel_prepare_plane_fb()! */
12813 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12814 if (vma) {
12815 mutex_lock(&plane->dev->struct_mutex);
12816 intel_unpin_fb_vma(vma);
12817 mutex_unlock(&plane->dev->struct_mutex);
12818 }
12819 }
12820
12821 int
12822 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12823 {
12824 struct drm_i915_private *dev_priv;
12825 int max_scale;
12826 int crtc_clock, max_dotclk;
12827
12828 if (!intel_crtc || !crtc_state->base.enable)
12829 return DRM_PLANE_HELPER_NO_SCALING;
12830
12831 dev_priv = to_i915(intel_crtc->base.dev);
12832
12833 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12834 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12835
12836 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
12837 max_dotclk *= 2;
12838
12839 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12840 return DRM_PLANE_HELPER_NO_SCALING;
12841
12842 /*
12843 * skl max scale is lower of:
12844 * close to 3 but not 3, -1 is for that purpose
12845 * or
12846 * cdclk/crtc_clock
12847 */
12848 max_scale = min((1 << 16) * 3 - 1,
12849 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12850
12851 return max_scale;
12852 }
12853
12854 static int
12855 intel_check_primary_plane(struct intel_plane *plane,
12856 struct intel_crtc_state *crtc_state,
12857 struct intel_plane_state *state)
12858 {
12859 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12860 struct drm_crtc *crtc = state->base.crtc;
12861 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12862 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12863 bool can_position = false;
12864 int ret;
12865
12866 if (INTEL_GEN(dev_priv) >= 9) {
12867 /* use scaler when colorkey is not required */
12868 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12869 min_scale = 1;
12870 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12871 }
12872 can_position = true;
12873 }
12874
12875 ret = drm_atomic_helper_check_plane_state(&state->base,
12876 &crtc_state->base,
12877 &state->clip,
12878 min_scale, max_scale,
12879 can_position, true);
12880 if (ret)
12881 return ret;
12882
12883 if (!state->base.fb)
12884 return 0;
12885
12886 if (INTEL_GEN(dev_priv) >= 9) {
12887 ret = skl_check_plane_surface(state);
12888 if (ret)
12889 return ret;
12890
12891 state->ctl = skl_plane_ctl(crtc_state, state);
12892 } else {
12893 ret = i9xx_check_plane_surface(state);
12894 if (ret)
12895 return ret;
12896
12897 state->ctl = i9xx_plane_ctl(crtc_state, state);
12898 }
12899
12900 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
12901 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
12902
12903 return 0;
12904 }
12905
12906 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12907 struct drm_crtc_state *old_crtc_state)
12908 {
12909 struct drm_device *dev = crtc->dev;
12910 struct drm_i915_private *dev_priv = to_i915(dev);
12911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12912 struct intel_crtc_state *old_intel_cstate =
12913 to_intel_crtc_state(old_crtc_state);
12914 struct intel_atomic_state *old_intel_state =
12915 to_intel_atomic_state(old_crtc_state->state);
12916 struct intel_crtc_state *intel_cstate =
12917 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12918 bool modeset = needs_modeset(&intel_cstate->base);
12919
12920 if (!modeset &&
12921 (intel_cstate->base.color_mgmt_changed ||
12922 intel_cstate->update_pipe)) {
12923 intel_color_set_csc(&intel_cstate->base);
12924 intel_color_load_luts(&intel_cstate->base);
12925 }
12926
12927 /* Perform vblank evasion around commit operation */
12928 intel_pipe_update_start(intel_cstate);
12929
12930 if (modeset)
12931 goto out;
12932
12933 if (intel_cstate->update_pipe)
12934 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12935 else if (INTEL_GEN(dev_priv) >= 9)
12936 skl_detach_scalers(intel_crtc);
12937
12938 out:
12939 if (dev_priv->display.atomic_update_watermarks)
12940 dev_priv->display.atomic_update_watermarks(old_intel_state,
12941 intel_cstate);
12942 }
12943
12944 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12945 struct drm_crtc_state *old_crtc_state)
12946 {
12947 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12949 struct intel_atomic_state *old_intel_state =
12950 to_intel_atomic_state(old_crtc_state->state);
12951 struct intel_crtc_state *new_crtc_state =
12952 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12953
12954 intel_pipe_update_end(new_crtc_state);
12955
12956 if (new_crtc_state->update_pipe &&
12957 !needs_modeset(&new_crtc_state->base) &&
12958 old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED) {
12959 if (!IS_GEN2(dev_priv))
12960 intel_set_cpu_fifo_underrun_reporting(dev_priv, intel_crtc->pipe, true);
12961
12962 if (new_crtc_state->has_pch_encoder) {
12963 enum pipe pch_transcoder =
12964 intel_crtc_pch_transcoder(intel_crtc);
12965
12966 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
12967 }
12968 }
12969 }
12970
12971 /**
12972 * intel_plane_destroy - destroy a plane
12973 * @plane: plane to destroy
12974 *
12975 * Common destruction function for all types of planes (primary, cursor,
12976 * sprite).
12977 */
12978 void intel_plane_destroy(struct drm_plane *plane)
12979 {
12980 drm_plane_cleanup(plane);
12981 kfree(to_intel_plane(plane));
12982 }
12983
12984 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12985 {
12986 switch (format) {
12987 case DRM_FORMAT_C8:
12988 case DRM_FORMAT_RGB565:
12989 case DRM_FORMAT_XRGB1555:
12990 case DRM_FORMAT_XRGB8888:
12991 return modifier == DRM_FORMAT_MOD_LINEAR ||
12992 modifier == I915_FORMAT_MOD_X_TILED;
12993 default:
12994 return false;
12995 }
12996 }
12997
12998 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
12999 {
13000 switch (format) {
13001 case DRM_FORMAT_C8:
13002 case DRM_FORMAT_RGB565:
13003 case DRM_FORMAT_XRGB8888:
13004 case DRM_FORMAT_XBGR8888:
13005 case DRM_FORMAT_XRGB2101010:
13006 case DRM_FORMAT_XBGR2101010:
13007 return modifier == DRM_FORMAT_MOD_LINEAR ||
13008 modifier == I915_FORMAT_MOD_X_TILED;
13009 default:
13010 return false;
13011 }
13012 }
13013
13014 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
13015 {
13016 switch (format) {
13017 case DRM_FORMAT_XRGB8888:
13018 case DRM_FORMAT_XBGR8888:
13019 case DRM_FORMAT_ARGB8888:
13020 case DRM_FORMAT_ABGR8888:
13021 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13022 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13023 return true;
13024 /* fall through */
13025 case DRM_FORMAT_RGB565:
13026 case DRM_FORMAT_XRGB2101010:
13027 case DRM_FORMAT_XBGR2101010:
13028 case DRM_FORMAT_YUYV:
13029 case DRM_FORMAT_YVYU:
13030 case DRM_FORMAT_UYVY:
13031 case DRM_FORMAT_VYUY:
13032 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13033 return true;
13034 /* fall through */
13035 case DRM_FORMAT_C8:
13036 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13037 modifier == I915_FORMAT_MOD_X_TILED ||
13038 modifier == I915_FORMAT_MOD_Y_TILED)
13039 return true;
13040 /* fall through */
13041 default:
13042 return false;
13043 }
13044 }
13045
13046 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
13047 uint32_t format,
13048 uint64_t modifier)
13049 {
13050 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13051
13052 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13053 return false;
13054
13055 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13056 modifier != DRM_FORMAT_MOD_LINEAR)
13057 return false;
13058
13059 if (INTEL_GEN(dev_priv) >= 9)
13060 return skl_mod_supported(format, modifier);
13061 else if (INTEL_GEN(dev_priv) >= 4)
13062 return i965_mod_supported(format, modifier);
13063 else
13064 return i8xx_mod_supported(format, modifier);
13065
13066 unreachable();
13067 }
13068
13069 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
13070 uint32_t format,
13071 uint64_t modifier)
13072 {
13073 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13074 return false;
13075
13076 return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
13077 }
13078
13079 static struct drm_plane_funcs intel_plane_funcs = {
13080 .update_plane = drm_atomic_helper_update_plane,
13081 .disable_plane = drm_atomic_helper_disable_plane,
13082 .destroy = intel_plane_destroy,
13083 .atomic_get_property = intel_plane_atomic_get_property,
13084 .atomic_set_property = intel_plane_atomic_set_property,
13085 .atomic_duplicate_state = intel_plane_duplicate_state,
13086 .atomic_destroy_state = intel_plane_destroy_state,
13087 .format_mod_supported = intel_primary_plane_format_mod_supported,
13088 };
13089
13090 static int
13091 intel_legacy_cursor_update(struct drm_plane *plane,
13092 struct drm_crtc *crtc,
13093 struct drm_framebuffer *fb,
13094 int crtc_x, int crtc_y,
13095 unsigned int crtc_w, unsigned int crtc_h,
13096 uint32_t src_x, uint32_t src_y,
13097 uint32_t src_w, uint32_t src_h,
13098 struct drm_modeset_acquire_ctx *ctx)
13099 {
13100 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13101 int ret;
13102 struct drm_plane_state *old_plane_state, *new_plane_state;
13103 struct intel_plane *intel_plane = to_intel_plane(plane);
13104 struct drm_framebuffer *old_fb;
13105 struct drm_crtc_state *crtc_state = crtc->state;
13106 struct i915_vma *old_vma, *vma;
13107
13108 /*
13109 * When crtc is inactive or there is a modeset pending,
13110 * wait for it to complete in the slowpath
13111 */
13112 if (!crtc_state->active || needs_modeset(crtc_state) ||
13113 to_intel_crtc_state(crtc_state)->update_pipe)
13114 goto slow;
13115
13116 old_plane_state = plane->state;
13117 /*
13118 * Don't do an async update if there is an outstanding commit modifying
13119 * the plane. This prevents our async update's changes from getting
13120 * overridden by a previous synchronous update's state.
13121 */
13122 if (old_plane_state->commit &&
13123 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13124 goto slow;
13125
13126 /*
13127 * If any parameters change that may affect watermarks,
13128 * take the slowpath. Only changing fb or position should be
13129 * in the fastpath.
13130 */
13131 if (old_plane_state->crtc != crtc ||
13132 old_plane_state->src_w != src_w ||
13133 old_plane_state->src_h != src_h ||
13134 old_plane_state->crtc_w != crtc_w ||
13135 old_plane_state->crtc_h != crtc_h ||
13136 !old_plane_state->fb != !fb)
13137 goto slow;
13138
13139 new_plane_state = intel_plane_duplicate_state(plane);
13140 if (!new_plane_state)
13141 return -ENOMEM;
13142
13143 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13144
13145 new_plane_state->src_x = src_x;
13146 new_plane_state->src_y = src_y;
13147 new_plane_state->src_w = src_w;
13148 new_plane_state->src_h = src_h;
13149 new_plane_state->crtc_x = crtc_x;
13150 new_plane_state->crtc_y = crtc_y;
13151 new_plane_state->crtc_w = crtc_w;
13152 new_plane_state->crtc_h = crtc_h;
13153
13154 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13155 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13156 to_intel_plane_state(plane->state),
13157 to_intel_plane_state(new_plane_state));
13158 if (ret)
13159 goto out_free;
13160
13161 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13162 if (ret)
13163 goto out_free;
13164
13165 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13166 int align = intel_cursor_alignment(dev_priv);
13167
13168 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13169 if (ret) {
13170 DRM_DEBUG_KMS("failed to attach phys object\n");
13171 goto out_unlock;
13172 }
13173 } else {
13174 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13175 if (IS_ERR(vma)) {
13176 DRM_DEBUG_KMS("failed to pin object\n");
13177
13178 ret = PTR_ERR(vma);
13179 goto out_unlock;
13180 }
13181
13182 to_intel_plane_state(new_plane_state)->vma = vma;
13183 }
13184
13185 old_fb = old_plane_state->fb;
13186
13187 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13188 intel_plane->frontbuffer_bit);
13189
13190 /* Swap plane state */
13191 plane->state = new_plane_state;
13192
13193 if (plane->state->visible) {
13194 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13195 intel_plane->update_plane(intel_plane,
13196 to_intel_crtc_state(crtc->state),
13197 to_intel_plane_state(plane->state));
13198 } else {
13199 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13200 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13201 }
13202
13203 old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13204 if (old_vma)
13205 intel_unpin_fb_vma(old_vma);
13206
13207 out_unlock:
13208 mutex_unlock(&dev_priv->drm.struct_mutex);
13209 out_free:
13210 if (ret)
13211 intel_plane_destroy_state(plane, new_plane_state);
13212 else
13213 intel_plane_destroy_state(plane, old_plane_state);
13214 return ret;
13215
13216 slow:
13217 return drm_atomic_helper_update_plane(plane, crtc, fb,
13218 crtc_x, crtc_y, crtc_w, crtc_h,
13219 src_x, src_y, src_w, src_h, ctx);
13220 }
13221
13222 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13223 .update_plane = intel_legacy_cursor_update,
13224 .disable_plane = drm_atomic_helper_disable_plane,
13225 .destroy = intel_plane_destroy,
13226 .atomic_get_property = intel_plane_atomic_get_property,
13227 .atomic_set_property = intel_plane_atomic_set_property,
13228 .atomic_duplicate_state = intel_plane_duplicate_state,
13229 .atomic_destroy_state = intel_plane_destroy_state,
13230 .format_mod_supported = intel_cursor_plane_format_mod_supported,
13231 };
13232
13233 static struct intel_plane *
13234 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13235 {
13236 struct intel_plane *primary = NULL;
13237 struct intel_plane_state *state = NULL;
13238 const uint32_t *intel_primary_formats;
13239 unsigned int supported_rotations;
13240 unsigned int num_formats;
13241 const uint64_t *modifiers;
13242 int ret;
13243
13244 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13245 if (!primary) {
13246 ret = -ENOMEM;
13247 goto fail;
13248 }
13249
13250 state = intel_create_plane_state(&primary->base);
13251 if (!state) {
13252 ret = -ENOMEM;
13253 goto fail;
13254 }
13255
13256 primary->base.state = &state->base;
13257
13258 primary->can_scale = false;
13259 primary->max_downscale = 1;
13260 if (INTEL_GEN(dev_priv) >= 9) {
13261 primary->can_scale = true;
13262 state->scaler_id = -1;
13263 }
13264 primary->pipe = pipe;
13265 /*
13266 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13267 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13268 */
13269 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13270 primary->plane = (enum plane) !pipe;
13271 else
13272 primary->plane = (enum plane) pipe;
13273 primary->id = PLANE_PRIMARY;
13274 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13275 primary->check_plane = intel_check_primary_plane;
13276
13277 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13278 intel_primary_formats = skl_primary_formats;
13279 num_formats = ARRAY_SIZE(skl_primary_formats);
13280 modifiers = skl_format_modifiers_ccs;
13281
13282 primary->update_plane = skl_update_plane;
13283 primary->disable_plane = skl_disable_plane;
13284 } else if (INTEL_GEN(dev_priv) >= 9) {
13285 intel_primary_formats = skl_primary_formats;
13286 num_formats = ARRAY_SIZE(skl_primary_formats);
13287 if (pipe < PIPE_C)
13288 modifiers = skl_format_modifiers_ccs;
13289 else
13290 modifiers = skl_format_modifiers_noccs;
13291
13292 primary->update_plane = skl_update_plane;
13293 primary->disable_plane = skl_disable_plane;
13294 } else if (INTEL_GEN(dev_priv) >= 4) {
13295 intel_primary_formats = i965_primary_formats;
13296 num_formats = ARRAY_SIZE(i965_primary_formats);
13297 modifiers = i9xx_format_modifiers;
13298
13299 primary->update_plane = i9xx_update_primary_plane;
13300 primary->disable_plane = i9xx_disable_primary_plane;
13301 } else {
13302 intel_primary_formats = i8xx_primary_formats;
13303 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13304 modifiers = i9xx_format_modifiers;
13305
13306 primary->update_plane = i9xx_update_primary_plane;
13307 primary->disable_plane = i9xx_disable_primary_plane;
13308 }
13309
13310 if (INTEL_GEN(dev_priv) >= 9)
13311 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13312 0, &intel_plane_funcs,
13313 intel_primary_formats, num_formats,
13314 modifiers,
13315 DRM_PLANE_TYPE_PRIMARY,
13316 "plane 1%c", pipe_name(pipe));
13317 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13318 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13319 0, &intel_plane_funcs,
13320 intel_primary_formats, num_formats,
13321 modifiers,
13322 DRM_PLANE_TYPE_PRIMARY,
13323 "primary %c", pipe_name(pipe));
13324 else
13325 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13326 0, &intel_plane_funcs,
13327 intel_primary_formats, num_formats,
13328 modifiers,
13329 DRM_PLANE_TYPE_PRIMARY,
13330 "plane %c", plane_name(primary->plane));
13331 if (ret)
13332 goto fail;
13333
13334 if (INTEL_GEN(dev_priv) >= 9) {
13335 supported_rotations =
13336 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13337 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13338 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13339 supported_rotations =
13340 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13341 DRM_MODE_REFLECT_X;
13342 } else if (INTEL_GEN(dev_priv) >= 4) {
13343 supported_rotations =
13344 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13345 } else {
13346 supported_rotations = DRM_MODE_ROTATE_0;
13347 }
13348
13349 if (INTEL_GEN(dev_priv) >= 4)
13350 drm_plane_create_rotation_property(&primary->base,
13351 DRM_MODE_ROTATE_0,
13352 supported_rotations);
13353
13354 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13355
13356 return primary;
13357
13358 fail:
13359 kfree(state);
13360 kfree(primary);
13361
13362 return ERR_PTR(ret);
13363 }
13364
13365 static struct intel_plane *
13366 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13367 enum pipe pipe)
13368 {
13369 struct intel_plane *cursor = NULL;
13370 struct intel_plane_state *state = NULL;
13371 int ret;
13372
13373 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13374 if (!cursor) {
13375 ret = -ENOMEM;
13376 goto fail;
13377 }
13378
13379 state = intel_create_plane_state(&cursor->base);
13380 if (!state) {
13381 ret = -ENOMEM;
13382 goto fail;
13383 }
13384
13385 cursor->base.state = &state->base;
13386
13387 cursor->can_scale = false;
13388 cursor->max_downscale = 1;
13389 cursor->pipe = pipe;
13390 cursor->plane = pipe;
13391 cursor->id = PLANE_CURSOR;
13392 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13393
13394 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13395 cursor->update_plane = i845_update_cursor;
13396 cursor->disable_plane = i845_disable_cursor;
13397 cursor->check_plane = i845_check_cursor;
13398 } else {
13399 cursor->update_plane = i9xx_update_cursor;
13400 cursor->disable_plane = i9xx_disable_cursor;
13401 cursor->check_plane = i9xx_check_cursor;
13402 }
13403
13404 cursor->cursor.base = ~0;
13405 cursor->cursor.cntl = ~0;
13406
13407 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13408 cursor->cursor.size = ~0;
13409
13410 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13411 0, &intel_cursor_plane_funcs,
13412 intel_cursor_formats,
13413 ARRAY_SIZE(intel_cursor_formats),
13414 cursor_format_modifiers,
13415 DRM_PLANE_TYPE_CURSOR,
13416 "cursor %c", pipe_name(pipe));
13417 if (ret)
13418 goto fail;
13419
13420 if (INTEL_GEN(dev_priv) >= 4)
13421 drm_plane_create_rotation_property(&cursor->base,
13422 DRM_MODE_ROTATE_0,
13423 DRM_MODE_ROTATE_0 |
13424 DRM_MODE_ROTATE_180);
13425
13426 if (INTEL_GEN(dev_priv) >= 9)
13427 state->scaler_id = -1;
13428
13429 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13430
13431 return cursor;
13432
13433 fail:
13434 kfree(state);
13435 kfree(cursor);
13436
13437 return ERR_PTR(ret);
13438 }
13439
13440 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13441 struct intel_crtc_state *crtc_state)
13442 {
13443 struct intel_crtc_scaler_state *scaler_state =
13444 &crtc_state->scaler_state;
13445 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13446 int i;
13447
13448 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13449 if (!crtc->num_scalers)
13450 return;
13451
13452 for (i = 0; i < crtc->num_scalers; i++) {
13453 struct intel_scaler *scaler = &scaler_state->scalers[i];
13454
13455 scaler->in_use = 0;
13456 scaler->mode = PS_SCALER_MODE_DYN;
13457 }
13458
13459 scaler_state->scaler_id = -1;
13460 }
13461
13462 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13463 {
13464 struct intel_crtc *intel_crtc;
13465 struct intel_crtc_state *crtc_state = NULL;
13466 struct intel_plane *primary = NULL;
13467 struct intel_plane *cursor = NULL;
13468 int sprite, ret;
13469
13470 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13471 if (!intel_crtc)
13472 return -ENOMEM;
13473
13474 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13475 if (!crtc_state) {
13476 ret = -ENOMEM;
13477 goto fail;
13478 }
13479 intel_crtc->config = crtc_state;
13480 intel_crtc->base.state = &crtc_state->base;
13481 crtc_state->base.crtc = &intel_crtc->base;
13482
13483 primary = intel_primary_plane_create(dev_priv, pipe);
13484 if (IS_ERR(primary)) {
13485 ret = PTR_ERR(primary);
13486 goto fail;
13487 }
13488 intel_crtc->plane_ids_mask |= BIT(primary->id);
13489
13490 for_each_sprite(dev_priv, pipe, sprite) {
13491 struct intel_plane *plane;
13492
13493 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13494 if (IS_ERR(plane)) {
13495 ret = PTR_ERR(plane);
13496 goto fail;
13497 }
13498 intel_crtc->plane_ids_mask |= BIT(plane->id);
13499 }
13500
13501 cursor = intel_cursor_plane_create(dev_priv, pipe);
13502 if (IS_ERR(cursor)) {
13503 ret = PTR_ERR(cursor);
13504 goto fail;
13505 }
13506 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13507
13508 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13509 &primary->base, &cursor->base,
13510 &intel_crtc_funcs,
13511 "pipe %c", pipe_name(pipe));
13512 if (ret)
13513 goto fail;
13514
13515 intel_crtc->pipe = pipe;
13516 intel_crtc->plane = primary->plane;
13517
13518 /* initialize shared scalers */
13519 intel_crtc_init_scalers(intel_crtc, crtc_state);
13520
13521 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13522 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13523 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13524 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13525
13526 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13527
13528 intel_color_init(&intel_crtc->base);
13529
13530 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13531
13532 return 0;
13533
13534 fail:
13535 /*
13536 * drm_mode_config_cleanup() will free up any
13537 * crtcs/planes already initialized.
13538 */
13539 kfree(crtc_state);
13540 kfree(intel_crtc);
13541
13542 return ret;
13543 }
13544
13545 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13546 {
13547 struct drm_device *dev = connector->base.dev;
13548
13549 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13550
13551 if (!connector->base.state->crtc)
13552 return INVALID_PIPE;
13553
13554 return to_intel_crtc(connector->base.state->crtc)->pipe;
13555 }
13556
13557 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13558 struct drm_file *file)
13559 {
13560 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13561 struct drm_crtc *drmmode_crtc;
13562 struct intel_crtc *crtc;
13563
13564 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13565 if (!drmmode_crtc)
13566 return -ENOENT;
13567
13568 crtc = to_intel_crtc(drmmode_crtc);
13569 pipe_from_crtc_id->pipe = crtc->pipe;
13570
13571 return 0;
13572 }
13573
13574 static int intel_encoder_clones(struct intel_encoder *encoder)
13575 {
13576 struct drm_device *dev = encoder->base.dev;
13577 struct intel_encoder *source_encoder;
13578 int index_mask = 0;
13579 int entry = 0;
13580
13581 for_each_intel_encoder(dev, source_encoder) {
13582 if (encoders_cloneable(encoder, source_encoder))
13583 index_mask |= (1 << entry);
13584
13585 entry++;
13586 }
13587
13588 return index_mask;
13589 }
13590
13591 static bool has_edp_a(struct drm_i915_private *dev_priv)
13592 {
13593 if (!IS_MOBILE(dev_priv))
13594 return false;
13595
13596 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13597 return false;
13598
13599 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13600 return false;
13601
13602 return true;
13603 }
13604
13605 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13606 {
13607 if (INTEL_GEN(dev_priv) >= 9)
13608 return false;
13609
13610 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13611 return false;
13612
13613 if (IS_CHERRYVIEW(dev_priv))
13614 return false;
13615
13616 if (HAS_PCH_LPT_H(dev_priv) &&
13617 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13618 return false;
13619
13620 /* DDI E can't be used if DDI A requires 4 lanes */
13621 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13622 return false;
13623
13624 if (!dev_priv->vbt.int_crt_support)
13625 return false;
13626
13627 return true;
13628 }
13629
13630 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13631 {
13632 int pps_num;
13633 int pps_idx;
13634
13635 if (HAS_DDI(dev_priv))
13636 return;
13637 /*
13638 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13639 * everywhere where registers can be write protected.
13640 */
13641 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13642 pps_num = 2;
13643 else
13644 pps_num = 1;
13645
13646 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13647 u32 val = I915_READ(PP_CONTROL(pps_idx));
13648
13649 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13650 I915_WRITE(PP_CONTROL(pps_idx), val);
13651 }
13652 }
13653
13654 static void intel_pps_init(struct drm_i915_private *dev_priv)
13655 {
13656 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13657 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13658 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13659 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13660 else
13661 dev_priv->pps_mmio_base = PPS_BASE;
13662
13663 intel_pps_unlock_regs_wa(dev_priv);
13664 }
13665
13666 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13667 {
13668 struct intel_encoder *encoder;
13669 bool dpd_is_edp = false;
13670
13671 intel_pps_init(dev_priv);
13672
13673 /*
13674 * intel_edp_init_connector() depends on this completing first, to
13675 * prevent the registeration of both eDP and LVDS and the incorrect
13676 * sharing of the PPS.
13677 */
13678 intel_lvds_init(dev_priv);
13679
13680 if (intel_crt_present(dev_priv))
13681 intel_crt_init(dev_priv);
13682
13683 if (IS_GEN9_LP(dev_priv)) {
13684 /*
13685 * FIXME: Broxton doesn't support port detection via the
13686 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13687 * detect the ports.
13688 */
13689 intel_ddi_init(dev_priv, PORT_A);
13690 intel_ddi_init(dev_priv, PORT_B);
13691 intel_ddi_init(dev_priv, PORT_C);
13692
13693 intel_dsi_init(dev_priv);
13694 } else if (HAS_DDI(dev_priv)) {
13695 int found;
13696
13697 /*
13698 * Haswell uses DDI functions to detect digital outputs.
13699 * On SKL pre-D0 the strap isn't connected, so we assume
13700 * it's there.
13701 */
13702 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13703 /* WaIgnoreDDIAStrap: skl */
13704 if (found || IS_GEN9_BC(dev_priv))
13705 intel_ddi_init(dev_priv, PORT_A);
13706
13707 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13708 * register */
13709 found = I915_READ(SFUSE_STRAP);
13710
13711 if (found & SFUSE_STRAP_DDIB_DETECTED)
13712 intel_ddi_init(dev_priv, PORT_B);
13713 if (found & SFUSE_STRAP_DDIC_DETECTED)
13714 intel_ddi_init(dev_priv, PORT_C);
13715 if (found & SFUSE_STRAP_DDID_DETECTED)
13716 intel_ddi_init(dev_priv, PORT_D);
13717 /*
13718 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13719 */
13720 if (IS_GEN9_BC(dev_priv) &&
13721 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13722 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13723 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13724 intel_ddi_init(dev_priv, PORT_E);
13725
13726 } else if (HAS_PCH_SPLIT(dev_priv)) {
13727 int found;
13728 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13729
13730 if (has_edp_a(dev_priv))
13731 intel_dp_init(dev_priv, DP_A, PORT_A);
13732
13733 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13734 /* PCH SDVOB multiplex with HDMIB */
13735 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13736 if (!found)
13737 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13738 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13739 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13740 }
13741
13742 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13743 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13744
13745 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13746 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13747
13748 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13749 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13750
13751 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13752 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13753 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13754 bool has_edp, has_port;
13755
13756 /*
13757 * The DP_DETECTED bit is the latched state of the DDC
13758 * SDA pin at boot. However since eDP doesn't require DDC
13759 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13760 * eDP ports may have been muxed to an alternate function.
13761 * Thus we can't rely on the DP_DETECTED bit alone to detect
13762 * eDP ports. Consult the VBT as well as DP_DETECTED to
13763 * detect eDP ports.
13764 *
13765 * Sadly the straps seem to be missing sometimes even for HDMI
13766 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13767 * and VBT for the presence of the port. Additionally we can't
13768 * trust the port type the VBT declares as we've seen at least
13769 * HDMI ports that the VBT claim are DP or eDP.
13770 */
13771 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13772 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13773 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13774 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13775 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13776 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13777
13778 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13779 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13780 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13781 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13782 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13783 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13784
13785 if (IS_CHERRYVIEW(dev_priv)) {
13786 /*
13787 * eDP not supported on port D,
13788 * so no need to worry about it
13789 */
13790 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13791 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13792 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13793 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13794 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13795 }
13796
13797 intel_dsi_init(dev_priv);
13798 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13799 bool found = false;
13800
13801 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13802 DRM_DEBUG_KMS("probing SDVOB\n");
13803 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13804 if (!found && IS_G4X(dev_priv)) {
13805 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13806 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13807 }
13808
13809 if (!found && IS_G4X(dev_priv))
13810 intel_dp_init(dev_priv, DP_B, PORT_B);
13811 }
13812
13813 /* Before G4X SDVOC doesn't have its own detect register */
13814
13815 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13816 DRM_DEBUG_KMS("probing SDVOC\n");
13817 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13818 }
13819
13820 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13821
13822 if (IS_G4X(dev_priv)) {
13823 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13824 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13825 }
13826 if (IS_G4X(dev_priv))
13827 intel_dp_init(dev_priv, DP_C, PORT_C);
13828 }
13829
13830 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13831 intel_dp_init(dev_priv, DP_D, PORT_D);
13832 } else if (IS_GEN2(dev_priv))
13833 intel_dvo_init(dev_priv);
13834
13835 if (SUPPORTS_TV(dev_priv))
13836 intel_tv_init(dev_priv);
13837
13838 intel_psr_init(dev_priv);
13839
13840 for_each_intel_encoder(&dev_priv->drm, encoder) {
13841 encoder->base.possible_crtcs = encoder->crtc_mask;
13842 encoder->base.possible_clones =
13843 intel_encoder_clones(encoder);
13844 }
13845
13846 intel_init_pch_refclk(dev_priv);
13847
13848 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13849 }
13850
13851 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13852 {
13853 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13854
13855 drm_framebuffer_cleanup(fb);
13856
13857 i915_gem_object_lock(intel_fb->obj);
13858 WARN_ON(!intel_fb->obj->framebuffer_references--);
13859 i915_gem_object_unlock(intel_fb->obj);
13860
13861 i915_gem_object_put(intel_fb->obj);
13862
13863 kfree(intel_fb);
13864 }
13865
13866 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13867 struct drm_file *file,
13868 unsigned int *handle)
13869 {
13870 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13871 struct drm_i915_gem_object *obj = intel_fb->obj;
13872
13873 if (obj->userptr.mm) {
13874 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13875 return -EINVAL;
13876 }
13877
13878 return drm_gem_handle_create(file, &obj->base, handle);
13879 }
13880
13881 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13882 struct drm_file *file,
13883 unsigned flags, unsigned color,
13884 struct drm_clip_rect *clips,
13885 unsigned num_clips)
13886 {
13887 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13888
13889 i915_gem_object_flush_if_display(obj);
13890 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13891
13892 return 0;
13893 }
13894
13895 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13896 .destroy = intel_user_framebuffer_destroy,
13897 .create_handle = intel_user_framebuffer_create_handle,
13898 .dirty = intel_user_framebuffer_dirty,
13899 };
13900
13901 static
13902 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13903 uint64_t fb_modifier, uint32_t pixel_format)
13904 {
13905 u32 gen = INTEL_GEN(dev_priv);
13906
13907 if (gen >= 9) {
13908 int cpp = drm_format_plane_cpp(pixel_format, 0);
13909
13910 /* "The stride in bytes must not exceed the of the size of 8K
13911 * pixels and 32K bytes."
13912 */
13913 return min(8192 * cpp, 32768);
13914 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13915 return 32*1024;
13916 } else if (gen >= 4) {
13917 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13918 return 16*1024;
13919 else
13920 return 32*1024;
13921 } else if (gen >= 3) {
13922 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13923 return 8*1024;
13924 else
13925 return 16*1024;
13926 } else {
13927 /* XXX DSPC is limited to 4k tiled */
13928 return 8*1024;
13929 }
13930 }
13931
13932 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13933 struct drm_i915_gem_object *obj,
13934 struct drm_mode_fb_cmd2 *mode_cmd)
13935 {
13936 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13937 struct drm_framebuffer *fb = &intel_fb->base;
13938 struct drm_format_name_buf format_name;
13939 u32 pitch_limit;
13940 unsigned int tiling, stride;
13941 int ret = -EINVAL;
13942 int i;
13943
13944 i915_gem_object_lock(obj);
13945 obj->framebuffer_references++;
13946 tiling = i915_gem_object_get_tiling(obj);
13947 stride = i915_gem_object_get_stride(obj);
13948 i915_gem_object_unlock(obj);
13949
13950 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13951 /*
13952 * If there's a fence, enforce that
13953 * the fb modifier and tiling mode match.
13954 */
13955 if (tiling != I915_TILING_NONE &&
13956 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13957 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13958 goto err;
13959 }
13960 } else {
13961 if (tiling == I915_TILING_X) {
13962 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13963 } else if (tiling == I915_TILING_Y) {
13964 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13965 goto err;
13966 }
13967 }
13968
13969 /* Passed in modifier sanity checking. */
13970 switch (mode_cmd->modifier[0]) {
13971 case I915_FORMAT_MOD_Y_TILED_CCS:
13972 case I915_FORMAT_MOD_Yf_TILED_CCS:
13973 switch (mode_cmd->pixel_format) {
13974 case DRM_FORMAT_XBGR8888:
13975 case DRM_FORMAT_ABGR8888:
13976 case DRM_FORMAT_XRGB8888:
13977 case DRM_FORMAT_ARGB8888:
13978 break;
13979 default:
13980 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13981 goto err;
13982 }
13983 /* fall through */
13984 case I915_FORMAT_MOD_Y_TILED:
13985 case I915_FORMAT_MOD_Yf_TILED:
13986 if (INTEL_GEN(dev_priv) < 9) {
13987 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13988 mode_cmd->modifier[0]);
13989 goto err;
13990 }
13991 case DRM_FORMAT_MOD_LINEAR:
13992 case I915_FORMAT_MOD_X_TILED:
13993 break;
13994 default:
13995 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13996 mode_cmd->modifier[0]);
13997 goto err;
13998 }
13999
14000 /*
14001 * gen2/3 display engine uses the fence if present,
14002 * so the tiling mode must match the fb modifier exactly.
14003 */
14004 if (INTEL_INFO(dev_priv)->gen < 4 &&
14005 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14006 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14007 goto err;
14008 }
14009
14010 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14011 mode_cmd->pixel_format);
14012 if (mode_cmd->pitches[0] > pitch_limit) {
14013 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14014 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14015 "tiled" : "linear",
14016 mode_cmd->pitches[0], pitch_limit);
14017 goto err;
14018 }
14019
14020 /*
14021 * If there's a fence, enforce that
14022 * the fb pitch and fence stride match.
14023 */
14024 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14025 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14026 mode_cmd->pitches[0], stride);
14027 goto err;
14028 }
14029
14030 /* Reject formats not supported by any plane early. */
14031 switch (mode_cmd->pixel_format) {
14032 case DRM_FORMAT_C8:
14033 case DRM_FORMAT_RGB565:
14034 case DRM_FORMAT_XRGB8888:
14035 case DRM_FORMAT_ARGB8888:
14036 break;
14037 case DRM_FORMAT_XRGB1555:
14038 if (INTEL_GEN(dev_priv) > 3) {
14039 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14040 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14041 goto err;
14042 }
14043 break;
14044 case DRM_FORMAT_ABGR8888:
14045 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14046 INTEL_GEN(dev_priv) < 9) {
14047 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14048 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14049 goto err;
14050 }
14051 break;
14052 case DRM_FORMAT_XBGR8888:
14053 case DRM_FORMAT_XRGB2101010:
14054 case DRM_FORMAT_XBGR2101010:
14055 if (INTEL_GEN(dev_priv) < 4) {
14056 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14057 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14058 goto err;
14059 }
14060 break;
14061 case DRM_FORMAT_ABGR2101010:
14062 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14063 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14064 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14065 goto err;
14066 }
14067 break;
14068 case DRM_FORMAT_YUYV:
14069 case DRM_FORMAT_UYVY:
14070 case DRM_FORMAT_YVYU:
14071 case DRM_FORMAT_VYUY:
14072 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14073 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14074 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14075 goto err;
14076 }
14077 break;
14078 default:
14079 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14080 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14081 goto err;
14082 }
14083
14084 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14085 if (mode_cmd->offsets[0] != 0)
14086 goto err;
14087
14088 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14089
14090 for (i = 0; i < fb->format->num_planes; i++) {
14091 u32 stride_alignment;
14092
14093 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14094 DRM_DEBUG_KMS("bad plane %d handle\n", i);
14095 goto err;
14096 }
14097
14098 stride_alignment = intel_fb_stride_alignment(fb, i);
14099
14100 /*
14101 * Display WA #0531: skl,bxt,kbl,glk
14102 *
14103 * Render decompression and plane width > 3840
14104 * combined with horizontal panning requires the
14105 * plane stride to be a multiple of 4. We'll just
14106 * require the entire fb to accommodate that to avoid
14107 * potential runtime errors at plane configuration time.
14108 */
14109 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14110 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14111 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14112 stride_alignment *= 4;
14113
14114 if (fb->pitches[i] & (stride_alignment - 1)) {
14115 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14116 i, fb->pitches[i], stride_alignment);
14117 goto err;
14118 }
14119 }
14120
14121 intel_fb->obj = obj;
14122
14123 ret = intel_fill_fb_info(dev_priv, fb);
14124 if (ret)
14125 goto err;
14126
14127 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14128 if (ret) {
14129 DRM_ERROR("framebuffer init failed %d\n", ret);
14130 goto err;
14131 }
14132
14133 return 0;
14134
14135 err:
14136 i915_gem_object_lock(obj);
14137 obj->framebuffer_references--;
14138 i915_gem_object_unlock(obj);
14139 return ret;
14140 }
14141
14142 static struct drm_framebuffer *
14143 intel_user_framebuffer_create(struct drm_device *dev,
14144 struct drm_file *filp,
14145 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14146 {
14147 struct drm_framebuffer *fb;
14148 struct drm_i915_gem_object *obj;
14149 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14150
14151 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14152 if (!obj)
14153 return ERR_PTR(-ENOENT);
14154
14155 fb = intel_framebuffer_create(obj, &mode_cmd);
14156 if (IS_ERR(fb))
14157 i915_gem_object_put(obj);
14158
14159 return fb;
14160 }
14161
14162 static void intel_atomic_state_free(struct drm_atomic_state *state)
14163 {
14164 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14165
14166 drm_atomic_state_default_release(state);
14167
14168 i915_sw_fence_fini(&intel_state->commit_ready);
14169
14170 kfree(state);
14171 }
14172
14173 static const struct drm_mode_config_funcs intel_mode_funcs = {
14174 .fb_create = intel_user_framebuffer_create,
14175 .get_format_info = intel_get_format_info,
14176 .output_poll_changed = intel_fbdev_output_poll_changed,
14177 .atomic_check = intel_atomic_check,
14178 .atomic_commit = intel_atomic_commit,
14179 .atomic_state_alloc = intel_atomic_state_alloc,
14180 .atomic_state_clear = intel_atomic_state_clear,
14181 .atomic_state_free = intel_atomic_state_free,
14182 };
14183
14184 /**
14185 * intel_init_display_hooks - initialize the display modesetting hooks
14186 * @dev_priv: device private
14187 */
14188 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14189 {
14190 intel_init_cdclk_hooks(dev_priv);
14191
14192 if (INTEL_INFO(dev_priv)->gen >= 9) {
14193 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14194 dev_priv->display.get_initial_plane_config =
14195 skylake_get_initial_plane_config;
14196 dev_priv->display.crtc_compute_clock =
14197 haswell_crtc_compute_clock;
14198 dev_priv->display.crtc_enable = haswell_crtc_enable;
14199 dev_priv->display.crtc_disable = haswell_crtc_disable;
14200 } else if (HAS_DDI(dev_priv)) {
14201 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14202 dev_priv->display.get_initial_plane_config =
14203 ironlake_get_initial_plane_config;
14204 dev_priv->display.crtc_compute_clock =
14205 haswell_crtc_compute_clock;
14206 dev_priv->display.crtc_enable = haswell_crtc_enable;
14207 dev_priv->display.crtc_disable = haswell_crtc_disable;
14208 } else if (HAS_PCH_SPLIT(dev_priv)) {
14209 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14210 dev_priv->display.get_initial_plane_config =
14211 ironlake_get_initial_plane_config;
14212 dev_priv->display.crtc_compute_clock =
14213 ironlake_crtc_compute_clock;
14214 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14215 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14216 } else if (IS_CHERRYVIEW(dev_priv)) {
14217 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14218 dev_priv->display.get_initial_plane_config =
14219 i9xx_get_initial_plane_config;
14220 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14221 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14222 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14223 } else if (IS_VALLEYVIEW(dev_priv)) {
14224 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14225 dev_priv->display.get_initial_plane_config =
14226 i9xx_get_initial_plane_config;
14227 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14228 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14229 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14230 } else if (IS_G4X(dev_priv)) {
14231 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14232 dev_priv->display.get_initial_plane_config =
14233 i9xx_get_initial_plane_config;
14234 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14235 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14236 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14237 } else if (IS_PINEVIEW(dev_priv)) {
14238 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14239 dev_priv->display.get_initial_plane_config =
14240 i9xx_get_initial_plane_config;
14241 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14242 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14243 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14244 } else if (!IS_GEN2(dev_priv)) {
14245 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14246 dev_priv->display.get_initial_plane_config =
14247 i9xx_get_initial_plane_config;
14248 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14249 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14250 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14251 } else {
14252 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14253 dev_priv->display.get_initial_plane_config =
14254 i9xx_get_initial_plane_config;
14255 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14256 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14257 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14258 }
14259
14260 if (IS_GEN5(dev_priv)) {
14261 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14262 } else if (IS_GEN6(dev_priv)) {
14263 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14264 } else if (IS_IVYBRIDGE(dev_priv)) {
14265 /* FIXME: detect B0+ stepping and use auto training */
14266 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14267 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14268 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14269 }
14270
14271 if (INTEL_GEN(dev_priv) >= 9)
14272 dev_priv->display.update_crtcs = skl_update_crtcs;
14273 else
14274 dev_priv->display.update_crtcs = intel_update_crtcs;
14275 }
14276
14277 /*
14278 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14279 */
14280 static void quirk_ssc_force_disable(struct drm_device *dev)
14281 {
14282 struct drm_i915_private *dev_priv = to_i915(dev);
14283 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14284 DRM_INFO("applying lvds SSC disable quirk\n");
14285 }
14286
14287 /*
14288 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14289 * brightness value
14290 */
14291 static void quirk_invert_brightness(struct drm_device *dev)
14292 {
14293 struct drm_i915_private *dev_priv = to_i915(dev);
14294 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14295 DRM_INFO("applying inverted panel brightness quirk\n");
14296 }
14297
14298 /* Some VBT's incorrectly indicate no backlight is present */
14299 static void quirk_backlight_present(struct drm_device *dev)
14300 {
14301 struct drm_i915_private *dev_priv = to_i915(dev);
14302 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14303 DRM_INFO("applying backlight present quirk\n");
14304 }
14305
14306 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14307 * which is 300 ms greater than eDP spec T12 min.
14308 */
14309 static void quirk_increase_t12_delay(struct drm_device *dev)
14310 {
14311 struct drm_i915_private *dev_priv = to_i915(dev);
14312
14313 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14314 DRM_INFO("Applying T12 delay quirk\n");
14315 }
14316
14317 struct intel_quirk {
14318 int device;
14319 int subsystem_vendor;
14320 int subsystem_device;
14321 void (*hook)(struct drm_device *dev);
14322 };
14323
14324 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14325 struct intel_dmi_quirk {
14326 void (*hook)(struct drm_device *dev);
14327 const struct dmi_system_id (*dmi_id_list)[];
14328 };
14329
14330 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14331 {
14332 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14333 return 1;
14334 }
14335
14336 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14337 {
14338 .dmi_id_list = &(const struct dmi_system_id[]) {
14339 {
14340 .callback = intel_dmi_reverse_brightness,
14341 .ident = "NCR Corporation",
14342 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14343 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14344 },
14345 },
14346 { } /* terminating entry */
14347 },
14348 .hook = quirk_invert_brightness,
14349 },
14350 };
14351
14352 static struct intel_quirk intel_quirks[] = {
14353 /* Lenovo U160 cannot use SSC on LVDS */
14354 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14355
14356 /* Sony Vaio Y cannot use SSC on LVDS */
14357 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14358
14359 /* Acer Aspire 5734Z must invert backlight brightness */
14360 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14361
14362 /* Acer/eMachines G725 */
14363 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14364
14365 /* Acer/eMachines e725 */
14366 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14367
14368 /* Acer/Packard Bell NCL20 */
14369 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14370
14371 /* Acer Aspire 4736Z */
14372 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14373
14374 /* Acer Aspire 5336 */
14375 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14376
14377 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14378 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14379
14380 /* Acer C720 Chromebook (Core i3 4005U) */
14381 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14382
14383 /* Apple Macbook 2,1 (Core 2 T7400) */
14384 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14385
14386 /* Apple Macbook 4,1 */
14387 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14388
14389 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14390 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14391
14392 /* HP Chromebook 14 (Celeron 2955U) */
14393 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14394
14395 /* Dell Chromebook 11 */
14396 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14397
14398 /* Dell Chromebook 11 (2015 version) */
14399 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14400
14401 /* Toshiba Satellite P50-C-18C */
14402 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14403 };
14404
14405 static void intel_init_quirks(struct drm_device *dev)
14406 {
14407 struct pci_dev *d = dev->pdev;
14408 int i;
14409
14410 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14411 struct intel_quirk *q = &intel_quirks[i];
14412
14413 if (d->device == q->device &&
14414 (d->subsystem_vendor == q->subsystem_vendor ||
14415 q->subsystem_vendor == PCI_ANY_ID) &&
14416 (d->subsystem_device == q->subsystem_device ||
14417 q->subsystem_device == PCI_ANY_ID))
14418 q->hook(dev);
14419 }
14420 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14421 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14422 intel_dmi_quirks[i].hook(dev);
14423 }
14424 }
14425
14426 /* Disable the VGA plane that we never use */
14427 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14428 {
14429 struct pci_dev *pdev = dev_priv->drm.pdev;
14430 u8 sr1;
14431 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14432
14433 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14434 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14435 outb(SR01, VGA_SR_INDEX);
14436 sr1 = inb(VGA_SR_DATA);
14437 outb(sr1 | 1<<5, VGA_SR_DATA);
14438 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14439 udelay(300);
14440
14441 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14442 POSTING_READ(vga_reg);
14443 }
14444
14445 void intel_modeset_init_hw(struct drm_device *dev)
14446 {
14447 struct drm_i915_private *dev_priv = to_i915(dev);
14448
14449 intel_update_cdclk(dev_priv);
14450 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
14451 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14452 }
14453
14454 /*
14455 * Calculate what we think the watermarks should be for the state we've read
14456 * out of the hardware and then immediately program those watermarks so that
14457 * we ensure the hardware settings match our internal state.
14458 *
14459 * We can calculate what we think WM's should be by creating a duplicate of the
14460 * current state (which was constructed during hardware readout) and running it
14461 * through the atomic check code to calculate new watermark values in the
14462 * state object.
14463 */
14464 static void sanitize_watermarks(struct drm_device *dev)
14465 {
14466 struct drm_i915_private *dev_priv = to_i915(dev);
14467 struct drm_atomic_state *state;
14468 struct intel_atomic_state *intel_state;
14469 struct drm_crtc *crtc;
14470 struct drm_crtc_state *cstate;
14471 struct drm_modeset_acquire_ctx ctx;
14472 int ret;
14473 int i;
14474
14475 /* Only supported on platforms that use atomic watermark design */
14476 if (!dev_priv->display.optimize_watermarks)
14477 return;
14478
14479 /*
14480 * We need to hold connection_mutex before calling duplicate_state so
14481 * that the connector loop is protected.
14482 */
14483 drm_modeset_acquire_init(&ctx, 0);
14484 retry:
14485 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14486 if (ret == -EDEADLK) {
14487 drm_modeset_backoff(&ctx);
14488 goto retry;
14489 } else if (WARN_ON(ret)) {
14490 goto fail;
14491 }
14492
14493 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14494 if (WARN_ON(IS_ERR(state)))
14495 goto fail;
14496
14497 intel_state = to_intel_atomic_state(state);
14498
14499 /*
14500 * Hardware readout is the only time we don't want to calculate
14501 * intermediate watermarks (since we don't trust the current
14502 * watermarks).
14503 */
14504 if (!HAS_GMCH_DISPLAY(dev_priv))
14505 intel_state->skip_intermediate_wm = true;
14506
14507 ret = intel_atomic_check(dev, state);
14508 if (ret) {
14509 /*
14510 * If we fail here, it means that the hardware appears to be
14511 * programmed in a way that shouldn't be possible, given our
14512 * understanding of watermark requirements. This might mean a
14513 * mistake in the hardware readout code or a mistake in the
14514 * watermark calculations for a given platform. Raise a WARN
14515 * so that this is noticeable.
14516 *
14517 * If this actually happens, we'll have to just leave the
14518 * BIOS-programmed watermarks untouched and hope for the best.
14519 */
14520 WARN(true, "Could not determine valid watermarks for inherited state\n");
14521 goto put_state;
14522 }
14523
14524 /* Write calculated watermark values back */
14525 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14526 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14527
14528 cs->wm.need_postvbl_update = true;
14529 dev_priv->display.optimize_watermarks(intel_state, cs);
14530
14531 to_intel_crtc_state(crtc->state)->wm = cs->wm;
14532 }
14533
14534 put_state:
14535 drm_atomic_state_put(state);
14536 fail:
14537 drm_modeset_drop_locks(&ctx);
14538 drm_modeset_acquire_fini(&ctx);
14539 }
14540
14541 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
14542 {
14543 if (IS_GEN5(dev_priv)) {
14544 u32 fdi_pll_clk =
14545 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
14546
14547 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
14548 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
14549 dev_priv->fdi_pll_freq = 270000;
14550 } else {
14551 return;
14552 }
14553
14554 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
14555 }
14556
14557 int intel_modeset_init(struct drm_device *dev)
14558 {
14559 struct drm_i915_private *dev_priv = to_i915(dev);
14560 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14561 enum pipe pipe;
14562 struct intel_crtc *crtc;
14563
14564 drm_mode_config_init(dev);
14565
14566 dev->mode_config.min_width = 0;
14567 dev->mode_config.min_height = 0;
14568
14569 dev->mode_config.preferred_depth = 24;
14570 dev->mode_config.prefer_shadow = 1;
14571
14572 dev->mode_config.allow_fb_modifiers = true;
14573
14574 dev->mode_config.funcs = &intel_mode_funcs;
14575
14576 init_llist_head(&dev_priv->atomic_helper.free_list);
14577 INIT_WORK(&dev_priv->atomic_helper.free_work,
14578 intel_atomic_helper_free_state_worker);
14579
14580 intel_init_quirks(dev);
14581
14582 intel_init_pm(dev_priv);
14583
14584 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14585 return 0;
14586
14587 /*
14588 * There may be no VBT; and if the BIOS enabled SSC we can
14589 * just keep using it to avoid unnecessary flicker. Whereas if the
14590 * BIOS isn't using it, don't assume it will work even if the VBT
14591 * indicates as much.
14592 */
14593 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14594 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14595 DREF_SSC1_ENABLE);
14596
14597 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14598 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14599 bios_lvds_use_ssc ? "en" : "dis",
14600 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14601 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14602 }
14603 }
14604
14605 if (IS_GEN2(dev_priv)) {
14606 dev->mode_config.max_width = 2048;
14607 dev->mode_config.max_height = 2048;
14608 } else if (IS_GEN3(dev_priv)) {
14609 dev->mode_config.max_width = 4096;
14610 dev->mode_config.max_height = 4096;
14611 } else {
14612 dev->mode_config.max_width = 8192;
14613 dev->mode_config.max_height = 8192;
14614 }
14615
14616 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14617 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14618 dev->mode_config.cursor_height = 1023;
14619 } else if (IS_GEN2(dev_priv)) {
14620 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14621 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14622 } else {
14623 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14624 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14625 }
14626
14627 dev->mode_config.fb_base = ggtt->mappable_base;
14628
14629 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14630 INTEL_INFO(dev_priv)->num_pipes,
14631 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14632
14633 for_each_pipe(dev_priv, pipe) {
14634 int ret;
14635
14636 ret = intel_crtc_init(dev_priv, pipe);
14637 if (ret) {
14638 drm_mode_config_cleanup(dev);
14639 return ret;
14640 }
14641 }
14642
14643 intel_shared_dpll_init(dev);
14644 intel_update_fdi_pll_freq(dev_priv);
14645
14646 intel_update_czclk(dev_priv);
14647 intel_modeset_init_hw(dev);
14648
14649 if (dev_priv->max_cdclk_freq == 0)
14650 intel_update_max_cdclk(dev_priv);
14651
14652 /* Just disable it once at startup */
14653 i915_disable_vga(dev_priv);
14654 intel_setup_outputs(dev_priv);
14655
14656 drm_modeset_lock_all(dev);
14657 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14658 drm_modeset_unlock_all(dev);
14659
14660 for_each_intel_crtc(dev, crtc) {
14661 struct intel_initial_plane_config plane_config = {};
14662
14663 if (!crtc->active)
14664 continue;
14665
14666 /*
14667 * Note that reserving the BIOS fb up front prevents us
14668 * from stuffing other stolen allocations like the ring
14669 * on top. This prevents some ugliness at boot time, and
14670 * can even allow for smooth boot transitions if the BIOS
14671 * fb is large enough for the active pipe configuration.
14672 */
14673 dev_priv->display.get_initial_plane_config(crtc,
14674 &plane_config);
14675
14676 /*
14677 * If the fb is shared between multiple heads, we'll
14678 * just get the first one.
14679 */
14680 intel_find_initial_plane_obj(crtc, &plane_config);
14681 }
14682
14683 /*
14684 * Make sure hardware watermarks really match the state we read out.
14685 * Note that we need to do this after reconstructing the BIOS fb's
14686 * since the watermark calculation done here will use pstate->fb.
14687 */
14688 if (!HAS_GMCH_DISPLAY(dev_priv))
14689 sanitize_watermarks(dev);
14690
14691 return 0;
14692 }
14693
14694 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14695 {
14696 /* 640x480@60Hz, ~25175 kHz */
14697 struct dpll clock = {
14698 .m1 = 18,
14699 .m2 = 7,
14700 .p1 = 13,
14701 .p2 = 4,
14702 .n = 2,
14703 };
14704 u32 dpll, fp;
14705 int i;
14706
14707 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14708
14709 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14710 pipe_name(pipe), clock.vco, clock.dot);
14711
14712 fp = i9xx_dpll_compute_fp(&clock);
14713 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14714 DPLL_VGA_MODE_DIS |
14715 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14716 PLL_P2_DIVIDE_BY_4 |
14717 PLL_REF_INPUT_DREFCLK |
14718 DPLL_VCO_ENABLE;
14719
14720 I915_WRITE(FP0(pipe), fp);
14721 I915_WRITE(FP1(pipe), fp);
14722
14723 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14724 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14725 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14726 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14727 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14728 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14729 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14730
14731 /*
14732 * Apparently we need to have VGA mode enabled prior to changing
14733 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14734 * dividers, even though the register value does change.
14735 */
14736 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14737 I915_WRITE(DPLL(pipe), dpll);
14738
14739 /* Wait for the clocks to stabilize. */
14740 POSTING_READ(DPLL(pipe));
14741 udelay(150);
14742
14743 /* The pixel multiplier can only be updated once the
14744 * DPLL is enabled and the clocks are stable.
14745 *
14746 * So write it again.
14747 */
14748 I915_WRITE(DPLL(pipe), dpll);
14749
14750 /* We do this three times for luck */
14751 for (i = 0; i < 3 ; i++) {
14752 I915_WRITE(DPLL(pipe), dpll);
14753 POSTING_READ(DPLL(pipe));
14754 udelay(150); /* wait for warmup */
14755 }
14756
14757 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14758 POSTING_READ(PIPECONF(pipe));
14759 }
14760
14761 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14762 {
14763 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14764 pipe_name(pipe));
14765
14766 assert_plane_disabled(dev_priv, PLANE_A);
14767 assert_plane_disabled(dev_priv, PLANE_B);
14768
14769 I915_WRITE(PIPECONF(pipe), 0);
14770 POSTING_READ(PIPECONF(pipe));
14771
14772 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14773 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14774
14775 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14776 POSTING_READ(DPLL(pipe));
14777 }
14778
14779 static bool
14780 intel_check_plane_mapping(struct intel_crtc *crtc)
14781 {
14782 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14783 u32 val;
14784
14785 if (INTEL_INFO(dev_priv)->num_pipes == 1)
14786 return true;
14787
14788 val = I915_READ(DSPCNTR(!crtc->plane));
14789
14790 if ((val & DISPLAY_PLANE_ENABLE) &&
14791 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14792 return false;
14793
14794 return true;
14795 }
14796
14797 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14798 {
14799 struct drm_device *dev = crtc->base.dev;
14800 struct intel_encoder *encoder;
14801
14802 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14803 return true;
14804
14805 return false;
14806 }
14807
14808 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14809 {
14810 struct drm_device *dev = encoder->base.dev;
14811 struct intel_connector *connector;
14812
14813 for_each_connector_on_encoder(dev, &encoder->base, connector)
14814 return connector;
14815
14816 return NULL;
14817 }
14818
14819 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14820 enum pipe pch_transcoder)
14821 {
14822 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14823 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
14824 }
14825
14826 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14827 struct drm_modeset_acquire_ctx *ctx)
14828 {
14829 struct drm_device *dev = crtc->base.dev;
14830 struct drm_i915_private *dev_priv = to_i915(dev);
14831 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14832
14833 /* Clear any frame start delays used for debugging left by the BIOS */
14834 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
14835 i915_reg_t reg = PIPECONF(cpu_transcoder);
14836
14837 I915_WRITE(reg,
14838 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14839 }
14840
14841 /* restore vblank interrupts to correct state */
14842 drm_crtc_vblank_reset(&crtc->base);
14843 if (crtc->active) {
14844 struct intel_plane *plane;
14845
14846 drm_crtc_vblank_on(&crtc->base);
14847
14848 /* Disable everything but the primary plane */
14849 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14850 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14851 continue;
14852
14853 trace_intel_disable_plane(&plane->base, crtc);
14854 plane->disable_plane(plane, crtc);
14855 }
14856 }
14857
14858 /* We need to sanitize the plane -> pipe mapping first because this will
14859 * disable the crtc (and hence change the state) if it is wrong. Note
14860 * that gen4+ has a fixed plane -> pipe mapping. */
14861 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14862 bool plane;
14863
14864 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14865 crtc->base.base.id, crtc->base.name);
14866
14867 /* Pipe has the wrong plane attached and the plane is active.
14868 * Temporarily change the plane mapping and disable everything
14869 * ... */
14870 plane = crtc->plane;
14871 crtc->base.primary->state->visible = true;
14872 crtc->plane = !plane;
14873 intel_crtc_disable_noatomic(&crtc->base, ctx);
14874 crtc->plane = plane;
14875 }
14876
14877 /* Adjust the state of the output pipe according to whether we
14878 * have active connectors/encoders. */
14879 if (crtc->active && !intel_crtc_has_encoders(crtc))
14880 intel_crtc_disable_noatomic(&crtc->base, ctx);
14881
14882 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14883 /*
14884 * We start out with underrun reporting disabled to avoid races.
14885 * For correct bookkeeping mark this on active crtcs.
14886 *
14887 * Also on gmch platforms we dont have any hardware bits to
14888 * disable the underrun reporting. Which means we need to start
14889 * out with underrun reporting disabled also on inactive pipes,
14890 * since otherwise we'll complain about the garbage we read when
14891 * e.g. coming up after runtime pm.
14892 *
14893 * No protection against concurrent access is required - at
14894 * worst a fifo underrun happens which also sets this to false.
14895 */
14896 crtc->cpu_fifo_underrun_disabled = true;
14897 /*
14898 * We track the PCH trancoder underrun reporting state
14899 * within the crtc. With crtc for pipe A housing the underrun
14900 * reporting state for PCH transcoder A, crtc for pipe B housing
14901 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14902 * and marking underrun reporting as disabled for the non-existing
14903 * PCH transcoders B and C would prevent enabling the south
14904 * error interrupt (see cpt_can_enable_serr_int()).
14905 */
14906 if (has_pch_trancoder(dev_priv, crtc->pipe))
14907 crtc->pch_fifo_underrun_disabled = true;
14908 }
14909 }
14910
14911 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14912 {
14913 struct intel_connector *connector;
14914
14915 /* We need to check both for a crtc link (meaning that the
14916 * encoder is active and trying to read from a pipe) and the
14917 * pipe itself being active. */
14918 bool has_active_crtc = encoder->base.crtc &&
14919 to_intel_crtc(encoder->base.crtc)->active;
14920
14921 connector = intel_encoder_find_connector(encoder);
14922 if (connector && !has_active_crtc) {
14923 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14924 encoder->base.base.id,
14925 encoder->base.name);
14926
14927 /* Connector is active, but has no active pipe. This is
14928 * fallout from our resume register restoring. Disable
14929 * the encoder manually again. */
14930 if (encoder->base.crtc) {
14931 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14932
14933 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14934 encoder->base.base.id,
14935 encoder->base.name);
14936 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14937 if (encoder->post_disable)
14938 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14939 }
14940 encoder->base.crtc = NULL;
14941
14942 /* Inconsistent output/port/pipe state happens presumably due to
14943 * a bug in one of the get_hw_state functions. Or someplace else
14944 * in our code, like the register restore mess on resume. Clamp
14945 * things to off as a safer default. */
14946
14947 connector->base.dpms = DRM_MODE_DPMS_OFF;
14948 connector->base.encoder = NULL;
14949 }
14950 /* Enabled encoders without active connectors will be fixed in
14951 * the crtc fixup. */
14952 }
14953
14954 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14955 {
14956 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14957
14958 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14959 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14960 i915_disable_vga(dev_priv);
14961 }
14962 }
14963
14964 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14965 {
14966 /* This function can be called both from intel_modeset_setup_hw_state or
14967 * at a very early point in our resume sequence, where the power well
14968 * structures are not yet restored. Since this function is at a very
14969 * paranoid "someone might have enabled VGA while we were not looking"
14970 * level, just check if the power well is enabled instead of trying to
14971 * follow the "don't touch the power well if we don't need it" policy
14972 * the rest of the driver uses. */
14973 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14974 return;
14975
14976 i915_redisable_vga_power_on(dev_priv);
14977
14978 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14979 }
14980
14981 static bool primary_get_hw_state(struct intel_plane *plane)
14982 {
14983 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14984
14985 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14986 }
14987
14988 /* FIXME read out full plane state for all planes */
14989 static void readout_plane_state(struct intel_crtc *crtc)
14990 {
14991 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14992 bool visible;
14993
14994 visible = crtc->active && primary_get_hw_state(primary);
14995
14996 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14997 to_intel_plane_state(primary->base.state),
14998 visible);
14999 }
15000
15001 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15002 {
15003 struct drm_i915_private *dev_priv = to_i915(dev);
15004 enum pipe pipe;
15005 struct intel_crtc *crtc;
15006 struct intel_encoder *encoder;
15007 struct intel_connector *connector;
15008 struct drm_connector_list_iter conn_iter;
15009 int i;
15010
15011 dev_priv->active_crtcs = 0;
15012
15013 for_each_intel_crtc(dev, crtc) {
15014 struct intel_crtc_state *crtc_state =
15015 to_intel_crtc_state(crtc->base.state);
15016
15017 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15018 memset(crtc_state, 0, sizeof(*crtc_state));
15019 crtc_state->base.crtc = &crtc->base;
15020
15021 crtc_state->base.active = crtc_state->base.enable =
15022 dev_priv->display.get_pipe_config(crtc, crtc_state);
15023
15024 crtc->base.enabled = crtc_state->base.enable;
15025 crtc->active = crtc_state->base.active;
15026
15027 if (crtc_state->base.active)
15028 dev_priv->active_crtcs |= 1 << crtc->pipe;
15029
15030 readout_plane_state(crtc);
15031
15032 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15033 crtc->base.base.id, crtc->base.name,
15034 enableddisabled(crtc_state->base.active));
15035 }
15036
15037 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15038 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15039
15040 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15041 &pll->state.hw_state);
15042 pll->state.crtc_mask = 0;
15043 for_each_intel_crtc(dev, crtc) {
15044 struct intel_crtc_state *crtc_state =
15045 to_intel_crtc_state(crtc->base.state);
15046
15047 if (crtc_state->base.active &&
15048 crtc_state->shared_dpll == pll)
15049 pll->state.crtc_mask |= 1 << crtc->pipe;
15050 }
15051 pll->active_mask = pll->state.crtc_mask;
15052
15053 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15054 pll->name, pll->state.crtc_mask, pll->on);
15055 }
15056
15057 for_each_intel_encoder(dev, encoder) {
15058 pipe = 0;
15059
15060 if (encoder->get_hw_state(encoder, &pipe)) {
15061 struct intel_crtc_state *crtc_state;
15062
15063 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15064 crtc_state = to_intel_crtc_state(crtc->base.state);
15065
15066 encoder->base.crtc = &crtc->base;
15067 encoder->get_config(encoder, crtc_state);
15068 } else {
15069 encoder->base.crtc = NULL;
15070 }
15071
15072 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15073 encoder->base.base.id, encoder->base.name,
15074 enableddisabled(encoder->base.crtc),
15075 pipe_name(pipe));
15076 }
15077
15078 drm_connector_list_iter_begin(dev, &conn_iter);
15079 for_each_intel_connector_iter(connector, &conn_iter) {
15080 if (connector->get_hw_state(connector)) {
15081 connector->base.dpms = DRM_MODE_DPMS_ON;
15082
15083 encoder = connector->encoder;
15084 connector->base.encoder = &encoder->base;
15085
15086 if (encoder->base.crtc &&
15087 encoder->base.crtc->state->active) {
15088 /*
15089 * This has to be done during hardware readout
15090 * because anything calling .crtc_disable may
15091 * rely on the connector_mask being accurate.
15092 */
15093 encoder->base.crtc->state->connector_mask |=
15094 1 << drm_connector_index(&connector->base);
15095 encoder->base.crtc->state->encoder_mask |=
15096 1 << drm_encoder_index(&encoder->base);
15097 }
15098
15099 } else {
15100 connector->base.dpms = DRM_MODE_DPMS_OFF;
15101 connector->base.encoder = NULL;
15102 }
15103 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15104 connector->base.base.id, connector->base.name,
15105 enableddisabled(connector->base.encoder));
15106 }
15107 drm_connector_list_iter_end(&conn_iter);
15108
15109 for_each_intel_crtc(dev, crtc) {
15110 struct intel_crtc_state *crtc_state =
15111 to_intel_crtc_state(crtc->base.state);
15112 int min_cdclk = 0;
15113
15114 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15115 if (crtc_state->base.active) {
15116 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15117 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15118 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15119
15120 /*
15121 * The initial mode needs to be set in order to keep
15122 * the atomic core happy. It wants a valid mode if the
15123 * crtc's enabled, so we do the above call.
15124 *
15125 * But we don't set all the derived state fully, hence
15126 * set a flag to indicate that a full recalculation is
15127 * needed on the next commit.
15128 */
15129 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15130
15131 intel_crtc_compute_pixel_rate(crtc_state);
15132
15133 if (dev_priv->display.modeset_calc_cdclk) {
15134 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15135 if (WARN_ON(min_cdclk < 0))
15136 min_cdclk = 0;
15137 }
15138
15139 drm_calc_timestamping_constants(&crtc->base,
15140 &crtc_state->base.adjusted_mode);
15141 update_scanline_offset(crtc);
15142 }
15143
15144 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15145 dev_priv->min_voltage_level[crtc->pipe] =
15146 crtc_state->min_voltage_level;
15147
15148 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15149 }
15150 }
15151
15152 static void
15153 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15154 {
15155 struct intel_encoder *encoder;
15156
15157 for_each_intel_encoder(&dev_priv->drm, encoder) {
15158 u64 get_domains;
15159 enum intel_display_power_domain domain;
15160
15161 if (!encoder->get_power_domains)
15162 continue;
15163
15164 get_domains = encoder->get_power_domains(encoder);
15165 for_each_power_domain(domain, get_domains)
15166 intel_display_power_get(dev_priv, domain);
15167 }
15168 }
15169
15170 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15171 {
15172 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
15173 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
15174 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
15175 DARBF_GATING_DIS);
15176
15177 if (IS_HASWELL(dev_priv)) {
15178 /*
15179 * WaRsPkgCStateDisplayPMReq:hsw
15180 * System hang if this isn't done before disabling all planes!
15181 */
15182 I915_WRITE(CHICKEN_PAR1_1,
15183 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15184 }
15185 }
15186
15187 /* Scan out the current hw modeset state,
15188 * and sanitizes it to the current state
15189 */
15190 static void
15191 intel_modeset_setup_hw_state(struct drm_device *dev,
15192 struct drm_modeset_acquire_ctx *ctx)
15193 {
15194 struct drm_i915_private *dev_priv = to_i915(dev);
15195 enum pipe pipe;
15196 struct intel_crtc *crtc;
15197 struct intel_encoder *encoder;
15198 int i;
15199
15200 intel_early_display_was(dev_priv);
15201 intel_modeset_readout_hw_state(dev);
15202
15203 /* HW state is read out, now we need to sanitize this mess. */
15204 get_encoder_power_domains(dev_priv);
15205
15206 for_each_intel_encoder(dev, encoder) {
15207 intel_sanitize_encoder(encoder);
15208 }
15209
15210 for_each_pipe(dev_priv, pipe) {
15211 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15212
15213 intel_sanitize_crtc(crtc, ctx);
15214 intel_dump_pipe_config(crtc, crtc->config,
15215 "[setup_hw_state]");
15216 }
15217
15218 intel_modeset_update_connector_atomic_state(dev);
15219
15220 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15221 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15222
15223 if (!pll->on || pll->active_mask)
15224 continue;
15225
15226 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15227
15228 pll->funcs.disable(dev_priv, pll);
15229 pll->on = false;
15230 }
15231
15232 if (IS_G4X(dev_priv)) {
15233 g4x_wm_get_hw_state(dev);
15234 g4x_wm_sanitize(dev_priv);
15235 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15236 vlv_wm_get_hw_state(dev);
15237 vlv_wm_sanitize(dev_priv);
15238 } else if (INTEL_GEN(dev_priv) >= 9) {
15239 skl_wm_get_hw_state(dev);
15240 } else if (HAS_PCH_SPLIT(dev_priv)) {
15241 ilk_wm_get_hw_state(dev);
15242 }
15243
15244 for_each_intel_crtc(dev, crtc) {
15245 u64 put_domains;
15246
15247 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15248 if (WARN_ON(put_domains))
15249 modeset_put_power_domains(dev_priv, put_domains);
15250 }
15251 intel_display_set_init_power(dev_priv, false);
15252
15253 intel_power_domains_verify_state(dev_priv);
15254
15255 intel_fbc_init_pipe_state(dev_priv);
15256 }
15257
15258 void intel_display_resume(struct drm_device *dev)
15259 {
15260 struct drm_i915_private *dev_priv = to_i915(dev);
15261 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15262 struct drm_modeset_acquire_ctx ctx;
15263 int ret;
15264
15265 dev_priv->modeset_restore_state = NULL;
15266 if (state)
15267 state->acquire_ctx = &ctx;
15268
15269 drm_modeset_acquire_init(&ctx, 0);
15270
15271 while (1) {
15272 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15273 if (ret != -EDEADLK)
15274 break;
15275
15276 drm_modeset_backoff(&ctx);
15277 }
15278
15279 if (!ret)
15280 ret = __intel_display_resume(dev, state, &ctx);
15281
15282 intel_enable_ipc(dev_priv);
15283 drm_modeset_drop_locks(&ctx);
15284 drm_modeset_acquire_fini(&ctx);
15285
15286 if (ret)
15287 DRM_ERROR("Restoring old state failed with %i\n", ret);
15288 if (state)
15289 drm_atomic_state_put(state);
15290 }
15291
15292 int intel_connector_register(struct drm_connector *connector)
15293 {
15294 struct intel_connector *intel_connector = to_intel_connector(connector);
15295 int ret;
15296
15297 ret = intel_backlight_device_register(intel_connector);
15298 if (ret)
15299 goto err;
15300
15301 return 0;
15302
15303 err:
15304 return ret;
15305 }
15306
15307 void intel_connector_unregister(struct drm_connector *connector)
15308 {
15309 struct intel_connector *intel_connector = to_intel_connector(connector);
15310
15311 intel_backlight_device_unregister(intel_connector);
15312 intel_panel_destroy_backlight(connector);
15313 }
15314
15315 static void intel_hpd_poll_fini(struct drm_device *dev)
15316 {
15317 struct intel_connector *connector;
15318 struct drm_connector_list_iter conn_iter;
15319
15320 /* First disable polling... */
15321 drm_kms_helper_poll_fini(dev);
15322
15323 /* Then kill the work that may have been queued by hpd. */
15324 drm_connector_list_iter_begin(dev, &conn_iter);
15325 for_each_intel_connector_iter(connector, &conn_iter) {
15326 if (connector->modeset_retry_work.func)
15327 cancel_work_sync(&connector->modeset_retry_work);
15328 }
15329 drm_connector_list_iter_end(&conn_iter);
15330 }
15331
15332 void intel_modeset_cleanup(struct drm_device *dev)
15333 {
15334 struct drm_i915_private *dev_priv = to_i915(dev);
15335
15336 flush_work(&dev_priv->atomic_helper.free_work);
15337 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15338
15339 intel_disable_gt_powersave(dev_priv);
15340
15341 /*
15342 * Interrupts and polling as the first thing to avoid creating havoc.
15343 * Too much stuff here (turning of connectors, ...) would
15344 * experience fancy races otherwise.
15345 */
15346 intel_irq_uninstall(dev_priv);
15347
15348 /*
15349 * Due to the hpd irq storm handling the hotplug work can re-arm the
15350 * poll handlers. Hence disable polling after hpd handling is shut down.
15351 */
15352 intel_hpd_poll_fini(dev);
15353
15354 /* poll work can call into fbdev, hence clean that up afterwards */
15355 intel_fbdev_fini(dev_priv);
15356
15357 intel_unregister_dsm_handler();
15358
15359 intel_fbc_global_disable(dev_priv);
15360
15361 /* flush any delayed tasks or pending work */
15362 flush_scheduled_work();
15363
15364 drm_mode_config_cleanup(dev);
15365
15366 intel_cleanup_overlay(dev_priv);
15367
15368 intel_cleanup_gt_powersave(dev_priv);
15369
15370 intel_teardown_gmbus(dev_priv);
15371 }
15372
15373 void intel_connector_attach_encoder(struct intel_connector *connector,
15374 struct intel_encoder *encoder)
15375 {
15376 connector->encoder = encoder;
15377 drm_mode_connector_attach_encoder(&connector->base,
15378 &encoder->base);
15379 }
15380
15381 /*
15382 * set vga decode state - true == enable VGA decode
15383 */
15384 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15385 {
15386 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15387 u16 gmch_ctrl;
15388
15389 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15390 DRM_ERROR("failed to read control word\n");
15391 return -EIO;
15392 }
15393
15394 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15395 return 0;
15396
15397 if (state)
15398 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15399 else
15400 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15401
15402 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15403 DRM_ERROR("failed to write control word\n");
15404 return -EIO;
15405 }
15406
15407 return 0;
15408 }
15409
15410 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15411
15412 struct intel_display_error_state {
15413
15414 u32 power_well_driver;
15415
15416 int num_transcoders;
15417
15418 struct intel_cursor_error_state {
15419 u32 control;
15420 u32 position;
15421 u32 base;
15422 u32 size;
15423 } cursor[I915_MAX_PIPES];
15424
15425 struct intel_pipe_error_state {
15426 bool power_domain_on;
15427 u32 source;
15428 u32 stat;
15429 } pipe[I915_MAX_PIPES];
15430
15431 struct intel_plane_error_state {
15432 u32 control;
15433 u32 stride;
15434 u32 size;
15435 u32 pos;
15436 u32 addr;
15437 u32 surface;
15438 u32 tile_offset;
15439 } plane[I915_MAX_PIPES];
15440
15441 struct intel_transcoder_error_state {
15442 bool power_domain_on;
15443 enum transcoder cpu_transcoder;
15444
15445 u32 conf;
15446
15447 u32 htotal;
15448 u32 hblank;
15449 u32 hsync;
15450 u32 vtotal;
15451 u32 vblank;
15452 u32 vsync;
15453 } transcoder[4];
15454 };
15455
15456 struct intel_display_error_state *
15457 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15458 {
15459 struct intel_display_error_state *error;
15460 int transcoders[] = {
15461 TRANSCODER_A,
15462 TRANSCODER_B,
15463 TRANSCODER_C,
15464 TRANSCODER_EDP,
15465 };
15466 int i;
15467
15468 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15469 return NULL;
15470
15471 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15472 if (error == NULL)
15473 return NULL;
15474
15475 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15476 error->power_well_driver =
15477 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15478
15479 for_each_pipe(dev_priv, i) {
15480 error->pipe[i].power_domain_on =
15481 __intel_display_power_is_enabled(dev_priv,
15482 POWER_DOMAIN_PIPE(i));
15483 if (!error->pipe[i].power_domain_on)
15484 continue;
15485
15486 error->cursor[i].control = I915_READ(CURCNTR(i));
15487 error->cursor[i].position = I915_READ(CURPOS(i));
15488 error->cursor[i].base = I915_READ(CURBASE(i));
15489
15490 error->plane[i].control = I915_READ(DSPCNTR(i));
15491 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15492 if (INTEL_GEN(dev_priv) <= 3) {
15493 error->plane[i].size = I915_READ(DSPSIZE(i));
15494 error->plane[i].pos = I915_READ(DSPPOS(i));
15495 }
15496 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15497 error->plane[i].addr = I915_READ(DSPADDR(i));
15498 if (INTEL_GEN(dev_priv) >= 4) {
15499 error->plane[i].surface = I915_READ(DSPSURF(i));
15500 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15501 }
15502
15503 error->pipe[i].source = I915_READ(PIPESRC(i));
15504
15505 if (HAS_GMCH_DISPLAY(dev_priv))
15506 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15507 }
15508
15509 /* Note: this does not include DSI transcoders. */
15510 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15511 if (HAS_DDI(dev_priv))
15512 error->num_transcoders++; /* Account for eDP. */
15513
15514 for (i = 0; i < error->num_transcoders; i++) {
15515 enum transcoder cpu_transcoder = transcoders[i];
15516
15517 error->transcoder[i].power_domain_on =
15518 __intel_display_power_is_enabled(dev_priv,
15519 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15520 if (!error->transcoder[i].power_domain_on)
15521 continue;
15522
15523 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15524
15525 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15526 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15527 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15528 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15529 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15530 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15531 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15532 }
15533
15534 return error;
15535 }
15536
15537 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15538
15539 void
15540 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15541 struct intel_display_error_state *error)
15542 {
15543 struct drm_i915_private *dev_priv = m->i915;
15544 int i;
15545
15546 if (!error)
15547 return;
15548
15549 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15550 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15551 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15552 error->power_well_driver);
15553 for_each_pipe(dev_priv, i) {
15554 err_printf(m, "Pipe [%d]:\n", i);
15555 err_printf(m, " Power: %s\n",
15556 onoff(error->pipe[i].power_domain_on));
15557 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15558 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15559
15560 err_printf(m, "Plane [%d]:\n", i);
15561 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15562 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15563 if (INTEL_GEN(dev_priv) <= 3) {
15564 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15565 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15566 }
15567 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15568 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15569 if (INTEL_GEN(dev_priv) >= 4) {
15570 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15571 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15572 }
15573
15574 err_printf(m, "Cursor [%d]:\n", i);
15575 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15576 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15577 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15578 }
15579
15580 for (i = 0; i < error->num_transcoders; i++) {
15581 err_printf(m, "CPU transcoder: %s\n",
15582 transcoder_name(error->transcoder[i].cpu_transcoder));
15583 err_printf(m, " Power: %s\n",
15584 onoff(error->transcoder[i].power_domain_on));
15585 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15586 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15587 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15588 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15589 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15590 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15591 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15592 }
15593 }
15594
15595 #endif
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