2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
45 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
47 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
48 struct intel_crtc_config
*pipe_config
);
49 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
50 struct intel_crtc_config
*pipe_config
);
52 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
53 int x
, int y
, struct drm_framebuffer
*old_fb
);
65 typedef struct intel_limit intel_limit_t
;
67 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 intel_pch_rawclk(struct drm_device
*dev
)
74 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 WARN_ON(!HAS_PCH_SPLIT(dev
));
78 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
81 static inline u32
/* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device
*dev
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac
= {
92 .dot
= { .min
= 25000, .max
= 350000 },
93 .vco
= { .min
= 930000, .max
= 1400000 },
94 .n
= { .min
= 3, .max
= 16 },
95 .m
= { .min
= 96, .max
= 140 },
96 .m1
= { .min
= 18, .max
= 26 },
97 .m2
= { .min
= 6, .max
= 16 },
98 .p
= { .min
= 4, .max
= 128 },
99 .p1
= { .min
= 2, .max
= 33 },
100 .p2
= { .dot_limit
= 165000,
101 .p2_slow
= 4, .p2_fast
= 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo
= {
105 .dot
= { .min
= 25000, .max
= 350000 },
106 .vco
= { .min
= 930000, .max
= 1400000 },
107 .n
= { .min
= 3, .max
= 16 },
108 .m
= { .min
= 96, .max
= 140 },
109 .m1
= { .min
= 18, .max
= 26 },
110 .m2
= { .min
= 6, .max
= 16 },
111 .p
= { .min
= 4, .max
= 128 },
112 .p1
= { .min
= 2, .max
= 33 },
113 .p2
= { .dot_limit
= 165000,
114 .p2_slow
= 4, .p2_fast
= 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds
= {
118 .dot
= { .min
= 25000, .max
= 350000 },
119 .vco
= { .min
= 930000, .max
= 1400000 },
120 .n
= { .min
= 3, .max
= 16 },
121 .m
= { .min
= 96, .max
= 140 },
122 .m1
= { .min
= 18, .max
= 26 },
123 .m2
= { .min
= 6, .max
= 16 },
124 .p
= { .min
= 4, .max
= 128 },
125 .p1
= { .min
= 1, .max
= 6 },
126 .p2
= { .dot_limit
= 165000,
127 .p2_slow
= 14, .p2_fast
= 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo
= {
131 .dot
= { .min
= 20000, .max
= 400000 },
132 .vco
= { .min
= 1400000, .max
= 2800000 },
133 .n
= { .min
= 1, .max
= 6 },
134 .m
= { .min
= 70, .max
= 120 },
135 .m1
= { .min
= 8, .max
= 18 },
136 .m2
= { .min
= 3, .max
= 7 },
137 .p
= { .min
= 5, .max
= 80 },
138 .p1
= { .min
= 1, .max
= 8 },
139 .p2
= { .dot_limit
= 200000,
140 .p2_slow
= 10, .p2_fast
= 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds
= {
144 .dot
= { .min
= 20000, .max
= 400000 },
145 .vco
= { .min
= 1400000, .max
= 2800000 },
146 .n
= { .min
= 1, .max
= 6 },
147 .m
= { .min
= 70, .max
= 120 },
148 .m1
= { .min
= 8, .max
= 18 },
149 .m2
= { .min
= 3, .max
= 7 },
150 .p
= { .min
= 7, .max
= 98 },
151 .p1
= { .min
= 1, .max
= 8 },
152 .p2
= { .dot_limit
= 112000,
153 .p2_slow
= 14, .p2_fast
= 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo
= {
158 .dot
= { .min
= 25000, .max
= 270000 },
159 .vco
= { .min
= 1750000, .max
= 3500000},
160 .n
= { .min
= 1, .max
= 4 },
161 .m
= { .min
= 104, .max
= 138 },
162 .m1
= { .min
= 17, .max
= 23 },
163 .m2
= { .min
= 5, .max
= 11 },
164 .p
= { .min
= 10, .max
= 30 },
165 .p1
= { .min
= 1, .max
= 3},
166 .p2
= { .dot_limit
= 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi
= {
173 .dot
= { .min
= 22000, .max
= 400000 },
174 .vco
= { .min
= 1750000, .max
= 3500000},
175 .n
= { .min
= 1, .max
= 4 },
176 .m
= { .min
= 104, .max
= 138 },
177 .m1
= { .min
= 16, .max
= 23 },
178 .m2
= { .min
= 5, .max
= 11 },
179 .p
= { .min
= 5, .max
= 80 },
180 .p1
= { .min
= 1, .max
= 8},
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 10, .p2_fast
= 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
186 .dot
= { .min
= 20000, .max
= 115000 },
187 .vco
= { .min
= 1750000, .max
= 3500000 },
188 .n
= { .min
= 1, .max
= 3 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 17, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 28, .max
= 112 },
193 .p1
= { .min
= 2, .max
= 8 },
194 .p2
= { .dot_limit
= 0,
195 .p2_slow
= 14, .p2_fast
= 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
200 .dot
= { .min
= 80000, .max
= 224000 },
201 .vco
= { .min
= 1750000, .max
= 3500000 },
202 .n
= { .min
= 1, .max
= 3 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 17, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 14, .max
= 42 },
207 .p1
= { .min
= 2, .max
= 6 },
208 .p2
= { .dot_limit
= 0,
209 .p2_slow
= 7, .p2_fast
= 7
213 static const intel_limit_t intel_limits_pineview_sdvo
= {
214 .dot
= { .min
= 20000, .max
= 400000},
215 .vco
= { .min
= 1700000, .max
= 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n
= { .min
= 3, .max
= 6 },
218 .m
= { .min
= 2, .max
= 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1
= { .min
= 0, .max
= 0 },
221 .m2
= { .min
= 0, .max
= 254 },
222 .p
= { .min
= 5, .max
= 80 },
223 .p1
= { .min
= 1, .max
= 8 },
224 .p2
= { .dot_limit
= 200000,
225 .p2_slow
= 10, .p2_fast
= 5 },
228 static const intel_limit_t intel_limits_pineview_lvds
= {
229 .dot
= { .min
= 20000, .max
= 400000 },
230 .vco
= { .min
= 1700000, .max
= 3500000 },
231 .n
= { .min
= 3, .max
= 6 },
232 .m
= { .min
= 2, .max
= 256 },
233 .m1
= { .min
= 0, .max
= 0 },
234 .m2
= { .min
= 0, .max
= 254 },
235 .p
= { .min
= 7, .max
= 112 },
236 .p1
= { .min
= 1, .max
= 8 },
237 .p2
= { .dot_limit
= 112000,
238 .p2_slow
= 14, .p2_fast
= 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac
= {
247 .dot
= { .min
= 25000, .max
= 350000 },
248 .vco
= { .min
= 1760000, .max
= 3510000 },
249 .n
= { .min
= 1, .max
= 5 },
250 .m
= { .min
= 79, .max
= 127 },
251 .m1
= { .min
= 12, .max
= 22 },
252 .m2
= { .min
= 5, .max
= 9 },
253 .p
= { .min
= 5, .max
= 80 },
254 .p1
= { .min
= 1, .max
= 8 },
255 .p2
= { .dot_limit
= 225000,
256 .p2_slow
= 10, .p2_fast
= 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
260 .dot
= { .min
= 25000, .max
= 350000 },
261 .vco
= { .min
= 1760000, .max
= 3510000 },
262 .n
= { .min
= 1, .max
= 3 },
263 .m
= { .min
= 79, .max
= 118 },
264 .m1
= { .min
= 12, .max
= 22 },
265 .m2
= { .min
= 5, .max
= 9 },
266 .p
= { .min
= 28, .max
= 112 },
267 .p1
= { .min
= 2, .max
= 8 },
268 .p2
= { .dot_limit
= 225000,
269 .p2_slow
= 14, .p2_fast
= 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 1760000, .max
= 3510000 },
275 .n
= { .min
= 1, .max
= 3 },
276 .m
= { .min
= 79, .max
= 127 },
277 .m1
= { .min
= 12, .max
= 22 },
278 .m2
= { .min
= 5, .max
= 9 },
279 .p
= { .min
= 14, .max
= 56 },
280 .p1
= { .min
= 2, .max
= 8 },
281 .p2
= { .dot_limit
= 225000,
282 .p2_slow
= 7, .p2_fast
= 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
287 .dot
= { .min
= 25000, .max
= 350000 },
288 .vco
= { .min
= 1760000, .max
= 3510000 },
289 .n
= { .min
= 1, .max
= 2 },
290 .m
= { .min
= 79, .max
= 126 },
291 .m1
= { .min
= 12, .max
= 22 },
292 .m2
= { .min
= 5, .max
= 9 },
293 .p
= { .min
= 28, .max
= 112 },
294 .p1
= { .min
= 2, .max
= 8 },
295 .p2
= { .dot_limit
= 225000,
296 .p2_slow
= 14, .p2_fast
= 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
300 .dot
= { .min
= 25000, .max
= 350000 },
301 .vco
= { .min
= 1760000, .max
= 3510000 },
302 .n
= { .min
= 1, .max
= 3 },
303 .m
= { .min
= 79, .max
= 126 },
304 .m1
= { .min
= 12, .max
= 22 },
305 .m2
= { .min
= 5, .max
= 9 },
306 .p
= { .min
= 14, .max
= 42 },
307 .p1
= { .min
= 2, .max
= 6 },
308 .p2
= { .dot_limit
= 225000,
309 .p2_slow
= 7, .p2_fast
= 7 },
312 static const intel_limit_t intel_limits_vlv_dac
= {
313 .dot
= { .min
= 25000, .max
= 270000 },
314 .vco
= { .min
= 4000000, .max
= 6000000 },
315 .n
= { .min
= 1, .max
= 7 },
316 .m
= { .min
= 22, .max
= 450 }, /* guess */
317 .m1
= { .min
= 2, .max
= 3 },
318 .m2
= { .min
= 11, .max
= 156 },
319 .p
= { .min
= 10, .max
= 30 },
320 .p1
= { .min
= 1, .max
= 3 },
321 .p2
= { .dot_limit
= 270000,
322 .p2_slow
= 2, .p2_fast
= 20 },
325 static const intel_limit_t intel_limits_vlv_hdmi
= {
326 .dot
= { .min
= 25000, .max
= 270000 },
327 .vco
= { .min
= 4000000, .max
= 6000000 },
328 .n
= { .min
= 1, .max
= 7 },
329 .m
= { .min
= 60, .max
= 300 }, /* guess */
330 .m1
= { .min
= 2, .max
= 3 },
331 .m2
= { .min
= 11, .max
= 156 },
332 .p
= { .min
= 10, .max
= 30 },
333 .p1
= { .min
= 2, .max
= 3 },
334 .p2
= { .dot_limit
= 270000,
335 .p2_slow
= 2, .p2_fast
= 20 },
339 * Returns whether any output on the specified pipe is of the specified type
341 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
343 struct drm_device
*dev
= crtc
->dev
;
344 struct intel_encoder
*encoder
;
346 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
347 if (encoder
->type
== type
)
353 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
356 struct drm_device
*dev
= crtc
->dev
;
357 const intel_limit_t
*limit
;
359 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
360 if (intel_is_dual_link_lvds(dev
)) {
361 if (refclk
== 100000)
362 limit
= &intel_limits_ironlake_dual_lvds_100m
;
364 limit
= &intel_limits_ironlake_dual_lvds
;
366 if (refclk
== 100000)
367 limit
= &intel_limits_ironlake_single_lvds_100m
;
369 limit
= &intel_limits_ironlake_single_lvds
;
372 limit
= &intel_limits_ironlake_dac
;
377 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
379 struct drm_device
*dev
= crtc
->dev
;
380 const intel_limit_t
*limit
;
382 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
383 if (intel_is_dual_link_lvds(dev
))
384 limit
= &intel_limits_g4x_dual_channel_lvds
;
386 limit
= &intel_limits_g4x_single_channel_lvds
;
387 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
388 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
389 limit
= &intel_limits_g4x_hdmi
;
390 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
391 limit
= &intel_limits_g4x_sdvo
;
392 } else /* The option is for other outputs */
393 limit
= &intel_limits_i9xx_sdvo
;
398 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
400 struct drm_device
*dev
= crtc
->dev
;
401 const intel_limit_t
*limit
;
403 if (HAS_PCH_SPLIT(dev
))
404 limit
= intel_ironlake_limit(crtc
, refclk
);
405 else if (IS_G4X(dev
)) {
406 limit
= intel_g4x_limit(crtc
);
407 } else if (IS_PINEVIEW(dev
)) {
408 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
409 limit
= &intel_limits_pineview_lvds
;
411 limit
= &intel_limits_pineview_sdvo
;
412 } else if (IS_VALLEYVIEW(dev
)) {
413 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
414 limit
= &intel_limits_vlv_dac
;
416 limit
= &intel_limits_vlv_hdmi
;
417 } else if (!IS_GEN2(dev
)) {
418 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
419 limit
= &intel_limits_i9xx_lvds
;
421 limit
= &intel_limits_i9xx_sdvo
;
423 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
424 limit
= &intel_limits_i8xx_lvds
;
425 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
426 limit
= &intel_limits_i8xx_dvo
;
428 limit
= &intel_limits_i8xx_dac
;
433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
434 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
436 clock
->m
= clock
->m2
+ 2;
437 clock
->p
= clock
->p1
* clock
->p2
;
438 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
439 clock
->dot
= clock
->vco
/ clock
->p
;
442 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
444 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
447 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
449 clock
->m
= i9xx_dpll_compute_m(clock
);
450 clock
->p
= clock
->p1
* clock
->p2
;
451 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
452 clock
->dot
= clock
->vco
/ clock
->p
;
455 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
461 static bool intel_PLL_is_valid(struct drm_device
*dev
,
462 const intel_limit_t
*limit
,
463 const intel_clock_t
*clock
)
465 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
466 INTELPllInvalid("p1 out of range\n");
467 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
468 INTELPllInvalid("p out of range\n");
469 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
470 INTELPllInvalid("m2 out of range\n");
471 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
472 INTELPllInvalid("m1 out of range\n");
473 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
474 INTELPllInvalid("m1 <= m2\n");
475 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
476 INTELPllInvalid("m out of range\n");
477 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
478 INTELPllInvalid("n out of range\n");
479 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
480 INTELPllInvalid("vco out of range\n");
481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
484 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
485 INTELPllInvalid("dot out of range\n");
491 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
492 int target
, int refclk
, intel_clock_t
*match_clock
,
493 intel_clock_t
*best_clock
)
495 struct drm_device
*dev
= crtc
->dev
;
499 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
505 if (intel_is_dual_link_lvds(dev
))
506 clock
.p2
= limit
->p2
.p2_fast
;
508 clock
.p2
= limit
->p2
.p2_slow
;
510 if (target
< limit
->p2
.dot_limit
)
511 clock
.p2
= limit
->p2
.p2_slow
;
513 clock
.p2
= limit
->p2
.p2_fast
;
516 memset(best_clock
, 0, sizeof(*best_clock
));
518 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
520 for (clock
.m2
= limit
->m2
.min
;
521 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
522 if (clock
.m2
>= clock
.m1
)
524 for (clock
.n
= limit
->n
.min
;
525 clock
.n
<= limit
->n
.max
; clock
.n
++) {
526 for (clock
.p1
= limit
->p1
.min
;
527 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
530 i9xx_clock(refclk
, &clock
);
531 if (!intel_PLL_is_valid(dev
, limit
,
535 clock
.p
!= match_clock
->p
)
538 this_err
= abs(clock
.dot
- target
);
539 if (this_err
< err
) {
548 return (err
!= target
);
552 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
553 int target
, int refclk
, intel_clock_t
*match_clock
,
554 intel_clock_t
*best_clock
)
556 struct drm_device
*dev
= crtc
->dev
;
560 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
566 if (intel_is_dual_link_lvds(dev
))
567 clock
.p2
= limit
->p2
.p2_fast
;
569 clock
.p2
= limit
->p2
.p2_slow
;
571 if (target
< limit
->p2
.dot_limit
)
572 clock
.p2
= limit
->p2
.p2_slow
;
574 clock
.p2
= limit
->p2
.p2_fast
;
577 memset(best_clock
, 0, sizeof(*best_clock
));
579 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
581 for (clock
.m2
= limit
->m2
.min
;
582 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
583 for (clock
.n
= limit
->n
.min
;
584 clock
.n
<= limit
->n
.max
; clock
.n
++) {
585 for (clock
.p1
= limit
->p1
.min
;
586 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
589 pineview_clock(refclk
, &clock
);
590 if (!intel_PLL_is_valid(dev
, limit
,
594 clock
.p
!= match_clock
->p
)
597 this_err
= abs(clock
.dot
- target
);
598 if (this_err
< err
) {
607 return (err
!= target
);
611 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
612 int target
, int refclk
, intel_clock_t
*match_clock
,
613 intel_clock_t
*best_clock
)
615 struct drm_device
*dev
= crtc
->dev
;
619 /* approximately equals target * 0.00585 */
620 int err_most
= (target
>> 8) + (target
>> 9);
623 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
624 if (intel_is_dual_link_lvds(dev
))
625 clock
.p2
= limit
->p2
.p2_fast
;
627 clock
.p2
= limit
->p2
.p2_slow
;
629 if (target
< limit
->p2
.dot_limit
)
630 clock
.p2
= limit
->p2
.p2_slow
;
632 clock
.p2
= limit
->p2
.p2_fast
;
635 memset(best_clock
, 0, sizeof(*best_clock
));
636 max_n
= limit
->n
.max
;
637 /* based on hardware requirement, prefer smaller n to precision */
638 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
639 /* based on hardware requirement, prefere larger m1,m2 */
640 for (clock
.m1
= limit
->m1
.max
;
641 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
642 for (clock
.m2
= limit
->m2
.max
;
643 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
644 for (clock
.p1
= limit
->p1
.max
;
645 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
648 i9xx_clock(refclk
, &clock
);
649 if (!intel_PLL_is_valid(dev
, limit
,
653 this_err
= abs(clock
.dot
- target
);
654 if (this_err
< err_most
) {
668 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
669 int target
, int refclk
, intel_clock_t
*match_clock
,
670 intel_clock_t
*best_clock
)
672 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
674 u32 updrate
, minupdate
, p
;
675 unsigned long bestppm
, ppm
, absppm
;
679 dotclk
= target
* 1000;
682 fastclk
= dotclk
/ (2*100);
685 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
686 bestm1
= bestm2
= bestp1
= bestp2
= 0;
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
690 updrate
= refclk
/ n
;
691 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
692 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
698 m2
= DIV_ROUND_CLOSEST(fastclk
* p
* n
, refclk
* m1
);
702 if (vco
< limit
->vco
.min
|| vco
>= limit
->vco
.max
)
705 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
706 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
707 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
711 if (absppm
< bestppm
- 10) {
727 best_clock
->n
= bestn
;
728 best_clock
->m1
= bestm1
;
729 best_clock
->m2
= bestm2
;
730 best_clock
->p1
= bestp1
;
731 best_clock
->p2
= bestp2
;
736 bool intel_crtc_active(struct drm_crtc
*crtc
)
738 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
743 * We can ditch the adjusted_mode.crtc_clock check as soon
744 * as Haswell has gained clock readout/fastboot support.
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
749 return intel_crtc
->active
&& crtc
->fb
&&
750 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
753 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
756 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
757 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
759 return intel_crtc
->config
.cpu_transcoder
;
762 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
765 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
767 frame
= I915_READ(frame_reg
);
769 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
774 * intel_wait_for_vblank - wait for vblank on a given pipe
776 * @pipe: pipe to wait for
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
781 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
784 int pipestat_reg
= PIPESTAT(pipe
);
786 if (INTEL_INFO(dev
)->gen
>= 5) {
787 ironlake_wait_for_vblank(dev
, pipe
);
791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
804 I915_WRITE(pipestat_reg
,
805 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
807 /* Wait for vblank interrupt bit to set */
808 if (wait_for(I915_READ(pipestat_reg
) &
809 PIPE_VBLANK_INTERRUPT_STATUS
,
811 DRM_DEBUG_KMS("vblank wait timed out\n");
815 * intel_wait_for_pipe_off - wait for pipe to turn off
817 * @pipe: pipe to wait for
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
824 * wait for the pipe register state bit to turn off
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
831 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
834 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
837 if (INTEL_INFO(dev
)->gen
>= 4) {
838 int reg
= PIPECONF(cpu_transcoder
);
840 /* Wait for the Pipe State to go off */
841 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
843 WARN(1, "pipe_off wait timed out\n");
845 u32 last_line
, line_mask
;
846 int reg
= PIPEDSL(pipe
);
847 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
850 line_mask
= DSL_LINEMASK_GEN2
;
852 line_mask
= DSL_LINEMASK_GEN3
;
854 /* Wait for the display line to settle */
856 last_line
= I915_READ(reg
) & line_mask
;
858 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
859 time_after(timeout
, jiffies
));
860 if (time_after(jiffies
, timeout
))
861 WARN(1, "pipe_off wait timed out\n");
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
870 * Returns true if @port is connected, false otherwise.
872 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
873 struct intel_digital_port
*port
)
877 if (HAS_PCH_IBX(dev_priv
->dev
)) {
880 bit
= SDE_PORTB_HOTPLUG
;
883 bit
= SDE_PORTC_HOTPLUG
;
886 bit
= SDE_PORTD_HOTPLUG
;
894 bit
= SDE_PORTB_HOTPLUG_CPT
;
897 bit
= SDE_PORTC_HOTPLUG_CPT
;
900 bit
= SDE_PORTD_HOTPLUG_CPT
;
907 return I915_READ(SDEISR
) & bit
;
910 static const char *state_string(bool enabled
)
912 return enabled
? "on" : "off";
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private
*dev_priv
,
917 enum pipe pipe
, bool state
)
924 val
= I915_READ(reg
);
925 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
926 WARN(cur_state
!= state
,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state
), state_string(cur_state
));
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
937 mutex_lock(&dev_priv
->dpio_lock
);
938 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
939 mutex_unlock(&dev_priv
->dpio_lock
);
941 cur_state
= val
& DSI_PLL_VCO_EN
;
942 WARN(cur_state
!= state
,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state
), state_string(cur_state
));
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949 struct intel_shared_dpll
*
950 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
952 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
954 if (crtc
->config
.shared_dpll
< 0)
957 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
961 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
962 struct intel_shared_dpll
*pll
,
966 struct intel_dpll_hw_state hw_state
;
968 if (HAS_PCH_LPT(dev_priv
->dev
)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
974 "asserting DPLL %s with no DPLL\n", state_string(state
)))
977 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
978 WARN(cur_state
!= state
,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll
->name
, state_string(state
), state_string(cur_state
));
983 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
984 enum pipe pipe
, bool state
)
989 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
992 if (HAS_DDI(dev_priv
->dev
)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
995 val
= I915_READ(reg
);
996 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
998 reg
= FDI_TX_CTL(pipe
);
999 val
= I915_READ(reg
);
1000 cur_state
= !!(val
& FDI_TX_ENABLE
);
1002 WARN(cur_state
!= state
,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state
), state_string(cur_state
));
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1010 enum pipe pipe
, bool state
)
1016 reg
= FDI_RX_CTL(pipe
);
1017 val
= I915_READ(reg
);
1018 cur_state
= !!(val
& FDI_RX_ENABLE
);
1019 WARN(cur_state
!= state
,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state
), state_string(cur_state
));
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv
->info
->gen
== 5)
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv
->dev
))
1040 reg
= FDI_TX_CTL(pipe
);
1041 val
= I915_READ(reg
);
1042 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1045 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1046 enum pipe pipe
, bool state
)
1052 reg
= FDI_RX_CTL(pipe
);
1053 val
= I915_READ(reg
);
1054 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1055 WARN(cur_state
!= state
,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state
), state_string(cur_state
));
1060 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1063 int pp_reg
, lvds_reg
;
1065 enum pipe panel_pipe
= PIPE_A
;
1068 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1069 pp_reg
= PCH_PP_CONTROL
;
1070 lvds_reg
= PCH_LVDS
;
1072 pp_reg
= PP_CONTROL
;
1076 val
= I915_READ(pp_reg
);
1077 if (!(val
& PANEL_POWER_ON
) ||
1078 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1081 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1082 panel_pipe
= PIPE_B
;
1084 WARN(panel_pipe
== pipe
&& locked
,
1085 "panel assertion failure, pipe %c regs locked\n",
1089 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1090 enum pipe pipe
, bool state
)
1092 struct drm_device
*dev
= dev_priv
->dev
;
1095 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1096 cur_state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
1097 else if (IS_845G(dev
) || IS_I865G(dev
))
1098 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1100 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1102 WARN(cur_state
!= state
,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1109 void assert_pipe(struct drm_i915_private
*dev_priv
,
1110 enum pipe pipe
, bool state
)
1115 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1122 if (!intel_display_power_enabled(dev_priv
->dev
,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1126 reg
= PIPECONF(cpu_transcoder
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& PIPECONF_ENABLE
);
1131 WARN(cur_state
!= state
,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1136 static void assert_plane(struct drm_i915_private
*dev_priv
,
1137 enum plane plane
, bool state
)
1143 reg
= DSPCNTR(plane
);
1144 val
= I915_READ(reg
);
1145 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1146 WARN(cur_state
!= state
,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane
), state_string(state
), state_string(cur_state
));
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1154 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1157 struct drm_device
*dev
= dev_priv
->dev
;
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev
)->gen
>= 4) {
1164 reg
= DSPCNTR(pipe
);
1165 val
= I915_READ(reg
);
1166 WARN((val
& DISPLAY_PLANE_ENABLE
),
1167 "plane %c assertion failure, should be disabled but not\n",
1172 /* Need to check both planes against the pipe */
1175 val
= I915_READ(reg
);
1176 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1177 DISPPLANE_SEL_PIPE_SHIFT
;
1178 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i
), pipe_name(pipe
));
1184 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1187 struct drm_device
*dev
= dev_priv
->dev
;
1191 if (IS_VALLEYVIEW(dev
)) {
1192 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1193 reg
= SPCNTR(pipe
, i
);
1194 val
= I915_READ(reg
);
1195 WARN((val
& SP_ENABLE
),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe
, i
), pipe_name(pipe
));
1199 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1201 val
= I915_READ(reg
);
1202 WARN((val
& SPRITE_ENABLE
),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe
), pipe_name(pipe
));
1205 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1206 reg
= DVSCNTR(pipe
);
1207 val
= I915_READ(reg
);
1208 WARN((val
& DVS_ENABLE
),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe
), pipe_name(pipe
));
1214 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1219 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1224 val
= I915_READ(PCH_DREF_CONTROL
);
1225 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1226 DREF_SUPERSPREAD_SOURCE_MASK
));
1227 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1237 reg
= PCH_TRANSCONF(pipe
);
1238 val
= I915_READ(reg
);
1239 enabled
= !!(val
& TRANS_ENABLE
);
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1245 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1246 enum pipe pipe
, u32 port_sel
, u32 val
)
1248 if ((val
& DP_PORT_EN
) == 0)
1251 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1252 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1253 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1254 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1257 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1263 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1264 enum pipe pipe
, u32 val
)
1266 if ((val
& SDVO_ENABLE
) == 0)
1269 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1270 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1273 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1279 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1280 enum pipe pipe
, u32 val
)
1282 if ((val
& LVDS_PORT_EN
) == 0)
1285 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1286 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1289 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1295 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1296 enum pipe pipe
, u32 val
)
1298 if ((val
& ADPA_DAC_ENABLE
) == 0)
1300 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1301 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1304 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1310 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1311 enum pipe pipe
, int reg
, u32 port_sel
)
1313 u32 val
= I915_READ(reg
);
1314 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg
, pipe_name(pipe
));
1318 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1319 && (val
& DP_PIPEB_SELECT
),
1320 "IBX PCH dp port still using transcoder B\n");
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1324 enum pipe pipe
, int reg
)
1326 u32 val
= I915_READ(reg
);
1327 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg
, pipe_name(pipe
));
1331 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1332 && (val
& SDVO_PIPE_B_SELECT
),
1333 "IBX PCH hdmi port still using transcoder B\n");
1336 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1342 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1343 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1344 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1347 val
= I915_READ(reg
);
1348 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1353 val
= I915_READ(reg
);
1354 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1358 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1359 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1360 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1363 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1365 struct drm_device
*dev
= crtc
->base
.dev
;
1366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1367 int reg
= DPLL(crtc
->pipe
);
1368 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1370 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1377 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1379 I915_WRITE(reg
, dpll
);
1383 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1386 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1387 POSTING_READ(DPLL_MD(crtc
->pipe
));
1389 /* We do this three times for luck */
1390 I915_WRITE(reg
, dpll
);
1392 udelay(150); /* wait for warmup */
1393 I915_WRITE(reg
, dpll
);
1395 udelay(150); /* wait for warmup */
1396 I915_WRITE(reg
, dpll
);
1398 udelay(150); /* wait for warmup */
1401 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1403 struct drm_device
*dev
= crtc
->base
.dev
;
1404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1405 int reg
= DPLL(crtc
->pipe
);
1406 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1408 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1410 /* No really, not for ILK+ */
1411 BUG_ON(dev_priv
->info
->gen
>= 5);
1413 /* PLL is protected by panel, make sure we can write it */
1414 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1415 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1417 I915_WRITE(reg
, dpll
);
1419 /* Wait for the clocks to stabilize. */
1423 if (INTEL_INFO(dev
)->gen
>= 4) {
1424 I915_WRITE(DPLL_MD(crtc
->pipe
),
1425 crtc
->config
.dpll_hw_state
.dpll_md
);
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1430 * So write it again.
1432 I915_WRITE(reg
, dpll
);
1435 /* We do this three times for luck */
1436 I915_WRITE(reg
, dpll
);
1438 udelay(150); /* wait for warmup */
1439 I915_WRITE(reg
, dpll
);
1441 udelay(150); /* wait for warmup */
1442 I915_WRITE(reg
, dpll
);
1444 udelay(150); /* wait for warmup */
1448 * i9xx_disable_pll - disable a PLL
1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1454 * Note! This is for pre-ILK only.
1456 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv
, pipe
);
1465 I915_WRITE(DPLL(pipe
), 0);
1466 POSTING_READ(DPLL(pipe
));
1469 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1474 port_mask
= DPLL_PORTB_READY_MASK
;
1476 port_mask
= DPLL_PORTC_READY_MASK
;
1478 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1479 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480 'B' + port
, I915_READ(DPLL(0)));
1484 * ironlake_enable_shared_dpll - enable PCH PLL
1485 * @dev_priv: i915 private structure
1486 * @pipe: pipe PLL to enable
1488 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489 * drives the transcoder clock.
1491 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1493 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1494 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1496 /* PCH PLLs only available on ILK, SNB and IVB */
1497 BUG_ON(dev_priv
->info
->gen
< 5);
1498 if (WARN_ON(pll
== NULL
))
1501 if (WARN_ON(pll
->refcount
== 0))
1504 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505 pll
->name
, pll
->active
, pll
->on
,
1506 crtc
->base
.base
.id
);
1508 if (pll
->active
++) {
1510 assert_shared_dpll_enabled(dev_priv
, pll
);
1515 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1516 pll
->enable(dev_priv
, pll
);
1520 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1522 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1523 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1525 /* PCH only available on ILK+ */
1526 BUG_ON(dev_priv
->info
->gen
< 5);
1527 if (WARN_ON(pll
== NULL
))
1530 if (WARN_ON(pll
->refcount
== 0))
1533 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534 pll
->name
, pll
->active
, pll
->on
,
1535 crtc
->base
.base
.id
);
1537 if (WARN_ON(pll
->active
== 0)) {
1538 assert_shared_dpll_disabled(dev_priv
, pll
);
1542 assert_shared_dpll_enabled(dev_priv
, pll
);
1547 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1548 pll
->disable(dev_priv
, pll
);
1552 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1555 struct drm_device
*dev
= dev_priv
->dev
;
1556 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1557 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1558 uint32_t reg
, val
, pipeconf_val
;
1560 /* PCH only available on ILK+ */
1561 BUG_ON(dev_priv
->info
->gen
< 5);
1563 /* Make sure PCH DPLL is enabled */
1564 assert_shared_dpll_enabled(dev_priv
,
1565 intel_crtc_to_shared_dpll(intel_crtc
));
1567 /* FDI must be feeding us bits for PCH ports */
1568 assert_fdi_tx_enabled(dev_priv
, pipe
);
1569 assert_fdi_rx_enabled(dev_priv
, pipe
);
1571 if (HAS_PCH_CPT(dev
)) {
1572 /* Workaround: Set the timing override bit before enabling the
1573 * pch transcoder. */
1574 reg
= TRANS_CHICKEN2(pipe
);
1575 val
= I915_READ(reg
);
1576 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1577 I915_WRITE(reg
, val
);
1580 reg
= PCH_TRANSCONF(pipe
);
1581 val
= I915_READ(reg
);
1582 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1584 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1586 * make the BPC in transcoder be consistent with
1587 * that in pipeconf reg.
1589 val
&= ~PIPECONF_BPC_MASK
;
1590 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1593 val
&= ~TRANS_INTERLACE_MASK
;
1594 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1595 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1596 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1597 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1599 val
|= TRANS_INTERLACED
;
1601 val
|= TRANS_PROGRESSIVE
;
1603 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1604 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1605 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1608 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1609 enum transcoder cpu_transcoder
)
1611 u32 val
, pipeconf_val
;
1613 /* PCH only available on ILK+ */
1614 BUG_ON(dev_priv
->info
->gen
< 5);
1616 /* FDI must be feeding us bits for PCH ports */
1617 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1618 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1620 /* Workaround: set timing override bit. */
1621 val
= I915_READ(_TRANSA_CHICKEN2
);
1622 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1623 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1626 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1628 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1629 PIPECONF_INTERLACED_ILK
)
1630 val
|= TRANS_INTERLACED
;
1632 val
|= TRANS_PROGRESSIVE
;
1634 I915_WRITE(LPT_TRANSCONF
, val
);
1635 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1636 DRM_ERROR("Failed to enable PCH transcoder\n");
1639 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1642 struct drm_device
*dev
= dev_priv
->dev
;
1645 /* FDI relies on the transcoder */
1646 assert_fdi_tx_disabled(dev_priv
, pipe
);
1647 assert_fdi_rx_disabled(dev_priv
, pipe
);
1649 /* Ports must be off as well */
1650 assert_pch_ports_disabled(dev_priv
, pipe
);
1652 reg
= PCH_TRANSCONF(pipe
);
1653 val
= I915_READ(reg
);
1654 val
&= ~TRANS_ENABLE
;
1655 I915_WRITE(reg
, val
);
1656 /* wait for PCH transcoder off, transcoder state */
1657 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1658 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1660 if (!HAS_PCH_IBX(dev
)) {
1661 /* Workaround: Clear the timing override chicken bit again. */
1662 reg
= TRANS_CHICKEN2(pipe
);
1663 val
= I915_READ(reg
);
1664 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1665 I915_WRITE(reg
, val
);
1669 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1673 val
= I915_READ(LPT_TRANSCONF
);
1674 val
&= ~TRANS_ENABLE
;
1675 I915_WRITE(LPT_TRANSCONF
, val
);
1676 /* wait for PCH transcoder off, transcoder state */
1677 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1678 DRM_ERROR("Failed to disable PCH transcoder\n");
1680 /* Workaround: clear timing override bit. */
1681 val
= I915_READ(_TRANSA_CHICKEN2
);
1682 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1683 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1687 * intel_enable_pipe - enable a pipe, asserting requirements
1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe to enable
1690 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1692 * Enable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1695 * @pipe should be %PIPE_A or %PIPE_B.
1697 * Will wait until the pipe is actually running (i.e. first vblank) before
1700 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1701 bool pch_port
, bool dsi
)
1703 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1705 enum pipe pch_transcoder
;
1709 assert_planes_disabled(dev_priv
, pipe
);
1710 assert_cursor_disabled(dev_priv
, pipe
);
1711 assert_sprites_disabled(dev_priv
, pipe
);
1713 if (HAS_PCH_LPT(dev_priv
->dev
))
1714 pch_transcoder
= TRANSCODER_A
;
1716 pch_transcoder
= pipe
;
1719 * A pipe without a PLL won't actually be able to drive bits from
1720 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1723 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1725 assert_dsi_pll_enabled(dev_priv
);
1727 assert_pll_enabled(dev_priv
, pipe
);
1730 /* if driving the PCH, we need FDI enabled */
1731 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1732 assert_fdi_tx_pll_enabled(dev_priv
,
1733 (enum pipe
) cpu_transcoder
);
1735 /* FIXME: assert CPU port conditions for SNB+ */
1738 reg
= PIPECONF(cpu_transcoder
);
1739 val
= I915_READ(reg
);
1740 if (val
& PIPECONF_ENABLE
)
1743 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1744 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1748 * intel_disable_pipe - disable a pipe, asserting requirements
1749 * @dev_priv: i915 private structure
1750 * @pipe: pipe to disable
1752 * Disable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1755 * @pipe should be %PIPE_A or %PIPE_B.
1757 * Will wait until the pipe has shut down before returning.
1759 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1762 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1768 * Make sure planes won't keep trying to pump pixels to us,
1769 * or we might hang the display.
1771 assert_planes_disabled(dev_priv
, pipe
);
1772 assert_cursor_disabled(dev_priv
, pipe
);
1773 assert_sprites_disabled(dev_priv
, pipe
);
1775 /* Don't disable pipe A or pipe A PLLs if needed */
1776 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1779 reg
= PIPECONF(cpu_transcoder
);
1780 val
= I915_READ(reg
);
1781 if ((val
& PIPECONF_ENABLE
) == 0)
1784 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1785 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1789 * Plane regs are double buffered, going from enabled->disabled needs a
1790 * trigger in order to latch. The display address reg provides this.
1792 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1795 if (dev_priv
->info
->gen
>= 4)
1796 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1798 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1802 * intel_enable_plane - enable a display plane on a given pipe
1803 * @dev_priv: i915 private structure
1804 * @plane: plane to enable
1805 * @pipe: pipe being fed
1807 * Enable @plane on @pipe, making sure that @pipe is running first.
1809 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1810 enum plane plane
, enum pipe pipe
)
1815 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816 assert_pipe_enabled(dev_priv
, pipe
);
1818 reg
= DSPCNTR(plane
);
1819 val
= I915_READ(reg
);
1820 if (val
& DISPLAY_PLANE_ENABLE
)
1823 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1824 intel_flush_display_plane(dev_priv
, plane
);
1825 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1829 * intel_disable_plane - disable a display plane
1830 * @dev_priv: i915 private structure
1831 * @plane: plane to disable
1832 * @pipe: pipe consuming the data
1834 * Disable @plane; should be an independent operation.
1836 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1837 enum plane plane
, enum pipe pipe
)
1842 reg
= DSPCNTR(plane
);
1843 val
= I915_READ(reg
);
1844 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1847 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1848 intel_flush_display_plane(dev_priv
, plane
);
1849 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1852 static bool need_vtd_wa(struct drm_device
*dev
)
1854 #ifdef CONFIG_INTEL_IOMMU
1855 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1862 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1863 struct drm_i915_gem_object
*obj
,
1864 struct intel_ring_buffer
*pipelined
)
1866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1870 switch (obj
->tiling_mode
) {
1871 case I915_TILING_NONE
:
1872 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1873 alignment
= 128 * 1024;
1874 else if (INTEL_INFO(dev
)->gen
>= 4)
1875 alignment
= 4 * 1024;
1877 alignment
= 64 * 1024;
1880 /* pin() will align the object as required by fence */
1884 /* Despite that we check this in framebuffer_init userspace can
1885 * screw us over and change the tiling after the fact. Only
1886 * pinned buffers can't change their tiling. */
1887 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1893 /* Note that the w/a also requires 64 PTE of padding following the
1894 * bo. We currently fill all unused PTE with the shadow page and so
1895 * we should always have valid PTE following the scanout preventing
1898 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1899 alignment
= 256 * 1024;
1901 dev_priv
->mm
.interruptible
= false;
1902 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1904 goto err_interruptible
;
1906 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907 * fence, whereas 965+ only requires a fence if using
1908 * framebuffer compression. For simplicity, we always install
1909 * a fence as the cost is not that onerous.
1911 ret
= i915_gem_object_get_fence(obj
);
1915 i915_gem_object_pin_fence(obj
);
1917 dev_priv
->mm
.interruptible
= true;
1921 i915_gem_object_unpin_from_display_plane(obj
);
1923 dev_priv
->mm
.interruptible
= true;
1927 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1929 i915_gem_object_unpin_fence(obj
);
1930 i915_gem_object_unpin_from_display_plane(obj
);
1933 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934 * is assumed to be a power-of-two. */
1935 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1936 unsigned int tiling_mode
,
1940 if (tiling_mode
!= I915_TILING_NONE
) {
1941 unsigned int tile_rows
, tiles
;
1946 tiles
= *x
/ (512/cpp
);
1949 return tile_rows
* pitch
* 8 + tiles
* 4096;
1951 unsigned int offset
;
1953 offset
= *y
* pitch
+ *x
* cpp
;
1955 *x
= (offset
& 4095) / cpp
;
1956 return offset
& -4096;
1960 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1963 struct drm_device
*dev
= crtc
->dev
;
1964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1965 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1966 struct intel_framebuffer
*intel_fb
;
1967 struct drm_i915_gem_object
*obj
;
1968 int plane
= intel_crtc
->plane
;
1969 unsigned long linear_offset
;
1978 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
1982 intel_fb
= to_intel_framebuffer(fb
);
1983 obj
= intel_fb
->obj
;
1985 reg
= DSPCNTR(plane
);
1986 dspcntr
= I915_READ(reg
);
1987 /* Mask out pixel format bits in case we change it */
1988 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1989 switch (fb
->pixel_format
) {
1991 dspcntr
|= DISPPLANE_8BPP
;
1993 case DRM_FORMAT_XRGB1555
:
1994 case DRM_FORMAT_ARGB1555
:
1995 dspcntr
|= DISPPLANE_BGRX555
;
1997 case DRM_FORMAT_RGB565
:
1998 dspcntr
|= DISPPLANE_BGRX565
;
2000 case DRM_FORMAT_XRGB8888
:
2001 case DRM_FORMAT_ARGB8888
:
2002 dspcntr
|= DISPPLANE_BGRX888
;
2004 case DRM_FORMAT_XBGR8888
:
2005 case DRM_FORMAT_ABGR8888
:
2006 dspcntr
|= DISPPLANE_RGBX888
;
2008 case DRM_FORMAT_XRGB2101010
:
2009 case DRM_FORMAT_ARGB2101010
:
2010 dspcntr
|= DISPPLANE_BGRX101010
;
2012 case DRM_FORMAT_XBGR2101010
:
2013 case DRM_FORMAT_ABGR2101010
:
2014 dspcntr
|= DISPPLANE_RGBX101010
;
2020 if (INTEL_INFO(dev
)->gen
>= 4) {
2021 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2022 dspcntr
|= DISPPLANE_TILED
;
2024 dspcntr
&= ~DISPPLANE_TILED
;
2028 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2030 I915_WRITE(reg
, dspcntr
);
2032 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2034 if (INTEL_INFO(dev
)->gen
>= 4) {
2035 intel_crtc
->dspaddr_offset
=
2036 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2037 fb
->bits_per_pixel
/ 8,
2039 linear_offset
-= intel_crtc
->dspaddr_offset
;
2041 intel_crtc
->dspaddr_offset
= linear_offset
;
2044 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2047 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2048 if (INTEL_INFO(dev
)->gen
>= 4) {
2049 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2050 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2051 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2052 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2054 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2060 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2061 struct drm_framebuffer
*fb
, int x
, int y
)
2063 struct drm_device
*dev
= crtc
->dev
;
2064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2065 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2066 struct intel_framebuffer
*intel_fb
;
2067 struct drm_i915_gem_object
*obj
;
2068 int plane
= intel_crtc
->plane
;
2069 unsigned long linear_offset
;
2079 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2083 intel_fb
= to_intel_framebuffer(fb
);
2084 obj
= intel_fb
->obj
;
2086 reg
= DSPCNTR(plane
);
2087 dspcntr
= I915_READ(reg
);
2088 /* Mask out pixel format bits in case we change it */
2089 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2090 switch (fb
->pixel_format
) {
2092 dspcntr
|= DISPPLANE_8BPP
;
2094 case DRM_FORMAT_RGB565
:
2095 dspcntr
|= DISPPLANE_BGRX565
;
2097 case DRM_FORMAT_XRGB8888
:
2098 case DRM_FORMAT_ARGB8888
:
2099 dspcntr
|= DISPPLANE_BGRX888
;
2101 case DRM_FORMAT_XBGR8888
:
2102 case DRM_FORMAT_ABGR8888
:
2103 dspcntr
|= DISPPLANE_RGBX888
;
2105 case DRM_FORMAT_XRGB2101010
:
2106 case DRM_FORMAT_ARGB2101010
:
2107 dspcntr
|= DISPPLANE_BGRX101010
;
2109 case DRM_FORMAT_XBGR2101010
:
2110 case DRM_FORMAT_ABGR2101010
:
2111 dspcntr
|= DISPPLANE_RGBX101010
;
2117 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2118 dspcntr
|= DISPPLANE_TILED
;
2120 dspcntr
&= ~DISPPLANE_TILED
;
2122 if (IS_HASWELL(dev
))
2123 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2125 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2127 I915_WRITE(reg
, dspcntr
);
2129 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2130 intel_crtc
->dspaddr_offset
=
2131 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2132 fb
->bits_per_pixel
/ 8,
2134 linear_offset
-= intel_crtc
->dspaddr_offset
;
2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2139 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2140 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2141 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2142 if (IS_HASWELL(dev
)) {
2143 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2145 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2146 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2153 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2155 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2156 int x
, int y
, enum mode_set_atomic state
)
2158 struct drm_device
*dev
= crtc
->dev
;
2159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2161 if (dev_priv
->display
.disable_fbc
)
2162 dev_priv
->display
.disable_fbc(dev
);
2163 intel_increase_pllclock(crtc
);
2165 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2168 void intel_display_handle_reset(struct drm_device
*dev
)
2170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2171 struct drm_crtc
*crtc
;
2174 * Flips in the rings have been nuked by the reset,
2175 * so complete all pending flips so that user space
2176 * will get its events and not get stuck.
2178 * Also update the base address of all primary
2179 * planes to the the last fb to make sure we're
2180 * showing the correct fb after a reset.
2182 * Need to make two loops over the crtcs so that we
2183 * don't try to grab a crtc mutex before the
2184 * pending_flip_queue really got woken up.
2187 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2188 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2189 enum plane plane
= intel_crtc
->plane
;
2191 intel_prepare_page_flip(dev
, plane
);
2192 intel_finish_page_flip_plane(dev
, plane
);
2195 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2196 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2198 mutex_lock(&crtc
->mutex
);
2199 if (intel_crtc
->active
)
2200 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2202 mutex_unlock(&crtc
->mutex
);
2207 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2209 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2210 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2211 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2214 /* Big Hammer, we also need to ensure that any pending
2215 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216 * current scanout is retired before unpinning the old
2219 * This should only fail upon a hung GPU, in which case we
2220 * can safely continue.
2222 dev_priv
->mm
.interruptible
= false;
2223 ret
= i915_gem_object_finish_gpu(obj
);
2224 dev_priv
->mm
.interruptible
= was_interruptible
;
2229 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2231 struct drm_device
*dev
= crtc
->dev
;
2232 struct drm_i915_master_private
*master_priv
;
2233 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2235 if (!dev
->primary
->master
)
2238 master_priv
= dev
->primary
->master
->driver_priv
;
2239 if (!master_priv
->sarea_priv
)
2242 switch (intel_crtc
->pipe
) {
2244 master_priv
->sarea_priv
->pipeA_x
= x
;
2245 master_priv
->sarea_priv
->pipeA_y
= y
;
2248 master_priv
->sarea_priv
->pipeB_x
= x
;
2249 master_priv
->sarea_priv
->pipeB_y
= y
;
2257 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2258 struct drm_framebuffer
*fb
)
2260 struct drm_device
*dev
= crtc
->dev
;
2261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2262 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2263 struct drm_framebuffer
*old_fb
;
2268 DRM_ERROR("No FB bound\n");
2272 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2273 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274 plane_name(intel_crtc
->plane
),
2275 INTEL_INFO(dev
)->num_pipes
);
2279 mutex_lock(&dev
->struct_mutex
);
2280 ret
= intel_pin_and_fence_fb_obj(dev
,
2281 to_intel_framebuffer(fb
)->obj
,
2284 mutex_unlock(&dev
->struct_mutex
);
2285 DRM_ERROR("pin & fence failed\n");
2289 /* Update pipe size and adjust fitter if needed */
2290 if (i915_fastboot
) {
2291 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2292 ((crtc
->mode
.hdisplay
- 1) << 16) |
2293 (crtc
->mode
.vdisplay
- 1));
2294 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2295 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2296 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2297 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2298 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2299 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2303 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2305 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2306 mutex_unlock(&dev
->struct_mutex
);
2307 DRM_ERROR("failed to update base address\n");
2317 if (intel_crtc
->active
&& old_fb
!= fb
)
2318 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2319 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2322 intel_update_fbc(dev
);
2323 intel_edp_psr_update(dev
);
2324 mutex_unlock(&dev
->struct_mutex
);
2326 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2331 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2333 struct drm_device
*dev
= crtc
->dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2336 int pipe
= intel_crtc
->pipe
;
2339 /* enable normal train */
2340 reg
= FDI_TX_CTL(pipe
);
2341 temp
= I915_READ(reg
);
2342 if (IS_IVYBRIDGE(dev
)) {
2343 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2344 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2346 temp
&= ~FDI_LINK_TRAIN_NONE
;
2347 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2349 I915_WRITE(reg
, temp
);
2351 reg
= FDI_RX_CTL(pipe
);
2352 temp
= I915_READ(reg
);
2353 if (HAS_PCH_CPT(dev
)) {
2354 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2355 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2357 temp
&= ~FDI_LINK_TRAIN_NONE
;
2358 temp
|= FDI_LINK_TRAIN_NONE
;
2360 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2362 /* wait one idle pattern time */
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev
))
2368 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2369 FDI_FE_ERRC_ENABLE
);
2372 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2374 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2377 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2380 struct intel_crtc
*pipe_B_crtc
=
2381 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2382 struct intel_crtc
*pipe_C_crtc
=
2383 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2391 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2396 temp
= I915_READ(SOUTH_CHICKEN1
);
2397 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2403 /* The FDI link training functions for ILK/Ibexpeak. */
2404 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2406 struct drm_device
*dev
= crtc
->dev
;
2407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2408 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2409 int pipe
= intel_crtc
->pipe
;
2410 int plane
= intel_crtc
->plane
;
2411 u32 reg
, temp
, tries
;
2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv
, pipe
);
2415 assert_plane_enabled(dev_priv
, plane
);
2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2419 reg
= FDI_RX_IMR(pipe
);
2420 temp
= I915_READ(reg
);
2421 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2422 temp
&= ~FDI_RX_BIT_LOCK
;
2423 I915_WRITE(reg
, temp
);
2427 /* enable CPU FDI TX and PCH FDI RX */
2428 reg
= FDI_TX_CTL(pipe
);
2429 temp
= I915_READ(reg
);
2430 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2431 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2432 temp
&= ~FDI_LINK_TRAIN_NONE
;
2433 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2434 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2436 reg
= FDI_RX_CTL(pipe
);
2437 temp
= I915_READ(reg
);
2438 temp
&= ~FDI_LINK_TRAIN_NONE
;
2439 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2440 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
2446 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2448 FDI_RX_PHASE_SYNC_POINTER_EN
);
2450 reg
= FDI_RX_IIR(pipe
);
2451 for (tries
= 0; tries
< 5; tries
++) {
2452 temp
= I915_READ(reg
);
2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2455 if ((temp
& FDI_RX_BIT_LOCK
)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
2457 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2462 DRM_ERROR("FDI train 1 fail!\n");
2465 reg
= FDI_TX_CTL(pipe
);
2466 temp
= I915_READ(reg
);
2467 temp
&= ~FDI_LINK_TRAIN_NONE
;
2468 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2469 I915_WRITE(reg
, temp
);
2471 reg
= FDI_RX_CTL(pipe
);
2472 temp
= I915_READ(reg
);
2473 temp
&= ~FDI_LINK_TRAIN_NONE
;
2474 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2475 I915_WRITE(reg
, temp
);
2480 reg
= FDI_RX_IIR(pipe
);
2481 for (tries
= 0; tries
< 5; tries
++) {
2482 temp
= I915_READ(reg
);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2485 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2486 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2492 DRM_ERROR("FDI train 2 fail!\n");
2494 DRM_DEBUG_KMS("FDI train done\n");
2498 static const int snb_b_fdi_train_param
[] = {
2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2505 /* The FDI link training functions for SNB/Cougarpoint. */
2506 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2508 struct drm_device
*dev
= crtc
->dev
;
2509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2510 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2511 int pipe
= intel_crtc
->pipe
;
2512 u32 reg
, temp
, i
, retry
;
2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2516 reg
= FDI_RX_IMR(pipe
);
2517 temp
= I915_READ(reg
);
2518 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2519 temp
&= ~FDI_RX_BIT_LOCK
;
2520 I915_WRITE(reg
, temp
);
2525 /* enable CPU FDI TX and PCH FDI RX */
2526 reg
= FDI_TX_CTL(pipe
);
2527 temp
= I915_READ(reg
);
2528 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2529 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2530 temp
&= ~FDI_LINK_TRAIN_NONE
;
2531 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2532 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2534 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2535 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2537 I915_WRITE(FDI_RX_MISC(pipe
),
2538 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2540 reg
= FDI_RX_CTL(pipe
);
2541 temp
= I915_READ(reg
);
2542 if (HAS_PCH_CPT(dev
)) {
2543 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2544 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2546 temp
&= ~FDI_LINK_TRAIN_NONE
;
2547 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2549 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2554 for (i
= 0; i
< 4; i
++) {
2555 reg
= FDI_TX_CTL(pipe
);
2556 temp
= I915_READ(reg
);
2557 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2558 temp
|= snb_b_fdi_train_param
[i
];
2559 I915_WRITE(reg
, temp
);
2564 for (retry
= 0; retry
< 5; retry
++) {
2565 reg
= FDI_RX_IIR(pipe
);
2566 temp
= I915_READ(reg
);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2568 if (temp
& FDI_RX_BIT_LOCK
) {
2569 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579 DRM_ERROR("FDI train 1 fail!\n");
2582 reg
= FDI_TX_CTL(pipe
);
2583 temp
= I915_READ(reg
);
2584 temp
&= ~FDI_LINK_TRAIN_NONE
;
2585 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2587 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2589 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2591 I915_WRITE(reg
, temp
);
2593 reg
= FDI_RX_CTL(pipe
);
2594 temp
= I915_READ(reg
);
2595 if (HAS_PCH_CPT(dev
)) {
2596 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2597 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2599 temp
&= ~FDI_LINK_TRAIN_NONE
;
2600 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2602 I915_WRITE(reg
, temp
);
2607 for (i
= 0; i
< 4; i
++) {
2608 reg
= FDI_TX_CTL(pipe
);
2609 temp
= I915_READ(reg
);
2610 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2611 temp
|= snb_b_fdi_train_param
[i
];
2612 I915_WRITE(reg
, temp
);
2617 for (retry
= 0; retry
< 5; retry
++) {
2618 reg
= FDI_RX_IIR(pipe
);
2619 temp
= I915_READ(reg
);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2621 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2622 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632 DRM_ERROR("FDI train 2 fail!\n");
2634 DRM_DEBUG_KMS("FDI train done.\n");
2637 /* Manual link training for Ivy Bridge A0 parts */
2638 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2640 struct drm_device
*dev
= crtc
->dev
;
2641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2642 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2643 int pipe
= intel_crtc
->pipe
;
2644 u32 reg
, temp
, i
, j
;
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2648 reg
= FDI_RX_IMR(pipe
);
2649 temp
= I915_READ(reg
);
2650 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2651 temp
&= ~FDI_RX_BIT_LOCK
;
2652 I915_WRITE(reg
, temp
);
2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe
)));
2660 /* Try each vswing and preemphasis setting twice before moving on */
2661 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2662 /* disable first in case we need to retry */
2663 reg
= FDI_TX_CTL(pipe
);
2664 temp
= I915_READ(reg
);
2665 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2666 temp
&= ~FDI_TX_ENABLE
;
2667 I915_WRITE(reg
, temp
);
2669 reg
= FDI_RX_CTL(pipe
);
2670 temp
= I915_READ(reg
);
2671 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2672 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2673 temp
&= ~FDI_RX_ENABLE
;
2674 I915_WRITE(reg
, temp
);
2676 /* enable CPU FDI TX and PCH FDI RX */
2677 reg
= FDI_TX_CTL(pipe
);
2678 temp
= I915_READ(reg
);
2679 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2680 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2681 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2682 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2683 temp
|= snb_b_fdi_train_param
[j
/2];
2684 temp
|= FDI_COMPOSITE_SYNC
;
2685 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2687 I915_WRITE(FDI_RX_MISC(pipe
),
2688 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2690 reg
= FDI_RX_CTL(pipe
);
2691 temp
= I915_READ(reg
);
2692 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2693 temp
|= FDI_COMPOSITE_SYNC
;
2694 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2697 udelay(1); /* should be 0.5us */
2699 for (i
= 0; i
< 4; i
++) {
2700 reg
= FDI_RX_IIR(pipe
);
2701 temp
= I915_READ(reg
);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2704 if (temp
& FDI_RX_BIT_LOCK
||
2705 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2706 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2711 udelay(1); /* should be 0.5us */
2714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2719 reg
= FDI_TX_CTL(pipe
);
2720 temp
= I915_READ(reg
);
2721 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2722 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2723 I915_WRITE(reg
, temp
);
2725 reg
= FDI_RX_CTL(pipe
);
2726 temp
= I915_READ(reg
);
2727 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2728 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2729 I915_WRITE(reg
, temp
);
2732 udelay(2); /* should be 1.5us */
2734 for (i
= 0; i
< 4; i
++) {
2735 reg
= FDI_RX_IIR(pipe
);
2736 temp
= I915_READ(reg
);
2737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2739 if (temp
& FDI_RX_SYMBOL_LOCK
||
2740 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2741 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2746 udelay(2); /* should be 1.5us */
2749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2753 DRM_DEBUG_KMS("FDI train done.\n");
2756 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2758 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 int pipe
= intel_crtc
->pipe
;
2764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2765 reg
= FDI_RX_CTL(pipe
);
2766 temp
= I915_READ(reg
);
2767 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2768 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2769 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2770 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2775 /* Switch from Rawclk to PCDclk */
2776 temp
= I915_READ(reg
);
2777 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2782 /* Enable CPU FDI TX PLL, always on for Ironlake */
2783 reg
= FDI_TX_CTL(pipe
);
2784 temp
= I915_READ(reg
);
2785 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2786 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2793 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2795 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2797 int pipe
= intel_crtc
->pipe
;
2800 /* Switch from PCDclk to Rawclk */
2801 reg
= FDI_RX_CTL(pipe
);
2802 temp
= I915_READ(reg
);
2803 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2805 /* Disable CPU FDI TX PLL */
2806 reg
= FDI_TX_CTL(pipe
);
2807 temp
= I915_READ(reg
);
2808 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2813 reg
= FDI_RX_CTL(pipe
);
2814 temp
= I915_READ(reg
);
2815 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2817 /* Wait for the clocks to turn off. */
2822 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2824 struct drm_device
*dev
= crtc
->dev
;
2825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2827 int pipe
= intel_crtc
->pipe
;
2830 /* disable CPU FDI tx and PCH FDI rx */
2831 reg
= FDI_TX_CTL(pipe
);
2832 temp
= I915_READ(reg
);
2833 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2836 reg
= FDI_RX_CTL(pipe
);
2837 temp
= I915_READ(reg
);
2838 temp
&= ~(0x7 << 16);
2839 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2840 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2845 /* Ironlake workaround, disable clock pointer after downing FDI */
2846 if (HAS_PCH_IBX(dev
)) {
2847 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2850 /* still set train pattern 1 */
2851 reg
= FDI_TX_CTL(pipe
);
2852 temp
= I915_READ(reg
);
2853 temp
&= ~FDI_LINK_TRAIN_NONE
;
2854 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2855 I915_WRITE(reg
, temp
);
2857 reg
= FDI_RX_CTL(pipe
);
2858 temp
= I915_READ(reg
);
2859 if (HAS_PCH_CPT(dev
)) {
2860 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2861 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2863 temp
&= ~FDI_LINK_TRAIN_NONE
;
2864 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2866 /* BPC in FDI rx is consistent with that in PIPECONF */
2867 temp
&= ~(0x07 << 16);
2868 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2869 I915_WRITE(reg
, temp
);
2875 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2877 struct drm_device
*dev
= crtc
->dev
;
2878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2879 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2880 unsigned long flags
;
2883 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2884 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2887 spin_lock_irqsave(&dev
->event_lock
, flags
);
2888 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2889 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2894 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2896 struct drm_device
*dev
= crtc
->dev
;
2897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2899 if (crtc
->fb
== NULL
)
2902 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2904 wait_event(dev_priv
->pending_flip_queue
,
2905 !intel_crtc_has_pending_flip(crtc
));
2907 mutex_lock(&dev
->struct_mutex
);
2908 intel_finish_fb(crtc
->fb
);
2909 mutex_unlock(&dev
->struct_mutex
);
2912 /* Program iCLKIP clock to the desired frequency */
2913 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2915 struct drm_device
*dev
= crtc
->dev
;
2916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2917 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
2918 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2921 mutex_lock(&dev_priv
->dpio_lock
);
2923 /* It is necessary to ungate the pixclk gate prior to programming
2924 * the divisors, and gate it back when it is done.
2926 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2928 /* Disable SSCCTL */
2929 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2930 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2934 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2935 if (clock
== 20000) {
2940 /* The iCLK virtual clock root frequency is in MHz,
2941 * but the adjusted_mode->crtc_clock in in KHz. To get the
2942 * divisors, it is necessary to divide one by another, so we
2943 * convert the virtual clock precision to KHz here for higher
2946 u32 iclk_virtual_root_freq
= 172800 * 1000;
2947 u32 iclk_pi_range
= 64;
2948 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2950 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
2951 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2952 pi_value
= desired_divisor
% iclk_pi_range
;
2955 divsel
= msb_divisor_value
- 2;
2956 phaseinc
= pi_value
;
2959 /* This should not happen with any sane values */
2960 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2961 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2962 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2963 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2965 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2972 /* Program SSCDIVINTPHASE6 */
2973 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2974 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2975 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2976 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2977 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2978 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2979 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2980 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2982 /* Program SSCAUXDIV */
2983 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2984 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2986 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2988 /* Enable modulator and associated divider */
2989 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
2990 temp
&= ~SBI_SSCCTL_DISABLE
;
2991 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
2993 /* Wait for initialization time */
2996 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2998 mutex_unlock(&dev_priv
->dpio_lock
);
3001 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3002 enum pipe pch_transcoder
)
3004 struct drm_device
*dev
= crtc
->base
.dev
;
3005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3006 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3008 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3009 I915_READ(HTOTAL(cpu_transcoder
)));
3010 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3011 I915_READ(HBLANK(cpu_transcoder
)));
3012 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3013 I915_READ(HSYNC(cpu_transcoder
)));
3015 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3016 I915_READ(VTOTAL(cpu_transcoder
)));
3017 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3018 I915_READ(VBLANK(cpu_transcoder
)));
3019 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3020 I915_READ(VSYNC(cpu_transcoder
)));
3021 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3022 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3026 * Enable PCH resources required for PCH ports:
3028 * - FDI training & RX/TX
3029 * - update transcoder timings
3030 * - DP transcoding bits
3033 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3035 struct drm_device
*dev
= crtc
->dev
;
3036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3037 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3038 int pipe
= intel_crtc
->pipe
;
3041 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3043 /* Write the TU size bits before fdi link training, so that error
3044 * detection works. */
3045 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3046 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3048 /* For PCH output, training FDI link */
3049 dev_priv
->display
.fdi_link_train(crtc
);
3051 /* We need to program the right clock selection before writing the pixel
3052 * mutliplier into the DPLL. */
3053 if (HAS_PCH_CPT(dev
)) {
3056 temp
= I915_READ(PCH_DPLL_SEL
);
3057 temp
|= TRANS_DPLL_ENABLE(pipe
);
3058 sel
= TRANS_DPLLB_SEL(pipe
);
3059 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3063 I915_WRITE(PCH_DPLL_SEL
, temp
);
3066 /* XXX: pch pll's can be enabled any time before we enable the PCH
3067 * transcoder, and we actually should do this to not upset any PCH
3068 * transcoder that already use the clock when we share it.
3070 * Note that enable_shared_dpll tries to do the right thing, but
3071 * get_shared_dpll unconditionally resets the pll - we need that to have
3072 * the right LVDS enable sequence. */
3073 ironlake_enable_shared_dpll(intel_crtc
);
3075 /* set transcoder timing, panel must allow it */
3076 assert_panel_unlocked(dev_priv
, pipe
);
3077 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3079 intel_fdi_normal_train(crtc
);
3081 /* For PCH DP, enable TRANS_DP_CTL */
3082 if (HAS_PCH_CPT(dev
) &&
3083 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3084 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3085 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3086 reg
= TRANS_DP_CTL(pipe
);
3087 temp
= I915_READ(reg
);
3088 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3089 TRANS_DP_SYNC_MASK
|
3091 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3092 TRANS_DP_ENH_FRAMING
);
3093 temp
|= bpc
<< 9; /* same format but at 11:9 */
3095 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3096 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3097 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3098 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3100 switch (intel_trans_dp_port_sel(crtc
)) {
3102 temp
|= TRANS_DP_PORT_SEL_B
;
3105 temp
|= TRANS_DP_PORT_SEL_C
;
3108 temp
|= TRANS_DP_PORT_SEL_D
;
3114 I915_WRITE(reg
, temp
);
3117 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3120 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3122 struct drm_device
*dev
= crtc
->dev
;
3123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3124 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3125 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3127 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3129 lpt_program_iclkip(crtc
);
3131 /* Set transcoder timing. */
3132 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3134 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3137 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3139 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3144 if (pll
->refcount
== 0) {
3145 WARN(1, "bad %s refcount\n", pll
->name
);
3149 if (--pll
->refcount
== 0) {
3151 WARN_ON(pll
->active
);
3154 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3157 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3159 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3160 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3161 enum intel_dpll_id i
;
3164 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165 crtc
->base
.base
.id
, pll
->name
);
3166 intel_put_shared_dpll(crtc
);
3169 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3171 i
= (enum intel_dpll_id
) crtc
->pipe
;
3172 pll
= &dev_priv
->shared_dplls
[i
];
3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175 crtc
->base
.base
.id
, pll
->name
);
3180 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3181 pll
= &dev_priv
->shared_dplls
[i
];
3183 /* Only want to check enabled timings first */
3184 if (pll
->refcount
== 0)
3187 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3188 sizeof(pll
->hw_state
)) == 0) {
3189 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3191 pll
->name
, pll
->refcount
, pll
->active
);
3197 /* Ok no matching timings, maybe there's a free one? */
3198 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3199 pll
= &dev_priv
->shared_dplls
[i
];
3200 if (pll
->refcount
== 0) {
3201 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202 crtc
->base
.base
.id
, pll
->name
);
3210 crtc
->config
.shared_dpll
= i
;
3211 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3212 pipe_name(crtc
->pipe
));
3214 if (pll
->active
== 0) {
3215 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3216 sizeof(pll
->hw_state
));
3218 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3220 assert_shared_dpll_disabled(dev_priv
, pll
);
3222 pll
->mode_set(dev_priv
, pll
);
3229 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3232 int dslreg
= PIPEDSL(pipe
);
3235 temp
= I915_READ(dslreg
);
3237 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3238 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3239 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3243 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3245 struct drm_device
*dev
= crtc
->base
.dev
;
3246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3247 int pipe
= crtc
->pipe
;
3249 if (crtc
->config
.pch_pfit
.enabled
) {
3250 /* Force use of hard-coded filter coefficients
3251 * as some pre-programmed values are broken,
3254 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3255 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3256 PF_PIPE_SEL_IVB(pipe
));
3258 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3259 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3260 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3264 static void intel_enable_planes(struct drm_crtc
*crtc
)
3266 struct drm_device
*dev
= crtc
->dev
;
3267 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3268 struct intel_plane
*intel_plane
;
3270 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3271 if (intel_plane
->pipe
== pipe
)
3272 intel_plane_restore(&intel_plane
->base
);
3275 static void intel_disable_planes(struct drm_crtc
*crtc
)
3277 struct drm_device
*dev
= crtc
->dev
;
3278 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3279 struct intel_plane
*intel_plane
;
3281 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3282 if (intel_plane
->pipe
== pipe
)
3283 intel_plane_disable(&intel_plane
->base
);
3286 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3288 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3290 if (!crtc
->config
.ips_enabled
)
3293 /* We can only enable IPS after we enable a plane and wait for a vblank.
3294 * We guarantee that the plane is enabled by calling intel_enable_ips
3295 * only after intel_enable_plane. And intel_enable_plane already waits
3296 * for a vblank, so all we need to do here is to enable the IPS bit. */
3297 assert_plane_enabled(dev_priv
, crtc
->plane
);
3298 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3301 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3303 struct drm_device
*dev
= crtc
->base
.dev
;
3304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3306 if (!crtc
->config
.ips_enabled
)
3309 assert_plane_enabled(dev_priv
, crtc
->plane
);
3310 I915_WRITE(IPS_CTL
, 0);
3311 POSTING_READ(IPS_CTL
);
3313 /* We need to wait for a vblank before we can disable the plane. */
3314 intel_wait_for_vblank(dev
, crtc
->pipe
);
3317 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3318 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3320 struct drm_device
*dev
= crtc
->dev
;
3321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3322 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3323 enum pipe pipe
= intel_crtc
->pipe
;
3324 int palreg
= PALETTE(pipe
);
3326 bool reenable_ips
= false;
3328 /* The clocks have to be on to load the palette. */
3329 if (!crtc
->enabled
|| !intel_crtc
->active
)
3332 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3333 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3334 assert_dsi_pll_enabled(dev_priv
);
3336 assert_pll_enabled(dev_priv
, pipe
);
3339 /* use legacy palette for Ironlake */
3340 if (HAS_PCH_SPLIT(dev
))
3341 palreg
= LGC_PALETTE(pipe
);
3343 /* Workaround : Do not read or write the pipe palette/gamma data while
3344 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3346 if (intel_crtc
->config
.ips_enabled
&&
3347 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3348 GAMMA_MODE_MODE_SPLIT
)) {
3349 hsw_disable_ips(intel_crtc
);
3350 reenable_ips
= true;
3353 for (i
= 0; i
< 256; i
++) {
3354 I915_WRITE(palreg
+ 4 * i
,
3355 (intel_crtc
->lut_r
[i
] << 16) |
3356 (intel_crtc
->lut_g
[i
] << 8) |
3357 intel_crtc
->lut_b
[i
]);
3361 hsw_enable_ips(intel_crtc
);
3364 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3366 struct drm_device
*dev
= crtc
->dev
;
3367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3368 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3369 struct intel_encoder
*encoder
;
3370 int pipe
= intel_crtc
->pipe
;
3371 int plane
= intel_crtc
->plane
;
3373 WARN_ON(!crtc
->enabled
);
3375 if (intel_crtc
->active
)
3378 intel_crtc
->active
= true;
3380 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3381 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3383 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3384 if (encoder
->pre_enable
)
3385 encoder
->pre_enable(encoder
);
3387 if (intel_crtc
->config
.has_pch_encoder
) {
3388 /* Note: FDI PLL enabling _must_ be done before we enable the
3389 * cpu pipes, hence this is separate from all the other fdi/pch
3391 ironlake_fdi_pll_enable(intel_crtc
);
3393 assert_fdi_tx_disabled(dev_priv
, pipe
);
3394 assert_fdi_rx_disabled(dev_priv
, pipe
);
3397 ironlake_pfit_enable(intel_crtc
);
3400 * On ILK+ LUT must be loaded before the pipe is running but with
3403 intel_crtc_load_lut(crtc
);
3405 intel_update_watermarks(crtc
);
3406 intel_enable_pipe(dev_priv
, pipe
,
3407 intel_crtc
->config
.has_pch_encoder
, false);
3408 intel_enable_plane(dev_priv
, plane
, pipe
);
3409 intel_enable_planes(crtc
);
3410 intel_crtc_update_cursor(crtc
, true);
3412 if (intel_crtc
->config
.has_pch_encoder
)
3413 ironlake_pch_enable(crtc
);
3415 mutex_lock(&dev
->struct_mutex
);
3416 intel_update_fbc(dev
);
3417 mutex_unlock(&dev
->struct_mutex
);
3419 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3420 encoder
->enable(encoder
);
3422 if (HAS_PCH_CPT(dev
))
3423 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3426 * There seems to be a race in PCH platform hw (at least on some
3427 * outputs) where an enabled pipe still completes any pageflip right
3428 * away (as if the pipe is off) instead of waiting for vblank. As soon
3429 * as the first vblank happend, everything works as expected. Hence just
3430 * wait for one vblank before returning to avoid strange things
3433 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3436 /* IPS only exists on ULT machines and is tied to pipe A. */
3437 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3439 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3442 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3444 struct drm_device
*dev
= crtc
->dev
;
3445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3446 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3447 struct intel_encoder
*encoder
;
3448 int pipe
= intel_crtc
->pipe
;
3449 int plane
= intel_crtc
->plane
;
3451 WARN_ON(!crtc
->enabled
);
3453 if (intel_crtc
->active
)
3456 intel_crtc
->active
= true;
3458 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3459 if (intel_crtc
->config
.has_pch_encoder
)
3460 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3462 if (intel_crtc
->config
.has_pch_encoder
)
3463 dev_priv
->display
.fdi_link_train(crtc
);
3465 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3466 if (encoder
->pre_enable
)
3467 encoder
->pre_enable(encoder
);
3469 intel_ddi_enable_pipe_clock(intel_crtc
);
3471 ironlake_pfit_enable(intel_crtc
);
3474 * On ILK+ LUT must be loaded before the pipe is running but with
3477 intel_crtc_load_lut(crtc
);
3479 intel_ddi_set_pipe_settings(crtc
);
3480 intel_ddi_enable_transcoder_func(crtc
);
3482 intel_update_watermarks(crtc
);
3483 intel_enable_pipe(dev_priv
, pipe
,
3484 intel_crtc
->config
.has_pch_encoder
, false);
3485 intel_enable_plane(dev_priv
, plane
, pipe
);
3486 intel_enable_planes(crtc
);
3487 intel_crtc_update_cursor(crtc
, true);
3489 hsw_enable_ips(intel_crtc
);
3491 if (intel_crtc
->config
.has_pch_encoder
)
3492 lpt_pch_enable(crtc
);
3494 mutex_lock(&dev
->struct_mutex
);
3495 intel_update_fbc(dev
);
3496 mutex_unlock(&dev
->struct_mutex
);
3498 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3499 encoder
->enable(encoder
);
3500 intel_opregion_notify_encoder(encoder
, true);
3504 * There seems to be a race in PCH platform hw (at least on some
3505 * outputs) where an enabled pipe still completes any pageflip right
3506 * away (as if the pipe is off) instead of waiting for vblank. As soon
3507 * as the first vblank happend, everything works as expected. Hence just
3508 * wait for one vblank before returning to avoid strange things
3511 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3514 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3516 struct drm_device
*dev
= crtc
->base
.dev
;
3517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3518 int pipe
= crtc
->pipe
;
3520 /* To avoid upsetting the power well on haswell only disable the pfit if
3521 * it's in use. The hw state code will make sure we get this right. */
3522 if (crtc
->config
.pch_pfit
.enabled
) {
3523 I915_WRITE(PF_CTL(pipe
), 0);
3524 I915_WRITE(PF_WIN_POS(pipe
), 0);
3525 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3529 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3531 struct drm_device
*dev
= crtc
->dev
;
3532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3533 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3534 struct intel_encoder
*encoder
;
3535 int pipe
= intel_crtc
->pipe
;
3536 int plane
= intel_crtc
->plane
;
3540 if (!intel_crtc
->active
)
3543 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3544 encoder
->disable(encoder
);
3546 intel_crtc_wait_for_pending_flips(crtc
);
3547 drm_vblank_off(dev
, pipe
);
3549 if (dev_priv
->fbc
.plane
== plane
)
3550 intel_disable_fbc(dev
);
3552 intel_crtc_update_cursor(crtc
, false);
3553 intel_disable_planes(crtc
);
3554 intel_disable_plane(dev_priv
, plane
, pipe
);
3556 if (intel_crtc
->config
.has_pch_encoder
)
3557 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3559 intel_disable_pipe(dev_priv
, pipe
);
3561 ironlake_pfit_disable(intel_crtc
);
3563 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3564 if (encoder
->post_disable
)
3565 encoder
->post_disable(encoder
);
3567 if (intel_crtc
->config
.has_pch_encoder
) {
3568 ironlake_fdi_disable(crtc
);
3570 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3571 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3573 if (HAS_PCH_CPT(dev
)) {
3574 /* disable TRANS_DP_CTL */
3575 reg
= TRANS_DP_CTL(pipe
);
3576 temp
= I915_READ(reg
);
3577 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3578 TRANS_DP_PORT_SEL_MASK
);
3579 temp
|= TRANS_DP_PORT_SEL_NONE
;
3580 I915_WRITE(reg
, temp
);
3582 /* disable DPLL_SEL */
3583 temp
= I915_READ(PCH_DPLL_SEL
);
3584 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3585 I915_WRITE(PCH_DPLL_SEL
, temp
);
3588 /* disable PCH DPLL */
3589 intel_disable_shared_dpll(intel_crtc
);
3591 ironlake_fdi_pll_disable(intel_crtc
);
3594 intel_crtc
->active
= false;
3595 intel_update_watermarks(crtc
);
3597 mutex_lock(&dev
->struct_mutex
);
3598 intel_update_fbc(dev
);
3599 mutex_unlock(&dev
->struct_mutex
);
3602 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3604 struct drm_device
*dev
= crtc
->dev
;
3605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3606 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3607 struct intel_encoder
*encoder
;
3608 int pipe
= intel_crtc
->pipe
;
3609 int plane
= intel_crtc
->plane
;
3610 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3612 if (!intel_crtc
->active
)
3615 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3616 intel_opregion_notify_encoder(encoder
, false);
3617 encoder
->disable(encoder
);
3620 intel_crtc_wait_for_pending_flips(crtc
);
3621 drm_vblank_off(dev
, pipe
);
3623 /* FBC must be disabled before disabling the plane on HSW. */
3624 if (dev_priv
->fbc
.plane
== plane
)
3625 intel_disable_fbc(dev
);
3627 hsw_disable_ips(intel_crtc
);
3629 intel_crtc_update_cursor(crtc
, false);
3630 intel_disable_planes(crtc
);
3631 intel_disable_plane(dev_priv
, plane
, pipe
);
3633 if (intel_crtc
->config
.has_pch_encoder
)
3634 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3635 intel_disable_pipe(dev_priv
, pipe
);
3637 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3639 ironlake_pfit_disable(intel_crtc
);
3641 intel_ddi_disable_pipe_clock(intel_crtc
);
3643 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3644 if (encoder
->post_disable
)
3645 encoder
->post_disable(encoder
);
3647 if (intel_crtc
->config
.has_pch_encoder
) {
3648 lpt_disable_pch_transcoder(dev_priv
);
3649 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3650 intel_ddi_fdi_disable(crtc
);
3653 intel_crtc
->active
= false;
3654 intel_update_watermarks(crtc
);
3656 mutex_lock(&dev
->struct_mutex
);
3657 intel_update_fbc(dev
);
3658 mutex_unlock(&dev
->struct_mutex
);
3661 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3663 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3664 intel_put_shared_dpll(intel_crtc
);
3667 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3669 intel_ddi_put_crtc_pll(crtc
);
3672 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3674 if (!enable
&& intel_crtc
->overlay
) {
3675 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3678 mutex_lock(&dev
->struct_mutex
);
3679 dev_priv
->mm
.interruptible
= false;
3680 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3681 dev_priv
->mm
.interruptible
= true;
3682 mutex_unlock(&dev
->struct_mutex
);
3685 /* Let userspace switch the overlay on again. In most cases userspace
3686 * has to recompute where to put it anyway.
3691 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3692 * cursor plane briefly if not already running after enabling the display
3694 * This workaround avoids occasional blank screens when self refresh is
3698 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3700 u32 cntl
= I915_READ(CURCNTR(pipe
));
3702 if ((cntl
& CURSOR_MODE
) == 0) {
3703 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3705 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3706 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3707 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3708 I915_WRITE(CURCNTR(pipe
), cntl
);
3709 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3710 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3714 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3716 struct drm_device
*dev
= crtc
->base
.dev
;
3717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3718 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3720 if (!crtc
->config
.gmch_pfit
.control
)
3724 * The panel fitter should only be adjusted whilst the pipe is disabled,
3725 * according to register description and PRM.
3727 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3728 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3730 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3731 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3733 /* Border color in case we don't scale up to the full screen. Black by
3734 * default, change to something else for debugging. */
3735 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3738 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3740 struct drm_device
*dev
= crtc
->dev
;
3741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3742 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3743 struct intel_encoder
*encoder
;
3744 int pipe
= intel_crtc
->pipe
;
3745 int plane
= intel_crtc
->plane
;
3748 WARN_ON(!crtc
->enabled
);
3750 if (intel_crtc
->active
)
3753 intel_crtc
->active
= true;
3755 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3756 if (encoder
->pre_pll_enable
)
3757 encoder
->pre_pll_enable(encoder
);
3759 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
3762 vlv_enable_pll(intel_crtc
);
3764 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3765 if (encoder
->pre_enable
)
3766 encoder
->pre_enable(encoder
);
3768 i9xx_pfit_enable(intel_crtc
);
3770 intel_crtc_load_lut(crtc
);
3772 intel_update_watermarks(crtc
);
3773 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
3774 intel_enable_plane(dev_priv
, plane
, pipe
);
3775 intel_enable_planes(crtc
);
3776 intel_crtc_update_cursor(crtc
, true);
3778 intel_update_fbc(dev
);
3780 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3781 encoder
->enable(encoder
);
3784 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3786 struct drm_device
*dev
= crtc
->dev
;
3787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3788 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3789 struct intel_encoder
*encoder
;
3790 int pipe
= intel_crtc
->pipe
;
3791 int plane
= intel_crtc
->plane
;
3793 WARN_ON(!crtc
->enabled
);
3795 if (intel_crtc
->active
)
3798 intel_crtc
->active
= true;
3800 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3801 if (encoder
->pre_enable
)
3802 encoder
->pre_enable(encoder
);
3804 i9xx_enable_pll(intel_crtc
);
3806 i9xx_pfit_enable(intel_crtc
);
3808 intel_crtc_load_lut(crtc
);
3810 intel_update_watermarks(crtc
);
3811 intel_enable_pipe(dev_priv
, pipe
, false, false);
3812 intel_enable_plane(dev_priv
, plane
, pipe
);
3813 intel_enable_planes(crtc
);
3814 /* The fixup needs to happen before cursor is enabled */
3816 g4x_fixup_plane(dev_priv
, pipe
);
3817 intel_crtc_update_cursor(crtc
, true);
3819 /* Give the overlay scaler a chance to enable if it's on this pipe */
3820 intel_crtc_dpms_overlay(intel_crtc
, true);
3822 intel_update_fbc(dev
);
3824 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3825 encoder
->enable(encoder
);
3828 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3830 struct drm_device
*dev
= crtc
->base
.dev
;
3831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3833 if (!crtc
->config
.gmch_pfit
.control
)
3836 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3838 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3839 I915_READ(PFIT_CONTROL
));
3840 I915_WRITE(PFIT_CONTROL
, 0);
3843 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3845 struct drm_device
*dev
= crtc
->dev
;
3846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3847 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3848 struct intel_encoder
*encoder
;
3849 int pipe
= intel_crtc
->pipe
;
3850 int plane
= intel_crtc
->plane
;
3852 if (!intel_crtc
->active
)
3855 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3856 encoder
->disable(encoder
);
3858 /* Give the overlay scaler a chance to disable if it's on this pipe */
3859 intel_crtc_wait_for_pending_flips(crtc
);
3860 drm_vblank_off(dev
, pipe
);
3862 if (dev_priv
->fbc
.plane
== plane
)
3863 intel_disable_fbc(dev
);
3865 intel_crtc_dpms_overlay(intel_crtc
, false);
3866 intel_crtc_update_cursor(crtc
, false);
3867 intel_disable_planes(crtc
);
3868 intel_disable_plane(dev_priv
, plane
, pipe
);
3870 intel_disable_pipe(dev_priv
, pipe
);
3872 i9xx_pfit_disable(intel_crtc
);
3874 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3875 if (encoder
->post_disable
)
3876 encoder
->post_disable(encoder
);
3878 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3879 i9xx_disable_pll(dev_priv
, pipe
);
3881 intel_crtc
->active
= false;
3882 intel_update_watermarks(crtc
);
3884 intel_update_fbc(dev
);
3887 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3891 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3894 struct drm_device
*dev
= crtc
->dev
;
3895 struct drm_i915_master_private
*master_priv
;
3896 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3897 int pipe
= intel_crtc
->pipe
;
3899 if (!dev
->primary
->master
)
3902 master_priv
= dev
->primary
->master
->driver_priv
;
3903 if (!master_priv
->sarea_priv
)
3908 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3909 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3912 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3913 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3916 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3922 * Sets the power management mode of the pipe and plane.
3924 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3926 struct drm_device
*dev
= crtc
->dev
;
3927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3928 struct intel_encoder
*intel_encoder
;
3929 bool enable
= false;
3931 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3932 enable
|= intel_encoder
->connectors_active
;
3935 dev_priv
->display
.crtc_enable(crtc
);
3937 dev_priv
->display
.crtc_disable(crtc
);
3939 intel_crtc_update_sarea(crtc
, enable
);
3942 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3944 struct drm_device
*dev
= crtc
->dev
;
3945 struct drm_connector
*connector
;
3946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3947 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3949 /* crtc should still be enabled when we disable it. */
3950 WARN_ON(!crtc
->enabled
);
3952 dev_priv
->display
.crtc_disable(crtc
);
3953 intel_crtc
->eld_vld
= false;
3954 intel_crtc_update_sarea(crtc
, false);
3955 dev_priv
->display
.off(crtc
);
3957 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3958 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
3959 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3962 mutex_lock(&dev
->struct_mutex
);
3963 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3964 mutex_unlock(&dev
->struct_mutex
);
3968 /* Update computed state. */
3969 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3970 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3973 if (connector
->encoder
->crtc
!= crtc
)
3976 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3977 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3981 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3983 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3985 drm_encoder_cleanup(encoder
);
3986 kfree(intel_encoder
);
3989 /* Simple dpms helper for encoders with just one connector, no cloning and only
3990 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3991 * state of the entire output pipe. */
3992 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3994 if (mode
== DRM_MODE_DPMS_ON
) {
3995 encoder
->connectors_active
= true;
3997 intel_crtc_update_dpms(encoder
->base
.crtc
);
3999 encoder
->connectors_active
= false;
4001 intel_crtc_update_dpms(encoder
->base
.crtc
);
4005 /* Cross check the actual hw state with our own modeset state tracking (and it's
4006 * internal consistency). */
4007 static void intel_connector_check_state(struct intel_connector
*connector
)
4009 if (connector
->get_hw_state(connector
)) {
4010 struct intel_encoder
*encoder
= connector
->encoder
;
4011 struct drm_crtc
*crtc
;
4012 bool encoder_enabled
;
4015 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4016 connector
->base
.base
.id
,
4017 drm_get_connector_name(&connector
->base
));
4019 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
4020 "wrong connector dpms state\n");
4021 WARN(connector
->base
.encoder
!= &encoder
->base
,
4022 "active connector not linked to encoder\n");
4023 WARN(!encoder
->connectors_active
,
4024 "encoder->connectors_active not set\n");
4026 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
4027 WARN(!encoder_enabled
, "encoder not enabled\n");
4028 if (WARN_ON(!encoder
->base
.crtc
))
4031 crtc
= encoder
->base
.crtc
;
4033 WARN(!crtc
->enabled
, "crtc not enabled\n");
4034 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
4035 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4036 "encoder active on the wrong pipe\n");
4040 /* Even simpler default implementation, if there's really no special case to
4042 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4044 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
4046 /* All the simple cases only support two dpms states. */
4047 if (mode
!= DRM_MODE_DPMS_ON
)
4048 mode
= DRM_MODE_DPMS_OFF
;
4050 if (mode
== connector
->dpms
)
4053 connector
->dpms
= mode
;
4055 /* Only need to change hw state when actually enabled */
4056 if (encoder
->base
.crtc
)
4057 intel_encoder_dpms(encoder
, mode
);
4059 WARN_ON(encoder
->connectors_active
!= false);
4061 intel_modeset_check_state(connector
->dev
);
4064 /* Simple connector->get_hw_state implementation for encoders that support only
4065 * one connector and no cloning and hence the encoder state determines the state
4066 * of the connector. */
4067 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4070 struct intel_encoder
*encoder
= connector
->encoder
;
4072 return encoder
->get_hw_state(encoder
, &pipe
);
4075 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4076 struct intel_crtc_config
*pipe_config
)
4078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4079 struct intel_crtc
*pipe_B_crtc
=
4080 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
4082 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4083 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4084 if (pipe_config
->fdi_lanes
> 4) {
4085 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4086 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4090 if (IS_HASWELL(dev
)) {
4091 if (pipe_config
->fdi_lanes
> 2) {
4092 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4093 pipe_config
->fdi_lanes
);
4100 if (INTEL_INFO(dev
)->num_pipes
== 2)
4103 /* Ivybridge 3 pipe is really complicated */
4108 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4109 pipe_config
->fdi_lanes
> 2) {
4110 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4111 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4116 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4117 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4118 if (pipe_config
->fdi_lanes
> 2) {
4119 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4120 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4124 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4134 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4135 struct intel_crtc_config
*pipe_config
)
4137 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4138 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4139 int lane
, link_bw
, fdi_dotclock
;
4140 bool setup_ok
, needs_recompute
= false;
4143 /* FDI is a binary signal running at ~2.7GHz, encoding
4144 * each output octet as 10 bits. The actual frequency
4145 * is stored as a divider into a 100MHz clock, and the
4146 * mode pixel clock is stored in units of 1KHz.
4147 * Hence the bw of each lane in terms of the mode signal
4150 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4152 fdi_dotclock
= adjusted_mode
->crtc_clock
;
4154 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4155 pipe_config
->pipe_bpp
);
4157 pipe_config
->fdi_lanes
= lane
;
4159 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4160 link_bw
, &pipe_config
->fdi_m_n
);
4162 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4163 intel_crtc
->pipe
, pipe_config
);
4164 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4165 pipe_config
->pipe_bpp
-= 2*3;
4166 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4167 pipe_config
->pipe_bpp
);
4168 needs_recompute
= true;
4169 pipe_config
->bw_constrained
= true;
4174 if (needs_recompute
)
4177 return setup_ok
? 0 : -EINVAL
;
4180 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4181 struct intel_crtc_config
*pipe_config
)
4183 pipe_config
->ips_enabled
= i915_enable_ips
&&
4184 hsw_crtc_supports_ips(crtc
) &&
4185 pipe_config
->pipe_bpp
<= 24;
4188 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4189 struct intel_crtc_config
*pipe_config
)
4191 struct drm_device
*dev
= crtc
->base
.dev
;
4192 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4194 /* FIXME should check pixel clock limits on all platforms */
4195 if (INTEL_INFO(dev
)->gen
< 4) {
4196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4198 dev_priv
->display
.get_display_clock_speed(dev
);
4201 * Enable pixel doubling when the dot clock
4202 * is > 90% of the (display) core speed.
4204 * GDG double wide on either pipe,
4205 * otherwise pipe A only.
4207 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
4208 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
4210 pipe_config
->double_wide
= true;
4213 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
4218 * Pipe horizontal size must be even in:
4220 * - LVDS dual channel mode
4221 * - Double wide pipe
4223 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4224 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
4225 pipe_config
->pipe_src_w
&= ~1;
4227 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4228 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4230 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4231 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4234 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4235 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4236 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4237 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4239 pipe_config
->pipe_bpp
= 8*3;
4243 hsw_compute_ips_config(crtc
, pipe_config
);
4245 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4246 * clock survives for now. */
4247 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4248 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4250 if (pipe_config
->has_pch_encoder
)
4251 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4256 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4258 return 400000; /* FIXME */
4261 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4266 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4271 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4276 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4280 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4282 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4283 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4285 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4287 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4289 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4292 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4293 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4295 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4300 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4304 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4306 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4309 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4310 case GC_DISPLAY_CLOCK_333_MHZ
:
4313 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4319 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4324 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4327 /* Assume that the hardware is in the high speed state. This
4328 * should be the default.
4330 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4331 case GC_CLOCK_133_200
:
4332 case GC_CLOCK_100_200
:
4334 case GC_CLOCK_166_250
:
4336 case GC_CLOCK_100_133
:
4340 /* Shouldn't happen */
4344 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4350 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4352 while (*num
> DATA_LINK_M_N_MASK
||
4353 *den
> DATA_LINK_M_N_MASK
) {
4359 static void compute_m_n(unsigned int m
, unsigned int n
,
4360 uint32_t *ret_m
, uint32_t *ret_n
)
4362 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4363 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4364 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4368 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4369 int pixel_clock
, int link_clock
,
4370 struct intel_link_m_n
*m_n
)
4374 compute_m_n(bits_per_pixel
* pixel_clock
,
4375 link_clock
* nlanes
* 8,
4376 &m_n
->gmch_m
, &m_n
->gmch_n
);
4378 compute_m_n(pixel_clock
, link_clock
,
4379 &m_n
->link_m
, &m_n
->link_n
);
4382 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4384 if (i915_panel_use_ssc
>= 0)
4385 return i915_panel_use_ssc
!= 0;
4386 return dev_priv
->vbt
.lvds_use_ssc
4387 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4390 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4392 struct drm_device
*dev
= crtc
->dev
;
4393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4396 if (IS_VALLEYVIEW(dev
)) {
4398 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4399 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4400 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4401 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4403 } else if (!IS_GEN2(dev
)) {
4412 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4414 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4417 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4419 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4422 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4423 intel_clock_t
*reduced_clock
)
4425 struct drm_device
*dev
= crtc
->base
.dev
;
4426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4427 int pipe
= crtc
->pipe
;
4430 if (IS_PINEVIEW(dev
)) {
4431 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4433 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4435 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4437 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4440 I915_WRITE(FP0(pipe
), fp
);
4441 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4443 crtc
->lowfreq_avail
= false;
4444 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4445 reduced_clock
&& i915_powersave
) {
4446 I915_WRITE(FP1(pipe
), fp2
);
4447 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4448 crtc
->lowfreq_avail
= true;
4450 I915_WRITE(FP1(pipe
), fp
);
4451 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4455 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4461 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4462 * and set it to a reasonable value instead.
4464 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4465 reg_val
&= 0xffffff00;
4466 reg_val
|= 0x00000030;
4467 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4469 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4470 reg_val
&= 0x8cffffff;
4471 reg_val
= 0x8c000000;
4472 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4474 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4475 reg_val
&= 0xffffff00;
4476 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4478 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4479 reg_val
&= 0x00ffffff;
4480 reg_val
|= 0xb0000000;
4481 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4484 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4485 struct intel_link_m_n
*m_n
)
4487 struct drm_device
*dev
= crtc
->base
.dev
;
4488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4489 int pipe
= crtc
->pipe
;
4491 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4492 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4493 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4494 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4497 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4498 struct intel_link_m_n
*m_n
)
4500 struct drm_device
*dev
= crtc
->base
.dev
;
4501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4502 int pipe
= crtc
->pipe
;
4503 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4505 if (INTEL_INFO(dev
)->gen
>= 5) {
4506 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4507 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4508 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4509 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4511 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4512 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4513 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4514 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4518 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4520 if (crtc
->config
.has_pch_encoder
)
4521 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4523 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4526 static void vlv_update_pll(struct intel_crtc
*crtc
)
4528 struct drm_device
*dev
= crtc
->base
.dev
;
4529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4530 int pipe
= crtc
->pipe
;
4532 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4533 u32 coreclk
, reg_val
, dpll_md
;
4535 mutex_lock(&dev_priv
->dpio_lock
);
4537 bestn
= crtc
->config
.dpll
.n
;
4538 bestm1
= crtc
->config
.dpll
.m1
;
4539 bestm2
= crtc
->config
.dpll
.m2
;
4540 bestp1
= crtc
->config
.dpll
.p1
;
4541 bestp2
= crtc
->config
.dpll
.p2
;
4543 /* See eDP HDMI DPIO driver vbios notes doc */
4545 /* PLL B needs special handling */
4547 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4549 /* Set up Tx target for periodic Rcomp update */
4550 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_BCAST
, 0x0100000f);
4552 /* Disable target IRef on PLL */
4553 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
));
4554 reg_val
&= 0x00ffffff;
4555 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
), reg_val
);
4557 /* Disable fast lock */
4558 vlv_dpio_write(dev_priv
, pipe
, DPIO_FASTCLK_DISABLE
, 0x610);
4560 /* Set idtafcrecal before PLL is enabled */
4561 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4562 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4563 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4564 mdiv
|= (1 << DPIO_K_SHIFT
);
4567 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4568 * but we don't support that).
4569 * Note: don't use the DAC post divider as it seems unstable.
4571 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4572 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4574 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4575 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4577 /* Set HBR and RBR LPF coefficients */
4578 if (crtc
->config
.port_clock
== 162000 ||
4579 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4580 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4581 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4584 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4587 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4588 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4589 /* Use SSC source */
4591 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4594 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4596 } else { /* HDMI or VGA */
4597 /* Use bend source */
4599 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4602 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4606 coreclk
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
));
4607 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4608 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4609 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4610 coreclk
|= 0x01000000;
4611 vlv_dpio_write(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
), coreclk
);
4613 vlv_dpio_write(dev_priv
, pipe
, DPIO_PLL_CML(pipe
), 0x87871000);
4615 /* Enable DPIO clock input */
4616 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4617 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4619 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4621 dpll
|= DPLL_VCO_ENABLE
;
4622 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4624 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4625 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4626 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4628 if (crtc
->config
.has_dp_encoder
)
4629 intel_dp_set_m_n(crtc
);
4631 mutex_unlock(&dev_priv
->dpio_lock
);
4634 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4635 intel_clock_t
*reduced_clock
,
4638 struct drm_device
*dev
= crtc
->base
.dev
;
4639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4642 struct dpll
*clock
= &crtc
->config
.dpll
;
4644 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4646 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4647 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4649 dpll
= DPLL_VGA_MODE_DIS
;
4651 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4652 dpll
|= DPLLB_MODE_LVDS
;
4654 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4656 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4657 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4658 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4662 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4664 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4665 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4667 /* compute bitmask from p1 value */
4668 if (IS_PINEVIEW(dev
))
4669 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4671 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4672 if (IS_G4X(dev
) && reduced_clock
)
4673 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4675 switch (clock
->p2
) {
4677 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4680 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4683 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4686 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4689 if (INTEL_INFO(dev
)->gen
>= 4)
4690 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4692 if (crtc
->config
.sdvo_tv_clock
)
4693 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4694 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4695 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4696 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4698 dpll
|= PLL_REF_INPUT_DREFCLK
;
4700 dpll
|= DPLL_VCO_ENABLE
;
4701 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4703 if (INTEL_INFO(dev
)->gen
>= 4) {
4704 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4705 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4706 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4709 if (crtc
->config
.has_dp_encoder
)
4710 intel_dp_set_m_n(crtc
);
4713 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4714 intel_clock_t
*reduced_clock
,
4717 struct drm_device
*dev
= crtc
->base
.dev
;
4718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4720 struct dpll
*clock
= &crtc
->config
.dpll
;
4722 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4724 dpll
= DPLL_VGA_MODE_DIS
;
4726 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4727 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4730 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4732 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4734 dpll
|= PLL_P2_DIVIDE_BY_4
;
4737 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
4738 dpll
|= DPLL_DVO_2X_MODE
;
4740 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4741 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4742 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4744 dpll
|= PLL_REF_INPUT_DREFCLK
;
4746 dpll
|= DPLL_VCO_ENABLE
;
4747 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4750 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4752 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4754 enum pipe pipe
= intel_crtc
->pipe
;
4755 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4756 struct drm_display_mode
*adjusted_mode
=
4757 &intel_crtc
->config
.adjusted_mode
;
4758 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4760 /* We need to be careful not to changed the adjusted mode, for otherwise
4761 * the hw state checker will get angry at the mismatch. */
4762 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4763 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4765 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4766 /* the chip adds 2 halflines automatically */
4768 crtc_vblank_end
-= 1;
4769 vsyncshift
= adjusted_mode
->crtc_hsync_start
4770 - adjusted_mode
->crtc_htotal
/ 2;
4775 if (INTEL_INFO(dev
)->gen
> 3)
4776 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4778 I915_WRITE(HTOTAL(cpu_transcoder
),
4779 (adjusted_mode
->crtc_hdisplay
- 1) |
4780 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4781 I915_WRITE(HBLANK(cpu_transcoder
),
4782 (adjusted_mode
->crtc_hblank_start
- 1) |
4783 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4784 I915_WRITE(HSYNC(cpu_transcoder
),
4785 (adjusted_mode
->crtc_hsync_start
- 1) |
4786 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4788 I915_WRITE(VTOTAL(cpu_transcoder
),
4789 (adjusted_mode
->crtc_vdisplay
- 1) |
4790 ((crtc_vtotal
- 1) << 16));
4791 I915_WRITE(VBLANK(cpu_transcoder
),
4792 (adjusted_mode
->crtc_vblank_start
- 1) |
4793 ((crtc_vblank_end
- 1) << 16));
4794 I915_WRITE(VSYNC(cpu_transcoder
),
4795 (adjusted_mode
->crtc_vsync_start
- 1) |
4796 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4798 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4799 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4800 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4802 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4803 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4804 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4806 /* pipesrc controls the size that is scaled from, which should
4807 * always be the user's requested size.
4809 I915_WRITE(PIPESRC(pipe
),
4810 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
4811 (intel_crtc
->config
.pipe_src_h
- 1));
4814 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4815 struct intel_crtc_config
*pipe_config
)
4817 struct drm_device
*dev
= crtc
->base
.dev
;
4818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4819 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4822 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4823 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4824 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4825 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4826 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4827 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4828 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4829 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4830 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4832 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4833 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4834 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4835 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4836 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4837 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4838 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4839 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4840 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4842 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4843 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4844 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4845 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4848 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4849 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
4850 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
4852 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
4853 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
4856 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
4857 struct intel_crtc_config
*pipe_config
)
4859 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4861 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
4862 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
4863 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
4864 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
4866 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
4867 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
4868 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
4869 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
4871 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
4873 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.crtc_clock
;
4874 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
4877 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4879 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4885 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
4886 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
4887 pipeconf
|= PIPECONF_ENABLE
;
4889 if (intel_crtc
->config
.double_wide
)
4890 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4892 /* only g4x and later have fancy bpc/dither controls */
4893 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4894 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4895 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
4896 pipeconf
|= PIPECONF_DITHER_EN
|
4897 PIPECONF_DITHER_TYPE_SP
;
4899 switch (intel_crtc
->config
.pipe_bpp
) {
4901 pipeconf
|= PIPECONF_6BPC
;
4904 pipeconf
|= PIPECONF_8BPC
;
4907 pipeconf
|= PIPECONF_10BPC
;
4910 /* Case prevented by intel_choose_pipe_bpp_dither. */
4915 if (HAS_PIPE_CXSR(dev
)) {
4916 if (intel_crtc
->lowfreq_avail
) {
4917 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4918 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4920 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4924 if (!IS_GEN2(dev
) &&
4925 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4926 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4928 pipeconf
|= PIPECONF_PROGRESSIVE
;
4930 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
4931 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4933 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4934 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4937 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4939 struct drm_framebuffer
*fb
)
4941 struct drm_device
*dev
= crtc
->dev
;
4942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4943 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4944 int pipe
= intel_crtc
->pipe
;
4945 int plane
= intel_crtc
->plane
;
4946 int refclk
, num_connectors
= 0;
4947 intel_clock_t clock
, reduced_clock
;
4949 bool ok
, has_reduced_clock
= false;
4950 bool is_lvds
= false, is_dsi
= false;
4951 struct intel_encoder
*encoder
;
4952 const intel_limit_t
*limit
;
4955 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4956 switch (encoder
->type
) {
4957 case INTEL_OUTPUT_LVDS
:
4960 case INTEL_OUTPUT_DSI
:
4971 if (!intel_crtc
->config
.clock_set
) {
4972 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4975 * Returns a set of divisors for the desired target clock with
4976 * the given refclk, or FALSE. The returned values represent
4977 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4980 limit
= intel_limit(crtc
, refclk
);
4981 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
4982 intel_crtc
->config
.port_clock
,
4983 refclk
, NULL
, &clock
);
4985 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4989 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4991 * Ensure we match the reduced clock's P to the target
4992 * clock. If the clocks don't match, we can't switch
4993 * the display clock by using the FP0/FP1. In such case
4994 * we will disable the LVDS downclock feature.
4997 dev_priv
->display
.find_dpll(limit
, crtc
,
4998 dev_priv
->lvds_downclock
,
5002 /* Compat-code for transition, will disappear. */
5003 intel_crtc
->config
.dpll
.n
= clock
.n
;
5004 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5005 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5006 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5007 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5011 i8xx_update_pll(intel_crtc
,
5012 has_reduced_clock
? &reduced_clock
: NULL
,
5014 } else if (IS_VALLEYVIEW(dev
)) {
5015 vlv_update_pll(intel_crtc
);
5017 i9xx_update_pll(intel_crtc
,
5018 has_reduced_clock
? &reduced_clock
: NULL
,
5023 /* Set up the display plane register */
5024 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5026 if (!IS_VALLEYVIEW(dev
)) {
5028 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5030 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5033 intel_set_pipe_timings(intel_crtc
);
5035 /* pipesrc and dspsize control the size that is scaled from,
5036 * which should always be the user's requested size.
5038 I915_WRITE(DSPSIZE(plane
),
5039 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
5040 (intel_crtc
->config
.pipe_src_w
- 1));
5041 I915_WRITE(DSPPOS(plane
), 0);
5043 i9xx_set_pipeconf(intel_crtc
);
5045 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5046 POSTING_READ(DSPCNTR(plane
));
5048 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5053 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
5054 struct intel_crtc_config
*pipe_config
)
5056 struct drm_device
*dev
= crtc
->base
.dev
;
5057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5060 tmp
= I915_READ(PFIT_CONTROL
);
5061 if (!(tmp
& PFIT_ENABLE
))
5064 /* Check whether the pfit is attached to our pipe. */
5065 if (INTEL_INFO(dev
)->gen
< 4) {
5066 if (crtc
->pipe
!= PIPE_B
)
5069 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
5073 pipe_config
->gmch_pfit
.control
= tmp
;
5074 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
5075 if (INTEL_INFO(dev
)->gen
< 5)
5076 pipe_config
->gmch_pfit
.lvds_border_bits
=
5077 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
5080 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
5081 struct intel_crtc_config
*pipe_config
)
5083 struct drm_device
*dev
= crtc
->base
.dev
;
5084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5085 int pipe
= pipe_config
->cpu_transcoder
;
5086 intel_clock_t clock
;
5088 int refclk
= 100000;
5090 mutex_lock(&dev_priv
->dpio_lock
);
5091 mdiv
= vlv_dpio_read(dev_priv
, pipe
, DPIO_DIV(pipe
));
5092 mutex_unlock(&dev_priv
->dpio_lock
);
5094 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
5095 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
5096 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
5097 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
5098 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
5100 clock
.vco
= refclk
* clock
.m1
* clock
.m2
/ clock
.n
;
5101 clock
.dot
= 2 * clock
.vco
/ (clock
.p1
* clock
.p2
);
5103 pipe_config
->port_clock
= clock
.dot
/ 10;
5106 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
5107 struct intel_crtc_config
*pipe_config
)
5109 struct drm_device
*dev
= crtc
->base
.dev
;
5110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5113 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5114 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5116 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5117 if (!(tmp
& PIPECONF_ENABLE
))
5120 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5121 switch (tmp
& PIPECONF_BPC_MASK
) {
5123 pipe_config
->pipe_bpp
= 18;
5126 pipe_config
->pipe_bpp
= 24;
5128 case PIPECONF_10BPC
:
5129 pipe_config
->pipe_bpp
= 30;
5136 if (INTEL_INFO(dev
)->gen
< 4)
5137 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
5139 intel_get_pipe_timings(crtc
, pipe_config
);
5141 i9xx_get_pfit_config(crtc
, pipe_config
);
5143 if (INTEL_INFO(dev
)->gen
>= 4) {
5144 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5145 pipe_config
->pixel_multiplier
=
5146 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5147 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5148 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5149 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5150 tmp
= I915_READ(DPLL(crtc
->pipe
));
5151 pipe_config
->pixel_multiplier
=
5152 ((tmp
& SDVO_MULTIPLIER_MASK
)
5153 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5155 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5156 * port and will be fixed up in the encoder->get_config
5158 pipe_config
->pixel_multiplier
= 1;
5160 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5161 if (!IS_VALLEYVIEW(dev
)) {
5162 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5163 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5165 /* Mask out read-only status bits. */
5166 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5167 DPLL_PORTC_READY_MASK
|
5168 DPLL_PORTB_READY_MASK
);
5171 if (IS_VALLEYVIEW(dev
))
5172 vlv_crtc_clock_get(crtc
, pipe_config
);
5174 i9xx_crtc_clock_get(crtc
, pipe_config
);
5179 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5182 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5183 struct intel_encoder
*encoder
;
5185 bool has_lvds
= false;
5186 bool has_cpu_edp
= false;
5187 bool has_panel
= false;
5188 bool has_ck505
= false;
5189 bool can_ssc
= false;
5191 /* We need to take the global config into account */
5192 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5194 switch (encoder
->type
) {
5195 case INTEL_OUTPUT_LVDS
:
5199 case INTEL_OUTPUT_EDP
:
5201 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5207 if (HAS_PCH_IBX(dev
)) {
5208 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5209 can_ssc
= has_ck505
;
5215 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5216 has_panel
, has_lvds
, has_ck505
);
5218 /* Ironlake: try to setup display ref clock before DPLL
5219 * enabling. This is only under driver's control after
5220 * PCH B stepping, previous chipset stepping should be
5221 * ignoring this setting.
5223 val
= I915_READ(PCH_DREF_CONTROL
);
5225 /* As we must carefully and slowly disable/enable each source in turn,
5226 * compute the final state we want first and check if we need to
5227 * make any changes at all.
5230 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5232 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5234 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5236 final
&= ~DREF_SSC_SOURCE_MASK
;
5237 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5238 final
&= ~DREF_SSC1_ENABLE
;
5241 final
|= DREF_SSC_SOURCE_ENABLE
;
5243 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5244 final
|= DREF_SSC1_ENABLE
;
5247 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5248 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5250 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5252 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5254 final
|= DREF_SSC_SOURCE_DISABLE
;
5255 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5261 /* Always enable nonspread source */
5262 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5265 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5267 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5270 val
&= ~DREF_SSC_SOURCE_MASK
;
5271 val
|= DREF_SSC_SOURCE_ENABLE
;
5273 /* SSC must be turned on before enabling the CPU output */
5274 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5275 DRM_DEBUG_KMS("Using SSC on panel\n");
5276 val
|= DREF_SSC1_ENABLE
;
5278 val
&= ~DREF_SSC1_ENABLE
;
5280 /* Get SSC going before enabling the outputs */
5281 I915_WRITE(PCH_DREF_CONTROL
, val
);
5282 POSTING_READ(PCH_DREF_CONTROL
);
5285 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5287 /* Enable CPU source on CPU attached eDP */
5289 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5290 DRM_DEBUG_KMS("Using SSC on eDP\n");
5291 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5294 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5296 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5298 I915_WRITE(PCH_DREF_CONTROL
, val
);
5299 POSTING_READ(PCH_DREF_CONTROL
);
5302 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5304 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5306 /* Turn off CPU output */
5307 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5309 I915_WRITE(PCH_DREF_CONTROL
, val
);
5310 POSTING_READ(PCH_DREF_CONTROL
);
5313 /* Turn off the SSC source */
5314 val
&= ~DREF_SSC_SOURCE_MASK
;
5315 val
|= DREF_SSC_SOURCE_DISABLE
;
5318 val
&= ~DREF_SSC1_ENABLE
;
5320 I915_WRITE(PCH_DREF_CONTROL
, val
);
5321 POSTING_READ(PCH_DREF_CONTROL
);
5325 BUG_ON(val
!= final
);
5328 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5332 tmp
= I915_READ(SOUTH_CHICKEN2
);
5333 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5334 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5336 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5337 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5338 DRM_ERROR("FDI mPHY reset assert timeout\n");
5340 tmp
= I915_READ(SOUTH_CHICKEN2
);
5341 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5342 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5344 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5345 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5346 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5349 /* WaMPhyProgramming:hsw */
5350 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5354 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5355 tmp
&= ~(0xFF << 24);
5356 tmp
|= (0x12 << 24);
5357 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5359 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5361 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5363 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5365 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5367 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5368 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5369 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5371 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5372 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5373 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5375 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5378 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5380 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5383 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5385 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5388 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5390 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5393 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5395 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5396 tmp
&= ~(0xFF << 16);
5397 tmp
|= (0x1C << 16);
5398 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5400 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5401 tmp
&= ~(0xFF << 16);
5402 tmp
|= (0x1C << 16);
5403 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5405 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5407 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5409 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5411 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5413 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5414 tmp
&= ~(0xF << 28);
5416 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5418 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5419 tmp
&= ~(0xF << 28);
5421 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5424 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5425 * Programming" based on the parameters passed:
5426 * - Sequence to enable CLKOUT_DP
5427 * - Sequence to enable CLKOUT_DP without spread
5428 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5430 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5436 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5438 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5439 with_fdi
, "LP PCH doesn't have FDI\n"))
5442 mutex_lock(&dev_priv
->dpio_lock
);
5444 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5445 tmp
&= ~SBI_SSCCTL_DISABLE
;
5446 tmp
|= SBI_SSCCTL_PATHALT
;
5447 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5452 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5453 tmp
&= ~SBI_SSCCTL_PATHALT
;
5454 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5457 lpt_reset_fdi_mphy(dev_priv
);
5458 lpt_program_fdi_mphy(dev_priv
);
5462 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5463 SBI_GEN0
: SBI_DBUFF0
;
5464 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5465 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5466 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5468 mutex_unlock(&dev_priv
->dpio_lock
);
5471 /* Sequence to disable CLKOUT_DP */
5472 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5477 mutex_lock(&dev_priv
->dpio_lock
);
5479 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5480 SBI_GEN0
: SBI_DBUFF0
;
5481 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5482 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5483 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5485 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5486 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5487 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5488 tmp
|= SBI_SSCCTL_PATHALT
;
5489 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5492 tmp
|= SBI_SSCCTL_DISABLE
;
5493 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5496 mutex_unlock(&dev_priv
->dpio_lock
);
5499 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5501 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5502 struct intel_encoder
*encoder
;
5503 bool has_vga
= false;
5505 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5506 switch (encoder
->type
) {
5507 case INTEL_OUTPUT_ANALOG
:
5514 lpt_enable_clkout_dp(dev
, true, true);
5516 lpt_disable_clkout_dp(dev
);
5520 * Initialize reference clocks when the driver loads
5522 void intel_init_pch_refclk(struct drm_device
*dev
)
5524 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5525 ironlake_init_pch_refclk(dev
);
5526 else if (HAS_PCH_LPT(dev
))
5527 lpt_init_pch_refclk(dev
);
5530 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5532 struct drm_device
*dev
= crtc
->dev
;
5533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5534 struct intel_encoder
*encoder
;
5535 int num_connectors
= 0;
5536 bool is_lvds
= false;
5538 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5539 switch (encoder
->type
) {
5540 case INTEL_OUTPUT_LVDS
:
5547 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5548 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5549 dev_priv
->vbt
.lvds_ssc_freq
);
5550 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5556 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5558 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5559 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5560 int pipe
= intel_crtc
->pipe
;
5565 switch (intel_crtc
->config
.pipe_bpp
) {
5567 val
|= PIPECONF_6BPC
;
5570 val
|= PIPECONF_8BPC
;
5573 val
|= PIPECONF_10BPC
;
5576 val
|= PIPECONF_12BPC
;
5579 /* Case prevented by intel_choose_pipe_bpp_dither. */
5583 if (intel_crtc
->config
.dither
)
5584 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5586 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5587 val
|= PIPECONF_INTERLACED_ILK
;
5589 val
|= PIPECONF_PROGRESSIVE
;
5591 if (intel_crtc
->config
.limited_color_range
)
5592 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5594 I915_WRITE(PIPECONF(pipe
), val
);
5595 POSTING_READ(PIPECONF(pipe
));
5599 * Set up the pipe CSC unit.
5601 * Currently only full range RGB to limited range RGB conversion
5602 * is supported, but eventually this should handle various
5603 * RGB<->YCbCr scenarios as well.
5605 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5607 struct drm_device
*dev
= crtc
->dev
;
5608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5609 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5610 int pipe
= intel_crtc
->pipe
;
5611 uint16_t coeff
= 0x7800; /* 1.0 */
5614 * TODO: Check what kind of values actually come out of the pipe
5615 * with these coeff/postoff values and adjust to get the best
5616 * accuracy. Perhaps we even need to take the bpc value into
5620 if (intel_crtc
->config
.limited_color_range
)
5621 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5624 * GY/GU and RY/RU should be the other way around according
5625 * to BSpec, but reality doesn't agree. Just set them up in
5626 * a way that results in the correct picture.
5628 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5629 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5631 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5632 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5634 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5635 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5637 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5638 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5639 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5641 if (INTEL_INFO(dev
)->gen
> 6) {
5642 uint16_t postoff
= 0;
5644 if (intel_crtc
->config
.limited_color_range
)
5645 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5647 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5648 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5649 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5651 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5653 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5655 if (intel_crtc
->config
.limited_color_range
)
5656 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5658 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5662 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5664 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5665 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5666 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5671 if (intel_crtc
->config
.dither
)
5672 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5674 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5675 val
|= PIPECONF_INTERLACED_ILK
;
5677 val
|= PIPECONF_PROGRESSIVE
;
5679 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5680 POSTING_READ(PIPECONF(cpu_transcoder
));
5682 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5683 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5686 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5687 intel_clock_t
*clock
,
5688 bool *has_reduced_clock
,
5689 intel_clock_t
*reduced_clock
)
5691 struct drm_device
*dev
= crtc
->dev
;
5692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5693 struct intel_encoder
*intel_encoder
;
5695 const intel_limit_t
*limit
;
5696 bool ret
, is_lvds
= false;
5698 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5699 switch (intel_encoder
->type
) {
5700 case INTEL_OUTPUT_LVDS
:
5706 refclk
= ironlake_get_refclk(crtc
);
5709 * Returns a set of divisors for the desired target clock with the given
5710 * refclk, or FALSE. The returned values represent the clock equation:
5711 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5713 limit
= intel_limit(crtc
, refclk
);
5714 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5715 to_intel_crtc(crtc
)->config
.port_clock
,
5716 refclk
, NULL
, clock
);
5720 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5722 * Ensure we match the reduced clock's P to the target clock.
5723 * If the clocks don't match, we can't switch the display clock
5724 * by using the FP0/FP1. In such case we will disable the LVDS
5725 * downclock feature.
5727 *has_reduced_clock
=
5728 dev_priv
->display
.find_dpll(limit
, crtc
,
5729 dev_priv
->lvds_downclock
,
5737 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5742 temp
= I915_READ(SOUTH_CHICKEN1
);
5743 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5746 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5747 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5749 temp
|= FDI_BC_BIFURCATION_SELECT
;
5750 DRM_DEBUG_KMS("enabling fdi C rx\n");
5751 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5752 POSTING_READ(SOUTH_CHICKEN1
);
5755 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5757 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5760 switch (intel_crtc
->pipe
) {
5764 if (intel_crtc
->config
.fdi_lanes
> 2)
5765 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5767 cpt_enable_fdi_bc_bifurcation(dev
);
5771 cpt_enable_fdi_bc_bifurcation(dev
);
5779 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5782 * Account for spread spectrum to avoid
5783 * oversubscribing the link. Max center spread
5784 * is 2.5%; use 5% for safety's sake.
5786 u32 bps
= target_clock
* bpp
* 21 / 20;
5787 return bps
/ (link_bw
* 8) + 1;
5790 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5792 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5795 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5797 intel_clock_t
*reduced_clock
, u32
*fp2
)
5799 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5800 struct drm_device
*dev
= crtc
->dev
;
5801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5802 struct intel_encoder
*intel_encoder
;
5804 int factor
, num_connectors
= 0;
5805 bool is_lvds
= false, is_sdvo
= false;
5807 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5808 switch (intel_encoder
->type
) {
5809 case INTEL_OUTPUT_LVDS
:
5812 case INTEL_OUTPUT_SDVO
:
5813 case INTEL_OUTPUT_HDMI
:
5821 /* Enable autotuning of the PLL clock (if permissible) */
5824 if ((intel_panel_use_ssc(dev_priv
) &&
5825 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5826 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5828 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5831 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5834 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5840 dpll
|= DPLLB_MODE_LVDS
;
5842 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5844 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5845 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5848 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5849 if (intel_crtc
->config
.has_dp_encoder
)
5850 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5852 /* compute bitmask from p1 value */
5853 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5855 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5857 switch (intel_crtc
->config
.dpll
.p2
) {
5859 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5862 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5865 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5868 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5872 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5873 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5875 dpll
|= PLL_REF_INPUT_DREFCLK
;
5877 return dpll
| DPLL_VCO_ENABLE
;
5880 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5882 struct drm_framebuffer
*fb
)
5884 struct drm_device
*dev
= crtc
->dev
;
5885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5886 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5887 int pipe
= intel_crtc
->pipe
;
5888 int plane
= intel_crtc
->plane
;
5889 int num_connectors
= 0;
5890 intel_clock_t clock
, reduced_clock
;
5891 u32 dpll
= 0, fp
= 0, fp2
= 0;
5892 bool ok
, has_reduced_clock
= false;
5893 bool is_lvds
= false;
5894 struct intel_encoder
*encoder
;
5895 struct intel_shared_dpll
*pll
;
5898 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5899 switch (encoder
->type
) {
5900 case INTEL_OUTPUT_LVDS
:
5908 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5909 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5911 ok
= ironlake_compute_clocks(crtc
, &clock
,
5912 &has_reduced_clock
, &reduced_clock
);
5913 if (!ok
&& !intel_crtc
->config
.clock_set
) {
5914 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5917 /* Compat-code for transition, will disappear. */
5918 if (!intel_crtc
->config
.clock_set
) {
5919 intel_crtc
->config
.dpll
.n
= clock
.n
;
5920 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5921 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5922 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5923 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5926 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5927 if (intel_crtc
->config
.has_pch_encoder
) {
5928 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
5929 if (has_reduced_clock
)
5930 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
5932 dpll
= ironlake_compute_dpll(intel_crtc
,
5933 &fp
, &reduced_clock
,
5934 has_reduced_clock
? &fp2
: NULL
);
5936 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5937 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
5938 if (has_reduced_clock
)
5939 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5941 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
5943 pll
= intel_get_shared_dpll(intel_crtc
);
5945 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5950 intel_put_shared_dpll(intel_crtc
);
5952 if (intel_crtc
->config
.has_dp_encoder
)
5953 intel_dp_set_m_n(intel_crtc
);
5955 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
5956 intel_crtc
->lowfreq_avail
= true;
5958 intel_crtc
->lowfreq_avail
= false;
5960 if (intel_crtc
->config
.has_pch_encoder
) {
5961 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
5965 intel_set_pipe_timings(intel_crtc
);
5967 if (intel_crtc
->config
.has_pch_encoder
) {
5968 intel_cpu_transcoder_set_m_n(intel_crtc
,
5969 &intel_crtc
->config
.fdi_m_n
);
5972 if (IS_IVYBRIDGE(dev
))
5973 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
5975 ironlake_set_pipeconf(crtc
);
5977 /* Set up the display plane register */
5978 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5979 POSTING_READ(DSPCNTR(plane
));
5981 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5986 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
5987 struct intel_link_m_n
*m_n
)
5989 struct drm_device
*dev
= crtc
->base
.dev
;
5990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5991 enum pipe pipe
= crtc
->pipe
;
5993 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
5994 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
5995 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
5997 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
5998 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
5999 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6002 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
6003 enum transcoder transcoder
,
6004 struct intel_link_m_n
*m_n
)
6006 struct drm_device
*dev
= crtc
->base
.dev
;
6007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6008 enum pipe pipe
= crtc
->pipe
;
6010 if (INTEL_INFO(dev
)->gen
>= 5) {
6011 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
6012 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
6013 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
6015 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
6016 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
6017 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6019 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
6020 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
6021 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
6023 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
6024 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
6025 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6029 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
6030 struct intel_crtc_config
*pipe_config
)
6032 if (crtc
->config
.has_pch_encoder
)
6033 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
6035 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6036 &pipe_config
->dp_m_n
);
6039 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
6040 struct intel_crtc_config
*pipe_config
)
6042 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6043 &pipe_config
->fdi_m_n
);
6046 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
6047 struct intel_crtc_config
*pipe_config
)
6049 struct drm_device
*dev
= crtc
->base
.dev
;
6050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6053 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
6055 if (tmp
& PF_ENABLE
) {
6056 pipe_config
->pch_pfit
.enabled
= true;
6057 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
6058 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
6060 /* We currently do not free assignements of panel fitters on
6061 * ivb/hsw (since we don't use the higher upscaling modes which
6062 * differentiates them) so just WARN about this case for now. */
6064 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
6065 PF_PIPE_SEL_IVB(crtc
->pipe
));
6070 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
6071 struct intel_crtc_config
*pipe_config
)
6073 struct drm_device
*dev
= crtc
->base
.dev
;
6074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6077 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6078 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6080 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6081 if (!(tmp
& PIPECONF_ENABLE
))
6084 switch (tmp
& PIPECONF_BPC_MASK
) {
6086 pipe_config
->pipe_bpp
= 18;
6089 pipe_config
->pipe_bpp
= 24;
6091 case PIPECONF_10BPC
:
6092 pipe_config
->pipe_bpp
= 30;
6094 case PIPECONF_12BPC
:
6095 pipe_config
->pipe_bpp
= 36;
6101 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
6102 struct intel_shared_dpll
*pll
;
6104 pipe_config
->has_pch_encoder
= true;
6106 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
6107 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6108 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6110 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6112 if (HAS_PCH_IBX(dev_priv
->dev
)) {
6113 pipe_config
->shared_dpll
=
6114 (enum intel_dpll_id
) crtc
->pipe
;
6116 tmp
= I915_READ(PCH_DPLL_SEL
);
6117 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
6118 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
6120 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
6123 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
6125 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
6126 &pipe_config
->dpll_hw_state
));
6128 tmp
= pipe_config
->dpll_hw_state
.dpll
;
6129 pipe_config
->pixel_multiplier
=
6130 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
6131 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
6133 ironlake_pch_clock_get(crtc
, pipe_config
);
6135 pipe_config
->pixel_multiplier
= 1;
6138 intel_get_pipe_timings(crtc
, pipe_config
);
6140 ironlake_get_pfit_config(crtc
, pipe_config
);
6145 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
6147 struct drm_device
*dev
= dev_priv
->dev
;
6148 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
6149 struct intel_crtc
*crtc
;
6150 unsigned long irqflags
;
6153 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6154 WARN(crtc
->base
.enabled
, "CRTC for pipe %c enabled\n",
6155 pipe_name(crtc
->pipe
));
6157 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
6158 WARN(plls
->spll_refcount
, "SPLL enabled\n");
6159 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
6160 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
6161 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
6162 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
6163 "CPU PWM1 enabled\n");
6164 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
6165 "CPU PWM2 enabled\n");
6166 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
6167 "PCH PWM1 enabled\n");
6168 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
6169 "Utility pin enabled\n");
6170 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
6172 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
6173 val
= I915_READ(DEIMR
);
6174 WARN((val
& ~DE_PCH_EVENT_IVB
) != val
,
6175 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
6176 val
= I915_READ(SDEIMR
);
6177 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
6178 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
6179 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
6183 * This function implements pieces of two sequences from BSpec:
6184 * - Sequence for display software to disable LCPLL
6185 * - Sequence for display software to allow package C8+
6186 * The steps implemented here are just the steps that actually touch the LCPLL
6187 * register. Callers should take care of disabling all the display engine
6188 * functions, doing the mode unset, fixing interrupts, etc.
6190 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
6191 bool switch_to_fclk
, bool allow_power_down
)
6195 assert_can_disable_lcpll(dev_priv
);
6197 val
= I915_READ(LCPLL_CTL
);
6199 if (switch_to_fclk
) {
6200 val
|= LCPLL_CD_SOURCE_FCLK
;
6201 I915_WRITE(LCPLL_CTL
, val
);
6203 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6204 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6205 DRM_ERROR("Switching to FCLK failed\n");
6207 val
= I915_READ(LCPLL_CTL
);
6210 val
|= LCPLL_PLL_DISABLE
;
6211 I915_WRITE(LCPLL_CTL
, val
);
6212 POSTING_READ(LCPLL_CTL
);
6214 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6215 DRM_ERROR("LCPLL still locked\n");
6217 val
= I915_READ(D_COMP
);
6218 val
|= D_COMP_COMP_DISABLE
;
6219 mutex_lock(&dev_priv
->rps
.hw_lock
);
6220 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6221 DRM_ERROR("Failed to disable D_COMP\n");
6222 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6223 POSTING_READ(D_COMP
);
6226 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6227 DRM_ERROR("D_COMP RCOMP still in progress\n");
6229 if (allow_power_down
) {
6230 val
= I915_READ(LCPLL_CTL
);
6231 val
|= LCPLL_POWER_DOWN_ALLOW
;
6232 I915_WRITE(LCPLL_CTL
, val
);
6233 POSTING_READ(LCPLL_CTL
);
6238 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6241 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6245 val
= I915_READ(LCPLL_CTL
);
6247 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6248 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6251 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6252 * we'll hang the machine! */
6253 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
);
6255 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6256 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6257 I915_WRITE(LCPLL_CTL
, val
);
6258 POSTING_READ(LCPLL_CTL
);
6261 val
= I915_READ(D_COMP
);
6262 val
|= D_COMP_COMP_FORCE
;
6263 val
&= ~D_COMP_COMP_DISABLE
;
6264 mutex_lock(&dev_priv
->rps
.hw_lock
);
6265 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6266 DRM_ERROR("Failed to enable D_COMP\n");
6267 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6268 POSTING_READ(D_COMP
);
6270 val
= I915_READ(LCPLL_CTL
);
6271 val
&= ~LCPLL_PLL_DISABLE
;
6272 I915_WRITE(LCPLL_CTL
, val
);
6274 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6275 DRM_ERROR("LCPLL not locked yet\n");
6277 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6278 val
= I915_READ(LCPLL_CTL
);
6279 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6280 I915_WRITE(LCPLL_CTL
, val
);
6282 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6283 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6284 DRM_ERROR("Switching back to LCPLL failed\n");
6287 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
);
6290 void hsw_enable_pc8_work(struct work_struct
*__work
)
6292 struct drm_i915_private
*dev_priv
=
6293 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6295 struct drm_device
*dev
= dev_priv
->dev
;
6298 if (dev_priv
->pc8
.enabled
)
6301 DRM_DEBUG_KMS("Enabling package C8+\n");
6303 dev_priv
->pc8
.enabled
= true;
6305 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6306 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6307 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6308 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6311 lpt_disable_clkout_dp(dev
);
6312 hsw_pc8_disable_interrupts(dev
);
6313 hsw_disable_lcpll(dev_priv
, true, true);
6316 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6318 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6319 WARN(dev_priv
->pc8
.disable_count
< 1,
6320 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6322 dev_priv
->pc8
.disable_count
--;
6323 if (dev_priv
->pc8
.disable_count
!= 0)
6326 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6327 msecs_to_jiffies(i915_pc8_timeout
));
6330 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6332 struct drm_device
*dev
= dev_priv
->dev
;
6335 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6336 WARN(dev_priv
->pc8
.disable_count
< 0,
6337 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6339 dev_priv
->pc8
.disable_count
++;
6340 if (dev_priv
->pc8
.disable_count
!= 1)
6343 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6344 if (!dev_priv
->pc8
.enabled
)
6347 DRM_DEBUG_KMS("Disabling package C8+\n");
6349 hsw_restore_lcpll(dev_priv
);
6350 hsw_pc8_restore_interrupts(dev
);
6351 lpt_init_pch_refclk(dev
);
6353 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6354 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6355 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6356 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6359 intel_prepare_ddi(dev
);
6360 i915_gem_init_swizzling(dev
);
6361 mutex_lock(&dev_priv
->rps
.hw_lock
);
6362 gen6_update_ring_freq(dev
);
6363 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6364 dev_priv
->pc8
.enabled
= false;
6367 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6369 mutex_lock(&dev_priv
->pc8
.lock
);
6370 __hsw_enable_package_c8(dev_priv
);
6371 mutex_unlock(&dev_priv
->pc8
.lock
);
6374 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6376 mutex_lock(&dev_priv
->pc8
.lock
);
6377 __hsw_disable_package_c8(dev_priv
);
6378 mutex_unlock(&dev_priv
->pc8
.lock
);
6381 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6383 struct drm_device
*dev
= dev_priv
->dev
;
6384 struct intel_crtc
*crtc
;
6387 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6388 if (crtc
->base
.enabled
)
6391 /* This case is still possible since we have the i915.disable_power_well
6392 * parameter and also the KVMr or something else might be requesting the
6394 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6396 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6403 /* Since we're called from modeset_global_resources there's no way to
6404 * symmetrically increase and decrease the refcount, so we use
6405 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6408 static void hsw_update_package_c8(struct drm_device
*dev
)
6410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6413 if (!i915_enable_pc8
)
6416 mutex_lock(&dev_priv
->pc8
.lock
);
6418 allow
= hsw_can_enable_package_c8(dev_priv
);
6420 if (allow
== dev_priv
->pc8
.requirements_met
)
6423 dev_priv
->pc8
.requirements_met
= allow
;
6426 __hsw_enable_package_c8(dev_priv
);
6428 __hsw_disable_package_c8(dev_priv
);
6431 mutex_unlock(&dev_priv
->pc8
.lock
);
6434 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6436 if (!dev_priv
->pc8
.gpu_idle
) {
6437 dev_priv
->pc8
.gpu_idle
= true;
6438 hsw_enable_package_c8(dev_priv
);
6442 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6444 if (dev_priv
->pc8
.gpu_idle
) {
6445 dev_priv
->pc8
.gpu_idle
= false;
6446 hsw_disable_package_c8(dev_priv
);
6450 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6452 bool enable
= false;
6453 struct intel_crtc
*crtc
;
6455 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6456 if (!crtc
->base
.enabled
)
6459 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.enabled
||
6460 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
6464 intel_set_power_well(dev
, enable
);
6466 hsw_update_package_c8(dev
);
6469 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6471 struct drm_framebuffer
*fb
)
6473 struct drm_device
*dev
= crtc
->dev
;
6474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6475 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6476 int plane
= intel_crtc
->plane
;
6479 if (!intel_ddi_pll_mode_set(crtc
))
6482 if (intel_crtc
->config
.has_dp_encoder
)
6483 intel_dp_set_m_n(intel_crtc
);
6485 intel_crtc
->lowfreq_avail
= false;
6487 intel_set_pipe_timings(intel_crtc
);
6489 if (intel_crtc
->config
.has_pch_encoder
) {
6490 intel_cpu_transcoder_set_m_n(intel_crtc
,
6491 &intel_crtc
->config
.fdi_m_n
);
6494 haswell_set_pipeconf(crtc
);
6496 intel_set_pipe_csc(crtc
);
6498 /* Set up the display plane register */
6499 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6500 POSTING_READ(DSPCNTR(plane
));
6502 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6507 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6508 struct intel_crtc_config
*pipe_config
)
6510 struct drm_device
*dev
= crtc
->base
.dev
;
6511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6512 enum intel_display_power_domain pfit_domain
;
6515 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6516 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6518 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6519 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6520 enum pipe trans_edp_pipe
;
6521 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6523 WARN(1, "unknown pipe linked to edp transcoder\n");
6524 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6525 case TRANS_DDI_EDP_INPUT_A_ON
:
6526 trans_edp_pipe
= PIPE_A
;
6528 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6529 trans_edp_pipe
= PIPE_B
;
6531 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6532 trans_edp_pipe
= PIPE_C
;
6536 if (trans_edp_pipe
== crtc
->pipe
)
6537 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6540 if (!intel_display_power_enabled(dev
,
6541 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6544 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6545 if (!(tmp
& PIPECONF_ENABLE
))
6549 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6550 * DDI E. So just check whether this pipe is wired to DDI E and whether
6551 * the PCH transcoder is on.
6553 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6554 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6555 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6556 pipe_config
->has_pch_encoder
= true;
6558 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6559 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6560 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6562 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6565 intel_get_pipe_timings(crtc
, pipe_config
);
6567 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6568 if (intel_display_power_enabled(dev
, pfit_domain
))
6569 ironlake_get_pfit_config(crtc
, pipe_config
);
6571 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6572 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6574 pipe_config
->pixel_multiplier
= 1;
6579 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6581 struct drm_framebuffer
*fb
)
6583 struct drm_device
*dev
= crtc
->dev
;
6584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6585 struct intel_encoder
*encoder
;
6586 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6587 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6588 int pipe
= intel_crtc
->pipe
;
6591 drm_vblank_pre_modeset(dev
, pipe
);
6593 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6595 drm_vblank_post_modeset(dev
, pipe
);
6600 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6601 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6602 encoder
->base
.base
.id
,
6603 drm_get_encoder_name(&encoder
->base
),
6604 mode
->base
.id
, mode
->name
);
6605 encoder
->mode_set(encoder
);
6611 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6612 int reg_eldv
, uint32_t bits_eldv
,
6613 int reg_elda
, uint32_t bits_elda
,
6616 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6617 uint8_t *eld
= connector
->eld
;
6620 i
= I915_READ(reg_eldv
);
6629 i
= I915_READ(reg_elda
);
6631 I915_WRITE(reg_elda
, i
);
6633 for (i
= 0; i
< eld
[2]; i
++)
6634 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6640 static void g4x_write_eld(struct drm_connector
*connector
,
6641 struct drm_crtc
*crtc
)
6643 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6644 uint8_t *eld
= connector
->eld
;
6649 i
= I915_READ(G4X_AUD_VID_DID
);
6651 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6652 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6654 eldv
= G4X_ELDV_DEVCTG
;
6656 if (intel_eld_uptodate(connector
,
6657 G4X_AUD_CNTL_ST
, eldv
,
6658 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6659 G4X_HDMIW_HDMIEDID
))
6662 i
= I915_READ(G4X_AUD_CNTL_ST
);
6663 i
&= ~(eldv
| G4X_ELD_ADDR
);
6664 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6665 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6670 len
= min_t(uint8_t, eld
[2], len
);
6671 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6672 for (i
= 0; i
< len
; i
++)
6673 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6675 i
= I915_READ(G4X_AUD_CNTL_ST
);
6677 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6680 static void haswell_write_eld(struct drm_connector
*connector
,
6681 struct drm_crtc
*crtc
)
6683 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6684 uint8_t *eld
= connector
->eld
;
6685 struct drm_device
*dev
= crtc
->dev
;
6686 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6690 int pipe
= to_intel_crtc(crtc
)->pipe
;
6693 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6694 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6695 int aud_config
= HSW_AUD_CFG(pipe
);
6696 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6699 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6701 /* Audio output enable */
6702 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6703 tmp
= I915_READ(aud_cntrl_st2
);
6704 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6705 I915_WRITE(aud_cntrl_st2
, tmp
);
6707 /* Wait for 1 vertical blank */
6708 intel_wait_for_vblank(dev
, pipe
);
6710 /* Set ELD valid state */
6711 tmp
= I915_READ(aud_cntrl_st2
);
6712 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
6713 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6714 I915_WRITE(aud_cntrl_st2
, tmp
);
6715 tmp
= I915_READ(aud_cntrl_st2
);
6716 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
6718 /* Enable HDMI mode */
6719 tmp
= I915_READ(aud_config
);
6720 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
6721 /* clear N_programing_enable and N_value_index */
6722 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6723 I915_WRITE(aud_config
, tmp
);
6725 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6727 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6728 intel_crtc
->eld_vld
= true;
6730 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6731 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6732 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6733 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6735 I915_WRITE(aud_config
, 0);
6737 if (intel_eld_uptodate(connector
,
6738 aud_cntrl_st2
, eldv
,
6739 aud_cntl_st
, IBX_ELD_ADDRESS
,
6743 i
= I915_READ(aud_cntrl_st2
);
6745 I915_WRITE(aud_cntrl_st2
, i
);
6750 i
= I915_READ(aud_cntl_st
);
6751 i
&= ~IBX_ELD_ADDRESS
;
6752 I915_WRITE(aud_cntl_st
, i
);
6753 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6754 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6756 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6757 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6758 for (i
= 0; i
< len
; i
++)
6759 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6761 i
= I915_READ(aud_cntrl_st2
);
6763 I915_WRITE(aud_cntrl_st2
, i
);
6767 static void ironlake_write_eld(struct drm_connector
*connector
,
6768 struct drm_crtc
*crtc
)
6770 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6771 uint8_t *eld
= connector
->eld
;
6779 int pipe
= to_intel_crtc(crtc
)->pipe
;
6781 if (HAS_PCH_IBX(connector
->dev
)) {
6782 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6783 aud_config
= IBX_AUD_CFG(pipe
);
6784 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6785 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6787 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6788 aud_config
= CPT_AUD_CFG(pipe
);
6789 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6790 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6793 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6795 i
= I915_READ(aud_cntl_st
);
6796 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6798 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6799 /* operate blindly on all ports */
6800 eldv
= IBX_ELD_VALIDB
;
6801 eldv
|= IBX_ELD_VALIDB
<< 4;
6802 eldv
|= IBX_ELD_VALIDB
<< 8;
6804 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6805 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6808 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6809 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6810 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6811 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6813 I915_WRITE(aud_config
, 0);
6815 if (intel_eld_uptodate(connector
,
6816 aud_cntrl_st2
, eldv
,
6817 aud_cntl_st
, IBX_ELD_ADDRESS
,
6821 i
= I915_READ(aud_cntrl_st2
);
6823 I915_WRITE(aud_cntrl_st2
, i
);
6828 i
= I915_READ(aud_cntl_st
);
6829 i
&= ~IBX_ELD_ADDRESS
;
6830 I915_WRITE(aud_cntl_st
, i
);
6832 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6833 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6834 for (i
= 0; i
< len
; i
++)
6835 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6837 i
= I915_READ(aud_cntrl_st2
);
6839 I915_WRITE(aud_cntrl_st2
, i
);
6842 void intel_write_eld(struct drm_encoder
*encoder
,
6843 struct drm_display_mode
*mode
)
6845 struct drm_crtc
*crtc
= encoder
->crtc
;
6846 struct drm_connector
*connector
;
6847 struct drm_device
*dev
= encoder
->dev
;
6848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6850 connector
= drm_select_eld(encoder
, mode
);
6854 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6856 drm_get_connector_name(connector
),
6857 connector
->encoder
->base
.id
,
6858 drm_get_encoder_name(connector
->encoder
));
6860 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6862 if (dev_priv
->display
.write_eld
)
6863 dev_priv
->display
.write_eld(connector
, crtc
);
6866 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6868 struct drm_device
*dev
= crtc
->dev
;
6869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6870 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6871 bool visible
= base
!= 0;
6874 if (intel_crtc
->cursor_visible
== visible
)
6877 cntl
= I915_READ(_CURACNTR
);
6879 /* On these chipsets we can only modify the base whilst
6880 * the cursor is disabled.
6882 I915_WRITE(_CURABASE
, base
);
6884 cntl
&= ~(CURSOR_FORMAT_MASK
);
6885 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6886 cntl
|= CURSOR_ENABLE
|
6887 CURSOR_GAMMA_ENABLE
|
6890 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6891 I915_WRITE(_CURACNTR
, cntl
);
6893 intel_crtc
->cursor_visible
= visible
;
6896 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6898 struct drm_device
*dev
= crtc
->dev
;
6899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6900 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6901 int pipe
= intel_crtc
->pipe
;
6902 bool visible
= base
!= 0;
6904 if (intel_crtc
->cursor_visible
!= visible
) {
6905 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6907 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6908 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6909 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6911 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6912 cntl
|= CURSOR_MODE_DISABLE
;
6914 I915_WRITE(CURCNTR(pipe
), cntl
);
6916 intel_crtc
->cursor_visible
= visible
;
6918 /* and commit changes on next vblank */
6919 I915_WRITE(CURBASE(pipe
), base
);
6922 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6924 struct drm_device
*dev
= crtc
->dev
;
6925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6926 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6927 int pipe
= intel_crtc
->pipe
;
6928 bool visible
= base
!= 0;
6930 if (intel_crtc
->cursor_visible
!= visible
) {
6931 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6933 cntl
&= ~CURSOR_MODE
;
6934 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6936 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6937 cntl
|= CURSOR_MODE_DISABLE
;
6939 if (IS_HASWELL(dev
)) {
6940 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6941 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
6943 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6945 intel_crtc
->cursor_visible
= visible
;
6947 /* and commit changes on next vblank */
6948 I915_WRITE(CURBASE_IVB(pipe
), base
);
6951 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6952 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6955 struct drm_device
*dev
= crtc
->dev
;
6956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6957 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6958 int pipe
= intel_crtc
->pipe
;
6959 int x
= intel_crtc
->cursor_x
;
6960 int y
= intel_crtc
->cursor_y
;
6961 u32 base
= 0, pos
= 0;
6965 base
= intel_crtc
->cursor_addr
;
6967 if (x
>= intel_crtc
->config
.pipe_src_w
)
6970 if (y
>= intel_crtc
->config
.pipe_src_h
)
6974 if (x
+ intel_crtc
->cursor_width
<= 0)
6977 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6980 pos
|= x
<< CURSOR_X_SHIFT
;
6983 if (y
+ intel_crtc
->cursor_height
<= 0)
6986 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6989 pos
|= y
<< CURSOR_Y_SHIFT
;
6991 visible
= base
!= 0;
6992 if (!visible
&& !intel_crtc
->cursor_visible
)
6995 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6996 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6997 ivb_update_cursor(crtc
, base
);
6999 I915_WRITE(CURPOS(pipe
), pos
);
7000 if (IS_845G(dev
) || IS_I865G(dev
))
7001 i845_update_cursor(crtc
, base
);
7003 i9xx_update_cursor(crtc
, base
);
7007 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
7008 struct drm_file
*file
,
7010 uint32_t width
, uint32_t height
)
7012 struct drm_device
*dev
= crtc
->dev
;
7013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7014 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7015 struct drm_i915_gem_object
*obj
;
7019 /* if we want to turn off the cursor ignore width and height */
7021 DRM_DEBUG_KMS("cursor off\n");
7024 mutex_lock(&dev
->struct_mutex
);
7028 /* Currently we only support 64x64 cursors */
7029 if (width
!= 64 || height
!= 64) {
7030 DRM_ERROR("we currently only support 64x64 cursors\n");
7034 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
7035 if (&obj
->base
== NULL
)
7038 if (obj
->base
.size
< width
* height
* 4) {
7039 DRM_ERROR("buffer is to small\n");
7044 /* we only need to pin inside GTT if cursor is non-phy */
7045 mutex_lock(&dev
->struct_mutex
);
7046 if (!dev_priv
->info
->cursor_needs_physical
) {
7049 if (obj
->tiling_mode
) {
7050 DRM_ERROR("cursor cannot be tiled\n");
7055 /* Note that the w/a also requires 2 PTE of padding following
7056 * the bo. We currently fill all unused PTE with the shadow
7057 * page and so we should always have valid PTE following the
7058 * cursor preventing the VT-d warning.
7061 if (need_vtd_wa(dev
))
7062 alignment
= 64*1024;
7064 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
7066 DRM_ERROR("failed to move cursor bo into the GTT\n");
7070 ret
= i915_gem_object_put_fence(obj
);
7072 DRM_ERROR("failed to release fence for cursor");
7076 addr
= i915_gem_obj_ggtt_offset(obj
);
7078 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
7079 ret
= i915_gem_attach_phys_object(dev
, obj
,
7080 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
7083 DRM_ERROR("failed to attach phys object\n");
7086 addr
= obj
->phys_obj
->handle
->busaddr
;
7090 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
7093 if (intel_crtc
->cursor_bo
) {
7094 if (dev_priv
->info
->cursor_needs_physical
) {
7095 if (intel_crtc
->cursor_bo
!= obj
)
7096 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
7098 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
7099 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
7102 mutex_unlock(&dev
->struct_mutex
);
7104 intel_crtc
->cursor_addr
= addr
;
7105 intel_crtc
->cursor_bo
= obj
;
7106 intel_crtc
->cursor_width
= width
;
7107 intel_crtc
->cursor_height
= height
;
7109 if (intel_crtc
->active
)
7110 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7114 i915_gem_object_unpin_from_display_plane(obj
);
7116 mutex_unlock(&dev
->struct_mutex
);
7118 drm_gem_object_unreference_unlocked(&obj
->base
);
7122 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
7124 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7126 intel_crtc
->cursor_x
= x
;
7127 intel_crtc
->cursor_y
= y
;
7129 if (intel_crtc
->active
)
7130 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7135 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7136 u16
*blue
, uint32_t start
, uint32_t size
)
7138 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7139 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7141 for (i
= start
; i
< end
; i
++) {
7142 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7143 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7144 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7147 intel_crtc_load_lut(crtc
);
7150 /* VESA 640x480x72Hz mode to set on the pipe */
7151 static struct drm_display_mode load_detect_mode
= {
7152 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7153 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7156 static struct drm_framebuffer
*
7157 intel_framebuffer_create(struct drm_device
*dev
,
7158 struct drm_mode_fb_cmd2
*mode_cmd
,
7159 struct drm_i915_gem_object
*obj
)
7161 struct intel_framebuffer
*intel_fb
;
7164 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7166 drm_gem_object_unreference_unlocked(&obj
->base
);
7167 return ERR_PTR(-ENOMEM
);
7170 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7172 drm_gem_object_unreference_unlocked(&obj
->base
);
7174 return ERR_PTR(ret
);
7177 return &intel_fb
->base
;
7181 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7183 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7184 return ALIGN(pitch
, 64);
7188 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7190 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7191 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7194 static struct drm_framebuffer
*
7195 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7196 struct drm_display_mode
*mode
,
7199 struct drm_i915_gem_object
*obj
;
7200 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7202 obj
= i915_gem_alloc_object(dev
,
7203 intel_framebuffer_size_for_mode(mode
, bpp
));
7205 return ERR_PTR(-ENOMEM
);
7207 mode_cmd
.width
= mode
->hdisplay
;
7208 mode_cmd
.height
= mode
->vdisplay
;
7209 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7211 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7213 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7216 static struct drm_framebuffer
*
7217 mode_fits_in_fbdev(struct drm_device
*dev
,
7218 struct drm_display_mode
*mode
)
7220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7221 struct drm_i915_gem_object
*obj
;
7222 struct drm_framebuffer
*fb
;
7224 if (dev_priv
->fbdev
== NULL
)
7227 obj
= dev_priv
->fbdev
->ifb
.obj
;
7231 fb
= &dev_priv
->fbdev
->ifb
.base
;
7232 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7233 fb
->bits_per_pixel
))
7236 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7242 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7243 struct drm_display_mode
*mode
,
7244 struct intel_load_detect_pipe
*old
)
7246 struct intel_crtc
*intel_crtc
;
7247 struct intel_encoder
*intel_encoder
=
7248 intel_attached_encoder(connector
);
7249 struct drm_crtc
*possible_crtc
;
7250 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7251 struct drm_crtc
*crtc
= NULL
;
7252 struct drm_device
*dev
= encoder
->dev
;
7253 struct drm_framebuffer
*fb
;
7256 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7257 connector
->base
.id
, drm_get_connector_name(connector
),
7258 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7261 * Algorithm gets a little messy:
7263 * - if the connector already has an assigned crtc, use it (but make
7264 * sure it's on first)
7266 * - try to find the first unused crtc that can drive this connector,
7267 * and use that if we find one
7270 /* See if we already have a CRTC for this connector */
7271 if (encoder
->crtc
) {
7272 crtc
= encoder
->crtc
;
7274 mutex_lock(&crtc
->mutex
);
7276 old
->dpms_mode
= connector
->dpms
;
7277 old
->load_detect_temp
= false;
7279 /* Make sure the crtc and connector are running */
7280 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7281 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7286 /* Find an unused one (if possible) */
7287 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7289 if (!(encoder
->possible_crtcs
& (1 << i
)))
7291 if (!possible_crtc
->enabled
) {
7292 crtc
= possible_crtc
;
7298 * If we didn't find an unused CRTC, don't use any.
7301 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7305 mutex_lock(&crtc
->mutex
);
7306 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7307 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7309 intel_crtc
= to_intel_crtc(crtc
);
7310 old
->dpms_mode
= connector
->dpms
;
7311 old
->load_detect_temp
= true;
7312 old
->release_fb
= NULL
;
7315 mode
= &load_detect_mode
;
7317 /* We need a framebuffer large enough to accommodate all accesses
7318 * that the plane may generate whilst we perform load detection.
7319 * We can not rely on the fbcon either being present (we get called
7320 * during its initialisation to detect all boot displays, or it may
7321 * not even exist) or that it is large enough to satisfy the
7324 fb
= mode_fits_in_fbdev(dev
, mode
);
7326 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7327 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7328 old
->release_fb
= fb
;
7330 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7332 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7333 mutex_unlock(&crtc
->mutex
);
7337 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7338 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7339 if (old
->release_fb
)
7340 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7341 mutex_unlock(&crtc
->mutex
);
7345 /* let the connector get through one full cycle before testing */
7346 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7350 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7351 struct intel_load_detect_pipe
*old
)
7353 struct intel_encoder
*intel_encoder
=
7354 intel_attached_encoder(connector
);
7355 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7356 struct drm_crtc
*crtc
= encoder
->crtc
;
7358 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7359 connector
->base
.id
, drm_get_connector_name(connector
),
7360 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7362 if (old
->load_detect_temp
) {
7363 to_intel_connector(connector
)->new_encoder
= NULL
;
7364 intel_encoder
->new_crtc
= NULL
;
7365 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7367 if (old
->release_fb
) {
7368 drm_framebuffer_unregister_private(old
->release_fb
);
7369 drm_framebuffer_unreference(old
->release_fb
);
7372 mutex_unlock(&crtc
->mutex
);
7376 /* Switch crtc and encoder back off if necessary */
7377 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7378 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7380 mutex_unlock(&crtc
->mutex
);
7383 static int i9xx_pll_refclk(struct drm_device
*dev
,
7384 const struct intel_crtc_config
*pipe_config
)
7386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7387 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7389 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
7390 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
7391 else if (HAS_PCH_SPLIT(dev
))
7393 else if (!IS_GEN2(dev
))
7399 /* Returns the clock of the currently programmed mode of the given pipe. */
7400 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7401 struct intel_crtc_config
*pipe_config
)
7403 struct drm_device
*dev
= crtc
->base
.dev
;
7404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7405 int pipe
= pipe_config
->cpu_transcoder
;
7406 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7408 intel_clock_t clock
;
7409 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
7411 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7412 fp
= pipe_config
->dpll_hw_state
.fp0
;
7414 fp
= pipe_config
->dpll_hw_state
.fp1
;
7416 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7417 if (IS_PINEVIEW(dev
)) {
7418 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7419 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7421 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7422 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7425 if (!IS_GEN2(dev
)) {
7426 if (IS_PINEVIEW(dev
))
7427 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7428 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7430 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7431 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7433 switch (dpll
& DPLL_MODE_MASK
) {
7434 case DPLLB_MODE_DAC_SERIAL
:
7435 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7438 case DPLLB_MODE_LVDS
:
7439 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7443 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7444 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7448 if (IS_PINEVIEW(dev
))
7449 pineview_clock(refclk
, &clock
);
7451 i9xx_clock(refclk
, &clock
);
7453 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7456 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7457 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7460 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7463 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7464 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7466 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7472 i9xx_clock(refclk
, &clock
);
7476 * This value includes pixel_multiplier. We will use
7477 * port_clock to compute adjusted_mode.crtc_clock in the
7478 * encoder's get_config() function.
7480 pipe_config
->port_clock
= clock
.dot
;
7483 int intel_dotclock_calculate(int link_freq
,
7484 const struct intel_link_m_n
*m_n
)
7487 * The calculation for the data clock is:
7488 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7489 * But we want to avoid losing precison if possible, so:
7490 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7492 * and the link clock is simpler:
7493 * link_clock = (m * link_clock) / n
7499 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
7502 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
7503 struct intel_crtc_config
*pipe_config
)
7505 struct drm_device
*dev
= crtc
->base
.dev
;
7507 /* read out port_clock from the DPLL */
7508 i9xx_crtc_clock_get(crtc
, pipe_config
);
7511 * This value does not include pixel_multiplier.
7512 * We will check that port_clock and adjusted_mode.crtc_clock
7513 * agree once we know their relationship in the encoder's
7514 * get_config() function.
7516 pipe_config
->adjusted_mode
.crtc_clock
=
7517 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
7518 &pipe_config
->fdi_m_n
);
7521 /** Returns the currently programmed mode of the given pipe. */
7522 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7523 struct drm_crtc
*crtc
)
7525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7526 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7527 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7528 struct drm_display_mode
*mode
;
7529 struct intel_crtc_config pipe_config
;
7530 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7531 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7532 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7533 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7534 enum pipe pipe
= intel_crtc
->pipe
;
7536 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7541 * Construct a pipe_config sufficient for getting the clock info
7542 * back out of crtc_clock_get.
7544 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7545 * to use a real value here instead.
7547 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
7548 pipe_config
.pixel_multiplier
= 1;
7549 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
7550 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
7551 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
7552 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
7554 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
7555 mode
->hdisplay
= (htot
& 0xffff) + 1;
7556 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7557 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7558 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7559 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7560 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7561 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7562 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7564 drm_mode_set_name(mode
);
7569 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7571 struct drm_device
*dev
= crtc
->dev
;
7572 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7573 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7574 int pipe
= intel_crtc
->pipe
;
7575 int dpll_reg
= DPLL(pipe
);
7578 if (HAS_PCH_SPLIT(dev
))
7581 if (!dev_priv
->lvds_downclock_avail
)
7584 dpll
= I915_READ(dpll_reg
);
7585 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7586 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7588 assert_panel_unlocked(dev_priv
, pipe
);
7590 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7591 I915_WRITE(dpll_reg
, dpll
);
7592 intel_wait_for_vblank(dev
, pipe
);
7594 dpll
= I915_READ(dpll_reg
);
7595 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7596 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7600 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7602 struct drm_device
*dev
= crtc
->dev
;
7603 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7604 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7606 if (HAS_PCH_SPLIT(dev
))
7609 if (!dev_priv
->lvds_downclock_avail
)
7613 * Since this is called by a timer, we should never get here in
7616 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7617 int pipe
= intel_crtc
->pipe
;
7618 int dpll_reg
= DPLL(pipe
);
7621 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7623 assert_panel_unlocked(dev_priv
, pipe
);
7625 dpll
= I915_READ(dpll_reg
);
7626 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7627 I915_WRITE(dpll_reg
, dpll
);
7628 intel_wait_for_vblank(dev
, pipe
);
7629 dpll
= I915_READ(dpll_reg
);
7630 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7631 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7636 void intel_mark_busy(struct drm_device
*dev
)
7638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7640 hsw_package_c8_gpu_busy(dev_priv
);
7641 i915_update_gfx_val(dev_priv
);
7644 void intel_mark_idle(struct drm_device
*dev
)
7646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7647 struct drm_crtc
*crtc
;
7649 hsw_package_c8_gpu_idle(dev_priv
);
7651 if (!i915_powersave
)
7654 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7658 intel_decrease_pllclock(crtc
);
7662 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7663 struct intel_ring_buffer
*ring
)
7665 struct drm_device
*dev
= obj
->base
.dev
;
7666 struct drm_crtc
*crtc
;
7668 if (!i915_powersave
)
7671 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7675 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7678 intel_increase_pllclock(crtc
);
7679 if (ring
&& intel_fbc_enabled(dev
))
7680 ring
->fbc_dirty
= true;
7684 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7686 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7687 struct drm_device
*dev
= crtc
->dev
;
7688 struct intel_unpin_work
*work
;
7689 unsigned long flags
;
7691 spin_lock_irqsave(&dev
->event_lock
, flags
);
7692 work
= intel_crtc
->unpin_work
;
7693 intel_crtc
->unpin_work
= NULL
;
7694 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7697 cancel_work_sync(&work
->work
);
7701 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7703 drm_crtc_cleanup(crtc
);
7708 static void intel_unpin_work_fn(struct work_struct
*__work
)
7710 struct intel_unpin_work
*work
=
7711 container_of(__work
, struct intel_unpin_work
, work
);
7712 struct drm_device
*dev
= work
->crtc
->dev
;
7714 mutex_lock(&dev
->struct_mutex
);
7715 intel_unpin_fb_obj(work
->old_fb_obj
);
7716 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7717 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7719 intel_update_fbc(dev
);
7720 mutex_unlock(&dev
->struct_mutex
);
7722 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7723 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7728 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7729 struct drm_crtc
*crtc
)
7731 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7732 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7733 struct intel_unpin_work
*work
;
7734 unsigned long flags
;
7736 /* Ignore early vblank irqs */
7737 if (intel_crtc
== NULL
)
7740 spin_lock_irqsave(&dev
->event_lock
, flags
);
7741 work
= intel_crtc
->unpin_work
;
7743 /* Ensure we don't miss a work->pending update ... */
7746 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7747 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7751 /* and that the unpin work is consistent wrt ->pending. */
7754 intel_crtc
->unpin_work
= NULL
;
7757 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7759 drm_vblank_put(dev
, intel_crtc
->pipe
);
7761 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7763 wake_up_all(&dev_priv
->pending_flip_queue
);
7765 queue_work(dev_priv
->wq
, &work
->work
);
7767 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7770 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7772 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7773 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7775 do_intel_finish_page_flip(dev
, crtc
);
7778 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7780 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7781 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7783 do_intel_finish_page_flip(dev
, crtc
);
7786 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7788 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7789 struct intel_crtc
*intel_crtc
=
7790 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7791 unsigned long flags
;
7793 /* NB: An MMIO update of the plane base pointer will also
7794 * generate a page-flip completion irq, i.e. every modeset
7795 * is also accompanied by a spurious intel_prepare_page_flip().
7797 spin_lock_irqsave(&dev
->event_lock
, flags
);
7798 if (intel_crtc
->unpin_work
)
7799 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7800 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7803 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7805 /* Ensure that the work item is consistent when activating it ... */
7807 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7808 /* and that it is marked active as soon as the irq could fire. */
7812 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7813 struct drm_crtc
*crtc
,
7814 struct drm_framebuffer
*fb
,
7815 struct drm_i915_gem_object
*obj
,
7818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7819 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7821 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7824 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7828 ret
= intel_ring_begin(ring
, 6);
7832 /* Can't queue multiple flips, so wait for the previous
7833 * one to finish before executing the next.
7835 if (intel_crtc
->plane
)
7836 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7838 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7839 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7840 intel_ring_emit(ring
, MI_NOOP
);
7841 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7842 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7843 intel_ring_emit(ring
, fb
->pitches
[0]);
7844 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7845 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7847 intel_mark_page_flip_active(intel_crtc
);
7848 __intel_ring_advance(ring
);
7852 intel_unpin_fb_obj(obj
);
7857 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7858 struct drm_crtc
*crtc
,
7859 struct drm_framebuffer
*fb
,
7860 struct drm_i915_gem_object
*obj
,
7863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7864 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7866 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7869 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7873 ret
= intel_ring_begin(ring
, 6);
7877 if (intel_crtc
->plane
)
7878 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7880 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7881 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7882 intel_ring_emit(ring
, MI_NOOP
);
7883 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7884 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7885 intel_ring_emit(ring
, fb
->pitches
[0]);
7886 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7887 intel_ring_emit(ring
, MI_NOOP
);
7889 intel_mark_page_flip_active(intel_crtc
);
7890 __intel_ring_advance(ring
);
7894 intel_unpin_fb_obj(obj
);
7899 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7900 struct drm_crtc
*crtc
,
7901 struct drm_framebuffer
*fb
,
7902 struct drm_i915_gem_object
*obj
,
7905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7906 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7907 uint32_t pf
, pipesrc
;
7908 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7911 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7915 ret
= intel_ring_begin(ring
, 4);
7919 /* i965+ uses the linear or tiled offsets from the
7920 * Display Registers (which do not change across a page-flip)
7921 * so we need only reprogram the base address.
7923 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7924 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7925 intel_ring_emit(ring
, fb
->pitches
[0]);
7926 intel_ring_emit(ring
,
7927 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
7930 /* XXX Enabling the panel-fitter across page-flip is so far
7931 * untested on non-native modes, so ignore it for now.
7932 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7935 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7936 intel_ring_emit(ring
, pf
| pipesrc
);
7938 intel_mark_page_flip_active(intel_crtc
);
7939 __intel_ring_advance(ring
);
7943 intel_unpin_fb_obj(obj
);
7948 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7949 struct drm_crtc
*crtc
,
7950 struct drm_framebuffer
*fb
,
7951 struct drm_i915_gem_object
*obj
,
7954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7955 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7956 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7957 uint32_t pf
, pipesrc
;
7960 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7964 ret
= intel_ring_begin(ring
, 4);
7968 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7969 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7970 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7971 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7973 /* Contrary to the suggestions in the documentation,
7974 * "Enable Panel Fitter" does not seem to be required when page
7975 * flipping with a non-native mode, and worse causes a normal
7977 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7980 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7981 intel_ring_emit(ring
, pf
| pipesrc
);
7983 intel_mark_page_flip_active(intel_crtc
);
7984 __intel_ring_advance(ring
);
7988 intel_unpin_fb_obj(obj
);
7993 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7994 struct drm_crtc
*crtc
,
7995 struct drm_framebuffer
*fb
,
7996 struct drm_i915_gem_object
*obj
,
7999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8000 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8001 struct intel_ring_buffer
*ring
;
8002 uint32_t plane_bit
= 0;
8006 if (IS_VALLEYVIEW(dev
) || ring
== NULL
|| ring
->id
!= RCS
)
8007 ring
= &dev_priv
->ring
[BCS
];
8009 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8013 switch(intel_crtc
->plane
) {
8015 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
8018 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
8021 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
8024 WARN_ONCE(1, "unknown plane in flip command\n");
8030 if (ring
->id
== RCS
)
8033 ret
= intel_ring_begin(ring
, len
);
8037 /* Unmask the flip-done completion message. Note that the bspec says that
8038 * we should do this for both the BCS and RCS, and that we must not unmask
8039 * more than one flip event at any time (or ensure that one flip message
8040 * can be sent by waiting for flip-done prior to queueing new flips).
8041 * Experimentation says that BCS works despite DERRMR masking all
8042 * flip-done completion events and that unmasking all planes at once
8043 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8044 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8046 if (ring
->id
== RCS
) {
8047 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
8048 intel_ring_emit(ring
, DERRMR
);
8049 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
8050 DERRMR_PIPEB_PRI_FLIP_DONE
|
8051 DERRMR_PIPEC_PRI_FLIP_DONE
));
8052 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1));
8053 intel_ring_emit(ring
, DERRMR
);
8054 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
8057 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
8058 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
8059 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8060 intel_ring_emit(ring
, (MI_NOOP
));
8062 intel_mark_page_flip_active(intel_crtc
);
8063 __intel_ring_advance(ring
);
8067 intel_unpin_fb_obj(obj
);
8072 static int intel_default_queue_flip(struct drm_device
*dev
,
8073 struct drm_crtc
*crtc
,
8074 struct drm_framebuffer
*fb
,
8075 struct drm_i915_gem_object
*obj
,
8081 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
8082 struct drm_framebuffer
*fb
,
8083 struct drm_pending_vblank_event
*event
,
8084 uint32_t page_flip_flags
)
8086 struct drm_device
*dev
= crtc
->dev
;
8087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8088 struct drm_framebuffer
*old_fb
= crtc
->fb
;
8089 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
8090 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8091 struct intel_unpin_work
*work
;
8092 unsigned long flags
;
8095 /* Can't change pixel format via MI display flips. */
8096 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
8100 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8101 * Note that pitch changes could also affect these register.
8103 if (INTEL_INFO(dev
)->gen
> 3 &&
8104 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
8105 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
8108 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
8112 work
->event
= event
;
8114 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
8115 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
8117 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
8121 /* We borrow the event spin lock for protecting unpin_work */
8122 spin_lock_irqsave(&dev
->event_lock
, flags
);
8123 if (intel_crtc
->unpin_work
) {
8124 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8126 drm_vblank_put(dev
, intel_crtc
->pipe
);
8128 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8131 intel_crtc
->unpin_work
= work
;
8132 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8134 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
8135 flush_workqueue(dev_priv
->wq
);
8137 ret
= i915_mutex_lock_interruptible(dev
);
8141 /* Reference the objects for the scheduled work. */
8142 drm_gem_object_reference(&work
->old_fb_obj
->base
);
8143 drm_gem_object_reference(&obj
->base
);
8147 work
->pending_flip_obj
= obj
;
8149 work
->enable_stall_check
= true;
8151 atomic_inc(&intel_crtc
->unpin_work_count
);
8152 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8154 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8156 goto cleanup_pending
;
8158 intel_disable_fbc(dev
);
8159 intel_mark_fb_busy(obj
, NULL
);
8160 mutex_unlock(&dev
->struct_mutex
);
8162 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8167 atomic_dec(&intel_crtc
->unpin_work_count
);
8169 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8170 drm_gem_object_unreference(&obj
->base
);
8171 mutex_unlock(&dev
->struct_mutex
);
8174 spin_lock_irqsave(&dev
->event_lock
, flags
);
8175 intel_crtc
->unpin_work
= NULL
;
8176 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8178 drm_vblank_put(dev
, intel_crtc
->pipe
);
8185 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8186 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8187 .load_lut
= intel_crtc_load_lut
,
8190 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
8191 struct drm_crtc
*crtc
)
8193 struct drm_device
*dev
;
8194 struct drm_crtc
*tmp
;
8197 WARN(!crtc
, "checking null crtc?\n");
8201 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
8207 if (encoder
->possible_crtcs
& crtc_mask
)
8213 * intel_modeset_update_staged_output_state
8215 * Updates the staged output configuration state, e.g. after we've read out the
8218 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8220 struct intel_encoder
*encoder
;
8221 struct intel_connector
*connector
;
8223 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8225 connector
->new_encoder
=
8226 to_intel_encoder(connector
->base
.encoder
);
8229 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8232 to_intel_crtc(encoder
->base
.crtc
);
8237 * intel_modeset_commit_output_state
8239 * This function copies the stage display pipe configuration to the real one.
8241 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8243 struct intel_encoder
*encoder
;
8244 struct intel_connector
*connector
;
8246 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8248 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8251 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8253 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8258 connected_sink_compute_bpp(struct intel_connector
* connector
,
8259 struct intel_crtc_config
*pipe_config
)
8261 int bpp
= pipe_config
->pipe_bpp
;
8263 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8264 connector
->base
.base
.id
,
8265 drm_get_connector_name(&connector
->base
));
8267 /* Don't use an invalid EDID bpc value */
8268 if (connector
->base
.display_info
.bpc
&&
8269 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8270 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8271 bpp
, connector
->base
.display_info
.bpc
*3);
8272 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8275 /* Clamp bpp to 8 on screens without EDID 1.4 */
8276 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8277 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8279 pipe_config
->pipe_bpp
= 24;
8284 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8285 struct drm_framebuffer
*fb
,
8286 struct intel_crtc_config
*pipe_config
)
8288 struct drm_device
*dev
= crtc
->base
.dev
;
8289 struct intel_connector
*connector
;
8292 switch (fb
->pixel_format
) {
8294 bpp
= 8*3; /* since we go through a colormap */
8296 case DRM_FORMAT_XRGB1555
:
8297 case DRM_FORMAT_ARGB1555
:
8298 /* checked in intel_framebuffer_init already */
8299 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8301 case DRM_FORMAT_RGB565
:
8302 bpp
= 6*3; /* min is 18bpp */
8304 case DRM_FORMAT_XBGR8888
:
8305 case DRM_FORMAT_ABGR8888
:
8306 /* checked in intel_framebuffer_init already */
8307 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8309 case DRM_FORMAT_XRGB8888
:
8310 case DRM_FORMAT_ARGB8888
:
8313 case DRM_FORMAT_XRGB2101010
:
8314 case DRM_FORMAT_ARGB2101010
:
8315 case DRM_FORMAT_XBGR2101010
:
8316 case DRM_FORMAT_ABGR2101010
:
8317 /* checked in intel_framebuffer_init already */
8318 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8322 /* TODO: gen4+ supports 16 bpc floating point, too. */
8324 DRM_DEBUG_KMS("unsupported depth\n");
8328 pipe_config
->pipe_bpp
= bpp
;
8330 /* Clamp display bpp to EDID value */
8331 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8333 if (!connector
->new_encoder
||
8334 connector
->new_encoder
->new_crtc
!= crtc
)
8337 connected_sink_compute_bpp(connector
, pipe_config
);
8343 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
8345 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8346 "type: 0x%x flags: 0x%x\n",
8348 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
8349 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
8350 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
8351 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
8354 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8355 struct intel_crtc_config
*pipe_config
,
8356 const char *context
)
8358 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8359 context
, pipe_name(crtc
->pipe
));
8361 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8362 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8363 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8364 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8365 pipe_config
->has_pch_encoder
,
8366 pipe_config
->fdi_lanes
,
8367 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8368 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8369 pipe_config
->fdi_m_n
.tu
);
8370 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8371 pipe_config
->has_dp_encoder
,
8372 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
8373 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
8374 pipe_config
->dp_m_n
.tu
);
8375 DRM_DEBUG_KMS("requested mode:\n");
8376 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8377 DRM_DEBUG_KMS("adjusted mode:\n");
8378 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8379 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
8380 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
8381 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8382 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
8383 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8384 pipe_config
->gmch_pfit
.control
,
8385 pipe_config
->gmch_pfit
.pgm_ratios
,
8386 pipe_config
->gmch_pfit
.lvds_border_bits
);
8387 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8388 pipe_config
->pch_pfit
.pos
,
8389 pipe_config
->pch_pfit
.size
,
8390 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
8391 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8392 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
8395 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8397 int num_encoders
= 0;
8398 bool uncloneable_encoders
= false;
8399 struct intel_encoder
*encoder
;
8401 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8403 if (&encoder
->new_crtc
->base
!= crtc
)
8407 if (!encoder
->cloneable
)
8408 uncloneable_encoders
= true;
8411 return !(num_encoders
> 1 && uncloneable_encoders
);
8414 static struct intel_crtc_config
*
8415 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8416 struct drm_framebuffer
*fb
,
8417 struct drm_display_mode
*mode
)
8419 struct drm_device
*dev
= crtc
->dev
;
8420 struct intel_encoder
*encoder
;
8421 struct intel_crtc_config
*pipe_config
;
8422 int plane_bpp
, ret
= -EINVAL
;
8425 if (!check_encoder_cloning(crtc
)) {
8426 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8427 return ERR_PTR(-EINVAL
);
8430 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8432 return ERR_PTR(-ENOMEM
);
8434 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8435 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8437 pipe_config
->cpu_transcoder
=
8438 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8439 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8442 * Sanitize sync polarity flags based on requested ones. If neither
8443 * positive or negative polarity is requested, treat this as meaning
8444 * negative polarity.
8446 if (!(pipe_config
->adjusted_mode
.flags
&
8447 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
8448 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
8450 if (!(pipe_config
->adjusted_mode
.flags
&
8451 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
8452 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
8454 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8455 * plane pixel format and any sink constraints into account. Returns the
8456 * source plane bpp so that dithering can be selected on mismatches
8457 * after encoders and crtc also have had their say. */
8458 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
8464 /* Ensure the port clock defaults are reset when retrying. */
8465 pipe_config
->port_clock
= 0;
8466 pipe_config
->pixel_multiplier
= 1;
8468 /* Fill in default crtc timings, allow encoders to overwrite them. */
8469 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
8471 /* set_crtcinfo() may have adjusted hdisplay/vdisplay */
8472 pipe_config
->pipe_src_w
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
8473 pipe_config
->pipe_src_h
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
8475 /* Pass our mode to the connectors and the CRTC to give them a chance to
8476 * adjust it according to limitations or connector properties, and also
8477 * a chance to reject the mode entirely.
8479 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8482 if (&encoder
->new_crtc
->base
!= crtc
)
8485 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
8486 DRM_DEBUG_KMS("Encoder config failure\n");
8491 /* Set default port clock if not overwritten by the encoder. Needs to be
8492 * done afterwards in case the encoder adjusts the mode. */
8493 if (!pipe_config
->port_clock
)
8494 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
8495 * pipe_config
->pixel_multiplier
;
8497 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
8499 DRM_DEBUG_KMS("CRTC fixup failed\n");
8504 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
8509 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8514 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
8515 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8516 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
8521 return ERR_PTR(ret
);
8524 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8525 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8527 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
8528 unsigned *prepare_pipes
, unsigned *disable_pipes
)
8530 struct intel_crtc
*intel_crtc
;
8531 struct drm_device
*dev
= crtc
->dev
;
8532 struct intel_encoder
*encoder
;
8533 struct intel_connector
*connector
;
8534 struct drm_crtc
*tmp_crtc
;
8536 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
8538 /* Check which crtcs have changed outputs connected to them, these need
8539 * to be part of the prepare_pipes mask. We don't (yet) support global
8540 * modeset across multiple crtcs, so modeset_pipes will only have one
8541 * bit set at most. */
8542 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8544 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
8547 if (connector
->base
.encoder
) {
8548 tmp_crtc
= connector
->base
.encoder
->crtc
;
8550 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8553 if (connector
->new_encoder
)
8555 1 << connector
->new_encoder
->new_crtc
->pipe
;
8558 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8560 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
8563 if (encoder
->base
.crtc
) {
8564 tmp_crtc
= encoder
->base
.crtc
;
8566 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8569 if (encoder
->new_crtc
)
8570 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
8573 /* Check for any pipes that will be fully disabled ... */
8574 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8578 /* Don't try to disable disabled crtcs. */
8579 if (!intel_crtc
->base
.enabled
)
8582 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8584 if (encoder
->new_crtc
== intel_crtc
)
8589 *disable_pipes
|= 1 << intel_crtc
->pipe
;
8593 /* set_mode is also used to update properties on life display pipes. */
8594 intel_crtc
= to_intel_crtc(crtc
);
8596 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
8599 * For simplicity do a full modeset on any pipe where the output routing
8600 * changed. We could be more clever, but that would require us to be
8601 * more careful with calling the relevant encoder->mode_set functions.
8604 *modeset_pipes
= *prepare_pipes
;
8606 /* ... and mask these out. */
8607 *modeset_pipes
&= ~(*disable_pipes
);
8608 *prepare_pipes
&= ~(*disable_pipes
);
8611 * HACK: We don't (yet) fully support global modesets. intel_set_config
8612 * obies this rule, but the modeset restore mode of
8613 * intel_modeset_setup_hw_state does not.
8615 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
8616 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
8618 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8619 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
8622 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
8624 struct drm_encoder
*encoder
;
8625 struct drm_device
*dev
= crtc
->dev
;
8627 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
8628 if (encoder
->crtc
== crtc
)
8635 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8637 struct intel_encoder
*intel_encoder
;
8638 struct intel_crtc
*intel_crtc
;
8639 struct drm_connector
*connector
;
8641 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8643 if (!intel_encoder
->base
.crtc
)
8646 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8648 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8649 intel_encoder
->connectors_active
= false;
8652 intel_modeset_commit_output_state(dev
);
8654 /* Update computed state. */
8655 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8657 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8660 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8661 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8664 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8666 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8667 struct drm_property
*dpms_property
=
8668 dev
->mode_config
.dpms_property
;
8670 connector
->dpms
= DRM_MODE_DPMS_ON
;
8671 drm_object_property_set_value(&connector
->base
,
8675 intel_encoder
= to_intel_encoder(connector
->encoder
);
8676 intel_encoder
->connectors_active
= true;
8682 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
8686 if (clock1
== clock2
)
8689 if (!clock1
|| !clock2
)
8692 diff
= abs(clock1
- clock2
);
8694 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
8700 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8701 list_for_each_entry((intel_crtc), \
8702 &(dev)->mode_config.crtc_list, \
8704 if (mask & (1 <<(intel_crtc)->pipe))
8707 intel_pipe_config_compare(struct drm_device
*dev
,
8708 struct intel_crtc_config
*current_config
,
8709 struct intel_crtc_config
*pipe_config
)
8711 #define PIPE_CONF_CHECK_X(name) \
8712 if (current_config->name != pipe_config->name) { \
8713 DRM_ERROR("mismatch in " #name " " \
8714 "(expected 0x%08x, found 0x%08x)\n", \
8715 current_config->name, \
8716 pipe_config->name); \
8720 #define PIPE_CONF_CHECK_I(name) \
8721 if (current_config->name != pipe_config->name) { \
8722 DRM_ERROR("mismatch in " #name " " \
8723 "(expected %i, found %i)\n", \
8724 current_config->name, \
8725 pipe_config->name); \
8729 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8730 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8731 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8732 "(expected %i, found %i)\n", \
8733 current_config->name & (mask), \
8734 pipe_config->name & (mask)); \
8738 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8739 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8740 DRM_ERROR("mismatch in " #name " " \
8741 "(expected %i, found %i)\n", \
8742 current_config->name, \
8743 pipe_config->name); \
8747 #define PIPE_CONF_QUIRK(quirk) \
8748 ((current_config->quirks | pipe_config->quirks) & (quirk))
8750 PIPE_CONF_CHECK_I(cpu_transcoder
);
8752 PIPE_CONF_CHECK_I(has_pch_encoder
);
8753 PIPE_CONF_CHECK_I(fdi_lanes
);
8754 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8755 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8756 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8757 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8758 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8760 PIPE_CONF_CHECK_I(has_dp_encoder
);
8761 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
8762 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
8763 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
8764 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
8765 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
8767 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8768 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8769 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8770 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8771 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8772 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8774 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8775 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8776 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8777 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8778 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8779 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8781 PIPE_CONF_CHECK_I(pixel_multiplier
);
8783 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8784 DRM_MODE_FLAG_INTERLACE
);
8786 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8787 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8788 DRM_MODE_FLAG_PHSYNC
);
8789 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8790 DRM_MODE_FLAG_NHSYNC
);
8791 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8792 DRM_MODE_FLAG_PVSYNC
);
8793 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8794 DRM_MODE_FLAG_NVSYNC
);
8797 PIPE_CONF_CHECK_I(pipe_src_w
);
8798 PIPE_CONF_CHECK_I(pipe_src_h
);
8800 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8801 /* pfit ratios are autocomputed by the hw on gen4+ */
8802 if (INTEL_INFO(dev
)->gen
< 4)
8803 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8804 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8805 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
8806 if (current_config
->pch_pfit
.enabled
) {
8807 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8808 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8811 PIPE_CONF_CHECK_I(ips_enabled
);
8813 PIPE_CONF_CHECK_I(double_wide
);
8815 PIPE_CONF_CHECK_I(shared_dpll
);
8816 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8817 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8818 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8819 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8821 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
8822 PIPE_CONF_CHECK_I(pipe_bpp
);
8824 if (!IS_HASWELL(dev
)) {
8825 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
8826 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
8829 #undef PIPE_CONF_CHECK_X
8830 #undef PIPE_CONF_CHECK_I
8831 #undef PIPE_CONF_CHECK_FLAGS
8832 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8833 #undef PIPE_CONF_QUIRK
8839 check_connector_state(struct drm_device
*dev
)
8841 struct intel_connector
*connector
;
8843 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8845 /* This also checks the encoder/connector hw state with the
8846 * ->get_hw_state callbacks. */
8847 intel_connector_check_state(connector
);
8849 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8850 "connector's staged encoder doesn't match current encoder\n");
8855 check_encoder_state(struct drm_device
*dev
)
8857 struct intel_encoder
*encoder
;
8858 struct intel_connector
*connector
;
8860 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8862 bool enabled
= false;
8863 bool active
= false;
8864 enum pipe pipe
, tracked_pipe
;
8866 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8867 encoder
->base
.base
.id
,
8868 drm_get_encoder_name(&encoder
->base
));
8870 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8871 "encoder's stage crtc doesn't match current crtc\n");
8872 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8873 "encoder's active_connectors set, but no crtc\n");
8875 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8877 if (connector
->base
.encoder
!= &encoder
->base
)
8880 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8883 WARN(!!encoder
->base
.crtc
!= enabled
,
8884 "encoder's enabled state mismatch "
8885 "(expected %i, found %i)\n",
8886 !!encoder
->base
.crtc
, enabled
);
8887 WARN(active
&& !encoder
->base
.crtc
,
8888 "active encoder with no crtc\n");
8890 WARN(encoder
->connectors_active
!= active
,
8891 "encoder's computed active state doesn't match tracked active state "
8892 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8894 active
= encoder
->get_hw_state(encoder
, &pipe
);
8895 WARN(active
!= encoder
->connectors_active
,
8896 "encoder's hw state doesn't match sw tracking "
8897 "(expected %i, found %i)\n",
8898 encoder
->connectors_active
, active
);
8900 if (!encoder
->base
.crtc
)
8903 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
8904 WARN(active
&& pipe
!= tracked_pipe
,
8905 "active encoder's pipe doesn't match"
8906 "(expected %i, found %i)\n",
8907 tracked_pipe
, pipe
);
8913 check_crtc_state(struct drm_device
*dev
)
8915 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8916 struct intel_crtc
*crtc
;
8917 struct intel_encoder
*encoder
;
8918 struct intel_crtc_config pipe_config
;
8920 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8922 bool enabled
= false;
8923 bool active
= false;
8925 memset(&pipe_config
, 0, sizeof(pipe_config
));
8927 DRM_DEBUG_KMS("[CRTC:%d]\n",
8928 crtc
->base
.base
.id
);
8930 WARN(crtc
->active
&& !crtc
->base
.enabled
,
8931 "active crtc, but not enabled in sw tracking\n");
8933 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8935 if (encoder
->base
.crtc
!= &crtc
->base
)
8938 if (encoder
->connectors_active
)
8942 WARN(active
!= crtc
->active
,
8943 "crtc's computed active state doesn't match tracked active state "
8944 "(expected %i, found %i)\n", active
, crtc
->active
);
8945 WARN(enabled
!= crtc
->base
.enabled
,
8946 "crtc's computed enabled state doesn't match tracked enabled state "
8947 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
8949 active
= dev_priv
->display
.get_pipe_config(crtc
,
8952 /* hw state is inconsistent with the pipe A quirk */
8953 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
8954 active
= crtc
->active
;
8956 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8959 if (encoder
->base
.crtc
!= &crtc
->base
)
8961 if (encoder
->get_config
&&
8962 encoder
->get_hw_state(encoder
, &pipe
))
8963 encoder
->get_config(encoder
, &pipe_config
);
8966 WARN(crtc
->active
!= active
,
8967 "crtc active state doesn't match with hw state "
8968 "(expected %i, found %i)\n", crtc
->active
, active
);
8971 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
8972 WARN(1, "pipe state doesn't match!\n");
8973 intel_dump_pipe_config(crtc
, &pipe_config
,
8975 intel_dump_pipe_config(crtc
, &crtc
->config
,
8982 check_shared_dpll_state(struct drm_device
*dev
)
8984 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8985 struct intel_crtc
*crtc
;
8986 struct intel_dpll_hw_state dpll_hw_state
;
8989 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8990 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
8991 int enabled_crtcs
= 0, active_crtcs
= 0;
8994 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
8996 DRM_DEBUG_KMS("%s\n", pll
->name
);
8998 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
9000 WARN(pll
->active
> pll
->refcount
,
9001 "more active pll users than references: %i vs %i\n",
9002 pll
->active
, pll
->refcount
);
9003 WARN(pll
->active
&& !pll
->on
,
9004 "pll in active use but not on in sw tracking\n");
9005 WARN(pll
->on
&& !pll
->active
,
9006 "pll in on but not on in use in sw tracking\n");
9007 WARN(pll
->on
!= active
,
9008 "pll on state mismatch (expected %i, found %i)\n",
9011 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9013 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9015 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9018 WARN(pll
->active
!= active_crtcs
,
9019 "pll active crtcs mismatch (expected %i, found %i)\n",
9020 pll
->active
, active_crtcs
);
9021 WARN(pll
->refcount
!= enabled_crtcs
,
9022 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9023 pll
->refcount
, enabled_crtcs
);
9025 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
9026 sizeof(dpll_hw_state
)),
9027 "pll hw state mismatch\n");
9032 intel_modeset_check_state(struct drm_device
*dev
)
9034 check_connector_state(dev
);
9035 check_encoder_state(dev
);
9036 check_crtc_state(dev
);
9037 check_shared_dpll_state(dev
);
9040 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
9044 * FDI already provided one idea for the dotclock.
9045 * Yell if the encoder disagrees.
9047 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
9048 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9049 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
9052 static int __intel_set_mode(struct drm_crtc
*crtc
,
9053 struct drm_display_mode
*mode
,
9054 int x
, int y
, struct drm_framebuffer
*fb
)
9056 struct drm_device
*dev
= crtc
->dev
;
9057 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9058 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
9059 struct intel_crtc_config
*pipe_config
= NULL
;
9060 struct intel_crtc
*intel_crtc
;
9061 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
9064 saved_mode
= kcalloc(2, sizeof(*saved_mode
), GFP_KERNEL
);
9067 saved_hwmode
= saved_mode
+ 1;
9069 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
9070 &prepare_pipes
, &disable_pipes
);
9072 *saved_hwmode
= crtc
->hwmode
;
9073 *saved_mode
= crtc
->mode
;
9075 /* Hack: Because we don't (yet) support global modeset on multiple
9076 * crtcs, we don't keep track of the new mode for more than one crtc.
9077 * Hence simply check whether any bit is set in modeset_pipes in all the
9078 * pieces of code that are not yet converted to deal with mutliple crtcs
9079 * changing their mode at the same time. */
9080 if (modeset_pipes
) {
9081 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
9082 if (IS_ERR(pipe_config
)) {
9083 ret
= PTR_ERR(pipe_config
);
9088 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
9092 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
9093 intel_crtc_disable(&intel_crtc
->base
);
9095 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
9096 if (intel_crtc
->base
.enabled
)
9097 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
9100 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9101 * to set it here already despite that we pass it down the callchain.
9103 if (modeset_pipes
) {
9105 /* mode_set/enable/disable functions rely on a correct pipe
9107 to_intel_crtc(crtc
)->config
= *pipe_config
;
9110 /* Only after disabling all output pipelines that will be changed can we
9111 * update the the output configuration. */
9112 intel_modeset_update_state(dev
, prepare_pipes
);
9114 if (dev_priv
->display
.modeset_global_resources
)
9115 dev_priv
->display
.modeset_global_resources(dev
);
9117 /* Set up the DPLL and any encoders state that needs to adjust or depend
9120 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
9121 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
9127 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9128 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
9129 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
9131 if (modeset_pipes
) {
9132 /* Store real post-adjustment hardware mode. */
9133 crtc
->hwmode
= pipe_config
->adjusted_mode
;
9135 /* Calculate and store various constants which
9136 * are later needed by vblank and swap-completion
9137 * timestamping. They are derived from true hwmode.
9139 drm_calc_timestamping_constants(crtc
);
9142 /* FIXME: add subpixel order */
9144 if (ret
&& crtc
->enabled
) {
9145 crtc
->hwmode
= *saved_hwmode
;
9146 crtc
->mode
= *saved_mode
;
9155 static int intel_set_mode(struct drm_crtc
*crtc
,
9156 struct drm_display_mode
*mode
,
9157 int x
, int y
, struct drm_framebuffer
*fb
)
9161 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
9164 intel_modeset_check_state(crtc
->dev
);
9169 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
9171 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
9174 #undef for_each_intel_crtc_masked
9176 static void intel_set_config_free(struct intel_set_config
*config
)
9181 kfree(config
->save_connector_encoders
);
9182 kfree(config
->save_encoder_crtcs
);
9186 static int intel_set_config_save_state(struct drm_device
*dev
,
9187 struct intel_set_config
*config
)
9189 struct drm_encoder
*encoder
;
9190 struct drm_connector
*connector
;
9193 config
->save_encoder_crtcs
=
9194 kcalloc(dev
->mode_config
.num_encoder
,
9195 sizeof(struct drm_crtc
*), GFP_KERNEL
);
9196 if (!config
->save_encoder_crtcs
)
9199 config
->save_connector_encoders
=
9200 kcalloc(dev
->mode_config
.num_connector
,
9201 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9202 if (!config
->save_connector_encoders
)
9205 /* Copy data. Note that driver private data is not affected.
9206 * Should anything bad happen only the expected state is
9207 * restored, not the drivers personal bookkeeping.
9210 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9211 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9215 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9216 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9222 static void intel_set_config_restore_state(struct drm_device
*dev
,
9223 struct intel_set_config
*config
)
9225 struct intel_encoder
*encoder
;
9226 struct intel_connector
*connector
;
9230 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9232 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9236 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9237 connector
->new_encoder
=
9238 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9243 is_crtc_connector_off(struct drm_mode_set
*set
)
9247 if (set
->num_connectors
== 0)
9250 if (WARN_ON(set
->connectors
== NULL
))
9253 for (i
= 0; i
< set
->num_connectors
; i
++)
9254 if (set
->connectors
[i
]->encoder
&&
9255 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9256 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9263 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9264 struct intel_set_config
*config
)
9267 /* We should be able to check here if the fb has the same properties
9268 * and then just flip_or_move it */
9269 if (is_crtc_connector_off(set
)) {
9270 config
->mode_changed
= true;
9271 } else if (set
->crtc
->fb
!= set
->fb
) {
9272 /* If we have no fb then treat it as a full mode set */
9273 if (set
->crtc
->fb
== NULL
) {
9274 struct intel_crtc
*intel_crtc
=
9275 to_intel_crtc(set
->crtc
);
9277 if (intel_crtc
->active
&& i915_fastboot
) {
9278 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9279 config
->fb_changed
= true;
9281 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9282 config
->mode_changed
= true;
9284 } else if (set
->fb
== NULL
) {
9285 config
->mode_changed
= true;
9286 } else if (set
->fb
->pixel_format
!=
9287 set
->crtc
->fb
->pixel_format
) {
9288 config
->mode_changed
= true;
9290 config
->fb_changed
= true;
9294 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9295 config
->fb_changed
= true;
9297 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9298 DRM_DEBUG_KMS("modes are different, full mode set\n");
9299 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9300 drm_mode_debug_printmodeline(set
->mode
);
9301 config
->mode_changed
= true;
9304 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9305 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9309 intel_modeset_stage_output_state(struct drm_device
*dev
,
9310 struct drm_mode_set
*set
,
9311 struct intel_set_config
*config
)
9313 struct drm_crtc
*new_crtc
;
9314 struct intel_connector
*connector
;
9315 struct intel_encoder
*encoder
;
9318 /* The upper layers ensure that we either disable a crtc or have a list
9319 * of connectors. For paranoia, double-check this. */
9320 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9321 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9323 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9325 /* Otherwise traverse passed in connector list and get encoders
9327 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9328 if (set
->connectors
[ro
] == &connector
->base
) {
9329 connector
->new_encoder
= connector
->encoder
;
9334 /* If we disable the crtc, disable all its connectors. Also, if
9335 * the connector is on the changing crtc but not on the new
9336 * connector list, disable it. */
9337 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9338 connector
->base
.encoder
&&
9339 connector
->base
.encoder
->crtc
== set
->crtc
) {
9340 connector
->new_encoder
= NULL
;
9342 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9343 connector
->base
.base
.id
,
9344 drm_get_connector_name(&connector
->base
));
9348 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9349 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9350 config
->mode_changed
= true;
9353 /* connector->new_encoder is now updated for all connectors. */
9355 /* Update crtc of enabled connectors. */
9356 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9358 if (!connector
->new_encoder
)
9361 new_crtc
= connector
->new_encoder
->base
.crtc
;
9363 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9364 if (set
->connectors
[ro
] == &connector
->base
)
9365 new_crtc
= set
->crtc
;
9368 /* Make sure the new CRTC will work with the encoder */
9369 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
9373 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9376 connector
->base
.base
.id
,
9377 drm_get_connector_name(&connector
->base
),
9381 /* Check for any encoders that needs to be disabled. */
9382 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9384 list_for_each_entry(connector
,
9385 &dev
->mode_config
.connector_list
,
9387 if (connector
->new_encoder
== encoder
) {
9388 WARN_ON(!connector
->new_encoder
->new_crtc
);
9393 encoder
->new_crtc
= NULL
;
9395 /* Only now check for crtc changes so we don't miss encoders
9396 * that will be disabled. */
9397 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9398 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9399 config
->mode_changed
= true;
9402 /* Now we've also updated encoder->new_crtc for all encoders. */
9407 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9409 struct drm_device
*dev
;
9410 struct drm_mode_set save_set
;
9411 struct intel_set_config
*config
;
9416 BUG_ON(!set
->crtc
->helper_private
);
9418 /* Enforce sane interface api - has been abused by the fb helper. */
9419 BUG_ON(!set
->mode
&& set
->fb
);
9420 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9423 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9424 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9425 (int)set
->num_connectors
, set
->x
, set
->y
);
9427 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
9430 dev
= set
->crtc
->dev
;
9433 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
9437 ret
= intel_set_config_save_state(dev
, config
);
9441 save_set
.crtc
= set
->crtc
;
9442 save_set
.mode
= &set
->crtc
->mode
;
9443 save_set
.x
= set
->crtc
->x
;
9444 save_set
.y
= set
->crtc
->y
;
9445 save_set
.fb
= set
->crtc
->fb
;
9447 /* Compute whether we need a full modeset, only an fb base update or no
9448 * change at all. In the future we might also check whether only the
9449 * mode changed, e.g. for LVDS where we only change the panel fitter in
9451 intel_set_config_compute_mode_changes(set
, config
);
9453 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
9457 if (config
->mode_changed
) {
9458 ret
= intel_set_mode(set
->crtc
, set
->mode
,
9459 set
->x
, set
->y
, set
->fb
);
9460 } else if (config
->fb_changed
) {
9461 intel_crtc_wait_for_pending_flips(set
->crtc
);
9463 ret
= intel_pipe_set_base(set
->crtc
,
9464 set
->x
, set
->y
, set
->fb
);
9468 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9469 set
->crtc
->base
.id
, ret
);
9471 intel_set_config_restore_state(dev
, config
);
9473 /* Try to restore the config */
9474 if (config
->mode_changed
&&
9475 intel_set_mode(save_set
.crtc
, save_set
.mode
,
9476 save_set
.x
, save_set
.y
, save_set
.fb
))
9477 DRM_ERROR("failed to restore config after modeset failure\n");
9481 intel_set_config_free(config
);
9485 static const struct drm_crtc_funcs intel_crtc_funcs
= {
9486 .cursor_set
= intel_crtc_cursor_set
,
9487 .cursor_move
= intel_crtc_cursor_move
,
9488 .gamma_set
= intel_crtc_gamma_set
,
9489 .set_config
= intel_crtc_set_config
,
9490 .destroy
= intel_crtc_destroy
,
9491 .page_flip
= intel_crtc_page_flip
,
9494 static void intel_cpu_pll_init(struct drm_device
*dev
)
9497 intel_ddi_pll_init(dev
);
9500 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
9501 struct intel_shared_dpll
*pll
,
9502 struct intel_dpll_hw_state
*hw_state
)
9506 val
= I915_READ(PCH_DPLL(pll
->id
));
9507 hw_state
->dpll
= val
;
9508 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
9509 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
9511 return val
& DPLL_VCO_ENABLE
;
9514 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
9515 struct intel_shared_dpll
*pll
)
9517 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
9518 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
9521 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
9522 struct intel_shared_dpll
*pll
)
9524 /* PCH refclock must be enabled first */
9525 assert_pch_refclk_enabled(dev_priv
);
9527 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9529 /* Wait for the clocks to stabilize. */
9530 POSTING_READ(PCH_DPLL(pll
->id
));
9533 /* The pixel multiplier can only be updated once the
9534 * DPLL is enabled and the clocks are stable.
9536 * So write it again.
9538 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9539 POSTING_READ(PCH_DPLL(pll
->id
));
9543 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
9544 struct intel_shared_dpll
*pll
)
9546 struct drm_device
*dev
= dev_priv
->dev
;
9547 struct intel_crtc
*crtc
;
9549 /* Make sure no transcoder isn't still depending on us. */
9550 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
9551 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
9552 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
9555 I915_WRITE(PCH_DPLL(pll
->id
), 0);
9556 POSTING_READ(PCH_DPLL(pll
->id
));
9560 static char *ibx_pch_dpll_names
[] = {
9565 static void ibx_pch_dpll_init(struct drm_device
*dev
)
9567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9570 dev_priv
->num_shared_dpll
= 2;
9572 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9573 dev_priv
->shared_dplls
[i
].id
= i
;
9574 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
9575 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
9576 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
9577 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
9578 dev_priv
->shared_dplls
[i
].get_hw_state
=
9579 ibx_pch_dpll_get_hw_state
;
9583 static void intel_shared_dpll_init(struct drm_device
*dev
)
9585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9587 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
9588 ibx_pch_dpll_init(dev
);
9590 dev_priv
->num_shared_dpll
= 0;
9592 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
9593 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9594 dev_priv
->num_shared_dpll
);
9597 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
9599 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9600 struct intel_crtc
*intel_crtc
;
9603 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
9604 if (intel_crtc
== NULL
)
9607 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
9609 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
9610 for (i
= 0; i
< 256; i
++) {
9611 intel_crtc
->lut_r
[i
] = i
;
9612 intel_crtc
->lut_g
[i
] = i
;
9613 intel_crtc
->lut_b
[i
] = i
;
9616 /* Swap pipes & planes for FBC on pre-965 */
9617 intel_crtc
->pipe
= pipe
;
9618 intel_crtc
->plane
= pipe
;
9619 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
9620 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9621 intel_crtc
->plane
= !pipe
;
9624 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
9625 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
9626 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
9627 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
9629 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
9632 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
9633 struct drm_file
*file
)
9635 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
9636 struct drm_mode_object
*drmmode_obj
;
9637 struct intel_crtc
*crtc
;
9639 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
9642 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
9643 DRM_MODE_OBJECT_CRTC
);
9646 DRM_ERROR("no such CRTC id\n");
9650 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
9651 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
9656 static int intel_encoder_clones(struct intel_encoder
*encoder
)
9658 struct drm_device
*dev
= encoder
->base
.dev
;
9659 struct intel_encoder
*source_encoder
;
9663 list_for_each_entry(source_encoder
,
9664 &dev
->mode_config
.encoder_list
, base
.head
) {
9666 if (encoder
== source_encoder
)
9667 index_mask
|= (1 << entry
);
9669 /* Intel hw has only one MUX where enocoders could be cloned. */
9670 if (encoder
->cloneable
&& source_encoder
->cloneable
)
9671 index_mask
|= (1 << entry
);
9679 static bool has_edp_a(struct drm_device
*dev
)
9681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9683 if (!IS_MOBILE(dev
))
9686 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
9690 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
9696 static void intel_setup_outputs(struct drm_device
*dev
)
9698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9699 struct intel_encoder
*encoder
;
9700 bool dpd_is_edp
= false;
9702 intel_lvds_init(dev
);
9705 intel_crt_init(dev
);
9710 /* Haswell uses DDI functions to detect digital outputs */
9711 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
9712 /* DDI A only supports eDP */
9714 intel_ddi_init(dev
, PORT_A
);
9716 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9718 found
= I915_READ(SFUSE_STRAP
);
9720 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
9721 intel_ddi_init(dev
, PORT_B
);
9722 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
9723 intel_ddi_init(dev
, PORT_C
);
9724 if (found
& SFUSE_STRAP_DDID_DETECTED
)
9725 intel_ddi_init(dev
, PORT_D
);
9726 } else if (HAS_PCH_SPLIT(dev
)) {
9728 dpd_is_edp
= intel_dpd_is_edp(dev
);
9731 intel_dp_init(dev
, DP_A
, PORT_A
);
9733 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9734 /* PCH SDVOB multiplex with HDMIB */
9735 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9737 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9738 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9739 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9742 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9743 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9745 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9746 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9748 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9749 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9751 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9752 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9753 } else if (IS_VALLEYVIEW(dev
)) {
9754 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9755 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
9756 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
9758 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9759 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
,
9763 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9764 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9766 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9767 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9770 intel_dsi_init(dev
);
9771 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9774 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9775 DRM_DEBUG_KMS("probing SDVOB\n");
9776 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9777 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9778 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9779 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9782 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9783 intel_dp_init(dev
, DP_B
, PORT_B
);
9786 /* Before G4X SDVOC doesn't have its own detect register */
9788 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9789 DRM_DEBUG_KMS("probing SDVOC\n");
9790 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9793 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9795 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9796 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9797 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9799 if (SUPPORTS_INTEGRATED_DP(dev
))
9800 intel_dp_init(dev
, DP_C
, PORT_C
);
9803 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9804 (I915_READ(DP_D
) & DP_DETECTED
))
9805 intel_dp_init(dev
, DP_D
, PORT_D
);
9806 } else if (IS_GEN2(dev
))
9807 intel_dvo_init(dev
);
9809 if (SUPPORTS_TV(dev
))
9812 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9813 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9814 encoder
->base
.possible_clones
=
9815 intel_encoder_clones(encoder
);
9818 intel_init_pch_refclk(dev
);
9820 drm_helper_move_panel_connectors_to_head(dev
);
9823 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
9825 drm_framebuffer_cleanup(&fb
->base
);
9826 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
9829 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9831 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9833 intel_framebuffer_fini(intel_fb
);
9837 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9838 struct drm_file
*file
,
9839 unsigned int *handle
)
9841 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9842 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9844 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9847 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9848 .destroy
= intel_user_framebuffer_destroy
,
9849 .create_handle
= intel_user_framebuffer_create_handle
,
9852 int intel_framebuffer_init(struct drm_device
*dev
,
9853 struct intel_framebuffer
*intel_fb
,
9854 struct drm_mode_fb_cmd2
*mode_cmd
,
9855 struct drm_i915_gem_object
*obj
)
9860 if (obj
->tiling_mode
== I915_TILING_Y
) {
9861 DRM_DEBUG("hardware does not support tiling Y\n");
9865 if (mode_cmd
->pitches
[0] & 63) {
9866 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9867 mode_cmd
->pitches
[0]);
9871 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
9872 pitch_limit
= 32*1024;
9873 } else if (INTEL_INFO(dev
)->gen
>= 4) {
9874 if (obj
->tiling_mode
)
9875 pitch_limit
= 16*1024;
9877 pitch_limit
= 32*1024;
9878 } else if (INTEL_INFO(dev
)->gen
>= 3) {
9879 if (obj
->tiling_mode
)
9880 pitch_limit
= 8*1024;
9882 pitch_limit
= 16*1024;
9884 /* XXX DSPC is limited to 4k tiled */
9885 pitch_limit
= 8*1024;
9887 if (mode_cmd
->pitches
[0] > pitch_limit
) {
9888 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9889 obj
->tiling_mode
? "tiled" : "linear",
9890 mode_cmd
->pitches
[0], pitch_limit
);
9894 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
9895 mode_cmd
->pitches
[0] != obj
->stride
) {
9896 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9897 mode_cmd
->pitches
[0], obj
->stride
);
9901 /* Reject formats not supported by any plane early. */
9902 switch (mode_cmd
->pixel_format
) {
9904 case DRM_FORMAT_RGB565
:
9905 case DRM_FORMAT_XRGB8888
:
9906 case DRM_FORMAT_ARGB8888
:
9908 case DRM_FORMAT_XRGB1555
:
9909 case DRM_FORMAT_ARGB1555
:
9910 if (INTEL_INFO(dev
)->gen
> 3) {
9911 DRM_DEBUG("unsupported pixel format: %s\n",
9912 drm_get_format_name(mode_cmd
->pixel_format
));
9916 case DRM_FORMAT_XBGR8888
:
9917 case DRM_FORMAT_ABGR8888
:
9918 case DRM_FORMAT_XRGB2101010
:
9919 case DRM_FORMAT_ARGB2101010
:
9920 case DRM_FORMAT_XBGR2101010
:
9921 case DRM_FORMAT_ABGR2101010
:
9922 if (INTEL_INFO(dev
)->gen
< 4) {
9923 DRM_DEBUG("unsupported pixel format: %s\n",
9924 drm_get_format_name(mode_cmd
->pixel_format
));
9928 case DRM_FORMAT_YUYV
:
9929 case DRM_FORMAT_UYVY
:
9930 case DRM_FORMAT_YVYU
:
9931 case DRM_FORMAT_VYUY
:
9932 if (INTEL_INFO(dev
)->gen
< 5) {
9933 DRM_DEBUG("unsupported pixel format: %s\n",
9934 drm_get_format_name(mode_cmd
->pixel_format
));
9939 DRM_DEBUG("unsupported pixel format: %s\n",
9940 drm_get_format_name(mode_cmd
->pixel_format
));
9944 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9945 if (mode_cmd
->offsets
[0] != 0)
9948 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
9949 intel_fb
->obj
= obj
;
9951 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
9953 DRM_ERROR("framebuffer init failed %d\n", ret
);
9960 static struct drm_framebuffer
*
9961 intel_user_framebuffer_create(struct drm_device
*dev
,
9962 struct drm_file
*filp
,
9963 struct drm_mode_fb_cmd2
*mode_cmd
)
9965 struct drm_i915_gem_object
*obj
;
9967 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
9968 mode_cmd
->handles
[0]));
9969 if (&obj
->base
== NULL
)
9970 return ERR_PTR(-ENOENT
);
9972 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
9975 static const struct drm_mode_config_funcs intel_mode_funcs
= {
9976 .fb_create
= intel_user_framebuffer_create
,
9977 .output_poll_changed
= intel_fb_output_poll_changed
,
9980 /* Set up chip specific display functions */
9981 static void intel_init_display(struct drm_device
*dev
)
9983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9985 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
9986 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
9987 else if (IS_VALLEYVIEW(dev
))
9988 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
9989 else if (IS_PINEVIEW(dev
))
9990 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
9992 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
9995 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
9996 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
9997 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
9998 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
9999 dev_priv
->display
.off
= haswell_crtc_off
;
10000 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10001 } else if (HAS_PCH_SPLIT(dev
)) {
10002 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
10003 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
10004 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
10005 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
10006 dev_priv
->display
.off
= ironlake_crtc_off
;
10007 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10008 } else if (IS_VALLEYVIEW(dev
)) {
10009 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10010 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10011 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
10012 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10013 dev_priv
->display
.off
= i9xx_crtc_off
;
10014 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10016 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10017 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10018 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
10019 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10020 dev_priv
->display
.off
= i9xx_crtc_off
;
10021 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10024 /* Returns the core display clock speed */
10025 if (IS_VALLEYVIEW(dev
))
10026 dev_priv
->display
.get_display_clock_speed
=
10027 valleyview_get_display_clock_speed
;
10028 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
10029 dev_priv
->display
.get_display_clock_speed
=
10030 i945_get_display_clock_speed
;
10031 else if (IS_I915G(dev
))
10032 dev_priv
->display
.get_display_clock_speed
=
10033 i915_get_display_clock_speed
;
10034 else if (IS_I945GM(dev
) || IS_845G(dev
))
10035 dev_priv
->display
.get_display_clock_speed
=
10036 i9xx_misc_get_display_clock_speed
;
10037 else if (IS_PINEVIEW(dev
))
10038 dev_priv
->display
.get_display_clock_speed
=
10039 pnv_get_display_clock_speed
;
10040 else if (IS_I915GM(dev
))
10041 dev_priv
->display
.get_display_clock_speed
=
10042 i915gm_get_display_clock_speed
;
10043 else if (IS_I865G(dev
))
10044 dev_priv
->display
.get_display_clock_speed
=
10045 i865_get_display_clock_speed
;
10046 else if (IS_I85X(dev
))
10047 dev_priv
->display
.get_display_clock_speed
=
10048 i855_get_display_clock_speed
;
10049 else /* 852, 830 */
10050 dev_priv
->display
.get_display_clock_speed
=
10051 i830_get_display_clock_speed
;
10053 if (HAS_PCH_SPLIT(dev
)) {
10054 if (IS_GEN5(dev
)) {
10055 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
10056 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10057 } else if (IS_GEN6(dev
)) {
10058 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
10059 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10060 } else if (IS_IVYBRIDGE(dev
)) {
10061 /* FIXME: detect B0+ stepping and use auto training */
10062 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
10063 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10064 dev_priv
->display
.modeset_global_resources
=
10065 ivb_modeset_global_resources
;
10066 } else if (IS_HASWELL(dev
)) {
10067 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
10068 dev_priv
->display
.write_eld
= haswell_write_eld
;
10069 dev_priv
->display
.modeset_global_resources
=
10070 haswell_modeset_global_resources
;
10072 } else if (IS_G4X(dev
)) {
10073 dev_priv
->display
.write_eld
= g4x_write_eld
;
10076 /* Default just returns -ENODEV to indicate unsupported */
10077 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
10079 switch (INTEL_INFO(dev
)->gen
) {
10081 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
10085 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
10090 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
10094 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
10097 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
10103 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10104 * resume, or other times. This quirk makes sure that's the case for
10105 * affected systems.
10107 static void quirk_pipea_force(struct drm_device
*dev
)
10109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10111 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
10112 DRM_INFO("applying pipe a force quirk\n");
10116 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10118 static void quirk_ssc_force_disable(struct drm_device
*dev
)
10120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10121 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
10122 DRM_INFO("applying lvds SSC disable quirk\n");
10126 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10129 static void quirk_invert_brightness(struct drm_device
*dev
)
10131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10132 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
10133 DRM_INFO("applying inverted panel brightness quirk\n");
10137 * Some machines (Dell XPS13) suffer broken backlight controls if
10138 * BLM_PCH_PWM_ENABLE is set.
10140 static void quirk_no_pcm_pwm_enable(struct drm_device
*dev
)
10142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10143 dev_priv
->quirks
|= QUIRK_NO_PCH_PWM_ENABLE
;
10144 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10147 struct intel_quirk
{
10149 int subsystem_vendor
;
10150 int subsystem_device
;
10151 void (*hook
)(struct drm_device
*dev
);
10154 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10155 struct intel_dmi_quirk
{
10156 void (*hook
)(struct drm_device
*dev
);
10157 const struct dmi_system_id (*dmi_id_list
)[];
10160 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
10162 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
10166 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
10168 .dmi_id_list
= &(const struct dmi_system_id
[]) {
10170 .callback
= intel_dmi_reverse_brightness
,
10171 .ident
= "NCR Corporation",
10172 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
10173 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
10176 { } /* terminating entry */
10178 .hook
= quirk_invert_brightness
,
10182 static struct intel_quirk intel_quirks
[] = {
10183 /* HP Mini needs pipe A force quirk (LP: #322104) */
10184 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
10186 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10187 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
10189 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10190 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
10192 /* 830/845 need to leave pipe A & dpll A up */
10193 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10194 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10196 /* Lenovo U160 cannot use SSC on LVDS */
10197 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10199 /* Sony Vaio Y cannot use SSC on LVDS */
10200 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10203 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10204 * seem to use inverted backlight PWM.
10206 { 0x2a42, 0x1025, PCI_ANY_ID
, quirk_invert_brightness
},
10208 /* Dell XPS13 HD Sandy Bridge */
10209 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable
},
10210 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10211 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable
},
10214 static void intel_init_quirks(struct drm_device
*dev
)
10216 struct pci_dev
*d
= dev
->pdev
;
10219 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10220 struct intel_quirk
*q
= &intel_quirks
[i
];
10222 if (d
->device
== q
->device
&&
10223 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10224 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10225 (d
->subsystem_device
== q
->subsystem_device
||
10226 q
->subsystem_device
== PCI_ANY_ID
))
10229 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10230 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10231 intel_dmi_quirks
[i
].hook(dev
);
10235 /* Disable the VGA plane that we never use */
10236 static void i915_disable_vga(struct drm_device
*dev
)
10238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10240 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10242 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10243 outb(SR01
, VGA_SR_INDEX
);
10244 sr1
= inb(VGA_SR_DATA
);
10245 outb(sr1
| 1<<5, VGA_SR_DATA
);
10246 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10249 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10250 POSTING_READ(vga_reg
);
10253 static void i915_enable_vga_mem(struct drm_device
*dev
)
10255 /* Enable VGA memory on Intel HD */
10256 if (HAS_PCH_SPLIT(dev
)) {
10257 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10258 outb(inb(VGA_MSR_READ
) | VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10259 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10260 VGA_RSRC_LEGACY_MEM
|
10261 VGA_RSRC_NORMAL_IO
|
10262 VGA_RSRC_NORMAL_MEM
);
10263 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10267 void i915_disable_vga_mem(struct drm_device
*dev
)
10269 /* Disable VGA memory on Intel HD */
10270 if (HAS_PCH_SPLIT(dev
)) {
10271 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10272 outb(inb(VGA_MSR_READ
) & ~VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10273 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10274 VGA_RSRC_NORMAL_IO
|
10275 VGA_RSRC_NORMAL_MEM
);
10276 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10280 void intel_modeset_init_hw(struct drm_device
*dev
)
10282 intel_prepare_ddi(dev
);
10284 intel_init_clock_gating(dev
);
10286 mutex_lock(&dev
->struct_mutex
);
10287 intel_enable_gt_powersave(dev
);
10288 mutex_unlock(&dev
->struct_mutex
);
10291 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10293 intel_suspend_hw(dev
);
10296 void intel_modeset_init(struct drm_device
*dev
)
10298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10301 drm_mode_config_init(dev
);
10303 dev
->mode_config
.min_width
= 0;
10304 dev
->mode_config
.min_height
= 0;
10306 dev
->mode_config
.preferred_depth
= 24;
10307 dev
->mode_config
.prefer_shadow
= 1;
10309 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10311 intel_init_quirks(dev
);
10313 intel_init_pm(dev
);
10315 if (INTEL_INFO(dev
)->num_pipes
== 0)
10318 intel_init_display(dev
);
10320 if (IS_GEN2(dev
)) {
10321 dev
->mode_config
.max_width
= 2048;
10322 dev
->mode_config
.max_height
= 2048;
10323 } else if (IS_GEN3(dev
)) {
10324 dev
->mode_config
.max_width
= 4096;
10325 dev
->mode_config
.max_height
= 4096;
10327 dev
->mode_config
.max_width
= 8192;
10328 dev
->mode_config
.max_height
= 8192;
10330 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10332 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10333 INTEL_INFO(dev
)->num_pipes
,
10334 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10337 intel_crtc_init(dev
, i
);
10338 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10339 ret
= intel_plane_init(dev
, i
, j
);
10341 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10342 pipe_name(i
), sprite_name(i
, j
), ret
);
10346 intel_cpu_pll_init(dev
);
10347 intel_shared_dpll_init(dev
);
10349 /* Just disable it once at startup */
10350 i915_disable_vga(dev
);
10351 intel_setup_outputs(dev
);
10353 /* Just in case the BIOS is doing something questionable. */
10354 intel_disable_fbc(dev
);
10358 intel_connector_break_all_links(struct intel_connector
*connector
)
10360 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10361 connector
->base
.encoder
= NULL
;
10362 connector
->encoder
->connectors_active
= false;
10363 connector
->encoder
->base
.crtc
= NULL
;
10366 static void intel_enable_pipe_a(struct drm_device
*dev
)
10368 struct intel_connector
*connector
;
10369 struct drm_connector
*crt
= NULL
;
10370 struct intel_load_detect_pipe load_detect_temp
;
10372 /* We can't just switch on the pipe A, we need to set things up with a
10373 * proper mode and output configuration. As a gross hack, enable pipe A
10374 * by enabling the load detect pipe once. */
10375 list_for_each_entry(connector
,
10376 &dev
->mode_config
.connector_list
,
10378 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
10379 crt
= &connector
->base
;
10387 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
10388 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
10394 intel_check_plane_mapping(struct intel_crtc
*crtc
)
10396 struct drm_device
*dev
= crtc
->base
.dev
;
10397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10400 if (INTEL_INFO(dev
)->num_pipes
== 1)
10403 reg
= DSPCNTR(!crtc
->plane
);
10404 val
= I915_READ(reg
);
10406 if ((val
& DISPLAY_PLANE_ENABLE
) &&
10407 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
10413 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
10415 struct drm_device
*dev
= crtc
->base
.dev
;
10416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10419 /* Clear any frame start delays used for debugging left by the BIOS */
10420 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
10421 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
10423 /* We need to sanitize the plane -> pipe mapping first because this will
10424 * disable the crtc (and hence change the state) if it is wrong. Note
10425 * that gen4+ has a fixed plane -> pipe mapping. */
10426 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
10427 struct intel_connector
*connector
;
10430 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10431 crtc
->base
.base
.id
);
10433 /* Pipe has the wrong plane attached and the plane is active.
10434 * Temporarily change the plane mapping and disable everything
10436 plane
= crtc
->plane
;
10437 crtc
->plane
= !plane
;
10438 dev_priv
->display
.crtc_disable(&crtc
->base
);
10439 crtc
->plane
= plane
;
10441 /* ... and break all links. */
10442 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10444 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
10447 intel_connector_break_all_links(connector
);
10450 WARN_ON(crtc
->active
);
10451 crtc
->base
.enabled
= false;
10454 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
10455 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
10456 /* BIOS forgot to enable pipe A, this mostly happens after
10457 * resume. Force-enable the pipe to fix this, the update_dpms
10458 * call below we restore the pipe to the right state, but leave
10459 * the required bits on. */
10460 intel_enable_pipe_a(dev
);
10463 /* Adjust the state of the output pipe according to whether we
10464 * have active connectors/encoders. */
10465 intel_crtc_update_dpms(&crtc
->base
);
10467 if (crtc
->active
!= crtc
->base
.enabled
) {
10468 struct intel_encoder
*encoder
;
10470 /* This can happen either due to bugs in the get_hw_state
10471 * functions or because the pipe is force-enabled due to the
10473 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10474 crtc
->base
.base
.id
,
10475 crtc
->base
.enabled
? "enabled" : "disabled",
10476 crtc
->active
? "enabled" : "disabled");
10478 crtc
->base
.enabled
= crtc
->active
;
10480 /* Because we only establish the connector -> encoder ->
10481 * crtc links if something is active, this means the
10482 * crtc is now deactivated. Break the links. connector
10483 * -> encoder links are only establish when things are
10484 * actually up, hence no need to break them. */
10485 WARN_ON(crtc
->active
);
10487 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
10488 WARN_ON(encoder
->connectors_active
);
10489 encoder
->base
.crtc
= NULL
;
10494 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
10496 struct intel_connector
*connector
;
10497 struct drm_device
*dev
= encoder
->base
.dev
;
10499 /* We need to check both for a crtc link (meaning that the
10500 * encoder is active and trying to read from a pipe) and the
10501 * pipe itself being active. */
10502 bool has_active_crtc
= encoder
->base
.crtc
&&
10503 to_intel_crtc(encoder
->base
.crtc
)->active
;
10505 if (encoder
->connectors_active
&& !has_active_crtc
) {
10506 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10507 encoder
->base
.base
.id
,
10508 drm_get_encoder_name(&encoder
->base
));
10510 /* Connector is active, but has no active pipe. This is
10511 * fallout from our resume register restoring. Disable
10512 * the encoder manually again. */
10513 if (encoder
->base
.crtc
) {
10514 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10515 encoder
->base
.base
.id
,
10516 drm_get_encoder_name(&encoder
->base
));
10517 encoder
->disable(encoder
);
10520 /* Inconsistent output/port/pipe state happens presumably due to
10521 * a bug in one of the get_hw_state functions. Or someplace else
10522 * in our code, like the register restore mess on resume. Clamp
10523 * things to off as a safer default. */
10524 list_for_each_entry(connector
,
10525 &dev
->mode_config
.connector_list
,
10527 if (connector
->encoder
!= encoder
)
10530 intel_connector_break_all_links(connector
);
10533 /* Enabled encoders without active connectors will be fixed in
10534 * the crtc fixup. */
10537 void i915_redisable_vga(struct drm_device
*dev
)
10539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10540 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10542 /* This function can be called both from intel_modeset_setup_hw_state or
10543 * at a very early point in our resume sequence, where the power well
10544 * structures are not yet restored. Since this function is at a very
10545 * paranoid "someone might have enabled VGA while we were not looking"
10546 * level, just check if the power well is enabled instead of trying to
10547 * follow the "don't touch the power well if we don't need it" policy
10548 * the rest of the driver uses. */
10549 if (HAS_POWER_WELL(dev
) &&
10550 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
10553 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
10554 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10555 i915_disable_vga(dev
);
10556 i915_disable_vga_mem(dev
);
10560 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
10562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10564 struct intel_crtc
*crtc
;
10565 struct intel_encoder
*encoder
;
10566 struct intel_connector
*connector
;
10569 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10571 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
10573 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
10576 crtc
->base
.enabled
= crtc
->active
;
10578 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10579 crtc
->base
.base
.id
,
10580 crtc
->active
? "enabled" : "disabled");
10583 /* FIXME: Smash this into the new shared dpll infrastructure. */
10585 intel_ddi_setup_hw_pll_state(dev
);
10587 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10588 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10590 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
10592 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10594 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10597 pll
->refcount
= pll
->active
;
10599 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10600 pll
->name
, pll
->refcount
, pll
->on
);
10603 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10607 if (encoder
->get_hw_state(encoder
, &pipe
)) {
10608 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10609 encoder
->base
.crtc
= &crtc
->base
;
10610 if (encoder
->get_config
)
10611 encoder
->get_config(encoder
, &crtc
->config
);
10613 encoder
->base
.crtc
= NULL
;
10616 encoder
->connectors_active
= false;
10617 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10618 encoder
->base
.base
.id
,
10619 drm_get_encoder_name(&encoder
->base
),
10620 encoder
->base
.crtc
? "enabled" : "disabled",
10624 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10626 if (connector
->get_hw_state(connector
)) {
10627 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
10628 connector
->encoder
->connectors_active
= true;
10629 connector
->base
.encoder
= &connector
->encoder
->base
;
10631 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10632 connector
->base
.encoder
= NULL
;
10634 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10635 connector
->base
.base
.id
,
10636 drm_get_connector_name(&connector
->base
),
10637 connector
->base
.encoder
? "enabled" : "disabled");
10641 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10642 * and i915 state tracking structures. */
10643 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
10644 bool force_restore
)
10646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10648 struct intel_crtc
*crtc
;
10649 struct intel_encoder
*encoder
;
10652 intel_modeset_readout_hw_state(dev
);
10655 * Now that we have the config, copy it to each CRTC struct
10656 * Note that this could go away if we move to using crtc_config
10657 * checking everywhere.
10659 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10661 if (crtc
->active
&& i915_fastboot
) {
10662 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
10664 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10665 crtc
->base
.base
.id
);
10666 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
10670 /* HW state is read out, now we need to sanitize this mess. */
10671 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10673 intel_sanitize_encoder(encoder
);
10676 for_each_pipe(pipe
) {
10677 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10678 intel_sanitize_crtc(crtc
);
10679 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
10682 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10683 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10685 if (!pll
->on
|| pll
->active
)
10688 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
10690 pll
->disable(dev_priv
, pll
);
10694 if (force_restore
) {
10695 i915_redisable_vga(dev
);
10698 * We need to use raw interfaces for restoring state to avoid
10699 * checking (bogus) intermediate states.
10701 for_each_pipe(pipe
) {
10702 struct drm_crtc
*crtc
=
10703 dev_priv
->pipe_to_crtc_mapping
[pipe
];
10705 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
10709 intel_modeset_update_staged_output_state(dev
);
10712 intel_modeset_check_state(dev
);
10714 drm_mode_config_reset(dev
);
10717 void intel_modeset_gem_init(struct drm_device
*dev
)
10719 intel_modeset_init_hw(dev
);
10721 intel_setup_overlay(dev
);
10723 intel_modeset_setup_hw_state(dev
, false);
10726 void intel_modeset_cleanup(struct drm_device
*dev
)
10728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10729 struct drm_crtc
*crtc
;
10730 struct drm_connector
*connector
;
10733 * Interrupts and polling as the first thing to avoid creating havoc.
10734 * Too much stuff here (turning of rps, connectors, ...) would
10735 * experience fancy races otherwise.
10737 drm_irq_uninstall(dev
);
10738 cancel_work_sync(&dev_priv
->hotplug_work
);
10740 * Due to the hpd irq storm handling the hotplug work can re-arm the
10741 * poll handlers. Hence disable polling after hpd handling is shut down.
10743 drm_kms_helper_poll_fini(dev
);
10745 mutex_lock(&dev
->struct_mutex
);
10747 intel_unregister_dsm_handler();
10749 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
10750 /* Skip inactive CRTCs */
10754 intel_increase_pllclock(crtc
);
10757 intel_disable_fbc(dev
);
10759 i915_enable_vga_mem(dev
);
10761 intel_disable_gt_powersave(dev
);
10763 ironlake_teardown_rc6(dev
);
10765 mutex_unlock(&dev
->struct_mutex
);
10767 /* flush any delayed tasks or pending work */
10768 flush_scheduled_work();
10770 /* destroy backlight, if any, before the connectors */
10771 intel_panel_destroy_backlight(dev
);
10773 /* destroy the sysfs files before encoders/connectors */
10774 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
)
10775 drm_sysfs_connector_remove(connector
);
10777 drm_mode_config_cleanup(dev
);
10779 intel_cleanup_overlay(dev
);
10783 * Return which encoder is currently attached for connector.
10785 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
10787 return &intel_attached_encoder(connector
)->base
;
10790 void intel_connector_attach_encoder(struct intel_connector
*connector
,
10791 struct intel_encoder
*encoder
)
10793 connector
->encoder
= encoder
;
10794 drm_mode_connector_attach_encoder(&connector
->base
,
10799 * set vga decode state - true == enable VGA decode
10801 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
10803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10806 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
10808 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
10810 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
10811 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
10815 struct intel_display_error_state
{
10817 u32 power_well_driver
;
10819 int num_transcoders
;
10821 struct intel_cursor_error_state
{
10826 } cursor
[I915_MAX_PIPES
];
10828 struct intel_pipe_error_state
{
10830 } pipe
[I915_MAX_PIPES
];
10832 struct intel_plane_error_state
{
10840 } plane
[I915_MAX_PIPES
];
10842 struct intel_transcoder_error_state
{
10843 enum transcoder cpu_transcoder
;
10856 struct intel_display_error_state
*
10857 intel_display_capture_error_state(struct drm_device
*dev
)
10859 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10860 struct intel_display_error_state
*error
;
10861 int transcoders
[] = {
10869 if (INTEL_INFO(dev
)->num_pipes
== 0)
10872 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
10876 if (HAS_POWER_WELL(dev
))
10877 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
10880 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
10881 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
10882 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
10883 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
10885 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
10886 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
10887 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
10890 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
10891 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
10892 if (INTEL_INFO(dev
)->gen
<= 3) {
10893 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
10894 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
10896 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10897 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
10898 if (INTEL_INFO(dev
)->gen
>= 4) {
10899 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
10900 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
10903 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
10906 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
10907 if (HAS_DDI(dev_priv
->dev
))
10908 error
->num_transcoders
++; /* Account for eDP. */
10910 for (i
= 0; i
< error
->num_transcoders
; i
++) {
10911 enum transcoder cpu_transcoder
= transcoders
[i
];
10913 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
10915 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
10916 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
10917 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
10918 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
10919 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
10920 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
10921 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
10924 /* In the code above we read the registers without checking if the power
10925 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10926 * prevent the next I915_WRITE from detecting it and printing an error
10928 intel_uncore_clear_errors(dev
);
10933 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10936 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
10937 struct drm_device
*dev
,
10938 struct intel_display_error_state
*error
)
10945 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
10946 if (HAS_POWER_WELL(dev
))
10947 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
10948 error
->power_well_driver
);
10950 err_printf(m
, "Pipe [%d]:\n", i
);
10951 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
10953 err_printf(m
, "Plane [%d]:\n", i
);
10954 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
10955 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
10956 if (INTEL_INFO(dev
)->gen
<= 3) {
10957 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
10958 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
10960 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10961 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
10962 if (INTEL_INFO(dev
)->gen
>= 4) {
10963 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
10964 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
10967 err_printf(m
, "Cursor [%d]:\n", i
);
10968 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
10969 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
10970 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
10973 for (i
= 0; i
< error
->num_transcoders
; i
++) {
10974 err_printf(m
, " CPU transcoder: %c\n",
10975 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
10976 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
10977 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
10978 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
10979 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
10980 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
10981 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
10982 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);