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drm: add backwards compatibility support for drm_kms_helper.edid_firmware
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 static bool is_mmio_work(struct intel_flip_work *work)
53 {
54 return work->mmio_work.func;
55 }
56
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_XRGB1555,
62 DRM_FORMAT_XRGB8888,
63 };
64
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73 };
74
75 static const uint32_t skl_primary_formats[] = {
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
79 DRM_FORMAT_XBGR8888,
80 DRM_FORMAT_ARGB8888,
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
88 };
89
90 /* Cursor formats */
91 static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93 };
94
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
99
100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101 struct drm_i915_gem_object *obj,
102 struct drm_mode_fb_cmd2 *mode_cmd);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev,
124 struct drm_modeset_acquire_ctx *ctx);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126
127 struct intel_limit {
128 struct {
129 int min, max;
130 } dot, vco, n, m, m1, m2, p, p1;
131
132 struct {
133 int dot_limit;
134 int p2_slow, p2_fast;
135 } p2;
136 };
137
138 /* returns HPLL frequency in kHz */
139 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
140 {
141 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142
143 /* Obtain SKU information */
144 mutex_lock(&dev_priv->sb_lock);
145 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
146 CCK_FUSE_HPLL_FREQ_MASK;
147 mutex_unlock(&dev_priv->sb_lock);
148
149 return vco_freq[hpll_freq] * 1000;
150 }
151
152 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg, int ref_freq)
154 {
155 u32 val;
156 int divider;
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
169 }
170
171 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
172 const char *name, u32 reg)
173 {
174 if (dev_priv->hpll_freq == 0)
175 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
176
177 return vlv_get_cck_clock(dev_priv, name, reg,
178 dev_priv->hpll_freq);
179 }
180
181 static void intel_update_czclk(struct drm_i915_private *dev_priv)
182 {
183 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
184 return;
185
186 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
187 CCK_CZ_CLOCK_CONTROL);
188
189 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
190 }
191
192 static inline u32 /* units of 100MHz */
193 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
194 const struct intel_crtc_state *pipe_config)
195 {
196 if (HAS_DDI(dev_priv))
197 return pipe_config->port_clock; /* SPLL */
198 else if (IS_GEN5(dev_priv))
199 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
200 else
201 return 270000;
202 }
203
204 static const struct intel_limit intel_limits_i8xx_dac = {
205 .dot = { .min = 25000, .max = 350000 },
206 .vco = { .min = 908000, .max = 1512000 },
207 .n = { .min = 2, .max = 16 },
208 .m = { .min = 96, .max = 140 },
209 .m1 = { .min = 18, .max = 26 },
210 .m2 = { .min = 6, .max = 16 },
211 .p = { .min = 4, .max = 128 },
212 .p1 = { .min = 2, .max = 33 },
213 .p2 = { .dot_limit = 165000,
214 .p2_slow = 4, .p2_fast = 2 },
215 };
216
217 static const struct intel_limit intel_limits_i8xx_dvo = {
218 .dot = { .min = 25000, .max = 350000 },
219 .vco = { .min = 908000, .max = 1512000 },
220 .n = { .min = 2, .max = 16 },
221 .m = { .min = 96, .max = 140 },
222 .m1 = { .min = 18, .max = 26 },
223 .m2 = { .min = 6, .max = 16 },
224 .p = { .min = 4, .max = 128 },
225 .p1 = { .min = 2, .max = 33 },
226 .p2 = { .dot_limit = 165000,
227 .p2_slow = 4, .p2_fast = 4 },
228 };
229
230 static const struct intel_limit intel_limits_i8xx_lvds = {
231 .dot = { .min = 25000, .max = 350000 },
232 .vco = { .min = 908000, .max = 1512000 },
233 .n = { .min = 2, .max = 16 },
234 .m = { .min = 96, .max = 140 },
235 .m1 = { .min = 18, .max = 26 },
236 .m2 = { .min = 6, .max = 16 },
237 .p = { .min = 4, .max = 128 },
238 .p1 = { .min = 1, .max = 6 },
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 14, .p2_fast = 7 },
241 };
242
243 static const struct intel_limit intel_limits_i9xx_sdvo = {
244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1400000, .max = 2800000 },
246 .n = { .min = 1, .max = 6 },
247 .m = { .min = 70, .max = 120 },
248 .m1 = { .min = 8, .max = 18 },
249 .m2 = { .min = 3, .max = 7 },
250 .p = { .min = 5, .max = 80 },
251 .p1 = { .min = 1, .max = 8 },
252 .p2 = { .dot_limit = 200000,
253 .p2_slow = 10, .p2_fast = 5 },
254 };
255
256 static const struct intel_limit intel_limits_i9xx_lvds = {
257 .dot = { .min = 20000, .max = 400000 },
258 .vco = { .min = 1400000, .max = 2800000 },
259 .n = { .min = 1, .max = 6 },
260 .m = { .min = 70, .max = 120 },
261 .m1 = { .min = 8, .max = 18 },
262 .m2 = { .min = 3, .max = 7 },
263 .p = { .min = 7, .max = 98 },
264 .p1 = { .min = 1, .max = 8 },
265 .p2 = { .dot_limit = 112000,
266 .p2_slow = 14, .p2_fast = 7 },
267 };
268
269
270 static const struct intel_limit intel_limits_g4x_sdvo = {
271 .dot = { .min = 25000, .max = 270000 },
272 .vco = { .min = 1750000, .max = 3500000},
273 .n = { .min = 1, .max = 4 },
274 .m = { .min = 104, .max = 138 },
275 .m1 = { .min = 17, .max = 23 },
276 .m2 = { .min = 5, .max = 11 },
277 .p = { .min = 10, .max = 30 },
278 .p1 = { .min = 1, .max = 3},
279 .p2 = { .dot_limit = 270000,
280 .p2_slow = 10,
281 .p2_fast = 10
282 },
283 };
284
285 static const struct intel_limit intel_limits_g4x_hdmi = {
286 .dot = { .min = 22000, .max = 400000 },
287 .vco = { .min = 1750000, .max = 3500000},
288 .n = { .min = 1, .max = 4 },
289 .m = { .min = 104, .max = 138 },
290 .m1 = { .min = 16, .max = 23 },
291 .m2 = { .min = 5, .max = 11 },
292 .p = { .min = 5, .max = 80 },
293 .p1 = { .min = 1, .max = 8},
294 .p2 = { .dot_limit = 165000,
295 .p2_slow = 10, .p2_fast = 5 },
296 };
297
298 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
299 .dot = { .min = 20000, .max = 115000 },
300 .vco = { .min = 1750000, .max = 3500000 },
301 .n = { .min = 1, .max = 3 },
302 .m = { .min = 104, .max = 138 },
303 .m1 = { .min = 17, .max = 23 },
304 .m2 = { .min = 5, .max = 11 },
305 .p = { .min = 28, .max = 112 },
306 .p1 = { .min = 2, .max = 8 },
307 .p2 = { .dot_limit = 0,
308 .p2_slow = 14, .p2_fast = 14
309 },
310 };
311
312 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
313 .dot = { .min = 80000, .max = 224000 },
314 .vco = { .min = 1750000, .max = 3500000 },
315 .n = { .min = 1, .max = 3 },
316 .m = { .min = 104, .max = 138 },
317 .m1 = { .min = 17, .max = 23 },
318 .m2 = { .min = 5, .max = 11 },
319 .p = { .min = 14, .max = 42 },
320 .p1 = { .min = 2, .max = 6 },
321 .p2 = { .dot_limit = 0,
322 .p2_slow = 7, .p2_fast = 7
323 },
324 };
325
326 static const struct intel_limit intel_limits_pineview_sdvo = {
327 .dot = { .min = 20000, .max = 400000},
328 .vco = { .min = 1700000, .max = 3500000 },
329 /* Pineview's Ncounter is a ring counter */
330 .n = { .min = 3, .max = 6 },
331 .m = { .min = 2, .max = 256 },
332 /* Pineview only has one combined m divider, which we treat as m2. */
333 .m1 = { .min = 0, .max = 0 },
334 .m2 = { .min = 0, .max = 254 },
335 .p = { .min = 5, .max = 80 },
336 .p1 = { .min = 1, .max = 8 },
337 .p2 = { .dot_limit = 200000,
338 .p2_slow = 10, .p2_fast = 5 },
339 };
340
341 static const struct intel_limit intel_limits_pineview_lvds = {
342 .dot = { .min = 20000, .max = 400000 },
343 .vco = { .min = 1700000, .max = 3500000 },
344 .n = { .min = 3, .max = 6 },
345 .m = { .min = 2, .max = 256 },
346 .m1 = { .min = 0, .max = 0 },
347 .m2 = { .min = 0, .max = 254 },
348 .p = { .min = 7, .max = 112 },
349 .p1 = { .min = 1, .max = 8 },
350 .p2 = { .dot_limit = 112000,
351 .p2_slow = 14, .p2_fast = 14 },
352 };
353
354 /* Ironlake / Sandybridge
355 *
356 * We calculate clock using (register_value + 2) for N/M1/M2, so here
357 * the range value for them is (actual_value - 2).
358 */
359 static const struct intel_limit intel_limits_ironlake_dac = {
360 .dot = { .min = 25000, .max = 350000 },
361 .vco = { .min = 1760000, .max = 3510000 },
362 .n = { .min = 1, .max = 5 },
363 .m = { .min = 79, .max = 127 },
364 .m1 = { .min = 12, .max = 22 },
365 .m2 = { .min = 5, .max = 9 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 225000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const struct intel_limit intel_limits_ironlake_single_lvds = {
373 .dot = { .min = 25000, .max = 350000 },
374 .vco = { .min = 1760000, .max = 3510000 },
375 .n = { .min = 1, .max = 3 },
376 .m = { .min = 79, .max = 118 },
377 .m1 = { .min = 12, .max = 22 },
378 .m2 = { .min = 5, .max = 9 },
379 .p = { .min = 28, .max = 112 },
380 .p1 = { .min = 2, .max = 8 },
381 .p2 = { .dot_limit = 225000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
386 .dot = { .min = 25000, .max = 350000 },
387 .vco = { .min = 1760000, .max = 3510000 },
388 .n = { .min = 1, .max = 3 },
389 .m = { .min = 79, .max = 127 },
390 .m1 = { .min = 12, .max = 22 },
391 .m2 = { .min = 5, .max = 9 },
392 .p = { .min = 14, .max = 56 },
393 .p1 = { .min = 2, .max = 8 },
394 .p2 = { .dot_limit = 225000,
395 .p2_slow = 7, .p2_fast = 7 },
396 };
397
398 /* LVDS 100mhz refclk limits. */
399 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
400 .dot = { .min = 25000, .max = 350000 },
401 .vco = { .min = 1760000, .max = 3510000 },
402 .n = { .min = 1, .max = 2 },
403 .m = { .min = 79, .max = 126 },
404 .m1 = { .min = 12, .max = 22 },
405 .m2 = { .min = 5, .max = 9 },
406 .p = { .min = 28, .max = 112 },
407 .p1 = { .min = 2, .max = 8 },
408 .p2 = { .dot_limit = 225000,
409 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
413 .dot = { .min = 25000, .max = 350000 },
414 .vco = { .min = 1760000, .max = 3510000 },
415 .n = { .min = 1, .max = 3 },
416 .m = { .min = 79, .max = 126 },
417 .m1 = { .min = 12, .max = 22 },
418 .m2 = { .min = 5, .max = 9 },
419 .p = { .min = 14, .max = 42 },
420 .p1 = { .min = 2, .max = 6 },
421 .p2 = { .dot_limit = 225000,
422 .p2_slow = 7, .p2_fast = 7 },
423 };
424
425 static const struct intel_limit intel_limits_vlv = {
426 /*
427 * These are the data rate limits (measured in fast clocks)
428 * since those are the strictest limits we have. The fast
429 * clock and actual rate limits are more relaxed, so checking
430 * them would make no difference.
431 */
432 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
433 .vco = { .min = 4000000, .max = 6000000 },
434 .n = { .min = 1, .max = 7 },
435 .m1 = { .min = 2, .max = 3 },
436 .m2 = { .min = 11, .max = 156 },
437 .p1 = { .min = 2, .max = 3 },
438 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
439 };
440
441 static const struct intel_limit intel_limits_chv = {
442 /*
443 * These are the data rate limits (measured in fast clocks)
444 * since those are the strictest limits we have. The fast
445 * clock and actual rate limits are more relaxed, so checking
446 * them would make no difference.
447 */
448 .dot = { .min = 25000 * 5, .max = 540000 * 5},
449 .vco = { .min = 4800000, .max = 6480000 },
450 .n = { .min = 1, .max = 1 },
451 .m1 = { .min = 2, .max = 2 },
452 .m2 = { .min = 24 << 22, .max = 175 << 22 },
453 .p1 = { .min = 2, .max = 4 },
454 .p2 = { .p2_slow = 1, .p2_fast = 14 },
455 };
456
457 static const struct intel_limit intel_limits_bxt = {
458 /* FIXME: find real dot limits */
459 .dot = { .min = 0, .max = INT_MAX },
460 .vco = { .min = 4800000, .max = 6700000 },
461 .n = { .min = 1, .max = 1 },
462 .m1 = { .min = 2, .max = 2 },
463 /* FIXME: find real m2 limits */
464 .m2 = { .min = 2 << 22, .max = 255 << 22 },
465 .p1 = { .min = 2, .max = 4 },
466 .p2 = { .p2_slow = 1, .p2_fast = 20 },
467 };
468
469 static bool
470 needs_modeset(struct drm_crtc_state *state)
471 {
472 return drm_atomic_crtc_needs_modeset(state);
473 }
474
475 /*
476 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
477 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
478 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
479 * The helpers' return value is the rate of the clock that is fed to the
480 * display engine's pipe which can be the above fast dot clock rate or a
481 * divided-down version of it.
482 */
483 /* m1 is reserved as 0 in Pineview, n is a ring counter */
484 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
485 {
486 clock->m = clock->m2 + 2;
487 clock->p = clock->p1 * clock->p2;
488 if (WARN_ON(clock->n == 0 || clock->p == 0))
489 return 0;
490 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
491 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
492
493 return clock->dot;
494 }
495
496 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
497 {
498 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
499 }
500
501 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
502 {
503 clock->m = i9xx_dpll_compute_m(clock);
504 clock->p = clock->p1 * clock->p2;
505 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
506 return 0;
507 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
508 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
509
510 return clock->dot;
511 }
512
513 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
514 {
515 clock->m = clock->m1 * clock->m2;
516 clock->p = clock->p1 * clock->p2;
517 if (WARN_ON(clock->n == 0 || clock->p == 0))
518 return 0;
519 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
520 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
521
522 return clock->dot / 5;
523 }
524
525 int chv_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527 clock->m = clock->m1 * clock->m2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return 0;
531 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
532 clock->n << 22);
533 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
534
535 return clock->dot / 5;
536 }
537
538 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
539 /**
540 * Returns whether the given set of divisors are valid for a given refclk with
541 * the given connectors.
542 */
543
544 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
545 const struct intel_limit *limit,
546 const struct dpll *clock)
547 {
548 if (clock->n < limit->n.min || limit->n.max < clock->n)
549 INTELPllInvalid("n out of range\n");
550 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
551 INTELPllInvalid("p1 out of range\n");
552 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
553 INTELPllInvalid("m2 out of range\n");
554 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
555 INTELPllInvalid("m1 out of range\n");
556
557 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
558 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
559 if (clock->m1 <= clock->m2)
560 INTELPllInvalid("m1 <= m2\n");
561
562 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
563 !IS_GEN9_LP(dev_priv)) {
564 if (clock->p < limit->p.min || limit->p.max < clock->p)
565 INTELPllInvalid("p out of range\n");
566 if (clock->m < limit->m.min || limit->m.max < clock->m)
567 INTELPllInvalid("m out of range\n");
568 }
569
570 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
571 INTELPllInvalid("vco out of range\n");
572 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
573 * connector, etc., rather than just a single range.
574 */
575 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
576 INTELPllInvalid("dot out of range\n");
577
578 return true;
579 }
580
581 static int
582 i9xx_select_p2_div(const struct intel_limit *limit,
583 const struct intel_crtc_state *crtc_state,
584 int target)
585 {
586 struct drm_device *dev = crtc_state->base.crtc->dev;
587
588 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
589 /*
590 * For LVDS just rely on its current settings for dual-channel.
591 * We haven't figured out how to reliably set up different
592 * single/dual channel state, if we even can.
593 */
594 if (intel_is_dual_link_lvds(dev))
595 return limit->p2.p2_fast;
596 else
597 return limit->p2.p2_slow;
598 } else {
599 if (target < limit->p2.dot_limit)
600 return limit->p2.p2_slow;
601 else
602 return limit->p2.p2_fast;
603 }
604 }
605
606 /*
607 * Returns a set of divisors for the desired target clock with the given
608 * refclk, or FALSE. The returned values represent the clock equation:
609 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
610 *
611 * Target and reference clocks are specified in kHz.
612 *
613 * If match_clock is provided, then best_clock P divider must match the P
614 * divider from @match_clock used for LVDS downclocking.
615 */
616 static bool
617 i9xx_find_best_dpll(const struct intel_limit *limit,
618 struct intel_crtc_state *crtc_state,
619 int target, int refclk, struct dpll *match_clock,
620 struct dpll *best_clock)
621 {
622 struct drm_device *dev = crtc_state->base.crtc->dev;
623 struct dpll clock;
624 int err = target;
625
626 memset(best_clock, 0, sizeof(*best_clock));
627
628 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_calc_dpll_params(refclk, &clock);
643 if (!intel_PLL_is_valid(to_i915(dev),
644 limit,
645 &clock))
646 continue;
647 if (match_clock &&
648 clock.p != match_clock->p)
649 continue;
650
651 this_err = abs(clock.dot - target);
652 if (this_err < err) {
653 *best_clock = clock;
654 err = this_err;
655 }
656 }
657 }
658 }
659 }
660
661 return (err != target);
662 }
663
664 /*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 *
669 * Target and reference clocks are specified in kHz.
670 *
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
673 */
674 static bool
675 pnv_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
679 {
680 struct drm_device *dev = crtc_state->base.crtc->dev;
681 struct dpll clock;
682 int err = target;
683
684 memset(best_clock, 0, sizeof(*best_clock));
685
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 for (clock.n = limit->n.min;
693 clock.n <= limit->n.max; clock.n++) {
694 for (clock.p1 = limit->p1.min;
695 clock.p1 <= limit->p1.max; clock.p1++) {
696 int this_err;
697
698 pnv_calc_dpll_params(refclk, &clock);
699 if (!intel_PLL_is_valid(to_i915(dev),
700 limit,
701 &clock))
702 continue;
703 if (match_clock &&
704 clock.p != match_clock->p)
705 continue;
706
707 this_err = abs(clock.dot - target);
708 if (this_err < err) {
709 *best_clock = clock;
710 err = this_err;
711 }
712 }
713 }
714 }
715 }
716
717 return (err != target);
718 }
719
720 /*
721 * Returns a set of divisors for the desired target clock with the given
722 * refclk, or FALSE. The returned values represent the clock equation:
723 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
724 *
725 * Target and reference clocks are specified in kHz.
726 *
727 * If match_clock is provided, then best_clock P divider must match the P
728 * divider from @match_clock used for LVDS downclocking.
729 */
730 static bool
731 g4x_find_best_dpll(const struct intel_limit *limit,
732 struct intel_crtc_state *crtc_state,
733 int target, int refclk, struct dpll *match_clock,
734 struct dpll *best_clock)
735 {
736 struct drm_device *dev = crtc_state->base.crtc->dev;
737 struct dpll clock;
738 int max_n;
739 bool found = false;
740 /* approximately equals target * 0.00585 */
741 int err_most = (target >> 8) + (target >> 9);
742
743 memset(best_clock, 0, sizeof(*best_clock));
744
745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_calc_dpll_params(refclk, &clock);
760 if (!intel_PLL_is_valid(to_i915(dev),
761 limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 /*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const struct dpll *calculated_clock,
785 const struct dpll *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788 {
789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(to_i915(dev))) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
799 if (WARN_ON_ONCE(!target_freq))
800 return false;
801
802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817 }
818
819 /*
820 * Returns a set of divisors for the desired target clock with the given
821 * refclk, or FALSE. The returned values represent the clock equation:
822 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
823 */
824 static bool
825 vlv_find_best_dpll(const struct intel_limit *limit,
826 struct intel_crtc_state *crtc_state,
827 int target, int refclk, struct dpll *match_clock,
828 struct dpll *best_clock)
829 {
830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
831 struct drm_device *dev = crtc->base.dev;
832 struct dpll clock;
833 unsigned int bestppm = 1000000;
834 /* min update 19.2 MHz */
835 int max_n = min(limit->n.max, refclk / 19200);
836 bool found = false;
837
838 target *= 5; /* fast clock */
839
840 memset(best_clock, 0, sizeof(*best_clock));
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
844 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
845 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
846 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
847 clock.p = clock.p1 * clock.p2;
848 /* based on hardware requirement, prefer bigger m1,m2 values */
849 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
850 unsigned int ppm;
851
852 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
853 refclk * clock.m1);
854
855 vlv_calc_dpll_params(refclk, &clock);
856
857 if (!intel_PLL_is_valid(to_i915(dev),
858 limit,
859 &clock))
860 continue;
861
862 if (!vlv_PLL_is_optimal(dev, target,
863 &clock,
864 best_clock,
865 bestppm, &ppm))
866 continue;
867
868 *best_clock = clock;
869 bestppm = ppm;
870 found = true;
871 }
872 }
873 }
874 }
875
876 return found;
877 }
878
879 /*
880 * Returns a set of divisors for the desired target clock with the given
881 * refclk, or FALSE. The returned values represent the clock equation:
882 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
883 */
884 static bool
885 chv_find_best_dpll(const struct intel_limit *limit,
886 struct intel_crtc_state *crtc_state,
887 int target, int refclk, struct dpll *match_clock,
888 struct dpll *best_clock)
889 {
890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
891 struct drm_device *dev = crtc->base.dev;
892 unsigned int best_error_ppm;
893 struct dpll clock;
894 uint64_t m2;
895 int found = false;
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 best_error_ppm = 1000000;
899
900 /*
901 * Based on hardware doc, the n always set to 1, and m1 always
902 * set to 2. If requires to support 200Mhz refclk, we need to
903 * revisit this because n may not 1 anymore.
904 */
905 clock.n = 1, clock.m1 = 2;
906 target *= 5; /* fast clock */
907
908 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
909 for (clock.p2 = limit->p2.p2_fast;
910 clock.p2 >= limit->p2.p2_slow;
911 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
912 unsigned int error_ppm;
913
914 clock.p = clock.p1 * clock.p2;
915
916 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
917 clock.n) << 22, refclk * clock.m1);
918
919 if (m2 > INT_MAX/clock.m1)
920 continue;
921
922 clock.m2 = m2;
923
924 chv_calc_dpll_params(refclk, &clock);
925
926 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
927 continue;
928
929 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
930 best_error_ppm, &error_ppm))
931 continue;
932
933 *best_clock = clock;
934 best_error_ppm = error_ppm;
935 found = true;
936 }
937 }
938
939 return found;
940 }
941
942 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
943 struct dpll *best_clock)
944 {
945 int refclk = 100000;
946 const struct intel_limit *limit = &intel_limits_bxt;
947
948 return chv_find_best_dpll(limit, crtc_state,
949 target_clock, refclk, NULL, best_clock);
950 }
951
952 bool intel_crtc_active(struct intel_crtc *crtc)
953 {
954 /* Be paranoid as we can arrive here with only partial
955 * state retrieved from the hardware during setup.
956 *
957 * We can ditch the adjusted_mode.crtc_clock check as soon
958 * as Haswell has gained clock readout/fastboot support.
959 *
960 * We can ditch the crtc->primary->fb check as soon as we can
961 * properly reconstruct framebuffers.
962 *
963 * FIXME: The intel_crtc->active here should be switched to
964 * crtc->state->active once we have proper CRTC states wired up
965 * for atomic.
966 */
967 return crtc->active && crtc->base.primary->state->fb &&
968 crtc->config->base.adjusted_mode.crtc_clock;
969 }
970
971 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
972 enum pipe pipe)
973 {
974 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
975
976 return crtc->config->cpu_transcoder;
977 }
978
979 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
980 {
981 i915_reg_t reg = PIPEDSL(pipe);
982 u32 line1, line2;
983 u32 line_mask;
984
985 if (IS_GEN2(dev_priv))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
990 line1 = I915_READ(reg) & line_mask;
991 msleep(5);
992 line2 = I915_READ(reg) & line_mask;
993
994 return line1 == line2;
995 }
996
997 /*
998 * intel_wait_for_pipe_off - wait for pipe to turn off
999 * @crtc: crtc whose pipe to wait for
1000 *
1001 * After disabling a pipe, we can't wait for vblank in the usual way,
1002 * spinning on the vblank interrupt status bit, since we won't actually
1003 * see an interrupt when the pipe is disabled.
1004 *
1005 * On Gen4 and above:
1006 * wait for the pipe register state bit to turn off
1007 *
1008 * Otherwise:
1009 * wait for the display line value to settle (it usually
1010 * ends up stopping at the start of the next frame).
1011 *
1012 */
1013 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1014 {
1015 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1016 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1017 enum pipe pipe = crtc->pipe;
1018
1019 if (INTEL_GEN(dev_priv) >= 4) {
1020 i915_reg_t reg = PIPECONF(cpu_transcoder);
1021
1022 /* Wait for the Pipe State to go off */
1023 if (intel_wait_for_register(dev_priv,
1024 reg, I965_PIPECONF_ACTIVE, 0,
1025 100))
1026 WARN(1, "pipe_off wait timed out\n");
1027 } else {
1028 /* Wait for the display line to settle */
1029 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1030 WARN(1, "pipe_off wait timed out\n");
1031 }
1032 }
1033
1034 /* Only for pre-ILK configs */
1035 void assert_pll(struct drm_i915_private *dev_priv,
1036 enum pipe pipe, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 val = I915_READ(DPLL(pipe));
1042 cur_state = !!(val & DPLL_VCO_ENABLE);
1043 I915_STATE_WARN(cur_state != state,
1044 "PLL state assertion failure (expected %s, current %s)\n",
1045 onoff(state), onoff(cur_state));
1046 }
1047
1048 /* XXX: the dsi pll is shared between MIPI DSI ports */
1049 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1050 {
1051 u32 val;
1052 bool cur_state;
1053
1054 mutex_lock(&dev_priv->sb_lock);
1055 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1056 mutex_unlock(&dev_priv->sb_lock);
1057
1058 cur_state = val & DSI_PLL_VCO_EN;
1059 I915_STATE_WARN(cur_state != state,
1060 "DSI PLL state assertion failure (expected %s, current %s)\n",
1061 onoff(state), onoff(cur_state));
1062 }
1063
1064 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1066 {
1067 bool cur_state;
1068 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1069 pipe);
1070
1071 if (HAS_DDI(dev_priv)) {
1072 /* DDI does not have a specific FDI_TX register */
1073 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1074 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1075 } else {
1076 u32 val = I915_READ(FDI_TX_CTL(pipe));
1077 cur_state = !!(val & FDI_TX_ENABLE);
1078 }
1079 I915_STATE_WARN(cur_state != state,
1080 "FDI TX state assertion failure (expected %s, current %s)\n",
1081 onoff(state), onoff(cur_state));
1082 }
1083 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1084 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1085
1086 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1087 enum pipe pipe, bool state)
1088 {
1089 u32 val;
1090 bool cur_state;
1091
1092 val = I915_READ(FDI_RX_CTL(pipe));
1093 cur_state = !!(val & FDI_RX_ENABLE);
1094 I915_STATE_WARN(cur_state != state,
1095 "FDI RX state assertion failure (expected %s, current %s)\n",
1096 onoff(state), onoff(cur_state));
1097 }
1098 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1099 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1100
1101 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1102 enum pipe pipe)
1103 {
1104 u32 val;
1105
1106 /* ILK FDI PLL is always enabled */
1107 if (IS_GEN5(dev_priv))
1108 return;
1109
1110 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1111 if (HAS_DDI(dev_priv))
1112 return;
1113
1114 val = I915_READ(FDI_TX_CTL(pipe));
1115 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1116 }
1117
1118 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 u32 val;
1122 bool cur_state;
1123
1124 val = I915_READ(FDI_RX_CTL(pipe));
1125 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1126 I915_STATE_WARN(cur_state != state,
1127 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1128 onoff(state), onoff(cur_state));
1129 }
1130
1131 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1132 {
1133 i915_reg_t pp_reg;
1134 u32 val;
1135 enum pipe panel_pipe = PIPE_A;
1136 bool locked = true;
1137
1138 if (WARN_ON(HAS_DDI(dev_priv)))
1139 return;
1140
1141 if (HAS_PCH_SPLIT(dev_priv)) {
1142 u32 port_sel;
1143
1144 pp_reg = PP_CONTROL(0);
1145 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1146
1147 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1148 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1149 panel_pipe = PIPE_B;
1150 /* XXX: else fix for eDP */
1151 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1152 /* presumably write lock depends on pipe, not port select */
1153 pp_reg = PP_CONTROL(pipe);
1154 panel_pipe = pipe;
1155 } else {
1156 pp_reg = PP_CONTROL(0);
1157 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1158 panel_pipe = PIPE_B;
1159 }
1160
1161 val = I915_READ(pp_reg);
1162 if (!(val & PANEL_POWER_ON) ||
1163 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1164 locked = false;
1165
1166 I915_STATE_WARN(panel_pipe == pipe && locked,
1167 "panel assertion failure, pipe %c regs locked\n",
1168 pipe_name(pipe));
1169 }
1170
1171 static void assert_cursor(struct drm_i915_private *dev_priv,
1172 enum pipe pipe, bool state)
1173 {
1174 bool cur_state;
1175
1176 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1177 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1178 else
1179 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1180
1181 I915_STATE_WARN(cur_state != state,
1182 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1183 pipe_name(pipe), onoff(state), onoff(cur_state));
1184 }
1185 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1186 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1187
1188 void assert_pipe(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190 {
1191 bool cur_state;
1192 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1193 pipe);
1194 enum intel_display_power_domain power_domain;
1195
1196 /* we keep both pipes enabled on 830 */
1197 if (IS_I830(dev_priv))
1198 state = true;
1199
1200 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205 intel_display_power_put(dev_priv, power_domain);
1206 } else {
1207 cur_state = false;
1208 }
1209
1210 I915_STATE_WARN(cur_state != state,
1211 "pipe %c assertion failure (expected %s, current %s)\n",
1212 pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216 enum plane plane, bool state)
1217 {
1218 u32 val;
1219 bool cur_state;
1220
1221 val = I915_READ(DSPCNTR(plane));
1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "plane %c assertion failure (expected %s, current %s)\n",
1225 plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233 {
1234 int i;
1235
1236 /* Primary planes are fixed to pipes on gen4+ */
1237 if (INTEL_GEN(dev_priv) >= 4) {
1238 u32 val = I915_READ(DSPCNTR(pipe));
1239 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240 "plane %c assertion failure, should be disabled but not\n",
1241 plane_name(pipe));
1242 return;
1243 }
1244
1245 /* Need to check both planes against the pipe */
1246 for_each_pipe(dev_priv, i) {
1247 u32 val = I915_READ(DSPCNTR(i));
1248 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249 DISPPLANE_SEL_PIPE_SHIFT;
1250 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252 plane_name(i), pipe_name(pipe));
1253 }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
1258 {
1259 int sprite;
1260
1261 if (INTEL_GEN(dev_priv) >= 9) {
1262 for_each_sprite(dev_priv, pipe, sprite) {
1263 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266 sprite, pipe_name(pipe));
1267 }
1268 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269 for_each_sprite(dev_priv, pipe, sprite) {
1270 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271 I915_STATE_WARN(val & SP_ENABLE,
1272 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273 sprite_name(pipe, sprite), pipe_name(pipe));
1274 }
1275 } else if (INTEL_GEN(dev_priv) >= 7) {
1276 u32 val = I915_READ(SPRCTL(pipe));
1277 I915_STATE_WARN(val & SPRITE_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1281 u32 val = I915_READ(DVSCNTR(pipe));
1282 I915_STATE_WARN(val & DVS_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 plane_name(pipe), pipe_name(pipe));
1285 }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 u32 val;
1298 bool enabled;
1299
1300 val = I915_READ(PCH_TRANSCONF(pipe));
1301 enabled = !!(val & TRANS_ENABLE);
1302 I915_STATE_WARN(enabled,
1303 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304 pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310 if ((val & DP_PORT_EN) == 0)
1311 return false;
1312
1313 if (HAS_PCH_CPT(dev_priv)) {
1314 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else if (IS_CHERRYVIEW(dev_priv)) {
1318 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329 {
1330 if ((val & SDVO_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv)) {
1334 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335 return false;
1336 } else if (IS_CHERRYVIEW(dev_priv)) {
1337 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338 return false;
1339 } else {
1340 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341 return false;
1342 }
1343 return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1348 {
1349 if ((val & LVDS_PORT_EN) == 0)
1350 return false;
1351
1352 if (HAS_PCH_CPT(dev_priv)) {
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354 return false;
1355 } else {
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357 return false;
1358 }
1359 return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1366 return false;
1367 if (HAS_PCH_CPT(dev_priv)) {
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 return false;
1370 } else {
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372 return false;
1373 }
1374 return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe, i915_reg_t reg,
1379 u32 port_sel)
1380 {
1381 u32 val = I915_READ(reg);
1382 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384 i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387 && (val & DP_PIPEB_SELECT),
1388 "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, i915_reg_t reg)
1393 {
1394 u32 val = I915_READ(reg);
1395 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397 i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400 && (val & SDVO_PIPE_B_SELECT),
1401 "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
1406 {
1407 u32 val;
1408
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413 val = I915_READ(PCH_ADPA);
1414 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415 "PCH VGA enabled on transcoder %c, should be disabled\n",
1416 pipe_name(pipe));
1417
1418 val = I915_READ(PCH_LVDS);
1419 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421 pipe_name(pipe));
1422
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429 const struct intel_crtc_state *pipe_config)
1430 {
1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432 enum pipe pipe = crtc->pipe;
1433
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435 POSTING_READ(DPLL(pipe));
1436 udelay(150);
1437
1438 if (intel_wait_for_register(dev_priv,
1439 DPLL(pipe),
1440 DPLL_LOCK_VLV,
1441 DPLL_LOCK_VLV,
1442 1))
1443 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447 const struct intel_crtc_state *pipe_config)
1448 {
1449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450 enum pipe pipe = crtc->pipe;
1451
1452 assert_pipe_disabled(dev_priv, pipe);
1453
1454 /* PLL is protected by panel, make sure we can write it */
1455 assert_panel_unlocked(dev_priv, pipe);
1456
1457 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458 _vlv_enable_pll(crtc, pipe_config);
1459
1460 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461 POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466 const struct intel_crtc_state *pipe_config)
1467 {
1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469 enum pipe pipe = crtc->pipe;
1470 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471 u32 tmp;
1472
1473 mutex_lock(&dev_priv->sb_lock);
1474
1475 /* Enable back the 10bit clock to display controller */
1476 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477 tmp |= DPIO_DCLKP_EN;
1478 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480 mutex_unlock(&dev_priv->sb_lock);
1481
1482 /*
1483 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484 */
1485 udelay(1);
1486
1487 /* Enable PLL */
1488 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490 /* Check PLL is locked */
1491 if (intel_wait_for_register(dev_priv,
1492 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493 1))
1494 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498 const struct intel_crtc_state *pipe_config)
1499 {
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501 enum pipe pipe = crtc->pipe;
1502
1503 assert_pipe_disabled(dev_priv, pipe);
1504
1505 /* PLL is protected by panel, make sure we can write it */
1506 assert_panel_unlocked(dev_priv, pipe);
1507
1508 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509 _chv_enable_pll(crtc, pipe_config);
1510
1511 if (pipe != PIPE_A) {
1512 /*
1513 * WaPixelRepeatModeFixForC0:chv
1514 *
1515 * DPLLCMD is AWOL. Use chicken bits to propagate
1516 * the value from DPLLBMD to either pipe B or C.
1517 */
1518 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520 I915_WRITE(CBR4_VLV, 0);
1521 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523 /*
1524 * DPLLB VGA mode also seems to cause problems.
1525 * We should always have it disabled.
1526 */
1527 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528 } else {
1529 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530 POSTING_READ(DPLL_MD(pipe));
1531 }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536 struct intel_crtc *crtc;
1537 int count = 0;
1538
1539 for_each_intel_crtc(&dev_priv->drm, crtc) {
1540 count += crtc->base.state->active &&
1541 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542 }
1543
1544 return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 i915_reg_t reg = DPLL(crtc->pipe);
1551 u32 dpll = crtc->config->dpll_hw_state.dpll;
1552 int i;
1553
1554 assert_pipe_disabled(dev_priv, crtc->pipe);
1555
1556 /* PLL is protected by panel, make sure we can write it */
1557 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1558 assert_panel_unlocked(dev_priv, crtc->pipe);
1559
1560 /* Enable DVO 2x clock on both PLLs if necessary */
1561 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1562 /*
1563 * It appears to be important that we don't enable this
1564 * for the current pipe before otherwise configuring the
1565 * PLL. No idea how this should be handled if multiple
1566 * DVO outputs are enabled simultaneosly.
1567 */
1568 dpll |= DPLL_DVO_2X_MODE;
1569 I915_WRITE(DPLL(!crtc->pipe),
1570 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1571 }
1572
1573 /*
1574 * Apparently we need to have VGA mode enabled prior to changing
1575 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1576 * dividers, even though the register value does change.
1577 */
1578 I915_WRITE(reg, 0);
1579
1580 I915_WRITE(reg, dpll);
1581
1582 /* Wait for the clocks to stabilize. */
1583 POSTING_READ(reg);
1584 udelay(150);
1585
1586 if (INTEL_GEN(dev_priv) >= 4) {
1587 I915_WRITE(DPLL_MD(crtc->pipe),
1588 crtc->config->dpll_hw_state.dpll_md);
1589 } else {
1590 /* The pixel multiplier can only be updated once the
1591 * DPLL is enabled and the clocks are stable.
1592 *
1593 * So write it again.
1594 */
1595 I915_WRITE(reg, dpll);
1596 }
1597
1598 /* We do this three times for luck */
1599 for (i = 0; i < 3; i++) {
1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150); /* wait for warmup */
1603 }
1604 }
1605
1606 /**
1607 * i9xx_disable_pll - disable a PLL
1608 * @dev_priv: i915 private structure
1609 * @pipe: pipe PLL to disable
1610 *
1611 * Disable the PLL for @pipe, making sure the pipe is off first.
1612 *
1613 * Note! This is for pre-ILK only.
1614 */
1615 static void i9xx_disable_pll(struct intel_crtc *crtc)
1616 {
1617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1618 enum pipe pipe = crtc->pipe;
1619
1620 /* Disable DVO 2x clock on both PLLs if necessary */
1621 if (IS_I830(dev_priv) &&
1622 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1623 !intel_num_dvo_pipes(dev_priv)) {
1624 I915_WRITE(DPLL(PIPE_B),
1625 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1626 I915_WRITE(DPLL(PIPE_A),
1627 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1628 }
1629
1630 /* Don't disable pipe or pipe PLLs if needed */
1631 if (IS_I830(dev_priv))
1632 return;
1633
1634 /* Make sure the pipe isn't still relying on us */
1635 assert_pipe_disabled(dev_priv, pipe);
1636
1637 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1638 POSTING_READ(DPLL(pipe));
1639 }
1640
1641 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1642 {
1643 u32 val;
1644
1645 /* Make sure the pipe isn't still relying on us */
1646 assert_pipe_disabled(dev_priv, pipe);
1647
1648 val = DPLL_INTEGRATED_REF_CLK_VLV |
1649 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1650 if (pipe != PIPE_A)
1651 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1652
1653 I915_WRITE(DPLL(pipe), val);
1654 POSTING_READ(DPLL(pipe));
1655 }
1656
1657 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1658 {
1659 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1660 u32 val;
1661
1662 /* Make sure the pipe isn't still relying on us */
1663 assert_pipe_disabled(dev_priv, pipe);
1664
1665 val = DPLL_SSC_REF_CLK_CHV |
1666 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1667 if (pipe != PIPE_A)
1668 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1669
1670 I915_WRITE(DPLL(pipe), val);
1671 POSTING_READ(DPLL(pipe));
1672
1673 mutex_lock(&dev_priv->sb_lock);
1674
1675 /* Disable 10bit clock to display controller */
1676 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1677 val &= ~DPIO_DCLKP_EN;
1678 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1679
1680 mutex_unlock(&dev_priv->sb_lock);
1681 }
1682
1683 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1684 struct intel_digital_port *dport,
1685 unsigned int expected_mask)
1686 {
1687 u32 port_mask;
1688 i915_reg_t dpll_reg;
1689
1690 switch (dport->port) {
1691 case PORT_B:
1692 port_mask = DPLL_PORTB_READY_MASK;
1693 dpll_reg = DPLL(0);
1694 break;
1695 case PORT_C:
1696 port_mask = DPLL_PORTC_READY_MASK;
1697 dpll_reg = DPLL(0);
1698 expected_mask <<= 4;
1699 break;
1700 case PORT_D:
1701 port_mask = DPLL_PORTD_READY_MASK;
1702 dpll_reg = DPIO_PHY_STATUS;
1703 break;
1704 default:
1705 BUG();
1706 }
1707
1708 if (intel_wait_for_register(dev_priv,
1709 dpll_reg, port_mask, expected_mask,
1710 1000))
1711 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1712 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1713 }
1714
1715 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1716 enum pipe pipe)
1717 {
1718 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1719 pipe);
1720 i915_reg_t reg;
1721 uint32_t val, pipeconf_val;
1722
1723 /* Make sure PCH DPLL is enabled */
1724 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1725
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv, pipe);
1728 assert_fdi_rx_enabled(dev_priv, pipe);
1729
1730 if (HAS_PCH_CPT(dev_priv)) {
1731 /* Workaround: Set the timing override bit before enabling the
1732 * pch transcoder. */
1733 reg = TRANS_CHICKEN2(pipe);
1734 val = I915_READ(reg);
1735 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1736 I915_WRITE(reg, val);
1737 }
1738
1739 reg = PCH_TRANSCONF(pipe);
1740 val = I915_READ(reg);
1741 pipeconf_val = I915_READ(PIPECONF(pipe));
1742
1743 if (HAS_PCH_IBX(dev_priv)) {
1744 /*
1745 * Make the BPC in transcoder be consistent with
1746 * that in pipeconf reg. For HDMI we must use 8bpc
1747 * here for both 8bpc and 12bpc.
1748 */
1749 val &= ~PIPECONF_BPC_MASK;
1750 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1751 val |= PIPECONF_8BPC;
1752 else
1753 val |= pipeconf_val & PIPECONF_BPC_MASK;
1754 }
1755
1756 val &= ~TRANS_INTERLACE_MASK;
1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1758 if (HAS_PCH_IBX(dev_priv) &&
1759 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1760 val |= TRANS_LEGACY_INTERLACED_ILK;
1761 else
1762 val |= TRANS_INTERLACED;
1763 else
1764 val |= TRANS_PROGRESSIVE;
1765
1766 I915_WRITE(reg, val | TRANS_ENABLE);
1767 if (intel_wait_for_register(dev_priv,
1768 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1769 100))
1770 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1771 }
1772
1773 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1774 enum transcoder cpu_transcoder)
1775 {
1776 u32 val, pipeconf_val;
1777
1778 /* FDI must be feeding us bits for PCH ports */
1779 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1780 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1781
1782 /* Workaround: set timing override bit. */
1783 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1784 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1785 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1786
1787 val = TRANS_ENABLE;
1788 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1789
1790 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1791 PIPECONF_INTERLACED_ILK)
1792 val |= TRANS_INTERLACED;
1793 else
1794 val |= TRANS_PROGRESSIVE;
1795
1796 I915_WRITE(LPT_TRANSCONF, val);
1797 if (intel_wait_for_register(dev_priv,
1798 LPT_TRANSCONF,
1799 TRANS_STATE_ENABLE,
1800 TRANS_STATE_ENABLE,
1801 100))
1802 DRM_ERROR("Failed to enable PCH transcoder\n");
1803 }
1804
1805 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807 {
1808 i915_reg_t reg;
1809 uint32_t val;
1810
1811 /* FDI relies on the transcoder */
1812 assert_fdi_tx_disabled(dev_priv, pipe);
1813 assert_fdi_rx_disabled(dev_priv, pipe);
1814
1815 /* Ports must be off as well */
1816 assert_pch_ports_disabled(dev_priv, pipe);
1817
1818 reg = PCH_TRANSCONF(pipe);
1819 val = I915_READ(reg);
1820 val &= ~TRANS_ENABLE;
1821 I915_WRITE(reg, val);
1822 /* wait for PCH transcoder off, transcoder state */
1823 if (intel_wait_for_register(dev_priv,
1824 reg, TRANS_STATE_ENABLE, 0,
1825 50))
1826 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1827
1828 if (HAS_PCH_CPT(dev_priv)) {
1829 /* Workaround: Clear the timing override chicken bit again. */
1830 reg = TRANS_CHICKEN2(pipe);
1831 val = I915_READ(reg);
1832 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1833 I915_WRITE(reg, val);
1834 }
1835 }
1836
1837 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1838 {
1839 u32 val;
1840
1841 val = I915_READ(LPT_TRANSCONF);
1842 val &= ~TRANS_ENABLE;
1843 I915_WRITE(LPT_TRANSCONF, val);
1844 /* wait for PCH transcoder off, transcoder state */
1845 if (intel_wait_for_register(dev_priv,
1846 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1847 50))
1848 DRM_ERROR("Failed to disable PCH transcoder\n");
1849
1850 /* Workaround: clear timing override bit. */
1851 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1852 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1853 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1854 }
1855
1856 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1857 {
1858 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1859
1860 WARN_ON(!crtc->config->has_pch_encoder);
1861
1862 if (HAS_PCH_LPT(dev_priv))
1863 return TRANSCODER_A;
1864 else
1865 return (enum transcoder) crtc->pipe;
1866 }
1867
1868 /**
1869 * intel_enable_pipe - enable a pipe, asserting requirements
1870 * @crtc: crtc responsible for the pipe
1871 *
1872 * Enable @crtc's pipe, making sure that various hardware specific requirements
1873 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1874 */
1875 static void intel_enable_pipe(struct intel_crtc *crtc)
1876 {
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = to_i915(dev);
1879 enum pipe pipe = crtc->pipe;
1880 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1881 i915_reg_t reg;
1882 u32 val;
1883
1884 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1885
1886 assert_planes_disabled(dev_priv, pipe);
1887 assert_cursor_disabled(dev_priv, pipe);
1888 assert_sprites_disabled(dev_priv, pipe);
1889
1890 /*
1891 * A pipe without a PLL won't actually be able to drive bits from
1892 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1893 * need the check.
1894 */
1895 if (HAS_GMCH_DISPLAY(dev_priv)) {
1896 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1897 assert_dsi_pll_enabled(dev_priv);
1898 else
1899 assert_pll_enabled(dev_priv, pipe);
1900 } else {
1901 if (crtc->config->has_pch_encoder) {
1902 /* if driving the PCH, we need FDI enabled */
1903 assert_fdi_rx_pll_enabled(dev_priv,
1904 (enum pipe) intel_crtc_pch_transcoder(crtc));
1905 assert_fdi_tx_pll_enabled(dev_priv,
1906 (enum pipe) cpu_transcoder);
1907 }
1908 /* FIXME: assert CPU port conditions for SNB+ */
1909 }
1910
1911 reg = PIPECONF(cpu_transcoder);
1912 val = I915_READ(reg);
1913 if (val & PIPECONF_ENABLE) {
1914 /* we keep both pipes enabled on 830 */
1915 WARN_ON(!IS_I830(dev_priv));
1916 return;
1917 }
1918
1919 I915_WRITE(reg, val | PIPECONF_ENABLE);
1920 POSTING_READ(reg);
1921
1922 /*
1923 * Until the pipe starts DSL will read as 0, which would cause
1924 * an apparent vblank timestamp jump, which messes up also the
1925 * frame count when it's derived from the timestamps. So let's
1926 * wait for the pipe to start properly before we call
1927 * drm_crtc_vblank_on()
1928 */
1929 if (dev->max_vblank_count == 0 &&
1930 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1931 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1932 }
1933
1934 /**
1935 * intel_disable_pipe - disable a pipe, asserting requirements
1936 * @crtc: crtc whose pipes is to be disabled
1937 *
1938 * Disable the pipe of @crtc, making sure that various hardware
1939 * specific requirements are met, if applicable, e.g. plane
1940 * disabled, panel fitter off, etc.
1941 *
1942 * Will wait until the pipe has shut down before returning.
1943 */
1944 static void intel_disable_pipe(struct intel_crtc *crtc)
1945 {
1946 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1947 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1948 enum pipe pipe = crtc->pipe;
1949 i915_reg_t reg;
1950 u32 val;
1951
1952 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1953
1954 /*
1955 * Make sure planes won't keep trying to pump pixels to us,
1956 * or we might hang the display.
1957 */
1958 assert_planes_disabled(dev_priv, pipe);
1959 assert_cursor_disabled(dev_priv, pipe);
1960 assert_sprites_disabled(dev_priv, pipe);
1961
1962 reg = PIPECONF(cpu_transcoder);
1963 val = I915_READ(reg);
1964 if ((val & PIPECONF_ENABLE) == 0)
1965 return;
1966
1967 /*
1968 * Double wide has implications for planes
1969 * so best keep it disabled when not needed.
1970 */
1971 if (crtc->config->double_wide)
1972 val &= ~PIPECONF_DOUBLE_WIDE;
1973
1974 /* Don't disable pipe or pipe PLLs if needed */
1975 if (!IS_I830(dev_priv))
1976 val &= ~PIPECONF_ENABLE;
1977
1978 I915_WRITE(reg, val);
1979 if ((val & PIPECONF_ENABLE) == 0)
1980 intel_wait_for_pipe_off(crtc);
1981 }
1982
1983 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1984 {
1985 return IS_GEN2(dev_priv) ? 2048 : 4096;
1986 }
1987
1988 static unsigned int
1989 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1990 {
1991 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1992 unsigned int cpp = fb->format->cpp[plane];
1993
1994 switch (fb->modifier) {
1995 case DRM_FORMAT_MOD_LINEAR:
1996 return cpp;
1997 case I915_FORMAT_MOD_X_TILED:
1998 if (IS_GEN2(dev_priv))
1999 return 128;
2000 else
2001 return 512;
2002 case I915_FORMAT_MOD_Y_TILED:
2003 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2004 return 128;
2005 else
2006 return 512;
2007 case I915_FORMAT_MOD_Yf_TILED:
2008 switch (cpp) {
2009 case 1:
2010 return 64;
2011 case 2:
2012 case 4:
2013 return 128;
2014 case 8:
2015 case 16:
2016 return 256;
2017 default:
2018 MISSING_CASE(cpp);
2019 return cpp;
2020 }
2021 break;
2022 default:
2023 MISSING_CASE(fb->modifier);
2024 return cpp;
2025 }
2026 }
2027
2028 static unsigned int
2029 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2030 {
2031 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2032 return 1;
2033 else
2034 return intel_tile_size(to_i915(fb->dev)) /
2035 intel_tile_width_bytes(fb, plane);
2036 }
2037
2038 /* Return the tile dimensions in pixel units */
2039 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2040 unsigned int *tile_width,
2041 unsigned int *tile_height)
2042 {
2043 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2044 unsigned int cpp = fb->format->cpp[plane];
2045
2046 *tile_width = tile_width_bytes / cpp;
2047 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2048 }
2049
2050 unsigned int
2051 intel_fb_align_height(const struct drm_framebuffer *fb,
2052 int plane, unsigned int height)
2053 {
2054 unsigned int tile_height = intel_tile_height(fb, plane);
2055
2056 return ALIGN(height, tile_height);
2057 }
2058
2059 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2060 {
2061 unsigned int size = 0;
2062 int i;
2063
2064 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2065 size += rot_info->plane[i].width * rot_info->plane[i].height;
2066
2067 return size;
2068 }
2069
2070 static void
2071 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2072 const struct drm_framebuffer *fb,
2073 unsigned int rotation)
2074 {
2075 view->type = I915_GGTT_VIEW_NORMAL;
2076 if (drm_rotation_90_or_270(rotation)) {
2077 view->type = I915_GGTT_VIEW_ROTATED;
2078 view->rotated = to_intel_framebuffer(fb)->rot_info;
2079 }
2080 }
2081
2082 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2083 {
2084 if (IS_I830(dev_priv))
2085 return 16 * 1024;
2086 else if (IS_I85X(dev_priv))
2087 return 256;
2088 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2089 return 32;
2090 else
2091 return 4 * 1024;
2092 }
2093
2094 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2095 {
2096 if (INTEL_INFO(dev_priv)->gen >= 9)
2097 return 256 * 1024;
2098 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2099 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2100 return 128 * 1024;
2101 else if (INTEL_INFO(dev_priv)->gen >= 4)
2102 return 4 * 1024;
2103 else
2104 return 0;
2105 }
2106
2107 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2108 int plane)
2109 {
2110 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2111
2112 /* AUX_DIST needs only 4K alignment */
2113 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2114 return 4096;
2115
2116 switch (fb->modifier) {
2117 case DRM_FORMAT_MOD_LINEAR:
2118 return intel_linear_alignment(dev_priv);
2119 case I915_FORMAT_MOD_X_TILED:
2120 if (INTEL_GEN(dev_priv) >= 9)
2121 return 256 * 1024;
2122 return 0;
2123 case I915_FORMAT_MOD_Y_TILED:
2124 case I915_FORMAT_MOD_Yf_TILED:
2125 return 1 * 1024 * 1024;
2126 default:
2127 MISSING_CASE(fb->modifier);
2128 return 0;
2129 }
2130 }
2131
2132 struct i915_vma *
2133 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2134 {
2135 struct drm_device *dev = fb->dev;
2136 struct drm_i915_private *dev_priv = to_i915(dev);
2137 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2138 struct i915_ggtt_view view;
2139 struct i915_vma *vma;
2140 u32 alignment;
2141
2142 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2143
2144 alignment = intel_surf_alignment(fb, 0);
2145
2146 intel_fill_fb_ggtt_view(&view, fb, rotation);
2147
2148 /* Note that the w/a also requires 64 PTE of padding following the
2149 * bo. We currently fill all unused PTE with the shadow page and so
2150 * we should always have valid PTE following the scanout preventing
2151 * the VT-d warning.
2152 */
2153 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2154 alignment = 256 * 1024;
2155
2156 /*
2157 * Global gtt pte registers are special registers which actually forward
2158 * writes to a chunk of system memory. Which means that there is no risk
2159 * that the register values disappear as soon as we call
2160 * intel_runtime_pm_put(), so it is correct to wrap only the
2161 * pin/unpin/fence and not more.
2162 */
2163 intel_runtime_pm_get(dev_priv);
2164
2165 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2166 if (IS_ERR(vma))
2167 goto err;
2168
2169 if (i915_vma_is_map_and_fenceable(vma)) {
2170 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2171 * fence, whereas 965+ only requires a fence if using
2172 * framebuffer compression. For simplicity, we always, when
2173 * possible, install a fence as the cost is not that onerous.
2174 *
2175 * If we fail to fence the tiled scanout, then either the
2176 * modeset will reject the change (which is highly unlikely as
2177 * the affected systems, all but one, do not have unmappable
2178 * space) or we will not be able to enable full powersaving
2179 * techniques (also likely not to apply due to various limits
2180 * FBC and the like impose on the size of the buffer, which
2181 * presumably we violated anyway with this unmappable buffer).
2182 * Anyway, it is presumably better to stumble onwards with
2183 * something and try to run the system in a "less than optimal"
2184 * mode that matches the user configuration.
2185 */
2186 if (i915_vma_get_fence(vma) == 0)
2187 i915_vma_pin_fence(vma);
2188 }
2189
2190 i915_vma_get(vma);
2191 err:
2192 intel_runtime_pm_put(dev_priv);
2193 return vma;
2194 }
2195
2196 void intel_unpin_fb_vma(struct i915_vma *vma)
2197 {
2198 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2199
2200 i915_vma_unpin_fence(vma);
2201 i915_gem_object_unpin_from_display_plane(vma);
2202 i915_vma_put(vma);
2203 }
2204
2205 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2206 unsigned int rotation)
2207 {
2208 if (drm_rotation_90_or_270(rotation))
2209 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2210 else
2211 return fb->pitches[plane];
2212 }
2213
2214 /*
2215 * Convert the x/y offsets into a linear offset.
2216 * Only valid with 0/180 degree rotation, which is fine since linear
2217 * offset is only used with linear buffers on pre-hsw and tiled buffers
2218 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2219 */
2220 u32 intel_fb_xy_to_linear(int x, int y,
2221 const struct intel_plane_state *state,
2222 int plane)
2223 {
2224 const struct drm_framebuffer *fb = state->base.fb;
2225 unsigned int cpp = fb->format->cpp[plane];
2226 unsigned int pitch = fb->pitches[plane];
2227
2228 return y * pitch + x * cpp;
2229 }
2230
2231 /*
2232 * Add the x/y offsets derived from fb->offsets[] to the user
2233 * specified plane src x/y offsets. The resulting x/y offsets
2234 * specify the start of scanout from the beginning of the gtt mapping.
2235 */
2236 void intel_add_fb_offsets(int *x, int *y,
2237 const struct intel_plane_state *state,
2238 int plane)
2239
2240 {
2241 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2242 unsigned int rotation = state->base.rotation;
2243
2244 if (drm_rotation_90_or_270(rotation)) {
2245 *x += intel_fb->rotated[plane].x;
2246 *y += intel_fb->rotated[plane].y;
2247 } else {
2248 *x += intel_fb->normal[plane].x;
2249 *y += intel_fb->normal[plane].y;
2250 }
2251 }
2252
2253 /*
2254 * Input tile dimensions and pitch must already be
2255 * rotated to match x and y, and in pixel units.
2256 */
2257 static u32 _intel_adjust_tile_offset(int *x, int *y,
2258 unsigned int tile_width,
2259 unsigned int tile_height,
2260 unsigned int tile_size,
2261 unsigned int pitch_tiles,
2262 u32 old_offset,
2263 u32 new_offset)
2264 {
2265 unsigned int pitch_pixels = pitch_tiles * tile_width;
2266 unsigned int tiles;
2267
2268 WARN_ON(old_offset & (tile_size - 1));
2269 WARN_ON(new_offset & (tile_size - 1));
2270 WARN_ON(new_offset > old_offset);
2271
2272 tiles = (old_offset - new_offset) / tile_size;
2273
2274 *y += tiles / pitch_tiles * tile_height;
2275 *x += tiles % pitch_tiles * tile_width;
2276
2277 /* minimize x in case it got needlessly big */
2278 *y += *x / pitch_pixels * tile_height;
2279 *x %= pitch_pixels;
2280
2281 return new_offset;
2282 }
2283
2284 /*
2285 * Adjust the tile offset by moving the difference into
2286 * the x/y offsets.
2287 */
2288 static u32 intel_adjust_tile_offset(int *x, int *y,
2289 const struct intel_plane_state *state, int plane,
2290 u32 old_offset, u32 new_offset)
2291 {
2292 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2293 const struct drm_framebuffer *fb = state->base.fb;
2294 unsigned int cpp = fb->format->cpp[plane];
2295 unsigned int rotation = state->base.rotation;
2296 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2297
2298 WARN_ON(new_offset > old_offset);
2299
2300 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2301 unsigned int tile_size, tile_width, tile_height;
2302 unsigned int pitch_tiles;
2303
2304 tile_size = intel_tile_size(dev_priv);
2305 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2306
2307 if (drm_rotation_90_or_270(rotation)) {
2308 pitch_tiles = pitch / tile_height;
2309 swap(tile_width, tile_height);
2310 } else {
2311 pitch_tiles = pitch / (tile_width * cpp);
2312 }
2313
2314 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2315 tile_size, pitch_tiles,
2316 old_offset, new_offset);
2317 } else {
2318 old_offset += *y * pitch + *x * cpp;
2319
2320 *y = (old_offset - new_offset) / pitch;
2321 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2322 }
2323
2324 return new_offset;
2325 }
2326
2327 /*
2328 * Computes the linear offset to the base tile and adjusts
2329 * x, y. bytes per pixel is assumed to be a power-of-two.
2330 *
2331 * In the 90/270 rotated case, x and y are assumed
2332 * to be already rotated to match the rotated GTT view, and
2333 * pitch is the tile_height aligned framebuffer height.
2334 *
2335 * This function is used when computing the derived information
2336 * under intel_framebuffer, so using any of that information
2337 * here is not allowed. Anything under drm_framebuffer can be
2338 * used. This is why the user has to pass in the pitch since it
2339 * is specified in the rotated orientation.
2340 */
2341 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2342 int *x, int *y,
2343 const struct drm_framebuffer *fb, int plane,
2344 unsigned int pitch,
2345 unsigned int rotation,
2346 u32 alignment)
2347 {
2348 uint64_t fb_modifier = fb->modifier;
2349 unsigned int cpp = fb->format->cpp[plane];
2350 u32 offset, offset_aligned;
2351
2352 if (alignment)
2353 alignment--;
2354
2355 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2356 unsigned int tile_size, tile_width, tile_height;
2357 unsigned int tile_rows, tiles, pitch_tiles;
2358
2359 tile_size = intel_tile_size(dev_priv);
2360 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2361
2362 if (drm_rotation_90_or_270(rotation)) {
2363 pitch_tiles = pitch / tile_height;
2364 swap(tile_width, tile_height);
2365 } else {
2366 pitch_tiles = pitch / (tile_width * cpp);
2367 }
2368
2369 tile_rows = *y / tile_height;
2370 *y %= tile_height;
2371
2372 tiles = *x / tile_width;
2373 *x %= tile_width;
2374
2375 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2376 offset_aligned = offset & ~alignment;
2377
2378 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2379 tile_size, pitch_tiles,
2380 offset, offset_aligned);
2381 } else {
2382 offset = *y * pitch + *x * cpp;
2383 offset_aligned = offset & ~alignment;
2384
2385 *y = (offset & alignment) / pitch;
2386 *x = ((offset & alignment) - *y * pitch) / cpp;
2387 }
2388
2389 return offset_aligned;
2390 }
2391
2392 u32 intel_compute_tile_offset(int *x, int *y,
2393 const struct intel_plane_state *state,
2394 int plane)
2395 {
2396 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2397 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2398 const struct drm_framebuffer *fb = state->base.fb;
2399 unsigned int rotation = state->base.rotation;
2400 int pitch = intel_fb_pitch(fb, plane, rotation);
2401 u32 alignment;
2402
2403 if (intel_plane->id == PLANE_CURSOR)
2404 alignment = intel_cursor_alignment(dev_priv);
2405 else
2406 alignment = intel_surf_alignment(fb, plane);
2407
2408 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2409 rotation, alignment);
2410 }
2411
2412 /* Convert the fb->offset[] linear offset into x/y offsets */
2413 static void intel_fb_offset_to_xy(int *x, int *y,
2414 const struct drm_framebuffer *fb, int plane)
2415 {
2416 unsigned int cpp = fb->format->cpp[plane];
2417 unsigned int pitch = fb->pitches[plane];
2418 u32 linear_offset = fb->offsets[plane];
2419
2420 *y = linear_offset / pitch;
2421 *x = linear_offset % pitch / cpp;
2422 }
2423
2424 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2425 {
2426 switch (fb_modifier) {
2427 case I915_FORMAT_MOD_X_TILED:
2428 return I915_TILING_X;
2429 case I915_FORMAT_MOD_Y_TILED:
2430 return I915_TILING_Y;
2431 default:
2432 return I915_TILING_NONE;
2433 }
2434 }
2435
2436 static int
2437 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2438 struct drm_framebuffer *fb)
2439 {
2440 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2441 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2442 u32 gtt_offset_rotated = 0;
2443 unsigned int max_size = 0;
2444 int i, num_planes = fb->format->num_planes;
2445 unsigned int tile_size = intel_tile_size(dev_priv);
2446
2447 for (i = 0; i < num_planes; i++) {
2448 unsigned int width, height;
2449 unsigned int cpp, size;
2450 u32 offset;
2451 int x, y;
2452
2453 cpp = fb->format->cpp[i];
2454 width = drm_framebuffer_plane_width(fb->width, fb, i);
2455 height = drm_framebuffer_plane_height(fb->height, fb, i);
2456
2457 intel_fb_offset_to_xy(&x, &y, fb, i);
2458
2459 /*
2460 * The fence (if used) is aligned to the start of the object
2461 * so having the framebuffer wrap around across the edge of the
2462 * fenced region doesn't really work. We have no API to configure
2463 * the fence start offset within the object (nor could we probably
2464 * on gen2/3). So it's just easier if we just require that the
2465 * fb layout agrees with the fence layout. We already check that the
2466 * fb stride matches the fence stride elsewhere.
2467 */
2468 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2469 (x + width) * cpp > fb->pitches[i]) {
2470 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2471 i, fb->offsets[i]);
2472 return -EINVAL;
2473 }
2474
2475 /*
2476 * First pixel of the framebuffer from
2477 * the start of the normal gtt mapping.
2478 */
2479 intel_fb->normal[i].x = x;
2480 intel_fb->normal[i].y = y;
2481
2482 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2483 fb, i, fb->pitches[i],
2484 DRM_MODE_ROTATE_0, tile_size);
2485 offset /= tile_size;
2486
2487 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2488 unsigned int tile_width, tile_height;
2489 unsigned int pitch_tiles;
2490 struct drm_rect r;
2491
2492 intel_tile_dims(fb, i, &tile_width, &tile_height);
2493
2494 rot_info->plane[i].offset = offset;
2495 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2496 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2497 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2498
2499 intel_fb->rotated[i].pitch =
2500 rot_info->plane[i].height * tile_height;
2501
2502 /* how many tiles does this plane need */
2503 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2504 /*
2505 * If the plane isn't horizontally tile aligned,
2506 * we need one more tile.
2507 */
2508 if (x != 0)
2509 size++;
2510
2511 /* rotate the x/y offsets to match the GTT view */
2512 r.x1 = x;
2513 r.y1 = y;
2514 r.x2 = x + width;
2515 r.y2 = y + height;
2516 drm_rect_rotate(&r,
2517 rot_info->plane[i].width * tile_width,
2518 rot_info->plane[i].height * tile_height,
2519 DRM_MODE_ROTATE_270);
2520 x = r.x1;
2521 y = r.y1;
2522
2523 /* rotate the tile dimensions to match the GTT view */
2524 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2525 swap(tile_width, tile_height);
2526
2527 /*
2528 * We only keep the x/y offsets, so push all of the
2529 * gtt offset into the x/y offsets.
2530 */
2531 _intel_adjust_tile_offset(&x, &y,
2532 tile_width, tile_height,
2533 tile_size, pitch_tiles,
2534 gtt_offset_rotated * tile_size, 0);
2535
2536 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2537
2538 /*
2539 * First pixel of the framebuffer from
2540 * the start of the rotated gtt mapping.
2541 */
2542 intel_fb->rotated[i].x = x;
2543 intel_fb->rotated[i].y = y;
2544 } else {
2545 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2546 x * cpp, tile_size);
2547 }
2548
2549 /* how many tiles in total needed in the bo */
2550 max_size = max(max_size, offset + size);
2551 }
2552
2553 if (max_size * tile_size > intel_fb->obj->base.size) {
2554 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2555 max_size * tile_size, intel_fb->obj->base.size);
2556 return -EINVAL;
2557 }
2558
2559 return 0;
2560 }
2561
2562 static int i9xx_format_to_fourcc(int format)
2563 {
2564 switch (format) {
2565 case DISPPLANE_8BPP:
2566 return DRM_FORMAT_C8;
2567 case DISPPLANE_BGRX555:
2568 return DRM_FORMAT_XRGB1555;
2569 case DISPPLANE_BGRX565:
2570 return DRM_FORMAT_RGB565;
2571 default:
2572 case DISPPLANE_BGRX888:
2573 return DRM_FORMAT_XRGB8888;
2574 case DISPPLANE_RGBX888:
2575 return DRM_FORMAT_XBGR8888;
2576 case DISPPLANE_BGRX101010:
2577 return DRM_FORMAT_XRGB2101010;
2578 case DISPPLANE_RGBX101010:
2579 return DRM_FORMAT_XBGR2101010;
2580 }
2581 }
2582
2583 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2584 {
2585 switch (format) {
2586 case PLANE_CTL_FORMAT_RGB_565:
2587 return DRM_FORMAT_RGB565;
2588 default:
2589 case PLANE_CTL_FORMAT_XRGB_8888:
2590 if (rgb_order) {
2591 if (alpha)
2592 return DRM_FORMAT_ABGR8888;
2593 else
2594 return DRM_FORMAT_XBGR8888;
2595 } else {
2596 if (alpha)
2597 return DRM_FORMAT_ARGB8888;
2598 else
2599 return DRM_FORMAT_XRGB8888;
2600 }
2601 case PLANE_CTL_FORMAT_XRGB_2101010:
2602 if (rgb_order)
2603 return DRM_FORMAT_XBGR2101010;
2604 else
2605 return DRM_FORMAT_XRGB2101010;
2606 }
2607 }
2608
2609 static bool
2610 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2611 struct intel_initial_plane_config *plane_config)
2612 {
2613 struct drm_device *dev = crtc->base.dev;
2614 struct drm_i915_private *dev_priv = to_i915(dev);
2615 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2616 struct drm_i915_gem_object *obj = NULL;
2617 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2618 struct drm_framebuffer *fb = &plane_config->fb->base;
2619 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2620 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2621 PAGE_SIZE);
2622
2623 size_aligned -= base_aligned;
2624
2625 if (plane_config->size == 0)
2626 return false;
2627
2628 /* If the FB is too big, just don't use it since fbdev is not very
2629 * important and we should probably use that space with FBC or other
2630 * features. */
2631 if (size_aligned * 2 > ggtt->stolen_usable_size)
2632 return false;
2633
2634 mutex_lock(&dev->struct_mutex);
2635 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2636 base_aligned,
2637 base_aligned,
2638 size_aligned);
2639 mutex_unlock(&dev->struct_mutex);
2640 if (!obj)
2641 return false;
2642
2643 if (plane_config->tiling == I915_TILING_X)
2644 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2645
2646 mode_cmd.pixel_format = fb->format->format;
2647 mode_cmd.width = fb->width;
2648 mode_cmd.height = fb->height;
2649 mode_cmd.pitches[0] = fb->pitches[0];
2650 mode_cmd.modifier[0] = fb->modifier;
2651 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2652
2653 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2654 DRM_DEBUG_KMS("intel fb init failed\n");
2655 goto out_unref_obj;
2656 }
2657
2658
2659 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2660 return true;
2661
2662 out_unref_obj:
2663 i915_gem_object_put(obj);
2664 return false;
2665 }
2666
2667 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2668 static void
2669 update_state_fb(struct drm_plane *plane)
2670 {
2671 if (plane->fb == plane->state->fb)
2672 return;
2673
2674 if (plane->state->fb)
2675 drm_framebuffer_unreference(plane->state->fb);
2676 plane->state->fb = plane->fb;
2677 if (plane->state->fb)
2678 drm_framebuffer_reference(plane->state->fb);
2679 }
2680
2681 static void
2682 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2683 struct intel_plane_state *plane_state,
2684 bool visible)
2685 {
2686 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2687
2688 plane_state->base.visible = visible;
2689
2690 /* FIXME pre-g4x don't work like this */
2691 if (visible) {
2692 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2693 crtc_state->active_planes |= BIT(plane->id);
2694 } else {
2695 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2696 crtc_state->active_planes &= ~BIT(plane->id);
2697 }
2698
2699 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2700 crtc_state->base.crtc->name,
2701 crtc_state->active_planes);
2702 }
2703
2704 static void
2705 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2706 struct intel_initial_plane_config *plane_config)
2707 {
2708 struct drm_device *dev = intel_crtc->base.dev;
2709 struct drm_i915_private *dev_priv = to_i915(dev);
2710 struct drm_crtc *c;
2711 struct drm_i915_gem_object *obj;
2712 struct drm_plane *primary = intel_crtc->base.primary;
2713 struct drm_plane_state *plane_state = primary->state;
2714 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2715 struct intel_plane *intel_plane = to_intel_plane(primary);
2716 struct intel_plane_state *intel_state =
2717 to_intel_plane_state(plane_state);
2718 struct drm_framebuffer *fb;
2719
2720 if (!plane_config->fb)
2721 return;
2722
2723 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2724 fb = &plane_config->fb->base;
2725 goto valid_fb;
2726 }
2727
2728 kfree(plane_config->fb);
2729
2730 /*
2731 * Failed to alloc the obj, check to see if we should share
2732 * an fb with another CRTC instead
2733 */
2734 for_each_crtc(dev, c) {
2735 struct intel_plane_state *state;
2736
2737 if (c == &intel_crtc->base)
2738 continue;
2739
2740 if (!to_intel_crtc(c)->active)
2741 continue;
2742
2743 state = to_intel_plane_state(c->primary->state);
2744 if (!state->vma)
2745 continue;
2746
2747 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2748 fb = c->primary->fb;
2749 drm_framebuffer_reference(fb);
2750 goto valid_fb;
2751 }
2752 }
2753
2754 /*
2755 * We've failed to reconstruct the BIOS FB. Current display state
2756 * indicates that the primary plane is visible, but has a NULL FB,
2757 * which will lead to problems later if we don't fix it up. The
2758 * simplest solution is to just disable the primary plane now and
2759 * pretend the BIOS never had it enabled.
2760 */
2761 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2762 to_intel_plane_state(plane_state),
2763 false);
2764 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2765 trace_intel_disable_plane(primary, intel_crtc);
2766 intel_plane->disable_plane(intel_plane, intel_crtc);
2767
2768 return;
2769
2770 valid_fb:
2771 mutex_lock(&dev->struct_mutex);
2772 intel_state->vma =
2773 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2774 mutex_unlock(&dev->struct_mutex);
2775 if (IS_ERR(intel_state->vma)) {
2776 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2777 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2778
2779 intel_state->vma = NULL;
2780 drm_framebuffer_unreference(fb);
2781 return;
2782 }
2783
2784 plane_state->src_x = 0;
2785 plane_state->src_y = 0;
2786 plane_state->src_w = fb->width << 16;
2787 plane_state->src_h = fb->height << 16;
2788
2789 plane_state->crtc_x = 0;
2790 plane_state->crtc_y = 0;
2791 plane_state->crtc_w = fb->width;
2792 plane_state->crtc_h = fb->height;
2793
2794 intel_state->base.src = drm_plane_state_src(plane_state);
2795 intel_state->base.dst = drm_plane_state_dest(plane_state);
2796
2797 obj = intel_fb_obj(fb);
2798 if (i915_gem_object_is_tiled(obj))
2799 dev_priv->preserve_bios_swizzle = true;
2800
2801 drm_framebuffer_reference(fb);
2802 primary->fb = primary->state->fb = fb;
2803 primary->crtc = primary->state->crtc = &intel_crtc->base;
2804
2805 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2806 to_intel_plane_state(plane_state),
2807 true);
2808
2809 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2810 &obj->frontbuffer_bits);
2811 }
2812
2813 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2814 unsigned int rotation)
2815 {
2816 int cpp = fb->format->cpp[plane];
2817
2818 switch (fb->modifier) {
2819 case DRM_FORMAT_MOD_LINEAR:
2820 case I915_FORMAT_MOD_X_TILED:
2821 switch (cpp) {
2822 case 8:
2823 return 4096;
2824 case 4:
2825 case 2:
2826 case 1:
2827 return 8192;
2828 default:
2829 MISSING_CASE(cpp);
2830 break;
2831 }
2832 break;
2833 case I915_FORMAT_MOD_Y_TILED:
2834 case I915_FORMAT_MOD_Yf_TILED:
2835 switch (cpp) {
2836 case 8:
2837 return 2048;
2838 case 4:
2839 return 4096;
2840 case 2:
2841 case 1:
2842 return 8192;
2843 default:
2844 MISSING_CASE(cpp);
2845 break;
2846 }
2847 break;
2848 default:
2849 MISSING_CASE(fb->modifier);
2850 }
2851
2852 return 2048;
2853 }
2854
2855 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2856 {
2857 const struct drm_framebuffer *fb = plane_state->base.fb;
2858 unsigned int rotation = plane_state->base.rotation;
2859 int x = plane_state->base.src.x1 >> 16;
2860 int y = plane_state->base.src.y1 >> 16;
2861 int w = drm_rect_width(&plane_state->base.src) >> 16;
2862 int h = drm_rect_height(&plane_state->base.src) >> 16;
2863 int max_width = skl_max_plane_width(fb, 0, rotation);
2864 int max_height = 4096;
2865 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2866
2867 if (w > max_width || h > max_height) {
2868 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2869 w, h, max_width, max_height);
2870 return -EINVAL;
2871 }
2872
2873 intel_add_fb_offsets(&x, &y, plane_state, 0);
2874 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2875 alignment = intel_surf_alignment(fb, 0);
2876
2877 /*
2878 * AUX surface offset is specified as the distance from the
2879 * main surface offset, and it must be non-negative. Make
2880 * sure that is what we will get.
2881 */
2882 if (offset > aux_offset)
2883 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2884 offset, aux_offset & ~(alignment - 1));
2885
2886 /*
2887 * When using an X-tiled surface, the plane blows up
2888 * if the x offset + width exceed the stride.
2889 *
2890 * TODO: linear and Y-tiled seem fine, Yf untested,
2891 */
2892 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2893 int cpp = fb->format->cpp[0];
2894
2895 while ((x + w) * cpp > fb->pitches[0]) {
2896 if (offset == 0) {
2897 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2898 return -EINVAL;
2899 }
2900
2901 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2902 offset, offset - alignment);
2903 }
2904 }
2905
2906 plane_state->main.offset = offset;
2907 plane_state->main.x = x;
2908 plane_state->main.y = y;
2909
2910 return 0;
2911 }
2912
2913 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2914 {
2915 const struct drm_framebuffer *fb = plane_state->base.fb;
2916 unsigned int rotation = plane_state->base.rotation;
2917 int max_width = skl_max_plane_width(fb, 1, rotation);
2918 int max_height = 4096;
2919 int x = plane_state->base.src.x1 >> 17;
2920 int y = plane_state->base.src.y1 >> 17;
2921 int w = drm_rect_width(&plane_state->base.src) >> 17;
2922 int h = drm_rect_height(&plane_state->base.src) >> 17;
2923 u32 offset;
2924
2925 intel_add_fb_offsets(&x, &y, plane_state, 1);
2926 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2927
2928 /* FIXME not quite sure how/if these apply to the chroma plane */
2929 if (w > max_width || h > max_height) {
2930 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2931 w, h, max_width, max_height);
2932 return -EINVAL;
2933 }
2934
2935 plane_state->aux.offset = offset;
2936 plane_state->aux.x = x;
2937 plane_state->aux.y = y;
2938
2939 return 0;
2940 }
2941
2942 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2943 {
2944 const struct drm_framebuffer *fb = plane_state->base.fb;
2945 unsigned int rotation = plane_state->base.rotation;
2946 int ret;
2947
2948 if (!plane_state->base.visible)
2949 return 0;
2950
2951 /* Rotate src coordinates to match rotated GTT view */
2952 if (drm_rotation_90_or_270(rotation))
2953 drm_rect_rotate(&plane_state->base.src,
2954 fb->width << 16, fb->height << 16,
2955 DRM_MODE_ROTATE_270);
2956
2957 /*
2958 * Handle the AUX surface first since
2959 * the main surface setup depends on it.
2960 */
2961 if (fb->format->format == DRM_FORMAT_NV12) {
2962 ret = skl_check_nv12_aux_surface(plane_state);
2963 if (ret)
2964 return ret;
2965 } else {
2966 plane_state->aux.offset = ~0xfff;
2967 plane_state->aux.x = 0;
2968 plane_state->aux.y = 0;
2969 }
2970
2971 ret = skl_check_main_surface(plane_state);
2972 if (ret)
2973 return ret;
2974
2975 return 0;
2976 }
2977
2978 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2979 const struct intel_plane_state *plane_state)
2980 {
2981 struct drm_i915_private *dev_priv =
2982 to_i915(plane_state->base.plane->dev);
2983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2984 const struct drm_framebuffer *fb = plane_state->base.fb;
2985 unsigned int rotation = plane_state->base.rotation;
2986 u32 dspcntr;
2987
2988 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2989
2990 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2991 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2992 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2993
2994 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2995 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2996
2997 if (INTEL_GEN(dev_priv) < 4)
2998 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
2999
3000 switch (fb->format->format) {
3001 case DRM_FORMAT_C8:
3002 dspcntr |= DISPPLANE_8BPP;
3003 break;
3004 case DRM_FORMAT_XRGB1555:
3005 dspcntr |= DISPPLANE_BGRX555;
3006 break;
3007 case DRM_FORMAT_RGB565:
3008 dspcntr |= DISPPLANE_BGRX565;
3009 break;
3010 case DRM_FORMAT_XRGB8888:
3011 dspcntr |= DISPPLANE_BGRX888;
3012 break;
3013 case DRM_FORMAT_XBGR8888:
3014 dspcntr |= DISPPLANE_RGBX888;
3015 break;
3016 case DRM_FORMAT_XRGB2101010:
3017 dspcntr |= DISPPLANE_BGRX101010;
3018 break;
3019 case DRM_FORMAT_XBGR2101010:
3020 dspcntr |= DISPPLANE_RGBX101010;
3021 break;
3022 default:
3023 MISSING_CASE(fb->format->format);
3024 return 0;
3025 }
3026
3027 if (INTEL_GEN(dev_priv) >= 4 &&
3028 fb->modifier == I915_FORMAT_MOD_X_TILED)
3029 dspcntr |= DISPPLANE_TILED;
3030
3031 if (rotation & DRM_MODE_ROTATE_180)
3032 dspcntr |= DISPPLANE_ROTATE_180;
3033
3034 if (rotation & DRM_MODE_REFLECT_X)
3035 dspcntr |= DISPPLANE_MIRROR;
3036
3037 return dspcntr;
3038 }
3039
3040 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3041 {
3042 struct drm_i915_private *dev_priv =
3043 to_i915(plane_state->base.plane->dev);
3044 int src_x = plane_state->base.src.x1 >> 16;
3045 int src_y = plane_state->base.src.y1 >> 16;
3046 u32 offset;
3047
3048 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3049
3050 if (INTEL_GEN(dev_priv) >= 4)
3051 offset = intel_compute_tile_offset(&src_x, &src_y,
3052 plane_state, 0);
3053 else
3054 offset = 0;
3055
3056 /* HSW/BDW do this automagically in hardware */
3057 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3058 unsigned int rotation = plane_state->base.rotation;
3059 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3060 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3061
3062 if (rotation & DRM_MODE_ROTATE_180) {
3063 src_x += src_w - 1;
3064 src_y += src_h - 1;
3065 } else if (rotation & DRM_MODE_REFLECT_X) {
3066 src_x += src_w - 1;
3067 }
3068 }
3069
3070 plane_state->main.offset = offset;
3071 plane_state->main.x = src_x;
3072 plane_state->main.y = src_y;
3073
3074 return 0;
3075 }
3076
3077 static void i9xx_update_primary_plane(struct intel_plane *primary,
3078 const struct intel_crtc_state *crtc_state,
3079 const struct intel_plane_state *plane_state)
3080 {
3081 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3082 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3083 const struct drm_framebuffer *fb = plane_state->base.fb;
3084 enum plane plane = primary->plane;
3085 u32 linear_offset;
3086 u32 dspcntr = plane_state->ctl;
3087 i915_reg_t reg = DSPCNTR(plane);
3088 int x = plane_state->main.x;
3089 int y = plane_state->main.y;
3090 unsigned long irqflags;
3091
3092 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3093
3094 if (INTEL_GEN(dev_priv) >= 4)
3095 crtc->dspaddr_offset = plane_state->main.offset;
3096 else
3097 crtc->dspaddr_offset = linear_offset;
3098
3099 crtc->adjusted_x = x;
3100 crtc->adjusted_y = y;
3101
3102 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3103
3104 if (INTEL_GEN(dev_priv) < 4) {
3105 /* pipesrc and dspsize control the size that is scaled from,
3106 * which should always be the user's requested size.
3107 */
3108 I915_WRITE_FW(DSPSIZE(plane),
3109 ((crtc_state->pipe_src_h - 1) << 16) |
3110 (crtc_state->pipe_src_w - 1));
3111 I915_WRITE_FW(DSPPOS(plane), 0);
3112 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3113 I915_WRITE_FW(PRIMSIZE(plane),
3114 ((crtc_state->pipe_src_h - 1) << 16) |
3115 (crtc_state->pipe_src_w - 1));
3116 I915_WRITE_FW(PRIMPOS(plane), 0);
3117 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3118 }
3119
3120 I915_WRITE_FW(reg, dspcntr);
3121
3122 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3123 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3124 I915_WRITE_FW(DSPSURF(plane),
3125 intel_plane_ggtt_offset(plane_state) +
3126 crtc->dspaddr_offset);
3127 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3128 } else if (INTEL_GEN(dev_priv) >= 4) {
3129 I915_WRITE_FW(DSPSURF(plane),
3130 intel_plane_ggtt_offset(plane_state) +
3131 crtc->dspaddr_offset);
3132 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3133 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3134 } else {
3135 I915_WRITE_FW(DSPADDR(plane),
3136 intel_plane_ggtt_offset(plane_state) +
3137 crtc->dspaddr_offset);
3138 }
3139 POSTING_READ_FW(reg);
3140
3141 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3142 }
3143
3144 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3145 struct intel_crtc *crtc)
3146 {
3147 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3148 enum plane plane = primary->plane;
3149 unsigned long irqflags;
3150
3151 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3152
3153 I915_WRITE_FW(DSPCNTR(plane), 0);
3154 if (INTEL_INFO(dev_priv)->gen >= 4)
3155 I915_WRITE_FW(DSPSURF(plane), 0);
3156 else
3157 I915_WRITE_FW(DSPADDR(plane), 0);
3158 POSTING_READ_FW(DSPCNTR(plane));
3159
3160 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3161 }
3162
3163 static u32
3164 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3165 {
3166 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3167 return 64;
3168 else
3169 return intel_tile_width_bytes(fb, plane);
3170 }
3171
3172 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3173 {
3174 struct drm_device *dev = intel_crtc->base.dev;
3175 struct drm_i915_private *dev_priv = to_i915(dev);
3176
3177 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3178 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3179 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3180 }
3181
3182 /*
3183 * This function detaches (aka. unbinds) unused scalers in hardware
3184 */
3185 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3186 {
3187 struct intel_crtc_scaler_state *scaler_state;
3188 int i;
3189
3190 scaler_state = &intel_crtc->config->scaler_state;
3191
3192 /* loop through and disable scalers that aren't in use */
3193 for (i = 0; i < intel_crtc->num_scalers; i++) {
3194 if (!scaler_state->scalers[i].in_use)
3195 skl_detach_scaler(intel_crtc, i);
3196 }
3197 }
3198
3199 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3200 unsigned int rotation)
3201 {
3202 u32 stride;
3203
3204 if (plane >= fb->format->num_planes)
3205 return 0;
3206
3207 stride = intel_fb_pitch(fb, plane, rotation);
3208
3209 /*
3210 * The stride is either expressed as a multiple of 64 bytes chunks for
3211 * linear buffers or in number of tiles for tiled buffers.
3212 */
3213 if (drm_rotation_90_or_270(rotation))
3214 stride /= intel_tile_height(fb, plane);
3215 else
3216 stride /= intel_fb_stride_alignment(fb, plane);
3217
3218 return stride;
3219 }
3220
3221 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3222 {
3223 switch (pixel_format) {
3224 case DRM_FORMAT_C8:
3225 return PLANE_CTL_FORMAT_INDEXED;
3226 case DRM_FORMAT_RGB565:
3227 return PLANE_CTL_FORMAT_RGB_565;
3228 case DRM_FORMAT_XBGR8888:
3229 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3230 case DRM_FORMAT_XRGB8888:
3231 return PLANE_CTL_FORMAT_XRGB_8888;
3232 /*
3233 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3234 * to be already pre-multiplied. We need to add a knob (or a different
3235 * DRM_FORMAT) for user-space to configure that.
3236 */
3237 case DRM_FORMAT_ABGR8888:
3238 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3239 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3240 case DRM_FORMAT_ARGB8888:
3241 return PLANE_CTL_FORMAT_XRGB_8888 |
3242 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3243 case DRM_FORMAT_XRGB2101010:
3244 return PLANE_CTL_FORMAT_XRGB_2101010;
3245 case DRM_FORMAT_XBGR2101010:
3246 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3247 case DRM_FORMAT_YUYV:
3248 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3249 case DRM_FORMAT_YVYU:
3250 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3251 case DRM_FORMAT_UYVY:
3252 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3253 case DRM_FORMAT_VYUY:
3254 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3255 default:
3256 MISSING_CASE(pixel_format);
3257 }
3258
3259 return 0;
3260 }
3261
3262 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3263 {
3264 switch (fb_modifier) {
3265 case DRM_FORMAT_MOD_LINEAR:
3266 break;
3267 case I915_FORMAT_MOD_X_TILED:
3268 return PLANE_CTL_TILED_X;
3269 case I915_FORMAT_MOD_Y_TILED:
3270 return PLANE_CTL_TILED_Y;
3271 case I915_FORMAT_MOD_Yf_TILED:
3272 return PLANE_CTL_TILED_YF;
3273 default:
3274 MISSING_CASE(fb_modifier);
3275 }
3276
3277 return 0;
3278 }
3279
3280 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3281 {
3282 switch (rotation) {
3283 case DRM_MODE_ROTATE_0:
3284 break;
3285 /*
3286 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3287 * while i915 HW rotation is clockwise, thats why this swapping.
3288 */
3289 case DRM_MODE_ROTATE_90:
3290 return PLANE_CTL_ROTATE_270;
3291 case DRM_MODE_ROTATE_180:
3292 return PLANE_CTL_ROTATE_180;
3293 case DRM_MODE_ROTATE_270:
3294 return PLANE_CTL_ROTATE_90;
3295 default:
3296 MISSING_CASE(rotation);
3297 }
3298
3299 return 0;
3300 }
3301
3302 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3303 const struct intel_plane_state *plane_state)
3304 {
3305 struct drm_i915_private *dev_priv =
3306 to_i915(plane_state->base.plane->dev);
3307 const struct drm_framebuffer *fb = plane_state->base.fb;
3308 unsigned int rotation = plane_state->base.rotation;
3309 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3310 u32 plane_ctl;
3311
3312 plane_ctl = PLANE_CTL_ENABLE;
3313
3314 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3315 plane_ctl |=
3316 PLANE_CTL_PIPE_GAMMA_ENABLE |
3317 PLANE_CTL_PIPE_CSC_ENABLE |
3318 PLANE_CTL_PLANE_GAMMA_DISABLE;
3319 }
3320
3321 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3322 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3323 plane_ctl |= skl_plane_ctl_rotation(rotation);
3324
3325 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3326 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3327 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3328 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3329
3330 return plane_ctl;
3331 }
3332
3333 static void skylake_update_primary_plane(struct intel_plane *plane,
3334 const struct intel_crtc_state *crtc_state,
3335 const struct intel_plane_state *plane_state)
3336 {
3337 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3338 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3339 const struct drm_framebuffer *fb = plane_state->base.fb;
3340 enum plane_id plane_id = plane->id;
3341 enum pipe pipe = plane->pipe;
3342 u32 plane_ctl = plane_state->ctl;
3343 unsigned int rotation = plane_state->base.rotation;
3344 u32 stride = skl_plane_stride(fb, 0, rotation);
3345 u32 surf_addr = plane_state->main.offset;
3346 int scaler_id = plane_state->scaler_id;
3347 int src_x = plane_state->main.x;
3348 int src_y = plane_state->main.y;
3349 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3350 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3351 int dst_x = plane_state->base.dst.x1;
3352 int dst_y = plane_state->base.dst.y1;
3353 int dst_w = drm_rect_width(&plane_state->base.dst);
3354 int dst_h = drm_rect_height(&plane_state->base.dst);
3355 unsigned long irqflags;
3356
3357 /* Sizes are 0 based */
3358 src_w--;
3359 src_h--;
3360 dst_w--;
3361 dst_h--;
3362
3363 crtc->dspaddr_offset = surf_addr;
3364
3365 crtc->adjusted_x = src_x;
3366 crtc->adjusted_y = src_y;
3367
3368 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3369
3370 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3371 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3372 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3373 PLANE_COLOR_PIPE_CSC_ENABLE |
3374 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3375 }
3376
3377 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3378 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3379 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3380 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3381
3382 if (scaler_id >= 0) {
3383 uint32_t ps_ctrl = 0;
3384
3385 WARN_ON(!dst_w || !dst_h);
3386 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3387 crtc_state->scaler_state.scalers[scaler_id].mode;
3388 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3389 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3390 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3391 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3392 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3393 } else {
3394 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3395 }
3396
3397 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3398 intel_plane_ggtt_offset(plane_state) + surf_addr);
3399
3400 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3401
3402 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3403 }
3404
3405 static void skylake_disable_primary_plane(struct intel_plane *primary,
3406 struct intel_crtc *crtc)
3407 {
3408 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3409 enum plane_id plane_id = primary->id;
3410 enum pipe pipe = primary->pipe;
3411 unsigned long irqflags;
3412
3413 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3414
3415 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3416 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3417 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3418
3419 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3420 }
3421
3422 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3423 {
3424 struct intel_crtc *crtc;
3425
3426 for_each_intel_crtc(&dev_priv->drm, crtc)
3427 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3428 }
3429
3430 static int
3431 __intel_display_resume(struct drm_device *dev,
3432 struct drm_atomic_state *state,
3433 struct drm_modeset_acquire_ctx *ctx)
3434 {
3435 struct drm_crtc_state *crtc_state;
3436 struct drm_crtc *crtc;
3437 int i, ret;
3438
3439 intel_modeset_setup_hw_state(dev, ctx);
3440 i915_redisable_vga(to_i915(dev));
3441
3442 if (!state)
3443 return 0;
3444
3445 /*
3446 * We've duplicated the state, pointers to the old state are invalid.
3447 *
3448 * Don't attempt to use the old state until we commit the duplicated state.
3449 */
3450 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3451 /*
3452 * Force recalculation even if we restore
3453 * current state. With fast modeset this may not result
3454 * in a modeset when the state is compatible.
3455 */
3456 crtc_state->mode_changed = true;
3457 }
3458
3459 /* ignore any reset values/BIOS leftovers in the WM registers */
3460 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3461 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3462
3463 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3464
3465 WARN_ON(ret == -EDEADLK);
3466 return ret;
3467 }
3468
3469 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3470 {
3471 return intel_has_gpu_reset(dev_priv) &&
3472 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3473 }
3474
3475 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3476 {
3477 struct drm_device *dev = &dev_priv->drm;
3478 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3479 struct drm_atomic_state *state;
3480 int ret;
3481
3482
3483 /* reset doesn't touch the display */
3484 if (!i915.force_reset_modeset_test &&
3485 !gpu_reset_clobbers_display(dev_priv))
3486 return;
3487
3488 /*
3489 * Need mode_config.mutex so that we don't
3490 * trample ongoing ->detect() and whatnot.
3491 */
3492 mutex_lock(&dev->mode_config.mutex);
3493 drm_modeset_acquire_init(ctx, 0);
3494 while (1) {
3495 ret = drm_modeset_lock_all_ctx(dev, ctx);
3496 if (ret != -EDEADLK)
3497 break;
3498
3499 drm_modeset_backoff(ctx);
3500 }
3501 /*
3502 * Disabling the crtcs gracefully seems nicer. Also the
3503 * g33 docs say we should at least disable all the planes.
3504 */
3505 state = drm_atomic_helper_duplicate_state(dev, ctx);
3506 if (IS_ERR(state)) {
3507 ret = PTR_ERR(state);
3508 DRM_ERROR("Duplicating state failed with %i\n", ret);
3509 return;
3510 }
3511
3512 ret = drm_atomic_helper_disable_all(dev, ctx);
3513 if (ret) {
3514 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3515 drm_atomic_state_put(state);
3516 return;
3517 }
3518
3519 dev_priv->modeset_restore_state = state;
3520 state->acquire_ctx = ctx;
3521 }
3522
3523 void intel_finish_reset(struct drm_i915_private *dev_priv)
3524 {
3525 struct drm_device *dev = &dev_priv->drm;
3526 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3527 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3528 int ret;
3529
3530 /* reset doesn't touch the display */
3531 if (!i915.force_reset_modeset_test &&
3532 !gpu_reset_clobbers_display(dev_priv))
3533 return;
3534
3535 if (!state)
3536 goto unlock;
3537
3538 /*
3539 * Flips in the rings will be nuked by the reset,
3540 * so complete all pending flips so that user space
3541 * will get its events and not get stuck.
3542 */
3543 intel_complete_page_flips(dev_priv);
3544
3545 dev_priv->modeset_restore_state = NULL;
3546
3547 /* reset doesn't touch the display */
3548 if (!gpu_reset_clobbers_display(dev_priv)) {
3549 /* for testing only restore the display */
3550 ret = __intel_display_resume(dev, state, ctx);
3551 if (ret)
3552 DRM_ERROR("Restoring old state failed with %i\n", ret);
3553 } else {
3554 /*
3555 * The display has been reset as well,
3556 * so need a full re-initialization.
3557 */
3558 intel_runtime_pm_disable_interrupts(dev_priv);
3559 intel_runtime_pm_enable_interrupts(dev_priv);
3560
3561 intel_pps_unlock_regs_wa(dev_priv);
3562 intel_modeset_init_hw(dev);
3563
3564 spin_lock_irq(&dev_priv->irq_lock);
3565 if (dev_priv->display.hpd_irq_setup)
3566 dev_priv->display.hpd_irq_setup(dev_priv);
3567 spin_unlock_irq(&dev_priv->irq_lock);
3568
3569 ret = __intel_display_resume(dev, state, ctx);
3570 if (ret)
3571 DRM_ERROR("Restoring old state failed with %i\n", ret);
3572
3573 intel_hpd_init(dev_priv);
3574 }
3575
3576 drm_atomic_state_put(state);
3577 unlock:
3578 drm_modeset_drop_locks(ctx);
3579 drm_modeset_acquire_fini(ctx);
3580 mutex_unlock(&dev->mode_config.mutex);
3581 }
3582
3583 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3584 {
3585 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3586
3587 if (i915_reset_backoff(error))
3588 return true;
3589
3590 if (crtc->reset_count != i915_reset_count(error))
3591 return true;
3592
3593 return false;
3594 }
3595
3596 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3597 {
3598 struct drm_device *dev = crtc->dev;
3599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3600 bool pending;
3601
3602 if (abort_flip_on_reset(intel_crtc))
3603 return false;
3604
3605 spin_lock_irq(&dev->event_lock);
3606 pending = to_intel_crtc(crtc)->flip_work != NULL;
3607 spin_unlock_irq(&dev->event_lock);
3608
3609 return pending;
3610 }
3611
3612 static void intel_update_pipe_config(struct intel_crtc *crtc,
3613 struct intel_crtc_state *old_crtc_state)
3614 {
3615 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3616 struct intel_crtc_state *pipe_config =
3617 to_intel_crtc_state(crtc->base.state);
3618
3619 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3620 crtc->base.mode = crtc->base.state->mode;
3621
3622 /*
3623 * Update pipe size and adjust fitter if needed: the reason for this is
3624 * that in compute_mode_changes we check the native mode (not the pfit
3625 * mode) to see if we can flip rather than do a full mode set. In the
3626 * fastboot case, we'll flip, but if we don't update the pipesrc and
3627 * pfit state, we'll end up with a big fb scanned out into the wrong
3628 * sized surface.
3629 */
3630
3631 I915_WRITE(PIPESRC(crtc->pipe),
3632 ((pipe_config->pipe_src_w - 1) << 16) |
3633 (pipe_config->pipe_src_h - 1));
3634
3635 /* on skylake this is done by detaching scalers */
3636 if (INTEL_GEN(dev_priv) >= 9) {
3637 skl_detach_scalers(crtc);
3638
3639 if (pipe_config->pch_pfit.enabled)
3640 skylake_pfit_enable(crtc);
3641 } else if (HAS_PCH_SPLIT(dev_priv)) {
3642 if (pipe_config->pch_pfit.enabled)
3643 ironlake_pfit_enable(crtc);
3644 else if (old_crtc_state->pch_pfit.enabled)
3645 ironlake_pfit_disable(crtc, true);
3646 }
3647 }
3648
3649 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3650 {
3651 struct drm_device *dev = crtc->base.dev;
3652 struct drm_i915_private *dev_priv = to_i915(dev);
3653 int pipe = crtc->pipe;
3654 i915_reg_t reg;
3655 u32 temp;
3656
3657 /* enable normal train */
3658 reg = FDI_TX_CTL(pipe);
3659 temp = I915_READ(reg);
3660 if (IS_IVYBRIDGE(dev_priv)) {
3661 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3662 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3663 } else {
3664 temp &= ~FDI_LINK_TRAIN_NONE;
3665 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3666 }
3667 I915_WRITE(reg, temp);
3668
3669 reg = FDI_RX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 if (HAS_PCH_CPT(dev_priv)) {
3672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3673 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3674 } else {
3675 temp &= ~FDI_LINK_TRAIN_NONE;
3676 temp |= FDI_LINK_TRAIN_NONE;
3677 }
3678 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3679
3680 /* wait one idle pattern time */
3681 POSTING_READ(reg);
3682 udelay(1000);
3683
3684 /* IVB wants error correction enabled */
3685 if (IS_IVYBRIDGE(dev_priv))
3686 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3687 FDI_FE_ERRC_ENABLE);
3688 }
3689
3690 /* The FDI link training functions for ILK/Ibexpeak. */
3691 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3692 const struct intel_crtc_state *crtc_state)
3693 {
3694 struct drm_device *dev = crtc->base.dev;
3695 struct drm_i915_private *dev_priv = to_i915(dev);
3696 int pipe = crtc->pipe;
3697 i915_reg_t reg;
3698 u32 temp, tries;
3699
3700 /* FDI needs bits from pipe first */
3701 assert_pipe_enabled(dev_priv, pipe);
3702
3703 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3704 for train result */
3705 reg = FDI_RX_IMR(pipe);
3706 temp = I915_READ(reg);
3707 temp &= ~FDI_RX_SYMBOL_LOCK;
3708 temp &= ~FDI_RX_BIT_LOCK;
3709 I915_WRITE(reg, temp);
3710 I915_READ(reg);
3711 udelay(150);
3712
3713 /* enable CPU FDI TX and PCH FDI RX */
3714 reg = FDI_TX_CTL(pipe);
3715 temp = I915_READ(reg);
3716 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3717 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3718 temp &= ~FDI_LINK_TRAIN_NONE;
3719 temp |= FDI_LINK_TRAIN_PATTERN_1;
3720 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3721
3722 reg = FDI_RX_CTL(pipe);
3723 temp = I915_READ(reg);
3724 temp &= ~FDI_LINK_TRAIN_NONE;
3725 temp |= FDI_LINK_TRAIN_PATTERN_1;
3726 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3727
3728 POSTING_READ(reg);
3729 udelay(150);
3730
3731 /* Ironlake workaround, enable clock pointer after FDI enable*/
3732 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3733 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3734 FDI_RX_PHASE_SYNC_POINTER_EN);
3735
3736 reg = FDI_RX_IIR(pipe);
3737 for (tries = 0; tries < 5; tries++) {
3738 temp = I915_READ(reg);
3739 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3740
3741 if ((temp & FDI_RX_BIT_LOCK)) {
3742 DRM_DEBUG_KMS("FDI train 1 done.\n");
3743 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3744 break;
3745 }
3746 }
3747 if (tries == 5)
3748 DRM_ERROR("FDI train 1 fail!\n");
3749
3750 /* Train 2 */
3751 reg = FDI_TX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 temp &= ~FDI_LINK_TRAIN_NONE;
3754 temp |= FDI_LINK_TRAIN_PATTERN_2;
3755 I915_WRITE(reg, temp);
3756
3757 reg = FDI_RX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 temp &= ~FDI_LINK_TRAIN_NONE;
3760 temp |= FDI_LINK_TRAIN_PATTERN_2;
3761 I915_WRITE(reg, temp);
3762
3763 POSTING_READ(reg);
3764 udelay(150);
3765
3766 reg = FDI_RX_IIR(pipe);
3767 for (tries = 0; tries < 5; tries++) {
3768 temp = I915_READ(reg);
3769 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3770
3771 if (temp & FDI_RX_SYMBOL_LOCK) {
3772 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3773 DRM_DEBUG_KMS("FDI train 2 done.\n");
3774 break;
3775 }
3776 }
3777 if (tries == 5)
3778 DRM_ERROR("FDI train 2 fail!\n");
3779
3780 DRM_DEBUG_KMS("FDI train done\n");
3781
3782 }
3783
3784 static const int snb_b_fdi_train_param[] = {
3785 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3786 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3787 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3788 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3789 };
3790
3791 /* The FDI link training functions for SNB/Cougarpoint. */
3792 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3793 const struct intel_crtc_state *crtc_state)
3794 {
3795 struct drm_device *dev = crtc->base.dev;
3796 struct drm_i915_private *dev_priv = to_i915(dev);
3797 int pipe = crtc->pipe;
3798 i915_reg_t reg;
3799 u32 temp, i, retry;
3800
3801 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3802 for train result */
3803 reg = FDI_RX_IMR(pipe);
3804 temp = I915_READ(reg);
3805 temp &= ~FDI_RX_SYMBOL_LOCK;
3806 temp &= ~FDI_RX_BIT_LOCK;
3807 I915_WRITE(reg, temp);
3808
3809 POSTING_READ(reg);
3810 udelay(150);
3811
3812 /* enable CPU FDI TX and PCH FDI RX */
3813 reg = FDI_TX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3816 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3817 temp &= ~FDI_LINK_TRAIN_NONE;
3818 temp |= FDI_LINK_TRAIN_PATTERN_1;
3819 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3820 /* SNB-B */
3821 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3822 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3823
3824 I915_WRITE(FDI_RX_MISC(pipe),
3825 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3826
3827 reg = FDI_RX_CTL(pipe);
3828 temp = I915_READ(reg);
3829 if (HAS_PCH_CPT(dev_priv)) {
3830 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3831 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3832 } else {
3833 temp &= ~FDI_LINK_TRAIN_NONE;
3834 temp |= FDI_LINK_TRAIN_PATTERN_1;
3835 }
3836 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3837
3838 POSTING_READ(reg);
3839 udelay(150);
3840
3841 for (i = 0; i < 4; i++) {
3842 reg = FDI_TX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3845 temp |= snb_b_fdi_train_param[i];
3846 I915_WRITE(reg, temp);
3847
3848 POSTING_READ(reg);
3849 udelay(500);
3850
3851 for (retry = 0; retry < 5; retry++) {
3852 reg = FDI_RX_IIR(pipe);
3853 temp = I915_READ(reg);
3854 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3855 if (temp & FDI_RX_BIT_LOCK) {
3856 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3857 DRM_DEBUG_KMS("FDI train 1 done.\n");
3858 break;
3859 }
3860 udelay(50);
3861 }
3862 if (retry < 5)
3863 break;
3864 }
3865 if (i == 4)
3866 DRM_ERROR("FDI train 1 fail!\n");
3867
3868 /* Train 2 */
3869 reg = FDI_TX_CTL(pipe);
3870 temp = I915_READ(reg);
3871 temp &= ~FDI_LINK_TRAIN_NONE;
3872 temp |= FDI_LINK_TRAIN_PATTERN_2;
3873 if (IS_GEN6(dev_priv)) {
3874 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3875 /* SNB-B */
3876 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3877 }
3878 I915_WRITE(reg, temp);
3879
3880 reg = FDI_RX_CTL(pipe);
3881 temp = I915_READ(reg);
3882 if (HAS_PCH_CPT(dev_priv)) {
3883 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3884 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3885 } else {
3886 temp &= ~FDI_LINK_TRAIN_NONE;
3887 temp |= FDI_LINK_TRAIN_PATTERN_2;
3888 }
3889 I915_WRITE(reg, temp);
3890
3891 POSTING_READ(reg);
3892 udelay(150);
3893
3894 for (i = 0; i < 4; i++) {
3895 reg = FDI_TX_CTL(pipe);
3896 temp = I915_READ(reg);
3897 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3898 temp |= snb_b_fdi_train_param[i];
3899 I915_WRITE(reg, temp);
3900
3901 POSTING_READ(reg);
3902 udelay(500);
3903
3904 for (retry = 0; retry < 5; retry++) {
3905 reg = FDI_RX_IIR(pipe);
3906 temp = I915_READ(reg);
3907 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3908 if (temp & FDI_RX_SYMBOL_LOCK) {
3909 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3910 DRM_DEBUG_KMS("FDI train 2 done.\n");
3911 break;
3912 }
3913 udelay(50);
3914 }
3915 if (retry < 5)
3916 break;
3917 }
3918 if (i == 4)
3919 DRM_ERROR("FDI train 2 fail!\n");
3920
3921 DRM_DEBUG_KMS("FDI train done.\n");
3922 }
3923
3924 /* Manual link training for Ivy Bridge A0 parts */
3925 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3926 const struct intel_crtc_state *crtc_state)
3927 {
3928 struct drm_device *dev = crtc->base.dev;
3929 struct drm_i915_private *dev_priv = to_i915(dev);
3930 int pipe = crtc->pipe;
3931 i915_reg_t reg;
3932 u32 temp, i, j;
3933
3934 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3935 for train result */
3936 reg = FDI_RX_IMR(pipe);
3937 temp = I915_READ(reg);
3938 temp &= ~FDI_RX_SYMBOL_LOCK;
3939 temp &= ~FDI_RX_BIT_LOCK;
3940 I915_WRITE(reg, temp);
3941
3942 POSTING_READ(reg);
3943 udelay(150);
3944
3945 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3946 I915_READ(FDI_RX_IIR(pipe)));
3947
3948 /* Try each vswing and preemphasis setting twice before moving on */
3949 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3950 /* disable first in case we need to retry */
3951 reg = FDI_TX_CTL(pipe);
3952 temp = I915_READ(reg);
3953 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3954 temp &= ~FDI_TX_ENABLE;
3955 I915_WRITE(reg, temp);
3956
3957 reg = FDI_RX_CTL(pipe);
3958 temp = I915_READ(reg);
3959 temp &= ~FDI_LINK_TRAIN_AUTO;
3960 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3961 temp &= ~FDI_RX_ENABLE;
3962 I915_WRITE(reg, temp);
3963
3964 /* enable CPU FDI TX and PCH FDI RX */
3965 reg = FDI_TX_CTL(pipe);
3966 temp = I915_READ(reg);
3967 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3968 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3969 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3970 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3971 temp |= snb_b_fdi_train_param[j/2];
3972 temp |= FDI_COMPOSITE_SYNC;
3973 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3974
3975 I915_WRITE(FDI_RX_MISC(pipe),
3976 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3977
3978 reg = FDI_RX_CTL(pipe);
3979 temp = I915_READ(reg);
3980 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3981 temp |= FDI_COMPOSITE_SYNC;
3982 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3983
3984 POSTING_READ(reg);
3985 udelay(1); /* should be 0.5us */
3986
3987 for (i = 0; i < 4; i++) {
3988 reg = FDI_RX_IIR(pipe);
3989 temp = I915_READ(reg);
3990 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3991
3992 if (temp & FDI_RX_BIT_LOCK ||
3993 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3994 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3995 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3996 i);
3997 break;
3998 }
3999 udelay(1); /* should be 0.5us */
4000 }
4001 if (i == 4) {
4002 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4003 continue;
4004 }
4005
4006 /* Train 2 */
4007 reg = FDI_TX_CTL(pipe);
4008 temp = I915_READ(reg);
4009 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4010 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4011 I915_WRITE(reg, temp);
4012
4013 reg = FDI_RX_CTL(pipe);
4014 temp = I915_READ(reg);
4015 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4016 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4017 I915_WRITE(reg, temp);
4018
4019 POSTING_READ(reg);
4020 udelay(2); /* should be 1.5us */
4021
4022 for (i = 0; i < 4; i++) {
4023 reg = FDI_RX_IIR(pipe);
4024 temp = I915_READ(reg);
4025 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4026
4027 if (temp & FDI_RX_SYMBOL_LOCK ||
4028 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4029 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4030 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4031 i);
4032 goto train_done;
4033 }
4034 udelay(2); /* should be 1.5us */
4035 }
4036 if (i == 4)
4037 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4038 }
4039
4040 train_done:
4041 DRM_DEBUG_KMS("FDI train done.\n");
4042 }
4043
4044 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4045 {
4046 struct drm_device *dev = intel_crtc->base.dev;
4047 struct drm_i915_private *dev_priv = to_i915(dev);
4048 int pipe = intel_crtc->pipe;
4049 i915_reg_t reg;
4050 u32 temp;
4051
4052 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4053 reg = FDI_RX_CTL(pipe);
4054 temp = I915_READ(reg);
4055 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4056 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4057 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4058 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4059
4060 POSTING_READ(reg);
4061 udelay(200);
4062
4063 /* Switch from Rawclk to PCDclk */
4064 temp = I915_READ(reg);
4065 I915_WRITE(reg, temp | FDI_PCDCLK);
4066
4067 POSTING_READ(reg);
4068 udelay(200);
4069
4070 /* Enable CPU FDI TX PLL, always on for Ironlake */
4071 reg = FDI_TX_CTL(pipe);
4072 temp = I915_READ(reg);
4073 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4074 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4075
4076 POSTING_READ(reg);
4077 udelay(100);
4078 }
4079 }
4080
4081 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4082 {
4083 struct drm_device *dev = intel_crtc->base.dev;
4084 struct drm_i915_private *dev_priv = to_i915(dev);
4085 int pipe = intel_crtc->pipe;
4086 i915_reg_t reg;
4087 u32 temp;
4088
4089 /* Switch from PCDclk to Rawclk */
4090 reg = FDI_RX_CTL(pipe);
4091 temp = I915_READ(reg);
4092 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4093
4094 /* Disable CPU FDI TX PLL */
4095 reg = FDI_TX_CTL(pipe);
4096 temp = I915_READ(reg);
4097 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4098
4099 POSTING_READ(reg);
4100 udelay(100);
4101
4102 reg = FDI_RX_CTL(pipe);
4103 temp = I915_READ(reg);
4104 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4105
4106 /* Wait for the clocks to turn off. */
4107 POSTING_READ(reg);
4108 udelay(100);
4109 }
4110
4111 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4112 {
4113 struct drm_device *dev = crtc->dev;
4114 struct drm_i915_private *dev_priv = to_i915(dev);
4115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4116 int pipe = intel_crtc->pipe;
4117 i915_reg_t reg;
4118 u32 temp;
4119
4120 /* disable CPU FDI tx and PCH FDI rx */
4121 reg = FDI_TX_CTL(pipe);
4122 temp = I915_READ(reg);
4123 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4124 POSTING_READ(reg);
4125
4126 reg = FDI_RX_CTL(pipe);
4127 temp = I915_READ(reg);
4128 temp &= ~(0x7 << 16);
4129 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4130 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4131
4132 POSTING_READ(reg);
4133 udelay(100);
4134
4135 /* Ironlake workaround, disable clock pointer after downing FDI */
4136 if (HAS_PCH_IBX(dev_priv))
4137 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4138
4139 /* still set train pattern 1 */
4140 reg = FDI_TX_CTL(pipe);
4141 temp = I915_READ(reg);
4142 temp &= ~FDI_LINK_TRAIN_NONE;
4143 temp |= FDI_LINK_TRAIN_PATTERN_1;
4144 I915_WRITE(reg, temp);
4145
4146 reg = FDI_RX_CTL(pipe);
4147 temp = I915_READ(reg);
4148 if (HAS_PCH_CPT(dev_priv)) {
4149 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4150 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4151 } else {
4152 temp &= ~FDI_LINK_TRAIN_NONE;
4153 temp |= FDI_LINK_TRAIN_PATTERN_1;
4154 }
4155 /* BPC in FDI rx is consistent with that in PIPECONF */
4156 temp &= ~(0x07 << 16);
4157 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4158 I915_WRITE(reg, temp);
4159
4160 POSTING_READ(reg);
4161 udelay(100);
4162 }
4163
4164 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4165 {
4166 struct intel_crtc *crtc;
4167
4168 /* Note that we don't need to be called with mode_config.lock here
4169 * as our list of CRTC objects is static for the lifetime of the
4170 * device and so cannot disappear as we iterate. Similarly, we can
4171 * happily treat the predicates as racy, atomic checks as userspace
4172 * cannot claim and pin a new fb without at least acquring the
4173 * struct_mutex and so serialising with us.
4174 */
4175 for_each_intel_crtc(&dev_priv->drm, crtc) {
4176 if (atomic_read(&crtc->unpin_work_count) == 0)
4177 continue;
4178
4179 if (crtc->flip_work)
4180 intel_wait_for_vblank(dev_priv, crtc->pipe);
4181
4182 return true;
4183 }
4184
4185 return false;
4186 }
4187
4188 static void page_flip_completed(struct intel_crtc *intel_crtc)
4189 {
4190 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4191 struct intel_flip_work *work = intel_crtc->flip_work;
4192
4193 intel_crtc->flip_work = NULL;
4194
4195 if (work->event)
4196 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4197
4198 drm_crtc_vblank_put(&intel_crtc->base);
4199
4200 wake_up_all(&dev_priv->pending_flip_queue);
4201 trace_i915_flip_complete(intel_crtc->plane,
4202 work->pending_flip_obj);
4203
4204 queue_work(dev_priv->wq, &work->unpin_work);
4205 }
4206
4207 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4208 {
4209 struct drm_device *dev = crtc->dev;
4210 struct drm_i915_private *dev_priv = to_i915(dev);
4211 long ret;
4212
4213 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4214
4215 ret = wait_event_interruptible_timeout(
4216 dev_priv->pending_flip_queue,
4217 !intel_crtc_has_pending_flip(crtc),
4218 60*HZ);
4219
4220 if (ret < 0)
4221 return ret;
4222
4223 if (ret == 0) {
4224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4225 struct intel_flip_work *work;
4226
4227 spin_lock_irq(&dev->event_lock);
4228 work = intel_crtc->flip_work;
4229 if (work && !is_mmio_work(work)) {
4230 WARN_ONCE(1, "Removing stuck page flip\n");
4231 page_flip_completed(intel_crtc);
4232 }
4233 spin_unlock_irq(&dev->event_lock);
4234 }
4235
4236 return 0;
4237 }
4238
4239 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4240 {
4241 u32 temp;
4242
4243 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4244
4245 mutex_lock(&dev_priv->sb_lock);
4246
4247 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4248 temp |= SBI_SSCCTL_DISABLE;
4249 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4250
4251 mutex_unlock(&dev_priv->sb_lock);
4252 }
4253
4254 /* Program iCLKIP clock to the desired frequency */
4255 static void lpt_program_iclkip(struct intel_crtc *crtc)
4256 {
4257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4258 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4259 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4260 u32 temp;
4261
4262 lpt_disable_iclkip(dev_priv);
4263
4264 /* The iCLK virtual clock root frequency is in MHz,
4265 * but the adjusted_mode->crtc_clock in in KHz. To get the
4266 * divisors, it is necessary to divide one by another, so we
4267 * convert the virtual clock precision to KHz here for higher
4268 * precision.
4269 */
4270 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4271 u32 iclk_virtual_root_freq = 172800 * 1000;
4272 u32 iclk_pi_range = 64;
4273 u32 desired_divisor;
4274
4275 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4276 clock << auxdiv);
4277 divsel = (desired_divisor / iclk_pi_range) - 2;
4278 phaseinc = desired_divisor % iclk_pi_range;
4279
4280 /*
4281 * Near 20MHz is a corner case which is
4282 * out of range for the 7-bit divisor
4283 */
4284 if (divsel <= 0x7f)
4285 break;
4286 }
4287
4288 /* This should not happen with any sane values */
4289 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4290 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4291 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4292 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4293
4294 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4295 clock,
4296 auxdiv,
4297 divsel,
4298 phasedir,
4299 phaseinc);
4300
4301 mutex_lock(&dev_priv->sb_lock);
4302
4303 /* Program SSCDIVINTPHASE6 */
4304 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4305 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4306 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4307 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4308 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4309 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4310 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4311 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4312
4313 /* Program SSCAUXDIV */
4314 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4315 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4316 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4317 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4318
4319 /* Enable modulator and associated divider */
4320 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4321 temp &= ~SBI_SSCCTL_DISABLE;
4322 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4323
4324 mutex_unlock(&dev_priv->sb_lock);
4325
4326 /* Wait for initialization time */
4327 udelay(24);
4328
4329 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4330 }
4331
4332 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4333 {
4334 u32 divsel, phaseinc, auxdiv;
4335 u32 iclk_virtual_root_freq = 172800 * 1000;
4336 u32 iclk_pi_range = 64;
4337 u32 desired_divisor;
4338 u32 temp;
4339
4340 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4341 return 0;
4342
4343 mutex_lock(&dev_priv->sb_lock);
4344
4345 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4346 if (temp & SBI_SSCCTL_DISABLE) {
4347 mutex_unlock(&dev_priv->sb_lock);
4348 return 0;
4349 }
4350
4351 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4352 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4353 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4354 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4355 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4356
4357 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4358 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4359 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4360
4361 mutex_unlock(&dev_priv->sb_lock);
4362
4363 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4364
4365 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4366 desired_divisor << auxdiv);
4367 }
4368
4369 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4370 enum pipe pch_transcoder)
4371 {
4372 struct drm_device *dev = crtc->base.dev;
4373 struct drm_i915_private *dev_priv = to_i915(dev);
4374 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4375
4376 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4377 I915_READ(HTOTAL(cpu_transcoder)));
4378 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4379 I915_READ(HBLANK(cpu_transcoder)));
4380 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4381 I915_READ(HSYNC(cpu_transcoder)));
4382
4383 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4384 I915_READ(VTOTAL(cpu_transcoder)));
4385 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4386 I915_READ(VBLANK(cpu_transcoder)));
4387 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4388 I915_READ(VSYNC(cpu_transcoder)));
4389 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4390 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4391 }
4392
4393 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4394 {
4395 struct drm_i915_private *dev_priv = to_i915(dev);
4396 uint32_t temp;
4397
4398 temp = I915_READ(SOUTH_CHICKEN1);
4399 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4400 return;
4401
4402 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4403 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4404
4405 temp &= ~FDI_BC_BIFURCATION_SELECT;
4406 if (enable)
4407 temp |= FDI_BC_BIFURCATION_SELECT;
4408
4409 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4410 I915_WRITE(SOUTH_CHICKEN1, temp);
4411 POSTING_READ(SOUTH_CHICKEN1);
4412 }
4413
4414 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4415 {
4416 struct drm_device *dev = intel_crtc->base.dev;
4417
4418 switch (intel_crtc->pipe) {
4419 case PIPE_A:
4420 break;
4421 case PIPE_B:
4422 if (intel_crtc->config->fdi_lanes > 2)
4423 cpt_set_fdi_bc_bifurcation(dev, false);
4424 else
4425 cpt_set_fdi_bc_bifurcation(dev, true);
4426
4427 break;
4428 case PIPE_C:
4429 cpt_set_fdi_bc_bifurcation(dev, true);
4430
4431 break;
4432 default:
4433 BUG();
4434 }
4435 }
4436
4437 /* Return which DP Port should be selected for Transcoder DP control */
4438 static enum port
4439 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4440 {
4441 struct drm_device *dev = crtc->base.dev;
4442 struct intel_encoder *encoder;
4443
4444 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4445 if (encoder->type == INTEL_OUTPUT_DP ||
4446 encoder->type == INTEL_OUTPUT_EDP)
4447 return enc_to_dig_port(&encoder->base)->port;
4448 }
4449
4450 return -1;
4451 }
4452
4453 /*
4454 * Enable PCH resources required for PCH ports:
4455 * - PCH PLLs
4456 * - FDI training & RX/TX
4457 * - update transcoder timings
4458 * - DP transcoding bits
4459 * - transcoder
4460 */
4461 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4462 {
4463 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4464 struct drm_device *dev = crtc->base.dev;
4465 struct drm_i915_private *dev_priv = to_i915(dev);
4466 int pipe = crtc->pipe;
4467 u32 temp;
4468
4469 assert_pch_transcoder_disabled(dev_priv, pipe);
4470
4471 if (IS_IVYBRIDGE(dev_priv))
4472 ivybridge_update_fdi_bc_bifurcation(crtc);
4473
4474 /* Write the TU size bits before fdi link training, so that error
4475 * detection works. */
4476 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4477 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4478
4479 /* For PCH output, training FDI link */
4480 dev_priv->display.fdi_link_train(crtc, crtc_state);
4481
4482 /* We need to program the right clock selection before writing the pixel
4483 * mutliplier into the DPLL. */
4484 if (HAS_PCH_CPT(dev_priv)) {
4485 u32 sel;
4486
4487 temp = I915_READ(PCH_DPLL_SEL);
4488 temp |= TRANS_DPLL_ENABLE(pipe);
4489 sel = TRANS_DPLLB_SEL(pipe);
4490 if (crtc_state->shared_dpll ==
4491 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4492 temp |= sel;
4493 else
4494 temp &= ~sel;
4495 I915_WRITE(PCH_DPLL_SEL, temp);
4496 }
4497
4498 /* XXX: pch pll's can be enabled any time before we enable the PCH
4499 * transcoder, and we actually should do this to not upset any PCH
4500 * transcoder that already use the clock when we share it.
4501 *
4502 * Note that enable_shared_dpll tries to do the right thing, but
4503 * get_shared_dpll unconditionally resets the pll - we need that to have
4504 * the right LVDS enable sequence. */
4505 intel_enable_shared_dpll(crtc);
4506
4507 /* set transcoder timing, panel must allow it */
4508 assert_panel_unlocked(dev_priv, pipe);
4509 ironlake_pch_transcoder_set_timings(crtc, pipe);
4510
4511 intel_fdi_normal_train(crtc);
4512
4513 /* For PCH DP, enable TRANS_DP_CTL */
4514 if (HAS_PCH_CPT(dev_priv) &&
4515 intel_crtc_has_dp_encoder(crtc_state)) {
4516 const struct drm_display_mode *adjusted_mode =
4517 &crtc_state->base.adjusted_mode;
4518 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4519 i915_reg_t reg = TRANS_DP_CTL(pipe);
4520 temp = I915_READ(reg);
4521 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4522 TRANS_DP_SYNC_MASK |
4523 TRANS_DP_BPC_MASK);
4524 temp |= TRANS_DP_OUTPUT_ENABLE;
4525 temp |= bpc << 9; /* same format but at 11:9 */
4526
4527 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4528 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4529 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4530 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4531
4532 switch (intel_trans_dp_port_sel(crtc)) {
4533 case PORT_B:
4534 temp |= TRANS_DP_PORT_SEL_B;
4535 break;
4536 case PORT_C:
4537 temp |= TRANS_DP_PORT_SEL_C;
4538 break;
4539 case PORT_D:
4540 temp |= TRANS_DP_PORT_SEL_D;
4541 break;
4542 default:
4543 BUG();
4544 }
4545
4546 I915_WRITE(reg, temp);
4547 }
4548
4549 ironlake_enable_pch_transcoder(dev_priv, pipe);
4550 }
4551
4552 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4553 {
4554 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4555 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4556 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4557
4558 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4559
4560 lpt_program_iclkip(crtc);
4561
4562 /* Set transcoder timing. */
4563 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4564
4565 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4566 }
4567
4568 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4569 {
4570 struct drm_i915_private *dev_priv = to_i915(dev);
4571 i915_reg_t dslreg = PIPEDSL(pipe);
4572 u32 temp;
4573
4574 temp = I915_READ(dslreg);
4575 udelay(500);
4576 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4577 if (wait_for(I915_READ(dslreg) != temp, 5))
4578 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4579 }
4580 }
4581
4582 static int
4583 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4584 unsigned int scaler_user, int *scaler_id,
4585 int src_w, int src_h, int dst_w, int dst_h)
4586 {
4587 struct intel_crtc_scaler_state *scaler_state =
4588 &crtc_state->scaler_state;
4589 struct intel_crtc *intel_crtc =
4590 to_intel_crtc(crtc_state->base.crtc);
4591 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4592 const struct drm_display_mode *adjusted_mode =
4593 &crtc_state->base.adjusted_mode;
4594 int need_scaling;
4595
4596 /*
4597 * Src coordinates are already rotated by 270 degrees for
4598 * the 90/270 degree plane rotation cases (to match the
4599 * GTT mapping), hence no need to account for rotation here.
4600 */
4601 need_scaling = src_w != dst_w || src_h != dst_h;
4602
4603 /*
4604 * Scaling/fitting not supported in IF-ID mode in GEN9+
4605 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4606 * Once NV12 is enabled, handle it here while allocating scaler
4607 * for NV12.
4608 */
4609 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4610 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4611 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4612 return -EINVAL;
4613 }
4614
4615 /*
4616 * if plane is being disabled or scaler is no more required or force detach
4617 * - free scaler binded to this plane/crtc
4618 * - in order to do this, update crtc->scaler_usage
4619 *
4620 * Here scaler state in crtc_state is set free so that
4621 * scaler can be assigned to other user. Actual register
4622 * update to free the scaler is done in plane/panel-fit programming.
4623 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4624 */
4625 if (force_detach || !need_scaling) {
4626 if (*scaler_id >= 0) {
4627 scaler_state->scaler_users &= ~(1 << scaler_user);
4628 scaler_state->scalers[*scaler_id].in_use = 0;
4629
4630 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4631 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4632 intel_crtc->pipe, scaler_user, *scaler_id,
4633 scaler_state->scaler_users);
4634 *scaler_id = -1;
4635 }
4636 return 0;
4637 }
4638
4639 /* range checks */
4640 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4641 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4642
4643 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4644 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4645 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4646 "size is out of scaler range\n",
4647 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4648 return -EINVAL;
4649 }
4650
4651 /* mark this plane as a scaler user in crtc_state */
4652 scaler_state->scaler_users |= (1 << scaler_user);
4653 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4654 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4655 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4656 scaler_state->scaler_users);
4657
4658 return 0;
4659 }
4660
4661 /**
4662 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4663 *
4664 * @state: crtc's scaler state
4665 *
4666 * Return
4667 * 0 - scaler_usage updated successfully
4668 * error - requested scaling cannot be supported or other error condition
4669 */
4670 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4671 {
4672 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4673
4674 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4675 &state->scaler_state.scaler_id,
4676 state->pipe_src_w, state->pipe_src_h,
4677 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4678 }
4679
4680 /**
4681 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4682 *
4683 * @state: crtc's scaler state
4684 * @plane_state: atomic plane state to update
4685 *
4686 * Return
4687 * 0 - scaler_usage updated successfully
4688 * error - requested scaling cannot be supported or other error condition
4689 */
4690 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4691 struct intel_plane_state *plane_state)
4692 {
4693
4694 struct intel_plane *intel_plane =
4695 to_intel_plane(plane_state->base.plane);
4696 struct drm_framebuffer *fb = plane_state->base.fb;
4697 int ret;
4698
4699 bool force_detach = !fb || !plane_state->base.visible;
4700
4701 ret = skl_update_scaler(crtc_state, force_detach,
4702 drm_plane_index(&intel_plane->base),
4703 &plane_state->scaler_id,
4704 drm_rect_width(&plane_state->base.src) >> 16,
4705 drm_rect_height(&plane_state->base.src) >> 16,
4706 drm_rect_width(&plane_state->base.dst),
4707 drm_rect_height(&plane_state->base.dst));
4708
4709 if (ret || plane_state->scaler_id < 0)
4710 return ret;
4711
4712 /* check colorkey */
4713 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4714 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4715 intel_plane->base.base.id,
4716 intel_plane->base.name);
4717 return -EINVAL;
4718 }
4719
4720 /* Check src format */
4721 switch (fb->format->format) {
4722 case DRM_FORMAT_RGB565:
4723 case DRM_FORMAT_XBGR8888:
4724 case DRM_FORMAT_XRGB8888:
4725 case DRM_FORMAT_ABGR8888:
4726 case DRM_FORMAT_ARGB8888:
4727 case DRM_FORMAT_XRGB2101010:
4728 case DRM_FORMAT_XBGR2101010:
4729 case DRM_FORMAT_YUYV:
4730 case DRM_FORMAT_YVYU:
4731 case DRM_FORMAT_UYVY:
4732 case DRM_FORMAT_VYUY:
4733 break;
4734 default:
4735 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4736 intel_plane->base.base.id, intel_plane->base.name,
4737 fb->base.id, fb->format->format);
4738 return -EINVAL;
4739 }
4740
4741 return 0;
4742 }
4743
4744 static void skylake_scaler_disable(struct intel_crtc *crtc)
4745 {
4746 int i;
4747
4748 for (i = 0; i < crtc->num_scalers; i++)
4749 skl_detach_scaler(crtc, i);
4750 }
4751
4752 static void skylake_pfit_enable(struct intel_crtc *crtc)
4753 {
4754 struct drm_device *dev = crtc->base.dev;
4755 struct drm_i915_private *dev_priv = to_i915(dev);
4756 int pipe = crtc->pipe;
4757 struct intel_crtc_scaler_state *scaler_state =
4758 &crtc->config->scaler_state;
4759
4760 if (crtc->config->pch_pfit.enabled) {
4761 int id;
4762
4763 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4764 return;
4765
4766 id = scaler_state->scaler_id;
4767 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4768 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4769 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4770 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4771 }
4772 }
4773
4774 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4775 {
4776 struct drm_device *dev = crtc->base.dev;
4777 struct drm_i915_private *dev_priv = to_i915(dev);
4778 int pipe = crtc->pipe;
4779
4780 if (crtc->config->pch_pfit.enabled) {
4781 /* Force use of hard-coded filter coefficients
4782 * as some pre-programmed values are broken,
4783 * e.g. x201.
4784 */
4785 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4786 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4787 PF_PIPE_SEL_IVB(pipe));
4788 else
4789 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4790 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4791 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4792 }
4793 }
4794
4795 void hsw_enable_ips(struct intel_crtc *crtc)
4796 {
4797 struct drm_device *dev = crtc->base.dev;
4798 struct drm_i915_private *dev_priv = to_i915(dev);
4799
4800 if (!crtc->config->ips_enabled)
4801 return;
4802
4803 /*
4804 * We can only enable IPS after we enable a plane and wait for a vblank
4805 * This function is called from post_plane_update, which is run after
4806 * a vblank wait.
4807 */
4808
4809 assert_plane_enabled(dev_priv, crtc->plane);
4810 if (IS_BROADWELL(dev_priv)) {
4811 mutex_lock(&dev_priv->rps.hw_lock);
4812 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4813 mutex_unlock(&dev_priv->rps.hw_lock);
4814 /* Quoting Art Runyan: "its not safe to expect any particular
4815 * value in IPS_CTL bit 31 after enabling IPS through the
4816 * mailbox." Moreover, the mailbox may return a bogus state,
4817 * so we need to just enable it and continue on.
4818 */
4819 } else {
4820 I915_WRITE(IPS_CTL, IPS_ENABLE);
4821 /* The bit only becomes 1 in the next vblank, so this wait here
4822 * is essentially intel_wait_for_vblank. If we don't have this
4823 * and don't wait for vblanks until the end of crtc_enable, then
4824 * the HW state readout code will complain that the expected
4825 * IPS_CTL value is not the one we read. */
4826 if (intel_wait_for_register(dev_priv,
4827 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4828 50))
4829 DRM_ERROR("Timed out waiting for IPS enable\n");
4830 }
4831 }
4832
4833 void hsw_disable_ips(struct intel_crtc *crtc)
4834 {
4835 struct drm_device *dev = crtc->base.dev;
4836 struct drm_i915_private *dev_priv = to_i915(dev);
4837
4838 if (!crtc->config->ips_enabled)
4839 return;
4840
4841 assert_plane_enabled(dev_priv, crtc->plane);
4842 if (IS_BROADWELL(dev_priv)) {
4843 mutex_lock(&dev_priv->rps.hw_lock);
4844 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4845 mutex_unlock(&dev_priv->rps.hw_lock);
4846 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4847 if (intel_wait_for_register(dev_priv,
4848 IPS_CTL, IPS_ENABLE, 0,
4849 42))
4850 DRM_ERROR("Timed out waiting for IPS disable\n");
4851 } else {
4852 I915_WRITE(IPS_CTL, 0);
4853 POSTING_READ(IPS_CTL);
4854 }
4855
4856 /* We need to wait for a vblank before we can disable the plane. */
4857 intel_wait_for_vblank(dev_priv, crtc->pipe);
4858 }
4859
4860 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4861 {
4862 if (intel_crtc->overlay) {
4863 struct drm_device *dev = intel_crtc->base.dev;
4864
4865 mutex_lock(&dev->struct_mutex);
4866 (void) intel_overlay_switch_off(intel_crtc->overlay);
4867 mutex_unlock(&dev->struct_mutex);
4868 }
4869
4870 /* Let userspace switch the overlay on again. In most cases userspace
4871 * has to recompute where to put it anyway.
4872 */
4873 }
4874
4875 /**
4876 * intel_post_enable_primary - Perform operations after enabling primary plane
4877 * @crtc: the CRTC whose primary plane was just enabled
4878 *
4879 * Performs potentially sleeping operations that must be done after the primary
4880 * plane is enabled, such as updating FBC and IPS. Note that this may be
4881 * called due to an explicit primary plane update, or due to an implicit
4882 * re-enable that is caused when a sprite plane is updated to no longer
4883 * completely hide the primary plane.
4884 */
4885 static void
4886 intel_post_enable_primary(struct drm_crtc *crtc)
4887 {
4888 struct drm_device *dev = crtc->dev;
4889 struct drm_i915_private *dev_priv = to_i915(dev);
4890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4891 int pipe = intel_crtc->pipe;
4892
4893 /*
4894 * FIXME IPS should be fine as long as one plane is
4895 * enabled, but in practice it seems to have problems
4896 * when going from primary only to sprite only and vice
4897 * versa.
4898 */
4899 hsw_enable_ips(intel_crtc);
4900
4901 /*
4902 * Gen2 reports pipe underruns whenever all planes are disabled.
4903 * So don't enable underrun reporting before at least some planes
4904 * are enabled.
4905 * FIXME: Need to fix the logic to work when we turn off all planes
4906 * but leave the pipe running.
4907 */
4908 if (IS_GEN2(dev_priv))
4909 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4910
4911 /* Underruns don't always raise interrupts, so check manually. */
4912 intel_check_cpu_fifo_underruns(dev_priv);
4913 intel_check_pch_fifo_underruns(dev_priv);
4914 }
4915
4916 /* FIXME move all this to pre_plane_update() with proper state tracking */
4917 static void
4918 intel_pre_disable_primary(struct drm_crtc *crtc)
4919 {
4920 struct drm_device *dev = crtc->dev;
4921 struct drm_i915_private *dev_priv = to_i915(dev);
4922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4923 int pipe = intel_crtc->pipe;
4924
4925 /*
4926 * Gen2 reports pipe underruns whenever all planes are disabled.
4927 * So diasble underrun reporting before all the planes get disabled.
4928 * FIXME: Need to fix the logic to work when we turn off all planes
4929 * but leave the pipe running.
4930 */
4931 if (IS_GEN2(dev_priv))
4932 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4933
4934 /*
4935 * FIXME IPS should be fine as long as one plane is
4936 * enabled, but in practice it seems to have problems
4937 * when going from primary only to sprite only and vice
4938 * versa.
4939 */
4940 hsw_disable_ips(intel_crtc);
4941 }
4942
4943 /* FIXME get rid of this and use pre_plane_update */
4944 static void
4945 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4946 {
4947 struct drm_device *dev = crtc->dev;
4948 struct drm_i915_private *dev_priv = to_i915(dev);
4949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4950 int pipe = intel_crtc->pipe;
4951
4952 intel_pre_disable_primary(crtc);
4953
4954 /*
4955 * Vblank time updates from the shadow to live plane control register
4956 * are blocked if the memory self-refresh mode is active at that
4957 * moment. So to make sure the plane gets truly disabled, disable
4958 * first the self-refresh mode. The self-refresh enable bit in turn
4959 * will be checked/applied by the HW only at the next frame start
4960 * event which is after the vblank start event, so we need to have a
4961 * wait-for-vblank between disabling the plane and the pipe.
4962 */
4963 if (HAS_GMCH_DISPLAY(dev_priv) &&
4964 intel_set_memory_cxsr(dev_priv, false))
4965 intel_wait_for_vblank(dev_priv, pipe);
4966 }
4967
4968 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4969 {
4970 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4971 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4972 struct intel_crtc_state *pipe_config =
4973 to_intel_crtc_state(crtc->base.state);
4974 struct drm_plane *primary = crtc->base.primary;
4975 struct drm_plane_state *old_pri_state =
4976 drm_atomic_get_existing_plane_state(old_state, primary);
4977
4978 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4979
4980 if (pipe_config->update_wm_post && pipe_config->base.active)
4981 intel_update_watermarks(crtc);
4982
4983 if (old_pri_state) {
4984 struct intel_plane_state *primary_state =
4985 to_intel_plane_state(primary->state);
4986 struct intel_plane_state *old_primary_state =
4987 to_intel_plane_state(old_pri_state);
4988
4989 intel_fbc_post_update(crtc);
4990
4991 if (primary_state->base.visible &&
4992 (needs_modeset(&pipe_config->base) ||
4993 !old_primary_state->base.visible))
4994 intel_post_enable_primary(&crtc->base);
4995 }
4996 }
4997
4998 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
4999 struct intel_crtc_state *pipe_config)
5000 {
5001 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5002 struct drm_device *dev = crtc->base.dev;
5003 struct drm_i915_private *dev_priv = to_i915(dev);
5004 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5005 struct drm_plane *primary = crtc->base.primary;
5006 struct drm_plane_state *old_pri_state =
5007 drm_atomic_get_existing_plane_state(old_state, primary);
5008 bool modeset = needs_modeset(&pipe_config->base);
5009 struct intel_atomic_state *old_intel_state =
5010 to_intel_atomic_state(old_state);
5011
5012 if (old_pri_state) {
5013 struct intel_plane_state *primary_state =
5014 to_intel_plane_state(primary->state);
5015 struct intel_plane_state *old_primary_state =
5016 to_intel_plane_state(old_pri_state);
5017
5018 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5019
5020 if (old_primary_state->base.visible &&
5021 (modeset || !primary_state->base.visible))
5022 intel_pre_disable_primary(&crtc->base);
5023 }
5024
5025 /*
5026 * Vblank time updates from the shadow to live plane control register
5027 * are blocked if the memory self-refresh mode is active at that
5028 * moment. So to make sure the plane gets truly disabled, disable
5029 * first the self-refresh mode. The self-refresh enable bit in turn
5030 * will be checked/applied by the HW only at the next frame start
5031 * event which is after the vblank start event, so we need to have a
5032 * wait-for-vblank between disabling the plane and the pipe.
5033 */
5034 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5035 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5036 intel_wait_for_vblank(dev_priv, crtc->pipe);
5037
5038 /*
5039 * IVB workaround: must disable low power watermarks for at least
5040 * one frame before enabling scaling. LP watermarks can be re-enabled
5041 * when scaling is disabled.
5042 *
5043 * WaCxSRDisabledForSpriteScaling:ivb
5044 */
5045 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5046 intel_wait_for_vblank(dev_priv, crtc->pipe);
5047
5048 /*
5049 * If we're doing a modeset, we're done. No need to do any pre-vblank
5050 * watermark programming here.
5051 */
5052 if (needs_modeset(&pipe_config->base))
5053 return;
5054
5055 /*
5056 * For platforms that support atomic watermarks, program the
5057 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5058 * will be the intermediate values that are safe for both pre- and
5059 * post- vblank; when vblank happens, the 'active' values will be set
5060 * to the final 'target' values and we'll do this again to get the
5061 * optimal watermarks. For gen9+ platforms, the values we program here
5062 * will be the final target values which will get automatically latched
5063 * at vblank time; no further programming will be necessary.
5064 *
5065 * If a platform hasn't been transitioned to atomic watermarks yet,
5066 * we'll continue to update watermarks the old way, if flags tell
5067 * us to.
5068 */
5069 if (dev_priv->display.initial_watermarks != NULL)
5070 dev_priv->display.initial_watermarks(old_intel_state,
5071 pipe_config);
5072 else if (pipe_config->update_wm_pre)
5073 intel_update_watermarks(crtc);
5074 }
5075
5076 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5077 {
5078 struct drm_device *dev = crtc->dev;
5079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5080 struct drm_plane *p;
5081 int pipe = intel_crtc->pipe;
5082
5083 intel_crtc_dpms_overlay_disable(intel_crtc);
5084
5085 drm_for_each_plane_mask(p, dev, plane_mask)
5086 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5087
5088 /*
5089 * FIXME: Once we grow proper nuclear flip support out of this we need
5090 * to compute the mask of flip planes precisely. For the time being
5091 * consider this a flip to a NULL plane.
5092 */
5093 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5094 }
5095
5096 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5097 struct intel_crtc_state *crtc_state,
5098 struct drm_atomic_state *old_state)
5099 {
5100 struct drm_connector_state *conn_state;
5101 struct drm_connector *conn;
5102 int i;
5103
5104 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5105 struct intel_encoder *encoder =
5106 to_intel_encoder(conn_state->best_encoder);
5107
5108 if (conn_state->crtc != crtc)
5109 continue;
5110
5111 if (encoder->pre_pll_enable)
5112 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5113 }
5114 }
5115
5116 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5117 struct intel_crtc_state *crtc_state,
5118 struct drm_atomic_state *old_state)
5119 {
5120 struct drm_connector_state *conn_state;
5121 struct drm_connector *conn;
5122 int i;
5123
5124 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5125 struct intel_encoder *encoder =
5126 to_intel_encoder(conn_state->best_encoder);
5127
5128 if (conn_state->crtc != crtc)
5129 continue;
5130
5131 if (encoder->pre_enable)
5132 encoder->pre_enable(encoder, crtc_state, conn_state);
5133 }
5134 }
5135
5136 static void intel_encoders_enable(struct drm_crtc *crtc,
5137 struct intel_crtc_state *crtc_state,
5138 struct drm_atomic_state *old_state)
5139 {
5140 struct drm_connector_state *conn_state;
5141 struct drm_connector *conn;
5142 int i;
5143
5144 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5145 struct intel_encoder *encoder =
5146 to_intel_encoder(conn_state->best_encoder);
5147
5148 if (conn_state->crtc != crtc)
5149 continue;
5150
5151 encoder->enable(encoder, crtc_state, conn_state);
5152 intel_opregion_notify_encoder(encoder, true);
5153 }
5154 }
5155
5156 static void intel_encoders_disable(struct drm_crtc *crtc,
5157 struct intel_crtc_state *old_crtc_state,
5158 struct drm_atomic_state *old_state)
5159 {
5160 struct drm_connector_state *old_conn_state;
5161 struct drm_connector *conn;
5162 int i;
5163
5164 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5165 struct intel_encoder *encoder =
5166 to_intel_encoder(old_conn_state->best_encoder);
5167
5168 if (old_conn_state->crtc != crtc)
5169 continue;
5170
5171 intel_opregion_notify_encoder(encoder, false);
5172 encoder->disable(encoder, old_crtc_state, old_conn_state);
5173 }
5174 }
5175
5176 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5177 struct intel_crtc_state *old_crtc_state,
5178 struct drm_atomic_state *old_state)
5179 {
5180 struct drm_connector_state *old_conn_state;
5181 struct drm_connector *conn;
5182 int i;
5183
5184 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5185 struct intel_encoder *encoder =
5186 to_intel_encoder(old_conn_state->best_encoder);
5187
5188 if (old_conn_state->crtc != crtc)
5189 continue;
5190
5191 if (encoder->post_disable)
5192 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5193 }
5194 }
5195
5196 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5197 struct intel_crtc_state *old_crtc_state,
5198 struct drm_atomic_state *old_state)
5199 {
5200 struct drm_connector_state *old_conn_state;
5201 struct drm_connector *conn;
5202 int i;
5203
5204 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5205 struct intel_encoder *encoder =
5206 to_intel_encoder(old_conn_state->best_encoder);
5207
5208 if (old_conn_state->crtc != crtc)
5209 continue;
5210
5211 if (encoder->post_pll_disable)
5212 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5213 }
5214 }
5215
5216 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5217 struct drm_atomic_state *old_state)
5218 {
5219 struct drm_crtc *crtc = pipe_config->base.crtc;
5220 struct drm_device *dev = crtc->dev;
5221 struct drm_i915_private *dev_priv = to_i915(dev);
5222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5223 int pipe = intel_crtc->pipe;
5224 struct intel_atomic_state *old_intel_state =
5225 to_intel_atomic_state(old_state);
5226
5227 if (WARN_ON(intel_crtc->active))
5228 return;
5229
5230 /*
5231 * Sometimes spurious CPU pipe underruns happen during FDI
5232 * training, at least with VGA+HDMI cloning. Suppress them.
5233 *
5234 * On ILK we get an occasional spurious CPU pipe underruns
5235 * between eDP port A enable and vdd enable. Also PCH port
5236 * enable seems to result in the occasional CPU pipe underrun.
5237 *
5238 * Spurious PCH underruns also occur during PCH enabling.
5239 */
5240 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5241 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5242 if (intel_crtc->config->has_pch_encoder)
5243 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5244
5245 if (intel_crtc->config->has_pch_encoder)
5246 intel_prepare_shared_dpll(intel_crtc);
5247
5248 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5249 intel_dp_set_m_n(intel_crtc, M1_N1);
5250
5251 intel_set_pipe_timings(intel_crtc);
5252 intel_set_pipe_src_size(intel_crtc);
5253
5254 if (intel_crtc->config->has_pch_encoder) {
5255 intel_cpu_transcoder_set_m_n(intel_crtc,
5256 &intel_crtc->config->fdi_m_n, NULL);
5257 }
5258
5259 ironlake_set_pipeconf(crtc);
5260
5261 intel_crtc->active = true;
5262
5263 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5264
5265 if (intel_crtc->config->has_pch_encoder) {
5266 /* Note: FDI PLL enabling _must_ be done before we enable the
5267 * cpu pipes, hence this is separate from all the other fdi/pch
5268 * enabling. */
5269 ironlake_fdi_pll_enable(intel_crtc);
5270 } else {
5271 assert_fdi_tx_disabled(dev_priv, pipe);
5272 assert_fdi_rx_disabled(dev_priv, pipe);
5273 }
5274
5275 ironlake_pfit_enable(intel_crtc);
5276
5277 /*
5278 * On ILK+ LUT must be loaded before the pipe is running but with
5279 * clocks enabled
5280 */
5281 intel_color_load_luts(&pipe_config->base);
5282
5283 if (dev_priv->display.initial_watermarks != NULL)
5284 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5285 intel_enable_pipe(intel_crtc);
5286
5287 if (intel_crtc->config->has_pch_encoder)
5288 ironlake_pch_enable(pipe_config);
5289
5290 assert_vblank_disabled(crtc);
5291 drm_crtc_vblank_on(crtc);
5292
5293 intel_encoders_enable(crtc, pipe_config, old_state);
5294
5295 if (HAS_PCH_CPT(dev_priv))
5296 cpt_verify_modeset(dev, intel_crtc->pipe);
5297
5298 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5299 if (intel_crtc->config->has_pch_encoder)
5300 intel_wait_for_vblank(dev_priv, pipe);
5301 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5302 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5303 }
5304
5305 /* IPS only exists on ULT machines and is tied to pipe A. */
5306 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5307 {
5308 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5309 }
5310
5311 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5312 struct drm_atomic_state *old_state)
5313 {
5314 struct drm_crtc *crtc = pipe_config->base.crtc;
5315 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5317 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5318 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5319 struct intel_atomic_state *old_intel_state =
5320 to_intel_atomic_state(old_state);
5321
5322 if (WARN_ON(intel_crtc->active))
5323 return;
5324
5325 if (intel_crtc->config->has_pch_encoder)
5326 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5327 false);
5328
5329 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5330
5331 if (intel_crtc->config->shared_dpll)
5332 intel_enable_shared_dpll(intel_crtc);
5333
5334 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5335 intel_dp_set_m_n(intel_crtc, M1_N1);
5336
5337 if (!transcoder_is_dsi(cpu_transcoder))
5338 intel_set_pipe_timings(intel_crtc);
5339
5340 intel_set_pipe_src_size(intel_crtc);
5341
5342 if (cpu_transcoder != TRANSCODER_EDP &&
5343 !transcoder_is_dsi(cpu_transcoder)) {
5344 I915_WRITE(PIPE_MULT(cpu_transcoder),
5345 intel_crtc->config->pixel_multiplier - 1);
5346 }
5347
5348 if (intel_crtc->config->has_pch_encoder) {
5349 intel_cpu_transcoder_set_m_n(intel_crtc,
5350 &intel_crtc->config->fdi_m_n, NULL);
5351 }
5352
5353 if (!transcoder_is_dsi(cpu_transcoder))
5354 haswell_set_pipeconf(crtc);
5355
5356 haswell_set_pipemisc(crtc);
5357
5358 intel_color_set_csc(&pipe_config->base);
5359
5360 intel_crtc->active = true;
5361
5362 if (intel_crtc->config->has_pch_encoder)
5363 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5364 else
5365 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5366
5367 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5368
5369 if (intel_crtc->config->has_pch_encoder)
5370 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5371
5372 if (!transcoder_is_dsi(cpu_transcoder))
5373 intel_ddi_enable_pipe_clock(pipe_config);
5374
5375 if (INTEL_GEN(dev_priv) >= 9)
5376 skylake_pfit_enable(intel_crtc);
5377 else
5378 ironlake_pfit_enable(intel_crtc);
5379
5380 /*
5381 * On ILK+ LUT must be loaded before the pipe is running but with
5382 * clocks enabled
5383 */
5384 intel_color_load_luts(&pipe_config->base);
5385
5386 intel_ddi_set_pipe_settings(pipe_config);
5387 if (!transcoder_is_dsi(cpu_transcoder))
5388 intel_ddi_enable_transcoder_func(pipe_config);
5389
5390 if (dev_priv->display.initial_watermarks != NULL)
5391 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5392
5393 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5394 if (!transcoder_is_dsi(cpu_transcoder))
5395 intel_enable_pipe(intel_crtc);
5396
5397 if (intel_crtc->config->has_pch_encoder)
5398 lpt_pch_enable(pipe_config);
5399
5400 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5401 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5402
5403 assert_vblank_disabled(crtc);
5404 drm_crtc_vblank_on(crtc);
5405
5406 intel_encoders_enable(crtc, pipe_config, old_state);
5407
5408 if (intel_crtc->config->has_pch_encoder) {
5409 intel_wait_for_vblank(dev_priv, pipe);
5410 intel_wait_for_vblank(dev_priv, pipe);
5411 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5412 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5413 true);
5414 }
5415
5416 /* If we change the relative order between pipe/planes enabling, we need
5417 * to change the workaround. */
5418 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5419 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5420 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5421 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5422 }
5423 }
5424
5425 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5426 {
5427 struct drm_device *dev = crtc->base.dev;
5428 struct drm_i915_private *dev_priv = to_i915(dev);
5429 int pipe = crtc->pipe;
5430
5431 /* To avoid upsetting the power well on haswell only disable the pfit if
5432 * it's in use. The hw state code will make sure we get this right. */
5433 if (force || crtc->config->pch_pfit.enabled) {
5434 I915_WRITE(PF_CTL(pipe), 0);
5435 I915_WRITE(PF_WIN_POS(pipe), 0);
5436 I915_WRITE(PF_WIN_SZ(pipe), 0);
5437 }
5438 }
5439
5440 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5441 struct drm_atomic_state *old_state)
5442 {
5443 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5444 struct drm_device *dev = crtc->dev;
5445 struct drm_i915_private *dev_priv = to_i915(dev);
5446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5447 int pipe = intel_crtc->pipe;
5448
5449 /*
5450 * Sometimes spurious CPU pipe underruns happen when the
5451 * pipe is already disabled, but FDI RX/TX is still enabled.
5452 * Happens at least with VGA+HDMI cloning. Suppress them.
5453 */
5454 if (intel_crtc->config->has_pch_encoder) {
5455 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5456 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5457 }
5458
5459 intel_encoders_disable(crtc, old_crtc_state, old_state);
5460
5461 drm_crtc_vblank_off(crtc);
5462 assert_vblank_disabled(crtc);
5463
5464 intel_disable_pipe(intel_crtc);
5465
5466 ironlake_pfit_disable(intel_crtc, false);
5467
5468 if (intel_crtc->config->has_pch_encoder)
5469 ironlake_fdi_disable(crtc);
5470
5471 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5472
5473 if (intel_crtc->config->has_pch_encoder) {
5474 ironlake_disable_pch_transcoder(dev_priv, pipe);
5475
5476 if (HAS_PCH_CPT(dev_priv)) {
5477 i915_reg_t reg;
5478 u32 temp;
5479
5480 /* disable TRANS_DP_CTL */
5481 reg = TRANS_DP_CTL(pipe);
5482 temp = I915_READ(reg);
5483 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5484 TRANS_DP_PORT_SEL_MASK);
5485 temp |= TRANS_DP_PORT_SEL_NONE;
5486 I915_WRITE(reg, temp);
5487
5488 /* disable DPLL_SEL */
5489 temp = I915_READ(PCH_DPLL_SEL);
5490 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5491 I915_WRITE(PCH_DPLL_SEL, temp);
5492 }
5493
5494 ironlake_fdi_pll_disable(intel_crtc);
5495 }
5496
5497 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5498 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5499 }
5500
5501 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5502 struct drm_atomic_state *old_state)
5503 {
5504 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5505 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5507 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5508
5509 if (intel_crtc->config->has_pch_encoder)
5510 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5511 false);
5512
5513 intel_encoders_disable(crtc, old_crtc_state, old_state);
5514
5515 drm_crtc_vblank_off(crtc);
5516 assert_vblank_disabled(crtc);
5517
5518 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5519 if (!transcoder_is_dsi(cpu_transcoder))
5520 intel_disable_pipe(intel_crtc);
5521
5522 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5523 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5524
5525 if (!transcoder_is_dsi(cpu_transcoder))
5526 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5527
5528 if (INTEL_GEN(dev_priv) >= 9)
5529 skylake_scaler_disable(intel_crtc);
5530 else
5531 ironlake_pfit_disable(intel_crtc, false);
5532
5533 if (!transcoder_is_dsi(cpu_transcoder))
5534 intel_ddi_disable_pipe_clock(intel_crtc->config);
5535
5536 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5537
5538 if (old_crtc_state->has_pch_encoder)
5539 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5540 true);
5541 }
5542
5543 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5544 {
5545 struct drm_device *dev = crtc->base.dev;
5546 struct drm_i915_private *dev_priv = to_i915(dev);
5547 struct intel_crtc_state *pipe_config = crtc->config;
5548
5549 if (!pipe_config->gmch_pfit.control)
5550 return;
5551
5552 /*
5553 * The panel fitter should only be adjusted whilst the pipe is disabled,
5554 * according to register description and PRM.
5555 */
5556 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5557 assert_pipe_disabled(dev_priv, crtc->pipe);
5558
5559 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5560 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5561
5562 /* Border color in case we don't scale up to the full screen. Black by
5563 * default, change to something else for debugging. */
5564 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5565 }
5566
5567 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5568 {
5569 switch (port) {
5570 case PORT_A:
5571 return POWER_DOMAIN_PORT_DDI_A_LANES;
5572 case PORT_B:
5573 return POWER_DOMAIN_PORT_DDI_B_LANES;
5574 case PORT_C:
5575 return POWER_DOMAIN_PORT_DDI_C_LANES;
5576 case PORT_D:
5577 return POWER_DOMAIN_PORT_DDI_D_LANES;
5578 case PORT_E:
5579 return POWER_DOMAIN_PORT_DDI_E_LANES;
5580 default:
5581 MISSING_CASE(port);
5582 return POWER_DOMAIN_PORT_OTHER;
5583 }
5584 }
5585
5586 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5587 struct intel_crtc_state *crtc_state)
5588 {
5589 struct drm_device *dev = crtc->dev;
5590 struct drm_i915_private *dev_priv = to_i915(dev);
5591 struct drm_encoder *encoder;
5592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5593 enum pipe pipe = intel_crtc->pipe;
5594 u64 mask;
5595 enum transcoder transcoder = crtc_state->cpu_transcoder;
5596
5597 if (!crtc_state->base.active)
5598 return 0;
5599
5600 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5601 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5602 if (crtc_state->pch_pfit.enabled ||
5603 crtc_state->pch_pfit.force_thru)
5604 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5605
5606 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5607 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5608
5609 mask |= BIT_ULL(intel_encoder->power_domain);
5610 }
5611
5612 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5613 mask |= BIT(POWER_DOMAIN_AUDIO);
5614
5615 if (crtc_state->shared_dpll)
5616 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5617
5618 return mask;
5619 }
5620
5621 static u64
5622 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5623 struct intel_crtc_state *crtc_state)
5624 {
5625 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5627 enum intel_display_power_domain domain;
5628 u64 domains, new_domains, old_domains;
5629
5630 old_domains = intel_crtc->enabled_power_domains;
5631 intel_crtc->enabled_power_domains = new_domains =
5632 get_crtc_power_domains(crtc, crtc_state);
5633
5634 domains = new_domains & ~old_domains;
5635
5636 for_each_power_domain(domain, domains)
5637 intel_display_power_get(dev_priv, domain);
5638
5639 return old_domains & ~new_domains;
5640 }
5641
5642 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5643 u64 domains)
5644 {
5645 enum intel_display_power_domain domain;
5646
5647 for_each_power_domain(domain, domains)
5648 intel_display_power_put(dev_priv, domain);
5649 }
5650
5651 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5652 struct drm_atomic_state *old_state)
5653 {
5654 struct intel_atomic_state *old_intel_state =
5655 to_intel_atomic_state(old_state);
5656 struct drm_crtc *crtc = pipe_config->base.crtc;
5657 struct drm_device *dev = crtc->dev;
5658 struct drm_i915_private *dev_priv = to_i915(dev);
5659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5660 int pipe = intel_crtc->pipe;
5661
5662 if (WARN_ON(intel_crtc->active))
5663 return;
5664
5665 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5666 intel_dp_set_m_n(intel_crtc, M1_N1);
5667
5668 intel_set_pipe_timings(intel_crtc);
5669 intel_set_pipe_src_size(intel_crtc);
5670
5671 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5672 struct drm_i915_private *dev_priv = to_i915(dev);
5673
5674 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5675 I915_WRITE(CHV_CANVAS(pipe), 0);
5676 }
5677
5678 i9xx_set_pipeconf(intel_crtc);
5679
5680 intel_crtc->active = true;
5681
5682 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5683
5684 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5685
5686 if (IS_CHERRYVIEW(dev_priv)) {
5687 chv_prepare_pll(intel_crtc, intel_crtc->config);
5688 chv_enable_pll(intel_crtc, intel_crtc->config);
5689 } else {
5690 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5691 vlv_enable_pll(intel_crtc, intel_crtc->config);
5692 }
5693
5694 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5695
5696 i9xx_pfit_enable(intel_crtc);
5697
5698 intel_color_load_luts(&pipe_config->base);
5699
5700 dev_priv->display.initial_watermarks(old_intel_state,
5701 pipe_config);
5702 intel_enable_pipe(intel_crtc);
5703
5704 assert_vblank_disabled(crtc);
5705 drm_crtc_vblank_on(crtc);
5706
5707 intel_encoders_enable(crtc, pipe_config, old_state);
5708 }
5709
5710 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5711 {
5712 struct drm_device *dev = crtc->base.dev;
5713 struct drm_i915_private *dev_priv = to_i915(dev);
5714
5715 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5716 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5717 }
5718
5719 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5720 struct drm_atomic_state *old_state)
5721 {
5722 struct intel_atomic_state *old_intel_state =
5723 to_intel_atomic_state(old_state);
5724 struct drm_crtc *crtc = pipe_config->base.crtc;
5725 struct drm_device *dev = crtc->dev;
5726 struct drm_i915_private *dev_priv = to_i915(dev);
5727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5728 enum pipe pipe = intel_crtc->pipe;
5729
5730 if (WARN_ON(intel_crtc->active))
5731 return;
5732
5733 i9xx_set_pll_dividers(intel_crtc);
5734
5735 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5736 intel_dp_set_m_n(intel_crtc, M1_N1);
5737
5738 intel_set_pipe_timings(intel_crtc);
5739 intel_set_pipe_src_size(intel_crtc);
5740
5741 i9xx_set_pipeconf(intel_crtc);
5742
5743 intel_crtc->active = true;
5744
5745 if (!IS_GEN2(dev_priv))
5746 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5747
5748 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5749
5750 i9xx_enable_pll(intel_crtc);
5751
5752 i9xx_pfit_enable(intel_crtc);
5753
5754 intel_color_load_luts(&pipe_config->base);
5755
5756 if (dev_priv->display.initial_watermarks != NULL)
5757 dev_priv->display.initial_watermarks(old_intel_state,
5758 intel_crtc->config);
5759 else
5760 intel_update_watermarks(intel_crtc);
5761 intel_enable_pipe(intel_crtc);
5762
5763 assert_vblank_disabled(crtc);
5764 drm_crtc_vblank_on(crtc);
5765
5766 intel_encoders_enable(crtc, pipe_config, old_state);
5767 }
5768
5769 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5770 {
5771 struct drm_device *dev = crtc->base.dev;
5772 struct drm_i915_private *dev_priv = to_i915(dev);
5773
5774 if (!crtc->config->gmch_pfit.control)
5775 return;
5776
5777 assert_pipe_disabled(dev_priv, crtc->pipe);
5778
5779 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5780 I915_READ(PFIT_CONTROL));
5781 I915_WRITE(PFIT_CONTROL, 0);
5782 }
5783
5784 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5785 struct drm_atomic_state *old_state)
5786 {
5787 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5788 struct drm_device *dev = crtc->dev;
5789 struct drm_i915_private *dev_priv = to_i915(dev);
5790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5791 int pipe = intel_crtc->pipe;
5792
5793 /*
5794 * On gen2 planes are double buffered but the pipe isn't, so we must
5795 * wait for planes to fully turn off before disabling the pipe.
5796 */
5797 if (IS_GEN2(dev_priv))
5798 intel_wait_for_vblank(dev_priv, pipe);
5799
5800 intel_encoders_disable(crtc, old_crtc_state, old_state);
5801
5802 drm_crtc_vblank_off(crtc);
5803 assert_vblank_disabled(crtc);
5804
5805 intel_disable_pipe(intel_crtc);
5806
5807 i9xx_pfit_disable(intel_crtc);
5808
5809 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5810
5811 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5812 if (IS_CHERRYVIEW(dev_priv))
5813 chv_disable_pll(dev_priv, pipe);
5814 else if (IS_VALLEYVIEW(dev_priv))
5815 vlv_disable_pll(dev_priv, pipe);
5816 else
5817 i9xx_disable_pll(intel_crtc);
5818 }
5819
5820 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5821
5822 if (!IS_GEN2(dev_priv))
5823 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5824
5825 if (!dev_priv->display.initial_watermarks)
5826 intel_update_watermarks(intel_crtc);
5827
5828 /* clock the pipe down to 640x480@60 to potentially save power */
5829 if (IS_I830(dev_priv))
5830 i830_enable_pipe(dev_priv, pipe);
5831 }
5832
5833 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5834 struct drm_modeset_acquire_ctx *ctx)
5835 {
5836 struct intel_encoder *encoder;
5837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5838 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5839 enum intel_display_power_domain domain;
5840 u64 domains;
5841 struct drm_atomic_state *state;
5842 struct intel_crtc_state *crtc_state;
5843 int ret;
5844
5845 if (!intel_crtc->active)
5846 return;
5847
5848 if (crtc->primary->state->visible) {
5849 WARN_ON(intel_crtc->flip_work);
5850
5851 intel_pre_disable_primary_noatomic(crtc);
5852
5853 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5854 crtc->primary->state->visible = false;
5855 }
5856
5857 state = drm_atomic_state_alloc(crtc->dev);
5858 if (!state) {
5859 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5860 crtc->base.id, crtc->name);
5861 return;
5862 }
5863
5864 state->acquire_ctx = ctx;
5865
5866 /* Everything's already locked, -EDEADLK can't happen. */
5867 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5868 ret = drm_atomic_add_affected_connectors(state, crtc);
5869
5870 WARN_ON(IS_ERR(crtc_state) || ret);
5871
5872 dev_priv->display.crtc_disable(crtc_state, state);
5873
5874 drm_atomic_state_put(state);
5875
5876 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5877 crtc->base.id, crtc->name);
5878
5879 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5880 crtc->state->active = false;
5881 intel_crtc->active = false;
5882 crtc->enabled = false;
5883 crtc->state->connector_mask = 0;
5884 crtc->state->encoder_mask = 0;
5885
5886 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5887 encoder->base.crtc = NULL;
5888
5889 intel_fbc_disable(intel_crtc);
5890 intel_update_watermarks(intel_crtc);
5891 intel_disable_shared_dpll(intel_crtc);
5892
5893 domains = intel_crtc->enabled_power_domains;
5894 for_each_power_domain(domain, domains)
5895 intel_display_power_put(dev_priv, domain);
5896 intel_crtc->enabled_power_domains = 0;
5897
5898 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5899 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5900 }
5901
5902 /*
5903 * turn all crtc's off, but do not adjust state
5904 * This has to be paired with a call to intel_modeset_setup_hw_state.
5905 */
5906 int intel_display_suspend(struct drm_device *dev)
5907 {
5908 struct drm_i915_private *dev_priv = to_i915(dev);
5909 struct drm_atomic_state *state;
5910 int ret;
5911
5912 state = drm_atomic_helper_suspend(dev);
5913 ret = PTR_ERR_OR_ZERO(state);
5914 if (ret)
5915 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5916 else
5917 dev_priv->modeset_restore_state = state;
5918 return ret;
5919 }
5920
5921 void intel_encoder_destroy(struct drm_encoder *encoder)
5922 {
5923 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5924
5925 drm_encoder_cleanup(encoder);
5926 kfree(intel_encoder);
5927 }
5928
5929 /* Cross check the actual hw state with our own modeset state tracking (and it's
5930 * internal consistency). */
5931 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5932 struct drm_connector_state *conn_state)
5933 {
5934 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5935
5936 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5937 connector->base.base.id,
5938 connector->base.name);
5939
5940 if (connector->get_hw_state(connector)) {
5941 struct intel_encoder *encoder = connector->encoder;
5942
5943 I915_STATE_WARN(!crtc_state,
5944 "connector enabled without attached crtc\n");
5945
5946 if (!crtc_state)
5947 return;
5948
5949 I915_STATE_WARN(!crtc_state->active,
5950 "connector is active, but attached crtc isn't\n");
5951
5952 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5953 return;
5954
5955 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5956 "atomic encoder doesn't match attached encoder\n");
5957
5958 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5959 "attached encoder crtc differs from connector crtc\n");
5960 } else {
5961 I915_STATE_WARN(crtc_state && crtc_state->active,
5962 "attached crtc is active, but connector isn't\n");
5963 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
5964 "best encoder set without crtc!\n");
5965 }
5966 }
5967
5968 int intel_connector_init(struct intel_connector *connector)
5969 {
5970 struct intel_digital_connector_state *conn_state;
5971
5972 /*
5973 * Allocate enough memory to hold intel_digital_connector_state,
5974 * This might be a few bytes too many, but for connectors that don't
5975 * need it we'll free the state and allocate a smaller one on the first
5976 * succesful commit anyway.
5977 */
5978 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
5979 if (!conn_state)
5980 return -ENOMEM;
5981
5982 __drm_atomic_helper_connector_reset(&connector->base,
5983 &conn_state->base);
5984
5985 return 0;
5986 }
5987
5988 struct intel_connector *intel_connector_alloc(void)
5989 {
5990 struct intel_connector *connector;
5991
5992 connector = kzalloc(sizeof *connector, GFP_KERNEL);
5993 if (!connector)
5994 return NULL;
5995
5996 if (intel_connector_init(connector) < 0) {
5997 kfree(connector);
5998 return NULL;
5999 }
6000
6001 return connector;
6002 }
6003
6004 /* Simple connector->get_hw_state implementation for encoders that support only
6005 * one connector and no cloning and hence the encoder state determines the state
6006 * of the connector. */
6007 bool intel_connector_get_hw_state(struct intel_connector *connector)
6008 {
6009 enum pipe pipe = 0;
6010 struct intel_encoder *encoder = connector->encoder;
6011
6012 return encoder->get_hw_state(encoder, &pipe);
6013 }
6014
6015 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6016 {
6017 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6018 return crtc_state->fdi_lanes;
6019
6020 return 0;
6021 }
6022
6023 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6024 struct intel_crtc_state *pipe_config)
6025 {
6026 struct drm_i915_private *dev_priv = to_i915(dev);
6027 struct drm_atomic_state *state = pipe_config->base.state;
6028 struct intel_crtc *other_crtc;
6029 struct intel_crtc_state *other_crtc_state;
6030
6031 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6032 pipe_name(pipe), pipe_config->fdi_lanes);
6033 if (pipe_config->fdi_lanes > 4) {
6034 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6035 pipe_name(pipe), pipe_config->fdi_lanes);
6036 return -EINVAL;
6037 }
6038
6039 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6040 if (pipe_config->fdi_lanes > 2) {
6041 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6042 pipe_config->fdi_lanes);
6043 return -EINVAL;
6044 } else {
6045 return 0;
6046 }
6047 }
6048
6049 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6050 return 0;
6051
6052 /* Ivybridge 3 pipe is really complicated */
6053 switch (pipe) {
6054 case PIPE_A:
6055 return 0;
6056 case PIPE_B:
6057 if (pipe_config->fdi_lanes <= 2)
6058 return 0;
6059
6060 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6061 other_crtc_state =
6062 intel_atomic_get_crtc_state(state, other_crtc);
6063 if (IS_ERR(other_crtc_state))
6064 return PTR_ERR(other_crtc_state);
6065
6066 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6067 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6068 pipe_name(pipe), pipe_config->fdi_lanes);
6069 return -EINVAL;
6070 }
6071 return 0;
6072 case PIPE_C:
6073 if (pipe_config->fdi_lanes > 2) {
6074 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6075 pipe_name(pipe), pipe_config->fdi_lanes);
6076 return -EINVAL;
6077 }
6078
6079 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6080 other_crtc_state =
6081 intel_atomic_get_crtc_state(state, other_crtc);
6082 if (IS_ERR(other_crtc_state))
6083 return PTR_ERR(other_crtc_state);
6084
6085 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6086 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6087 return -EINVAL;
6088 }
6089 return 0;
6090 default:
6091 BUG();
6092 }
6093 }
6094
6095 #define RETRY 1
6096 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6097 struct intel_crtc_state *pipe_config)
6098 {
6099 struct drm_device *dev = intel_crtc->base.dev;
6100 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6101 int lane, link_bw, fdi_dotclock, ret;
6102 bool needs_recompute = false;
6103
6104 retry:
6105 /* FDI is a binary signal running at ~2.7GHz, encoding
6106 * each output octet as 10 bits. The actual frequency
6107 * is stored as a divider into a 100MHz clock, and the
6108 * mode pixel clock is stored in units of 1KHz.
6109 * Hence the bw of each lane in terms of the mode signal
6110 * is:
6111 */
6112 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6113
6114 fdi_dotclock = adjusted_mode->crtc_clock;
6115
6116 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6117 pipe_config->pipe_bpp);
6118
6119 pipe_config->fdi_lanes = lane;
6120
6121 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6122 link_bw, &pipe_config->fdi_m_n, false);
6123
6124 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6125 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6126 pipe_config->pipe_bpp -= 2*3;
6127 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6128 pipe_config->pipe_bpp);
6129 needs_recompute = true;
6130 pipe_config->bw_constrained = true;
6131
6132 goto retry;
6133 }
6134
6135 if (needs_recompute)
6136 return RETRY;
6137
6138 return ret;
6139 }
6140
6141 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6142 struct intel_crtc_state *pipe_config)
6143 {
6144 if (pipe_config->pipe_bpp > 24)
6145 return false;
6146
6147 /* HSW can handle pixel rate up to cdclk? */
6148 if (IS_HASWELL(dev_priv))
6149 return true;
6150
6151 /*
6152 * We compare against max which means we must take
6153 * the increased cdclk requirement into account when
6154 * calculating the new cdclk.
6155 *
6156 * Should measure whether using a lower cdclk w/o IPS
6157 */
6158 return pipe_config->pixel_rate <=
6159 dev_priv->max_cdclk_freq * 95 / 100;
6160 }
6161
6162 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6163 struct intel_crtc_state *pipe_config)
6164 {
6165 struct drm_device *dev = crtc->base.dev;
6166 struct drm_i915_private *dev_priv = to_i915(dev);
6167
6168 pipe_config->ips_enabled = i915.enable_ips &&
6169 hsw_crtc_supports_ips(crtc) &&
6170 pipe_config_supports_ips(dev_priv, pipe_config);
6171 }
6172
6173 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6174 {
6175 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6176
6177 /* GDG double wide on either pipe, otherwise pipe A only */
6178 return INTEL_INFO(dev_priv)->gen < 4 &&
6179 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6180 }
6181
6182 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6183 {
6184 uint32_t pixel_rate;
6185
6186 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6187
6188 /*
6189 * We only use IF-ID interlacing. If we ever use
6190 * PF-ID we'll need to adjust the pixel_rate here.
6191 */
6192
6193 if (pipe_config->pch_pfit.enabled) {
6194 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6195 uint32_t pfit_size = pipe_config->pch_pfit.size;
6196
6197 pipe_w = pipe_config->pipe_src_w;
6198 pipe_h = pipe_config->pipe_src_h;
6199
6200 pfit_w = (pfit_size >> 16) & 0xFFFF;
6201 pfit_h = pfit_size & 0xFFFF;
6202 if (pipe_w < pfit_w)
6203 pipe_w = pfit_w;
6204 if (pipe_h < pfit_h)
6205 pipe_h = pfit_h;
6206
6207 if (WARN_ON(!pfit_w || !pfit_h))
6208 return pixel_rate;
6209
6210 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6211 pfit_w * pfit_h);
6212 }
6213
6214 return pixel_rate;
6215 }
6216
6217 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6218 {
6219 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6220
6221 if (HAS_GMCH_DISPLAY(dev_priv))
6222 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6223 crtc_state->pixel_rate =
6224 crtc_state->base.adjusted_mode.crtc_clock;
6225 else
6226 crtc_state->pixel_rate =
6227 ilk_pipe_pixel_rate(crtc_state);
6228 }
6229
6230 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6231 struct intel_crtc_state *pipe_config)
6232 {
6233 struct drm_device *dev = crtc->base.dev;
6234 struct drm_i915_private *dev_priv = to_i915(dev);
6235 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6236 int clock_limit = dev_priv->max_dotclk_freq;
6237
6238 if (INTEL_GEN(dev_priv) < 4) {
6239 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6240
6241 /*
6242 * Enable double wide mode when the dot clock
6243 * is > 90% of the (display) core speed.
6244 */
6245 if (intel_crtc_supports_double_wide(crtc) &&
6246 adjusted_mode->crtc_clock > clock_limit) {
6247 clock_limit = dev_priv->max_dotclk_freq;
6248 pipe_config->double_wide = true;
6249 }
6250 }
6251
6252 if (adjusted_mode->crtc_clock > clock_limit) {
6253 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6254 adjusted_mode->crtc_clock, clock_limit,
6255 yesno(pipe_config->double_wide));
6256 return -EINVAL;
6257 }
6258
6259 /*
6260 * Pipe horizontal size must be even in:
6261 * - DVO ganged mode
6262 * - LVDS dual channel mode
6263 * - Double wide pipe
6264 */
6265 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6266 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6267 pipe_config->pipe_src_w &= ~1;
6268
6269 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6270 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6271 */
6272 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6273 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6274 return -EINVAL;
6275
6276 intel_crtc_compute_pixel_rate(pipe_config);
6277
6278 if (HAS_IPS(dev_priv))
6279 hsw_compute_ips_config(crtc, pipe_config);
6280
6281 if (pipe_config->has_pch_encoder)
6282 return ironlake_fdi_compute_config(crtc, pipe_config);
6283
6284 return 0;
6285 }
6286
6287 static void
6288 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6289 {
6290 while (*num > DATA_LINK_M_N_MASK ||
6291 *den > DATA_LINK_M_N_MASK) {
6292 *num >>= 1;
6293 *den >>= 1;
6294 }
6295 }
6296
6297 static void compute_m_n(unsigned int m, unsigned int n,
6298 uint32_t *ret_m, uint32_t *ret_n,
6299 bool reduce_m_n)
6300 {
6301 /*
6302 * Reduce M/N as much as possible without loss in precision. Several DP
6303 * dongles in particular seem to be fussy about too large *link* M/N
6304 * values. The passed in values are more likely to have the least
6305 * significant bits zero than M after rounding below, so do this first.
6306 */
6307 if (reduce_m_n) {
6308 while ((m & 1) == 0 && (n & 1) == 0) {
6309 m >>= 1;
6310 n >>= 1;
6311 }
6312 }
6313
6314 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6315 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6316 intel_reduce_m_n_ratio(ret_m, ret_n);
6317 }
6318
6319 void
6320 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6321 int pixel_clock, int link_clock,
6322 struct intel_link_m_n *m_n,
6323 bool reduce_m_n)
6324 {
6325 m_n->tu = 64;
6326
6327 compute_m_n(bits_per_pixel * pixel_clock,
6328 link_clock * nlanes * 8,
6329 &m_n->gmch_m, &m_n->gmch_n,
6330 reduce_m_n);
6331
6332 compute_m_n(pixel_clock, link_clock,
6333 &m_n->link_m, &m_n->link_n,
6334 reduce_m_n);
6335 }
6336
6337 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6338 {
6339 if (i915.panel_use_ssc >= 0)
6340 return i915.panel_use_ssc != 0;
6341 return dev_priv->vbt.lvds_use_ssc
6342 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6343 }
6344
6345 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6346 {
6347 return (1 << dpll->n) << 16 | dpll->m2;
6348 }
6349
6350 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6351 {
6352 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6353 }
6354
6355 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6356 struct intel_crtc_state *crtc_state,
6357 struct dpll *reduced_clock)
6358 {
6359 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6360 u32 fp, fp2 = 0;
6361
6362 if (IS_PINEVIEW(dev_priv)) {
6363 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6364 if (reduced_clock)
6365 fp2 = pnv_dpll_compute_fp(reduced_clock);
6366 } else {
6367 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6368 if (reduced_clock)
6369 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6370 }
6371
6372 crtc_state->dpll_hw_state.fp0 = fp;
6373
6374 crtc->lowfreq_avail = false;
6375 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6376 reduced_clock) {
6377 crtc_state->dpll_hw_state.fp1 = fp2;
6378 crtc->lowfreq_avail = true;
6379 } else {
6380 crtc_state->dpll_hw_state.fp1 = fp;
6381 }
6382 }
6383
6384 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6385 pipe)
6386 {
6387 u32 reg_val;
6388
6389 /*
6390 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6391 * and set it to a reasonable value instead.
6392 */
6393 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6394 reg_val &= 0xffffff00;
6395 reg_val |= 0x00000030;
6396 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6397
6398 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6399 reg_val &= 0x00ffffff;
6400 reg_val |= 0x8c000000;
6401 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6402
6403 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6404 reg_val &= 0xffffff00;
6405 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6406
6407 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6408 reg_val &= 0x00ffffff;
6409 reg_val |= 0xb0000000;
6410 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6411 }
6412
6413 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6414 struct intel_link_m_n *m_n)
6415 {
6416 struct drm_device *dev = crtc->base.dev;
6417 struct drm_i915_private *dev_priv = to_i915(dev);
6418 int pipe = crtc->pipe;
6419
6420 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6421 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6422 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6423 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6424 }
6425
6426 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6427 struct intel_link_m_n *m_n,
6428 struct intel_link_m_n *m2_n2)
6429 {
6430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6431 int pipe = crtc->pipe;
6432 enum transcoder transcoder = crtc->config->cpu_transcoder;
6433
6434 if (INTEL_GEN(dev_priv) >= 5) {
6435 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6436 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6437 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6438 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6439 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6440 * for gen < 8) and if DRRS is supported (to make sure the
6441 * registers are not unnecessarily accessed).
6442 */
6443 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6444 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6445 I915_WRITE(PIPE_DATA_M2(transcoder),
6446 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6447 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6448 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6449 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6450 }
6451 } else {
6452 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6453 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6454 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6455 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6456 }
6457 }
6458
6459 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6460 {
6461 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6462
6463 if (m_n == M1_N1) {
6464 dp_m_n = &crtc->config->dp_m_n;
6465 dp_m2_n2 = &crtc->config->dp_m2_n2;
6466 } else if (m_n == M2_N2) {
6467
6468 /*
6469 * M2_N2 registers are not supported. Hence m2_n2 divider value
6470 * needs to be programmed into M1_N1.
6471 */
6472 dp_m_n = &crtc->config->dp_m2_n2;
6473 } else {
6474 DRM_ERROR("Unsupported divider value\n");
6475 return;
6476 }
6477
6478 if (crtc->config->has_pch_encoder)
6479 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6480 else
6481 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6482 }
6483
6484 static void vlv_compute_dpll(struct intel_crtc *crtc,
6485 struct intel_crtc_state *pipe_config)
6486 {
6487 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6488 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6489 if (crtc->pipe != PIPE_A)
6490 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6491
6492 /* DPLL not used with DSI, but still need the rest set up */
6493 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6494 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6495 DPLL_EXT_BUFFER_ENABLE_VLV;
6496
6497 pipe_config->dpll_hw_state.dpll_md =
6498 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6499 }
6500
6501 static void chv_compute_dpll(struct intel_crtc *crtc,
6502 struct intel_crtc_state *pipe_config)
6503 {
6504 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6505 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6506 if (crtc->pipe != PIPE_A)
6507 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6508
6509 /* DPLL not used with DSI, but still need the rest set up */
6510 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6511 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6512
6513 pipe_config->dpll_hw_state.dpll_md =
6514 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6515 }
6516
6517 static void vlv_prepare_pll(struct intel_crtc *crtc,
6518 const struct intel_crtc_state *pipe_config)
6519 {
6520 struct drm_device *dev = crtc->base.dev;
6521 struct drm_i915_private *dev_priv = to_i915(dev);
6522 enum pipe pipe = crtc->pipe;
6523 u32 mdiv;
6524 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6525 u32 coreclk, reg_val;
6526
6527 /* Enable Refclk */
6528 I915_WRITE(DPLL(pipe),
6529 pipe_config->dpll_hw_state.dpll &
6530 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6531
6532 /* No need to actually set up the DPLL with DSI */
6533 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6534 return;
6535
6536 mutex_lock(&dev_priv->sb_lock);
6537
6538 bestn = pipe_config->dpll.n;
6539 bestm1 = pipe_config->dpll.m1;
6540 bestm2 = pipe_config->dpll.m2;
6541 bestp1 = pipe_config->dpll.p1;
6542 bestp2 = pipe_config->dpll.p2;
6543
6544 /* See eDP HDMI DPIO driver vbios notes doc */
6545
6546 /* PLL B needs special handling */
6547 if (pipe == PIPE_B)
6548 vlv_pllb_recal_opamp(dev_priv, pipe);
6549
6550 /* Set up Tx target for periodic Rcomp update */
6551 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6552
6553 /* Disable target IRef on PLL */
6554 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6555 reg_val &= 0x00ffffff;
6556 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6557
6558 /* Disable fast lock */
6559 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6560
6561 /* Set idtafcrecal before PLL is enabled */
6562 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6563 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6564 mdiv |= ((bestn << DPIO_N_SHIFT));
6565 mdiv |= (1 << DPIO_K_SHIFT);
6566
6567 /*
6568 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6569 * but we don't support that).
6570 * Note: don't use the DAC post divider as it seems unstable.
6571 */
6572 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6573 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6574
6575 mdiv |= DPIO_ENABLE_CALIBRATION;
6576 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6577
6578 /* Set HBR and RBR LPF coefficients */
6579 if (pipe_config->port_clock == 162000 ||
6580 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6581 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6582 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6583 0x009f0003);
6584 else
6585 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6586 0x00d0000f);
6587
6588 if (intel_crtc_has_dp_encoder(pipe_config)) {
6589 /* Use SSC source */
6590 if (pipe == PIPE_A)
6591 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6592 0x0df40000);
6593 else
6594 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6595 0x0df70000);
6596 } else { /* HDMI or VGA */
6597 /* Use bend source */
6598 if (pipe == PIPE_A)
6599 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6600 0x0df70000);
6601 else
6602 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6603 0x0df40000);
6604 }
6605
6606 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6607 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6608 if (intel_crtc_has_dp_encoder(crtc->config))
6609 coreclk |= 0x01000000;
6610 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6611
6612 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6613 mutex_unlock(&dev_priv->sb_lock);
6614 }
6615
6616 static void chv_prepare_pll(struct intel_crtc *crtc,
6617 const struct intel_crtc_state *pipe_config)
6618 {
6619 struct drm_device *dev = crtc->base.dev;
6620 struct drm_i915_private *dev_priv = to_i915(dev);
6621 enum pipe pipe = crtc->pipe;
6622 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6623 u32 loopfilter, tribuf_calcntr;
6624 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6625 u32 dpio_val;
6626 int vco;
6627
6628 /* Enable Refclk and SSC */
6629 I915_WRITE(DPLL(pipe),
6630 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6631
6632 /* No need to actually set up the DPLL with DSI */
6633 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6634 return;
6635
6636 bestn = pipe_config->dpll.n;
6637 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6638 bestm1 = pipe_config->dpll.m1;
6639 bestm2 = pipe_config->dpll.m2 >> 22;
6640 bestp1 = pipe_config->dpll.p1;
6641 bestp2 = pipe_config->dpll.p2;
6642 vco = pipe_config->dpll.vco;
6643 dpio_val = 0;
6644 loopfilter = 0;
6645
6646 mutex_lock(&dev_priv->sb_lock);
6647
6648 /* p1 and p2 divider */
6649 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6650 5 << DPIO_CHV_S1_DIV_SHIFT |
6651 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6652 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6653 1 << DPIO_CHV_K_DIV_SHIFT);
6654
6655 /* Feedback post-divider - m2 */
6656 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6657
6658 /* Feedback refclk divider - n and m1 */
6659 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6660 DPIO_CHV_M1_DIV_BY_2 |
6661 1 << DPIO_CHV_N_DIV_SHIFT);
6662
6663 /* M2 fraction division */
6664 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6665
6666 /* M2 fraction division enable */
6667 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6668 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6669 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6670 if (bestm2_frac)
6671 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6672 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6673
6674 /* Program digital lock detect threshold */
6675 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6676 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6677 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6678 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6679 if (!bestm2_frac)
6680 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6681 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6682
6683 /* Loop filter */
6684 if (vco == 5400000) {
6685 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6686 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6687 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6688 tribuf_calcntr = 0x9;
6689 } else if (vco <= 6200000) {
6690 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6691 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6692 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6693 tribuf_calcntr = 0x9;
6694 } else if (vco <= 6480000) {
6695 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6696 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6697 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6698 tribuf_calcntr = 0x8;
6699 } else {
6700 /* Not supported. Apply the same limits as in the max case */
6701 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6702 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6703 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6704 tribuf_calcntr = 0;
6705 }
6706 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6707
6708 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6709 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6710 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6711 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6712
6713 /* AFC Recal */
6714 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6715 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6716 DPIO_AFC_RECAL);
6717
6718 mutex_unlock(&dev_priv->sb_lock);
6719 }
6720
6721 /**
6722 * vlv_force_pll_on - forcibly enable just the PLL
6723 * @dev_priv: i915 private structure
6724 * @pipe: pipe PLL to enable
6725 * @dpll: PLL configuration
6726 *
6727 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6728 * in cases where we need the PLL enabled even when @pipe is not going to
6729 * be enabled.
6730 */
6731 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6732 const struct dpll *dpll)
6733 {
6734 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6735 struct intel_crtc_state *pipe_config;
6736
6737 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6738 if (!pipe_config)
6739 return -ENOMEM;
6740
6741 pipe_config->base.crtc = &crtc->base;
6742 pipe_config->pixel_multiplier = 1;
6743 pipe_config->dpll = *dpll;
6744
6745 if (IS_CHERRYVIEW(dev_priv)) {
6746 chv_compute_dpll(crtc, pipe_config);
6747 chv_prepare_pll(crtc, pipe_config);
6748 chv_enable_pll(crtc, pipe_config);
6749 } else {
6750 vlv_compute_dpll(crtc, pipe_config);
6751 vlv_prepare_pll(crtc, pipe_config);
6752 vlv_enable_pll(crtc, pipe_config);
6753 }
6754
6755 kfree(pipe_config);
6756
6757 return 0;
6758 }
6759
6760 /**
6761 * vlv_force_pll_off - forcibly disable just the PLL
6762 * @dev_priv: i915 private structure
6763 * @pipe: pipe PLL to disable
6764 *
6765 * Disable the PLL for @pipe. To be used in cases where we need
6766 * the PLL enabled even when @pipe is not going to be enabled.
6767 */
6768 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6769 {
6770 if (IS_CHERRYVIEW(dev_priv))
6771 chv_disable_pll(dev_priv, pipe);
6772 else
6773 vlv_disable_pll(dev_priv, pipe);
6774 }
6775
6776 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6777 struct intel_crtc_state *crtc_state,
6778 struct dpll *reduced_clock)
6779 {
6780 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6781 u32 dpll;
6782 struct dpll *clock = &crtc_state->dpll;
6783
6784 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6785
6786 dpll = DPLL_VGA_MODE_DIS;
6787
6788 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6789 dpll |= DPLLB_MODE_LVDS;
6790 else
6791 dpll |= DPLLB_MODE_DAC_SERIAL;
6792
6793 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6794 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6795 dpll |= (crtc_state->pixel_multiplier - 1)
6796 << SDVO_MULTIPLIER_SHIFT_HIRES;
6797 }
6798
6799 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6800 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6801 dpll |= DPLL_SDVO_HIGH_SPEED;
6802
6803 if (intel_crtc_has_dp_encoder(crtc_state))
6804 dpll |= DPLL_SDVO_HIGH_SPEED;
6805
6806 /* compute bitmask from p1 value */
6807 if (IS_PINEVIEW(dev_priv))
6808 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6809 else {
6810 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6811 if (IS_G4X(dev_priv) && reduced_clock)
6812 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6813 }
6814 switch (clock->p2) {
6815 case 5:
6816 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6817 break;
6818 case 7:
6819 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6820 break;
6821 case 10:
6822 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6823 break;
6824 case 14:
6825 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6826 break;
6827 }
6828 if (INTEL_GEN(dev_priv) >= 4)
6829 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6830
6831 if (crtc_state->sdvo_tv_clock)
6832 dpll |= PLL_REF_INPUT_TVCLKINBC;
6833 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6834 intel_panel_use_ssc(dev_priv))
6835 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6836 else
6837 dpll |= PLL_REF_INPUT_DREFCLK;
6838
6839 dpll |= DPLL_VCO_ENABLE;
6840 crtc_state->dpll_hw_state.dpll = dpll;
6841
6842 if (INTEL_GEN(dev_priv) >= 4) {
6843 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6844 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6845 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6846 }
6847 }
6848
6849 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6850 struct intel_crtc_state *crtc_state,
6851 struct dpll *reduced_clock)
6852 {
6853 struct drm_device *dev = crtc->base.dev;
6854 struct drm_i915_private *dev_priv = to_i915(dev);
6855 u32 dpll;
6856 struct dpll *clock = &crtc_state->dpll;
6857
6858 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6859
6860 dpll = DPLL_VGA_MODE_DIS;
6861
6862 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6863 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6864 } else {
6865 if (clock->p1 == 2)
6866 dpll |= PLL_P1_DIVIDE_BY_TWO;
6867 else
6868 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6869 if (clock->p2 == 4)
6870 dpll |= PLL_P2_DIVIDE_BY_4;
6871 }
6872
6873 if (!IS_I830(dev_priv) &&
6874 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6875 dpll |= DPLL_DVO_2X_MODE;
6876
6877 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6878 intel_panel_use_ssc(dev_priv))
6879 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6880 else
6881 dpll |= PLL_REF_INPUT_DREFCLK;
6882
6883 dpll |= DPLL_VCO_ENABLE;
6884 crtc_state->dpll_hw_state.dpll = dpll;
6885 }
6886
6887 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6888 {
6889 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6890 enum pipe pipe = intel_crtc->pipe;
6891 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6892 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6893 uint32_t crtc_vtotal, crtc_vblank_end;
6894 int vsyncshift = 0;
6895
6896 /* We need to be careful not to changed the adjusted mode, for otherwise
6897 * the hw state checker will get angry at the mismatch. */
6898 crtc_vtotal = adjusted_mode->crtc_vtotal;
6899 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6900
6901 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6902 /* the chip adds 2 halflines automatically */
6903 crtc_vtotal -= 1;
6904 crtc_vblank_end -= 1;
6905
6906 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6907 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6908 else
6909 vsyncshift = adjusted_mode->crtc_hsync_start -
6910 adjusted_mode->crtc_htotal / 2;
6911 if (vsyncshift < 0)
6912 vsyncshift += adjusted_mode->crtc_htotal;
6913 }
6914
6915 if (INTEL_GEN(dev_priv) > 3)
6916 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6917
6918 I915_WRITE(HTOTAL(cpu_transcoder),
6919 (adjusted_mode->crtc_hdisplay - 1) |
6920 ((adjusted_mode->crtc_htotal - 1) << 16));
6921 I915_WRITE(HBLANK(cpu_transcoder),
6922 (adjusted_mode->crtc_hblank_start - 1) |
6923 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6924 I915_WRITE(HSYNC(cpu_transcoder),
6925 (adjusted_mode->crtc_hsync_start - 1) |
6926 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6927
6928 I915_WRITE(VTOTAL(cpu_transcoder),
6929 (adjusted_mode->crtc_vdisplay - 1) |
6930 ((crtc_vtotal - 1) << 16));
6931 I915_WRITE(VBLANK(cpu_transcoder),
6932 (adjusted_mode->crtc_vblank_start - 1) |
6933 ((crtc_vblank_end - 1) << 16));
6934 I915_WRITE(VSYNC(cpu_transcoder),
6935 (adjusted_mode->crtc_vsync_start - 1) |
6936 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6937
6938 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6939 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6940 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6941 * bits. */
6942 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6943 (pipe == PIPE_B || pipe == PIPE_C))
6944 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6945
6946 }
6947
6948 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6949 {
6950 struct drm_device *dev = intel_crtc->base.dev;
6951 struct drm_i915_private *dev_priv = to_i915(dev);
6952 enum pipe pipe = intel_crtc->pipe;
6953
6954 /* pipesrc controls the size that is scaled from, which should
6955 * always be the user's requested size.
6956 */
6957 I915_WRITE(PIPESRC(pipe),
6958 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6959 (intel_crtc->config->pipe_src_h - 1));
6960 }
6961
6962 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6963 struct intel_crtc_state *pipe_config)
6964 {
6965 struct drm_device *dev = crtc->base.dev;
6966 struct drm_i915_private *dev_priv = to_i915(dev);
6967 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6968 uint32_t tmp;
6969
6970 tmp = I915_READ(HTOTAL(cpu_transcoder));
6971 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6972 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6973 tmp = I915_READ(HBLANK(cpu_transcoder));
6974 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6975 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6976 tmp = I915_READ(HSYNC(cpu_transcoder));
6977 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6978 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6979
6980 tmp = I915_READ(VTOTAL(cpu_transcoder));
6981 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6982 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6983 tmp = I915_READ(VBLANK(cpu_transcoder));
6984 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6985 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6986 tmp = I915_READ(VSYNC(cpu_transcoder));
6987 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6988 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6989
6990 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6991 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6992 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6993 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6994 }
6995 }
6996
6997 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6998 struct intel_crtc_state *pipe_config)
6999 {
7000 struct drm_device *dev = crtc->base.dev;
7001 struct drm_i915_private *dev_priv = to_i915(dev);
7002 u32 tmp;
7003
7004 tmp = I915_READ(PIPESRC(crtc->pipe));
7005 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7006 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7007
7008 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7009 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7010 }
7011
7012 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7013 struct intel_crtc_state *pipe_config)
7014 {
7015 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7016 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7017 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7018 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7019
7020 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7021 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7022 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7023 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7024
7025 mode->flags = pipe_config->base.adjusted_mode.flags;
7026 mode->type = DRM_MODE_TYPE_DRIVER;
7027
7028 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7029
7030 mode->hsync = drm_mode_hsync(mode);
7031 mode->vrefresh = drm_mode_vrefresh(mode);
7032 drm_mode_set_name(mode);
7033 }
7034
7035 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7036 {
7037 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7038 uint32_t pipeconf;
7039
7040 pipeconf = 0;
7041
7042 /* we keep both pipes enabled on 830 */
7043 if (IS_I830(dev_priv))
7044 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7045
7046 if (intel_crtc->config->double_wide)
7047 pipeconf |= PIPECONF_DOUBLE_WIDE;
7048
7049 /* only g4x and later have fancy bpc/dither controls */
7050 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7051 IS_CHERRYVIEW(dev_priv)) {
7052 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7053 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7054 pipeconf |= PIPECONF_DITHER_EN |
7055 PIPECONF_DITHER_TYPE_SP;
7056
7057 switch (intel_crtc->config->pipe_bpp) {
7058 case 18:
7059 pipeconf |= PIPECONF_6BPC;
7060 break;
7061 case 24:
7062 pipeconf |= PIPECONF_8BPC;
7063 break;
7064 case 30:
7065 pipeconf |= PIPECONF_10BPC;
7066 break;
7067 default:
7068 /* Case prevented by intel_choose_pipe_bpp_dither. */
7069 BUG();
7070 }
7071 }
7072
7073 if (HAS_PIPE_CXSR(dev_priv)) {
7074 if (intel_crtc->lowfreq_avail) {
7075 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7076 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7077 } else {
7078 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7079 }
7080 }
7081
7082 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7083 if (INTEL_GEN(dev_priv) < 4 ||
7084 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7085 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7086 else
7087 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7088 } else
7089 pipeconf |= PIPECONF_PROGRESSIVE;
7090
7091 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7092 intel_crtc->config->limited_color_range)
7093 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7094
7095 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7096 POSTING_READ(PIPECONF(intel_crtc->pipe));
7097 }
7098
7099 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7100 struct intel_crtc_state *crtc_state)
7101 {
7102 struct drm_device *dev = crtc->base.dev;
7103 struct drm_i915_private *dev_priv = to_i915(dev);
7104 const struct intel_limit *limit;
7105 int refclk = 48000;
7106
7107 memset(&crtc_state->dpll_hw_state, 0,
7108 sizeof(crtc_state->dpll_hw_state));
7109
7110 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7111 if (intel_panel_use_ssc(dev_priv)) {
7112 refclk = dev_priv->vbt.lvds_ssc_freq;
7113 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7114 }
7115
7116 limit = &intel_limits_i8xx_lvds;
7117 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7118 limit = &intel_limits_i8xx_dvo;
7119 } else {
7120 limit = &intel_limits_i8xx_dac;
7121 }
7122
7123 if (!crtc_state->clock_set &&
7124 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7125 refclk, NULL, &crtc_state->dpll)) {
7126 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7127 return -EINVAL;
7128 }
7129
7130 i8xx_compute_dpll(crtc, crtc_state, NULL);
7131
7132 return 0;
7133 }
7134
7135 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7136 struct intel_crtc_state *crtc_state)
7137 {
7138 struct drm_device *dev = crtc->base.dev;
7139 struct drm_i915_private *dev_priv = to_i915(dev);
7140 const struct intel_limit *limit;
7141 int refclk = 96000;
7142
7143 memset(&crtc_state->dpll_hw_state, 0,
7144 sizeof(crtc_state->dpll_hw_state));
7145
7146 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7147 if (intel_panel_use_ssc(dev_priv)) {
7148 refclk = dev_priv->vbt.lvds_ssc_freq;
7149 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7150 }
7151
7152 if (intel_is_dual_link_lvds(dev))
7153 limit = &intel_limits_g4x_dual_channel_lvds;
7154 else
7155 limit = &intel_limits_g4x_single_channel_lvds;
7156 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7157 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7158 limit = &intel_limits_g4x_hdmi;
7159 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7160 limit = &intel_limits_g4x_sdvo;
7161 } else {
7162 /* The option is for other outputs */
7163 limit = &intel_limits_i9xx_sdvo;
7164 }
7165
7166 if (!crtc_state->clock_set &&
7167 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7168 refclk, NULL, &crtc_state->dpll)) {
7169 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7170 return -EINVAL;
7171 }
7172
7173 i9xx_compute_dpll(crtc, crtc_state, NULL);
7174
7175 return 0;
7176 }
7177
7178 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7179 struct intel_crtc_state *crtc_state)
7180 {
7181 struct drm_device *dev = crtc->base.dev;
7182 struct drm_i915_private *dev_priv = to_i915(dev);
7183 const struct intel_limit *limit;
7184 int refclk = 96000;
7185
7186 memset(&crtc_state->dpll_hw_state, 0,
7187 sizeof(crtc_state->dpll_hw_state));
7188
7189 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7190 if (intel_panel_use_ssc(dev_priv)) {
7191 refclk = dev_priv->vbt.lvds_ssc_freq;
7192 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7193 }
7194
7195 limit = &intel_limits_pineview_lvds;
7196 } else {
7197 limit = &intel_limits_pineview_sdvo;
7198 }
7199
7200 if (!crtc_state->clock_set &&
7201 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7202 refclk, NULL, &crtc_state->dpll)) {
7203 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7204 return -EINVAL;
7205 }
7206
7207 i9xx_compute_dpll(crtc, crtc_state, NULL);
7208
7209 return 0;
7210 }
7211
7212 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7213 struct intel_crtc_state *crtc_state)
7214 {
7215 struct drm_device *dev = crtc->base.dev;
7216 struct drm_i915_private *dev_priv = to_i915(dev);
7217 const struct intel_limit *limit;
7218 int refclk = 96000;
7219
7220 memset(&crtc_state->dpll_hw_state, 0,
7221 sizeof(crtc_state->dpll_hw_state));
7222
7223 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7224 if (intel_panel_use_ssc(dev_priv)) {
7225 refclk = dev_priv->vbt.lvds_ssc_freq;
7226 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7227 }
7228
7229 limit = &intel_limits_i9xx_lvds;
7230 } else {
7231 limit = &intel_limits_i9xx_sdvo;
7232 }
7233
7234 if (!crtc_state->clock_set &&
7235 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7236 refclk, NULL, &crtc_state->dpll)) {
7237 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7238 return -EINVAL;
7239 }
7240
7241 i9xx_compute_dpll(crtc, crtc_state, NULL);
7242
7243 return 0;
7244 }
7245
7246 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7247 struct intel_crtc_state *crtc_state)
7248 {
7249 int refclk = 100000;
7250 const struct intel_limit *limit = &intel_limits_chv;
7251
7252 memset(&crtc_state->dpll_hw_state, 0,
7253 sizeof(crtc_state->dpll_hw_state));
7254
7255 if (!crtc_state->clock_set &&
7256 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7257 refclk, NULL, &crtc_state->dpll)) {
7258 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7259 return -EINVAL;
7260 }
7261
7262 chv_compute_dpll(crtc, crtc_state);
7263
7264 return 0;
7265 }
7266
7267 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7268 struct intel_crtc_state *crtc_state)
7269 {
7270 int refclk = 100000;
7271 const struct intel_limit *limit = &intel_limits_vlv;
7272
7273 memset(&crtc_state->dpll_hw_state, 0,
7274 sizeof(crtc_state->dpll_hw_state));
7275
7276 if (!crtc_state->clock_set &&
7277 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7278 refclk, NULL, &crtc_state->dpll)) {
7279 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7280 return -EINVAL;
7281 }
7282
7283 vlv_compute_dpll(crtc, crtc_state);
7284
7285 return 0;
7286 }
7287
7288 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7289 struct intel_crtc_state *pipe_config)
7290 {
7291 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7292 uint32_t tmp;
7293
7294 if (INTEL_GEN(dev_priv) <= 3 &&
7295 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7296 return;
7297
7298 tmp = I915_READ(PFIT_CONTROL);
7299 if (!(tmp & PFIT_ENABLE))
7300 return;
7301
7302 /* Check whether the pfit is attached to our pipe. */
7303 if (INTEL_GEN(dev_priv) < 4) {
7304 if (crtc->pipe != PIPE_B)
7305 return;
7306 } else {
7307 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7308 return;
7309 }
7310
7311 pipe_config->gmch_pfit.control = tmp;
7312 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7313 }
7314
7315 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7316 struct intel_crtc_state *pipe_config)
7317 {
7318 struct drm_device *dev = crtc->base.dev;
7319 struct drm_i915_private *dev_priv = to_i915(dev);
7320 int pipe = pipe_config->cpu_transcoder;
7321 struct dpll clock;
7322 u32 mdiv;
7323 int refclk = 100000;
7324
7325 /* In case of DSI, DPLL will not be used */
7326 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7327 return;
7328
7329 mutex_lock(&dev_priv->sb_lock);
7330 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7331 mutex_unlock(&dev_priv->sb_lock);
7332
7333 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7334 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7335 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7336 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7337 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7338
7339 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7340 }
7341
7342 static void
7343 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7344 struct intel_initial_plane_config *plane_config)
7345 {
7346 struct drm_device *dev = crtc->base.dev;
7347 struct drm_i915_private *dev_priv = to_i915(dev);
7348 u32 val, base, offset;
7349 int pipe = crtc->pipe, plane = crtc->plane;
7350 int fourcc, pixel_format;
7351 unsigned int aligned_height;
7352 struct drm_framebuffer *fb;
7353 struct intel_framebuffer *intel_fb;
7354
7355 val = I915_READ(DSPCNTR(plane));
7356 if (!(val & DISPLAY_PLANE_ENABLE))
7357 return;
7358
7359 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7360 if (!intel_fb) {
7361 DRM_DEBUG_KMS("failed to alloc fb\n");
7362 return;
7363 }
7364
7365 fb = &intel_fb->base;
7366
7367 fb->dev = dev;
7368
7369 if (INTEL_GEN(dev_priv) >= 4) {
7370 if (val & DISPPLANE_TILED) {
7371 plane_config->tiling = I915_TILING_X;
7372 fb->modifier = I915_FORMAT_MOD_X_TILED;
7373 }
7374 }
7375
7376 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7377 fourcc = i9xx_format_to_fourcc(pixel_format);
7378 fb->format = drm_format_info(fourcc);
7379
7380 if (INTEL_GEN(dev_priv) >= 4) {
7381 if (plane_config->tiling)
7382 offset = I915_READ(DSPTILEOFF(plane));
7383 else
7384 offset = I915_READ(DSPLINOFF(plane));
7385 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7386 } else {
7387 base = I915_READ(DSPADDR(plane));
7388 }
7389 plane_config->base = base;
7390
7391 val = I915_READ(PIPESRC(pipe));
7392 fb->width = ((val >> 16) & 0xfff) + 1;
7393 fb->height = ((val >> 0) & 0xfff) + 1;
7394
7395 val = I915_READ(DSPSTRIDE(pipe));
7396 fb->pitches[0] = val & 0xffffffc0;
7397
7398 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7399
7400 plane_config->size = fb->pitches[0] * aligned_height;
7401
7402 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7403 pipe_name(pipe), plane, fb->width, fb->height,
7404 fb->format->cpp[0] * 8, base, fb->pitches[0],
7405 plane_config->size);
7406
7407 plane_config->fb = intel_fb;
7408 }
7409
7410 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7411 struct intel_crtc_state *pipe_config)
7412 {
7413 struct drm_device *dev = crtc->base.dev;
7414 struct drm_i915_private *dev_priv = to_i915(dev);
7415 int pipe = pipe_config->cpu_transcoder;
7416 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7417 struct dpll clock;
7418 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7419 int refclk = 100000;
7420
7421 /* In case of DSI, DPLL will not be used */
7422 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7423 return;
7424
7425 mutex_lock(&dev_priv->sb_lock);
7426 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7427 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7428 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7429 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7430 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7431 mutex_unlock(&dev_priv->sb_lock);
7432
7433 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7434 clock.m2 = (pll_dw0 & 0xff) << 22;
7435 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7436 clock.m2 |= pll_dw2 & 0x3fffff;
7437 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7438 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7439 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7440
7441 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7442 }
7443
7444 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7445 struct intel_crtc_state *pipe_config)
7446 {
7447 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7448 enum intel_display_power_domain power_domain;
7449 uint32_t tmp;
7450 bool ret;
7451
7452 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7453 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7454 return false;
7455
7456 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7457 pipe_config->shared_dpll = NULL;
7458
7459 ret = false;
7460
7461 tmp = I915_READ(PIPECONF(crtc->pipe));
7462 if (!(tmp & PIPECONF_ENABLE))
7463 goto out;
7464
7465 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7466 IS_CHERRYVIEW(dev_priv)) {
7467 switch (tmp & PIPECONF_BPC_MASK) {
7468 case PIPECONF_6BPC:
7469 pipe_config->pipe_bpp = 18;
7470 break;
7471 case PIPECONF_8BPC:
7472 pipe_config->pipe_bpp = 24;
7473 break;
7474 case PIPECONF_10BPC:
7475 pipe_config->pipe_bpp = 30;
7476 break;
7477 default:
7478 break;
7479 }
7480 }
7481
7482 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7483 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7484 pipe_config->limited_color_range = true;
7485
7486 if (INTEL_GEN(dev_priv) < 4)
7487 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7488
7489 intel_get_pipe_timings(crtc, pipe_config);
7490 intel_get_pipe_src_size(crtc, pipe_config);
7491
7492 i9xx_get_pfit_config(crtc, pipe_config);
7493
7494 if (INTEL_GEN(dev_priv) >= 4) {
7495 /* No way to read it out on pipes B and C */
7496 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7497 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7498 else
7499 tmp = I915_READ(DPLL_MD(crtc->pipe));
7500 pipe_config->pixel_multiplier =
7501 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7502 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7503 pipe_config->dpll_hw_state.dpll_md = tmp;
7504 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7505 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7506 tmp = I915_READ(DPLL(crtc->pipe));
7507 pipe_config->pixel_multiplier =
7508 ((tmp & SDVO_MULTIPLIER_MASK)
7509 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7510 } else {
7511 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7512 * port and will be fixed up in the encoder->get_config
7513 * function. */
7514 pipe_config->pixel_multiplier = 1;
7515 }
7516 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7517 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7518 /*
7519 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7520 * on 830. Filter it out here so that we don't
7521 * report errors due to that.
7522 */
7523 if (IS_I830(dev_priv))
7524 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7525
7526 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7527 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7528 } else {
7529 /* Mask out read-only status bits. */
7530 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7531 DPLL_PORTC_READY_MASK |
7532 DPLL_PORTB_READY_MASK);
7533 }
7534
7535 if (IS_CHERRYVIEW(dev_priv))
7536 chv_crtc_clock_get(crtc, pipe_config);
7537 else if (IS_VALLEYVIEW(dev_priv))
7538 vlv_crtc_clock_get(crtc, pipe_config);
7539 else
7540 i9xx_crtc_clock_get(crtc, pipe_config);
7541
7542 /*
7543 * Normally the dotclock is filled in by the encoder .get_config()
7544 * but in case the pipe is enabled w/o any ports we need a sane
7545 * default.
7546 */
7547 pipe_config->base.adjusted_mode.crtc_clock =
7548 pipe_config->port_clock / pipe_config->pixel_multiplier;
7549
7550 ret = true;
7551
7552 out:
7553 intel_display_power_put(dev_priv, power_domain);
7554
7555 return ret;
7556 }
7557
7558 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7559 {
7560 struct intel_encoder *encoder;
7561 int i;
7562 u32 val, final;
7563 bool has_lvds = false;
7564 bool has_cpu_edp = false;
7565 bool has_panel = false;
7566 bool has_ck505 = false;
7567 bool can_ssc = false;
7568 bool using_ssc_source = false;
7569
7570 /* We need to take the global config into account */
7571 for_each_intel_encoder(&dev_priv->drm, encoder) {
7572 switch (encoder->type) {
7573 case INTEL_OUTPUT_LVDS:
7574 has_panel = true;
7575 has_lvds = true;
7576 break;
7577 case INTEL_OUTPUT_EDP:
7578 has_panel = true;
7579 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7580 has_cpu_edp = true;
7581 break;
7582 default:
7583 break;
7584 }
7585 }
7586
7587 if (HAS_PCH_IBX(dev_priv)) {
7588 has_ck505 = dev_priv->vbt.display_clock_mode;
7589 can_ssc = has_ck505;
7590 } else {
7591 has_ck505 = false;
7592 can_ssc = true;
7593 }
7594
7595 /* Check if any DPLLs are using the SSC source */
7596 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7597 u32 temp = I915_READ(PCH_DPLL(i));
7598
7599 if (!(temp & DPLL_VCO_ENABLE))
7600 continue;
7601
7602 if ((temp & PLL_REF_INPUT_MASK) ==
7603 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7604 using_ssc_source = true;
7605 break;
7606 }
7607 }
7608
7609 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7610 has_panel, has_lvds, has_ck505, using_ssc_source);
7611
7612 /* Ironlake: try to setup display ref clock before DPLL
7613 * enabling. This is only under driver's control after
7614 * PCH B stepping, previous chipset stepping should be
7615 * ignoring this setting.
7616 */
7617 val = I915_READ(PCH_DREF_CONTROL);
7618
7619 /* As we must carefully and slowly disable/enable each source in turn,
7620 * compute the final state we want first and check if we need to
7621 * make any changes at all.
7622 */
7623 final = val;
7624 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7625 if (has_ck505)
7626 final |= DREF_NONSPREAD_CK505_ENABLE;
7627 else
7628 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7629
7630 final &= ~DREF_SSC_SOURCE_MASK;
7631 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7632 final &= ~DREF_SSC1_ENABLE;
7633
7634 if (has_panel) {
7635 final |= DREF_SSC_SOURCE_ENABLE;
7636
7637 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7638 final |= DREF_SSC1_ENABLE;
7639
7640 if (has_cpu_edp) {
7641 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7642 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7643 else
7644 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7645 } else
7646 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7647 } else if (using_ssc_source) {
7648 final |= DREF_SSC_SOURCE_ENABLE;
7649 final |= DREF_SSC1_ENABLE;
7650 }
7651
7652 if (final == val)
7653 return;
7654
7655 /* Always enable nonspread source */
7656 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7657
7658 if (has_ck505)
7659 val |= DREF_NONSPREAD_CK505_ENABLE;
7660 else
7661 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7662
7663 if (has_panel) {
7664 val &= ~DREF_SSC_SOURCE_MASK;
7665 val |= DREF_SSC_SOURCE_ENABLE;
7666
7667 /* SSC must be turned on before enabling the CPU output */
7668 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7669 DRM_DEBUG_KMS("Using SSC on panel\n");
7670 val |= DREF_SSC1_ENABLE;
7671 } else
7672 val &= ~DREF_SSC1_ENABLE;
7673
7674 /* Get SSC going before enabling the outputs */
7675 I915_WRITE(PCH_DREF_CONTROL, val);
7676 POSTING_READ(PCH_DREF_CONTROL);
7677 udelay(200);
7678
7679 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7680
7681 /* Enable CPU source on CPU attached eDP */
7682 if (has_cpu_edp) {
7683 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7684 DRM_DEBUG_KMS("Using SSC on eDP\n");
7685 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7686 } else
7687 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7688 } else
7689 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7690
7691 I915_WRITE(PCH_DREF_CONTROL, val);
7692 POSTING_READ(PCH_DREF_CONTROL);
7693 udelay(200);
7694 } else {
7695 DRM_DEBUG_KMS("Disabling CPU source output\n");
7696
7697 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7698
7699 /* Turn off CPU output */
7700 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7701
7702 I915_WRITE(PCH_DREF_CONTROL, val);
7703 POSTING_READ(PCH_DREF_CONTROL);
7704 udelay(200);
7705
7706 if (!using_ssc_source) {
7707 DRM_DEBUG_KMS("Disabling SSC source\n");
7708
7709 /* Turn off the SSC source */
7710 val &= ~DREF_SSC_SOURCE_MASK;
7711 val |= DREF_SSC_SOURCE_DISABLE;
7712
7713 /* Turn off SSC1 */
7714 val &= ~DREF_SSC1_ENABLE;
7715
7716 I915_WRITE(PCH_DREF_CONTROL, val);
7717 POSTING_READ(PCH_DREF_CONTROL);
7718 udelay(200);
7719 }
7720 }
7721
7722 BUG_ON(val != final);
7723 }
7724
7725 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7726 {
7727 uint32_t tmp;
7728
7729 tmp = I915_READ(SOUTH_CHICKEN2);
7730 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7731 I915_WRITE(SOUTH_CHICKEN2, tmp);
7732
7733 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7734 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7735 DRM_ERROR("FDI mPHY reset assert timeout\n");
7736
7737 tmp = I915_READ(SOUTH_CHICKEN2);
7738 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7739 I915_WRITE(SOUTH_CHICKEN2, tmp);
7740
7741 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7742 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7743 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7744 }
7745
7746 /* WaMPhyProgramming:hsw */
7747 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7748 {
7749 uint32_t tmp;
7750
7751 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7752 tmp &= ~(0xFF << 24);
7753 tmp |= (0x12 << 24);
7754 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7755
7756 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7757 tmp |= (1 << 11);
7758 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7759
7760 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7761 tmp |= (1 << 11);
7762 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7763
7764 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7765 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7766 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7767
7768 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7769 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7770 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7771
7772 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7773 tmp &= ~(7 << 13);
7774 tmp |= (5 << 13);
7775 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7776
7777 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7778 tmp &= ~(7 << 13);
7779 tmp |= (5 << 13);
7780 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7781
7782 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7783 tmp &= ~0xFF;
7784 tmp |= 0x1C;
7785 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7786
7787 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7788 tmp &= ~0xFF;
7789 tmp |= 0x1C;
7790 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7791
7792 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7793 tmp &= ~(0xFF << 16);
7794 tmp |= (0x1C << 16);
7795 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7796
7797 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7798 tmp &= ~(0xFF << 16);
7799 tmp |= (0x1C << 16);
7800 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7801
7802 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7803 tmp |= (1 << 27);
7804 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7805
7806 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7807 tmp |= (1 << 27);
7808 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7809
7810 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7811 tmp &= ~(0xF << 28);
7812 tmp |= (4 << 28);
7813 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7814
7815 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7816 tmp &= ~(0xF << 28);
7817 tmp |= (4 << 28);
7818 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7819 }
7820
7821 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7822 * Programming" based on the parameters passed:
7823 * - Sequence to enable CLKOUT_DP
7824 * - Sequence to enable CLKOUT_DP without spread
7825 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7826 */
7827 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7828 bool with_spread, bool with_fdi)
7829 {
7830 uint32_t reg, tmp;
7831
7832 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7833 with_spread = true;
7834 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7835 with_fdi, "LP PCH doesn't have FDI\n"))
7836 with_fdi = false;
7837
7838 mutex_lock(&dev_priv->sb_lock);
7839
7840 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7841 tmp &= ~SBI_SSCCTL_DISABLE;
7842 tmp |= SBI_SSCCTL_PATHALT;
7843 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7844
7845 udelay(24);
7846
7847 if (with_spread) {
7848 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7849 tmp &= ~SBI_SSCCTL_PATHALT;
7850 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7851
7852 if (with_fdi) {
7853 lpt_reset_fdi_mphy(dev_priv);
7854 lpt_program_fdi_mphy(dev_priv);
7855 }
7856 }
7857
7858 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7859 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7860 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7861 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7862
7863 mutex_unlock(&dev_priv->sb_lock);
7864 }
7865
7866 /* Sequence to disable CLKOUT_DP */
7867 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7868 {
7869 uint32_t reg, tmp;
7870
7871 mutex_lock(&dev_priv->sb_lock);
7872
7873 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7874 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7875 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7876 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7877
7878 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7879 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7880 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7881 tmp |= SBI_SSCCTL_PATHALT;
7882 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7883 udelay(32);
7884 }
7885 tmp |= SBI_SSCCTL_DISABLE;
7886 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7887 }
7888
7889 mutex_unlock(&dev_priv->sb_lock);
7890 }
7891
7892 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7893
7894 static const uint16_t sscdivintphase[] = {
7895 [BEND_IDX( 50)] = 0x3B23,
7896 [BEND_IDX( 45)] = 0x3B23,
7897 [BEND_IDX( 40)] = 0x3C23,
7898 [BEND_IDX( 35)] = 0x3C23,
7899 [BEND_IDX( 30)] = 0x3D23,
7900 [BEND_IDX( 25)] = 0x3D23,
7901 [BEND_IDX( 20)] = 0x3E23,
7902 [BEND_IDX( 15)] = 0x3E23,
7903 [BEND_IDX( 10)] = 0x3F23,
7904 [BEND_IDX( 5)] = 0x3F23,
7905 [BEND_IDX( 0)] = 0x0025,
7906 [BEND_IDX( -5)] = 0x0025,
7907 [BEND_IDX(-10)] = 0x0125,
7908 [BEND_IDX(-15)] = 0x0125,
7909 [BEND_IDX(-20)] = 0x0225,
7910 [BEND_IDX(-25)] = 0x0225,
7911 [BEND_IDX(-30)] = 0x0325,
7912 [BEND_IDX(-35)] = 0x0325,
7913 [BEND_IDX(-40)] = 0x0425,
7914 [BEND_IDX(-45)] = 0x0425,
7915 [BEND_IDX(-50)] = 0x0525,
7916 };
7917
7918 /*
7919 * Bend CLKOUT_DP
7920 * steps -50 to 50 inclusive, in steps of 5
7921 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7922 * change in clock period = -(steps / 10) * 5.787 ps
7923 */
7924 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7925 {
7926 uint32_t tmp;
7927 int idx = BEND_IDX(steps);
7928
7929 if (WARN_ON(steps % 5 != 0))
7930 return;
7931
7932 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7933 return;
7934
7935 mutex_lock(&dev_priv->sb_lock);
7936
7937 if (steps % 10 != 0)
7938 tmp = 0xAAAAAAAB;
7939 else
7940 tmp = 0x00000000;
7941 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7942
7943 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7944 tmp &= 0xffff0000;
7945 tmp |= sscdivintphase[idx];
7946 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7947
7948 mutex_unlock(&dev_priv->sb_lock);
7949 }
7950
7951 #undef BEND_IDX
7952
7953 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7954 {
7955 struct intel_encoder *encoder;
7956 bool has_vga = false;
7957
7958 for_each_intel_encoder(&dev_priv->drm, encoder) {
7959 switch (encoder->type) {
7960 case INTEL_OUTPUT_ANALOG:
7961 has_vga = true;
7962 break;
7963 default:
7964 break;
7965 }
7966 }
7967
7968 if (has_vga) {
7969 lpt_bend_clkout_dp(dev_priv, 0);
7970 lpt_enable_clkout_dp(dev_priv, true, true);
7971 } else {
7972 lpt_disable_clkout_dp(dev_priv);
7973 }
7974 }
7975
7976 /*
7977 * Initialize reference clocks when the driver loads
7978 */
7979 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7980 {
7981 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7982 ironlake_init_pch_refclk(dev_priv);
7983 else if (HAS_PCH_LPT(dev_priv))
7984 lpt_init_pch_refclk(dev_priv);
7985 }
7986
7987 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7988 {
7989 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7991 int pipe = intel_crtc->pipe;
7992 uint32_t val;
7993
7994 val = 0;
7995
7996 switch (intel_crtc->config->pipe_bpp) {
7997 case 18:
7998 val |= PIPECONF_6BPC;
7999 break;
8000 case 24:
8001 val |= PIPECONF_8BPC;
8002 break;
8003 case 30:
8004 val |= PIPECONF_10BPC;
8005 break;
8006 case 36:
8007 val |= PIPECONF_12BPC;
8008 break;
8009 default:
8010 /* Case prevented by intel_choose_pipe_bpp_dither. */
8011 BUG();
8012 }
8013
8014 if (intel_crtc->config->dither)
8015 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8016
8017 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8018 val |= PIPECONF_INTERLACED_ILK;
8019 else
8020 val |= PIPECONF_PROGRESSIVE;
8021
8022 if (intel_crtc->config->limited_color_range)
8023 val |= PIPECONF_COLOR_RANGE_SELECT;
8024
8025 I915_WRITE(PIPECONF(pipe), val);
8026 POSTING_READ(PIPECONF(pipe));
8027 }
8028
8029 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8030 {
8031 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8033 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8034 u32 val = 0;
8035
8036 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8037 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8038
8039 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8040 val |= PIPECONF_INTERLACED_ILK;
8041 else
8042 val |= PIPECONF_PROGRESSIVE;
8043
8044 I915_WRITE(PIPECONF(cpu_transcoder), val);
8045 POSTING_READ(PIPECONF(cpu_transcoder));
8046 }
8047
8048 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8049 {
8050 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8052
8053 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8054 u32 val = 0;
8055
8056 switch (intel_crtc->config->pipe_bpp) {
8057 case 18:
8058 val |= PIPEMISC_DITHER_6_BPC;
8059 break;
8060 case 24:
8061 val |= PIPEMISC_DITHER_8_BPC;
8062 break;
8063 case 30:
8064 val |= PIPEMISC_DITHER_10_BPC;
8065 break;
8066 case 36:
8067 val |= PIPEMISC_DITHER_12_BPC;
8068 break;
8069 default:
8070 /* Case prevented by pipe_config_set_bpp. */
8071 BUG();
8072 }
8073
8074 if (intel_crtc->config->dither)
8075 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8076
8077 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8078 }
8079 }
8080
8081 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8082 {
8083 /*
8084 * Account for spread spectrum to avoid
8085 * oversubscribing the link. Max center spread
8086 * is 2.5%; use 5% for safety's sake.
8087 */
8088 u32 bps = target_clock * bpp * 21 / 20;
8089 return DIV_ROUND_UP(bps, link_bw * 8);
8090 }
8091
8092 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8093 {
8094 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8095 }
8096
8097 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8098 struct intel_crtc_state *crtc_state,
8099 struct dpll *reduced_clock)
8100 {
8101 struct drm_crtc *crtc = &intel_crtc->base;
8102 struct drm_device *dev = crtc->dev;
8103 struct drm_i915_private *dev_priv = to_i915(dev);
8104 u32 dpll, fp, fp2;
8105 int factor;
8106
8107 /* Enable autotuning of the PLL clock (if permissible) */
8108 factor = 21;
8109 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8110 if ((intel_panel_use_ssc(dev_priv) &&
8111 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8112 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8113 factor = 25;
8114 } else if (crtc_state->sdvo_tv_clock)
8115 factor = 20;
8116
8117 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8118
8119 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8120 fp |= FP_CB_TUNE;
8121
8122 if (reduced_clock) {
8123 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8124
8125 if (reduced_clock->m < factor * reduced_clock->n)
8126 fp2 |= FP_CB_TUNE;
8127 } else {
8128 fp2 = fp;
8129 }
8130
8131 dpll = 0;
8132
8133 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8134 dpll |= DPLLB_MODE_LVDS;
8135 else
8136 dpll |= DPLLB_MODE_DAC_SERIAL;
8137
8138 dpll |= (crtc_state->pixel_multiplier - 1)
8139 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8140
8141 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8142 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8143 dpll |= DPLL_SDVO_HIGH_SPEED;
8144
8145 if (intel_crtc_has_dp_encoder(crtc_state))
8146 dpll |= DPLL_SDVO_HIGH_SPEED;
8147
8148 /*
8149 * The high speed IO clock is only really required for
8150 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8151 * possible to share the DPLL between CRT and HDMI. Enabling
8152 * the clock needlessly does no real harm, except use up a
8153 * bit of power potentially.
8154 *
8155 * We'll limit this to IVB with 3 pipes, since it has only two
8156 * DPLLs and so DPLL sharing is the only way to get three pipes
8157 * driving PCH ports at the same time. On SNB we could do this,
8158 * and potentially avoid enabling the second DPLL, but it's not
8159 * clear if it''s a win or loss power wise. No point in doing
8160 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8161 */
8162 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8163 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8164 dpll |= DPLL_SDVO_HIGH_SPEED;
8165
8166 /* compute bitmask from p1 value */
8167 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8168 /* also FPA1 */
8169 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8170
8171 switch (crtc_state->dpll.p2) {
8172 case 5:
8173 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8174 break;
8175 case 7:
8176 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8177 break;
8178 case 10:
8179 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8180 break;
8181 case 14:
8182 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8183 break;
8184 }
8185
8186 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8187 intel_panel_use_ssc(dev_priv))
8188 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8189 else
8190 dpll |= PLL_REF_INPUT_DREFCLK;
8191
8192 dpll |= DPLL_VCO_ENABLE;
8193
8194 crtc_state->dpll_hw_state.dpll = dpll;
8195 crtc_state->dpll_hw_state.fp0 = fp;
8196 crtc_state->dpll_hw_state.fp1 = fp2;
8197 }
8198
8199 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8200 struct intel_crtc_state *crtc_state)
8201 {
8202 struct drm_device *dev = crtc->base.dev;
8203 struct drm_i915_private *dev_priv = to_i915(dev);
8204 const struct intel_limit *limit;
8205 int refclk = 120000;
8206
8207 memset(&crtc_state->dpll_hw_state, 0,
8208 sizeof(crtc_state->dpll_hw_state));
8209
8210 crtc->lowfreq_avail = false;
8211
8212 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8213 if (!crtc_state->has_pch_encoder)
8214 return 0;
8215
8216 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8217 if (intel_panel_use_ssc(dev_priv)) {
8218 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8219 dev_priv->vbt.lvds_ssc_freq);
8220 refclk = dev_priv->vbt.lvds_ssc_freq;
8221 }
8222
8223 if (intel_is_dual_link_lvds(dev)) {
8224 if (refclk == 100000)
8225 limit = &intel_limits_ironlake_dual_lvds_100m;
8226 else
8227 limit = &intel_limits_ironlake_dual_lvds;
8228 } else {
8229 if (refclk == 100000)
8230 limit = &intel_limits_ironlake_single_lvds_100m;
8231 else
8232 limit = &intel_limits_ironlake_single_lvds;
8233 }
8234 } else {
8235 limit = &intel_limits_ironlake_dac;
8236 }
8237
8238 if (!crtc_state->clock_set &&
8239 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8240 refclk, NULL, &crtc_state->dpll)) {
8241 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8242 return -EINVAL;
8243 }
8244
8245 ironlake_compute_dpll(crtc, crtc_state, NULL);
8246
8247 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8248 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8249 pipe_name(crtc->pipe));
8250 return -EINVAL;
8251 }
8252
8253 return 0;
8254 }
8255
8256 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8257 struct intel_link_m_n *m_n)
8258 {
8259 struct drm_device *dev = crtc->base.dev;
8260 struct drm_i915_private *dev_priv = to_i915(dev);
8261 enum pipe pipe = crtc->pipe;
8262
8263 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8264 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8265 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8266 & ~TU_SIZE_MASK;
8267 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8268 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8269 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8270 }
8271
8272 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8273 enum transcoder transcoder,
8274 struct intel_link_m_n *m_n,
8275 struct intel_link_m_n *m2_n2)
8276 {
8277 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8278 enum pipe pipe = crtc->pipe;
8279
8280 if (INTEL_GEN(dev_priv) >= 5) {
8281 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8282 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8283 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8284 & ~TU_SIZE_MASK;
8285 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8286 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8287 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8288 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8289 * gen < 8) and if DRRS is supported (to make sure the
8290 * registers are not unnecessarily read).
8291 */
8292 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8293 crtc->config->has_drrs) {
8294 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8295 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8296 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8297 & ~TU_SIZE_MASK;
8298 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8299 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8300 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8301 }
8302 } else {
8303 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8304 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8305 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8306 & ~TU_SIZE_MASK;
8307 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8308 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8309 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8310 }
8311 }
8312
8313 void intel_dp_get_m_n(struct intel_crtc *crtc,
8314 struct intel_crtc_state *pipe_config)
8315 {
8316 if (pipe_config->has_pch_encoder)
8317 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8318 else
8319 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8320 &pipe_config->dp_m_n,
8321 &pipe_config->dp_m2_n2);
8322 }
8323
8324 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8325 struct intel_crtc_state *pipe_config)
8326 {
8327 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8328 &pipe_config->fdi_m_n, NULL);
8329 }
8330
8331 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8332 struct intel_crtc_state *pipe_config)
8333 {
8334 struct drm_device *dev = crtc->base.dev;
8335 struct drm_i915_private *dev_priv = to_i915(dev);
8336 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8337 uint32_t ps_ctrl = 0;
8338 int id = -1;
8339 int i;
8340
8341 /* find scaler attached to this pipe */
8342 for (i = 0; i < crtc->num_scalers; i++) {
8343 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8344 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8345 id = i;
8346 pipe_config->pch_pfit.enabled = true;
8347 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8348 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8349 break;
8350 }
8351 }
8352
8353 scaler_state->scaler_id = id;
8354 if (id >= 0) {
8355 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8356 } else {
8357 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8358 }
8359 }
8360
8361 static void
8362 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8363 struct intel_initial_plane_config *plane_config)
8364 {
8365 struct drm_device *dev = crtc->base.dev;
8366 struct drm_i915_private *dev_priv = to_i915(dev);
8367 u32 val, base, offset, stride_mult, tiling;
8368 int pipe = crtc->pipe;
8369 int fourcc, pixel_format;
8370 unsigned int aligned_height;
8371 struct drm_framebuffer *fb;
8372 struct intel_framebuffer *intel_fb;
8373
8374 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8375 if (!intel_fb) {
8376 DRM_DEBUG_KMS("failed to alloc fb\n");
8377 return;
8378 }
8379
8380 fb = &intel_fb->base;
8381
8382 fb->dev = dev;
8383
8384 val = I915_READ(PLANE_CTL(pipe, 0));
8385 if (!(val & PLANE_CTL_ENABLE))
8386 goto error;
8387
8388 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8389 fourcc = skl_format_to_fourcc(pixel_format,
8390 val & PLANE_CTL_ORDER_RGBX,
8391 val & PLANE_CTL_ALPHA_MASK);
8392 fb->format = drm_format_info(fourcc);
8393
8394 tiling = val & PLANE_CTL_TILED_MASK;
8395 switch (tiling) {
8396 case PLANE_CTL_TILED_LINEAR:
8397 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8398 break;
8399 case PLANE_CTL_TILED_X:
8400 plane_config->tiling = I915_TILING_X;
8401 fb->modifier = I915_FORMAT_MOD_X_TILED;
8402 break;
8403 case PLANE_CTL_TILED_Y:
8404 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8405 break;
8406 case PLANE_CTL_TILED_YF:
8407 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8408 break;
8409 default:
8410 MISSING_CASE(tiling);
8411 goto error;
8412 }
8413
8414 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8415 plane_config->base = base;
8416
8417 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8418
8419 val = I915_READ(PLANE_SIZE(pipe, 0));
8420 fb->height = ((val >> 16) & 0xfff) + 1;
8421 fb->width = ((val >> 0) & 0x1fff) + 1;
8422
8423 val = I915_READ(PLANE_STRIDE(pipe, 0));
8424 stride_mult = intel_fb_stride_alignment(fb, 0);
8425 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8426
8427 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8428
8429 plane_config->size = fb->pitches[0] * aligned_height;
8430
8431 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8432 pipe_name(pipe), fb->width, fb->height,
8433 fb->format->cpp[0] * 8, base, fb->pitches[0],
8434 plane_config->size);
8435
8436 plane_config->fb = intel_fb;
8437 return;
8438
8439 error:
8440 kfree(intel_fb);
8441 }
8442
8443 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8444 struct intel_crtc_state *pipe_config)
8445 {
8446 struct drm_device *dev = crtc->base.dev;
8447 struct drm_i915_private *dev_priv = to_i915(dev);
8448 uint32_t tmp;
8449
8450 tmp = I915_READ(PF_CTL(crtc->pipe));
8451
8452 if (tmp & PF_ENABLE) {
8453 pipe_config->pch_pfit.enabled = true;
8454 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8455 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8456
8457 /* We currently do not free assignements of panel fitters on
8458 * ivb/hsw (since we don't use the higher upscaling modes which
8459 * differentiates them) so just WARN about this case for now. */
8460 if (IS_GEN7(dev_priv)) {
8461 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8462 PF_PIPE_SEL_IVB(crtc->pipe));
8463 }
8464 }
8465 }
8466
8467 static void
8468 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8469 struct intel_initial_plane_config *plane_config)
8470 {
8471 struct drm_device *dev = crtc->base.dev;
8472 struct drm_i915_private *dev_priv = to_i915(dev);
8473 u32 val, base, offset;
8474 int pipe = crtc->pipe;
8475 int fourcc, pixel_format;
8476 unsigned int aligned_height;
8477 struct drm_framebuffer *fb;
8478 struct intel_framebuffer *intel_fb;
8479
8480 val = I915_READ(DSPCNTR(pipe));
8481 if (!(val & DISPLAY_PLANE_ENABLE))
8482 return;
8483
8484 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8485 if (!intel_fb) {
8486 DRM_DEBUG_KMS("failed to alloc fb\n");
8487 return;
8488 }
8489
8490 fb = &intel_fb->base;
8491
8492 fb->dev = dev;
8493
8494 if (INTEL_GEN(dev_priv) >= 4) {
8495 if (val & DISPPLANE_TILED) {
8496 plane_config->tiling = I915_TILING_X;
8497 fb->modifier = I915_FORMAT_MOD_X_TILED;
8498 }
8499 }
8500
8501 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8502 fourcc = i9xx_format_to_fourcc(pixel_format);
8503 fb->format = drm_format_info(fourcc);
8504
8505 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8506 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8507 offset = I915_READ(DSPOFFSET(pipe));
8508 } else {
8509 if (plane_config->tiling)
8510 offset = I915_READ(DSPTILEOFF(pipe));
8511 else
8512 offset = I915_READ(DSPLINOFF(pipe));
8513 }
8514 plane_config->base = base;
8515
8516 val = I915_READ(PIPESRC(pipe));
8517 fb->width = ((val >> 16) & 0xfff) + 1;
8518 fb->height = ((val >> 0) & 0xfff) + 1;
8519
8520 val = I915_READ(DSPSTRIDE(pipe));
8521 fb->pitches[0] = val & 0xffffffc0;
8522
8523 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8524
8525 plane_config->size = fb->pitches[0] * aligned_height;
8526
8527 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8528 pipe_name(pipe), fb->width, fb->height,
8529 fb->format->cpp[0] * 8, base, fb->pitches[0],
8530 plane_config->size);
8531
8532 plane_config->fb = intel_fb;
8533 }
8534
8535 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8536 struct intel_crtc_state *pipe_config)
8537 {
8538 struct drm_device *dev = crtc->base.dev;
8539 struct drm_i915_private *dev_priv = to_i915(dev);
8540 enum intel_display_power_domain power_domain;
8541 uint32_t tmp;
8542 bool ret;
8543
8544 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8545 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8546 return false;
8547
8548 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8549 pipe_config->shared_dpll = NULL;
8550
8551 ret = false;
8552 tmp = I915_READ(PIPECONF(crtc->pipe));
8553 if (!(tmp & PIPECONF_ENABLE))
8554 goto out;
8555
8556 switch (tmp & PIPECONF_BPC_MASK) {
8557 case PIPECONF_6BPC:
8558 pipe_config->pipe_bpp = 18;
8559 break;
8560 case PIPECONF_8BPC:
8561 pipe_config->pipe_bpp = 24;
8562 break;
8563 case PIPECONF_10BPC:
8564 pipe_config->pipe_bpp = 30;
8565 break;
8566 case PIPECONF_12BPC:
8567 pipe_config->pipe_bpp = 36;
8568 break;
8569 default:
8570 break;
8571 }
8572
8573 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8574 pipe_config->limited_color_range = true;
8575
8576 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8577 struct intel_shared_dpll *pll;
8578 enum intel_dpll_id pll_id;
8579
8580 pipe_config->has_pch_encoder = true;
8581
8582 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8583 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8584 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8585
8586 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8587
8588 if (HAS_PCH_IBX(dev_priv)) {
8589 /*
8590 * The pipe->pch transcoder and pch transcoder->pll
8591 * mapping is fixed.
8592 */
8593 pll_id = (enum intel_dpll_id) crtc->pipe;
8594 } else {
8595 tmp = I915_READ(PCH_DPLL_SEL);
8596 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8597 pll_id = DPLL_ID_PCH_PLL_B;
8598 else
8599 pll_id= DPLL_ID_PCH_PLL_A;
8600 }
8601
8602 pipe_config->shared_dpll =
8603 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8604 pll = pipe_config->shared_dpll;
8605
8606 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8607 &pipe_config->dpll_hw_state));
8608
8609 tmp = pipe_config->dpll_hw_state.dpll;
8610 pipe_config->pixel_multiplier =
8611 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8612 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8613
8614 ironlake_pch_clock_get(crtc, pipe_config);
8615 } else {
8616 pipe_config->pixel_multiplier = 1;
8617 }
8618
8619 intel_get_pipe_timings(crtc, pipe_config);
8620 intel_get_pipe_src_size(crtc, pipe_config);
8621
8622 ironlake_get_pfit_config(crtc, pipe_config);
8623
8624 ret = true;
8625
8626 out:
8627 intel_display_power_put(dev_priv, power_domain);
8628
8629 return ret;
8630 }
8631
8632 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8633 {
8634 struct drm_device *dev = &dev_priv->drm;
8635 struct intel_crtc *crtc;
8636
8637 for_each_intel_crtc(dev, crtc)
8638 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8639 pipe_name(crtc->pipe));
8640
8641 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8642 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8643 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8644 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8645 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8646 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8647 "CPU PWM1 enabled\n");
8648 if (IS_HASWELL(dev_priv))
8649 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8650 "CPU PWM2 enabled\n");
8651 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8652 "PCH PWM1 enabled\n");
8653 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8654 "Utility pin enabled\n");
8655 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8656
8657 /*
8658 * In theory we can still leave IRQs enabled, as long as only the HPD
8659 * interrupts remain enabled. We used to check for that, but since it's
8660 * gen-specific and since we only disable LCPLL after we fully disable
8661 * the interrupts, the check below should be enough.
8662 */
8663 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8664 }
8665
8666 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8667 {
8668 if (IS_HASWELL(dev_priv))
8669 return I915_READ(D_COMP_HSW);
8670 else
8671 return I915_READ(D_COMP_BDW);
8672 }
8673
8674 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8675 {
8676 if (IS_HASWELL(dev_priv)) {
8677 mutex_lock(&dev_priv->rps.hw_lock);
8678 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8679 val))
8680 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8681 mutex_unlock(&dev_priv->rps.hw_lock);
8682 } else {
8683 I915_WRITE(D_COMP_BDW, val);
8684 POSTING_READ(D_COMP_BDW);
8685 }
8686 }
8687
8688 /*
8689 * This function implements pieces of two sequences from BSpec:
8690 * - Sequence for display software to disable LCPLL
8691 * - Sequence for display software to allow package C8+
8692 * The steps implemented here are just the steps that actually touch the LCPLL
8693 * register. Callers should take care of disabling all the display engine
8694 * functions, doing the mode unset, fixing interrupts, etc.
8695 */
8696 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8697 bool switch_to_fclk, bool allow_power_down)
8698 {
8699 uint32_t val;
8700
8701 assert_can_disable_lcpll(dev_priv);
8702
8703 val = I915_READ(LCPLL_CTL);
8704
8705 if (switch_to_fclk) {
8706 val |= LCPLL_CD_SOURCE_FCLK;
8707 I915_WRITE(LCPLL_CTL, val);
8708
8709 if (wait_for_us(I915_READ(LCPLL_CTL) &
8710 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8711 DRM_ERROR("Switching to FCLK failed\n");
8712
8713 val = I915_READ(LCPLL_CTL);
8714 }
8715
8716 val |= LCPLL_PLL_DISABLE;
8717 I915_WRITE(LCPLL_CTL, val);
8718 POSTING_READ(LCPLL_CTL);
8719
8720 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8721 DRM_ERROR("LCPLL still locked\n");
8722
8723 val = hsw_read_dcomp(dev_priv);
8724 val |= D_COMP_COMP_DISABLE;
8725 hsw_write_dcomp(dev_priv, val);
8726 ndelay(100);
8727
8728 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8729 1))
8730 DRM_ERROR("D_COMP RCOMP still in progress\n");
8731
8732 if (allow_power_down) {
8733 val = I915_READ(LCPLL_CTL);
8734 val |= LCPLL_POWER_DOWN_ALLOW;
8735 I915_WRITE(LCPLL_CTL, val);
8736 POSTING_READ(LCPLL_CTL);
8737 }
8738 }
8739
8740 /*
8741 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8742 * source.
8743 */
8744 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8745 {
8746 uint32_t val;
8747
8748 val = I915_READ(LCPLL_CTL);
8749
8750 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8751 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8752 return;
8753
8754 /*
8755 * Make sure we're not on PC8 state before disabling PC8, otherwise
8756 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8757 */
8758 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8759
8760 if (val & LCPLL_POWER_DOWN_ALLOW) {
8761 val &= ~LCPLL_POWER_DOWN_ALLOW;
8762 I915_WRITE(LCPLL_CTL, val);
8763 POSTING_READ(LCPLL_CTL);
8764 }
8765
8766 val = hsw_read_dcomp(dev_priv);
8767 val |= D_COMP_COMP_FORCE;
8768 val &= ~D_COMP_COMP_DISABLE;
8769 hsw_write_dcomp(dev_priv, val);
8770
8771 val = I915_READ(LCPLL_CTL);
8772 val &= ~LCPLL_PLL_DISABLE;
8773 I915_WRITE(LCPLL_CTL, val);
8774
8775 if (intel_wait_for_register(dev_priv,
8776 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8777 5))
8778 DRM_ERROR("LCPLL not locked yet\n");
8779
8780 if (val & LCPLL_CD_SOURCE_FCLK) {
8781 val = I915_READ(LCPLL_CTL);
8782 val &= ~LCPLL_CD_SOURCE_FCLK;
8783 I915_WRITE(LCPLL_CTL, val);
8784
8785 if (wait_for_us((I915_READ(LCPLL_CTL) &
8786 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8787 DRM_ERROR("Switching back to LCPLL failed\n");
8788 }
8789
8790 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8791 intel_update_cdclk(dev_priv);
8792 }
8793
8794 /*
8795 * Package states C8 and deeper are really deep PC states that can only be
8796 * reached when all the devices on the system allow it, so even if the graphics
8797 * device allows PC8+, it doesn't mean the system will actually get to these
8798 * states. Our driver only allows PC8+ when going into runtime PM.
8799 *
8800 * The requirements for PC8+ are that all the outputs are disabled, the power
8801 * well is disabled and most interrupts are disabled, and these are also
8802 * requirements for runtime PM. When these conditions are met, we manually do
8803 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8804 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8805 * hang the machine.
8806 *
8807 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8808 * the state of some registers, so when we come back from PC8+ we need to
8809 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8810 * need to take care of the registers kept by RC6. Notice that this happens even
8811 * if we don't put the device in PCI D3 state (which is what currently happens
8812 * because of the runtime PM support).
8813 *
8814 * For more, read "Display Sequences for Package C8" on the hardware
8815 * documentation.
8816 */
8817 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8818 {
8819 uint32_t val;
8820
8821 DRM_DEBUG_KMS("Enabling package C8+\n");
8822
8823 if (HAS_PCH_LPT_LP(dev_priv)) {
8824 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8825 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8826 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8827 }
8828
8829 lpt_disable_clkout_dp(dev_priv);
8830 hsw_disable_lcpll(dev_priv, true, true);
8831 }
8832
8833 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8834 {
8835 uint32_t val;
8836
8837 DRM_DEBUG_KMS("Disabling package C8+\n");
8838
8839 hsw_restore_lcpll(dev_priv);
8840 lpt_init_pch_refclk(dev_priv);
8841
8842 if (HAS_PCH_LPT_LP(dev_priv)) {
8843 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8844 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8845 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8846 }
8847 }
8848
8849 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8850 struct intel_crtc_state *crtc_state)
8851 {
8852 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8853 struct intel_encoder *encoder =
8854 intel_ddi_get_crtc_new_encoder(crtc_state);
8855
8856 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8857 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8858 pipe_name(crtc->pipe));
8859 return -EINVAL;
8860 }
8861 }
8862
8863 crtc->lowfreq_avail = false;
8864
8865 return 0;
8866 }
8867
8868 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8869 enum port port,
8870 struct intel_crtc_state *pipe_config)
8871 {
8872 enum intel_dpll_id id;
8873 u32 temp;
8874
8875 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8876 id = temp >> (port * 2);
8877
8878 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8879 return;
8880
8881 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8882 }
8883
8884 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8885 enum port port,
8886 struct intel_crtc_state *pipe_config)
8887 {
8888 enum intel_dpll_id id;
8889
8890 switch (port) {
8891 case PORT_A:
8892 id = DPLL_ID_SKL_DPLL0;
8893 break;
8894 case PORT_B:
8895 id = DPLL_ID_SKL_DPLL1;
8896 break;
8897 case PORT_C:
8898 id = DPLL_ID_SKL_DPLL2;
8899 break;
8900 default:
8901 DRM_ERROR("Incorrect port type\n");
8902 return;
8903 }
8904
8905 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8906 }
8907
8908 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8909 enum port port,
8910 struct intel_crtc_state *pipe_config)
8911 {
8912 enum intel_dpll_id id;
8913 u32 temp;
8914
8915 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8916 id = temp >> (port * 3 + 1);
8917
8918 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8919 return;
8920
8921 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8922 }
8923
8924 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8925 enum port port,
8926 struct intel_crtc_state *pipe_config)
8927 {
8928 enum intel_dpll_id id;
8929 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8930
8931 switch (ddi_pll_sel) {
8932 case PORT_CLK_SEL_WRPLL1:
8933 id = DPLL_ID_WRPLL1;
8934 break;
8935 case PORT_CLK_SEL_WRPLL2:
8936 id = DPLL_ID_WRPLL2;
8937 break;
8938 case PORT_CLK_SEL_SPLL:
8939 id = DPLL_ID_SPLL;
8940 break;
8941 case PORT_CLK_SEL_LCPLL_810:
8942 id = DPLL_ID_LCPLL_810;
8943 break;
8944 case PORT_CLK_SEL_LCPLL_1350:
8945 id = DPLL_ID_LCPLL_1350;
8946 break;
8947 case PORT_CLK_SEL_LCPLL_2700:
8948 id = DPLL_ID_LCPLL_2700;
8949 break;
8950 default:
8951 MISSING_CASE(ddi_pll_sel);
8952 /* fall through */
8953 case PORT_CLK_SEL_NONE:
8954 return;
8955 }
8956
8957 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8958 }
8959
8960 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8961 struct intel_crtc_state *pipe_config,
8962 u64 *power_domain_mask)
8963 {
8964 struct drm_device *dev = crtc->base.dev;
8965 struct drm_i915_private *dev_priv = to_i915(dev);
8966 enum intel_display_power_domain power_domain;
8967 u32 tmp;
8968
8969 /*
8970 * The pipe->transcoder mapping is fixed with the exception of the eDP
8971 * transcoder handled below.
8972 */
8973 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8974
8975 /*
8976 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8977 * consistency and less surprising code; it's in always on power).
8978 */
8979 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8980 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8981 enum pipe trans_edp_pipe;
8982 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8983 default:
8984 WARN(1, "unknown pipe linked to edp transcoder\n");
8985 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8986 case TRANS_DDI_EDP_INPUT_A_ON:
8987 trans_edp_pipe = PIPE_A;
8988 break;
8989 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8990 trans_edp_pipe = PIPE_B;
8991 break;
8992 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8993 trans_edp_pipe = PIPE_C;
8994 break;
8995 }
8996
8997 if (trans_edp_pipe == crtc->pipe)
8998 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8999 }
9000
9001 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9002 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9003 return false;
9004 *power_domain_mask |= BIT_ULL(power_domain);
9005
9006 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9007
9008 return tmp & PIPECONF_ENABLE;
9009 }
9010
9011 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9012 struct intel_crtc_state *pipe_config,
9013 u64 *power_domain_mask)
9014 {
9015 struct drm_device *dev = crtc->base.dev;
9016 struct drm_i915_private *dev_priv = to_i915(dev);
9017 enum intel_display_power_domain power_domain;
9018 enum port port;
9019 enum transcoder cpu_transcoder;
9020 u32 tmp;
9021
9022 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9023 if (port == PORT_A)
9024 cpu_transcoder = TRANSCODER_DSI_A;
9025 else
9026 cpu_transcoder = TRANSCODER_DSI_C;
9027
9028 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9029 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9030 continue;
9031 *power_domain_mask |= BIT_ULL(power_domain);
9032
9033 /*
9034 * The PLL needs to be enabled with a valid divider
9035 * configuration, otherwise accessing DSI registers will hang
9036 * the machine. See BSpec North Display Engine
9037 * registers/MIPI[BXT]. We can break out here early, since we
9038 * need the same DSI PLL to be enabled for both DSI ports.
9039 */
9040 if (!intel_dsi_pll_is_enabled(dev_priv))
9041 break;
9042
9043 /* XXX: this works for video mode only */
9044 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9045 if (!(tmp & DPI_ENABLE))
9046 continue;
9047
9048 tmp = I915_READ(MIPI_CTRL(port));
9049 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9050 continue;
9051
9052 pipe_config->cpu_transcoder = cpu_transcoder;
9053 break;
9054 }
9055
9056 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9057 }
9058
9059 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9060 struct intel_crtc_state *pipe_config)
9061 {
9062 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9063 struct intel_shared_dpll *pll;
9064 enum port port;
9065 uint32_t tmp;
9066
9067 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9068
9069 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9070
9071 if (IS_CANNONLAKE(dev_priv))
9072 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9073 else if (IS_GEN9_BC(dev_priv))
9074 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9075 else if (IS_GEN9_LP(dev_priv))
9076 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9077 else
9078 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9079
9080 pll = pipe_config->shared_dpll;
9081 if (pll) {
9082 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9083 &pipe_config->dpll_hw_state));
9084 }
9085
9086 /*
9087 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9088 * DDI E. So just check whether this pipe is wired to DDI E and whether
9089 * the PCH transcoder is on.
9090 */
9091 if (INTEL_GEN(dev_priv) < 9 &&
9092 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9093 pipe_config->has_pch_encoder = true;
9094
9095 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9096 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9097 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9098
9099 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9100 }
9101 }
9102
9103 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9104 struct intel_crtc_state *pipe_config)
9105 {
9106 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9107 enum intel_display_power_domain power_domain;
9108 u64 power_domain_mask;
9109 bool active;
9110
9111 if (INTEL_GEN(dev_priv) >= 9) {
9112 intel_crtc_init_scalers(crtc, pipe_config);
9113
9114 pipe_config->scaler_state.scaler_id = -1;
9115 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9116 }
9117
9118 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9119 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9120 return false;
9121 power_domain_mask = BIT_ULL(power_domain);
9122
9123 pipe_config->shared_dpll = NULL;
9124
9125 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9126
9127 if (IS_GEN9_LP(dev_priv) &&
9128 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9129 WARN_ON(active);
9130 active = true;
9131 }
9132
9133 if (!active)
9134 goto out;
9135
9136 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9137 haswell_get_ddi_port_state(crtc, pipe_config);
9138 intel_get_pipe_timings(crtc, pipe_config);
9139 }
9140
9141 intel_get_pipe_src_size(crtc, pipe_config);
9142
9143 pipe_config->gamma_mode =
9144 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9145
9146 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9147 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9148 power_domain_mask |= BIT_ULL(power_domain);
9149 if (INTEL_GEN(dev_priv) >= 9)
9150 skylake_get_pfit_config(crtc, pipe_config);
9151 else
9152 ironlake_get_pfit_config(crtc, pipe_config);
9153 }
9154
9155 if (IS_HASWELL(dev_priv))
9156 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9157 (I915_READ(IPS_CTL) & IPS_ENABLE);
9158
9159 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9160 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9161 pipe_config->pixel_multiplier =
9162 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9163 } else {
9164 pipe_config->pixel_multiplier = 1;
9165 }
9166
9167 out:
9168 for_each_power_domain(power_domain, power_domain_mask)
9169 intel_display_power_put(dev_priv, power_domain);
9170
9171 return active;
9172 }
9173
9174 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9175 {
9176 struct drm_i915_private *dev_priv =
9177 to_i915(plane_state->base.plane->dev);
9178 const struct drm_framebuffer *fb = plane_state->base.fb;
9179 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9180 u32 base;
9181
9182 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9183 base = obj->phys_handle->busaddr;
9184 else
9185 base = intel_plane_ggtt_offset(plane_state);
9186
9187 base += plane_state->main.offset;
9188
9189 /* ILK+ do this automagically */
9190 if (HAS_GMCH_DISPLAY(dev_priv) &&
9191 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9192 base += (plane_state->base.crtc_h *
9193 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9194
9195 return base;
9196 }
9197
9198 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9199 {
9200 int x = plane_state->base.crtc_x;
9201 int y = plane_state->base.crtc_y;
9202 u32 pos = 0;
9203
9204 if (x < 0) {
9205 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9206 x = -x;
9207 }
9208 pos |= x << CURSOR_X_SHIFT;
9209
9210 if (y < 0) {
9211 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9212 y = -y;
9213 }
9214 pos |= y << CURSOR_Y_SHIFT;
9215
9216 return pos;
9217 }
9218
9219 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9220 {
9221 const struct drm_mode_config *config =
9222 &plane_state->base.plane->dev->mode_config;
9223 int width = plane_state->base.crtc_w;
9224 int height = plane_state->base.crtc_h;
9225
9226 return width > 0 && width <= config->cursor_width &&
9227 height > 0 && height <= config->cursor_height;
9228 }
9229
9230 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9231 struct intel_plane_state *plane_state)
9232 {
9233 const struct drm_framebuffer *fb = plane_state->base.fb;
9234 int src_x, src_y;
9235 u32 offset;
9236 int ret;
9237
9238 ret = drm_plane_helper_check_state(&plane_state->base,
9239 &plane_state->clip,
9240 DRM_PLANE_HELPER_NO_SCALING,
9241 DRM_PLANE_HELPER_NO_SCALING,
9242 true, true);
9243 if (ret)
9244 return ret;
9245
9246 if (!fb)
9247 return 0;
9248
9249 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9250 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9251 return -EINVAL;
9252 }
9253
9254 src_x = plane_state->base.src_x >> 16;
9255 src_y = plane_state->base.src_y >> 16;
9256
9257 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9258 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9259
9260 if (src_x != 0 || src_y != 0) {
9261 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9262 return -EINVAL;
9263 }
9264
9265 plane_state->main.offset = offset;
9266
9267 return 0;
9268 }
9269
9270 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9271 const struct intel_plane_state *plane_state)
9272 {
9273 const struct drm_framebuffer *fb = plane_state->base.fb;
9274
9275 return CURSOR_ENABLE |
9276 CURSOR_GAMMA_ENABLE |
9277 CURSOR_FORMAT_ARGB |
9278 CURSOR_STRIDE(fb->pitches[0]);
9279 }
9280
9281 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9282 {
9283 int width = plane_state->base.crtc_w;
9284
9285 /*
9286 * 845g/865g are only limited by the width of their cursors,
9287 * the height is arbitrary up to the precision of the register.
9288 */
9289 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9290 }
9291
9292 static int i845_check_cursor(struct intel_plane *plane,
9293 struct intel_crtc_state *crtc_state,
9294 struct intel_plane_state *plane_state)
9295 {
9296 const struct drm_framebuffer *fb = plane_state->base.fb;
9297 int ret;
9298
9299 ret = intel_check_cursor(crtc_state, plane_state);
9300 if (ret)
9301 return ret;
9302
9303 /* if we want to turn off the cursor ignore width and height */
9304 if (!fb)
9305 return 0;
9306
9307 /* Check for which cursor types we support */
9308 if (!i845_cursor_size_ok(plane_state)) {
9309 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9310 plane_state->base.crtc_w,
9311 plane_state->base.crtc_h);
9312 return -EINVAL;
9313 }
9314
9315 switch (fb->pitches[0]) {
9316 case 256:
9317 case 512:
9318 case 1024:
9319 case 2048:
9320 break;
9321 default:
9322 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9323 fb->pitches[0]);
9324 return -EINVAL;
9325 }
9326
9327 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9328
9329 return 0;
9330 }
9331
9332 static void i845_update_cursor(struct intel_plane *plane,
9333 const struct intel_crtc_state *crtc_state,
9334 const struct intel_plane_state *plane_state)
9335 {
9336 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9337 u32 cntl = 0, base = 0, pos = 0, size = 0;
9338 unsigned long irqflags;
9339
9340 if (plane_state && plane_state->base.visible) {
9341 unsigned int width = plane_state->base.crtc_w;
9342 unsigned int height = plane_state->base.crtc_h;
9343
9344 cntl = plane_state->ctl;
9345 size = (height << 12) | width;
9346
9347 base = intel_cursor_base(plane_state);
9348 pos = intel_cursor_position(plane_state);
9349 }
9350
9351 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9352
9353 /* On these chipsets we can only modify the base/size/stride
9354 * whilst the cursor is disabled.
9355 */
9356 if (plane->cursor.base != base ||
9357 plane->cursor.size != size ||
9358 plane->cursor.cntl != cntl) {
9359 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9360 I915_WRITE_FW(CURBASE(PIPE_A), base);
9361 I915_WRITE_FW(CURSIZE, size);
9362 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9363 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9364
9365 plane->cursor.base = base;
9366 plane->cursor.size = size;
9367 plane->cursor.cntl = cntl;
9368 } else {
9369 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9370 }
9371
9372 POSTING_READ_FW(CURCNTR(PIPE_A));
9373
9374 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9375 }
9376
9377 static void i845_disable_cursor(struct intel_plane *plane,
9378 struct intel_crtc *crtc)
9379 {
9380 i845_update_cursor(plane, NULL, NULL);
9381 }
9382
9383 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9384 const struct intel_plane_state *plane_state)
9385 {
9386 struct drm_i915_private *dev_priv =
9387 to_i915(plane_state->base.plane->dev);
9388 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9389 u32 cntl;
9390
9391 cntl = MCURSOR_GAMMA_ENABLE;
9392
9393 if (HAS_DDI(dev_priv))
9394 cntl |= CURSOR_PIPE_CSC_ENABLE;
9395
9396 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9397
9398 switch (plane_state->base.crtc_w) {
9399 case 64:
9400 cntl |= CURSOR_MODE_64_ARGB_AX;
9401 break;
9402 case 128:
9403 cntl |= CURSOR_MODE_128_ARGB_AX;
9404 break;
9405 case 256:
9406 cntl |= CURSOR_MODE_256_ARGB_AX;
9407 break;
9408 default:
9409 MISSING_CASE(plane_state->base.crtc_w);
9410 return 0;
9411 }
9412
9413 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9414 cntl |= CURSOR_ROTATE_180;
9415
9416 return cntl;
9417 }
9418
9419 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9420 {
9421 struct drm_i915_private *dev_priv =
9422 to_i915(plane_state->base.plane->dev);
9423 int width = plane_state->base.crtc_w;
9424 int height = plane_state->base.crtc_h;
9425
9426 if (!intel_cursor_size_ok(plane_state))
9427 return false;
9428
9429 /* Cursor width is limited to a few power-of-two sizes */
9430 switch (width) {
9431 case 256:
9432 case 128:
9433 case 64:
9434 break;
9435 default:
9436 return false;
9437 }
9438
9439 /*
9440 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9441 * height from 8 lines up to the cursor width, when the
9442 * cursor is not rotated. Everything else requires square
9443 * cursors.
9444 */
9445 if (HAS_CUR_FBC(dev_priv) &&
9446 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9447 if (height < 8 || height > width)
9448 return false;
9449 } else {
9450 if (height != width)
9451 return false;
9452 }
9453
9454 return true;
9455 }
9456
9457 static int i9xx_check_cursor(struct intel_plane *plane,
9458 struct intel_crtc_state *crtc_state,
9459 struct intel_plane_state *plane_state)
9460 {
9461 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9462 const struct drm_framebuffer *fb = plane_state->base.fb;
9463 enum pipe pipe = plane->pipe;
9464 int ret;
9465
9466 ret = intel_check_cursor(crtc_state, plane_state);
9467 if (ret)
9468 return ret;
9469
9470 /* if we want to turn off the cursor ignore width and height */
9471 if (!fb)
9472 return 0;
9473
9474 /* Check for which cursor types we support */
9475 if (!i9xx_cursor_size_ok(plane_state)) {
9476 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9477 plane_state->base.crtc_w,
9478 plane_state->base.crtc_h);
9479 return -EINVAL;
9480 }
9481
9482 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9483 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9484 fb->pitches[0], plane_state->base.crtc_w);
9485 return -EINVAL;
9486 }
9487
9488 /*
9489 * There's something wrong with the cursor on CHV pipe C.
9490 * If it straddles the left edge of the screen then
9491 * moving it away from the edge or disabling it often
9492 * results in a pipe underrun, and often that can lead to
9493 * dead pipe (constant underrun reported, and it scans
9494 * out just a solid color). To recover from that, the
9495 * display power well must be turned off and on again.
9496 * Refuse the put the cursor into that compromised position.
9497 */
9498 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9499 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9500 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9501 return -EINVAL;
9502 }
9503
9504 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9505
9506 return 0;
9507 }
9508
9509 static void i9xx_update_cursor(struct intel_plane *plane,
9510 const struct intel_crtc_state *crtc_state,
9511 const struct intel_plane_state *plane_state)
9512 {
9513 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9514 enum pipe pipe = plane->pipe;
9515 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9516 unsigned long irqflags;
9517
9518 if (plane_state && plane_state->base.visible) {
9519 cntl = plane_state->ctl;
9520
9521 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9522 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9523
9524 base = intel_cursor_base(plane_state);
9525 pos = intel_cursor_position(plane_state);
9526 }
9527
9528 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9529
9530 /*
9531 * On some platforms writing CURCNTR first will also
9532 * cause CURPOS to be armed by the CURBASE write.
9533 * Without the CURCNTR write the CURPOS write would
9534 * arm itself. Thus we always start the full update
9535 * with a CURCNTR write.
9536 *
9537 * On other platforms CURPOS always requires the
9538 * CURBASE write to arm the update. Additonally
9539 * a write to any of the cursor register will cancel
9540 * an already armed cursor update. Thus leaving out
9541 * the CURBASE write after CURPOS could lead to a
9542 * cursor that doesn't appear to move, or even change
9543 * shape. Thus we always write CURBASE.
9544 *
9545 * CURCNTR and CUR_FBC_CTL are always
9546 * armed by the CURBASE write only.
9547 */
9548 if (plane->cursor.base != base ||
9549 plane->cursor.size != fbc_ctl ||
9550 plane->cursor.cntl != cntl) {
9551 I915_WRITE_FW(CURCNTR(pipe), cntl);
9552 if (HAS_CUR_FBC(dev_priv))
9553 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9554 I915_WRITE_FW(CURPOS(pipe), pos);
9555 I915_WRITE_FW(CURBASE(pipe), base);
9556
9557 plane->cursor.base = base;
9558 plane->cursor.size = fbc_ctl;
9559 plane->cursor.cntl = cntl;
9560 } else {
9561 I915_WRITE_FW(CURPOS(pipe), pos);
9562 I915_WRITE_FW(CURBASE(pipe), base);
9563 }
9564
9565 POSTING_READ_FW(CURBASE(pipe));
9566
9567 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9568 }
9569
9570 static void i9xx_disable_cursor(struct intel_plane *plane,
9571 struct intel_crtc *crtc)
9572 {
9573 i9xx_update_cursor(plane, NULL, NULL);
9574 }
9575
9576
9577 /* VESA 640x480x72Hz mode to set on the pipe */
9578 static struct drm_display_mode load_detect_mode = {
9579 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9580 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9581 };
9582
9583 struct drm_framebuffer *
9584 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9585 struct drm_mode_fb_cmd2 *mode_cmd)
9586 {
9587 struct intel_framebuffer *intel_fb;
9588 int ret;
9589
9590 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9591 if (!intel_fb)
9592 return ERR_PTR(-ENOMEM);
9593
9594 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9595 if (ret)
9596 goto err;
9597
9598 return &intel_fb->base;
9599
9600 err:
9601 kfree(intel_fb);
9602 return ERR_PTR(ret);
9603 }
9604
9605 static u32
9606 intel_framebuffer_pitch_for_width(int width, int bpp)
9607 {
9608 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9609 return ALIGN(pitch, 64);
9610 }
9611
9612 static u32
9613 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9614 {
9615 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9616 return PAGE_ALIGN(pitch * mode->vdisplay);
9617 }
9618
9619 static struct drm_framebuffer *
9620 intel_framebuffer_create_for_mode(struct drm_device *dev,
9621 struct drm_display_mode *mode,
9622 int depth, int bpp)
9623 {
9624 struct drm_framebuffer *fb;
9625 struct drm_i915_gem_object *obj;
9626 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9627
9628 obj = i915_gem_object_create(to_i915(dev),
9629 intel_framebuffer_size_for_mode(mode, bpp));
9630 if (IS_ERR(obj))
9631 return ERR_CAST(obj);
9632
9633 mode_cmd.width = mode->hdisplay;
9634 mode_cmd.height = mode->vdisplay;
9635 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9636 bpp);
9637 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9638
9639 fb = intel_framebuffer_create(obj, &mode_cmd);
9640 if (IS_ERR(fb))
9641 i915_gem_object_put(obj);
9642
9643 return fb;
9644 }
9645
9646 static struct drm_framebuffer *
9647 mode_fits_in_fbdev(struct drm_device *dev,
9648 struct drm_display_mode *mode)
9649 {
9650 #ifdef CONFIG_DRM_FBDEV_EMULATION
9651 struct drm_i915_private *dev_priv = to_i915(dev);
9652 struct drm_i915_gem_object *obj;
9653 struct drm_framebuffer *fb;
9654
9655 if (!dev_priv->fbdev)
9656 return NULL;
9657
9658 if (!dev_priv->fbdev->fb)
9659 return NULL;
9660
9661 obj = dev_priv->fbdev->fb->obj;
9662 BUG_ON(!obj);
9663
9664 fb = &dev_priv->fbdev->fb->base;
9665 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9666 fb->format->cpp[0] * 8))
9667 return NULL;
9668
9669 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9670 return NULL;
9671
9672 drm_framebuffer_reference(fb);
9673 return fb;
9674 #else
9675 return NULL;
9676 #endif
9677 }
9678
9679 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9680 struct drm_crtc *crtc,
9681 struct drm_display_mode *mode,
9682 struct drm_framebuffer *fb,
9683 int x, int y)
9684 {
9685 struct drm_plane_state *plane_state;
9686 int hdisplay, vdisplay;
9687 int ret;
9688
9689 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9690 if (IS_ERR(plane_state))
9691 return PTR_ERR(plane_state);
9692
9693 if (mode)
9694 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9695 else
9696 hdisplay = vdisplay = 0;
9697
9698 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9699 if (ret)
9700 return ret;
9701 drm_atomic_set_fb_for_plane(plane_state, fb);
9702 plane_state->crtc_x = 0;
9703 plane_state->crtc_y = 0;
9704 plane_state->crtc_w = hdisplay;
9705 plane_state->crtc_h = vdisplay;
9706 plane_state->src_x = x << 16;
9707 plane_state->src_y = y << 16;
9708 plane_state->src_w = hdisplay << 16;
9709 plane_state->src_h = vdisplay << 16;
9710
9711 return 0;
9712 }
9713
9714 int intel_get_load_detect_pipe(struct drm_connector *connector,
9715 struct drm_display_mode *mode,
9716 struct intel_load_detect_pipe *old,
9717 struct drm_modeset_acquire_ctx *ctx)
9718 {
9719 struct intel_crtc *intel_crtc;
9720 struct intel_encoder *intel_encoder =
9721 intel_attached_encoder(connector);
9722 struct drm_crtc *possible_crtc;
9723 struct drm_encoder *encoder = &intel_encoder->base;
9724 struct drm_crtc *crtc = NULL;
9725 struct drm_device *dev = encoder->dev;
9726 struct drm_i915_private *dev_priv = to_i915(dev);
9727 struct drm_framebuffer *fb;
9728 struct drm_mode_config *config = &dev->mode_config;
9729 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9730 struct drm_connector_state *connector_state;
9731 struct intel_crtc_state *crtc_state;
9732 int ret, i = -1;
9733
9734 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9735 connector->base.id, connector->name,
9736 encoder->base.id, encoder->name);
9737
9738 old->restore_state = NULL;
9739
9740 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9741
9742 /*
9743 * Algorithm gets a little messy:
9744 *
9745 * - if the connector already has an assigned crtc, use it (but make
9746 * sure it's on first)
9747 *
9748 * - try to find the first unused crtc that can drive this connector,
9749 * and use that if we find one
9750 */
9751
9752 /* See if we already have a CRTC for this connector */
9753 if (connector->state->crtc) {
9754 crtc = connector->state->crtc;
9755
9756 ret = drm_modeset_lock(&crtc->mutex, ctx);
9757 if (ret)
9758 goto fail;
9759
9760 /* Make sure the crtc and connector are running */
9761 goto found;
9762 }
9763
9764 /* Find an unused one (if possible) */
9765 for_each_crtc(dev, possible_crtc) {
9766 i++;
9767 if (!(encoder->possible_crtcs & (1 << i)))
9768 continue;
9769
9770 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9771 if (ret)
9772 goto fail;
9773
9774 if (possible_crtc->state->enable) {
9775 drm_modeset_unlock(&possible_crtc->mutex);
9776 continue;
9777 }
9778
9779 crtc = possible_crtc;
9780 break;
9781 }
9782
9783 /*
9784 * If we didn't find an unused CRTC, don't use any.
9785 */
9786 if (!crtc) {
9787 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9788 ret = -ENODEV;
9789 goto fail;
9790 }
9791
9792 found:
9793 intel_crtc = to_intel_crtc(crtc);
9794
9795 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9796 if (ret)
9797 goto fail;
9798
9799 state = drm_atomic_state_alloc(dev);
9800 restore_state = drm_atomic_state_alloc(dev);
9801 if (!state || !restore_state) {
9802 ret = -ENOMEM;
9803 goto fail;
9804 }
9805
9806 state->acquire_ctx = ctx;
9807 restore_state->acquire_ctx = ctx;
9808
9809 connector_state = drm_atomic_get_connector_state(state, connector);
9810 if (IS_ERR(connector_state)) {
9811 ret = PTR_ERR(connector_state);
9812 goto fail;
9813 }
9814
9815 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9816 if (ret)
9817 goto fail;
9818
9819 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9820 if (IS_ERR(crtc_state)) {
9821 ret = PTR_ERR(crtc_state);
9822 goto fail;
9823 }
9824
9825 crtc_state->base.active = crtc_state->base.enable = true;
9826
9827 if (!mode)
9828 mode = &load_detect_mode;
9829
9830 /* We need a framebuffer large enough to accommodate all accesses
9831 * that the plane may generate whilst we perform load detection.
9832 * We can not rely on the fbcon either being present (we get called
9833 * during its initialisation to detect all boot displays, or it may
9834 * not even exist) or that it is large enough to satisfy the
9835 * requested mode.
9836 */
9837 fb = mode_fits_in_fbdev(dev, mode);
9838 if (fb == NULL) {
9839 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9840 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9841 } else
9842 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9843 if (IS_ERR(fb)) {
9844 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9845 ret = PTR_ERR(fb);
9846 goto fail;
9847 }
9848
9849 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9850 if (ret)
9851 goto fail;
9852
9853 drm_framebuffer_unreference(fb);
9854
9855 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9856 if (ret)
9857 goto fail;
9858
9859 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9860 if (!ret)
9861 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9862 if (!ret)
9863 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9864 if (ret) {
9865 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9866 goto fail;
9867 }
9868
9869 ret = drm_atomic_commit(state);
9870 if (ret) {
9871 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9872 goto fail;
9873 }
9874
9875 old->restore_state = restore_state;
9876 drm_atomic_state_put(state);
9877
9878 /* let the connector get through one full cycle before testing */
9879 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9880 return true;
9881
9882 fail:
9883 if (state) {
9884 drm_atomic_state_put(state);
9885 state = NULL;
9886 }
9887 if (restore_state) {
9888 drm_atomic_state_put(restore_state);
9889 restore_state = NULL;
9890 }
9891
9892 if (ret == -EDEADLK)
9893 return ret;
9894
9895 return false;
9896 }
9897
9898 void intel_release_load_detect_pipe(struct drm_connector *connector,
9899 struct intel_load_detect_pipe *old,
9900 struct drm_modeset_acquire_ctx *ctx)
9901 {
9902 struct intel_encoder *intel_encoder =
9903 intel_attached_encoder(connector);
9904 struct drm_encoder *encoder = &intel_encoder->base;
9905 struct drm_atomic_state *state = old->restore_state;
9906 int ret;
9907
9908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9909 connector->base.id, connector->name,
9910 encoder->base.id, encoder->name);
9911
9912 if (!state)
9913 return;
9914
9915 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9916 if (ret)
9917 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9918 drm_atomic_state_put(state);
9919 }
9920
9921 static int i9xx_pll_refclk(struct drm_device *dev,
9922 const struct intel_crtc_state *pipe_config)
9923 {
9924 struct drm_i915_private *dev_priv = to_i915(dev);
9925 u32 dpll = pipe_config->dpll_hw_state.dpll;
9926
9927 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9928 return dev_priv->vbt.lvds_ssc_freq;
9929 else if (HAS_PCH_SPLIT(dev_priv))
9930 return 120000;
9931 else if (!IS_GEN2(dev_priv))
9932 return 96000;
9933 else
9934 return 48000;
9935 }
9936
9937 /* Returns the clock of the currently programmed mode of the given pipe. */
9938 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9939 struct intel_crtc_state *pipe_config)
9940 {
9941 struct drm_device *dev = crtc->base.dev;
9942 struct drm_i915_private *dev_priv = to_i915(dev);
9943 int pipe = pipe_config->cpu_transcoder;
9944 u32 dpll = pipe_config->dpll_hw_state.dpll;
9945 u32 fp;
9946 struct dpll clock;
9947 int port_clock;
9948 int refclk = i9xx_pll_refclk(dev, pipe_config);
9949
9950 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9951 fp = pipe_config->dpll_hw_state.fp0;
9952 else
9953 fp = pipe_config->dpll_hw_state.fp1;
9954
9955 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9956 if (IS_PINEVIEW(dev_priv)) {
9957 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9958 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9959 } else {
9960 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9961 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9962 }
9963
9964 if (!IS_GEN2(dev_priv)) {
9965 if (IS_PINEVIEW(dev_priv))
9966 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9967 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9968 else
9969 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9970 DPLL_FPA01_P1_POST_DIV_SHIFT);
9971
9972 switch (dpll & DPLL_MODE_MASK) {
9973 case DPLLB_MODE_DAC_SERIAL:
9974 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9975 5 : 10;
9976 break;
9977 case DPLLB_MODE_LVDS:
9978 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9979 7 : 14;
9980 break;
9981 default:
9982 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9983 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9984 return;
9985 }
9986
9987 if (IS_PINEVIEW(dev_priv))
9988 port_clock = pnv_calc_dpll_params(refclk, &clock);
9989 else
9990 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9991 } else {
9992 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9993 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9994
9995 if (is_lvds) {
9996 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9997 DPLL_FPA01_P1_POST_DIV_SHIFT);
9998
9999 if (lvds & LVDS_CLKB_POWER_UP)
10000 clock.p2 = 7;
10001 else
10002 clock.p2 = 14;
10003 } else {
10004 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10005 clock.p1 = 2;
10006 else {
10007 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10008 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10009 }
10010 if (dpll & PLL_P2_DIVIDE_BY_4)
10011 clock.p2 = 4;
10012 else
10013 clock.p2 = 2;
10014 }
10015
10016 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10017 }
10018
10019 /*
10020 * This value includes pixel_multiplier. We will use
10021 * port_clock to compute adjusted_mode.crtc_clock in the
10022 * encoder's get_config() function.
10023 */
10024 pipe_config->port_clock = port_clock;
10025 }
10026
10027 int intel_dotclock_calculate(int link_freq,
10028 const struct intel_link_m_n *m_n)
10029 {
10030 /*
10031 * The calculation for the data clock is:
10032 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10033 * But we want to avoid losing precison if possible, so:
10034 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10035 *
10036 * and the link clock is simpler:
10037 * link_clock = (m * link_clock) / n
10038 */
10039
10040 if (!m_n->link_n)
10041 return 0;
10042
10043 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10044 }
10045
10046 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10047 struct intel_crtc_state *pipe_config)
10048 {
10049 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10050
10051 /* read out port_clock from the DPLL */
10052 i9xx_crtc_clock_get(crtc, pipe_config);
10053
10054 /*
10055 * In case there is an active pipe without active ports,
10056 * we may need some idea for the dotclock anyway.
10057 * Calculate one based on the FDI configuration.
10058 */
10059 pipe_config->base.adjusted_mode.crtc_clock =
10060 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10061 &pipe_config->fdi_m_n);
10062 }
10063
10064 /** Returns the currently programmed mode of the given pipe. */
10065 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10066 struct drm_crtc *crtc)
10067 {
10068 struct drm_i915_private *dev_priv = to_i915(dev);
10069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10070 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10071 struct drm_display_mode *mode;
10072 struct intel_crtc_state *pipe_config;
10073 int htot = I915_READ(HTOTAL(cpu_transcoder));
10074 int hsync = I915_READ(HSYNC(cpu_transcoder));
10075 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10076 int vsync = I915_READ(VSYNC(cpu_transcoder));
10077 enum pipe pipe = intel_crtc->pipe;
10078
10079 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10080 if (!mode)
10081 return NULL;
10082
10083 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10084 if (!pipe_config) {
10085 kfree(mode);
10086 return NULL;
10087 }
10088
10089 /*
10090 * Construct a pipe_config sufficient for getting the clock info
10091 * back out of crtc_clock_get.
10092 *
10093 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10094 * to use a real value here instead.
10095 */
10096 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10097 pipe_config->pixel_multiplier = 1;
10098 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10099 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10100 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10101 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10102
10103 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10104 mode->hdisplay = (htot & 0xffff) + 1;
10105 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10106 mode->hsync_start = (hsync & 0xffff) + 1;
10107 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10108 mode->vdisplay = (vtot & 0xffff) + 1;
10109 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10110 mode->vsync_start = (vsync & 0xffff) + 1;
10111 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10112
10113 drm_mode_set_name(mode);
10114
10115 kfree(pipe_config);
10116
10117 return mode;
10118 }
10119
10120 static void intel_crtc_destroy(struct drm_crtc *crtc)
10121 {
10122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10123 struct drm_device *dev = crtc->dev;
10124 struct intel_flip_work *work;
10125
10126 spin_lock_irq(&dev->event_lock);
10127 work = intel_crtc->flip_work;
10128 intel_crtc->flip_work = NULL;
10129 spin_unlock_irq(&dev->event_lock);
10130
10131 if (work) {
10132 cancel_work_sync(&work->mmio_work);
10133 cancel_work_sync(&work->unpin_work);
10134 kfree(work);
10135 }
10136
10137 drm_crtc_cleanup(crtc);
10138
10139 kfree(intel_crtc);
10140 }
10141
10142 static void intel_unpin_work_fn(struct work_struct *__work)
10143 {
10144 struct intel_flip_work *work =
10145 container_of(__work, struct intel_flip_work, unpin_work);
10146 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10147 struct drm_device *dev = crtc->base.dev;
10148 struct drm_plane *primary = crtc->base.primary;
10149
10150 if (is_mmio_work(work))
10151 flush_work(&work->mmio_work);
10152
10153 mutex_lock(&dev->struct_mutex);
10154 intel_unpin_fb_vma(work->old_vma);
10155 i915_gem_object_put(work->pending_flip_obj);
10156 mutex_unlock(&dev->struct_mutex);
10157
10158 i915_gem_request_put(work->flip_queued_req);
10159
10160 intel_frontbuffer_flip_complete(to_i915(dev),
10161 to_intel_plane(primary)->frontbuffer_bit);
10162 intel_fbc_post_update(crtc);
10163 drm_framebuffer_unreference(work->old_fb);
10164
10165 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10166 atomic_dec(&crtc->unpin_work_count);
10167
10168 kfree(work);
10169 }
10170
10171 /* Is 'a' after or equal to 'b'? */
10172 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10173 {
10174 return !((a - b) & 0x80000000);
10175 }
10176
10177 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10178 struct intel_flip_work *work)
10179 {
10180 struct drm_device *dev = crtc->base.dev;
10181 struct drm_i915_private *dev_priv = to_i915(dev);
10182
10183 if (abort_flip_on_reset(crtc))
10184 return true;
10185
10186 /*
10187 * The relevant registers doen't exist on pre-ctg.
10188 * As the flip done interrupt doesn't trigger for mmio
10189 * flips on gmch platforms, a flip count check isn't
10190 * really needed there. But since ctg has the registers,
10191 * include it in the check anyway.
10192 */
10193 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10194 return true;
10195
10196 /*
10197 * BDW signals flip done immediately if the plane
10198 * is disabled, even if the plane enable is already
10199 * armed to occur at the next vblank :(
10200 */
10201
10202 /*
10203 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10204 * used the same base address. In that case the mmio flip might
10205 * have completed, but the CS hasn't even executed the flip yet.
10206 *
10207 * A flip count check isn't enough as the CS might have updated
10208 * the base address just after start of vblank, but before we
10209 * managed to process the interrupt. This means we'd complete the
10210 * CS flip too soon.
10211 *
10212 * Combining both checks should get us a good enough result. It may
10213 * still happen that the CS flip has been executed, but has not
10214 * yet actually completed. But in case the base address is the same
10215 * anyway, we don't really care.
10216 */
10217 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10218 crtc->flip_work->gtt_offset &&
10219 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10220 crtc->flip_work->flip_count);
10221 }
10222
10223 static bool
10224 __pageflip_finished_mmio(struct intel_crtc *crtc,
10225 struct intel_flip_work *work)
10226 {
10227 /*
10228 * MMIO work completes when vblank is different from
10229 * flip_queued_vblank.
10230 *
10231 * Reset counter value doesn't matter, this is handled by
10232 * i915_wait_request finishing early, so no need to handle
10233 * reset here.
10234 */
10235 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10236 }
10237
10238
10239 static bool pageflip_finished(struct intel_crtc *crtc,
10240 struct intel_flip_work *work)
10241 {
10242 if (!atomic_read(&work->pending))
10243 return false;
10244
10245 smp_rmb();
10246
10247 if (is_mmio_work(work))
10248 return __pageflip_finished_mmio(crtc, work);
10249 else
10250 return __pageflip_finished_cs(crtc, work);
10251 }
10252
10253 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10254 {
10255 struct drm_device *dev = &dev_priv->drm;
10256 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10257 struct intel_flip_work *work;
10258 unsigned long flags;
10259
10260 /* Ignore early vblank irqs */
10261 if (!crtc)
10262 return;
10263
10264 /*
10265 * This is called both by irq handlers and the reset code (to complete
10266 * lost pageflips) so needs the full irqsave spinlocks.
10267 */
10268 spin_lock_irqsave(&dev->event_lock, flags);
10269 work = crtc->flip_work;
10270
10271 if (work != NULL &&
10272 !is_mmio_work(work) &&
10273 pageflip_finished(crtc, work))
10274 page_flip_completed(crtc);
10275
10276 spin_unlock_irqrestore(&dev->event_lock, flags);
10277 }
10278
10279 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10280 {
10281 struct drm_device *dev = &dev_priv->drm;
10282 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10283 struct intel_flip_work *work;
10284 unsigned long flags;
10285
10286 /* Ignore early vblank irqs */
10287 if (!crtc)
10288 return;
10289
10290 /*
10291 * This is called both by irq handlers and the reset code (to complete
10292 * lost pageflips) so needs the full irqsave spinlocks.
10293 */
10294 spin_lock_irqsave(&dev->event_lock, flags);
10295 work = crtc->flip_work;
10296
10297 if (work != NULL &&
10298 is_mmio_work(work) &&
10299 pageflip_finished(crtc, work))
10300 page_flip_completed(crtc);
10301
10302 spin_unlock_irqrestore(&dev->event_lock, flags);
10303 }
10304
10305 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10306 struct intel_flip_work *work)
10307 {
10308 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10309
10310 /* Ensure that the work item is consistent when activating it ... */
10311 smp_mb__before_atomic();
10312 atomic_set(&work->pending, 1);
10313 }
10314
10315 static int intel_gen2_queue_flip(struct drm_device *dev,
10316 struct drm_crtc *crtc,
10317 struct drm_framebuffer *fb,
10318 struct drm_i915_gem_object *obj,
10319 struct drm_i915_gem_request *req,
10320 uint32_t flags)
10321 {
10322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10323 u32 flip_mask, *cs;
10324
10325 cs = intel_ring_begin(req, 6);
10326 if (IS_ERR(cs))
10327 return PTR_ERR(cs);
10328
10329 /* Can't queue multiple flips, so wait for the previous
10330 * one to finish before executing the next.
10331 */
10332 if (intel_crtc->plane)
10333 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10334 else
10335 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10336 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10337 *cs++ = MI_NOOP;
10338 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10339 *cs++ = fb->pitches[0];
10340 *cs++ = intel_crtc->flip_work->gtt_offset;
10341 *cs++ = 0; /* aux display base address, unused */
10342
10343 return 0;
10344 }
10345
10346 static int intel_gen3_queue_flip(struct drm_device *dev,
10347 struct drm_crtc *crtc,
10348 struct drm_framebuffer *fb,
10349 struct drm_i915_gem_object *obj,
10350 struct drm_i915_gem_request *req,
10351 uint32_t flags)
10352 {
10353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10354 u32 flip_mask, *cs;
10355
10356 cs = intel_ring_begin(req, 6);
10357 if (IS_ERR(cs))
10358 return PTR_ERR(cs);
10359
10360 if (intel_crtc->plane)
10361 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10362 else
10363 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10364 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10365 *cs++ = MI_NOOP;
10366 *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10367 *cs++ = fb->pitches[0];
10368 *cs++ = intel_crtc->flip_work->gtt_offset;
10369 *cs++ = MI_NOOP;
10370
10371 return 0;
10372 }
10373
10374 static int intel_gen4_queue_flip(struct drm_device *dev,
10375 struct drm_crtc *crtc,
10376 struct drm_framebuffer *fb,
10377 struct drm_i915_gem_object *obj,
10378 struct drm_i915_gem_request *req,
10379 uint32_t flags)
10380 {
10381 struct drm_i915_private *dev_priv = to_i915(dev);
10382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10383 u32 pf, pipesrc, *cs;
10384
10385 cs = intel_ring_begin(req, 4);
10386 if (IS_ERR(cs))
10387 return PTR_ERR(cs);
10388
10389 /* i965+ uses the linear or tiled offsets from the
10390 * Display Registers (which do not change across a page-flip)
10391 * so we need only reprogram the base address.
10392 */
10393 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10394 *cs++ = fb->pitches[0];
10395 *cs++ = intel_crtc->flip_work->gtt_offset |
10396 intel_fb_modifier_to_tiling(fb->modifier);
10397
10398 /* XXX Enabling the panel-fitter across page-flip is so far
10399 * untested on non-native modes, so ignore it for now.
10400 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10401 */
10402 pf = 0;
10403 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10404 *cs++ = pf | pipesrc;
10405
10406 return 0;
10407 }
10408
10409 static int intel_gen6_queue_flip(struct drm_device *dev,
10410 struct drm_crtc *crtc,
10411 struct drm_framebuffer *fb,
10412 struct drm_i915_gem_object *obj,
10413 struct drm_i915_gem_request *req,
10414 uint32_t flags)
10415 {
10416 struct drm_i915_private *dev_priv = to_i915(dev);
10417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10418 u32 pf, pipesrc, *cs;
10419
10420 cs = intel_ring_begin(req, 4);
10421 if (IS_ERR(cs))
10422 return PTR_ERR(cs);
10423
10424 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10425 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10426 *cs++ = intel_crtc->flip_work->gtt_offset;
10427
10428 /* Contrary to the suggestions in the documentation,
10429 * "Enable Panel Fitter" does not seem to be required when page
10430 * flipping with a non-native mode, and worse causes a normal
10431 * modeset to fail.
10432 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10433 */
10434 pf = 0;
10435 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10436 *cs++ = pf | pipesrc;
10437
10438 return 0;
10439 }
10440
10441 static int intel_gen7_queue_flip(struct drm_device *dev,
10442 struct drm_crtc *crtc,
10443 struct drm_framebuffer *fb,
10444 struct drm_i915_gem_object *obj,
10445 struct drm_i915_gem_request *req,
10446 uint32_t flags)
10447 {
10448 struct drm_i915_private *dev_priv = to_i915(dev);
10449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10450 u32 *cs, plane_bit = 0;
10451 int len, ret;
10452
10453 switch (intel_crtc->plane) {
10454 case PLANE_A:
10455 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10456 break;
10457 case PLANE_B:
10458 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10459 break;
10460 case PLANE_C:
10461 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10462 break;
10463 default:
10464 WARN_ONCE(1, "unknown plane in flip command\n");
10465 return -ENODEV;
10466 }
10467
10468 len = 4;
10469 if (req->engine->id == RCS) {
10470 len += 6;
10471 /*
10472 * On Gen 8, SRM is now taking an extra dword to accommodate
10473 * 48bits addresses, and we need a NOOP for the batch size to
10474 * stay even.
10475 */
10476 if (IS_GEN8(dev_priv))
10477 len += 2;
10478 }
10479
10480 /*
10481 * BSpec MI_DISPLAY_FLIP for IVB:
10482 * "The full packet must be contained within the same cache line."
10483 *
10484 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10485 * cacheline, if we ever start emitting more commands before
10486 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10487 * then do the cacheline alignment, and finally emit the
10488 * MI_DISPLAY_FLIP.
10489 */
10490 ret = intel_ring_cacheline_align(req);
10491 if (ret)
10492 return ret;
10493
10494 cs = intel_ring_begin(req, len);
10495 if (IS_ERR(cs))
10496 return PTR_ERR(cs);
10497
10498 /* Unmask the flip-done completion message. Note that the bspec says that
10499 * we should do this for both the BCS and RCS, and that we must not unmask
10500 * more than one flip event at any time (or ensure that one flip message
10501 * can be sent by waiting for flip-done prior to queueing new flips).
10502 * Experimentation says that BCS works despite DERRMR masking all
10503 * flip-done completion events and that unmasking all planes at once
10504 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10505 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10506 */
10507 if (req->engine->id == RCS) {
10508 *cs++ = MI_LOAD_REGISTER_IMM(1);
10509 *cs++ = i915_mmio_reg_offset(DERRMR);
10510 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10511 DERRMR_PIPEB_PRI_FLIP_DONE |
10512 DERRMR_PIPEC_PRI_FLIP_DONE);
10513 if (IS_GEN8(dev_priv))
10514 *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10515 MI_SRM_LRM_GLOBAL_GTT;
10516 else
10517 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10518 *cs++ = i915_mmio_reg_offset(DERRMR);
10519 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10520 if (IS_GEN8(dev_priv)) {
10521 *cs++ = 0;
10522 *cs++ = MI_NOOP;
10523 }
10524 }
10525
10526 *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10527 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10528 *cs++ = intel_crtc->flip_work->gtt_offset;
10529 *cs++ = MI_NOOP;
10530
10531 return 0;
10532 }
10533
10534 static bool use_mmio_flip(struct intel_engine_cs *engine,
10535 struct drm_i915_gem_object *obj)
10536 {
10537 /*
10538 * This is not being used for older platforms, because
10539 * non-availability of flip done interrupt forces us to use
10540 * CS flips. Older platforms derive flip done using some clever
10541 * tricks involving the flip_pending status bits and vblank irqs.
10542 * So using MMIO flips there would disrupt this mechanism.
10543 */
10544
10545 if (engine == NULL)
10546 return true;
10547
10548 if (INTEL_GEN(engine->i915) < 5)
10549 return false;
10550
10551 if (i915.use_mmio_flip < 0)
10552 return false;
10553 else if (i915.use_mmio_flip > 0)
10554 return true;
10555 else if (i915.enable_execlists)
10556 return true;
10557
10558 return engine != i915_gem_object_last_write_engine(obj);
10559 }
10560
10561 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10562 unsigned int rotation,
10563 struct intel_flip_work *work)
10564 {
10565 struct drm_device *dev = intel_crtc->base.dev;
10566 struct drm_i915_private *dev_priv = to_i915(dev);
10567 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10568 const enum pipe pipe = intel_crtc->pipe;
10569 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10570
10571 ctl = I915_READ(PLANE_CTL(pipe, 0));
10572 ctl &= ~PLANE_CTL_TILED_MASK;
10573 switch (fb->modifier) {
10574 case DRM_FORMAT_MOD_LINEAR:
10575 break;
10576 case I915_FORMAT_MOD_X_TILED:
10577 ctl |= PLANE_CTL_TILED_X;
10578 break;
10579 case I915_FORMAT_MOD_Y_TILED:
10580 ctl |= PLANE_CTL_TILED_Y;
10581 break;
10582 case I915_FORMAT_MOD_Yf_TILED:
10583 ctl |= PLANE_CTL_TILED_YF;
10584 break;
10585 default:
10586 MISSING_CASE(fb->modifier);
10587 }
10588
10589 /*
10590 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10591 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10592 */
10593 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10594 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10595
10596 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10597 POSTING_READ(PLANE_SURF(pipe, 0));
10598 }
10599
10600 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10601 struct intel_flip_work *work)
10602 {
10603 struct drm_device *dev = intel_crtc->base.dev;
10604 struct drm_i915_private *dev_priv = to_i915(dev);
10605 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10606 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10607 u32 dspcntr;
10608
10609 dspcntr = I915_READ(reg);
10610
10611 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10612 dspcntr |= DISPPLANE_TILED;
10613 else
10614 dspcntr &= ~DISPPLANE_TILED;
10615
10616 I915_WRITE(reg, dspcntr);
10617
10618 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10619 POSTING_READ(DSPSURF(intel_crtc->plane));
10620 }
10621
10622 static void intel_mmio_flip_work_func(struct work_struct *w)
10623 {
10624 struct intel_flip_work *work =
10625 container_of(w, struct intel_flip_work, mmio_work);
10626 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10627 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10628 struct intel_framebuffer *intel_fb =
10629 to_intel_framebuffer(crtc->base.primary->fb);
10630 struct drm_i915_gem_object *obj = intel_fb->obj;
10631
10632 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10633
10634 intel_pipe_update_start(crtc);
10635
10636 if (INTEL_GEN(dev_priv) >= 9)
10637 skl_do_mmio_flip(crtc, work->rotation, work);
10638 else
10639 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10640 ilk_do_mmio_flip(crtc, work);
10641
10642 intel_pipe_update_end(crtc, work);
10643 }
10644
10645 static int intel_default_queue_flip(struct drm_device *dev,
10646 struct drm_crtc *crtc,
10647 struct drm_framebuffer *fb,
10648 struct drm_i915_gem_object *obj,
10649 struct drm_i915_gem_request *req,
10650 uint32_t flags)
10651 {
10652 return -ENODEV;
10653 }
10654
10655 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10656 struct intel_crtc *intel_crtc,
10657 struct intel_flip_work *work)
10658 {
10659 u32 addr, vblank;
10660
10661 if (!atomic_read(&work->pending))
10662 return false;
10663
10664 smp_rmb();
10665
10666 vblank = intel_crtc_get_vblank_counter(intel_crtc);
10667 if (work->flip_ready_vblank == 0) {
10668 if (work->flip_queued_req &&
10669 !i915_gem_request_completed(work->flip_queued_req))
10670 return false;
10671
10672 work->flip_ready_vblank = vblank;
10673 }
10674
10675 if (vblank - work->flip_ready_vblank < 3)
10676 return false;
10677
10678 /* Potential stall - if we see that the flip has happened,
10679 * assume a missed interrupt. */
10680 if (INTEL_GEN(dev_priv) >= 4)
10681 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10682 else
10683 addr = I915_READ(DSPADDR(intel_crtc->plane));
10684
10685 /* There is a potential issue here with a false positive after a flip
10686 * to the same address. We could address this by checking for a
10687 * non-incrementing frame counter.
10688 */
10689 return addr == work->gtt_offset;
10690 }
10691
10692 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10693 {
10694 struct drm_device *dev = &dev_priv->drm;
10695 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10696 struct intel_flip_work *work;
10697
10698 WARN_ON(!in_interrupt());
10699
10700 if (crtc == NULL)
10701 return;
10702
10703 spin_lock(&dev->event_lock);
10704 work = crtc->flip_work;
10705
10706 if (work != NULL && !is_mmio_work(work) &&
10707 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10708 WARN_ONCE(1,
10709 "Kicking stuck page flip: queued at %d, now %d\n",
10710 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10711 page_flip_completed(crtc);
10712 work = NULL;
10713 }
10714
10715 if (work != NULL && !is_mmio_work(work) &&
10716 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10717 intel_queue_rps_boost_for_request(work->flip_queued_req);
10718 spin_unlock(&dev->event_lock);
10719 }
10720
10721 __maybe_unused
10722 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10723 struct drm_framebuffer *fb,
10724 struct drm_pending_vblank_event *event,
10725 uint32_t page_flip_flags)
10726 {
10727 struct drm_device *dev = crtc->dev;
10728 struct drm_i915_private *dev_priv = to_i915(dev);
10729 struct drm_framebuffer *old_fb = crtc->primary->fb;
10730 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10732 struct drm_plane *primary = crtc->primary;
10733 enum pipe pipe = intel_crtc->pipe;
10734 struct intel_flip_work *work;
10735 struct intel_engine_cs *engine;
10736 bool mmio_flip;
10737 struct drm_i915_gem_request *request;
10738 struct i915_vma *vma;
10739 int ret;
10740
10741 /*
10742 * drm_mode_page_flip_ioctl() should already catch this, but double
10743 * check to be safe. In the future we may enable pageflipping from
10744 * a disabled primary plane.
10745 */
10746 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10747 return -EBUSY;
10748
10749 /* Can't change pixel format via MI display flips. */
10750 if (fb->format != crtc->primary->fb->format)
10751 return -EINVAL;
10752
10753 /*
10754 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10755 * Note that pitch changes could also affect these register.
10756 */
10757 if (INTEL_GEN(dev_priv) > 3 &&
10758 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10759 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10760 return -EINVAL;
10761
10762 if (i915_terminally_wedged(&dev_priv->gpu_error))
10763 goto out_hang;
10764
10765 work = kzalloc(sizeof(*work), GFP_KERNEL);
10766 if (work == NULL)
10767 return -ENOMEM;
10768
10769 work->event = event;
10770 work->crtc = crtc;
10771 work->old_fb = old_fb;
10772 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10773
10774 ret = drm_crtc_vblank_get(crtc);
10775 if (ret)
10776 goto free_work;
10777
10778 /* We borrow the event spin lock for protecting flip_work */
10779 spin_lock_irq(&dev->event_lock);
10780 if (intel_crtc->flip_work) {
10781 /* Before declaring the flip queue wedged, check if
10782 * the hardware completed the operation behind our backs.
10783 */
10784 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10785 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10786 page_flip_completed(intel_crtc);
10787 } else {
10788 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10789 spin_unlock_irq(&dev->event_lock);
10790
10791 drm_crtc_vblank_put(crtc);
10792 kfree(work);
10793 return -EBUSY;
10794 }
10795 }
10796 intel_crtc->flip_work = work;
10797 spin_unlock_irq(&dev->event_lock);
10798
10799 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10800 flush_workqueue(dev_priv->wq);
10801
10802 /* Reference the objects for the scheduled work. */
10803 drm_framebuffer_reference(work->old_fb);
10804
10805 crtc->primary->fb = fb;
10806 update_state_fb(crtc->primary);
10807
10808 work->pending_flip_obj = i915_gem_object_get(obj);
10809
10810 ret = i915_mutex_lock_interruptible(dev);
10811 if (ret)
10812 goto cleanup;
10813
10814 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10815 if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10816 ret = -EIO;
10817 goto unlock;
10818 }
10819
10820 atomic_inc(&intel_crtc->unpin_work_count);
10821
10822 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10823 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10824
10825 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10826 engine = dev_priv->engine[BCS];
10827 if (fb->modifier != old_fb->modifier)
10828 /* vlv: DISPLAY_FLIP fails to change tiling */
10829 engine = NULL;
10830 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10831 engine = dev_priv->engine[BCS];
10832 } else if (INTEL_GEN(dev_priv) >= 7) {
10833 engine = i915_gem_object_last_write_engine(obj);
10834 if (engine == NULL || engine->id != RCS)
10835 engine = dev_priv->engine[BCS];
10836 } else {
10837 engine = dev_priv->engine[RCS];
10838 }
10839
10840 mmio_flip = use_mmio_flip(engine, obj);
10841
10842 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10843 if (IS_ERR(vma)) {
10844 ret = PTR_ERR(vma);
10845 goto cleanup_pending;
10846 }
10847
10848 work->old_vma = to_intel_plane_state(primary->state)->vma;
10849 to_intel_plane_state(primary->state)->vma = vma;
10850
10851 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10852 work->rotation = crtc->primary->state->rotation;
10853
10854 /*
10855 * There's the potential that the next frame will not be compatible with
10856 * FBC, so we want to call pre_update() before the actual page flip.
10857 * The problem is that pre_update() caches some information about the fb
10858 * object, so we want to do this only after the object is pinned. Let's
10859 * be on the safe side and do this immediately before scheduling the
10860 * flip.
10861 */
10862 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10863 to_intel_plane_state(primary->state));
10864
10865 if (mmio_flip) {
10866 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10867 queue_work(system_unbound_wq, &work->mmio_work);
10868 } else {
10869 request = i915_gem_request_alloc(engine,
10870 dev_priv->kernel_context);
10871 if (IS_ERR(request)) {
10872 ret = PTR_ERR(request);
10873 goto cleanup_unpin;
10874 }
10875
10876 ret = i915_gem_request_await_object(request, obj, false);
10877 if (ret)
10878 goto cleanup_request;
10879
10880 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10881 page_flip_flags);
10882 if (ret)
10883 goto cleanup_request;
10884
10885 intel_mark_page_flip_active(intel_crtc, work);
10886
10887 work->flip_queued_req = i915_gem_request_get(request);
10888 i915_add_request(request);
10889 }
10890
10891 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10892 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10893 to_intel_plane(primary)->frontbuffer_bit);
10894 mutex_unlock(&dev->struct_mutex);
10895
10896 intel_frontbuffer_flip_prepare(to_i915(dev),
10897 to_intel_plane(primary)->frontbuffer_bit);
10898
10899 trace_i915_flip_request(intel_crtc->plane, obj);
10900
10901 return 0;
10902
10903 cleanup_request:
10904 i915_add_request(request);
10905 cleanup_unpin:
10906 to_intel_plane_state(primary->state)->vma = work->old_vma;
10907 intel_unpin_fb_vma(vma);
10908 cleanup_pending:
10909 atomic_dec(&intel_crtc->unpin_work_count);
10910 unlock:
10911 mutex_unlock(&dev->struct_mutex);
10912 cleanup:
10913 crtc->primary->fb = old_fb;
10914 update_state_fb(crtc->primary);
10915
10916 i915_gem_object_put(obj);
10917 drm_framebuffer_unreference(work->old_fb);
10918
10919 spin_lock_irq(&dev->event_lock);
10920 intel_crtc->flip_work = NULL;
10921 spin_unlock_irq(&dev->event_lock);
10922
10923 drm_crtc_vblank_put(crtc);
10924 free_work:
10925 kfree(work);
10926
10927 if (ret == -EIO) {
10928 struct drm_atomic_state *state;
10929 struct drm_plane_state *plane_state;
10930
10931 out_hang:
10932 state = drm_atomic_state_alloc(dev);
10933 if (!state)
10934 return -ENOMEM;
10935 state->acquire_ctx = dev->mode_config.acquire_ctx;
10936
10937 retry:
10938 plane_state = drm_atomic_get_plane_state(state, primary);
10939 ret = PTR_ERR_OR_ZERO(plane_state);
10940 if (!ret) {
10941 drm_atomic_set_fb_for_plane(plane_state, fb);
10942
10943 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10944 if (!ret)
10945 ret = drm_atomic_commit(state);
10946 }
10947
10948 if (ret == -EDEADLK) {
10949 drm_modeset_backoff(state->acquire_ctx);
10950 drm_atomic_state_clear(state);
10951 goto retry;
10952 }
10953
10954 drm_atomic_state_put(state);
10955
10956 if (ret == 0 && event) {
10957 spin_lock_irq(&dev->event_lock);
10958 drm_crtc_send_vblank_event(crtc, event);
10959 spin_unlock_irq(&dev->event_lock);
10960 }
10961 }
10962 return ret;
10963 }
10964
10965
10966 /**
10967 * intel_wm_need_update - Check whether watermarks need updating
10968 * @plane: drm plane
10969 * @state: new plane state
10970 *
10971 * Check current plane state versus the new one to determine whether
10972 * watermarks need to be recalculated.
10973 *
10974 * Returns true or false.
10975 */
10976 static bool intel_wm_need_update(struct drm_plane *plane,
10977 struct drm_plane_state *state)
10978 {
10979 struct intel_plane_state *new = to_intel_plane_state(state);
10980 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10981
10982 /* Update watermarks on tiling or size changes. */
10983 if (new->base.visible != cur->base.visible)
10984 return true;
10985
10986 if (!cur->base.fb || !new->base.fb)
10987 return false;
10988
10989 if (cur->base.fb->modifier != new->base.fb->modifier ||
10990 cur->base.rotation != new->base.rotation ||
10991 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10992 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10993 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10994 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10995 return true;
10996
10997 return false;
10998 }
10999
11000 static bool needs_scaling(struct intel_plane_state *state)
11001 {
11002 int src_w = drm_rect_width(&state->base.src) >> 16;
11003 int src_h = drm_rect_height(&state->base.src) >> 16;
11004 int dst_w = drm_rect_width(&state->base.dst);
11005 int dst_h = drm_rect_height(&state->base.dst);
11006
11007 return (src_w != dst_w || src_h != dst_h);
11008 }
11009
11010 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11011 struct drm_plane_state *plane_state)
11012 {
11013 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11014 struct drm_crtc *crtc = crtc_state->crtc;
11015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11016 struct intel_plane *plane = to_intel_plane(plane_state->plane);
11017 struct drm_device *dev = crtc->dev;
11018 struct drm_i915_private *dev_priv = to_i915(dev);
11019 struct intel_plane_state *old_plane_state =
11020 to_intel_plane_state(plane->base.state);
11021 bool mode_changed = needs_modeset(crtc_state);
11022 bool was_crtc_enabled = crtc->state->active;
11023 bool is_crtc_enabled = crtc_state->active;
11024 bool turn_off, turn_on, visible, was_visible;
11025 struct drm_framebuffer *fb = plane_state->fb;
11026 int ret;
11027
11028 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11029 ret = skl_update_scaler_plane(
11030 to_intel_crtc_state(crtc_state),
11031 to_intel_plane_state(plane_state));
11032 if (ret)
11033 return ret;
11034 }
11035
11036 was_visible = old_plane_state->base.visible;
11037 visible = plane_state->visible;
11038
11039 if (!was_crtc_enabled && WARN_ON(was_visible))
11040 was_visible = false;
11041
11042 /*
11043 * Visibility is calculated as if the crtc was on, but
11044 * after scaler setup everything depends on it being off
11045 * when the crtc isn't active.
11046 *
11047 * FIXME this is wrong for watermarks. Watermarks should also
11048 * be computed as if the pipe would be active. Perhaps move
11049 * per-plane wm computation to the .check_plane() hook, and
11050 * only combine the results from all planes in the current place?
11051 */
11052 if (!is_crtc_enabled) {
11053 plane_state->visible = visible = false;
11054 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
11055 }
11056
11057 if (!was_visible && !visible)
11058 return 0;
11059
11060 if (fb != old_plane_state->base.fb)
11061 pipe_config->fb_changed = true;
11062
11063 turn_off = was_visible && (!visible || mode_changed);
11064 turn_on = visible && (!was_visible || mode_changed);
11065
11066 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11067 intel_crtc->base.base.id, intel_crtc->base.name,
11068 plane->base.base.id, plane->base.name,
11069 fb ? fb->base.id : -1);
11070
11071 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11072 plane->base.base.id, plane->base.name,
11073 was_visible, visible,
11074 turn_off, turn_on, mode_changed);
11075
11076 if (turn_on) {
11077 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11078 pipe_config->update_wm_pre = true;
11079
11080 /* must disable cxsr around plane enable/disable */
11081 if (plane->id != PLANE_CURSOR)
11082 pipe_config->disable_cxsr = true;
11083 } else if (turn_off) {
11084 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11085 pipe_config->update_wm_post = true;
11086
11087 /* must disable cxsr around plane enable/disable */
11088 if (plane->id != PLANE_CURSOR)
11089 pipe_config->disable_cxsr = true;
11090 } else if (intel_wm_need_update(&plane->base, plane_state)) {
11091 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11092 /* FIXME bollocks */
11093 pipe_config->update_wm_pre = true;
11094 pipe_config->update_wm_post = true;
11095 }
11096 }
11097
11098 if (visible || was_visible)
11099 pipe_config->fb_bits |= plane->frontbuffer_bit;
11100
11101 /*
11102 * WaCxSRDisabledForSpriteScaling:ivb
11103 *
11104 * cstate->update_wm was already set above, so this flag will
11105 * take effect when we commit and program watermarks.
11106 */
11107 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
11108 needs_scaling(to_intel_plane_state(plane_state)) &&
11109 !needs_scaling(old_plane_state))
11110 pipe_config->disable_lp_wm = true;
11111
11112 return 0;
11113 }
11114
11115 static bool encoders_cloneable(const struct intel_encoder *a,
11116 const struct intel_encoder *b)
11117 {
11118 /* masks could be asymmetric, so check both ways */
11119 return a == b || (a->cloneable & (1 << b->type) &&
11120 b->cloneable & (1 << a->type));
11121 }
11122
11123 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11124 struct intel_crtc *crtc,
11125 struct intel_encoder *encoder)
11126 {
11127 struct intel_encoder *source_encoder;
11128 struct drm_connector *connector;
11129 struct drm_connector_state *connector_state;
11130 int i;
11131
11132 for_each_new_connector_in_state(state, connector, connector_state, i) {
11133 if (connector_state->crtc != &crtc->base)
11134 continue;
11135
11136 source_encoder =
11137 to_intel_encoder(connector_state->best_encoder);
11138 if (!encoders_cloneable(encoder, source_encoder))
11139 return false;
11140 }
11141
11142 return true;
11143 }
11144
11145 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11146 struct drm_crtc_state *crtc_state)
11147 {
11148 struct drm_device *dev = crtc->dev;
11149 struct drm_i915_private *dev_priv = to_i915(dev);
11150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11151 struct intel_crtc_state *pipe_config =
11152 to_intel_crtc_state(crtc_state);
11153 struct drm_atomic_state *state = crtc_state->state;
11154 int ret;
11155 bool mode_changed = needs_modeset(crtc_state);
11156
11157 if (mode_changed && !crtc_state->active)
11158 pipe_config->update_wm_post = true;
11159
11160 if (mode_changed && crtc_state->enable &&
11161 dev_priv->display.crtc_compute_clock &&
11162 !WARN_ON(pipe_config->shared_dpll)) {
11163 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11164 pipe_config);
11165 if (ret)
11166 return ret;
11167 }
11168
11169 if (crtc_state->color_mgmt_changed) {
11170 ret = intel_color_check(crtc, crtc_state);
11171 if (ret)
11172 return ret;
11173
11174 /*
11175 * Changing color management on Intel hardware is
11176 * handled as part of planes update.
11177 */
11178 crtc_state->planes_changed = true;
11179 }
11180
11181 ret = 0;
11182 if (dev_priv->display.compute_pipe_wm) {
11183 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11184 if (ret) {
11185 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11186 return ret;
11187 }
11188 }
11189
11190 if (dev_priv->display.compute_intermediate_wm &&
11191 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11192 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11193 return 0;
11194
11195 /*
11196 * Calculate 'intermediate' watermarks that satisfy both the
11197 * old state and the new state. We can program these
11198 * immediately.
11199 */
11200 ret = dev_priv->display.compute_intermediate_wm(dev,
11201 intel_crtc,
11202 pipe_config);
11203 if (ret) {
11204 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11205 return ret;
11206 }
11207 } else if (dev_priv->display.compute_intermediate_wm) {
11208 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11209 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11210 }
11211
11212 if (INTEL_GEN(dev_priv) >= 9) {
11213 if (mode_changed)
11214 ret = skl_update_scaler_crtc(pipe_config);
11215
11216 if (!ret)
11217 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
11218 pipe_config);
11219 if (!ret)
11220 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11221 pipe_config);
11222 }
11223
11224 return ret;
11225 }
11226
11227 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11228 .atomic_begin = intel_begin_crtc_commit,
11229 .atomic_flush = intel_finish_crtc_commit,
11230 .atomic_check = intel_crtc_atomic_check,
11231 };
11232
11233 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11234 {
11235 struct intel_connector *connector;
11236 struct drm_connector_list_iter conn_iter;
11237
11238 drm_connector_list_iter_begin(dev, &conn_iter);
11239 for_each_intel_connector_iter(connector, &conn_iter) {
11240 if (connector->base.state->crtc)
11241 drm_connector_unreference(&connector->base);
11242
11243 if (connector->base.encoder) {
11244 connector->base.state->best_encoder =
11245 connector->base.encoder;
11246 connector->base.state->crtc =
11247 connector->base.encoder->crtc;
11248
11249 drm_connector_reference(&connector->base);
11250 } else {
11251 connector->base.state->best_encoder = NULL;
11252 connector->base.state->crtc = NULL;
11253 }
11254 }
11255 drm_connector_list_iter_end(&conn_iter);
11256 }
11257
11258 static void
11259 connected_sink_compute_bpp(struct intel_connector *connector,
11260 struct intel_crtc_state *pipe_config)
11261 {
11262 const struct drm_display_info *info = &connector->base.display_info;
11263 int bpp = pipe_config->pipe_bpp;
11264
11265 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11266 connector->base.base.id,
11267 connector->base.name);
11268
11269 /* Don't use an invalid EDID bpc value */
11270 if (info->bpc != 0 && info->bpc * 3 < bpp) {
11271 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11272 bpp, info->bpc * 3);
11273 pipe_config->pipe_bpp = info->bpc * 3;
11274 }
11275
11276 /* Clamp bpp to 8 on screens without EDID 1.4 */
11277 if (info->bpc == 0 && bpp > 24) {
11278 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11279 bpp);
11280 pipe_config->pipe_bpp = 24;
11281 }
11282 }
11283
11284 static int
11285 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11286 struct intel_crtc_state *pipe_config)
11287 {
11288 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11289 struct drm_atomic_state *state;
11290 struct drm_connector *connector;
11291 struct drm_connector_state *connector_state;
11292 int bpp, i;
11293
11294 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11295 IS_CHERRYVIEW(dev_priv)))
11296 bpp = 10*3;
11297 else if (INTEL_GEN(dev_priv) >= 5)
11298 bpp = 12*3;
11299 else
11300 bpp = 8*3;
11301
11302
11303 pipe_config->pipe_bpp = bpp;
11304
11305 state = pipe_config->base.state;
11306
11307 /* Clamp display bpp to EDID value */
11308 for_each_new_connector_in_state(state, connector, connector_state, i) {
11309 if (connector_state->crtc != &crtc->base)
11310 continue;
11311
11312 connected_sink_compute_bpp(to_intel_connector(connector),
11313 pipe_config);
11314 }
11315
11316 return bpp;
11317 }
11318
11319 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11320 {
11321 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11322 "type: 0x%x flags: 0x%x\n",
11323 mode->crtc_clock,
11324 mode->crtc_hdisplay, mode->crtc_hsync_start,
11325 mode->crtc_hsync_end, mode->crtc_htotal,
11326 mode->crtc_vdisplay, mode->crtc_vsync_start,
11327 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11328 }
11329
11330 static inline void
11331 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11332 unsigned int lane_count, struct intel_link_m_n *m_n)
11333 {
11334 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11335 id, lane_count,
11336 m_n->gmch_m, m_n->gmch_n,
11337 m_n->link_m, m_n->link_n, m_n->tu);
11338 }
11339
11340 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11341 struct intel_crtc_state *pipe_config,
11342 const char *context)
11343 {
11344 struct drm_device *dev = crtc->base.dev;
11345 struct drm_i915_private *dev_priv = to_i915(dev);
11346 struct drm_plane *plane;
11347 struct intel_plane *intel_plane;
11348 struct intel_plane_state *state;
11349 struct drm_framebuffer *fb;
11350
11351 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11352 crtc->base.base.id, crtc->base.name, context);
11353
11354 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11355 transcoder_name(pipe_config->cpu_transcoder),
11356 pipe_config->pipe_bpp, pipe_config->dither);
11357
11358 if (pipe_config->has_pch_encoder)
11359 intel_dump_m_n_config(pipe_config, "fdi",
11360 pipe_config->fdi_lanes,
11361 &pipe_config->fdi_m_n);
11362
11363 if (intel_crtc_has_dp_encoder(pipe_config)) {
11364 intel_dump_m_n_config(pipe_config, "dp m_n",
11365 pipe_config->lane_count, &pipe_config->dp_m_n);
11366 if (pipe_config->has_drrs)
11367 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11368 pipe_config->lane_count,
11369 &pipe_config->dp_m2_n2);
11370 }
11371
11372 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11373 pipe_config->has_audio, pipe_config->has_infoframe);
11374
11375 DRM_DEBUG_KMS("requested mode:\n");
11376 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11377 DRM_DEBUG_KMS("adjusted mode:\n");
11378 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11379 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11380 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11381 pipe_config->port_clock,
11382 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11383 pipe_config->pixel_rate);
11384
11385 if (INTEL_GEN(dev_priv) >= 9)
11386 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11387 crtc->num_scalers,
11388 pipe_config->scaler_state.scaler_users,
11389 pipe_config->scaler_state.scaler_id);
11390
11391 if (HAS_GMCH_DISPLAY(dev_priv))
11392 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11393 pipe_config->gmch_pfit.control,
11394 pipe_config->gmch_pfit.pgm_ratios,
11395 pipe_config->gmch_pfit.lvds_border_bits);
11396 else
11397 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11398 pipe_config->pch_pfit.pos,
11399 pipe_config->pch_pfit.size,
11400 enableddisabled(pipe_config->pch_pfit.enabled));
11401
11402 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11403 pipe_config->ips_enabled, pipe_config->double_wide);
11404
11405 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11406
11407 DRM_DEBUG_KMS("planes on this crtc\n");
11408 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11409 struct drm_format_name_buf format_name;
11410 intel_plane = to_intel_plane(plane);
11411 if (intel_plane->pipe != crtc->pipe)
11412 continue;
11413
11414 state = to_intel_plane_state(plane->state);
11415 fb = state->base.fb;
11416 if (!fb) {
11417 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11418 plane->base.id, plane->name, state->scaler_id);
11419 continue;
11420 }
11421
11422 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11423 plane->base.id, plane->name,
11424 fb->base.id, fb->width, fb->height,
11425 drm_get_format_name(fb->format->format, &format_name));
11426 if (INTEL_GEN(dev_priv) >= 9)
11427 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11428 state->scaler_id,
11429 state->base.src.x1 >> 16,
11430 state->base.src.y1 >> 16,
11431 drm_rect_width(&state->base.src) >> 16,
11432 drm_rect_height(&state->base.src) >> 16,
11433 state->base.dst.x1, state->base.dst.y1,
11434 drm_rect_width(&state->base.dst),
11435 drm_rect_height(&state->base.dst));
11436 }
11437 }
11438
11439 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11440 {
11441 struct drm_device *dev = state->dev;
11442 struct drm_connector *connector;
11443 struct drm_connector_list_iter conn_iter;
11444 unsigned int used_ports = 0;
11445 unsigned int used_mst_ports = 0;
11446
11447 /*
11448 * Walk the connector list instead of the encoder
11449 * list to detect the problem on ddi platforms
11450 * where there's just one encoder per digital port.
11451 */
11452 drm_connector_list_iter_begin(dev, &conn_iter);
11453 drm_for_each_connector_iter(connector, &conn_iter) {
11454 struct drm_connector_state *connector_state;
11455 struct intel_encoder *encoder;
11456
11457 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11458 if (!connector_state)
11459 connector_state = connector->state;
11460
11461 if (!connector_state->best_encoder)
11462 continue;
11463
11464 encoder = to_intel_encoder(connector_state->best_encoder);
11465
11466 WARN_ON(!connector_state->crtc);
11467
11468 switch (encoder->type) {
11469 unsigned int port_mask;
11470 case INTEL_OUTPUT_UNKNOWN:
11471 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11472 break;
11473 case INTEL_OUTPUT_DP:
11474 case INTEL_OUTPUT_HDMI:
11475 case INTEL_OUTPUT_EDP:
11476 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11477
11478 /* the same port mustn't appear more than once */
11479 if (used_ports & port_mask)
11480 return false;
11481
11482 used_ports |= port_mask;
11483 break;
11484 case INTEL_OUTPUT_DP_MST:
11485 used_mst_ports |=
11486 1 << enc_to_mst(&encoder->base)->primary->port;
11487 break;
11488 default:
11489 break;
11490 }
11491 }
11492 drm_connector_list_iter_end(&conn_iter);
11493
11494 /* can't mix MST and SST/HDMI on the same port */
11495 if (used_ports & used_mst_ports)
11496 return false;
11497
11498 return true;
11499 }
11500
11501 static void
11502 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11503 {
11504 struct drm_i915_private *dev_priv =
11505 to_i915(crtc_state->base.crtc->dev);
11506 struct intel_crtc_scaler_state scaler_state;
11507 struct intel_dpll_hw_state dpll_hw_state;
11508 struct intel_shared_dpll *shared_dpll;
11509 struct intel_crtc_wm_state wm_state;
11510 bool force_thru;
11511
11512 /* FIXME: before the switch to atomic started, a new pipe_config was
11513 * kzalloc'd. Code that depends on any field being zero should be
11514 * fixed, so that the crtc_state can be safely duplicated. For now,
11515 * only fields that are know to not cause problems are preserved. */
11516
11517 scaler_state = crtc_state->scaler_state;
11518 shared_dpll = crtc_state->shared_dpll;
11519 dpll_hw_state = crtc_state->dpll_hw_state;
11520 force_thru = crtc_state->pch_pfit.force_thru;
11521 if (IS_G4X(dev_priv) ||
11522 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11523 wm_state = crtc_state->wm;
11524
11525 /* Keep base drm_crtc_state intact, only clear our extended struct */
11526 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11527 memset(&crtc_state->base + 1, 0,
11528 sizeof(*crtc_state) - sizeof(crtc_state->base));
11529
11530 crtc_state->scaler_state = scaler_state;
11531 crtc_state->shared_dpll = shared_dpll;
11532 crtc_state->dpll_hw_state = dpll_hw_state;
11533 crtc_state->pch_pfit.force_thru = force_thru;
11534 if (IS_G4X(dev_priv) ||
11535 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11536 crtc_state->wm = wm_state;
11537 }
11538
11539 static int
11540 intel_modeset_pipe_config(struct drm_crtc *crtc,
11541 struct intel_crtc_state *pipe_config)
11542 {
11543 struct drm_atomic_state *state = pipe_config->base.state;
11544 struct intel_encoder *encoder;
11545 struct drm_connector *connector;
11546 struct drm_connector_state *connector_state;
11547 int base_bpp, ret = -EINVAL;
11548 int i;
11549 bool retry = true;
11550
11551 clear_intel_crtc_state(pipe_config);
11552
11553 pipe_config->cpu_transcoder =
11554 (enum transcoder) to_intel_crtc(crtc)->pipe;
11555
11556 /*
11557 * Sanitize sync polarity flags based on requested ones. If neither
11558 * positive or negative polarity is requested, treat this as meaning
11559 * negative polarity.
11560 */
11561 if (!(pipe_config->base.adjusted_mode.flags &
11562 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11563 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11564
11565 if (!(pipe_config->base.adjusted_mode.flags &
11566 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11567 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11568
11569 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11570 pipe_config);
11571 if (base_bpp < 0)
11572 goto fail;
11573
11574 /*
11575 * Determine the real pipe dimensions. Note that stereo modes can
11576 * increase the actual pipe size due to the frame doubling and
11577 * insertion of additional space for blanks between the frame. This
11578 * is stored in the crtc timings. We use the requested mode to do this
11579 * computation to clearly distinguish it from the adjusted mode, which
11580 * can be changed by the connectors in the below retry loop.
11581 */
11582 drm_mode_get_hv_timing(&pipe_config->base.mode,
11583 &pipe_config->pipe_src_w,
11584 &pipe_config->pipe_src_h);
11585
11586 for_each_new_connector_in_state(state, connector, connector_state, i) {
11587 if (connector_state->crtc != crtc)
11588 continue;
11589
11590 encoder = to_intel_encoder(connector_state->best_encoder);
11591
11592 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11593 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11594 goto fail;
11595 }
11596
11597 /*
11598 * Determine output_types before calling the .compute_config()
11599 * hooks so that the hooks can use this information safely.
11600 */
11601 pipe_config->output_types |= 1 << encoder->type;
11602 }
11603
11604 encoder_retry:
11605 /* Ensure the port clock defaults are reset when retrying. */
11606 pipe_config->port_clock = 0;
11607 pipe_config->pixel_multiplier = 1;
11608
11609 /* Fill in default crtc timings, allow encoders to overwrite them. */
11610 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11611 CRTC_STEREO_DOUBLE);
11612
11613 /* Pass our mode to the connectors and the CRTC to give them a chance to
11614 * adjust it according to limitations or connector properties, and also
11615 * a chance to reject the mode entirely.
11616 */
11617 for_each_new_connector_in_state(state, connector, connector_state, i) {
11618 if (connector_state->crtc != crtc)
11619 continue;
11620
11621 encoder = to_intel_encoder(connector_state->best_encoder);
11622
11623 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11624 DRM_DEBUG_KMS("Encoder config failure\n");
11625 goto fail;
11626 }
11627 }
11628
11629 /* Set default port clock if not overwritten by the encoder. Needs to be
11630 * done afterwards in case the encoder adjusts the mode. */
11631 if (!pipe_config->port_clock)
11632 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11633 * pipe_config->pixel_multiplier;
11634
11635 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11636 if (ret < 0) {
11637 DRM_DEBUG_KMS("CRTC fixup failed\n");
11638 goto fail;
11639 }
11640
11641 if (ret == RETRY) {
11642 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11643 ret = -EINVAL;
11644 goto fail;
11645 }
11646
11647 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11648 retry = false;
11649 goto encoder_retry;
11650 }
11651
11652 /* Dithering seems to not pass-through bits correctly when it should, so
11653 * only enable it on 6bpc panels and when its not a compliance
11654 * test requesting 6bpc video pattern.
11655 */
11656 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11657 !pipe_config->dither_force_disable;
11658 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11659 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11660
11661 fail:
11662 return ret;
11663 }
11664
11665 static void
11666 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11667 {
11668 struct drm_crtc *crtc;
11669 struct drm_crtc_state *new_crtc_state;
11670 int i;
11671
11672 /* Double check state. */
11673 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11674 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11675
11676 /*
11677 * Update legacy state to satisfy fbc code. This can
11678 * be removed when fbc uses the atomic state.
11679 */
11680 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11681 struct drm_plane_state *plane_state = crtc->primary->state;
11682
11683 crtc->primary->fb = plane_state->fb;
11684 crtc->x = plane_state->src_x >> 16;
11685 crtc->y = plane_state->src_y >> 16;
11686 }
11687 }
11688 }
11689
11690 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11691 {
11692 int diff;
11693
11694 if (clock1 == clock2)
11695 return true;
11696
11697 if (!clock1 || !clock2)
11698 return false;
11699
11700 diff = abs(clock1 - clock2);
11701
11702 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11703 return true;
11704
11705 return false;
11706 }
11707
11708 static bool
11709 intel_compare_m_n(unsigned int m, unsigned int n,
11710 unsigned int m2, unsigned int n2,
11711 bool exact)
11712 {
11713 if (m == m2 && n == n2)
11714 return true;
11715
11716 if (exact || !m || !n || !m2 || !n2)
11717 return false;
11718
11719 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11720
11721 if (n > n2) {
11722 while (n > n2) {
11723 m2 <<= 1;
11724 n2 <<= 1;
11725 }
11726 } else if (n < n2) {
11727 while (n < n2) {
11728 m <<= 1;
11729 n <<= 1;
11730 }
11731 }
11732
11733 if (n != n2)
11734 return false;
11735
11736 return intel_fuzzy_clock_check(m, m2);
11737 }
11738
11739 static bool
11740 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11741 struct intel_link_m_n *m2_n2,
11742 bool adjust)
11743 {
11744 if (m_n->tu == m2_n2->tu &&
11745 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11746 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11747 intel_compare_m_n(m_n->link_m, m_n->link_n,
11748 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11749 if (adjust)
11750 *m2_n2 = *m_n;
11751
11752 return true;
11753 }
11754
11755 return false;
11756 }
11757
11758 static void __printf(3, 4)
11759 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11760 {
11761 char *level;
11762 unsigned int category;
11763 struct va_format vaf;
11764 va_list args;
11765
11766 if (adjust) {
11767 level = KERN_DEBUG;
11768 category = DRM_UT_KMS;
11769 } else {
11770 level = KERN_ERR;
11771 category = DRM_UT_NONE;
11772 }
11773
11774 va_start(args, format);
11775 vaf.fmt = format;
11776 vaf.va = &args;
11777
11778 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11779
11780 va_end(args);
11781 }
11782
11783 static bool
11784 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11785 struct intel_crtc_state *current_config,
11786 struct intel_crtc_state *pipe_config,
11787 bool adjust)
11788 {
11789 bool ret = true;
11790
11791 #define PIPE_CONF_CHECK_X(name) \
11792 if (current_config->name != pipe_config->name) { \
11793 pipe_config_err(adjust, __stringify(name), \
11794 "(expected 0x%08x, found 0x%08x)\n", \
11795 current_config->name, \
11796 pipe_config->name); \
11797 ret = false; \
11798 }
11799
11800 #define PIPE_CONF_CHECK_I(name) \
11801 if (current_config->name != pipe_config->name) { \
11802 pipe_config_err(adjust, __stringify(name), \
11803 "(expected %i, found %i)\n", \
11804 current_config->name, \
11805 pipe_config->name); \
11806 ret = false; \
11807 }
11808
11809 #define PIPE_CONF_CHECK_P(name) \
11810 if (current_config->name != pipe_config->name) { \
11811 pipe_config_err(adjust, __stringify(name), \
11812 "(expected %p, found %p)\n", \
11813 current_config->name, \
11814 pipe_config->name); \
11815 ret = false; \
11816 }
11817
11818 #define PIPE_CONF_CHECK_M_N(name) \
11819 if (!intel_compare_link_m_n(&current_config->name, \
11820 &pipe_config->name,\
11821 adjust)) { \
11822 pipe_config_err(adjust, __stringify(name), \
11823 "(expected tu %i gmch %i/%i link %i/%i, " \
11824 "found tu %i, gmch %i/%i link %i/%i)\n", \
11825 current_config->name.tu, \
11826 current_config->name.gmch_m, \
11827 current_config->name.gmch_n, \
11828 current_config->name.link_m, \
11829 current_config->name.link_n, \
11830 pipe_config->name.tu, \
11831 pipe_config->name.gmch_m, \
11832 pipe_config->name.gmch_n, \
11833 pipe_config->name.link_m, \
11834 pipe_config->name.link_n); \
11835 ret = false; \
11836 }
11837
11838 /* This is required for BDW+ where there is only one set of registers for
11839 * switching between high and low RR.
11840 * This macro can be used whenever a comparison has to be made between one
11841 * hw state and multiple sw state variables.
11842 */
11843 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11844 if (!intel_compare_link_m_n(&current_config->name, \
11845 &pipe_config->name, adjust) && \
11846 !intel_compare_link_m_n(&current_config->alt_name, \
11847 &pipe_config->name, adjust)) { \
11848 pipe_config_err(adjust, __stringify(name), \
11849 "(expected tu %i gmch %i/%i link %i/%i, " \
11850 "or tu %i gmch %i/%i link %i/%i, " \
11851 "found tu %i, gmch %i/%i link %i/%i)\n", \
11852 current_config->name.tu, \
11853 current_config->name.gmch_m, \
11854 current_config->name.gmch_n, \
11855 current_config->name.link_m, \
11856 current_config->name.link_n, \
11857 current_config->alt_name.tu, \
11858 current_config->alt_name.gmch_m, \
11859 current_config->alt_name.gmch_n, \
11860 current_config->alt_name.link_m, \
11861 current_config->alt_name.link_n, \
11862 pipe_config->name.tu, \
11863 pipe_config->name.gmch_m, \
11864 pipe_config->name.gmch_n, \
11865 pipe_config->name.link_m, \
11866 pipe_config->name.link_n); \
11867 ret = false; \
11868 }
11869
11870 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11871 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11872 pipe_config_err(adjust, __stringify(name), \
11873 "(%x) (expected %i, found %i)\n", \
11874 (mask), \
11875 current_config->name & (mask), \
11876 pipe_config->name & (mask)); \
11877 ret = false; \
11878 }
11879
11880 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11881 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11882 pipe_config_err(adjust, __stringify(name), \
11883 "(expected %i, found %i)\n", \
11884 current_config->name, \
11885 pipe_config->name); \
11886 ret = false; \
11887 }
11888
11889 #define PIPE_CONF_QUIRK(quirk) \
11890 ((current_config->quirks | pipe_config->quirks) & (quirk))
11891
11892 PIPE_CONF_CHECK_I(cpu_transcoder);
11893
11894 PIPE_CONF_CHECK_I(has_pch_encoder);
11895 PIPE_CONF_CHECK_I(fdi_lanes);
11896 PIPE_CONF_CHECK_M_N(fdi_m_n);
11897
11898 PIPE_CONF_CHECK_I(lane_count);
11899 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11900
11901 if (INTEL_GEN(dev_priv) < 8) {
11902 PIPE_CONF_CHECK_M_N(dp_m_n);
11903
11904 if (current_config->has_drrs)
11905 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11906 } else
11907 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11908
11909 PIPE_CONF_CHECK_X(output_types);
11910
11911 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11912 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11913 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11914 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11915 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11916 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11917
11918 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11919 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11920 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11921 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11922 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11923 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11924
11925 PIPE_CONF_CHECK_I(pixel_multiplier);
11926 PIPE_CONF_CHECK_I(has_hdmi_sink);
11927 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11928 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11929 PIPE_CONF_CHECK_I(limited_color_range);
11930
11931 PIPE_CONF_CHECK_I(hdmi_scrambling);
11932 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11933 PIPE_CONF_CHECK_I(has_infoframe);
11934
11935 PIPE_CONF_CHECK_I(has_audio);
11936
11937 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11938 DRM_MODE_FLAG_INTERLACE);
11939
11940 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11941 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11942 DRM_MODE_FLAG_PHSYNC);
11943 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11944 DRM_MODE_FLAG_NHSYNC);
11945 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11946 DRM_MODE_FLAG_PVSYNC);
11947 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11948 DRM_MODE_FLAG_NVSYNC);
11949 }
11950
11951 PIPE_CONF_CHECK_X(gmch_pfit.control);
11952 /* pfit ratios are autocomputed by the hw on gen4+ */
11953 if (INTEL_GEN(dev_priv) < 4)
11954 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11955 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11956
11957 if (!adjust) {
11958 PIPE_CONF_CHECK_I(pipe_src_w);
11959 PIPE_CONF_CHECK_I(pipe_src_h);
11960
11961 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11962 if (current_config->pch_pfit.enabled) {
11963 PIPE_CONF_CHECK_X(pch_pfit.pos);
11964 PIPE_CONF_CHECK_X(pch_pfit.size);
11965 }
11966
11967 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11968 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11969 }
11970
11971 /* BDW+ don't expose a synchronous way to read the state */
11972 if (IS_HASWELL(dev_priv))
11973 PIPE_CONF_CHECK_I(ips_enabled);
11974
11975 PIPE_CONF_CHECK_I(double_wide);
11976
11977 PIPE_CONF_CHECK_P(shared_dpll);
11978 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11979 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11980 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11981 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11982 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11983 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11984 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11985 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11986 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11987
11988 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11989 PIPE_CONF_CHECK_X(dsi_pll.div);
11990
11991 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11992 PIPE_CONF_CHECK_I(pipe_bpp);
11993
11994 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11995 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11996
11997 #undef PIPE_CONF_CHECK_X
11998 #undef PIPE_CONF_CHECK_I
11999 #undef PIPE_CONF_CHECK_P
12000 #undef PIPE_CONF_CHECK_FLAGS
12001 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12002 #undef PIPE_CONF_QUIRK
12003
12004 return ret;
12005 }
12006
12007 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12008 const struct intel_crtc_state *pipe_config)
12009 {
12010 if (pipe_config->has_pch_encoder) {
12011 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12012 &pipe_config->fdi_m_n);
12013 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12014
12015 /*
12016 * FDI already provided one idea for the dotclock.
12017 * Yell if the encoder disagrees.
12018 */
12019 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12020 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12021 fdi_dotclock, dotclock);
12022 }
12023 }
12024
12025 static void verify_wm_state(struct drm_crtc *crtc,
12026 struct drm_crtc_state *new_state)
12027 {
12028 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
12029 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12030 struct skl_pipe_wm hw_wm, *sw_wm;
12031 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12032 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
12033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12034 const enum pipe pipe = intel_crtc->pipe;
12035 int plane, level, max_level = ilk_wm_max_level(dev_priv);
12036
12037 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
12038 return;
12039
12040 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
12041 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
12042
12043 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12044 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12045
12046 /* planes */
12047 for_each_universal_plane(dev_priv, pipe, plane) {
12048 hw_plane_wm = &hw_wm.planes[plane];
12049 sw_plane_wm = &sw_wm->planes[plane];
12050
12051 /* Watermarks */
12052 for (level = 0; level <= max_level; level++) {
12053 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12054 &sw_plane_wm->wm[level]))
12055 continue;
12056
12057 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12058 pipe_name(pipe), plane + 1, level,
12059 sw_plane_wm->wm[level].plane_en,
12060 sw_plane_wm->wm[level].plane_res_b,
12061 sw_plane_wm->wm[level].plane_res_l,
12062 hw_plane_wm->wm[level].plane_en,
12063 hw_plane_wm->wm[level].plane_res_b,
12064 hw_plane_wm->wm[level].plane_res_l);
12065 }
12066
12067 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12068 &sw_plane_wm->trans_wm)) {
12069 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12070 pipe_name(pipe), plane + 1,
12071 sw_plane_wm->trans_wm.plane_en,
12072 sw_plane_wm->trans_wm.plane_res_b,
12073 sw_plane_wm->trans_wm.plane_res_l,
12074 hw_plane_wm->trans_wm.plane_en,
12075 hw_plane_wm->trans_wm.plane_res_b,
12076 hw_plane_wm->trans_wm.plane_res_l);
12077 }
12078
12079 /* DDB */
12080 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
12081 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
12082
12083 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12084 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12085 pipe_name(pipe), plane + 1,
12086 sw_ddb_entry->start, sw_ddb_entry->end,
12087 hw_ddb_entry->start, hw_ddb_entry->end);
12088 }
12089 }
12090
12091 /*
12092 * cursor
12093 * If the cursor plane isn't active, we may not have updated it's ddb
12094 * allocation. In that case since the ddb allocation will be updated
12095 * once the plane becomes visible, we can skip this check
12096 */
12097 if (1) {
12098 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
12099 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12100
12101 /* Watermarks */
12102 for (level = 0; level <= max_level; level++) {
12103 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12104 &sw_plane_wm->wm[level]))
12105 continue;
12106
12107 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12108 pipe_name(pipe), level,
12109 sw_plane_wm->wm[level].plane_en,
12110 sw_plane_wm->wm[level].plane_res_b,
12111 sw_plane_wm->wm[level].plane_res_l,
12112 hw_plane_wm->wm[level].plane_en,
12113 hw_plane_wm->wm[level].plane_res_b,
12114 hw_plane_wm->wm[level].plane_res_l);
12115 }
12116
12117 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12118 &sw_plane_wm->trans_wm)) {
12119 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12120 pipe_name(pipe),
12121 sw_plane_wm->trans_wm.plane_en,
12122 sw_plane_wm->trans_wm.plane_res_b,
12123 sw_plane_wm->trans_wm.plane_res_l,
12124 hw_plane_wm->trans_wm.plane_en,
12125 hw_plane_wm->trans_wm.plane_res_b,
12126 hw_plane_wm->trans_wm.plane_res_l);
12127 }
12128
12129 /* DDB */
12130 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12131 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12132
12133 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12134 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
12135 pipe_name(pipe),
12136 sw_ddb_entry->start, sw_ddb_entry->end,
12137 hw_ddb_entry->start, hw_ddb_entry->end);
12138 }
12139 }
12140 }
12141
12142 static void
12143 verify_connector_state(struct drm_device *dev,
12144 struct drm_atomic_state *state,
12145 struct drm_crtc *crtc)
12146 {
12147 struct drm_connector *connector;
12148 struct drm_connector_state *new_conn_state;
12149 int i;
12150
12151 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
12152 struct drm_encoder *encoder = connector->encoder;
12153 struct drm_crtc_state *crtc_state = NULL;
12154
12155 if (new_conn_state->crtc != crtc)
12156 continue;
12157
12158 if (crtc)
12159 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
12160
12161 intel_connector_verify_state(crtc_state, new_conn_state);
12162
12163 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
12164 "connector's atomic encoder doesn't match legacy encoder\n");
12165 }
12166 }
12167
12168 static void
12169 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
12170 {
12171 struct intel_encoder *encoder;
12172 struct drm_connector *connector;
12173 struct drm_connector_state *old_conn_state, *new_conn_state;
12174 int i;
12175
12176 for_each_intel_encoder(dev, encoder) {
12177 bool enabled = false, found = false;
12178 enum pipe pipe;
12179
12180 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12181 encoder->base.base.id,
12182 encoder->base.name);
12183
12184 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
12185 new_conn_state, i) {
12186 if (old_conn_state->best_encoder == &encoder->base)
12187 found = true;
12188
12189 if (new_conn_state->best_encoder != &encoder->base)
12190 continue;
12191 found = enabled = true;
12192
12193 I915_STATE_WARN(new_conn_state->crtc !=
12194 encoder->base.crtc,
12195 "connector's crtc doesn't match encoder crtc\n");
12196 }
12197
12198 if (!found)
12199 continue;
12200
12201 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12202 "encoder's enabled state mismatch "
12203 "(expected %i, found %i)\n",
12204 !!encoder->base.crtc, enabled);
12205
12206 if (!encoder->base.crtc) {
12207 bool active;
12208
12209 active = encoder->get_hw_state(encoder, &pipe);
12210 I915_STATE_WARN(active,
12211 "encoder detached but still enabled on pipe %c.\n",
12212 pipe_name(pipe));
12213 }
12214 }
12215 }
12216
12217 static void
12218 verify_crtc_state(struct drm_crtc *crtc,
12219 struct drm_crtc_state *old_crtc_state,
12220 struct drm_crtc_state *new_crtc_state)
12221 {
12222 struct drm_device *dev = crtc->dev;
12223 struct drm_i915_private *dev_priv = to_i915(dev);
12224 struct intel_encoder *encoder;
12225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12226 struct intel_crtc_state *pipe_config, *sw_config;
12227 struct drm_atomic_state *old_state;
12228 bool active;
12229
12230 old_state = old_crtc_state->state;
12231 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12232 pipe_config = to_intel_crtc_state(old_crtc_state);
12233 memset(pipe_config, 0, sizeof(*pipe_config));
12234 pipe_config->base.crtc = crtc;
12235 pipe_config->base.state = old_state;
12236
12237 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12238
12239 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12240
12241 /* we keep both pipes enabled on 830 */
12242 if (IS_I830(dev_priv))
12243 active = new_crtc_state->active;
12244
12245 I915_STATE_WARN(new_crtc_state->active != active,
12246 "crtc active state doesn't match with hw state "
12247 "(expected %i, found %i)\n", new_crtc_state->active, active);
12248
12249 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12250 "transitional active state does not match atomic hw state "
12251 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12252
12253 for_each_encoder_on_crtc(dev, crtc, encoder) {
12254 enum pipe pipe;
12255
12256 active = encoder->get_hw_state(encoder, &pipe);
12257 I915_STATE_WARN(active != new_crtc_state->active,
12258 "[ENCODER:%i] active %i with crtc active %i\n",
12259 encoder->base.base.id, active, new_crtc_state->active);
12260
12261 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12262 "Encoder connected to wrong pipe %c\n",
12263 pipe_name(pipe));
12264
12265 if (active) {
12266 pipe_config->output_types |= 1 << encoder->type;
12267 encoder->get_config(encoder, pipe_config);
12268 }
12269 }
12270
12271 intel_crtc_compute_pixel_rate(pipe_config);
12272
12273 if (!new_crtc_state->active)
12274 return;
12275
12276 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12277
12278 sw_config = to_intel_crtc_state(new_crtc_state);
12279 if (!intel_pipe_config_compare(dev_priv, sw_config,
12280 pipe_config, false)) {
12281 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12282 intel_dump_pipe_config(intel_crtc, pipe_config,
12283 "[hw state]");
12284 intel_dump_pipe_config(intel_crtc, sw_config,
12285 "[sw state]");
12286 }
12287 }
12288
12289 static void
12290 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12291 struct intel_shared_dpll *pll,
12292 struct drm_crtc *crtc,
12293 struct drm_crtc_state *new_state)
12294 {
12295 struct intel_dpll_hw_state dpll_hw_state;
12296 unsigned crtc_mask;
12297 bool active;
12298
12299 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12300
12301 DRM_DEBUG_KMS("%s\n", pll->name);
12302
12303 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12304
12305 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12306 I915_STATE_WARN(!pll->on && pll->active_mask,
12307 "pll in active use but not on in sw tracking\n");
12308 I915_STATE_WARN(pll->on && !pll->active_mask,
12309 "pll is on but not used by any active crtc\n");
12310 I915_STATE_WARN(pll->on != active,
12311 "pll on state mismatch (expected %i, found %i)\n",
12312 pll->on, active);
12313 }
12314
12315 if (!crtc) {
12316 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12317 "more active pll users than references: %x vs %x\n",
12318 pll->active_mask, pll->state.crtc_mask);
12319
12320 return;
12321 }
12322
12323 crtc_mask = 1 << drm_crtc_index(crtc);
12324
12325 if (new_state->active)
12326 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12327 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12328 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12329 else
12330 I915_STATE_WARN(pll->active_mask & crtc_mask,
12331 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12332 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12333
12334 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12335 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12336 crtc_mask, pll->state.crtc_mask);
12337
12338 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12339 &dpll_hw_state,
12340 sizeof(dpll_hw_state)),
12341 "pll hw state mismatch\n");
12342 }
12343
12344 static void
12345 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12346 struct drm_crtc_state *old_crtc_state,
12347 struct drm_crtc_state *new_crtc_state)
12348 {
12349 struct drm_i915_private *dev_priv = to_i915(dev);
12350 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12351 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12352
12353 if (new_state->shared_dpll)
12354 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12355
12356 if (old_state->shared_dpll &&
12357 old_state->shared_dpll != new_state->shared_dpll) {
12358 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12359 struct intel_shared_dpll *pll = old_state->shared_dpll;
12360
12361 I915_STATE_WARN(pll->active_mask & crtc_mask,
12362 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12363 pipe_name(drm_crtc_index(crtc)));
12364 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12365 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12366 pipe_name(drm_crtc_index(crtc)));
12367 }
12368 }
12369
12370 static void
12371 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12372 struct drm_atomic_state *state,
12373 struct drm_crtc_state *old_state,
12374 struct drm_crtc_state *new_state)
12375 {
12376 if (!needs_modeset(new_state) &&
12377 !to_intel_crtc_state(new_state)->update_pipe)
12378 return;
12379
12380 verify_wm_state(crtc, new_state);
12381 verify_connector_state(crtc->dev, state, crtc);
12382 verify_crtc_state(crtc, old_state, new_state);
12383 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12384 }
12385
12386 static void
12387 verify_disabled_dpll_state(struct drm_device *dev)
12388 {
12389 struct drm_i915_private *dev_priv = to_i915(dev);
12390 int i;
12391
12392 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12393 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12394 }
12395
12396 static void
12397 intel_modeset_verify_disabled(struct drm_device *dev,
12398 struct drm_atomic_state *state)
12399 {
12400 verify_encoder_state(dev, state);
12401 verify_connector_state(dev, state, NULL);
12402 verify_disabled_dpll_state(dev);
12403 }
12404
12405 static void update_scanline_offset(struct intel_crtc *crtc)
12406 {
12407 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12408
12409 /*
12410 * The scanline counter increments at the leading edge of hsync.
12411 *
12412 * On most platforms it starts counting from vtotal-1 on the
12413 * first active line. That means the scanline counter value is
12414 * always one less than what we would expect. Ie. just after
12415 * start of vblank, which also occurs at start of hsync (on the
12416 * last active line), the scanline counter will read vblank_start-1.
12417 *
12418 * On gen2 the scanline counter starts counting from 1 instead
12419 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12420 * to keep the value positive), instead of adding one.
12421 *
12422 * On HSW+ the behaviour of the scanline counter depends on the output
12423 * type. For DP ports it behaves like most other platforms, but on HDMI
12424 * there's an extra 1 line difference. So we need to add two instead of
12425 * one to the value.
12426 *
12427 * On VLV/CHV DSI the scanline counter would appear to increment
12428 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12429 * that means we can't tell whether we're in vblank or not while
12430 * we're on that particular line. We must still set scanline_offset
12431 * to 1 so that the vblank timestamps come out correct when we query
12432 * the scanline counter from within the vblank interrupt handler.
12433 * However if queried just before the start of vblank we'll get an
12434 * answer that's slightly in the future.
12435 */
12436 if (IS_GEN2(dev_priv)) {
12437 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12438 int vtotal;
12439
12440 vtotal = adjusted_mode->crtc_vtotal;
12441 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12442 vtotal /= 2;
12443
12444 crtc->scanline_offset = vtotal - 1;
12445 } else if (HAS_DDI(dev_priv) &&
12446 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12447 crtc->scanline_offset = 2;
12448 } else
12449 crtc->scanline_offset = 1;
12450 }
12451
12452 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12453 {
12454 struct drm_device *dev = state->dev;
12455 struct drm_i915_private *dev_priv = to_i915(dev);
12456 struct drm_crtc *crtc;
12457 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12458 int i;
12459
12460 if (!dev_priv->display.crtc_compute_clock)
12461 return;
12462
12463 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12465 struct intel_shared_dpll *old_dpll =
12466 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12467
12468 if (!needs_modeset(new_crtc_state))
12469 continue;
12470
12471 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12472
12473 if (!old_dpll)
12474 continue;
12475
12476 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12477 }
12478 }
12479
12480 /*
12481 * This implements the workaround described in the "notes" section of the mode
12482 * set sequence documentation. When going from no pipes or single pipe to
12483 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12484 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12485 */
12486 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12487 {
12488 struct drm_crtc_state *crtc_state;
12489 struct intel_crtc *intel_crtc;
12490 struct drm_crtc *crtc;
12491 struct intel_crtc_state *first_crtc_state = NULL;
12492 struct intel_crtc_state *other_crtc_state = NULL;
12493 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12494 int i;
12495
12496 /* look at all crtc's that are going to be enabled in during modeset */
12497 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12498 intel_crtc = to_intel_crtc(crtc);
12499
12500 if (!crtc_state->active || !needs_modeset(crtc_state))
12501 continue;
12502
12503 if (first_crtc_state) {
12504 other_crtc_state = to_intel_crtc_state(crtc_state);
12505 break;
12506 } else {
12507 first_crtc_state = to_intel_crtc_state(crtc_state);
12508 first_pipe = intel_crtc->pipe;
12509 }
12510 }
12511
12512 /* No workaround needed? */
12513 if (!first_crtc_state)
12514 return 0;
12515
12516 /* w/a possibly needed, check how many crtc's are already enabled. */
12517 for_each_intel_crtc(state->dev, intel_crtc) {
12518 struct intel_crtc_state *pipe_config;
12519
12520 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12521 if (IS_ERR(pipe_config))
12522 return PTR_ERR(pipe_config);
12523
12524 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12525
12526 if (!pipe_config->base.active ||
12527 needs_modeset(&pipe_config->base))
12528 continue;
12529
12530 /* 2 or more enabled crtcs means no need for w/a */
12531 if (enabled_pipe != INVALID_PIPE)
12532 return 0;
12533
12534 enabled_pipe = intel_crtc->pipe;
12535 }
12536
12537 if (enabled_pipe != INVALID_PIPE)
12538 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12539 else if (other_crtc_state)
12540 other_crtc_state->hsw_workaround_pipe = first_pipe;
12541
12542 return 0;
12543 }
12544
12545 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12546 {
12547 struct drm_crtc *crtc;
12548
12549 /* Add all pipes to the state */
12550 for_each_crtc(state->dev, crtc) {
12551 struct drm_crtc_state *crtc_state;
12552
12553 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12554 if (IS_ERR(crtc_state))
12555 return PTR_ERR(crtc_state);
12556 }
12557
12558 return 0;
12559 }
12560
12561 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12562 {
12563 struct drm_crtc *crtc;
12564
12565 /*
12566 * Add all pipes to the state, and force
12567 * a modeset on all the active ones.
12568 */
12569 for_each_crtc(state->dev, crtc) {
12570 struct drm_crtc_state *crtc_state;
12571 int ret;
12572
12573 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12574 if (IS_ERR(crtc_state))
12575 return PTR_ERR(crtc_state);
12576
12577 if (!crtc_state->active || needs_modeset(crtc_state))
12578 continue;
12579
12580 crtc_state->mode_changed = true;
12581
12582 ret = drm_atomic_add_affected_connectors(state, crtc);
12583 if (ret)
12584 return ret;
12585
12586 ret = drm_atomic_add_affected_planes(state, crtc);
12587 if (ret)
12588 return ret;
12589 }
12590
12591 return 0;
12592 }
12593
12594 static int intel_modeset_checks(struct drm_atomic_state *state)
12595 {
12596 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12597 struct drm_i915_private *dev_priv = to_i915(state->dev);
12598 struct drm_crtc *crtc;
12599 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12600 int ret = 0, i;
12601
12602 if (!check_digital_port_conflicts(state)) {
12603 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12604 return -EINVAL;
12605 }
12606
12607 intel_state->modeset = true;
12608 intel_state->active_crtcs = dev_priv->active_crtcs;
12609 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12610 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12611
12612 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12613 if (new_crtc_state->active)
12614 intel_state->active_crtcs |= 1 << i;
12615 else
12616 intel_state->active_crtcs &= ~(1 << i);
12617
12618 if (old_crtc_state->active != new_crtc_state->active)
12619 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12620 }
12621
12622 /*
12623 * See if the config requires any additional preparation, e.g.
12624 * to adjust global state with pipes off. We need to do this
12625 * here so we can get the modeset_pipe updated config for the new
12626 * mode set on this crtc. For other crtcs we need to use the
12627 * adjusted_mode bits in the crtc directly.
12628 */
12629 if (dev_priv->display.modeset_calc_cdclk) {
12630 ret = dev_priv->display.modeset_calc_cdclk(state);
12631 if (ret < 0)
12632 return ret;
12633
12634 /*
12635 * Writes to dev_priv->cdclk.logical must protected by
12636 * holding all the crtc locks, even if we don't end up
12637 * touching the hardware
12638 */
12639 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12640 &intel_state->cdclk.logical)) {
12641 ret = intel_lock_all_pipes(state);
12642 if (ret < 0)
12643 return ret;
12644 }
12645
12646 /* All pipes must be switched off while we change the cdclk. */
12647 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12648 &intel_state->cdclk.actual)) {
12649 ret = intel_modeset_all_pipes(state);
12650 if (ret < 0)
12651 return ret;
12652 }
12653
12654 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12655 intel_state->cdclk.logical.cdclk,
12656 intel_state->cdclk.actual.cdclk);
12657 } else {
12658 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12659 }
12660
12661 intel_modeset_clear_plls(state);
12662
12663 if (IS_HASWELL(dev_priv))
12664 return haswell_mode_set_planes_workaround(state);
12665
12666 return 0;
12667 }
12668
12669 /*
12670 * Handle calculation of various watermark data at the end of the atomic check
12671 * phase. The code here should be run after the per-crtc and per-plane 'check'
12672 * handlers to ensure that all derived state has been updated.
12673 */
12674 static int calc_watermark_data(struct drm_atomic_state *state)
12675 {
12676 struct drm_device *dev = state->dev;
12677 struct drm_i915_private *dev_priv = to_i915(dev);
12678
12679 /* Is there platform-specific watermark information to calculate? */
12680 if (dev_priv->display.compute_global_watermarks)
12681 return dev_priv->display.compute_global_watermarks(state);
12682
12683 return 0;
12684 }
12685
12686 /**
12687 * intel_atomic_check - validate state object
12688 * @dev: drm device
12689 * @state: state to validate
12690 */
12691 static int intel_atomic_check(struct drm_device *dev,
12692 struct drm_atomic_state *state)
12693 {
12694 struct drm_i915_private *dev_priv = to_i915(dev);
12695 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12696 struct drm_crtc *crtc;
12697 struct drm_crtc_state *old_crtc_state, *crtc_state;
12698 int ret, i;
12699 bool any_ms = false;
12700
12701 ret = drm_atomic_helper_check_modeset(dev, state);
12702 if (ret)
12703 return ret;
12704
12705 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12706 struct intel_crtc_state *pipe_config =
12707 to_intel_crtc_state(crtc_state);
12708
12709 /* Catch I915_MODE_FLAG_INHERITED */
12710 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12711 crtc_state->mode_changed = true;
12712
12713 if (!needs_modeset(crtc_state))
12714 continue;
12715
12716 if (!crtc_state->enable) {
12717 any_ms = true;
12718 continue;
12719 }
12720
12721 /* FIXME: For only active_changed we shouldn't need to do any
12722 * state recomputation at all. */
12723
12724 ret = drm_atomic_add_affected_connectors(state, crtc);
12725 if (ret)
12726 return ret;
12727
12728 ret = intel_modeset_pipe_config(crtc, pipe_config);
12729 if (ret) {
12730 intel_dump_pipe_config(to_intel_crtc(crtc),
12731 pipe_config, "[failed]");
12732 return ret;
12733 }
12734
12735 if (i915.fastboot &&
12736 intel_pipe_config_compare(dev_priv,
12737 to_intel_crtc_state(old_crtc_state),
12738 pipe_config, true)) {
12739 crtc_state->mode_changed = false;
12740 pipe_config->update_pipe = true;
12741 }
12742
12743 if (needs_modeset(crtc_state))
12744 any_ms = true;
12745
12746 ret = drm_atomic_add_affected_planes(state, crtc);
12747 if (ret)
12748 return ret;
12749
12750 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12751 needs_modeset(crtc_state) ?
12752 "[modeset]" : "[fastset]");
12753 }
12754
12755 if (any_ms) {
12756 ret = intel_modeset_checks(state);
12757
12758 if (ret)
12759 return ret;
12760 } else {
12761 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12762 }
12763
12764 ret = drm_atomic_helper_check_planes(dev, state);
12765 if (ret)
12766 return ret;
12767
12768 intel_fbc_choose_crtc(dev_priv, state);
12769 return calc_watermark_data(state);
12770 }
12771
12772 static int intel_atomic_prepare_commit(struct drm_device *dev,
12773 struct drm_atomic_state *state)
12774 {
12775 struct drm_i915_private *dev_priv = to_i915(dev);
12776 struct drm_crtc_state *crtc_state;
12777 struct drm_crtc *crtc;
12778 int i, ret;
12779
12780 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12781 if (state->legacy_cursor_update)
12782 continue;
12783
12784 ret = intel_crtc_wait_for_pending_flips(crtc);
12785 if (ret)
12786 return ret;
12787
12788 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12789 flush_workqueue(dev_priv->wq);
12790 }
12791
12792 ret = mutex_lock_interruptible(&dev->struct_mutex);
12793 if (ret)
12794 return ret;
12795
12796 ret = drm_atomic_helper_prepare_planes(dev, state);
12797 mutex_unlock(&dev->struct_mutex);
12798
12799 return ret;
12800 }
12801
12802 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12803 {
12804 struct drm_device *dev = crtc->base.dev;
12805
12806 if (!dev->max_vblank_count)
12807 return drm_crtc_accurate_vblank_count(&crtc->base);
12808
12809 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12810 }
12811
12812 static void intel_update_crtc(struct drm_crtc *crtc,
12813 struct drm_atomic_state *state,
12814 struct drm_crtc_state *old_crtc_state,
12815 struct drm_crtc_state *new_crtc_state)
12816 {
12817 struct drm_device *dev = crtc->dev;
12818 struct drm_i915_private *dev_priv = to_i915(dev);
12819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12820 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12821 bool modeset = needs_modeset(new_crtc_state);
12822
12823 if (modeset) {
12824 update_scanline_offset(intel_crtc);
12825 dev_priv->display.crtc_enable(pipe_config, state);
12826 } else {
12827 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12828 pipe_config);
12829 }
12830
12831 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12832 intel_fbc_enable(
12833 intel_crtc, pipe_config,
12834 to_intel_plane_state(crtc->primary->state));
12835 }
12836
12837 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12838 }
12839
12840 static void intel_update_crtcs(struct drm_atomic_state *state)
12841 {
12842 struct drm_crtc *crtc;
12843 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12844 int i;
12845
12846 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12847 if (!new_crtc_state->active)
12848 continue;
12849
12850 intel_update_crtc(crtc, state, old_crtc_state,
12851 new_crtc_state);
12852 }
12853 }
12854
12855 static void skl_update_crtcs(struct drm_atomic_state *state)
12856 {
12857 struct drm_i915_private *dev_priv = to_i915(state->dev);
12858 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12859 struct drm_crtc *crtc;
12860 struct intel_crtc *intel_crtc;
12861 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12862 struct intel_crtc_state *cstate;
12863 unsigned int updated = 0;
12864 bool progress;
12865 enum pipe pipe;
12866 int i;
12867
12868 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12869
12870 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12871 /* ignore allocations for crtc's that have been turned off. */
12872 if (new_crtc_state->active)
12873 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12874
12875 /*
12876 * Whenever the number of active pipes changes, we need to make sure we
12877 * update the pipes in the right order so that their ddb allocations
12878 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12879 * cause pipe underruns and other bad stuff.
12880 */
12881 do {
12882 progress = false;
12883
12884 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12885 bool vbl_wait = false;
12886 unsigned int cmask = drm_crtc_mask(crtc);
12887
12888 intel_crtc = to_intel_crtc(crtc);
12889 cstate = to_intel_crtc_state(crtc->state);
12890 pipe = intel_crtc->pipe;
12891
12892 if (updated & cmask || !cstate->base.active)
12893 continue;
12894
12895 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12896 continue;
12897
12898 updated |= cmask;
12899 entries[i] = &cstate->wm.skl.ddb;
12900
12901 /*
12902 * If this is an already active pipe, it's DDB changed,
12903 * and this isn't the last pipe that needs updating
12904 * then we need to wait for a vblank to pass for the
12905 * new ddb allocation to take effect.
12906 */
12907 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12908 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12909 !new_crtc_state->active_changed &&
12910 intel_state->wm_results.dirty_pipes != updated)
12911 vbl_wait = true;
12912
12913 intel_update_crtc(crtc, state, old_crtc_state,
12914 new_crtc_state);
12915
12916 if (vbl_wait)
12917 intel_wait_for_vblank(dev_priv, pipe);
12918
12919 progress = true;
12920 }
12921 } while (progress);
12922 }
12923
12924 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12925 {
12926 struct intel_atomic_state *state, *next;
12927 struct llist_node *freed;
12928
12929 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12930 llist_for_each_entry_safe(state, next, freed, freed)
12931 drm_atomic_state_put(&state->base);
12932 }
12933
12934 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12935 {
12936 struct drm_i915_private *dev_priv =
12937 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12938
12939 intel_atomic_helper_free_state(dev_priv);
12940 }
12941
12942 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12943 {
12944 struct drm_device *dev = state->dev;
12945 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12946 struct drm_i915_private *dev_priv = to_i915(dev);
12947 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12948 struct drm_crtc *crtc;
12949 struct intel_crtc_state *intel_cstate;
12950 bool hw_check = intel_state->modeset;
12951 u64 put_domains[I915_MAX_PIPES] = {};
12952 int i;
12953
12954 drm_atomic_helper_wait_for_dependencies(state);
12955
12956 if (intel_state->modeset)
12957 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12958
12959 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12961
12962 if (needs_modeset(new_crtc_state) ||
12963 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12964 hw_check = true;
12965
12966 put_domains[to_intel_crtc(crtc)->pipe] =
12967 modeset_get_crtc_power_domains(crtc,
12968 to_intel_crtc_state(new_crtc_state));
12969 }
12970
12971 if (!needs_modeset(new_crtc_state))
12972 continue;
12973
12974 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12975 to_intel_crtc_state(new_crtc_state));
12976
12977 if (old_crtc_state->active) {
12978 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12979 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12980 intel_crtc->active = false;
12981 intel_fbc_disable(intel_crtc);
12982 intel_disable_shared_dpll(intel_crtc);
12983
12984 /*
12985 * Underruns don't always raise
12986 * interrupts, so check manually.
12987 */
12988 intel_check_cpu_fifo_underruns(dev_priv);
12989 intel_check_pch_fifo_underruns(dev_priv);
12990
12991 if (!crtc->state->active) {
12992 /*
12993 * Make sure we don't call initial_watermarks
12994 * for ILK-style watermark updates.
12995 *
12996 * No clue what this is supposed to achieve.
12997 */
12998 if (INTEL_GEN(dev_priv) >= 9)
12999 dev_priv->display.initial_watermarks(intel_state,
13000 to_intel_crtc_state(crtc->state));
13001 }
13002 }
13003 }
13004
13005 /* Only after disabling all output pipelines that will be changed can we
13006 * update the the output configuration. */
13007 intel_modeset_update_crtc_state(state);
13008
13009 if (intel_state->modeset) {
13010 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13011
13012 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
13013
13014 /*
13015 * SKL workaround: bspec recommends we disable the SAGV when we
13016 * have more then one pipe enabled
13017 */
13018 if (!intel_can_enable_sagv(state))
13019 intel_disable_sagv(dev_priv);
13020
13021 intel_modeset_verify_disabled(dev, state);
13022 }
13023
13024 /* Complete the events for pipes that have now been disabled */
13025 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13026 bool modeset = needs_modeset(new_crtc_state);
13027
13028 /* Complete events for now disable pipes here. */
13029 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
13030 spin_lock_irq(&dev->event_lock);
13031 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
13032 spin_unlock_irq(&dev->event_lock);
13033
13034 new_crtc_state->event = NULL;
13035 }
13036 }
13037
13038 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13039 dev_priv->display.update_crtcs(state);
13040
13041 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13042 * already, but still need the state for the delayed optimization. To
13043 * fix this:
13044 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13045 * - schedule that vblank worker _before_ calling hw_done
13046 * - at the start of commit_tail, cancel it _synchrously
13047 * - switch over to the vblank wait helper in the core after that since
13048 * we don't need out special handling any more.
13049 */
13050 drm_atomic_helper_wait_for_flip_done(dev, state);
13051
13052 /*
13053 * Now that the vblank has passed, we can go ahead and program the
13054 * optimal watermarks on platforms that need two-step watermark
13055 * programming.
13056 *
13057 * TODO: Move this (and other cleanup) to an async worker eventually.
13058 */
13059 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
13060 intel_cstate = to_intel_crtc_state(new_crtc_state);
13061
13062 if (dev_priv->display.optimize_watermarks)
13063 dev_priv->display.optimize_watermarks(intel_state,
13064 intel_cstate);
13065 }
13066
13067 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13068 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13069
13070 if (put_domains[i])
13071 modeset_put_power_domains(dev_priv, put_domains[i]);
13072
13073 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13074 }
13075
13076 if (intel_state->modeset && intel_can_enable_sagv(state))
13077 intel_enable_sagv(dev_priv);
13078
13079 drm_atomic_helper_commit_hw_done(state);
13080
13081 if (intel_state->modeset) {
13082 /* As one of the primary mmio accessors, KMS has a high
13083 * likelihood of triggering bugs in unclaimed access. After we
13084 * finish modesetting, see if an error has been flagged, and if
13085 * so enable debugging for the next modeset - and hope we catch
13086 * the culprit.
13087 */
13088 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13089 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13090 }
13091
13092 mutex_lock(&dev->struct_mutex);
13093 drm_atomic_helper_cleanup_planes(dev, state);
13094 mutex_unlock(&dev->struct_mutex);
13095
13096 drm_atomic_helper_commit_cleanup_done(state);
13097
13098 drm_atomic_state_put(state);
13099
13100 intel_atomic_helper_free_state(dev_priv);
13101 }
13102
13103 static void intel_atomic_commit_work(struct work_struct *work)
13104 {
13105 struct drm_atomic_state *state =
13106 container_of(work, struct drm_atomic_state, commit_work);
13107
13108 intel_atomic_commit_tail(state);
13109 }
13110
13111 static int __i915_sw_fence_call
13112 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13113 enum i915_sw_fence_notify notify)
13114 {
13115 struct intel_atomic_state *state =
13116 container_of(fence, struct intel_atomic_state, commit_ready);
13117
13118 switch (notify) {
13119 case FENCE_COMPLETE:
13120 if (state->base.commit_work.func)
13121 queue_work(system_unbound_wq, &state->base.commit_work);
13122 break;
13123
13124 case FENCE_FREE:
13125 {
13126 struct intel_atomic_helper *helper =
13127 &to_i915(state->base.dev)->atomic_helper;
13128
13129 if (llist_add(&state->freed, &helper->free_list))
13130 schedule_work(&helper->free_work);
13131 break;
13132 }
13133 }
13134
13135 return NOTIFY_DONE;
13136 }
13137
13138 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13139 {
13140 struct drm_plane_state *old_plane_state, *new_plane_state;
13141 struct drm_plane *plane;
13142 int i;
13143
13144 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13145 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13146 intel_fb_obj(new_plane_state->fb),
13147 to_intel_plane(plane)->frontbuffer_bit);
13148 }
13149
13150 /**
13151 * intel_atomic_commit - commit validated state object
13152 * @dev: DRM device
13153 * @state: the top-level driver state object
13154 * @nonblock: nonblocking commit
13155 *
13156 * This function commits a top-level state object that has been validated
13157 * with drm_atomic_helper_check().
13158 *
13159 * RETURNS
13160 * Zero for success or -errno.
13161 */
13162 static int intel_atomic_commit(struct drm_device *dev,
13163 struct drm_atomic_state *state,
13164 bool nonblock)
13165 {
13166 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13167 struct drm_i915_private *dev_priv = to_i915(dev);
13168 int ret = 0;
13169
13170 ret = drm_atomic_helper_setup_commit(state, nonblock);
13171 if (ret)
13172 return ret;
13173
13174 drm_atomic_state_get(state);
13175 i915_sw_fence_init(&intel_state->commit_ready,
13176 intel_atomic_commit_ready);
13177
13178 ret = intel_atomic_prepare_commit(dev, state);
13179 if (ret) {
13180 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13181 i915_sw_fence_commit(&intel_state->commit_ready);
13182 return ret;
13183 }
13184
13185 /*
13186 * The intel_legacy_cursor_update() fast path takes care
13187 * of avoiding the vblank waits for simple cursor
13188 * movement and flips. For cursor on/off and size changes,
13189 * we want to perform the vblank waits so that watermark
13190 * updates happen during the correct frames. Gen9+ have
13191 * double buffered watermarks and so shouldn't need this.
13192 *
13193 * Do this after drm_atomic_helper_setup_commit() and
13194 * intel_atomic_prepare_commit() because we still want
13195 * to skip the flip and fb cleanup waits. Although that
13196 * does risk yanking the mapping from under the display
13197 * engine.
13198 *
13199 * FIXME doing watermarks and fb cleanup from a vblank worker
13200 * (assuming we had any) would solve these problems.
13201 */
13202 if (INTEL_GEN(dev_priv) < 9)
13203 state->legacy_cursor_update = false;
13204
13205 ret = drm_atomic_helper_swap_state(state, true);
13206 if (ret) {
13207 i915_sw_fence_commit(&intel_state->commit_ready);
13208
13209 mutex_lock(&dev->struct_mutex);
13210 drm_atomic_helper_cleanup_planes(dev, state);
13211 mutex_unlock(&dev->struct_mutex);
13212 return ret;
13213 }
13214 dev_priv->wm.distrust_bios_wm = false;
13215 intel_shared_dpll_swap_state(state);
13216 intel_atomic_track_fbs(state);
13217
13218 if (intel_state->modeset) {
13219 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13220 sizeof(intel_state->min_pixclk));
13221 dev_priv->active_crtcs = intel_state->active_crtcs;
13222 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13223 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13224 }
13225
13226 drm_atomic_state_get(state);
13227 INIT_WORK(&state->commit_work,
13228 nonblock ? intel_atomic_commit_work : NULL);
13229
13230 i915_sw_fence_commit(&intel_state->commit_ready);
13231 if (!nonblock) {
13232 i915_sw_fence_wait(&intel_state->commit_ready);
13233 intel_atomic_commit_tail(state);
13234 }
13235
13236 return 0;
13237 }
13238
13239 static const struct drm_crtc_funcs intel_crtc_funcs = {
13240 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13241 .set_config = drm_atomic_helper_set_config,
13242 .destroy = intel_crtc_destroy,
13243 .page_flip = drm_atomic_helper_page_flip,
13244 .atomic_duplicate_state = intel_crtc_duplicate_state,
13245 .atomic_destroy_state = intel_crtc_destroy_state,
13246 .set_crc_source = intel_crtc_set_crc_source,
13247 };
13248
13249 /**
13250 * intel_prepare_plane_fb - Prepare fb for usage on plane
13251 * @plane: drm plane to prepare for
13252 * @fb: framebuffer to prepare for presentation
13253 *
13254 * Prepares a framebuffer for usage on a display plane. Generally this
13255 * involves pinning the underlying object and updating the frontbuffer tracking
13256 * bits. Some older platforms need special physical address handling for
13257 * cursor planes.
13258 *
13259 * Must be called with struct_mutex held.
13260 *
13261 * Returns 0 on success, negative error code on failure.
13262 */
13263 int
13264 intel_prepare_plane_fb(struct drm_plane *plane,
13265 struct drm_plane_state *new_state)
13266 {
13267 struct intel_atomic_state *intel_state =
13268 to_intel_atomic_state(new_state->state);
13269 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13270 struct drm_framebuffer *fb = new_state->fb;
13271 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13272 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13273 int ret;
13274
13275 if (obj) {
13276 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13277 INTEL_INFO(dev_priv)->cursor_needs_physical) {
13278 const int align = intel_cursor_alignment(dev_priv);
13279
13280 ret = i915_gem_object_attach_phys(obj, align);
13281 if (ret) {
13282 DRM_DEBUG_KMS("failed to attach phys object\n");
13283 return ret;
13284 }
13285 } else {
13286 struct i915_vma *vma;
13287
13288 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13289 if (IS_ERR(vma)) {
13290 DRM_DEBUG_KMS("failed to pin object\n");
13291 return PTR_ERR(vma);
13292 }
13293
13294 to_intel_plane_state(new_state)->vma = vma;
13295 }
13296 }
13297
13298 if (!obj && !old_obj)
13299 return 0;
13300
13301 if (old_obj) {
13302 struct drm_crtc_state *crtc_state =
13303 drm_atomic_get_existing_crtc_state(new_state->state,
13304 plane->state->crtc);
13305
13306 /* Big Hammer, we also need to ensure that any pending
13307 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13308 * current scanout is retired before unpinning the old
13309 * framebuffer. Note that we rely on userspace rendering
13310 * into the buffer attached to the pipe they are waiting
13311 * on. If not, userspace generates a GPU hang with IPEHR
13312 * point to the MI_WAIT_FOR_EVENT.
13313 *
13314 * This should only fail upon a hung GPU, in which case we
13315 * can safely continue.
13316 */
13317 if (needs_modeset(crtc_state)) {
13318 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13319 old_obj->resv, NULL,
13320 false, 0,
13321 GFP_KERNEL);
13322 if (ret < 0)
13323 return ret;
13324 }
13325 }
13326
13327 if (new_state->fence) { /* explicit fencing */
13328 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13329 new_state->fence,
13330 I915_FENCE_TIMEOUT,
13331 GFP_KERNEL);
13332 if (ret < 0)
13333 return ret;
13334 }
13335
13336 if (!obj)
13337 return 0;
13338
13339 if (!new_state->fence) { /* implicit fencing */
13340 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13341 obj->resv, NULL,
13342 false, I915_FENCE_TIMEOUT,
13343 GFP_KERNEL);
13344 if (ret < 0)
13345 return ret;
13346
13347 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13348 }
13349
13350 return 0;
13351 }
13352
13353 /**
13354 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13355 * @plane: drm plane to clean up for
13356 * @fb: old framebuffer that was on plane
13357 *
13358 * Cleans up a framebuffer that has just been removed from a plane.
13359 *
13360 * Must be called with struct_mutex held.
13361 */
13362 void
13363 intel_cleanup_plane_fb(struct drm_plane *plane,
13364 struct drm_plane_state *old_state)
13365 {
13366 struct i915_vma *vma;
13367
13368 /* Should only be called after a successful intel_prepare_plane_fb()! */
13369 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13370 if (vma)
13371 intel_unpin_fb_vma(vma);
13372 }
13373
13374 int
13375 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13376 {
13377 struct drm_i915_private *dev_priv;
13378 int max_scale;
13379 int crtc_clock, max_dotclk;
13380
13381 if (!intel_crtc || !crtc_state->base.enable)
13382 return DRM_PLANE_HELPER_NO_SCALING;
13383
13384 dev_priv = to_i915(intel_crtc->base.dev);
13385
13386 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13387 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13388
13389 if (IS_GEMINILAKE(dev_priv))
13390 max_dotclk *= 2;
13391
13392 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13393 return DRM_PLANE_HELPER_NO_SCALING;
13394
13395 /*
13396 * skl max scale is lower of:
13397 * close to 3 but not 3, -1 is for that purpose
13398 * or
13399 * cdclk/crtc_clock
13400 */
13401 max_scale = min((1 << 16) * 3 - 1,
13402 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13403
13404 return max_scale;
13405 }
13406
13407 static int
13408 intel_check_primary_plane(struct intel_plane *plane,
13409 struct intel_crtc_state *crtc_state,
13410 struct intel_plane_state *state)
13411 {
13412 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13413 struct drm_crtc *crtc = state->base.crtc;
13414 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13415 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13416 bool can_position = false;
13417 int ret;
13418
13419 if (INTEL_GEN(dev_priv) >= 9) {
13420 /* use scaler when colorkey is not required */
13421 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13422 min_scale = 1;
13423 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13424 }
13425 can_position = true;
13426 }
13427
13428 ret = drm_plane_helper_check_state(&state->base,
13429 &state->clip,
13430 min_scale, max_scale,
13431 can_position, true);
13432 if (ret)
13433 return ret;
13434
13435 if (!state->base.fb)
13436 return 0;
13437
13438 if (INTEL_GEN(dev_priv) >= 9) {
13439 ret = skl_check_plane_surface(state);
13440 if (ret)
13441 return ret;
13442
13443 state->ctl = skl_plane_ctl(crtc_state, state);
13444 } else {
13445 ret = i9xx_check_plane_surface(state);
13446 if (ret)
13447 return ret;
13448
13449 state->ctl = i9xx_plane_ctl(crtc_state, state);
13450 }
13451
13452 return 0;
13453 }
13454
13455 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13456 struct drm_crtc_state *old_crtc_state)
13457 {
13458 struct drm_device *dev = crtc->dev;
13459 struct drm_i915_private *dev_priv = to_i915(dev);
13460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13461 struct intel_crtc_state *intel_cstate =
13462 to_intel_crtc_state(crtc->state);
13463 struct intel_crtc_state *old_intel_cstate =
13464 to_intel_crtc_state(old_crtc_state);
13465 struct intel_atomic_state *old_intel_state =
13466 to_intel_atomic_state(old_crtc_state->state);
13467 bool modeset = needs_modeset(crtc->state);
13468
13469 if (!modeset &&
13470 (intel_cstate->base.color_mgmt_changed ||
13471 intel_cstate->update_pipe)) {
13472 intel_color_set_csc(crtc->state);
13473 intel_color_load_luts(crtc->state);
13474 }
13475
13476 /* Perform vblank evasion around commit operation */
13477 intel_pipe_update_start(intel_crtc);
13478
13479 if (modeset)
13480 goto out;
13481
13482 if (intel_cstate->update_pipe)
13483 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13484 else if (INTEL_GEN(dev_priv) >= 9)
13485 skl_detach_scalers(intel_crtc);
13486
13487 out:
13488 if (dev_priv->display.atomic_update_watermarks)
13489 dev_priv->display.atomic_update_watermarks(old_intel_state,
13490 intel_cstate);
13491 }
13492
13493 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13494 struct drm_crtc_state *old_crtc_state)
13495 {
13496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13497
13498 intel_pipe_update_end(intel_crtc, NULL);
13499 }
13500
13501 /**
13502 * intel_plane_destroy - destroy a plane
13503 * @plane: plane to destroy
13504 *
13505 * Common destruction function for all types of planes (primary, cursor,
13506 * sprite).
13507 */
13508 void intel_plane_destroy(struct drm_plane *plane)
13509 {
13510 drm_plane_cleanup(plane);
13511 kfree(to_intel_plane(plane));
13512 }
13513
13514 const struct drm_plane_funcs intel_plane_funcs = {
13515 .update_plane = drm_atomic_helper_update_plane,
13516 .disable_plane = drm_atomic_helper_disable_plane,
13517 .destroy = intel_plane_destroy,
13518 .atomic_get_property = intel_plane_atomic_get_property,
13519 .atomic_set_property = intel_plane_atomic_set_property,
13520 .atomic_duplicate_state = intel_plane_duplicate_state,
13521 .atomic_destroy_state = intel_plane_destroy_state,
13522 };
13523
13524 static int
13525 intel_legacy_cursor_update(struct drm_plane *plane,
13526 struct drm_crtc *crtc,
13527 struct drm_framebuffer *fb,
13528 int crtc_x, int crtc_y,
13529 unsigned int crtc_w, unsigned int crtc_h,
13530 uint32_t src_x, uint32_t src_y,
13531 uint32_t src_w, uint32_t src_h,
13532 struct drm_modeset_acquire_ctx *ctx)
13533 {
13534 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13535 int ret;
13536 struct drm_plane_state *old_plane_state, *new_plane_state;
13537 struct intel_plane *intel_plane = to_intel_plane(plane);
13538 struct drm_framebuffer *old_fb;
13539 struct drm_crtc_state *crtc_state = crtc->state;
13540 struct i915_vma *old_vma;
13541
13542 /*
13543 * When crtc is inactive or there is a modeset pending,
13544 * wait for it to complete in the slowpath
13545 */
13546 if (!crtc_state->active || needs_modeset(crtc_state) ||
13547 to_intel_crtc_state(crtc_state)->update_pipe)
13548 goto slow;
13549
13550 old_plane_state = plane->state;
13551 /*
13552 * Don't do an async update if there is an outstanding commit modifying
13553 * the plane. This prevents our async update's changes from getting
13554 * overridden by a previous synchronous update's state.
13555 */
13556 if (old_plane_state->commit &&
13557 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13558 goto slow;
13559
13560 /*
13561 * If any parameters change that may affect watermarks,
13562 * take the slowpath. Only changing fb or position should be
13563 * in the fastpath.
13564 */
13565 if (old_plane_state->crtc != crtc ||
13566 old_plane_state->src_w != src_w ||
13567 old_plane_state->src_h != src_h ||
13568 old_plane_state->crtc_w != crtc_w ||
13569 old_plane_state->crtc_h != crtc_h ||
13570 !old_plane_state->fb != !fb)
13571 goto slow;
13572
13573 new_plane_state = intel_plane_duplicate_state(plane);
13574 if (!new_plane_state)
13575 return -ENOMEM;
13576
13577 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13578
13579 new_plane_state->src_x = src_x;
13580 new_plane_state->src_y = src_y;
13581 new_plane_state->src_w = src_w;
13582 new_plane_state->src_h = src_h;
13583 new_plane_state->crtc_x = crtc_x;
13584 new_plane_state->crtc_y = crtc_y;
13585 new_plane_state->crtc_w = crtc_w;
13586 new_plane_state->crtc_h = crtc_h;
13587
13588 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13589 to_intel_plane_state(new_plane_state));
13590 if (ret)
13591 goto out_free;
13592
13593 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13594 if (ret)
13595 goto out_free;
13596
13597 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13598 int align = intel_cursor_alignment(dev_priv);
13599
13600 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13601 if (ret) {
13602 DRM_DEBUG_KMS("failed to attach phys object\n");
13603 goto out_unlock;
13604 }
13605 } else {
13606 struct i915_vma *vma;
13607
13608 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13609 if (IS_ERR(vma)) {
13610 DRM_DEBUG_KMS("failed to pin object\n");
13611
13612 ret = PTR_ERR(vma);
13613 goto out_unlock;
13614 }
13615
13616 to_intel_plane_state(new_plane_state)->vma = vma;
13617 }
13618
13619 old_fb = old_plane_state->fb;
13620
13621 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13622 intel_plane->frontbuffer_bit);
13623
13624 /* Swap plane state */
13625 plane->state = new_plane_state;
13626
13627 if (plane->state->visible) {
13628 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13629 intel_plane->update_plane(intel_plane,
13630 to_intel_crtc_state(crtc->state),
13631 to_intel_plane_state(plane->state));
13632 } else {
13633 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13634 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13635 }
13636
13637 old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13638 if (old_vma)
13639 intel_unpin_fb_vma(old_vma);
13640
13641 out_unlock:
13642 mutex_unlock(&dev_priv->drm.struct_mutex);
13643 out_free:
13644 if (ret)
13645 intel_plane_destroy_state(plane, new_plane_state);
13646 else
13647 intel_plane_destroy_state(plane, old_plane_state);
13648 return ret;
13649
13650 slow:
13651 return drm_atomic_helper_update_plane(plane, crtc, fb,
13652 crtc_x, crtc_y, crtc_w, crtc_h,
13653 src_x, src_y, src_w, src_h, ctx);
13654 }
13655
13656 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13657 .update_plane = intel_legacy_cursor_update,
13658 .disable_plane = drm_atomic_helper_disable_plane,
13659 .destroy = intel_plane_destroy,
13660 .atomic_get_property = intel_plane_atomic_get_property,
13661 .atomic_set_property = intel_plane_atomic_set_property,
13662 .atomic_duplicate_state = intel_plane_duplicate_state,
13663 .atomic_destroy_state = intel_plane_destroy_state,
13664 };
13665
13666 static struct intel_plane *
13667 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13668 {
13669 struct intel_plane *primary = NULL;
13670 struct intel_plane_state *state = NULL;
13671 const uint32_t *intel_primary_formats;
13672 unsigned int supported_rotations;
13673 unsigned int num_formats;
13674 int ret;
13675
13676 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13677 if (!primary) {
13678 ret = -ENOMEM;
13679 goto fail;
13680 }
13681
13682 state = intel_create_plane_state(&primary->base);
13683 if (!state) {
13684 ret = -ENOMEM;
13685 goto fail;
13686 }
13687
13688 primary->base.state = &state->base;
13689
13690 primary->can_scale = false;
13691 primary->max_downscale = 1;
13692 if (INTEL_GEN(dev_priv) >= 9) {
13693 primary->can_scale = true;
13694 state->scaler_id = -1;
13695 }
13696 primary->pipe = pipe;
13697 /*
13698 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13699 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13700 */
13701 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13702 primary->plane = (enum plane) !pipe;
13703 else
13704 primary->plane = (enum plane) pipe;
13705 primary->id = PLANE_PRIMARY;
13706 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13707 primary->check_plane = intel_check_primary_plane;
13708
13709 if (INTEL_GEN(dev_priv) >= 9) {
13710 intel_primary_formats = skl_primary_formats;
13711 num_formats = ARRAY_SIZE(skl_primary_formats);
13712
13713 primary->update_plane = skylake_update_primary_plane;
13714 primary->disable_plane = skylake_disable_primary_plane;
13715 } else if (INTEL_GEN(dev_priv) >= 4) {
13716 intel_primary_formats = i965_primary_formats;
13717 num_formats = ARRAY_SIZE(i965_primary_formats);
13718
13719 primary->update_plane = i9xx_update_primary_plane;
13720 primary->disable_plane = i9xx_disable_primary_plane;
13721 } else {
13722 intel_primary_formats = i8xx_primary_formats;
13723 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13724
13725 primary->update_plane = i9xx_update_primary_plane;
13726 primary->disable_plane = i9xx_disable_primary_plane;
13727 }
13728
13729 if (INTEL_GEN(dev_priv) >= 9)
13730 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13731 0, &intel_plane_funcs,
13732 intel_primary_formats, num_formats,
13733 NULL,
13734 DRM_PLANE_TYPE_PRIMARY,
13735 "plane 1%c", pipe_name(pipe));
13736 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13737 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13738 0, &intel_plane_funcs,
13739 intel_primary_formats, num_formats,
13740 NULL,
13741 DRM_PLANE_TYPE_PRIMARY,
13742 "primary %c", pipe_name(pipe));
13743 else
13744 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13745 0, &intel_plane_funcs,
13746 intel_primary_formats, num_formats,
13747 NULL,
13748 DRM_PLANE_TYPE_PRIMARY,
13749 "plane %c", plane_name(primary->plane));
13750 if (ret)
13751 goto fail;
13752
13753 if (INTEL_GEN(dev_priv) >= 9) {
13754 supported_rotations =
13755 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13756 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13757 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13758 supported_rotations =
13759 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13760 DRM_MODE_REFLECT_X;
13761 } else if (INTEL_GEN(dev_priv) >= 4) {
13762 supported_rotations =
13763 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13764 } else {
13765 supported_rotations = DRM_MODE_ROTATE_0;
13766 }
13767
13768 if (INTEL_GEN(dev_priv) >= 4)
13769 drm_plane_create_rotation_property(&primary->base,
13770 DRM_MODE_ROTATE_0,
13771 supported_rotations);
13772
13773 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13774
13775 return primary;
13776
13777 fail:
13778 kfree(state);
13779 kfree(primary);
13780
13781 return ERR_PTR(ret);
13782 }
13783
13784 static struct intel_plane *
13785 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13786 enum pipe pipe)
13787 {
13788 struct intel_plane *cursor = NULL;
13789 struct intel_plane_state *state = NULL;
13790 int ret;
13791
13792 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13793 if (!cursor) {
13794 ret = -ENOMEM;
13795 goto fail;
13796 }
13797
13798 state = intel_create_plane_state(&cursor->base);
13799 if (!state) {
13800 ret = -ENOMEM;
13801 goto fail;
13802 }
13803
13804 cursor->base.state = &state->base;
13805
13806 cursor->can_scale = false;
13807 cursor->max_downscale = 1;
13808 cursor->pipe = pipe;
13809 cursor->plane = pipe;
13810 cursor->id = PLANE_CURSOR;
13811 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13812
13813 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13814 cursor->update_plane = i845_update_cursor;
13815 cursor->disable_plane = i845_disable_cursor;
13816 cursor->check_plane = i845_check_cursor;
13817 } else {
13818 cursor->update_plane = i9xx_update_cursor;
13819 cursor->disable_plane = i9xx_disable_cursor;
13820 cursor->check_plane = i9xx_check_cursor;
13821 }
13822
13823 cursor->cursor.base = ~0;
13824 cursor->cursor.cntl = ~0;
13825
13826 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13827 cursor->cursor.size = ~0;
13828
13829 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13830 0, &intel_cursor_plane_funcs,
13831 intel_cursor_formats,
13832 ARRAY_SIZE(intel_cursor_formats),
13833 NULL, DRM_PLANE_TYPE_CURSOR,
13834 "cursor %c", pipe_name(pipe));
13835 if (ret)
13836 goto fail;
13837
13838 if (INTEL_GEN(dev_priv) >= 4)
13839 drm_plane_create_rotation_property(&cursor->base,
13840 DRM_MODE_ROTATE_0,
13841 DRM_MODE_ROTATE_0 |
13842 DRM_MODE_ROTATE_180);
13843
13844 if (INTEL_GEN(dev_priv) >= 9)
13845 state->scaler_id = -1;
13846
13847 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13848
13849 return cursor;
13850
13851 fail:
13852 kfree(state);
13853 kfree(cursor);
13854
13855 return ERR_PTR(ret);
13856 }
13857
13858 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13859 struct intel_crtc_state *crtc_state)
13860 {
13861 struct intel_crtc_scaler_state *scaler_state =
13862 &crtc_state->scaler_state;
13863 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13864 int i;
13865
13866 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13867 if (!crtc->num_scalers)
13868 return;
13869
13870 for (i = 0; i < crtc->num_scalers; i++) {
13871 struct intel_scaler *scaler = &scaler_state->scalers[i];
13872
13873 scaler->in_use = 0;
13874 scaler->mode = PS_SCALER_MODE_DYN;
13875 }
13876
13877 scaler_state->scaler_id = -1;
13878 }
13879
13880 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13881 {
13882 struct intel_crtc *intel_crtc;
13883 struct intel_crtc_state *crtc_state = NULL;
13884 struct intel_plane *primary = NULL;
13885 struct intel_plane *cursor = NULL;
13886 int sprite, ret;
13887
13888 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13889 if (!intel_crtc)
13890 return -ENOMEM;
13891
13892 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13893 if (!crtc_state) {
13894 ret = -ENOMEM;
13895 goto fail;
13896 }
13897 intel_crtc->config = crtc_state;
13898 intel_crtc->base.state = &crtc_state->base;
13899 crtc_state->base.crtc = &intel_crtc->base;
13900
13901 primary = intel_primary_plane_create(dev_priv, pipe);
13902 if (IS_ERR(primary)) {
13903 ret = PTR_ERR(primary);
13904 goto fail;
13905 }
13906 intel_crtc->plane_ids_mask |= BIT(primary->id);
13907
13908 for_each_sprite(dev_priv, pipe, sprite) {
13909 struct intel_plane *plane;
13910
13911 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13912 if (IS_ERR(plane)) {
13913 ret = PTR_ERR(plane);
13914 goto fail;
13915 }
13916 intel_crtc->plane_ids_mask |= BIT(plane->id);
13917 }
13918
13919 cursor = intel_cursor_plane_create(dev_priv, pipe);
13920 if (IS_ERR(cursor)) {
13921 ret = PTR_ERR(cursor);
13922 goto fail;
13923 }
13924 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13925
13926 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13927 &primary->base, &cursor->base,
13928 &intel_crtc_funcs,
13929 "pipe %c", pipe_name(pipe));
13930 if (ret)
13931 goto fail;
13932
13933 intel_crtc->pipe = pipe;
13934 intel_crtc->plane = primary->plane;
13935
13936 /* initialize shared scalers */
13937 intel_crtc_init_scalers(intel_crtc, crtc_state);
13938
13939 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13940 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13941 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13942 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13943
13944 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13945
13946 intel_color_init(&intel_crtc->base);
13947
13948 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13949
13950 return 0;
13951
13952 fail:
13953 /*
13954 * drm_mode_config_cleanup() will free up any
13955 * crtcs/planes already initialized.
13956 */
13957 kfree(crtc_state);
13958 kfree(intel_crtc);
13959
13960 return ret;
13961 }
13962
13963 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13964 {
13965 struct drm_device *dev = connector->base.dev;
13966
13967 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13968
13969 if (!connector->base.state->crtc)
13970 return INVALID_PIPE;
13971
13972 return to_intel_crtc(connector->base.state->crtc)->pipe;
13973 }
13974
13975 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13976 struct drm_file *file)
13977 {
13978 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13979 struct drm_crtc *drmmode_crtc;
13980 struct intel_crtc *crtc;
13981
13982 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13983 if (!drmmode_crtc)
13984 return -ENOENT;
13985
13986 crtc = to_intel_crtc(drmmode_crtc);
13987 pipe_from_crtc_id->pipe = crtc->pipe;
13988
13989 return 0;
13990 }
13991
13992 static int intel_encoder_clones(struct intel_encoder *encoder)
13993 {
13994 struct drm_device *dev = encoder->base.dev;
13995 struct intel_encoder *source_encoder;
13996 int index_mask = 0;
13997 int entry = 0;
13998
13999 for_each_intel_encoder(dev, source_encoder) {
14000 if (encoders_cloneable(encoder, source_encoder))
14001 index_mask |= (1 << entry);
14002
14003 entry++;
14004 }
14005
14006 return index_mask;
14007 }
14008
14009 static bool has_edp_a(struct drm_i915_private *dev_priv)
14010 {
14011 if (!IS_MOBILE(dev_priv))
14012 return false;
14013
14014 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14015 return false;
14016
14017 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14018 return false;
14019
14020 return true;
14021 }
14022
14023 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14024 {
14025 if (INTEL_GEN(dev_priv) >= 9)
14026 return false;
14027
14028 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14029 return false;
14030
14031 if (IS_CHERRYVIEW(dev_priv))
14032 return false;
14033
14034 if (HAS_PCH_LPT_H(dev_priv) &&
14035 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14036 return false;
14037
14038 /* DDI E can't be used if DDI A requires 4 lanes */
14039 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14040 return false;
14041
14042 if (!dev_priv->vbt.int_crt_support)
14043 return false;
14044
14045 return true;
14046 }
14047
14048 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14049 {
14050 int pps_num;
14051 int pps_idx;
14052
14053 if (HAS_DDI(dev_priv))
14054 return;
14055 /*
14056 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14057 * everywhere where registers can be write protected.
14058 */
14059 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14060 pps_num = 2;
14061 else
14062 pps_num = 1;
14063
14064 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14065 u32 val = I915_READ(PP_CONTROL(pps_idx));
14066
14067 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14068 I915_WRITE(PP_CONTROL(pps_idx), val);
14069 }
14070 }
14071
14072 static void intel_pps_init(struct drm_i915_private *dev_priv)
14073 {
14074 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14075 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14076 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14077 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14078 else
14079 dev_priv->pps_mmio_base = PPS_BASE;
14080
14081 intel_pps_unlock_regs_wa(dev_priv);
14082 }
14083
14084 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14085 {
14086 struct intel_encoder *encoder;
14087 bool dpd_is_edp = false;
14088
14089 intel_pps_init(dev_priv);
14090
14091 /*
14092 * intel_edp_init_connector() depends on this completing first, to
14093 * prevent the registeration of both eDP and LVDS and the incorrect
14094 * sharing of the PPS.
14095 */
14096 intel_lvds_init(dev_priv);
14097
14098 if (intel_crt_present(dev_priv))
14099 intel_crt_init(dev_priv);
14100
14101 if (IS_GEN9_LP(dev_priv)) {
14102 /*
14103 * FIXME: Broxton doesn't support port detection via the
14104 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14105 * detect the ports.
14106 */
14107 intel_ddi_init(dev_priv, PORT_A);
14108 intel_ddi_init(dev_priv, PORT_B);
14109 intel_ddi_init(dev_priv, PORT_C);
14110
14111 intel_dsi_init(dev_priv);
14112 } else if (HAS_DDI(dev_priv)) {
14113 int found;
14114
14115 /*
14116 * Haswell uses DDI functions to detect digital outputs.
14117 * On SKL pre-D0 the strap isn't connected, so we assume
14118 * it's there.
14119 */
14120 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14121 /* WaIgnoreDDIAStrap: skl */
14122 if (found || IS_GEN9_BC(dev_priv))
14123 intel_ddi_init(dev_priv, PORT_A);
14124
14125 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14126 * register */
14127 found = I915_READ(SFUSE_STRAP);
14128
14129 if (found & SFUSE_STRAP_DDIB_DETECTED)
14130 intel_ddi_init(dev_priv, PORT_B);
14131 if (found & SFUSE_STRAP_DDIC_DETECTED)
14132 intel_ddi_init(dev_priv, PORT_C);
14133 if (found & SFUSE_STRAP_DDID_DETECTED)
14134 intel_ddi_init(dev_priv, PORT_D);
14135 /*
14136 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14137 */
14138 if (IS_GEN9_BC(dev_priv) &&
14139 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14140 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14141 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14142 intel_ddi_init(dev_priv, PORT_E);
14143
14144 } else if (HAS_PCH_SPLIT(dev_priv)) {
14145 int found;
14146 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14147
14148 if (has_edp_a(dev_priv))
14149 intel_dp_init(dev_priv, DP_A, PORT_A);
14150
14151 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14152 /* PCH SDVOB multiplex with HDMIB */
14153 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14154 if (!found)
14155 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14156 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14157 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14158 }
14159
14160 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14161 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14162
14163 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14164 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14165
14166 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14167 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14168
14169 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14170 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14171 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14172 bool has_edp, has_port;
14173
14174 /*
14175 * The DP_DETECTED bit is the latched state of the DDC
14176 * SDA pin at boot. However since eDP doesn't require DDC
14177 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14178 * eDP ports may have been muxed to an alternate function.
14179 * Thus we can't rely on the DP_DETECTED bit alone to detect
14180 * eDP ports. Consult the VBT as well as DP_DETECTED to
14181 * detect eDP ports.
14182 *
14183 * Sadly the straps seem to be missing sometimes even for HDMI
14184 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14185 * and VBT for the presence of the port. Additionally we can't
14186 * trust the port type the VBT declares as we've seen at least
14187 * HDMI ports that the VBT claim are DP or eDP.
14188 */
14189 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14190 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14191 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14192 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14193 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14194 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14195
14196 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14197 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14198 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14199 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14200 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14201 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14202
14203 if (IS_CHERRYVIEW(dev_priv)) {
14204 /*
14205 * eDP not supported on port D,
14206 * so no need to worry about it
14207 */
14208 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14209 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14210 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14211 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14212 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14213 }
14214
14215 intel_dsi_init(dev_priv);
14216 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14217 bool found = false;
14218
14219 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14220 DRM_DEBUG_KMS("probing SDVOB\n");
14221 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14222 if (!found && IS_G4X(dev_priv)) {
14223 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14224 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14225 }
14226
14227 if (!found && IS_G4X(dev_priv))
14228 intel_dp_init(dev_priv, DP_B, PORT_B);
14229 }
14230
14231 /* Before G4X SDVOC doesn't have its own detect register */
14232
14233 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14234 DRM_DEBUG_KMS("probing SDVOC\n");
14235 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14236 }
14237
14238 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14239
14240 if (IS_G4X(dev_priv)) {
14241 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14242 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14243 }
14244 if (IS_G4X(dev_priv))
14245 intel_dp_init(dev_priv, DP_C, PORT_C);
14246 }
14247
14248 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14249 intel_dp_init(dev_priv, DP_D, PORT_D);
14250 } else if (IS_GEN2(dev_priv))
14251 intel_dvo_init(dev_priv);
14252
14253 if (SUPPORTS_TV(dev_priv))
14254 intel_tv_init(dev_priv);
14255
14256 intel_psr_init(dev_priv);
14257
14258 for_each_intel_encoder(&dev_priv->drm, encoder) {
14259 encoder->base.possible_crtcs = encoder->crtc_mask;
14260 encoder->base.possible_clones =
14261 intel_encoder_clones(encoder);
14262 }
14263
14264 intel_init_pch_refclk(dev_priv);
14265
14266 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14267 }
14268
14269 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14270 {
14271 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14272
14273 drm_framebuffer_cleanup(fb);
14274
14275 i915_gem_object_lock(intel_fb->obj);
14276 WARN_ON(!intel_fb->obj->framebuffer_references--);
14277 i915_gem_object_unlock(intel_fb->obj);
14278
14279 i915_gem_object_put(intel_fb->obj);
14280
14281 kfree(intel_fb);
14282 }
14283
14284 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14285 struct drm_file *file,
14286 unsigned int *handle)
14287 {
14288 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14289 struct drm_i915_gem_object *obj = intel_fb->obj;
14290
14291 if (obj->userptr.mm) {
14292 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14293 return -EINVAL;
14294 }
14295
14296 return drm_gem_handle_create(file, &obj->base, handle);
14297 }
14298
14299 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14300 struct drm_file *file,
14301 unsigned flags, unsigned color,
14302 struct drm_clip_rect *clips,
14303 unsigned num_clips)
14304 {
14305 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14306
14307 i915_gem_object_flush_if_display(obj);
14308 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14309
14310 return 0;
14311 }
14312
14313 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14314 .destroy = intel_user_framebuffer_destroy,
14315 .create_handle = intel_user_framebuffer_create_handle,
14316 .dirty = intel_user_framebuffer_dirty,
14317 };
14318
14319 static
14320 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14321 uint64_t fb_modifier, uint32_t pixel_format)
14322 {
14323 u32 gen = INTEL_GEN(dev_priv);
14324
14325 if (gen >= 9) {
14326 int cpp = drm_format_plane_cpp(pixel_format, 0);
14327
14328 /* "The stride in bytes must not exceed the of the size of 8K
14329 * pixels and 32K bytes."
14330 */
14331 return min(8192 * cpp, 32768);
14332 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14333 return 32*1024;
14334 } else if (gen >= 4) {
14335 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14336 return 16*1024;
14337 else
14338 return 32*1024;
14339 } else if (gen >= 3) {
14340 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14341 return 8*1024;
14342 else
14343 return 16*1024;
14344 } else {
14345 /* XXX DSPC is limited to 4k tiled */
14346 return 8*1024;
14347 }
14348 }
14349
14350 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14351 struct drm_i915_gem_object *obj,
14352 struct drm_mode_fb_cmd2 *mode_cmd)
14353 {
14354 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14355 struct drm_format_name_buf format_name;
14356 u32 pitch_limit, stride_alignment;
14357 unsigned int tiling, stride;
14358 int ret = -EINVAL;
14359
14360 i915_gem_object_lock(obj);
14361 obj->framebuffer_references++;
14362 tiling = i915_gem_object_get_tiling(obj);
14363 stride = i915_gem_object_get_stride(obj);
14364 i915_gem_object_unlock(obj);
14365
14366 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14367 /*
14368 * If there's a fence, enforce that
14369 * the fb modifier and tiling mode match.
14370 */
14371 if (tiling != I915_TILING_NONE &&
14372 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14373 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14374 goto err;
14375 }
14376 } else {
14377 if (tiling == I915_TILING_X) {
14378 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14379 } else if (tiling == I915_TILING_Y) {
14380 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14381 goto err;
14382 }
14383 }
14384
14385 /* Passed in modifier sanity checking. */
14386 switch (mode_cmd->modifier[0]) {
14387 case I915_FORMAT_MOD_Y_TILED:
14388 case I915_FORMAT_MOD_Yf_TILED:
14389 if (INTEL_GEN(dev_priv) < 9) {
14390 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14391 mode_cmd->modifier[0]);
14392 goto err;
14393 }
14394 case DRM_FORMAT_MOD_LINEAR:
14395 case I915_FORMAT_MOD_X_TILED:
14396 break;
14397 default:
14398 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14399 mode_cmd->modifier[0]);
14400 goto err;
14401 }
14402
14403 /*
14404 * gen2/3 display engine uses the fence if present,
14405 * so the tiling mode must match the fb modifier exactly.
14406 */
14407 if (INTEL_INFO(dev_priv)->gen < 4 &&
14408 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14409 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14410 goto err;
14411 }
14412
14413 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14414 mode_cmd->pixel_format);
14415 if (mode_cmd->pitches[0] > pitch_limit) {
14416 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14417 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14418 "tiled" : "linear",
14419 mode_cmd->pitches[0], pitch_limit);
14420 goto err;
14421 }
14422
14423 /*
14424 * If there's a fence, enforce that
14425 * the fb pitch and fence stride match.
14426 */
14427 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14428 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14429 mode_cmd->pitches[0], stride);
14430 goto err;
14431 }
14432
14433 /* Reject formats not supported by any plane early. */
14434 switch (mode_cmd->pixel_format) {
14435 case DRM_FORMAT_C8:
14436 case DRM_FORMAT_RGB565:
14437 case DRM_FORMAT_XRGB8888:
14438 case DRM_FORMAT_ARGB8888:
14439 break;
14440 case DRM_FORMAT_XRGB1555:
14441 if (INTEL_GEN(dev_priv) > 3) {
14442 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14443 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14444 goto err;
14445 }
14446 break;
14447 case DRM_FORMAT_ABGR8888:
14448 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14449 INTEL_GEN(dev_priv) < 9) {
14450 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14451 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14452 goto err;
14453 }
14454 break;
14455 case DRM_FORMAT_XBGR8888:
14456 case DRM_FORMAT_XRGB2101010:
14457 case DRM_FORMAT_XBGR2101010:
14458 if (INTEL_GEN(dev_priv) < 4) {
14459 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14460 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14461 goto err;
14462 }
14463 break;
14464 case DRM_FORMAT_ABGR2101010:
14465 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14466 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14467 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14468 goto err;
14469 }
14470 break;
14471 case DRM_FORMAT_YUYV:
14472 case DRM_FORMAT_UYVY:
14473 case DRM_FORMAT_YVYU:
14474 case DRM_FORMAT_VYUY:
14475 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14476 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14477 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14478 goto err;
14479 }
14480 break;
14481 default:
14482 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14483 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14484 goto err;
14485 }
14486
14487 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14488 if (mode_cmd->offsets[0] != 0)
14489 goto err;
14490
14491 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14492 &intel_fb->base, mode_cmd);
14493
14494 stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14495 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14496 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14497 mode_cmd->pitches[0], stride_alignment);
14498 goto err;
14499 }
14500
14501 intel_fb->obj = obj;
14502
14503 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14504 if (ret)
14505 goto err;
14506
14507 ret = drm_framebuffer_init(obj->base.dev,
14508 &intel_fb->base,
14509 &intel_fb_funcs);
14510 if (ret) {
14511 DRM_ERROR("framebuffer init failed %d\n", ret);
14512 goto err;
14513 }
14514
14515 return 0;
14516
14517 err:
14518 i915_gem_object_lock(obj);
14519 obj->framebuffer_references--;
14520 i915_gem_object_unlock(obj);
14521 return ret;
14522 }
14523
14524 static struct drm_framebuffer *
14525 intel_user_framebuffer_create(struct drm_device *dev,
14526 struct drm_file *filp,
14527 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14528 {
14529 struct drm_framebuffer *fb;
14530 struct drm_i915_gem_object *obj;
14531 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14532
14533 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14534 if (!obj)
14535 return ERR_PTR(-ENOENT);
14536
14537 fb = intel_framebuffer_create(obj, &mode_cmd);
14538 if (IS_ERR(fb))
14539 i915_gem_object_put(obj);
14540
14541 return fb;
14542 }
14543
14544 static void intel_atomic_state_free(struct drm_atomic_state *state)
14545 {
14546 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14547
14548 drm_atomic_state_default_release(state);
14549
14550 i915_sw_fence_fini(&intel_state->commit_ready);
14551
14552 kfree(state);
14553 }
14554
14555 static const struct drm_mode_config_funcs intel_mode_funcs = {
14556 .fb_create = intel_user_framebuffer_create,
14557 .output_poll_changed = intel_fbdev_output_poll_changed,
14558 .atomic_check = intel_atomic_check,
14559 .atomic_commit = intel_atomic_commit,
14560 .atomic_state_alloc = intel_atomic_state_alloc,
14561 .atomic_state_clear = intel_atomic_state_clear,
14562 .atomic_state_free = intel_atomic_state_free,
14563 };
14564
14565 /**
14566 * intel_init_display_hooks - initialize the display modesetting hooks
14567 * @dev_priv: device private
14568 */
14569 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14570 {
14571 intel_init_cdclk_hooks(dev_priv);
14572
14573 if (INTEL_INFO(dev_priv)->gen >= 9) {
14574 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14575 dev_priv->display.get_initial_plane_config =
14576 skylake_get_initial_plane_config;
14577 dev_priv->display.crtc_compute_clock =
14578 haswell_crtc_compute_clock;
14579 dev_priv->display.crtc_enable = haswell_crtc_enable;
14580 dev_priv->display.crtc_disable = haswell_crtc_disable;
14581 } else if (HAS_DDI(dev_priv)) {
14582 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14583 dev_priv->display.get_initial_plane_config =
14584 ironlake_get_initial_plane_config;
14585 dev_priv->display.crtc_compute_clock =
14586 haswell_crtc_compute_clock;
14587 dev_priv->display.crtc_enable = haswell_crtc_enable;
14588 dev_priv->display.crtc_disable = haswell_crtc_disable;
14589 } else if (HAS_PCH_SPLIT(dev_priv)) {
14590 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14591 dev_priv->display.get_initial_plane_config =
14592 ironlake_get_initial_plane_config;
14593 dev_priv->display.crtc_compute_clock =
14594 ironlake_crtc_compute_clock;
14595 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14596 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14597 } else if (IS_CHERRYVIEW(dev_priv)) {
14598 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14599 dev_priv->display.get_initial_plane_config =
14600 i9xx_get_initial_plane_config;
14601 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14602 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14603 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14604 } else if (IS_VALLEYVIEW(dev_priv)) {
14605 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14606 dev_priv->display.get_initial_plane_config =
14607 i9xx_get_initial_plane_config;
14608 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14609 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14610 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14611 } else if (IS_G4X(dev_priv)) {
14612 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14613 dev_priv->display.get_initial_plane_config =
14614 i9xx_get_initial_plane_config;
14615 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14616 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14617 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14618 } else if (IS_PINEVIEW(dev_priv)) {
14619 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14620 dev_priv->display.get_initial_plane_config =
14621 i9xx_get_initial_plane_config;
14622 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14623 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14624 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14625 } else if (!IS_GEN2(dev_priv)) {
14626 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14627 dev_priv->display.get_initial_plane_config =
14628 i9xx_get_initial_plane_config;
14629 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14630 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14631 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14632 } else {
14633 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14634 dev_priv->display.get_initial_plane_config =
14635 i9xx_get_initial_plane_config;
14636 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14637 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14638 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14639 }
14640
14641 if (IS_GEN5(dev_priv)) {
14642 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14643 } else if (IS_GEN6(dev_priv)) {
14644 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14645 } else if (IS_IVYBRIDGE(dev_priv)) {
14646 /* FIXME: detect B0+ stepping and use auto training */
14647 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14648 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14649 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14650 }
14651
14652 if (dev_priv->info.gen >= 9)
14653 dev_priv->display.update_crtcs = skl_update_crtcs;
14654 else
14655 dev_priv->display.update_crtcs = intel_update_crtcs;
14656
14657 switch (INTEL_INFO(dev_priv)->gen) {
14658 case 2:
14659 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14660 break;
14661
14662 case 3:
14663 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14664 break;
14665
14666 case 4:
14667 case 5:
14668 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14669 break;
14670
14671 case 6:
14672 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14673 break;
14674 case 7:
14675 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14676 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14677 break;
14678 case 9:
14679 /* Drop through - unsupported since execlist only. */
14680 default:
14681 /* Default just returns -ENODEV to indicate unsupported */
14682 dev_priv->display.queue_flip = intel_default_queue_flip;
14683 }
14684 }
14685
14686 /*
14687 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14688 */
14689 static void quirk_ssc_force_disable(struct drm_device *dev)
14690 {
14691 struct drm_i915_private *dev_priv = to_i915(dev);
14692 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14693 DRM_INFO("applying lvds SSC disable quirk\n");
14694 }
14695
14696 /*
14697 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14698 * brightness value
14699 */
14700 static void quirk_invert_brightness(struct drm_device *dev)
14701 {
14702 struct drm_i915_private *dev_priv = to_i915(dev);
14703 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14704 DRM_INFO("applying inverted panel brightness quirk\n");
14705 }
14706
14707 /* Some VBT's incorrectly indicate no backlight is present */
14708 static void quirk_backlight_present(struct drm_device *dev)
14709 {
14710 struct drm_i915_private *dev_priv = to_i915(dev);
14711 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14712 DRM_INFO("applying backlight present quirk\n");
14713 }
14714
14715 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14716 * which is 300 ms greater than eDP spec T12 min.
14717 */
14718 static void quirk_increase_t12_delay(struct drm_device *dev)
14719 {
14720 struct drm_i915_private *dev_priv = to_i915(dev);
14721
14722 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14723 DRM_INFO("Applying T12 delay quirk\n");
14724 }
14725
14726 struct intel_quirk {
14727 int device;
14728 int subsystem_vendor;
14729 int subsystem_device;
14730 void (*hook)(struct drm_device *dev);
14731 };
14732
14733 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14734 struct intel_dmi_quirk {
14735 void (*hook)(struct drm_device *dev);
14736 const struct dmi_system_id (*dmi_id_list)[];
14737 };
14738
14739 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14740 {
14741 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14742 return 1;
14743 }
14744
14745 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14746 {
14747 .dmi_id_list = &(const struct dmi_system_id[]) {
14748 {
14749 .callback = intel_dmi_reverse_brightness,
14750 .ident = "NCR Corporation",
14751 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14752 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14753 },
14754 },
14755 { } /* terminating entry */
14756 },
14757 .hook = quirk_invert_brightness,
14758 },
14759 };
14760
14761 static struct intel_quirk intel_quirks[] = {
14762 /* Lenovo U160 cannot use SSC on LVDS */
14763 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14764
14765 /* Sony Vaio Y cannot use SSC on LVDS */
14766 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14767
14768 /* Acer Aspire 5734Z must invert backlight brightness */
14769 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14770
14771 /* Acer/eMachines G725 */
14772 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14773
14774 /* Acer/eMachines e725 */
14775 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14776
14777 /* Acer/Packard Bell NCL20 */
14778 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14779
14780 /* Acer Aspire 4736Z */
14781 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14782
14783 /* Acer Aspire 5336 */
14784 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14785
14786 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14787 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14788
14789 /* Acer C720 Chromebook (Core i3 4005U) */
14790 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14791
14792 /* Apple Macbook 2,1 (Core 2 T7400) */
14793 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14794
14795 /* Apple Macbook 4,1 */
14796 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14797
14798 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14799 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14800
14801 /* HP Chromebook 14 (Celeron 2955U) */
14802 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14803
14804 /* Dell Chromebook 11 */
14805 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14806
14807 /* Dell Chromebook 11 (2015 version) */
14808 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14809
14810 /* Toshiba Satellite P50-C-18C */
14811 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14812 };
14813
14814 static void intel_init_quirks(struct drm_device *dev)
14815 {
14816 struct pci_dev *d = dev->pdev;
14817 int i;
14818
14819 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14820 struct intel_quirk *q = &intel_quirks[i];
14821
14822 if (d->device == q->device &&
14823 (d->subsystem_vendor == q->subsystem_vendor ||
14824 q->subsystem_vendor == PCI_ANY_ID) &&
14825 (d->subsystem_device == q->subsystem_device ||
14826 q->subsystem_device == PCI_ANY_ID))
14827 q->hook(dev);
14828 }
14829 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14830 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14831 intel_dmi_quirks[i].hook(dev);
14832 }
14833 }
14834
14835 /* Disable the VGA plane that we never use */
14836 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14837 {
14838 struct pci_dev *pdev = dev_priv->drm.pdev;
14839 u8 sr1;
14840 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14841
14842 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14843 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14844 outb(SR01, VGA_SR_INDEX);
14845 sr1 = inb(VGA_SR_DATA);
14846 outb(sr1 | 1<<5, VGA_SR_DATA);
14847 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14848 udelay(300);
14849
14850 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14851 POSTING_READ(vga_reg);
14852 }
14853
14854 void intel_modeset_init_hw(struct drm_device *dev)
14855 {
14856 struct drm_i915_private *dev_priv = to_i915(dev);
14857
14858 intel_update_cdclk(dev_priv);
14859 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14860
14861 intel_init_clock_gating(dev_priv);
14862 }
14863
14864 /*
14865 * Calculate what we think the watermarks should be for the state we've read
14866 * out of the hardware and then immediately program those watermarks so that
14867 * we ensure the hardware settings match our internal state.
14868 *
14869 * We can calculate what we think WM's should be by creating a duplicate of the
14870 * current state (which was constructed during hardware readout) and running it
14871 * through the atomic check code to calculate new watermark values in the
14872 * state object.
14873 */
14874 static void sanitize_watermarks(struct drm_device *dev)
14875 {
14876 struct drm_i915_private *dev_priv = to_i915(dev);
14877 struct drm_atomic_state *state;
14878 struct intel_atomic_state *intel_state;
14879 struct drm_crtc *crtc;
14880 struct drm_crtc_state *cstate;
14881 struct drm_modeset_acquire_ctx ctx;
14882 int ret;
14883 int i;
14884
14885 /* Only supported on platforms that use atomic watermark design */
14886 if (!dev_priv->display.optimize_watermarks)
14887 return;
14888
14889 /*
14890 * We need to hold connection_mutex before calling duplicate_state so
14891 * that the connector loop is protected.
14892 */
14893 drm_modeset_acquire_init(&ctx, 0);
14894 retry:
14895 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14896 if (ret == -EDEADLK) {
14897 drm_modeset_backoff(&ctx);
14898 goto retry;
14899 } else if (WARN_ON(ret)) {
14900 goto fail;
14901 }
14902
14903 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14904 if (WARN_ON(IS_ERR(state)))
14905 goto fail;
14906
14907 intel_state = to_intel_atomic_state(state);
14908
14909 /*
14910 * Hardware readout is the only time we don't want to calculate
14911 * intermediate watermarks (since we don't trust the current
14912 * watermarks).
14913 */
14914 if (!HAS_GMCH_DISPLAY(dev_priv))
14915 intel_state->skip_intermediate_wm = true;
14916
14917 ret = intel_atomic_check(dev, state);
14918 if (ret) {
14919 /*
14920 * If we fail here, it means that the hardware appears to be
14921 * programmed in a way that shouldn't be possible, given our
14922 * understanding of watermark requirements. This might mean a
14923 * mistake in the hardware readout code or a mistake in the
14924 * watermark calculations for a given platform. Raise a WARN
14925 * so that this is noticeable.
14926 *
14927 * If this actually happens, we'll have to just leave the
14928 * BIOS-programmed watermarks untouched and hope for the best.
14929 */
14930 WARN(true, "Could not determine valid watermarks for inherited state\n");
14931 goto put_state;
14932 }
14933
14934 /* Write calculated watermark values back */
14935 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14936 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14937
14938 cs->wm.need_postvbl_update = true;
14939 dev_priv->display.optimize_watermarks(intel_state, cs);
14940 }
14941
14942 put_state:
14943 drm_atomic_state_put(state);
14944 fail:
14945 drm_modeset_drop_locks(&ctx);
14946 drm_modeset_acquire_fini(&ctx);
14947 }
14948
14949 int intel_modeset_init(struct drm_device *dev)
14950 {
14951 struct drm_i915_private *dev_priv = to_i915(dev);
14952 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14953 enum pipe pipe;
14954 struct intel_crtc *crtc;
14955
14956 drm_mode_config_init(dev);
14957
14958 dev->mode_config.min_width = 0;
14959 dev->mode_config.min_height = 0;
14960
14961 dev->mode_config.preferred_depth = 24;
14962 dev->mode_config.prefer_shadow = 1;
14963
14964 dev->mode_config.allow_fb_modifiers = true;
14965
14966 dev->mode_config.funcs = &intel_mode_funcs;
14967
14968 init_llist_head(&dev_priv->atomic_helper.free_list);
14969 INIT_WORK(&dev_priv->atomic_helper.free_work,
14970 intel_atomic_helper_free_state_worker);
14971
14972 intel_init_quirks(dev);
14973
14974 intel_init_pm(dev_priv);
14975
14976 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14977 return 0;
14978
14979 /*
14980 * There may be no VBT; and if the BIOS enabled SSC we can
14981 * just keep using it to avoid unnecessary flicker. Whereas if the
14982 * BIOS isn't using it, don't assume it will work even if the VBT
14983 * indicates as much.
14984 */
14985 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14986 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14987 DREF_SSC1_ENABLE);
14988
14989 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14990 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14991 bios_lvds_use_ssc ? "en" : "dis",
14992 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14993 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14994 }
14995 }
14996
14997 if (IS_GEN2(dev_priv)) {
14998 dev->mode_config.max_width = 2048;
14999 dev->mode_config.max_height = 2048;
15000 } else if (IS_GEN3(dev_priv)) {
15001 dev->mode_config.max_width = 4096;
15002 dev->mode_config.max_height = 4096;
15003 } else {
15004 dev->mode_config.max_width = 8192;
15005 dev->mode_config.max_height = 8192;
15006 }
15007
15008 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15009 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15010 dev->mode_config.cursor_height = 1023;
15011 } else if (IS_GEN2(dev_priv)) {
15012 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15013 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15014 } else {
15015 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15016 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15017 }
15018
15019 dev->mode_config.fb_base = ggtt->mappable_base;
15020
15021 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15022 INTEL_INFO(dev_priv)->num_pipes,
15023 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15024
15025 for_each_pipe(dev_priv, pipe) {
15026 int ret;
15027
15028 ret = intel_crtc_init(dev_priv, pipe);
15029 if (ret) {
15030 drm_mode_config_cleanup(dev);
15031 return ret;
15032 }
15033 }
15034
15035 intel_shared_dpll_init(dev);
15036
15037 intel_update_czclk(dev_priv);
15038 intel_modeset_init_hw(dev);
15039
15040 if (dev_priv->max_cdclk_freq == 0)
15041 intel_update_max_cdclk(dev_priv);
15042
15043 /* Just disable it once at startup */
15044 i915_disable_vga(dev_priv);
15045 intel_setup_outputs(dev_priv);
15046
15047 drm_modeset_lock_all(dev);
15048 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15049 drm_modeset_unlock_all(dev);
15050
15051 for_each_intel_crtc(dev, crtc) {
15052 struct intel_initial_plane_config plane_config = {};
15053
15054 if (!crtc->active)
15055 continue;
15056
15057 /*
15058 * Note that reserving the BIOS fb up front prevents us
15059 * from stuffing other stolen allocations like the ring
15060 * on top. This prevents some ugliness at boot time, and
15061 * can even allow for smooth boot transitions if the BIOS
15062 * fb is large enough for the active pipe configuration.
15063 */
15064 dev_priv->display.get_initial_plane_config(crtc,
15065 &plane_config);
15066
15067 /*
15068 * If the fb is shared between multiple heads, we'll
15069 * just get the first one.
15070 */
15071 intel_find_initial_plane_obj(crtc, &plane_config);
15072 }
15073
15074 /*
15075 * Make sure hardware watermarks really match the state we read out.
15076 * Note that we need to do this after reconstructing the BIOS fb's
15077 * since the watermark calculation done here will use pstate->fb.
15078 */
15079 if (!HAS_GMCH_DISPLAY(dev_priv))
15080 sanitize_watermarks(dev);
15081
15082 return 0;
15083 }
15084
15085 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15086 {
15087 /* 640x480@60Hz, ~25175 kHz */
15088 struct dpll clock = {
15089 .m1 = 18,
15090 .m2 = 7,
15091 .p1 = 13,
15092 .p2 = 4,
15093 .n = 2,
15094 };
15095 u32 dpll, fp;
15096 int i;
15097
15098 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15099
15100 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15101 pipe_name(pipe), clock.vco, clock.dot);
15102
15103 fp = i9xx_dpll_compute_fp(&clock);
15104 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
15105 DPLL_VGA_MODE_DIS |
15106 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15107 PLL_P2_DIVIDE_BY_4 |
15108 PLL_REF_INPUT_DREFCLK |
15109 DPLL_VCO_ENABLE;
15110
15111 I915_WRITE(FP0(pipe), fp);
15112 I915_WRITE(FP1(pipe), fp);
15113
15114 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15115 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15116 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15117 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15118 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15119 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15120 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15121
15122 /*
15123 * Apparently we need to have VGA mode enabled prior to changing
15124 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15125 * dividers, even though the register value does change.
15126 */
15127 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15128 I915_WRITE(DPLL(pipe), dpll);
15129
15130 /* Wait for the clocks to stabilize. */
15131 POSTING_READ(DPLL(pipe));
15132 udelay(150);
15133
15134 /* The pixel multiplier can only be updated once the
15135 * DPLL is enabled and the clocks are stable.
15136 *
15137 * So write it again.
15138 */
15139 I915_WRITE(DPLL(pipe), dpll);
15140
15141 /* We do this three times for luck */
15142 for (i = 0; i < 3 ; i++) {
15143 I915_WRITE(DPLL(pipe), dpll);
15144 POSTING_READ(DPLL(pipe));
15145 udelay(150); /* wait for warmup */
15146 }
15147
15148 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15149 POSTING_READ(PIPECONF(pipe));
15150 }
15151
15152 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15153 {
15154 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15155 pipe_name(pipe));
15156
15157 assert_plane_disabled(dev_priv, PLANE_A);
15158 assert_plane_disabled(dev_priv, PLANE_B);
15159
15160 I915_WRITE(PIPECONF(pipe), 0);
15161 POSTING_READ(PIPECONF(pipe));
15162
15163 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
15164 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
15165
15166 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15167 POSTING_READ(DPLL(pipe));
15168 }
15169
15170 static bool
15171 intel_check_plane_mapping(struct intel_crtc *crtc)
15172 {
15173 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15174 u32 val;
15175
15176 if (INTEL_INFO(dev_priv)->num_pipes == 1)
15177 return true;
15178
15179 val = I915_READ(DSPCNTR(!crtc->plane));
15180
15181 if ((val & DISPLAY_PLANE_ENABLE) &&
15182 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15183 return false;
15184
15185 return true;
15186 }
15187
15188 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15189 {
15190 struct drm_device *dev = crtc->base.dev;
15191 struct intel_encoder *encoder;
15192
15193 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15194 return true;
15195
15196 return false;
15197 }
15198
15199 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15200 {
15201 struct drm_device *dev = encoder->base.dev;
15202 struct intel_connector *connector;
15203
15204 for_each_connector_on_encoder(dev, &encoder->base, connector)
15205 return connector;
15206
15207 return NULL;
15208 }
15209
15210 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15211 enum transcoder pch_transcoder)
15212 {
15213 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15214 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15215 }
15216
15217 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15218 struct drm_modeset_acquire_ctx *ctx)
15219 {
15220 struct drm_device *dev = crtc->base.dev;
15221 struct drm_i915_private *dev_priv = to_i915(dev);
15222 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15223
15224 /* Clear any frame start delays used for debugging left by the BIOS */
15225 if (!transcoder_is_dsi(cpu_transcoder)) {
15226 i915_reg_t reg = PIPECONF(cpu_transcoder);
15227
15228 I915_WRITE(reg,
15229 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15230 }
15231
15232 /* restore vblank interrupts to correct state */
15233 drm_crtc_vblank_reset(&crtc->base);
15234 if (crtc->active) {
15235 struct intel_plane *plane;
15236
15237 drm_crtc_vblank_on(&crtc->base);
15238
15239 /* Disable everything but the primary plane */
15240 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15241 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15242 continue;
15243
15244 trace_intel_disable_plane(&plane->base, crtc);
15245 plane->disable_plane(plane, crtc);
15246 }
15247 }
15248
15249 /* We need to sanitize the plane -> pipe mapping first because this will
15250 * disable the crtc (and hence change the state) if it is wrong. Note
15251 * that gen4+ has a fixed plane -> pipe mapping. */
15252 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15253 bool plane;
15254
15255 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15256 crtc->base.base.id, crtc->base.name);
15257
15258 /* Pipe has the wrong plane attached and the plane is active.
15259 * Temporarily change the plane mapping and disable everything
15260 * ... */
15261 plane = crtc->plane;
15262 crtc->base.primary->state->visible = true;
15263 crtc->plane = !plane;
15264 intel_crtc_disable_noatomic(&crtc->base, ctx);
15265 crtc->plane = plane;
15266 }
15267
15268 /* Adjust the state of the output pipe according to whether we
15269 * have active connectors/encoders. */
15270 if (crtc->active && !intel_crtc_has_encoders(crtc))
15271 intel_crtc_disable_noatomic(&crtc->base, ctx);
15272
15273 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15274 /*
15275 * We start out with underrun reporting disabled to avoid races.
15276 * For correct bookkeeping mark this on active crtcs.
15277 *
15278 * Also on gmch platforms we dont have any hardware bits to
15279 * disable the underrun reporting. Which means we need to start
15280 * out with underrun reporting disabled also on inactive pipes,
15281 * since otherwise we'll complain about the garbage we read when
15282 * e.g. coming up after runtime pm.
15283 *
15284 * No protection against concurrent access is required - at
15285 * worst a fifo underrun happens which also sets this to false.
15286 */
15287 crtc->cpu_fifo_underrun_disabled = true;
15288 /*
15289 * We track the PCH trancoder underrun reporting state
15290 * within the crtc. With crtc for pipe A housing the underrun
15291 * reporting state for PCH transcoder A, crtc for pipe B housing
15292 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15293 * and marking underrun reporting as disabled for the non-existing
15294 * PCH transcoders B and C would prevent enabling the south
15295 * error interrupt (see cpt_can_enable_serr_int()).
15296 */
15297 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15298 crtc->pch_fifo_underrun_disabled = true;
15299 }
15300 }
15301
15302 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15303 {
15304 struct intel_connector *connector;
15305
15306 /* We need to check both for a crtc link (meaning that the
15307 * encoder is active and trying to read from a pipe) and the
15308 * pipe itself being active. */
15309 bool has_active_crtc = encoder->base.crtc &&
15310 to_intel_crtc(encoder->base.crtc)->active;
15311
15312 connector = intel_encoder_find_connector(encoder);
15313 if (connector && !has_active_crtc) {
15314 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15315 encoder->base.base.id,
15316 encoder->base.name);
15317
15318 /* Connector is active, but has no active pipe. This is
15319 * fallout from our resume register restoring. Disable
15320 * the encoder manually again. */
15321 if (encoder->base.crtc) {
15322 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15323
15324 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15325 encoder->base.base.id,
15326 encoder->base.name);
15327 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15328 if (encoder->post_disable)
15329 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15330 }
15331 encoder->base.crtc = NULL;
15332
15333 /* Inconsistent output/port/pipe state happens presumably due to
15334 * a bug in one of the get_hw_state functions. Or someplace else
15335 * in our code, like the register restore mess on resume. Clamp
15336 * things to off as a safer default. */
15337
15338 connector->base.dpms = DRM_MODE_DPMS_OFF;
15339 connector->base.encoder = NULL;
15340 }
15341 /* Enabled encoders without active connectors will be fixed in
15342 * the crtc fixup. */
15343 }
15344
15345 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15346 {
15347 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15348
15349 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15350 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15351 i915_disable_vga(dev_priv);
15352 }
15353 }
15354
15355 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15356 {
15357 /* This function can be called both from intel_modeset_setup_hw_state or
15358 * at a very early point in our resume sequence, where the power well
15359 * structures are not yet restored. Since this function is at a very
15360 * paranoid "someone might have enabled VGA while we were not looking"
15361 * level, just check if the power well is enabled instead of trying to
15362 * follow the "don't touch the power well if we don't need it" policy
15363 * the rest of the driver uses. */
15364 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15365 return;
15366
15367 i915_redisable_vga_power_on(dev_priv);
15368
15369 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15370 }
15371
15372 static bool primary_get_hw_state(struct intel_plane *plane)
15373 {
15374 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15375
15376 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15377 }
15378
15379 /* FIXME read out full plane state for all planes */
15380 static void readout_plane_state(struct intel_crtc *crtc)
15381 {
15382 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15383 bool visible;
15384
15385 visible = crtc->active && primary_get_hw_state(primary);
15386
15387 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15388 to_intel_plane_state(primary->base.state),
15389 visible);
15390 }
15391
15392 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15393 {
15394 struct drm_i915_private *dev_priv = to_i915(dev);
15395 enum pipe pipe;
15396 struct intel_crtc *crtc;
15397 struct intel_encoder *encoder;
15398 struct intel_connector *connector;
15399 struct drm_connector_list_iter conn_iter;
15400 int i;
15401
15402 dev_priv->active_crtcs = 0;
15403
15404 for_each_intel_crtc(dev, crtc) {
15405 struct intel_crtc_state *crtc_state =
15406 to_intel_crtc_state(crtc->base.state);
15407
15408 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15409 memset(crtc_state, 0, sizeof(*crtc_state));
15410 crtc_state->base.crtc = &crtc->base;
15411
15412 crtc_state->base.active = crtc_state->base.enable =
15413 dev_priv->display.get_pipe_config(crtc, crtc_state);
15414
15415 crtc->base.enabled = crtc_state->base.enable;
15416 crtc->active = crtc_state->base.active;
15417
15418 if (crtc_state->base.active)
15419 dev_priv->active_crtcs |= 1 << crtc->pipe;
15420
15421 readout_plane_state(crtc);
15422
15423 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15424 crtc->base.base.id, crtc->base.name,
15425 enableddisabled(crtc_state->base.active));
15426 }
15427
15428 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15429 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15430
15431 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15432 &pll->state.hw_state);
15433 pll->state.crtc_mask = 0;
15434 for_each_intel_crtc(dev, crtc) {
15435 struct intel_crtc_state *crtc_state =
15436 to_intel_crtc_state(crtc->base.state);
15437
15438 if (crtc_state->base.active &&
15439 crtc_state->shared_dpll == pll)
15440 pll->state.crtc_mask |= 1 << crtc->pipe;
15441 }
15442 pll->active_mask = pll->state.crtc_mask;
15443
15444 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15445 pll->name, pll->state.crtc_mask, pll->on);
15446 }
15447
15448 for_each_intel_encoder(dev, encoder) {
15449 pipe = 0;
15450
15451 if (encoder->get_hw_state(encoder, &pipe)) {
15452 struct intel_crtc_state *crtc_state;
15453
15454 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15455 crtc_state = to_intel_crtc_state(crtc->base.state);
15456
15457 encoder->base.crtc = &crtc->base;
15458 crtc_state->output_types |= 1 << encoder->type;
15459 encoder->get_config(encoder, crtc_state);
15460 } else {
15461 encoder->base.crtc = NULL;
15462 }
15463
15464 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15465 encoder->base.base.id, encoder->base.name,
15466 enableddisabled(encoder->base.crtc),
15467 pipe_name(pipe));
15468 }
15469
15470 drm_connector_list_iter_begin(dev, &conn_iter);
15471 for_each_intel_connector_iter(connector, &conn_iter) {
15472 if (connector->get_hw_state(connector)) {
15473 connector->base.dpms = DRM_MODE_DPMS_ON;
15474
15475 encoder = connector->encoder;
15476 connector->base.encoder = &encoder->base;
15477
15478 if (encoder->base.crtc &&
15479 encoder->base.crtc->state->active) {
15480 /*
15481 * This has to be done during hardware readout
15482 * because anything calling .crtc_disable may
15483 * rely on the connector_mask being accurate.
15484 */
15485 encoder->base.crtc->state->connector_mask |=
15486 1 << drm_connector_index(&connector->base);
15487 encoder->base.crtc->state->encoder_mask |=
15488 1 << drm_encoder_index(&encoder->base);
15489 }
15490
15491 } else {
15492 connector->base.dpms = DRM_MODE_DPMS_OFF;
15493 connector->base.encoder = NULL;
15494 }
15495 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15496 connector->base.base.id, connector->base.name,
15497 enableddisabled(connector->base.encoder));
15498 }
15499 drm_connector_list_iter_end(&conn_iter);
15500
15501 for_each_intel_crtc(dev, crtc) {
15502 struct intel_crtc_state *crtc_state =
15503 to_intel_crtc_state(crtc->base.state);
15504 int pixclk = 0;
15505
15506 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15507 if (crtc_state->base.active) {
15508 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15509 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15510 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15511
15512 /*
15513 * The initial mode needs to be set in order to keep
15514 * the atomic core happy. It wants a valid mode if the
15515 * crtc's enabled, so we do the above call.
15516 *
15517 * But we don't set all the derived state fully, hence
15518 * set a flag to indicate that a full recalculation is
15519 * needed on the next commit.
15520 */
15521 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15522
15523 intel_crtc_compute_pixel_rate(crtc_state);
15524
15525 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15526 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15527 pixclk = crtc_state->pixel_rate;
15528 else
15529 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15530
15531 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15532 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15533 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15534
15535 drm_calc_timestamping_constants(&crtc->base,
15536 &crtc_state->base.adjusted_mode);
15537 update_scanline_offset(crtc);
15538 }
15539
15540 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15541
15542 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15543 }
15544 }
15545
15546 static void
15547 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15548 {
15549 struct intel_encoder *encoder;
15550
15551 for_each_intel_encoder(&dev_priv->drm, encoder) {
15552 u64 get_domains;
15553 enum intel_display_power_domain domain;
15554
15555 if (!encoder->get_power_domains)
15556 continue;
15557
15558 get_domains = encoder->get_power_domains(encoder);
15559 for_each_power_domain(domain, get_domains)
15560 intel_display_power_get(dev_priv, domain);
15561 }
15562 }
15563
15564 /* Scan out the current hw modeset state,
15565 * and sanitizes it to the current state
15566 */
15567 static void
15568 intel_modeset_setup_hw_state(struct drm_device *dev,
15569 struct drm_modeset_acquire_ctx *ctx)
15570 {
15571 struct drm_i915_private *dev_priv = to_i915(dev);
15572 enum pipe pipe;
15573 struct intel_crtc *crtc;
15574 struct intel_encoder *encoder;
15575 int i;
15576
15577 intel_modeset_readout_hw_state(dev);
15578
15579 /* HW state is read out, now we need to sanitize this mess. */
15580 get_encoder_power_domains(dev_priv);
15581
15582 for_each_intel_encoder(dev, encoder) {
15583 intel_sanitize_encoder(encoder);
15584 }
15585
15586 for_each_pipe(dev_priv, pipe) {
15587 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15588
15589 intel_sanitize_crtc(crtc, ctx);
15590 intel_dump_pipe_config(crtc, crtc->config,
15591 "[setup_hw_state]");
15592 }
15593
15594 intel_modeset_update_connector_atomic_state(dev);
15595
15596 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15597 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15598
15599 if (!pll->on || pll->active_mask)
15600 continue;
15601
15602 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15603
15604 pll->funcs.disable(dev_priv, pll);
15605 pll->on = false;
15606 }
15607
15608 if (IS_G4X(dev_priv)) {
15609 g4x_wm_get_hw_state(dev);
15610 g4x_wm_sanitize(dev_priv);
15611 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15612 vlv_wm_get_hw_state(dev);
15613 vlv_wm_sanitize(dev_priv);
15614 } else if (IS_GEN9(dev_priv)) {
15615 skl_wm_get_hw_state(dev);
15616 } else if (HAS_PCH_SPLIT(dev_priv)) {
15617 ilk_wm_get_hw_state(dev);
15618 }
15619
15620 for_each_intel_crtc(dev, crtc) {
15621 u64 put_domains;
15622
15623 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15624 if (WARN_ON(put_domains))
15625 modeset_put_power_domains(dev_priv, put_domains);
15626 }
15627 intel_display_set_init_power(dev_priv, false);
15628
15629 intel_power_domains_verify_state(dev_priv);
15630
15631 intel_fbc_init_pipe_state(dev_priv);
15632 }
15633
15634 void intel_display_resume(struct drm_device *dev)
15635 {
15636 struct drm_i915_private *dev_priv = to_i915(dev);
15637 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15638 struct drm_modeset_acquire_ctx ctx;
15639 int ret;
15640
15641 dev_priv->modeset_restore_state = NULL;
15642 if (state)
15643 state->acquire_ctx = &ctx;
15644
15645 drm_modeset_acquire_init(&ctx, 0);
15646
15647 while (1) {
15648 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15649 if (ret != -EDEADLK)
15650 break;
15651
15652 drm_modeset_backoff(&ctx);
15653 }
15654
15655 if (!ret)
15656 ret = __intel_display_resume(dev, state, &ctx);
15657
15658 drm_modeset_drop_locks(&ctx);
15659 drm_modeset_acquire_fini(&ctx);
15660
15661 if (ret)
15662 DRM_ERROR("Restoring old state failed with %i\n", ret);
15663 if (state)
15664 drm_atomic_state_put(state);
15665 }
15666
15667 void intel_modeset_gem_init(struct drm_device *dev)
15668 {
15669 struct drm_i915_private *dev_priv = to_i915(dev);
15670
15671 intel_init_gt_powersave(dev_priv);
15672
15673 intel_setup_overlay(dev_priv);
15674 }
15675
15676 int intel_connector_register(struct drm_connector *connector)
15677 {
15678 struct intel_connector *intel_connector = to_intel_connector(connector);
15679 int ret;
15680
15681 ret = intel_backlight_device_register(intel_connector);
15682 if (ret)
15683 goto err;
15684
15685 return 0;
15686
15687 err:
15688 return ret;
15689 }
15690
15691 void intel_connector_unregister(struct drm_connector *connector)
15692 {
15693 struct intel_connector *intel_connector = to_intel_connector(connector);
15694
15695 intel_backlight_device_unregister(intel_connector);
15696 intel_panel_destroy_backlight(connector);
15697 }
15698
15699 void intel_modeset_cleanup(struct drm_device *dev)
15700 {
15701 struct drm_i915_private *dev_priv = to_i915(dev);
15702
15703 flush_work(&dev_priv->atomic_helper.free_work);
15704 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15705
15706 intel_disable_gt_powersave(dev_priv);
15707
15708 /*
15709 * Interrupts and polling as the first thing to avoid creating havoc.
15710 * Too much stuff here (turning of connectors, ...) would
15711 * experience fancy races otherwise.
15712 */
15713 intel_irq_uninstall(dev_priv);
15714
15715 /*
15716 * Due to the hpd irq storm handling the hotplug work can re-arm the
15717 * poll handlers. Hence disable polling after hpd handling is shut down.
15718 */
15719 drm_kms_helper_poll_fini(dev);
15720
15721 intel_unregister_dsm_handler();
15722
15723 intel_fbc_global_disable(dev_priv);
15724
15725 /* flush any delayed tasks or pending work */
15726 flush_scheduled_work();
15727
15728 drm_mode_config_cleanup(dev);
15729
15730 intel_cleanup_overlay(dev_priv);
15731
15732 intel_cleanup_gt_powersave(dev_priv);
15733
15734 intel_teardown_gmbus(dev_priv);
15735 }
15736
15737 void intel_connector_attach_encoder(struct intel_connector *connector,
15738 struct intel_encoder *encoder)
15739 {
15740 connector->encoder = encoder;
15741 drm_mode_connector_attach_encoder(&connector->base,
15742 &encoder->base);
15743 }
15744
15745 /*
15746 * set vga decode state - true == enable VGA decode
15747 */
15748 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15749 {
15750 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15751 u16 gmch_ctrl;
15752
15753 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15754 DRM_ERROR("failed to read control word\n");
15755 return -EIO;
15756 }
15757
15758 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15759 return 0;
15760
15761 if (state)
15762 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15763 else
15764 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15765
15766 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15767 DRM_ERROR("failed to write control word\n");
15768 return -EIO;
15769 }
15770
15771 return 0;
15772 }
15773
15774 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15775
15776 struct intel_display_error_state {
15777
15778 u32 power_well_driver;
15779
15780 int num_transcoders;
15781
15782 struct intel_cursor_error_state {
15783 u32 control;
15784 u32 position;
15785 u32 base;
15786 u32 size;
15787 } cursor[I915_MAX_PIPES];
15788
15789 struct intel_pipe_error_state {
15790 bool power_domain_on;
15791 u32 source;
15792 u32 stat;
15793 } pipe[I915_MAX_PIPES];
15794
15795 struct intel_plane_error_state {
15796 u32 control;
15797 u32 stride;
15798 u32 size;
15799 u32 pos;
15800 u32 addr;
15801 u32 surface;
15802 u32 tile_offset;
15803 } plane[I915_MAX_PIPES];
15804
15805 struct intel_transcoder_error_state {
15806 bool power_domain_on;
15807 enum transcoder cpu_transcoder;
15808
15809 u32 conf;
15810
15811 u32 htotal;
15812 u32 hblank;
15813 u32 hsync;
15814 u32 vtotal;
15815 u32 vblank;
15816 u32 vsync;
15817 } transcoder[4];
15818 };
15819
15820 struct intel_display_error_state *
15821 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15822 {
15823 struct intel_display_error_state *error;
15824 int transcoders[] = {
15825 TRANSCODER_A,
15826 TRANSCODER_B,
15827 TRANSCODER_C,
15828 TRANSCODER_EDP,
15829 };
15830 int i;
15831
15832 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15833 return NULL;
15834
15835 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15836 if (error == NULL)
15837 return NULL;
15838
15839 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15840 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15841
15842 for_each_pipe(dev_priv, i) {
15843 error->pipe[i].power_domain_on =
15844 __intel_display_power_is_enabled(dev_priv,
15845 POWER_DOMAIN_PIPE(i));
15846 if (!error->pipe[i].power_domain_on)
15847 continue;
15848
15849 error->cursor[i].control = I915_READ(CURCNTR(i));
15850 error->cursor[i].position = I915_READ(CURPOS(i));
15851 error->cursor[i].base = I915_READ(CURBASE(i));
15852
15853 error->plane[i].control = I915_READ(DSPCNTR(i));
15854 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15855 if (INTEL_GEN(dev_priv) <= 3) {
15856 error->plane[i].size = I915_READ(DSPSIZE(i));
15857 error->plane[i].pos = I915_READ(DSPPOS(i));
15858 }
15859 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15860 error->plane[i].addr = I915_READ(DSPADDR(i));
15861 if (INTEL_GEN(dev_priv) >= 4) {
15862 error->plane[i].surface = I915_READ(DSPSURF(i));
15863 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15864 }
15865
15866 error->pipe[i].source = I915_READ(PIPESRC(i));
15867
15868 if (HAS_GMCH_DISPLAY(dev_priv))
15869 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15870 }
15871
15872 /* Note: this does not include DSI transcoders. */
15873 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15874 if (HAS_DDI(dev_priv))
15875 error->num_transcoders++; /* Account for eDP. */
15876
15877 for (i = 0; i < error->num_transcoders; i++) {
15878 enum transcoder cpu_transcoder = transcoders[i];
15879
15880 error->transcoder[i].power_domain_on =
15881 __intel_display_power_is_enabled(dev_priv,
15882 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15883 if (!error->transcoder[i].power_domain_on)
15884 continue;
15885
15886 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15887
15888 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15889 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15890 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15891 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15892 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15893 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15894 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15895 }
15896
15897 return error;
15898 }
15899
15900 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15901
15902 void
15903 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15904 struct intel_display_error_state *error)
15905 {
15906 struct drm_i915_private *dev_priv = m->i915;
15907 int i;
15908
15909 if (!error)
15910 return;
15911
15912 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15913 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15914 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15915 error->power_well_driver);
15916 for_each_pipe(dev_priv, i) {
15917 err_printf(m, "Pipe [%d]:\n", i);
15918 err_printf(m, " Power: %s\n",
15919 onoff(error->pipe[i].power_domain_on));
15920 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15921 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15922
15923 err_printf(m, "Plane [%d]:\n", i);
15924 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15925 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15926 if (INTEL_GEN(dev_priv) <= 3) {
15927 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15928 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15929 }
15930 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15931 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15932 if (INTEL_GEN(dev_priv) >= 4) {
15933 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15934 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15935 }
15936
15937 err_printf(m, "Cursor [%d]:\n", i);
15938 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15939 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15940 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15941 }
15942
15943 for (i = 0; i < error->num_transcoders; i++) {
15944 err_printf(m, "CPU transcoder: %s\n",
15945 transcoder_name(error->transcoder[i].cpu_transcoder));
15946 err_printf(m, " Power: %s\n",
15947 onoff(error->transcoder[i].power_domain_on));
15948 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15949 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15950 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15951 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15952 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15953 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15954 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15955 }
15956 }
15957
15958 #endif
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