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drm: i915: Rely on the default ->best_encoder() behavior where appropriate
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
126 static int broxton_calc_cdclk(int max_pixclk);
127
128 struct intel_limit {
129 struct {
130 int min, max;
131 } dot, vco, n, m, m1, m2, p, p1;
132
133 struct {
134 int dot_limit;
135 int p2_slow, p2_fast;
136 } p2;
137 };
138
139 /* returns HPLL frequency in kHz */
140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
141 {
142 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
143
144 /* Obtain SKU information */
145 mutex_lock(&dev_priv->sb_lock);
146 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
147 CCK_FUSE_HPLL_FREQ_MASK;
148 mutex_unlock(&dev_priv->sb_lock);
149
150 return vco_freq[hpll_freq] * 1000;
151 }
152
153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
154 const char *name, u32 reg, int ref_freq)
155 {
156 u32 val;
157 int divider;
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
170 }
171
172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
173 const char *name, u32 reg)
174 {
175 if (dev_priv->hpll_freq == 0)
176 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
177
178 return vlv_get_cck_clock(dev_priv, name, reg,
179 dev_priv->hpll_freq);
180 }
181
182 static int
183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
184 {
185 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
186 }
187
188 static int
189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
190 {
191 /* RAWCLK_FREQ_VLV register updated from power well code */
192 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
193 CCK_DISPLAY_REF_CLOCK_CONTROL);
194 }
195
196 static int
197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
198 {
199 uint32_t clkcfg;
200
201 /* hrawclock is 1/4 the FSB frequency */
202 clkcfg = I915_READ(CLKCFG);
203 switch (clkcfg & CLKCFG_FSB_MASK) {
204 case CLKCFG_FSB_400:
205 return 100000;
206 case CLKCFG_FSB_533:
207 return 133333;
208 case CLKCFG_FSB_667:
209 return 166667;
210 case CLKCFG_FSB_800:
211 return 200000;
212 case CLKCFG_FSB_1067:
213 return 266667;
214 case CLKCFG_FSB_1333:
215 return 333333;
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600:
218 case CLKCFG_FSB_1600_ALT:
219 return 400000;
220 default:
221 return 133333;
222 }
223 }
224
225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
226 {
227 if (HAS_PCH_SPLIT(dev_priv))
228 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
229 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
230 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
231 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
232 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
233 else
234 return; /* no rawclk on other platforms, or no need to know it */
235
236 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
237 }
238
239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
240 {
241 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
242 return;
243
244 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
245 CCK_CZ_CLOCK_CONTROL);
246
247 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
248 }
249
250 static inline u32 /* units of 100MHz */
251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
252 const struct intel_crtc_state *pipe_config)
253 {
254 if (HAS_DDI(dev_priv))
255 return pipe_config->port_clock; /* SPLL */
256 else if (IS_GEN5(dev_priv))
257 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
258 else
259 return 270000;
260 }
261
262 static const struct intel_limit intel_limits_i8xx_dac = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 908000, .max = 1512000 },
265 .n = { .min = 2, .max = 16 },
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 2, .max = 33 },
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 4, .p2_fast = 2 },
273 };
274
275 static const struct intel_limit intel_limits_i8xx_dvo = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 908000, .max = 1512000 },
278 .n = { .min = 2, .max = 16 },
279 .m = { .min = 96, .max = 140 },
280 .m1 = { .min = 18, .max = 26 },
281 .m2 = { .min = 6, .max = 16 },
282 .p = { .min = 4, .max = 128 },
283 .p1 = { .min = 2, .max = 33 },
284 .p2 = { .dot_limit = 165000,
285 .p2_slow = 4, .p2_fast = 4 },
286 };
287
288 static const struct intel_limit intel_limits_i8xx_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 908000, .max = 1512000 },
291 .n = { .min = 2, .max = 16 },
292 .m = { .min = 96, .max = 140 },
293 .m1 = { .min = 18, .max = 26 },
294 .m2 = { .min = 6, .max = 16 },
295 .p = { .min = 4, .max = 128 },
296 .p1 = { .min = 1, .max = 6 },
297 .p2 = { .dot_limit = 165000,
298 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301 static const struct intel_limit intel_limits_i9xx_sdvo = {
302 .dot = { .min = 20000, .max = 400000 },
303 .vco = { .min = 1400000, .max = 2800000 },
304 .n = { .min = 1, .max = 6 },
305 .m = { .min = 70, .max = 120 },
306 .m1 = { .min = 8, .max = 18 },
307 .m2 = { .min = 3, .max = 7 },
308 .p = { .min = 5, .max = 80 },
309 .p1 = { .min = 1, .max = 8 },
310 .p2 = { .dot_limit = 200000,
311 .p2_slow = 10, .p2_fast = 5 },
312 };
313
314 static const struct intel_limit intel_limits_i9xx_lvds = {
315 .dot = { .min = 20000, .max = 400000 },
316 .vco = { .min = 1400000, .max = 2800000 },
317 .n = { .min = 1, .max = 6 },
318 .m = { .min = 70, .max = 120 },
319 .m1 = { .min = 8, .max = 18 },
320 .m2 = { .min = 3, .max = 7 },
321 .p = { .min = 7, .max = 98 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 112000,
324 .p2_slow = 14, .p2_fast = 7 },
325 };
326
327
328 static const struct intel_limit intel_limits_g4x_sdvo = {
329 .dot = { .min = 25000, .max = 270000 },
330 .vco = { .min = 1750000, .max = 3500000},
331 .n = { .min = 1, .max = 4 },
332 .m = { .min = 104, .max = 138 },
333 .m1 = { .min = 17, .max = 23 },
334 .m2 = { .min = 5, .max = 11 },
335 .p = { .min = 10, .max = 30 },
336 .p1 = { .min = 1, .max = 3},
337 .p2 = { .dot_limit = 270000,
338 .p2_slow = 10,
339 .p2_fast = 10
340 },
341 };
342
343 static const struct intel_limit intel_limits_g4x_hdmi = {
344 .dot = { .min = 22000, .max = 400000 },
345 .vco = { .min = 1750000, .max = 3500000},
346 .n = { .min = 1, .max = 4 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 16, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 5, .max = 80 },
351 .p1 = { .min = 1, .max = 8},
352 .p2 = { .dot_limit = 165000,
353 .p2_slow = 10, .p2_fast = 5 },
354 };
355
356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
357 .dot = { .min = 20000, .max = 115000 },
358 .vco = { .min = 1750000, .max = 3500000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 104, .max = 138 },
361 .m1 = { .min = 17, .max = 23 },
362 .m2 = { .min = 5, .max = 11 },
363 .p = { .min = 28, .max = 112 },
364 .p1 = { .min = 2, .max = 8 },
365 .p2 = { .dot_limit = 0,
366 .p2_slow = 14, .p2_fast = 14
367 },
368 };
369
370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
371 .dot = { .min = 80000, .max = 224000 },
372 .vco = { .min = 1750000, .max = 3500000 },
373 .n = { .min = 1, .max = 3 },
374 .m = { .min = 104, .max = 138 },
375 .m1 = { .min = 17, .max = 23 },
376 .m2 = { .min = 5, .max = 11 },
377 .p = { .min = 14, .max = 42 },
378 .p1 = { .min = 2, .max = 6 },
379 .p2 = { .dot_limit = 0,
380 .p2_slow = 7, .p2_fast = 7
381 },
382 };
383
384 static const struct intel_limit intel_limits_pineview_sdvo = {
385 .dot = { .min = 20000, .max = 400000},
386 .vco = { .min = 1700000, .max = 3500000 },
387 /* Pineview's Ncounter is a ring counter */
388 .n = { .min = 3, .max = 6 },
389 .m = { .min = 2, .max = 256 },
390 /* Pineview only has one combined m divider, which we treat as m2. */
391 .m1 = { .min = 0, .max = 0 },
392 .m2 = { .min = 0, .max = 254 },
393 .p = { .min = 5, .max = 80 },
394 .p1 = { .min = 1, .max = 8 },
395 .p2 = { .dot_limit = 200000,
396 .p2_slow = 10, .p2_fast = 5 },
397 };
398
399 static const struct intel_limit intel_limits_pineview_lvds = {
400 .dot = { .min = 20000, .max = 400000 },
401 .vco = { .min = 1700000, .max = 3500000 },
402 .n = { .min = 3, .max = 6 },
403 .m = { .min = 2, .max = 256 },
404 .m1 = { .min = 0, .max = 0 },
405 .m2 = { .min = 0, .max = 254 },
406 .p = { .min = 7, .max = 112 },
407 .p1 = { .min = 1, .max = 8 },
408 .p2 = { .dot_limit = 112000,
409 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 /* Ironlake / Sandybridge
413 *
414 * We calculate clock using (register_value + 2) for N/M1/M2, so here
415 * the range value for them is (actual_value - 2).
416 */
417 static const struct intel_limit intel_limits_ironlake_dac = {
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 5 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 5, .max = 80 },
425 .p1 = { .min = 1, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 10, .p2_fast = 5 },
428 };
429
430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 3 },
434 .m = { .min = 79, .max = 118 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 127 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 56 },
451 .p1 = { .min = 2, .max = 8 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 /* LVDS 100mhz refclk limits. */
457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
458 .dot = { .min = 25000, .max = 350000 },
459 .vco = { .min = 1760000, .max = 3510000 },
460 .n = { .min = 1, .max = 2 },
461 .m = { .min = 79, .max = 126 },
462 .m1 = { .min = 12, .max = 22 },
463 .m2 = { .min = 5, .max = 9 },
464 .p = { .min = 28, .max = 112 },
465 .p1 = { .min = 2, .max = 8 },
466 .p2 = { .dot_limit = 225000,
467 .p2_slow = 14, .p2_fast = 14 },
468 };
469
470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
471 .dot = { .min = 25000, .max = 350000 },
472 .vco = { .min = 1760000, .max = 3510000 },
473 .n = { .min = 1, .max = 3 },
474 .m = { .min = 79, .max = 126 },
475 .m1 = { .min = 12, .max = 22 },
476 .m2 = { .min = 5, .max = 9 },
477 .p = { .min = 14, .max = 42 },
478 .p1 = { .min = 2, .max = 6 },
479 .p2 = { .dot_limit = 225000,
480 .p2_slow = 7, .p2_fast = 7 },
481 };
482
483 static const struct intel_limit intel_limits_vlv = {
484 /*
485 * These are the data rate limits (measured in fast clocks)
486 * since those are the strictest limits we have. The fast
487 * clock and actual rate limits are more relaxed, so checking
488 * them would make no difference.
489 */
490 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
491 .vco = { .min = 4000000, .max = 6000000 },
492 .n = { .min = 1, .max = 7 },
493 .m1 = { .min = 2, .max = 3 },
494 .m2 = { .min = 11, .max = 156 },
495 .p1 = { .min = 2, .max = 3 },
496 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
497 };
498
499 static const struct intel_limit intel_limits_chv = {
500 /*
501 * These are the data rate limits (measured in fast clocks)
502 * since those are the strictest limits we have. The fast
503 * clock and actual rate limits are more relaxed, so checking
504 * them would make no difference.
505 */
506 .dot = { .min = 25000 * 5, .max = 540000 * 5},
507 .vco = { .min = 4800000, .max = 6480000 },
508 .n = { .min = 1, .max = 1 },
509 .m1 = { .min = 2, .max = 2 },
510 .m2 = { .min = 24 << 22, .max = 175 << 22 },
511 .p1 = { .min = 2, .max = 4 },
512 .p2 = { .p2_slow = 1, .p2_fast = 14 },
513 };
514
515 static const struct intel_limit intel_limits_bxt = {
516 /* FIXME: find real dot limits */
517 .dot = { .min = 0, .max = INT_MAX },
518 .vco = { .min = 4800000, .max = 6700000 },
519 .n = { .min = 1, .max = 1 },
520 .m1 = { .min = 2, .max = 2 },
521 /* FIXME: find real m2 limits */
522 .m2 = { .min = 2 << 22, .max = 255 << 22 },
523 .p1 = { .min = 2, .max = 4 },
524 .p2 = { .p2_slow = 1, .p2_fast = 20 },
525 };
526
527 static bool
528 needs_modeset(struct drm_crtc_state *state)
529 {
530 return drm_atomic_crtc_needs_modeset(state);
531 }
532
533 /**
534 * Returns whether any output on the specified pipe is of the specified type
535 */
536 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
537 {
538 struct drm_device *dev = crtc->base.dev;
539 struct intel_encoder *encoder;
540
541 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
542 if (encoder->type == type)
543 return true;
544
545 return false;
546 }
547
548 /**
549 * Returns whether any output on the specified pipe will have the specified
550 * type after a staged modeset is complete, i.e., the same as
551 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
552 * encoder->crtc.
553 */
554 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
555 int type)
556 {
557 struct drm_atomic_state *state = crtc_state->base.state;
558 struct drm_connector *connector;
559 struct drm_connector_state *connector_state;
560 struct intel_encoder *encoder;
561 int i, num_connectors = 0;
562
563 for_each_connector_in_state(state, connector, connector_state, i) {
564 if (connector_state->crtc != crtc_state->base.crtc)
565 continue;
566
567 num_connectors++;
568
569 encoder = to_intel_encoder(connector_state->best_encoder);
570 if (encoder->type == type)
571 return true;
572 }
573
574 WARN_ON(num_connectors == 0);
575
576 return false;
577 }
578
579 /*
580 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
581 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
582 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
583 * The helpers' return value is the rate of the clock that is fed to the
584 * display engine's pipe which can be the above fast dot clock rate or a
585 * divided-down version of it.
586 */
587 /* m1 is reserved as 0 in Pineview, n is a ring counter */
588 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
589 {
590 clock->m = clock->m2 + 2;
591 clock->p = clock->p1 * clock->p2;
592 if (WARN_ON(clock->n == 0 || clock->p == 0))
593 return 0;
594 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
595 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
596
597 return clock->dot;
598 }
599
600 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
601 {
602 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
603 }
604
605 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
606 {
607 clock->m = i9xx_dpll_compute_m(clock);
608 clock->p = clock->p1 * clock->p2;
609 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
610 return 0;
611 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
612 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
613
614 return clock->dot;
615 }
616
617 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
618 {
619 clock->m = clock->m1 * clock->m2;
620 clock->p = clock->p1 * clock->p2;
621 if (WARN_ON(clock->n == 0 || clock->p == 0))
622 return 0;
623 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
624 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
625
626 return clock->dot / 5;
627 }
628
629 int chv_calc_dpll_params(int refclk, struct dpll *clock)
630 {
631 clock->m = clock->m1 * clock->m2;
632 clock->p = clock->p1 * clock->p2;
633 if (WARN_ON(clock->n == 0 || clock->p == 0))
634 return 0;
635 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
636 clock->n << 22);
637 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
638
639 return clock->dot / 5;
640 }
641
642 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
643 /**
644 * Returns whether the given set of divisors are valid for a given refclk with
645 * the given connectors.
646 */
647
648 static bool intel_PLL_is_valid(struct drm_device *dev,
649 const struct intel_limit *limit,
650 const struct dpll *clock)
651 {
652 if (clock->n < limit->n.min || limit->n.max < clock->n)
653 INTELPllInvalid("n out of range\n");
654 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
655 INTELPllInvalid("p1 out of range\n");
656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
657 INTELPllInvalid("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid("m1 out of range\n");
660
661 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
662 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
663 if (clock->m1 <= clock->m2)
664 INTELPllInvalid("m1 <= m2\n");
665
666 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
667 if (clock->p < limit->p.min || limit->p.max < clock->p)
668 INTELPllInvalid("p out of range\n");
669 if (clock->m < limit->m.min || limit->m.max < clock->m)
670 INTELPllInvalid("m out of range\n");
671 }
672
673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
679 INTELPllInvalid("dot out of range\n");
680
681 return true;
682 }
683
684 static int
685 i9xx_select_p2_div(const struct intel_limit *limit,
686 const struct intel_crtc_state *crtc_state,
687 int target)
688 {
689 struct drm_device *dev = crtc_state->base.crtc->dev;
690
691 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
692 /*
693 * For LVDS just rely on its current settings for dual-channel.
694 * We haven't figured out how to reliably set up different
695 * single/dual channel state, if we even can.
696 */
697 if (intel_is_dual_link_lvds(dev))
698 return limit->p2.p2_fast;
699 else
700 return limit->p2.p2_slow;
701 } else {
702 if (target < limit->p2.dot_limit)
703 return limit->p2.p2_slow;
704 else
705 return limit->p2.p2_fast;
706 }
707 }
708
709 /*
710 * Returns a set of divisors for the desired target clock with the given
711 * refclk, or FALSE. The returned values represent the clock equation:
712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
713 *
714 * Target and reference clocks are specified in kHz.
715 *
716 * If match_clock is provided, then best_clock P divider must match the P
717 * divider from @match_clock used for LVDS downclocking.
718 */
719 static bool
720 i9xx_find_best_dpll(const struct intel_limit *limit,
721 struct intel_crtc_state *crtc_state,
722 int target, int refclk, struct dpll *match_clock,
723 struct dpll *best_clock)
724 {
725 struct drm_device *dev = crtc_state->base.crtc->dev;
726 struct dpll clock;
727 int err = target;
728
729 memset(best_clock, 0, sizeof(*best_clock));
730
731 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
732
733 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
734 clock.m1++) {
735 for (clock.m2 = limit->m2.min;
736 clock.m2 <= limit->m2.max; clock.m2++) {
737 if (clock.m2 >= clock.m1)
738 break;
739 for (clock.n = limit->n.min;
740 clock.n <= limit->n.max; clock.n++) {
741 for (clock.p1 = limit->p1.min;
742 clock.p1 <= limit->p1.max; clock.p1++) {
743 int this_err;
744
745 i9xx_calc_dpll_params(refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err) {
755 *best_clock = clock;
756 err = this_err;
757 }
758 }
759 }
760 }
761 }
762
763 return (err != target);
764 }
765
766 /*
767 * Returns a set of divisors for the desired target clock with the given
768 * refclk, or FALSE. The returned values represent the clock equation:
769 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
770 *
771 * Target and reference clocks are specified in kHz.
772 *
773 * If match_clock is provided, then best_clock P divider must match the P
774 * divider from @match_clock used for LVDS downclocking.
775 */
776 static bool
777 pnv_find_best_dpll(const struct intel_limit *limit,
778 struct intel_crtc_state *crtc_state,
779 int target, int refclk, struct dpll *match_clock,
780 struct dpll *best_clock)
781 {
782 struct drm_device *dev = crtc_state->base.crtc->dev;
783 struct dpll clock;
784 int err = target;
785
786 memset(best_clock, 0, sizeof(*best_clock));
787
788 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
789
790 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
791 clock.m1++) {
792 for (clock.m2 = limit->m2.min;
793 clock.m2 <= limit->m2.max; clock.m2++) {
794 for (clock.n = limit->n.min;
795 clock.n <= limit->n.max; clock.n++) {
796 for (clock.p1 = limit->p1.min;
797 clock.p1 <= limit->p1.max; clock.p1++) {
798 int this_err;
799
800 pnv_calc_dpll_params(refclk, &clock);
801 if (!intel_PLL_is_valid(dev, limit,
802 &clock))
803 continue;
804 if (match_clock &&
805 clock.p != match_clock->p)
806 continue;
807
808 this_err = abs(clock.dot - target);
809 if (this_err < err) {
810 *best_clock = clock;
811 err = this_err;
812 }
813 }
814 }
815 }
816 }
817
818 return (err != target);
819 }
820
821 /*
822 * Returns a set of divisors for the desired target clock with the given
823 * refclk, or FALSE. The returned values represent the clock equation:
824 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
825 *
826 * Target and reference clocks are specified in kHz.
827 *
828 * If match_clock is provided, then best_clock P divider must match the P
829 * divider from @match_clock used for LVDS downclocking.
830 */
831 static bool
832 g4x_find_best_dpll(const struct intel_limit *limit,
833 struct intel_crtc_state *crtc_state,
834 int target, int refclk, struct dpll *match_clock,
835 struct dpll *best_clock)
836 {
837 struct drm_device *dev = crtc_state->base.crtc->dev;
838 struct dpll clock;
839 int max_n;
840 bool found = false;
841 /* approximately equals target * 0.00585 */
842 int err_most = (target >> 8) + (target >> 9);
843
844 memset(best_clock, 0, sizeof(*best_clock));
845
846 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
847
848 max_n = limit->n.max;
849 /* based on hardware requirement, prefer smaller n to precision */
850 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
851 /* based on hardware requirement, prefere larger m1,m2 */
852 for (clock.m1 = limit->m1.max;
853 clock.m1 >= limit->m1.min; clock.m1--) {
854 for (clock.m2 = limit->m2.max;
855 clock.m2 >= limit->m2.min; clock.m2--) {
856 for (clock.p1 = limit->p1.max;
857 clock.p1 >= limit->p1.min; clock.p1--) {
858 int this_err;
859
860 i9xx_calc_dpll_params(refclk, &clock);
861 if (!intel_PLL_is_valid(dev, limit,
862 &clock))
863 continue;
864
865 this_err = abs(clock.dot - target);
866 if (this_err < err_most) {
867 *best_clock = clock;
868 err_most = this_err;
869 max_n = clock.n;
870 found = true;
871 }
872 }
873 }
874 }
875 }
876 return found;
877 }
878
879 /*
880 * Check if the calculated PLL configuration is more optimal compared to the
881 * best configuration and error found so far. Return the calculated error.
882 */
883 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
884 const struct dpll *calculated_clock,
885 const struct dpll *best_clock,
886 unsigned int best_error_ppm,
887 unsigned int *error_ppm)
888 {
889 /*
890 * For CHV ignore the error and consider only the P value.
891 * Prefer a bigger P value based on HW requirements.
892 */
893 if (IS_CHERRYVIEW(dev)) {
894 *error_ppm = 0;
895
896 return calculated_clock->p > best_clock->p;
897 }
898
899 if (WARN_ON_ONCE(!target_freq))
900 return false;
901
902 *error_ppm = div_u64(1000000ULL *
903 abs(target_freq - calculated_clock->dot),
904 target_freq);
905 /*
906 * Prefer a better P value over a better (smaller) error if the error
907 * is small. Ensure this preference for future configurations too by
908 * setting the error to 0.
909 */
910 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
911 *error_ppm = 0;
912
913 return true;
914 }
915
916 return *error_ppm + 10 < best_error_ppm;
917 }
918
919 /*
920 * Returns a set of divisors for the desired target clock with the given
921 * refclk, or FALSE. The returned values represent the clock equation:
922 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
923 */
924 static bool
925 vlv_find_best_dpll(const struct intel_limit *limit,
926 struct intel_crtc_state *crtc_state,
927 int target, int refclk, struct dpll *match_clock,
928 struct dpll *best_clock)
929 {
930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
931 struct drm_device *dev = crtc->base.dev;
932 struct dpll clock;
933 unsigned int bestppm = 1000000;
934 /* min update 19.2 MHz */
935 int max_n = min(limit->n.max, refclk / 19200);
936 bool found = false;
937
938 target *= 5; /* fast clock */
939
940 memset(best_clock, 0, sizeof(*best_clock));
941
942 /* based on hardware requirement, prefer smaller n to precision */
943 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
944 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
945 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
947 clock.p = clock.p1 * clock.p2;
948 /* based on hardware requirement, prefer bigger m1,m2 values */
949 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
950 unsigned int ppm;
951
952 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
953 refclk * clock.m1);
954
955 vlv_calc_dpll_params(refclk, &clock);
956
957 if (!intel_PLL_is_valid(dev, limit,
958 &clock))
959 continue;
960
961 if (!vlv_PLL_is_optimal(dev, target,
962 &clock,
963 best_clock,
964 bestppm, &ppm))
965 continue;
966
967 *best_clock = clock;
968 bestppm = ppm;
969 found = true;
970 }
971 }
972 }
973 }
974
975 return found;
976 }
977
978 /*
979 * Returns a set of divisors for the desired target clock with the given
980 * refclk, or FALSE. The returned values represent the clock equation:
981 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
982 */
983 static bool
984 chv_find_best_dpll(const struct intel_limit *limit,
985 struct intel_crtc_state *crtc_state,
986 int target, int refclk, struct dpll *match_clock,
987 struct dpll *best_clock)
988 {
989 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
990 struct drm_device *dev = crtc->base.dev;
991 unsigned int best_error_ppm;
992 struct dpll clock;
993 uint64_t m2;
994 int found = false;
995
996 memset(best_clock, 0, sizeof(*best_clock));
997 best_error_ppm = 1000000;
998
999 /*
1000 * Based on hardware doc, the n always set to 1, and m1 always
1001 * set to 2. If requires to support 200Mhz refclk, we need to
1002 * revisit this because n may not 1 anymore.
1003 */
1004 clock.n = 1, clock.m1 = 2;
1005 target *= 5; /* fast clock */
1006
1007 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1008 for (clock.p2 = limit->p2.p2_fast;
1009 clock.p2 >= limit->p2.p2_slow;
1010 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1011 unsigned int error_ppm;
1012
1013 clock.p = clock.p1 * clock.p2;
1014
1015 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1016 clock.n) << 22, refclk * clock.m1);
1017
1018 if (m2 > INT_MAX/clock.m1)
1019 continue;
1020
1021 clock.m2 = m2;
1022
1023 chv_calc_dpll_params(refclk, &clock);
1024
1025 if (!intel_PLL_is_valid(dev, limit, &clock))
1026 continue;
1027
1028 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1029 best_error_ppm, &error_ppm))
1030 continue;
1031
1032 *best_clock = clock;
1033 best_error_ppm = error_ppm;
1034 found = true;
1035 }
1036 }
1037
1038 return found;
1039 }
1040
1041 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1042 struct dpll *best_clock)
1043 {
1044 int refclk = 100000;
1045 const struct intel_limit *limit = &intel_limits_bxt;
1046
1047 return chv_find_best_dpll(limit, crtc_state,
1048 target_clock, refclk, NULL, best_clock);
1049 }
1050
1051 bool intel_crtc_active(struct drm_crtc *crtc)
1052 {
1053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1054
1055 /* Be paranoid as we can arrive here with only partial
1056 * state retrieved from the hardware during setup.
1057 *
1058 * We can ditch the adjusted_mode.crtc_clock check as soon
1059 * as Haswell has gained clock readout/fastboot support.
1060 *
1061 * We can ditch the crtc->primary->fb check as soon as we can
1062 * properly reconstruct framebuffers.
1063 *
1064 * FIXME: The intel_crtc->active here should be switched to
1065 * crtc->state->active once we have proper CRTC states wired up
1066 * for atomic.
1067 */
1068 return intel_crtc->active && crtc->primary->state->fb &&
1069 intel_crtc->config->base.adjusted_mode.crtc_clock;
1070 }
1071
1072 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1073 enum pipe pipe)
1074 {
1075 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1077
1078 return intel_crtc->config->cpu_transcoder;
1079 }
1080
1081 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1082 {
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 i915_reg_t reg = PIPEDSL(pipe);
1085 u32 line1, line2;
1086 u32 line_mask;
1087
1088 if (IS_GEN2(dev))
1089 line_mask = DSL_LINEMASK_GEN2;
1090 else
1091 line_mask = DSL_LINEMASK_GEN3;
1092
1093 line1 = I915_READ(reg) & line_mask;
1094 msleep(5);
1095 line2 = I915_READ(reg) & line_mask;
1096
1097 return line1 == line2;
1098 }
1099
1100 /*
1101 * intel_wait_for_pipe_off - wait for pipe to turn off
1102 * @crtc: crtc whose pipe to wait for
1103 *
1104 * After disabling a pipe, we can't wait for vblank in the usual way,
1105 * spinning on the vblank interrupt status bit, since we won't actually
1106 * see an interrupt when the pipe is disabled.
1107 *
1108 * On Gen4 and above:
1109 * wait for the pipe register state bit to turn off
1110 *
1111 * Otherwise:
1112 * wait for the display line value to settle (it usually
1113 * ends up stopping at the start of the next frame).
1114 *
1115 */
1116 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1117 {
1118 struct drm_device *dev = crtc->base.dev;
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1121 enum pipe pipe = crtc->pipe;
1122
1123 if (INTEL_INFO(dev)->gen >= 4) {
1124 i915_reg_t reg = PIPECONF(cpu_transcoder);
1125
1126 /* Wait for the Pipe State to go off */
1127 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1128 100))
1129 WARN(1, "pipe_off wait timed out\n");
1130 } else {
1131 /* Wait for the display line to settle */
1132 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1133 WARN(1, "pipe_off wait timed out\n");
1134 }
1135 }
1136
1137 /* Only for pre-ILK configs */
1138 void assert_pll(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, bool state)
1140 {
1141 u32 val;
1142 bool cur_state;
1143
1144 val = I915_READ(DPLL(pipe));
1145 cur_state = !!(val & DPLL_VCO_ENABLE);
1146 I915_STATE_WARN(cur_state != state,
1147 "PLL state assertion failure (expected %s, current %s)\n",
1148 onoff(state), onoff(cur_state));
1149 }
1150
1151 /* XXX: the dsi pll is shared between MIPI DSI ports */
1152 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1153 {
1154 u32 val;
1155 bool cur_state;
1156
1157 mutex_lock(&dev_priv->sb_lock);
1158 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1159 mutex_unlock(&dev_priv->sb_lock);
1160
1161 cur_state = val & DSI_PLL_VCO_EN;
1162 I915_STATE_WARN(cur_state != state,
1163 "DSI PLL state assertion failure (expected %s, current %s)\n",
1164 onoff(state), onoff(cur_state));
1165 }
1166
1167 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1168 enum pipe pipe, bool state)
1169 {
1170 bool cur_state;
1171 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1172 pipe);
1173
1174 if (HAS_DDI(dev_priv)) {
1175 /* DDI does not have a specific FDI_TX register */
1176 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1177 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1178 } else {
1179 u32 val = I915_READ(FDI_TX_CTL(pipe));
1180 cur_state = !!(val & FDI_TX_ENABLE);
1181 }
1182 I915_STATE_WARN(cur_state != state,
1183 "FDI TX state assertion failure (expected %s, current %s)\n",
1184 onoff(state), onoff(cur_state));
1185 }
1186 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1187 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1188
1189 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191 {
1192 u32 val;
1193 bool cur_state;
1194
1195 val = I915_READ(FDI_RX_CTL(pipe));
1196 cur_state = !!(val & FDI_RX_ENABLE);
1197 I915_STATE_WARN(cur_state != state,
1198 "FDI RX state assertion failure (expected %s, current %s)\n",
1199 onoff(state), onoff(cur_state));
1200 }
1201 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1202 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1203
1204 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe)
1206 {
1207 u32 val;
1208
1209 /* ILK FDI PLL is always enabled */
1210 if (IS_GEN5(dev_priv))
1211 return;
1212
1213 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1214 if (HAS_DDI(dev_priv))
1215 return;
1216
1217 val = I915_READ(FDI_TX_CTL(pipe));
1218 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1219 }
1220
1221 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1223 {
1224 u32 val;
1225 bool cur_state;
1226
1227 val = I915_READ(FDI_RX_CTL(pipe));
1228 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1229 I915_STATE_WARN(cur_state != state,
1230 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1231 onoff(state), onoff(cur_state));
1232 }
1233
1234 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1235 enum pipe pipe)
1236 {
1237 struct drm_device *dev = dev_priv->dev;
1238 i915_reg_t pp_reg;
1239 u32 val;
1240 enum pipe panel_pipe = PIPE_A;
1241 bool locked = true;
1242
1243 if (WARN_ON(HAS_DDI(dev)))
1244 return;
1245
1246 if (HAS_PCH_SPLIT(dev)) {
1247 u32 port_sel;
1248
1249 pp_reg = PCH_PP_CONTROL;
1250 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1251
1252 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1253 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1254 panel_pipe = PIPE_B;
1255 /* XXX: else fix for eDP */
1256 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1257 /* presumably write lock depends on pipe, not port select */
1258 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1259 panel_pipe = pipe;
1260 } else {
1261 pp_reg = PP_CONTROL;
1262 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1263 panel_pipe = PIPE_B;
1264 }
1265
1266 val = I915_READ(pp_reg);
1267 if (!(val & PANEL_POWER_ON) ||
1268 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1269 locked = false;
1270
1271 I915_STATE_WARN(panel_pipe == pipe && locked,
1272 "panel assertion failure, pipe %c regs locked\n",
1273 pipe_name(pipe));
1274 }
1275
1276 static void assert_cursor(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, bool state)
1278 {
1279 struct drm_device *dev = dev_priv->dev;
1280 bool cur_state;
1281
1282 if (IS_845G(dev) || IS_I865G(dev))
1283 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1284 else
1285 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1286
1287 I915_STATE_WARN(cur_state != state,
1288 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1289 pipe_name(pipe), onoff(state), onoff(cur_state));
1290 }
1291 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1292 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1293
1294 void assert_pipe(struct drm_i915_private *dev_priv,
1295 enum pipe pipe, bool state)
1296 {
1297 bool cur_state;
1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299 pipe);
1300 enum intel_display_power_domain power_domain;
1301
1302 /* if we need the pipe quirk it must be always on */
1303 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1304 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1305 state = true;
1306
1307 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1308 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1309 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1310 cur_state = !!(val & PIPECONF_ENABLE);
1311
1312 intel_display_power_put(dev_priv, power_domain);
1313 } else {
1314 cur_state = false;
1315 }
1316
1317 I915_STATE_WARN(cur_state != state,
1318 "pipe %c assertion failure (expected %s, current %s)\n",
1319 pipe_name(pipe), onoff(state), onoff(cur_state));
1320 }
1321
1322 static void assert_plane(struct drm_i915_private *dev_priv,
1323 enum plane plane, bool state)
1324 {
1325 u32 val;
1326 bool cur_state;
1327
1328 val = I915_READ(DSPCNTR(plane));
1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1330 I915_STATE_WARN(cur_state != state,
1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane), onoff(state), onoff(cur_state));
1333 }
1334
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337
1338 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe)
1340 {
1341 struct drm_device *dev = dev_priv->dev;
1342 int i;
1343
1344 /* Primary planes are fixed to pipes on gen4+ */
1345 if (INTEL_INFO(dev)->gen >= 4) {
1346 u32 val = I915_READ(DSPCNTR(pipe));
1347 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1348 "plane %c assertion failure, should be disabled but not\n",
1349 plane_name(pipe));
1350 return;
1351 }
1352
1353 /* Need to check both planes against the pipe */
1354 for_each_pipe(dev_priv, i) {
1355 u32 val = I915_READ(DSPCNTR(i));
1356 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1357 DISPPLANE_SEL_PIPE_SHIFT;
1358 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1359 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1360 plane_name(i), pipe_name(pipe));
1361 }
1362 }
1363
1364 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366 {
1367 struct drm_device *dev = dev_priv->dev;
1368 int sprite;
1369
1370 if (INTEL_INFO(dev)->gen >= 9) {
1371 for_each_sprite(dev_priv, pipe, sprite) {
1372 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1373 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1374 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1375 sprite, pipe_name(pipe));
1376 }
1377 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1378 for_each_sprite(dev_priv, pipe, sprite) {
1379 u32 val = I915_READ(SPCNTR(pipe, sprite));
1380 I915_STATE_WARN(val & SP_ENABLE,
1381 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1382 sprite_name(pipe, sprite), pipe_name(pipe));
1383 }
1384 } else if (INTEL_INFO(dev)->gen >= 7) {
1385 u32 val = I915_READ(SPRCTL(pipe));
1386 I915_STATE_WARN(val & SPRITE_ENABLE,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 plane_name(pipe), pipe_name(pipe));
1389 } else if (INTEL_INFO(dev)->gen >= 5) {
1390 u32 val = I915_READ(DVSCNTR(pipe));
1391 I915_STATE_WARN(val & DVS_ENABLE,
1392 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(pipe), pipe_name(pipe));
1394 }
1395 }
1396
1397 static void assert_vblank_disabled(struct drm_crtc *crtc)
1398 {
1399 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1400 drm_crtc_vblank_put(crtc);
1401 }
1402
1403 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe)
1405 {
1406 u32 val;
1407 bool enabled;
1408
1409 val = I915_READ(PCH_TRANSCONF(pipe));
1410 enabled = !!(val & TRANS_ENABLE);
1411 I915_STATE_WARN(enabled,
1412 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1413 pipe_name(pipe));
1414 }
1415
1416 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, u32 port_sel, u32 val)
1418 {
1419 if ((val & DP_PORT_EN) == 0)
1420 return false;
1421
1422 if (HAS_PCH_CPT(dev_priv)) {
1423 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1424 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1425 return false;
1426 } else if (IS_CHERRYVIEW(dev_priv)) {
1427 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1428 return false;
1429 } else {
1430 if ((val & DP_PIPE_MASK) != (pipe << 30))
1431 return false;
1432 }
1433 return true;
1434 }
1435
1436 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, u32 val)
1438 {
1439 if ((val & SDVO_ENABLE) == 0)
1440 return false;
1441
1442 if (HAS_PCH_CPT(dev_priv)) {
1443 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1444 return false;
1445 } else if (IS_CHERRYVIEW(dev_priv)) {
1446 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1447 return false;
1448 } else {
1449 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1450 return false;
1451 }
1452 return true;
1453 }
1454
1455 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1456 enum pipe pipe, u32 val)
1457 {
1458 if ((val & LVDS_PORT_EN) == 0)
1459 return false;
1460
1461 if (HAS_PCH_CPT(dev_priv)) {
1462 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1463 return false;
1464 } else {
1465 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1466 return false;
1467 }
1468 return true;
1469 }
1470
1471 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1472 enum pipe pipe, u32 val)
1473 {
1474 if ((val & ADPA_DAC_ENABLE) == 0)
1475 return false;
1476 if (HAS_PCH_CPT(dev_priv)) {
1477 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1478 return false;
1479 } else {
1480 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1481 return false;
1482 }
1483 return true;
1484 }
1485
1486 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1487 enum pipe pipe, i915_reg_t reg,
1488 u32 port_sel)
1489 {
1490 u32 val = I915_READ(reg);
1491 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1492 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1493 i915_mmio_reg_offset(reg), pipe_name(pipe));
1494
1495 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1496 && (val & DP_PIPEB_SELECT),
1497 "IBX PCH dp port still using transcoder B\n");
1498 }
1499
1500 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1501 enum pipe pipe, i915_reg_t reg)
1502 {
1503 u32 val = I915_READ(reg);
1504 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1505 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1506 i915_mmio_reg_offset(reg), pipe_name(pipe));
1507
1508 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1509 && (val & SDVO_PIPE_B_SELECT),
1510 "IBX PCH hdmi port still using transcoder B\n");
1511 }
1512
1513 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe)
1515 {
1516 u32 val;
1517
1518 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1519 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1520 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1521
1522 val = I915_READ(PCH_ADPA);
1523 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1524 "PCH VGA enabled on transcoder %c, should be disabled\n",
1525 pipe_name(pipe));
1526
1527 val = I915_READ(PCH_LVDS);
1528 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1529 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1530 pipe_name(pipe));
1531
1532 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1533 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1534 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1535 }
1536
1537 static void _vlv_enable_pll(struct intel_crtc *crtc,
1538 const struct intel_crtc_state *pipe_config)
1539 {
1540 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1541 enum pipe pipe = crtc->pipe;
1542
1543 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1544 POSTING_READ(DPLL(pipe));
1545 udelay(150);
1546
1547 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1548 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1549 }
1550
1551 static void vlv_enable_pll(struct intel_crtc *crtc,
1552 const struct intel_crtc_state *pipe_config)
1553 {
1554 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1555 enum pipe pipe = crtc->pipe;
1556
1557 assert_pipe_disabled(dev_priv, pipe);
1558
1559 /* PLL is protected by panel, make sure we can write it */
1560 assert_panel_unlocked(dev_priv, pipe);
1561
1562 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1563 _vlv_enable_pll(crtc, pipe_config);
1564
1565 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1566 POSTING_READ(DPLL_MD(pipe));
1567 }
1568
1569
1570 static void _chv_enable_pll(struct intel_crtc *crtc,
1571 const struct intel_crtc_state *pipe_config)
1572 {
1573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574 enum pipe pipe = crtc->pipe;
1575 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1576 u32 tmp;
1577
1578 mutex_lock(&dev_priv->sb_lock);
1579
1580 /* Enable back the 10bit clock to display controller */
1581 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1582 tmp |= DPIO_DCLKP_EN;
1583 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1584
1585 mutex_unlock(&dev_priv->sb_lock);
1586
1587 /*
1588 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1589 */
1590 udelay(1);
1591
1592 /* Enable PLL */
1593 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1594
1595 /* Check PLL is locked */
1596 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1597 DRM_ERROR("PLL %d failed to lock\n", pipe);
1598 }
1599
1600 static void chv_enable_pll(struct intel_crtc *crtc,
1601 const struct intel_crtc_state *pipe_config)
1602 {
1603 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1604 enum pipe pipe = crtc->pipe;
1605
1606 assert_pipe_disabled(dev_priv, pipe);
1607
1608 /* PLL is protected by panel, make sure we can write it */
1609 assert_panel_unlocked(dev_priv, pipe);
1610
1611 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1612 _chv_enable_pll(crtc, pipe_config);
1613
1614 if (pipe != PIPE_A) {
1615 /*
1616 * WaPixelRepeatModeFixForC0:chv
1617 *
1618 * DPLLCMD is AWOL. Use chicken bits to propagate
1619 * the value from DPLLBMD to either pipe B or C.
1620 */
1621 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1622 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1623 I915_WRITE(CBR4_VLV, 0);
1624 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1625
1626 /*
1627 * DPLLB VGA mode also seems to cause problems.
1628 * We should always have it disabled.
1629 */
1630 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1631 } else {
1632 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(pipe));
1634 }
1635 }
1636
1637 static int intel_num_dvo_pipes(struct drm_device *dev)
1638 {
1639 struct intel_crtc *crtc;
1640 int count = 0;
1641
1642 for_each_intel_crtc(dev, crtc)
1643 count += crtc->base.state->active &&
1644 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1645
1646 return count;
1647 }
1648
1649 static void i9xx_enable_pll(struct intel_crtc *crtc)
1650 {
1651 struct drm_device *dev = crtc->base.dev;
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 i915_reg_t reg = DPLL(crtc->pipe);
1654 u32 dpll = crtc->config->dpll_hw_state.dpll;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 /* PLL is protected by panel, make sure we can write it */
1659 if (IS_MOBILE(dev) && !IS_I830(dev))
1660 assert_panel_unlocked(dev_priv, crtc->pipe);
1661
1662 /* Enable DVO 2x clock on both PLLs if necessary */
1663 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1664 /*
1665 * It appears to be important that we don't enable this
1666 * for the current pipe before otherwise configuring the
1667 * PLL. No idea how this should be handled if multiple
1668 * DVO outputs are enabled simultaneosly.
1669 */
1670 dpll |= DPLL_DVO_2X_MODE;
1671 I915_WRITE(DPLL(!crtc->pipe),
1672 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1673 }
1674
1675 /*
1676 * Apparently we need to have VGA mode enabled prior to changing
1677 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1678 * dividers, even though the register value does change.
1679 */
1680 I915_WRITE(reg, 0);
1681
1682 I915_WRITE(reg, dpll);
1683
1684 /* Wait for the clocks to stabilize. */
1685 POSTING_READ(reg);
1686 udelay(150);
1687
1688 if (INTEL_INFO(dev)->gen >= 4) {
1689 I915_WRITE(DPLL_MD(crtc->pipe),
1690 crtc->config->dpll_hw_state.dpll_md);
1691 } else {
1692 /* The pixel multiplier can only be updated once the
1693 * DPLL is enabled and the clocks are stable.
1694 *
1695 * So write it again.
1696 */
1697 I915_WRITE(reg, dpll);
1698 }
1699
1700 /* We do this three times for luck */
1701 I915_WRITE(reg, dpll);
1702 POSTING_READ(reg);
1703 udelay(150); /* wait for warmup */
1704 I915_WRITE(reg, dpll);
1705 POSTING_READ(reg);
1706 udelay(150); /* wait for warmup */
1707 I915_WRITE(reg, dpll);
1708 POSTING_READ(reg);
1709 udelay(150); /* wait for warmup */
1710 }
1711
1712 /**
1713 * i9xx_disable_pll - disable a PLL
1714 * @dev_priv: i915 private structure
1715 * @pipe: pipe PLL to disable
1716 *
1717 * Disable the PLL for @pipe, making sure the pipe is off first.
1718 *
1719 * Note! This is for pre-ILK only.
1720 */
1721 static void i9xx_disable_pll(struct intel_crtc *crtc)
1722 {
1723 struct drm_device *dev = crtc->base.dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 enum pipe pipe = crtc->pipe;
1726
1727 /* Disable DVO 2x clock on both PLLs if necessary */
1728 if (IS_I830(dev) &&
1729 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1730 !intel_num_dvo_pipes(dev)) {
1731 I915_WRITE(DPLL(PIPE_B),
1732 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1733 I915_WRITE(DPLL(PIPE_A),
1734 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1735 }
1736
1737 /* Don't disable pipe or pipe PLLs if needed */
1738 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1739 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1740 return;
1741
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv, pipe);
1744
1745 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1746 POSTING_READ(DPLL(pipe));
1747 }
1748
1749 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1750 {
1751 u32 val;
1752
1753 /* Make sure the pipe isn't still relying on us */
1754 assert_pipe_disabled(dev_priv, pipe);
1755
1756 val = DPLL_INTEGRATED_REF_CLK_VLV |
1757 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1758 if (pipe != PIPE_A)
1759 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1760
1761 I915_WRITE(DPLL(pipe), val);
1762 POSTING_READ(DPLL(pipe));
1763 }
1764
1765 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1766 {
1767 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1768 u32 val;
1769
1770 /* Make sure the pipe isn't still relying on us */
1771 assert_pipe_disabled(dev_priv, pipe);
1772
1773 val = DPLL_SSC_REF_CLK_CHV |
1774 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1775 if (pipe != PIPE_A)
1776 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1777
1778 I915_WRITE(DPLL(pipe), val);
1779 POSTING_READ(DPLL(pipe));
1780
1781 mutex_lock(&dev_priv->sb_lock);
1782
1783 /* Disable 10bit clock to display controller */
1784 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1785 val &= ~DPIO_DCLKP_EN;
1786 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1787
1788 mutex_unlock(&dev_priv->sb_lock);
1789 }
1790
1791 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1792 struct intel_digital_port *dport,
1793 unsigned int expected_mask)
1794 {
1795 u32 port_mask;
1796 i915_reg_t dpll_reg;
1797
1798 switch (dport->port) {
1799 case PORT_B:
1800 port_mask = DPLL_PORTB_READY_MASK;
1801 dpll_reg = DPLL(0);
1802 break;
1803 case PORT_C:
1804 port_mask = DPLL_PORTC_READY_MASK;
1805 dpll_reg = DPLL(0);
1806 expected_mask <<= 4;
1807 break;
1808 case PORT_D:
1809 port_mask = DPLL_PORTD_READY_MASK;
1810 dpll_reg = DPIO_PHY_STATUS;
1811 break;
1812 default:
1813 BUG();
1814 }
1815
1816 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1817 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1818 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1819 }
1820
1821 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1822 enum pipe pipe)
1823 {
1824 struct drm_device *dev = dev_priv->dev;
1825 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1827 i915_reg_t reg;
1828 uint32_t val, pipeconf_val;
1829
1830 /* Make sure PCH DPLL is enabled */
1831 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1832
1833 /* FDI must be feeding us bits for PCH ports */
1834 assert_fdi_tx_enabled(dev_priv, pipe);
1835 assert_fdi_rx_enabled(dev_priv, pipe);
1836
1837 if (HAS_PCH_CPT(dev)) {
1838 /* Workaround: Set the timing override bit before enabling the
1839 * pch transcoder. */
1840 reg = TRANS_CHICKEN2(pipe);
1841 val = I915_READ(reg);
1842 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1843 I915_WRITE(reg, val);
1844 }
1845
1846 reg = PCH_TRANSCONF(pipe);
1847 val = I915_READ(reg);
1848 pipeconf_val = I915_READ(PIPECONF(pipe));
1849
1850 if (HAS_PCH_IBX(dev_priv)) {
1851 /*
1852 * Make the BPC in transcoder be consistent with
1853 * that in pipeconf reg. For HDMI we must use 8bpc
1854 * here for both 8bpc and 12bpc.
1855 */
1856 val &= ~PIPECONF_BPC_MASK;
1857 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1858 val |= PIPECONF_8BPC;
1859 else
1860 val |= pipeconf_val & PIPECONF_BPC_MASK;
1861 }
1862
1863 val &= ~TRANS_INTERLACE_MASK;
1864 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1865 if (HAS_PCH_IBX(dev_priv) &&
1866 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1867 val |= TRANS_LEGACY_INTERLACED_ILK;
1868 else
1869 val |= TRANS_INTERLACED;
1870 else
1871 val |= TRANS_PROGRESSIVE;
1872
1873 I915_WRITE(reg, val | TRANS_ENABLE);
1874 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1875 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1876 }
1877
1878 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1879 enum transcoder cpu_transcoder)
1880 {
1881 u32 val, pipeconf_val;
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1885 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1886
1887 /* Workaround: set timing override bit. */
1888 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1891
1892 val = TRANS_ENABLE;
1893 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1894
1895 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1896 PIPECONF_INTERLACED_ILK)
1897 val |= TRANS_INTERLACED;
1898 else
1899 val |= TRANS_PROGRESSIVE;
1900
1901 I915_WRITE(LPT_TRANSCONF, val);
1902 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1903 DRM_ERROR("Failed to enable PCH transcoder\n");
1904 }
1905
1906 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1907 enum pipe pipe)
1908 {
1909 struct drm_device *dev = dev_priv->dev;
1910 i915_reg_t reg;
1911 uint32_t val;
1912
1913 /* FDI relies on the transcoder */
1914 assert_fdi_tx_disabled(dev_priv, pipe);
1915 assert_fdi_rx_disabled(dev_priv, pipe);
1916
1917 /* Ports must be off as well */
1918 assert_pch_ports_disabled(dev_priv, pipe);
1919
1920 reg = PCH_TRANSCONF(pipe);
1921 val = I915_READ(reg);
1922 val &= ~TRANS_ENABLE;
1923 I915_WRITE(reg, val);
1924 /* wait for PCH transcoder off, transcoder state */
1925 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1926 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1927
1928 if (HAS_PCH_CPT(dev)) {
1929 /* Workaround: Clear the timing override chicken bit again. */
1930 reg = TRANS_CHICKEN2(pipe);
1931 val = I915_READ(reg);
1932 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1933 I915_WRITE(reg, val);
1934 }
1935 }
1936
1937 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1938 {
1939 u32 val;
1940
1941 val = I915_READ(LPT_TRANSCONF);
1942 val &= ~TRANS_ENABLE;
1943 I915_WRITE(LPT_TRANSCONF, val);
1944 /* wait for PCH transcoder off, transcoder state */
1945 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1946 DRM_ERROR("Failed to disable PCH transcoder\n");
1947
1948 /* Workaround: clear timing override bit. */
1949 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1950 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1951 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1952 }
1953
1954 /**
1955 * intel_enable_pipe - enable a pipe, asserting requirements
1956 * @crtc: crtc responsible for the pipe
1957 *
1958 * Enable @crtc's pipe, making sure that various hardware specific requirements
1959 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1960 */
1961 static void intel_enable_pipe(struct intel_crtc *crtc)
1962 {
1963 struct drm_device *dev = crtc->base.dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 enum pipe pipe = crtc->pipe;
1966 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1967 enum pipe pch_transcoder;
1968 i915_reg_t reg;
1969 u32 val;
1970
1971 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1972
1973 assert_planes_disabled(dev_priv, pipe);
1974 assert_cursor_disabled(dev_priv, pipe);
1975 assert_sprites_disabled(dev_priv, pipe);
1976
1977 if (HAS_PCH_LPT(dev_priv))
1978 pch_transcoder = TRANSCODER_A;
1979 else
1980 pch_transcoder = pipe;
1981
1982 /*
1983 * A pipe without a PLL won't actually be able to drive bits from
1984 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1985 * need the check.
1986 */
1987 if (HAS_GMCH_DISPLAY(dev_priv))
1988 if (crtc->config->has_dsi_encoder)
1989 assert_dsi_pll_enabled(dev_priv);
1990 else
1991 assert_pll_enabled(dev_priv, pipe);
1992 else {
1993 if (crtc->config->has_pch_encoder) {
1994 /* if driving the PCH, we need FDI enabled */
1995 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1996 assert_fdi_tx_pll_enabled(dev_priv,
1997 (enum pipe) cpu_transcoder);
1998 }
1999 /* FIXME: assert CPU port conditions for SNB+ */
2000 }
2001
2002 reg = PIPECONF(cpu_transcoder);
2003 val = I915_READ(reg);
2004 if (val & PIPECONF_ENABLE) {
2005 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2006 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2007 return;
2008 }
2009
2010 I915_WRITE(reg, val | PIPECONF_ENABLE);
2011 POSTING_READ(reg);
2012
2013 /*
2014 * Until the pipe starts DSL will read as 0, which would cause
2015 * an apparent vblank timestamp jump, which messes up also the
2016 * frame count when it's derived from the timestamps. So let's
2017 * wait for the pipe to start properly before we call
2018 * drm_crtc_vblank_on()
2019 */
2020 if (dev->max_vblank_count == 0 &&
2021 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2022 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2023 }
2024
2025 /**
2026 * intel_disable_pipe - disable a pipe, asserting requirements
2027 * @crtc: crtc whose pipes is to be disabled
2028 *
2029 * Disable the pipe of @crtc, making sure that various hardware
2030 * specific requirements are met, if applicable, e.g. plane
2031 * disabled, panel fitter off, etc.
2032 *
2033 * Will wait until the pipe has shut down before returning.
2034 */
2035 static void intel_disable_pipe(struct intel_crtc *crtc)
2036 {
2037 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2038 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2039 enum pipe pipe = crtc->pipe;
2040 i915_reg_t reg;
2041 u32 val;
2042
2043 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2044
2045 /*
2046 * Make sure planes won't keep trying to pump pixels to us,
2047 * or we might hang the display.
2048 */
2049 assert_planes_disabled(dev_priv, pipe);
2050 assert_cursor_disabled(dev_priv, pipe);
2051 assert_sprites_disabled(dev_priv, pipe);
2052
2053 reg = PIPECONF(cpu_transcoder);
2054 val = I915_READ(reg);
2055 if ((val & PIPECONF_ENABLE) == 0)
2056 return;
2057
2058 /*
2059 * Double wide has implications for planes
2060 * so best keep it disabled when not needed.
2061 */
2062 if (crtc->config->double_wide)
2063 val &= ~PIPECONF_DOUBLE_WIDE;
2064
2065 /* Don't disable pipe or pipe PLLs if needed */
2066 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2067 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2068 val &= ~PIPECONF_ENABLE;
2069
2070 I915_WRITE(reg, val);
2071 if ((val & PIPECONF_ENABLE) == 0)
2072 intel_wait_for_pipe_off(crtc);
2073 }
2074
2075 static bool need_vtd_wa(struct drm_device *dev)
2076 {
2077 #ifdef CONFIG_INTEL_IOMMU
2078 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2079 return true;
2080 #endif
2081 return false;
2082 }
2083
2084 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2085 {
2086 return IS_GEN2(dev_priv) ? 2048 : 4096;
2087 }
2088
2089 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2090 uint64_t fb_modifier, unsigned int cpp)
2091 {
2092 switch (fb_modifier) {
2093 case DRM_FORMAT_MOD_NONE:
2094 return cpp;
2095 case I915_FORMAT_MOD_X_TILED:
2096 if (IS_GEN2(dev_priv))
2097 return 128;
2098 else
2099 return 512;
2100 case I915_FORMAT_MOD_Y_TILED:
2101 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2102 return 128;
2103 else
2104 return 512;
2105 case I915_FORMAT_MOD_Yf_TILED:
2106 switch (cpp) {
2107 case 1:
2108 return 64;
2109 case 2:
2110 case 4:
2111 return 128;
2112 case 8:
2113 case 16:
2114 return 256;
2115 default:
2116 MISSING_CASE(cpp);
2117 return cpp;
2118 }
2119 break;
2120 default:
2121 MISSING_CASE(fb_modifier);
2122 return cpp;
2123 }
2124 }
2125
2126 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2127 uint64_t fb_modifier, unsigned int cpp)
2128 {
2129 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2130 return 1;
2131 else
2132 return intel_tile_size(dev_priv) /
2133 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2134 }
2135
2136 /* Return the tile dimensions in pixel units */
2137 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2138 unsigned int *tile_width,
2139 unsigned int *tile_height,
2140 uint64_t fb_modifier,
2141 unsigned int cpp)
2142 {
2143 unsigned int tile_width_bytes =
2144 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2145
2146 *tile_width = tile_width_bytes / cpp;
2147 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2148 }
2149
2150 unsigned int
2151 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2152 uint32_t pixel_format, uint64_t fb_modifier)
2153 {
2154 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2155 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2156
2157 return ALIGN(height, tile_height);
2158 }
2159
2160 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2161 {
2162 unsigned int size = 0;
2163 int i;
2164
2165 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2166 size += rot_info->plane[i].width * rot_info->plane[i].height;
2167
2168 return size;
2169 }
2170
2171 static void
2172 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2173 const struct drm_framebuffer *fb,
2174 unsigned int rotation)
2175 {
2176 if (intel_rotation_90_or_270(rotation)) {
2177 *view = i915_ggtt_view_rotated;
2178 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2179 } else {
2180 *view = i915_ggtt_view_normal;
2181 }
2182 }
2183
2184 static void
2185 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2186 struct drm_framebuffer *fb)
2187 {
2188 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2189 unsigned int tile_size, tile_width, tile_height, cpp;
2190
2191 tile_size = intel_tile_size(dev_priv);
2192
2193 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2194 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2195 fb->modifier[0], cpp);
2196
2197 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2198 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2199
2200 if (info->pixel_format == DRM_FORMAT_NV12) {
2201 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2202 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2203 fb->modifier[1], cpp);
2204
2205 info->uv_offset = fb->offsets[1];
2206 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2207 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2208 }
2209 }
2210
2211 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2212 {
2213 if (INTEL_INFO(dev_priv)->gen >= 9)
2214 return 256 * 1024;
2215 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2216 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2217 return 128 * 1024;
2218 else if (INTEL_INFO(dev_priv)->gen >= 4)
2219 return 4 * 1024;
2220 else
2221 return 0;
2222 }
2223
2224 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2225 uint64_t fb_modifier)
2226 {
2227 switch (fb_modifier) {
2228 case DRM_FORMAT_MOD_NONE:
2229 return intel_linear_alignment(dev_priv);
2230 case I915_FORMAT_MOD_X_TILED:
2231 if (INTEL_INFO(dev_priv)->gen >= 9)
2232 return 256 * 1024;
2233 return 0;
2234 case I915_FORMAT_MOD_Y_TILED:
2235 case I915_FORMAT_MOD_Yf_TILED:
2236 return 1 * 1024 * 1024;
2237 default:
2238 MISSING_CASE(fb_modifier);
2239 return 0;
2240 }
2241 }
2242
2243 int
2244 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2245 unsigned int rotation)
2246 {
2247 struct drm_device *dev = fb->dev;
2248 struct drm_i915_private *dev_priv = dev->dev_private;
2249 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2250 struct i915_ggtt_view view;
2251 u32 alignment;
2252 int ret;
2253
2254 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2255
2256 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2257
2258 intel_fill_fb_ggtt_view(&view, fb, rotation);
2259
2260 /* Note that the w/a also requires 64 PTE of padding following the
2261 * bo. We currently fill all unused PTE with the shadow page and so
2262 * we should always have valid PTE following the scanout preventing
2263 * the VT-d warning.
2264 */
2265 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2266 alignment = 256 * 1024;
2267
2268 /*
2269 * Global gtt pte registers are special registers which actually forward
2270 * writes to a chunk of system memory. Which means that there is no risk
2271 * that the register values disappear as soon as we call
2272 * intel_runtime_pm_put(), so it is correct to wrap only the
2273 * pin/unpin/fence and not more.
2274 */
2275 intel_runtime_pm_get(dev_priv);
2276
2277 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2278 &view);
2279 if (ret)
2280 goto err_pm;
2281
2282 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2283 * fence, whereas 965+ only requires a fence if using
2284 * framebuffer compression. For simplicity, we always install
2285 * a fence as the cost is not that onerous.
2286 */
2287 if (view.type == I915_GGTT_VIEW_NORMAL) {
2288 ret = i915_gem_object_get_fence(obj);
2289 if (ret == -EDEADLK) {
2290 /*
2291 * -EDEADLK means there are no free fences
2292 * no pending flips.
2293 *
2294 * This is propagated to atomic, but it uses
2295 * -EDEADLK to force a locking recovery, so
2296 * change the returned error to -EBUSY.
2297 */
2298 ret = -EBUSY;
2299 goto err_unpin;
2300 } else if (ret)
2301 goto err_unpin;
2302
2303 i915_gem_object_pin_fence(obj);
2304 }
2305
2306 intel_runtime_pm_put(dev_priv);
2307 return 0;
2308
2309 err_unpin:
2310 i915_gem_object_unpin_from_display_plane(obj, &view);
2311 err_pm:
2312 intel_runtime_pm_put(dev_priv);
2313 return ret;
2314 }
2315
2316 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2317 {
2318 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2319 struct i915_ggtt_view view;
2320
2321 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2322
2323 intel_fill_fb_ggtt_view(&view, fb, rotation);
2324
2325 if (view.type == I915_GGTT_VIEW_NORMAL)
2326 i915_gem_object_unpin_fence(obj);
2327
2328 i915_gem_object_unpin_from_display_plane(obj, &view);
2329 }
2330
2331 /*
2332 * Adjust the tile offset by moving the difference into
2333 * the x/y offsets.
2334 *
2335 * Input tile dimensions and pitch must already be
2336 * rotated to match x and y, and in pixel units.
2337 */
2338 static u32 intel_adjust_tile_offset(int *x, int *y,
2339 unsigned int tile_width,
2340 unsigned int tile_height,
2341 unsigned int tile_size,
2342 unsigned int pitch_tiles,
2343 u32 old_offset,
2344 u32 new_offset)
2345 {
2346 unsigned int tiles;
2347
2348 WARN_ON(old_offset & (tile_size - 1));
2349 WARN_ON(new_offset & (tile_size - 1));
2350 WARN_ON(new_offset > old_offset);
2351
2352 tiles = (old_offset - new_offset) / tile_size;
2353
2354 *y += tiles / pitch_tiles * tile_height;
2355 *x += tiles % pitch_tiles * tile_width;
2356
2357 return new_offset;
2358 }
2359
2360 /*
2361 * Computes the linear offset to the base tile and adjusts
2362 * x, y. bytes per pixel is assumed to be a power-of-two.
2363 *
2364 * In the 90/270 rotated case, x and y are assumed
2365 * to be already rotated to match the rotated GTT view, and
2366 * pitch is the tile_height aligned framebuffer height.
2367 */
2368 u32 intel_compute_tile_offset(int *x, int *y,
2369 const struct drm_framebuffer *fb, int plane,
2370 unsigned int pitch,
2371 unsigned int rotation)
2372 {
2373 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2374 uint64_t fb_modifier = fb->modifier[plane];
2375 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2376 u32 offset, offset_aligned, alignment;
2377
2378 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2379 if (alignment)
2380 alignment--;
2381
2382 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2383 unsigned int tile_size, tile_width, tile_height;
2384 unsigned int tile_rows, tiles, pitch_tiles;
2385
2386 tile_size = intel_tile_size(dev_priv);
2387 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2388 fb_modifier, cpp);
2389
2390 if (intel_rotation_90_or_270(rotation)) {
2391 pitch_tiles = pitch / tile_height;
2392 swap(tile_width, tile_height);
2393 } else {
2394 pitch_tiles = pitch / (tile_width * cpp);
2395 }
2396
2397 tile_rows = *y / tile_height;
2398 *y %= tile_height;
2399
2400 tiles = *x / tile_width;
2401 *x %= tile_width;
2402
2403 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2404 offset_aligned = offset & ~alignment;
2405
2406 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2407 tile_size, pitch_tiles,
2408 offset, offset_aligned);
2409 } else {
2410 offset = *y * pitch + *x * cpp;
2411 offset_aligned = offset & ~alignment;
2412
2413 *y = (offset & alignment) / pitch;
2414 *x = ((offset & alignment) - *y * pitch) / cpp;
2415 }
2416
2417 return offset_aligned;
2418 }
2419
2420 static int i9xx_format_to_fourcc(int format)
2421 {
2422 switch (format) {
2423 case DISPPLANE_8BPP:
2424 return DRM_FORMAT_C8;
2425 case DISPPLANE_BGRX555:
2426 return DRM_FORMAT_XRGB1555;
2427 case DISPPLANE_BGRX565:
2428 return DRM_FORMAT_RGB565;
2429 default:
2430 case DISPPLANE_BGRX888:
2431 return DRM_FORMAT_XRGB8888;
2432 case DISPPLANE_RGBX888:
2433 return DRM_FORMAT_XBGR8888;
2434 case DISPPLANE_BGRX101010:
2435 return DRM_FORMAT_XRGB2101010;
2436 case DISPPLANE_RGBX101010:
2437 return DRM_FORMAT_XBGR2101010;
2438 }
2439 }
2440
2441 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2442 {
2443 switch (format) {
2444 case PLANE_CTL_FORMAT_RGB_565:
2445 return DRM_FORMAT_RGB565;
2446 default:
2447 case PLANE_CTL_FORMAT_XRGB_8888:
2448 if (rgb_order) {
2449 if (alpha)
2450 return DRM_FORMAT_ABGR8888;
2451 else
2452 return DRM_FORMAT_XBGR8888;
2453 } else {
2454 if (alpha)
2455 return DRM_FORMAT_ARGB8888;
2456 else
2457 return DRM_FORMAT_XRGB8888;
2458 }
2459 case PLANE_CTL_FORMAT_XRGB_2101010:
2460 if (rgb_order)
2461 return DRM_FORMAT_XBGR2101010;
2462 else
2463 return DRM_FORMAT_XRGB2101010;
2464 }
2465 }
2466
2467 static bool
2468 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2469 struct intel_initial_plane_config *plane_config)
2470 {
2471 struct drm_device *dev = crtc->base.dev;
2472 struct drm_i915_private *dev_priv = to_i915(dev);
2473 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2474 struct drm_i915_gem_object *obj = NULL;
2475 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2476 struct drm_framebuffer *fb = &plane_config->fb->base;
2477 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2478 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2479 PAGE_SIZE);
2480
2481 size_aligned -= base_aligned;
2482
2483 if (plane_config->size == 0)
2484 return false;
2485
2486 /* If the FB is too big, just don't use it since fbdev is not very
2487 * important and we should probably use that space with FBC or other
2488 * features. */
2489 if (size_aligned * 2 > ggtt->stolen_usable_size)
2490 return false;
2491
2492 mutex_lock(&dev->struct_mutex);
2493
2494 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2495 base_aligned,
2496 base_aligned,
2497 size_aligned);
2498 if (!obj) {
2499 mutex_unlock(&dev->struct_mutex);
2500 return false;
2501 }
2502
2503 obj->tiling_mode = plane_config->tiling;
2504 if (obj->tiling_mode == I915_TILING_X)
2505 obj->stride = fb->pitches[0];
2506
2507 mode_cmd.pixel_format = fb->pixel_format;
2508 mode_cmd.width = fb->width;
2509 mode_cmd.height = fb->height;
2510 mode_cmd.pitches[0] = fb->pitches[0];
2511 mode_cmd.modifier[0] = fb->modifier[0];
2512 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2513
2514 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2515 &mode_cmd, obj)) {
2516 DRM_DEBUG_KMS("intel fb init failed\n");
2517 goto out_unref_obj;
2518 }
2519
2520 mutex_unlock(&dev->struct_mutex);
2521
2522 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2523 return true;
2524
2525 out_unref_obj:
2526 drm_gem_object_unreference(&obj->base);
2527 mutex_unlock(&dev->struct_mutex);
2528 return false;
2529 }
2530
2531 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2532 static void
2533 update_state_fb(struct drm_plane *plane)
2534 {
2535 if (plane->fb == plane->state->fb)
2536 return;
2537
2538 if (plane->state->fb)
2539 drm_framebuffer_unreference(plane->state->fb);
2540 plane->state->fb = plane->fb;
2541 if (plane->state->fb)
2542 drm_framebuffer_reference(plane->state->fb);
2543 }
2544
2545 static void
2546 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2547 struct intel_initial_plane_config *plane_config)
2548 {
2549 struct drm_device *dev = intel_crtc->base.dev;
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551 struct drm_crtc *c;
2552 struct intel_crtc *i;
2553 struct drm_i915_gem_object *obj;
2554 struct drm_plane *primary = intel_crtc->base.primary;
2555 struct drm_plane_state *plane_state = primary->state;
2556 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2557 struct intel_plane *intel_plane = to_intel_plane(primary);
2558 struct intel_plane_state *intel_state =
2559 to_intel_plane_state(plane_state);
2560 struct drm_framebuffer *fb;
2561
2562 if (!plane_config->fb)
2563 return;
2564
2565 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2566 fb = &plane_config->fb->base;
2567 goto valid_fb;
2568 }
2569
2570 kfree(plane_config->fb);
2571
2572 /*
2573 * Failed to alloc the obj, check to see if we should share
2574 * an fb with another CRTC instead
2575 */
2576 for_each_crtc(dev, c) {
2577 i = to_intel_crtc(c);
2578
2579 if (c == &intel_crtc->base)
2580 continue;
2581
2582 if (!i->active)
2583 continue;
2584
2585 fb = c->primary->fb;
2586 if (!fb)
2587 continue;
2588
2589 obj = intel_fb_obj(fb);
2590 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2591 drm_framebuffer_reference(fb);
2592 goto valid_fb;
2593 }
2594 }
2595
2596 /*
2597 * We've failed to reconstruct the BIOS FB. Current display state
2598 * indicates that the primary plane is visible, but has a NULL FB,
2599 * which will lead to problems later if we don't fix it up. The
2600 * simplest solution is to just disable the primary plane now and
2601 * pretend the BIOS never had it enabled.
2602 */
2603 to_intel_plane_state(plane_state)->visible = false;
2604 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2605 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2606 intel_plane->disable_plane(primary, &intel_crtc->base);
2607
2608 return;
2609
2610 valid_fb:
2611 plane_state->src_x = 0;
2612 plane_state->src_y = 0;
2613 plane_state->src_w = fb->width << 16;
2614 plane_state->src_h = fb->height << 16;
2615
2616 plane_state->crtc_x = 0;
2617 plane_state->crtc_y = 0;
2618 plane_state->crtc_w = fb->width;
2619 plane_state->crtc_h = fb->height;
2620
2621 intel_state->src.x1 = plane_state->src_x;
2622 intel_state->src.y1 = plane_state->src_y;
2623 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2624 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2625 intel_state->dst.x1 = plane_state->crtc_x;
2626 intel_state->dst.y1 = plane_state->crtc_y;
2627 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2628 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2629
2630 obj = intel_fb_obj(fb);
2631 if (obj->tiling_mode != I915_TILING_NONE)
2632 dev_priv->preserve_bios_swizzle = true;
2633
2634 drm_framebuffer_reference(fb);
2635 primary->fb = primary->state->fb = fb;
2636 primary->crtc = primary->state->crtc = &intel_crtc->base;
2637 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2638 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2639 }
2640
2641 static void i9xx_update_primary_plane(struct drm_plane *primary,
2642 const struct intel_crtc_state *crtc_state,
2643 const struct intel_plane_state *plane_state)
2644 {
2645 struct drm_device *dev = primary->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2648 struct drm_framebuffer *fb = plane_state->base.fb;
2649 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2650 int plane = intel_crtc->plane;
2651 u32 linear_offset;
2652 u32 dspcntr;
2653 i915_reg_t reg = DSPCNTR(plane);
2654 unsigned int rotation = plane_state->base.rotation;
2655 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2656 int x = plane_state->src.x1 >> 16;
2657 int y = plane_state->src.y1 >> 16;
2658
2659 dspcntr = DISPPLANE_GAMMA_ENABLE;
2660
2661 dspcntr |= DISPLAY_PLANE_ENABLE;
2662
2663 if (INTEL_INFO(dev)->gen < 4) {
2664 if (intel_crtc->pipe == PIPE_B)
2665 dspcntr |= DISPPLANE_SEL_PIPE_B;
2666
2667 /* pipesrc and dspsize control the size that is scaled from,
2668 * which should always be the user's requested size.
2669 */
2670 I915_WRITE(DSPSIZE(plane),
2671 ((crtc_state->pipe_src_h - 1) << 16) |
2672 (crtc_state->pipe_src_w - 1));
2673 I915_WRITE(DSPPOS(plane), 0);
2674 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2675 I915_WRITE(PRIMSIZE(plane),
2676 ((crtc_state->pipe_src_h - 1) << 16) |
2677 (crtc_state->pipe_src_w - 1));
2678 I915_WRITE(PRIMPOS(plane), 0);
2679 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2680 }
2681
2682 switch (fb->pixel_format) {
2683 case DRM_FORMAT_C8:
2684 dspcntr |= DISPPLANE_8BPP;
2685 break;
2686 case DRM_FORMAT_XRGB1555:
2687 dspcntr |= DISPPLANE_BGRX555;
2688 break;
2689 case DRM_FORMAT_RGB565:
2690 dspcntr |= DISPPLANE_BGRX565;
2691 break;
2692 case DRM_FORMAT_XRGB8888:
2693 dspcntr |= DISPPLANE_BGRX888;
2694 break;
2695 case DRM_FORMAT_XBGR8888:
2696 dspcntr |= DISPPLANE_RGBX888;
2697 break;
2698 case DRM_FORMAT_XRGB2101010:
2699 dspcntr |= DISPPLANE_BGRX101010;
2700 break;
2701 case DRM_FORMAT_XBGR2101010:
2702 dspcntr |= DISPPLANE_RGBX101010;
2703 break;
2704 default:
2705 BUG();
2706 }
2707
2708 if (INTEL_INFO(dev)->gen >= 4 &&
2709 obj->tiling_mode != I915_TILING_NONE)
2710 dspcntr |= DISPPLANE_TILED;
2711
2712 if (IS_G4X(dev))
2713 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2714
2715 linear_offset = y * fb->pitches[0] + x * cpp;
2716
2717 if (INTEL_INFO(dev)->gen >= 4) {
2718 intel_crtc->dspaddr_offset =
2719 intel_compute_tile_offset(&x, &y, fb, 0,
2720 fb->pitches[0], rotation);
2721 linear_offset -= intel_crtc->dspaddr_offset;
2722 } else {
2723 intel_crtc->dspaddr_offset = linear_offset;
2724 }
2725
2726 if (rotation == BIT(DRM_ROTATE_180)) {
2727 dspcntr |= DISPPLANE_ROTATE_180;
2728
2729 x += (crtc_state->pipe_src_w - 1);
2730 y += (crtc_state->pipe_src_h - 1);
2731
2732 /* Finding the last pixel of the last line of the display
2733 data and adding to linear_offset*/
2734 linear_offset +=
2735 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2736 (crtc_state->pipe_src_w - 1) * cpp;
2737 }
2738
2739 intel_crtc->adjusted_x = x;
2740 intel_crtc->adjusted_y = y;
2741
2742 I915_WRITE(reg, dspcntr);
2743
2744 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2745 if (INTEL_INFO(dev)->gen >= 4) {
2746 I915_WRITE(DSPSURF(plane),
2747 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2748 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2749 I915_WRITE(DSPLINOFF(plane), linear_offset);
2750 } else
2751 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2752 POSTING_READ(reg);
2753 }
2754
2755 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2756 struct drm_crtc *crtc)
2757 {
2758 struct drm_device *dev = crtc->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2761 int plane = intel_crtc->plane;
2762
2763 I915_WRITE(DSPCNTR(plane), 0);
2764 if (INTEL_INFO(dev_priv)->gen >= 4)
2765 I915_WRITE(DSPSURF(plane), 0);
2766 else
2767 I915_WRITE(DSPADDR(plane), 0);
2768 POSTING_READ(DSPCNTR(plane));
2769 }
2770
2771 static void ironlake_update_primary_plane(struct drm_plane *primary,
2772 const struct intel_crtc_state *crtc_state,
2773 const struct intel_plane_state *plane_state)
2774 {
2775 struct drm_device *dev = primary->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2778 struct drm_framebuffer *fb = plane_state->base.fb;
2779 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2780 int plane = intel_crtc->plane;
2781 u32 linear_offset;
2782 u32 dspcntr;
2783 i915_reg_t reg = DSPCNTR(plane);
2784 unsigned int rotation = plane_state->base.rotation;
2785 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2786 int x = plane_state->src.x1 >> 16;
2787 int y = plane_state->src.y1 >> 16;
2788
2789 dspcntr = DISPPLANE_GAMMA_ENABLE;
2790 dspcntr |= DISPLAY_PLANE_ENABLE;
2791
2792 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2793 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2794
2795 switch (fb->pixel_format) {
2796 case DRM_FORMAT_C8:
2797 dspcntr |= DISPPLANE_8BPP;
2798 break;
2799 case DRM_FORMAT_RGB565:
2800 dspcntr |= DISPPLANE_BGRX565;
2801 break;
2802 case DRM_FORMAT_XRGB8888:
2803 dspcntr |= DISPPLANE_BGRX888;
2804 break;
2805 case DRM_FORMAT_XBGR8888:
2806 dspcntr |= DISPPLANE_RGBX888;
2807 break;
2808 case DRM_FORMAT_XRGB2101010:
2809 dspcntr |= DISPPLANE_BGRX101010;
2810 break;
2811 case DRM_FORMAT_XBGR2101010:
2812 dspcntr |= DISPPLANE_RGBX101010;
2813 break;
2814 default:
2815 BUG();
2816 }
2817
2818 if (obj->tiling_mode != I915_TILING_NONE)
2819 dspcntr |= DISPPLANE_TILED;
2820
2821 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2822 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2823
2824 linear_offset = y * fb->pitches[0] + x * cpp;
2825 intel_crtc->dspaddr_offset =
2826 intel_compute_tile_offset(&x, &y, fb, 0,
2827 fb->pitches[0], rotation);
2828 linear_offset -= intel_crtc->dspaddr_offset;
2829 if (rotation == BIT(DRM_ROTATE_180)) {
2830 dspcntr |= DISPPLANE_ROTATE_180;
2831
2832 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2833 x += (crtc_state->pipe_src_w - 1);
2834 y += (crtc_state->pipe_src_h - 1);
2835
2836 /* Finding the last pixel of the last line of the display
2837 data and adding to linear_offset*/
2838 linear_offset +=
2839 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2840 (crtc_state->pipe_src_w - 1) * cpp;
2841 }
2842 }
2843
2844 intel_crtc->adjusted_x = x;
2845 intel_crtc->adjusted_y = y;
2846
2847 I915_WRITE(reg, dspcntr);
2848
2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
2858 POSTING_READ(reg);
2859 }
2860
2861 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2862 uint64_t fb_modifier, uint32_t pixel_format)
2863 {
2864 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2865 return 64;
2866 } else {
2867 int cpp = drm_format_plane_cpp(pixel_format, 0);
2868
2869 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2870 }
2871 }
2872
2873 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2874 struct drm_i915_gem_object *obj,
2875 unsigned int plane)
2876 {
2877 struct i915_ggtt_view view;
2878 struct i915_vma *vma;
2879 u64 offset;
2880
2881 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2882 intel_plane->base.state->rotation);
2883
2884 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2885 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2886 view.type))
2887 return -1;
2888
2889 offset = vma->node.start;
2890
2891 if (plane == 1) {
2892 offset += vma->ggtt_view.params.rotated.uv_start_page *
2893 PAGE_SIZE;
2894 }
2895
2896 WARN_ON(upper_32_bits(offset));
2897
2898 return lower_32_bits(offset);
2899 }
2900
2901 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2902 {
2903 struct drm_device *dev = intel_crtc->base.dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905
2906 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2907 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2908 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2909 }
2910
2911 /*
2912 * This function detaches (aka. unbinds) unused scalers in hardware
2913 */
2914 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2915 {
2916 struct intel_crtc_scaler_state *scaler_state;
2917 int i;
2918
2919 scaler_state = &intel_crtc->config->scaler_state;
2920
2921 /* loop through and disable scalers that aren't in use */
2922 for (i = 0; i < intel_crtc->num_scalers; i++) {
2923 if (!scaler_state->scalers[i].in_use)
2924 skl_detach_scaler(intel_crtc, i);
2925 }
2926 }
2927
2928 u32 skl_plane_ctl_format(uint32_t pixel_format)
2929 {
2930 switch (pixel_format) {
2931 case DRM_FORMAT_C8:
2932 return PLANE_CTL_FORMAT_INDEXED;
2933 case DRM_FORMAT_RGB565:
2934 return PLANE_CTL_FORMAT_RGB_565;
2935 case DRM_FORMAT_XBGR8888:
2936 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2937 case DRM_FORMAT_XRGB8888:
2938 return PLANE_CTL_FORMAT_XRGB_8888;
2939 /*
2940 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2941 * to be already pre-multiplied. We need to add a knob (or a different
2942 * DRM_FORMAT) for user-space to configure that.
2943 */
2944 case DRM_FORMAT_ABGR8888:
2945 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2946 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2947 case DRM_FORMAT_ARGB8888:
2948 return PLANE_CTL_FORMAT_XRGB_8888 |
2949 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2950 case DRM_FORMAT_XRGB2101010:
2951 return PLANE_CTL_FORMAT_XRGB_2101010;
2952 case DRM_FORMAT_XBGR2101010:
2953 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2954 case DRM_FORMAT_YUYV:
2955 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2956 case DRM_FORMAT_YVYU:
2957 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2958 case DRM_FORMAT_UYVY:
2959 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2960 case DRM_FORMAT_VYUY:
2961 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2962 default:
2963 MISSING_CASE(pixel_format);
2964 }
2965
2966 return 0;
2967 }
2968
2969 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2970 {
2971 switch (fb_modifier) {
2972 case DRM_FORMAT_MOD_NONE:
2973 break;
2974 case I915_FORMAT_MOD_X_TILED:
2975 return PLANE_CTL_TILED_X;
2976 case I915_FORMAT_MOD_Y_TILED:
2977 return PLANE_CTL_TILED_Y;
2978 case I915_FORMAT_MOD_Yf_TILED:
2979 return PLANE_CTL_TILED_YF;
2980 default:
2981 MISSING_CASE(fb_modifier);
2982 }
2983
2984 return 0;
2985 }
2986
2987 u32 skl_plane_ctl_rotation(unsigned int rotation)
2988 {
2989 switch (rotation) {
2990 case BIT(DRM_ROTATE_0):
2991 break;
2992 /*
2993 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2994 * while i915 HW rotation is clockwise, thats why this swapping.
2995 */
2996 case BIT(DRM_ROTATE_90):
2997 return PLANE_CTL_ROTATE_270;
2998 case BIT(DRM_ROTATE_180):
2999 return PLANE_CTL_ROTATE_180;
3000 case BIT(DRM_ROTATE_270):
3001 return PLANE_CTL_ROTATE_90;
3002 default:
3003 MISSING_CASE(rotation);
3004 }
3005
3006 return 0;
3007 }
3008
3009 static void skylake_update_primary_plane(struct drm_plane *plane,
3010 const struct intel_crtc_state *crtc_state,
3011 const struct intel_plane_state *plane_state)
3012 {
3013 struct drm_device *dev = plane->dev;
3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3016 struct drm_framebuffer *fb = plane_state->base.fb;
3017 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3018 int pipe = intel_crtc->pipe;
3019 u32 plane_ctl, stride_div, stride;
3020 u32 tile_height, plane_offset, plane_size;
3021 unsigned int rotation = plane_state->base.rotation;
3022 int x_offset, y_offset;
3023 u32 surf_addr;
3024 int scaler_id = plane_state->scaler_id;
3025 int src_x = plane_state->src.x1 >> 16;
3026 int src_y = plane_state->src.y1 >> 16;
3027 int src_w = drm_rect_width(&plane_state->src) >> 16;
3028 int src_h = drm_rect_height(&plane_state->src) >> 16;
3029 int dst_x = plane_state->dst.x1;
3030 int dst_y = plane_state->dst.y1;
3031 int dst_w = drm_rect_width(&plane_state->dst);
3032 int dst_h = drm_rect_height(&plane_state->dst);
3033
3034 plane_ctl = PLANE_CTL_ENABLE |
3035 PLANE_CTL_PIPE_GAMMA_ENABLE |
3036 PLANE_CTL_PIPE_CSC_ENABLE;
3037
3038 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3039 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3040 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3041 plane_ctl |= skl_plane_ctl_rotation(rotation);
3042
3043 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3044 fb->pixel_format);
3045 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3046
3047 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3048
3049 if (intel_rotation_90_or_270(rotation)) {
3050 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3051
3052 /* stride = Surface height in tiles */
3053 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3054 stride = DIV_ROUND_UP(fb->height, tile_height);
3055 x_offset = stride * tile_height - src_y - src_h;
3056 y_offset = src_x;
3057 plane_size = (src_w - 1) << 16 | (src_h - 1);
3058 } else {
3059 stride = fb->pitches[0] / stride_div;
3060 x_offset = src_x;
3061 y_offset = src_y;
3062 plane_size = (src_h - 1) << 16 | (src_w - 1);
3063 }
3064 plane_offset = y_offset << 16 | x_offset;
3065
3066 intel_crtc->adjusted_x = x_offset;
3067 intel_crtc->adjusted_y = y_offset;
3068
3069 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3070 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3071 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3072 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3073
3074 if (scaler_id >= 0) {
3075 uint32_t ps_ctrl = 0;
3076
3077 WARN_ON(!dst_w || !dst_h);
3078 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3079 crtc_state->scaler_state.scalers[scaler_id].mode;
3080 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3081 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3082 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3083 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3084 I915_WRITE(PLANE_POS(pipe, 0), 0);
3085 } else {
3086 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3087 }
3088
3089 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3090
3091 POSTING_READ(PLANE_SURF(pipe, 0));
3092 }
3093
3094 static void skylake_disable_primary_plane(struct drm_plane *primary,
3095 struct drm_crtc *crtc)
3096 {
3097 struct drm_device *dev = crtc->dev;
3098 struct drm_i915_private *dev_priv = dev->dev_private;
3099 int pipe = to_intel_crtc(crtc)->pipe;
3100
3101 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3102 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3103 POSTING_READ(PLANE_SURF(pipe, 0));
3104 }
3105
3106 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3107 static int
3108 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3109 int x, int y, enum mode_set_atomic state)
3110 {
3111 /* Support for kgdboc is disabled, this needs a major rework. */
3112 DRM_ERROR("legacy panic handler not supported any more.\n");
3113
3114 return -ENODEV;
3115 }
3116
3117 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3118 {
3119 struct intel_crtc *crtc;
3120
3121 for_each_intel_crtc(dev_priv->dev, crtc)
3122 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3123 }
3124
3125 static void intel_update_primary_planes(struct drm_device *dev)
3126 {
3127 struct drm_crtc *crtc;
3128
3129 for_each_crtc(dev, crtc) {
3130 struct intel_plane *plane = to_intel_plane(crtc->primary);
3131 struct intel_plane_state *plane_state;
3132
3133 drm_modeset_lock_crtc(crtc, &plane->base);
3134 plane_state = to_intel_plane_state(plane->base.state);
3135
3136 if (plane_state->visible)
3137 plane->update_plane(&plane->base,
3138 to_intel_crtc_state(crtc->state),
3139 plane_state);
3140
3141 drm_modeset_unlock_crtc(crtc);
3142 }
3143 }
3144
3145 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3146 {
3147 /* no reset support for gen2 */
3148 if (IS_GEN2(dev_priv))
3149 return;
3150
3151 /* reset doesn't touch the display */
3152 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3153 return;
3154
3155 drm_modeset_lock_all(dev_priv->dev);
3156 /*
3157 * Disabling the crtcs gracefully seems nicer. Also the
3158 * g33 docs say we should at least disable all the planes.
3159 */
3160 intel_display_suspend(dev_priv->dev);
3161 }
3162
3163 void intel_finish_reset(struct drm_i915_private *dev_priv)
3164 {
3165 /*
3166 * Flips in the rings will be nuked by the reset,
3167 * so complete all pending flips so that user space
3168 * will get its events and not get stuck.
3169 */
3170 intel_complete_page_flips(dev_priv);
3171
3172 /* no reset support for gen2 */
3173 if (IS_GEN2(dev_priv))
3174 return;
3175
3176 /* reset doesn't touch the display */
3177 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3178 /*
3179 * Flips in the rings have been nuked by the reset,
3180 * so update the base address of all primary
3181 * planes to the the last fb to make sure we're
3182 * showing the correct fb after a reset.
3183 *
3184 * FIXME: Atomic will make this obsolete since we won't schedule
3185 * CS-based flips (which might get lost in gpu resets) any more.
3186 */
3187 intel_update_primary_planes(dev_priv->dev);
3188 return;
3189 }
3190
3191 /*
3192 * The display has been reset as well,
3193 * so need a full re-initialization.
3194 */
3195 intel_runtime_pm_disable_interrupts(dev_priv);
3196 intel_runtime_pm_enable_interrupts(dev_priv);
3197
3198 intel_modeset_init_hw(dev_priv->dev);
3199
3200 spin_lock_irq(&dev_priv->irq_lock);
3201 if (dev_priv->display.hpd_irq_setup)
3202 dev_priv->display.hpd_irq_setup(dev_priv);
3203 spin_unlock_irq(&dev_priv->irq_lock);
3204
3205 intel_display_resume(dev_priv->dev);
3206
3207 intel_hpd_init(dev_priv);
3208
3209 drm_modeset_unlock_all(dev_priv->dev);
3210 }
3211
3212 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3213 {
3214 struct drm_device *dev = crtc->dev;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216 unsigned reset_counter;
3217 bool pending;
3218
3219 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3220 if (intel_crtc->reset_counter != reset_counter)
3221 return false;
3222
3223 spin_lock_irq(&dev->event_lock);
3224 pending = to_intel_crtc(crtc)->flip_work != NULL;
3225 spin_unlock_irq(&dev->event_lock);
3226
3227 return pending;
3228 }
3229
3230 static void intel_update_pipe_config(struct intel_crtc *crtc,
3231 struct intel_crtc_state *old_crtc_state)
3232 {
3233 struct drm_device *dev = crtc->base.dev;
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 struct intel_crtc_state *pipe_config =
3236 to_intel_crtc_state(crtc->base.state);
3237
3238 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3239 crtc->base.mode = crtc->base.state->mode;
3240
3241 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3242 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3243 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3244
3245 /*
3246 * Update pipe size and adjust fitter if needed: the reason for this is
3247 * that in compute_mode_changes we check the native mode (not the pfit
3248 * mode) to see if we can flip rather than do a full mode set. In the
3249 * fastboot case, we'll flip, but if we don't update the pipesrc and
3250 * pfit state, we'll end up with a big fb scanned out into the wrong
3251 * sized surface.
3252 */
3253
3254 I915_WRITE(PIPESRC(crtc->pipe),
3255 ((pipe_config->pipe_src_w - 1) << 16) |
3256 (pipe_config->pipe_src_h - 1));
3257
3258 /* on skylake this is done by detaching scalers */
3259 if (INTEL_INFO(dev)->gen >= 9) {
3260 skl_detach_scalers(crtc);
3261
3262 if (pipe_config->pch_pfit.enabled)
3263 skylake_pfit_enable(crtc);
3264 } else if (HAS_PCH_SPLIT(dev)) {
3265 if (pipe_config->pch_pfit.enabled)
3266 ironlake_pfit_enable(crtc);
3267 else if (old_crtc_state->pch_pfit.enabled)
3268 ironlake_pfit_disable(crtc, true);
3269 }
3270 }
3271
3272 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3273 {
3274 struct drm_device *dev = crtc->dev;
3275 struct drm_i915_private *dev_priv = dev->dev_private;
3276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3277 int pipe = intel_crtc->pipe;
3278 i915_reg_t reg;
3279 u32 temp;
3280
3281 /* enable normal train */
3282 reg = FDI_TX_CTL(pipe);
3283 temp = I915_READ(reg);
3284 if (IS_IVYBRIDGE(dev)) {
3285 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3286 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3287 } else {
3288 temp &= ~FDI_LINK_TRAIN_NONE;
3289 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3290 }
3291 I915_WRITE(reg, temp);
3292
3293 reg = FDI_RX_CTL(pipe);
3294 temp = I915_READ(reg);
3295 if (HAS_PCH_CPT(dev)) {
3296 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3297 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3298 } else {
3299 temp &= ~FDI_LINK_TRAIN_NONE;
3300 temp |= FDI_LINK_TRAIN_NONE;
3301 }
3302 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3303
3304 /* wait one idle pattern time */
3305 POSTING_READ(reg);
3306 udelay(1000);
3307
3308 /* IVB wants error correction enabled */
3309 if (IS_IVYBRIDGE(dev))
3310 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3311 FDI_FE_ERRC_ENABLE);
3312 }
3313
3314 /* The FDI link training functions for ILK/Ibexpeak. */
3315 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3316 {
3317 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3320 int pipe = intel_crtc->pipe;
3321 i915_reg_t reg;
3322 u32 temp, tries;
3323
3324 /* FDI needs bits from pipe first */
3325 assert_pipe_enabled(dev_priv, pipe);
3326
3327 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3328 for train result */
3329 reg = FDI_RX_IMR(pipe);
3330 temp = I915_READ(reg);
3331 temp &= ~FDI_RX_SYMBOL_LOCK;
3332 temp &= ~FDI_RX_BIT_LOCK;
3333 I915_WRITE(reg, temp);
3334 I915_READ(reg);
3335 udelay(150);
3336
3337 /* enable CPU FDI TX and PCH FDI RX */
3338 reg = FDI_TX_CTL(pipe);
3339 temp = I915_READ(reg);
3340 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3341 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3342 temp &= ~FDI_LINK_TRAIN_NONE;
3343 temp |= FDI_LINK_TRAIN_PATTERN_1;
3344 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3345
3346 reg = FDI_RX_CTL(pipe);
3347 temp = I915_READ(reg);
3348 temp &= ~FDI_LINK_TRAIN_NONE;
3349 temp |= FDI_LINK_TRAIN_PATTERN_1;
3350 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3351
3352 POSTING_READ(reg);
3353 udelay(150);
3354
3355 /* Ironlake workaround, enable clock pointer after FDI enable*/
3356 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3357 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3358 FDI_RX_PHASE_SYNC_POINTER_EN);
3359
3360 reg = FDI_RX_IIR(pipe);
3361 for (tries = 0; tries < 5; tries++) {
3362 temp = I915_READ(reg);
3363 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3364
3365 if ((temp & FDI_RX_BIT_LOCK)) {
3366 DRM_DEBUG_KMS("FDI train 1 done.\n");
3367 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3368 break;
3369 }
3370 }
3371 if (tries == 5)
3372 DRM_ERROR("FDI train 1 fail!\n");
3373
3374 /* Train 2 */
3375 reg = FDI_TX_CTL(pipe);
3376 temp = I915_READ(reg);
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_PATTERN_2;
3379 I915_WRITE(reg, temp);
3380
3381 reg = FDI_RX_CTL(pipe);
3382 temp = I915_READ(reg);
3383 temp &= ~FDI_LINK_TRAIN_NONE;
3384 temp |= FDI_LINK_TRAIN_PATTERN_2;
3385 I915_WRITE(reg, temp);
3386
3387 POSTING_READ(reg);
3388 udelay(150);
3389
3390 reg = FDI_RX_IIR(pipe);
3391 for (tries = 0; tries < 5; tries++) {
3392 temp = I915_READ(reg);
3393 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3394
3395 if (temp & FDI_RX_SYMBOL_LOCK) {
3396 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3397 DRM_DEBUG_KMS("FDI train 2 done.\n");
3398 break;
3399 }
3400 }
3401 if (tries == 5)
3402 DRM_ERROR("FDI train 2 fail!\n");
3403
3404 DRM_DEBUG_KMS("FDI train done\n");
3405
3406 }
3407
3408 static const int snb_b_fdi_train_param[] = {
3409 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3410 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3411 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3412 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3413 };
3414
3415 /* The FDI link training functions for SNB/Cougarpoint. */
3416 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3417 {
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 int pipe = intel_crtc->pipe;
3422 i915_reg_t reg;
3423 u32 temp, i, retry;
3424
3425 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3426 for train result */
3427 reg = FDI_RX_IMR(pipe);
3428 temp = I915_READ(reg);
3429 temp &= ~FDI_RX_SYMBOL_LOCK;
3430 temp &= ~FDI_RX_BIT_LOCK;
3431 I915_WRITE(reg, temp);
3432
3433 POSTING_READ(reg);
3434 udelay(150);
3435
3436 /* enable CPU FDI TX and PCH FDI RX */
3437 reg = FDI_TX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3440 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_1;
3443 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3444 /* SNB-B */
3445 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3446 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3447
3448 I915_WRITE(FDI_RX_MISC(pipe),
3449 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3450
3451 reg = FDI_RX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 if (HAS_PCH_CPT(dev)) {
3454 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3455 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3456 } else {
3457 temp &= ~FDI_LINK_TRAIN_NONE;
3458 temp |= FDI_LINK_TRAIN_PATTERN_1;
3459 }
3460 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3461
3462 POSTING_READ(reg);
3463 udelay(150);
3464
3465 for (i = 0; i < 4; i++) {
3466 reg = FDI_TX_CTL(pipe);
3467 temp = I915_READ(reg);
3468 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3469 temp |= snb_b_fdi_train_param[i];
3470 I915_WRITE(reg, temp);
3471
3472 POSTING_READ(reg);
3473 udelay(500);
3474
3475 for (retry = 0; retry < 5; retry++) {
3476 reg = FDI_RX_IIR(pipe);
3477 temp = I915_READ(reg);
3478 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3479 if (temp & FDI_RX_BIT_LOCK) {
3480 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3481 DRM_DEBUG_KMS("FDI train 1 done.\n");
3482 break;
3483 }
3484 udelay(50);
3485 }
3486 if (retry < 5)
3487 break;
3488 }
3489 if (i == 4)
3490 DRM_ERROR("FDI train 1 fail!\n");
3491
3492 /* Train 2 */
3493 reg = FDI_TX_CTL(pipe);
3494 temp = I915_READ(reg);
3495 temp &= ~FDI_LINK_TRAIN_NONE;
3496 temp |= FDI_LINK_TRAIN_PATTERN_2;
3497 if (IS_GEN6(dev)) {
3498 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3499 /* SNB-B */
3500 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3501 }
3502 I915_WRITE(reg, temp);
3503
3504 reg = FDI_RX_CTL(pipe);
3505 temp = I915_READ(reg);
3506 if (HAS_PCH_CPT(dev)) {
3507 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3508 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3509 } else {
3510 temp &= ~FDI_LINK_TRAIN_NONE;
3511 temp |= FDI_LINK_TRAIN_PATTERN_2;
3512 }
3513 I915_WRITE(reg, temp);
3514
3515 POSTING_READ(reg);
3516 udelay(150);
3517
3518 for (i = 0; i < 4; i++) {
3519 reg = FDI_TX_CTL(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3522 temp |= snb_b_fdi_train_param[i];
3523 I915_WRITE(reg, temp);
3524
3525 POSTING_READ(reg);
3526 udelay(500);
3527
3528 for (retry = 0; retry < 5; retry++) {
3529 reg = FDI_RX_IIR(pipe);
3530 temp = I915_READ(reg);
3531 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3532 if (temp & FDI_RX_SYMBOL_LOCK) {
3533 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3534 DRM_DEBUG_KMS("FDI train 2 done.\n");
3535 break;
3536 }
3537 udelay(50);
3538 }
3539 if (retry < 5)
3540 break;
3541 }
3542 if (i == 4)
3543 DRM_ERROR("FDI train 2 fail!\n");
3544
3545 DRM_DEBUG_KMS("FDI train done.\n");
3546 }
3547
3548 /* Manual link training for Ivy Bridge A0 parts */
3549 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3550 {
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554 int pipe = intel_crtc->pipe;
3555 i915_reg_t reg;
3556 u32 temp, i, j;
3557
3558 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3559 for train result */
3560 reg = FDI_RX_IMR(pipe);
3561 temp = I915_READ(reg);
3562 temp &= ~FDI_RX_SYMBOL_LOCK;
3563 temp &= ~FDI_RX_BIT_LOCK;
3564 I915_WRITE(reg, temp);
3565
3566 POSTING_READ(reg);
3567 udelay(150);
3568
3569 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3570 I915_READ(FDI_RX_IIR(pipe)));
3571
3572 /* Try each vswing and preemphasis setting twice before moving on */
3573 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3574 /* disable first in case we need to retry */
3575 reg = FDI_TX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3578 temp &= ~FDI_TX_ENABLE;
3579 I915_WRITE(reg, temp);
3580
3581 reg = FDI_RX_CTL(pipe);
3582 temp = I915_READ(reg);
3583 temp &= ~FDI_LINK_TRAIN_AUTO;
3584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585 temp &= ~FDI_RX_ENABLE;
3586 I915_WRITE(reg, temp);
3587
3588 /* enable CPU FDI TX and PCH FDI RX */
3589 reg = FDI_TX_CTL(pipe);
3590 temp = I915_READ(reg);
3591 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3592 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3593 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3594 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3595 temp |= snb_b_fdi_train_param[j/2];
3596 temp |= FDI_COMPOSITE_SYNC;
3597 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3598
3599 I915_WRITE(FDI_RX_MISC(pipe),
3600 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3601
3602 reg = FDI_RX_CTL(pipe);
3603 temp = I915_READ(reg);
3604 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3605 temp |= FDI_COMPOSITE_SYNC;
3606 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3607
3608 POSTING_READ(reg);
3609 udelay(1); /* should be 0.5us */
3610
3611 for (i = 0; i < 4; i++) {
3612 reg = FDI_RX_IIR(pipe);
3613 temp = I915_READ(reg);
3614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3615
3616 if (temp & FDI_RX_BIT_LOCK ||
3617 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3618 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3619 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3620 i);
3621 break;
3622 }
3623 udelay(1); /* should be 0.5us */
3624 }
3625 if (i == 4) {
3626 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3627 continue;
3628 }
3629
3630 /* Train 2 */
3631 reg = FDI_TX_CTL(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3634 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3635 I915_WRITE(reg, temp);
3636
3637 reg = FDI_RX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3640 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3641 I915_WRITE(reg, temp);
3642
3643 POSTING_READ(reg);
3644 udelay(2); /* should be 1.5us */
3645
3646 for (i = 0; i < 4; i++) {
3647 reg = FDI_RX_IIR(pipe);
3648 temp = I915_READ(reg);
3649 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3650
3651 if (temp & FDI_RX_SYMBOL_LOCK ||
3652 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3653 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3654 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3655 i);
3656 goto train_done;
3657 }
3658 udelay(2); /* should be 1.5us */
3659 }
3660 if (i == 4)
3661 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3662 }
3663
3664 train_done:
3665 DRM_DEBUG_KMS("FDI train done.\n");
3666 }
3667
3668 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3669 {
3670 struct drm_device *dev = intel_crtc->base.dev;
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3672 int pipe = intel_crtc->pipe;
3673 i915_reg_t reg;
3674 u32 temp;
3675
3676 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3677 reg = FDI_RX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3681 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3682 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3683
3684 POSTING_READ(reg);
3685 udelay(200);
3686
3687 /* Switch from Rawclk to PCDclk */
3688 temp = I915_READ(reg);
3689 I915_WRITE(reg, temp | FDI_PCDCLK);
3690
3691 POSTING_READ(reg);
3692 udelay(200);
3693
3694 /* Enable CPU FDI TX PLL, always on for Ironlake */
3695 reg = FDI_TX_CTL(pipe);
3696 temp = I915_READ(reg);
3697 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3698 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3699
3700 POSTING_READ(reg);
3701 udelay(100);
3702 }
3703 }
3704
3705 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3706 {
3707 struct drm_device *dev = intel_crtc->base.dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709 int pipe = intel_crtc->pipe;
3710 i915_reg_t reg;
3711 u32 temp;
3712
3713 /* Switch from PCDclk to Rawclk */
3714 reg = FDI_RX_CTL(pipe);
3715 temp = I915_READ(reg);
3716 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3717
3718 /* Disable CPU FDI TX PLL */
3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
3721 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3722
3723 POSTING_READ(reg);
3724 udelay(100);
3725
3726 reg = FDI_RX_CTL(pipe);
3727 temp = I915_READ(reg);
3728 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3729
3730 /* Wait for the clocks to turn off. */
3731 POSTING_READ(reg);
3732 udelay(100);
3733 }
3734
3735 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3736 {
3737 struct drm_device *dev = crtc->dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740 int pipe = intel_crtc->pipe;
3741 i915_reg_t reg;
3742 u32 temp;
3743
3744 /* disable CPU FDI tx and PCH FDI rx */
3745 reg = FDI_TX_CTL(pipe);
3746 temp = I915_READ(reg);
3747 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3748 POSTING_READ(reg);
3749
3750 reg = FDI_RX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~(0x7 << 16);
3753 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3754 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3755
3756 POSTING_READ(reg);
3757 udelay(100);
3758
3759 /* Ironlake workaround, disable clock pointer after downing FDI */
3760 if (HAS_PCH_IBX(dev))
3761 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3762
3763 /* still set train pattern 1 */
3764 reg = FDI_TX_CTL(pipe);
3765 temp = I915_READ(reg);
3766 temp &= ~FDI_LINK_TRAIN_NONE;
3767 temp |= FDI_LINK_TRAIN_PATTERN_1;
3768 I915_WRITE(reg, temp);
3769
3770 reg = FDI_RX_CTL(pipe);
3771 temp = I915_READ(reg);
3772 if (HAS_PCH_CPT(dev)) {
3773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3775 } else {
3776 temp &= ~FDI_LINK_TRAIN_NONE;
3777 temp |= FDI_LINK_TRAIN_PATTERN_1;
3778 }
3779 /* BPC in FDI rx is consistent with that in PIPECONF */
3780 temp &= ~(0x07 << 16);
3781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3782 I915_WRITE(reg, temp);
3783
3784 POSTING_READ(reg);
3785 udelay(100);
3786 }
3787
3788 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3789 {
3790 struct intel_crtc *crtc;
3791
3792 /* Note that we don't need to be called with mode_config.lock here
3793 * as our list of CRTC objects is static for the lifetime of the
3794 * device and so cannot disappear as we iterate. Similarly, we can
3795 * happily treat the predicates as racy, atomic checks as userspace
3796 * cannot claim and pin a new fb without at least acquring the
3797 * struct_mutex and so serialising with us.
3798 */
3799 for_each_intel_crtc(dev, crtc) {
3800 if (atomic_read(&crtc->unpin_work_count) == 0)
3801 continue;
3802
3803 if (crtc->flip_work)
3804 intel_wait_for_vblank(dev, crtc->pipe);
3805
3806 return true;
3807 }
3808
3809 return false;
3810 }
3811
3812 static void page_flip_completed(struct intel_crtc *intel_crtc)
3813 {
3814 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3815 struct intel_flip_work *work = intel_crtc->flip_work;
3816
3817 intel_crtc->flip_work = NULL;
3818
3819 if (work->event)
3820 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3821
3822 drm_crtc_vblank_put(&intel_crtc->base);
3823
3824 wake_up_all(&dev_priv->pending_flip_queue);
3825 queue_work(dev_priv->wq, &work->unpin_work);
3826
3827 trace_i915_flip_complete(intel_crtc->plane,
3828 work->pending_flip_obj);
3829 }
3830
3831 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3832 {
3833 struct drm_device *dev = crtc->dev;
3834 struct drm_i915_private *dev_priv = dev->dev_private;
3835 long ret;
3836
3837 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3838
3839 ret = wait_event_interruptible_timeout(
3840 dev_priv->pending_flip_queue,
3841 !intel_crtc_has_pending_flip(crtc),
3842 60*HZ);
3843
3844 if (ret < 0)
3845 return ret;
3846
3847 if (ret == 0) {
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 struct intel_flip_work *work;
3850
3851 spin_lock_irq(&dev->event_lock);
3852 work = intel_crtc->flip_work;
3853 if (work && !is_mmio_work(work)) {
3854 WARN_ONCE(1, "Removing stuck page flip\n");
3855 page_flip_completed(intel_crtc);
3856 }
3857 spin_unlock_irq(&dev->event_lock);
3858 }
3859
3860 return 0;
3861 }
3862
3863 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3864 {
3865 u32 temp;
3866
3867 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3868
3869 mutex_lock(&dev_priv->sb_lock);
3870
3871 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3872 temp |= SBI_SSCCTL_DISABLE;
3873 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3874
3875 mutex_unlock(&dev_priv->sb_lock);
3876 }
3877
3878 /* Program iCLKIP clock to the desired frequency */
3879 static void lpt_program_iclkip(struct drm_crtc *crtc)
3880 {
3881 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3882 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3883 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3884 u32 temp;
3885
3886 lpt_disable_iclkip(dev_priv);
3887
3888 /* The iCLK virtual clock root frequency is in MHz,
3889 * but the adjusted_mode->crtc_clock in in KHz. To get the
3890 * divisors, it is necessary to divide one by another, so we
3891 * convert the virtual clock precision to KHz here for higher
3892 * precision.
3893 */
3894 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3895 u32 iclk_virtual_root_freq = 172800 * 1000;
3896 u32 iclk_pi_range = 64;
3897 u32 desired_divisor;
3898
3899 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3900 clock << auxdiv);
3901 divsel = (desired_divisor / iclk_pi_range) - 2;
3902 phaseinc = desired_divisor % iclk_pi_range;
3903
3904 /*
3905 * Near 20MHz is a corner case which is
3906 * out of range for the 7-bit divisor
3907 */
3908 if (divsel <= 0x7f)
3909 break;
3910 }
3911
3912 /* This should not happen with any sane values */
3913 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3914 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3915 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3916 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3917
3918 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3919 clock,
3920 auxdiv,
3921 divsel,
3922 phasedir,
3923 phaseinc);
3924
3925 mutex_lock(&dev_priv->sb_lock);
3926
3927 /* Program SSCDIVINTPHASE6 */
3928 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3929 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3930 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3931 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3932 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3933 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3934 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3935 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3936
3937 /* Program SSCAUXDIV */
3938 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3939 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3940 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3941 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3942
3943 /* Enable modulator and associated divider */
3944 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3945 temp &= ~SBI_SSCCTL_DISABLE;
3946 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3947
3948 mutex_unlock(&dev_priv->sb_lock);
3949
3950 /* Wait for initialization time */
3951 udelay(24);
3952
3953 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3954 }
3955
3956 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3957 {
3958 u32 divsel, phaseinc, auxdiv;
3959 u32 iclk_virtual_root_freq = 172800 * 1000;
3960 u32 iclk_pi_range = 64;
3961 u32 desired_divisor;
3962 u32 temp;
3963
3964 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3965 return 0;
3966
3967 mutex_lock(&dev_priv->sb_lock);
3968
3969 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3970 if (temp & SBI_SSCCTL_DISABLE) {
3971 mutex_unlock(&dev_priv->sb_lock);
3972 return 0;
3973 }
3974
3975 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3976 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3977 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3978 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3979 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3980
3981 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3982 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3983 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3984
3985 mutex_unlock(&dev_priv->sb_lock);
3986
3987 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3988
3989 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3990 desired_divisor << auxdiv);
3991 }
3992
3993 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3994 enum pipe pch_transcoder)
3995 {
3996 struct drm_device *dev = crtc->base.dev;
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3999
4000 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4001 I915_READ(HTOTAL(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4003 I915_READ(HBLANK(cpu_transcoder)));
4004 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4005 I915_READ(HSYNC(cpu_transcoder)));
4006
4007 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4008 I915_READ(VTOTAL(cpu_transcoder)));
4009 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4010 I915_READ(VBLANK(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4012 I915_READ(VSYNC(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4014 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4015 }
4016
4017 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4018 {
4019 struct drm_i915_private *dev_priv = dev->dev_private;
4020 uint32_t temp;
4021
4022 temp = I915_READ(SOUTH_CHICKEN1);
4023 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4024 return;
4025
4026 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4027 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4028
4029 temp &= ~FDI_BC_BIFURCATION_SELECT;
4030 if (enable)
4031 temp |= FDI_BC_BIFURCATION_SELECT;
4032
4033 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4034 I915_WRITE(SOUTH_CHICKEN1, temp);
4035 POSTING_READ(SOUTH_CHICKEN1);
4036 }
4037
4038 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4039 {
4040 struct drm_device *dev = intel_crtc->base.dev;
4041
4042 switch (intel_crtc->pipe) {
4043 case PIPE_A:
4044 break;
4045 case PIPE_B:
4046 if (intel_crtc->config->fdi_lanes > 2)
4047 cpt_set_fdi_bc_bifurcation(dev, false);
4048 else
4049 cpt_set_fdi_bc_bifurcation(dev, true);
4050
4051 break;
4052 case PIPE_C:
4053 cpt_set_fdi_bc_bifurcation(dev, true);
4054
4055 break;
4056 default:
4057 BUG();
4058 }
4059 }
4060
4061 /* Return which DP Port should be selected for Transcoder DP control */
4062 static enum port
4063 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4064 {
4065 struct drm_device *dev = crtc->dev;
4066 struct intel_encoder *encoder;
4067
4068 for_each_encoder_on_crtc(dev, crtc, encoder) {
4069 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4070 encoder->type == INTEL_OUTPUT_EDP)
4071 return enc_to_dig_port(&encoder->base)->port;
4072 }
4073
4074 return -1;
4075 }
4076
4077 /*
4078 * Enable PCH resources required for PCH ports:
4079 * - PCH PLLs
4080 * - FDI training & RX/TX
4081 * - update transcoder timings
4082 * - DP transcoding bits
4083 * - transcoder
4084 */
4085 static void ironlake_pch_enable(struct drm_crtc *crtc)
4086 {
4087 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4090 int pipe = intel_crtc->pipe;
4091 u32 temp;
4092
4093 assert_pch_transcoder_disabled(dev_priv, pipe);
4094
4095 if (IS_IVYBRIDGE(dev))
4096 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4097
4098 /* Write the TU size bits before fdi link training, so that error
4099 * detection works. */
4100 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4101 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4102
4103 /* For PCH output, training FDI link */
4104 dev_priv->display.fdi_link_train(crtc);
4105
4106 /* We need to program the right clock selection before writing the pixel
4107 * mutliplier into the DPLL. */
4108 if (HAS_PCH_CPT(dev)) {
4109 u32 sel;
4110
4111 temp = I915_READ(PCH_DPLL_SEL);
4112 temp |= TRANS_DPLL_ENABLE(pipe);
4113 sel = TRANS_DPLLB_SEL(pipe);
4114 if (intel_crtc->config->shared_dpll ==
4115 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4116 temp |= sel;
4117 else
4118 temp &= ~sel;
4119 I915_WRITE(PCH_DPLL_SEL, temp);
4120 }
4121
4122 /* XXX: pch pll's can be enabled any time before we enable the PCH
4123 * transcoder, and we actually should do this to not upset any PCH
4124 * transcoder that already use the clock when we share it.
4125 *
4126 * Note that enable_shared_dpll tries to do the right thing, but
4127 * get_shared_dpll unconditionally resets the pll - we need that to have
4128 * the right LVDS enable sequence. */
4129 intel_enable_shared_dpll(intel_crtc);
4130
4131 /* set transcoder timing, panel must allow it */
4132 assert_panel_unlocked(dev_priv, pipe);
4133 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4134
4135 intel_fdi_normal_train(crtc);
4136
4137 /* For PCH DP, enable TRANS_DP_CTL */
4138 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4139 const struct drm_display_mode *adjusted_mode =
4140 &intel_crtc->config->base.adjusted_mode;
4141 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4142 i915_reg_t reg = TRANS_DP_CTL(pipe);
4143 temp = I915_READ(reg);
4144 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4145 TRANS_DP_SYNC_MASK |
4146 TRANS_DP_BPC_MASK);
4147 temp |= TRANS_DP_OUTPUT_ENABLE;
4148 temp |= bpc << 9; /* same format but at 11:9 */
4149
4150 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4151 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4152 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4153 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4154
4155 switch (intel_trans_dp_port_sel(crtc)) {
4156 case PORT_B:
4157 temp |= TRANS_DP_PORT_SEL_B;
4158 break;
4159 case PORT_C:
4160 temp |= TRANS_DP_PORT_SEL_C;
4161 break;
4162 case PORT_D:
4163 temp |= TRANS_DP_PORT_SEL_D;
4164 break;
4165 default:
4166 BUG();
4167 }
4168
4169 I915_WRITE(reg, temp);
4170 }
4171
4172 ironlake_enable_pch_transcoder(dev_priv, pipe);
4173 }
4174
4175 static void lpt_pch_enable(struct drm_crtc *crtc)
4176 {
4177 struct drm_device *dev = crtc->dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4180 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4181
4182 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4183
4184 lpt_program_iclkip(crtc);
4185
4186 /* Set transcoder timing. */
4187 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4188
4189 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4190 }
4191
4192 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4193 {
4194 struct drm_i915_private *dev_priv = dev->dev_private;
4195 i915_reg_t dslreg = PIPEDSL(pipe);
4196 u32 temp;
4197
4198 temp = I915_READ(dslreg);
4199 udelay(500);
4200 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4201 if (wait_for(I915_READ(dslreg) != temp, 5))
4202 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4203 }
4204 }
4205
4206 static int
4207 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4208 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4209 int src_w, int src_h, int dst_w, int dst_h)
4210 {
4211 struct intel_crtc_scaler_state *scaler_state =
4212 &crtc_state->scaler_state;
4213 struct intel_crtc *intel_crtc =
4214 to_intel_crtc(crtc_state->base.crtc);
4215 int need_scaling;
4216
4217 need_scaling = intel_rotation_90_or_270(rotation) ?
4218 (src_h != dst_w || src_w != dst_h):
4219 (src_w != dst_w || src_h != dst_h);
4220
4221 /*
4222 * if plane is being disabled or scaler is no more required or force detach
4223 * - free scaler binded to this plane/crtc
4224 * - in order to do this, update crtc->scaler_usage
4225 *
4226 * Here scaler state in crtc_state is set free so that
4227 * scaler can be assigned to other user. Actual register
4228 * update to free the scaler is done in plane/panel-fit programming.
4229 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4230 */
4231 if (force_detach || !need_scaling) {
4232 if (*scaler_id >= 0) {
4233 scaler_state->scaler_users &= ~(1 << scaler_user);
4234 scaler_state->scalers[*scaler_id].in_use = 0;
4235
4236 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4237 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4238 intel_crtc->pipe, scaler_user, *scaler_id,
4239 scaler_state->scaler_users);
4240 *scaler_id = -1;
4241 }
4242 return 0;
4243 }
4244
4245 /* range checks */
4246 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4247 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4248
4249 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4250 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4251 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4252 "size is out of scaler range\n",
4253 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4254 return -EINVAL;
4255 }
4256
4257 /* mark this plane as a scaler user in crtc_state */
4258 scaler_state->scaler_users |= (1 << scaler_user);
4259 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4260 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4261 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4262 scaler_state->scaler_users);
4263
4264 return 0;
4265 }
4266
4267 /**
4268 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4269 *
4270 * @state: crtc's scaler state
4271 *
4272 * Return
4273 * 0 - scaler_usage updated successfully
4274 * error - requested scaling cannot be supported or other error condition
4275 */
4276 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4277 {
4278 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4279 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4280
4281 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4282 intel_crtc->base.base.id, intel_crtc->base.name,
4283 intel_crtc->pipe, SKL_CRTC_INDEX);
4284
4285 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4286 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4287 state->pipe_src_w, state->pipe_src_h,
4288 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4289 }
4290
4291 /**
4292 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4293 *
4294 * @state: crtc's scaler state
4295 * @plane_state: atomic plane state to update
4296 *
4297 * Return
4298 * 0 - scaler_usage updated successfully
4299 * error - requested scaling cannot be supported or other error condition
4300 */
4301 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4302 struct intel_plane_state *plane_state)
4303 {
4304
4305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4306 struct intel_plane *intel_plane =
4307 to_intel_plane(plane_state->base.plane);
4308 struct drm_framebuffer *fb = plane_state->base.fb;
4309 int ret;
4310
4311 bool force_detach = !fb || !plane_state->visible;
4312
4313 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4314 intel_plane->base.base.id, intel_plane->base.name,
4315 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4316
4317 ret = skl_update_scaler(crtc_state, force_detach,
4318 drm_plane_index(&intel_plane->base),
4319 &plane_state->scaler_id,
4320 plane_state->base.rotation,
4321 drm_rect_width(&plane_state->src) >> 16,
4322 drm_rect_height(&plane_state->src) >> 16,
4323 drm_rect_width(&plane_state->dst),
4324 drm_rect_height(&plane_state->dst));
4325
4326 if (ret || plane_state->scaler_id < 0)
4327 return ret;
4328
4329 /* check colorkey */
4330 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4331 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4332 intel_plane->base.base.id,
4333 intel_plane->base.name);
4334 return -EINVAL;
4335 }
4336
4337 /* Check src format */
4338 switch (fb->pixel_format) {
4339 case DRM_FORMAT_RGB565:
4340 case DRM_FORMAT_XBGR8888:
4341 case DRM_FORMAT_XRGB8888:
4342 case DRM_FORMAT_ABGR8888:
4343 case DRM_FORMAT_ARGB8888:
4344 case DRM_FORMAT_XRGB2101010:
4345 case DRM_FORMAT_XBGR2101010:
4346 case DRM_FORMAT_YUYV:
4347 case DRM_FORMAT_YVYU:
4348 case DRM_FORMAT_UYVY:
4349 case DRM_FORMAT_VYUY:
4350 break;
4351 default:
4352 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4353 intel_plane->base.base.id, intel_plane->base.name,
4354 fb->base.id, fb->pixel_format);
4355 return -EINVAL;
4356 }
4357
4358 return 0;
4359 }
4360
4361 static void skylake_scaler_disable(struct intel_crtc *crtc)
4362 {
4363 int i;
4364
4365 for (i = 0; i < crtc->num_scalers; i++)
4366 skl_detach_scaler(crtc, i);
4367 }
4368
4369 static void skylake_pfit_enable(struct intel_crtc *crtc)
4370 {
4371 struct drm_device *dev = crtc->base.dev;
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 int pipe = crtc->pipe;
4374 struct intel_crtc_scaler_state *scaler_state =
4375 &crtc->config->scaler_state;
4376
4377 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4378
4379 if (crtc->config->pch_pfit.enabled) {
4380 int id;
4381
4382 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4383 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4384 return;
4385 }
4386
4387 id = scaler_state->scaler_id;
4388 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4389 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4390 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4391 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4392
4393 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4394 }
4395 }
4396
4397 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4398 {
4399 struct drm_device *dev = crtc->base.dev;
4400 struct drm_i915_private *dev_priv = dev->dev_private;
4401 int pipe = crtc->pipe;
4402
4403 if (crtc->config->pch_pfit.enabled) {
4404 /* Force use of hard-coded filter coefficients
4405 * as some pre-programmed values are broken,
4406 * e.g. x201.
4407 */
4408 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4409 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4410 PF_PIPE_SEL_IVB(pipe));
4411 else
4412 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4413 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4414 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4415 }
4416 }
4417
4418 void hsw_enable_ips(struct intel_crtc *crtc)
4419 {
4420 struct drm_device *dev = crtc->base.dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422
4423 if (!crtc->config->ips_enabled)
4424 return;
4425
4426 /*
4427 * We can only enable IPS after we enable a plane and wait for a vblank
4428 * This function is called from post_plane_update, which is run after
4429 * a vblank wait.
4430 */
4431
4432 assert_plane_enabled(dev_priv, crtc->plane);
4433 if (IS_BROADWELL(dev)) {
4434 mutex_lock(&dev_priv->rps.hw_lock);
4435 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4436 mutex_unlock(&dev_priv->rps.hw_lock);
4437 /* Quoting Art Runyan: "its not safe to expect any particular
4438 * value in IPS_CTL bit 31 after enabling IPS through the
4439 * mailbox." Moreover, the mailbox may return a bogus state,
4440 * so we need to just enable it and continue on.
4441 */
4442 } else {
4443 I915_WRITE(IPS_CTL, IPS_ENABLE);
4444 /* The bit only becomes 1 in the next vblank, so this wait here
4445 * is essentially intel_wait_for_vblank. If we don't have this
4446 * and don't wait for vblanks until the end of crtc_enable, then
4447 * the HW state readout code will complain that the expected
4448 * IPS_CTL value is not the one we read. */
4449 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4450 DRM_ERROR("Timed out waiting for IPS enable\n");
4451 }
4452 }
4453
4454 void hsw_disable_ips(struct intel_crtc *crtc)
4455 {
4456 struct drm_device *dev = crtc->base.dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458
4459 if (!crtc->config->ips_enabled)
4460 return;
4461
4462 assert_plane_enabled(dev_priv, crtc->plane);
4463 if (IS_BROADWELL(dev)) {
4464 mutex_lock(&dev_priv->rps.hw_lock);
4465 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4466 mutex_unlock(&dev_priv->rps.hw_lock);
4467 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4468 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4469 DRM_ERROR("Timed out waiting for IPS disable\n");
4470 } else {
4471 I915_WRITE(IPS_CTL, 0);
4472 POSTING_READ(IPS_CTL);
4473 }
4474
4475 /* We need to wait for a vblank before we can disable the plane. */
4476 intel_wait_for_vblank(dev, crtc->pipe);
4477 }
4478
4479 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4480 {
4481 if (intel_crtc->overlay) {
4482 struct drm_device *dev = intel_crtc->base.dev;
4483 struct drm_i915_private *dev_priv = dev->dev_private;
4484
4485 mutex_lock(&dev->struct_mutex);
4486 dev_priv->mm.interruptible = false;
4487 (void) intel_overlay_switch_off(intel_crtc->overlay);
4488 dev_priv->mm.interruptible = true;
4489 mutex_unlock(&dev->struct_mutex);
4490 }
4491
4492 /* Let userspace switch the overlay on again. In most cases userspace
4493 * has to recompute where to put it anyway.
4494 */
4495 }
4496
4497 /**
4498 * intel_post_enable_primary - Perform operations after enabling primary plane
4499 * @crtc: the CRTC whose primary plane was just enabled
4500 *
4501 * Performs potentially sleeping operations that must be done after the primary
4502 * plane is enabled, such as updating FBC and IPS. Note that this may be
4503 * called due to an explicit primary plane update, or due to an implicit
4504 * re-enable that is caused when a sprite plane is updated to no longer
4505 * completely hide the primary plane.
4506 */
4507 static void
4508 intel_post_enable_primary(struct drm_crtc *crtc)
4509 {
4510 struct drm_device *dev = crtc->dev;
4511 struct drm_i915_private *dev_priv = dev->dev_private;
4512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4513 int pipe = intel_crtc->pipe;
4514
4515 /*
4516 * FIXME IPS should be fine as long as one plane is
4517 * enabled, but in practice it seems to have problems
4518 * when going from primary only to sprite only and vice
4519 * versa.
4520 */
4521 hsw_enable_ips(intel_crtc);
4522
4523 /*
4524 * Gen2 reports pipe underruns whenever all planes are disabled.
4525 * So don't enable underrun reporting before at least some planes
4526 * are enabled.
4527 * FIXME: Need to fix the logic to work when we turn off all planes
4528 * but leave the pipe running.
4529 */
4530 if (IS_GEN2(dev))
4531 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4532
4533 /* Underruns don't always raise interrupts, so check manually. */
4534 intel_check_cpu_fifo_underruns(dev_priv);
4535 intel_check_pch_fifo_underruns(dev_priv);
4536 }
4537
4538 /* FIXME move all this to pre_plane_update() with proper state tracking */
4539 static void
4540 intel_pre_disable_primary(struct drm_crtc *crtc)
4541 {
4542 struct drm_device *dev = crtc->dev;
4543 struct drm_i915_private *dev_priv = dev->dev_private;
4544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4545 int pipe = intel_crtc->pipe;
4546
4547 /*
4548 * Gen2 reports pipe underruns whenever all planes are disabled.
4549 * So diasble underrun reporting before all the planes get disabled.
4550 * FIXME: Need to fix the logic to work when we turn off all planes
4551 * but leave the pipe running.
4552 */
4553 if (IS_GEN2(dev))
4554 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4555
4556 /*
4557 * FIXME IPS should be fine as long as one plane is
4558 * enabled, but in practice it seems to have problems
4559 * when going from primary only to sprite only and vice
4560 * versa.
4561 */
4562 hsw_disable_ips(intel_crtc);
4563 }
4564
4565 /* FIXME get rid of this and use pre_plane_update */
4566 static void
4567 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4568 {
4569 struct drm_device *dev = crtc->dev;
4570 struct drm_i915_private *dev_priv = dev->dev_private;
4571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4572 int pipe = intel_crtc->pipe;
4573
4574 intel_pre_disable_primary(crtc);
4575
4576 /*
4577 * Vblank time updates from the shadow to live plane control register
4578 * are blocked if the memory self-refresh mode is active at that
4579 * moment. So to make sure the plane gets truly disabled, disable
4580 * first the self-refresh mode. The self-refresh enable bit in turn
4581 * will be checked/applied by the HW only at the next frame start
4582 * event which is after the vblank start event, so we need to have a
4583 * wait-for-vblank between disabling the plane and the pipe.
4584 */
4585 if (HAS_GMCH_DISPLAY(dev)) {
4586 intel_set_memory_cxsr(dev_priv, false);
4587 dev_priv->wm.vlv.cxsr = false;
4588 intel_wait_for_vblank(dev, pipe);
4589 }
4590 }
4591
4592 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4593 {
4594 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4595 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4596 struct intel_crtc_state *pipe_config =
4597 to_intel_crtc_state(crtc->base.state);
4598 struct drm_device *dev = crtc->base.dev;
4599 struct drm_plane *primary = crtc->base.primary;
4600 struct drm_plane_state *old_pri_state =
4601 drm_atomic_get_existing_plane_state(old_state, primary);
4602
4603 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4604
4605 crtc->wm.cxsr_allowed = true;
4606
4607 if (pipe_config->update_wm_post && pipe_config->base.active)
4608 intel_update_watermarks(&crtc->base);
4609
4610 if (old_pri_state) {
4611 struct intel_plane_state *primary_state =
4612 to_intel_plane_state(primary->state);
4613 struct intel_plane_state *old_primary_state =
4614 to_intel_plane_state(old_pri_state);
4615
4616 intel_fbc_post_update(crtc);
4617
4618 if (primary_state->visible &&
4619 (needs_modeset(&pipe_config->base) ||
4620 !old_primary_state->visible))
4621 intel_post_enable_primary(&crtc->base);
4622 }
4623 }
4624
4625 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4626 {
4627 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4628 struct drm_device *dev = crtc->base.dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 struct intel_crtc_state *pipe_config =
4631 to_intel_crtc_state(crtc->base.state);
4632 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4633 struct drm_plane *primary = crtc->base.primary;
4634 struct drm_plane_state *old_pri_state =
4635 drm_atomic_get_existing_plane_state(old_state, primary);
4636 bool modeset = needs_modeset(&pipe_config->base);
4637
4638 if (old_pri_state) {
4639 struct intel_plane_state *primary_state =
4640 to_intel_plane_state(primary->state);
4641 struct intel_plane_state *old_primary_state =
4642 to_intel_plane_state(old_pri_state);
4643
4644 intel_fbc_pre_update(crtc);
4645
4646 if (old_primary_state->visible &&
4647 (modeset || !primary_state->visible))
4648 intel_pre_disable_primary(&crtc->base);
4649 }
4650
4651 if (pipe_config->disable_cxsr) {
4652 crtc->wm.cxsr_allowed = false;
4653
4654 /*
4655 * Vblank time updates from the shadow to live plane control register
4656 * are blocked if the memory self-refresh mode is active at that
4657 * moment. So to make sure the plane gets truly disabled, disable
4658 * first the self-refresh mode. The self-refresh enable bit in turn
4659 * will be checked/applied by the HW only at the next frame start
4660 * event which is after the vblank start event, so we need to have a
4661 * wait-for-vblank between disabling the plane and the pipe.
4662 */
4663 if (old_crtc_state->base.active) {
4664 intel_set_memory_cxsr(dev_priv, false);
4665 dev_priv->wm.vlv.cxsr = false;
4666 intel_wait_for_vblank(dev, crtc->pipe);
4667 }
4668 }
4669
4670 /*
4671 * IVB workaround: must disable low power watermarks for at least
4672 * one frame before enabling scaling. LP watermarks can be re-enabled
4673 * when scaling is disabled.
4674 *
4675 * WaCxSRDisabledForSpriteScaling:ivb
4676 */
4677 if (pipe_config->disable_lp_wm) {
4678 ilk_disable_lp_wm(dev);
4679 intel_wait_for_vblank(dev, crtc->pipe);
4680 }
4681
4682 /*
4683 * If we're doing a modeset, we're done. No need to do any pre-vblank
4684 * watermark programming here.
4685 */
4686 if (needs_modeset(&pipe_config->base))
4687 return;
4688
4689 /*
4690 * For platforms that support atomic watermarks, program the
4691 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4692 * will be the intermediate values that are safe for both pre- and
4693 * post- vblank; when vblank happens, the 'active' values will be set
4694 * to the final 'target' values and we'll do this again to get the
4695 * optimal watermarks. For gen9+ platforms, the values we program here
4696 * will be the final target values which will get automatically latched
4697 * at vblank time; no further programming will be necessary.
4698 *
4699 * If a platform hasn't been transitioned to atomic watermarks yet,
4700 * we'll continue to update watermarks the old way, if flags tell
4701 * us to.
4702 */
4703 if (dev_priv->display.initial_watermarks != NULL)
4704 dev_priv->display.initial_watermarks(pipe_config);
4705 else if (pipe_config->update_wm_pre)
4706 intel_update_watermarks(&crtc->base);
4707 }
4708
4709 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4710 {
4711 struct drm_device *dev = crtc->dev;
4712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713 struct drm_plane *p;
4714 int pipe = intel_crtc->pipe;
4715
4716 intel_crtc_dpms_overlay_disable(intel_crtc);
4717
4718 drm_for_each_plane_mask(p, dev, plane_mask)
4719 to_intel_plane(p)->disable_plane(p, crtc);
4720
4721 /*
4722 * FIXME: Once we grow proper nuclear flip support out of this we need
4723 * to compute the mask of flip planes precisely. For the time being
4724 * consider this a flip to a NULL plane.
4725 */
4726 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4727 }
4728
4729 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4730 {
4731 struct drm_device *dev = crtc->dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734 struct intel_encoder *encoder;
4735 int pipe = intel_crtc->pipe;
4736 struct intel_crtc_state *pipe_config =
4737 to_intel_crtc_state(crtc->state);
4738
4739 if (WARN_ON(intel_crtc->active))
4740 return;
4741
4742 /*
4743 * Sometimes spurious CPU pipe underruns happen during FDI
4744 * training, at least with VGA+HDMI cloning. Suppress them.
4745 *
4746 * On ILK we get an occasional spurious CPU pipe underruns
4747 * between eDP port A enable and vdd enable. Also PCH port
4748 * enable seems to result in the occasional CPU pipe underrun.
4749 *
4750 * Spurious PCH underruns also occur during PCH enabling.
4751 */
4752 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4753 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4754 if (intel_crtc->config->has_pch_encoder)
4755 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4756
4757 if (intel_crtc->config->has_pch_encoder)
4758 intel_prepare_shared_dpll(intel_crtc);
4759
4760 if (intel_crtc->config->has_dp_encoder)
4761 intel_dp_set_m_n(intel_crtc, M1_N1);
4762
4763 intel_set_pipe_timings(intel_crtc);
4764 intel_set_pipe_src_size(intel_crtc);
4765
4766 if (intel_crtc->config->has_pch_encoder) {
4767 intel_cpu_transcoder_set_m_n(intel_crtc,
4768 &intel_crtc->config->fdi_m_n, NULL);
4769 }
4770
4771 ironlake_set_pipeconf(crtc);
4772
4773 intel_crtc->active = true;
4774
4775 for_each_encoder_on_crtc(dev, crtc, encoder)
4776 if (encoder->pre_enable)
4777 encoder->pre_enable(encoder);
4778
4779 if (intel_crtc->config->has_pch_encoder) {
4780 /* Note: FDI PLL enabling _must_ be done before we enable the
4781 * cpu pipes, hence this is separate from all the other fdi/pch
4782 * enabling. */
4783 ironlake_fdi_pll_enable(intel_crtc);
4784 } else {
4785 assert_fdi_tx_disabled(dev_priv, pipe);
4786 assert_fdi_rx_disabled(dev_priv, pipe);
4787 }
4788
4789 ironlake_pfit_enable(intel_crtc);
4790
4791 /*
4792 * On ILK+ LUT must be loaded before the pipe is running but with
4793 * clocks enabled
4794 */
4795 intel_color_load_luts(&pipe_config->base);
4796
4797 if (dev_priv->display.initial_watermarks != NULL)
4798 dev_priv->display.initial_watermarks(intel_crtc->config);
4799 intel_enable_pipe(intel_crtc);
4800
4801 if (intel_crtc->config->has_pch_encoder)
4802 ironlake_pch_enable(crtc);
4803
4804 assert_vblank_disabled(crtc);
4805 drm_crtc_vblank_on(crtc);
4806
4807 for_each_encoder_on_crtc(dev, crtc, encoder)
4808 encoder->enable(encoder);
4809
4810 if (HAS_PCH_CPT(dev))
4811 cpt_verify_modeset(dev, intel_crtc->pipe);
4812
4813 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4814 if (intel_crtc->config->has_pch_encoder)
4815 intel_wait_for_vblank(dev, pipe);
4816 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4817 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4818 }
4819
4820 /* IPS only exists on ULT machines and is tied to pipe A. */
4821 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4822 {
4823 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4824 }
4825
4826 static void haswell_crtc_enable(struct drm_crtc *crtc)
4827 {
4828 struct drm_device *dev = crtc->dev;
4829 struct drm_i915_private *dev_priv = dev->dev_private;
4830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4831 struct intel_encoder *encoder;
4832 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4833 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4834 struct intel_crtc_state *pipe_config =
4835 to_intel_crtc_state(crtc->state);
4836
4837 if (WARN_ON(intel_crtc->active))
4838 return;
4839
4840 if (intel_crtc->config->has_pch_encoder)
4841 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4842 false);
4843
4844 if (intel_crtc->config->shared_dpll)
4845 intel_enable_shared_dpll(intel_crtc);
4846
4847 if (intel_crtc->config->has_dp_encoder)
4848 intel_dp_set_m_n(intel_crtc, M1_N1);
4849
4850 if (!intel_crtc->config->has_dsi_encoder)
4851 intel_set_pipe_timings(intel_crtc);
4852
4853 intel_set_pipe_src_size(intel_crtc);
4854
4855 if (cpu_transcoder != TRANSCODER_EDP &&
4856 !transcoder_is_dsi(cpu_transcoder)) {
4857 I915_WRITE(PIPE_MULT(cpu_transcoder),
4858 intel_crtc->config->pixel_multiplier - 1);
4859 }
4860
4861 if (intel_crtc->config->has_pch_encoder) {
4862 intel_cpu_transcoder_set_m_n(intel_crtc,
4863 &intel_crtc->config->fdi_m_n, NULL);
4864 }
4865
4866 if (!intel_crtc->config->has_dsi_encoder)
4867 haswell_set_pipeconf(crtc);
4868
4869 haswell_set_pipemisc(crtc);
4870
4871 intel_color_set_csc(&pipe_config->base);
4872
4873 intel_crtc->active = true;
4874
4875 if (intel_crtc->config->has_pch_encoder)
4876 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4877 else
4878 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4879
4880 for_each_encoder_on_crtc(dev, crtc, encoder) {
4881 if (encoder->pre_enable)
4882 encoder->pre_enable(encoder);
4883 }
4884
4885 if (intel_crtc->config->has_pch_encoder)
4886 dev_priv->display.fdi_link_train(crtc);
4887
4888 if (!intel_crtc->config->has_dsi_encoder)
4889 intel_ddi_enable_pipe_clock(intel_crtc);
4890
4891 if (INTEL_INFO(dev)->gen >= 9)
4892 skylake_pfit_enable(intel_crtc);
4893 else
4894 ironlake_pfit_enable(intel_crtc);
4895
4896 /*
4897 * On ILK+ LUT must be loaded before the pipe is running but with
4898 * clocks enabled
4899 */
4900 intel_color_load_luts(&pipe_config->base);
4901
4902 intel_ddi_set_pipe_settings(crtc);
4903 if (!intel_crtc->config->has_dsi_encoder)
4904 intel_ddi_enable_transcoder_func(crtc);
4905
4906 if (dev_priv->display.initial_watermarks != NULL)
4907 dev_priv->display.initial_watermarks(pipe_config);
4908 else
4909 intel_update_watermarks(crtc);
4910
4911 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4912 if (!intel_crtc->config->has_dsi_encoder)
4913 intel_enable_pipe(intel_crtc);
4914
4915 if (intel_crtc->config->has_pch_encoder)
4916 lpt_pch_enable(crtc);
4917
4918 if (intel_crtc->config->dp_encoder_is_mst)
4919 intel_ddi_set_vc_payload_alloc(crtc, true);
4920
4921 assert_vblank_disabled(crtc);
4922 drm_crtc_vblank_on(crtc);
4923
4924 for_each_encoder_on_crtc(dev, crtc, encoder) {
4925 encoder->enable(encoder);
4926 intel_opregion_notify_encoder(encoder, true);
4927 }
4928
4929 if (intel_crtc->config->has_pch_encoder) {
4930 intel_wait_for_vblank(dev, pipe);
4931 intel_wait_for_vblank(dev, pipe);
4932 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4933 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4934 true);
4935 }
4936
4937 /* If we change the relative order between pipe/planes enabling, we need
4938 * to change the workaround. */
4939 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4940 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4941 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4942 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4943 }
4944 }
4945
4946 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4947 {
4948 struct drm_device *dev = crtc->base.dev;
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 int pipe = crtc->pipe;
4951
4952 /* To avoid upsetting the power well on haswell only disable the pfit if
4953 * it's in use. The hw state code will make sure we get this right. */
4954 if (force || crtc->config->pch_pfit.enabled) {
4955 I915_WRITE(PF_CTL(pipe), 0);
4956 I915_WRITE(PF_WIN_POS(pipe), 0);
4957 I915_WRITE(PF_WIN_SZ(pipe), 0);
4958 }
4959 }
4960
4961 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4962 {
4963 struct drm_device *dev = crtc->dev;
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4966 struct intel_encoder *encoder;
4967 int pipe = intel_crtc->pipe;
4968
4969 /*
4970 * Sometimes spurious CPU pipe underruns happen when the
4971 * pipe is already disabled, but FDI RX/TX is still enabled.
4972 * Happens at least with VGA+HDMI cloning. Suppress them.
4973 */
4974 if (intel_crtc->config->has_pch_encoder) {
4975 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4976 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4977 }
4978
4979 for_each_encoder_on_crtc(dev, crtc, encoder)
4980 encoder->disable(encoder);
4981
4982 drm_crtc_vblank_off(crtc);
4983 assert_vblank_disabled(crtc);
4984
4985 intel_disable_pipe(intel_crtc);
4986
4987 ironlake_pfit_disable(intel_crtc, false);
4988
4989 if (intel_crtc->config->has_pch_encoder)
4990 ironlake_fdi_disable(crtc);
4991
4992 for_each_encoder_on_crtc(dev, crtc, encoder)
4993 if (encoder->post_disable)
4994 encoder->post_disable(encoder);
4995
4996 if (intel_crtc->config->has_pch_encoder) {
4997 ironlake_disable_pch_transcoder(dev_priv, pipe);
4998
4999 if (HAS_PCH_CPT(dev)) {
5000 i915_reg_t reg;
5001 u32 temp;
5002
5003 /* disable TRANS_DP_CTL */
5004 reg = TRANS_DP_CTL(pipe);
5005 temp = I915_READ(reg);
5006 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5007 TRANS_DP_PORT_SEL_MASK);
5008 temp |= TRANS_DP_PORT_SEL_NONE;
5009 I915_WRITE(reg, temp);
5010
5011 /* disable DPLL_SEL */
5012 temp = I915_READ(PCH_DPLL_SEL);
5013 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5014 I915_WRITE(PCH_DPLL_SEL, temp);
5015 }
5016
5017 ironlake_fdi_pll_disable(intel_crtc);
5018 }
5019
5020 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5021 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5022 }
5023
5024 static void haswell_crtc_disable(struct drm_crtc *crtc)
5025 {
5026 struct drm_device *dev = crtc->dev;
5027 struct drm_i915_private *dev_priv = dev->dev_private;
5028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5029 struct intel_encoder *encoder;
5030 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5031
5032 if (intel_crtc->config->has_pch_encoder)
5033 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5034 false);
5035
5036 for_each_encoder_on_crtc(dev, crtc, encoder) {
5037 intel_opregion_notify_encoder(encoder, false);
5038 encoder->disable(encoder);
5039 }
5040
5041 drm_crtc_vblank_off(crtc);
5042 assert_vblank_disabled(crtc);
5043
5044 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5045 if (!intel_crtc->config->has_dsi_encoder)
5046 intel_disable_pipe(intel_crtc);
5047
5048 if (intel_crtc->config->dp_encoder_is_mst)
5049 intel_ddi_set_vc_payload_alloc(crtc, false);
5050
5051 if (!intel_crtc->config->has_dsi_encoder)
5052 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5053
5054 if (INTEL_INFO(dev)->gen >= 9)
5055 skylake_scaler_disable(intel_crtc);
5056 else
5057 ironlake_pfit_disable(intel_crtc, false);
5058
5059 if (!intel_crtc->config->has_dsi_encoder)
5060 intel_ddi_disable_pipe_clock(intel_crtc);
5061
5062 for_each_encoder_on_crtc(dev, crtc, encoder)
5063 if (encoder->post_disable)
5064 encoder->post_disable(encoder);
5065
5066 if (intel_crtc->config->has_pch_encoder) {
5067 lpt_disable_pch_transcoder(dev_priv);
5068 lpt_disable_iclkip(dev_priv);
5069 intel_ddi_fdi_disable(crtc);
5070
5071 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5072 true);
5073 }
5074 }
5075
5076 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5077 {
5078 struct drm_device *dev = crtc->base.dev;
5079 struct drm_i915_private *dev_priv = dev->dev_private;
5080 struct intel_crtc_state *pipe_config = crtc->config;
5081
5082 if (!pipe_config->gmch_pfit.control)
5083 return;
5084
5085 /*
5086 * The panel fitter should only be adjusted whilst the pipe is disabled,
5087 * according to register description and PRM.
5088 */
5089 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5090 assert_pipe_disabled(dev_priv, crtc->pipe);
5091
5092 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5093 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5094
5095 /* Border color in case we don't scale up to the full screen. Black by
5096 * default, change to something else for debugging. */
5097 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5098 }
5099
5100 static enum intel_display_power_domain port_to_power_domain(enum port port)
5101 {
5102 switch (port) {
5103 case PORT_A:
5104 return POWER_DOMAIN_PORT_DDI_A_LANES;
5105 case PORT_B:
5106 return POWER_DOMAIN_PORT_DDI_B_LANES;
5107 case PORT_C:
5108 return POWER_DOMAIN_PORT_DDI_C_LANES;
5109 case PORT_D:
5110 return POWER_DOMAIN_PORT_DDI_D_LANES;
5111 case PORT_E:
5112 return POWER_DOMAIN_PORT_DDI_E_LANES;
5113 default:
5114 MISSING_CASE(port);
5115 return POWER_DOMAIN_PORT_OTHER;
5116 }
5117 }
5118
5119 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5120 {
5121 switch (port) {
5122 case PORT_A:
5123 return POWER_DOMAIN_AUX_A;
5124 case PORT_B:
5125 return POWER_DOMAIN_AUX_B;
5126 case PORT_C:
5127 return POWER_DOMAIN_AUX_C;
5128 case PORT_D:
5129 return POWER_DOMAIN_AUX_D;
5130 case PORT_E:
5131 /* FIXME: Check VBT for actual wiring of PORT E */
5132 return POWER_DOMAIN_AUX_D;
5133 default:
5134 MISSING_CASE(port);
5135 return POWER_DOMAIN_AUX_A;
5136 }
5137 }
5138
5139 enum intel_display_power_domain
5140 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5141 {
5142 struct drm_device *dev = intel_encoder->base.dev;
5143 struct intel_digital_port *intel_dig_port;
5144
5145 switch (intel_encoder->type) {
5146 case INTEL_OUTPUT_UNKNOWN:
5147 /* Only DDI platforms should ever use this output type */
5148 WARN_ON_ONCE(!HAS_DDI(dev));
5149 case INTEL_OUTPUT_DISPLAYPORT:
5150 case INTEL_OUTPUT_HDMI:
5151 case INTEL_OUTPUT_EDP:
5152 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5153 return port_to_power_domain(intel_dig_port->port);
5154 case INTEL_OUTPUT_DP_MST:
5155 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5156 return port_to_power_domain(intel_dig_port->port);
5157 case INTEL_OUTPUT_ANALOG:
5158 return POWER_DOMAIN_PORT_CRT;
5159 case INTEL_OUTPUT_DSI:
5160 return POWER_DOMAIN_PORT_DSI;
5161 default:
5162 return POWER_DOMAIN_PORT_OTHER;
5163 }
5164 }
5165
5166 enum intel_display_power_domain
5167 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5168 {
5169 struct drm_device *dev = intel_encoder->base.dev;
5170 struct intel_digital_port *intel_dig_port;
5171
5172 switch (intel_encoder->type) {
5173 case INTEL_OUTPUT_UNKNOWN:
5174 case INTEL_OUTPUT_HDMI:
5175 /*
5176 * Only DDI platforms should ever use these output types.
5177 * We can get here after the HDMI detect code has already set
5178 * the type of the shared encoder. Since we can't be sure
5179 * what's the status of the given connectors, play safe and
5180 * run the DP detection too.
5181 */
5182 WARN_ON_ONCE(!HAS_DDI(dev));
5183 case INTEL_OUTPUT_DISPLAYPORT:
5184 case INTEL_OUTPUT_EDP:
5185 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5186 return port_to_aux_power_domain(intel_dig_port->port);
5187 case INTEL_OUTPUT_DP_MST:
5188 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5189 return port_to_aux_power_domain(intel_dig_port->port);
5190 default:
5191 MISSING_CASE(intel_encoder->type);
5192 return POWER_DOMAIN_AUX_A;
5193 }
5194 }
5195
5196 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5197 struct intel_crtc_state *crtc_state)
5198 {
5199 struct drm_device *dev = crtc->dev;
5200 struct drm_encoder *encoder;
5201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5202 enum pipe pipe = intel_crtc->pipe;
5203 unsigned long mask;
5204 enum transcoder transcoder = crtc_state->cpu_transcoder;
5205
5206 if (!crtc_state->base.active)
5207 return 0;
5208
5209 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5210 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5211 if (crtc_state->pch_pfit.enabled ||
5212 crtc_state->pch_pfit.force_thru)
5213 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5214
5215 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5216 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5217
5218 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5219 }
5220
5221 if (crtc_state->shared_dpll)
5222 mask |= BIT(POWER_DOMAIN_PLLS);
5223
5224 return mask;
5225 }
5226
5227 static unsigned long
5228 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5229 struct intel_crtc_state *crtc_state)
5230 {
5231 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5233 enum intel_display_power_domain domain;
5234 unsigned long domains, new_domains, old_domains;
5235
5236 old_domains = intel_crtc->enabled_power_domains;
5237 intel_crtc->enabled_power_domains = new_domains =
5238 get_crtc_power_domains(crtc, crtc_state);
5239
5240 domains = new_domains & ~old_domains;
5241
5242 for_each_power_domain(domain, domains)
5243 intel_display_power_get(dev_priv, domain);
5244
5245 return old_domains & ~new_domains;
5246 }
5247
5248 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5249 unsigned long domains)
5250 {
5251 enum intel_display_power_domain domain;
5252
5253 for_each_power_domain(domain, domains)
5254 intel_display_power_put(dev_priv, domain);
5255 }
5256
5257 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5258 {
5259 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5260
5261 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5262 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5263 return max_cdclk_freq;
5264 else if (IS_CHERRYVIEW(dev_priv))
5265 return max_cdclk_freq*95/100;
5266 else if (INTEL_INFO(dev_priv)->gen < 4)
5267 return 2*max_cdclk_freq*90/100;
5268 else
5269 return max_cdclk_freq*90/100;
5270 }
5271
5272 static int skl_calc_cdclk(int max_pixclk, int vco);
5273
5274 static void intel_update_max_cdclk(struct drm_device *dev)
5275 {
5276 struct drm_i915_private *dev_priv = dev->dev_private;
5277
5278 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5279 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5280 int max_cdclk, vco;
5281
5282 vco = dev_priv->skl_preferred_vco_freq;
5283 WARN_ON(vco != 8100000 && vco != 8640000);
5284
5285 /*
5286 * Use the lower (vco 8640) cdclk values as a
5287 * first guess. skl_calc_cdclk() will correct it
5288 * if the preferred vco is 8100 instead.
5289 */
5290 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5291 max_cdclk = 617143;
5292 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5293 max_cdclk = 540000;
5294 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5295 max_cdclk = 432000;
5296 else
5297 max_cdclk = 308571;
5298
5299 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5300 } else if (IS_BROXTON(dev)) {
5301 dev_priv->max_cdclk_freq = 624000;
5302 } else if (IS_BROADWELL(dev)) {
5303 /*
5304 * FIXME with extra cooling we can allow
5305 * 540 MHz for ULX and 675 Mhz for ULT.
5306 * How can we know if extra cooling is
5307 * available? PCI ID, VTB, something else?
5308 */
5309 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5310 dev_priv->max_cdclk_freq = 450000;
5311 else if (IS_BDW_ULX(dev))
5312 dev_priv->max_cdclk_freq = 450000;
5313 else if (IS_BDW_ULT(dev))
5314 dev_priv->max_cdclk_freq = 540000;
5315 else
5316 dev_priv->max_cdclk_freq = 675000;
5317 } else if (IS_CHERRYVIEW(dev)) {
5318 dev_priv->max_cdclk_freq = 320000;
5319 } else if (IS_VALLEYVIEW(dev)) {
5320 dev_priv->max_cdclk_freq = 400000;
5321 } else {
5322 /* otherwise assume cdclk is fixed */
5323 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5324 }
5325
5326 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5327
5328 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5329 dev_priv->max_cdclk_freq);
5330
5331 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5332 dev_priv->max_dotclk_freq);
5333 }
5334
5335 static void intel_update_cdclk(struct drm_device *dev)
5336 {
5337 struct drm_i915_private *dev_priv = dev->dev_private;
5338
5339 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5340
5341 if (INTEL_GEN(dev_priv) >= 9)
5342 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5343 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5344 dev_priv->cdclk_pll.ref);
5345 else
5346 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5347 dev_priv->cdclk_freq);
5348
5349 /*
5350 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5351 * Programmng [sic] note: bit[9:2] should be programmed to the number
5352 * of cdclk that generates 4MHz reference clock freq which is used to
5353 * generate GMBus clock. This will vary with the cdclk freq.
5354 */
5355 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5356 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5357 }
5358
5359 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5360 static int skl_cdclk_decimal(int cdclk)
5361 {
5362 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5363 }
5364
5365 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5366 {
5367 int ratio;
5368
5369 if (cdclk == dev_priv->cdclk_pll.ref)
5370 return 0;
5371
5372 switch (cdclk) {
5373 default:
5374 MISSING_CASE(cdclk);
5375 case 144000:
5376 case 288000:
5377 case 384000:
5378 case 576000:
5379 ratio = 60;
5380 break;
5381 case 624000:
5382 ratio = 65;
5383 break;
5384 }
5385
5386 return dev_priv->cdclk_pll.ref * ratio;
5387 }
5388
5389 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5390 {
5391 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5392
5393 /* Timeout 200us */
5394 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
5395 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5396
5397 dev_priv->cdclk_pll.vco = 0;
5398 }
5399
5400 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5401 {
5402 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5403 u32 val;
5404
5405 val = I915_READ(BXT_DE_PLL_CTL);
5406 val &= ~BXT_DE_PLL_RATIO_MASK;
5407 val |= BXT_DE_PLL_RATIO(ratio);
5408 I915_WRITE(BXT_DE_PLL_CTL, val);
5409
5410 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5411
5412 /* Timeout 200us */
5413 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
5414 DRM_ERROR("timeout waiting for DE PLL lock\n");
5415
5416 dev_priv->cdclk_pll.vco = vco;
5417 }
5418
5419 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5420 {
5421 u32 val, divider;
5422 int vco, ret;
5423
5424 vco = bxt_de_pll_vco(dev_priv, cdclk);
5425
5426 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5427
5428 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5429 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5430 case 8:
5431 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5432 break;
5433 case 4:
5434 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5435 break;
5436 case 3:
5437 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5438 break;
5439 case 2:
5440 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5441 break;
5442 default:
5443 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5444 WARN_ON(vco != 0);
5445
5446 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5447 break;
5448 }
5449
5450 /* Inform power controller of upcoming frequency change */
5451 mutex_lock(&dev_priv->rps.hw_lock);
5452 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5453 0x80000000);
5454 mutex_unlock(&dev_priv->rps.hw_lock);
5455
5456 if (ret) {
5457 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5458 ret, cdclk);
5459 return;
5460 }
5461
5462 if (dev_priv->cdclk_pll.vco != 0 &&
5463 dev_priv->cdclk_pll.vco != vco)
5464 bxt_de_pll_disable(dev_priv);
5465
5466 if (dev_priv->cdclk_pll.vco != vco)
5467 bxt_de_pll_enable(dev_priv, vco);
5468
5469 val = divider | skl_cdclk_decimal(cdclk);
5470 /*
5471 * FIXME if only the cd2x divider needs changing, it could be done
5472 * without shutting off the pipe (if only one pipe is active).
5473 */
5474 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5475 /*
5476 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5477 * enable otherwise.
5478 */
5479 if (cdclk >= 500000)
5480 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5481 I915_WRITE(CDCLK_CTL, val);
5482
5483 mutex_lock(&dev_priv->rps.hw_lock);
5484 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5485 DIV_ROUND_UP(cdclk, 25000));
5486 mutex_unlock(&dev_priv->rps.hw_lock);
5487
5488 if (ret) {
5489 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5490 ret, cdclk);
5491 return;
5492 }
5493
5494 intel_update_cdclk(dev_priv->dev);
5495 }
5496
5497 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5498 {
5499 u32 cdctl, expected;
5500
5501 intel_update_cdclk(dev_priv->dev);
5502
5503 if (dev_priv->cdclk_pll.vco == 0 ||
5504 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5505 goto sanitize;
5506
5507 /* DPLL okay; verify the cdclock
5508 *
5509 * Some BIOS versions leave an incorrect decimal frequency value and
5510 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5511 * so sanitize this register.
5512 */
5513 cdctl = I915_READ(CDCLK_CTL);
5514 /*
5515 * Let's ignore the pipe field, since BIOS could have configured the
5516 * dividers both synching to an active pipe, or asynchronously
5517 * (PIPE_NONE).
5518 */
5519 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5520
5521 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5522 skl_cdclk_decimal(dev_priv->cdclk_freq);
5523 /*
5524 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5525 * enable otherwise.
5526 */
5527 if (dev_priv->cdclk_freq >= 500000)
5528 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5529
5530 if (cdctl == expected)
5531 /* All well; nothing to sanitize */
5532 return;
5533
5534 sanitize:
5535 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5536
5537 /* force cdclk programming */
5538 dev_priv->cdclk_freq = 0;
5539
5540 /* force full PLL disable + enable */
5541 dev_priv->cdclk_pll.vco = -1;
5542 }
5543
5544 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5545 {
5546 bxt_sanitize_cdclk(dev_priv);
5547
5548 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5549 return;
5550
5551 /*
5552 * FIXME:
5553 * - The initial CDCLK needs to be read from VBT.
5554 * Need to make this change after VBT has changes for BXT.
5555 */
5556 broxton_set_cdclk(dev_priv, broxton_calc_cdclk(0));
5557 }
5558
5559 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5560 {
5561 broxton_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5562 }
5563
5564 static int skl_calc_cdclk(int max_pixclk, int vco)
5565 {
5566 if (vco == 8640000) {
5567 if (max_pixclk > 540000)
5568 return 617143;
5569 else if (max_pixclk > 432000)
5570 return 540000;
5571 else if (max_pixclk > 308571)
5572 return 432000;
5573 else
5574 return 308571;
5575 } else {
5576 if (max_pixclk > 540000)
5577 return 675000;
5578 else if (max_pixclk > 450000)
5579 return 540000;
5580 else if (max_pixclk > 337500)
5581 return 450000;
5582 else
5583 return 337500;
5584 }
5585 }
5586
5587 static void
5588 skl_dpll0_update(struct drm_i915_private *dev_priv)
5589 {
5590 u32 val;
5591
5592 dev_priv->cdclk_pll.ref = 24000;
5593 dev_priv->cdclk_pll.vco = 0;
5594
5595 val = I915_READ(LCPLL1_CTL);
5596 if ((val & LCPLL_PLL_ENABLE) == 0)
5597 return;
5598
5599 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5600 return;
5601
5602 val = I915_READ(DPLL_CTRL1);
5603
5604 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5605 DPLL_CTRL1_SSC(SKL_DPLL0) |
5606 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5607 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5608 return;
5609
5610 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5611 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5612 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5613 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5614 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5615 dev_priv->cdclk_pll.vco = 8100000;
5616 break;
5617 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5618 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5619 dev_priv->cdclk_pll.vco = 8640000;
5620 break;
5621 default:
5622 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5623 break;
5624 }
5625 }
5626
5627 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5628 {
5629 bool changed = dev_priv->skl_preferred_vco_freq != vco;
5630
5631 dev_priv->skl_preferred_vco_freq = vco;
5632
5633 if (changed)
5634 intel_update_max_cdclk(dev_priv->dev);
5635 }
5636
5637 static void
5638 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5639 {
5640 int min_cdclk = skl_calc_cdclk(0, vco);
5641 u32 val;
5642
5643 WARN_ON(vco != 8100000 && vco != 8640000);
5644
5645 /* select the minimum CDCLK before enabling DPLL 0 */
5646 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5647 I915_WRITE(CDCLK_CTL, val);
5648 POSTING_READ(CDCLK_CTL);
5649
5650 /*
5651 * We always enable DPLL0 with the lowest link rate possible, but still
5652 * taking into account the VCO required to operate the eDP panel at the
5653 * desired frequency. The usual DP link rates operate with a VCO of
5654 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5655 * The modeset code is responsible for the selection of the exact link
5656 * rate later on, with the constraint of choosing a frequency that
5657 * works with vco.
5658 */
5659 val = I915_READ(DPLL_CTRL1);
5660
5661 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5662 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5663 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5664 if (vco == 8640000)
5665 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5666 SKL_DPLL0);
5667 else
5668 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5669 SKL_DPLL0);
5670
5671 I915_WRITE(DPLL_CTRL1, val);
5672 POSTING_READ(DPLL_CTRL1);
5673
5674 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5675
5676 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5677 DRM_ERROR("DPLL0 not locked\n");
5678
5679 dev_priv->cdclk_pll.vco = vco;
5680
5681 /* We'll want to keep using the current vco from now on. */
5682 skl_set_preferred_cdclk_vco(dev_priv, vco);
5683 }
5684
5685 static void
5686 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5687 {
5688 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5689 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5690 DRM_ERROR("Couldn't disable DPLL0\n");
5691
5692 dev_priv->cdclk_pll.vco = 0;
5693 }
5694
5695 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5696 {
5697 int ret;
5698 u32 val;
5699
5700 /* inform PCU we want to change CDCLK */
5701 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5702 mutex_lock(&dev_priv->rps.hw_lock);
5703 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5704 mutex_unlock(&dev_priv->rps.hw_lock);
5705
5706 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5707 }
5708
5709 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5710 {
5711 unsigned int i;
5712
5713 for (i = 0; i < 15; i++) {
5714 if (skl_cdclk_pcu_ready(dev_priv))
5715 return true;
5716 udelay(10);
5717 }
5718
5719 return false;
5720 }
5721
5722 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5723 {
5724 struct drm_device *dev = dev_priv->dev;
5725 u32 freq_select, pcu_ack;
5726
5727 WARN_ON((cdclk == 24000) != (vco == 0));
5728
5729 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5730
5731 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5732 DRM_ERROR("failed to inform PCU about cdclk change\n");
5733 return;
5734 }
5735
5736 /* set CDCLK_CTL */
5737 switch (cdclk) {
5738 case 450000:
5739 case 432000:
5740 freq_select = CDCLK_FREQ_450_432;
5741 pcu_ack = 1;
5742 break;
5743 case 540000:
5744 freq_select = CDCLK_FREQ_540;
5745 pcu_ack = 2;
5746 break;
5747 case 308571:
5748 case 337500:
5749 default:
5750 freq_select = CDCLK_FREQ_337_308;
5751 pcu_ack = 0;
5752 break;
5753 case 617143:
5754 case 675000:
5755 freq_select = CDCLK_FREQ_675_617;
5756 pcu_ack = 3;
5757 break;
5758 }
5759
5760 if (dev_priv->cdclk_pll.vco != 0 &&
5761 dev_priv->cdclk_pll.vco != vco)
5762 skl_dpll0_disable(dev_priv);
5763
5764 if (dev_priv->cdclk_pll.vco != vco)
5765 skl_dpll0_enable(dev_priv, vco);
5766
5767 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5768 POSTING_READ(CDCLK_CTL);
5769
5770 /* inform PCU of the change */
5771 mutex_lock(&dev_priv->rps.hw_lock);
5772 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5773 mutex_unlock(&dev_priv->rps.hw_lock);
5774
5775 intel_update_cdclk(dev);
5776 }
5777
5778 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5779
5780 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5781 {
5782 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5783 }
5784
5785 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5786 {
5787 int cdclk, vco;
5788
5789 skl_sanitize_cdclk(dev_priv);
5790
5791 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5792 /*
5793 * Use the current vco as our initial
5794 * guess as to what the preferred vco is.
5795 */
5796 if (dev_priv->skl_preferred_vco_freq == 0)
5797 skl_set_preferred_cdclk_vco(dev_priv,
5798 dev_priv->cdclk_pll.vco);
5799 return;
5800 }
5801
5802 vco = dev_priv->skl_preferred_vco_freq;
5803 if (vco == 0)
5804 vco = 8100000;
5805 cdclk = skl_calc_cdclk(0, vco);
5806
5807 skl_set_cdclk(dev_priv, cdclk, vco);
5808 }
5809
5810 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5811 {
5812 uint32_t cdctl, expected;
5813
5814 /*
5815 * check if the pre-os intialized the display
5816 * There is SWF18 scratchpad register defined which is set by the
5817 * pre-os which can be used by the OS drivers to check the status
5818 */
5819 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5820 goto sanitize;
5821
5822 intel_update_cdclk(dev_priv->dev);
5823 /* Is PLL enabled and locked ? */
5824 if (dev_priv->cdclk_pll.vco == 0 ||
5825 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5826 goto sanitize;
5827
5828 /* DPLL okay; verify the cdclock
5829 *
5830 * Noticed in some instances that the freq selection is correct but
5831 * decimal part is programmed wrong from BIOS where pre-os does not
5832 * enable display. Verify the same as well.
5833 */
5834 cdctl = I915_READ(CDCLK_CTL);
5835 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5836 skl_cdclk_decimal(dev_priv->cdclk_freq);
5837 if (cdctl == expected)
5838 /* All well; nothing to sanitize */
5839 return;
5840
5841 sanitize:
5842 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5843
5844 /* force cdclk programming */
5845 dev_priv->cdclk_freq = 0;
5846 /* force full PLL disable + enable */
5847 dev_priv->cdclk_pll.vco = -1;
5848 }
5849
5850 /* Adjust CDclk dividers to allow high res or save power if possible */
5851 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5852 {
5853 struct drm_i915_private *dev_priv = dev->dev_private;
5854 u32 val, cmd;
5855
5856 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5857 != dev_priv->cdclk_freq);
5858
5859 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5860 cmd = 2;
5861 else if (cdclk == 266667)
5862 cmd = 1;
5863 else
5864 cmd = 0;
5865
5866 mutex_lock(&dev_priv->rps.hw_lock);
5867 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5868 val &= ~DSPFREQGUAR_MASK;
5869 val |= (cmd << DSPFREQGUAR_SHIFT);
5870 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5871 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5872 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5873 50)) {
5874 DRM_ERROR("timed out waiting for CDclk change\n");
5875 }
5876 mutex_unlock(&dev_priv->rps.hw_lock);
5877
5878 mutex_lock(&dev_priv->sb_lock);
5879
5880 if (cdclk == 400000) {
5881 u32 divider;
5882
5883 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5884
5885 /* adjust cdclk divider */
5886 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5887 val &= ~CCK_FREQUENCY_VALUES;
5888 val |= divider;
5889 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5890
5891 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5892 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5893 50))
5894 DRM_ERROR("timed out waiting for CDclk change\n");
5895 }
5896
5897 /* adjust self-refresh exit latency value */
5898 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5899 val &= ~0x7f;
5900
5901 /*
5902 * For high bandwidth configs, we set a higher latency in the bunit
5903 * so that the core display fetch happens in time to avoid underruns.
5904 */
5905 if (cdclk == 400000)
5906 val |= 4500 / 250; /* 4.5 usec */
5907 else
5908 val |= 3000 / 250; /* 3.0 usec */
5909 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5910
5911 mutex_unlock(&dev_priv->sb_lock);
5912
5913 intel_update_cdclk(dev);
5914 }
5915
5916 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5917 {
5918 struct drm_i915_private *dev_priv = dev->dev_private;
5919 u32 val, cmd;
5920
5921 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5922 != dev_priv->cdclk_freq);
5923
5924 switch (cdclk) {
5925 case 333333:
5926 case 320000:
5927 case 266667:
5928 case 200000:
5929 break;
5930 default:
5931 MISSING_CASE(cdclk);
5932 return;
5933 }
5934
5935 /*
5936 * Specs are full of misinformation, but testing on actual
5937 * hardware has shown that we just need to write the desired
5938 * CCK divider into the Punit register.
5939 */
5940 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5941
5942 mutex_lock(&dev_priv->rps.hw_lock);
5943 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5944 val &= ~DSPFREQGUAR_MASK_CHV;
5945 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5946 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5947 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5948 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5949 50)) {
5950 DRM_ERROR("timed out waiting for CDclk change\n");
5951 }
5952 mutex_unlock(&dev_priv->rps.hw_lock);
5953
5954 intel_update_cdclk(dev);
5955 }
5956
5957 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5958 int max_pixclk)
5959 {
5960 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5961 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5962
5963 /*
5964 * Really only a few cases to deal with, as only 4 CDclks are supported:
5965 * 200MHz
5966 * 267MHz
5967 * 320/333MHz (depends on HPLL freq)
5968 * 400MHz (VLV only)
5969 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5970 * of the lower bin and adjust if needed.
5971 *
5972 * We seem to get an unstable or solid color picture at 200MHz.
5973 * Not sure what's wrong. For now use 200MHz only when all pipes
5974 * are off.
5975 */
5976 if (!IS_CHERRYVIEW(dev_priv) &&
5977 max_pixclk > freq_320*limit/100)
5978 return 400000;
5979 else if (max_pixclk > 266667*limit/100)
5980 return freq_320;
5981 else if (max_pixclk > 0)
5982 return 266667;
5983 else
5984 return 200000;
5985 }
5986
5987 static int broxton_calc_cdclk(int max_pixclk)
5988 {
5989 if (max_pixclk > 576000)
5990 return 624000;
5991 else if (max_pixclk > 384000)
5992 return 576000;
5993 else if (max_pixclk > 288000)
5994 return 384000;
5995 else if (max_pixclk > 144000)
5996 return 288000;
5997 else
5998 return 144000;
5999 }
6000
6001 /* Compute the max pixel clock for new configuration. */
6002 static int intel_mode_max_pixclk(struct drm_device *dev,
6003 struct drm_atomic_state *state)
6004 {
6005 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6006 struct drm_i915_private *dev_priv = dev->dev_private;
6007 struct drm_crtc *crtc;
6008 struct drm_crtc_state *crtc_state;
6009 unsigned max_pixclk = 0, i;
6010 enum pipe pipe;
6011
6012 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6013 sizeof(intel_state->min_pixclk));
6014
6015 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6016 int pixclk = 0;
6017
6018 if (crtc_state->enable)
6019 pixclk = crtc_state->adjusted_mode.crtc_clock;
6020
6021 intel_state->min_pixclk[i] = pixclk;
6022 }
6023
6024 for_each_pipe(dev_priv, pipe)
6025 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6026
6027 return max_pixclk;
6028 }
6029
6030 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6031 {
6032 struct drm_device *dev = state->dev;
6033 struct drm_i915_private *dev_priv = dev->dev_private;
6034 int max_pixclk = intel_mode_max_pixclk(dev, state);
6035 struct intel_atomic_state *intel_state =
6036 to_intel_atomic_state(state);
6037
6038 intel_state->cdclk = intel_state->dev_cdclk =
6039 valleyview_calc_cdclk(dev_priv, max_pixclk);
6040
6041 if (!intel_state->active_crtcs)
6042 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6043
6044 return 0;
6045 }
6046
6047 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6048 {
6049 int max_pixclk = ilk_max_pixel_rate(state);
6050 struct intel_atomic_state *intel_state =
6051 to_intel_atomic_state(state);
6052
6053 intel_state->cdclk = intel_state->dev_cdclk =
6054 broxton_calc_cdclk(max_pixclk);
6055
6056 if (!intel_state->active_crtcs)
6057 intel_state->dev_cdclk = broxton_calc_cdclk(0);
6058
6059 return 0;
6060 }
6061
6062 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6063 {
6064 unsigned int credits, default_credits;
6065
6066 if (IS_CHERRYVIEW(dev_priv))
6067 default_credits = PFI_CREDIT(12);
6068 else
6069 default_credits = PFI_CREDIT(8);
6070
6071 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6072 /* CHV suggested value is 31 or 63 */
6073 if (IS_CHERRYVIEW(dev_priv))
6074 credits = PFI_CREDIT_63;
6075 else
6076 credits = PFI_CREDIT(15);
6077 } else {
6078 credits = default_credits;
6079 }
6080
6081 /*
6082 * WA - write default credits before re-programming
6083 * FIXME: should we also set the resend bit here?
6084 */
6085 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6086 default_credits);
6087
6088 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6089 credits | PFI_CREDIT_RESEND);
6090
6091 /*
6092 * FIXME is this guaranteed to clear
6093 * immediately or should we poll for it?
6094 */
6095 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6096 }
6097
6098 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6099 {
6100 struct drm_device *dev = old_state->dev;
6101 struct drm_i915_private *dev_priv = dev->dev_private;
6102 struct intel_atomic_state *old_intel_state =
6103 to_intel_atomic_state(old_state);
6104 unsigned req_cdclk = old_intel_state->dev_cdclk;
6105
6106 /*
6107 * FIXME: We can end up here with all power domains off, yet
6108 * with a CDCLK frequency other than the minimum. To account
6109 * for this take the PIPE-A power domain, which covers the HW
6110 * blocks needed for the following programming. This can be
6111 * removed once it's guaranteed that we get here either with
6112 * the minimum CDCLK set, or the required power domains
6113 * enabled.
6114 */
6115 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6116
6117 if (IS_CHERRYVIEW(dev))
6118 cherryview_set_cdclk(dev, req_cdclk);
6119 else
6120 valleyview_set_cdclk(dev, req_cdclk);
6121
6122 vlv_program_pfi_credits(dev_priv);
6123
6124 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6125 }
6126
6127 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6128 {
6129 struct drm_device *dev = crtc->dev;
6130 struct drm_i915_private *dev_priv = to_i915(dev);
6131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6132 struct intel_encoder *encoder;
6133 struct intel_crtc_state *pipe_config =
6134 to_intel_crtc_state(crtc->state);
6135 int pipe = intel_crtc->pipe;
6136
6137 if (WARN_ON(intel_crtc->active))
6138 return;
6139
6140 if (intel_crtc->config->has_dp_encoder)
6141 intel_dp_set_m_n(intel_crtc, M1_N1);
6142
6143 intel_set_pipe_timings(intel_crtc);
6144 intel_set_pipe_src_size(intel_crtc);
6145
6146 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6147 struct drm_i915_private *dev_priv = dev->dev_private;
6148
6149 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6150 I915_WRITE(CHV_CANVAS(pipe), 0);
6151 }
6152
6153 i9xx_set_pipeconf(intel_crtc);
6154
6155 intel_crtc->active = true;
6156
6157 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6158
6159 for_each_encoder_on_crtc(dev, crtc, encoder)
6160 if (encoder->pre_pll_enable)
6161 encoder->pre_pll_enable(encoder);
6162
6163 if (IS_CHERRYVIEW(dev)) {
6164 chv_prepare_pll(intel_crtc, intel_crtc->config);
6165 chv_enable_pll(intel_crtc, intel_crtc->config);
6166 } else {
6167 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6168 vlv_enable_pll(intel_crtc, intel_crtc->config);
6169 }
6170
6171 for_each_encoder_on_crtc(dev, crtc, encoder)
6172 if (encoder->pre_enable)
6173 encoder->pre_enable(encoder);
6174
6175 i9xx_pfit_enable(intel_crtc);
6176
6177 intel_color_load_luts(&pipe_config->base);
6178
6179 intel_update_watermarks(crtc);
6180 intel_enable_pipe(intel_crtc);
6181
6182 assert_vblank_disabled(crtc);
6183 drm_crtc_vblank_on(crtc);
6184
6185 for_each_encoder_on_crtc(dev, crtc, encoder)
6186 encoder->enable(encoder);
6187 }
6188
6189 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6190 {
6191 struct drm_device *dev = crtc->base.dev;
6192 struct drm_i915_private *dev_priv = dev->dev_private;
6193
6194 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6195 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6196 }
6197
6198 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6199 {
6200 struct drm_device *dev = crtc->dev;
6201 struct drm_i915_private *dev_priv = to_i915(dev);
6202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203 struct intel_encoder *encoder;
6204 struct intel_crtc_state *pipe_config =
6205 to_intel_crtc_state(crtc->state);
6206 enum pipe pipe = intel_crtc->pipe;
6207
6208 if (WARN_ON(intel_crtc->active))
6209 return;
6210
6211 i9xx_set_pll_dividers(intel_crtc);
6212
6213 if (intel_crtc->config->has_dp_encoder)
6214 intel_dp_set_m_n(intel_crtc, M1_N1);
6215
6216 intel_set_pipe_timings(intel_crtc);
6217 intel_set_pipe_src_size(intel_crtc);
6218
6219 i9xx_set_pipeconf(intel_crtc);
6220
6221 intel_crtc->active = true;
6222
6223 if (!IS_GEN2(dev))
6224 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6225
6226 for_each_encoder_on_crtc(dev, crtc, encoder)
6227 if (encoder->pre_enable)
6228 encoder->pre_enable(encoder);
6229
6230 i9xx_enable_pll(intel_crtc);
6231
6232 i9xx_pfit_enable(intel_crtc);
6233
6234 intel_color_load_luts(&pipe_config->base);
6235
6236 intel_update_watermarks(crtc);
6237 intel_enable_pipe(intel_crtc);
6238
6239 assert_vblank_disabled(crtc);
6240 drm_crtc_vblank_on(crtc);
6241
6242 for_each_encoder_on_crtc(dev, crtc, encoder)
6243 encoder->enable(encoder);
6244 }
6245
6246 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6247 {
6248 struct drm_device *dev = crtc->base.dev;
6249 struct drm_i915_private *dev_priv = dev->dev_private;
6250
6251 if (!crtc->config->gmch_pfit.control)
6252 return;
6253
6254 assert_pipe_disabled(dev_priv, crtc->pipe);
6255
6256 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6257 I915_READ(PFIT_CONTROL));
6258 I915_WRITE(PFIT_CONTROL, 0);
6259 }
6260
6261 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6262 {
6263 struct drm_device *dev = crtc->dev;
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6266 struct intel_encoder *encoder;
6267 int pipe = intel_crtc->pipe;
6268
6269 /*
6270 * On gen2 planes are double buffered but the pipe isn't, so we must
6271 * wait for planes to fully turn off before disabling the pipe.
6272 */
6273 if (IS_GEN2(dev))
6274 intel_wait_for_vblank(dev, pipe);
6275
6276 for_each_encoder_on_crtc(dev, crtc, encoder)
6277 encoder->disable(encoder);
6278
6279 drm_crtc_vblank_off(crtc);
6280 assert_vblank_disabled(crtc);
6281
6282 intel_disable_pipe(intel_crtc);
6283
6284 i9xx_pfit_disable(intel_crtc);
6285
6286 for_each_encoder_on_crtc(dev, crtc, encoder)
6287 if (encoder->post_disable)
6288 encoder->post_disable(encoder);
6289
6290 if (!intel_crtc->config->has_dsi_encoder) {
6291 if (IS_CHERRYVIEW(dev))
6292 chv_disable_pll(dev_priv, pipe);
6293 else if (IS_VALLEYVIEW(dev))
6294 vlv_disable_pll(dev_priv, pipe);
6295 else
6296 i9xx_disable_pll(intel_crtc);
6297 }
6298
6299 for_each_encoder_on_crtc(dev, crtc, encoder)
6300 if (encoder->post_pll_disable)
6301 encoder->post_pll_disable(encoder);
6302
6303 if (!IS_GEN2(dev))
6304 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6305 }
6306
6307 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6308 {
6309 struct intel_encoder *encoder;
6310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6311 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6312 enum intel_display_power_domain domain;
6313 unsigned long domains;
6314
6315 if (!intel_crtc->active)
6316 return;
6317
6318 if (to_intel_plane_state(crtc->primary->state)->visible) {
6319 WARN_ON(intel_crtc->flip_work);
6320
6321 intel_pre_disable_primary_noatomic(crtc);
6322
6323 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6324 to_intel_plane_state(crtc->primary->state)->visible = false;
6325 }
6326
6327 dev_priv->display.crtc_disable(crtc);
6328
6329 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6330 crtc->base.id, crtc->name);
6331
6332 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6333 crtc->state->active = false;
6334 intel_crtc->active = false;
6335 crtc->enabled = false;
6336 crtc->state->connector_mask = 0;
6337 crtc->state->encoder_mask = 0;
6338
6339 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6340 encoder->base.crtc = NULL;
6341
6342 intel_fbc_disable(intel_crtc);
6343 intel_update_watermarks(crtc);
6344 intel_disable_shared_dpll(intel_crtc);
6345
6346 domains = intel_crtc->enabled_power_domains;
6347 for_each_power_domain(domain, domains)
6348 intel_display_power_put(dev_priv, domain);
6349 intel_crtc->enabled_power_domains = 0;
6350
6351 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6352 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6353 }
6354
6355 /*
6356 * turn all crtc's off, but do not adjust state
6357 * This has to be paired with a call to intel_modeset_setup_hw_state.
6358 */
6359 int intel_display_suspend(struct drm_device *dev)
6360 {
6361 struct drm_i915_private *dev_priv = to_i915(dev);
6362 struct drm_atomic_state *state;
6363 int ret;
6364
6365 state = drm_atomic_helper_suspend(dev);
6366 ret = PTR_ERR_OR_ZERO(state);
6367 if (ret)
6368 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6369 else
6370 dev_priv->modeset_restore_state = state;
6371 return ret;
6372 }
6373
6374 void intel_encoder_destroy(struct drm_encoder *encoder)
6375 {
6376 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6377
6378 drm_encoder_cleanup(encoder);
6379 kfree(intel_encoder);
6380 }
6381
6382 /* Cross check the actual hw state with our own modeset state tracking (and it's
6383 * internal consistency). */
6384 static void intel_connector_verify_state(struct intel_connector *connector)
6385 {
6386 struct drm_crtc *crtc = connector->base.state->crtc;
6387
6388 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6389 connector->base.base.id,
6390 connector->base.name);
6391
6392 if (connector->get_hw_state(connector)) {
6393 struct intel_encoder *encoder = connector->encoder;
6394 struct drm_connector_state *conn_state = connector->base.state;
6395
6396 I915_STATE_WARN(!crtc,
6397 "connector enabled without attached crtc\n");
6398
6399 if (!crtc)
6400 return;
6401
6402 I915_STATE_WARN(!crtc->state->active,
6403 "connector is active, but attached crtc isn't\n");
6404
6405 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6406 return;
6407
6408 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6409 "atomic encoder doesn't match attached encoder\n");
6410
6411 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6412 "attached encoder crtc differs from connector crtc\n");
6413 } else {
6414 I915_STATE_WARN(crtc && crtc->state->active,
6415 "attached crtc is active, but connector isn't\n");
6416 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6417 "best encoder set without crtc!\n");
6418 }
6419 }
6420
6421 int intel_connector_init(struct intel_connector *connector)
6422 {
6423 drm_atomic_helper_connector_reset(&connector->base);
6424
6425 if (!connector->base.state)
6426 return -ENOMEM;
6427
6428 return 0;
6429 }
6430
6431 struct intel_connector *intel_connector_alloc(void)
6432 {
6433 struct intel_connector *connector;
6434
6435 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6436 if (!connector)
6437 return NULL;
6438
6439 if (intel_connector_init(connector) < 0) {
6440 kfree(connector);
6441 return NULL;
6442 }
6443
6444 return connector;
6445 }
6446
6447 /* Simple connector->get_hw_state implementation for encoders that support only
6448 * one connector and no cloning and hence the encoder state determines the state
6449 * of the connector. */
6450 bool intel_connector_get_hw_state(struct intel_connector *connector)
6451 {
6452 enum pipe pipe = 0;
6453 struct intel_encoder *encoder = connector->encoder;
6454
6455 return encoder->get_hw_state(encoder, &pipe);
6456 }
6457
6458 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6459 {
6460 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6461 return crtc_state->fdi_lanes;
6462
6463 return 0;
6464 }
6465
6466 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6467 struct intel_crtc_state *pipe_config)
6468 {
6469 struct drm_atomic_state *state = pipe_config->base.state;
6470 struct intel_crtc *other_crtc;
6471 struct intel_crtc_state *other_crtc_state;
6472
6473 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6474 pipe_name(pipe), pipe_config->fdi_lanes);
6475 if (pipe_config->fdi_lanes > 4) {
6476 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6477 pipe_name(pipe), pipe_config->fdi_lanes);
6478 return -EINVAL;
6479 }
6480
6481 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6482 if (pipe_config->fdi_lanes > 2) {
6483 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6484 pipe_config->fdi_lanes);
6485 return -EINVAL;
6486 } else {
6487 return 0;
6488 }
6489 }
6490
6491 if (INTEL_INFO(dev)->num_pipes == 2)
6492 return 0;
6493
6494 /* Ivybridge 3 pipe is really complicated */
6495 switch (pipe) {
6496 case PIPE_A:
6497 return 0;
6498 case PIPE_B:
6499 if (pipe_config->fdi_lanes <= 2)
6500 return 0;
6501
6502 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6503 other_crtc_state =
6504 intel_atomic_get_crtc_state(state, other_crtc);
6505 if (IS_ERR(other_crtc_state))
6506 return PTR_ERR(other_crtc_state);
6507
6508 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6509 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6510 pipe_name(pipe), pipe_config->fdi_lanes);
6511 return -EINVAL;
6512 }
6513 return 0;
6514 case PIPE_C:
6515 if (pipe_config->fdi_lanes > 2) {
6516 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6517 pipe_name(pipe), pipe_config->fdi_lanes);
6518 return -EINVAL;
6519 }
6520
6521 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6522 other_crtc_state =
6523 intel_atomic_get_crtc_state(state, other_crtc);
6524 if (IS_ERR(other_crtc_state))
6525 return PTR_ERR(other_crtc_state);
6526
6527 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6528 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6529 return -EINVAL;
6530 }
6531 return 0;
6532 default:
6533 BUG();
6534 }
6535 }
6536
6537 #define RETRY 1
6538 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6539 struct intel_crtc_state *pipe_config)
6540 {
6541 struct drm_device *dev = intel_crtc->base.dev;
6542 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6543 int lane, link_bw, fdi_dotclock, ret;
6544 bool needs_recompute = false;
6545
6546 retry:
6547 /* FDI is a binary signal running at ~2.7GHz, encoding
6548 * each output octet as 10 bits. The actual frequency
6549 * is stored as a divider into a 100MHz clock, and the
6550 * mode pixel clock is stored in units of 1KHz.
6551 * Hence the bw of each lane in terms of the mode signal
6552 * is:
6553 */
6554 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6555
6556 fdi_dotclock = adjusted_mode->crtc_clock;
6557
6558 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6559 pipe_config->pipe_bpp);
6560
6561 pipe_config->fdi_lanes = lane;
6562
6563 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6564 link_bw, &pipe_config->fdi_m_n);
6565
6566 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6567 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6568 pipe_config->pipe_bpp -= 2*3;
6569 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6570 pipe_config->pipe_bpp);
6571 needs_recompute = true;
6572 pipe_config->bw_constrained = true;
6573
6574 goto retry;
6575 }
6576
6577 if (needs_recompute)
6578 return RETRY;
6579
6580 return ret;
6581 }
6582
6583 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6584 struct intel_crtc_state *pipe_config)
6585 {
6586 if (pipe_config->pipe_bpp > 24)
6587 return false;
6588
6589 /* HSW can handle pixel rate up to cdclk? */
6590 if (IS_HASWELL(dev_priv))
6591 return true;
6592
6593 /*
6594 * We compare against max which means we must take
6595 * the increased cdclk requirement into account when
6596 * calculating the new cdclk.
6597 *
6598 * Should measure whether using a lower cdclk w/o IPS
6599 */
6600 return ilk_pipe_pixel_rate(pipe_config) <=
6601 dev_priv->max_cdclk_freq * 95 / 100;
6602 }
6603
6604 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6605 struct intel_crtc_state *pipe_config)
6606 {
6607 struct drm_device *dev = crtc->base.dev;
6608 struct drm_i915_private *dev_priv = dev->dev_private;
6609
6610 pipe_config->ips_enabled = i915.enable_ips &&
6611 hsw_crtc_supports_ips(crtc) &&
6612 pipe_config_supports_ips(dev_priv, pipe_config);
6613 }
6614
6615 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6616 {
6617 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6618
6619 /* GDG double wide on either pipe, otherwise pipe A only */
6620 return INTEL_INFO(dev_priv)->gen < 4 &&
6621 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6622 }
6623
6624 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6625 struct intel_crtc_state *pipe_config)
6626 {
6627 struct drm_device *dev = crtc->base.dev;
6628 struct drm_i915_private *dev_priv = dev->dev_private;
6629 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6630 int clock_limit = dev_priv->max_dotclk_freq;
6631
6632 if (INTEL_INFO(dev)->gen < 4) {
6633 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6634
6635 /*
6636 * Enable double wide mode when the dot clock
6637 * is > 90% of the (display) core speed.
6638 */
6639 if (intel_crtc_supports_double_wide(crtc) &&
6640 adjusted_mode->crtc_clock > clock_limit) {
6641 clock_limit = dev_priv->max_dotclk_freq;
6642 pipe_config->double_wide = true;
6643 }
6644 }
6645
6646 if (adjusted_mode->crtc_clock > clock_limit) {
6647 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6648 adjusted_mode->crtc_clock, clock_limit,
6649 yesno(pipe_config->double_wide));
6650 return -EINVAL;
6651 }
6652
6653 /*
6654 * Pipe horizontal size must be even in:
6655 * - DVO ganged mode
6656 * - LVDS dual channel mode
6657 * - Double wide pipe
6658 */
6659 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6660 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6661 pipe_config->pipe_src_w &= ~1;
6662
6663 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6664 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6665 */
6666 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6667 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6668 return -EINVAL;
6669
6670 if (HAS_IPS(dev))
6671 hsw_compute_ips_config(crtc, pipe_config);
6672
6673 if (pipe_config->has_pch_encoder)
6674 return ironlake_fdi_compute_config(crtc, pipe_config);
6675
6676 return 0;
6677 }
6678
6679 static int skylake_get_display_clock_speed(struct drm_device *dev)
6680 {
6681 struct drm_i915_private *dev_priv = to_i915(dev);
6682 uint32_t cdctl;
6683
6684 skl_dpll0_update(dev_priv);
6685
6686 if (dev_priv->cdclk_pll.vco == 0)
6687 return dev_priv->cdclk_pll.ref;
6688
6689 cdctl = I915_READ(CDCLK_CTL);
6690
6691 if (dev_priv->cdclk_pll.vco == 8640000) {
6692 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6693 case CDCLK_FREQ_450_432:
6694 return 432000;
6695 case CDCLK_FREQ_337_308:
6696 return 308571;
6697 case CDCLK_FREQ_540:
6698 return 540000;
6699 case CDCLK_FREQ_675_617:
6700 return 617143;
6701 default:
6702 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6703 }
6704 } else {
6705 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6706 case CDCLK_FREQ_450_432:
6707 return 450000;
6708 case CDCLK_FREQ_337_308:
6709 return 337500;
6710 case CDCLK_FREQ_540:
6711 return 540000;
6712 case CDCLK_FREQ_675_617:
6713 return 675000;
6714 default:
6715 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6716 }
6717 }
6718
6719 return dev_priv->cdclk_pll.ref;
6720 }
6721
6722 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6723 {
6724 u32 val;
6725
6726 dev_priv->cdclk_pll.ref = 19200;
6727 dev_priv->cdclk_pll.vco = 0;
6728
6729 val = I915_READ(BXT_DE_PLL_ENABLE);
6730 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
6731 return;
6732
6733 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6734 return;
6735
6736 val = I915_READ(BXT_DE_PLL_CTL);
6737 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6738 dev_priv->cdclk_pll.ref;
6739 }
6740
6741 static int broxton_get_display_clock_speed(struct drm_device *dev)
6742 {
6743 struct drm_i915_private *dev_priv = to_i915(dev);
6744 u32 divider;
6745 int div, vco;
6746
6747 bxt_de_pll_update(dev_priv);
6748
6749 vco = dev_priv->cdclk_pll.vco;
6750 if (vco == 0)
6751 return dev_priv->cdclk_pll.ref;
6752
6753 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6754
6755 switch (divider) {
6756 case BXT_CDCLK_CD2X_DIV_SEL_1:
6757 div = 2;
6758 break;
6759 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6760 div = 3;
6761 break;
6762 case BXT_CDCLK_CD2X_DIV_SEL_2:
6763 div = 4;
6764 break;
6765 case BXT_CDCLK_CD2X_DIV_SEL_4:
6766 div = 8;
6767 break;
6768 default:
6769 MISSING_CASE(divider);
6770 return dev_priv->cdclk_pll.ref;
6771 }
6772
6773 return DIV_ROUND_CLOSEST(vco, div);
6774 }
6775
6776 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6777 {
6778 struct drm_i915_private *dev_priv = dev->dev_private;
6779 uint32_t lcpll = I915_READ(LCPLL_CTL);
6780 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6781
6782 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6783 return 800000;
6784 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6785 return 450000;
6786 else if (freq == LCPLL_CLK_FREQ_450)
6787 return 450000;
6788 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6789 return 540000;
6790 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6791 return 337500;
6792 else
6793 return 675000;
6794 }
6795
6796 static int haswell_get_display_clock_speed(struct drm_device *dev)
6797 {
6798 struct drm_i915_private *dev_priv = dev->dev_private;
6799 uint32_t lcpll = I915_READ(LCPLL_CTL);
6800 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6801
6802 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6803 return 800000;
6804 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6805 return 450000;
6806 else if (freq == LCPLL_CLK_FREQ_450)
6807 return 450000;
6808 else if (IS_HSW_ULT(dev))
6809 return 337500;
6810 else
6811 return 540000;
6812 }
6813
6814 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6815 {
6816 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6817 CCK_DISPLAY_CLOCK_CONTROL);
6818 }
6819
6820 static int ilk_get_display_clock_speed(struct drm_device *dev)
6821 {
6822 return 450000;
6823 }
6824
6825 static int i945_get_display_clock_speed(struct drm_device *dev)
6826 {
6827 return 400000;
6828 }
6829
6830 static int i915_get_display_clock_speed(struct drm_device *dev)
6831 {
6832 return 333333;
6833 }
6834
6835 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6836 {
6837 return 200000;
6838 }
6839
6840 static int pnv_get_display_clock_speed(struct drm_device *dev)
6841 {
6842 u16 gcfgc = 0;
6843
6844 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6845
6846 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6847 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6848 return 266667;
6849 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6850 return 333333;
6851 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6852 return 444444;
6853 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6854 return 200000;
6855 default:
6856 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6857 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6858 return 133333;
6859 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6860 return 166667;
6861 }
6862 }
6863
6864 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6865 {
6866 u16 gcfgc = 0;
6867
6868 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6869
6870 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6871 return 133333;
6872 else {
6873 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6874 case GC_DISPLAY_CLOCK_333_MHZ:
6875 return 333333;
6876 default:
6877 case GC_DISPLAY_CLOCK_190_200_MHZ:
6878 return 190000;
6879 }
6880 }
6881 }
6882
6883 static int i865_get_display_clock_speed(struct drm_device *dev)
6884 {
6885 return 266667;
6886 }
6887
6888 static int i85x_get_display_clock_speed(struct drm_device *dev)
6889 {
6890 u16 hpllcc = 0;
6891
6892 /*
6893 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6894 * encoding is different :(
6895 * FIXME is this the right way to detect 852GM/852GMV?
6896 */
6897 if (dev->pdev->revision == 0x1)
6898 return 133333;
6899
6900 pci_bus_read_config_word(dev->pdev->bus,
6901 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6902
6903 /* Assume that the hardware is in the high speed state. This
6904 * should be the default.
6905 */
6906 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6907 case GC_CLOCK_133_200:
6908 case GC_CLOCK_133_200_2:
6909 case GC_CLOCK_100_200:
6910 return 200000;
6911 case GC_CLOCK_166_250:
6912 return 250000;
6913 case GC_CLOCK_100_133:
6914 return 133333;
6915 case GC_CLOCK_133_266:
6916 case GC_CLOCK_133_266_2:
6917 case GC_CLOCK_166_266:
6918 return 266667;
6919 }
6920
6921 /* Shouldn't happen */
6922 return 0;
6923 }
6924
6925 static int i830_get_display_clock_speed(struct drm_device *dev)
6926 {
6927 return 133333;
6928 }
6929
6930 static unsigned int intel_hpll_vco(struct drm_device *dev)
6931 {
6932 struct drm_i915_private *dev_priv = dev->dev_private;
6933 static const unsigned int blb_vco[8] = {
6934 [0] = 3200000,
6935 [1] = 4000000,
6936 [2] = 5333333,
6937 [3] = 4800000,
6938 [4] = 6400000,
6939 };
6940 static const unsigned int pnv_vco[8] = {
6941 [0] = 3200000,
6942 [1] = 4000000,
6943 [2] = 5333333,
6944 [3] = 4800000,
6945 [4] = 2666667,
6946 };
6947 static const unsigned int cl_vco[8] = {
6948 [0] = 3200000,
6949 [1] = 4000000,
6950 [2] = 5333333,
6951 [3] = 6400000,
6952 [4] = 3333333,
6953 [5] = 3566667,
6954 [6] = 4266667,
6955 };
6956 static const unsigned int elk_vco[8] = {
6957 [0] = 3200000,
6958 [1] = 4000000,
6959 [2] = 5333333,
6960 [3] = 4800000,
6961 };
6962 static const unsigned int ctg_vco[8] = {
6963 [0] = 3200000,
6964 [1] = 4000000,
6965 [2] = 5333333,
6966 [3] = 6400000,
6967 [4] = 2666667,
6968 [5] = 4266667,
6969 };
6970 const unsigned int *vco_table;
6971 unsigned int vco;
6972 uint8_t tmp = 0;
6973
6974 /* FIXME other chipsets? */
6975 if (IS_GM45(dev))
6976 vco_table = ctg_vco;
6977 else if (IS_G4X(dev))
6978 vco_table = elk_vco;
6979 else if (IS_CRESTLINE(dev))
6980 vco_table = cl_vco;
6981 else if (IS_PINEVIEW(dev))
6982 vco_table = pnv_vco;
6983 else if (IS_G33(dev))
6984 vco_table = blb_vco;
6985 else
6986 return 0;
6987
6988 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6989
6990 vco = vco_table[tmp & 0x7];
6991 if (vco == 0)
6992 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6993 else
6994 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6995
6996 return vco;
6997 }
6998
6999 static int gm45_get_display_clock_speed(struct drm_device *dev)
7000 {
7001 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7002 uint16_t tmp = 0;
7003
7004 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7005
7006 cdclk_sel = (tmp >> 12) & 0x1;
7007
7008 switch (vco) {
7009 case 2666667:
7010 case 4000000:
7011 case 5333333:
7012 return cdclk_sel ? 333333 : 222222;
7013 case 3200000:
7014 return cdclk_sel ? 320000 : 228571;
7015 default:
7016 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7017 return 222222;
7018 }
7019 }
7020
7021 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7022 {
7023 static const uint8_t div_3200[] = { 16, 10, 8 };
7024 static const uint8_t div_4000[] = { 20, 12, 10 };
7025 static const uint8_t div_5333[] = { 24, 16, 14 };
7026 const uint8_t *div_table;
7027 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7028 uint16_t tmp = 0;
7029
7030 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7031
7032 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7033
7034 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7035 goto fail;
7036
7037 switch (vco) {
7038 case 3200000:
7039 div_table = div_3200;
7040 break;
7041 case 4000000:
7042 div_table = div_4000;
7043 break;
7044 case 5333333:
7045 div_table = div_5333;
7046 break;
7047 default:
7048 goto fail;
7049 }
7050
7051 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7052
7053 fail:
7054 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7055 return 200000;
7056 }
7057
7058 static int g33_get_display_clock_speed(struct drm_device *dev)
7059 {
7060 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7061 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7062 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7063 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7064 const uint8_t *div_table;
7065 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7066 uint16_t tmp = 0;
7067
7068 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7069
7070 cdclk_sel = (tmp >> 4) & 0x7;
7071
7072 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7073 goto fail;
7074
7075 switch (vco) {
7076 case 3200000:
7077 div_table = div_3200;
7078 break;
7079 case 4000000:
7080 div_table = div_4000;
7081 break;
7082 case 4800000:
7083 div_table = div_4800;
7084 break;
7085 case 5333333:
7086 div_table = div_5333;
7087 break;
7088 default:
7089 goto fail;
7090 }
7091
7092 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7093
7094 fail:
7095 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7096 return 190476;
7097 }
7098
7099 static void
7100 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7101 {
7102 while (*num > DATA_LINK_M_N_MASK ||
7103 *den > DATA_LINK_M_N_MASK) {
7104 *num >>= 1;
7105 *den >>= 1;
7106 }
7107 }
7108
7109 static void compute_m_n(unsigned int m, unsigned int n,
7110 uint32_t *ret_m, uint32_t *ret_n)
7111 {
7112 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7113 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7114 intel_reduce_m_n_ratio(ret_m, ret_n);
7115 }
7116
7117 void
7118 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7119 int pixel_clock, int link_clock,
7120 struct intel_link_m_n *m_n)
7121 {
7122 m_n->tu = 64;
7123
7124 compute_m_n(bits_per_pixel * pixel_clock,
7125 link_clock * nlanes * 8,
7126 &m_n->gmch_m, &m_n->gmch_n);
7127
7128 compute_m_n(pixel_clock, link_clock,
7129 &m_n->link_m, &m_n->link_n);
7130 }
7131
7132 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7133 {
7134 if (i915.panel_use_ssc >= 0)
7135 return i915.panel_use_ssc != 0;
7136 return dev_priv->vbt.lvds_use_ssc
7137 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7138 }
7139
7140 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7141 {
7142 return (1 << dpll->n) << 16 | dpll->m2;
7143 }
7144
7145 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7146 {
7147 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7148 }
7149
7150 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7151 struct intel_crtc_state *crtc_state,
7152 struct dpll *reduced_clock)
7153 {
7154 struct drm_device *dev = crtc->base.dev;
7155 u32 fp, fp2 = 0;
7156
7157 if (IS_PINEVIEW(dev)) {
7158 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7159 if (reduced_clock)
7160 fp2 = pnv_dpll_compute_fp(reduced_clock);
7161 } else {
7162 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7163 if (reduced_clock)
7164 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7165 }
7166
7167 crtc_state->dpll_hw_state.fp0 = fp;
7168
7169 crtc->lowfreq_avail = false;
7170 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7171 reduced_clock) {
7172 crtc_state->dpll_hw_state.fp1 = fp2;
7173 crtc->lowfreq_avail = true;
7174 } else {
7175 crtc_state->dpll_hw_state.fp1 = fp;
7176 }
7177 }
7178
7179 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7180 pipe)
7181 {
7182 u32 reg_val;
7183
7184 /*
7185 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7186 * and set it to a reasonable value instead.
7187 */
7188 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7189 reg_val &= 0xffffff00;
7190 reg_val |= 0x00000030;
7191 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7192
7193 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7194 reg_val &= 0x8cffffff;
7195 reg_val = 0x8c000000;
7196 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7197
7198 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7199 reg_val &= 0xffffff00;
7200 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7201
7202 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7203 reg_val &= 0x00ffffff;
7204 reg_val |= 0xb0000000;
7205 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7206 }
7207
7208 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7209 struct intel_link_m_n *m_n)
7210 {
7211 struct drm_device *dev = crtc->base.dev;
7212 struct drm_i915_private *dev_priv = dev->dev_private;
7213 int pipe = crtc->pipe;
7214
7215 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7216 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7217 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7218 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7219 }
7220
7221 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7222 struct intel_link_m_n *m_n,
7223 struct intel_link_m_n *m2_n2)
7224 {
7225 struct drm_device *dev = crtc->base.dev;
7226 struct drm_i915_private *dev_priv = dev->dev_private;
7227 int pipe = crtc->pipe;
7228 enum transcoder transcoder = crtc->config->cpu_transcoder;
7229
7230 if (INTEL_INFO(dev)->gen >= 5) {
7231 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7232 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7233 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7234 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7235 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7236 * for gen < 8) and if DRRS is supported (to make sure the
7237 * registers are not unnecessarily accessed).
7238 */
7239 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7240 crtc->config->has_drrs) {
7241 I915_WRITE(PIPE_DATA_M2(transcoder),
7242 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7243 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7244 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7245 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7246 }
7247 } else {
7248 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7249 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7250 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7251 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7252 }
7253 }
7254
7255 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7256 {
7257 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7258
7259 if (m_n == M1_N1) {
7260 dp_m_n = &crtc->config->dp_m_n;
7261 dp_m2_n2 = &crtc->config->dp_m2_n2;
7262 } else if (m_n == M2_N2) {
7263
7264 /*
7265 * M2_N2 registers are not supported. Hence m2_n2 divider value
7266 * needs to be programmed into M1_N1.
7267 */
7268 dp_m_n = &crtc->config->dp_m2_n2;
7269 } else {
7270 DRM_ERROR("Unsupported divider value\n");
7271 return;
7272 }
7273
7274 if (crtc->config->has_pch_encoder)
7275 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7276 else
7277 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7278 }
7279
7280 static void vlv_compute_dpll(struct intel_crtc *crtc,
7281 struct intel_crtc_state *pipe_config)
7282 {
7283 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7284 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7285 if (crtc->pipe != PIPE_A)
7286 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7287
7288 /* DPLL not used with DSI, but still need the rest set up */
7289 if (!pipe_config->has_dsi_encoder)
7290 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7291 DPLL_EXT_BUFFER_ENABLE_VLV;
7292
7293 pipe_config->dpll_hw_state.dpll_md =
7294 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7295 }
7296
7297 static void chv_compute_dpll(struct intel_crtc *crtc,
7298 struct intel_crtc_state *pipe_config)
7299 {
7300 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7301 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7302 if (crtc->pipe != PIPE_A)
7303 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7304
7305 /* DPLL not used with DSI, but still need the rest set up */
7306 if (!pipe_config->has_dsi_encoder)
7307 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7308
7309 pipe_config->dpll_hw_state.dpll_md =
7310 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7311 }
7312
7313 static void vlv_prepare_pll(struct intel_crtc *crtc,
7314 const struct intel_crtc_state *pipe_config)
7315 {
7316 struct drm_device *dev = crtc->base.dev;
7317 struct drm_i915_private *dev_priv = dev->dev_private;
7318 enum pipe pipe = crtc->pipe;
7319 u32 mdiv;
7320 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7321 u32 coreclk, reg_val;
7322
7323 /* Enable Refclk */
7324 I915_WRITE(DPLL(pipe),
7325 pipe_config->dpll_hw_state.dpll &
7326 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7327
7328 /* No need to actually set up the DPLL with DSI */
7329 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7330 return;
7331
7332 mutex_lock(&dev_priv->sb_lock);
7333
7334 bestn = pipe_config->dpll.n;
7335 bestm1 = pipe_config->dpll.m1;
7336 bestm2 = pipe_config->dpll.m2;
7337 bestp1 = pipe_config->dpll.p1;
7338 bestp2 = pipe_config->dpll.p2;
7339
7340 /* See eDP HDMI DPIO driver vbios notes doc */
7341
7342 /* PLL B needs special handling */
7343 if (pipe == PIPE_B)
7344 vlv_pllb_recal_opamp(dev_priv, pipe);
7345
7346 /* Set up Tx target for periodic Rcomp update */
7347 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7348
7349 /* Disable target IRef on PLL */
7350 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7351 reg_val &= 0x00ffffff;
7352 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7353
7354 /* Disable fast lock */
7355 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7356
7357 /* Set idtafcrecal before PLL is enabled */
7358 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7359 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7360 mdiv |= ((bestn << DPIO_N_SHIFT));
7361 mdiv |= (1 << DPIO_K_SHIFT);
7362
7363 /*
7364 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7365 * but we don't support that).
7366 * Note: don't use the DAC post divider as it seems unstable.
7367 */
7368 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7369 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7370
7371 mdiv |= DPIO_ENABLE_CALIBRATION;
7372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7373
7374 /* Set HBR and RBR LPF coefficients */
7375 if (pipe_config->port_clock == 162000 ||
7376 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7377 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7378 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7379 0x009f0003);
7380 else
7381 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7382 0x00d0000f);
7383
7384 if (pipe_config->has_dp_encoder) {
7385 /* Use SSC source */
7386 if (pipe == PIPE_A)
7387 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7388 0x0df40000);
7389 else
7390 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7391 0x0df70000);
7392 } else { /* HDMI or VGA */
7393 /* Use bend source */
7394 if (pipe == PIPE_A)
7395 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7396 0x0df70000);
7397 else
7398 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7399 0x0df40000);
7400 }
7401
7402 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7403 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7405 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7406 coreclk |= 0x01000000;
7407 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7408
7409 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7410 mutex_unlock(&dev_priv->sb_lock);
7411 }
7412
7413 static void chv_prepare_pll(struct intel_crtc *crtc,
7414 const struct intel_crtc_state *pipe_config)
7415 {
7416 struct drm_device *dev = crtc->base.dev;
7417 struct drm_i915_private *dev_priv = dev->dev_private;
7418 enum pipe pipe = crtc->pipe;
7419 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7420 u32 loopfilter, tribuf_calcntr;
7421 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7422 u32 dpio_val;
7423 int vco;
7424
7425 /* Enable Refclk and SSC */
7426 I915_WRITE(DPLL(pipe),
7427 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7428
7429 /* No need to actually set up the DPLL with DSI */
7430 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7431 return;
7432
7433 bestn = pipe_config->dpll.n;
7434 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7435 bestm1 = pipe_config->dpll.m1;
7436 bestm2 = pipe_config->dpll.m2 >> 22;
7437 bestp1 = pipe_config->dpll.p1;
7438 bestp2 = pipe_config->dpll.p2;
7439 vco = pipe_config->dpll.vco;
7440 dpio_val = 0;
7441 loopfilter = 0;
7442
7443 mutex_lock(&dev_priv->sb_lock);
7444
7445 /* p1 and p2 divider */
7446 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7447 5 << DPIO_CHV_S1_DIV_SHIFT |
7448 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7449 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7450 1 << DPIO_CHV_K_DIV_SHIFT);
7451
7452 /* Feedback post-divider - m2 */
7453 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7454
7455 /* Feedback refclk divider - n and m1 */
7456 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7457 DPIO_CHV_M1_DIV_BY_2 |
7458 1 << DPIO_CHV_N_DIV_SHIFT);
7459
7460 /* M2 fraction division */
7461 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7462
7463 /* M2 fraction division enable */
7464 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7465 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7466 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7467 if (bestm2_frac)
7468 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7469 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7470
7471 /* Program digital lock detect threshold */
7472 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7473 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7474 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7475 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7476 if (!bestm2_frac)
7477 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7478 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7479
7480 /* Loop filter */
7481 if (vco == 5400000) {
7482 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7483 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7484 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7485 tribuf_calcntr = 0x9;
7486 } else if (vco <= 6200000) {
7487 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7488 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7489 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7490 tribuf_calcntr = 0x9;
7491 } else if (vco <= 6480000) {
7492 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7493 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7494 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7495 tribuf_calcntr = 0x8;
7496 } else {
7497 /* Not supported. Apply the same limits as in the max case */
7498 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7499 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7500 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7501 tribuf_calcntr = 0;
7502 }
7503 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7504
7505 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7506 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7507 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7508 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7509
7510 /* AFC Recal */
7511 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7512 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7513 DPIO_AFC_RECAL);
7514
7515 mutex_unlock(&dev_priv->sb_lock);
7516 }
7517
7518 /**
7519 * vlv_force_pll_on - forcibly enable just the PLL
7520 * @dev_priv: i915 private structure
7521 * @pipe: pipe PLL to enable
7522 * @dpll: PLL configuration
7523 *
7524 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7525 * in cases where we need the PLL enabled even when @pipe is not going to
7526 * be enabled.
7527 */
7528 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7529 const struct dpll *dpll)
7530 {
7531 struct intel_crtc *crtc =
7532 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7533 struct intel_crtc_state *pipe_config;
7534
7535 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7536 if (!pipe_config)
7537 return -ENOMEM;
7538
7539 pipe_config->base.crtc = &crtc->base;
7540 pipe_config->pixel_multiplier = 1;
7541 pipe_config->dpll = *dpll;
7542
7543 if (IS_CHERRYVIEW(dev)) {
7544 chv_compute_dpll(crtc, pipe_config);
7545 chv_prepare_pll(crtc, pipe_config);
7546 chv_enable_pll(crtc, pipe_config);
7547 } else {
7548 vlv_compute_dpll(crtc, pipe_config);
7549 vlv_prepare_pll(crtc, pipe_config);
7550 vlv_enable_pll(crtc, pipe_config);
7551 }
7552
7553 kfree(pipe_config);
7554
7555 return 0;
7556 }
7557
7558 /**
7559 * vlv_force_pll_off - forcibly disable just the PLL
7560 * @dev_priv: i915 private structure
7561 * @pipe: pipe PLL to disable
7562 *
7563 * Disable the PLL for @pipe. To be used in cases where we need
7564 * the PLL enabled even when @pipe is not going to be enabled.
7565 */
7566 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7567 {
7568 if (IS_CHERRYVIEW(dev))
7569 chv_disable_pll(to_i915(dev), pipe);
7570 else
7571 vlv_disable_pll(to_i915(dev), pipe);
7572 }
7573
7574 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7575 struct intel_crtc_state *crtc_state,
7576 struct dpll *reduced_clock)
7577 {
7578 struct drm_device *dev = crtc->base.dev;
7579 struct drm_i915_private *dev_priv = dev->dev_private;
7580 u32 dpll;
7581 bool is_sdvo;
7582 struct dpll *clock = &crtc_state->dpll;
7583
7584 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7585
7586 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7587 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7588
7589 dpll = DPLL_VGA_MODE_DIS;
7590
7591 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7592 dpll |= DPLLB_MODE_LVDS;
7593 else
7594 dpll |= DPLLB_MODE_DAC_SERIAL;
7595
7596 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7597 dpll |= (crtc_state->pixel_multiplier - 1)
7598 << SDVO_MULTIPLIER_SHIFT_HIRES;
7599 }
7600
7601 if (is_sdvo)
7602 dpll |= DPLL_SDVO_HIGH_SPEED;
7603
7604 if (crtc_state->has_dp_encoder)
7605 dpll |= DPLL_SDVO_HIGH_SPEED;
7606
7607 /* compute bitmask from p1 value */
7608 if (IS_PINEVIEW(dev))
7609 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7610 else {
7611 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7612 if (IS_G4X(dev) && reduced_clock)
7613 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7614 }
7615 switch (clock->p2) {
7616 case 5:
7617 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7618 break;
7619 case 7:
7620 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7621 break;
7622 case 10:
7623 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7624 break;
7625 case 14:
7626 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7627 break;
7628 }
7629 if (INTEL_INFO(dev)->gen >= 4)
7630 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7631
7632 if (crtc_state->sdvo_tv_clock)
7633 dpll |= PLL_REF_INPUT_TVCLKINBC;
7634 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7635 intel_panel_use_ssc(dev_priv))
7636 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7637 else
7638 dpll |= PLL_REF_INPUT_DREFCLK;
7639
7640 dpll |= DPLL_VCO_ENABLE;
7641 crtc_state->dpll_hw_state.dpll = dpll;
7642
7643 if (INTEL_INFO(dev)->gen >= 4) {
7644 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7645 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7646 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7647 }
7648 }
7649
7650 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7651 struct intel_crtc_state *crtc_state,
7652 struct dpll *reduced_clock)
7653 {
7654 struct drm_device *dev = crtc->base.dev;
7655 struct drm_i915_private *dev_priv = dev->dev_private;
7656 u32 dpll;
7657 struct dpll *clock = &crtc_state->dpll;
7658
7659 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7660
7661 dpll = DPLL_VGA_MODE_DIS;
7662
7663 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7664 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7665 } else {
7666 if (clock->p1 == 2)
7667 dpll |= PLL_P1_DIVIDE_BY_TWO;
7668 else
7669 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7670 if (clock->p2 == 4)
7671 dpll |= PLL_P2_DIVIDE_BY_4;
7672 }
7673
7674 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7675 dpll |= DPLL_DVO_2X_MODE;
7676
7677 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7678 intel_panel_use_ssc(dev_priv))
7679 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7680 else
7681 dpll |= PLL_REF_INPUT_DREFCLK;
7682
7683 dpll |= DPLL_VCO_ENABLE;
7684 crtc_state->dpll_hw_state.dpll = dpll;
7685 }
7686
7687 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7688 {
7689 struct drm_device *dev = intel_crtc->base.dev;
7690 struct drm_i915_private *dev_priv = dev->dev_private;
7691 enum pipe pipe = intel_crtc->pipe;
7692 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7693 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7694 uint32_t crtc_vtotal, crtc_vblank_end;
7695 int vsyncshift = 0;
7696
7697 /* We need to be careful not to changed the adjusted mode, for otherwise
7698 * the hw state checker will get angry at the mismatch. */
7699 crtc_vtotal = adjusted_mode->crtc_vtotal;
7700 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7701
7702 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7703 /* the chip adds 2 halflines automatically */
7704 crtc_vtotal -= 1;
7705 crtc_vblank_end -= 1;
7706
7707 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7708 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7709 else
7710 vsyncshift = adjusted_mode->crtc_hsync_start -
7711 adjusted_mode->crtc_htotal / 2;
7712 if (vsyncshift < 0)
7713 vsyncshift += adjusted_mode->crtc_htotal;
7714 }
7715
7716 if (INTEL_INFO(dev)->gen > 3)
7717 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7718
7719 I915_WRITE(HTOTAL(cpu_transcoder),
7720 (adjusted_mode->crtc_hdisplay - 1) |
7721 ((adjusted_mode->crtc_htotal - 1) << 16));
7722 I915_WRITE(HBLANK(cpu_transcoder),
7723 (adjusted_mode->crtc_hblank_start - 1) |
7724 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7725 I915_WRITE(HSYNC(cpu_transcoder),
7726 (adjusted_mode->crtc_hsync_start - 1) |
7727 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7728
7729 I915_WRITE(VTOTAL(cpu_transcoder),
7730 (adjusted_mode->crtc_vdisplay - 1) |
7731 ((crtc_vtotal - 1) << 16));
7732 I915_WRITE(VBLANK(cpu_transcoder),
7733 (adjusted_mode->crtc_vblank_start - 1) |
7734 ((crtc_vblank_end - 1) << 16));
7735 I915_WRITE(VSYNC(cpu_transcoder),
7736 (adjusted_mode->crtc_vsync_start - 1) |
7737 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7738
7739 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7740 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7741 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7742 * bits. */
7743 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7744 (pipe == PIPE_B || pipe == PIPE_C))
7745 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7746
7747 }
7748
7749 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7750 {
7751 struct drm_device *dev = intel_crtc->base.dev;
7752 struct drm_i915_private *dev_priv = dev->dev_private;
7753 enum pipe pipe = intel_crtc->pipe;
7754
7755 /* pipesrc controls the size that is scaled from, which should
7756 * always be the user's requested size.
7757 */
7758 I915_WRITE(PIPESRC(pipe),
7759 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7760 (intel_crtc->config->pipe_src_h - 1));
7761 }
7762
7763 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7764 struct intel_crtc_state *pipe_config)
7765 {
7766 struct drm_device *dev = crtc->base.dev;
7767 struct drm_i915_private *dev_priv = dev->dev_private;
7768 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7769 uint32_t tmp;
7770
7771 tmp = I915_READ(HTOTAL(cpu_transcoder));
7772 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7773 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7774 tmp = I915_READ(HBLANK(cpu_transcoder));
7775 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7776 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7777 tmp = I915_READ(HSYNC(cpu_transcoder));
7778 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7779 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7780
7781 tmp = I915_READ(VTOTAL(cpu_transcoder));
7782 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7783 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7784 tmp = I915_READ(VBLANK(cpu_transcoder));
7785 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7786 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7787 tmp = I915_READ(VSYNC(cpu_transcoder));
7788 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7789 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7790
7791 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7792 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7793 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7794 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7795 }
7796 }
7797
7798 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7799 struct intel_crtc_state *pipe_config)
7800 {
7801 struct drm_device *dev = crtc->base.dev;
7802 struct drm_i915_private *dev_priv = dev->dev_private;
7803 u32 tmp;
7804
7805 tmp = I915_READ(PIPESRC(crtc->pipe));
7806 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7807 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7808
7809 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7810 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7811 }
7812
7813 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7814 struct intel_crtc_state *pipe_config)
7815 {
7816 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7817 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7818 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7819 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7820
7821 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7822 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7823 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7824 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7825
7826 mode->flags = pipe_config->base.adjusted_mode.flags;
7827 mode->type = DRM_MODE_TYPE_DRIVER;
7828
7829 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7830 mode->flags |= pipe_config->base.adjusted_mode.flags;
7831
7832 mode->hsync = drm_mode_hsync(mode);
7833 mode->vrefresh = drm_mode_vrefresh(mode);
7834 drm_mode_set_name(mode);
7835 }
7836
7837 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7838 {
7839 struct drm_device *dev = intel_crtc->base.dev;
7840 struct drm_i915_private *dev_priv = dev->dev_private;
7841 uint32_t pipeconf;
7842
7843 pipeconf = 0;
7844
7845 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7846 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7847 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7848
7849 if (intel_crtc->config->double_wide)
7850 pipeconf |= PIPECONF_DOUBLE_WIDE;
7851
7852 /* only g4x and later have fancy bpc/dither controls */
7853 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7854 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7855 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7856 pipeconf |= PIPECONF_DITHER_EN |
7857 PIPECONF_DITHER_TYPE_SP;
7858
7859 switch (intel_crtc->config->pipe_bpp) {
7860 case 18:
7861 pipeconf |= PIPECONF_6BPC;
7862 break;
7863 case 24:
7864 pipeconf |= PIPECONF_8BPC;
7865 break;
7866 case 30:
7867 pipeconf |= PIPECONF_10BPC;
7868 break;
7869 default:
7870 /* Case prevented by intel_choose_pipe_bpp_dither. */
7871 BUG();
7872 }
7873 }
7874
7875 if (HAS_PIPE_CXSR(dev)) {
7876 if (intel_crtc->lowfreq_avail) {
7877 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7878 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7879 } else {
7880 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7881 }
7882 }
7883
7884 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7885 if (INTEL_INFO(dev)->gen < 4 ||
7886 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7887 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7888 else
7889 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7890 } else
7891 pipeconf |= PIPECONF_PROGRESSIVE;
7892
7893 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7894 intel_crtc->config->limited_color_range)
7895 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7896
7897 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7898 POSTING_READ(PIPECONF(intel_crtc->pipe));
7899 }
7900
7901 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7902 struct intel_crtc_state *crtc_state)
7903 {
7904 struct drm_device *dev = crtc->base.dev;
7905 struct drm_i915_private *dev_priv = dev->dev_private;
7906 const struct intel_limit *limit;
7907 int refclk = 48000;
7908
7909 memset(&crtc_state->dpll_hw_state, 0,
7910 sizeof(crtc_state->dpll_hw_state));
7911
7912 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7913 if (intel_panel_use_ssc(dev_priv)) {
7914 refclk = dev_priv->vbt.lvds_ssc_freq;
7915 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7916 }
7917
7918 limit = &intel_limits_i8xx_lvds;
7919 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7920 limit = &intel_limits_i8xx_dvo;
7921 } else {
7922 limit = &intel_limits_i8xx_dac;
7923 }
7924
7925 if (!crtc_state->clock_set &&
7926 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7927 refclk, NULL, &crtc_state->dpll)) {
7928 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7929 return -EINVAL;
7930 }
7931
7932 i8xx_compute_dpll(crtc, crtc_state, NULL);
7933
7934 return 0;
7935 }
7936
7937 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7938 struct intel_crtc_state *crtc_state)
7939 {
7940 struct drm_device *dev = crtc->base.dev;
7941 struct drm_i915_private *dev_priv = dev->dev_private;
7942 const struct intel_limit *limit;
7943 int refclk = 96000;
7944
7945 memset(&crtc_state->dpll_hw_state, 0,
7946 sizeof(crtc_state->dpll_hw_state));
7947
7948 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7949 if (intel_panel_use_ssc(dev_priv)) {
7950 refclk = dev_priv->vbt.lvds_ssc_freq;
7951 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7952 }
7953
7954 if (intel_is_dual_link_lvds(dev))
7955 limit = &intel_limits_g4x_dual_channel_lvds;
7956 else
7957 limit = &intel_limits_g4x_single_channel_lvds;
7958 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7959 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7960 limit = &intel_limits_g4x_hdmi;
7961 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7962 limit = &intel_limits_g4x_sdvo;
7963 } else {
7964 /* The option is for other outputs */
7965 limit = &intel_limits_i9xx_sdvo;
7966 }
7967
7968 if (!crtc_state->clock_set &&
7969 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7970 refclk, NULL, &crtc_state->dpll)) {
7971 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7972 return -EINVAL;
7973 }
7974
7975 i9xx_compute_dpll(crtc, crtc_state, NULL);
7976
7977 return 0;
7978 }
7979
7980 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7981 struct intel_crtc_state *crtc_state)
7982 {
7983 struct drm_device *dev = crtc->base.dev;
7984 struct drm_i915_private *dev_priv = dev->dev_private;
7985 const struct intel_limit *limit;
7986 int refclk = 96000;
7987
7988 memset(&crtc_state->dpll_hw_state, 0,
7989 sizeof(crtc_state->dpll_hw_state));
7990
7991 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7992 if (intel_panel_use_ssc(dev_priv)) {
7993 refclk = dev_priv->vbt.lvds_ssc_freq;
7994 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7995 }
7996
7997 limit = &intel_limits_pineview_lvds;
7998 } else {
7999 limit = &intel_limits_pineview_sdvo;
8000 }
8001
8002 if (!crtc_state->clock_set &&
8003 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8004 refclk, NULL, &crtc_state->dpll)) {
8005 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8006 return -EINVAL;
8007 }
8008
8009 i9xx_compute_dpll(crtc, crtc_state, NULL);
8010
8011 return 0;
8012 }
8013
8014 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8015 struct intel_crtc_state *crtc_state)
8016 {
8017 struct drm_device *dev = crtc->base.dev;
8018 struct drm_i915_private *dev_priv = dev->dev_private;
8019 const struct intel_limit *limit;
8020 int refclk = 96000;
8021
8022 memset(&crtc_state->dpll_hw_state, 0,
8023 sizeof(crtc_state->dpll_hw_state));
8024
8025 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8026 if (intel_panel_use_ssc(dev_priv)) {
8027 refclk = dev_priv->vbt.lvds_ssc_freq;
8028 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8029 }
8030
8031 limit = &intel_limits_i9xx_lvds;
8032 } else {
8033 limit = &intel_limits_i9xx_sdvo;
8034 }
8035
8036 if (!crtc_state->clock_set &&
8037 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8038 refclk, NULL, &crtc_state->dpll)) {
8039 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8040 return -EINVAL;
8041 }
8042
8043 i9xx_compute_dpll(crtc, crtc_state, NULL);
8044
8045 return 0;
8046 }
8047
8048 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8049 struct intel_crtc_state *crtc_state)
8050 {
8051 int refclk = 100000;
8052 const struct intel_limit *limit = &intel_limits_chv;
8053
8054 memset(&crtc_state->dpll_hw_state, 0,
8055 sizeof(crtc_state->dpll_hw_state));
8056
8057 if (!crtc_state->clock_set &&
8058 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8059 refclk, NULL, &crtc_state->dpll)) {
8060 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8061 return -EINVAL;
8062 }
8063
8064 chv_compute_dpll(crtc, crtc_state);
8065
8066 return 0;
8067 }
8068
8069 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8070 struct intel_crtc_state *crtc_state)
8071 {
8072 int refclk = 100000;
8073 const struct intel_limit *limit = &intel_limits_vlv;
8074
8075 memset(&crtc_state->dpll_hw_state, 0,
8076 sizeof(crtc_state->dpll_hw_state));
8077
8078 if (!crtc_state->clock_set &&
8079 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8080 refclk, NULL, &crtc_state->dpll)) {
8081 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8082 return -EINVAL;
8083 }
8084
8085 vlv_compute_dpll(crtc, crtc_state);
8086
8087 return 0;
8088 }
8089
8090 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8091 struct intel_crtc_state *pipe_config)
8092 {
8093 struct drm_device *dev = crtc->base.dev;
8094 struct drm_i915_private *dev_priv = dev->dev_private;
8095 uint32_t tmp;
8096
8097 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8098 return;
8099
8100 tmp = I915_READ(PFIT_CONTROL);
8101 if (!(tmp & PFIT_ENABLE))
8102 return;
8103
8104 /* Check whether the pfit is attached to our pipe. */
8105 if (INTEL_INFO(dev)->gen < 4) {
8106 if (crtc->pipe != PIPE_B)
8107 return;
8108 } else {
8109 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8110 return;
8111 }
8112
8113 pipe_config->gmch_pfit.control = tmp;
8114 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8115 }
8116
8117 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8118 struct intel_crtc_state *pipe_config)
8119 {
8120 struct drm_device *dev = crtc->base.dev;
8121 struct drm_i915_private *dev_priv = dev->dev_private;
8122 int pipe = pipe_config->cpu_transcoder;
8123 struct dpll clock;
8124 u32 mdiv;
8125 int refclk = 100000;
8126
8127 /* In case of DSI, DPLL will not be used */
8128 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8129 return;
8130
8131 mutex_lock(&dev_priv->sb_lock);
8132 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8133 mutex_unlock(&dev_priv->sb_lock);
8134
8135 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8136 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8137 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8138 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8139 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8140
8141 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8142 }
8143
8144 static void
8145 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8146 struct intel_initial_plane_config *plane_config)
8147 {
8148 struct drm_device *dev = crtc->base.dev;
8149 struct drm_i915_private *dev_priv = dev->dev_private;
8150 u32 val, base, offset;
8151 int pipe = crtc->pipe, plane = crtc->plane;
8152 int fourcc, pixel_format;
8153 unsigned int aligned_height;
8154 struct drm_framebuffer *fb;
8155 struct intel_framebuffer *intel_fb;
8156
8157 val = I915_READ(DSPCNTR(plane));
8158 if (!(val & DISPLAY_PLANE_ENABLE))
8159 return;
8160
8161 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8162 if (!intel_fb) {
8163 DRM_DEBUG_KMS("failed to alloc fb\n");
8164 return;
8165 }
8166
8167 fb = &intel_fb->base;
8168
8169 if (INTEL_INFO(dev)->gen >= 4) {
8170 if (val & DISPPLANE_TILED) {
8171 plane_config->tiling = I915_TILING_X;
8172 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8173 }
8174 }
8175
8176 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8177 fourcc = i9xx_format_to_fourcc(pixel_format);
8178 fb->pixel_format = fourcc;
8179 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8180
8181 if (INTEL_INFO(dev)->gen >= 4) {
8182 if (plane_config->tiling)
8183 offset = I915_READ(DSPTILEOFF(plane));
8184 else
8185 offset = I915_READ(DSPLINOFF(plane));
8186 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8187 } else {
8188 base = I915_READ(DSPADDR(plane));
8189 }
8190 plane_config->base = base;
8191
8192 val = I915_READ(PIPESRC(pipe));
8193 fb->width = ((val >> 16) & 0xfff) + 1;
8194 fb->height = ((val >> 0) & 0xfff) + 1;
8195
8196 val = I915_READ(DSPSTRIDE(pipe));
8197 fb->pitches[0] = val & 0xffffffc0;
8198
8199 aligned_height = intel_fb_align_height(dev, fb->height,
8200 fb->pixel_format,
8201 fb->modifier[0]);
8202
8203 plane_config->size = fb->pitches[0] * aligned_height;
8204
8205 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8206 pipe_name(pipe), plane, fb->width, fb->height,
8207 fb->bits_per_pixel, base, fb->pitches[0],
8208 plane_config->size);
8209
8210 plane_config->fb = intel_fb;
8211 }
8212
8213 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8214 struct intel_crtc_state *pipe_config)
8215 {
8216 struct drm_device *dev = crtc->base.dev;
8217 struct drm_i915_private *dev_priv = dev->dev_private;
8218 int pipe = pipe_config->cpu_transcoder;
8219 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8220 struct dpll clock;
8221 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8222 int refclk = 100000;
8223
8224 /* In case of DSI, DPLL will not be used */
8225 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8226 return;
8227
8228 mutex_lock(&dev_priv->sb_lock);
8229 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8230 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8231 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8232 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8233 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8234 mutex_unlock(&dev_priv->sb_lock);
8235
8236 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8237 clock.m2 = (pll_dw0 & 0xff) << 22;
8238 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8239 clock.m2 |= pll_dw2 & 0x3fffff;
8240 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8241 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8242 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8243
8244 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8245 }
8246
8247 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8248 struct intel_crtc_state *pipe_config)
8249 {
8250 struct drm_device *dev = crtc->base.dev;
8251 struct drm_i915_private *dev_priv = dev->dev_private;
8252 enum intel_display_power_domain power_domain;
8253 uint32_t tmp;
8254 bool ret;
8255
8256 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8257 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8258 return false;
8259
8260 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8261 pipe_config->shared_dpll = NULL;
8262
8263 ret = false;
8264
8265 tmp = I915_READ(PIPECONF(crtc->pipe));
8266 if (!(tmp & PIPECONF_ENABLE))
8267 goto out;
8268
8269 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8270 switch (tmp & PIPECONF_BPC_MASK) {
8271 case PIPECONF_6BPC:
8272 pipe_config->pipe_bpp = 18;
8273 break;
8274 case PIPECONF_8BPC:
8275 pipe_config->pipe_bpp = 24;
8276 break;
8277 case PIPECONF_10BPC:
8278 pipe_config->pipe_bpp = 30;
8279 break;
8280 default:
8281 break;
8282 }
8283 }
8284
8285 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8286 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8287 pipe_config->limited_color_range = true;
8288
8289 if (INTEL_INFO(dev)->gen < 4)
8290 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8291
8292 intel_get_pipe_timings(crtc, pipe_config);
8293 intel_get_pipe_src_size(crtc, pipe_config);
8294
8295 i9xx_get_pfit_config(crtc, pipe_config);
8296
8297 if (INTEL_INFO(dev)->gen >= 4) {
8298 /* No way to read it out on pipes B and C */
8299 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8300 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8301 else
8302 tmp = I915_READ(DPLL_MD(crtc->pipe));
8303 pipe_config->pixel_multiplier =
8304 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8305 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8306 pipe_config->dpll_hw_state.dpll_md = tmp;
8307 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8308 tmp = I915_READ(DPLL(crtc->pipe));
8309 pipe_config->pixel_multiplier =
8310 ((tmp & SDVO_MULTIPLIER_MASK)
8311 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8312 } else {
8313 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8314 * port and will be fixed up in the encoder->get_config
8315 * function. */
8316 pipe_config->pixel_multiplier = 1;
8317 }
8318 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8319 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8320 /*
8321 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8322 * on 830. Filter it out here so that we don't
8323 * report errors due to that.
8324 */
8325 if (IS_I830(dev))
8326 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8327
8328 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8329 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8330 } else {
8331 /* Mask out read-only status bits. */
8332 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8333 DPLL_PORTC_READY_MASK |
8334 DPLL_PORTB_READY_MASK);
8335 }
8336
8337 if (IS_CHERRYVIEW(dev))
8338 chv_crtc_clock_get(crtc, pipe_config);
8339 else if (IS_VALLEYVIEW(dev))
8340 vlv_crtc_clock_get(crtc, pipe_config);
8341 else
8342 i9xx_crtc_clock_get(crtc, pipe_config);
8343
8344 /*
8345 * Normally the dotclock is filled in by the encoder .get_config()
8346 * but in case the pipe is enabled w/o any ports we need a sane
8347 * default.
8348 */
8349 pipe_config->base.adjusted_mode.crtc_clock =
8350 pipe_config->port_clock / pipe_config->pixel_multiplier;
8351
8352 ret = true;
8353
8354 out:
8355 intel_display_power_put(dev_priv, power_domain);
8356
8357 return ret;
8358 }
8359
8360 static void ironlake_init_pch_refclk(struct drm_device *dev)
8361 {
8362 struct drm_i915_private *dev_priv = dev->dev_private;
8363 struct intel_encoder *encoder;
8364 int i;
8365 u32 val, final;
8366 bool has_lvds = false;
8367 bool has_cpu_edp = false;
8368 bool has_panel = false;
8369 bool has_ck505 = false;
8370 bool can_ssc = false;
8371 bool using_ssc_source = false;
8372
8373 /* We need to take the global config into account */
8374 for_each_intel_encoder(dev, encoder) {
8375 switch (encoder->type) {
8376 case INTEL_OUTPUT_LVDS:
8377 has_panel = true;
8378 has_lvds = true;
8379 break;
8380 case INTEL_OUTPUT_EDP:
8381 has_panel = true;
8382 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8383 has_cpu_edp = true;
8384 break;
8385 default:
8386 break;
8387 }
8388 }
8389
8390 if (HAS_PCH_IBX(dev)) {
8391 has_ck505 = dev_priv->vbt.display_clock_mode;
8392 can_ssc = has_ck505;
8393 } else {
8394 has_ck505 = false;
8395 can_ssc = true;
8396 }
8397
8398 /* Check if any DPLLs are using the SSC source */
8399 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8400 u32 temp = I915_READ(PCH_DPLL(i));
8401
8402 if (!(temp & DPLL_VCO_ENABLE))
8403 continue;
8404
8405 if ((temp & PLL_REF_INPUT_MASK) ==
8406 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8407 using_ssc_source = true;
8408 break;
8409 }
8410 }
8411
8412 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8413 has_panel, has_lvds, has_ck505, using_ssc_source);
8414
8415 /* Ironlake: try to setup display ref clock before DPLL
8416 * enabling. This is only under driver's control after
8417 * PCH B stepping, previous chipset stepping should be
8418 * ignoring this setting.
8419 */
8420 val = I915_READ(PCH_DREF_CONTROL);
8421
8422 /* As we must carefully and slowly disable/enable each source in turn,
8423 * compute the final state we want first and check if we need to
8424 * make any changes at all.
8425 */
8426 final = val;
8427 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8428 if (has_ck505)
8429 final |= DREF_NONSPREAD_CK505_ENABLE;
8430 else
8431 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8432
8433 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8434
8435 if (!using_ssc_source) {
8436 final &= ~DREF_SSC_SOURCE_MASK;
8437 final &= ~DREF_SSC1_ENABLE;
8438 }
8439
8440 if (has_panel) {
8441 final |= DREF_SSC_SOURCE_ENABLE;
8442
8443 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8444 final |= DREF_SSC1_ENABLE;
8445
8446 if (has_cpu_edp) {
8447 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8448 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8449 else
8450 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8451 } else
8452 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8453 } else {
8454 final |= DREF_SSC_SOURCE_DISABLE;
8455 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8456 }
8457
8458 if (final == val)
8459 return;
8460
8461 /* Always enable nonspread source */
8462 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8463
8464 if (has_ck505)
8465 val |= DREF_NONSPREAD_CK505_ENABLE;
8466 else
8467 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8468
8469 if (has_panel) {
8470 val &= ~DREF_SSC_SOURCE_MASK;
8471 val |= DREF_SSC_SOURCE_ENABLE;
8472
8473 /* SSC must be turned on before enabling the CPU output */
8474 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8475 DRM_DEBUG_KMS("Using SSC on panel\n");
8476 val |= DREF_SSC1_ENABLE;
8477 } else
8478 val &= ~DREF_SSC1_ENABLE;
8479
8480 /* Get SSC going before enabling the outputs */
8481 I915_WRITE(PCH_DREF_CONTROL, val);
8482 POSTING_READ(PCH_DREF_CONTROL);
8483 udelay(200);
8484
8485 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8486
8487 /* Enable CPU source on CPU attached eDP */
8488 if (has_cpu_edp) {
8489 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8490 DRM_DEBUG_KMS("Using SSC on eDP\n");
8491 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8492 } else
8493 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8494 } else
8495 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8496
8497 I915_WRITE(PCH_DREF_CONTROL, val);
8498 POSTING_READ(PCH_DREF_CONTROL);
8499 udelay(200);
8500 } else {
8501 DRM_DEBUG_KMS("Disabling CPU source output\n");
8502
8503 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8504
8505 /* Turn off CPU output */
8506 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8507
8508 I915_WRITE(PCH_DREF_CONTROL, val);
8509 POSTING_READ(PCH_DREF_CONTROL);
8510 udelay(200);
8511
8512 if (!using_ssc_source) {
8513 DRM_DEBUG_KMS("Disabling SSC source\n");
8514
8515 /* Turn off the SSC source */
8516 val &= ~DREF_SSC_SOURCE_MASK;
8517 val |= DREF_SSC_SOURCE_DISABLE;
8518
8519 /* Turn off SSC1 */
8520 val &= ~DREF_SSC1_ENABLE;
8521
8522 I915_WRITE(PCH_DREF_CONTROL, val);
8523 POSTING_READ(PCH_DREF_CONTROL);
8524 udelay(200);
8525 }
8526 }
8527
8528 BUG_ON(val != final);
8529 }
8530
8531 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8532 {
8533 uint32_t tmp;
8534
8535 tmp = I915_READ(SOUTH_CHICKEN2);
8536 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8537 I915_WRITE(SOUTH_CHICKEN2, tmp);
8538
8539 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8540 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8541 DRM_ERROR("FDI mPHY reset assert timeout\n");
8542
8543 tmp = I915_READ(SOUTH_CHICKEN2);
8544 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8545 I915_WRITE(SOUTH_CHICKEN2, tmp);
8546
8547 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8548 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8549 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8550 }
8551
8552 /* WaMPhyProgramming:hsw */
8553 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8554 {
8555 uint32_t tmp;
8556
8557 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8558 tmp &= ~(0xFF << 24);
8559 tmp |= (0x12 << 24);
8560 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8561
8562 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8563 tmp |= (1 << 11);
8564 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8565
8566 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8567 tmp |= (1 << 11);
8568 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8569
8570 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8571 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8572 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8573
8574 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8575 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8576 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8577
8578 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8579 tmp &= ~(7 << 13);
8580 tmp |= (5 << 13);
8581 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8582
8583 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8584 tmp &= ~(7 << 13);
8585 tmp |= (5 << 13);
8586 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8587
8588 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8589 tmp &= ~0xFF;
8590 tmp |= 0x1C;
8591 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8592
8593 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8594 tmp &= ~0xFF;
8595 tmp |= 0x1C;
8596 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8597
8598 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8599 tmp &= ~(0xFF << 16);
8600 tmp |= (0x1C << 16);
8601 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8602
8603 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8604 tmp &= ~(0xFF << 16);
8605 tmp |= (0x1C << 16);
8606 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8607
8608 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8609 tmp |= (1 << 27);
8610 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8611
8612 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8613 tmp |= (1 << 27);
8614 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8615
8616 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8617 tmp &= ~(0xF << 28);
8618 tmp |= (4 << 28);
8619 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8620
8621 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8622 tmp &= ~(0xF << 28);
8623 tmp |= (4 << 28);
8624 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8625 }
8626
8627 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8628 * Programming" based on the parameters passed:
8629 * - Sequence to enable CLKOUT_DP
8630 * - Sequence to enable CLKOUT_DP without spread
8631 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8632 */
8633 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8634 bool with_fdi)
8635 {
8636 struct drm_i915_private *dev_priv = dev->dev_private;
8637 uint32_t reg, tmp;
8638
8639 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8640 with_spread = true;
8641 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8642 with_fdi = false;
8643
8644 mutex_lock(&dev_priv->sb_lock);
8645
8646 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8647 tmp &= ~SBI_SSCCTL_DISABLE;
8648 tmp |= SBI_SSCCTL_PATHALT;
8649 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8650
8651 udelay(24);
8652
8653 if (with_spread) {
8654 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8655 tmp &= ~SBI_SSCCTL_PATHALT;
8656 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8657
8658 if (with_fdi) {
8659 lpt_reset_fdi_mphy(dev_priv);
8660 lpt_program_fdi_mphy(dev_priv);
8661 }
8662 }
8663
8664 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8665 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8666 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8667 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8668
8669 mutex_unlock(&dev_priv->sb_lock);
8670 }
8671
8672 /* Sequence to disable CLKOUT_DP */
8673 static void lpt_disable_clkout_dp(struct drm_device *dev)
8674 {
8675 struct drm_i915_private *dev_priv = dev->dev_private;
8676 uint32_t reg, tmp;
8677
8678 mutex_lock(&dev_priv->sb_lock);
8679
8680 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8681 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8682 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8683 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8684
8685 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8686 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8687 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8688 tmp |= SBI_SSCCTL_PATHALT;
8689 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8690 udelay(32);
8691 }
8692 tmp |= SBI_SSCCTL_DISABLE;
8693 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8694 }
8695
8696 mutex_unlock(&dev_priv->sb_lock);
8697 }
8698
8699 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8700
8701 static const uint16_t sscdivintphase[] = {
8702 [BEND_IDX( 50)] = 0x3B23,
8703 [BEND_IDX( 45)] = 0x3B23,
8704 [BEND_IDX( 40)] = 0x3C23,
8705 [BEND_IDX( 35)] = 0x3C23,
8706 [BEND_IDX( 30)] = 0x3D23,
8707 [BEND_IDX( 25)] = 0x3D23,
8708 [BEND_IDX( 20)] = 0x3E23,
8709 [BEND_IDX( 15)] = 0x3E23,
8710 [BEND_IDX( 10)] = 0x3F23,
8711 [BEND_IDX( 5)] = 0x3F23,
8712 [BEND_IDX( 0)] = 0x0025,
8713 [BEND_IDX( -5)] = 0x0025,
8714 [BEND_IDX(-10)] = 0x0125,
8715 [BEND_IDX(-15)] = 0x0125,
8716 [BEND_IDX(-20)] = 0x0225,
8717 [BEND_IDX(-25)] = 0x0225,
8718 [BEND_IDX(-30)] = 0x0325,
8719 [BEND_IDX(-35)] = 0x0325,
8720 [BEND_IDX(-40)] = 0x0425,
8721 [BEND_IDX(-45)] = 0x0425,
8722 [BEND_IDX(-50)] = 0x0525,
8723 };
8724
8725 /*
8726 * Bend CLKOUT_DP
8727 * steps -50 to 50 inclusive, in steps of 5
8728 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8729 * change in clock period = -(steps / 10) * 5.787 ps
8730 */
8731 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8732 {
8733 uint32_t tmp;
8734 int idx = BEND_IDX(steps);
8735
8736 if (WARN_ON(steps % 5 != 0))
8737 return;
8738
8739 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8740 return;
8741
8742 mutex_lock(&dev_priv->sb_lock);
8743
8744 if (steps % 10 != 0)
8745 tmp = 0xAAAAAAAB;
8746 else
8747 tmp = 0x00000000;
8748 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8749
8750 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8751 tmp &= 0xffff0000;
8752 tmp |= sscdivintphase[idx];
8753 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8754
8755 mutex_unlock(&dev_priv->sb_lock);
8756 }
8757
8758 #undef BEND_IDX
8759
8760 static void lpt_init_pch_refclk(struct drm_device *dev)
8761 {
8762 struct intel_encoder *encoder;
8763 bool has_vga = false;
8764
8765 for_each_intel_encoder(dev, encoder) {
8766 switch (encoder->type) {
8767 case INTEL_OUTPUT_ANALOG:
8768 has_vga = true;
8769 break;
8770 default:
8771 break;
8772 }
8773 }
8774
8775 if (has_vga) {
8776 lpt_bend_clkout_dp(to_i915(dev), 0);
8777 lpt_enable_clkout_dp(dev, true, true);
8778 } else {
8779 lpt_disable_clkout_dp(dev);
8780 }
8781 }
8782
8783 /*
8784 * Initialize reference clocks when the driver loads
8785 */
8786 void intel_init_pch_refclk(struct drm_device *dev)
8787 {
8788 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8789 ironlake_init_pch_refclk(dev);
8790 else if (HAS_PCH_LPT(dev))
8791 lpt_init_pch_refclk(dev);
8792 }
8793
8794 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8795 {
8796 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8798 int pipe = intel_crtc->pipe;
8799 uint32_t val;
8800
8801 val = 0;
8802
8803 switch (intel_crtc->config->pipe_bpp) {
8804 case 18:
8805 val |= PIPECONF_6BPC;
8806 break;
8807 case 24:
8808 val |= PIPECONF_8BPC;
8809 break;
8810 case 30:
8811 val |= PIPECONF_10BPC;
8812 break;
8813 case 36:
8814 val |= PIPECONF_12BPC;
8815 break;
8816 default:
8817 /* Case prevented by intel_choose_pipe_bpp_dither. */
8818 BUG();
8819 }
8820
8821 if (intel_crtc->config->dither)
8822 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8823
8824 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8825 val |= PIPECONF_INTERLACED_ILK;
8826 else
8827 val |= PIPECONF_PROGRESSIVE;
8828
8829 if (intel_crtc->config->limited_color_range)
8830 val |= PIPECONF_COLOR_RANGE_SELECT;
8831
8832 I915_WRITE(PIPECONF(pipe), val);
8833 POSTING_READ(PIPECONF(pipe));
8834 }
8835
8836 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8837 {
8838 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8840 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8841 u32 val = 0;
8842
8843 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8844 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8845
8846 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8847 val |= PIPECONF_INTERLACED_ILK;
8848 else
8849 val |= PIPECONF_PROGRESSIVE;
8850
8851 I915_WRITE(PIPECONF(cpu_transcoder), val);
8852 POSTING_READ(PIPECONF(cpu_transcoder));
8853 }
8854
8855 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8856 {
8857 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8859
8860 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8861 u32 val = 0;
8862
8863 switch (intel_crtc->config->pipe_bpp) {
8864 case 18:
8865 val |= PIPEMISC_DITHER_6_BPC;
8866 break;
8867 case 24:
8868 val |= PIPEMISC_DITHER_8_BPC;
8869 break;
8870 case 30:
8871 val |= PIPEMISC_DITHER_10_BPC;
8872 break;
8873 case 36:
8874 val |= PIPEMISC_DITHER_12_BPC;
8875 break;
8876 default:
8877 /* Case prevented by pipe_config_set_bpp. */
8878 BUG();
8879 }
8880
8881 if (intel_crtc->config->dither)
8882 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8883
8884 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8885 }
8886 }
8887
8888 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8889 {
8890 /*
8891 * Account for spread spectrum to avoid
8892 * oversubscribing the link. Max center spread
8893 * is 2.5%; use 5% for safety's sake.
8894 */
8895 u32 bps = target_clock * bpp * 21 / 20;
8896 return DIV_ROUND_UP(bps, link_bw * 8);
8897 }
8898
8899 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8900 {
8901 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8902 }
8903
8904 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8905 struct intel_crtc_state *crtc_state,
8906 struct dpll *reduced_clock)
8907 {
8908 struct drm_crtc *crtc = &intel_crtc->base;
8909 struct drm_device *dev = crtc->dev;
8910 struct drm_i915_private *dev_priv = dev->dev_private;
8911 struct drm_atomic_state *state = crtc_state->base.state;
8912 struct drm_connector *connector;
8913 struct drm_connector_state *connector_state;
8914 struct intel_encoder *encoder;
8915 u32 dpll, fp, fp2;
8916 int factor, i;
8917 bool is_lvds = false, is_sdvo = false;
8918
8919 for_each_connector_in_state(state, connector, connector_state, i) {
8920 if (connector_state->crtc != crtc_state->base.crtc)
8921 continue;
8922
8923 encoder = to_intel_encoder(connector_state->best_encoder);
8924
8925 switch (encoder->type) {
8926 case INTEL_OUTPUT_LVDS:
8927 is_lvds = true;
8928 break;
8929 case INTEL_OUTPUT_SDVO:
8930 case INTEL_OUTPUT_HDMI:
8931 is_sdvo = true;
8932 break;
8933 default:
8934 break;
8935 }
8936 }
8937
8938 /* Enable autotuning of the PLL clock (if permissible) */
8939 factor = 21;
8940 if (is_lvds) {
8941 if ((intel_panel_use_ssc(dev_priv) &&
8942 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8943 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8944 factor = 25;
8945 } else if (crtc_state->sdvo_tv_clock)
8946 factor = 20;
8947
8948 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8949
8950 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8951 fp |= FP_CB_TUNE;
8952
8953 if (reduced_clock) {
8954 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8955
8956 if (reduced_clock->m < factor * reduced_clock->n)
8957 fp2 |= FP_CB_TUNE;
8958 } else {
8959 fp2 = fp;
8960 }
8961
8962 dpll = 0;
8963
8964 if (is_lvds)
8965 dpll |= DPLLB_MODE_LVDS;
8966 else
8967 dpll |= DPLLB_MODE_DAC_SERIAL;
8968
8969 dpll |= (crtc_state->pixel_multiplier - 1)
8970 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8971
8972 if (is_sdvo)
8973 dpll |= DPLL_SDVO_HIGH_SPEED;
8974 if (crtc_state->has_dp_encoder)
8975 dpll |= DPLL_SDVO_HIGH_SPEED;
8976
8977 /* compute bitmask from p1 value */
8978 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8979 /* also FPA1 */
8980 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8981
8982 switch (crtc_state->dpll.p2) {
8983 case 5:
8984 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8985 break;
8986 case 7:
8987 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8988 break;
8989 case 10:
8990 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8991 break;
8992 case 14:
8993 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8994 break;
8995 }
8996
8997 if (is_lvds && intel_panel_use_ssc(dev_priv))
8998 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8999 else
9000 dpll |= PLL_REF_INPUT_DREFCLK;
9001
9002 dpll |= DPLL_VCO_ENABLE;
9003
9004 crtc_state->dpll_hw_state.dpll = dpll;
9005 crtc_state->dpll_hw_state.fp0 = fp;
9006 crtc_state->dpll_hw_state.fp1 = fp2;
9007 }
9008
9009 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9010 struct intel_crtc_state *crtc_state)
9011 {
9012 struct drm_device *dev = crtc->base.dev;
9013 struct drm_i915_private *dev_priv = dev->dev_private;
9014 struct dpll reduced_clock;
9015 bool has_reduced_clock = false;
9016 struct intel_shared_dpll *pll;
9017 const struct intel_limit *limit;
9018 int refclk = 120000;
9019
9020 memset(&crtc_state->dpll_hw_state, 0,
9021 sizeof(crtc_state->dpll_hw_state));
9022
9023 crtc->lowfreq_avail = false;
9024
9025 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9026 if (!crtc_state->has_pch_encoder)
9027 return 0;
9028
9029 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9030 if (intel_panel_use_ssc(dev_priv)) {
9031 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9032 dev_priv->vbt.lvds_ssc_freq);
9033 refclk = dev_priv->vbt.lvds_ssc_freq;
9034 }
9035
9036 if (intel_is_dual_link_lvds(dev)) {
9037 if (refclk == 100000)
9038 limit = &intel_limits_ironlake_dual_lvds_100m;
9039 else
9040 limit = &intel_limits_ironlake_dual_lvds;
9041 } else {
9042 if (refclk == 100000)
9043 limit = &intel_limits_ironlake_single_lvds_100m;
9044 else
9045 limit = &intel_limits_ironlake_single_lvds;
9046 }
9047 } else {
9048 limit = &intel_limits_ironlake_dac;
9049 }
9050
9051 if (!crtc_state->clock_set &&
9052 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9053 refclk, NULL, &crtc_state->dpll)) {
9054 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9055 return -EINVAL;
9056 }
9057
9058 ironlake_compute_dpll(crtc, crtc_state,
9059 has_reduced_clock ? &reduced_clock : NULL);
9060
9061 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9062 if (pll == NULL) {
9063 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9064 pipe_name(crtc->pipe));
9065 return -EINVAL;
9066 }
9067
9068 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9069 has_reduced_clock)
9070 crtc->lowfreq_avail = true;
9071
9072 return 0;
9073 }
9074
9075 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9076 struct intel_link_m_n *m_n)
9077 {
9078 struct drm_device *dev = crtc->base.dev;
9079 struct drm_i915_private *dev_priv = dev->dev_private;
9080 enum pipe pipe = crtc->pipe;
9081
9082 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9083 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9084 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9085 & ~TU_SIZE_MASK;
9086 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9087 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9088 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9089 }
9090
9091 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9092 enum transcoder transcoder,
9093 struct intel_link_m_n *m_n,
9094 struct intel_link_m_n *m2_n2)
9095 {
9096 struct drm_device *dev = crtc->base.dev;
9097 struct drm_i915_private *dev_priv = dev->dev_private;
9098 enum pipe pipe = crtc->pipe;
9099
9100 if (INTEL_INFO(dev)->gen >= 5) {
9101 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9102 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9103 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9104 & ~TU_SIZE_MASK;
9105 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9106 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9107 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9108 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9109 * gen < 8) and if DRRS is supported (to make sure the
9110 * registers are not unnecessarily read).
9111 */
9112 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9113 crtc->config->has_drrs) {
9114 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9115 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9116 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9117 & ~TU_SIZE_MASK;
9118 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9119 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9120 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9121 }
9122 } else {
9123 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9124 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9125 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9126 & ~TU_SIZE_MASK;
9127 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9128 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9129 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9130 }
9131 }
9132
9133 void intel_dp_get_m_n(struct intel_crtc *crtc,
9134 struct intel_crtc_state *pipe_config)
9135 {
9136 if (pipe_config->has_pch_encoder)
9137 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9138 else
9139 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9140 &pipe_config->dp_m_n,
9141 &pipe_config->dp_m2_n2);
9142 }
9143
9144 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9145 struct intel_crtc_state *pipe_config)
9146 {
9147 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9148 &pipe_config->fdi_m_n, NULL);
9149 }
9150
9151 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9152 struct intel_crtc_state *pipe_config)
9153 {
9154 struct drm_device *dev = crtc->base.dev;
9155 struct drm_i915_private *dev_priv = dev->dev_private;
9156 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9157 uint32_t ps_ctrl = 0;
9158 int id = -1;
9159 int i;
9160
9161 /* find scaler attached to this pipe */
9162 for (i = 0; i < crtc->num_scalers; i++) {
9163 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9164 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9165 id = i;
9166 pipe_config->pch_pfit.enabled = true;
9167 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9168 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9169 break;
9170 }
9171 }
9172
9173 scaler_state->scaler_id = id;
9174 if (id >= 0) {
9175 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9176 } else {
9177 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9178 }
9179 }
9180
9181 static void
9182 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9183 struct intel_initial_plane_config *plane_config)
9184 {
9185 struct drm_device *dev = crtc->base.dev;
9186 struct drm_i915_private *dev_priv = dev->dev_private;
9187 u32 val, base, offset, stride_mult, tiling;
9188 int pipe = crtc->pipe;
9189 int fourcc, pixel_format;
9190 unsigned int aligned_height;
9191 struct drm_framebuffer *fb;
9192 struct intel_framebuffer *intel_fb;
9193
9194 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9195 if (!intel_fb) {
9196 DRM_DEBUG_KMS("failed to alloc fb\n");
9197 return;
9198 }
9199
9200 fb = &intel_fb->base;
9201
9202 val = I915_READ(PLANE_CTL(pipe, 0));
9203 if (!(val & PLANE_CTL_ENABLE))
9204 goto error;
9205
9206 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9207 fourcc = skl_format_to_fourcc(pixel_format,
9208 val & PLANE_CTL_ORDER_RGBX,
9209 val & PLANE_CTL_ALPHA_MASK);
9210 fb->pixel_format = fourcc;
9211 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9212
9213 tiling = val & PLANE_CTL_TILED_MASK;
9214 switch (tiling) {
9215 case PLANE_CTL_TILED_LINEAR:
9216 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9217 break;
9218 case PLANE_CTL_TILED_X:
9219 plane_config->tiling = I915_TILING_X;
9220 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9221 break;
9222 case PLANE_CTL_TILED_Y:
9223 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9224 break;
9225 case PLANE_CTL_TILED_YF:
9226 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9227 break;
9228 default:
9229 MISSING_CASE(tiling);
9230 goto error;
9231 }
9232
9233 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9234 plane_config->base = base;
9235
9236 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9237
9238 val = I915_READ(PLANE_SIZE(pipe, 0));
9239 fb->height = ((val >> 16) & 0xfff) + 1;
9240 fb->width = ((val >> 0) & 0x1fff) + 1;
9241
9242 val = I915_READ(PLANE_STRIDE(pipe, 0));
9243 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9244 fb->pixel_format);
9245 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9246
9247 aligned_height = intel_fb_align_height(dev, fb->height,
9248 fb->pixel_format,
9249 fb->modifier[0]);
9250
9251 plane_config->size = fb->pitches[0] * aligned_height;
9252
9253 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9254 pipe_name(pipe), fb->width, fb->height,
9255 fb->bits_per_pixel, base, fb->pitches[0],
9256 plane_config->size);
9257
9258 plane_config->fb = intel_fb;
9259 return;
9260
9261 error:
9262 kfree(fb);
9263 }
9264
9265 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9266 struct intel_crtc_state *pipe_config)
9267 {
9268 struct drm_device *dev = crtc->base.dev;
9269 struct drm_i915_private *dev_priv = dev->dev_private;
9270 uint32_t tmp;
9271
9272 tmp = I915_READ(PF_CTL(crtc->pipe));
9273
9274 if (tmp & PF_ENABLE) {
9275 pipe_config->pch_pfit.enabled = true;
9276 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9277 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9278
9279 /* We currently do not free assignements of panel fitters on
9280 * ivb/hsw (since we don't use the higher upscaling modes which
9281 * differentiates them) so just WARN about this case for now. */
9282 if (IS_GEN7(dev)) {
9283 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9284 PF_PIPE_SEL_IVB(crtc->pipe));
9285 }
9286 }
9287 }
9288
9289 static void
9290 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9291 struct intel_initial_plane_config *plane_config)
9292 {
9293 struct drm_device *dev = crtc->base.dev;
9294 struct drm_i915_private *dev_priv = dev->dev_private;
9295 u32 val, base, offset;
9296 int pipe = crtc->pipe;
9297 int fourcc, pixel_format;
9298 unsigned int aligned_height;
9299 struct drm_framebuffer *fb;
9300 struct intel_framebuffer *intel_fb;
9301
9302 val = I915_READ(DSPCNTR(pipe));
9303 if (!(val & DISPLAY_PLANE_ENABLE))
9304 return;
9305
9306 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9307 if (!intel_fb) {
9308 DRM_DEBUG_KMS("failed to alloc fb\n");
9309 return;
9310 }
9311
9312 fb = &intel_fb->base;
9313
9314 if (INTEL_INFO(dev)->gen >= 4) {
9315 if (val & DISPPLANE_TILED) {
9316 plane_config->tiling = I915_TILING_X;
9317 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9318 }
9319 }
9320
9321 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9322 fourcc = i9xx_format_to_fourcc(pixel_format);
9323 fb->pixel_format = fourcc;
9324 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9325
9326 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9327 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9328 offset = I915_READ(DSPOFFSET(pipe));
9329 } else {
9330 if (plane_config->tiling)
9331 offset = I915_READ(DSPTILEOFF(pipe));
9332 else
9333 offset = I915_READ(DSPLINOFF(pipe));
9334 }
9335 plane_config->base = base;
9336
9337 val = I915_READ(PIPESRC(pipe));
9338 fb->width = ((val >> 16) & 0xfff) + 1;
9339 fb->height = ((val >> 0) & 0xfff) + 1;
9340
9341 val = I915_READ(DSPSTRIDE(pipe));
9342 fb->pitches[0] = val & 0xffffffc0;
9343
9344 aligned_height = intel_fb_align_height(dev, fb->height,
9345 fb->pixel_format,
9346 fb->modifier[0]);
9347
9348 plane_config->size = fb->pitches[0] * aligned_height;
9349
9350 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9351 pipe_name(pipe), fb->width, fb->height,
9352 fb->bits_per_pixel, base, fb->pitches[0],
9353 plane_config->size);
9354
9355 plane_config->fb = intel_fb;
9356 }
9357
9358 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9359 struct intel_crtc_state *pipe_config)
9360 {
9361 struct drm_device *dev = crtc->base.dev;
9362 struct drm_i915_private *dev_priv = dev->dev_private;
9363 enum intel_display_power_domain power_domain;
9364 uint32_t tmp;
9365 bool ret;
9366
9367 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9368 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9369 return false;
9370
9371 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9372 pipe_config->shared_dpll = NULL;
9373
9374 ret = false;
9375 tmp = I915_READ(PIPECONF(crtc->pipe));
9376 if (!(tmp & PIPECONF_ENABLE))
9377 goto out;
9378
9379 switch (tmp & PIPECONF_BPC_MASK) {
9380 case PIPECONF_6BPC:
9381 pipe_config->pipe_bpp = 18;
9382 break;
9383 case PIPECONF_8BPC:
9384 pipe_config->pipe_bpp = 24;
9385 break;
9386 case PIPECONF_10BPC:
9387 pipe_config->pipe_bpp = 30;
9388 break;
9389 case PIPECONF_12BPC:
9390 pipe_config->pipe_bpp = 36;
9391 break;
9392 default:
9393 break;
9394 }
9395
9396 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9397 pipe_config->limited_color_range = true;
9398
9399 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9400 struct intel_shared_dpll *pll;
9401 enum intel_dpll_id pll_id;
9402
9403 pipe_config->has_pch_encoder = true;
9404
9405 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9406 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9407 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9408
9409 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9410
9411 if (HAS_PCH_IBX(dev_priv)) {
9412 /*
9413 * The pipe->pch transcoder and pch transcoder->pll
9414 * mapping is fixed.
9415 */
9416 pll_id = (enum intel_dpll_id) crtc->pipe;
9417 } else {
9418 tmp = I915_READ(PCH_DPLL_SEL);
9419 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9420 pll_id = DPLL_ID_PCH_PLL_B;
9421 else
9422 pll_id= DPLL_ID_PCH_PLL_A;
9423 }
9424
9425 pipe_config->shared_dpll =
9426 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9427 pll = pipe_config->shared_dpll;
9428
9429 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9430 &pipe_config->dpll_hw_state));
9431
9432 tmp = pipe_config->dpll_hw_state.dpll;
9433 pipe_config->pixel_multiplier =
9434 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9435 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9436
9437 ironlake_pch_clock_get(crtc, pipe_config);
9438 } else {
9439 pipe_config->pixel_multiplier = 1;
9440 }
9441
9442 intel_get_pipe_timings(crtc, pipe_config);
9443 intel_get_pipe_src_size(crtc, pipe_config);
9444
9445 ironlake_get_pfit_config(crtc, pipe_config);
9446
9447 ret = true;
9448
9449 out:
9450 intel_display_power_put(dev_priv, power_domain);
9451
9452 return ret;
9453 }
9454
9455 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9456 {
9457 struct drm_device *dev = dev_priv->dev;
9458 struct intel_crtc *crtc;
9459
9460 for_each_intel_crtc(dev, crtc)
9461 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9462 pipe_name(crtc->pipe));
9463
9464 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9465 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9466 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9467 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9468 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9469 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9470 "CPU PWM1 enabled\n");
9471 if (IS_HASWELL(dev))
9472 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9473 "CPU PWM2 enabled\n");
9474 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9475 "PCH PWM1 enabled\n");
9476 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9477 "Utility pin enabled\n");
9478 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9479
9480 /*
9481 * In theory we can still leave IRQs enabled, as long as only the HPD
9482 * interrupts remain enabled. We used to check for that, but since it's
9483 * gen-specific and since we only disable LCPLL after we fully disable
9484 * the interrupts, the check below should be enough.
9485 */
9486 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9487 }
9488
9489 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9490 {
9491 struct drm_device *dev = dev_priv->dev;
9492
9493 if (IS_HASWELL(dev))
9494 return I915_READ(D_COMP_HSW);
9495 else
9496 return I915_READ(D_COMP_BDW);
9497 }
9498
9499 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9500 {
9501 struct drm_device *dev = dev_priv->dev;
9502
9503 if (IS_HASWELL(dev)) {
9504 mutex_lock(&dev_priv->rps.hw_lock);
9505 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9506 val))
9507 DRM_ERROR("Failed to write to D_COMP\n");
9508 mutex_unlock(&dev_priv->rps.hw_lock);
9509 } else {
9510 I915_WRITE(D_COMP_BDW, val);
9511 POSTING_READ(D_COMP_BDW);
9512 }
9513 }
9514
9515 /*
9516 * This function implements pieces of two sequences from BSpec:
9517 * - Sequence for display software to disable LCPLL
9518 * - Sequence for display software to allow package C8+
9519 * The steps implemented here are just the steps that actually touch the LCPLL
9520 * register. Callers should take care of disabling all the display engine
9521 * functions, doing the mode unset, fixing interrupts, etc.
9522 */
9523 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9524 bool switch_to_fclk, bool allow_power_down)
9525 {
9526 uint32_t val;
9527
9528 assert_can_disable_lcpll(dev_priv);
9529
9530 val = I915_READ(LCPLL_CTL);
9531
9532 if (switch_to_fclk) {
9533 val |= LCPLL_CD_SOURCE_FCLK;
9534 I915_WRITE(LCPLL_CTL, val);
9535
9536 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9537 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9538 DRM_ERROR("Switching to FCLK failed\n");
9539
9540 val = I915_READ(LCPLL_CTL);
9541 }
9542
9543 val |= LCPLL_PLL_DISABLE;
9544 I915_WRITE(LCPLL_CTL, val);
9545 POSTING_READ(LCPLL_CTL);
9546
9547 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9548 DRM_ERROR("LCPLL still locked\n");
9549
9550 val = hsw_read_dcomp(dev_priv);
9551 val |= D_COMP_COMP_DISABLE;
9552 hsw_write_dcomp(dev_priv, val);
9553 ndelay(100);
9554
9555 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9556 1))
9557 DRM_ERROR("D_COMP RCOMP still in progress\n");
9558
9559 if (allow_power_down) {
9560 val = I915_READ(LCPLL_CTL);
9561 val |= LCPLL_POWER_DOWN_ALLOW;
9562 I915_WRITE(LCPLL_CTL, val);
9563 POSTING_READ(LCPLL_CTL);
9564 }
9565 }
9566
9567 /*
9568 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9569 * source.
9570 */
9571 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9572 {
9573 uint32_t val;
9574
9575 val = I915_READ(LCPLL_CTL);
9576
9577 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9578 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9579 return;
9580
9581 /*
9582 * Make sure we're not on PC8 state before disabling PC8, otherwise
9583 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9584 */
9585 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9586
9587 if (val & LCPLL_POWER_DOWN_ALLOW) {
9588 val &= ~LCPLL_POWER_DOWN_ALLOW;
9589 I915_WRITE(LCPLL_CTL, val);
9590 POSTING_READ(LCPLL_CTL);
9591 }
9592
9593 val = hsw_read_dcomp(dev_priv);
9594 val |= D_COMP_COMP_FORCE;
9595 val &= ~D_COMP_COMP_DISABLE;
9596 hsw_write_dcomp(dev_priv, val);
9597
9598 val = I915_READ(LCPLL_CTL);
9599 val &= ~LCPLL_PLL_DISABLE;
9600 I915_WRITE(LCPLL_CTL, val);
9601
9602 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9603 DRM_ERROR("LCPLL not locked yet\n");
9604
9605 if (val & LCPLL_CD_SOURCE_FCLK) {
9606 val = I915_READ(LCPLL_CTL);
9607 val &= ~LCPLL_CD_SOURCE_FCLK;
9608 I915_WRITE(LCPLL_CTL, val);
9609
9610 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9611 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9612 DRM_ERROR("Switching back to LCPLL failed\n");
9613 }
9614
9615 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9616 intel_update_cdclk(dev_priv->dev);
9617 }
9618
9619 /*
9620 * Package states C8 and deeper are really deep PC states that can only be
9621 * reached when all the devices on the system allow it, so even if the graphics
9622 * device allows PC8+, it doesn't mean the system will actually get to these
9623 * states. Our driver only allows PC8+ when going into runtime PM.
9624 *
9625 * The requirements for PC8+ are that all the outputs are disabled, the power
9626 * well is disabled and most interrupts are disabled, and these are also
9627 * requirements for runtime PM. When these conditions are met, we manually do
9628 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9629 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9630 * hang the machine.
9631 *
9632 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9633 * the state of some registers, so when we come back from PC8+ we need to
9634 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9635 * need to take care of the registers kept by RC6. Notice that this happens even
9636 * if we don't put the device in PCI D3 state (which is what currently happens
9637 * because of the runtime PM support).
9638 *
9639 * For more, read "Display Sequences for Package C8" on the hardware
9640 * documentation.
9641 */
9642 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9643 {
9644 struct drm_device *dev = dev_priv->dev;
9645 uint32_t val;
9646
9647 DRM_DEBUG_KMS("Enabling package C8+\n");
9648
9649 if (HAS_PCH_LPT_LP(dev)) {
9650 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9651 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9652 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9653 }
9654
9655 lpt_disable_clkout_dp(dev);
9656 hsw_disable_lcpll(dev_priv, true, true);
9657 }
9658
9659 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9660 {
9661 struct drm_device *dev = dev_priv->dev;
9662 uint32_t val;
9663
9664 DRM_DEBUG_KMS("Disabling package C8+\n");
9665
9666 hsw_restore_lcpll(dev_priv);
9667 lpt_init_pch_refclk(dev);
9668
9669 if (HAS_PCH_LPT_LP(dev)) {
9670 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9671 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9672 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9673 }
9674 }
9675
9676 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9677 {
9678 struct drm_device *dev = old_state->dev;
9679 struct intel_atomic_state *old_intel_state =
9680 to_intel_atomic_state(old_state);
9681 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9682
9683 broxton_set_cdclk(to_i915(dev), req_cdclk);
9684 }
9685
9686 /* compute the max rate for new configuration */
9687 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9688 {
9689 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9690 struct drm_i915_private *dev_priv = state->dev->dev_private;
9691 struct drm_crtc *crtc;
9692 struct drm_crtc_state *cstate;
9693 struct intel_crtc_state *crtc_state;
9694 unsigned max_pixel_rate = 0, i;
9695 enum pipe pipe;
9696
9697 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9698 sizeof(intel_state->min_pixclk));
9699
9700 for_each_crtc_in_state(state, crtc, cstate, i) {
9701 int pixel_rate;
9702
9703 crtc_state = to_intel_crtc_state(cstate);
9704 if (!crtc_state->base.enable) {
9705 intel_state->min_pixclk[i] = 0;
9706 continue;
9707 }
9708
9709 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9710
9711 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9712 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9713 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9714
9715 intel_state->min_pixclk[i] = pixel_rate;
9716 }
9717
9718 for_each_pipe(dev_priv, pipe)
9719 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9720
9721 return max_pixel_rate;
9722 }
9723
9724 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9725 {
9726 struct drm_i915_private *dev_priv = dev->dev_private;
9727 uint32_t val, data;
9728 int ret;
9729
9730 if (WARN((I915_READ(LCPLL_CTL) &
9731 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9732 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9733 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9734 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9735 "trying to change cdclk frequency with cdclk not enabled\n"))
9736 return;
9737
9738 mutex_lock(&dev_priv->rps.hw_lock);
9739 ret = sandybridge_pcode_write(dev_priv,
9740 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9741 mutex_unlock(&dev_priv->rps.hw_lock);
9742 if (ret) {
9743 DRM_ERROR("failed to inform pcode about cdclk change\n");
9744 return;
9745 }
9746
9747 val = I915_READ(LCPLL_CTL);
9748 val |= LCPLL_CD_SOURCE_FCLK;
9749 I915_WRITE(LCPLL_CTL, val);
9750
9751 if (wait_for_us(I915_READ(LCPLL_CTL) &
9752 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9753 DRM_ERROR("Switching to FCLK failed\n");
9754
9755 val = I915_READ(LCPLL_CTL);
9756 val &= ~LCPLL_CLK_FREQ_MASK;
9757
9758 switch (cdclk) {
9759 case 450000:
9760 val |= LCPLL_CLK_FREQ_450;
9761 data = 0;
9762 break;
9763 case 540000:
9764 val |= LCPLL_CLK_FREQ_54O_BDW;
9765 data = 1;
9766 break;
9767 case 337500:
9768 val |= LCPLL_CLK_FREQ_337_5_BDW;
9769 data = 2;
9770 break;
9771 case 675000:
9772 val |= LCPLL_CLK_FREQ_675_BDW;
9773 data = 3;
9774 break;
9775 default:
9776 WARN(1, "invalid cdclk frequency\n");
9777 return;
9778 }
9779
9780 I915_WRITE(LCPLL_CTL, val);
9781
9782 val = I915_READ(LCPLL_CTL);
9783 val &= ~LCPLL_CD_SOURCE_FCLK;
9784 I915_WRITE(LCPLL_CTL, val);
9785
9786 if (wait_for_us((I915_READ(LCPLL_CTL) &
9787 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9788 DRM_ERROR("Switching back to LCPLL failed\n");
9789
9790 mutex_lock(&dev_priv->rps.hw_lock);
9791 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9792 mutex_unlock(&dev_priv->rps.hw_lock);
9793
9794 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9795
9796 intel_update_cdclk(dev);
9797
9798 WARN(cdclk != dev_priv->cdclk_freq,
9799 "cdclk requested %d kHz but got %d kHz\n",
9800 cdclk, dev_priv->cdclk_freq);
9801 }
9802
9803 static int broadwell_calc_cdclk(int max_pixclk)
9804 {
9805 if (max_pixclk > 540000)
9806 return 675000;
9807 else if (max_pixclk > 450000)
9808 return 540000;
9809 else if (max_pixclk > 337500)
9810 return 450000;
9811 else
9812 return 337500;
9813 }
9814
9815 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9816 {
9817 struct drm_i915_private *dev_priv = to_i915(state->dev);
9818 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9819 int max_pixclk = ilk_max_pixel_rate(state);
9820 int cdclk;
9821
9822 /*
9823 * FIXME should also account for plane ratio
9824 * once 64bpp pixel formats are supported.
9825 */
9826 cdclk = broadwell_calc_cdclk(max_pixclk);
9827
9828 if (cdclk > dev_priv->max_cdclk_freq) {
9829 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9830 cdclk, dev_priv->max_cdclk_freq);
9831 return -EINVAL;
9832 }
9833
9834 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9835 if (!intel_state->active_crtcs)
9836 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9837
9838 return 0;
9839 }
9840
9841 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9842 {
9843 struct drm_device *dev = old_state->dev;
9844 struct intel_atomic_state *old_intel_state =
9845 to_intel_atomic_state(old_state);
9846 unsigned req_cdclk = old_intel_state->dev_cdclk;
9847
9848 broadwell_set_cdclk(dev, req_cdclk);
9849 }
9850
9851 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9852 {
9853 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9854 struct drm_i915_private *dev_priv = to_i915(state->dev);
9855 const int max_pixclk = ilk_max_pixel_rate(state);
9856 int vco = intel_state->cdclk_pll_vco;
9857 int cdclk;
9858
9859 /*
9860 * FIXME should also account for plane ratio
9861 * once 64bpp pixel formats are supported.
9862 */
9863 cdclk = skl_calc_cdclk(max_pixclk, vco);
9864
9865 /*
9866 * FIXME move the cdclk caclulation to
9867 * compute_config() so we can fail gracegully.
9868 */
9869 if (cdclk > dev_priv->max_cdclk_freq) {
9870 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9871 cdclk, dev_priv->max_cdclk_freq);
9872 cdclk = dev_priv->max_cdclk_freq;
9873 }
9874
9875 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9876 if (!intel_state->active_crtcs)
9877 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9878
9879 return 0;
9880 }
9881
9882 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9883 {
9884 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9885 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9886 unsigned int req_cdclk = intel_state->dev_cdclk;
9887 unsigned int req_vco = intel_state->cdclk_pll_vco;
9888
9889 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9890 }
9891
9892 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9893 struct intel_crtc_state *crtc_state)
9894 {
9895 struct intel_encoder *intel_encoder =
9896 intel_ddi_get_crtc_new_encoder(crtc_state);
9897
9898 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9899 if (!intel_ddi_pll_select(crtc, crtc_state))
9900 return -EINVAL;
9901 }
9902
9903 crtc->lowfreq_avail = false;
9904
9905 return 0;
9906 }
9907
9908 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9909 enum port port,
9910 struct intel_crtc_state *pipe_config)
9911 {
9912 enum intel_dpll_id id;
9913
9914 switch (port) {
9915 case PORT_A:
9916 pipe_config->ddi_pll_sel = SKL_DPLL0;
9917 id = DPLL_ID_SKL_DPLL0;
9918 break;
9919 case PORT_B:
9920 pipe_config->ddi_pll_sel = SKL_DPLL1;
9921 id = DPLL_ID_SKL_DPLL1;
9922 break;
9923 case PORT_C:
9924 pipe_config->ddi_pll_sel = SKL_DPLL2;
9925 id = DPLL_ID_SKL_DPLL2;
9926 break;
9927 default:
9928 DRM_ERROR("Incorrect port type\n");
9929 return;
9930 }
9931
9932 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9933 }
9934
9935 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9936 enum port port,
9937 struct intel_crtc_state *pipe_config)
9938 {
9939 enum intel_dpll_id id;
9940 u32 temp;
9941
9942 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9943 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9944
9945 switch (pipe_config->ddi_pll_sel) {
9946 case SKL_DPLL0:
9947 id = DPLL_ID_SKL_DPLL0;
9948 break;
9949 case SKL_DPLL1:
9950 id = DPLL_ID_SKL_DPLL1;
9951 break;
9952 case SKL_DPLL2:
9953 id = DPLL_ID_SKL_DPLL2;
9954 break;
9955 case SKL_DPLL3:
9956 id = DPLL_ID_SKL_DPLL3;
9957 break;
9958 default:
9959 MISSING_CASE(pipe_config->ddi_pll_sel);
9960 return;
9961 }
9962
9963 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9964 }
9965
9966 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9967 enum port port,
9968 struct intel_crtc_state *pipe_config)
9969 {
9970 enum intel_dpll_id id;
9971
9972 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9973
9974 switch (pipe_config->ddi_pll_sel) {
9975 case PORT_CLK_SEL_WRPLL1:
9976 id = DPLL_ID_WRPLL1;
9977 break;
9978 case PORT_CLK_SEL_WRPLL2:
9979 id = DPLL_ID_WRPLL2;
9980 break;
9981 case PORT_CLK_SEL_SPLL:
9982 id = DPLL_ID_SPLL;
9983 break;
9984 case PORT_CLK_SEL_LCPLL_810:
9985 id = DPLL_ID_LCPLL_810;
9986 break;
9987 case PORT_CLK_SEL_LCPLL_1350:
9988 id = DPLL_ID_LCPLL_1350;
9989 break;
9990 case PORT_CLK_SEL_LCPLL_2700:
9991 id = DPLL_ID_LCPLL_2700;
9992 break;
9993 default:
9994 MISSING_CASE(pipe_config->ddi_pll_sel);
9995 /* fall through */
9996 case PORT_CLK_SEL_NONE:
9997 return;
9998 }
9999
10000 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10001 }
10002
10003 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10004 struct intel_crtc_state *pipe_config,
10005 unsigned long *power_domain_mask)
10006 {
10007 struct drm_device *dev = crtc->base.dev;
10008 struct drm_i915_private *dev_priv = dev->dev_private;
10009 enum intel_display_power_domain power_domain;
10010 u32 tmp;
10011
10012 /*
10013 * The pipe->transcoder mapping is fixed with the exception of the eDP
10014 * transcoder handled below.
10015 */
10016 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10017
10018 /*
10019 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10020 * consistency and less surprising code; it's in always on power).
10021 */
10022 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10023 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10024 enum pipe trans_edp_pipe;
10025 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10026 default:
10027 WARN(1, "unknown pipe linked to edp transcoder\n");
10028 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10029 case TRANS_DDI_EDP_INPUT_A_ON:
10030 trans_edp_pipe = PIPE_A;
10031 break;
10032 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10033 trans_edp_pipe = PIPE_B;
10034 break;
10035 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10036 trans_edp_pipe = PIPE_C;
10037 break;
10038 }
10039
10040 if (trans_edp_pipe == crtc->pipe)
10041 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10042 }
10043
10044 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10045 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10046 return false;
10047 *power_domain_mask |= BIT(power_domain);
10048
10049 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10050
10051 return tmp & PIPECONF_ENABLE;
10052 }
10053
10054 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10055 struct intel_crtc_state *pipe_config,
10056 unsigned long *power_domain_mask)
10057 {
10058 struct drm_device *dev = crtc->base.dev;
10059 struct drm_i915_private *dev_priv = dev->dev_private;
10060 enum intel_display_power_domain power_domain;
10061 enum port port;
10062 enum transcoder cpu_transcoder;
10063 u32 tmp;
10064
10065 pipe_config->has_dsi_encoder = false;
10066
10067 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10068 if (port == PORT_A)
10069 cpu_transcoder = TRANSCODER_DSI_A;
10070 else
10071 cpu_transcoder = TRANSCODER_DSI_C;
10072
10073 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10074 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10075 continue;
10076 *power_domain_mask |= BIT(power_domain);
10077
10078 /*
10079 * The PLL needs to be enabled with a valid divider
10080 * configuration, otherwise accessing DSI registers will hang
10081 * the machine. See BSpec North Display Engine
10082 * registers/MIPI[BXT]. We can break out here early, since we
10083 * need the same DSI PLL to be enabled for both DSI ports.
10084 */
10085 if (!intel_dsi_pll_is_enabled(dev_priv))
10086 break;
10087
10088 /* XXX: this works for video mode only */
10089 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10090 if (!(tmp & DPI_ENABLE))
10091 continue;
10092
10093 tmp = I915_READ(MIPI_CTRL(port));
10094 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10095 continue;
10096
10097 pipe_config->cpu_transcoder = cpu_transcoder;
10098 pipe_config->has_dsi_encoder = true;
10099 break;
10100 }
10101
10102 return pipe_config->has_dsi_encoder;
10103 }
10104
10105 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10106 struct intel_crtc_state *pipe_config)
10107 {
10108 struct drm_device *dev = crtc->base.dev;
10109 struct drm_i915_private *dev_priv = dev->dev_private;
10110 struct intel_shared_dpll *pll;
10111 enum port port;
10112 uint32_t tmp;
10113
10114 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10115
10116 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10117
10118 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10119 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10120 else if (IS_BROXTON(dev))
10121 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10122 else
10123 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10124
10125 pll = pipe_config->shared_dpll;
10126 if (pll) {
10127 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10128 &pipe_config->dpll_hw_state));
10129 }
10130
10131 /*
10132 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10133 * DDI E. So just check whether this pipe is wired to DDI E and whether
10134 * the PCH transcoder is on.
10135 */
10136 if (INTEL_INFO(dev)->gen < 9 &&
10137 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10138 pipe_config->has_pch_encoder = true;
10139
10140 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10141 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10142 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10143
10144 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10145 }
10146 }
10147
10148 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10149 struct intel_crtc_state *pipe_config)
10150 {
10151 struct drm_device *dev = crtc->base.dev;
10152 struct drm_i915_private *dev_priv = dev->dev_private;
10153 enum intel_display_power_domain power_domain;
10154 unsigned long power_domain_mask;
10155 bool active;
10156
10157 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10158 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10159 return false;
10160 power_domain_mask = BIT(power_domain);
10161
10162 pipe_config->shared_dpll = NULL;
10163
10164 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10165
10166 if (IS_BROXTON(dev_priv)) {
10167 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10168 &power_domain_mask);
10169 WARN_ON(active && pipe_config->has_dsi_encoder);
10170 if (pipe_config->has_dsi_encoder)
10171 active = true;
10172 }
10173
10174 if (!active)
10175 goto out;
10176
10177 if (!pipe_config->has_dsi_encoder) {
10178 haswell_get_ddi_port_state(crtc, pipe_config);
10179 intel_get_pipe_timings(crtc, pipe_config);
10180 }
10181
10182 intel_get_pipe_src_size(crtc, pipe_config);
10183
10184 pipe_config->gamma_mode =
10185 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10186
10187 if (INTEL_INFO(dev)->gen >= 9) {
10188 skl_init_scalers(dev, crtc, pipe_config);
10189 }
10190
10191 if (INTEL_INFO(dev)->gen >= 9) {
10192 pipe_config->scaler_state.scaler_id = -1;
10193 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10194 }
10195
10196 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10197 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10198 power_domain_mask |= BIT(power_domain);
10199 if (INTEL_INFO(dev)->gen >= 9)
10200 skylake_get_pfit_config(crtc, pipe_config);
10201 else
10202 ironlake_get_pfit_config(crtc, pipe_config);
10203 }
10204
10205 if (IS_HASWELL(dev))
10206 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10207 (I915_READ(IPS_CTL) & IPS_ENABLE);
10208
10209 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10210 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10211 pipe_config->pixel_multiplier =
10212 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10213 } else {
10214 pipe_config->pixel_multiplier = 1;
10215 }
10216
10217 out:
10218 for_each_power_domain(power_domain, power_domain_mask)
10219 intel_display_power_put(dev_priv, power_domain);
10220
10221 return active;
10222 }
10223
10224 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10225 const struct intel_plane_state *plane_state)
10226 {
10227 struct drm_device *dev = crtc->dev;
10228 struct drm_i915_private *dev_priv = dev->dev_private;
10229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10230 uint32_t cntl = 0, size = 0;
10231
10232 if (plane_state && plane_state->visible) {
10233 unsigned int width = plane_state->base.crtc_w;
10234 unsigned int height = plane_state->base.crtc_h;
10235 unsigned int stride = roundup_pow_of_two(width) * 4;
10236
10237 switch (stride) {
10238 default:
10239 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10240 width, stride);
10241 stride = 256;
10242 /* fallthrough */
10243 case 256:
10244 case 512:
10245 case 1024:
10246 case 2048:
10247 break;
10248 }
10249
10250 cntl |= CURSOR_ENABLE |
10251 CURSOR_GAMMA_ENABLE |
10252 CURSOR_FORMAT_ARGB |
10253 CURSOR_STRIDE(stride);
10254
10255 size = (height << 12) | width;
10256 }
10257
10258 if (intel_crtc->cursor_cntl != 0 &&
10259 (intel_crtc->cursor_base != base ||
10260 intel_crtc->cursor_size != size ||
10261 intel_crtc->cursor_cntl != cntl)) {
10262 /* On these chipsets we can only modify the base/size/stride
10263 * whilst the cursor is disabled.
10264 */
10265 I915_WRITE(CURCNTR(PIPE_A), 0);
10266 POSTING_READ(CURCNTR(PIPE_A));
10267 intel_crtc->cursor_cntl = 0;
10268 }
10269
10270 if (intel_crtc->cursor_base != base) {
10271 I915_WRITE(CURBASE(PIPE_A), base);
10272 intel_crtc->cursor_base = base;
10273 }
10274
10275 if (intel_crtc->cursor_size != size) {
10276 I915_WRITE(CURSIZE, size);
10277 intel_crtc->cursor_size = size;
10278 }
10279
10280 if (intel_crtc->cursor_cntl != cntl) {
10281 I915_WRITE(CURCNTR(PIPE_A), cntl);
10282 POSTING_READ(CURCNTR(PIPE_A));
10283 intel_crtc->cursor_cntl = cntl;
10284 }
10285 }
10286
10287 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10288 const struct intel_plane_state *plane_state)
10289 {
10290 struct drm_device *dev = crtc->dev;
10291 struct drm_i915_private *dev_priv = dev->dev_private;
10292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10293 int pipe = intel_crtc->pipe;
10294 uint32_t cntl = 0;
10295
10296 if (plane_state && plane_state->visible) {
10297 cntl = MCURSOR_GAMMA_ENABLE;
10298 switch (plane_state->base.crtc_w) {
10299 case 64:
10300 cntl |= CURSOR_MODE_64_ARGB_AX;
10301 break;
10302 case 128:
10303 cntl |= CURSOR_MODE_128_ARGB_AX;
10304 break;
10305 case 256:
10306 cntl |= CURSOR_MODE_256_ARGB_AX;
10307 break;
10308 default:
10309 MISSING_CASE(plane_state->base.crtc_w);
10310 return;
10311 }
10312 cntl |= pipe << 28; /* Connect to correct pipe */
10313
10314 if (HAS_DDI(dev))
10315 cntl |= CURSOR_PIPE_CSC_ENABLE;
10316
10317 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10318 cntl |= CURSOR_ROTATE_180;
10319 }
10320
10321 if (intel_crtc->cursor_cntl != cntl) {
10322 I915_WRITE(CURCNTR(pipe), cntl);
10323 POSTING_READ(CURCNTR(pipe));
10324 intel_crtc->cursor_cntl = cntl;
10325 }
10326
10327 /* and commit changes on next vblank */
10328 I915_WRITE(CURBASE(pipe), base);
10329 POSTING_READ(CURBASE(pipe));
10330
10331 intel_crtc->cursor_base = base;
10332 }
10333
10334 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10335 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10336 const struct intel_plane_state *plane_state)
10337 {
10338 struct drm_device *dev = crtc->dev;
10339 struct drm_i915_private *dev_priv = dev->dev_private;
10340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10341 int pipe = intel_crtc->pipe;
10342 u32 base = intel_crtc->cursor_addr;
10343 u32 pos = 0;
10344
10345 if (plane_state) {
10346 int x = plane_state->base.crtc_x;
10347 int y = plane_state->base.crtc_y;
10348
10349 if (x < 0) {
10350 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10351 x = -x;
10352 }
10353 pos |= x << CURSOR_X_SHIFT;
10354
10355 if (y < 0) {
10356 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10357 y = -y;
10358 }
10359 pos |= y << CURSOR_Y_SHIFT;
10360
10361 /* ILK+ do this automagically */
10362 if (HAS_GMCH_DISPLAY(dev) &&
10363 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10364 base += (plane_state->base.crtc_h *
10365 plane_state->base.crtc_w - 1) * 4;
10366 }
10367 }
10368
10369 I915_WRITE(CURPOS(pipe), pos);
10370
10371 if (IS_845G(dev) || IS_I865G(dev))
10372 i845_update_cursor(crtc, base, plane_state);
10373 else
10374 i9xx_update_cursor(crtc, base, plane_state);
10375 }
10376
10377 static bool cursor_size_ok(struct drm_device *dev,
10378 uint32_t width, uint32_t height)
10379 {
10380 if (width == 0 || height == 0)
10381 return false;
10382
10383 /*
10384 * 845g/865g are special in that they are only limited by
10385 * the width of their cursors, the height is arbitrary up to
10386 * the precision of the register. Everything else requires
10387 * square cursors, limited to a few power-of-two sizes.
10388 */
10389 if (IS_845G(dev) || IS_I865G(dev)) {
10390 if ((width & 63) != 0)
10391 return false;
10392
10393 if (width > (IS_845G(dev) ? 64 : 512))
10394 return false;
10395
10396 if (height > 1023)
10397 return false;
10398 } else {
10399 switch (width | height) {
10400 case 256:
10401 case 128:
10402 if (IS_GEN2(dev))
10403 return false;
10404 case 64:
10405 break;
10406 default:
10407 return false;
10408 }
10409 }
10410
10411 return true;
10412 }
10413
10414 /* VESA 640x480x72Hz mode to set on the pipe */
10415 static struct drm_display_mode load_detect_mode = {
10416 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10417 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10418 };
10419
10420 struct drm_framebuffer *
10421 __intel_framebuffer_create(struct drm_device *dev,
10422 struct drm_mode_fb_cmd2 *mode_cmd,
10423 struct drm_i915_gem_object *obj)
10424 {
10425 struct intel_framebuffer *intel_fb;
10426 int ret;
10427
10428 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10429 if (!intel_fb)
10430 return ERR_PTR(-ENOMEM);
10431
10432 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10433 if (ret)
10434 goto err;
10435
10436 return &intel_fb->base;
10437
10438 err:
10439 kfree(intel_fb);
10440 return ERR_PTR(ret);
10441 }
10442
10443 static struct drm_framebuffer *
10444 intel_framebuffer_create(struct drm_device *dev,
10445 struct drm_mode_fb_cmd2 *mode_cmd,
10446 struct drm_i915_gem_object *obj)
10447 {
10448 struct drm_framebuffer *fb;
10449 int ret;
10450
10451 ret = i915_mutex_lock_interruptible(dev);
10452 if (ret)
10453 return ERR_PTR(ret);
10454 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10455 mutex_unlock(&dev->struct_mutex);
10456
10457 return fb;
10458 }
10459
10460 static u32
10461 intel_framebuffer_pitch_for_width(int width, int bpp)
10462 {
10463 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10464 return ALIGN(pitch, 64);
10465 }
10466
10467 static u32
10468 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10469 {
10470 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10471 return PAGE_ALIGN(pitch * mode->vdisplay);
10472 }
10473
10474 static struct drm_framebuffer *
10475 intel_framebuffer_create_for_mode(struct drm_device *dev,
10476 struct drm_display_mode *mode,
10477 int depth, int bpp)
10478 {
10479 struct drm_framebuffer *fb;
10480 struct drm_i915_gem_object *obj;
10481 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10482
10483 obj = i915_gem_object_create(dev,
10484 intel_framebuffer_size_for_mode(mode, bpp));
10485 if (IS_ERR(obj))
10486 return ERR_CAST(obj);
10487
10488 mode_cmd.width = mode->hdisplay;
10489 mode_cmd.height = mode->vdisplay;
10490 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10491 bpp);
10492 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10493
10494 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10495 if (IS_ERR(fb))
10496 drm_gem_object_unreference_unlocked(&obj->base);
10497
10498 return fb;
10499 }
10500
10501 static struct drm_framebuffer *
10502 mode_fits_in_fbdev(struct drm_device *dev,
10503 struct drm_display_mode *mode)
10504 {
10505 #ifdef CONFIG_DRM_FBDEV_EMULATION
10506 struct drm_i915_private *dev_priv = dev->dev_private;
10507 struct drm_i915_gem_object *obj;
10508 struct drm_framebuffer *fb;
10509
10510 if (!dev_priv->fbdev)
10511 return NULL;
10512
10513 if (!dev_priv->fbdev->fb)
10514 return NULL;
10515
10516 obj = dev_priv->fbdev->fb->obj;
10517 BUG_ON(!obj);
10518
10519 fb = &dev_priv->fbdev->fb->base;
10520 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10521 fb->bits_per_pixel))
10522 return NULL;
10523
10524 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10525 return NULL;
10526
10527 drm_framebuffer_reference(fb);
10528 return fb;
10529 #else
10530 return NULL;
10531 #endif
10532 }
10533
10534 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10535 struct drm_crtc *crtc,
10536 struct drm_display_mode *mode,
10537 struct drm_framebuffer *fb,
10538 int x, int y)
10539 {
10540 struct drm_plane_state *plane_state;
10541 int hdisplay, vdisplay;
10542 int ret;
10543
10544 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10545 if (IS_ERR(plane_state))
10546 return PTR_ERR(plane_state);
10547
10548 if (mode)
10549 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10550 else
10551 hdisplay = vdisplay = 0;
10552
10553 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10554 if (ret)
10555 return ret;
10556 drm_atomic_set_fb_for_plane(plane_state, fb);
10557 plane_state->crtc_x = 0;
10558 plane_state->crtc_y = 0;
10559 plane_state->crtc_w = hdisplay;
10560 plane_state->crtc_h = vdisplay;
10561 plane_state->src_x = x << 16;
10562 plane_state->src_y = y << 16;
10563 plane_state->src_w = hdisplay << 16;
10564 plane_state->src_h = vdisplay << 16;
10565
10566 return 0;
10567 }
10568
10569 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10570 struct drm_display_mode *mode,
10571 struct intel_load_detect_pipe *old,
10572 struct drm_modeset_acquire_ctx *ctx)
10573 {
10574 struct intel_crtc *intel_crtc;
10575 struct intel_encoder *intel_encoder =
10576 intel_attached_encoder(connector);
10577 struct drm_crtc *possible_crtc;
10578 struct drm_encoder *encoder = &intel_encoder->base;
10579 struct drm_crtc *crtc = NULL;
10580 struct drm_device *dev = encoder->dev;
10581 struct drm_framebuffer *fb;
10582 struct drm_mode_config *config = &dev->mode_config;
10583 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10584 struct drm_connector_state *connector_state;
10585 struct intel_crtc_state *crtc_state;
10586 int ret, i = -1;
10587
10588 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10589 connector->base.id, connector->name,
10590 encoder->base.id, encoder->name);
10591
10592 old->restore_state = NULL;
10593
10594 retry:
10595 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10596 if (ret)
10597 goto fail;
10598
10599 /*
10600 * Algorithm gets a little messy:
10601 *
10602 * - if the connector already has an assigned crtc, use it (but make
10603 * sure it's on first)
10604 *
10605 * - try to find the first unused crtc that can drive this connector,
10606 * and use that if we find one
10607 */
10608
10609 /* See if we already have a CRTC for this connector */
10610 if (connector->state->crtc) {
10611 crtc = connector->state->crtc;
10612
10613 ret = drm_modeset_lock(&crtc->mutex, ctx);
10614 if (ret)
10615 goto fail;
10616
10617 /* Make sure the crtc and connector are running */
10618 goto found;
10619 }
10620
10621 /* Find an unused one (if possible) */
10622 for_each_crtc(dev, possible_crtc) {
10623 i++;
10624 if (!(encoder->possible_crtcs & (1 << i)))
10625 continue;
10626
10627 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10628 if (ret)
10629 goto fail;
10630
10631 if (possible_crtc->state->enable) {
10632 drm_modeset_unlock(&possible_crtc->mutex);
10633 continue;
10634 }
10635
10636 crtc = possible_crtc;
10637 break;
10638 }
10639
10640 /*
10641 * If we didn't find an unused CRTC, don't use any.
10642 */
10643 if (!crtc) {
10644 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10645 goto fail;
10646 }
10647
10648 found:
10649 intel_crtc = to_intel_crtc(crtc);
10650
10651 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10652 if (ret)
10653 goto fail;
10654
10655 state = drm_atomic_state_alloc(dev);
10656 restore_state = drm_atomic_state_alloc(dev);
10657 if (!state || !restore_state) {
10658 ret = -ENOMEM;
10659 goto fail;
10660 }
10661
10662 state->acquire_ctx = ctx;
10663 restore_state->acquire_ctx = ctx;
10664
10665 connector_state = drm_atomic_get_connector_state(state, connector);
10666 if (IS_ERR(connector_state)) {
10667 ret = PTR_ERR(connector_state);
10668 goto fail;
10669 }
10670
10671 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10672 if (ret)
10673 goto fail;
10674
10675 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10676 if (IS_ERR(crtc_state)) {
10677 ret = PTR_ERR(crtc_state);
10678 goto fail;
10679 }
10680
10681 crtc_state->base.active = crtc_state->base.enable = true;
10682
10683 if (!mode)
10684 mode = &load_detect_mode;
10685
10686 /* We need a framebuffer large enough to accommodate all accesses
10687 * that the plane may generate whilst we perform load detection.
10688 * We can not rely on the fbcon either being present (we get called
10689 * during its initialisation to detect all boot displays, or it may
10690 * not even exist) or that it is large enough to satisfy the
10691 * requested mode.
10692 */
10693 fb = mode_fits_in_fbdev(dev, mode);
10694 if (fb == NULL) {
10695 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10696 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10697 } else
10698 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10699 if (IS_ERR(fb)) {
10700 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10701 goto fail;
10702 }
10703
10704 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10705 if (ret)
10706 goto fail;
10707
10708 drm_framebuffer_unreference(fb);
10709
10710 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10711 if (ret)
10712 goto fail;
10713
10714 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10715 if (!ret)
10716 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10717 if (!ret)
10718 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10719 if (ret) {
10720 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10721 goto fail;
10722 }
10723
10724 ret = drm_atomic_commit(state);
10725 if (ret) {
10726 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10727 goto fail;
10728 }
10729
10730 old->restore_state = restore_state;
10731
10732 /* let the connector get through one full cycle before testing */
10733 intel_wait_for_vblank(dev, intel_crtc->pipe);
10734 return true;
10735
10736 fail:
10737 drm_atomic_state_free(state);
10738 drm_atomic_state_free(restore_state);
10739 restore_state = state = NULL;
10740
10741 if (ret == -EDEADLK) {
10742 drm_modeset_backoff(ctx);
10743 goto retry;
10744 }
10745
10746 return false;
10747 }
10748
10749 void intel_release_load_detect_pipe(struct drm_connector *connector,
10750 struct intel_load_detect_pipe *old,
10751 struct drm_modeset_acquire_ctx *ctx)
10752 {
10753 struct intel_encoder *intel_encoder =
10754 intel_attached_encoder(connector);
10755 struct drm_encoder *encoder = &intel_encoder->base;
10756 struct drm_atomic_state *state = old->restore_state;
10757 int ret;
10758
10759 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10760 connector->base.id, connector->name,
10761 encoder->base.id, encoder->name);
10762
10763 if (!state)
10764 return;
10765
10766 ret = drm_atomic_commit(state);
10767 if (ret) {
10768 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10769 drm_atomic_state_free(state);
10770 }
10771 }
10772
10773 static int i9xx_pll_refclk(struct drm_device *dev,
10774 const struct intel_crtc_state *pipe_config)
10775 {
10776 struct drm_i915_private *dev_priv = dev->dev_private;
10777 u32 dpll = pipe_config->dpll_hw_state.dpll;
10778
10779 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10780 return dev_priv->vbt.lvds_ssc_freq;
10781 else if (HAS_PCH_SPLIT(dev))
10782 return 120000;
10783 else if (!IS_GEN2(dev))
10784 return 96000;
10785 else
10786 return 48000;
10787 }
10788
10789 /* Returns the clock of the currently programmed mode of the given pipe. */
10790 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10791 struct intel_crtc_state *pipe_config)
10792 {
10793 struct drm_device *dev = crtc->base.dev;
10794 struct drm_i915_private *dev_priv = dev->dev_private;
10795 int pipe = pipe_config->cpu_transcoder;
10796 u32 dpll = pipe_config->dpll_hw_state.dpll;
10797 u32 fp;
10798 struct dpll clock;
10799 int port_clock;
10800 int refclk = i9xx_pll_refclk(dev, pipe_config);
10801
10802 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10803 fp = pipe_config->dpll_hw_state.fp0;
10804 else
10805 fp = pipe_config->dpll_hw_state.fp1;
10806
10807 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10808 if (IS_PINEVIEW(dev)) {
10809 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10810 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10811 } else {
10812 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10813 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10814 }
10815
10816 if (!IS_GEN2(dev)) {
10817 if (IS_PINEVIEW(dev))
10818 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10819 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10820 else
10821 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10822 DPLL_FPA01_P1_POST_DIV_SHIFT);
10823
10824 switch (dpll & DPLL_MODE_MASK) {
10825 case DPLLB_MODE_DAC_SERIAL:
10826 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10827 5 : 10;
10828 break;
10829 case DPLLB_MODE_LVDS:
10830 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10831 7 : 14;
10832 break;
10833 default:
10834 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10835 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10836 return;
10837 }
10838
10839 if (IS_PINEVIEW(dev))
10840 port_clock = pnv_calc_dpll_params(refclk, &clock);
10841 else
10842 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10843 } else {
10844 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10845 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10846
10847 if (is_lvds) {
10848 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10849 DPLL_FPA01_P1_POST_DIV_SHIFT);
10850
10851 if (lvds & LVDS_CLKB_POWER_UP)
10852 clock.p2 = 7;
10853 else
10854 clock.p2 = 14;
10855 } else {
10856 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10857 clock.p1 = 2;
10858 else {
10859 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10860 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10861 }
10862 if (dpll & PLL_P2_DIVIDE_BY_4)
10863 clock.p2 = 4;
10864 else
10865 clock.p2 = 2;
10866 }
10867
10868 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10869 }
10870
10871 /*
10872 * This value includes pixel_multiplier. We will use
10873 * port_clock to compute adjusted_mode.crtc_clock in the
10874 * encoder's get_config() function.
10875 */
10876 pipe_config->port_clock = port_clock;
10877 }
10878
10879 int intel_dotclock_calculate(int link_freq,
10880 const struct intel_link_m_n *m_n)
10881 {
10882 /*
10883 * The calculation for the data clock is:
10884 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10885 * But we want to avoid losing precison if possible, so:
10886 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10887 *
10888 * and the link clock is simpler:
10889 * link_clock = (m * link_clock) / n
10890 */
10891
10892 if (!m_n->link_n)
10893 return 0;
10894
10895 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10896 }
10897
10898 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10899 struct intel_crtc_state *pipe_config)
10900 {
10901 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10902
10903 /* read out port_clock from the DPLL */
10904 i9xx_crtc_clock_get(crtc, pipe_config);
10905
10906 /*
10907 * In case there is an active pipe without active ports,
10908 * we may need some idea for the dotclock anyway.
10909 * Calculate one based on the FDI configuration.
10910 */
10911 pipe_config->base.adjusted_mode.crtc_clock =
10912 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10913 &pipe_config->fdi_m_n);
10914 }
10915
10916 /** Returns the currently programmed mode of the given pipe. */
10917 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10918 struct drm_crtc *crtc)
10919 {
10920 struct drm_i915_private *dev_priv = dev->dev_private;
10921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10922 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10923 struct drm_display_mode *mode;
10924 struct intel_crtc_state *pipe_config;
10925 int htot = I915_READ(HTOTAL(cpu_transcoder));
10926 int hsync = I915_READ(HSYNC(cpu_transcoder));
10927 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10928 int vsync = I915_READ(VSYNC(cpu_transcoder));
10929 enum pipe pipe = intel_crtc->pipe;
10930
10931 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10932 if (!mode)
10933 return NULL;
10934
10935 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10936 if (!pipe_config) {
10937 kfree(mode);
10938 return NULL;
10939 }
10940
10941 /*
10942 * Construct a pipe_config sufficient for getting the clock info
10943 * back out of crtc_clock_get.
10944 *
10945 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10946 * to use a real value here instead.
10947 */
10948 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10949 pipe_config->pixel_multiplier = 1;
10950 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10951 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10952 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10953 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10954
10955 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10956 mode->hdisplay = (htot & 0xffff) + 1;
10957 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10958 mode->hsync_start = (hsync & 0xffff) + 1;
10959 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10960 mode->vdisplay = (vtot & 0xffff) + 1;
10961 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10962 mode->vsync_start = (vsync & 0xffff) + 1;
10963 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10964
10965 drm_mode_set_name(mode);
10966
10967 kfree(pipe_config);
10968
10969 return mode;
10970 }
10971
10972 void intel_mark_busy(struct drm_i915_private *dev_priv)
10973 {
10974 if (dev_priv->mm.busy)
10975 return;
10976
10977 intel_runtime_pm_get(dev_priv);
10978 i915_update_gfx_val(dev_priv);
10979 if (INTEL_GEN(dev_priv) >= 6)
10980 gen6_rps_busy(dev_priv);
10981 dev_priv->mm.busy = true;
10982 }
10983
10984 void intel_mark_idle(struct drm_i915_private *dev_priv)
10985 {
10986 if (!dev_priv->mm.busy)
10987 return;
10988
10989 dev_priv->mm.busy = false;
10990
10991 if (INTEL_GEN(dev_priv) >= 6)
10992 gen6_rps_idle(dev_priv);
10993
10994 intel_runtime_pm_put(dev_priv);
10995 }
10996
10997 static void intel_crtc_destroy(struct drm_crtc *crtc)
10998 {
10999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11000 struct drm_device *dev = crtc->dev;
11001 struct intel_flip_work *work;
11002
11003 spin_lock_irq(&dev->event_lock);
11004 work = intel_crtc->flip_work;
11005 intel_crtc->flip_work = NULL;
11006 spin_unlock_irq(&dev->event_lock);
11007
11008 if (work) {
11009 cancel_work_sync(&work->mmio_work);
11010 cancel_work_sync(&work->unpin_work);
11011 kfree(work);
11012 }
11013
11014 drm_crtc_cleanup(crtc);
11015
11016 kfree(intel_crtc);
11017 }
11018
11019 static void intel_unpin_work_fn(struct work_struct *__work)
11020 {
11021 struct intel_flip_work *work =
11022 container_of(__work, struct intel_flip_work, unpin_work);
11023 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11024 struct drm_device *dev = crtc->base.dev;
11025 struct drm_plane *primary = crtc->base.primary;
11026
11027 if (is_mmio_work(work))
11028 flush_work(&work->mmio_work);
11029
11030 mutex_lock(&dev->struct_mutex);
11031 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11032 drm_gem_object_unreference(&work->pending_flip_obj->base);
11033
11034 if (work->flip_queued_req)
11035 i915_gem_request_assign(&work->flip_queued_req, NULL);
11036 mutex_unlock(&dev->struct_mutex);
11037
11038 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
11039 intel_fbc_post_update(crtc);
11040 drm_framebuffer_unreference(work->old_fb);
11041
11042 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11043 atomic_dec(&crtc->unpin_work_count);
11044
11045 kfree(work);
11046 }
11047
11048 /* Is 'a' after or equal to 'b'? */
11049 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11050 {
11051 return !((a - b) & 0x80000000);
11052 }
11053
11054 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11055 struct intel_flip_work *work)
11056 {
11057 struct drm_device *dev = crtc->base.dev;
11058 struct drm_i915_private *dev_priv = dev->dev_private;
11059 unsigned reset_counter;
11060
11061 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11062 if (crtc->reset_counter != reset_counter)
11063 return true;
11064
11065 /*
11066 * The relevant registers doen't exist on pre-ctg.
11067 * As the flip done interrupt doesn't trigger for mmio
11068 * flips on gmch platforms, a flip count check isn't
11069 * really needed there. But since ctg has the registers,
11070 * include it in the check anyway.
11071 */
11072 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11073 return true;
11074
11075 /*
11076 * BDW signals flip done immediately if the plane
11077 * is disabled, even if the plane enable is already
11078 * armed to occur at the next vblank :(
11079 */
11080
11081 /*
11082 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11083 * used the same base address. In that case the mmio flip might
11084 * have completed, but the CS hasn't even executed the flip yet.
11085 *
11086 * A flip count check isn't enough as the CS might have updated
11087 * the base address just after start of vblank, but before we
11088 * managed to process the interrupt. This means we'd complete the
11089 * CS flip too soon.
11090 *
11091 * Combining both checks should get us a good enough result. It may
11092 * still happen that the CS flip has been executed, but has not
11093 * yet actually completed. But in case the base address is the same
11094 * anyway, we don't really care.
11095 */
11096 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11097 crtc->flip_work->gtt_offset &&
11098 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11099 crtc->flip_work->flip_count);
11100 }
11101
11102 static bool
11103 __pageflip_finished_mmio(struct intel_crtc *crtc,
11104 struct intel_flip_work *work)
11105 {
11106 /*
11107 * MMIO work completes when vblank is different from
11108 * flip_queued_vblank.
11109 *
11110 * Reset counter value doesn't matter, this is handled by
11111 * i915_wait_request finishing early, so no need to handle
11112 * reset here.
11113 */
11114 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11115 }
11116
11117
11118 static bool pageflip_finished(struct intel_crtc *crtc,
11119 struct intel_flip_work *work)
11120 {
11121 if (!atomic_read(&work->pending))
11122 return false;
11123
11124 smp_rmb();
11125
11126 if (is_mmio_work(work))
11127 return __pageflip_finished_mmio(crtc, work);
11128 else
11129 return __pageflip_finished_cs(crtc, work);
11130 }
11131
11132 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11133 {
11134 struct drm_device *dev = dev_priv->dev;
11135 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11137 struct intel_flip_work *work;
11138 unsigned long flags;
11139
11140 /* Ignore early vblank irqs */
11141 if (!crtc)
11142 return;
11143
11144 /*
11145 * This is called both by irq handlers and the reset code (to complete
11146 * lost pageflips) so needs the full irqsave spinlocks.
11147 */
11148 spin_lock_irqsave(&dev->event_lock, flags);
11149 work = intel_crtc->flip_work;
11150
11151 if (work != NULL &&
11152 !is_mmio_work(work) &&
11153 pageflip_finished(intel_crtc, work))
11154 page_flip_completed(intel_crtc);
11155
11156 spin_unlock_irqrestore(&dev->event_lock, flags);
11157 }
11158
11159 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11160 {
11161 struct drm_device *dev = dev_priv->dev;
11162 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11164 struct intel_flip_work *work;
11165 unsigned long flags;
11166
11167 /* Ignore early vblank irqs */
11168 if (!crtc)
11169 return;
11170
11171 /*
11172 * This is called both by irq handlers and the reset code (to complete
11173 * lost pageflips) so needs the full irqsave spinlocks.
11174 */
11175 spin_lock_irqsave(&dev->event_lock, flags);
11176 work = intel_crtc->flip_work;
11177
11178 if (work != NULL &&
11179 is_mmio_work(work) &&
11180 pageflip_finished(intel_crtc, work))
11181 page_flip_completed(intel_crtc);
11182
11183 spin_unlock_irqrestore(&dev->event_lock, flags);
11184 }
11185
11186 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11187 struct intel_flip_work *work)
11188 {
11189 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11190
11191 /* Ensure that the work item is consistent when activating it ... */
11192 smp_mb__before_atomic();
11193 atomic_set(&work->pending, 1);
11194 }
11195
11196 static int intel_gen2_queue_flip(struct drm_device *dev,
11197 struct drm_crtc *crtc,
11198 struct drm_framebuffer *fb,
11199 struct drm_i915_gem_object *obj,
11200 struct drm_i915_gem_request *req,
11201 uint32_t flags)
11202 {
11203 struct intel_engine_cs *engine = req->engine;
11204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11205 u32 flip_mask;
11206 int ret;
11207
11208 ret = intel_ring_begin(req, 6);
11209 if (ret)
11210 return ret;
11211
11212 /* Can't queue multiple flips, so wait for the previous
11213 * one to finish before executing the next.
11214 */
11215 if (intel_crtc->plane)
11216 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11217 else
11218 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11219 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11220 intel_ring_emit(engine, MI_NOOP);
11221 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11222 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11223 intel_ring_emit(engine, fb->pitches[0]);
11224 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11225 intel_ring_emit(engine, 0); /* aux display base address, unused */
11226
11227 return 0;
11228 }
11229
11230 static int intel_gen3_queue_flip(struct drm_device *dev,
11231 struct drm_crtc *crtc,
11232 struct drm_framebuffer *fb,
11233 struct drm_i915_gem_object *obj,
11234 struct drm_i915_gem_request *req,
11235 uint32_t flags)
11236 {
11237 struct intel_engine_cs *engine = req->engine;
11238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11239 u32 flip_mask;
11240 int ret;
11241
11242 ret = intel_ring_begin(req, 6);
11243 if (ret)
11244 return ret;
11245
11246 if (intel_crtc->plane)
11247 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11248 else
11249 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11250 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11251 intel_ring_emit(engine, MI_NOOP);
11252 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11253 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11254 intel_ring_emit(engine, fb->pitches[0]);
11255 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11256 intel_ring_emit(engine, MI_NOOP);
11257
11258 return 0;
11259 }
11260
11261 static int intel_gen4_queue_flip(struct drm_device *dev,
11262 struct drm_crtc *crtc,
11263 struct drm_framebuffer *fb,
11264 struct drm_i915_gem_object *obj,
11265 struct drm_i915_gem_request *req,
11266 uint32_t flags)
11267 {
11268 struct intel_engine_cs *engine = req->engine;
11269 struct drm_i915_private *dev_priv = dev->dev_private;
11270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11271 uint32_t pf, pipesrc;
11272 int ret;
11273
11274 ret = intel_ring_begin(req, 4);
11275 if (ret)
11276 return ret;
11277
11278 /* i965+ uses the linear or tiled offsets from the
11279 * Display Registers (which do not change across a page-flip)
11280 * so we need only reprogram the base address.
11281 */
11282 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11283 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11284 intel_ring_emit(engine, fb->pitches[0]);
11285 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
11286 obj->tiling_mode);
11287
11288 /* XXX Enabling the panel-fitter across page-flip is so far
11289 * untested on non-native modes, so ignore it for now.
11290 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11291 */
11292 pf = 0;
11293 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11294 intel_ring_emit(engine, pf | pipesrc);
11295
11296 return 0;
11297 }
11298
11299 static int intel_gen6_queue_flip(struct drm_device *dev,
11300 struct drm_crtc *crtc,
11301 struct drm_framebuffer *fb,
11302 struct drm_i915_gem_object *obj,
11303 struct drm_i915_gem_request *req,
11304 uint32_t flags)
11305 {
11306 struct intel_engine_cs *engine = req->engine;
11307 struct drm_i915_private *dev_priv = dev->dev_private;
11308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11309 uint32_t pf, pipesrc;
11310 int ret;
11311
11312 ret = intel_ring_begin(req, 4);
11313 if (ret)
11314 return ret;
11315
11316 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11317 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11318 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11319 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11320
11321 /* Contrary to the suggestions in the documentation,
11322 * "Enable Panel Fitter" does not seem to be required when page
11323 * flipping with a non-native mode, and worse causes a normal
11324 * modeset to fail.
11325 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11326 */
11327 pf = 0;
11328 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11329 intel_ring_emit(engine, pf | pipesrc);
11330
11331 return 0;
11332 }
11333
11334 static int intel_gen7_queue_flip(struct drm_device *dev,
11335 struct drm_crtc *crtc,
11336 struct drm_framebuffer *fb,
11337 struct drm_i915_gem_object *obj,
11338 struct drm_i915_gem_request *req,
11339 uint32_t flags)
11340 {
11341 struct intel_engine_cs *engine = req->engine;
11342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11343 uint32_t plane_bit = 0;
11344 int len, ret;
11345
11346 switch (intel_crtc->plane) {
11347 case PLANE_A:
11348 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11349 break;
11350 case PLANE_B:
11351 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11352 break;
11353 case PLANE_C:
11354 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11355 break;
11356 default:
11357 WARN_ONCE(1, "unknown plane in flip command\n");
11358 return -ENODEV;
11359 }
11360
11361 len = 4;
11362 if (engine->id == RCS) {
11363 len += 6;
11364 /*
11365 * On Gen 8, SRM is now taking an extra dword to accommodate
11366 * 48bits addresses, and we need a NOOP for the batch size to
11367 * stay even.
11368 */
11369 if (IS_GEN8(dev))
11370 len += 2;
11371 }
11372
11373 /*
11374 * BSpec MI_DISPLAY_FLIP for IVB:
11375 * "The full packet must be contained within the same cache line."
11376 *
11377 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11378 * cacheline, if we ever start emitting more commands before
11379 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11380 * then do the cacheline alignment, and finally emit the
11381 * MI_DISPLAY_FLIP.
11382 */
11383 ret = intel_ring_cacheline_align(req);
11384 if (ret)
11385 return ret;
11386
11387 ret = intel_ring_begin(req, len);
11388 if (ret)
11389 return ret;
11390
11391 /* Unmask the flip-done completion message. Note that the bspec says that
11392 * we should do this for both the BCS and RCS, and that we must not unmask
11393 * more than one flip event at any time (or ensure that one flip message
11394 * can be sent by waiting for flip-done prior to queueing new flips).
11395 * Experimentation says that BCS works despite DERRMR masking all
11396 * flip-done completion events and that unmasking all planes at once
11397 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11398 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11399 */
11400 if (engine->id == RCS) {
11401 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11402 intel_ring_emit_reg(engine, DERRMR);
11403 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11404 DERRMR_PIPEB_PRI_FLIP_DONE |
11405 DERRMR_PIPEC_PRI_FLIP_DONE));
11406 if (IS_GEN8(dev))
11407 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11408 MI_SRM_LRM_GLOBAL_GTT);
11409 else
11410 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11411 MI_SRM_LRM_GLOBAL_GTT);
11412 intel_ring_emit_reg(engine, DERRMR);
11413 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11414 if (IS_GEN8(dev)) {
11415 intel_ring_emit(engine, 0);
11416 intel_ring_emit(engine, MI_NOOP);
11417 }
11418 }
11419
11420 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11421 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11422 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11423 intel_ring_emit(engine, (MI_NOOP));
11424
11425 return 0;
11426 }
11427
11428 static bool use_mmio_flip(struct intel_engine_cs *engine,
11429 struct drm_i915_gem_object *obj)
11430 {
11431 /*
11432 * This is not being used for older platforms, because
11433 * non-availability of flip done interrupt forces us to use
11434 * CS flips. Older platforms derive flip done using some clever
11435 * tricks involving the flip_pending status bits and vblank irqs.
11436 * So using MMIO flips there would disrupt this mechanism.
11437 */
11438
11439 if (engine == NULL)
11440 return true;
11441
11442 if (INTEL_GEN(engine->i915) < 5)
11443 return false;
11444
11445 if (i915.use_mmio_flip < 0)
11446 return false;
11447 else if (i915.use_mmio_flip > 0)
11448 return true;
11449 else if (i915.enable_execlists)
11450 return true;
11451 else if (obj->base.dma_buf &&
11452 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11453 false))
11454 return true;
11455 else
11456 return engine != i915_gem_request_get_engine(obj->last_write_req);
11457 }
11458
11459 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11460 unsigned int rotation,
11461 struct intel_flip_work *work)
11462 {
11463 struct drm_device *dev = intel_crtc->base.dev;
11464 struct drm_i915_private *dev_priv = dev->dev_private;
11465 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11466 const enum pipe pipe = intel_crtc->pipe;
11467 u32 ctl, stride, tile_height;
11468
11469 ctl = I915_READ(PLANE_CTL(pipe, 0));
11470 ctl &= ~PLANE_CTL_TILED_MASK;
11471 switch (fb->modifier[0]) {
11472 case DRM_FORMAT_MOD_NONE:
11473 break;
11474 case I915_FORMAT_MOD_X_TILED:
11475 ctl |= PLANE_CTL_TILED_X;
11476 break;
11477 case I915_FORMAT_MOD_Y_TILED:
11478 ctl |= PLANE_CTL_TILED_Y;
11479 break;
11480 case I915_FORMAT_MOD_Yf_TILED:
11481 ctl |= PLANE_CTL_TILED_YF;
11482 break;
11483 default:
11484 MISSING_CASE(fb->modifier[0]);
11485 }
11486
11487 /*
11488 * The stride is either expressed as a multiple of 64 bytes chunks for
11489 * linear buffers or in number of tiles for tiled buffers.
11490 */
11491 if (intel_rotation_90_or_270(rotation)) {
11492 /* stride = Surface height in tiles */
11493 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11494 stride = DIV_ROUND_UP(fb->height, tile_height);
11495 } else {
11496 stride = fb->pitches[0] /
11497 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11498 fb->pixel_format);
11499 }
11500
11501 /*
11502 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11503 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11504 */
11505 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11506 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11507
11508 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11509 POSTING_READ(PLANE_SURF(pipe, 0));
11510 }
11511
11512 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11513 struct intel_flip_work *work)
11514 {
11515 struct drm_device *dev = intel_crtc->base.dev;
11516 struct drm_i915_private *dev_priv = dev->dev_private;
11517 struct intel_framebuffer *intel_fb =
11518 to_intel_framebuffer(intel_crtc->base.primary->fb);
11519 struct drm_i915_gem_object *obj = intel_fb->obj;
11520 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11521 u32 dspcntr;
11522
11523 dspcntr = I915_READ(reg);
11524
11525 if (obj->tiling_mode != I915_TILING_NONE)
11526 dspcntr |= DISPPLANE_TILED;
11527 else
11528 dspcntr &= ~DISPPLANE_TILED;
11529
11530 I915_WRITE(reg, dspcntr);
11531
11532 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11533 POSTING_READ(DSPSURF(intel_crtc->plane));
11534 }
11535
11536 static void intel_mmio_flip_work_func(struct work_struct *w)
11537 {
11538 struct intel_flip_work *work =
11539 container_of(w, struct intel_flip_work, mmio_work);
11540 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11541 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11542 struct intel_framebuffer *intel_fb =
11543 to_intel_framebuffer(crtc->base.primary->fb);
11544 struct drm_i915_gem_object *obj = intel_fb->obj;
11545
11546 if (work->flip_queued_req)
11547 WARN_ON(__i915_wait_request(work->flip_queued_req,
11548 false, NULL,
11549 &dev_priv->rps.mmioflips));
11550
11551 /* For framebuffer backed by dmabuf, wait for fence */
11552 if (obj->base.dma_buf)
11553 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11554 false, false,
11555 MAX_SCHEDULE_TIMEOUT) < 0);
11556
11557 intel_pipe_update_start(crtc);
11558
11559 if (INTEL_GEN(dev_priv) >= 9)
11560 skl_do_mmio_flip(crtc, work->rotation, work);
11561 else
11562 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11563 ilk_do_mmio_flip(crtc, work);
11564
11565 intel_pipe_update_end(crtc, work);
11566 }
11567
11568 static int intel_default_queue_flip(struct drm_device *dev,
11569 struct drm_crtc *crtc,
11570 struct drm_framebuffer *fb,
11571 struct drm_i915_gem_object *obj,
11572 struct drm_i915_gem_request *req,
11573 uint32_t flags)
11574 {
11575 return -ENODEV;
11576 }
11577
11578 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11579 struct intel_crtc *intel_crtc,
11580 struct intel_flip_work *work)
11581 {
11582 u32 addr, vblank;
11583
11584 if (!atomic_read(&work->pending))
11585 return false;
11586
11587 smp_rmb();
11588
11589 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11590 if (work->flip_ready_vblank == 0) {
11591 if (work->flip_queued_req &&
11592 !i915_gem_request_completed(work->flip_queued_req, true))
11593 return false;
11594
11595 work->flip_ready_vblank = vblank;
11596 }
11597
11598 if (vblank - work->flip_ready_vblank < 3)
11599 return false;
11600
11601 /* Potential stall - if we see that the flip has happened,
11602 * assume a missed interrupt. */
11603 if (INTEL_GEN(dev_priv) >= 4)
11604 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11605 else
11606 addr = I915_READ(DSPADDR(intel_crtc->plane));
11607
11608 /* There is a potential issue here with a false positive after a flip
11609 * to the same address. We could address this by checking for a
11610 * non-incrementing frame counter.
11611 */
11612 return addr == work->gtt_offset;
11613 }
11614
11615 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11616 {
11617 struct drm_device *dev = dev_priv->dev;
11618 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11620 struct intel_flip_work *work;
11621
11622 WARN_ON(!in_interrupt());
11623
11624 if (crtc == NULL)
11625 return;
11626
11627 spin_lock(&dev->event_lock);
11628 work = intel_crtc->flip_work;
11629
11630 if (work != NULL && !is_mmio_work(work) &&
11631 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11632 WARN_ONCE(1,
11633 "Kicking stuck page flip: queued at %d, now %d\n",
11634 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11635 page_flip_completed(intel_crtc);
11636 work = NULL;
11637 }
11638
11639 if (work != NULL && !is_mmio_work(work) &&
11640 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11641 intel_queue_rps_boost_for_request(work->flip_queued_req);
11642 spin_unlock(&dev->event_lock);
11643 }
11644
11645 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11646 struct drm_framebuffer *fb,
11647 struct drm_pending_vblank_event *event,
11648 uint32_t page_flip_flags)
11649 {
11650 struct drm_device *dev = crtc->dev;
11651 struct drm_i915_private *dev_priv = dev->dev_private;
11652 struct drm_framebuffer *old_fb = crtc->primary->fb;
11653 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11655 struct drm_plane *primary = crtc->primary;
11656 enum pipe pipe = intel_crtc->pipe;
11657 struct intel_flip_work *work;
11658 struct intel_engine_cs *engine;
11659 bool mmio_flip;
11660 struct drm_i915_gem_request *request = NULL;
11661 int ret;
11662
11663 /*
11664 * drm_mode_page_flip_ioctl() should already catch this, but double
11665 * check to be safe. In the future we may enable pageflipping from
11666 * a disabled primary plane.
11667 */
11668 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11669 return -EBUSY;
11670
11671 /* Can't change pixel format via MI display flips. */
11672 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11673 return -EINVAL;
11674
11675 /*
11676 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11677 * Note that pitch changes could also affect these register.
11678 */
11679 if (INTEL_INFO(dev)->gen > 3 &&
11680 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11681 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11682 return -EINVAL;
11683
11684 if (i915_terminally_wedged(&dev_priv->gpu_error))
11685 goto out_hang;
11686
11687 work = kzalloc(sizeof(*work), GFP_KERNEL);
11688 if (work == NULL)
11689 return -ENOMEM;
11690
11691 work->event = event;
11692 work->crtc = crtc;
11693 work->old_fb = old_fb;
11694 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11695
11696 ret = drm_crtc_vblank_get(crtc);
11697 if (ret)
11698 goto free_work;
11699
11700 /* We borrow the event spin lock for protecting flip_work */
11701 spin_lock_irq(&dev->event_lock);
11702 if (intel_crtc->flip_work) {
11703 /* Before declaring the flip queue wedged, check if
11704 * the hardware completed the operation behind our backs.
11705 */
11706 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11707 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11708 page_flip_completed(intel_crtc);
11709 } else {
11710 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11711 spin_unlock_irq(&dev->event_lock);
11712
11713 drm_crtc_vblank_put(crtc);
11714 kfree(work);
11715 return -EBUSY;
11716 }
11717 }
11718 intel_crtc->flip_work = work;
11719 spin_unlock_irq(&dev->event_lock);
11720
11721 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11722 flush_workqueue(dev_priv->wq);
11723
11724 /* Reference the objects for the scheduled work. */
11725 drm_framebuffer_reference(work->old_fb);
11726 drm_gem_object_reference(&obj->base);
11727
11728 crtc->primary->fb = fb;
11729 update_state_fb(crtc->primary);
11730 intel_fbc_pre_update(intel_crtc);
11731
11732 work->pending_flip_obj = obj;
11733
11734 ret = i915_mutex_lock_interruptible(dev);
11735 if (ret)
11736 goto cleanup;
11737
11738 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11739 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11740 ret = -EIO;
11741 goto cleanup;
11742 }
11743
11744 atomic_inc(&intel_crtc->unpin_work_count);
11745
11746 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11747 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11748
11749 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11750 engine = &dev_priv->engine[BCS];
11751 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11752 /* vlv: DISPLAY_FLIP fails to change tiling */
11753 engine = NULL;
11754 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11755 engine = &dev_priv->engine[BCS];
11756 } else if (INTEL_INFO(dev)->gen >= 7) {
11757 engine = i915_gem_request_get_engine(obj->last_write_req);
11758 if (engine == NULL || engine->id != RCS)
11759 engine = &dev_priv->engine[BCS];
11760 } else {
11761 engine = &dev_priv->engine[RCS];
11762 }
11763
11764 mmio_flip = use_mmio_flip(engine, obj);
11765
11766 /* When using CS flips, we want to emit semaphores between rings.
11767 * However, when using mmio flips we will create a task to do the
11768 * synchronisation, so all we want here is to pin the framebuffer
11769 * into the display plane and skip any waits.
11770 */
11771 if (!mmio_flip) {
11772 ret = i915_gem_object_sync(obj, engine, &request);
11773 if (!ret && !request) {
11774 request = i915_gem_request_alloc(engine, NULL);
11775 ret = PTR_ERR_OR_ZERO(request);
11776 }
11777
11778 if (ret)
11779 goto cleanup_pending;
11780 }
11781
11782 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11783 if (ret)
11784 goto cleanup_pending;
11785
11786 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11787 obj, 0);
11788 work->gtt_offset += intel_crtc->dspaddr_offset;
11789 work->rotation = crtc->primary->state->rotation;
11790
11791 if (mmio_flip) {
11792 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11793
11794 i915_gem_request_assign(&work->flip_queued_req,
11795 obj->last_write_req);
11796
11797 schedule_work(&work->mmio_work);
11798 } else {
11799 i915_gem_request_assign(&work->flip_queued_req, request);
11800 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11801 page_flip_flags);
11802 if (ret)
11803 goto cleanup_unpin;
11804
11805 intel_mark_page_flip_active(intel_crtc, work);
11806
11807 i915_add_request_no_flush(request);
11808 }
11809
11810 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11811 to_intel_plane(primary)->frontbuffer_bit);
11812 mutex_unlock(&dev->struct_mutex);
11813
11814 intel_frontbuffer_flip_prepare(dev,
11815 to_intel_plane(primary)->frontbuffer_bit);
11816
11817 trace_i915_flip_request(intel_crtc->plane, obj);
11818
11819 return 0;
11820
11821 cleanup_unpin:
11822 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11823 cleanup_pending:
11824 if (!IS_ERR_OR_NULL(request))
11825 i915_add_request_no_flush(request);
11826 atomic_dec(&intel_crtc->unpin_work_count);
11827 mutex_unlock(&dev->struct_mutex);
11828 cleanup:
11829 crtc->primary->fb = old_fb;
11830 update_state_fb(crtc->primary);
11831
11832 drm_gem_object_unreference_unlocked(&obj->base);
11833 drm_framebuffer_unreference(work->old_fb);
11834
11835 spin_lock_irq(&dev->event_lock);
11836 intel_crtc->flip_work = NULL;
11837 spin_unlock_irq(&dev->event_lock);
11838
11839 drm_crtc_vblank_put(crtc);
11840 free_work:
11841 kfree(work);
11842
11843 if (ret == -EIO) {
11844 struct drm_atomic_state *state;
11845 struct drm_plane_state *plane_state;
11846
11847 out_hang:
11848 state = drm_atomic_state_alloc(dev);
11849 if (!state)
11850 return -ENOMEM;
11851 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11852
11853 retry:
11854 plane_state = drm_atomic_get_plane_state(state, primary);
11855 ret = PTR_ERR_OR_ZERO(plane_state);
11856 if (!ret) {
11857 drm_atomic_set_fb_for_plane(plane_state, fb);
11858
11859 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11860 if (!ret)
11861 ret = drm_atomic_commit(state);
11862 }
11863
11864 if (ret == -EDEADLK) {
11865 drm_modeset_backoff(state->acquire_ctx);
11866 drm_atomic_state_clear(state);
11867 goto retry;
11868 }
11869
11870 if (ret)
11871 drm_atomic_state_free(state);
11872
11873 if (ret == 0 && event) {
11874 spin_lock_irq(&dev->event_lock);
11875 drm_crtc_send_vblank_event(crtc, event);
11876 spin_unlock_irq(&dev->event_lock);
11877 }
11878 }
11879 return ret;
11880 }
11881
11882
11883 /**
11884 * intel_wm_need_update - Check whether watermarks need updating
11885 * @plane: drm plane
11886 * @state: new plane state
11887 *
11888 * Check current plane state versus the new one to determine whether
11889 * watermarks need to be recalculated.
11890 *
11891 * Returns true or false.
11892 */
11893 static bool intel_wm_need_update(struct drm_plane *plane,
11894 struct drm_plane_state *state)
11895 {
11896 struct intel_plane_state *new = to_intel_plane_state(state);
11897 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11898
11899 /* Update watermarks on tiling or size changes. */
11900 if (new->visible != cur->visible)
11901 return true;
11902
11903 if (!cur->base.fb || !new->base.fb)
11904 return false;
11905
11906 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11907 cur->base.rotation != new->base.rotation ||
11908 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11909 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11910 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11911 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11912 return true;
11913
11914 return false;
11915 }
11916
11917 static bool needs_scaling(struct intel_plane_state *state)
11918 {
11919 int src_w = drm_rect_width(&state->src) >> 16;
11920 int src_h = drm_rect_height(&state->src) >> 16;
11921 int dst_w = drm_rect_width(&state->dst);
11922 int dst_h = drm_rect_height(&state->dst);
11923
11924 return (src_w != dst_w || src_h != dst_h);
11925 }
11926
11927 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11928 struct drm_plane_state *plane_state)
11929 {
11930 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11931 struct drm_crtc *crtc = crtc_state->crtc;
11932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11933 struct drm_plane *plane = plane_state->plane;
11934 struct drm_device *dev = crtc->dev;
11935 struct drm_i915_private *dev_priv = to_i915(dev);
11936 struct intel_plane_state *old_plane_state =
11937 to_intel_plane_state(plane->state);
11938 bool mode_changed = needs_modeset(crtc_state);
11939 bool was_crtc_enabled = crtc->state->active;
11940 bool is_crtc_enabled = crtc_state->active;
11941 bool turn_off, turn_on, visible, was_visible;
11942 struct drm_framebuffer *fb = plane_state->fb;
11943 int ret;
11944
11945 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11946 plane->type != DRM_PLANE_TYPE_CURSOR) {
11947 ret = skl_update_scaler_plane(
11948 to_intel_crtc_state(crtc_state),
11949 to_intel_plane_state(plane_state));
11950 if (ret)
11951 return ret;
11952 }
11953
11954 was_visible = old_plane_state->visible;
11955 visible = to_intel_plane_state(plane_state)->visible;
11956
11957 if (!was_crtc_enabled && WARN_ON(was_visible))
11958 was_visible = false;
11959
11960 /*
11961 * Visibility is calculated as if the crtc was on, but
11962 * after scaler setup everything depends on it being off
11963 * when the crtc isn't active.
11964 *
11965 * FIXME this is wrong for watermarks. Watermarks should also
11966 * be computed as if the pipe would be active. Perhaps move
11967 * per-plane wm computation to the .check_plane() hook, and
11968 * only combine the results from all planes in the current place?
11969 */
11970 if (!is_crtc_enabled)
11971 to_intel_plane_state(plane_state)->visible = visible = false;
11972
11973 if (!was_visible && !visible)
11974 return 0;
11975
11976 if (fb != old_plane_state->base.fb)
11977 pipe_config->fb_changed = true;
11978
11979 turn_off = was_visible && (!visible || mode_changed);
11980 turn_on = visible && (!was_visible || mode_changed);
11981
11982 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11983 intel_crtc->base.base.id,
11984 intel_crtc->base.name,
11985 plane->base.id, plane->name,
11986 fb ? fb->base.id : -1);
11987
11988 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11989 plane->base.id, plane->name,
11990 was_visible, visible,
11991 turn_off, turn_on, mode_changed);
11992
11993 if (turn_on) {
11994 pipe_config->update_wm_pre = true;
11995
11996 /* must disable cxsr around plane enable/disable */
11997 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11998 pipe_config->disable_cxsr = true;
11999 } else if (turn_off) {
12000 pipe_config->update_wm_post = true;
12001
12002 /* must disable cxsr around plane enable/disable */
12003 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12004 pipe_config->disable_cxsr = true;
12005 } else if (intel_wm_need_update(plane, plane_state)) {
12006 /* FIXME bollocks */
12007 pipe_config->update_wm_pre = true;
12008 pipe_config->update_wm_post = true;
12009 }
12010
12011 /* Pre-gen9 platforms need two-step watermark updates */
12012 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12013 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12014 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12015
12016 if (visible || was_visible)
12017 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12018
12019 /*
12020 * WaCxSRDisabledForSpriteScaling:ivb
12021 *
12022 * cstate->update_wm was already set above, so this flag will
12023 * take effect when we commit and program watermarks.
12024 */
12025 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12026 needs_scaling(to_intel_plane_state(plane_state)) &&
12027 !needs_scaling(old_plane_state))
12028 pipe_config->disable_lp_wm = true;
12029
12030 return 0;
12031 }
12032
12033 static bool encoders_cloneable(const struct intel_encoder *a,
12034 const struct intel_encoder *b)
12035 {
12036 /* masks could be asymmetric, so check both ways */
12037 return a == b || (a->cloneable & (1 << b->type) &&
12038 b->cloneable & (1 << a->type));
12039 }
12040
12041 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12042 struct intel_crtc *crtc,
12043 struct intel_encoder *encoder)
12044 {
12045 struct intel_encoder *source_encoder;
12046 struct drm_connector *connector;
12047 struct drm_connector_state *connector_state;
12048 int i;
12049
12050 for_each_connector_in_state(state, connector, connector_state, i) {
12051 if (connector_state->crtc != &crtc->base)
12052 continue;
12053
12054 source_encoder =
12055 to_intel_encoder(connector_state->best_encoder);
12056 if (!encoders_cloneable(encoder, source_encoder))
12057 return false;
12058 }
12059
12060 return true;
12061 }
12062
12063 static bool check_encoder_cloning(struct drm_atomic_state *state,
12064 struct intel_crtc *crtc)
12065 {
12066 struct intel_encoder *encoder;
12067 struct drm_connector *connector;
12068 struct drm_connector_state *connector_state;
12069 int i;
12070
12071 for_each_connector_in_state(state, connector, connector_state, i) {
12072 if (connector_state->crtc != &crtc->base)
12073 continue;
12074
12075 encoder = to_intel_encoder(connector_state->best_encoder);
12076 if (!check_single_encoder_cloning(state, crtc, encoder))
12077 return false;
12078 }
12079
12080 return true;
12081 }
12082
12083 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12084 struct drm_crtc_state *crtc_state)
12085 {
12086 struct drm_device *dev = crtc->dev;
12087 struct drm_i915_private *dev_priv = dev->dev_private;
12088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12089 struct intel_crtc_state *pipe_config =
12090 to_intel_crtc_state(crtc_state);
12091 struct drm_atomic_state *state = crtc_state->state;
12092 int ret;
12093 bool mode_changed = needs_modeset(crtc_state);
12094
12095 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12096 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12097 return -EINVAL;
12098 }
12099
12100 if (mode_changed && !crtc_state->active)
12101 pipe_config->update_wm_post = true;
12102
12103 if (mode_changed && crtc_state->enable &&
12104 dev_priv->display.crtc_compute_clock &&
12105 !WARN_ON(pipe_config->shared_dpll)) {
12106 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12107 pipe_config);
12108 if (ret)
12109 return ret;
12110 }
12111
12112 if (crtc_state->color_mgmt_changed) {
12113 ret = intel_color_check(crtc, crtc_state);
12114 if (ret)
12115 return ret;
12116 }
12117
12118 ret = 0;
12119 if (dev_priv->display.compute_pipe_wm) {
12120 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12121 if (ret) {
12122 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12123 return ret;
12124 }
12125 }
12126
12127 if (dev_priv->display.compute_intermediate_wm &&
12128 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12129 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12130 return 0;
12131
12132 /*
12133 * Calculate 'intermediate' watermarks that satisfy both the
12134 * old state and the new state. We can program these
12135 * immediately.
12136 */
12137 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12138 intel_crtc,
12139 pipe_config);
12140 if (ret) {
12141 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12142 return ret;
12143 }
12144 } else if (dev_priv->display.compute_intermediate_wm) {
12145 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12146 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12147 }
12148
12149 if (INTEL_INFO(dev)->gen >= 9) {
12150 if (mode_changed)
12151 ret = skl_update_scaler_crtc(pipe_config);
12152
12153 if (!ret)
12154 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12155 pipe_config);
12156 }
12157
12158 return ret;
12159 }
12160
12161 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12162 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12163 .atomic_begin = intel_begin_crtc_commit,
12164 .atomic_flush = intel_finish_crtc_commit,
12165 .atomic_check = intel_crtc_atomic_check,
12166 };
12167
12168 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12169 {
12170 struct intel_connector *connector;
12171
12172 for_each_intel_connector(dev, connector) {
12173 if (connector->base.state->crtc)
12174 drm_connector_unreference(&connector->base);
12175
12176 if (connector->base.encoder) {
12177 connector->base.state->best_encoder =
12178 connector->base.encoder;
12179 connector->base.state->crtc =
12180 connector->base.encoder->crtc;
12181
12182 drm_connector_reference(&connector->base);
12183 } else {
12184 connector->base.state->best_encoder = NULL;
12185 connector->base.state->crtc = NULL;
12186 }
12187 }
12188 }
12189
12190 static void
12191 connected_sink_compute_bpp(struct intel_connector *connector,
12192 struct intel_crtc_state *pipe_config)
12193 {
12194 int bpp = pipe_config->pipe_bpp;
12195
12196 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12197 connector->base.base.id,
12198 connector->base.name);
12199
12200 /* Don't use an invalid EDID bpc value */
12201 if (connector->base.display_info.bpc &&
12202 connector->base.display_info.bpc * 3 < bpp) {
12203 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12204 bpp, connector->base.display_info.bpc*3);
12205 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12206 }
12207
12208 /* Clamp bpp to default limit on screens without EDID 1.4 */
12209 if (connector->base.display_info.bpc == 0) {
12210 int type = connector->base.connector_type;
12211 int clamp_bpp = 24;
12212
12213 /* Fall back to 18 bpp when DP sink capability is unknown. */
12214 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12215 type == DRM_MODE_CONNECTOR_eDP)
12216 clamp_bpp = 18;
12217
12218 if (bpp > clamp_bpp) {
12219 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12220 bpp, clamp_bpp);
12221 pipe_config->pipe_bpp = clamp_bpp;
12222 }
12223 }
12224 }
12225
12226 static int
12227 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12228 struct intel_crtc_state *pipe_config)
12229 {
12230 struct drm_device *dev = crtc->base.dev;
12231 struct drm_atomic_state *state;
12232 struct drm_connector *connector;
12233 struct drm_connector_state *connector_state;
12234 int bpp, i;
12235
12236 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12237 bpp = 10*3;
12238 else if (INTEL_INFO(dev)->gen >= 5)
12239 bpp = 12*3;
12240 else
12241 bpp = 8*3;
12242
12243
12244 pipe_config->pipe_bpp = bpp;
12245
12246 state = pipe_config->base.state;
12247
12248 /* Clamp display bpp to EDID value */
12249 for_each_connector_in_state(state, connector, connector_state, i) {
12250 if (connector_state->crtc != &crtc->base)
12251 continue;
12252
12253 connected_sink_compute_bpp(to_intel_connector(connector),
12254 pipe_config);
12255 }
12256
12257 return bpp;
12258 }
12259
12260 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12261 {
12262 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12263 "type: 0x%x flags: 0x%x\n",
12264 mode->crtc_clock,
12265 mode->crtc_hdisplay, mode->crtc_hsync_start,
12266 mode->crtc_hsync_end, mode->crtc_htotal,
12267 mode->crtc_vdisplay, mode->crtc_vsync_start,
12268 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12269 }
12270
12271 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12272 struct intel_crtc_state *pipe_config,
12273 const char *context)
12274 {
12275 struct drm_device *dev = crtc->base.dev;
12276 struct drm_plane *plane;
12277 struct intel_plane *intel_plane;
12278 struct intel_plane_state *state;
12279 struct drm_framebuffer *fb;
12280
12281 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12282 crtc->base.base.id, crtc->base.name,
12283 context, pipe_config, pipe_name(crtc->pipe));
12284
12285 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12286 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12287 pipe_config->pipe_bpp, pipe_config->dither);
12288 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12289 pipe_config->has_pch_encoder,
12290 pipe_config->fdi_lanes,
12291 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12292 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12293 pipe_config->fdi_m_n.tu);
12294 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12295 pipe_config->has_dp_encoder,
12296 pipe_config->lane_count,
12297 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12298 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12299 pipe_config->dp_m_n.tu);
12300
12301 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12302 pipe_config->has_dp_encoder,
12303 pipe_config->lane_count,
12304 pipe_config->dp_m2_n2.gmch_m,
12305 pipe_config->dp_m2_n2.gmch_n,
12306 pipe_config->dp_m2_n2.link_m,
12307 pipe_config->dp_m2_n2.link_n,
12308 pipe_config->dp_m2_n2.tu);
12309
12310 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12311 pipe_config->has_audio,
12312 pipe_config->has_infoframe);
12313
12314 DRM_DEBUG_KMS("requested mode:\n");
12315 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12316 DRM_DEBUG_KMS("adjusted mode:\n");
12317 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12318 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12319 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12320 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12321 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12322 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12323 crtc->num_scalers,
12324 pipe_config->scaler_state.scaler_users,
12325 pipe_config->scaler_state.scaler_id);
12326 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12327 pipe_config->gmch_pfit.control,
12328 pipe_config->gmch_pfit.pgm_ratios,
12329 pipe_config->gmch_pfit.lvds_border_bits);
12330 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12331 pipe_config->pch_pfit.pos,
12332 pipe_config->pch_pfit.size,
12333 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12334 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12335 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12336
12337 if (IS_BROXTON(dev)) {
12338 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12339 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12340 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12341 pipe_config->ddi_pll_sel,
12342 pipe_config->dpll_hw_state.ebb0,
12343 pipe_config->dpll_hw_state.ebb4,
12344 pipe_config->dpll_hw_state.pll0,
12345 pipe_config->dpll_hw_state.pll1,
12346 pipe_config->dpll_hw_state.pll2,
12347 pipe_config->dpll_hw_state.pll3,
12348 pipe_config->dpll_hw_state.pll6,
12349 pipe_config->dpll_hw_state.pll8,
12350 pipe_config->dpll_hw_state.pll9,
12351 pipe_config->dpll_hw_state.pll10,
12352 pipe_config->dpll_hw_state.pcsdw12);
12353 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12354 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12355 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12356 pipe_config->ddi_pll_sel,
12357 pipe_config->dpll_hw_state.ctrl1,
12358 pipe_config->dpll_hw_state.cfgcr1,
12359 pipe_config->dpll_hw_state.cfgcr2);
12360 } else if (HAS_DDI(dev)) {
12361 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12362 pipe_config->ddi_pll_sel,
12363 pipe_config->dpll_hw_state.wrpll,
12364 pipe_config->dpll_hw_state.spll);
12365 } else {
12366 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12367 "fp0: 0x%x, fp1: 0x%x\n",
12368 pipe_config->dpll_hw_state.dpll,
12369 pipe_config->dpll_hw_state.dpll_md,
12370 pipe_config->dpll_hw_state.fp0,
12371 pipe_config->dpll_hw_state.fp1);
12372 }
12373
12374 DRM_DEBUG_KMS("planes on this crtc\n");
12375 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12376 intel_plane = to_intel_plane(plane);
12377 if (intel_plane->pipe != crtc->pipe)
12378 continue;
12379
12380 state = to_intel_plane_state(plane->state);
12381 fb = state->base.fb;
12382 if (!fb) {
12383 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12384 plane->base.id, plane->name, state->scaler_id);
12385 continue;
12386 }
12387
12388 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12389 plane->base.id, plane->name);
12390 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12391 fb->base.id, fb->width, fb->height,
12392 drm_get_format_name(fb->pixel_format));
12393 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12394 state->scaler_id,
12395 state->src.x1 >> 16, state->src.y1 >> 16,
12396 drm_rect_width(&state->src) >> 16,
12397 drm_rect_height(&state->src) >> 16,
12398 state->dst.x1, state->dst.y1,
12399 drm_rect_width(&state->dst),
12400 drm_rect_height(&state->dst));
12401 }
12402 }
12403
12404 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12405 {
12406 struct drm_device *dev = state->dev;
12407 struct drm_connector *connector;
12408 unsigned int used_ports = 0;
12409
12410 /*
12411 * Walk the connector list instead of the encoder
12412 * list to detect the problem on ddi platforms
12413 * where there's just one encoder per digital port.
12414 */
12415 drm_for_each_connector(connector, dev) {
12416 struct drm_connector_state *connector_state;
12417 struct intel_encoder *encoder;
12418
12419 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12420 if (!connector_state)
12421 connector_state = connector->state;
12422
12423 if (!connector_state->best_encoder)
12424 continue;
12425
12426 encoder = to_intel_encoder(connector_state->best_encoder);
12427
12428 WARN_ON(!connector_state->crtc);
12429
12430 switch (encoder->type) {
12431 unsigned int port_mask;
12432 case INTEL_OUTPUT_UNKNOWN:
12433 if (WARN_ON(!HAS_DDI(dev)))
12434 break;
12435 case INTEL_OUTPUT_DISPLAYPORT:
12436 case INTEL_OUTPUT_HDMI:
12437 case INTEL_OUTPUT_EDP:
12438 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12439
12440 /* the same port mustn't appear more than once */
12441 if (used_ports & port_mask)
12442 return false;
12443
12444 used_ports |= port_mask;
12445 default:
12446 break;
12447 }
12448 }
12449
12450 return true;
12451 }
12452
12453 static void
12454 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12455 {
12456 struct drm_crtc_state tmp_state;
12457 struct intel_crtc_scaler_state scaler_state;
12458 struct intel_dpll_hw_state dpll_hw_state;
12459 struct intel_shared_dpll *shared_dpll;
12460 uint32_t ddi_pll_sel;
12461 bool force_thru;
12462
12463 /* FIXME: before the switch to atomic started, a new pipe_config was
12464 * kzalloc'd. Code that depends on any field being zero should be
12465 * fixed, so that the crtc_state can be safely duplicated. For now,
12466 * only fields that are know to not cause problems are preserved. */
12467
12468 tmp_state = crtc_state->base;
12469 scaler_state = crtc_state->scaler_state;
12470 shared_dpll = crtc_state->shared_dpll;
12471 dpll_hw_state = crtc_state->dpll_hw_state;
12472 ddi_pll_sel = crtc_state->ddi_pll_sel;
12473 force_thru = crtc_state->pch_pfit.force_thru;
12474
12475 memset(crtc_state, 0, sizeof *crtc_state);
12476
12477 crtc_state->base = tmp_state;
12478 crtc_state->scaler_state = scaler_state;
12479 crtc_state->shared_dpll = shared_dpll;
12480 crtc_state->dpll_hw_state = dpll_hw_state;
12481 crtc_state->ddi_pll_sel = ddi_pll_sel;
12482 crtc_state->pch_pfit.force_thru = force_thru;
12483 }
12484
12485 static int
12486 intel_modeset_pipe_config(struct drm_crtc *crtc,
12487 struct intel_crtc_state *pipe_config)
12488 {
12489 struct drm_atomic_state *state = pipe_config->base.state;
12490 struct intel_encoder *encoder;
12491 struct drm_connector *connector;
12492 struct drm_connector_state *connector_state;
12493 int base_bpp, ret = -EINVAL;
12494 int i;
12495 bool retry = true;
12496
12497 clear_intel_crtc_state(pipe_config);
12498
12499 pipe_config->cpu_transcoder =
12500 (enum transcoder) to_intel_crtc(crtc)->pipe;
12501
12502 /*
12503 * Sanitize sync polarity flags based on requested ones. If neither
12504 * positive or negative polarity is requested, treat this as meaning
12505 * negative polarity.
12506 */
12507 if (!(pipe_config->base.adjusted_mode.flags &
12508 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12509 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12510
12511 if (!(pipe_config->base.adjusted_mode.flags &
12512 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12513 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12514
12515 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12516 pipe_config);
12517 if (base_bpp < 0)
12518 goto fail;
12519
12520 /*
12521 * Determine the real pipe dimensions. Note that stereo modes can
12522 * increase the actual pipe size due to the frame doubling and
12523 * insertion of additional space for blanks between the frame. This
12524 * is stored in the crtc timings. We use the requested mode to do this
12525 * computation to clearly distinguish it from the adjusted mode, which
12526 * can be changed by the connectors in the below retry loop.
12527 */
12528 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12529 &pipe_config->pipe_src_w,
12530 &pipe_config->pipe_src_h);
12531
12532 encoder_retry:
12533 /* Ensure the port clock defaults are reset when retrying. */
12534 pipe_config->port_clock = 0;
12535 pipe_config->pixel_multiplier = 1;
12536
12537 /* Fill in default crtc timings, allow encoders to overwrite them. */
12538 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12539 CRTC_STEREO_DOUBLE);
12540
12541 /* Pass our mode to the connectors and the CRTC to give them a chance to
12542 * adjust it according to limitations or connector properties, and also
12543 * a chance to reject the mode entirely.
12544 */
12545 for_each_connector_in_state(state, connector, connector_state, i) {
12546 if (connector_state->crtc != crtc)
12547 continue;
12548
12549 encoder = to_intel_encoder(connector_state->best_encoder);
12550
12551 if (!(encoder->compute_config(encoder, pipe_config))) {
12552 DRM_DEBUG_KMS("Encoder config failure\n");
12553 goto fail;
12554 }
12555 }
12556
12557 /* Set default port clock if not overwritten by the encoder. Needs to be
12558 * done afterwards in case the encoder adjusts the mode. */
12559 if (!pipe_config->port_clock)
12560 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12561 * pipe_config->pixel_multiplier;
12562
12563 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12564 if (ret < 0) {
12565 DRM_DEBUG_KMS("CRTC fixup failed\n");
12566 goto fail;
12567 }
12568
12569 if (ret == RETRY) {
12570 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12571 ret = -EINVAL;
12572 goto fail;
12573 }
12574
12575 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12576 retry = false;
12577 goto encoder_retry;
12578 }
12579
12580 /* Dithering seems to not pass-through bits correctly when it should, so
12581 * only enable it on 6bpc panels. */
12582 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12583 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12584 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12585
12586 fail:
12587 return ret;
12588 }
12589
12590 static void
12591 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12592 {
12593 struct drm_crtc *crtc;
12594 struct drm_crtc_state *crtc_state;
12595 int i;
12596
12597 /* Double check state. */
12598 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12599 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12600
12601 /* Update hwmode for vblank functions */
12602 if (crtc->state->active)
12603 crtc->hwmode = crtc->state->adjusted_mode;
12604 else
12605 crtc->hwmode.crtc_clock = 0;
12606
12607 /*
12608 * Update legacy state to satisfy fbc code. This can
12609 * be removed when fbc uses the atomic state.
12610 */
12611 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12612 struct drm_plane_state *plane_state = crtc->primary->state;
12613
12614 crtc->primary->fb = plane_state->fb;
12615 crtc->x = plane_state->src_x >> 16;
12616 crtc->y = plane_state->src_y >> 16;
12617 }
12618 }
12619 }
12620
12621 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12622 {
12623 int diff;
12624
12625 if (clock1 == clock2)
12626 return true;
12627
12628 if (!clock1 || !clock2)
12629 return false;
12630
12631 diff = abs(clock1 - clock2);
12632
12633 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12634 return true;
12635
12636 return false;
12637 }
12638
12639 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12640 list_for_each_entry((intel_crtc), \
12641 &(dev)->mode_config.crtc_list, \
12642 base.head) \
12643 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12644
12645 static bool
12646 intel_compare_m_n(unsigned int m, unsigned int n,
12647 unsigned int m2, unsigned int n2,
12648 bool exact)
12649 {
12650 if (m == m2 && n == n2)
12651 return true;
12652
12653 if (exact || !m || !n || !m2 || !n2)
12654 return false;
12655
12656 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12657
12658 if (n > n2) {
12659 while (n > n2) {
12660 m2 <<= 1;
12661 n2 <<= 1;
12662 }
12663 } else if (n < n2) {
12664 while (n < n2) {
12665 m <<= 1;
12666 n <<= 1;
12667 }
12668 }
12669
12670 if (n != n2)
12671 return false;
12672
12673 return intel_fuzzy_clock_check(m, m2);
12674 }
12675
12676 static bool
12677 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12678 struct intel_link_m_n *m2_n2,
12679 bool adjust)
12680 {
12681 if (m_n->tu == m2_n2->tu &&
12682 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12683 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12684 intel_compare_m_n(m_n->link_m, m_n->link_n,
12685 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12686 if (adjust)
12687 *m2_n2 = *m_n;
12688
12689 return true;
12690 }
12691
12692 return false;
12693 }
12694
12695 static bool
12696 intel_pipe_config_compare(struct drm_device *dev,
12697 struct intel_crtc_state *current_config,
12698 struct intel_crtc_state *pipe_config,
12699 bool adjust)
12700 {
12701 bool ret = true;
12702
12703 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12704 do { \
12705 if (!adjust) \
12706 DRM_ERROR(fmt, ##__VA_ARGS__); \
12707 else \
12708 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12709 } while (0)
12710
12711 #define PIPE_CONF_CHECK_X(name) \
12712 if (current_config->name != pipe_config->name) { \
12713 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12714 "(expected 0x%08x, found 0x%08x)\n", \
12715 current_config->name, \
12716 pipe_config->name); \
12717 ret = false; \
12718 }
12719
12720 #define PIPE_CONF_CHECK_I(name) \
12721 if (current_config->name != pipe_config->name) { \
12722 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12723 "(expected %i, found %i)\n", \
12724 current_config->name, \
12725 pipe_config->name); \
12726 ret = false; \
12727 }
12728
12729 #define PIPE_CONF_CHECK_P(name) \
12730 if (current_config->name != pipe_config->name) { \
12731 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12732 "(expected %p, found %p)\n", \
12733 current_config->name, \
12734 pipe_config->name); \
12735 ret = false; \
12736 }
12737
12738 #define PIPE_CONF_CHECK_M_N(name) \
12739 if (!intel_compare_link_m_n(&current_config->name, \
12740 &pipe_config->name,\
12741 adjust)) { \
12742 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12743 "(expected tu %i gmch %i/%i link %i/%i, " \
12744 "found tu %i, gmch %i/%i link %i/%i)\n", \
12745 current_config->name.tu, \
12746 current_config->name.gmch_m, \
12747 current_config->name.gmch_n, \
12748 current_config->name.link_m, \
12749 current_config->name.link_n, \
12750 pipe_config->name.tu, \
12751 pipe_config->name.gmch_m, \
12752 pipe_config->name.gmch_n, \
12753 pipe_config->name.link_m, \
12754 pipe_config->name.link_n); \
12755 ret = false; \
12756 }
12757
12758 /* This is required for BDW+ where there is only one set of registers for
12759 * switching between high and low RR.
12760 * This macro can be used whenever a comparison has to be made between one
12761 * hw state and multiple sw state variables.
12762 */
12763 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12764 if (!intel_compare_link_m_n(&current_config->name, \
12765 &pipe_config->name, adjust) && \
12766 !intel_compare_link_m_n(&current_config->alt_name, \
12767 &pipe_config->name, adjust)) { \
12768 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12769 "(expected tu %i gmch %i/%i link %i/%i, " \
12770 "or tu %i gmch %i/%i link %i/%i, " \
12771 "found tu %i, gmch %i/%i link %i/%i)\n", \
12772 current_config->name.tu, \
12773 current_config->name.gmch_m, \
12774 current_config->name.gmch_n, \
12775 current_config->name.link_m, \
12776 current_config->name.link_n, \
12777 current_config->alt_name.tu, \
12778 current_config->alt_name.gmch_m, \
12779 current_config->alt_name.gmch_n, \
12780 current_config->alt_name.link_m, \
12781 current_config->alt_name.link_n, \
12782 pipe_config->name.tu, \
12783 pipe_config->name.gmch_m, \
12784 pipe_config->name.gmch_n, \
12785 pipe_config->name.link_m, \
12786 pipe_config->name.link_n); \
12787 ret = false; \
12788 }
12789
12790 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12791 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12792 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12793 "(expected %i, found %i)\n", \
12794 current_config->name & (mask), \
12795 pipe_config->name & (mask)); \
12796 ret = false; \
12797 }
12798
12799 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12800 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12801 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12802 "(expected %i, found %i)\n", \
12803 current_config->name, \
12804 pipe_config->name); \
12805 ret = false; \
12806 }
12807
12808 #define PIPE_CONF_QUIRK(quirk) \
12809 ((current_config->quirks | pipe_config->quirks) & (quirk))
12810
12811 PIPE_CONF_CHECK_I(cpu_transcoder);
12812
12813 PIPE_CONF_CHECK_I(has_pch_encoder);
12814 PIPE_CONF_CHECK_I(fdi_lanes);
12815 PIPE_CONF_CHECK_M_N(fdi_m_n);
12816
12817 PIPE_CONF_CHECK_I(has_dp_encoder);
12818 PIPE_CONF_CHECK_I(lane_count);
12819
12820 if (INTEL_INFO(dev)->gen < 8) {
12821 PIPE_CONF_CHECK_M_N(dp_m_n);
12822
12823 if (current_config->has_drrs)
12824 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12825 } else
12826 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12827
12828 PIPE_CONF_CHECK_I(has_dsi_encoder);
12829
12830 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12831 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12832 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12833 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12834 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12835 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12836
12837 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12838 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12839 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12840 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12841 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12842 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12843
12844 PIPE_CONF_CHECK_I(pixel_multiplier);
12845 PIPE_CONF_CHECK_I(has_hdmi_sink);
12846 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12847 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12848 PIPE_CONF_CHECK_I(limited_color_range);
12849 PIPE_CONF_CHECK_I(has_infoframe);
12850
12851 PIPE_CONF_CHECK_I(has_audio);
12852
12853 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12854 DRM_MODE_FLAG_INTERLACE);
12855
12856 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12857 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12858 DRM_MODE_FLAG_PHSYNC);
12859 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12860 DRM_MODE_FLAG_NHSYNC);
12861 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12862 DRM_MODE_FLAG_PVSYNC);
12863 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12864 DRM_MODE_FLAG_NVSYNC);
12865 }
12866
12867 PIPE_CONF_CHECK_X(gmch_pfit.control);
12868 /* pfit ratios are autocomputed by the hw on gen4+ */
12869 if (INTEL_INFO(dev)->gen < 4)
12870 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12871 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12872
12873 if (!adjust) {
12874 PIPE_CONF_CHECK_I(pipe_src_w);
12875 PIPE_CONF_CHECK_I(pipe_src_h);
12876
12877 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12878 if (current_config->pch_pfit.enabled) {
12879 PIPE_CONF_CHECK_X(pch_pfit.pos);
12880 PIPE_CONF_CHECK_X(pch_pfit.size);
12881 }
12882
12883 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12884 }
12885
12886 /* BDW+ don't expose a synchronous way to read the state */
12887 if (IS_HASWELL(dev))
12888 PIPE_CONF_CHECK_I(ips_enabled);
12889
12890 PIPE_CONF_CHECK_I(double_wide);
12891
12892 PIPE_CONF_CHECK_X(ddi_pll_sel);
12893
12894 PIPE_CONF_CHECK_P(shared_dpll);
12895 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12896 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12897 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12898 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12899 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12900 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12901 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12902 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12903 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12904
12905 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12906 PIPE_CONF_CHECK_X(dsi_pll.div);
12907
12908 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12909 PIPE_CONF_CHECK_I(pipe_bpp);
12910
12911 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12912 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12913
12914 #undef PIPE_CONF_CHECK_X
12915 #undef PIPE_CONF_CHECK_I
12916 #undef PIPE_CONF_CHECK_P
12917 #undef PIPE_CONF_CHECK_FLAGS
12918 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12919 #undef PIPE_CONF_QUIRK
12920 #undef INTEL_ERR_OR_DBG_KMS
12921
12922 return ret;
12923 }
12924
12925 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12926 const struct intel_crtc_state *pipe_config)
12927 {
12928 if (pipe_config->has_pch_encoder) {
12929 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12930 &pipe_config->fdi_m_n);
12931 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12932
12933 /*
12934 * FDI already provided one idea for the dotclock.
12935 * Yell if the encoder disagrees.
12936 */
12937 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12938 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12939 fdi_dotclock, dotclock);
12940 }
12941 }
12942
12943 static void verify_wm_state(struct drm_crtc *crtc,
12944 struct drm_crtc_state *new_state)
12945 {
12946 struct drm_device *dev = crtc->dev;
12947 struct drm_i915_private *dev_priv = dev->dev_private;
12948 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12949 struct skl_ddb_entry *hw_entry, *sw_entry;
12950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12951 const enum pipe pipe = intel_crtc->pipe;
12952 int plane;
12953
12954 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12955 return;
12956
12957 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12958 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12959
12960 /* planes */
12961 for_each_plane(dev_priv, pipe, plane) {
12962 hw_entry = &hw_ddb.plane[pipe][plane];
12963 sw_entry = &sw_ddb->plane[pipe][plane];
12964
12965 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12966 continue;
12967
12968 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12969 "(expected (%u,%u), found (%u,%u))\n",
12970 pipe_name(pipe), plane + 1,
12971 sw_entry->start, sw_entry->end,
12972 hw_entry->start, hw_entry->end);
12973 }
12974
12975 /* cursor */
12976 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12977 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12978
12979 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12980 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12981 "(expected (%u,%u), found (%u,%u))\n",
12982 pipe_name(pipe),
12983 sw_entry->start, sw_entry->end,
12984 hw_entry->start, hw_entry->end);
12985 }
12986 }
12987
12988 static void
12989 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12990 {
12991 struct drm_connector *connector;
12992
12993 drm_for_each_connector(connector, dev) {
12994 struct drm_encoder *encoder = connector->encoder;
12995 struct drm_connector_state *state = connector->state;
12996
12997 if (state->crtc != crtc)
12998 continue;
12999
13000 intel_connector_verify_state(to_intel_connector(connector));
13001
13002 I915_STATE_WARN(state->best_encoder != encoder,
13003 "connector's atomic encoder doesn't match legacy encoder\n");
13004 }
13005 }
13006
13007 static void
13008 verify_encoder_state(struct drm_device *dev)
13009 {
13010 struct intel_encoder *encoder;
13011 struct intel_connector *connector;
13012
13013 for_each_intel_encoder(dev, encoder) {
13014 bool enabled = false;
13015 enum pipe pipe;
13016
13017 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13018 encoder->base.base.id,
13019 encoder->base.name);
13020
13021 for_each_intel_connector(dev, connector) {
13022 if (connector->base.state->best_encoder != &encoder->base)
13023 continue;
13024 enabled = true;
13025
13026 I915_STATE_WARN(connector->base.state->crtc !=
13027 encoder->base.crtc,
13028 "connector's crtc doesn't match encoder crtc\n");
13029 }
13030
13031 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13032 "encoder's enabled state mismatch "
13033 "(expected %i, found %i)\n",
13034 !!encoder->base.crtc, enabled);
13035
13036 if (!encoder->base.crtc) {
13037 bool active;
13038
13039 active = encoder->get_hw_state(encoder, &pipe);
13040 I915_STATE_WARN(active,
13041 "encoder detached but still enabled on pipe %c.\n",
13042 pipe_name(pipe));
13043 }
13044 }
13045 }
13046
13047 static void
13048 verify_crtc_state(struct drm_crtc *crtc,
13049 struct drm_crtc_state *old_crtc_state,
13050 struct drm_crtc_state *new_crtc_state)
13051 {
13052 struct drm_device *dev = crtc->dev;
13053 struct drm_i915_private *dev_priv = dev->dev_private;
13054 struct intel_encoder *encoder;
13055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13056 struct intel_crtc_state *pipe_config, *sw_config;
13057 struct drm_atomic_state *old_state;
13058 bool active;
13059
13060 old_state = old_crtc_state->state;
13061 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13062 pipe_config = to_intel_crtc_state(old_crtc_state);
13063 memset(pipe_config, 0, sizeof(*pipe_config));
13064 pipe_config->base.crtc = crtc;
13065 pipe_config->base.state = old_state;
13066
13067 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13068
13069 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13070
13071 /* hw state is inconsistent with the pipe quirk */
13072 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13073 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13074 active = new_crtc_state->active;
13075
13076 I915_STATE_WARN(new_crtc_state->active != active,
13077 "crtc active state doesn't match with hw state "
13078 "(expected %i, found %i)\n", new_crtc_state->active, active);
13079
13080 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13081 "transitional active state does not match atomic hw state "
13082 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13083
13084 for_each_encoder_on_crtc(dev, crtc, encoder) {
13085 enum pipe pipe;
13086
13087 active = encoder->get_hw_state(encoder, &pipe);
13088 I915_STATE_WARN(active != new_crtc_state->active,
13089 "[ENCODER:%i] active %i with crtc active %i\n",
13090 encoder->base.base.id, active, new_crtc_state->active);
13091
13092 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13093 "Encoder connected to wrong pipe %c\n",
13094 pipe_name(pipe));
13095
13096 if (active)
13097 encoder->get_config(encoder, pipe_config);
13098 }
13099
13100 if (!new_crtc_state->active)
13101 return;
13102
13103 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13104
13105 sw_config = to_intel_crtc_state(crtc->state);
13106 if (!intel_pipe_config_compare(dev, sw_config,
13107 pipe_config, false)) {
13108 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13109 intel_dump_pipe_config(intel_crtc, pipe_config,
13110 "[hw state]");
13111 intel_dump_pipe_config(intel_crtc, sw_config,
13112 "[sw state]");
13113 }
13114 }
13115
13116 static void
13117 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13118 struct intel_shared_dpll *pll,
13119 struct drm_crtc *crtc,
13120 struct drm_crtc_state *new_state)
13121 {
13122 struct intel_dpll_hw_state dpll_hw_state;
13123 unsigned crtc_mask;
13124 bool active;
13125
13126 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13127
13128 DRM_DEBUG_KMS("%s\n", pll->name);
13129
13130 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13131
13132 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13133 I915_STATE_WARN(!pll->on && pll->active_mask,
13134 "pll in active use but not on in sw tracking\n");
13135 I915_STATE_WARN(pll->on && !pll->active_mask,
13136 "pll is on but not used by any active crtc\n");
13137 I915_STATE_WARN(pll->on != active,
13138 "pll on state mismatch (expected %i, found %i)\n",
13139 pll->on, active);
13140 }
13141
13142 if (!crtc) {
13143 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13144 "more active pll users than references: %x vs %x\n",
13145 pll->active_mask, pll->config.crtc_mask);
13146
13147 return;
13148 }
13149
13150 crtc_mask = 1 << drm_crtc_index(crtc);
13151
13152 if (new_state->active)
13153 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13154 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13155 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13156 else
13157 I915_STATE_WARN(pll->active_mask & crtc_mask,
13158 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13159 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13160
13161 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13162 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13163 crtc_mask, pll->config.crtc_mask);
13164
13165 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13166 &dpll_hw_state,
13167 sizeof(dpll_hw_state)),
13168 "pll hw state mismatch\n");
13169 }
13170
13171 static void
13172 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13173 struct drm_crtc_state *old_crtc_state,
13174 struct drm_crtc_state *new_crtc_state)
13175 {
13176 struct drm_i915_private *dev_priv = dev->dev_private;
13177 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13178 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13179
13180 if (new_state->shared_dpll)
13181 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13182
13183 if (old_state->shared_dpll &&
13184 old_state->shared_dpll != new_state->shared_dpll) {
13185 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13186 struct intel_shared_dpll *pll = old_state->shared_dpll;
13187
13188 I915_STATE_WARN(pll->active_mask & crtc_mask,
13189 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13190 pipe_name(drm_crtc_index(crtc)));
13191 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13192 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13193 pipe_name(drm_crtc_index(crtc)));
13194 }
13195 }
13196
13197 static void
13198 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13199 struct drm_crtc_state *old_state,
13200 struct drm_crtc_state *new_state)
13201 {
13202 if (!needs_modeset(new_state) &&
13203 !to_intel_crtc_state(new_state)->update_pipe)
13204 return;
13205
13206 verify_wm_state(crtc, new_state);
13207 verify_connector_state(crtc->dev, crtc);
13208 verify_crtc_state(crtc, old_state, new_state);
13209 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13210 }
13211
13212 static void
13213 verify_disabled_dpll_state(struct drm_device *dev)
13214 {
13215 struct drm_i915_private *dev_priv = dev->dev_private;
13216 int i;
13217
13218 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13219 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13220 }
13221
13222 static void
13223 intel_modeset_verify_disabled(struct drm_device *dev)
13224 {
13225 verify_encoder_state(dev);
13226 verify_connector_state(dev, NULL);
13227 verify_disabled_dpll_state(dev);
13228 }
13229
13230 static void update_scanline_offset(struct intel_crtc *crtc)
13231 {
13232 struct drm_device *dev = crtc->base.dev;
13233
13234 /*
13235 * The scanline counter increments at the leading edge of hsync.
13236 *
13237 * On most platforms it starts counting from vtotal-1 on the
13238 * first active line. That means the scanline counter value is
13239 * always one less than what we would expect. Ie. just after
13240 * start of vblank, which also occurs at start of hsync (on the
13241 * last active line), the scanline counter will read vblank_start-1.
13242 *
13243 * On gen2 the scanline counter starts counting from 1 instead
13244 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13245 * to keep the value positive), instead of adding one.
13246 *
13247 * On HSW+ the behaviour of the scanline counter depends on the output
13248 * type. For DP ports it behaves like most other platforms, but on HDMI
13249 * there's an extra 1 line difference. So we need to add two instead of
13250 * one to the value.
13251 */
13252 if (IS_GEN2(dev)) {
13253 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13254 int vtotal;
13255
13256 vtotal = adjusted_mode->crtc_vtotal;
13257 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13258 vtotal /= 2;
13259
13260 crtc->scanline_offset = vtotal - 1;
13261 } else if (HAS_DDI(dev) &&
13262 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13263 crtc->scanline_offset = 2;
13264 } else
13265 crtc->scanline_offset = 1;
13266 }
13267
13268 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13269 {
13270 struct drm_device *dev = state->dev;
13271 struct drm_i915_private *dev_priv = to_i915(dev);
13272 struct intel_shared_dpll_config *shared_dpll = NULL;
13273 struct drm_crtc *crtc;
13274 struct drm_crtc_state *crtc_state;
13275 int i;
13276
13277 if (!dev_priv->display.crtc_compute_clock)
13278 return;
13279
13280 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13282 struct intel_shared_dpll *old_dpll =
13283 to_intel_crtc_state(crtc->state)->shared_dpll;
13284
13285 if (!needs_modeset(crtc_state))
13286 continue;
13287
13288 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13289
13290 if (!old_dpll)
13291 continue;
13292
13293 if (!shared_dpll)
13294 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13295
13296 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13297 }
13298 }
13299
13300 /*
13301 * This implements the workaround described in the "notes" section of the mode
13302 * set sequence documentation. When going from no pipes or single pipe to
13303 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13304 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13305 */
13306 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13307 {
13308 struct drm_crtc_state *crtc_state;
13309 struct intel_crtc *intel_crtc;
13310 struct drm_crtc *crtc;
13311 struct intel_crtc_state *first_crtc_state = NULL;
13312 struct intel_crtc_state *other_crtc_state = NULL;
13313 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13314 int i;
13315
13316 /* look at all crtc's that are going to be enabled in during modeset */
13317 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13318 intel_crtc = to_intel_crtc(crtc);
13319
13320 if (!crtc_state->active || !needs_modeset(crtc_state))
13321 continue;
13322
13323 if (first_crtc_state) {
13324 other_crtc_state = to_intel_crtc_state(crtc_state);
13325 break;
13326 } else {
13327 first_crtc_state = to_intel_crtc_state(crtc_state);
13328 first_pipe = intel_crtc->pipe;
13329 }
13330 }
13331
13332 /* No workaround needed? */
13333 if (!first_crtc_state)
13334 return 0;
13335
13336 /* w/a possibly needed, check how many crtc's are already enabled. */
13337 for_each_intel_crtc(state->dev, intel_crtc) {
13338 struct intel_crtc_state *pipe_config;
13339
13340 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13341 if (IS_ERR(pipe_config))
13342 return PTR_ERR(pipe_config);
13343
13344 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13345
13346 if (!pipe_config->base.active ||
13347 needs_modeset(&pipe_config->base))
13348 continue;
13349
13350 /* 2 or more enabled crtcs means no need for w/a */
13351 if (enabled_pipe != INVALID_PIPE)
13352 return 0;
13353
13354 enabled_pipe = intel_crtc->pipe;
13355 }
13356
13357 if (enabled_pipe != INVALID_PIPE)
13358 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13359 else if (other_crtc_state)
13360 other_crtc_state->hsw_workaround_pipe = first_pipe;
13361
13362 return 0;
13363 }
13364
13365 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13366 {
13367 struct drm_crtc *crtc;
13368 struct drm_crtc_state *crtc_state;
13369 int ret = 0;
13370
13371 /* add all active pipes to the state */
13372 for_each_crtc(state->dev, crtc) {
13373 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13374 if (IS_ERR(crtc_state))
13375 return PTR_ERR(crtc_state);
13376
13377 if (!crtc_state->active || needs_modeset(crtc_state))
13378 continue;
13379
13380 crtc_state->mode_changed = true;
13381
13382 ret = drm_atomic_add_affected_connectors(state, crtc);
13383 if (ret)
13384 break;
13385
13386 ret = drm_atomic_add_affected_planes(state, crtc);
13387 if (ret)
13388 break;
13389 }
13390
13391 return ret;
13392 }
13393
13394 static int intel_modeset_checks(struct drm_atomic_state *state)
13395 {
13396 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13397 struct drm_i915_private *dev_priv = state->dev->dev_private;
13398 struct drm_crtc *crtc;
13399 struct drm_crtc_state *crtc_state;
13400 int ret = 0, i;
13401
13402 if (!check_digital_port_conflicts(state)) {
13403 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13404 return -EINVAL;
13405 }
13406
13407 intel_state->modeset = true;
13408 intel_state->active_crtcs = dev_priv->active_crtcs;
13409
13410 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13411 if (crtc_state->active)
13412 intel_state->active_crtcs |= 1 << i;
13413 else
13414 intel_state->active_crtcs &= ~(1 << i);
13415
13416 if (crtc_state->active != crtc->state->active)
13417 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13418 }
13419
13420 /*
13421 * See if the config requires any additional preparation, e.g.
13422 * to adjust global state with pipes off. We need to do this
13423 * here so we can get the modeset_pipe updated config for the new
13424 * mode set on this crtc. For other crtcs we need to use the
13425 * adjusted_mode bits in the crtc directly.
13426 */
13427 if (dev_priv->display.modeset_calc_cdclk) {
13428 if (!intel_state->cdclk_pll_vco)
13429 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13430 if (!intel_state->cdclk_pll_vco)
13431 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13432
13433 ret = dev_priv->display.modeset_calc_cdclk(state);
13434 if (ret < 0)
13435 return ret;
13436
13437 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13438 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13439 ret = intel_modeset_all_pipes(state);
13440
13441 if (ret < 0)
13442 return ret;
13443
13444 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13445 intel_state->cdclk, intel_state->dev_cdclk);
13446 } else
13447 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13448
13449 intel_modeset_clear_plls(state);
13450
13451 if (IS_HASWELL(dev_priv))
13452 return haswell_mode_set_planes_workaround(state);
13453
13454 return 0;
13455 }
13456
13457 /*
13458 * Handle calculation of various watermark data at the end of the atomic check
13459 * phase. The code here should be run after the per-crtc and per-plane 'check'
13460 * handlers to ensure that all derived state has been updated.
13461 */
13462 static int calc_watermark_data(struct drm_atomic_state *state)
13463 {
13464 struct drm_device *dev = state->dev;
13465 struct drm_i915_private *dev_priv = to_i915(dev);
13466
13467 /* Is there platform-specific watermark information to calculate? */
13468 if (dev_priv->display.compute_global_watermarks)
13469 return dev_priv->display.compute_global_watermarks(state);
13470
13471 return 0;
13472 }
13473
13474 /**
13475 * intel_atomic_check - validate state object
13476 * @dev: drm device
13477 * @state: state to validate
13478 */
13479 static int intel_atomic_check(struct drm_device *dev,
13480 struct drm_atomic_state *state)
13481 {
13482 struct drm_i915_private *dev_priv = to_i915(dev);
13483 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13484 struct drm_crtc *crtc;
13485 struct drm_crtc_state *crtc_state;
13486 int ret, i;
13487 bool any_ms = false;
13488
13489 ret = drm_atomic_helper_check_modeset(dev, state);
13490 if (ret)
13491 return ret;
13492
13493 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13494 struct intel_crtc_state *pipe_config =
13495 to_intel_crtc_state(crtc_state);
13496
13497 /* Catch I915_MODE_FLAG_INHERITED */
13498 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13499 crtc_state->mode_changed = true;
13500
13501 if (!needs_modeset(crtc_state))
13502 continue;
13503
13504 if (!crtc_state->enable) {
13505 any_ms = true;
13506 continue;
13507 }
13508
13509 /* FIXME: For only active_changed we shouldn't need to do any
13510 * state recomputation at all. */
13511
13512 ret = drm_atomic_add_affected_connectors(state, crtc);
13513 if (ret)
13514 return ret;
13515
13516 ret = intel_modeset_pipe_config(crtc, pipe_config);
13517 if (ret) {
13518 intel_dump_pipe_config(to_intel_crtc(crtc),
13519 pipe_config, "[failed]");
13520 return ret;
13521 }
13522
13523 if (i915.fastboot &&
13524 intel_pipe_config_compare(dev,
13525 to_intel_crtc_state(crtc->state),
13526 pipe_config, true)) {
13527 crtc_state->mode_changed = false;
13528 to_intel_crtc_state(crtc_state)->update_pipe = true;
13529 }
13530
13531 if (needs_modeset(crtc_state))
13532 any_ms = true;
13533
13534 ret = drm_atomic_add_affected_planes(state, crtc);
13535 if (ret)
13536 return ret;
13537
13538 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13539 needs_modeset(crtc_state) ?
13540 "[modeset]" : "[fastset]");
13541 }
13542
13543 if (any_ms) {
13544 ret = intel_modeset_checks(state);
13545
13546 if (ret)
13547 return ret;
13548 } else
13549 intel_state->cdclk = dev_priv->cdclk_freq;
13550
13551 ret = drm_atomic_helper_check_planes(dev, state);
13552 if (ret)
13553 return ret;
13554
13555 intel_fbc_choose_crtc(dev_priv, state);
13556 return calc_watermark_data(state);
13557 }
13558
13559 static int intel_atomic_prepare_commit(struct drm_device *dev,
13560 struct drm_atomic_state *state,
13561 bool nonblock)
13562 {
13563 struct drm_i915_private *dev_priv = dev->dev_private;
13564 struct drm_plane_state *plane_state;
13565 struct drm_crtc_state *crtc_state;
13566 struct drm_plane *plane;
13567 struct drm_crtc *crtc;
13568 int i, ret;
13569
13570 if (nonblock) {
13571 DRM_DEBUG_KMS("i915 does not yet support nonblocking commit\n");
13572 return -EINVAL;
13573 }
13574
13575 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13576 if (state->legacy_cursor_update)
13577 continue;
13578
13579 ret = intel_crtc_wait_for_pending_flips(crtc);
13580 if (ret)
13581 return ret;
13582
13583 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13584 flush_workqueue(dev_priv->wq);
13585 }
13586
13587 ret = mutex_lock_interruptible(&dev->struct_mutex);
13588 if (ret)
13589 return ret;
13590
13591 ret = drm_atomic_helper_prepare_planes(dev, state);
13592 mutex_unlock(&dev->struct_mutex);
13593
13594 if (!ret && !nonblock) {
13595 for_each_plane_in_state(state, plane, plane_state, i) {
13596 struct intel_plane_state *intel_plane_state =
13597 to_intel_plane_state(plane_state);
13598
13599 if (!intel_plane_state->wait_req)
13600 continue;
13601
13602 ret = __i915_wait_request(intel_plane_state->wait_req,
13603 true, NULL, NULL);
13604 if (ret) {
13605 /* Any hang should be swallowed by the wait */
13606 WARN_ON(ret == -EIO);
13607 mutex_lock(&dev->struct_mutex);
13608 drm_atomic_helper_cleanup_planes(dev, state);
13609 mutex_unlock(&dev->struct_mutex);
13610 break;
13611 }
13612 }
13613 }
13614
13615 return ret;
13616 }
13617
13618 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13619 {
13620 struct drm_device *dev = crtc->base.dev;
13621
13622 if (!dev->max_vblank_count)
13623 return drm_accurate_vblank_count(&crtc->base);
13624
13625 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13626 }
13627
13628 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13629 struct drm_i915_private *dev_priv,
13630 unsigned crtc_mask)
13631 {
13632 unsigned last_vblank_count[I915_MAX_PIPES];
13633 enum pipe pipe;
13634 int ret;
13635
13636 if (!crtc_mask)
13637 return;
13638
13639 for_each_pipe(dev_priv, pipe) {
13640 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13641
13642 if (!((1 << pipe) & crtc_mask))
13643 continue;
13644
13645 ret = drm_crtc_vblank_get(crtc);
13646 if (WARN_ON(ret != 0)) {
13647 crtc_mask &= ~(1 << pipe);
13648 continue;
13649 }
13650
13651 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13652 }
13653
13654 for_each_pipe(dev_priv, pipe) {
13655 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13656 long lret;
13657
13658 if (!((1 << pipe) & crtc_mask))
13659 continue;
13660
13661 lret = wait_event_timeout(dev->vblank[pipe].queue,
13662 last_vblank_count[pipe] !=
13663 drm_crtc_vblank_count(crtc),
13664 msecs_to_jiffies(50));
13665
13666 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13667
13668 drm_crtc_vblank_put(crtc);
13669 }
13670 }
13671
13672 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13673 {
13674 /* fb updated, need to unpin old fb */
13675 if (crtc_state->fb_changed)
13676 return true;
13677
13678 /* wm changes, need vblank before final wm's */
13679 if (crtc_state->update_wm_post)
13680 return true;
13681
13682 /*
13683 * cxsr is re-enabled after vblank.
13684 * This is already handled by crtc_state->update_wm_post,
13685 * but added for clarity.
13686 */
13687 if (crtc_state->disable_cxsr)
13688 return true;
13689
13690 return false;
13691 }
13692
13693 /**
13694 * intel_atomic_commit - commit validated state object
13695 * @dev: DRM device
13696 * @state: the top-level driver state object
13697 * @nonblock: nonblocking commit
13698 *
13699 * This function commits a top-level state object that has been validated
13700 * with drm_atomic_helper_check().
13701 *
13702 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13703 * we can only handle plane-related operations and do not yet support
13704 * nonblocking commit.
13705 *
13706 * RETURNS
13707 * Zero for success or -errno.
13708 */
13709 static int intel_atomic_commit(struct drm_device *dev,
13710 struct drm_atomic_state *state,
13711 bool nonblock)
13712 {
13713 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13714 struct drm_i915_private *dev_priv = dev->dev_private;
13715 struct drm_crtc_state *old_crtc_state;
13716 struct drm_crtc *crtc;
13717 struct intel_crtc_state *intel_cstate;
13718 int ret = 0, i;
13719 bool hw_check = intel_state->modeset;
13720 unsigned long put_domains[I915_MAX_PIPES] = {};
13721 unsigned crtc_vblank_mask = 0;
13722
13723 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13724 if (ret) {
13725 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13726 return ret;
13727 }
13728
13729 drm_atomic_helper_swap_state(state, true);
13730 dev_priv->wm.distrust_bios_wm = false;
13731 dev_priv->wm.skl_results = intel_state->wm_results;
13732 intel_shared_dpll_commit(state);
13733
13734 if (intel_state->modeset) {
13735 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13736 sizeof(intel_state->min_pixclk));
13737 dev_priv->active_crtcs = intel_state->active_crtcs;
13738 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13739
13740 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13741 }
13742
13743 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13745
13746 if (needs_modeset(crtc->state) ||
13747 to_intel_crtc_state(crtc->state)->update_pipe) {
13748 hw_check = true;
13749
13750 put_domains[to_intel_crtc(crtc)->pipe] =
13751 modeset_get_crtc_power_domains(crtc,
13752 to_intel_crtc_state(crtc->state));
13753 }
13754
13755 if (!needs_modeset(crtc->state))
13756 continue;
13757
13758 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13759
13760 if (old_crtc_state->active) {
13761 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13762 dev_priv->display.crtc_disable(crtc);
13763 intel_crtc->active = false;
13764 intel_fbc_disable(intel_crtc);
13765 intel_disable_shared_dpll(intel_crtc);
13766
13767 /*
13768 * Underruns don't always raise
13769 * interrupts, so check manually.
13770 */
13771 intel_check_cpu_fifo_underruns(dev_priv);
13772 intel_check_pch_fifo_underruns(dev_priv);
13773
13774 if (!crtc->state->active)
13775 intel_update_watermarks(crtc);
13776 }
13777 }
13778
13779 /* Only after disabling all output pipelines that will be changed can we
13780 * update the the output configuration. */
13781 intel_modeset_update_crtc_state(state);
13782
13783 if (intel_state->modeset) {
13784 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13785
13786 if (dev_priv->display.modeset_commit_cdclk &&
13787 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13788 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13789 dev_priv->display.modeset_commit_cdclk(state);
13790
13791 intel_modeset_verify_disabled(dev);
13792 }
13793
13794 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13795 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13797 bool modeset = needs_modeset(crtc->state);
13798 struct intel_crtc_state *pipe_config =
13799 to_intel_crtc_state(crtc->state);
13800 bool update_pipe = !modeset && pipe_config->update_pipe;
13801
13802 if (modeset && crtc->state->active) {
13803 update_scanline_offset(to_intel_crtc(crtc));
13804 dev_priv->display.crtc_enable(crtc);
13805 }
13806
13807 if (!modeset)
13808 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13809
13810 if (crtc->state->active &&
13811 drm_atomic_get_existing_plane_state(state, crtc->primary))
13812 intel_fbc_enable(intel_crtc);
13813
13814 if (crtc->state->active &&
13815 (crtc->state->planes_changed || update_pipe))
13816 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13817
13818 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13819 crtc_vblank_mask |= 1 << i;
13820 }
13821
13822 /* FIXME: add subpixel order */
13823
13824 if (!state->legacy_cursor_update)
13825 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13826
13827 /*
13828 * Now that the vblank has passed, we can go ahead and program the
13829 * optimal watermarks on platforms that need two-step watermark
13830 * programming.
13831 *
13832 * TODO: Move this (and other cleanup) to an async worker eventually.
13833 */
13834 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13835 intel_cstate = to_intel_crtc_state(crtc->state);
13836
13837 if (dev_priv->display.optimize_watermarks)
13838 dev_priv->display.optimize_watermarks(intel_cstate);
13839 }
13840
13841 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13842 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13843
13844 if (put_domains[i])
13845 modeset_put_power_domains(dev_priv, put_domains[i]);
13846
13847 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13848 }
13849
13850 if (intel_state->modeset)
13851 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13852
13853 mutex_lock(&dev->struct_mutex);
13854 drm_atomic_helper_cleanup_planes(dev, state);
13855 mutex_unlock(&dev->struct_mutex);
13856
13857 drm_atomic_state_free(state);
13858
13859 /* As one of the primary mmio accessors, KMS has a high likelihood
13860 * of triggering bugs in unclaimed access. After we finish
13861 * modesetting, see if an error has been flagged, and if so
13862 * enable debugging for the next modeset - and hope we catch
13863 * the culprit.
13864 *
13865 * XXX note that we assume display power is on at this point.
13866 * This might hold true now but we need to add pm helper to check
13867 * unclaimed only when the hardware is on, as atomic commits
13868 * can happen also when the device is completely off.
13869 */
13870 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13871
13872 return 0;
13873 }
13874
13875 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13876 {
13877 struct drm_device *dev = crtc->dev;
13878 struct drm_atomic_state *state;
13879 struct drm_crtc_state *crtc_state;
13880 int ret;
13881
13882 state = drm_atomic_state_alloc(dev);
13883 if (!state) {
13884 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13885 crtc->base.id, crtc->name);
13886 return;
13887 }
13888
13889 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13890
13891 retry:
13892 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13893 ret = PTR_ERR_OR_ZERO(crtc_state);
13894 if (!ret) {
13895 if (!crtc_state->active)
13896 goto out;
13897
13898 crtc_state->mode_changed = true;
13899 ret = drm_atomic_commit(state);
13900 }
13901
13902 if (ret == -EDEADLK) {
13903 drm_atomic_state_clear(state);
13904 drm_modeset_backoff(state->acquire_ctx);
13905 goto retry;
13906 }
13907
13908 if (ret)
13909 out:
13910 drm_atomic_state_free(state);
13911 }
13912
13913 #undef for_each_intel_crtc_masked
13914
13915 static const struct drm_crtc_funcs intel_crtc_funcs = {
13916 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13917 .set_config = drm_atomic_helper_set_config,
13918 .set_property = drm_atomic_helper_crtc_set_property,
13919 .destroy = intel_crtc_destroy,
13920 .page_flip = intel_crtc_page_flip,
13921 .atomic_duplicate_state = intel_crtc_duplicate_state,
13922 .atomic_destroy_state = intel_crtc_destroy_state,
13923 };
13924
13925 /**
13926 * intel_prepare_plane_fb - Prepare fb for usage on plane
13927 * @plane: drm plane to prepare for
13928 * @fb: framebuffer to prepare for presentation
13929 *
13930 * Prepares a framebuffer for usage on a display plane. Generally this
13931 * involves pinning the underlying object and updating the frontbuffer tracking
13932 * bits. Some older platforms need special physical address handling for
13933 * cursor planes.
13934 *
13935 * Must be called with struct_mutex held.
13936 *
13937 * Returns 0 on success, negative error code on failure.
13938 */
13939 int
13940 intel_prepare_plane_fb(struct drm_plane *plane,
13941 const struct drm_plane_state *new_state)
13942 {
13943 struct drm_device *dev = plane->dev;
13944 struct drm_framebuffer *fb = new_state->fb;
13945 struct intel_plane *intel_plane = to_intel_plane(plane);
13946 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13947 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13948 int ret = 0;
13949
13950 if (!obj && !old_obj)
13951 return 0;
13952
13953 if (old_obj) {
13954 struct drm_crtc_state *crtc_state =
13955 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13956
13957 /* Big Hammer, we also need to ensure that any pending
13958 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13959 * current scanout is retired before unpinning the old
13960 * framebuffer. Note that we rely on userspace rendering
13961 * into the buffer attached to the pipe they are waiting
13962 * on. If not, userspace generates a GPU hang with IPEHR
13963 * point to the MI_WAIT_FOR_EVENT.
13964 *
13965 * This should only fail upon a hung GPU, in which case we
13966 * can safely continue.
13967 */
13968 if (needs_modeset(crtc_state))
13969 ret = i915_gem_object_wait_rendering(old_obj, true);
13970 if (ret) {
13971 /* GPU hangs should have been swallowed by the wait */
13972 WARN_ON(ret == -EIO);
13973 return ret;
13974 }
13975 }
13976
13977 /* For framebuffer backed by dmabuf, wait for fence */
13978 if (obj && obj->base.dma_buf) {
13979 long lret;
13980
13981 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13982 false, true,
13983 MAX_SCHEDULE_TIMEOUT);
13984 if (lret == -ERESTARTSYS)
13985 return lret;
13986
13987 WARN(lret < 0, "waiting returns %li\n", lret);
13988 }
13989
13990 if (!obj) {
13991 ret = 0;
13992 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13993 INTEL_INFO(dev)->cursor_needs_physical) {
13994 int align = IS_I830(dev) ? 16 * 1024 : 256;
13995 ret = i915_gem_object_attach_phys(obj, align);
13996 if (ret)
13997 DRM_DEBUG_KMS("failed to attach phys object\n");
13998 } else {
13999 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14000 }
14001
14002 if (ret == 0) {
14003 if (obj) {
14004 struct intel_plane_state *plane_state =
14005 to_intel_plane_state(new_state);
14006
14007 i915_gem_request_assign(&plane_state->wait_req,
14008 obj->last_write_req);
14009 }
14010
14011 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
14012 }
14013
14014 return ret;
14015 }
14016
14017 /**
14018 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14019 * @plane: drm plane to clean up for
14020 * @fb: old framebuffer that was on plane
14021 *
14022 * Cleans up a framebuffer that has just been removed from a plane.
14023 *
14024 * Must be called with struct_mutex held.
14025 */
14026 void
14027 intel_cleanup_plane_fb(struct drm_plane *plane,
14028 const struct drm_plane_state *old_state)
14029 {
14030 struct drm_device *dev = plane->dev;
14031 struct intel_plane *intel_plane = to_intel_plane(plane);
14032 struct intel_plane_state *old_intel_state;
14033 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14034 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14035
14036 old_intel_state = to_intel_plane_state(old_state);
14037
14038 if (!obj && !old_obj)
14039 return;
14040
14041 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14042 !INTEL_INFO(dev)->cursor_needs_physical))
14043 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14044
14045 /* prepare_fb aborted? */
14046 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
14047 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
14048 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
14049
14050 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14051 }
14052
14053 int
14054 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14055 {
14056 int max_scale;
14057 struct drm_device *dev;
14058 struct drm_i915_private *dev_priv;
14059 int crtc_clock, cdclk;
14060
14061 if (!intel_crtc || !crtc_state->base.enable)
14062 return DRM_PLANE_HELPER_NO_SCALING;
14063
14064 dev = intel_crtc->base.dev;
14065 dev_priv = dev->dev_private;
14066 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14067 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14068
14069 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14070 return DRM_PLANE_HELPER_NO_SCALING;
14071
14072 /*
14073 * skl max scale is lower of:
14074 * close to 3 but not 3, -1 is for that purpose
14075 * or
14076 * cdclk/crtc_clock
14077 */
14078 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14079
14080 return max_scale;
14081 }
14082
14083 static int
14084 intel_check_primary_plane(struct drm_plane *plane,
14085 struct intel_crtc_state *crtc_state,
14086 struct intel_plane_state *state)
14087 {
14088 struct drm_crtc *crtc = state->base.crtc;
14089 struct drm_framebuffer *fb = state->base.fb;
14090 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14091 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14092 bool can_position = false;
14093
14094 if (INTEL_INFO(plane->dev)->gen >= 9) {
14095 /* use scaler when colorkey is not required */
14096 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14097 min_scale = 1;
14098 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14099 }
14100 can_position = true;
14101 }
14102
14103 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14104 &state->dst, &state->clip,
14105 min_scale, max_scale,
14106 can_position, true,
14107 &state->visible);
14108 }
14109
14110 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14111 struct drm_crtc_state *old_crtc_state)
14112 {
14113 struct drm_device *dev = crtc->dev;
14114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14115 struct intel_crtc_state *old_intel_state =
14116 to_intel_crtc_state(old_crtc_state);
14117 bool modeset = needs_modeset(crtc->state);
14118
14119 /* Perform vblank evasion around commit operation */
14120 intel_pipe_update_start(intel_crtc);
14121
14122 if (modeset)
14123 return;
14124
14125 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14126 intel_color_set_csc(crtc->state);
14127 intel_color_load_luts(crtc->state);
14128 }
14129
14130 if (to_intel_crtc_state(crtc->state)->update_pipe)
14131 intel_update_pipe_config(intel_crtc, old_intel_state);
14132 else if (INTEL_INFO(dev)->gen >= 9)
14133 skl_detach_scalers(intel_crtc);
14134 }
14135
14136 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14137 struct drm_crtc_state *old_crtc_state)
14138 {
14139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14140
14141 intel_pipe_update_end(intel_crtc, NULL);
14142 }
14143
14144 /**
14145 * intel_plane_destroy - destroy a plane
14146 * @plane: plane to destroy
14147 *
14148 * Common destruction function for all types of planes (primary, cursor,
14149 * sprite).
14150 */
14151 void intel_plane_destroy(struct drm_plane *plane)
14152 {
14153 if (!plane)
14154 return;
14155
14156 drm_plane_cleanup(plane);
14157 kfree(to_intel_plane(plane));
14158 }
14159
14160 const struct drm_plane_funcs intel_plane_funcs = {
14161 .update_plane = drm_atomic_helper_update_plane,
14162 .disable_plane = drm_atomic_helper_disable_plane,
14163 .destroy = intel_plane_destroy,
14164 .set_property = drm_atomic_helper_plane_set_property,
14165 .atomic_get_property = intel_plane_atomic_get_property,
14166 .atomic_set_property = intel_plane_atomic_set_property,
14167 .atomic_duplicate_state = intel_plane_duplicate_state,
14168 .atomic_destroy_state = intel_plane_destroy_state,
14169
14170 };
14171
14172 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14173 int pipe)
14174 {
14175 struct intel_plane *primary = NULL;
14176 struct intel_plane_state *state = NULL;
14177 const uint32_t *intel_primary_formats;
14178 unsigned int num_formats;
14179 int ret;
14180
14181 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14182 if (!primary)
14183 goto fail;
14184
14185 state = intel_create_plane_state(&primary->base);
14186 if (!state)
14187 goto fail;
14188 primary->base.state = &state->base;
14189
14190 primary->can_scale = false;
14191 primary->max_downscale = 1;
14192 if (INTEL_INFO(dev)->gen >= 9) {
14193 primary->can_scale = true;
14194 state->scaler_id = -1;
14195 }
14196 primary->pipe = pipe;
14197 primary->plane = pipe;
14198 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14199 primary->check_plane = intel_check_primary_plane;
14200 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14201 primary->plane = !pipe;
14202
14203 if (INTEL_INFO(dev)->gen >= 9) {
14204 intel_primary_formats = skl_primary_formats;
14205 num_formats = ARRAY_SIZE(skl_primary_formats);
14206
14207 primary->update_plane = skylake_update_primary_plane;
14208 primary->disable_plane = skylake_disable_primary_plane;
14209 } else if (HAS_PCH_SPLIT(dev)) {
14210 intel_primary_formats = i965_primary_formats;
14211 num_formats = ARRAY_SIZE(i965_primary_formats);
14212
14213 primary->update_plane = ironlake_update_primary_plane;
14214 primary->disable_plane = i9xx_disable_primary_plane;
14215 } else if (INTEL_INFO(dev)->gen >= 4) {
14216 intel_primary_formats = i965_primary_formats;
14217 num_formats = ARRAY_SIZE(i965_primary_formats);
14218
14219 primary->update_plane = i9xx_update_primary_plane;
14220 primary->disable_plane = i9xx_disable_primary_plane;
14221 } else {
14222 intel_primary_formats = i8xx_primary_formats;
14223 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14224
14225 primary->update_plane = i9xx_update_primary_plane;
14226 primary->disable_plane = i9xx_disable_primary_plane;
14227 }
14228
14229 if (INTEL_INFO(dev)->gen >= 9)
14230 ret = drm_universal_plane_init(dev, &primary->base, 0,
14231 &intel_plane_funcs,
14232 intel_primary_formats, num_formats,
14233 DRM_PLANE_TYPE_PRIMARY,
14234 "plane 1%c", pipe_name(pipe));
14235 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14236 ret = drm_universal_plane_init(dev, &primary->base, 0,
14237 &intel_plane_funcs,
14238 intel_primary_formats, num_formats,
14239 DRM_PLANE_TYPE_PRIMARY,
14240 "primary %c", pipe_name(pipe));
14241 else
14242 ret = drm_universal_plane_init(dev, &primary->base, 0,
14243 &intel_plane_funcs,
14244 intel_primary_formats, num_formats,
14245 DRM_PLANE_TYPE_PRIMARY,
14246 "plane %c", plane_name(primary->plane));
14247 if (ret)
14248 goto fail;
14249
14250 if (INTEL_INFO(dev)->gen >= 4)
14251 intel_create_rotation_property(dev, primary);
14252
14253 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14254
14255 return &primary->base;
14256
14257 fail:
14258 kfree(state);
14259 kfree(primary);
14260
14261 return NULL;
14262 }
14263
14264 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14265 {
14266 if (!dev->mode_config.rotation_property) {
14267 unsigned long flags = BIT(DRM_ROTATE_0) |
14268 BIT(DRM_ROTATE_180);
14269
14270 if (INTEL_INFO(dev)->gen >= 9)
14271 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14272
14273 dev->mode_config.rotation_property =
14274 drm_mode_create_rotation_property(dev, flags);
14275 }
14276 if (dev->mode_config.rotation_property)
14277 drm_object_attach_property(&plane->base.base,
14278 dev->mode_config.rotation_property,
14279 plane->base.state->rotation);
14280 }
14281
14282 static int
14283 intel_check_cursor_plane(struct drm_plane *plane,
14284 struct intel_crtc_state *crtc_state,
14285 struct intel_plane_state *state)
14286 {
14287 struct drm_crtc *crtc = crtc_state->base.crtc;
14288 struct drm_framebuffer *fb = state->base.fb;
14289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14290 enum pipe pipe = to_intel_plane(plane)->pipe;
14291 unsigned stride;
14292 int ret;
14293
14294 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14295 &state->dst, &state->clip,
14296 DRM_PLANE_HELPER_NO_SCALING,
14297 DRM_PLANE_HELPER_NO_SCALING,
14298 true, true, &state->visible);
14299 if (ret)
14300 return ret;
14301
14302 /* if we want to turn off the cursor ignore width and height */
14303 if (!obj)
14304 return 0;
14305
14306 /* Check for which cursor types we support */
14307 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14308 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14309 state->base.crtc_w, state->base.crtc_h);
14310 return -EINVAL;
14311 }
14312
14313 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14314 if (obj->base.size < stride * state->base.crtc_h) {
14315 DRM_DEBUG_KMS("buffer is too small\n");
14316 return -ENOMEM;
14317 }
14318
14319 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14320 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14321 return -EINVAL;
14322 }
14323
14324 /*
14325 * There's something wrong with the cursor on CHV pipe C.
14326 * If it straddles the left edge of the screen then
14327 * moving it away from the edge or disabling it often
14328 * results in a pipe underrun, and often that can lead to
14329 * dead pipe (constant underrun reported, and it scans
14330 * out just a solid color). To recover from that, the
14331 * display power well must be turned off and on again.
14332 * Refuse the put the cursor into that compromised position.
14333 */
14334 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14335 state->visible && state->base.crtc_x < 0) {
14336 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14337 return -EINVAL;
14338 }
14339
14340 return 0;
14341 }
14342
14343 static void
14344 intel_disable_cursor_plane(struct drm_plane *plane,
14345 struct drm_crtc *crtc)
14346 {
14347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14348
14349 intel_crtc->cursor_addr = 0;
14350 intel_crtc_update_cursor(crtc, NULL);
14351 }
14352
14353 static void
14354 intel_update_cursor_plane(struct drm_plane *plane,
14355 const struct intel_crtc_state *crtc_state,
14356 const struct intel_plane_state *state)
14357 {
14358 struct drm_crtc *crtc = crtc_state->base.crtc;
14359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14360 struct drm_device *dev = plane->dev;
14361 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14362 uint32_t addr;
14363
14364 if (!obj)
14365 addr = 0;
14366 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14367 addr = i915_gem_obj_ggtt_offset(obj);
14368 else
14369 addr = obj->phys_handle->busaddr;
14370
14371 intel_crtc->cursor_addr = addr;
14372 intel_crtc_update_cursor(crtc, state);
14373 }
14374
14375 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14376 int pipe)
14377 {
14378 struct intel_plane *cursor = NULL;
14379 struct intel_plane_state *state = NULL;
14380 int ret;
14381
14382 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14383 if (!cursor)
14384 goto fail;
14385
14386 state = intel_create_plane_state(&cursor->base);
14387 if (!state)
14388 goto fail;
14389 cursor->base.state = &state->base;
14390
14391 cursor->can_scale = false;
14392 cursor->max_downscale = 1;
14393 cursor->pipe = pipe;
14394 cursor->plane = pipe;
14395 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14396 cursor->check_plane = intel_check_cursor_plane;
14397 cursor->update_plane = intel_update_cursor_plane;
14398 cursor->disable_plane = intel_disable_cursor_plane;
14399
14400 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14401 &intel_plane_funcs,
14402 intel_cursor_formats,
14403 ARRAY_SIZE(intel_cursor_formats),
14404 DRM_PLANE_TYPE_CURSOR,
14405 "cursor %c", pipe_name(pipe));
14406 if (ret)
14407 goto fail;
14408
14409 if (INTEL_INFO(dev)->gen >= 4) {
14410 if (!dev->mode_config.rotation_property)
14411 dev->mode_config.rotation_property =
14412 drm_mode_create_rotation_property(dev,
14413 BIT(DRM_ROTATE_0) |
14414 BIT(DRM_ROTATE_180));
14415 if (dev->mode_config.rotation_property)
14416 drm_object_attach_property(&cursor->base.base,
14417 dev->mode_config.rotation_property,
14418 state->base.rotation);
14419 }
14420
14421 if (INTEL_INFO(dev)->gen >=9)
14422 state->scaler_id = -1;
14423
14424 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14425
14426 return &cursor->base;
14427
14428 fail:
14429 kfree(state);
14430 kfree(cursor);
14431
14432 return NULL;
14433 }
14434
14435 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14436 struct intel_crtc_state *crtc_state)
14437 {
14438 int i;
14439 struct intel_scaler *intel_scaler;
14440 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14441
14442 for (i = 0; i < intel_crtc->num_scalers; i++) {
14443 intel_scaler = &scaler_state->scalers[i];
14444 intel_scaler->in_use = 0;
14445 intel_scaler->mode = PS_SCALER_MODE_DYN;
14446 }
14447
14448 scaler_state->scaler_id = -1;
14449 }
14450
14451 static void intel_crtc_init(struct drm_device *dev, int pipe)
14452 {
14453 struct drm_i915_private *dev_priv = dev->dev_private;
14454 struct intel_crtc *intel_crtc;
14455 struct intel_crtc_state *crtc_state = NULL;
14456 struct drm_plane *primary = NULL;
14457 struct drm_plane *cursor = NULL;
14458 int ret;
14459
14460 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14461 if (intel_crtc == NULL)
14462 return;
14463
14464 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14465 if (!crtc_state)
14466 goto fail;
14467 intel_crtc->config = crtc_state;
14468 intel_crtc->base.state = &crtc_state->base;
14469 crtc_state->base.crtc = &intel_crtc->base;
14470
14471 /* initialize shared scalers */
14472 if (INTEL_INFO(dev)->gen >= 9) {
14473 if (pipe == PIPE_C)
14474 intel_crtc->num_scalers = 1;
14475 else
14476 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14477
14478 skl_init_scalers(dev, intel_crtc, crtc_state);
14479 }
14480
14481 primary = intel_primary_plane_create(dev, pipe);
14482 if (!primary)
14483 goto fail;
14484
14485 cursor = intel_cursor_plane_create(dev, pipe);
14486 if (!cursor)
14487 goto fail;
14488
14489 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14490 cursor, &intel_crtc_funcs,
14491 "pipe %c", pipe_name(pipe));
14492 if (ret)
14493 goto fail;
14494
14495 /*
14496 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14497 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14498 */
14499 intel_crtc->pipe = pipe;
14500 intel_crtc->plane = pipe;
14501 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14502 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14503 intel_crtc->plane = !pipe;
14504 }
14505
14506 intel_crtc->cursor_base = ~0;
14507 intel_crtc->cursor_cntl = ~0;
14508 intel_crtc->cursor_size = ~0;
14509
14510 intel_crtc->wm.cxsr_allowed = true;
14511
14512 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14513 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14514 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14515 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14516
14517 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14518
14519 intel_color_init(&intel_crtc->base);
14520
14521 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14522 return;
14523
14524 fail:
14525 intel_plane_destroy(primary);
14526 intel_plane_destroy(cursor);
14527 kfree(crtc_state);
14528 kfree(intel_crtc);
14529 }
14530
14531 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14532 {
14533 struct drm_encoder *encoder = connector->base.encoder;
14534 struct drm_device *dev = connector->base.dev;
14535
14536 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14537
14538 if (!encoder || WARN_ON(!encoder->crtc))
14539 return INVALID_PIPE;
14540
14541 return to_intel_crtc(encoder->crtc)->pipe;
14542 }
14543
14544 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14545 struct drm_file *file)
14546 {
14547 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14548 struct drm_crtc *drmmode_crtc;
14549 struct intel_crtc *crtc;
14550
14551 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14552
14553 if (!drmmode_crtc) {
14554 DRM_ERROR("no such CRTC id\n");
14555 return -ENOENT;
14556 }
14557
14558 crtc = to_intel_crtc(drmmode_crtc);
14559 pipe_from_crtc_id->pipe = crtc->pipe;
14560
14561 return 0;
14562 }
14563
14564 static int intel_encoder_clones(struct intel_encoder *encoder)
14565 {
14566 struct drm_device *dev = encoder->base.dev;
14567 struct intel_encoder *source_encoder;
14568 int index_mask = 0;
14569 int entry = 0;
14570
14571 for_each_intel_encoder(dev, source_encoder) {
14572 if (encoders_cloneable(encoder, source_encoder))
14573 index_mask |= (1 << entry);
14574
14575 entry++;
14576 }
14577
14578 return index_mask;
14579 }
14580
14581 static bool has_edp_a(struct drm_device *dev)
14582 {
14583 struct drm_i915_private *dev_priv = dev->dev_private;
14584
14585 if (!IS_MOBILE(dev))
14586 return false;
14587
14588 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14589 return false;
14590
14591 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14592 return false;
14593
14594 return true;
14595 }
14596
14597 static bool intel_crt_present(struct drm_device *dev)
14598 {
14599 struct drm_i915_private *dev_priv = dev->dev_private;
14600
14601 if (INTEL_INFO(dev)->gen >= 9)
14602 return false;
14603
14604 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14605 return false;
14606
14607 if (IS_CHERRYVIEW(dev))
14608 return false;
14609
14610 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14611 return false;
14612
14613 /* DDI E can't be used if DDI A requires 4 lanes */
14614 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14615 return false;
14616
14617 if (!dev_priv->vbt.int_crt_support)
14618 return false;
14619
14620 return true;
14621 }
14622
14623 static void intel_setup_outputs(struct drm_device *dev)
14624 {
14625 struct drm_i915_private *dev_priv = dev->dev_private;
14626 struct intel_encoder *encoder;
14627 bool dpd_is_edp = false;
14628
14629 intel_lvds_init(dev);
14630
14631 if (intel_crt_present(dev))
14632 intel_crt_init(dev);
14633
14634 if (IS_BROXTON(dev)) {
14635 /*
14636 * FIXME: Broxton doesn't support port detection via the
14637 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14638 * detect the ports.
14639 */
14640 intel_ddi_init(dev, PORT_A);
14641 intel_ddi_init(dev, PORT_B);
14642 intel_ddi_init(dev, PORT_C);
14643
14644 intel_dsi_init(dev);
14645 } else if (HAS_DDI(dev)) {
14646 int found;
14647
14648 /*
14649 * Haswell uses DDI functions to detect digital outputs.
14650 * On SKL pre-D0 the strap isn't connected, so we assume
14651 * it's there.
14652 */
14653 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14654 /* WaIgnoreDDIAStrap: skl */
14655 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14656 intel_ddi_init(dev, PORT_A);
14657
14658 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14659 * register */
14660 found = I915_READ(SFUSE_STRAP);
14661
14662 if (found & SFUSE_STRAP_DDIB_DETECTED)
14663 intel_ddi_init(dev, PORT_B);
14664 if (found & SFUSE_STRAP_DDIC_DETECTED)
14665 intel_ddi_init(dev, PORT_C);
14666 if (found & SFUSE_STRAP_DDID_DETECTED)
14667 intel_ddi_init(dev, PORT_D);
14668 /*
14669 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14670 */
14671 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14672 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14673 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14674 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14675 intel_ddi_init(dev, PORT_E);
14676
14677 } else if (HAS_PCH_SPLIT(dev)) {
14678 int found;
14679 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14680
14681 if (has_edp_a(dev))
14682 intel_dp_init(dev, DP_A, PORT_A);
14683
14684 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14685 /* PCH SDVOB multiplex with HDMIB */
14686 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14687 if (!found)
14688 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14689 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14690 intel_dp_init(dev, PCH_DP_B, PORT_B);
14691 }
14692
14693 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14694 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14695
14696 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14697 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14698
14699 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14700 intel_dp_init(dev, PCH_DP_C, PORT_C);
14701
14702 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14703 intel_dp_init(dev, PCH_DP_D, PORT_D);
14704 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14705 bool has_edp;
14706
14707 /*
14708 * The DP_DETECTED bit is the latched state of the DDC
14709 * SDA pin at boot. However since eDP doesn't require DDC
14710 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14711 * eDP ports may have been muxed to an alternate function.
14712 * Thus we can't rely on the DP_DETECTED bit alone to detect
14713 * eDP ports. Consult the VBT as well as DP_DETECTED to
14714 * detect eDP ports.
14715 */
14716 has_edp = intel_dp_is_edp(dev, PORT_B);
14717 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_edp)
14718 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14719 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && !has_edp)
14720 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14721
14722 has_edp = intel_dp_is_edp(dev, PORT_C);
14723 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_edp)
14724 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14725 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && !has_edp)
14726 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14727
14728 if (IS_CHERRYVIEW(dev)) {
14729 /* eDP not supported on port D, so don't check VBT */
14730 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14731 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14732 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14733 intel_dp_init(dev, CHV_DP_D, PORT_D);
14734 }
14735
14736 intel_dsi_init(dev);
14737 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14738 bool found = false;
14739
14740 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14741 DRM_DEBUG_KMS("probing SDVOB\n");
14742 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14743 if (!found && IS_G4X(dev)) {
14744 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14745 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14746 }
14747
14748 if (!found && IS_G4X(dev))
14749 intel_dp_init(dev, DP_B, PORT_B);
14750 }
14751
14752 /* Before G4X SDVOC doesn't have its own detect register */
14753
14754 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14755 DRM_DEBUG_KMS("probing SDVOC\n");
14756 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14757 }
14758
14759 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14760
14761 if (IS_G4X(dev)) {
14762 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14763 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14764 }
14765 if (IS_G4X(dev))
14766 intel_dp_init(dev, DP_C, PORT_C);
14767 }
14768
14769 if (IS_G4X(dev) &&
14770 (I915_READ(DP_D) & DP_DETECTED))
14771 intel_dp_init(dev, DP_D, PORT_D);
14772 } else if (IS_GEN2(dev))
14773 intel_dvo_init(dev);
14774
14775 if (SUPPORTS_TV(dev))
14776 intel_tv_init(dev);
14777
14778 intel_psr_init(dev);
14779
14780 for_each_intel_encoder(dev, encoder) {
14781 encoder->base.possible_crtcs = encoder->crtc_mask;
14782 encoder->base.possible_clones =
14783 intel_encoder_clones(encoder);
14784 }
14785
14786 intel_init_pch_refclk(dev);
14787
14788 drm_helper_move_panel_connectors_to_head(dev);
14789 }
14790
14791 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14792 {
14793 struct drm_device *dev = fb->dev;
14794 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14795
14796 drm_framebuffer_cleanup(fb);
14797 mutex_lock(&dev->struct_mutex);
14798 WARN_ON(!intel_fb->obj->framebuffer_references--);
14799 drm_gem_object_unreference(&intel_fb->obj->base);
14800 mutex_unlock(&dev->struct_mutex);
14801 kfree(intel_fb);
14802 }
14803
14804 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14805 struct drm_file *file,
14806 unsigned int *handle)
14807 {
14808 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14809 struct drm_i915_gem_object *obj = intel_fb->obj;
14810
14811 if (obj->userptr.mm) {
14812 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14813 return -EINVAL;
14814 }
14815
14816 return drm_gem_handle_create(file, &obj->base, handle);
14817 }
14818
14819 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14820 struct drm_file *file,
14821 unsigned flags, unsigned color,
14822 struct drm_clip_rect *clips,
14823 unsigned num_clips)
14824 {
14825 struct drm_device *dev = fb->dev;
14826 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14827 struct drm_i915_gem_object *obj = intel_fb->obj;
14828
14829 mutex_lock(&dev->struct_mutex);
14830 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14831 mutex_unlock(&dev->struct_mutex);
14832
14833 return 0;
14834 }
14835
14836 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14837 .destroy = intel_user_framebuffer_destroy,
14838 .create_handle = intel_user_framebuffer_create_handle,
14839 .dirty = intel_user_framebuffer_dirty,
14840 };
14841
14842 static
14843 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14844 uint32_t pixel_format)
14845 {
14846 u32 gen = INTEL_INFO(dev)->gen;
14847
14848 if (gen >= 9) {
14849 int cpp = drm_format_plane_cpp(pixel_format, 0);
14850
14851 /* "The stride in bytes must not exceed the of the size of 8K
14852 * pixels and 32K bytes."
14853 */
14854 return min(8192 * cpp, 32768);
14855 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14856 return 32*1024;
14857 } else if (gen >= 4) {
14858 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14859 return 16*1024;
14860 else
14861 return 32*1024;
14862 } else if (gen >= 3) {
14863 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14864 return 8*1024;
14865 else
14866 return 16*1024;
14867 } else {
14868 /* XXX DSPC is limited to 4k tiled */
14869 return 8*1024;
14870 }
14871 }
14872
14873 static int intel_framebuffer_init(struct drm_device *dev,
14874 struct intel_framebuffer *intel_fb,
14875 struct drm_mode_fb_cmd2 *mode_cmd,
14876 struct drm_i915_gem_object *obj)
14877 {
14878 struct drm_i915_private *dev_priv = to_i915(dev);
14879 unsigned int aligned_height;
14880 int ret;
14881 u32 pitch_limit, stride_alignment;
14882
14883 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14884
14885 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14886 /* Enforce that fb modifier and tiling mode match, but only for
14887 * X-tiled. This is needed for FBC. */
14888 if (!!(obj->tiling_mode == I915_TILING_X) !=
14889 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14890 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14891 return -EINVAL;
14892 }
14893 } else {
14894 if (obj->tiling_mode == I915_TILING_X)
14895 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14896 else if (obj->tiling_mode == I915_TILING_Y) {
14897 DRM_DEBUG("No Y tiling for legacy addfb\n");
14898 return -EINVAL;
14899 }
14900 }
14901
14902 /* Passed in modifier sanity checking. */
14903 switch (mode_cmd->modifier[0]) {
14904 case I915_FORMAT_MOD_Y_TILED:
14905 case I915_FORMAT_MOD_Yf_TILED:
14906 if (INTEL_INFO(dev)->gen < 9) {
14907 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14908 mode_cmd->modifier[0]);
14909 return -EINVAL;
14910 }
14911 case DRM_FORMAT_MOD_NONE:
14912 case I915_FORMAT_MOD_X_TILED:
14913 break;
14914 default:
14915 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14916 mode_cmd->modifier[0]);
14917 return -EINVAL;
14918 }
14919
14920 stride_alignment = intel_fb_stride_alignment(dev_priv,
14921 mode_cmd->modifier[0],
14922 mode_cmd->pixel_format);
14923 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14924 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14925 mode_cmd->pitches[0], stride_alignment);
14926 return -EINVAL;
14927 }
14928
14929 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14930 mode_cmd->pixel_format);
14931 if (mode_cmd->pitches[0] > pitch_limit) {
14932 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14933 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14934 "tiled" : "linear",
14935 mode_cmd->pitches[0], pitch_limit);
14936 return -EINVAL;
14937 }
14938
14939 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14940 mode_cmd->pitches[0] != obj->stride) {
14941 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14942 mode_cmd->pitches[0], obj->stride);
14943 return -EINVAL;
14944 }
14945
14946 /* Reject formats not supported by any plane early. */
14947 switch (mode_cmd->pixel_format) {
14948 case DRM_FORMAT_C8:
14949 case DRM_FORMAT_RGB565:
14950 case DRM_FORMAT_XRGB8888:
14951 case DRM_FORMAT_ARGB8888:
14952 break;
14953 case DRM_FORMAT_XRGB1555:
14954 if (INTEL_INFO(dev)->gen > 3) {
14955 DRM_DEBUG("unsupported pixel format: %s\n",
14956 drm_get_format_name(mode_cmd->pixel_format));
14957 return -EINVAL;
14958 }
14959 break;
14960 case DRM_FORMAT_ABGR8888:
14961 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14962 INTEL_INFO(dev)->gen < 9) {
14963 DRM_DEBUG("unsupported pixel format: %s\n",
14964 drm_get_format_name(mode_cmd->pixel_format));
14965 return -EINVAL;
14966 }
14967 break;
14968 case DRM_FORMAT_XBGR8888:
14969 case DRM_FORMAT_XRGB2101010:
14970 case DRM_FORMAT_XBGR2101010:
14971 if (INTEL_INFO(dev)->gen < 4) {
14972 DRM_DEBUG("unsupported pixel format: %s\n",
14973 drm_get_format_name(mode_cmd->pixel_format));
14974 return -EINVAL;
14975 }
14976 break;
14977 case DRM_FORMAT_ABGR2101010:
14978 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14979 DRM_DEBUG("unsupported pixel format: %s\n",
14980 drm_get_format_name(mode_cmd->pixel_format));
14981 return -EINVAL;
14982 }
14983 break;
14984 case DRM_FORMAT_YUYV:
14985 case DRM_FORMAT_UYVY:
14986 case DRM_FORMAT_YVYU:
14987 case DRM_FORMAT_VYUY:
14988 if (INTEL_INFO(dev)->gen < 5) {
14989 DRM_DEBUG("unsupported pixel format: %s\n",
14990 drm_get_format_name(mode_cmd->pixel_format));
14991 return -EINVAL;
14992 }
14993 break;
14994 default:
14995 DRM_DEBUG("unsupported pixel format: %s\n",
14996 drm_get_format_name(mode_cmd->pixel_format));
14997 return -EINVAL;
14998 }
14999
15000 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15001 if (mode_cmd->offsets[0] != 0)
15002 return -EINVAL;
15003
15004 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
15005 mode_cmd->pixel_format,
15006 mode_cmd->modifier[0]);
15007 /* FIXME drm helper for size checks (especially planar formats)? */
15008 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
15009 return -EINVAL;
15010
15011 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15012 intel_fb->obj = obj;
15013
15014 intel_fill_fb_info(dev_priv, &intel_fb->base);
15015
15016 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15017 if (ret) {
15018 DRM_ERROR("framebuffer init failed %d\n", ret);
15019 return ret;
15020 }
15021
15022 intel_fb->obj->framebuffer_references++;
15023
15024 return 0;
15025 }
15026
15027 static struct drm_framebuffer *
15028 intel_user_framebuffer_create(struct drm_device *dev,
15029 struct drm_file *filp,
15030 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15031 {
15032 struct drm_framebuffer *fb;
15033 struct drm_i915_gem_object *obj;
15034 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15035
15036 obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0]));
15037 if (&obj->base == NULL)
15038 return ERR_PTR(-ENOENT);
15039
15040 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15041 if (IS_ERR(fb))
15042 drm_gem_object_unreference_unlocked(&obj->base);
15043
15044 return fb;
15045 }
15046
15047 #ifndef CONFIG_DRM_FBDEV_EMULATION
15048 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15049 {
15050 }
15051 #endif
15052
15053 static const struct drm_mode_config_funcs intel_mode_funcs = {
15054 .fb_create = intel_user_framebuffer_create,
15055 .output_poll_changed = intel_fbdev_output_poll_changed,
15056 .atomic_check = intel_atomic_check,
15057 .atomic_commit = intel_atomic_commit,
15058 .atomic_state_alloc = intel_atomic_state_alloc,
15059 .atomic_state_clear = intel_atomic_state_clear,
15060 };
15061
15062 /**
15063 * intel_init_display_hooks - initialize the display modesetting hooks
15064 * @dev_priv: device private
15065 */
15066 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15067 {
15068 if (INTEL_INFO(dev_priv)->gen >= 9) {
15069 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15070 dev_priv->display.get_initial_plane_config =
15071 skylake_get_initial_plane_config;
15072 dev_priv->display.crtc_compute_clock =
15073 haswell_crtc_compute_clock;
15074 dev_priv->display.crtc_enable = haswell_crtc_enable;
15075 dev_priv->display.crtc_disable = haswell_crtc_disable;
15076 } else if (HAS_DDI(dev_priv)) {
15077 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15078 dev_priv->display.get_initial_plane_config =
15079 ironlake_get_initial_plane_config;
15080 dev_priv->display.crtc_compute_clock =
15081 haswell_crtc_compute_clock;
15082 dev_priv->display.crtc_enable = haswell_crtc_enable;
15083 dev_priv->display.crtc_disable = haswell_crtc_disable;
15084 } else if (HAS_PCH_SPLIT(dev_priv)) {
15085 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15086 dev_priv->display.get_initial_plane_config =
15087 ironlake_get_initial_plane_config;
15088 dev_priv->display.crtc_compute_clock =
15089 ironlake_crtc_compute_clock;
15090 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15091 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15092 } else if (IS_CHERRYVIEW(dev_priv)) {
15093 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15094 dev_priv->display.get_initial_plane_config =
15095 i9xx_get_initial_plane_config;
15096 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15097 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15098 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15099 } else if (IS_VALLEYVIEW(dev_priv)) {
15100 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15101 dev_priv->display.get_initial_plane_config =
15102 i9xx_get_initial_plane_config;
15103 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15104 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15105 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15106 } else if (IS_G4X(dev_priv)) {
15107 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15108 dev_priv->display.get_initial_plane_config =
15109 i9xx_get_initial_plane_config;
15110 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15111 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15112 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15113 } else if (IS_PINEVIEW(dev_priv)) {
15114 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15115 dev_priv->display.get_initial_plane_config =
15116 i9xx_get_initial_plane_config;
15117 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15118 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15119 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15120 } else if (!IS_GEN2(dev_priv)) {
15121 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15122 dev_priv->display.get_initial_plane_config =
15123 i9xx_get_initial_plane_config;
15124 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15125 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15126 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15127 } else {
15128 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15129 dev_priv->display.get_initial_plane_config =
15130 i9xx_get_initial_plane_config;
15131 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15132 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15133 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15134 }
15135
15136 /* Returns the core display clock speed */
15137 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15138 dev_priv->display.get_display_clock_speed =
15139 skylake_get_display_clock_speed;
15140 else if (IS_BROXTON(dev_priv))
15141 dev_priv->display.get_display_clock_speed =
15142 broxton_get_display_clock_speed;
15143 else if (IS_BROADWELL(dev_priv))
15144 dev_priv->display.get_display_clock_speed =
15145 broadwell_get_display_clock_speed;
15146 else if (IS_HASWELL(dev_priv))
15147 dev_priv->display.get_display_clock_speed =
15148 haswell_get_display_clock_speed;
15149 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15150 dev_priv->display.get_display_clock_speed =
15151 valleyview_get_display_clock_speed;
15152 else if (IS_GEN5(dev_priv))
15153 dev_priv->display.get_display_clock_speed =
15154 ilk_get_display_clock_speed;
15155 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15156 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15157 dev_priv->display.get_display_clock_speed =
15158 i945_get_display_clock_speed;
15159 else if (IS_GM45(dev_priv))
15160 dev_priv->display.get_display_clock_speed =
15161 gm45_get_display_clock_speed;
15162 else if (IS_CRESTLINE(dev_priv))
15163 dev_priv->display.get_display_clock_speed =
15164 i965gm_get_display_clock_speed;
15165 else if (IS_PINEVIEW(dev_priv))
15166 dev_priv->display.get_display_clock_speed =
15167 pnv_get_display_clock_speed;
15168 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15169 dev_priv->display.get_display_clock_speed =
15170 g33_get_display_clock_speed;
15171 else if (IS_I915G(dev_priv))
15172 dev_priv->display.get_display_clock_speed =
15173 i915_get_display_clock_speed;
15174 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15175 dev_priv->display.get_display_clock_speed =
15176 i9xx_misc_get_display_clock_speed;
15177 else if (IS_I915GM(dev_priv))
15178 dev_priv->display.get_display_clock_speed =
15179 i915gm_get_display_clock_speed;
15180 else if (IS_I865G(dev_priv))
15181 dev_priv->display.get_display_clock_speed =
15182 i865_get_display_clock_speed;
15183 else if (IS_I85X(dev_priv))
15184 dev_priv->display.get_display_clock_speed =
15185 i85x_get_display_clock_speed;
15186 else { /* 830 */
15187 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15188 dev_priv->display.get_display_clock_speed =
15189 i830_get_display_clock_speed;
15190 }
15191
15192 if (IS_GEN5(dev_priv)) {
15193 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15194 } else if (IS_GEN6(dev_priv)) {
15195 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15196 } else if (IS_IVYBRIDGE(dev_priv)) {
15197 /* FIXME: detect B0+ stepping and use auto training */
15198 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15199 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15200 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15201 }
15202
15203 if (IS_BROADWELL(dev_priv)) {
15204 dev_priv->display.modeset_commit_cdclk =
15205 broadwell_modeset_commit_cdclk;
15206 dev_priv->display.modeset_calc_cdclk =
15207 broadwell_modeset_calc_cdclk;
15208 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15209 dev_priv->display.modeset_commit_cdclk =
15210 valleyview_modeset_commit_cdclk;
15211 dev_priv->display.modeset_calc_cdclk =
15212 valleyview_modeset_calc_cdclk;
15213 } else if (IS_BROXTON(dev_priv)) {
15214 dev_priv->display.modeset_commit_cdclk =
15215 broxton_modeset_commit_cdclk;
15216 dev_priv->display.modeset_calc_cdclk =
15217 broxton_modeset_calc_cdclk;
15218 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15219 dev_priv->display.modeset_commit_cdclk =
15220 skl_modeset_commit_cdclk;
15221 dev_priv->display.modeset_calc_cdclk =
15222 skl_modeset_calc_cdclk;
15223 }
15224
15225 switch (INTEL_INFO(dev_priv)->gen) {
15226 case 2:
15227 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15228 break;
15229
15230 case 3:
15231 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15232 break;
15233
15234 case 4:
15235 case 5:
15236 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15237 break;
15238
15239 case 6:
15240 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15241 break;
15242 case 7:
15243 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15244 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15245 break;
15246 case 9:
15247 /* Drop through - unsupported since execlist only. */
15248 default:
15249 /* Default just returns -ENODEV to indicate unsupported */
15250 dev_priv->display.queue_flip = intel_default_queue_flip;
15251 }
15252 }
15253
15254 /*
15255 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15256 * resume, or other times. This quirk makes sure that's the case for
15257 * affected systems.
15258 */
15259 static void quirk_pipea_force(struct drm_device *dev)
15260 {
15261 struct drm_i915_private *dev_priv = dev->dev_private;
15262
15263 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15264 DRM_INFO("applying pipe a force quirk\n");
15265 }
15266
15267 static void quirk_pipeb_force(struct drm_device *dev)
15268 {
15269 struct drm_i915_private *dev_priv = dev->dev_private;
15270
15271 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15272 DRM_INFO("applying pipe b force quirk\n");
15273 }
15274
15275 /*
15276 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15277 */
15278 static void quirk_ssc_force_disable(struct drm_device *dev)
15279 {
15280 struct drm_i915_private *dev_priv = dev->dev_private;
15281 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15282 DRM_INFO("applying lvds SSC disable quirk\n");
15283 }
15284
15285 /*
15286 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15287 * brightness value
15288 */
15289 static void quirk_invert_brightness(struct drm_device *dev)
15290 {
15291 struct drm_i915_private *dev_priv = dev->dev_private;
15292 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15293 DRM_INFO("applying inverted panel brightness quirk\n");
15294 }
15295
15296 /* Some VBT's incorrectly indicate no backlight is present */
15297 static void quirk_backlight_present(struct drm_device *dev)
15298 {
15299 struct drm_i915_private *dev_priv = dev->dev_private;
15300 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15301 DRM_INFO("applying backlight present quirk\n");
15302 }
15303
15304 struct intel_quirk {
15305 int device;
15306 int subsystem_vendor;
15307 int subsystem_device;
15308 void (*hook)(struct drm_device *dev);
15309 };
15310
15311 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15312 struct intel_dmi_quirk {
15313 void (*hook)(struct drm_device *dev);
15314 const struct dmi_system_id (*dmi_id_list)[];
15315 };
15316
15317 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15318 {
15319 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15320 return 1;
15321 }
15322
15323 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15324 {
15325 .dmi_id_list = &(const struct dmi_system_id[]) {
15326 {
15327 .callback = intel_dmi_reverse_brightness,
15328 .ident = "NCR Corporation",
15329 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15330 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15331 },
15332 },
15333 { } /* terminating entry */
15334 },
15335 .hook = quirk_invert_brightness,
15336 },
15337 };
15338
15339 static struct intel_quirk intel_quirks[] = {
15340 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15341 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15342
15343 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15344 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15345
15346 /* 830 needs to leave pipe A & dpll A up */
15347 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15348
15349 /* 830 needs to leave pipe B & dpll B up */
15350 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15351
15352 /* Lenovo U160 cannot use SSC on LVDS */
15353 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15354
15355 /* Sony Vaio Y cannot use SSC on LVDS */
15356 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15357
15358 /* Acer Aspire 5734Z must invert backlight brightness */
15359 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15360
15361 /* Acer/eMachines G725 */
15362 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15363
15364 /* Acer/eMachines e725 */
15365 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15366
15367 /* Acer/Packard Bell NCL20 */
15368 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15369
15370 /* Acer Aspire 4736Z */
15371 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15372
15373 /* Acer Aspire 5336 */
15374 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15375
15376 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15377 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15378
15379 /* Acer C720 Chromebook (Core i3 4005U) */
15380 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15381
15382 /* Apple Macbook 2,1 (Core 2 T7400) */
15383 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15384
15385 /* Apple Macbook 4,1 */
15386 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15387
15388 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15389 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15390
15391 /* HP Chromebook 14 (Celeron 2955U) */
15392 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15393
15394 /* Dell Chromebook 11 */
15395 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15396
15397 /* Dell Chromebook 11 (2015 version) */
15398 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15399 };
15400
15401 static void intel_init_quirks(struct drm_device *dev)
15402 {
15403 struct pci_dev *d = dev->pdev;
15404 int i;
15405
15406 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15407 struct intel_quirk *q = &intel_quirks[i];
15408
15409 if (d->device == q->device &&
15410 (d->subsystem_vendor == q->subsystem_vendor ||
15411 q->subsystem_vendor == PCI_ANY_ID) &&
15412 (d->subsystem_device == q->subsystem_device ||
15413 q->subsystem_device == PCI_ANY_ID))
15414 q->hook(dev);
15415 }
15416 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15417 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15418 intel_dmi_quirks[i].hook(dev);
15419 }
15420 }
15421
15422 /* Disable the VGA plane that we never use */
15423 static void i915_disable_vga(struct drm_device *dev)
15424 {
15425 struct drm_i915_private *dev_priv = dev->dev_private;
15426 u8 sr1;
15427 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15428
15429 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15430 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15431 outb(SR01, VGA_SR_INDEX);
15432 sr1 = inb(VGA_SR_DATA);
15433 outb(sr1 | 1<<5, VGA_SR_DATA);
15434 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15435 udelay(300);
15436
15437 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15438 POSTING_READ(vga_reg);
15439 }
15440
15441 void intel_modeset_init_hw(struct drm_device *dev)
15442 {
15443 struct drm_i915_private *dev_priv = dev->dev_private;
15444
15445 intel_update_cdclk(dev);
15446
15447 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15448
15449 intel_init_clock_gating(dev);
15450 intel_enable_gt_powersave(dev_priv);
15451 }
15452
15453 /*
15454 * Calculate what we think the watermarks should be for the state we've read
15455 * out of the hardware and then immediately program those watermarks so that
15456 * we ensure the hardware settings match our internal state.
15457 *
15458 * We can calculate what we think WM's should be by creating a duplicate of the
15459 * current state (which was constructed during hardware readout) and running it
15460 * through the atomic check code to calculate new watermark values in the
15461 * state object.
15462 */
15463 static void sanitize_watermarks(struct drm_device *dev)
15464 {
15465 struct drm_i915_private *dev_priv = to_i915(dev);
15466 struct drm_atomic_state *state;
15467 struct drm_crtc *crtc;
15468 struct drm_crtc_state *cstate;
15469 struct drm_modeset_acquire_ctx ctx;
15470 int ret;
15471 int i;
15472
15473 /* Only supported on platforms that use atomic watermark design */
15474 if (!dev_priv->display.optimize_watermarks)
15475 return;
15476
15477 /*
15478 * We need to hold connection_mutex before calling duplicate_state so
15479 * that the connector loop is protected.
15480 */
15481 drm_modeset_acquire_init(&ctx, 0);
15482 retry:
15483 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15484 if (ret == -EDEADLK) {
15485 drm_modeset_backoff(&ctx);
15486 goto retry;
15487 } else if (WARN_ON(ret)) {
15488 goto fail;
15489 }
15490
15491 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15492 if (WARN_ON(IS_ERR(state)))
15493 goto fail;
15494
15495 /*
15496 * Hardware readout is the only time we don't want to calculate
15497 * intermediate watermarks (since we don't trust the current
15498 * watermarks).
15499 */
15500 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15501
15502 ret = intel_atomic_check(dev, state);
15503 if (ret) {
15504 /*
15505 * If we fail here, it means that the hardware appears to be
15506 * programmed in a way that shouldn't be possible, given our
15507 * understanding of watermark requirements. This might mean a
15508 * mistake in the hardware readout code or a mistake in the
15509 * watermark calculations for a given platform. Raise a WARN
15510 * so that this is noticeable.
15511 *
15512 * If this actually happens, we'll have to just leave the
15513 * BIOS-programmed watermarks untouched and hope for the best.
15514 */
15515 WARN(true, "Could not determine valid watermarks for inherited state\n");
15516 goto fail;
15517 }
15518
15519 /* Write calculated watermark values back */
15520 for_each_crtc_in_state(state, crtc, cstate, i) {
15521 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15522
15523 cs->wm.need_postvbl_update = true;
15524 dev_priv->display.optimize_watermarks(cs);
15525 }
15526
15527 drm_atomic_state_free(state);
15528 fail:
15529 drm_modeset_drop_locks(&ctx);
15530 drm_modeset_acquire_fini(&ctx);
15531 }
15532
15533 void intel_modeset_init(struct drm_device *dev)
15534 {
15535 struct drm_i915_private *dev_priv = to_i915(dev);
15536 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15537 int sprite, ret;
15538 enum pipe pipe;
15539 struct intel_crtc *crtc;
15540
15541 drm_mode_config_init(dev);
15542
15543 dev->mode_config.min_width = 0;
15544 dev->mode_config.min_height = 0;
15545
15546 dev->mode_config.preferred_depth = 24;
15547 dev->mode_config.prefer_shadow = 1;
15548
15549 dev->mode_config.allow_fb_modifiers = true;
15550
15551 dev->mode_config.funcs = &intel_mode_funcs;
15552
15553 intel_init_quirks(dev);
15554
15555 intel_init_pm(dev);
15556
15557 if (INTEL_INFO(dev)->num_pipes == 0)
15558 return;
15559
15560 /*
15561 * There may be no VBT; and if the BIOS enabled SSC we can
15562 * just keep using it to avoid unnecessary flicker. Whereas if the
15563 * BIOS isn't using it, don't assume it will work even if the VBT
15564 * indicates as much.
15565 */
15566 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15567 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15568 DREF_SSC1_ENABLE);
15569
15570 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15571 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15572 bios_lvds_use_ssc ? "en" : "dis",
15573 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15574 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15575 }
15576 }
15577
15578 if (IS_GEN2(dev)) {
15579 dev->mode_config.max_width = 2048;
15580 dev->mode_config.max_height = 2048;
15581 } else if (IS_GEN3(dev)) {
15582 dev->mode_config.max_width = 4096;
15583 dev->mode_config.max_height = 4096;
15584 } else {
15585 dev->mode_config.max_width = 8192;
15586 dev->mode_config.max_height = 8192;
15587 }
15588
15589 if (IS_845G(dev) || IS_I865G(dev)) {
15590 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15591 dev->mode_config.cursor_height = 1023;
15592 } else if (IS_GEN2(dev)) {
15593 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15594 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15595 } else {
15596 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15597 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15598 }
15599
15600 dev->mode_config.fb_base = ggtt->mappable_base;
15601
15602 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15603 INTEL_INFO(dev)->num_pipes,
15604 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15605
15606 for_each_pipe(dev_priv, pipe) {
15607 intel_crtc_init(dev, pipe);
15608 for_each_sprite(dev_priv, pipe, sprite) {
15609 ret = intel_plane_init(dev, pipe, sprite);
15610 if (ret)
15611 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15612 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15613 }
15614 }
15615
15616 intel_update_czclk(dev_priv);
15617 intel_update_cdclk(dev);
15618
15619 intel_shared_dpll_init(dev);
15620
15621 if (dev_priv->max_cdclk_freq == 0)
15622 intel_update_max_cdclk(dev);
15623
15624 /* Just disable it once at startup */
15625 i915_disable_vga(dev);
15626 intel_setup_outputs(dev);
15627
15628 drm_modeset_lock_all(dev);
15629 intel_modeset_setup_hw_state(dev);
15630 drm_modeset_unlock_all(dev);
15631
15632 for_each_intel_crtc(dev, crtc) {
15633 struct intel_initial_plane_config plane_config = {};
15634
15635 if (!crtc->active)
15636 continue;
15637
15638 /*
15639 * Note that reserving the BIOS fb up front prevents us
15640 * from stuffing other stolen allocations like the ring
15641 * on top. This prevents some ugliness at boot time, and
15642 * can even allow for smooth boot transitions if the BIOS
15643 * fb is large enough for the active pipe configuration.
15644 */
15645 dev_priv->display.get_initial_plane_config(crtc,
15646 &plane_config);
15647
15648 /*
15649 * If the fb is shared between multiple heads, we'll
15650 * just get the first one.
15651 */
15652 intel_find_initial_plane_obj(crtc, &plane_config);
15653 }
15654
15655 /*
15656 * Make sure hardware watermarks really match the state we read out.
15657 * Note that we need to do this after reconstructing the BIOS fb's
15658 * since the watermark calculation done here will use pstate->fb.
15659 */
15660 sanitize_watermarks(dev);
15661 }
15662
15663 static void intel_enable_pipe_a(struct drm_device *dev)
15664 {
15665 struct intel_connector *connector;
15666 struct drm_connector *crt = NULL;
15667 struct intel_load_detect_pipe load_detect_temp;
15668 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15669
15670 /* We can't just switch on the pipe A, we need to set things up with a
15671 * proper mode and output configuration. As a gross hack, enable pipe A
15672 * by enabling the load detect pipe once. */
15673 for_each_intel_connector(dev, connector) {
15674 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15675 crt = &connector->base;
15676 break;
15677 }
15678 }
15679
15680 if (!crt)
15681 return;
15682
15683 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15684 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15685 }
15686
15687 static bool
15688 intel_check_plane_mapping(struct intel_crtc *crtc)
15689 {
15690 struct drm_device *dev = crtc->base.dev;
15691 struct drm_i915_private *dev_priv = dev->dev_private;
15692 u32 val;
15693
15694 if (INTEL_INFO(dev)->num_pipes == 1)
15695 return true;
15696
15697 val = I915_READ(DSPCNTR(!crtc->plane));
15698
15699 if ((val & DISPLAY_PLANE_ENABLE) &&
15700 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15701 return false;
15702
15703 return true;
15704 }
15705
15706 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15707 {
15708 struct drm_device *dev = crtc->base.dev;
15709 struct intel_encoder *encoder;
15710
15711 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15712 return true;
15713
15714 return false;
15715 }
15716
15717 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15718 {
15719 struct drm_device *dev = encoder->base.dev;
15720 struct intel_connector *connector;
15721
15722 for_each_connector_on_encoder(dev, &encoder->base, connector)
15723 return true;
15724
15725 return false;
15726 }
15727
15728 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15729 {
15730 struct drm_device *dev = crtc->base.dev;
15731 struct drm_i915_private *dev_priv = dev->dev_private;
15732 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15733
15734 /* Clear any frame start delays used for debugging left by the BIOS */
15735 if (!transcoder_is_dsi(cpu_transcoder)) {
15736 i915_reg_t reg = PIPECONF(cpu_transcoder);
15737
15738 I915_WRITE(reg,
15739 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15740 }
15741
15742 /* restore vblank interrupts to correct state */
15743 drm_crtc_vblank_reset(&crtc->base);
15744 if (crtc->active) {
15745 struct intel_plane *plane;
15746
15747 drm_crtc_vblank_on(&crtc->base);
15748
15749 /* Disable everything but the primary plane */
15750 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15751 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15752 continue;
15753
15754 plane->disable_plane(&plane->base, &crtc->base);
15755 }
15756 }
15757
15758 /* We need to sanitize the plane -> pipe mapping first because this will
15759 * disable the crtc (and hence change the state) if it is wrong. Note
15760 * that gen4+ has a fixed plane -> pipe mapping. */
15761 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15762 bool plane;
15763
15764 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15765 crtc->base.base.id, crtc->base.name);
15766
15767 /* Pipe has the wrong plane attached and the plane is active.
15768 * Temporarily change the plane mapping and disable everything
15769 * ... */
15770 plane = crtc->plane;
15771 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15772 crtc->plane = !plane;
15773 intel_crtc_disable_noatomic(&crtc->base);
15774 crtc->plane = plane;
15775 }
15776
15777 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15778 crtc->pipe == PIPE_A && !crtc->active) {
15779 /* BIOS forgot to enable pipe A, this mostly happens after
15780 * resume. Force-enable the pipe to fix this, the update_dpms
15781 * call below we restore the pipe to the right state, but leave
15782 * the required bits on. */
15783 intel_enable_pipe_a(dev);
15784 }
15785
15786 /* Adjust the state of the output pipe according to whether we
15787 * have active connectors/encoders. */
15788 if (crtc->active && !intel_crtc_has_encoders(crtc))
15789 intel_crtc_disable_noatomic(&crtc->base);
15790
15791 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15792 /*
15793 * We start out with underrun reporting disabled to avoid races.
15794 * For correct bookkeeping mark this on active crtcs.
15795 *
15796 * Also on gmch platforms we dont have any hardware bits to
15797 * disable the underrun reporting. Which means we need to start
15798 * out with underrun reporting disabled also on inactive pipes,
15799 * since otherwise we'll complain about the garbage we read when
15800 * e.g. coming up after runtime pm.
15801 *
15802 * No protection against concurrent access is required - at
15803 * worst a fifo underrun happens which also sets this to false.
15804 */
15805 crtc->cpu_fifo_underrun_disabled = true;
15806 crtc->pch_fifo_underrun_disabled = true;
15807 }
15808 }
15809
15810 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15811 {
15812 struct intel_connector *connector;
15813 struct drm_device *dev = encoder->base.dev;
15814
15815 /* We need to check both for a crtc link (meaning that the
15816 * encoder is active and trying to read from a pipe) and the
15817 * pipe itself being active. */
15818 bool has_active_crtc = encoder->base.crtc &&
15819 to_intel_crtc(encoder->base.crtc)->active;
15820
15821 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15822 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15823 encoder->base.base.id,
15824 encoder->base.name);
15825
15826 /* Connector is active, but has no active pipe. This is
15827 * fallout from our resume register restoring. Disable
15828 * the encoder manually again. */
15829 if (encoder->base.crtc) {
15830 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15831 encoder->base.base.id,
15832 encoder->base.name);
15833 encoder->disable(encoder);
15834 if (encoder->post_disable)
15835 encoder->post_disable(encoder);
15836 }
15837 encoder->base.crtc = NULL;
15838
15839 /* Inconsistent output/port/pipe state happens presumably due to
15840 * a bug in one of the get_hw_state functions. Or someplace else
15841 * in our code, like the register restore mess on resume. Clamp
15842 * things to off as a safer default. */
15843 for_each_intel_connector(dev, connector) {
15844 if (connector->encoder != encoder)
15845 continue;
15846 connector->base.dpms = DRM_MODE_DPMS_OFF;
15847 connector->base.encoder = NULL;
15848 }
15849 }
15850 /* Enabled encoders without active connectors will be fixed in
15851 * the crtc fixup. */
15852 }
15853
15854 void i915_redisable_vga_power_on(struct drm_device *dev)
15855 {
15856 struct drm_i915_private *dev_priv = dev->dev_private;
15857 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15858
15859 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15860 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15861 i915_disable_vga(dev);
15862 }
15863 }
15864
15865 void i915_redisable_vga(struct drm_device *dev)
15866 {
15867 struct drm_i915_private *dev_priv = dev->dev_private;
15868
15869 /* This function can be called both from intel_modeset_setup_hw_state or
15870 * at a very early point in our resume sequence, where the power well
15871 * structures are not yet restored. Since this function is at a very
15872 * paranoid "someone might have enabled VGA while we were not looking"
15873 * level, just check if the power well is enabled instead of trying to
15874 * follow the "don't touch the power well if we don't need it" policy
15875 * the rest of the driver uses. */
15876 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15877 return;
15878
15879 i915_redisable_vga_power_on(dev);
15880
15881 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15882 }
15883
15884 static bool primary_get_hw_state(struct intel_plane *plane)
15885 {
15886 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15887
15888 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15889 }
15890
15891 /* FIXME read out full plane state for all planes */
15892 static void readout_plane_state(struct intel_crtc *crtc)
15893 {
15894 struct drm_plane *primary = crtc->base.primary;
15895 struct intel_plane_state *plane_state =
15896 to_intel_plane_state(primary->state);
15897
15898 plane_state->visible = crtc->active &&
15899 primary_get_hw_state(to_intel_plane(primary));
15900
15901 if (plane_state->visible)
15902 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15903 }
15904
15905 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15906 {
15907 struct drm_i915_private *dev_priv = dev->dev_private;
15908 enum pipe pipe;
15909 struct intel_crtc *crtc;
15910 struct intel_encoder *encoder;
15911 struct intel_connector *connector;
15912 int i;
15913
15914 dev_priv->active_crtcs = 0;
15915
15916 for_each_intel_crtc(dev, crtc) {
15917 struct intel_crtc_state *crtc_state = crtc->config;
15918 int pixclk = 0;
15919
15920 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15921 memset(crtc_state, 0, sizeof(*crtc_state));
15922 crtc_state->base.crtc = &crtc->base;
15923
15924 crtc_state->base.active = crtc_state->base.enable =
15925 dev_priv->display.get_pipe_config(crtc, crtc_state);
15926
15927 crtc->base.enabled = crtc_state->base.enable;
15928 crtc->active = crtc_state->base.active;
15929
15930 if (crtc_state->base.active) {
15931 dev_priv->active_crtcs |= 1 << crtc->pipe;
15932
15933 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15934 pixclk = ilk_pipe_pixel_rate(crtc_state);
15935 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15936 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15937 else
15938 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15939
15940 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15941 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15942 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15943 }
15944
15945 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15946
15947 readout_plane_state(crtc);
15948
15949 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15950 crtc->base.base.id, crtc->base.name,
15951 crtc->active ? "enabled" : "disabled");
15952 }
15953
15954 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15955 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15956
15957 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15958 &pll->config.hw_state);
15959 pll->config.crtc_mask = 0;
15960 for_each_intel_crtc(dev, crtc) {
15961 if (crtc->active && crtc->config->shared_dpll == pll)
15962 pll->config.crtc_mask |= 1 << crtc->pipe;
15963 }
15964 pll->active_mask = pll->config.crtc_mask;
15965
15966 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15967 pll->name, pll->config.crtc_mask, pll->on);
15968 }
15969
15970 for_each_intel_encoder(dev, encoder) {
15971 pipe = 0;
15972
15973 if (encoder->get_hw_state(encoder, &pipe)) {
15974 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15975 encoder->base.crtc = &crtc->base;
15976 encoder->get_config(encoder, crtc->config);
15977 } else {
15978 encoder->base.crtc = NULL;
15979 }
15980
15981 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15982 encoder->base.base.id,
15983 encoder->base.name,
15984 encoder->base.crtc ? "enabled" : "disabled",
15985 pipe_name(pipe));
15986 }
15987
15988 for_each_intel_connector(dev, connector) {
15989 if (connector->get_hw_state(connector)) {
15990 connector->base.dpms = DRM_MODE_DPMS_ON;
15991
15992 encoder = connector->encoder;
15993 connector->base.encoder = &encoder->base;
15994
15995 if (encoder->base.crtc &&
15996 encoder->base.crtc->state->active) {
15997 /*
15998 * This has to be done during hardware readout
15999 * because anything calling .crtc_disable may
16000 * rely on the connector_mask being accurate.
16001 */
16002 encoder->base.crtc->state->connector_mask |=
16003 1 << drm_connector_index(&connector->base);
16004 encoder->base.crtc->state->encoder_mask |=
16005 1 << drm_encoder_index(&encoder->base);
16006 }
16007
16008 } else {
16009 connector->base.dpms = DRM_MODE_DPMS_OFF;
16010 connector->base.encoder = NULL;
16011 }
16012 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16013 connector->base.base.id,
16014 connector->base.name,
16015 connector->base.encoder ? "enabled" : "disabled");
16016 }
16017
16018 for_each_intel_crtc(dev, crtc) {
16019 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16020
16021 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16022 if (crtc->base.state->active) {
16023 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16024 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16025 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16026
16027 /*
16028 * The initial mode needs to be set in order to keep
16029 * the atomic core happy. It wants a valid mode if the
16030 * crtc's enabled, so we do the above call.
16031 *
16032 * At this point some state updated by the connectors
16033 * in their ->detect() callback has not run yet, so
16034 * no recalculation can be done yet.
16035 *
16036 * Even if we could do a recalculation and modeset
16037 * right now it would cause a double modeset if
16038 * fbdev or userspace chooses a different initial mode.
16039 *
16040 * If that happens, someone indicated they wanted a
16041 * mode change, which means it's safe to do a full
16042 * recalculation.
16043 */
16044 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16045
16046 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16047 update_scanline_offset(crtc);
16048 }
16049
16050 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16051 }
16052 }
16053
16054 /* Scan out the current hw modeset state,
16055 * and sanitizes it to the current state
16056 */
16057 static void
16058 intel_modeset_setup_hw_state(struct drm_device *dev)
16059 {
16060 struct drm_i915_private *dev_priv = dev->dev_private;
16061 enum pipe pipe;
16062 struct intel_crtc *crtc;
16063 struct intel_encoder *encoder;
16064 int i;
16065
16066 intel_modeset_readout_hw_state(dev);
16067
16068 /* HW state is read out, now we need to sanitize this mess. */
16069 for_each_intel_encoder(dev, encoder) {
16070 intel_sanitize_encoder(encoder);
16071 }
16072
16073 for_each_pipe(dev_priv, pipe) {
16074 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16075 intel_sanitize_crtc(crtc);
16076 intel_dump_pipe_config(crtc, crtc->config,
16077 "[setup_hw_state]");
16078 }
16079
16080 intel_modeset_update_connector_atomic_state(dev);
16081
16082 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16083 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16084
16085 if (!pll->on || pll->active_mask)
16086 continue;
16087
16088 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16089
16090 pll->funcs.disable(dev_priv, pll);
16091 pll->on = false;
16092 }
16093
16094 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16095 vlv_wm_get_hw_state(dev);
16096 else if (IS_GEN9(dev))
16097 skl_wm_get_hw_state(dev);
16098 else if (HAS_PCH_SPLIT(dev))
16099 ilk_wm_get_hw_state(dev);
16100
16101 for_each_intel_crtc(dev, crtc) {
16102 unsigned long put_domains;
16103
16104 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16105 if (WARN_ON(put_domains))
16106 modeset_put_power_domains(dev_priv, put_domains);
16107 }
16108 intel_display_set_init_power(dev_priv, false);
16109
16110 intel_fbc_init_pipe_state(dev_priv);
16111 }
16112
16113 void intel_display_resume(struct drm_device *dev)
16114 {
16115 struct drm_i915_private *dev_priv = to_i915(dev);
16116 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16117 struct drm_modeset_acquire_ctx ctx;
16118 int ret;
16119 bool setup = false;
16120
16121 dev_priv->modeset_restore_state = NULL;
16122
16123 /*
16124 * This is a cludge because with real atomic modeset mode_config.mutex
16125 * won't be taken. Unfortunately some probed state like
16126 * audio_codec_enable is still protected by mode_config.mutex, so lock
16127 * it here for now.
16128 */
16129 mutex_lock(&dev->mode_config.mutex);
16130 drm_modeset_acquire_init(&ctx, 0);
16131
16132 retry:
16133 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16134
16135 if (ret == 0 && !setup) {
16136 setup = true;
16137
16138 intel_modeset_setup_hw_state(dev);
16139 i915_redisable_vga(dev);
16140 }
16141
16142 if (ret == 0 && state) {
16143 struct drm_crtc_state *crtc_state;
16144 struct drm_crtc *crtc;
16145 int i;
16146
16147 state->acquire_ctx = &ctx;
16148
16149 /* ignore any reset values/BIOS leftovers in the WM registers */
16150 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16151
16152 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16153 /*
16154 * Force recalculation even if we restore
16155 * current state. With fast modeset this may not result
16156 * in a modeset when the state is compatible.
16157 */
16158 crtc_state->mode_changed = true;
16159 }
16160
16161 ret = drm_atomic_commit(state);
16162 }
16163
16164 if (ret == -EDEADLK) {
16165 drm_modeset_backoff(&ctx);
16166 goto retry;
16167 }
16168
16169 drm_modeset_drop_locks(&ctx);
16170 drm_modeset_acquire_fini(&ctx);
16171 mutex_unlock(&dev->mode_config.mutex);
16172
16173 if (ret) {
16174 DRM_ERROR("Restoring old state failed with %i\n", ret);
16175 drm_atomic_state_free(state);
16176 }
16177 }
16178
16179 void intel_modeset_gem_init(struct drm_device *dev)
16180 {
16181 struct drm_i915_private *dev_priv = to_i915(dev);
16182 struct drm_crtc *c;
16183 struct drm_i915_gem_object *obj;
16184 int ret;
16185
16186 intel_init_gt_powersave(dev_priv);
16187
16188 intel_modeset_init_hw(dev);
16189
16190 intel_setup_overlay(dev_priv);
16191
16192 /*
16193 * Make sure any fbs we allocated at startup are properly
16194 * pinned & fenced. When we do the allocation it's too early
16195 * for this.
16196 */
16197 for_each_crtc(dev, c) {
16198 obj = intel_fb_obj(c->primary->fb);
16199 if (obj == NULL)
16200 continue;
16201
16202 mutex_lock(&dev->struct_mutex);
16203 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16204 c->primary->state->rotation);
16205 mutex_unlock(&dev->struct_mutex);
16206 if (ret) {
16207 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16208 to_intel_crtc(c)->pipe);
16209 drm_framebuffer_unreference(c->primary->fb);
16210 c->primary->fb = NULL;
16211 c->primary->crtc = c->primary->state->crtc = NULL;
16212 update_state_fb(c->primary);
16213 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16214 }
16215 }
16216
16217 intel_backlight_register(dev);
16218 }
16219
16220 void intel_connector_unregister(struct intel_connector *intel_connector)
16221 {
16222 struct drm_connector *connector = &intel_connector->base;
16223
16224 intel_panel_destroy_backlight(connector);
16225 drm_connector_unregister(connector);
16226 }
16227
16228 void intel_modeset_cleanup(struct drm_device *dev)
16229 {
16230 struct drm_i915_private *dev_priv = dev->dev_private;
16231 struct intel_connector *connector;
16232
16233 intel_disable_gt_powersave(dev_priv);
16234
16235 intel_backlight_unregister(dev);
16236
16237 /*
16238 * Interrupts and polling as the first thing to avoid creating havoc.
16239 * Too much stuff here (turning of connectors, ...) would
16240 * experience fancy races otherwise.
16241 */
16242 intel_irq_uninstall(dev_priv);
16243
16244 /*
16245 * Due to the hpd irq storm handling the hotplug work can re-arm the
16246 * poll handlers. Hence disable polling after hpd handling is shut down.
16247 */
16248 drm_kms_helper_poll_fini(dev);
16249
16250 intel_unregister_dsm_handler();
16251
16252 intel_fbc_global_disable(dev_priv);
16253
16254 /* flush any delayed tasks or pending work */
16255 flush_scheduled_work();
16256
16257 /* destroy the backlight and sysfs files before encoders/connectors */
16258 for_each_intel_connector(dev, connector)
16259 connector->unregister(connector);
16260
16261 drm_mode_config_cleanup(dev);
16262
16263 intel_cleanup_overlay(dev_priv);
16264
16265 intel_cleanup_gt_powersave(dev_priv);
16266
16267 intel_teardown_gmbus(dev);
16268 }
16269
16270 void intel_connector_attach_encoder(struct intel_connector *connector,
16271 struct intel_encoder *encoder)
16272 {
16273 connector->encoder = encoder;
16274 drm_mode_connector_attach_encoder(&connector->base,
16275 &encoder->base);
16276 }
16277
16278 /*
16279 * set vga decode state - true == enable VGA decode
16280 */
16281 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16282 {
16283 struct drm_i915_private *dev_priv = dev->dev_private;
16284 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16285 u16 gmch_ctrl;
16286
16287 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16288 DRM_ERROR("failed to read control word\n");
16289 return -EIO;
16290 }
16291
16292 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16293 return 0;
16294
16295 if (state)
16296 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16297 else
16298 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16299
16300 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16301 DRM_ERROR("failed to write control word\n");
16302 return -EIO;
16303 }
16304
16305 return 0;
16306 }
16307
16308 struct intel_display_error_state {
16309
16310 u32 power_well_driver;
16311
16312 int num_transcoders;
16313
16314 struct intel_cursor_error_state {
16315 u32 control;
16316 u32 position;
16317 u32 base;
16318 u32 size;
16319 } cursor[I915_MAX_PIPES];
16320
16321 struct intel_pipe_error_state {
16322 bool power_domain_on;
16323 u32 source;
16324 u32 stat;
16325 } pipe[I915_MAX_PIPES];
16326
16327 struct intel_plane_error_state {
16328 u32 control;
16329 u32 stride;
16330 u32 size;
16331 u32 pos;
16332 u32 addr;
16333 u32 surface;
16334 u32 tile_offset;
16335 } plane[I915_MAX_PIPES];
16336
16337 struct intel_transcoder_error_state {
16338 bool power_domain_on;
16339 enum transcoder cpu_transcoder;
16340
16341 u32 conf;
16342
16343 u32 htotal;
16344 u32 hblank;
16345 u32 hsync;
16346 u32 vtotal;
16347 u32 vblank;
16348 u32 vsync;
16349 } transcoder[4];
16350 };
16351
16352 struct intel_display_error_state *
16353 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16354 {
16355 struct intel_display_error_state *error;
16356 int transcoders[] = {
16357 TRANSCODER_A,
16358 TRANSCODER_B,
16359 TRANSCODER_C,
16360 TRANSCODER_EDP,
16361 };
16362 int i;
16363
16364 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16365 return NULL;
16366
16367 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16368 if (error == NULL)
16369 return NULL;
16370
16371 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16372 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16373
16374 for_each_pipe(dev_priv, i) {
16375 error->pipe[i].power_domain_on =
16376 __intel_display_power_is_enabled(dev_priv,
16377 POWER_DOMAIN_PIPE(i));
16378 if (!error->pipe[i].power_domain_on)
16379 continue;
16380
16381 error->cursor[i].control = I915_READ(CURCNTR(i));
16382 error->cursor[i].position = I915_READ(CURPOS(i));
16383 error->cursor[i].base = I915_READ(CURBASE(i));
16384
16385 error->plane[i].control = I915_READ(DSPCNTR(i));
16386 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16387 if (INTEL_GEN(dev_priv) <= 3) {
16388 error->plane[i].size = I915_READ(DSPSIZE(i));
16389 error->plane[i].pos = I915_READ(DSPPOS(i));
16390 }
16391 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16392 error->plane[i].addr = I915_READ(DSPADDR(i));
16393 if (INTEL_GEN(dev_priv) >= 4) {
16394 error->plane[i].surface = I915_READ(DSPSURF(i));
16395 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16396 }
16397
16398 error->pipe[i].source = I915_READ(PIPESRC(i));
16399
16400 if (HAS_GMCH_DISPLAY(dev_priv))
16401 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16402 }
16403
16404 /* Note: this does not include DSI transcoders. */
16405 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16406 if (HAS_DDI(dev_priv))
16407 error->num_transcoders++; /* Account for eDP. */
16408
16409 for (i = 0; i < error->num_transcoders; i++) {
16410 enum transcoder cpu_transcoder = transcoders[i];
16411
16412 error->transcoder[i].power_domain_on =
16413 __intel_display_power_is_enabled(dev_priv,
16414 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16415 if (!error->transcoder[i].power_domain_on)
16416 continue;
16417
16418 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16419
16420 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16421 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16422 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16423 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16424 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16425 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16426 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16427 }
16428
16429 return error;
16430 }
16431
16432 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16433
16434 void
16435 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16436 struct drm_device *dev,
16437 struct intel_display_error_state *error)
16438 {
16439 struct drm_i915_private *dev_priv = dev->dev_private;
16440 int i;
16441
16442 if (!error)
16443 return;
16444
16445 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16446 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16447 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16448 error->power_well_driver);
16449 for_each_pipe(dev_priv, i) {
16450 err_printf(m, "Pipe [%d]:\n", i);
16451 err_printf(m, " Power: %s\n",
16452 onoff(error->pipe[i].power_domain_on));
16453 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16454 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16455
16456 err_printf(m, "Plane [%d]:\n", i);
16457 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16458 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16459 if (INTEL_INFO(dev)->gen <= 3) {
16460 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16461 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16462 }
16463 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16464 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16465 if (INTEL_INFO(dev)->gen >= 4) {
16466 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16467 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16468 }
16469
16470 err_printf(m, "Cursor [%d]:\n", i);
16471 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16472 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16473 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16474 }
16475
16476 for (i = 0; i < error->num_transcoders; i++) {
16477 err_printf(m, "CPU transcoder: %s\n",
16478 transcoder_name(error->transcoder[i].cpu_transcoder));
16479 err_printf(m, " Power: %s\n",
16480 onoff(error->transcoder[i].power_domain_on));
16481 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16482 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16483 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16484 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16485 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16486 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16487 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16488 }
16489 }
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