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drm/i915: Treat fb->offsets[] as a raw byte offset instead of a linear offset
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54 DRM_FORMAT_C8,
55 DRM_FORMAT_RGB565,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_XRGB8888,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB8888,
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 };
69
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
74 };
75
76 static const uint32_t skl_primary_formats[] = {
77 DRM_FORMAT_C8,
78 DRM_FORMAT_RGB565,
79 DRM_FORMAT_XRGB8888,
80 DRM_FORMAT_XBGR8888,
81 DRM_FORMAT_ARGB8888,
82 DRM_FORMAT_ABGR8888,
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
85 DRM_FORMAT_YUYV,
86 DRM_FORMAT_YVYU,
87 DRM_FORMAT_UYVY,
88 DRM_FORMAT_VYUY,
89 };
90
91 static const uint64_t skl_format_modifiers_noccs[] = {
92 I915_FORMAT_MOD_Yf_TILED,
93 I915_FORMAT_MOD_Y_TILED,
94 I915_FORMAT_MOD_X_TILED,
95 DRM_FORMAT_MOD_LINEAR,
96 DRM_FORMAT_MOD_INVALID
97 };
98
99 static const uint64_t skl_format_modifiers_ccs[] = {
100 I915_FORMAT_MOD_Yf_TILED_CCS,
101 I915_FORMAT_MOD_Y_TILED_CCS,
102 I915_FORMAT_MOD_Yf_TILED,
103 I915_FORMAT_MOD_Y_TILED,
104 I915_FORMAT_MOD_X_TILED,
105 DRM_FORMAT_MOD_LINEAR,
106 DRM_FORMAT_MOD_INVALID
107 };
108
109 /* Cursor formats */
110 static const uint32_t intel_cursor_formats[] = {
111 DRM_FORMAT_ARGB8888,
112 };
113
114 static const uint64_t cursor_format_modifiers[] = {
115 DRM_FORMAT_MOD_LINEAR,
116 DRM_FORMAT_MOD_INVALID
117 };
118
119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
120 struct intel_crtc_state *pipe_config);
121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
122 struct intel_crtc_state *pipe_config);
123
124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
125 struct drm_i915_gem_object *obj,
126 struct drm_mode_fb_cmd2 *mode_cmd);
127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
131 struct intel_link_m_n *m_n,
132 struct intel_link_m_n *m2_n2);
133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
136 static void vlv_prepare_pll(struct intel_crtc *crtc,
137 const struct intel_crtc_state *pipe_config);
138 static void chv_prepare_pll(struct intel_crtc *crtc,
139 const struct intel_crtc_state *pipe_config);
140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
143 struct intel_crtc_state *crtc_state);
144 static void skylake_pfit_enable(struct intel_crtc *crtc);
145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
148 struct drm_modeset_acquire_ctx *ctx);
149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
150
151 struct intel_limit {
152 struct {
153 int min, max;
154 } dot, vco, n, m, m1, m2, p, p1;
155
156 struct {
157 int dot_limit;
158 int p2_slow, p2_fast;
159 } p2;
160 };
161
162 /* returns HPLL frequency in kHz */
163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
164 {
165 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
166
167 /* Obtain SKU information */
168 mutex_lock(&dev_priv->sb_lock);
169 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
170 CCK_FUSE_HPLL_FREQ_MASK;
171 mutex_unlock(&dev_priv->sb_lock);
172
173 return vco_freq[hpll_freq] * 1000;
174 }
175
176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
177 const char *name, u32 reg, int ref_freq)
178 {
179 u32 val;
180 int divider;
181
182 mutex_lock(&dev_priv->sb_lock);
183 val = vlv_cck_read(dev_priv, reg);
184 mutex_unlock(&dev_priv->sb_lock);
185
186 divider = val & CCK_FREQUENCY_VALUES;
187
188 WARN((val & CCK_FREQUENCY_STATUS) !=
189 (divider << CCK_FREQUENCY_STATUS_SHIFT),
190 "%s change in progress\n", name);
191
192 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
193 }
194
195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
196 const char *name, u32 reg)
197 {
198 if (dev_priv->hpll_freq == 0)
199 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
200
201 return vlv_get_cck_clock(dev_priv, name, reg,
202 dev_priv->hpll_freq);
203 }
204
205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
206 {
207 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
208 return;
209
210 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
211 CCK_CZ_CLOCK_CONTROL);
212
213 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
214 }
215
216 static inline u32 /* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
218 const struct intel_crtc_state *pipe_config)
219 {
220 if (HAS_DDI(dev_priv))
221 return pipe_config->port_clock; /* SPLL */
222 else if (IS_GEN5(dev_priv))
223 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
224 else
225 return 270000;
226 }
227
228 static const struct intel_limit intel_limits_i8xx_dac = {
229 .dot = { .min = 25000, .max = 350000 },
230 .vco = { .min = 908000, .max = 1512000 },
231 .n = { .min = 2, .max = 16 },
232 .m = { .min = 96, .max = 140 },
233 .m1 = { .min = 18, .max = 26 },
234 .m2 = { .min = 6, .max = 16 },
235 .p = { .min = 4, .max = 128 },
236 .p1 = { .min = 2, .max = 33 },
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 4, .p2_fast = 2 },
239 };
240
241 static const struct intel_limit intel_limits_i8xx_dvo = {
242 .dot = { .min = 25000, .max = 350000 },
243 .vco = { .min = 908000, .max = 1512000 },
244 .n = { .min = 2, .max = 16 },
245 .m = { .min = 96, .max = 140 },
246 .m1 = { .min = 18, .max = 26 },
247 .m2 = { .min = 6, .max = 16 },
248 .p = { .min = 4, .max = 128 },
249 .p1 = { .min = 2, .max = 33 },
250 .p2 = { .dot_limit = 165000,
251 .p2_slow = 4, .p2_fast = 4 },
252 };
253
254 static const struct intel_limit intel_limits_i8xx_lvds = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 1, .max = 6 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 14, .p2_fast = 7 },
265 };
266
267 static const struct intel_limit intel_limits_i9xx_sdvo = {
268 .dot = { .min = 20000, .max = 400000 },
269 .vco = { .min = 1400000, .max = 2800000 },
270 .n = { .min = 1, .max = 6 },
271 .m = { .min = 70, .max = 120 },
272 .m1 = { .min = 8, .max = 18 },
273 .m2 = { .min = 3, .max = 7 },
274 .p = { .min = 5, .max = 80 },
275 .p1 = { .min = 1, .max = 8 },
276 .p2 = { .dot_limit = 200000,
277 .p2_slow = 10, .p2_fast = 5 },
278 };
279
280 static const struct intel_limit intel_limits_i9xx_lvds = {
281 .dot = { .min = 20000, .max = 400000 },
282 .vco = { .min = 1400000, .max = 2800000 },
283 .n = { .min = 1, .max = 6 },
284 .m = { .min = 70, .max = 120 },
285 .m1 = { .min = 8, .max = 18 },
286 .m2 = { .min = 3, .max = 7 },
287 .p = { .min = 7, .max = 98 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 112000,
290 .p2_slow = 14, .p2_fast = 7 },
291 };
292
293
294 static const struct intel_limit intel_limits_g4x_sdvo = {
295 .dot = { .min = 25000, .max = 270000 },
296 .vco = { .min = 1750000, .max = 3500000},
297 .n = { .min = 1, .max = 4 },
298 .m = { .min = 104, .max = 138 },
299 .m1 = { .min = 17, .max = 23 },
300 .m2 = { .min = 5, .max = 11 },
301 .p = { .min = 10, .max = 30 },
302 .p1 = { .min = 1, .max = 3},
303 .p2 = { .dot_limit = 270000,
304 .p2_slow = 10,
305 .p2_fast = 10
306 },
307 };
308
309 static const struct intel_limit intel_limits_g4x_hdmi = {
310 .dot = { .min = 22000, .max = 400000 },
311 .vco = { .min = 1750000, .max = 3500000},
312 .n = { .min = 1, .max = 4 },
313 .m = { .min = 104, .max = 138 },
314 .m1 = { .min = 16, .max = 23 },
315 .m2 = { .min = 5, .max = 11 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8},
318 .p2 = { .dot_limit = 165000,
319 .p2_slow = 10, .p2_fast = 5 },
320 };
321
322 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
323 .dot = { .min = 20000, .max = 115000 },
324 .vco = { .min = 1750000, .max = 3500000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 104, .max = 138 },
327 .m1 = { .min = 17, .max = 23 },
328 .m2 = { .min = 5, .max = 11 },
329 .p = { .min = 28, .max = 112 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 0,
332 .p2_slow = 14, .p2_fast = 14
333 },
334 };
335
336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
337 .dot = { .min = 80000, .max = 224000 },
338 .vco = { .min = 1750000, .max = 3500000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 104, .max = 138 },
341 .m1 = { .min = 17, .max = 23 },
342 .m2 = { .min = 5, .max = 11 },
343 .p = { .min = 14, .max = 42 },
344 .p1 = { .min = 2, .max = 6 },
345 .p2 = { .dot_limit = 0,
346 .p2_slow = 7, .p2_fast = 7
347 },
348 };
349
350 static const struct intel_limit intel_limits_pineview_sdvo = {
351 .dot = { .min = 20000, .max = 400000},
352 .vco = { .min = 1700000, .max = 3500000 },
353 /* Pineview's Ncounter is a ring counter */
354 .n = { .min = 3, .max = 6 },
355 .m = { .min = 2, .max = 256 },
356 /* Pineview only has one combined m divider, which we treat as m2. */
357 .m1 = { .min = 0, .max = 0 },
358 .m2 = { .min = 0, .max = 254 },
359 .p = { .min = 5, .max = 80 },
360 .p1 = { .min = 1, .max = 8 },
361 .p2 = { .dot_limit = 200000,
362 .p2_slow = 10, .p2_fast = 5 },
363 };
364
365 static const struct intel_limit intel_limits_pineview_lvds = {
366 .dot = { .min = 20000, .max = 400000 },
367 .vco = { .min = 1700000, .max = 3500000 },
368 .n = { .min = 3, .max = 6 },
369 .m = { .min = 2, .max = 256 },
370 .m1 = { .min = 0, .max = 0 },
371 .m2 = { .min = 0, .max = 254 },
372 .p = { .min = 7, .max = 112 },
373 .p1 = { .min = 1, .max = 8 },
374 .p2 = { .dot_limit = 112000,
375 .p2_slow = 14, .p2_fast = 14 },
376 };
377
378 /* Ironlake / Sandybridge
379 *
380 * We calculate clock using (register_value + 2) for N/M1/M2, so here
381 * the range value for them is (actual_value - 2).
382 */
383 static const struct intel_limit intel_limits_ironlake_dac = {
384 .dot = { .min = 25000, .max = 350000 },
385 .vco = { .min = 1760000, .max = 3510000 },
386 .n = { .min = 1, .max = 5 },
387 .m = { .min = 79, .max = 127 },
388 .m1 = { .min = 12, .max = 22 },
389 .m2 = { .min = 5, .max = 9 },
390 .p = { .min = 5, .max = 80 },
391 .p1 = { .min = 1, .max = 8 },
392 .p2 = { .dot_limit = 225000,
393 .p2_slow = 10, .p2_fast = 5 },
394 };
395
396 static const struct intel_limit intel_limits_ironlake_single_lvds = {
397 .dot = { .min = 25000, .max = 350000 },
398 .vco = { .min = 1760000, .max = 3510000 },
399 .n = { .min = 1, .max = 3 },
400 .m = { .min = 79, .max = 118 },
401 .m1 = { .min = 12, .max = 22 },
402 .m2 = { .min = 5, .max = 9 },
403 .p = { .min = 28, .max = 112 },
404 .p1 = { .min = 2, .max = 8 },
405 .p2 = { .dot_limit = 225000,
406 .p2_slow = 14, .p2_fast = 14 },
407 };
408
409 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 3 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 14, .max = 56 },
417 .p1 = { .min = 2, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 7, .p2_fast = 7 },
420 };
421
422 /* LVDS 100mhz refclk limits. */
423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
424 .dot = { .min = 25000, .max = 350000 },
425 .vco = { .min = 1760000, .max = 3510000 },
426 .n = { .min = 1, .max = 2 },
427 .m = { .min = 79, .max = 126 },
428 .m1 = { .min = 12, .max = 22 },
429 .m2 = { .min = 5, .max = 9 },
430 .p = { .min = 28, .max = 112 },
431 .p1 = { .min = 2, .max = 8 },
432 .p2 = { .dot_limit = 225000,
433 .p2_slow = 14, .p2_fast = 14 },
434 };
435
436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
437 .dot = { .min = 25000, .max = 350000 },
438 .vco = { .min = 1760000, .max = 3510000 },
439 .n = { .min = 1, .max = 3 },
440 .m = { .min = 79, .max = 126 },
441 .m1 = { .min = 12, .max = 22 },
442 .m2 = { .min = 5, .max = 9 },
443 .p = { .min = 14, .max = 42 },
444 .p1 = { .min = 2, .max = 6 },
445 .p2 = { .dot_limit = 225000,
446 .p2_slow = 7, .p2_fast = 7 },
447 };
448
449 static const struct intel_limit intel_limits_vlv = {
450 /*
451 * These are the data rate limits (measured in fast clocks)
452 * since those are the strictest limits we have. The fast
453 * clock and actual rate limits are more relaxed, so checking
454 * them would make no difference.
455 */
456 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
457 .vco = { .min = 4000000, .max = 6000000 },
458 .n = { .min = 1, .max = 7 },
459 .m1 = { .min = 2, .max = 3 },
460 .m2 = { .min = 11, .max = 156 },
461 .p1 = { .min = 2, .max = 3 },
462 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
463 };
464
465 static const struct intel_limit intel_limits_chv = {
466 /*
467 * These are the data rate limits (measured in fast clocks)
468 * since those are the strictest limits we have. The fast
469 * clock and actual rate limits are more relaxed, so checking
470 * them would make no difference.
471 */
472 .dot = { .min = 25000 * 5, .max = 540000 * 5},
473 .vco = { .min = 4800000, .max = 6480000 },
474 .n = { .min = 1, .max = 1 },
475 .m1 = { .min = 2, .max = 2 },
476 .m2 = { .min = 24 << 22, .max = 175 << 22 },
477 .p1 = { .min = 2, .max = 4 },
478 .p2 = { .p2_slow = 1, .p2_fast = 14 },
479 };
480
481 static const struct intel_limit intel_limits_bxt = {
482 /* FIXME: find real dot limits */
483 .dot = { .min = 0, .max = INT_MAX },
484 .vco = { .min = 4800000, .max = 6700000 },
485 .n = { .min = 1, .max = 1 },
486 .m1 = { .min = 2, .max = 2 },
487 /* FIXME: find real m2 limits */
488 .m2 = { .min = 2 << 22, .max = 255 << 22 },
489 .p1 = { .min = 2, .max = 4 },
490 .p2 = { .p2_slow = 1, .p2_fast = 20 },
491 };
492
493 static bool
494 needs_modeset(struct drm_crtc_state *state)
495 {
496 return drm_atomic_crtc_needs_modeset(state);
497 }
498
499 /*
500 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
501 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
502 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
503 * The helpers' return value is the rate of the clock that is fed to the
504 * display engine's pipe which can be the above fast dot clock rate or a
505 * divided-down version of it.
506 */
507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
508 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
509 {
510 clock->m = clock->m2 + 2;
511 clock->p = clock->p1 * clock->p2;
512 if (WARN_ON(clock->n == 0 || clock->p == 0))
513 return 0;
514 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
515 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
516
517 return clock->dot;
518 }
519
520 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
521 {
522 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
523 }
524
525 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527 clock->m = i9xx_dpll_compute_m(clock);
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
530 return 0;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534 return clock->dot;
535 }
536
537 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
538 {
539 clock->m = clock->m1 * clock->m2;
540 clock->p = clock->p1 * clock->p2;
541 if (WARN_ON(clock->n == 0 || clock->p == 0))
542 return 0;
543 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
544 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
545
546 return clock->dot / 5;
547 }
548
549 int chv_calc_dpll_params(int refclk, struct dpll *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return 0;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558
559 return clock->dot / 5;
560 }
561
562 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
563 /**
564 * Returns whether the given set of divisors are valid for a given refclk with
565 * the given connectors.
566 */
567
568 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
569 const struct intel_limit *limit,
570 const struct dpll *clock)
571 {
572 if (clock->n < limit->n.min || limit->n.max < clock->n)
573 INTELPllInvalid("n out of range\n");
574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
577 INTELPllInvalid("m2 out of range\n");
578 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
579 INTELPllInvalid("m1 out of range\n");
580
581 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
582 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
583 if (clock->m1 <= clock->m2)
584 INTELPllInvalid("m1 <= m2\n");
585
586 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
587 !IS_GEN9_LP(dev_priv)) {
588 if (clock->p < limit->p.min || limit->p.max < clock->p)
589 INTELPllInvalid("p out of range\n");
590 if (clock->m < limit->m.min || limit->m.max < clock->m)
591 INTELPllInvalid("m out of range\n");
592 }
593
594 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
595 INTELPllInvalid("vco out of range\n");
596 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
597 * connector, etc., rather than just a single range.
598 */
599 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
600 INTELPllInvalid("dot out of range\n");
601
602 return true;
603 }
604
605 static int
606 i9xx_select_p2_div(const struct intel_limit *limit,
607 const struct intel_crtc_state *crtc_state,
608 int target)
609 {
610 struct drm_device *dev = crtc_state->base.crtc->dev;
611
612 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
613 /*
614 * For LVDS just rely on its current settings for dual-channel.
615 * We haven't figured out how to reliably set up different
616 * single/dual channel state, if we even can.
617 */
618 if (intel_is_dual_link_lvds(dev))
619 return limit->p2.p2_fast;
620 else
621 return limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 return limit->p2.p2_slow;
625 else
626 return limit->p2.p2_fast;
627 }
628 }
629
630 /*
631 * Returns a set of divisors for the desired target clock with the given
632 * refclk, or FALSE. The returned values represent the clock equation:
633 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
634 *
635 * Target and reference clocks are specified in kHz.
636 *
637 * If match_clock is provided, then best_clock P divider must match the P
638 * divider from @match_clock used for LVDS downclocking.
639 */
640 static bool
641 i9xx_find_best_dpll(const struct intel_limit *limit,
642 struct intel_crtc_state *crtc_state,
643 int target, int refclk, struct dpll *match_clock,
644 struct dpll *best_clock)
645 {
646 struct drm_device *dev = crtc_state->base.crtc->dev;
647 struct dpll clock;
648 int err = target;
649
650 memset(best_clock, 0, sizeof(*best_clock));
651
652 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
653
654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
658 if (clock.m2 >= clock.m1)
659 break;
660 for (clock.n = limit->n.min;
661 clock.n <= limit->n.max; clock.n++) {
662 for (clock.p1 = limit->p1.min;
663 clock.p1 <= limit->p1.max; clock.p1++) {
664 int this_err;
665
666 i9xx_calc_dpll_params(refclk, &clock);
667 if (!intel_PLL_is_valid(to_i915(dev),
668 limit,
669 &clock))
670 continue;
671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686 }
687
688 /*
689 * Returns a set of divisors for the desired target clock with the given
690 * refclk, or FALSE. The returned values represent the clock equation:
691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
692 *
693 * Target and reference clocks are specified in kHz.
694 *
695 * If match_clock is provided, then best_clock P divider must match the P
696 * divider from @match_clock used for LVDS downclocking.
697 */
698 static bool
699 pnv_find_best_dpll(const struct intel_limit *limit,
700 struct intel_crtc_state *crtc_state,
701 int target, int refclk, struct dpll *match_clock,
702 struct dpll *best_clock)
703 {
704 struct drm_device *dev = crtc_state->base.crtc->dev;
705 struct dpll clock;
706 int err = target;
707
708 memset(best_clock, 0, sizeof(*best_clock));
709
710 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
711
712 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
713 clock.m1++) {
714 for (clock.m2 = limit->m2.min;
715 clock.m2 <= limit->m2.max; clock.m2++) {
716 for (clock.n = limit->n.min;
717 clock.n <= limit->n.max; clock.n++) {
718 for (clock.p1 = limit->p1.min;
719 clock.p1 <= limit->p1.max; clock.p1++) {
720 int this_err;
721
722 pnv_calc_dpll_params(refclk, &clock);
723 if (!intel_PLL_is_valid(to_i915(dev),
724 limit,
725 &clock))
726 continue;
727 if (match_clock &&
728 clock.p != match_clock->p)
729 continue;
730
731 this_err = abs(clock.dot - target);
732 if (this_err < err) {
733 *best_clock = clock;
734 err = this_err;
735 }
736 }
737 }
738 }
739 }
740
741 return (err != target);
742 }
743
744 /*
745 * Returns a set of divisors for the desired target clock with the given
746 * refclk, or FALSE. The returned values represent the clock equation:
747 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
748 *
749 * Target and reference clocks are specified in kHz.
750 *
751 * If match_clock is provided, then best_clock P divider must match the P
752 * divider from @match_clock used for LVDS downclocking.
753 */
754 static bool
755 g4x_find_best_dpll(const struct intel_limit *limit,
756 struct intel_crtc_state *crtc_state,
757 int target, int refclk, struct dpll *match_clock,
758 struct dpll *best_clock)
759 {
760 struct drm_device *dev = crtc_state->base.crtc->dev;
761 struct dpll clock;
762 int max_n;
763 bool found = false;
764 /* approximately equals target * 0.00585 */
765 int err_most = (target >> 8) + (target >> 9);
766
767 memset(best_clock, 0, sizeof(*best_clock));
768
769 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
770
771 max_n = limit->n.max;
772 /* based on hardware requirement, prefer smaller n to precision */
773 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
774 /* based on hardware requirement, prefere larger m1,m2 */
775 for (clock.m1 = limit->m1.max;
776 clock.m1 >= limit->m1.min; clock.m1--) {
777 for (clock.m2 = limit->m2.max;
778 clock.m2 >= limit->m2.min; clock.m2--) {
779 for (clock.p1 = limit->p1.max;
780 clock.p1 >= limit->p1.min; clock.p1--) {
781 int this_err;
782
783 i9xx_calc_dpll_params(refclk, &clock);
784 if (!intel_PLL_is_valid(to_i915(dev),
785 limit,
786 &clock))
787 continue;
788
789 this_err = abs(clock.dot - target);
790 if (this_err < err_most) {
791 *best_clock = clock;
792 err_most = this_err;
793 max_n = clock.n;
794 found = true;
795 }
796 }
797 }
798 }
799 }
800 return found;
801 }
802
803 /*
804 * Check if the calculated PLL configuration is more optimal compared to the
805 * best configuration and error found so far. Return the calculated error.
806 */
807 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
808 const struct dpll *calculated_clock,
809 const struct dpll *best_clock,
810 unsigned int best_error_ppm,
811 unsigned int *error_ppm)
812 {
813 /*
814 * For CHV ignore the error and consider only the P value.
815 * Prefer a bigger P value based on HW requirements.
816 */
817 if (IS_CHERRYVIEW(to_i915(dev))) {
818 *error_ppm = 0;
819
820 return calculated_clock->p > best_clock->p;
821 }
822
823 if (WARN_ON_ONCE(!target_freq))
824 return false;
825
826 *error_ppm = div_u64(1000000ULL *
827 abs(target_freq - calculated_clock->dot),
828 target_freq);
829 /*
830 * Prefer a better P value over a better (smaller) error if the error
831 * is small. Ensure this preference for future configurations too by
832 * setting the error to 0.
833 */
834 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
835 *error_ppm = 0;
836
837 return true;
838 }
839
840 return *error_ppm + 10 < best_error_ppm;
841 }
842
843 /*
844 * Returns a set of divisors for the desired target clock with the given
845 * refclk, or FALSE. The returned values represent the clock equation:
846 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
847 */
848 static bool
849 vlv_find_best_dpll(const struct intel_limit *limit,
850 struct intel_crtc_state *crtc_state,
851 int target, int refclk, struct dpll *match_clock,
852 struct dpll *best_clock)
853 {
854 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
855 struct drm_device *dev = crtc->base.dev;
856 struct dpll clock;
857 unsigned int bestppm = 1000000;
858 /* min update 19.2 MHz */
859 int max_n = min(limit->n.max, refclk / 19200);
860 bool found = false;
861
862 target *= 5; /* fast clock */
863
864 memset(best_clock, 0, sizeof(*best_clock));
865
866 /* based on hardware requirement, prefer smaller n to precision */
867 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
868 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
869 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
870 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
871 clock.p = clock.p1 * clock.p2;
872 /* based on hardware requirement, prefer bigger m1,m2 values */
873 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
874 unsigned int ppm;
875
876 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
877 refclk * clock.m1);
878
879 vlv_calc_dpll_params(refclk, &clock);
880
881 if (!intel_PLL_is_valid(to_i915(dev),
882 limit,
883 &clock))
884 continue;
885
886 if (!vlv_PLL_is_optimal(dev, target,
887 &clock,
888 best_clock,
889 bestppm, &ppm))
890 continue;
891
892 *best_clock = clock;
893 bestppm = ppm;
894 found = true;
895 }
896 }
897 }
898 }
899
900 return found;
901 }
902
903 /*
904 * Returns a set of divisors for the desired target clock with the given
905 * refclk, or FALSE. The returned values represent the clock equation:
906 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
907 */
908 static bool
909 chv_find_best_dpll(const struct intel_limit *limit,
910 struct intel_crtc_state *crtc_state,
911 int target, int refclk, struct dpll *match_clock,
912 struct dpll *best_clock)
913 {
914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
915 struct drm_device *dev = crtc->base.dev;
916 unsigned int best_error_ppm;
917 struct dpll clock;
918 uint64_t m2;
919 int found = false;
920
921 memset(best_clock, 0, sizeof(*best_clock));
922 best_error_ppm = 1000000;
923
924 /*
925 * Based on hardware doc, the n always set to 1, and m1 always
926 * set to 2. If requires to support 200Mhz refclk, we need to
927 * revisit this because n may not 1 anymore.
928 */
929 clock.n = 1, clock.m1 = 2;
930 target *= 5; /* fast clock */
931
932 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
933 for (clock.p2 = limit->p2.p2_fast;
934 clock.p2 >= limit->p2.p2_slow;
935 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
936 unsigned int error_ppm;
937
938 clock.p = clock.p1 * clock.p2;
939
940 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
941 clock.n) << 22, refclk * clock.m1);
942
943 if (m2 > INT_MAX/clock.m1)
944 continue;
945
946 clock.m2 = m2;
947
948 chv_calc_dpll_params(refclk, &clock);
949
950 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
951 continue;
952
953 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
954 best_error_ppm, &error_ppm))
955 continue;
956
957 *best_clock = clock;
958 best_error_ppm = error_ppm;
959 found = true;
960 }
961 }
962
963 return found;
964 }
965
966 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
967 struct dpll *best_clock)
968 {
969 int refclk = 100000;
970 const struct intel_limit *limit = &intel_limits_bxt;
971
972 return chv_find_best_dpll(limit, crtc_state,
973 target_clock, refclk, NULL, best_clock);
974 }
975
976 bool intel_crtc_active(struct intel_crtc *crtc)
977 {
978 /* Be paranoid as we can arrive here with only partial
979 * state retrieved from the hardware during setup.
980 *
981 * We can ditch the adjusted_mode.crtc_clock check as soon
982 * as Haswell has gained clock readout/fastboot support.
983 *
984 * We can ditch the crtc->primary->fb check as soon as we can
985 * properly reconstruct framebuffers.
986 *
987 * FIXME: The intel_crtc->active here should be switched to
988 * crtc->state->active once we have proper CRTC states wired up
989 * for atomic.
990 */
991 return crtc->active && crtc->base.primary->state->fb &&
992 crtc->config->base.adjusted_mode.crtc_clock;
993 }
994
995 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
996 enum pipe pipe)
997 {
998 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
999
1000 return crtc->config->cpu_transcoder;
1001 }
1002
1003 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1004 {
1005 i915_reg_t reg = PIPEDSL(pipe);
1006 u32 line1, line2;
1007 u32 line_mask;
1008
1009 if (IS_GEN2(dev_priv))
1010 line_mask = DSL_LINEMASK_GEN2;
1011 else
1012 line_mask = DSL_LINEMASK_GEN3;
1013
1014 line1 = I915_READ(reg) & line_mask;
1015 msleep(5);
1016 line2 = I915_READ(reg) & line_mask;
1017
1018 return line1 == line2;
1019 }
1020
1021 /*
1022 * intel_wait_for_pipe_off - wait for pipe to turn off
1023 * @crtc: crtc whose pipe to wait for
1024 *
1025 * After disabling a pipe, we can't wait for vblank in the usual way,
1026 * spinning on the vblank interrupt status bit, since we won't actually
1027 * see an interrupt when the pipe is disabled.
1028 *
1029 * On Gen4 and above:
1030 * wait for the pipe register state bit to turn off
1031 *
1032 * Otherwise:
1033 * wait for the display line value to settle (it usually
1034 * ends up stopping at the start of the next frame).
1035 *
1036 */
1037 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1038 {
1039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1041 enum pipe pipe = crtc->pipe;
1042
1043 if (INTEL_GEN(dev_priv) >= 4) {
1044 i915_reg_t reg = PIPECONF(cpu_transcoder);
1045
1046 /* Wait for the Pipe State to go off */
1047 if (intel_wait_for_register(dev_priv,
1048 reg, I965_PIPECONF_ACTIVE, 0,
1049 100))
1050 WARN(1, "pipe_off wait timed out\n");
1051 } else {
1052 /* Wait for the display line to settle */
1053 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1054 WARN(1, "pipe_off wait timed out\n");
1055 }
1056 }
1057
1058 /* Only for pre-ILK configs */
1059 void assert_pll(struct drm_i915_private *dev_priv,
1060 enum pipe pipe, bool state)
1061 {
1062 u32 val;
1063 bool cur_state;
1064
1065 val = I915_READ(DPLL(pipe));
1066 cur_state = !!(val & DPLL_VCO_ENABLE);
1067 I915_STATE_WARN(cur_state != state,
1068 "PLL state assertion failure (expected %s, current %s)\n",
1069 onoff(state), onoff(cur_state));
1070 }
1071
1072 /* XXX: the dsi pll is shared between MIPI DSI ports */
1073 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1074 {
1075 u32 val;
1076 bool cur_state;
1077
1078 mutex_lock(&dev_priv->sb_lock);
1079 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1080 mutex_unlock(&dev_priv->sb_lock);
1081
1082 cur_state = val & DSI_PLL_VCO_EN;
1083 I915_STATE_WARN(cur_state != state,
1084 "DSI PLL state assertion failure (expected %s, current %s)\n",
1085 onoff(state), onoff(cur_state));
1086 }
1087
1088 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1089 enum pipe pipe, bool state)
1090 {
1091 bool cur_state;
1092 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093 pipe);
1094
1095 if (HAS_DDI(dev_priv)) {
1096 /* DDI does not have a specific FDI_TX register */
1097 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1098 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1099 } else {
1100 u32 val = I915_READ(FDI_TX_CTL(pipe));
1101 cur_state = !!(val & FDI_TX_ENABLE);
1102 }
1103 I915_STATE_WARN(cur_state != state,
1104 "FDI TX state assertion failure (expected %s, current %s)\n",
1105 onoff(state), onoff(cur_state));
1106 }
1107 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1108 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1109
1110 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1111 enum pipe pipe, bool state)
1112 {
1113 u32 val;
1114 bool cur_state;
1115
1116 val = I915_READ(FDI_RX_CTL(pipe));
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 u32 val;
1129
1130 /* ILK FDI PLL is always enabled */
1131 if (IS_GEN5(dev_priv))
1132 return;
1133
1134 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135 if (HAS_DDI(dev_priv))
1136 return;
1137
1138 val = I915_READ(FDI_TX_CTL(pipe));
1139 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1140 }
1141
1142 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, bool state)
1144 {
1145 u32 val;
1146 bool cur_state;
1147
1148 val = I915_READ(FDI_RX_CTL(pipe));
1149 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1150 I915_STATE_WARN(cur_state != state,
1151 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1152 onoff(state), onoff(cur_state));
1153 }
1154
1155 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157 i915_reg_t pp_reg;
1158 u32 val;
1159 enum pipe panel_pipe = PIPE_A;
1160 bool locked = true;
1161
1162 if (WARN_ON(HAS_DDI(dev_priv)))
1163 return;
1164
1165 if (HAS_PCH_SPLIT(dev_priv)) {
1166 u32 port_sel;
1167
1168 pp_reg = PP_CONTROL(0);
1169 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1170
1171 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1172 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1173 panel_pipe = PIPE_B;
1174 /* XXX: else fix for eDP */
1175 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1176 /* presumably write lock depends on pipe, not port select */
1177 pp_reg = PP_CONTROL(pipe);
1178 panel_pipe = pipe;
1179 } else {
1180 pp_reg = PP_CONTROL(0);
1181 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1182 panel_pipe = PIPE_B;
1183 }
1184
1185 val = I915_READ(pp_reg);
1186 if (!(val & PANEL_POWER_ON) ||
1187 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1188 locked = false;
1189
1190 I915_STATE_WARN(panel_pipe == pipe && locked,
1191 "panel assertion failure, pipe %c regs locked\n",
1192 pipe_name(pipe));
1193 }
1194
1195 static void assert_cursor(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1197 {
1198 bool cur_state;
1199
1200 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1201 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1202 else
1203 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1204
1205 I915_STATE_WARN(cur_state != state,
1206 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1207 pipe_name(pipe), onoff(state), onoff(cur_state));
1208 }
1209 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1210 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1211
1212 void assert_pipe(struct drm_i915_private *dev_priv,
1213 enum pipe pipe, bool state)
1214 {
1215 bool cur_state;
1216 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1217 pipe);
1218 enum intel_display_power_domain power_domain;
1219
1220 /* we keep both pipes enabled on 830 */
1221 if (IS_I830(dev_priv))
1222 state = true;
1223
1224 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1225 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1226 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1227 cur_state = !!(val & PIPECONF_ENABLE);
1228
1229 intel_display_power_put(dev_priv, power_domain);
1230 } else {
1231 cur_state = false;
1232 }
1233
1234 I915_STATE_WARN(cur_state != state,
1235 "pipe %c assertion failure (expected %s, current %s)\n",
1236 pipe_name(pipe), onoff(state), onoff(cur_state));
1237 }
1238
1239 static void assert_plane(struct drm_i915_private *dev_priv,
1240 enum plane plane, bool state)
1241 {
1242 u32 val;
1243 bool cur_state;
1244
1245 val = I915_READ(DSPCNTR(plane));
1246 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "plane %c assertion failure (expected %s, current %s)\n",
1249 plane_name(plane), onoff(state), onoff(cur_state));
1250 }
1251
1252 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1253 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1254
1255 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1256 enum pipe pipe)
1257 {
1258 int i;
1259
1260 /* Primary planes are fixed to pipes on gen4+ */
1261 if (INTEL_GEN(dev_priv) >= 4) {
1262 u32 val = I915_READ(DSPCNTR(pipe));
1263 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1264 "plane %c assertion failure, should be disabled but not\n",
1265 plane_name(pipe));
1266 return;
1267 }
1268
1269 /* Need to check both planes against the pipe */
1270 for_each_pipe(dev_priv, i) {
1271 u32 val = I915_READ(DSPCNTR(i));
1272 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1273 DISPPLANE_SEL_PIPE_SHIFT;
1274 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1275 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1276 plane_name(i), pipe_name(pipe));
1277 }
1278 }
1279
1280 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1281 enum pipe pipe)
1282 {
1283 int sprite;
1284
1285 if (INTEL_GEN(dev_priv) >= 9) {
1286 for_each_sprite(dev_priv, pipe, sprite) {
1287 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1288 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1289 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1290 sprite, pipe_name(pipe));
1291 }
1292 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1293 for_each_sprite(dev_priv, pipe, sprite) {
1294 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1295 I915_STATE_WARN(val & SP_ENABLE,
1296 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297 sprite_name(pipe, sprite), pipe_name(pipe));
1298 }
1299 } else if (INTEL_GEN(dev_priv) >= 7) {
1300 u32 val = I915_READ(SPRCTL(pipe));
1301 I915_STATE_WARN(val & SPRITE_ENABLE,
1302 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303 plane_name(pipe), pipe_name(pipe));
1304 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1305 u32 val = I915_READ(DVSCNTR(pipe));
1306 I915_STATE_WARN(val & DVS_ENABLE,
1307 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1308 plane_name(pipe), pipe_name(pipe));
1309 }
1310 }
1311
1312 static void assert_vblank_disabled(struct drm_crtc *crtc)
1313 {
1314 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1315 drm_crtc_vblank_put(crtc);
1316 }
1317
1318 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1319 enum pipe pipe)
1320 {
1321 u32 val;
1322 bool enabled;
1323
1324 val = I915_READ(PCH_TRANSCONF(pipe));
1325 enabled = !!(val & TRANS_ENABLE);
1326 I915_STATE_WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv)) {
1338 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1339 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1340 return false;
1341 } else if (IS_CHERRYVIEW(dev_priv)) {
1342 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1343 return false;
1344 } else {
1345 if ((val & DP_PIPE_MASK) != (pipe << 30))
1346 return false;
1347 }
1348 return true;
1349 }
1350
1351 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe, u32 val)
1353 {
1354 if ((val & SDVO_ENABLE) == 0)
1355 return false;
1356
1357 if (HAS_PCH_CPT(dev_priv)) {
1358 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1359 return false;
1360 } else if (IS_CHERRYVIEW(dev_priv)) {
1361 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1362 return false;
1363 } else {
1364 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1365 return false;
1366 }
1367 return true;
1368 }
1369
1370 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1372 {
1373 if ((val & LVDS_PORT_EN) == 0)
1374 return false;
1375
1376 if (HAS_PCH_CPT(dev_priv)) {
1377 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1378 return false;
1379 } else {
1380 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1381 return false;
1382 }
1383 return true;
1384 }
1385
1386 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1387 enum pipe pipe, u32 val)
1388 {
1389 if ((val & ADPA_DAC_ENABLE) == 0)
1390 return false;
1391 if (HAS_PCH_CPT(dev_priv)) {
1392 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1393 return false;
1394 } else {
1395 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1396 return false;
1397 }
1398 return true;
1399 }
1400
1401 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1402 enum pipe pipe, i915_reg_t reg,
1403 u32 port_sel)
1404 {
1405 u32 val = I915_READ(reg);
1406 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1407 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1408 i915_mmio_reg_offset(reg), pipe_name(pipe));
1409
1410 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1411 && (val & DP_PIPEB_SELECT),
1412 "IBX PCH dp port still using transcoder B\n");
1413 }
1414
1415 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1416 enum pipe pipe, i915_reg_t reg)
1417 {
1418 u32 val = I915_READ(reg);
1419 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1420 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1421 i915_mmio_reg_offset(reg), pipe_name(pipe));
1422
1423 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1424 && (val & SDVO_PIPE_B_SELECT),
1425 "IBX PCH hdmi port still using transcoder B\n");
1426 }
1427
1428 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1429 enum pipe pipe)
1430 {
1431 u32 val;
1432
1433 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1434 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1435 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1436
1437 val = I915_READ(PCH_ADPA);
1438 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439 "PCH VGA enabled on transcoder %c, should be disabled\n",
1440 pipe_name(pipe));
1441
1442 val = I915_READ(PCH_LVDS);
1443 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1444 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1445 pipe_name(pipe));
1446
1447 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1448 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1449 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1450 }
1451
1452 static void _vlv_enable_pll(struct intel_crtc *crtc,
1453 const struct intel_crtc_state *pipe_config)
1454 {
1455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1456 enum pipe pipe = crtc->pipe;
1457
1458 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1459 POSTING_READ(DPLL(pipe));
1460 udelay(150);
1461
1462 if (intel_wait_for_register(dev_priv,
1463 DPLL(pipe),
1464 DPLL_LOCK_VLV,
1465 DPLL_LOCK_VLV,
1466 1))
1467 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1468 }
1469
1470 static void vlv_enable_pll(struct intel_crtc *crtc,
1471 const struct intel_crtc_state *pipe_config)
1472 {
1473 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1474 enum pipe pipe = crtc->pipe;
1475
1476 assert_pipe_disabled(dev_priv, pipe);
1477
1478 /* PLL is protected by panel, make sure we can write it */
1479 assert_panel_unlocked(dev_priv, pipe);
1480
1481 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1482 _vlv_enable_pll(crtc, pipe_config);
1483
1484 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1485 POSTING_READ(DPLL_MD(pipe));
1486 }
1487
1488
1489 static void _chv_enable_pll(struct intel_crtc *crtc,
1490 const struct intel_crtc_state *pipe_config)
1491 {
1492 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1493 enum pipe pipe = crtc->pipe;
1494 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1495 u32 tmp;
1496
1497 mutex_lock(&dev_priv->sb_lock);
1498
1499 /* Enable back the 10bit clock to display controller */
1500 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1501 tmp |= DPIO_DCLKP_EN;
1502 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1503
1504 mutex_unlock(&dev_priv->sb_lock);
1505
1506 /*
1507 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1508 */
1509 udelay(1);
1510
1511 /* Enable PLL */
1512 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1513
1514 /* Check PLL is locked */
1515 if (intel_wait_for_register(dev_priv,
1516 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1517 1))
1518 DRM_ERROR("PLL %d failed to lock\n", pipe);
1519 }
1520
1521 static void chv_enable_pll(struct intel_crtc *crtc,
1522 const struct intel_crtc_state *pipe_config)
1523 {
1524 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1525 enum pipe pipe = crtc->pipe;
1526
1527 assert_pipe_disabled(dev_priv, pipe);
1528
1529 /* PLL is protected by panel, make sure we can write it */
1530 assert_panel_unlocked(dev_priv, pipe);
1531
1532 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1533 _chv_enable_pll(crtc, pipe_config);
1534
1535 if (pipe != PIPE_A) {
1536 /*
1537 * WaPixelRepeatModeFixForC0:chv
1538 *
1539 * DPLLCMD is AWOL. Use chicken bits to propagate
1540 * the value from DPLLBMD to either pipe B or C.
1541 */
1542 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1543 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1544 I915_WRITE(CBR4_VLV, 0);
1545 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1546
1547 /*
1548 * DPLLB VGA mode also seems to cause problems.
1549 * We should always have it disabled.
1550 */
1551 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1552 } else {
1553 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1554 POSTING_READ(DPLL_MD(pipe));
1555 }
1556 }
1557
1558 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1559 {
1560 struct intel_crtc *crtc;
1561 int count = 0;
1562
1563 for_each_intel_crtc(&dev_priv->drm, crtc) {
1564 count += crtc->base.state->active &&
1565 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1566 }
1567
1568 return count;
1569 }
1570
1571 static void i9xx_enable_pll(struct intel_crtc *crtc)
1572 {
1573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574 i915_reg_t reg = DPLL(crtc->pipe);
1575 u32 dpll = crtc->config->dpll_hw_state.dpll;
1576 int i;
1577
1578 assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580 /* PLL is protected by panel, make sure we can write it */
1581 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1582 assert_panel_unlocked(dev_priv, crtc->pipe);
1583
1584 /* Enable DVO 2x clock on both PLLs if necessary */
1585 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1586 /*
1587 * It appears to be important that we don't enable this
1588 * for the current pipe before otherwise configuring the
1589 * PLL. No idea how this should be handled if multiple
1590 * DVO outputs are enabled simultaneosly.
1591 */
1592 dpll |= DPLL_DVO_2X_MODE;
1593 I915_WRITE(DPLL(!crtc->pipe),
1594 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1595 }
1596
1597 /*
1598 * Apparently we need to have VGA mode enabled prior to changing
1599 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1600 * dividers, even though the register value does change.
1601 */
1602 I915_WRITE(reg, 0);
1603
1604 I915_WRITE(reg, dpll);
1605
1606 /* Wait for the clocks to stabilize. */
1607 POSTING_READ(reg);
1608 udelay(150);
1609
1610 if (INTEL_GEN(dev_priv) >= 4) {
1611 I915_WRITE(DPLL_MD(crtc->pipe),
1612 crtc->config->dpll_hw_state.dpll_md);
1613 } else {
1614 /* The pixel multiplier can only be updated once the
1615 * DPLL is enabled and the clocks are stable.
1616 *
1617 * So write it again.
1618 */
1619 I915_WRITE(reg, dpll);
1620 }
1621
1622 /* We do this three times for luck */
1623 for (i = 0; i < 3; i++) {
1624 I915_WRITE(reg, dpll);
1625 POSTING_READ(reg);
1626 udelay(150); /* wait for warmup */
1627 }
1628 }
1629
1630 /**
1631 * i9xx_disable_pll - disable a PLL
1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe PLL to disable
1634 *
1635 * Disable the PLL for @pipe, making sure the pipe is off first.
1636 *
1637 * Note! This is for pre-ILK only.
1638 */
1639 static void i9xx_disable_pll(struct intel_crtc *crtc)
1640 {
1641 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1642 enum pipe pipe = crtc->pipe;
1643
1644 /* Disable DVO 2x clock on both PLLs if necessary */
1645 if (IS_I830(dev_priv) &&
1646 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1647 !intel_num_dvo_pipes(dev_priv)) {
1648 I915_WRITE(DPLL(PIPE_B),
1649 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1650 I915_WRITE(DPLL(PIPE_A),
1651 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1652 }
1653
1654 /* Don't disable pipe or pipe PLLs if needed */
1655 if (IS_I830(dev_priv))
1656 return;
1657
1658 /* Make sure the pipe isn't still relying on us */
1659 assert_pipe_disabled(dev_priv, pipe);
1660
1661 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1662 POSTING_READ(DPLL(pipe));
1663 }
1664
1665 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1666 {
1667 u32 val;
1668
1669 /* Make sure the pipe isn't still relying on us */
1670 assert_pipe_disabled(dev_priv, pipe);
1671
1672 val = DPLL_INTEGRATED_REF_CLK_VLV |
1673 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1674 if (pipe != PIPE_A)
1675 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1676
1677 I915_WRITE(DPLL(pipe), val);
1678 POSTING_READ(DPLL(pipe));
1679 }
1680
1681 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1682 {
1683 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1684 u32 val;
1685
1686 /* Make sure the pipe isn't still relying on us */
1687 assert_pipe_disabled(dev_priv, pipe);
1688
1689 val = DPLL_SSC_REF_CLK_CHV |
1690 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1691 if (pipe != PIPE_A)
1692 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1693
1694 I915_WRITE(DPLL(pipe), val);
1695 POSTING_READ(DPLL(pipe));
1696
1697 mutex_lock(&dev_priv->sb_lock);
1698
1699 /* Disable 10bit clock to display controller */
1700 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1701 val &= ~DPIO_DCLKP_EN;
1702 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1703
1704 mutex_unlock(&dev_priv->sb_lock);
1705 }
1706
1707 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1708 struct intel_digital_port *dport,
1709 unsigned int expected_mask)
1710 {
1711 u32 port_mask;
1712 i915_reg_t dpll_reg;
1713
1714 switch (dport->port) {
1715 case PORT_B:
1716 port_mask = DPLL_PORTB_READY_MASK;
1717 dpll_reg = DPLL(0);
1718 break;
1719 case PORT_C:
1720 port_mask = DPLL_PORTC_READY_MASK;
1721 dpll_reg = DPLL(0);
1722 expected_mask <<= 4;
1723 break;
1724 case PORT_D:
1725 port_mask = DPLL_PORTD_READY_MASK;
1726 dpll_reg = DPIO_PHY_STATUS;
1727 break;
1728 default:
1729 BUG();
1730 }
1731
1732 if (intel_wait_for_register(dev_priv,
1733 dpll_reg, port_mask, expected_mask,
1734 1000))
1735 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1736 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1737 }
1738
1739 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1740 enum pipe pipe)
1741 {
1742 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1743 pipe);
1744 i915_reg_t reg;
1745 uint32_t val, pipeconf_val;
1746
1747 /* Make sure PCH DPLL is enabled */
1748 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1749
1750 /* FDI must be feeding us bits for PCH ports */
1751 assert_fdi_tx_enabled(dev_priv, pipe);
1752 assert_fdi_rx_enabled(dev_priv, pipe);
1753
1754 if (HAS_PCH_CPT(dev_priv)) {
1755 /* Workaround: Set the timing override bit before enabling the
1756 * pch transcoder. */
1757 reg = TRANS_CHICKEN2(pipe);
1758 val = I915_READ(reg);
1759 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1760 I915_WRITE(reg, val);
1761 }
1762
1763 reg = PCH_TRANSCONF(pipe);
1764 val = I915_READ(reg);
1765 pipeconf_val = I915_READ(PIPECONF(pipe));
1766
1767 if (HAS_PCH_IBX(dev_priv)) {
1768 /*
1769 * Make the BPC in transcoder be consistent with
1770 * that in pipeconf reg. For HDMI we must use 8bpc
1771 * here for both 8bpc and 12bpc.
1772 */
1773 val &= ~PIPECONF_BPC_MASK;
1774 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1775 val |= PIPECONF_8BPC;
1776 else
1777 val |= pipeconf_val & PIPECONF_BPC_MASK;
1778 }
1779
1780 val &= ~TRANS_INTERLACE_MASK;
1781 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1782 if (HAS_PCH_IBX(dev_priv) &&
1783 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1784 val |= TRANS_LEGACY_INTERLACED_ILK;
1785 else
1786 val |= TRANS_INTERLACED;
1787 else
1788 val |= TRANS_PROGRESSIVE;
1789
1790 I915_WRITE(reg, val | TRANS_ENABLE);
1791 if (intel_wait_for_register(dev_priv,
1792 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1793 100))
1794 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1795 }
1796
1797 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1798 enum transcoder cpu_transcoder)
1799 {
1800 u32 val, pipeconf_val;
1801
1802 /* FDI must be feeding us bits for PCH ports */
1803 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1804 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1805
1806 /* Workaround: set timing override bit. */
1807 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1808 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1809 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1810
1811 val = TRANS_ENABLE;
1812 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1813
1814 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1815 PIPECONF_INTERLACED_ILK)
1816 val |= TRANS_INTERLACED;
1817 else
1818 val |= TRANS_PROGRESSIVE;
1819
1820 I915_WRITE(LPT_TRANSCONF, val);
1821 if (intel_wait_for_register(dev_priv,
1822 LPT_TRANSCONF,
1823 TRANS_STATE_ENABLE,
1824 TRANS_STATE_ENABLE,
1825 100))
1826 DRM_ERROR("Failed to enable PCH transcoder\n");
1827 }
1828
1829 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1830 enum pipe pipe)
1831 {
1832 i915_reg_t reg;
1833 uint32_t val;
1834
1835 /* FDI relies on the transcoder */
1836 assert_fdi_tx_disabled(dev_priv, pipe);
1837 assert_fdi_rx_disabled(dev_priv, pipe);
1838
1839 /* Ports must be off as well */
1840 assert_pch_ports_disabled(dev_priv, pipe);
1841
1842 reg = PCH_TRANSCONF(pipe);
1843 val = I915_READ(reg);
1844 val &= ~TRANS_ENABLE;
1845 I915_WRITE(reg, val);
1846 /* wait for PCH transcoder off, transcoder state */
1847 if (intel_wait_for_register(dev_priv,
1848 reg, TRANS_STATE_ENABLE, 0,
1849 50))
1850 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1851
1852 if (HAS_PCH_CPT(dev_priv)) {
1853 /* Workaround: Clear the timing override chicken bit again. */
1854 reg = TRANS_CHICKEN2(pipe);
1855 val = I915_READ(reg);
1856 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(reg, val);
1858 }
1859 }
1860
1861 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1862 {
1863 u32 val;
1864
1865 val = I915_READ(LPT_TRANSCONF);
1866 val &= ~TRANS_ENABLE;
1867 I915_WRITE(LPT_TRANSCONF, val);
1868 /* wait for PCH transcoder off, transcoder state */
1869 if (intel_wait_for_register(dev_priv,
1870 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1871 50))
1872 DRM_ERROR("Failed to disable PCH transcoder\n");
1873
1874 /* Workaround: clear timing override bit. */
1875 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1876 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1877 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1878 }
1879
1880 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1881 {
1882 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1883
1884 WARN_ON(!crtc->config->has_pch_encoder);
1885
1886 if (HAS_PCH_LPT(dev_priv))
1887 return PIPE_A;
1888 else
1889 return crtc->pipe;
1890 }
1891
1892 /**
1893 * intel_enable_pipe - enable a pipe, asserting requirements
1894 * @crtc: crtc responsible for the pipe
1895 *
1896 * Enable @crtc's pipe, making sure that various hardware specific requirements
1897 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1898 */
1899 static void intel_enable_pipe(struct intel_crtc *crtc)
1900 {
1901 struct drm_device *dev = crtc->base.dev;
1902 struct drm_i915_private *dev_priv = to_i915(dev);
1903 enum pipe pipe = crtc->pipe;
1904 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1905 i915_reg_t reg;
1906 u32 val;
1907
1908 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1909
1910 assert_planes_disabled(dev_priv, pipe);
1911 assert_cursor_disabled(dev_priv, pipe);
1912 assert_sprites_disabled(dev_priv, pipe);
1913
1914 /*
1915 * A pipe without a PLL won't actually be able to drive bits from
1916 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1917 * need the check.
1918 */
1919 if (HAS_GMCH_DISPLAY(dev_priv)) {
1920 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1921 assert_dsi_pll_enabled(dev_priv);
1922 else
1923 assert_pll_enabled(dev_priv, pipe);
1924 } else {
1925 if (crtc->config->has_pch_encoder) {
1926 /* if driving the PCH, we need FDI enabled */
1927 assert_fdi_rx_pll_enabled(dev_priv,
1928 intel_crtc_pch_transcoder(crtc));
1929 assert_fdi_tx_pll_enabled(dev_priv,
1930 (enum pipe) cpu_transcoder);
1931 }
1932 /* FIXME: assert CPU port conditions for SNB+ */
1933 }
1934
1935 reg = PIPECONF(cpu_transcoder);
1936 val = I915_READ(reg);
1937 if (val & PIPECONF_ENABLE) {
1938 /* we keep both pipes enabled on 830 */
1939 WARN_ON(!IS_I830(dev_priv));
1940 return;
1941 }
1942
1943 I915_WRITE(reg, val | PIPECONF_ENABLE);
1944 POSTING_READ(reg);
1945
1946 /*
1947 * Until the pipe starts DSL will read as 0, which would cause
1948 * an apparent vblank timestamp jump, which messes up also the
1949 * frame count when it's derived from the timestamps. So let's
1950 * wait for the pipe to start properly before we call
1951 * drm_crtc_vblank_on()
1952 */
1953 if (dev->max_vblank_count == 0 &&
1954 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1955 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1956 }
1957
1958 /**
1959 * intel_disable_pipe - disable a pipe, asserting requirements
1960 * @crtc: crtc whose pipes is to be disabled
1961 *
1962 * Disable the pipe of @crtc, making sure that various hardware
1963 * specific requirements are met, if applicable, e.g. plane
1964 * disabled, panel fitter off, etc.
1965 *
1966 * Will wait until the pipe has shut down before returning.
1967 */
1968 static void intel_disable_pipe(struct intel_crtc *crtc)
1969 {
1970 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1971 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1972 enum pipe pipe = crtc->pipe;
1973 i915_reg_t reg;
1974 u32 val;
1975
1976 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1977
1978 /*
1979 * Make sure planes won't keep trying to pump pixels to us,
1980 * or we might hang the display.
1981 */
1982 assert_planes_disabled(dev_priv, pipe);
1983 assert_cursor_disabled(dev_priv, pipe);
1984 assert_sprites_disabled(dev_priv, pipe);
1985
1986 reg = PIPECONF(cpu_transcoder);
1987 val = I915_READ(reg);
1988 if ((val & PIPECONF_ENABLE) == 0)
1989 return;
1990
1991 /*
1992 * Double wide has implications for planes
1993 * so best keep it disabled when not needed.
1994 */
1995 if (crtc->config->double_wide)
1996 val &= ~PIPECONF_DOUBLE_WIDE;
1997
1998 /* Don't disable pipe or pipe PLLs if needed */
1999 if (!IS_I830(dev_priv))
2000 val &= ~PIPECONF_ENABLE;
2001
2002 I915_WRITE(reg, val);
2003 if ((val & PIPECONF_ENABLE) == 0)
2004 intel_wait_for_pipe_off(crtc);
2005 }
2006
2007 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2008 {
2009 return IS_GEN2(dev_priv) ? 2048 : 4096;
2010 }
2011
2012 static unsigned int
2013 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2014 {
2015 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2016 unsigned int cpp = fb->format->cpp[plane];
2017
2018 switch (fb->modifier) {
2019 case DRM_FORMAT_MOD_LINEAR:
2020 return cpp;
2021 case I915_FORMAT_MOD_X_TILED:
2022 if (IS_GEN2(dev_priv))
2023 return 128;
2024 else
2025 return 512;
2026 case I915_FORMAT_MOD_Y_TILED_CCS:
2027 if (plane == 1)
2028 return 128;
2029 /* fall through */
2030 case I915_FORMAT_MOD_Y_TILED:
2031 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2032 return 128;
2033 else
2034 return 512;
2035 case I915_FORMAT_MOD_Yf_TILED_CCS:
2036 if (plane == 1)
2037 return 128;
2038 /* fall through */
2039 case I915_FORMAT_MOD_Yf_TILED:
2040 switch (cpp) {
2041 case 1:
2042 return 64;
2043 case 2:
2044 case 4:
2045 return 128;
2046 case 8:
2047 case 16:
2048 return 256;
2049 default:
2050 MISSING_CASE(cpp);
2051 return cpp;
2052 }
2053 break;
2054 default:
2055 MISSING_CASE(fb->modifier);
2056 return cpp;
2057 }
2058 }
2059
2060 static unsigned int
2061 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2062 {
2063 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2064 return 1;
2065 else
2066 return intel_tile_size(to_i915(fb->dev)) /
2067 intel_tile_width_bytes(fb, plane);
2068 }
2069
2070 /* Return the tile dimensions in pixel units */
2071 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2072 unsigned int *tile_width,
2073 unsigned int *tile_height)
2074 {
2075 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2076 unsigned int cpp = fb->format->cpp[plane];
2077
2078 *tile_width = tile_width_bytes / cpp;
2079 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2080 }
2081
2082 unsigned int
2083 intel_fb_align_height(const struct drm_framebuffer *fb,
2084 int plane, unsigned int height)
2085 {
2086 unsigned int tile_height = intel_tile_height(fb, plane);
2087
2088 return ALIGN(height, tile_height);
2089 }
2090
2091 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2092 {
2093 unsigned int size = 0;
2094 int i;
2095
2096 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2097 size += rot_info->plane[i].width * rot_info->plane[i].height;
2098
2099 return size;
2100 }
2101
2102 static void
2103 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2104 const struct drm_framebuffer *fb,
2105 unsigned int rotation)
2106 {
2107 view->type = I915_GGTT_VIEW_NORMAL;
2108 if (drm_rotation_90_or_270(rotation)) {
2109 view->type = I915_GGTT_VIEW_ROTATED;
2110 view->rotated = to_intel_framebuffer(fb)->rot_info;
2111 }
2112 }
2113
2114 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2115 {
2116 if (IS_I830(dev_priv))
2117 return 16 * 1024;
2118 else if (IS_I85X(dev_priv))
2119 return 256;
2120 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2121 return 32;
2122 else
2123 return 4 * 1024;
2124 }
2125
2126 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2127 {
2128 if (INTEL_INFO(dev_priv)->gen >= 9)
2129 return 256 * 1024;
2130 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2131 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2132 return 128 * 1024;
2133 else if (INTEL_INFO(dev_priv)->gen >= 4)
2134 return 4 * 1024;
2135 else
2136 return 0;
2137 }
2138
2139 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2140 int plane)
2141 {
2142 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2143
2144 /* AUX_DIST needs only 4K alignment */
2145 if (plane == 1)
2146 return 4096;
2147
2148 switch (fb->modifier) {
2149 case DRM_FORMAT_MOD_LINEAR:
2150 return intel_linear_alignment(dev_priv);
2151 case I915_FORMAT_MOD_X_TILED:
2152 if (INTEL_GEN(dev_priv) >= 9)
2153 return 256 * 1024;
2154 return 0;
2155 case I915_FORMAT_MOD_Y_TILED_CCS:
2156 case I915_FORMAT_MOD_Yf_TILED_CCS:
2157 case I915_FORMAT_MOD_Y_TILED:
2158 case I915_FORMAT_MOD_Yf_TILED:
2159 return 1 * 1024 * 1024;
2160 default:
2161 MISSING_CASE(fb->modifier);
2162 return 0;
2163 }
2164 }
2165
2166 struct i915_vma *
2167 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2168 {
2169 struct drm_device *dev = fb->dev;
2170 struct drm_i915_private *dev_priv = to_i915(dev);
2171 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2172 struct i915_ggtt_view view;
2173 struct i915_vma *vma;
2174 u32 alignment;
2175
2176 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2177
2178 alignment = intel_surf_alignment(fb, 0);
2179
2180 intel_fill_fb_ggtt_view(&view, fb, rotation);
2181
2182 /* Note that the w/a also requires 64 PTE of padding following the
2183 * bo. We currently fill all unused PTE with the shadow page and so
2184 * we should always have valid PTE following the scanout preventing
2185 * the VT-d warning.
2186 */
2187 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2188 alignment = 256 * 1024;
2189
2190 /*
2191 * Global gtt pte registers are special registers which actually forward
2192 * writes to a chunk of system memory. Which means that there is no risk
2193 * that the register values disappear as soon as we call
2194 * intel_runtime_pm_put(), so it is correct to wrap only the
2195 * pin/unpin/fence and not more.
2196 */
2197 intel_runtime_pm_get(dev_priv);
2198
2199 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2200
2201 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2202 if (IS_ERR(vma))
2203 goto err;
2204
2205 if (i915_vma_is_map_and_fenceable(vma)) {
2206 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2207 * fence, whereas 965+ only requires a fence if using
2208 * framebuffer compression. For simplicity, we always, when
2209 * possible, install a fence as the cost is not that onerous.
2210 *
2211 * If we fail to fence the tiled scanout, then either the
2212 * modeset will reject the change (which is highly unlikely as
2213 * the affected systems, all but one, do not have unmappable
2214 * space) or we will not be able to enable full powersaving
2215 * techniques (also likely not to apply due to various limits
2216 * FBC and the like impose on the size of the buffer, which
2217 * presumably we violated anyway with this unmappable buffer).
2218 * Anyway, it is presumably better to stumble onwards with
2219 * something and try to run the system in a "less than optimal"
2220 * mode that matches the user configuration.
2221 */
2222 if (i915_vma_get_fence(vma) == 0)
2223 i915_vma_pin_fence(vma);
2224 }
2225
2226 i915_vma_get(vma);
2227 err:
2228 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2229
2230 intel_runtime_pm_put(dev_priv);
2231 return vma;
2232 }
2233
2234 void intel_unpin_fb_vma(struct i915_vma *vma)
2235 {
2236 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2237
2238 i915_vma_unpin_fence(vma);
2239 i915_gem_object_unpin_from_display_plane(vma);
2240 i915_vma_put(vma);
2241 }
2242
2243 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2244 unsigned int rotation)
2245 {
2246 if (drm_rotation_90_or_270(rotation))
2247 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2248 else
2249 return fb->pitches[plane];
2250 }
2251
2252 /*
2253 * Convert the x/y offsets into a linear offset.
2254 * Only valid with 0/180 degree rotation, which is fine since linear
2255 * offset is only used with linear buffers on pre-hsw and tiled buffers
2256 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2257 */
2258 u32 intel_fb_xy_to_linear(int x, int y,
2259 const struct intel_plane_state *state,
2260 int plane)
2261 {
2262 const struct drm_framebuffer *fb = state->base.fb;
2263 unsigned int cpp = fb->format->cpp[plane];
2264 unsigned int pitch = fb->pitches[plane];
2265
2266 return y * pitch + x * cpp;
2267 }
2268
2269 /*
2270 * Add the x/y offsets derived from fb->offsets[] to the user
2271 * specified plane src x/y offsets. The resulting x/y offsets
2272 * specify the start of scanout from the beginning of the gtt mapping.
2273 */
2274 void intel_add_fb_offsets(int *x, int *y,
2275 const struct intel_plane_state *state,
2276 int plane)
2277
2278 {
2279 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2280 unsigned int rotation = state->base.rotation;
2281
2282 if (drm_rotation_90_or_270(rotation)) {
2283 *x += intel_fb->rotated[plane].x;
2284 *y += intel_fb->rotated[plane].y;
2285 } else {
2286 *x += intel_fb->normal[plane].x;
2287 *y += intel_fb->normal[plane].y;
2288 }
2289 }
2290
2291 static u32 __intel_adjust_tile_offset(int *x, int *y,
2292 unsigned int tile_width,
2293 unsigned int tile_height,
2294 unsigned int tile_size,
2295 unsigned int pitch_tiles,
2296 u32 old_offset,
2297 u32 new_offset)
2298 {
2299 unsigned int pitch_pixels = pitch_tiles * tile_width;
2300 unsigned int tiles;
2301
2302 WARN_ON(old_offset & (tile_size - 1));
2303 WARN_ON(new_offset & (tile_size - 1));
2304 WARN_ON(new_offset > old_offset);
2305
2306 tiles = (old_offset - new_offset) / tile_size;
2307
2308 *y += tiles / pitch_tiles * tile_height;
2309 *x += tiles % pitch_tiles * tile_width;
2310
2311 /* minimize x in case it got needlessly big */
2312 *y += *x / pitch_pixels * tile_height;
2313 *x %= pitch_pixels;
2314
2315 return new_offset;
2316 }
2317
2318 static u32 _intel_adjust_tile_offset(int *x, int *y,
2319 const struct drm_framebuffer *fb, int plane,
2320 unsigned int rotation,
2321 u32 old_offset, u32 new_offset)
2322 {
2323 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2324 unsigned int cpp = fb->format->cpp[plane];
2325 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2326
2327 WARN_ON(new_offset > old_offset);
2328
2329 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2330 unsigned int tile_size, tile_width, tile_height;
2331 unsigned int pitch_tiles;
2332
2333 tile_size = intel_tile_size(dev_priv);
2334 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2335
2336 if (drm_rotation_90_or_270(rotation)) {
2337 pitch_tiles = pitch / tile_height;
2338 swap(tile_width, tile_height);
2339 } else {
2340 pitch_tiles = pitch / (tile_width * cpp);
2341 }
2342
2343 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2344 tile_size, pitch_tiles,
2345 old_offset, new_offset);
2346 } else {
2347 old_offset += *y * pitch + *x * cpp;
2348
2349 *y = (old_offset - new_offset) / pitch;
2350 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2351 }
2352
2353 return new_offset;
2354 }
2355
2356 /*
2357 * Adjust the tile offset by moving the difference into
2358 * the x/y offsets.
2359 */
2360 static u32 intel_adjust_tile_offset(int *x, int *y,
2361 const struct intel_plane_state *state, int plane,
2362 u32 old_offset, u32 new_offset)
2363 {
2364 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2365 state->base.rotation,
2366 old_offset, new_offset);
2367 }
2368
2369 /*
2370 * Computes the linear offset to the base tile and adjusts
2371 * x, y. bytes per pixel is assumed to be a power-of-two.
2372 *
2373 * In the 90/270 rotated case, x and y are assumed
2374 * to be already rotated to match the rotated GTT view, and
2375 * pitch is the tile_height aligned framebuffer height.
2376 *
2377 * This function is used when computing the derived information
2378 * under intel_framebuffer, so using any of that information
2379 * here is not allowed. Anything under drm_framebuffer can be
2380 * used. This is why the user has to pass in the pitch since it
2381 * is specified in the rotated orientation.
2382 */
2383 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2384 int *x, int *y,
2385 const struct drm_framebuffer *fb, int plane,
2386 unsigned int pitch,
2387 unsigned int rotation,
2388 u32 alignment)
2389 {
2390 uint64_t fb_modifier = fb->modifier;
2391 unsigned int cpp = fb->format->cpp[plane];
2392 u32 offset, offset_aligned;
2393
2394 if (alignment)
2395 alignment--;
2396
2397 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2398 unsigned int tile_size, tile_width, tile_height;
2399 unsigned int tile_rows, tiles, pitch_tiles;
2400
2401 tile_size = intel_tile_size(dev_priv);
2402 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2403
2404 if (drm_rotation_90_or_270(rotation)) {
2405 pitch_tiles = pitch / tile_height;
2406 swap(tile_width, tile_height);
2407 } else {
2408 pitch_tiles = pitch / (tile_width * cpp);
2409 }
2410
2411 tile_rows = *y / tile_height;
2412 *y %= tile_height;
2413
2414 tiles = *x / tile_width;
2415 *x %= tile_width;
2416
2417 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2418 offset_aligned = offset & ~alignment;
2419
2420 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2421 tile_size, pitch_tiles,
2422 offset, offset_aligned);
2423 } else {
2424 offset = *y * pitch + *x * cpp;
2425 offset_aligned = offset & ~alignment;
2426
2427 *y = (offset & alignment) / pitch;
2428 *x = ((offset & alignment) - *y * pitch) / cpp;
2429 }
2430
2431 return offset_aligned;
2432 }
2433
2434 u32 intel_compute_tile_offset(int *x, int *y,
2435 const struct intel_plane_state *state,
2436 int plane)
2437 {
2438 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2439 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2440 const struct drm_framebuffer *fb = state->base.fb;
2441 unsigned int rotation = state->base.rotation;
2442 int pitch = intel_fb_pitch(fb, plane, rotation);
2443 u32 alignment;
2444
2445 if (intel_plane->id == PLANE_CURSOR)
2446 alignment = intel_cursor_alignment(dev_priv);
2447 else
2448 alignment = intel_surf_alignment(fb, plane);
2449
2450 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2451 rotation, alignment);
2452 }
2453
2454 /* Convert the fb->offset[] into x/y offsets */
2455 static int intel_fb_offset_to_xy(int *x, int *y,
2456 const struct drm_framebuffer *fb, int plane)
2457 {
2458 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2459
2460 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2461 fb->offsets[plane] % intel_tile_size(dev_priv))
2462 return -EINVAL;
2463
2464 *x = 0;
2465 *y = 0;
2466
2467 _intel_adjust_tile_offset(x, y,
2468 fb, plane, DRM_MODE_ROTATE_0,
2469 fb->offsets[plane], 0);
2470
2471 return 0;
2472 }
2473
2474 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2475 {
2476 switch (fb_modifier) {
2477 case I915_FORMAT_MOD_X_TILED:
2478 return I915_TILING_X;
2479 case I915_FORMAT_MOD_Y_TILED:
2480 case I915_FORMAT_MOD_Y_TILED_CCS:
2481 return I915_TILING_Y;
2482 default:
2483 return I915_TILING_NONE;
2484 }
2485 }
2486
2487 static const struct drm_format_info ccs_formats[] = {
2488 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2489 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2490 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2491 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2492 };
2493
2494 static const struct drm_format_info *
2495 lookup_format_info(const struct drm_format_info formats[],
2496 int num_formats, u32 format)
2497 {
2498 int i;
2499
2500 for (i = 0; i < num_formats; i++) {
2501 if (formats[i].format == format)
2502 return &formats[i];
2503 }
2504
2505 return NULL;
2506 }
2507
2508 static const struct drm_format_info *
2509 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2510 {
2511 switch (cmd->modifier[0]) {
2512 case I915_FORMAT_MOD_Y_TILED_CCS:
2513 case I915_FORMAT_MOD_Yf_TILED_CCS:
2514 return lookup_format_info(ccs_formats,
2515 ARRAY_SIZE(ccs_formats),
2516 cmd->pixel_format);
2517 default:
2518 return NULL;
2519 }
2520 }
2521
2522 static int
2523 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2524 struct drm_framebuffer *fb)
2525 {
2526 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2527 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2528 u32 gtt_offset_rotated = 0;
2529 unsigned int max_size = 0;
2530 int i, num_planes = fb->format->num_planes;
2531 unsigned int tile_size = intel_tile_size(dev_priv);
2532
2533 for (i = 0; i < num_planes; i++) {
2534 unsigned int width, height;
2535 unsigned int cpp, size;
2536 u32 offset;
2537 int x, y;
2538 int ret;
2539
2540 cpp = fb->format->cpp[i];
2541 width = drm_framebuffer_plane_width(fb->width, fb, i);
2542 height = drm_framebuffer_plane_height(fb->height, fb, i);
2543
2544 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2545 if (ret) {
2546 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2547 i, fb->offsets[i]);
2548 return ret;
2549 }
2550
2551 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2552 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2553 int hsub = fb->format->hsub;
2554 int vsub = fb->format->vsub;
2555 int tile_width, tile_height;
2556 int main_x, main_y;
2557 int ccs_x, ccs_y;
2558
2559 intel_tile_dims(fb, i, &tile_width, &tile_height);
2560 tile_width *= hsub;
2561 tile_height *= vsub;
2562
2563 ccs_x = (x * hsub) % tile_width;
2564 ccs_y = (y * vsub) % tile_height;
2565 main_x = intel_fb->normal[0].x % tile_width;
2566 main_y = intel_fb->normal[0].y % tile_height;
2567
2568 /*
2569 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2570 * x/y offsets must match between CCS and the main surface.
2571 */
2572 if (main_x != ccs_x || main_y != ccs_y) {
2573 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2574 main_x, main_y,
2575 ccs_x, ccs_y,
2576 intel_fb->normal[0].x,
2577 intel_fb->normal[0].y,
2578 x, y);
2579 return -EINVAL;
2580 }
2581 }
2582
2583 /*
2584 * The fence (if used) is aligned to the start of the object
2585 * so having the framebuffer wrap around across the edge of the
2586 * fenced region doesn't really work. We have no API to configure
2587 * the fence start offset within the object (nor could we probably
2588 * on gen2/3). So it's just easier if we just require that the
2589 * fb layout agrees with the fence layout. We already check that the
2590 * fb stride matches the fence stride elsewhere.
2591 */
2592 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2593 (x + width) * cpp > fb->pitches[i]) {
2594 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2595 i, fb->offsets[i]);
2596 return -EINVAL;
2597 }
2598
2599 /*
2600 * First pixel of the framebuffer from
2601 * the start of the normal gtt mapping.
2602 */
2603 intel_fb->normal[i].x = x;
2604 intel_fb->normal[i].y = y;
2605
2606 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2607 fb, i, fb->pitches[i],
2608 DRM_MODE_ROTATE_0, tile_size);
2609 offset /= tile_size;
2610
2611 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2612 unsigned int tile_width, tile_height;
2613 unsigned int pitch_tiles;
2614 struct drm_rect r;
2615
2616 intel_tile_dims(fb, i, &tile_width, &tile_height);
2617
2618 rot_info->plane[i].offset = offset;
2619 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2620 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2621 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2622
2623 intel_fb->rotated[i].pitch =
2624 rot_info->plane[i].height * tile_height;
2625
2626 /* how many tiles does this plane need */
2627 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2628 /*
2629 * If the plane isn't horizontally tile aligned,
2630 * we need one more tile.
2631 */
2632 if (x != 0)
2633 size++;
2634
2635 /* rotate the x/y offsets to match the GTT view */
2636 r.x1 = x;
2637 r.y1 = y;
2638 r.x2 = x + width;
2639 r.y2 = y + height;
2640 drm_rect_rotate(&r,
2641 rot_info->plane[i].width * tile_width,
2642 rot_info->plane[i].height * tile_height,
2643 DRM_MODE_ROTATE_270);
2644 x = r.x1;
2645 y = r.y1;
2646
2647 /* rotate the tile dimensions to match the GTT view */
2648 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2649 swap(tile_width, tile_height);
2650
2651 /*
2652 * We only keep the x/y offsets, so push all of the
2653 * gtt offset into the x/y offsets.
2654 */
2655 __intel_adjust_tile_offset(&x, &y,
2656 tile_width, tile_height,
2657 tile_size, pitch_tiles,
2658 gtt_offset_rotated * tile_size, 0);
2659
2660 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2661
2662 /*
2663 * First pixel of the framebuffer from
2664 * the start of the rotated gtt mapping.
2665 */
2666 intel_fb->rotated[i].x = x;
2667 intel_fb->rotated[i].y = y;
2668 } else {
2669 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2670 x * cpp, tile_size);
2671 }
2672
2673 /* how many tiles in total needed in the bo */
2674 max_size = max(max_size, offset + size);
2675 }
2676
2677 if (max_size * tile_size > intel_fb->obj->base.size) {
2678 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2679 max_size * tile_size, intel_fb->obj->base.size);
2680 return -EINVAL;
2681 }
2682
2683 return 0;
2684 }
2685
2686 static int i9xx_format_to_fourcc(int format)
2687 {
2688 switch (format) {
2689 case DISPPLANE_8BPP:
2690 return DRM_FORMAT_C8;
2691 case DISPPLANE_BGRX555:
2692 return DRM_FORMAT_XRGB1555;
2693 case DISPPLANE_BGRX565:
2694 return DRM_FORMAT_RGB565;
2695 default:
2696 case DISPPLANE_BGRX888:
2697 return DRM_FORMAT_XRGB8888;
2698 case DISPPLANE_RGBX888:
2699 return DRM_FORMAT_XBGR8888;
2700 case DISPPLANE_BGRX101010:
2701 return DRM_FORMAT_XRGB2101010;
2702 case DISPPLANE_RGBX101010:
2703 return DRM_FORMAT_XBGR2101010;
2704 }
2705 }
2706
2707 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2708 {
2709 switch (format) {
2710 case PLANE_CTL_FORMAT_RGB_565:
2711 return DRM_FORMAT_RGB565;
2712 default:
2713 case PLANE_CTL_FORMAT_XRGB_8888:
2714 if (rgb_order) {
2715 if (alpha)
2716 return DRM_FORMAT_ABGR8888;
2717 else
2718 return DRM_FORMAT_XBGR8888;
2719 } else {
2720 if (alpha)
2721 return DRM_FORMAT_ARGB8888;
2722 else
2723 return DRM_FORMAT_XRGB8888;
2724 }
2725 case PLANE_CTL_FORMAT_XRGB_2101010:
2726 if (rgb_order)
2727 return DRM_FORMAT_XBGR2101010;
2728 else
2729 return DRM_FORMAT_XRGB2101010;
2730 }
2731 }
2732
2733 static bool
2734 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2735 struct intel_initial_plane_config *plane_config)
2736 {
2737 struct drm_device *dev = crtc->base.dev;
2738 struct drm_i915_private *dev_priv = to_i915(dev);
2739 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2740 struct drm_i915_gem_object *obj = NULL;
2741 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2742 struct drm_framebuffer *fb = &plane_config->fb->base;
2743 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2744 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2745 PAGE_SIZE);
2746
2747 size_aligned -= base_aligned;
2748
2749 if (plane_config->size == 0)
2750 return false;
2751
2752 /* If the FB is too big, just don't use it since fbdev is not very
2753 * important and we should probably use that space with FBC or other
2754 * features. */
2755 if (size_aligned * 2 > ggtt->stolen_usable_size)
2756 return false;
2757
2758 mutex_lock(&dev->struct_mutex);
2759 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2760 base_aligned,
2761 base_aligned,
2762 size_aligned);
2763 mutex_unlock(&dev->struct_mutex);
2764 if (!obj)
2765 return false;
2766
2767 if (plane_config->tiling == I915_TILING_X)
2768 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2769
2770 mode_cmd.pixel_format = fb->format->format;
2771 mode_cmd.width = fb->width;
2772 mode_cmd.height = fb->height;
2773 mode_cmd.pitches[0] = fb->pitches[0];
2774 mode_cmd.modifier[0] = fb->modifier;
2775 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2776
2777 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2778 DRM_DEBUG_KMS("intel fb init failed\n");
2779 goto out_unref_obj;
2780 }
2781
2782
2783 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2784 return true;
2785
2786 out_unref_obj:
2787 i915_gem_object_put(obj);
2788 return false;
2789 }
2790
2791 static void
2792 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2793 struct intel_plane_state *plane_state,
2794 bool visible)
2795 {
2796 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2797
2798 plane_state->base.visible = visible;
2799
2800 /* FIXME pre-g4x don't work like this */
2801 if (visible) {
2802 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2803 crtc_state->active_planes |= BIT(plane->id);
2804 } else {
2805 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2806 crtc_state->active_planes &= ~BIT(plane->id);
2807 }
2808
2809 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2810 crtc_state->base.crtc->name,
2811 crtc_state->active_planes);
2812 }
2813
2814 static void
2815 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2816 struct intel_initial_plane_config *plane_config)
2817 {
2818 struct drm_device *dev = intel_crtc->base.dev;
2819 struct drm_i915_private *dev_priv = to_i915(dev);
2820 struct drm_crtc *c;
2821 struct drm_i915_gem_object *obj;
2822 struct drm_plane *primary = intel_crtc->base.primary;
2823 struct drm_plane_state *plane_state = primary->state;
2824 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2825 struct intel_plane *intel_plane = to_intel_plane(primary);
2826 struct intel_plane_state *intel_state =
2827 to_intel_plane_state(plane_state);
2828 struct drm_framebuffer *fb;
2829
2830 if (!plane_config->fb)
2831 return;
2832
2833 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2834 fb = &plane_config->fb->base;
2835 goto valid_fb;
2836 }
2837
2838 kfree(plane_config->fb);
2839
2840 /*
2841 * Failed to alloc the obj, check to see if we should share
2842 * an fb with another CRTC instead
2843 */
2844 for_each_crtc(dev, c) {
2845 struct intel_plane_state *state;
2846
2847 if (c == &intel_crtc->base)
2848 continue;
2849
2850 if (!to_intel_crtc(c)->active)
2851 continue;
2852
2853 state = to_intel_plane_state(c->primary->state);
2854 if (!state->vma)
2855 continue;
2856
2857 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2858 fb = c->primary->fb;
2859 drm_framebuffer_reference(fb);
2860 goto valid_fb;
2861 }
2862 }
2863
2864 /*
2865 * We've failed to reconstruct the BIOS FB. Current display state
2866 * indicates that the primary plane is visible, but has a NULL FB,
2867 * which will lead to problems later if we don't fix it up. The
2868 * simplest solution is to just disable the primary plane now and
2869 * pretend the BIOS never had it enabled.
2870 */
2871 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2872 to_intel_plane_state(plane_state),
2873 false);
2874 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2875 trace_intel_disable_plane(primary, intel_crtc);
2876 intel_plane->disable_plane(intel_plane, intel_crtc);
2877
2878 return;
2879
2880 valid_fb:
2881 mutex_lock(&dev->struct_mutex);
2882 intel_state->vma =
2883 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2884 mutex_unlock(&dev->struct_mutex);
2885 if (IS_ERR(intel_state->vma)) {
2886 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2887 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2888
2889 intel_state->vma = NULL;
2890 drm_framebuffer_unreference(fb);
2891 return;
2892 }
2893
2894 plane_state->src_x = 0;
2895 plane_state->src_y = 0;
2896 plane_state->src_w = fb->width << 16;
2897 plane_state->src_h = fb->height << 16;
2898
2899 plane_state->crtc_x = 0;
2900 plane_state->crtc_y = 0;
2901 plane_state->crtc_w = fb->width;
2902 plane_state->crtc_h = fb->height;
2903
2904 intel_state->base.src = drm_plane_state_src(plane_state);
2905 intel_state->base.dst = drm_plane_state_dest(plane_state);
2906
2907 obj = intel_fb_obj(fb);
2908 if (i915_gem_object_is_tiled(obj))
2909 dev_priv->preserve_bios_swizzle = true;
2910
2911 drm_framebuffer_reference(fb);
2912 primary->fb = primary->state->fb = fb;
2913 primary->crtc = primary->state->crtc = &intel_crtc->base;
2914
2915 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2916 to_intel_plane_state(plane_state),
2917 true);
2918
2919 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2920 &obj->frontbuffer_bits);
2921 }
2922
2923 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2924 unsigned int rotation)
2925 {
2926 int cpp = fb->format->cpp[plane];
2927
2928 switch (fb->modifier) {
2929 case DRM_FORMAT_MOD_LINEAR:
2930 case I915_FORMAT_MOD_X_TILED:
2931 switch (cpp) {
2932 case 8:
2933 return 4096;
2934 case 4:
2935 case 2:
2936 case 1:
2937 return 8192;
2938 default:
2939 MISSING_CASE(cpp);
2940 break;
2941 }
2942 break;
2943 case I915_FORMAT_MOD_Y_TILED_CCS:
2944 case I915_FORMAT_MOD_Yf_TILED_CCS:
2945 /* FIXME AUX plane? */
2946 case I915_FORMAT_MOD_Y_TILED:
2947 case I915_FORMAT_MOD_Yf_TILED:
2948 switch (cpp) {
2949 case 8:
2950 return 2048;
2951 case 4:
2952 return 4096;
2953 case 2:
2954 case 1:
2955 return 8192;
2956 default:
2957 MISSING_CASE(cpp);
2958 break;
2959 }
2960 break;
2961 default:
2962 MISSING_CASE(fb->modifier);
2963 }
2964
2965 return 2048;
2966 }
2967
2968 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2969 int main_x, int main_y, u32 main_offset)
2970 {
2971 const struct drm_framebuffer *fb = plane_state->base.fb;
2972 int hsub = fb->format->hsub;
2973 int vsub = fb->format->vsub;
2974 int aux_x = plane_state->aux.x;
2975 int aux_y = plane_state->aux.y;
2976 u32 aux_offset = plane_state->aux.offset;
2977 u32 alignment = intel_surf_alignment(fb, 1);
2978
2979 while (aux_offset >= main_offset && aux_y <= main_y) {
2980 int x, y;
2981
2982 if (aux_x == main_x && aux_y == main_y)
2983 break;
2984
2985 if (aux_offset == 0)
2986 break;
2987
2988 x = aux_x / hsub;
2989 y = aux_y / vsub;
2990 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2991 aux_offset, aux_offset - alignment);
2992 aux_x = x * hsub + aux_x % hsub;
2993 aux_y = y * vsub + aux_y % vsub;
2994 }
2995
2996 if (aux_x != main_x || aux_y != main_y)
2997 return false;
2998
2999 plane_state->aux.offset = aux_offset;
3000 plane_state->aux.x = aux_x;
3001 plane_state->aux.y = aux_y;
3002
3003 return true;
3004 }
3005
3006 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3007 {
3008 const struct drm_framebuffer *fb = plane_state->base.fb;
3009 unsigned int rotation = plane_state->base.rotation;
3010 int x = plane_state->base.src.x1 >> 16;
3011 int y = plane_state->base.src.y1 >> 16;
3012 int w = drm_rect_width(&plane_state->base.src) >> 16;
3013 int h = drm_rect_height(&plane_state->base.src) >> 16;
3014 int max_width = skl_max_plane_width(fb, 0, rotation);
3015 int max_height = 4096;
3016 u32 alignment, offset, aux_offset = plane_state->aux.offset;
3017
3018 if (w > max_width || h > max_height) {
3019 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3020 w, h, max_width, max_height);
3021 return -EINVAL;
3022 }
3023
3024 intel_add_fb_offsets(&x, &y, plane_state, 0);
3025 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3026 alignment = intel_surf_alignment(fb, 0);
3027
3028 /*
3029 * AUX surface offset is specified as the distance from the
3030 * main surface offset, and it must be non-negative. Make
3031 * sure that is what we will get.
3032 */
3033 if (offset > aux_offset)
3034 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3035 offset, aux_offset & ~(alignment - 1));
3036
3037 /*
3038 * When using an X-tiled surface, the plane blows up
3039 * if the x offset + width exceed the stride.
3040 *
3041 * TODO: linear and Y-tiled seem fine, Yf untested,
3042 */
3043 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3044 int cpp = fb->format->cpp[0];
3045
3046 while ((x + w) * cpp > fb->pitches[0]) {
3047 if (offset == 0) {
3048 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3049 return -EINVAL;
3050 }
3051
3052 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3053 offset, offset - alignment);
3054 }
3055 }
3056
3057 /*
3058 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3059 * they match with the main surface x/y offsets.
3060 */
3061 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3062 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3063 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3064 if (offset == 0)
3065 break;
3066
3067 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3068 offset, offset - alignment);
3069 }
3070
3071 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3072 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3073 return -EINVAL;
3074 }
3075 }
3076
3077 plane_state->main.offset = offset;
3078 plane_state->main.x = x;
3079 plane_state->main.y = y;
3080
3081 return 0;
3082 }
3083
3084 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3085 {
3086 const struct drm_framebuffer *fb = plane_state->base.fb;
3087 unsigned int rotation = plane_state->base.rotation;
3088 int max_width = skl_max_plane_width(fb, 1, rotation);
3089 int max_height = 4096;
3090 int x = plane_state->base.src.x1 >> 17;
3091 int y = plane_state->base.src.y1 >> 17;
3092 int w = drm_rect_width(&plane_state->base.src) >> 17;
3093 int h = drm_rect_height(&plane_state->base.src) >> 17;
3094 u32 offset;
3095
3096 intel_add_fb_offsets(&x, &y, plane_state, 1);
3097 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3098
3099 /* FIXME not quite sure how/if these apply to the chroma plane */
3100 if (w > max_width || h > max_height) {
3101 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3102 w, h, max_width, max_height);
3103 return -EINVAL;
3104 }
3105
3106 plane_state->aux.offset = offset;
3107 plane_state->aux.x = x;
3108 plane_state->aux.y = y;
3109
3110 return 0;
3111 }
3112
3113 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3114 {
3115 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3116 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3117 const struct drm_framebuffer *fb = plane_state->base.fb;
3118 int src_x = plane_state->base.src.x1 >> 16;
3119 int src_y = plane_state->base.src.y1 >> 16;
3120 int hsub = fb->format->hsub;
3121 int vsub = fb->format->vsub;
3122 int x = src_x / hsub;
3123 int y = src_y / vsub;
3124 u32 offset;
3125
3126 switch (plane->id) {
3127 case PLANE_PRIMARY:
3128 case PLANE_SPRITE0:
3129 break;
3130 default:
3131 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3132 return -EINVAL;
3133 }
3134
3135 if (crtc->pipe == PIPE_C) {
3136 DRM_DEBUG_KMS("No RC support on pipe C\n");
3137 return -EINVAL;
3138 }
3139
3140 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3141 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3142 plane_state->base.rotation);
3143 return -EINVAL;
3144 }
3145
3146 intel_add_fb_offsets(&x, &y, plane_state, 1);
3147 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3148
3149 plane_state->aux.offset = offset;
3150 plane_state->aux.x = x * hsub + src_x % hsub;
3151 plane_state->aux.y = y * vsub + src_y % vsub;
3152
3153 return 0;
3154 }
3155
3156 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3157 {
3158 const struct drm_framebuffer *fb = plane_state->base.fb;
3159 unsigned int rotation = plane_state->base.rotation;
3160 int ret;
3161
3162 if (!plane_state->base.visible)
3163 return 0;
3164
3165 /* Rotate src coordinates to match rotated GTT view */
3166 if (drm_rotation_90_or_270(rotation))
3167 drm_rect_rotate(&plane_state->base.src,
3168 fb->width << 16, fb->height << 16,
3169 DRM_MODE_ROTATE_270);
3170
3171 /*
3172 * Handle the AUX surface first since
3173 * the main surface setup depends on it.
3174 */
3175 if (fb->format->format == DRM_FORMAT_NV12) {
3176 ret = skl_check_nv12_aux_surface(plane_state);
3177 if (ret)
3178 return ret;
3179 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3180 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3181 ret = skl_check_ccs_aux_surface(plane_state);
3182 if (ret)
3183 return ret;
3184 } else {
3185 plane_state->aux.offset = ~0xfff;
3186 plane_state->aux.x = 0;
3187 plane_state->aux.y = 0;
3188 }
3189
3190 ret = skl_check_main_surface(plane_state);
3191 if (ret)
3192 return ret;
3193
3194 return 0;
3195 }
3196
3197 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3198 const struct intel_plane_state *plane_state)
3199 {
3200 struct drm_i915_private *dev_priv =
3201 to_i915(plane_state->base.plane->dev);
3202 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3203 const struct drm_framebuffer *fb = plane_state->base.fb;
3204 unsigned int rotation = plane_state->base.rotation;
3205 u32 dspcntr;
3206
3207 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3208
3209 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3210 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3211 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3212
3213 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3214 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3215
3216 if (INTEL_GEN(dev_priv) < 4)
3217 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3218
3219 switch (fb->format->format) {
3220 case DRM_FORMAT_C8:
3221 dspcntr |= DISPPLANE_8BPP;
3222 break;
3223 case DRM_FORMAT_XRGB1555:
3224 dspcntr |= DISPPLANE_BGRX555;
3225 break;
3226 case DRM_FORMAT_RGB565:
3227 dspcntr |= DISPPLANE_BGRX565;
3228 break;
3229 case DRM_FORMAT_XRGB8888:
3230 dspcntr |= DISPPLANE_BGRX888;
3231 break;
3232 case DRM_FORMAT_XBGR8888:
3233 dspcntr |= DISPPLANE_RGBX888;
3234 break;
3235 case DRM_FORMAT_XRGB2101010:
3236 dspcntr |= DISPPLANE_BGRX101010;
3237 break;
3238 case DRM_FORMAT_XBGR2101010:
3239 dspcntr |= DISPPLANE_RGBX101010;
3240 break;
3241 default:
3242 MISSING_CASE(fb->format->format);
3243 return 0;
3244 }
3245
3246 if (INTEL_GEN(dev_priv) >= 4 &&
3247 fb->modifier == I915_FORMAT_MOD_X_TILED)
3248 dspcntr |= DISPPLANE_TILED;
3249
3250 if (rotation & DRM_MODE_ROTATE_180)
3251 dspcntr |= DISPPLANE_ROTATE_180;
3252
3253 if (rotation & DRM_MODE_REFLECT_X)
3254 dspcntr |= DISPPLANE_MIRROR;
3255
3256 return dspcntr;
3257 }
3258
3259 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3260 {
3261 struct drm_i915_private *dev_priv =
3262 to_i915(plane_state->base.plane->dev);
3263 int src_x = plane_state->base.src.x1 >> 16;
3264 int src_y = plane_state->base.src.y1 >> 16;
3265 u32 offset;
3266
3267 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3268
3269 if (INTEL_GEN(dev_priv) >= 4)
3270 offset = intel_compute_tile_offset(&src_x, &src_y,
3271 plane_state, 0);
3272 else
3273 offset = 0;
3274
3275 /* HSW/BDW do this automagically in hardware */
3276 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3277 unsigned int rotation = plane_state->base.rotation;
3278 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3279 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3280
3281 if (rotation & DRM_MODE_ROTATE_180) {
3282 src_x += src_w - 1;
3283 src_y += src_h - 1;
3284 } else if (rotation & DRM_MODE_REFLECT_X) {
3285 src_x += src_w - 1;
3286 }
3287 }
3288
3289 plane_state->main.offset = offset;
3290 plane_state->main.x = src_x;
3291 plane_state->main.y = src_y;
3292
3293 return 0;
3294 }
3295
3296 static void i9xx_update_primary_plane(struct intel_plane *primary,
3297 const struct intel_crtc_state *crtc_state,
3298 const struct intel_plane_state *plane_state)
3299 {
3300 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3301 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3302 const struct drm_framebuffer *fb = plane_state->base.fb;
3303 enum plane plane = primary->plane;
3304 u32 linear_offset;
3305 u32 dspcntr = plane_state->ctl;
3306 i915_reg_t reg = DSPCNTR(plane);
3307 int x = plane_state->main.x;
3308 int y = plane_state->main.y;
3309 unsigned long irqflags;
3310
3311 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3312
3313 if (INTEL_GEN(dev_priv) >= 4)
3314 crtc->dspaddr_offset = plane_state->main.offset;
3315 else
3316 crtc->dspaddr_offset = linear_offset;
3317
3318 crtc->adjusted_x = x;
3319 crtc->adjusted_y = y;
3320
3321 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3322
3323 if (INTEL_GEN(dev_priv) < 4) {
3324 /* pipesrc and dspsize control the size that is scaled from,
3325 * which should always be the user's requested size.
3326 */
3327 I915_WRITE_FW(DSPSIZE(plane),
3328 ((crtc_state->pipe_src_h - 1) << 16) |
3329 (crtc_state->pipe_src_w - 1));
3330 I915_WRITE_FW(DSPPOS(plane), 0);
3331 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3332 I915_WRITE_FW(PRIMSIZE(plane),
3333 ((crtc_state->pipe_src_h - 1) << 16) |
3334 (crtc_state->pipe_src_w - 1));
3335 I915_WRITE_FW(PRIMPOS(plane), 0);
3336 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3337 }
3338
3339 I915_WRITE_FW(reg, dspcntr);
3340
3341 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3342 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3343 I915_WRITE_FW(DSPSURF(plane),
3344 intel_plane_ggtt_offset(plane_state) +
3345 crtc->dspaddr_offset);
3346 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3347 } else if (INTEL_GEN(dev_priv) >= 4) {
3348 I915_WRITE_FW(DSPSURF(plane),
3349 intel_plane_ggtt_offset(plane_state) +
3350 crtc->dspaddr_offset);
3351 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3352 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3353 } else {
3354 I915_WRITE_FW(DSPADDR(plane),
3355 intel_plane_ggtt_offset(plane_state) +
3356 crtc->dspaddr_offset);
3357 }
3358 POSTING_READ_FW(reg);
3359
3360 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3361 }
3362
3363 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3364 struct intel_crtc *crtc)
3365 {
3366 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3367 enum plane plane = primary->plane;
3368 unsigned long irqflags;
3369
3370 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3371
3372 I915_WRITE_FW(DSPCNTR(plane), 0);
3373 if (INTEL_INFO(dev_priv)->gen >= 4)
3374 I915_WRITE_FW(DSPSURF(plane), 0);
3375 else
3376 I915_WRITE_FW(DSPADDR(plane), 0);
3377 POSTING_READ_FW(DSPCNTR(plane));
3378
3379 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3380 }
3381
3382 static u32
3383 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3384 {
3385 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3386 return 64;
3387 else
3388 return intel_tile_width_bytes(fb, plane);
3389 }
3390
3391 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3392 {
3393 struct drm_device *dev = intel_crtc->base.dev;
3394 struct drm_i915_private *dev_priv = to_i915(dev);
3395
3396 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3397 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3398 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3399 }
3400
3401 /*
3402 * This function detaches (aka. unbinds) unused scalers in hardware
3403 */
3404 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3405 {
3406 struct intel_crtc_scaler_state *scaler_state;
3407 int i;
3408
3409 scaler_state = &intel_crtc->config->scaler_state;
3410
3411 /* loop through and disable scalers that aren't in use */
3412 for (i = 0; i < intel_crtc->num_scalers; i++) {
3413 if (!scaler_state->scalers[i].in_use)
3414 skl_detach_scaler(intel_crtc, i);
3415 }
3416 }
3417
3418 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3419 unsigned int rotation)
3420 {
3421 u32 stride;
3422
3423 if (plane >= fb->format->num_planes)
3424 return 0;
3425
3426 stride = intel_fb_pitch(fb, plane, rotation);
3427
3428 /*
3429 * The stride is either expressed as a multiple of 64 bytes chunks for
3430 * linear buffers or in number of tiles for tiled buffers.
3431 */
3432 if (drm_rotation_90_or_270(rotation))
3433 stride /= intel_tile_height(fb, plane);
3434 else
3435 stride /= intel_fb_stride_alignment(fb, plane);
3436
3437 return stride;
3438 }
3439
3440 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3441 {
3442 switch (pixel_format) {
3443 case DRM_FORMAT_C8:
3444 return PLANE_CTL_FORMAT_INDEXED;
3445 case DRM_FORMAT_RGB565:
3446 return PLANE_CTL_FORMAT_RGB_565;
3447 case DRM_FORMAT_XBGR8888:
3448 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3449 case DRM_FORMAT_XRGB8888:
3450 return PLANE_CTL_FORMAT_XRGB_8888;
3451 /*
3452 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3453 * to be already pre-multiplied. We need to add a knob (or a different
3454 * DRM_FORMAT) for user-space to configure that.
3455 */
3456 case DRM_FORMAT_ABGR8888:
3457 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3458 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3459 case DRM_FORMAT_ARGB8888:
3460 return PLANE_CTL_FORMAT_XRGB_8888 |
3461 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3462 case DRM_FORMAT_XRGB2101010:
3463 return PLANE_CTL_FORMAT_XRGB_2101010;
3464 case DRM_FORMAT_XBGR2101010:
3465 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3466 case DRM_FORMAT_YUYV:
3467 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3468 case DRM_FORMAT_YVYU:
3469 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3470 case DRM_FORMAT_UYVY:
3471 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3472 case DRM_FORMAT_VYUY:
3473 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3474 default:
3475 MISSING_CASE(pixel_format);
3476 }
3477
3478 return 0;
3479 }
3480
3481 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3482 {
3483 switch (fb_modifier) {
3484 case DRM_FORMAT_MOD_LINEAR:
3485 break;
3486 case I915_FORMAT_MOD_X_TILED:
3487 return PLANE_CTL_TILED_X;
3488 case I915_FORMAT_MOD_Y_TILED:
3489 return PLANE_CTL_TILED_Y;
3490 case I915_FORMAT_MOD_Y_TILED_CCS:
3491 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3492 case I915_FORMAT_MOD_Yf_TILED:
3493 return PLANE_CTL_TILED_YF;
3494 case I915_FORMAT_MOD_Yf_TILED_CCS:
3495 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3496 default:
3497 MISSING_CASE(fb_modifier);
3498 }
3499
3500 return 0;
3501 }
3502
3503 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3504 {
3505 switch (rotation) {
3506 case DRM_MODE_ROTATE_0:
3507 break;
3508 /*
3509 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3510 * while i915 HW rotation is clockwise, thats why this swapping.
3511 */
3512 case DRM_MODE_ROTATE_90:
3513 return PLANE_CTL_ROTATE_270;
3514 case DRM_MODE_ROTATE_180:
3515 return PLANE_CTL_ROTATE_180;
3516 case DRM_MODE_ROTATE_270:
3517 return PLANE_CTL_ROTATE_90;
3518 default:
3519 MISSING_CASE(rotation);
3520 }
3521
3522 return 0;
3523 }
3524
3525 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3526 const struct intel_plane_state *plane_state)
3527 {
3528 struct drm_i915_private *dev_priv =
3529 to_i915(plane_state->base.plane->dev);
3530 const struct drm_framebuffer *fb = plane_state->base.fb;
3531 unsigned int rotation = plane_state->base.rotation;
3532 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3533 u32 plane_ctl;
3534
3535 plane_ctl = PLANE_CTL_ENABLE;
3536
3537 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3538 plane_ctl |=
3539 PLANE_CTL_PIPE_GAMMA_ENABLE |
3540 PLANE_CTL_PIPE_CSC_ENABLE |
3541 PLANE_CTL_PLANE_GAMMA_DISABLE;
3542 }
3543
3544 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3545 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3546 plane_ctl |= skl_plane_ctl_rotation(rotation);
3547
3548 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3549 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3550 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3551 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3552
3553 return plane_ctl;
3554 }
3555
3556 static void skylake_update_primary_plane(struct intel_plane *plane,
3557 const struct intel_crtc_state *crtc_state,
3558 const struct intel_plane_state *plane_state)
3559 {
3560 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3561 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3562 const struct drm_framebuffer *fb = plane_state->base.fb;
3563 enum plane_id plane_id = plane->id;
3564 enum pipe pipe = plane->pipe;
3565 u32 plane_ctl = plane_state->ctl;
3566 unsigned int rotation = plane_state->base.rotation;
3567 u32 stride = skl_plane_stride(fb, 0, rotation);
3568 u32 aux_stride = skl_plane_stride(fb, 1, rotation);
3569 u32 surf_addr = plane_state->main.offset;
3570 int scaler_id = plane_state->scaler_id;
3571 int src_x = plane_state->main.x;
3572 int src_y = plane_state->main.y;
3573 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3574 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3575 int dst_x = plane_state->base.dst.x1;
3576 int dst_y = plane_state->base.dst.y1;
3577 int dst_w = drm_rect_width(&plane_state->base.dst);
3578 int dst_h = drm_rect_height(&plane_state->base.dst);
3579 unsigned long irqflags;
3580
3581 /* Sizes are 0 based */
3582 src_w--;
3583 src_h--;
3584 dst_w--;
3585 dst_h--;
3586
3587 crtc->dspaddr_offset = surf_addr;
3588
3589 crtc->adjusted_x = src_x;
3590 crtc->adjusted_y = src_y;
3591
3592 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3593
3594 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3595 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3596 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3597 PLANE_COLOR_PIPE_CSC_ENABLE |
3598 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3599 }
3600
3601 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3602 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3603 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3604 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3605 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
3606 (plane_state->aux.offset - surf_addr) | aux_stride);
3607 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
3608 (plane_state->aux.y << 16) | plane_state->aux.x);
3609
3610 if (scaler_id >= 0) {
3611 uint32_t ps_ctrl = 0;
3612
3613 WARN_ON(!dst_w || !dst_h);
3614 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3615 crtc_state->scaler_state.scalers[scaler_id].mode;
3616 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3617 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3618 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3619 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3620 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3621 } else {
3622 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3623 }
3624
3625 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3626 intel_plane_ggtt_offset(plane_state) + surf_addr);
3627
3628 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3629
3630 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3631 }
3632
3633 static void skylake_disable_primary_plane(struct intel_plane *primary,
3634 struct intel_crtc *crtc)
3635 {
3636 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3637 enum plane_id plane_id = primary->id;
3638 enum pipe pipe = primary->pipe;
3639 unsigned long irqflags;
3640
3641 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3642
3643 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3644 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3645 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3646
3647 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3648 }
3649
3650 static int
3651 __intel_display_resume(struct drm_device *dev,
3652 struct drm_atomic_state *state,
3653 struct drm_modeset_acquire_ctx *ctx)
3654 {
3655 struct drm_crtc_state *crtc_state;
3656 struct drm_crtc *crtc;
3657 int i, ret;
3658
3659 intel_modeset_setup_hw_state(dev, ctx);
3660 i915_redisable_vga(to_i915(dev));
3661
3662 if (!state)
3663 return 0;
3664
3665 /*
3666 * We've duplicated the state, pointers to the old state are invalid.
3667 *
3668 * Don't attempt to use the old state until we commit the duplicated state.
3669 */
3670 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3671 /*
3672 * Force recalculation even if we restore
3673 * current state. With fast modeset this may not result
3674 * in a modeset when the state is compatible.
3675 */
3676 crtc_state->mode_changed = true;
3677 }
3678
3679 /* ignore any reset values/BIOS leftovers in the WM registers */
3680 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3681 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3682
3683 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3684
3685 WARN_ON(ret == -EDEADLK);
3686 return ret;
3687 }
3688
3689 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3690 {
3691 return intel_has_gpu_reset(dev_priv) &&
3692 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3693 }
3694
3695 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3696 {
3697 struct drm_device *dev = &dev_priv->drm;
3698 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3699 struct drm_atomic_state *state;
3700 int ret;
3701
3702
3703 /* reset doesn't touch the display */
3704 if (!i915.force_reset_modeset_test &&
3705 !gpu_reset_clobbers_display(dev_priv))
3706 return;
3707
3708 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3709 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3710 wake_up_all(&dev_priv->gpu_error.wait_queue);
3711
3712 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3713 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3714 i915_gem_set_wedged(dev_priv);
3715 }
3716
3717 /*
3718 * Need mode_config.mutex so that we don't
3719 * trample ongoing ->detect() and whatnot.
3720 */
3721 mutex_lock(&dev->mode_config.mutex);
3722 drm_modeset_acquire_init(ctx, 0);
3723 while (1) {
3724 ret = drm_modeset_lock_all_ctx(dev, ctx);
3725 if (ret != -EDEADLK)
3726 break;
3727
3728 drm_modeset_backoff(ctx);
3729 }
3730 /*
3731 * Disabling the crtcs gracefully seems nicer. Also the
3732 * g33 docs say we should at least disable all the planes.
3733 */
3734 state = drm_atomic_helper_duplicate_state(dev, ctx);
3735 if (IS_ERR(state)) {
3736 ret = PTR_ERR(state);
3737 DRM_ERROR("Duplicating state failed with %i\n", ret);
3738 return;
3739 }
3740
3741 ret = drm_atomic_helper_disable_all(dev, ctx);
3742 if (ret) {
3743 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3744 drm_atomic_state_put(state);
3745 return;
3746 }
3747
3748 dev_priv->modeset_restore_state = state;
3749 state->acquire_ctx = ctx;
3750 }
3751
3752 void intel_finish_reset(struct drm_i915_private *dev_priv)
3753 {
3754 struct drm_device *dev = &dev_priv->drm;
3755 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3756 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3757 int ret;
3758
3759 /* reset doesn't touch the display */
3760 if (!i915.force_reset_modeset_test &&
3761 !gpu_reset_clobbers_display(dev_priv))
3762 return;
3763
3764 if (!state)
3765 goto unlock;
3766
3767 dev_priv->modeset_restore_state = NULL;
3768
3769 /* reset doesn't touch the display */
3770 if (!gpu_reset_clobbers_display(dev_priv)) {
3771 /* for testing only restore the display */
3772 ret = __intel_display_resume(dev, state, ctx);
3773 if (ret)
3774 DRM_ERROR("Restoring old state failed with %i\n", ret);
3775 } else {
3776 /*
3777 * The display has been reset as well,
3778 * so need a full re-initialization.
3779 */
3780 intel_runtime_pm_disable_interrupts(dev_priv);
3781 intel_runtime_pm_enable_interrupts(dev_priv);
3782
3783 intel_pps_unlock_regs_wa(dev_priv);
3784 intel_modeset_init_hw(dev);
3785
3786 spin_lock_irq(&dev_priv->irq_lock);
3787 if (dev_priv->display.hpd_irq_setup)
3788 dev_priv->display.hpd_irq_setup(dev_priv);
3789 spin_unlock_irq(&dev_priv->irq_lock);
3790
3791 ret = __intel_display_resume(dev, state, ctx);
3792 if (ret)
3793 DRM_ERROR("Restoring old state failed with %i\n", ret);
3794
3795 intel_hpd_init(dev_priv);
3796 }
3797
3798 drm_atomic_state_put(state);
3799 unlock:
3800 drm_modeset_drop_locks(ctx);
3801 drm_modeset_acquire_fini(ctx);
3802 mutex_unlock(&dev->mode_config.mutex);
3803
3804 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3805 }
3806
3807 static void intel_update_pipe_config(struct intel_crtc *crtc,
3808 struct intel_crtc_state *old_crtc_state)
3809 {
3810 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3811 struct intel_crtc_state *pipe_config =
3812 to_intel_crtc_state(crtc->base.state);
3813
3814 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3815 crtc->base.mode = crtc->base.state->mode;
3816
3817 /*
3818 * Update pipe size and adjust fitter if needed: the reason for this is
3819 * that in compute_mode_changes we check the native mode (not the pfit
3820 * mode) to see if we can flip rather than do a full mode set. In the
3821 * fastboot case, we'll flip, but if we don't update the pipesrc and
3822 * pfit state, we'll end up with a big fb scanned out into the wrong
3823 * sized surface.
3824 */
3825
3826 I915_WRITE(PIPESRC(crtc->pipe),
3827 ((pipe_config->pipe_src_w - 1) << 16) |
3828 (pipe_config->pipe_src_h - 1));
3829
3830 /* on skylake this is done by detaching scalers */
3831 if (INTEL_GEN(dev_priv) >= 9) {
3832 skl_detach_scalers(crtc);
3833
3834 if (pipe_config->pch_pfit.enabled)
3835 skylake_pfit_enable(crtc);
3836 } else if (HAS_PCH_SPLIT(dev_priv)) {
3837 if (pipe_config->pch_pfit.enabled)
3838 ironlake_pfit_enable(crtc);
3839 else if (old_crtc_state->pch_pfit.enabled)
3840 ironlake_pfit_disable(crtc, true);
3841 }
3842 }
3843
3844 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3845 {
3846 struct drm_device *dev = crtc->base.dev;
3847 struct drm_i915_private *dev_priv = to_i915(dev);
3848 int pipe = crtc->pipe;
3849 i915_reg_t reg;
3850 u32 temp;
3851
3852 /* enable normal train */
3853 reg = FDI_TX_CTL(pipe);
3854 temp = I915_READ(reg);
3855 if (IS_IVYBRIDGE(dev_priv)) {
3856 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3857 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3858 } else {
3859 temp &= ~FDI_LINK_TRAIN_NONE;
3860 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3861 }
3862 I915_WRITE(reg, temp);
3863
3864 reg = FDI_RX_CTL(pipe);
3865 temp = I915_READ(reg);
3866 if (HAS_PCH_CPT(dev_priv)) {
3867 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3868 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3869 } else {
3870 temp &= ~FDI_LINK_TRAIN_NONE;
3871 temp |= FDI_LINK_TRAIN_NONE;
3872 }
3873 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3874
3875 /* wait one idle pattern time */
3876 POSTING_READ(reg);
3877 udelay(1000);
3878
3879 /* IVB wants error correction enabled */
3880 if (IS_IVYBRIDGE(dev_priv))
3881 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3882 FDI_FE_ERRC_ENABLE);
3883 }
3884
3885 /* The FDI link training functions for ILK/Ibexpeak. */
3886 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3887 const struct intel_crtc_state *crtc_state)
3888 {
3889 struct drm_device *dev = crtc->base.dev;
3890 struct drm_i915_private *dev_priv = to_i915(dev);
3891 int pipe = crtc->pipe;
3892 i915_reg_t reg;
3893 u32 temp, tries;
3894
3895 /* FDI needs bits from pipe first */
3896 assert_pipe_enabled(dev_priv, pipe);
3897
3898 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3899 for train result */
3900 reg = FDI_RX_IMR(pipe);
3901 temp = I915_READ(reg);
3902 temp &= ~FDI_RX_SYMBOL_LOCK;
3903 temp &= ~FDI_RX_BIT_LOCK;
3904 I915_WRITE(reg, temp);
3905 I915_READ(reg);
3906 udelay(150);
3907
3908 /* enable CPU FDI TX and PCH FDI RX */
3909 reg = FDI_TX_CTL(pipe);
3910 temp = I915_READ(reg);
3911 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3912 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3913 temp &= ~FDI_LINK_TRAIN_NONE;
3914 temp |= FDI_LINK_TRAIN_PATTERN_1;
3915 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3916
3917 reg = FDI_RX_CTL(pipe);
3918 temp = I915_READ(reg);
3919 temp &= ~FDI_LINK_TRAIN_NONE;
3920 temp |= FDI_LINK_TRAIN_PATTERN_1;
3921 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3922
3923 POSTING_READ(reg);
3924 udelay(150);
3925
3926 /* Ironlake workaround, enable clock pointer after FDI enable*/
3927 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3928 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3929 FDI_RX_PHASE_SYNC_POINTER_EN);
3930
3931 reg = FDI_RX_IIR(pipe);
3932 for (tries = 0; tries < 5; tries++) {
3933 temp = I915_READ(reg);
3934 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3935
3936 if ((temp & FDI_RX_BIT_LOCK)) {
3937 DRM_DEBUG_KMS("FDI train 1 done.\n");
3938 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3939 break;
3940 }
3941 }
3942 if (tries == 5)
3943 DRM_ERROR("FDI train 1 fail!\n");
3944
3945 /* Train 2 */
3946 reg = FDI_TX_CTL(pipe);
3947 temp = I915_READ(reg);
3948 temp &= ~FDI_LINK_TRAIN_NONE;
3949 temp |= FDI_LINK_TRAIN_PATTERN_2;
3950 I915_WRITE(reg, temp);
3951
3952 reg = FDI_RX_CTL(pipe);
3953 temp = I915_READ(reg);
3954 temp &= ~FDI_LINK_TRAIN_NONE;
3955 temp |= FDI_LINK_TRAIN_PATTERN_2;
3956 I915_WRITE(reg, temp);
3957
3958 POSTING_READ(reg);
3959 udelay(150);
3960
3961 reg = FDI_RX_IIR(pipe);
3962 for (tries = 0; tries < 5; tries++) {
3963 temp = I915_READ(reg);
3964 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3965
3966 if (temp & FDI_RX_SYMBOL_LOCK) {
3967 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3968 DRM_DEBUG_KMS("FDI train 2 done.\n");
3969 break;
3970 }
3971 }
3972 if (tries == 5)
3973 DRM_ERROR("FDI train 2 fail!\n");
3974
3975 DRM_DEBUG_KMS("FDI train done\n");
3976
3977 }
3978
3979 static const int snb_b_fdi_train_param[] = {
3980 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3981 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3982 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3983 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3984 };
3985
3986 /* The FDI link training functions for SNB/Cougarpoint. */
3987 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3988 const struct intel_crtc_state *crtc_state)
3989 {
3990 struct drm_device *dev = crtc->base.dev;
3991 struct drm_i915_private *dev_priv = to_i915(dev);
3992 int pipe = crtc->pipe;
3993 i915_reg_t reg;
3994 u32 temp, i, retry;
3995
3996 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3997 for train result */
3998 reg = FDI_RX_IMR(pipe);
3999 temp = I915_READ(reg);
4000 temp &= ~FDI_RX_SYMBOL_LOCK;
4001 temp &= ~FDI_RX_BIT_LOCK;
4002 I915_WRITE(reg, temp);
4003
4004 POSTING_READ(reg);
4005 udelay(150);
4006
4007 /* enable CPU FDI TX and PCH FDI RX */
4008 reg = FDI_TX_CTL(pipe);
4009 temp = I915_READ(reg);
4010 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4011 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4012 temp &= ~FDI_LINK_TRAIN_NONE;
4013 temp |= FDI_LINK_TRAIN_PATTERN_1;
4014 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4015 /* SNB-B */
4016 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4017 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4018
4019 I915_WRITE(FDI_RX_MISC(pipe),
4020 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4021
4022 reg = FDI_RX_CTL(pipe);
4023 temp = I915_READ(reg);
4024 if (HAS_PCH_CPT(dev_priv)) {
4025 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4026 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4027 } else {
4028 temp &= ~FDI_LINK_TRAIN_NONE;
4029 temp |= FDI_LINK_TRAIN_PATTERN_1;
4030 }
4031 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4032
4033 POSTING_READ(reg);
4034 udelay(150);
4035
4036 for (i = 0; i < 4; i++) {
4037 reg = FDI_TX_CTL(pipe);
4038 temp = I915_READ(reg);
4039 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4040 temp |= snb_b_fdi_train_param[i];
4041 I915_WRITE(reg, temp);
4042
4043 POSTING_READ(reg);
4044 udelay(500);
4045
4046 for (retry = 0; retry < 5; retry++) {
4047 reg = FDI_RX_IIR(pipe);
4048 temp = I915_READ(reg);
4049 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4050 if (temp & FDI_RX_BIT_LOCK) {
4051 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4052 DRM_DEBUG_KMS("FDI train 1 done.\n");
4053 break;
4054 }
4055 udelay(50);
4056 }
4057 if (retry < 5)
4058 break;
4059 }
4060 if (i == 4)
4061 DRM_ERROR("FDI train 1 fail!\n");
4062
4063 /* Train 2 */
4064 reg = FDI_TX_CTL(pipe);
4065 temp = I915_READ(reg);
4066 temp &= ~FDI_LINK_TRAIN_NONE;
4067 temp |= FDI_LINK_TRAIN_PATTERN_2;
4068 if (IS_GEN6(dev_priv)) {
4069 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4070 /* SNB-B */
4071 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4072 }
4073 I915_WRITE(reg, temp);
4074
4075 reg = FDI_RX_CTL(pipe);
4076 temp = I915_READ(reg);
4077 if (HAS_PCH_CPT(dev_priv)) {
4078 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4079 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4080 } else {
4081 temp &= ~FDI_LINK_TRAIN_NONE;
4082 temp |= FDI_LINK_TRAIN_PATTERN_2;
4083 }
4084 I915_WRITE(reg, temp);
4085
4086 POSTING_READ(reg);
4087 udelay(150);
4088
4089 for (i = 0; i < 4; i++) {
4090 reg = FDI_TX_CTL(pipe);
4091 temp = I915_READ(reg);
4092 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4093 temp |= snb_b_fdi_train_param[i];
4094 I915_WRITE(reg, temp);
4095
4096 POSTING_READ(reg);
4097 udelay(500);
4098
4099 for (retry = 0; retry < 5; retry++) {
4100 reg = FDI_RX_IIR(pipe);
4101 temp = I915_READ(reg);
4102 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4103 if (temp & FDI_RX_SYMBOL_LOCK) {
4104 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4105 DRM_DEBUG_KMS("FDI train 2 done.\n");
4106 break;
4107 }
4108 udelay(50);
4109 }
4110 if (retry < 5)
4111 break;
4112 }
4113 if (i == 4)
4114 DRM_ERROR("FDI train 2 fail!\n");
4115
4116 DRM_DEBUG_KMS("FDI train done.\n");
4117 }
4118
4119 /* Manual link training for Ivy Bridge A0 parts */
4120 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4121 const struct intel_crtc_state *crtc_state)
4122 {
4123 struct drm_device *dev = crtc->base.dev;
4124 struct drm_i915_private *dev_priv = to_i915(dev);
4125 int pipe = crtc->pipe;
4126 i915_reg_t reg;
4127 u32 temp, i, j;
4128
4129 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4130 for train result */
4131 reg = FDI_RX_IMR(pipe);
4132 temp = I915_READ(reg);
4133 temp &= ~FDI_RX_SYMBOL_LOCK;
4134 temp &= ~FDI_RX_BIT_LOCK;
4135 I915_WRITE(reg, temp);
4136
4137 POSTING_READ(reg);
4138 udelay(150);
4139
4140 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4141 I915_READ(FDI_RX_IIR(pipe)));
4142
4143 /* Try each vswing and preemphasis setting twice before moving on */
4144 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4145 /* disable first in case we need to retry */
4146 reg = FDI_TX_CTL(pipe);
4147 temp = I915_READ(reg);
4148 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4149 temp &= ~FDI_TX_ENABLE;
4150 I915_WRITE(reg, temp);
4151
4152 reg = FDI_RX_CTL(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~FDI_LINK_TRAIN_AUTO;
4155 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4156 temp &= ~FDI_RX_ENABLE;
4157 I915_WRITE(reg, temp);
4158
4159 /* enable CPU FDI TX and PCH FDI RX */
4160 reg = FDI_TX_CTL(pipe);
4161 temp = I915_READ(reg);
4162 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4163 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4164 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4165 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4166 temp |= snb_b_fdi_train_param[j/2];
4167 temp |= FDI_COMPOSITE_SYNC;
4168 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4169
4170 I915_WRITE(FDI_RX_MISC(pipe),
4171 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4172
4173 reg = FDI_RX_CTL(pipe);
4174 temp = I915_READ(reg);
4175 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4176 temp |= FDI_COMPOSITE_SYNC;
4177 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4178
4179 POSTING_READ(reg);
4180 udelay(1); /* should be 0.5us */
4181
4182 for (i = 0; i < 4; i++) {
4183 reg = FDI_RX_IIR(pipe);
4184 temp = I915_READ(reg);
4185 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4186
4187 if (temp & FDI_RX_BIT_LOCK ||
4188 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4189 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4190 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4191 i);
4192 break;
4193 }
4194 udelay(1); /* should be 0.5us */
4195 }
4196 if (i == 4) {
4197 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4198 continue;
4199 }
4200
4201 /* Train 2 */
4202 reg = FDI_TX_CTL(pipe);
4203 temp = I915_READ(reg);
4204 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4205 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4206 I915_WRITE(reg, temp);
4207
4208 reg = FDI_RX_CTL(pipe);
4209 temp = I915_READ(reg);
4210 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4211 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4212 I915_WRITE(reg, temp);
4213
4214 POSTING_READ(reg);
4215 udelay(2); /* should be 1.5us */
4216
4217 for (i = 0; i < 4; i++) {
4218 reg = FDI_RX_IIR(pipe);
4219 temp = I915_READ(reg);
4220 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4221
4222 if (temp & FDI_RX_SYMBOL_LOCK ||
4223 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4224 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4225 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4226 i);
4227 goto train_done;
4228 }
4229 udelay(2); /* should be 1.5us */
4230 }
4231 if (i == 4)
4232 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4233 }
4234
4235 train_done:
4236 DRM_DEBUG_KMS("FDI train done.\n");
4237 }
4238
4239 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4240 {
4241 struct drm_device *dev = intel_crtc->base.dev;
4242 struct drm_i915_private *dev_priv = to_i915(dev);
4243 int pipe = intel_crtc->pipe;
4244 i915_reg_t reg;
4245 u32 temp;
4246
4247 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4248 reg = FDI_RX_CTL(pipe);
4249 temp = I915_READ(reg);
4250 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4251 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4252 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4253 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4254
4255 POSTING_READ(reg);
4256 udelay(200);
4257
4258 /* Switch from Rawclk to PCDclk */
4259 temp = I915_READ(reg);
4260 I915_WRITE(reg, temp | FDI_PCDCLK);
4261
4262 POSTING_READ(reg);
4263 udelay(200);
4264
4265 /* Enable CPU FDI TX PLL, always on for Ironlake */
4266 reg = FDI_TX_CTL(pipe);
4267 temp = I915_READ(reg);
4268 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4269 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4270
4271 POSTING_READ(reg);
4272 udelay(100);
4273 }
4274 }
4275
4276 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4277 {
4278 struct drm_device *dev = intel_crtc->base.dev;
4279 struct drm_i915_private *dev_priv = to_i915(dev);
4280 int pipe = intel_crtc->pipe;
4281 i915_reg_t reg;
4282 u32 temp;
4283
4284 /* Switch from PCDclk to Rawclk */
4285 reg = FDI_RX_CTL(pipe);
4286 temp = I915_READ(reg);
4287 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4288
4289 /* Disable CPU FDI TX PLL */
4290 reg = FDI_TX_CTL(pipe);
4291 temp = I915_READ(reg);
4292 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4293
4294 POSTING_READ(reg);
4295 udelay(100);
4296
4297 reg = FDI_RX_CTL(pipe);
4298 temp = I915_READ(reg);
4299 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4300
4301 /* Wait for the clocks to turn off. */
4302 POSTING_READ(reg);
4303 udelay(100);
4304 }
4305
4306 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4307 {
4308 struct drm_device *dev = crtc->dev;
4309 struct drm_i915_private *dev_priv = to_i915(dev);
4310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4311 int pipe = intel_crtc->pipe;
4312 i915_reg_t reg;
4313 u32 temp;
4314
4315 /* disable CPU FDI tx and PCH FDI rx */
4316 reg = FDI_TX_CTL(pipe);
4317 temp = I915_READ(reg);
4318 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4319 POSTING_READ(reg);
4320
4321 reg = FDI_RX_CTL(pipe);
4322 temp = I915_READ(reg);
4323 temp &= ~(0x7 << 16);
4324 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4325 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4326
4327 POSTING_READ(reg);
4328 udelay(100);
4329
4330 /* Ironlake workaround, disable clock pointer after downing FDI */
4331 if (HAS_PCH_IBX(dev_priv))
4332 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4333
4334 /* still set train pattern 1 */
4335 reg = FDI_TX_CTL(pipe);
4336 temp = I915_READ(reg);
4337 temp &= ~FDI_LINK_TRAIN_NONE;
4338 temp |= FDI_LINK_TRAIN_PATTERN_1;
4339 I915_WRITE(reg, temp);
4340
4341 reg = FDI_RX_CTL(pipe);
4342 temp = I915_READ(reg);
4343 if (HAS_PCH_CPT(dev_priv)) {
4344 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4345 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4346 } else {
4347 temp &= ~FDI_LINK_TRAIN_NONE;
4348 temp |= FDI_LINK_TRAIN_PATTERN_1;
4349 }
4350 /* BPC in FDI rx is consistent with that in PIPECONF */
4351 temp &= ~(0x07 << 16);
4352 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4353 I915_WRITE(reg, temp);
4354
4355 POSTING_READ(reg);
4356 udelay(100);
4357 }
4358
4359 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4360 {
4361 struct drm_crtc *crtc;
4362 bool cleanup_done;
4363
4364 drm_for_each_crtc(crtc, &dev_priv->drm) {
4365 struct drm_crtc_commit *commit;
4366 spin_lock(&crtc->commit_lock);
4367 commit = list_first_entry_or_null(&crtc->commit_list,
4368 struct drm_crtc_commit, commit_entry);
4369 cleanup_done = commit ?
4370 try_wait_for_completion(&commit->cleanup_done) : true;
4371 spin_unlock(&crtc->commit_lock);
4372
4373 if (cleanup_done)
4374 continue;
4375
4376 drm_crtc_wait_one_vblank(crtc);
4377
4378 return true;
4379 }
4380
4381 return false;
4382 }
4383
4384 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4385 {
4386 u32 temp;
4387
4388 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4389
4390 mutex_lock(&dev_priv->sb_lock);
4391
4392 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4393 temp |= SBI_SSCCTL_DISABLE;
4394 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4395
4396 mutex_unlock(&dev_priv->sb_lock);
4397 }
4398
4399 /* Program iCLKIP clock to the desired frequency */
4400 static void lpt_program_iclkip(struct intel_crtc *crtc)
4401 {
4402 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4403 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4404 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4405 u32 temp;
4406
4407 lpt_disable_iclkip(dev_priv);
4408
4409 /* The iCLK virtual clock root frequency is in MHz,
4410 * but the adjusted_mode->crtc_clock in in KHz. To get the
4411 * divisors, it is necessary to divide one by another, so we
4412 * convert the virtual clock precision to KHz here for higher
4413 * precision.
4414 */
4415 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4416 u32 iclk_virtual_root_freq = 172800 * 1000;
4417 u32 iclk_pi_range = 64;
4418 u32 desired_divisor;
4419
4420 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4421 clock << auxdiv);
4422 divsel = (desired_divisor / iclk_pi_range) - 2;
4423 phaseinc = desired_divisor % iclk_pi_range;
4424
4425 /*
4426 * Near 20MHz is a corner case which is
4427 * out of range for the 7-bit divisor
4428 */
4429 if (divsel <= 0x7f)
4430 break;
4431 }
4432
4433 /* This should not happen with any sane values */
4434 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4435 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4436 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4437 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4438
4439 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4440 clock,
4441 auxdiv,
4442 divsel,
4443 phasedir,
4444 phaseinc);
4445
4446 mutex_lock(&dev_priv->sb_lock);
4447
4448 /* Program SSCDIVINTPHASE6 */
4449 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4450 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4451 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4452 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4453 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4454 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4455 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4456 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4457
4458 /* Program SSCAUXDIV */
4459 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4460 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4461 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4462 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4463
4464 /* Enable modulator and associated divider */
4465 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4466 temp &= ~SBI_SSCCTL_DISABLE;
4467 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4468
4469 mutex_unlock(&dev_priv->sb_lock);
4470
4471 /* Wait for initialization time */
4472 udelay(24);
4473
4474 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4475 }
4476
4477 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4478 {
4479 u32 divsel, phaseinc, auxdiv;
4480 u32 iclk_virtual_root_freq = 172800 * 1000;
4481 u32 iclk_pi_range = 64;
4482 u32 desired_divisor;
4483 u32 temp;
4484
4485 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4486 return 0;
4487
4488 mutex_lock(&dev_priv->sb_lock);
4489
4490 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4491 if (temp & SBI_SSCCTL_DISABLE) {
4492 mutex_unlock(&dev_priv->sb_lock);
4493 return 0;
4494 }
4495
4496 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4497 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4498 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4499 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4500 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4501
4502 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4503 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4504 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4505
4506 mutex_unlock(&dev_priv->sb_lock);
4507
4508 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4509
4510 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4511 desired_divisor << auxdiv);
4512 }
4513
4514 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4515 enum pipe pch_transcoder)
4516 {
4517 struct drm_device *dev = crtc->base.dev;
4518 struct drm_i915_private *dev_priv = to_i915(dev);
4519 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4520
4521 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4522 I915_READ(HTOTAL(cpu_transcoder)));
4523 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4524 I915_READ(HBLANK(cpu_transcoder)));
4525 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4526 I915_READ(HSYNC(cpu_transcoder)));
4527
4528 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4529 I915_READ(VTOTAL(cpu_transcoder)));
4530 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4531 I915_READ(VBLANK(cpu_transcoder)));
4532 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4533 I915_READ(VSYNC(cpu_transcoder)));
4534 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4535 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4536 }
4537
4538 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4539 {
4540 struct drm_i915_private *dev_priv = to_i915(dev);
4541 uint32_t temp;
4542
4543 temp = I915_READ(SOUTH_CHICKEN1);
4544 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4545 return;
4546
4547 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4548 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4549
4550 temp &= ~FDI_BC_BIFURCATION_SELECT;
4551 if (enable)
4552 temp |= FDI_BC_BIFURCATION_SELECT;
4553
4554 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4555 I915_WRITE(SOUTH_CHICKEN1, temp);
4556 POSTING_READ(SOUTH_CHICKEN1);
4557 }
4558
4559 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4560 {
4561 struct drm_device *dev = intel_crtc->base.dev;
4562
4563 switch (intel_crtc->pipe) {
4564 case PIPE_A:
4565 break;
4566 case PIPE_B:
4567 if (intel_crtc->config->fdi_lanes > 2)
4568 cpt_set_fdi_bc_bifurcation(dev, false);
4569 else
4570 cpt_set_fdi_bc_bifurcation(dev, true);
4571
4572 break;
4573 case PIPE_C:
4574 cpt_set_fdi_bc_bifurcation(dev, true);
4575
4576 break;
4577 default:
4578 BUG();
4579 }
4580 }
4581
4582 /* Return which DP Port should be selected for Transcoder DP control */
4583 static enum port
4584 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4585 {
4586 struct drm_device *dev = crtc->base.dev;
4587 struct intel_encoder *encoder;
4588
4589 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4590 if (encoder->type == INTEL_OUTPUT_DP ||
4591 encoder->type == INTEL_OUTPUT_EDP)
4592 return enc_to_dig_port(&encoder->base)->port;
4593 }
4594
4595 return -1;
4596 }
4597
4598 /*
4599 * Enable PCH resources required for PCH ports:
4600 * - PCH PLLs
4601 * - FDI training & RX/TX
4602 * - update transcoder timings
4603 * - DP transcoding bits
4604 * - transcoder
4605 */
4606 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4607 {
4608 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4609 struct drm_device *dev = crtc->base.dev;
4610 struct drm_i915_private *dev_priv = to_i915(dev);
4611 int pipe = crtc->pipe;
4612 u32 temp;
4613
4614 assert_pch_transcoder_disabled(dev_priv, pipe);
4615
4616 if (IS_IVYBRIDGE(dev_priv))
4617 ivybridge_update_fdi_bc_bifurcation(crtc);
4618
4619 /* Write the TU size bits before fdi link training, so that error
4620 * detection works. */
4621 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4622 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4623
4624 /* For PCH output, training FDI link */
4625 dev_priv->display.fdi_link_train(crtc, crtc_state);
4626
4627 /* We need to program the right clock selection before writing the pixel
4628 * mutliplier into the DPLL. */
4629 if (HAS_PCH_CPT(dev_priv)) {
4630 u32 sel;
4631
4632 temp = I915_READ(PCH_DPLL_SEL);
4633 temp |= TRANS_DPLL_ENABLE(pipe);
4634 sel = TRANS_DPLLB_SEL(pipe);
4635 if (crtc_state->shared_dpll ==
4636 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4637 temp |= sel;
4638 else
4639 temp &= ~sel;
4640 I915_WRITE(PCH_DPLL_SEL, temp);
4641 }
4642
4643 /* XXX: pch pll's can be enabled any time before we enable the PCH
4644 * transcoder, and we actually should do this to not upset any PCH
4645 * transcoder that already use the clock when we share it.
4646 *
4647 * Note that enable_shared_dpll tries to do the right thing, but
4648 * get_shared_dpll unconditionally resets the pll - we need that to have
4649 * the right LVDS enable sequence. */
4650 intel_enable_shared_dpll(crtc);
4651
4652 /* set transcoder timing, panel must allow it */
4653 assert_panel_unlocked(dev_priv, pipe);
4654 ironlake_pch_transcoder_set_timings(crtc, pipe);
4655
4656 intel_fdi_normal_train(crtc);
4657
4658 /* For PCH DP, enable TRANS_DP_CTL */
4659 if (HAS_PCH_CPT(dev_priv) &&
4660 intel_crtc_has_dp_encoder(crtc_state)) {
4661 const struct drm_display_mode *adjusted_mode =
4662 &crtc_state->base.adjusted_mode;
4663 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4664 i915_reg_t reg = TRANS_DP_CTL(pipe);
4665 temp = I915_READ(reg);
4666 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4667 TRANS_DP_SYNC_MASK |
4668 TRANS_DP_BPC_MASK);
4669 temp |= TRANS_DP_OUTPUT_ENABLE;
4670 temp |= bpc << 9; /* same format but at 11:9 */
4671
4672 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4673 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4674 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4675 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4676
4677 switch (intel_trans_dp_port_sel(crtc)) {
4678 case PORT_B:
4679 temp |= TRANS_DP_PORT_SEL_B;
4680 break;
4681 case PORT_C:
4682 temp |= TRANS_DP_PORT_SEL_C;
4683 break;
4684 case PORT_D:
4685 temp |= TRANS_DP_PORT_SEL_D;
4686 break;
4687 default:
4688 BUG();
4689 }
4690
4691 I915_WRITE(reg, temp);
4692 }
4693
4694 ironlake_enable_pch_transcoder(dev_priv, pipe);
4695 }
4696
4697 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4698 {
4699 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4700 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4701 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4702
4703 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4704
4705 lpt_program_iclkip(crtc);
4706
4707 /* Set transcoder timing. */
4708 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4709
4710 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4711 }
4712
4713 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4714 {
4715 struct drm_i915_private *dev_priv = to_i915(dev);
4716 i915_reg_t dslreg = PIPEDSL(pipe);
4717 u32 temp;
4718
4719 temp = I915_READ(dslreg);
4720 udelay(500);
4721 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4722 if (wait_for(I915_READ(dslreg) != temp, 5))
4723 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4724 }
4725 }
4726
4727 static int
4728 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4729 unsigned int scaler_user, int *scaler_id,
4730 int src_w, int src_h, int dst_w, int dst_h)
4731 {
4732 struct intel_crtc_scaler_state *scaler_state =
4733 &crtc_state->scaler_state;
4734 struct intel_crtc *intel_crtc =
4735 to_intel_crtc(crtc_state->base.crtc);
4736 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4737 const struct drm_display_mode *adjusted_mode =
4738 &crtc_state->base.adjusted_mode;
4739 int need_scaling;
4740
4741 /*
4742 * Src coordinates are already rotated by 270 degrees for
4743 * the 90/270 degree plane rotation cases (to match the
4744 * GTT mapping), hence no need to account for rotation here.
4745 */
4746 need_scaling = src_w != dst_w || src_h != dst_h;
4747
4748 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4749 need_scaling = true;
4750
4751 /*
4752 * Scaling/fitting not supported in IF-ID mode in GEN9+
4753 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4754 * Once NV12 is enabled, handle it here while allocating scaler
4755 * for NV12.
4756 */
4757 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4758 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4759 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4760 return -EINVAL;
4761 }
4762
4763 /*
4764 * if plane is being disabled or scaler is no more required or force detach
4765 * - free scaler binded to this plane/crtc
4766 * - in order to do this, update crtc->scaler_usage
4767 *
4768 * Here scaler state in crtc_state is set free so that
4769 * scaler can be assigned to other user. Actual register
4770 * update to free the scaler is done in plane/panel-fit programming.
4771 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4772 */
4773 if (force_detach || !need_scaling) {
4774 if (*scaler_id >= 0) {
4775 scaler_state->scaler_users &= ~(1 << scaler_user);
4776 scaler_state->scalers[*scaler_id].in_use = 0;
4777
4778 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4779 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4780 intel_crtc->pipe, scaler_user, *scaler_id,
4781 scaler_state->scaler_users);
4782 *scaler_id = -1;
4783 }
4784 return 0;
4785 }
4786
4787 /* range checks */
4788 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4789 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4790
4791 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4792 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4793 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4794 "size is out of scaler range\n",
4795 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4796 return -EINVAL;
4797 }
4798
4799 /* mark this plane as a scaler user in crtc_state */
4800 scaler_state->scaler_users |= (1 << scaler_user);
4801 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4802 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4803 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4804 scaler_state->scaler_users);
4805
4806 return 0;
4807 }
4808
4809 /**
4810 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4811 *
4812 * @state: crtc's scaler state
4813 *
4814 * Return
4815 * 0 - scaler_usage updated successfully
4816 * error - requested scaling cannot be supported or other error condition
4817 */
4818 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4819 {
4820 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4821
4822 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4823 &state->scaler_state.scaler_id,
4824 state->pipe_src_w, state->pipe_src_h,
4825 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4826 }
4827
4828 /**
4829 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4830 *
4831 * @state: crtc's scaler state
4832 * @plane_state: atomic plane state to update
4833 *
4834 * Return
4835 * 0 - scaler_usage updated successfully
4836 * error - requested scaling cannot be supported or other error condition
4837 */
4838 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4839 struct intel_plane_state *plane_state)
4840 {
4841
4842 struct intel_plane *intel_plane =
4843 to_intel_plane(plane_state->base.plane);
4844 struct drm_framebuffer *fb = plane_state->base.fb;
4845 int ret;
4846
4847 bool force_detach = !fb || !plane_state->base.visible;
4848
4849 ret = skl_update_scaler(crtc_state, force_detach,
4850 drm_plane_index(&intel_plane->base),
4851 &plane_state->scaler_id,
4852 drm_rect_width(&plane_state->base.src) >> 16,
4853 drm_rect_height(&plane_state->base.src) >> 16,
4854 drm_rect_width(&plane_state->base.dst),
4855 drm_rect_height(&plane_state->base.dst));
4856
4857 if (ret || plane_state->scaler_id < 0)
4858 return ret;
4859
4860 /* check colorkey */
4861 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4862 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4863 intel_plane->base.base.id,
4864 intel_plane->base.name);
4865 return -EINVAL;
4866 }
4867
4868 /* Check src format */
4869 switch (fb->format->format) {
4870 case DRM_FORMAT_RGB565:
4871 case DRM_FORMAT_XBGR8888:
4872 case DRM_FORMAT_XRGB8888:
4873 case DRM_FORMAT_ABGR8888:
4874 case DRM_FORMAT_ARGB8888:
4875 case DRM_FORMAT_XRGB2101010:
4876 case DRM_FORMAT_XBGR2101010:
4877 case DRM_FORMAT_YUYV:
4878 case DRM_FORMAT_YVYU:
4879 case DRM_FORMAT_UYVY:
4880 case DRM_FORMAT_VYUY:
4881 break;
4882 default:
4883 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4884 intel_plane->base.base.id, intel_plane->base.name,
4885 fb->base.id, fb->format->format);
4886 return -EINVAL;
4887 }
4888
4889 return 0;
4890 }
4891
4892 static void skylake_scaler_disable(struct intel_crtc *crtc)
4893 {
4894 int i;
4895
4896 for (i = 0; i < crtc->num_scalers; i++)
4897 skl_detach_scaler(crtc, i);
4898 }
4899
4900 static void skylake_pfit_enable(struct intel_crtc *crtc)
4901 {
4902 struct drm_device *dev = crtc->base.dev;
4903 struct drm_i915_private *dev_priv = to_i915(dev);
4904 int pipe = crtc->pipe;
4905 struct intel_crtc_scaler_state *scaler_state =
4906 &crtc->config->scaler_state;
4907
4908 if (crtc->config->pch_pfit.enabled) {
4909 int id;
4910
4911 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4912 return;
4913
4914 id = scaler_state->scaler_id;
4915 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4916 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4917 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4918 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4919 }
4920 }
4921
4922 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4923 {
4924 struct drm_device *dev = crtc->base.dev;
4925 struct drm_i915_private *dev_priv = to_i915(dev);
4926 int pipe = crtc->pipe;
4927
4928 if (crtc->config->pch_pfit.enabled) {
4929 /* Force use of hard-coded filter coefficients
4930 * as some pre-programmed values are broken,
4931 * e.g. x201.
4932 */
4933 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4934 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4935 PF_PIPE_SEL_IVB(pipe));
4936 else
4937 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4938 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4939 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4940 }
4941 }
4942
4943 void hsw_enable_ips(struct intel_crtc *crtc)
4944 {
4945 struct drm_device *dev = crtc->base.dev;
4946 struct drm_i915_private *dev_priv = to_i915(dev);
4947
4948 if (!crtc->config->ips_enabled)
4949 return;
4950
4951 /*
4952 * We can only enable IPS after we enable a plane and wait for a vblank
4953 * This function is called from post_plane_update, which is run after
4954 * a vblank wait.
4955 */
4956
4957 assert_plane_enabled(dev_priv, crtc->plane);
4958 if (IS_BROADWELL(dev_priv)) {
4959 mutex_lock(&dev_priv->rps.hw_lock);
4960 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4961 mutex_unlock(&dev_priv->rps.hw_lock);
4962 /* Quoting Art Runyan: "its not safe to expect any particular
4963 * value in IPS_CTL bit 31 after enabling IPS through the
4964 * mailbox." Moreover, the mailbox may return a bogus state,
4965 * so we need to just enable it and continue on.
4966 */
4967 } else {
4968 I915_WRITE(IPS_CTL, IPS_ENABLE);
4969 /* The bit only becomes 1 in the next vblank, so this wait here
4970 * is essentially intel_wait_for_vblank. If we don't have this
4971 * and don't wait for vblanks until the end of crtc_enable, then
4972 * the HW state readout code will complain that the expected
4973 * IPS_CTL value is not the one we read. */
4974 if (intel_wait_for_register(dev_priv,
4975 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4976 50))
4977 DRM_ERROR("Timed out waiting for IPS enable\n");
4978 }
4979 }
4980
4981 void hsw_disable_ips(struct intel_crtc *crtc)
4982 {
4983 struct drm_device *dev = crtc->base.dev;
4984 struct drm_i915_private *dev_priv = to_i915(dev);
4985
4986 if (!crtc->config->ips_enabled)
4987 return;
4988
4989 assert_plane_enabled(dev_priv, crtc->plane);
4990 if (IS_BROADWELL(dev_priv)) {
4991 mutex_lock(&dev_priv->rps.hw_lock);
4992 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4993 mutex_unlock(&dev_priv->rps.hw_lock);
4994 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4995 if (intel_wait_for_register(dev_priv,
4996 IPS_CTL, IPS_ENABLE, 0,
4997 42))
4998 DRM_ERROR("Timed out waiting for IPS disable\n");
4999 } else {
5000 I915_WRITE(IPS_CTL, 0);
5001 POSTING_READ(IPS_CTL);
5002 }
5003
5004 /* We need to wait for a vblank before we can disable the plane. */
5005 intel_wait_for_vblank(dev_priv, crtc->pipe);
5006 }
5007
5008 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5009 {
5010 if (intel_crtc->overlay) {
5011 struct drm_device *dev = intel_crtc->base.dev;
5012
5013 mutex_lock(&dev->struct_mutex);
5014 (void) intel_overlay_switch_off(intel_crtc->overlay);
5015 mutex_unlock(&dev->struct_mutex);
5016 }
5017
5018 /* Let userspace switch the overlay on again. In most cases userspace
5019 * has to recompute where to put it anyway.
5020 */
5021 }
5022
5023 /**
5024 * intel_post_enable_primary - Perform operations after enabling primary plane
5025 * @crtc: the CRTC whose primary plane was just enabled
5026 *
5027 * Performs potentially sleeping operations that must be done after the primary
5028 * plane is enabled, such as updating FBC and IPS. Note that this may be
5029 * called due to an explicit primary plane update, or due to an implicit
5030 * re-enable that is caused when a sprite plane is updated to no longer
5031 * completely hide the primary plane.
5032 */
5033 static void
5034 intel_post_enable_primary(struct drm_crtc *crtc)
5035 {
5036 struct drm_device *dev = crtc->dev;
5037 struct drm_i915_private *dev_priv = to_i915(dev);
5038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5039 int pipe = intel_crtc->pipe;
5040
5041 /*
5042 * FIXME IPS should be fine as long as one plane is
5043 * enabled, but in practice it seems to have problems
5044 * when going from primary only to sprite only and vice
5045 * versa.
5046 */
5047 hsw_enable_ips(intel_crtc);
5048
5049 /*
5050 * Gen2 reports pipe underruns whenever all planes are disabled.
5051 * So don't enable underrun reporting before at least some planes
5052 * are enabled.
5053 * FIXME: Need to fix the logic to work when we turn off all planes
5054 * but leave the pipe running.
5055 */
5056 if (IS_GEN2(dev_priv))
5057 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5058
5059 /* Underruns don't always raise interrupts, so check manually. */
5060 intel_check_cpu_fifo_underruns(dev_priv);
5061 intel_check_pch_fifo_underruns(dev_priv);
5062 }
5063
5064 /* FIXME move all this to pre_plane_update() with proper state tracking */
5065 static void
5066 intel_pre_disable_primary(struct drm_crtc *crtc)
5067 {
5068 struct drm_device *dev = crtc->dev;
5069 struct drm_i915_private *dev_priv = to_i915(dev);
5070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5071 int pipe = intel_crtc->pipe;
5072
5073 /*
5074 * Gen2 reports pipe underruns whenever all planes are disabled.
5075 * So diasble underrun reporting before all the planes get disabled.
5076 * FIXME: Need to fix the logic to work when we turn off all planes
5077 * but leave the pipe running.
5078 */
5079 if (IS_GEN2(dev_priv))
5080 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5081
5082 /*
5083 * FIXME IPS should be fine as long as one plane is
5084 * enabled, but in practice it seems to have problems
5085 * when going from primary only to sprite only and vice
5086 * versa.
5087 */
5088 hsw_disable_ips(intel_crtc);
5089 }
5090
5091 /* FIXME get rid of this and use pre_plane_update */
5092 static void
5093 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5094 {
5095 struct drm_device *dev = crtc->dev;
5096 struct drm_i915_private *dev_priv = to_i915(dev);
5097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5098 int pipe = intel_crtc->pipe;
5099
5100 intel_pre_disable_primary(crtc);
5101
5102 /*
5103 * Vblank time updates from the shadow to live plane control register
5104 * are blocked if the memory self-refresh mode is active at that
5105 * moment. So to make sure the plane gets truly disabled, disable
5106 * first the self-refresh mode. The self-refresh enable bit in turn
5107 * will be checked/applied by the HW only at the next frame start
5108 * event which is after the vblank start event, so we need to have a
5109 * wait-for-vblank between disabling the plane and the pipe.
5110 */
5111 if (HAS_GMCH_DISPLAY(dev_priv) &&
5112 intel_set_memory_cxsr(dev_priv, false))
5113 intel_wait_for_vblank(dev_priv, pipe);
5114 }
5115
5116 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5117 {
5118 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5119 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5120 struct intel_crtc_state *pipe_config =
5121 to_intel_crtc_state(crtc->base.state);
5122 struct drm_plane *primary = crtc->base.primary;
5123 struct drm_plane_state *old_pri_state =
5124 drm_atomic_get_existing_plane_state(old_state, primary);
5125
5126 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5127
5128 if (pipe_config->update_wm_post && pipe_config->base.active)
5129 intel_update_watermarks(crtc);
5130
5131 if (old_pri_state) {
5132 struct intel_plane_state *primary_state =
5133 to_intel_plane_state(primary->state);
5134 struct intel_plane_state *old_primary_state =
5135 to_intel_plane_state(old_pri_state);
5136
5137 intel_fbc_post_update(crtc);
5138
5139 if (primary_state->base.visible &&
5140 (needs_modeset(&pipe_config->base) ||
5141 !old_primary_state->base.visible))
5142 intel_post_enable_primary(&crtc->base);
5143 }
5144 }
5145
5146 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5147 struct intel_crtc_state *pipe_config)
5148 {
5149 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5150 struct drm_device *dev = crtc->base.dev;
5151 struct drm_i915_private *dev_priv = to_i915(dev);
5152 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5153 struct drm_plane *primary = crtc->base.primary;
5154 struct drm_plane_state *old_pri_state =
5155 drm_atomic_get_existing_plane_state(old_state, primary);
5156 bool modeset = needs_modeset(&pipe_config->base);
5157 struct intel_atomic_state *old_intel_state =
5158 to_intel_atomic_state(old_state);
5159
5160 if (old_pri_state) {
5161 struct intel_plane_state *primary_state =
5162 to_intel_plane_state(primary->state);
5163 struct intel_plane_state *old_primary_state =
5164 to_intel_plane_state(old_pri_state);
5165
5166 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5167
5168 if (old_primary_state->base.visible &&
5169 (modeset || !primary_state->base.visible))
5170 intel_pre_disable_primary(&crtc->base);
5171 }
5172
5173 /*
5174 * Vblank time updates from the shadow to live plane control register
5175 * are blocked if the memory self-refresh mode is active at that
5176 * moment. So to make sure the plane gets truly disabled, disable
5177 * first the self-refresh mode. The self-refresh enable bit in turn
5178 * will be checked/applied by the HW only at the next frame start
5179 * event which is after the vblank start event, so we need to have a
5180 * wait-for-vblank between disabling the plane and the pipe.
5181 */
5182 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5183 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5184 intel_wait_for_vblank(dev_priv, crtc->pipe);
5185
5186 /*
5187 * IVB workaround: must disable low power watermarks for at least
5188 * one frame before enabling scaling. LP watermarks can be re-enabled
5189 * when scaling is disabled.
5190 *
5191 * WaCxSRDisabledForSpriteScaling:ivb
5192 */
5193 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5194 intel_wait_for_vblank(dev_priv, crtc->pipe);
5195
5196 /*
5197 * If we're doing a modeset, we're done. No need to do any pre-vblank
5198 * watermark programming here.
5199 */
5200 if (needs_modeset(&pipe_config->base))
5201 return;
5202
5203 /*
5204 * For platforms that support atomic watermarks, program the
5205 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5206 * will be the intermediate values that are safe for both pre- and
5207 * post- vblank; when vblank happens, the 'active' values will be set
5208 * to the final 'target' values and we'll do this again to get the
5209 * optimal watermarks. For gen9+ platforms, the values we program here
5210 * will be the final target values which will get automatically latched
5211 * at vblank time; no further programming will be necessary.
5212 *
5213 * If a platform hasn't been transitioned to atomic watermarks yet,
5214 * we'll continue to update watermarks the old way, if flags tell
5215 * us to.
5216 */
5217 if (dev_priv->display.initial_watermarks != NULL)
5218 dev_priv->display.initial_watermarks(old_intel_state,
5219 pipe_config);
5220 else if (pipe_config->update_wm_pre)
5221 intel_update_watermarks(crtc);
5222 }
5223
5224 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5225 {
5226 struct drm_device *dev = crtc->dev;
5227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5228 struct drm_plane *p;
5229 int pipe = intel_crtc->pipe;
5230
5231 intel_crtc_dpms_overlay_disable(intel_crtc);
5232
5233 drm_for_each_plane_mask(p, dev, plane_mask)
5234 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5235
5236 /*
5237 * FIXME: Once we grow proper nuclear flip support out of this we need
5238 * to compute the mask of flip planes precisely. For the time being
5239 * consider this a flip to a NULL plane.
5240 */
5241 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5242 }
5243
5244 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5245 struct intel_crtc_state *crtc_state,
5246 struct drm_atomic_state *old_state)
5247 {
5248 struct drm_connector_state *conn_state;
5249 struct drm_connector *conn;
5250 int i;
5251
5252 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5253 struct intel_encoder *encoder =
5254 to_intel_encoder(conn_state->best_encoder);
5255
5256 if (conn_state->crtc != crtc)
5257 continue;
5258
5259 if (encoder->pre_pll_enable)
5260 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5261 }
5262 }
5263
5264 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5265 struct intel_crtc_state *crtc_state,
5266 struct drm_atomic_state *old_state)
5267 {
5268 struct drm_connector_state *conn_state;
5269 struct drm_connector *conn;
5270 int i;
5271
5272 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5273 struct intel_encoder *encoder =
5274 to_intel_encoder(conn_state->best_encoder);
5275
5276 if (conn_state->crtc != crtc)
5277 continue;
5278
5279 if (encoder->pre_enable)
5280 encoder->pre_enable(encoder, crtc_state, conn_state);
5281 }
5282 }
5283
5284 static void intel_encoders_enable(struct drm_crtc *crtc,
5285 struct intel_crtc_state *crtc_state,
5286 struct drm_atomic_state *old_state)
5287 {
5288 struct drm_connector_state *conn_state;
5289 struct drm_connector *conn;
5290 int i;
5291
5292 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5293 struct intel_encoder *encoder =
5294 to_intel_encoder(conn_state->best_encoder);
5295
5296 if (conn_state->crtc != crtc)
5297 continue;
5298
5299 encoder->enable(encoder, crtc_state, conn_state);
5300 intel_opregion_notify_encoder(encoder, true);
5301 }
5302 }
5303
5304 static void intel_encoders_disable(struct drm_crtc *crtc,
5305 struct intel_crtc_state *old_crtc_state,
5306 struct drm_atomic_state *old_state)
5307 {
5308 struct drm_connector_state *old_conn_state;
5309 struct drm_connector *conn;
5310 int i;
5311
5312 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5313 struct intel_encoder *encoder =
5314 to_intel_encoder(old_conn_state->best_encoder);
5315
5316 if (old_conn_state->crtc != crtc)
5317 continue;
5318
5319 intel_opregion_notify_encoder(encoder, false);
5320 encoder->disable(encoder, old_crtc_state, old_conn_state);
5321 }
5322 }
5323
5324 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5325 struct intel_crtc_state *old_crtc_state,
5326 struct drm_atomic_state *old_state)
5327 {
5328 struct drm_connector_state *old_conn_state;
5329 struct drm_connector *conn;
5330 int i;
5331
5332 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5333 struct intel_encoder *encoder =
5334 to_intel_encoder(old_conn_state->best_encoder);
5335
5336 if (old_conn_state->crtc != crtc)
5337 continue;
5338
5339 if (encoder->post_disable)
5340 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5341 }
5342 }
5343
5344 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5345 struct intel_crtc_state *old_crtc_state,
5346 struct drm_atomic_state *old_state)
5347 {
5348 struct drm_connector_state *old_conn_state;
5349 struct drm_connector *conn;
5350 int i;
5351
5352 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5353 struct intel_encoder *encoder =
5354 to_intel_encoder(old_conn_state->best_encoder);
5355
5356 if (old_conn_state->crtc != crtc)
5357 continue;
5358
5359 if (encoder->post_pll_disable)
5360 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5361 }
5362 }
5363
5364 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5365 struct drm_atomic_state *old_state)
5366 {
5367 struct drm_crtc *crtc = pipe_config->base.crtc;
5368 struct drm_device *dev = crtc->dev;
5369 struct drm_i915_private *dev_priv = to_i915(dev);
5370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5371 int pipe = intel_crtc->pipe;
5372 struct intel_atomic_state *old_intel_state =
5373 to_intel_atomic_state(old_state);
5374
5375 if (WARN_ON(intel_crtc->active))
5376 return;
5377
5378 /*
5379 * Sometimes spurious CPU pipe underruns happen during FDI
5380 * training, at least with VGA+HDMI cloning. Suppress them.
5381 *
5382 * On ILK we get an occasional spurious CPU pipe underruns
5383 * between eDP port A enable and vdd enable. Also PCH port
5384 * enable seems to result in the occasional CPU pipe underrun.
5385 *
5386 * Spurious PCH underruns also occur during PCH enabling.
5387 */
5388 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5389 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5390 if (intel_crtc->config->has_pch_encoder)
5391 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5392
5393 if (intel_crtc->config->has_pch_encoder)
5394 intel_prepare_shared_dpll(intel_crtc);
5395
5396 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5397 intel_dp_set_m_n(intel_crtc, M1_N1);
5398
5399 intel_set_pipe_timings(intel_crtc);
5400 intel_set_pipe_src_size(intel_crtc);
5401
5402 if (intel_crtc->config->has_pch_encoder) {
5403 intel_cpu_transcoder_set_m_n(intel_crtc,
5404 &intel_crtc->config->fdi_m_n, NULL);
5405 }
5406
5407 ironlake_set_pipeconf(crtc);
5408
5409 intel_crtc->active = true;
5410
5411 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5412
5413 if (intel_crtc->config->has_pch_encoder) {
5414 /* Note: FDI PLL enabling _must_ be done before we enable the
5415 * cpu pipes, hence this is separate from all the other fdi/pch
5416 * enabling. */
5417 ironlake_fdi_pll_enable(intel_crtc);
5418 } else {
5419 assert_fdi_tx_disabled(dev_priv, pipe);
5420 assert_fdi_rx_disabled(dev_priv, pipe);
5421 }
5422
5423 ironlake_pfit_enable(intel_crtc);
5424
5425 /*
5426 * On ILK+ LUT must be loaded before the pipe is running but with
5427 * clocks enabled
5428 */
5429 intel_color_load_luts(&pipe_config->base);
5430
5431 if (dev_priv->display.initial_watermarks != NULL)
5432 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5433 intel_enable_pipe(intel_crtc);
5434
5435 if (intel_crtc->config->has_pch_encoder)
5436 ironlake_pch_enable(pipe_config);
5437
5438 assert_vblank_disabled(crtc);
5439 drm_crtc_vblank_on(crtc);
5440
5441 intel_encoders_enable(crtc, pipe_config, old_state);
5442
5443 if (HAS_PCH_CPT(dev_priv))
5444 cpt_verify_modeset(dev, intel_crtc->pipe);
5445
5446 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5447 if (intel_crtc->config->has_pch_encoder)
5448 intel_wait_for_vblank(dev_priv, pipe);
5449 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5450 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5451 }
5452
5453 /* IPS only exists on ULT machines and is tied to pipe A. */
5454 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5455 {
5456 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5457 }
5458
5459 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5460 struct drm_atomic_state *old_state)
5461 {
5462 struct drm_crtc *crtc = pipe_config->base.crtc;
5463 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5465 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5466 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5467 struct intel_atomic_state *old_intel_state =
5468 to_intel_atomic_state(old_state);
5469
5470 if (WARN_ON(intel_crtc->active))
5471 return;
5472
5473 if (intel_crtc->config->has_pch_encoder)
5474 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5475
5476 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5477
5478 if (intel_crtc->config->shared_dpll)
5479 intel_enable_shared_dpll(intel_crtc);
5480
5481 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5482 intel_dp_set_m_n(intel_crtc, M1_N1);
5483
5484 if (!transcoder_is_dsi(cpu_transcoder))
5485 intel_set_pipe_timings(intel_crtc);
5486
5487 intel_set_pipe_src_size(intel_crtc);
5488
5489 if (cpu_transcoder != TRANSCODER_EDP &&
5490 !transcoder_is_dsi(cpu_transcoder)) {
5491 I915_WRITE(PIPE_MULT(cpu_transcoder),
5492 intel_crtc->config->pixel_multiplier - 1);
5493 }
5494
5495 if (intel_crtc->config->has_pch_encoder) {
5496 intel_cpu_transcoder_set_m_n(intel_crtc,
5497 &intel_crtc->config->fdi_m_n, NULL);
5498 }
5499
5500 if (!transcoder_is_dsi(cpu_transcoder))
5501 haswell_set_pipeconf(crtc);
5502
5503 haswell_set_pipemisc(crtc);
5504
5505 intel_color_set_csc(&pipe_config->base);
5506
5507 intel_crtc->active = true;
5508
5509 if (intel_crtc->config->has_pch_encoder)
5510 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5511 else
5512 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5513
5514 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5515
5516 if (intel_crtc->config->has_pch_encoder)
5517 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5518
5519 if (!transcoder_is_dsi(cpu_transcoder))
5520 intel_ddi_enable_pipe_clock(pipe_config);
5521
5522 if (INTEL_GEN(dev_priv) >= 9)
5523 skylake_pfit_enable(intel_crtc);
5524 else
5525 ironlake_pfit_enable(intel_crtc);
5526
5527 /*
5528 * On ILK+ LUT must be loaded before the pipe is running but with
5529 * clocks enabled
5530 */
5531 intel_color_load_luts(&pipe_config->base);
5532
5533 intel_ddi_set_pipe_settings(pipe_config);
5534 if (!transcoder_is_dsi(cpu_transcoder))
5535 intel_ddi_enable_transcoder_func(pipe_config);
5536
5537 if (dev_priv->display.initial_watermarks != NULL)
5538 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5539
5540 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5541 if (!transcoder_is_dsi(cpu_transcoder))
5542 intel_enable_pipe(intel_crtc);
5543
5544 if (intel_crtc->config->has_pch_encoder)
5545 lpt_pch_enable(pipe_config);
5546
5547 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5548 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5549
5550 assert_vblank_disabled(crtc);
5551 drm_crtc_vblank_on(crtc);
5552
5553 intel_encoders_enable(crtc, pipe_config, old_state);
5554
5555 if (intel_crtc->config->has_pch_encoder) {
5556 intel_wait_for_vblank(dev_priv, pipe);
5557 intel_wait_for_vblank(dev_priv, pipe);
5558 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5559 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5560 }
5561
5562 /* If we change the relative order between pipe/planes enabling, we need
5563 * to change the workaround. */
5564 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5565 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5566 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5567 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5568 }
5569 }
5570
5571 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5572 {
5573 struct drm_device *dev = crtc->base.dev;
5574 struct drm_i915_private *dev_priv = to_i915(dev);
5575 int pipe = crtc->pipe;
5576
5577 /* To avoid upsetting the power well on haswell only disable the pfit if
5578 * it's in use. The hw state code will make sure we get this right. */
5579 if (force || crtc->config->pch_pfit.enabled) {
5580 I915_WRITE(PF_CTL(pipe), 0);
5581 I915_WRITE(PF_WIN_POS(pipe), 0);
5582 I915_WRITE(PF_WIN_SZ(pipe), 0);
5583 }
5584 }
5585
5586 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5587 struct drm_atomic_state *old_state)
5588 {
5589 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5590 struct drm_device *dev = crtc->dev;
5591 struct drm_i915_private *dev_priv = to_i915(dev);
5592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5593 int pipe = intel_crtc->pipe;
5594
5595 /*
5596 * Sometimes spurious CPU pipe underruns happen when the
5597 * pipe is already disabled, but FDI RX/TX is still enabled.
5598 * Happens at least with VGA+HDMI cloning. Suppress them.
5599 */
5600 if (intel_crtc->config->has_pch_encoder) {
5601 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5602 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5603 }
5604
5605 intel_encoders_disable(crtc, old_crtc_state, old_state);
5606
5607 drm_crtc_vblank_off(crtc);
5608 assert_vblank_disabled(crtc);
5609
5610 intel_disable_pipe(intel_crtc);
5611
5612 ironlake_pfit_disable(intel_crtc, false);
5613
5614 if (intel_crtc->config->has_pch_encoder)
5615 ironlake_fdi_disable(crtc);
5616
5617 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5618
5619 if (intel_crtc->config->has_pch_encoder) {
5620 ironlake_disable_pch_transcoder(dev_priv, pipe);
5621
5622 if (HAS_PCH_CPT(dev_priv)) {
5623 i915_reg_t reg;
5624 u32 temp;
5625
5626 /* disable TRANS_DP_CTL */
5627 reg = TRANS_DP_CTL(pipe);
5628 temp = I915_READ(reg);
5629 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5630 TRANS_DP_PORT_SEL_MASK);
5631 temp |= TRANS_DP_PORT_SEL_NONE;
5632 I915_WRITE(reg, temp);
5633
5634 /* disable DPLL_SEL */
5635 temp = I915_READ(PCH_DPLL_SEL);
5636 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5637 I915_WRITE(PCH_DPLL_SEL, temp);
5638 }
5639
5640 ironlake_fdi_pll_disable(intel_crtc);
5641 }
5642
5643 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5644 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5645 }
5646
5647 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5648 struct drm_atomic_state *old_state)
5649 {
5650 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5651 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5653 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5654
5655 if (intel_crtc->config->has_pch_encoder)
5656 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5657
5658 intel_encoders_disable(crtc, old_crtc_state, old_state);
5659
5660 drm_crtc_vblank_off(crtc);
5661 assert_vblank_disabled(crtc);
5662
5663 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5664 if (!transcoder_is_dsi(cpu_transcoder))
5665 intel_disable_pipe(intel_crtc);
5666
5667 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5668 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5669
5670 if (!transcoder_is_dsi(cpu_transcoder))
5671 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5672
5673 if (INTEL_GEN(dev_priv) >= 9)
5674 skylake_scaler_disable(intel_crtc);
5675 else
5676 ironlake_pfit_disable(intel_crtc, false);
5677
5678 if (!transcoder_is_dsi(cpu_transcoder))
5679 intel_ddi_disable_pipe_clock(intel_crtc->config);
5680
5681 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5682
5683 if (old_crtc_state->has_pch_encoder)
5684 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5685 }
5686
5687 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5688 {
5689 struct drm_device *dev = crtc->base.dev;
5690 struct drm_i915_private *dev_priv = to_i915(dev);
5691 struct intel_crtc_state *pipe_config = crtc->config;
5692
5693 if (!pipe_config->gmch_pfit.control)
5694 return;
5695
5696 /*
5697 * The panel fitter should only be adjusted whilst the pipe is disabled,
5698 * according to register description and PRM.
5699 */
5700 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5701 assert_pipe_disabled(dev_priv, crtc->pipe);
5702
5703 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5704 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5705
5706 /* Border color in case we don't scale up to the full screen. Black by
5707 * default, change to something else for debugging. */
5708 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5709 }
5710
5711 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5712 {
5713 switch (port) {
5714 case PORT_A:
5715 return POWER_DOMAIN_PORT_DDI_A_LANES;
5716 case PORT_B:
5717 return POWER_DOMAIN_PORT_DDI_B_LANES;
5718 case PORT_C:
5719 return POWER_DOMAIN_PORT_DDI_C_LANES;
5720 case PORT_D:
5721 return POWER_DOMAIN_PORT_DDI_D_LANES;
5722 case PORT_E:
5723 return POWER_DOMAIN_PORT_DDI_E_LANES;
5724 default:
5725 MISSING_CASE(port);
5726 return POWER_DOMAIN_PORT_OTHER;
5727 }
5728 }
5729
5730 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5731 struct intel_crtc_state *crtc_state)
5732 {
5733 struct drm_device *dev = crtc->dev;
5734 struct drm_i915_private *dev_priv = to_i915(dev);
5735 struct drm_encoder *encoder;
5736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5737 enum pipe pipe = intel_crtc->pipe;
5738 u64 mask;
5739 enum transcoder transcoder = crtc_state->cpu_transcoder;
5740
5741 if (!crtc_state->base.active)
5742 return 0;
5743
5744 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5745 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5746 if (crtc_state->pch_pfit.enabled ||
5747 crtc_state->pch_pfit.force_thru)
5748 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5749
5750 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5751 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5752
5753 mask |= BIT_ULL(intel_encoder->power_domain);
5754 }
5755
5756 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5757 mask |= BIT(POWER_DOMAIN_AUDIO);
5758
5759 if (crtc_state->shared_dpll)
5760 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5761
5762 return mask;
5763 }
5764
5765 static u64
5766 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5767 struct intel_crtc_state *crtc_state)
5768 {
5769 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5771 enum intel_display_power_domain domain;
5772 u64 domains, new_domains, old_domains;
5773
5774 old_domains = intel_crtc->enabled_power_domains;
5775 intel_crtc->enabled_power_domains = new_domains =
5776 get_crtc_power_domains(crtc, crtc_state);
5777
5778 domains = new_domains & ~old_domains;
5779
5780 for_each_power_domain(domain, domains)
5781 intel_display_power_get(dev_priv, domain);
5782
5783 return old_domains & ~new_domains;
5784 }
5785
5786 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5787 u64 domains)
5788 {
5789 enum intel_display_power_domain domain;
5790
5791 for_each_power_domain(domain, domains)
5792 intel_display_power_put(dev_priv, domain);
5793 }
5794
5795 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5796 struct drm_atomic_state *old_state)
5797 {
5798 struct intel_atomic_state *old_intel_state =
5799 to_intel_atomic_state(old_state);
5800 struct drm_crtc *crtc = pipe_config->base.crtc;
5801 struct drm_device *dev = crtc->dev;
5802 struct drm_i915_private *dev_priv = to_i915(dev);
5803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5804 int pipe = intel_crtc->pipe;
5805
5806 if (WARN_ON(intel_crtc->active))
5807 return;
5808
5809 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5810 intel_dp_set_m_n(intel_crtc, M1_N1);
5811
5812 intel_set_pipe_timings(intel_crtc);
5813 intel_set_pipe_src_size(intel_crtc);
5814
5815 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5816 struct drm_i915_private *dev_priv = to_i915(dev);
5817
5818 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5819 I915_WRITE(CHV_CANVAS(pipe), 0);
5820 }
5821
5822 i9xx_set_pipeconf(intel_crtc);
5823
5824 intel_crtc->active = true;
5825
5826 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5827
5828 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5829
5830 if (IS_CHERRYVIEW(dev_priv)) {
5831 chv_prepare_pll(intel_crtc, intel_crtc->config);
5832 chv_enable_pll(intel_crtc, intel_crtc->config);
5833 } else {
5834 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5835 vlv_enable_pll(intel_crtc, intel_crtc->config);
5836 }
5837
5838 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5839
5840 i9xx_pfit_enable(intel_crtc);
5841
5842 intel_color_load_luts(&pipe_config->base);
5843
5844 dev_priv->display.initial_watermarks(old_intel_state,
5845 pipe_config);
5846 intel_enable_pipe(intel_crtc);
5847
5848 assert_vblank_disabled(crtc);
5849 drm_crtc_vblank_on(crtc);
5850
5851 intel_encoders_enable(crtc, pipe_config, old_state);
5852 }
5853
5854 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5855 {
5856 struct drm_device *dev = crtc->base.dev;
5857 struct drm_i915_private *dev_priv = to_i915(dev);
5858
5859 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5860 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5861 }
5862
5863 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5864 struct drm_atomic_state *old_state)
5865 {
5866 struct intel_atomic_state *old_intel_state =
5867 to_intel_atomic_state(old_state);
5868 struct drm_crtc *crtc = pipe_config->base.crtc;
5869 struct drm_device *dev = crtc->dev;
5870 struct drm_i915_private *dev_priv = to_i915(dev);
5871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5872 enum pipe pipe = intel_crtc->pipe;
5873
5874 if (WARN_ON(intel_crtc->active))
5875 return;
5876
5877 i9xx_set_pll_dividers(intel_crtc);
5878
5879 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5880 intel_dp_set_m_n(intel_crtc, M1_N1);
5881
5882 intel_set_pipe_timings(intel_crtc);
5883 intel_set_pipe_src_size(intel_crtc);
5884
5885 i9xx_set_pipeconf(intel_crtc);
5886
5887 intel_crtc->active = true;
5888
5889 if (!IS_GEN2(dev_priv))
5890 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5891
5892 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5893
5894 i9xx_enable_pll(intel_crtc);
5895
5896 i9xx_pfit_enable(intel_crtc);
5897
5898 intel_color_load_luts(&pipe_config->base);
5899
5900 if (dev_priv->display.initial_watermarks != NULL)
5901 dev_priv->display.initial_watermarks(old_intel_state,
5902 intel_crtc->config);
5903 else
5904 intel_update_watermarks(intel_crtc);
5905 intel_enable_pipe(intel_crtc);
5906
5907 assert_vblank_disabled(crtc);
5908 drm_crtc_vblank_on(crtc);
5909
5910 intel_encoders_enable(crtc, pipe_config, old_state);
5911 }
5912
5913 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5914 {
5915 struct drm_device *dev = crtc->base.dev;
5916 struct drm_i915_private *dev_priv = to_i915(dev);
5917
5918 if (!crtc->config->gmch_pfit.control)
5919 return;
5920
5921 assert_pipe_disabled(dev_priv, crtc->pipe);
5922
5923 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5924 I915_READ(PFIT_CONTROL));
5925 I915_WRITE(PFIT_CONTROL, 0);
5926 }
5927
5928 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5929 struct drm_atomic_state *old_state)
5930 {
5931 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5932 struct drm_device *dev = crtc->dev;
5933 struct drm_i915_private *dev_priv = to_i915(dev);
5934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5935 int pipe = intel_crtc->pipe;
5936
5937 /*
5938 * On gen2 planes are double buffered but the pipe isn't, so we must
5939 * wait for planes to fully turn off before disabling the pipe.
5940 */
5941 if (IS_GEN2(dev_priv))
5942 intel_wait_for_vblank(dev_priv, pipe);
5943
5944 intel_encoders_disable(crtc, old_crtc_state, old_state);
5945
5946 drm_crtc_vblank_off(crtc);
5947 assert_vblank_disabled(crtc);
5948
5949 intel_disable_pipe(intel_crtc);
5950
5951 i9xx_pfit_disable(intel_crtc);
5952
5953 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5954
5955 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5956 if (IS_CHERRYVIEW(dev_priv))
5957 chv_disable_pll(dev_priv, pipe);
5958 else if (IS_VALLEYVIEW(dev_priv))
5959 vlv_disable_pll(dev_priv, pipe);
5960 else
5961 i9xx_disable_pll(intel_crtc);
5962 }
5963
5964 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5965
5966 if (!IS_GEN2(dev_priv))
5967 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5968
5969 if (!dev_priv->display.initial_watermarks)
5970 intel_update_watermarks(intel_crtc);
5971
5972 /* clock the pipe down to 640x480@60 to potentially save power */
5973 if (IS_I830(dev_priv))
5974 i830_enable_pipe(dev_priv, pipe);
5975 }
5976
5977 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5978 struct drm_modeset_acquire_ctx *ctx)
5979 {
5980 struct intel_encoder *encoder;
5981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5982 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5983 enum intel_display_power_domain domain;
5984 u64 domains;
5985 struct drm_atomic_state *state;
5986 struct intel_crtc_state *crtc_state;
5987 int ret;
5988
5989 if (!intel_crtc->active)
5990 return;
5991
5992 if (crtc->primary->state->visible) {
5993 intel_pre_disable_primary_noatomic(crtc);
5994
5995 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5996 crtc->primary->state->visible = false;
5997 }
5998
5999 state = drm_atomic_state_alloc(crtc->dev);
6000 if (!state) {
6001 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6002 crtc->base.id, crtc->name);
6003 return;
6004 }
6005
6006 state->acquire_ctx = ctx;
6007
6008 /* Everything's already locked, -EDEADLK can't happen. */
6009 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6010 ret = drm_atomic_add_affected_connectors(state, crtc);
6011
6012 WARN_ON(IS_ERR(crtc_state) || ret);
6013
6014 dev_priv->display.crtc_disable(crtc_state, state);
6015
6016 drm_atomic_state_put(state);
6017
6018 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6019 crtc->base.id, crtc->name);
6020
6021 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6022 crtc->state->active = false;
6023 intel_crtc->active = false;
6024 crtc->enabled = false;
6025 crtc->state->connector_mask = 0;
6026 crtc->state->encoder_mask = 0;
6027
6028 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6029 encoder->base.crtc = NULL;
6030
6031 intel_fbc_disable(intel_crtc);
6032 intel_update_watermarks(intel_crtc);
6033 intel_disable_shared_dpll(intel_crtc);
6034
6035 domains = intel_crtc->enabled_power_domains;
6036 for_each_power_domain(domain, domains)
6037 intel_display_power_put(dev_priv, domain);
6038 intel_crtc->enabled_power_domains = 0;
6039
6040 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6041 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6042 }
6043
6044 /*
6045 * turn all crtc's off, but do not adjust state
6046 * This has to be paired with a call to intel_modeset_setup_hw_state.
6047 */
6048 int intel_display_suspend(struct drm_device *dev)
6049 {
6050 struct drm_i915_private *dev_priv = to_i915(dev);
6051 struct drm_atomic_state *state;
6052 int ret;
6053
6054 state = drm_atomic_helper_suspend(dev);
6055 ret = PTR_ERR_OR_ZERO(state);
6056 if (ret)
6057 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6058 else
6059 dev_priv->modeset_restore_state = state;
6060 return ret;
6061 }
6062
6063 void intel_encoder_destroy(struct drm_encoder *encoder)
6064 {
6065 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6066
6067 drm_encoder_cleanup(encoder);
6068 kfree(intel_encoder);
6069 }
6070
6071 /* Cross check the actual hw state with our own modeset state tracking (and it's
6072 * internal consistency). */
6073 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6074 struct drm_connector_state *conn_state)
6075 {
6076 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6077
6078 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6079 connector->base.base.id,
6080 connector->base.name);
6081
6082 if (connector->get_hw_state(connector)) {
6083 struct intel_encoder *encoder = connector->encoder;
6084
6085 I915_STATE_WARN(!crtc_state,
6086 "connector enabled without attached crtc\n");
6087
6088 if (!crtc_state)
6089 return;
6090
6091 I915_STATE_WARN(!crtc_state->active,
6092 "connector is active, but attached crtc isn't\n");
6093
6094 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6095 return;
6096
6097 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6098 "atomic encoder doesn't match attached encoder\n");
6099
6100 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6101 "attached encoder crtc differs from connector crtc\n");
6102 } else {
6103 I915_STATE_WARN(crtc_state && crtc_state->active,
6104 "attached crtc is active, but connector isn't\n");
6105 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6106 "best encoder set without crtc!\n");
6107 }
6108 }
6109
6110 int intel_connector_init(struct intel_connector *connector)
6111 {
6112 struct intel_digital_connector_state *conn_state;
6113
6114 /*
6115 * Allocate enough memory to hold intel_digital_connector_state,
6116 * This might be a few bytes too many, but for connectors that don't
6117 * need it we'll free the state and allocate a smaller one on the first
6118 * succesful commit anyway.
6119 */
6120 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6121 if (!conn_state)
6122 return -ENOMEM;
6123
6124 __drm_atomic_helper_connector_reset(&connector->base,
6125 &conn_state->base);
6126
6127 return 0;
6128 }
6129
6130 struct intel_connector *intel_connector_alloc(void)
6131 {
6132 struct intel_connector *connector;
6133
6134 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6135 if (!connector)
6136 return NULL;
6137
6138 if (intel_connector_init(connector) < 0) {
6139 kfree(connector);
6140 return NULL;
6141 }
6142
6143 return connector;
6144 }
6145
6146 /* Simple connector->get_hw_state implementation for encoders that support only
6147 * one connector and no cloning and hence the encoder state determines the state
6148 * of the connector. */
6149 bool intel_connector_get_hw_state(struct intel_connector *connector)
6150 {
6151 enum pipe pipe = 0;
6152 struct intel_encoder *encoder = connector->encoder;
6153
6154 return encoder->get_hw_state(encoder, &pipe);
6155 }
6156
6157 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6158 {
6159 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6160 return crtc_state->fdi_lanes;
6161
6162 return 0;
6163 }
6164
6165 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6166 struct intel_crtc_state *pipe_config)
6167 {
6168 struct drm_i915_private *dev_priv = to_i915(dev);
6169 struct drm_atomic_state *state = pipe_config->base.state;
6170 struct intel_crtc *other_crtc;
6171 struct intel_crtc_state *other_crtc_state;
6172
6173 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6174 pipe_name(pipe), pipe_config->fdi_lanes);
6175 if (pipe_config->fdi_lanes > 4) {
6176 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6177 pipe_name(pipe), pipe_config->fdi_lanes);
6178 return -EINVAL;
6179 }
6180
6181 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6182 if (pipe_config->fdi_lanes > 2) {
6183 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6184 pipe_config->fdi_lanes);
6185 return -EINVAL;
6186 } else {
6187 return 0;
6188 }
6189 }
6190
6191 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6192 return 0;
6193
6194 /* Ivybridge 3 pipe is really complicated */
6195 switch (pipe) {
6196 case PIPE_A:
6197 return 0;
6198 case PIPE_B:
6199 if (pipe_config->fdi_lanes <= 2)
6200 return 0;
6201
6202 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6203 other_crtc_state =
6204 intel_atomic_get_crtc_state(state, other_crtc);
6205 if (IS_ERR(other_crtc_state))
6206 return PTR_ERR(other_crtc_state);
6207
6208 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6209 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6210 pipe_name(pipe), pipe_config->fdi_lanes);
6211 return -EINVAL;
6212 }
6213 return 0;
6214 case PIPE_C:
6215 if (pipe_config->fdi_lanes > 2) {
6216 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6217 pipe_name(pipe), pipe_config->fdi_lanes);
6218 return -EINVAL;
6219 }
6220
6221 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6222 other_crtc_state =
6223 intel_atomic_get_crtc_state(state, other_crtc);
6224 if (IS_ERR(other_crtc_state))
6225 return PTR_ERR(other_crtc_state);
6226
6227 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6228 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6229 return -EINVAL;
6230 }
6231 return 0;
6232 default:
6233 BUG();
6234 }
6235 }
6236
6237 #define RETRY 1
6238 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6239 struct intel_crtc_state *pipe_config)
6240 {
6241 struct drm_device *dev = intel_crtc->base.dev;
6242 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6243 int lane, link_bw, fdi_dotclock, ret;
6244 bool needs_recompute = false;
6245
6246 retry:
6247 /* FDI is a binary signal running at ~2.7GHz, encoding
6248 * each output octet as 10 bits. The actual frequency
6249 * is stored as a divider into a 100MHz clock, and the
6250 * mode pixel clock is stored in units of 1KHz.
6251 * Hence the bw of each lane in terms of the mode signal
6252 * is:
6253 */
6254 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6255
6256 fdi_dotclock = adjusted_mode->crtc_clock;
6257
6258 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6259 pipe_config->pipe_bpp);
6260
6261 pipe_config->fdi_lanes = lane;
6262
6263 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6264 link_bw, &pipe_config->fdi_m_n, false);
6265
6266 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6267 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6268 pipe_config->pipe_bpp -= 2*3;
6269 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6270 pipe_config->pipe_bpp);
6271 needs_recompute = true;
6272 pipe_config->bw_constrained = true;
6273
6274 goto retry;
6275 }
6276
6277 if (needs_recompute)
6278 return RETRY;
6279
6280 return ret;
6281 }
6282
6283 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6284 struct intel_crtc_state *pipe_config)
6285 {
6286 if (pipe_config->ips_force_disable)
6287 return false;
6288
6289 if (pipe_config->pipe_bpp > 24)
6290 return false;
6291
6292 /* HSW can handle pixel rate up to cdclk? */
6293 if (IS_HASWELL(dev_priv))
6294 return true;
6295
6296 /*
6297 * We compare against max which means we must take
6298 * the increased cdclk requirement into account when
6299 * calculating the new cdclk.
6300 *
6301 * Should measure whether using a lower cdclk w/o IPS
6302 */
6303 return pipe_config->pixel_rate <=
6304 dev_priv->max_cdclk_freq * 95 / 100;
6305 }
6306
6307 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6308 struct intel_crtc_state *pipe_config)
6309 {
6310 struct drm_device *dev = crtc->base.dev;
6311 struct drm_i915_private *dev_priv = to_i915(dev);
6312
6313 pipe_config->ips_enabled = i915.enable_ips &&
6314 hsw_crtc_supports_ips(crtc) &&
6315 pipe_config_supports_ips(dev_priv, pipe_config);
6316 }
6317
6318 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6319 {
6320 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6321
6322 /* GDG double wide on either pipe, otherwise pipe A only */
6323 return INTEL_INFO(dev_priv)->gen < 4 &&
6324 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6325 }
6326
6327 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6328 {
6329 uint32_t pixel_rate;
6330
6331 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6332
6333 /*
6334 * We only use IF-ID interlacing. If we ever use
6335 * PF-ID we'll need to adjust the pixel_rate here.
6336 */
6337
6338 if (pipe_config->pch_pfit.enabled) {
6339 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6340 uint32_t pfit_size = pipe_config->pch_pfit.size;
6341
6342 pipe_w = pipe_config->pipe_src_w;
6343 pipe_h = pipe_config->pipe_src_h;
6344
6345 pfit_w = (pfit_size >> 16) & 0xFFFF;
6346 pfit_h = pfit_size & 0xFFFF;
6347 if (pipe_w < pfit_w)
6348 pipe_w = pfit_w;
6349 if (pipe_h < pfit_h)
6350 pipe_h = pfit_h;
6351
6352 if (WARN_ON(!pfit_w || !pfit_h))
6353 return pixel_rate;
6354
6355 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6356 pfit_w * pfit_h);
6357 }
6358
6359 return pixel_rate;
6360 }
6361
6362 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6363 {
6364 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6365
6366 if (HAS_GMCH_DISPLAY(dev_priv))
6367 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6368 crtc_state->pixel_rate =
6369 crtc_state->base.adjusted_mode.crtc_clock;
6370 else
6371 crtc_state->pixel_rate =
6372 ilk_pipe_pixel_rate(crtc_state);
6373 }
6374
6375 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6376 struct intel_crtc_state *pipe_config)
6377 {
6378 struct drm_device *dev = crtc->base.dev;
6379 struct drm_i915_private *dev_priv = to_i915(dev);
6380 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6381 int clock_limit = dev_priv->max_dotclk_freq;
6382
6383 if (INTEL_GEN(dev_priv) < 4) {
6384 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6385
6386 /*
6387 * Enable double wide mode when the dot clock
6388 * is > 90% of the (display) core speed.
6389 */
6390 if (intel_crtc_supports_double_wide(crtc) &&
6391 adjusted_mode->crtc_clock > clock_limit) {
6392 clock_limit = dev_priv->max_dotclk_freq;
6393 pipe_config->double_wide = true;
6394 }
6395 }
6396
6397 if (adjusted_mode->crtc_clock > clock_limit) {
6398 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6399 adjusted_mode->crtc_clock, clock_limit,
6400 yesno(pipe_config->double_wide));
6401 return -EINVAL;
6402 }
6403
6404 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6405 /*
6406 * There is only one pipe CSC unit per pipe, and we need that
6407 * for output conversion from RGB->YCBCR. So if CTM is already
6408 * applied we can't support YCBCR420 output.
6409 */
6410 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6411 return -EINVAL;
6412 }
6413
6414 /*
6415 * Pipe horizontal size must be even in:
6416 * - DVO ganged mode
6417 * - LVDS dual channel mode
6418 * - Double wide pipe
6419 */
6420 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6421 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6422 pipe_config->pipe_src_w &= ~1;
6423
6424 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6425 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6426 */
6427 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6428 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6429 return -EINVAL;
6430
6431 intel_crtc_compute_pixel_rate(pipe_config);
6432
6433 if (HAS_IPS(dev_priv))
6434 hsw_compute_ips_config(crtc, pipe_config);
6435
6436 if (pipe_config->has_pch_encoder)
6437 return ironlake_fdi_compute_config(crtc, pipe_config);
6438
6439 return 0;
6440 }
6441
6442 static void
6443 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6444 {
6445 while (*num > DATA_LINK_M_N_MASK ||
6446 *den > DATA_LINK_M_N_MASK) {
6447 *num >>= 1;
6448 *den >>= 1;
6449 }
6450 }
6451
6452 static void compute_m_n(unsigned int m, unsigned int n,
6453 uint32_t *ret_m, uint32_t *ret_n,
6454 bool reduce_m_n)
6455 {
6456 /*
6457 * Reduce M/N as much as possible without loss in precision. Several DP
6458 * dongles in particular seem to be fussy about too large *link* M/N
6459 * values. The passed in values are more likely to have the least
6460 * significant bits zero than M after rounding below, so do this first.
6461 */
6462 if (reduce_m_n) {
6463 while ((m & 1) == 0 && (n & 1) == 0) {
6464 m >>= 1;
6465 n >>= 1;
6466 }
6467 }
6468
6469 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6470 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6471 intel_reduce_m_n_ratio(ret_m, ret_n);
6472 }
6473
6474 void
6475 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6476 int pixel_clock, int link_clock,
6477 struct intel_link_m_n *m_n,
6478 bool reduce_m_n)
6479 {
6480 m_n->tu = 64;
6481
6482 compute_m_n(bits_per_pixel * pixel_clock,
6483 link_clock * nlanes * 8,
6484 &m_n->gmch_m, &m_n->gmch_n,
6485 reduce_m_n);
6486
6487 compute_m_n(pixel_clock, link_clock,
6488 &m_n->link_m, &m_n->link_n,
6489 reduce_m_n);
6490 }
6491
6492 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6493 {
6494 if (i915.panel_use_ssc >= 0)
6495 return i915.panel_use_ssc != 0;
6496 return dev_priv->vbt.lvds_use_ssc
6497 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6498 }
6499
6500 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6501 {
6502 return (1 << dpll->n) << 16 | dpll->m2;
6503 }
6504
6505 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6506 {
6507 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6508 }
6509
6510 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6511 struct intel_crtc_state *crtc_state,
6512 struct dpll *reduced_clock)
6513 {
6514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6515 u32 fp, fp2 = 0;
6516
6517 if (IS_PINEVIEW(dev_priv)) {
6518 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6519 if (reduced_clock)
6520 fp2 = pnv_dpll_compute_fp(reduced_clock);
6521 } else {
6522 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6523 if (reduced_clock)
6524 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6525 }
6526
6527 crtc_state->dpll_hw_state.fp0 = fp;
6528
6529 crtc->lowfreq_avail = false;
6530 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6531 reduced_clock) {
6532 crtc_state->dpll_hw_state.fp1 = fp2;
6533 crtc->lowfreq_avail = true;
6534 } else {
6535 crtc_state->dpll_hw_state.fp1 = fp;
6536 }
6537 }
6538
6539 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6540 pipe)
6541 {
6542 u32 reg_val;
6543
6544 /*
6545 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6546 * and set it to a reasonable value instead.
6547 */
6548 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6549 reg_val &= 0xffffff00;
6550 reg_val |= 0x00000030;
6551 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6552
6553 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6554 reg_val &= 0x00ffffff;
6555 reg_val |= 0x8c000000;
6556 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6557
6558 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6559 reg_val &= 0xffffff00;
6560 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6561
6562 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6563 reg_val &= 0x00ffffff;
6564 reg_val |= 0xb0000000;
6565 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6566 }
6567
6568 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6569 struct intel_link_m_n *m_n)
6570 {
6571 struct drm_device *dev = crtc->base.dev;
6572 struct drm_i915_private *dev_priv = to_i915(dev);
6573 int pipe = crtc->pipe;
6574
6575 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6576 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6577 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6578 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6579 }
6580
6581 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6582 struct intel_link_m_n *m_n,
6583 struct intel_link_m_n *m2_n2)
6584 {
6585 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6586 int pipe = crtc->pipe;
6587 enum transcoder transcoder = crtc->config->cpu_transcoder;
6588
6589 if (INTEL_GEN(dev_priv) >= 5) {
6590 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6591 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6592 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6593 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6594 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6595 * for gen < 8) and if DRRS is supported (to make sure the
6596 * registers are not unnecessarily accessed).
6597 */
6598 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6599 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6600 I915_WRITE(PIPE_DATA_M2(transcoder),
6601 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6602 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6603 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6604 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6605 }
6606 } else {
6607 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6608 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6609 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6610 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6611 }
6612 }
6613
6614 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6615 {
6616 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6617
6618 if (m_n == M1_N1) {
6619 dp_m_n = &crtc->config->dp_m_n;
6620 dp_m2_n2 = &crtc->config->dp_m2_n2;
6621 } else if (m_n == M2_N2) {
6622
6623 /*
6624 * M2_N2 registers are not supported. Hence m2_n2 divider value
6625 * needs to be programmed into M1_N1.
6626 */
6627 dp_m_n = &crtc->config->dp_m2_n2;
6628 } else {
6629 DRM_ERROR("Unsupported divider value\n");
6630 return;
6631 }
6632
6633 if (crtc->config->has_pch_encoder)
6634 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6635 else
6636 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6637 }
6638
6639 static void vlv_compute_dpll(struct intel_crtc *crtc,
6640 struct intel_crtc_state *pipe_config)
6641 {
6642 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6643 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6644 if (crtc->pipe != PIPE_A)
6645 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6646
6647 /* DPLL not used with DSI, but still need the rest set up */
6648 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6649 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6650 DPLL_EXT_BUFFER_ENABLE_VLV;
6651
6652 pipe_config->dpll_hw_state.dpll_md =
6653 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6654 }
6655
6656 static void chv_compute_dpll(struct intel_crtc *crtc,
6657 struct intel_crtc_state *pipe_config)
6658 {
6659 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6660 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6661 if (crtc->pipe != PIPE_A)
6662 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6663
6664 /* DPLL not used with DSI, but still need the rest set up */
6665 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6666 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6667
6668 pipe_config->dpll_hw_state.dpll_md =
6669 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6670 }
6671
6672 static void vlv_prepare_pll(struct intel_crtc *crtc,
6673 const struct intel_crtc_state *pipe_config)
6674 {
6675 struct drm_device *dev = crtc->base.dev;
6676 struct drm_i915_private *dev_priv = to_i915(dev);
6677 enum pipe pipe = crtc->pipe;
6678 u32 mdiv;
6679 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6680 u32 coreclk, reg_val;
6681
6682 /* Enable Refclk */
6683 I915_WRITE(DPLL(pipe),
6684 pipe_config->dpll_hw_state.dpll &
6685 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6686
6687 /* No need to actually set up the DPLL with DSI */
6688 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6689 return;
6690
6691 mutex_lock(&dev_priv->sb_lock);
6692
6693 bestn = pipe_config->dpll.n;
6694 bestm1 = pipe_config->dpll.m1;
6695 bestm2 = pipe_config->dpll.m2;
6696 bestp1 = pipe_config->dpll.p1;
6697 bestp2 = pipe_config->dpll.p2;
6698
6699 /* See eDP HDMI DPIO driver vbios notes doc */
6700
6701 /* PLL B needs special handling */
6702 if (pipe == PIPE_B)
6703 vlv_pllb_recal_opamp(dev_priv, pipe);
6704
6705 /* Set up Tx target for periodic Rcomp update */
6706 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6707
6708 /* Disable target IRef on PLL */
6709 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6710 reg_val &= 0x00ffffff;
6711 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6712
6713 /* Disable fast lock */
6714 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6715
6716 /* Set idtafcrecal before PLL is enabled */
6717 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6718 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6719 mdiv |= ((bestn << DPIO_N_SHIFT));
6720 mdiv |= (1 << DPIO_K_SHIFT);
6721
6722 /*
6723 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6724 * but we don't support that).
6725 * Note: don't use the DAC post divider as it seems unstable.
6726 */
6727 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6728 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6729
6730 mdiv |= DPIO_ENABLE_CALIBRATION;
6731 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6732
6733 /* Set HBR and RBR LPF coefficients */
6734 if (pipe_config->port_clock == 162000 ||
6735 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6736 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6737 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6738 0x009f0003);
6739 else
6740 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6741 0x00d0000f);
6742
6743 if (intel_crtc_has_dp_encoder(pipe_config)) {
6744 /* Use SSC source */
6745 if (pipe == PIPE_A)
6746 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6747 0x0df40000);
6748 else
6749 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6750 0x0df70000);
6751 } else { /* HDMI or VGA */
6752 /* Use bend source */
6753 if (pipe == PIPE_A)
6754 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6755 0x0df70000);
6756 else
6757 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6758 0x0df40000);
6759 }
6760
6761 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6762 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6763 if (intel_crtc_has_dp_encoder(crtc->config))
6764 coreclk |= 0x01000000;
6765 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6766
6767 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6768 mutex_unlock(&dev_priv->sb_lock);
6769 }
6770
6771 static void chv_prepare_pll(struct intel_crtc *crtc,
6772 const struct intel_crtc_state *pipe_config)
6773 {
6774 struct drm_device *dev = crtc->base.dev;
6775 struct drm_i915_private *dev_priv = to_i915(dev);
6776 enum pipe pipe = crtc->pipe;
6777 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6778 u32 loopfilter, tribuf_calcntr;
6779 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6780 u32 dpio_val;
6781 int vco;
6782
6783 /* Enable Refclk and SSC */
6784 I915_WRITE(DPLL(pipe),
6785 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6786
6787 /* No need to actually set up the DPLL with DSI */
6788 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6789 return;
6790
6791 bestn = pipe_config->dpll.n;
6792 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6793 bestm1 = pipe_config->dpll.m1;
6794 bestm2 = pipe_config->dpll.m2 >> 22;
6795 bestp1 = pipe_config->dpll.p1;
6796 bestp2 = pipe_config->dpll.p2;
6797 vco = pipe_config->dpll.vco;
6798 dpio_val = 0;
6799 loopfilter = 0;
6800
6801 mutex_lock(&dev_priv->sb_lock);
6802
6803 /* p1 and p2 divider */
6804 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6805 5 << DPIO_CHV_S1_DIV_SHIFT |
6806 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6807 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6808 1 << DPIO_CHV_K_DIV_SHIFT);
6809
6810 /* Feedback post-divider - m2 */
6811 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6812
6813 /* Feedback refclk divider - n and m1 */
6814 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6815 DPIO_CHV_M1_DIV_BY_2 |
6816 1 << DPIO_CHV_N_DIV_SHIFT);
6817
6818 /* M2 fraction division */
6819 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6820
6821 /* M2 fraction division enable */
6822 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6823 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6824 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6825 if (bestm2_frac)
6826 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6827 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6828
6829 /* Program digital lock detect threshold */
6830 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6831 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6832 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6833 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6834 if (!bestm2_frac)
6835 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6836 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6837
6838 /* Loop filter */
6839 if (vco == 5400000) {
6840 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6841 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6842 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6843 tribuf_calcntr = 0x9;
6844 } else if (vco <= 6200000) {
6845 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6846 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6847 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6848 tribuf_calcntr = 0x9;
6849 } else if (vco <= 6480000) {
6850 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6851 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6852 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6853 tribuf_calcntr = 0x8;
6854 } else {
6855 /* Not supported. Apply the same limits as in the max case */
6856 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6857 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6858 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6859 tribuf_calcntr = 0;
6860 }
6861 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6862
6863 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6864 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6865 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6866 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6867
6868 /* AFC Recal */
6869 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6870 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6871 DPIO_AFC_RECAL);
6872
6873 mutex_unlock(&dev_priv->sb_lock);
6874 }
6875
6876 /**
6877 * vlv_force_pll_on - forcibly enable just the PLL
6878 * @dev_priv: i915 private structure
6879 * @pipe: pipe PLL to enable
6880 * @dpll: PLL configuration
6881 *
6882 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6883 * in cases where we need the PLL enabled even when @pipe is not going to
6884 * be enabled.
6885 */
6886 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6887 const struct dpll *dpll)
6888 {
6889 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6890 struct intel_crtc_state *pipe_config;
6891
6892 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6893 if (!pipe_config)
6894 return -ENOMEM;
6895
6896 pipe_config->base.crtc = &crtc->base;
6897 pipe_config->pixel_multiplier = 1;
6898 pipe_config->dpll = *dpll;
6899
6900 if (IS_CHERRYVIEW(dev_priv)) {
6901 chv_compute_dpll(crtc, pipe_config);
6902 chv_prepare_pll(crtc, pipe_config);
6903 chv_enable_pll(crtc, pipe_config);
6904 } else {
6905 vlv_compute_dpll(crtc, pipe_config);
6906 vlv_prepare_pll(crtc, pipe_config);
6907 vlv_enable_pll(crtc, pipe_config);
6908 }
6909
6910 kfree(pipe_config);
6911
6912 return 0;
6913 }
6914
6915 /**
6916 * vlv_force_pll_off - forcibly disable just the PLL
6917 * @dev_priv: i915 private structure
6918 * @pipe: pipe PLL to disable
6919 *
6920 * Disable the PLL for @pipe. To be used in cases where we need
6921 * the PLL enabled even when @pipe is not going to be enabled.
6922 */
6923 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6924 {
6925 if (IS_CHERRYVIEW(dev_priv))
6926 chv_disable_pll(dev_priv, pipe);
6927 else
6928 vlv_disable_pll(dev_priv, pipe);
6929 }
6930
6931 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6932 struct intel_crtc_state *crtc_state,
6933 struct dpll *reduced_clock)
6934 {
6935 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6936 u32 dpll;
6937 struct dpll *clock = &crtc_state->dpll;
6938
6939 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6940
6941 dpll = DPLL_VGA_MODE_DIS;
6942
6943 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6944 dpll |= DPLLB_MODE_LVDS;
6945 else
6946 dpll |= DPLLB_MODE_DAC_SERIAL;
6947
6948 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6949 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6950 dpll |= (crtc_state->pixel_multiplier - 1)
6951 << SDVO_MULTIPLIER_SHIFT_HIRES;
6952 }
6953
6954 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6955 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6956 dpll |= DPLL_SDVO_HIGH_SPEED;
6957
6958 if (intel_crtc_has_dp_encoder(crtc_state))
6959 dpll |= DPLL_SDVO_HIGH_SPEED;
6960
6961 /* compute bitmask from p1 value */
6962 if (IS_PINEVIEW(dev_priv))
6963 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6964 else {
6965 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6966 if (IS_G4X(dev_priv) && reduced_clock)
6967 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6968 }
6969 switch (clock->p2) {
6970 case 5:
6971 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6972 break;
6973 case 7:
6974 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6975 break;
6976 case 10:
6977 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6978 break;
6979 case 14:
6980 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6981 break;
6982 }
6983 if (INTEL_GEN(dev_priv) >= 4)
6984 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6985
6986 if (crtc_state->sdvo_tv_clock)
6987 dpll |= PLL_REF_INPUT_TVCLKINBC;
6988 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6989 intel_panel_use_ssc(dev_priv))
6990 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6991 else
6992 dpll |= PLL_REF_INPUT_DREFCLK;
6993
6994 dpll |= DPLL_VCO_ENABLE;
6995 crtc_state->dpll_hw_state.dpll = dpll;
6996
6997 if (INTEL_GEN(dev_priv) >= 4) {
6998 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6999 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7000 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7001 }
7002 }
7003
7004 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7005 struct intel_crtc_state *crtc_state,
7006 struct dpll *reduced_clock)
7007 {
7008 struct drm_device *dev = crtc->base.dev;
7009 struct drm_i915_private *dev_priv = to_i915(dev);
7010 u32 dpll;
7011 struct dpll *clock = &crtc_state->dpll;
7012
7013 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7014
7015 dpll = DPLL_VGA_MODE_DIS;
7016
7017 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7018 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7019 } else {
7020 if (clock->p1 == 2)
7021 dpll |= PLL_P1_DIVIDE_BY_TWO;
7022 else
7023 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7024 if (clock->p2 == 4)
7025 dpll |= PLL_P2_DIVIDE_BY_4;
7026 }
7027
7028 if (!IS_I830(dev_priv) &&
7029 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7030 dpll |= DPLL_DVO_2X_MODE;
7031
7032 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7033 intel_panel_use_ssc(dev_priv))
7034 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7035 else
7036 dpll |= PLL_REF_INPUT_DREFCLK;
7037
7038 dpll |= DPLL_VCO_ENABLE;
7039 crtc_state->dpll_hw_state.dpll = dpll;
7040 }
7041
7042 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7043 {
7044 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7045 enum pipe pipe = intel_crtc->pipe;
7046 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7047 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7048 uint32_t crtc_vtotal, crtc_vblank_end;
7049 int vsyncshift = 0;
7050
7051 /* We need to be careful not to changed the adjusted mode, for otherwise
7052 * the hw state checker will get angry at the mismatch. */
7053 crtc_vtotal = adjusted_mode->crtc_vtotal;
7054 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7055
7056 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7057 /* the chip adds 2 halflines automatically */
7058 crtc_vtotal -= 1;
7059 crtc_vblank_end -= 1;
7060
7061 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7062 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7063 else
7064 vsyncshift = adjusted_mode->crtc_hsync_start -
7065 adjusted_mode->crtc_htotal / 2;
7066 if (vsyncshift < 0)
7067 vsyncshift += adjusted_mode->crtc_htotal;
7068 }
7069
7070 if (INTEL_GEN(dev_priv) > 3)
7071 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7072
7073 I915_WRITE(HTOTAL(cpu_transcoder),
7074 (adjusted_mode->crtc_hdisplay - 1) |
7075 ((adjusted_mode->crtc_htotal - 1) << 16));
7076 I915_WRITE(HBLANK(cpu_transcoder),
7077 (adjusted_mode->crtc_hblank_start - 1) |
7078 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7079 I915_WRITE(HSYNC(cpu_transcoder),
7080 (adjusted_mode->crtc_hsync_start - 1) |
7081 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7082
7083 I915_WRITE(VTOTAL(cpu_transcoder),
7084 (adjusted_mode->crtc_vdisplay - 1) |
7085 ((crtc_vtotal - 1) << 16));
7086 I915_WRITE(VBLANK(cpu_transcoder),
7087 (adjusted_mode->crtc_vblank_start - 1) |
7088 ((crtc_vblank_end - 1) << 16));
7089 I915_WRITE(VSYNC(cpu_transcoder),
7090 (adjusted_mode->crtc_vsync_start - 1) |
7091 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7092
7093 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7094 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7095 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7096 * bits. */
7097 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7098 (pipe == PIPE_B || pipe == PIPE_C))
7099 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7100
7101 }
7102
7103 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7104 {
7105 struct drm_device *dev = intel_crtc->base.dev;
7106 struct drm_i915_private *dev_priv = to_i915(dev);
7107 enum pipe pipe = intel_crtc->pipe;
7108
7109 /* pipesrc controls the size that is scaled from, which should
7110 * always be the user's requested size.
7111 */
7112 I915_WRITE(PIPESRC(pipe),
7113 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7114 (intel_crtc->config->pipe_src_h - 1));
7115 }
7116
7117 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7118 struct intel_crtc_state *pipe_config)
7119 {
7120 struct drm_device *dev = crtc->base.dev;
7121 struct drm_i915_private *dev_priv = to_i915(dev);
7122 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7123 uint32_t tmp;
7124
7125 tmp = I915_READ(HTOTAL(cpu_transcoder));
7126 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7127 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7128 tmp = I915_READ(HBLANK(cpu_transcoder));
7129 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7130 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7131 tmp = I915_READ(HSYNC(cpu_transcoder));
7132 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7133 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7134
7135 tmp = I915_READ(VTOTAL(cpu_transcoder));
7136 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7137 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7138 tmp = I915_READ(VBLANK(cpu_transcoder));
7139 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7140 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7141 tmp = I915_READ(VSYNC(cpu_transcoder));
7142 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7143 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7144
7145 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7146 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7147 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7148 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7149 }
7150 }
7151
7152 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7153 struct intel_crtc_state *pipe_config)
7154 {
7155 struct drm_device *dev = crtc->base.dev;
7156 struct drm_i915_private *dev_priv = to_i915(dev);
7157 u32 tmp;
7158
7159 tmp = I915_READ(PIPESRC(crtc->pipe));
7160 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7161 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7162
7163 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7164 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7165 }
7166
7167 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7168 struct intel_crtc_state *pipe_config)
7169 {
7170 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7171 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7172 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7173 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7174
7175 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7176 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7177 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7178 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7179
7180 mode->flags = pipe_config->base.adjusted_mode.flags;
7181 mode->type = DRM_MODE_TYPE_DRIVER;
7182
7183 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7184
7185 mode->hsync = drm_mode_hsync(mode);
7186 mode->vrefresh = drm_mode_vrefresh(mode);
7187 drm_mode_set_name(mode);
7188 }
7189
7190 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7191 {
7192 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7193 uint32_t pipeconf;
7194
7195 pipeconf = 0;
7196
7197 /* we keep both pipes enabled on 830 */
7198 if (IS_I830(dev_priv))
7199 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7200
7201 if (intel_crtc->config->double_wide)
7202 pipeconf |= PIPECONF_DOUBLE_WIDE;
7203
7204 /* only g4x and later have fancy bpc/dither controls */
7205 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7206 IS_CHERRYVIEW(dev_priv)) {
7207 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7208 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7209 pipeconf |= PIPECONF_DITHER_EN |
7210 PIPECONF_DITHER_TYPE_SP;
7211
7212 switch (intel_crtc->config->pipe_bpp) {
7213 case 18:
7214 pipeconf |= PIPECONF_6BPC;
7215 break;
7216 case 24:
7217 pipeconf |= PIPECONF_8BPC;
7218 break;
7219 case 30:
7220 pipeconf |= PIPECONF_10BPC;
7221 break;
7222 default:
7223 /* Case prevented by intel_choose_pipe_bpp_dither. */
7224 BUG();
7225 }
7226 }
7227
7228 if (HAS_PIPE_CXSR(dev_priv)) {
7229 if (intel_crtc->lowfreq_avail) {
7230 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7231 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7232 } else {
7233 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7234 }
7235 }
7236
7237 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7238 if (INTEL_GEN(dev_priv) < 4 ||
7239 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7240 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7241 else
7242 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7243 } else
7244 pipeconf |= PIPECONF_PROGRESSIVE;
7245
7246 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7247 intel_crtc->config->limited_color_range)
7248 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7249
7250 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7251 POSTING_READ(PIPECONF(intel_crtc->pipe));
7252 }
7253
7254 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7255 struct intel_crtc_state *crtc_state)
7256 {
7257 struct drm_device *dev = crtc->base.dev;
7258 struct drm_i915_private *dev_priv = to_i915(dev);
7259 const struct intel_limit *limit;
7260 int refclk = 48000;
7261
7262 memset(&crtc_state->dpll_hw_state, 0,
7263 sizeof(crtc_state->dpll_hw_state));
7264
7265 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7266 if (intel_panel_use_ssc(dev_priv)) {
7267 refclk = dev_priv->vbt.lvds_ssc_freq;
7268 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7269 }
7270
7271 limit = &intel_limits_i8xx_lvds;
7272 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7273 limit = &intel_limits_i8xx_dvo;
7274 } else {
7275 limit = &intel_limits_i8xx_dac;
7276 }
7277
7278 if (!crtc_state->clock_set &&
7279 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7280 refclk, NULL, &crtc_state->dpll)) {
7281 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7282 return -EINVAL;
7283 }
7284
7285 i8xx_compute_dpll(crtc, crtc_state, NULL);
7286
7287 return 0;
7288 }
7289
7290 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7291 struct intel_crtc_state *crtc_state)
7292 {
7293 struct drm_device *dev = crtc->base.dev;
7294 struct drm_i915_private *dev_priv = to_i915(dev);
7295 const struct intel_limit *limit;
7296 int refclk = 96000;
7297
7298 memset(&crtc_state->dpll_hw_state, 0,
7299 sizeof(crtc_state->dpll_hw_state));
7300
7301 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7302 if (intel_panel_use_ssc(dev_priv)) {
7303 refclk = dev_priv->vbt.lvds_ssc_freq;
7304 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7305 }
7306
7307 if (intel_is_dual_link_lvds(dev))
7308 limit = &intel_limits_g4x_dual_channel_lvds;
7309 else
7310 limit = &intel_limits_g4x_single_channel_lvds;
7311 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7312 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7313 limit = &intel_limits_g4x_hdmi;
7314 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7315 limit = &intel_limits_g4x_sdvo;
7316 } else {
7317 /* The option is for other outputs */
7318 limit = &intel_limits_i9xx_sdvo;
7319 }
7320
7321 if (!crtc_state->clock_set &&
7322 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7323 refclk, NULL, &crtc_state->dpll)) {
7324 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7325 return -EINVAL;
7326 }
7327
7328 i9xx_compute_dpll(crtc, crtc_state, NULL);
7329
7330 return 0;
7331 }
7332
7333 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7334 struct intel_crtc_state *crtc_state)
7335 {
7336 struct drm_device *dev = crtc->base.dev;
7337 struct drm_i915_private *dev_priv = to_i915(dev);
7338 const struct intel_limit *limit;
7339 int refclk = 96000;
7340
7341 memset(&crtc_state->dpll_hw_state, 0,
7342 sizeof(crtc_state->dpll_hw_state));
7343
7344 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7345 if (intel_panel_use_ssc(dev_priv)) {
7346 refclk = dev_priv->vbt.lvds_ssc_freq;
7347 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7348 }
7349
7350 limit = &intel_limits_pineview_lvds;
7351 } else {
7352 limit = &intel_limits_pineview_sdvo;
7353 }
7354
7355 if (!crtc_state->clock_set &&
7356 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7357 refclk, NULL, &crtc_state->dpll)) {
7358 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7359 return -EINVAL;
7360 }
7361
7362 i9xx_compute_dpll(crtc, crtc_state, NULL);
7363
7364 return 0;
7365 }
7366
7367 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7368 struct intel_crtc_state *crtc_state)
7369 {
7370 struct drm_device *dev = crtc->base.dev;
7371 struct drm_i915_private *dev_priv = to_i915(dev);
7372 const struct intel_limit *limit;
7373 int refclk = 96000;
7374
7375 memset(&crtc_state->dpll_hw_state, 0,
7376 sizeof(crtc_state->dpll_hw_state));
7377
7378 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7379 if (intel_panel_use_ssc(dev_priv)) {
7380 refclk = dev_priv->vbt.lvds_ssc_freq;
7381 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7382 }
7383
7384 limit = &intel_limits_i9xx_lvds;
7385 } else {
7386 limit = &intel_limits_i9xx_sdvo;
7387 }
7388
7389 if (!crtc_state->clock_set &&
7390 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7391 refclk, NULL, &crtc_state->dpll)) {
7392 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7393 return -EINVAL;
7394 }
7395
7396 i9xx_compute_dpll(crtc, crtc_state, NULL);
7397
7398 return 0;
7399 }
7400
7401 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7402 struct intel_crtc_state *crtc_state)
7403 {
7404 int refclk = 100000;
7405 const struct intel_limit *limit = &intel_limits_chv;
7406
7407 memset(&crtc_state->dpll_hw_state, 0,
7408 sizeof(crtc_state->dpll_hw_state));
7409
7410 if (!crtc_state->clock_set &&
7411 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7412 refclk, NULL, &crtc_state->dpll)) {
7413 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7414 return -EINVAL;
7415 }
7416
7417 chv_compute_dpll(crtc, crtc_state);
7418
7419 return 0;
7420 }
7421
7422 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7423 struct intel_crtc_state *crtc_state)
7424 {
7425 int refclk = 100000;
7426 const struct intel_limit *limit = &intel_limits_vlv;
7427
7428 memset(&crtc_state->dpll_hw_state, 0,
7429 sizeof(crtc_state->dpll_hw_state));
7430
7431 if (!crtc_state->clock_set &&
7432 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7433 refclk, NULL, &crtc_state->dpll)) {
7434 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7435 return -EINVAL;
7436 }
7437
7438 vlv_compute_dpll(crtc, crtc_state);
7439
7440 return 0;
7441 }
7442
7443 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7444 struct intel_crtc_state *pipe_config)
7445 {
7446 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7447 uint32_t tmp;
7448
7449 if (INTEL_GEN(dev_priv) <= 3 &&
7450 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7451 return;
7452
7453 tmp = I915_READ(PFIT_CONTROL);
7454 if (!(tmp & PFIT_ENABLE))
7455 return;
7456
7457 /* Check whether the pfit is attached to our pipe. */
7458 if (INTEL_GEN(dev_priv) < 4) {
7459 if (crtc->pipe != PIPE_B)
7460 return;
7461 } else {
7462 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7463 return;
7464 }
7465
7466 pipe_config->gmch_pfit.control = tmp;
7467 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7468 }
7469
7470 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7471 struct intel_crtc_state *pipe_config)
7472 {
7473 struct drm_device *dev = crtc->base.dev;
7474 struct drm_i915_private *dev_priv = to_i915(dev);
7475 int pipe = pipe_config->cpu_transcoder;
7476 struct dpll clock;
7477 u32 mdiv;
7478 int refclk = 100000;
7479
7480 /* In case of DSI, DPLL will not be used */
7481 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7482 return;
7483
7484 mutex_lock(&dev_priv->sb_lock);
7485 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7486 mutex_unlock(&dev_priv->sb_lock);
7487
7488 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7489 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7490 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7491 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7492 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7493
7494 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7495 }
7496
7497 static void
7498 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7499 struct intel_initial_plane_config *plane_config)
7500 {
7501 struct drm_device *dev = crtc->base.dev;
7502 struct drm_i915_private *dev_priv = to_i915(dev);
7503 u32 val, base, offset;
7504 int pipe = crtc->pipe, plane = crtc->plane;
7505 int fourcc, pixel_format;
7506 unsigned int aligned_height;
7507 struct drm_framebuffer *fb;
7508 struct intel_framebuffer *intel_fb;
7509
7510 val = I915_READ(DSPCNTR(plane));
7511 if (!(val & DISPLAY_PLANE_ENABLE))
7512 return;
7513
7514 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7515 if (!intel_fb) {
7516 DRM_DEBUG_KMS("failed to alloc fb\n");
7517 return;
7518 }
7519
7520 fb = &intel_fb->base;
7521
7522 fb->dev = dev;
7523
7524 if (INTEL_GEN(dev_priv) >= 4) {
7525 if (val & DISPPLANE_TILED) {
7526 plane_config->tiling = I915_TILING_X;
7527 fb->modifier = I915_FORMAT_MOD_X_TILED;
7528 }
7529 }
7530
7531 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7532 fourcc = i9xx_format_to_fourcc(pixel_format);
7533 fb->format = drm_format_info(fourcc);
7534
7535 if (INTEL_GEN(dev_priv) >= 4) {
7536 if (plane_config->tiling)
7537 offset = I915_READ(DSPTILEOFF(plane));
7538 else
7539 offset = I915_READ(DSPLINOFF(plane));
7540 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7541 } else {
7542 base = I915_READ(DSPADDR(plane));
7543 }
7544 plane_config->base = base;
7545
7546 val = I915_READ(PIPESRC(pipe));
7547 fb->width = ((val >> 16) & 0xfff) + 1;
7548 fb->height = ((val >> 0) & 0xfff) + 1;
7549
7550 val = I915_READ(DSPSTRIDE(pipe));
7551 fb->pitches[0] = val & 0xffffffc0;
7552
7553 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7554
7555 plane_config->size = fb->pitches[0] * aligned_height;
7556
7557 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7558 pipe_name(pipe), plane, fb->width, fb->height,
7559 fb->format->cpp[0] * 8, base, fb->pitches[0],
7560 plane_config->size);
7561
7562 plane_config->fb = intel_fb;
7563 }
7564
7565 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7566 struct intel_crtc_state *pipe_config)
7567 {
7568 struct drm_device *dev = crtc->base.dev;
7569 struct drm_i915_private *dev_priv = to_i915(dev);
7570 int pipe = pipe_config->cpu_transcoder;
7571 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7572 struct dpll clock;
7573 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7574 int refclk = 100000;
7575
7576 /* In case of DSI, DPLL will not be used */
7577 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7578 return;
7579
7580 mutex_lock(&dev_priv->sb_lock);
7581 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7582 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7583 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7584 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7585 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7586 mutex_unlock(&dev_priv->sb_lock);
7587
7588 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7589 clock.m2 = (pll_dw0 & 0xff) << 22;
7590 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7591 clock.m2 |= pll_dw2 & 0x3fffff;
7592 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7593 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7594 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7595
7596 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7597 }
7598
7599 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7600 struct intel_crtc_state *pipe_config)
7601 {
7602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7603 enum intel_display_power_domain power_domain;
7604 uint32_t tmp;
7605 bool ret;
7606
7607 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7608 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7609 return false;
7610
7611 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7612 pipe_config->shared_dpll = NULL;
7613
7614 ret = false;
7615
7616 tmp = I915_READ(PIPECONF(crtc->pipe));
7617 if (!(tmp & PIPECONF_ENABLE))
7618 goto out;
7619
7620 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7621 IS_CHERRYVIEW(dev_priv)) {
7622 switch (tmp & PIPECONF_BPC_MASK) {
7623 case PIPECONF_6BPC:
7624 pipe_config->pipe_bpp = 18;
7625 break;
7626 case PIPECONF_8BPC:
7627 pipe_config->pipe_bpp = 24;
7628 break;
7629 case PIPECONF_10BPC:
7630 pipe_config->pipe_bpp = 30;
7631 break;
7632 default:
7633 break;
7634 }
7635 }
7636
7637 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7638 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7639 pipe_config->limited_color_range = true;
7640
7641 if (INTEL_GEN(dev_priv) < 4)
7642 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7643
7644 intel_get_pipe_timings(crtc, pipe_config);
7645 intel_get_pipe_src_size(crtc, pipe_config);
7646
7647 i9xx_get_pfit_config(crtc, pipe_config);
7648
7649 if (INTEL_GEN(dev_priv) >= 4) {
7650 /* No way to read it out on pipes B and C */
7651 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7652 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7653 else
7654 tmp = I915_READ(DPLL_MD(crtc->pipe));
7655 pipe_config->pixel_multiplier =
7656 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7657 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7658 pipe_config->dpll_hw_state.dpll_md = tmp;
7659 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7660 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7661 tmp = I915_READ(DPLL(crtc->pipe));
7662 pipe_config->pixel_multiplier =
7663 ((tmp & SDVO_MULTIPLIER_MASK)
7664 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7665 } else {
7666 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7667 * port and will be fixed up in the encoder->get_config
7668 * function. */
7669 pipe_config->pixel_multiplier = 1;
7670 }
7671 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7672 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7673 /*
7674 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7675 * on 830. Filter it out here so that we don't
7676 * report errors due to that.
7677 */
7678 if (IS_I830(dev_priv))
7679 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7680
7681 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7682 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7683 } else {
7684 /* Mask out read-only status bits. */
7685 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7686 DPLL_PORTC_READY_MASK |
7687 DPLL_PORTB_READY_MASK);
7688 }
7689
7690 if (IS_CHERRYVIEW(dev_priv))
7691 chv_crtc_clock_get(crtc, pipe_config);
7692 else if (IS_VALLEYVIEW(dev_priv))
7693 vlv_crtc_clock_get(crtc, pipe_config);
7694 else
7695 i9xx_crtc_clock_get(crtc, pipe_config);
7696
7697 /*
7698 * Normally the dotclock is filled in by the encoder .get_config()
7699 * but in case the pipe is enabled w/o any ports we need a sane
7700 * default.
7701 */
7702 pipe_config->base.adjusted_mode.crtc_clock =
7703 pipe_config->port_clock / pipe_config->pixel_multiplier;
7704
7705 ret = true;
7706
7707 out:
7708 intel_display_power_put(dev_priv, power_domain);
7709
7710 return ret;
7711 }
7712
7713 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7714 {
7715 struct intel_encoder *encoder;
7716 int i;
7717 u32 val, final;
7718 bool has_lvds = false;
7719 bool has_cpu_edp = false;
7720 bool has_panel = false;
7721 bool has_ck505 = false;
7722 bool can_ssc = false;
7723 bool using_ssc_source = false;
7724
7725 /* We need to take the global config into account */
7726 for_each_intel_encoder(&dev_priv->drm, encoder) {
7727 switch (encoder->type) {
7728 case INTEL_OUTPUT_LVDS:
7729 has_panel = true;
7730 has_lvds = true;
7731 break;
7732 case INTEL_OUTPUT_EDP:
7733 has_panel = true;
7734 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7735 has_cpu_edp = true;
7736 break;
7737 default:
7738 break;
7739 }
7740 }
7741
7742 if (HAS_PCH_IBX(dev_priv)) {
7743 has_ck505 = dev_priv->vbt.display_clock_mode;
7744 can_ssc = has_ck505;
7745 } else {
7746 has_ck505 = false;
7747 can_ssc = true;
7748 }
7749
7750 /* Check if any DPLLs are using the SSC source */
7751 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7752 u32 temp = I915_READ(PCH_DPLL(i));
7753
7754 if (!(temp & DPLL_VCO_ENABLE))
7755 continue;
7756
7757 if ((temp & PLL_REF_INPUT_MASK) ==
7758 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7759 using_ssc_source = true;
7760 break;
7761 }
7762 }
7763
7764 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7765 has_panel, has_lvds, has_ck505, using_ssc_source);
7766
7767 /* Ironlake: try to setup display ref clock before DPLL
7768 * enabling. This is only under driver's control after
7769 * PCH B stepping, previous chipset stepping should be
7770 * ignoring this setting.
7771 */
7772 val = I915_READ(PCH_DREF_CONTROL);
7773
7774 /* As we must carefully and slowly disable/enable each source in turn,
7775 * compute the final state we want first and check if we need to
7776 * make any changes at all.
7777 */
7778 final = val;
7779 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7780 if (has_ck505)
7781 final |= DREF_NONSPREAD_CK505_ENABLE;
7782 else
7783 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7784
7785 final &= ~DREF_SSC_SOURCE_MASK;
7786 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7787 final &= ~DREF_SSC1_ENABLE;
7788
7789 if (has_panel) {
7790 final |= DREF_SSC_SOURCE_ENABLE;
7791
7792 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7793 final |= DREF_SSC1_ENABLE;
7794
7795 if (has_cpu_edp) {
7796 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7797 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7798 else
7799 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7800 } else
7801 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7802 } else if (using_ssc_source) {
7803 final |= DREF_SSC_SOURCE_ENABLE;
7804 final |= DREF_SSC1_ENABLE;
7805 }
7806
7807 if (final == val)
7808 return;
7809
7810 /* Always enable nonspread source */
7811 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7812
7813 if (has_ck505)
7814 val |= DREF_NONSPREAD_CK505_ENABLE;
7815 else
7816 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7817
7818 if (has_panel) {
7819 val &= ~DREF_SSC_SOURCE_MASK;
7820 val |= DREF_SSC_SOURCE_ENABLE;
7821
7822 /* SSC must be turned on before enabling the CPU output */
7823 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7824 DRM_DEBUG_KMS("Using SSC on panel\n");
7825 val |= DREF_SSC1_ENABLE;
7826 } else
7827 val &= ~DREF_SSC1_ENABLE;
7828
7829 /* Get SSC going before enabling the outputs */
7830 I915_WRITE(PCH_DREF_CONTROL, val);
7831 POSTING_READ(PCH_DREF_CONTROL);
7832 udelay(200);
7833
7834 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7835
7836 /* Enable CPU source on CPU attached eDP */
7837 if (has_cpu_edp) {
7838 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7839 DRM_DEBUG_KMS("Using SSC on eDP\n");
7840 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7841 } else
7842 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7843 } else
7844 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7845
7846 I915_WRITE(PCH_DREF_CONTROL, val);
7847 POSTING_READ(PCH_DREF_CONTROL);
7848 udelay(200);
7849 } else {
7850 DRM_DEBUG_KMS("Disabling CPU source output\n");
7851
7852 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7853
7854 /* Turn off CPU output */
7855 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7856
7857 I915_WRITE(PCH_DREF_CONTROL, val);
7858 POSTING_READ(PCH_DREF_CONTROL);
7859 udelay(200);
7860
7861 if (!using_ssc_source) {
7862 DRM_DEBUG_KMS("Disabling SSC source\n");
7863
7864 /* Turn off the SSC source */
7865 val &= ~DREF_SSC_SOURCE_MASK;
7866 val |= DREF_SSC_SOURCE_DISABLE;
7867
7868 /* Turn off SSC1 */
7869 val &= ~DREF_SSC1_ENABLE;
7870
7871 I915_WRITE(PCH_DREF_CONTROL, val);
7872 POSTING_READ(PCH_DREF_CONTROL);
7873 udelay(200);
7874 }
7875 }
7876
7877 BUG_ON(val != final);
7878 }
7879
7880 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7881 {
7882 uint32_t tmp;
7883
7884 tmp = I915_READ(SOUTH_CHICKEN2);
7885 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7886 I915_WRITE(SOUTH_CHICKEN2, tmp);
7887
7888 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7889 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7890 DRM_ERROR("FDI mPHY reset assert timeout\n");
7891
7892 tmp = I915_READ(SOUTH_CHICKEN2);
7893 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7894 I915_WRITE(SOUTH_CHICKEN2, tmp);
7895
7896 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7897 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7898 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7899 }
7900
7901 /* WaMPhyProgramming:hsw */
7902 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7903 {
7904 uint32_t tmp;
7905
7906 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7907 tmp &= ~(0xFF << 24);
7908 tmp |= (0x12 << 24);
7909 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7910
7911 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7912 tmp |= (1 << 11);
7913 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7914
7915 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7916 tmp |= (1 << 11);
7917 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7918
7919 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7920 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7921 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7922
7923 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7924 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7925 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7926
7927 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7928 tmp &= ~(7 << 13);
7929 tmp |= (5 << 13);
7930 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7931
7932 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7933 tmp &= ~(7 << 13);
7934 tmp |= (5 << 13);
7935 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7936
7937 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7938 tmp &= ~0xFF;
7939 tmp |= 0x1C;
7940 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7941
7942 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7943 tmp &= ~0xFF;
7944 tmp |= 0x1C;
7945 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7946
7947 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7948 tmp &= ~(0xFF << 16);
7949 tmp |= (0x1C << 16);
7950 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7951
7952 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7953 tmp &= ~(0xFF << 16);
7954 tmp |= (0x1C << 16);
7955 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7956
7957 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7958 tmp |= (1 << 27);
7959 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7960
7961 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7962 tmp |= (1 << 27);
7963 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7964
7965 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7966 tmp &= ~(0xF << 28);
7967 tmp |= (4 << 28);
7968 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7969
7970 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7971 tmp &= ~(0xF << 28);
7972 tmp |= (4 << 28);
7973 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7974 }
7975
7976 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7977 * Programming" based on the parameters passed:
7978 * - Sequence to enable CLKOUT_DP
7979 * - Sequence to enable CLKOUT_DP without spread
7980 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7981 */
7982 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7983 bool with_spread, bool with_fdi)
7984 {
7985 uint32_t reg, tmp;
7986
7987 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7988 with_spread = true;
7989 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7990 with_fdi, "LP PCH doesn't have FDI\n"))
7991 with_fdi = false;
7992
7993 mutex_lock(&dev_priv->sb_lock);
7994
7995 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7996 tmp &= ~SBI_SSCCTL_DISABLE;
7997 tmp |= SBI_SSCCTL_PATHALT;
7998 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7999
8000 udelay(24);
8001
8002 if (with_spread) {
8003 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8004 tmp &= ~SBI_SSCCTL_PATHALT;
8005 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8006
8007 if (with_fdi) {
8008 lpt_reset_fdi_mphy(dev_priv);
8009 lpt_program_fdi_mphy(dev_priv);
8010 }
8011 }
8012
8013 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8014 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8015 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8016 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8017
8018 mutex_unlock(&dev_priv->sb_lock);
8019 }
8020
8021 /* Sequence to disable CLKOUT_DP */
8022 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8023 {
8024 uint32_t reg, tmp;
8025
8026 mutex_lock(&dev_priv->sb_lock);
8027
8028 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8029 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8030 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8031 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8032
8033 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8034 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8035 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8036 tmp |= SBI_SSCCTL_PATHALT;
8037 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8038 udelay(32);
8039 }
8040 tmp |= SBI_SSCCTL_DISABLE;
8041 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8042 }
8043
8044 mutex_unlock(&dev_priv->sb_lock);
8045 }
8046
8047 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8048
8049 static const uint16_t sscdivintphase[] = {
8050 [BEND_IDX( 50)] = 0x3B23,
8051 [BEND_IDX( 45)] = 0x3B23,
8052 [BEND_IDX( 40)] = 0x3C23,
8053 [BEND_IDX( 35)] = 0x3C23,
8054 [BEND_IDX( 30)] = 0x3D23,
8055 [BEND_IDX( 25)] = 0x3D23,
8056 [BEND_IDX( 20)] = 0x3E23,
8057 [BEND_IDX( 15)] = 0x3E23,
8058 [BEND_IDX( 10)] = 0x3F23,
8059 [BEND_IDX( 5)] = 0x3F23,
8060 [BEND_IDX( 0)] = 0x0025,
8061 [BEND_IDX( -5)] = 0x0025,
8062 [BEND_IDX(-10)] = 0x0125,
8063 [BEND_IDX(-15)] = 0x0125,
8064 [BEND_IDX(-20)] = 0x0225,
8065 [BEND_IDX(-25)] = 0x0225,
8066 [BEND_IDX(-30)] = 0x0325,
8067 [BEND_IDX(-35)] = 0x0325,
8068 [BEND_IDX(-40)] = 0x0425,
8069 [BEND_IDX(-45)] = 0x0425,
8070 [BEND_IDX(-50)] = 0x0525,
8071 };
8072
8073 /*
8074 * Bend CLKOUT_DP
8075 * steps -50 to 50 inclusive, in steps of 5
8076 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8077 * change in clock period = -(steps / 10) * 5.787 ps
8078 */
8079 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8080 {
8081 uint32_t tmp;
8082 int idx = BEND_IDX(steps);
8083
8084 if (WARN_ON(steps % 5 != 0))
8085 return;
8086
8087 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8088 return;
8089
8090 mutex_lock(&dev_priv->sb_lock);
8091
8092 if (steps % 10 != 0)
8093 tmp = 0xAAAAAAAB;
8094 else
8095 tmp = 0x00000000;
8096 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8097
8098 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8099 tmp &= 0xffff0000;
8100 tmp |= sscdivintphase[idx];
8101 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8102
8103 mutex_unlock(&dev_priv->sb_lock);
8104 }
8105
8106 #undef BEND_IDX
8107
8108 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8109 {
8110 struct intel_encoder *encoder;
8111 bool has_vga = false;
8112
8113 for_each_intel_encoder(&dev_priv->drm, encoder) {
8114 switch (encoder->type) {
8115 case INTEL_OUTPUT_ANALOG:
8116 has_vga = true;
8117 break;
8118 default:
8119 break;
8120 }
8121 }
8122
8123 if (has_vga) {
8124 lpt_bend_clkout_dp(dev_priv, 0);
8125 lpt_enable_clkout_dp(dev_priv, true, true);
8126 } else {
8127 lpt_disable_clkout_dp(dev_priv);
8128 }
8129 }
8130
8131 /*
8132 * Initialize reference clocks when the driver loads
8133 */
8134 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8135 {
8136 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8137 ironlake_init_pch_refclk(dev_priv);
8138 else if (HAS_PCH_LPT(dev_priv))
8139 lpt_init_pch_refclk(dev_priv);
8140 }
8141
8142 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8143 {
8144 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8146 int pipe = intel_crtc->pipe;
8147 uint32_t val;
8148
8149 val = 0;
8150
8151 switch (intel_crtc->config->pipe_bpp) {
8152 case 18:
8153 val |= PIPECONF_6BPC;
8154 break;
8155 case 24:
8156 val |= PIPECONF_8BPC;
8157 break;
8158 case 30:
8159 val |= PIPECONF_10BPC;
8160 break;
8161 case 36:
8162 val |= PIPECONF_12BPC;
8163 break;
8164 default:
8165 /* Case prevented by intel_choose_pipe_bpp_dither. */
8166 BUG();
8167 }
8168
8169 if (intel_crtc->config->dither)
8170 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8171
8172 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8173 val |= PIPECONF_INTERLACED_ILK;
8174 else
8175 val |= PIPECONF_PROGRESSIVE;
8176
8177 if (intel_crtc->config->limited_color_range)
8178 val |= PIPECONF_COLOR_RANGE_SELECT;
8179
8180 I915_WRITE(PIPECONF(pipe), val);
8181 POSTING_READ(PIPECONF(pipe));
8182 }
8183
8184 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8185 {
8186 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8188 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8189 u32 val = 0;
8190
8191 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8192 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8193
8194 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8195 val |= PIPECONF_INTERLACED_ILK;
8196 else
8197 val |= PIPECONF_PROGRESSIVE;
8198
8199 I915_WRITE(PIPECONF(cpu_transcoder), val);
8200 POSTING_READ(PIPECONF(cpu_transcoder));
8201 }
8202
8203 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8204 {
8205 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8207 struct intel_crtc_state *config = intel_crtc->config;
8208
8209 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8210 u32 val = 0;
8211
8212 switch (intel_crtc->config->pipe_bpp) {
8213 case 18:
8214 val |= PIPEMISC_DITHER_6_BPC;
8215 break;
8216 case 24:
8217 val |= PIPEMISC_DITHER_8_BPC;
8218 break;
8219 case 30:
8220 val |= PIPEMISC_DITHER_10_BPC;
8221 break;
8222 case 36:
8223 val |= PIPEMISC_DITHER_12_BPC;
8224 break;
8225 default:
8226 /* Case prevented by pipe_config_set_bpp. */
8227 BUG();
8228 }
8229
8230 if (intel_crtc->config->dither)
8231 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8232
8233 if (config->ycbcr420) {
8234 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8235 PIPEMISC_YUV420_ENABLE |
8236 PIPEMISC_YUV420_MODE_FULL_BLEND;
8237 }
8238
8239 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8240 }
8241 }
8242
8243 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8244 {
8245 /*
8246 * Account for spread spectrum to avoid
8247 * oversubscribing the link. Max center spread
8248 * is 2.5%; use 5% for safety's sake.
8249 */
8250 u32 bps = target_clock * bpp * 21 / 20;
8251 return DIV_ROUND_UP(bps, link_bw * 8);
8252 }
8253
8254 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8255 {
8256 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8257 }
8258
8259 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8260 struct intel_crtc_state *crtc_state,
8261 struct dpll *reduced_clock)
8262 {
8263 struct drm_crtc *crtc = &intel_crtc->base;
8264 struct drm_device *dev = crtc->dev;
8265 struct drm_i915_private *dev_priv = to_i915(dev);
8266 u32 dpll, fp, fp2;
8267 int factor;
8268
8269 /* Enable autotuning of the PLL clock (if permissible) */
8270 factor = 21;
8271 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8272 if ((intel_panel_use_ssc(dev_priv) &&
8273 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8274 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8275 factor = 25;
8276 } else if (crtc_state->sdvo_tv_clock)
8277 factor = 20;
8278
8279 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8280
8281 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8282 fp |= FP_CB_TUNE;
8283
8284 if (reduced_clock) {
8285 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8286
8287 if (reduced_clock->m < factor * reduced_clock->n)
8288 fp2 |= FP_CB_TUNE;
8289 } else {
8290 fp2 = fp;
8291 }
8292
8293 dpll = 0;
8294
8295 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8296 dpll |= DPLLB_MODE_LVDS;
8297 else
8298 dpll |= DPLLB_MODE_DAC_SERIAL;
8299
8300 dpll |= (crtc_state->pixel_multiplier - 1)
8301 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8302
8303 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8304 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8305 dpll |= DPLL_SDVO_HIGH_SPEED;
8306
8307 if (intel_crtc_has_dp_encoder(crtc_state))
8308 dpll |= DPLL_SDVO_HIGH_SPEED;
8309
8310 /*
8311 * The high speed IO clock is only really required for
8312 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8313 * possible to share the DPLL between CRT and HDMI. Enabling
8314 * the clock needlessly does no real harm, except use up a
8315 * bit of power potentially.
8316 *
8317 * We'll limit this to IVB with 3 pipes, since it has only two
8318 * DPLLs and so DPLL sharing is the only way to get three pipes
8319 * driving PCH ports at the same time. On SNB we could do this,
8320 * and potentially avoid enabling the second DPLL, but it's not
8321 * clear if it''s a win or loss power wise. No point in doing
8322 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8323 */
8324 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8325 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8326 dpll |= DPLL_SDVO_HIGH_SPEED;
8327
8328 /* compute bitmask from p1 value */
8329 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8330 /* also FPA1 */
8331 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8332
8333 switch (crtc_state->dpll.p2) {
8334 case 5:
8335 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8336 break;
8337 case 7:
8338 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8339 break;
8340 case 10:
8341 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8342 break;
8343 case 14:
8344 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8345 break;
8346 }
8347
8348 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8349 intel_panel_use_ssc(dev_priv))
8350 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8351 else
8352 dpll |= PLL_REF_INPUT_DREFCLK;
8353
8354 dpll |= DPLL_VCO_ENABLE;
8355
8356 crtc_state->dpll_hw_state.dpll = dpll;
8357 crtc_state->dpll_hw_state.fp0 = fp;
8358 crtc_state->dpll_hw_state.fp1 = fp2;
8359 }
8360
8361 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8362 struct intel_crtc_state *crtc_state)
8363 {
8364 struct drm_device *dev = crtc->base.dev;
8365 struct drm_i915_private *dev_priv = to_i915(dev);
8366 const struct intel_limit *limit;
8367 int refclk = 120000;
8368
8369 memset(&crtc_state->dpll_hw_state, 0,
8370 sizeof(crtc_state->dpll_hw_state));
8371
8372 crtc->lowfreq_avail = false;
8373
8374 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8375 if (!crtc_state->has_pch_encoder)
8376 return 0;
8377
8378 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8379 if (intel_panel_use_ssc(dev_priv)) {
8380 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8381 dev_priv->vbt.lvds_ssc_freq);
8382 refclk = dev_priv->vbt.lvds_ssc_freq;
8383 }
8384
8385 if (intel_is_dual_link_lvds(dev)) {
8386 if (refclk == 100000)
8387 limit = &intel_limits_ironlake_dual_lvds_100m;
8388 else
8389 limit = &intel_limits_ironlake_dual_lvds;
8390 } else {
8391 if (refclk == 100000)
8392 limit = &intel_limits_ironlake_single_lvds_100m;
8393 else
8394 limit = &intel_limits_ironlake_single_lvds;
8395 }
8396 } else {
8397 limit = &intel_limits_ironlake_dac;
8398 }
8399
8400 if (!crtc_state->clock_set &&
8401 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8402 refclk, NULL, &crtc_state->dpll)) {
8403 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8404 return -EINVAL;
8405 }
8406
8407 ironlake_compute_dpll(crtc, crtc_state, NULL);
8408
8409 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8410 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8411 pipe_name(crtc->pipe));
8412 return -EINVAL;
8413 }
8414
8415 return 0;
8416 }
8417
8418 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8419 struct intel_link_m_n *m_n)
8420 {
8421 struct drm_device *dev = crtc->base.dev;
8422 struct drm_i915_private *dev_priv = to_i915(dev);
8423 enum pipe pipe = crtc->pipe;
8424
8425 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8426 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8427 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8428 & ~TU_SIZE_MASK;
8429 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8430 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8431 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8432 }
8433
8434 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8435 enum transcoder transcoder,
8436 struct intel_link_m_n *m_n,
8437 struct intel_link_m_n *m2_n2)
8438 {
8439 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8440 enum pipe pipe = crtc->pipe;
8441
8442 if (INTEL_GEN(dev_priv) >= 5) {
8443 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8444 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8445 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8446 & ~TU_SIZE_MASK;
8447 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8448 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8449 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8450 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8451 * gen < 8) and if DRRS is supported (to make sure the
8452 * registers are not unnecessarily read).
8453 */
8454 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8455 crtc->config->has_drrs) {
8456 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8457 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8458 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8459 & ~TU_SIZE_MASK;
8460 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8461 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8462 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8463 }
8464 } else {
8465 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8466 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8467 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8468 & ~TU_SIZE_MASK;
8469 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8470 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8471 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8472 }
8473 }
8474
8475 void intel_dp_get_m_n(struct intel_crtc *crtc,
8476 struct intel_crtc_state *pipe_config)
8477 {
8478 if (pipe_config->has_pch_encoder)
8479 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8480 else
8481 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8482 &pipe_config->dp_m_n,
8483 &pipe_config->dp_m2_n2);
8484 }
8485
8486 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8487 struct intel_crtc_state *pipe_config)
8488 {
8489 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8490 &pipe_config->fdi_m_n, NULL);
8491 }
8492
8493 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8494 struct intel_crtc_state *pipe_config)
8495 {
8496 struct drm_device *dev = crtc->base.dev;
8497 struct drm_i915_private *dev_priv = to_i915(dev);
8498 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8499 uint32_t ps_ctrl = 0;
8500 int id = -1;
8501 int i;
8502
8503 /* find scaler attached to this pipe */
8504 for (i = 0; i < crtc->num_scalers; i++) {
8505 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8506 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8507 id = i;
8508 pipe_config->pch_pfit.enabled = true;
8509 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8510 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8511 break;
8512 }
8513 }
8514
8515 scaler_state->scaler_id = id;
8516 if (id >= 0) {
8517 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8518 } else {
8519 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8520 }
8521 }
8522
8523 static void
8524 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8525 struct intel_initial_plane_config *plane_config)
8526 {
8527 struct drm_device *dev = crtc->base.dev;
8528 struct drm_i915_private *dev_priv = to_i915(dev);
8529 u32 val, base, offset, stride_mult, tiling;
8530 int pipe = crtc->pipe;
8531 int fourcc, pixel_format;
8532 unsigned int aligned_height;
8533 struct drm_framebuffer *fb;
8534 struct intel_framebuffer *intel_fb;
8535
8536 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8537 if (!intel_fb) {
8538 DRM_DEBUG_KMS("failed to alloc fb\n");
8539 return;
8540 }
8541
8542 fb = &intel_fb->base;
8543
8544 fb->dev = dev;
8545
8546 val = I915_READ(PLANE_CTL(pipe, 0));
8547 if (!(val & PLANE_CTL_ENABLE))
8548 goto error;
8549
8550 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8551 fourcc = skl_format_to_fourcc(pixel_format,
8552 val & PLANE_CTL_ORDER_RGBX,
8553 val & PLANE_CTL_ALPHA_MASK);
8554 fb->format = drm_format_info(fourcc);
8555
8556 tiling = val & PLANE_CTL_TILED_MASK;
8557 switch (tiling) {
8558 case PLANE_CTL_TILED_LINEAR:
8559 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8560 break;
8561 case PLANE_CTL_TILED_X:
8562 plane_config->tiling = I915_TILING_X;
8563 fb->modifier = I915_FORMAT_MOD_X_TILED;
8564 break;
8565 case PLANE_CTL_TILED_Y:
8566 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8567 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8568 else
8569 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8570 break;
8571 case PLANE_CTL_TILED_YF:
8572 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8573 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8574 else
8575 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8576 break;
8577 default:
8578 MISSING_CASE(tiling);
8579 goto error;
8580 }
8581
8582 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8583 plane_config->base = base;
8584
8585 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8586
8587 val = I915_READ(PLANE_SIZE(pipe, 0));
8588 fb->height = ((val >> 16) & 0xfff) + 1;
8589 fb->width = ((val >> 0) & 0x1fff) + 1;
8590
8591 val = I915_READ(PLANE_STRIDE(pipe, 0));
8592 stride_mult = intel_fb_stride_alignment(fb, 0);
8593 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8594
8595 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8596
8597 plane_config->size = fb->pitches[0] * aligned_height;
8598
8599 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8600 pipe_name(pipe), fb->width, fb->height,
8601 fb->format->cpp[0] * 8, base, fb->pitches[0],
8602 plane_config->size);
8603
8604 plane_config->fb = intel_fb;
8605 return;
8606
8607 error:
8608 kfree(intel_fb);
8609 }
8610
8611 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8612 struct intel_crtc_state *pipe_config)
8613 {
8614 struct drm_device *dev = crtc->base.dev;
8615 struct drm_i915_private *dev_priv = to_i915(dev);
8616 uint32_t tmp;
8617
8618 tmp = I915_READ(PF_CTL(crtc->pipe));
8619
8620 if (tmp & PF_ENABLE) {
8621 pipe_config->pch_pfit.enabled = true;
8622 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8623 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8624
8625 /* We currently do not free assignements of panel fitters on
8626 * ivb/hsw (since we don't use the higher upscaling modes which
8627 * differentiates them) so just WARN about this case for now. */
8628 if (IS_GEN7(dev_priv)) {
8629 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8630 PF_PIPE_SEL_IVB(crtc->pipe));
8631 }
8632 }
8633 }
8634
8635 static void
8636 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8637 struct intel_initial_plane_config *plane_config)
8638 {
8639 struct drm_device *dev = crtc->base.dev;
8640 struct drm_i915_private *dev_priv = to_i915(dev);
8641 u32 val, base, offset;
8642 int pipe = crtc->pipe;
8643 int fourcc, pixel_format;
8644 unsigned int aligned_height;
8645 struct drm_framebuffer *fb;
8646 struct intel_framebuffer *intel_fb;
8647
8648 val = I915_READ(DSPCNTR(pipe));
8649 if (!(val & DISPLAY_PLANE_ENABLE))
8650 return;
8651
8652 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8653 if (!intel_fb) {
8654 DRM_DEBUG_KMS("failed to alloc fb\n");
8655 return;
8656 }
8657
8658 fb = &intel_fb->base;
8659
8660 fb->dev = dev;
8661
8662 if (INTEL_GEN(dev_priv) >= 4) {
8663 if (val & DISPPLANE_TILED) {
8664 plane_config->tiling = I915_TILING_X;
8665 fb->modifier = I915_FORMAT_MOD_X_TILED;
8666 }
8667 }
8668
8669 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8670 fourcc = i9xx_format_to_fourcc(pixel_format);
8671 fb->format = drm_format_info(fourcc);
8672
8673 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8674 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8675 offset = I915_READ(DSPOFFSET(pipe));
8676 } else {
8677 if (plane_config->tiling)
8678 offset = I915_READ(DSPTILEOFF(pipe));
8679 else
8680 offset = I915_READ(DSPLINOFF(pipe));
8681 }
8682 plane_config->base = base;
8683
8684 val = I915_READ(PIPESRC(pipe));
8685 fb->width = ((val >> 16) & 0xfff) + 1;
8686 fb->height = ((val >> 0) & 0xfff) + 1;
8687
8688 val = I915_READ(DSPSTRIDE(pipe));
8689 fb->pitches[0] = val & 0xffffffc0;
8690
8691 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8692
8693 plane_config->size = fb->pitches[0] * aligned_height;
8694
8695 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8696 pipe_name(pipe), fb->width, fb->height,
8697 fb->format->cpp[0] * 8, base, fb->pitches[0],
8698 plane_config->size);
8699
8700 plane_config->fb = intel_fb;
8701 }
8702
8703 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8704 struct intel_crtc_state *pipe_config)
8705 {
8706 struct drm_device *dev = crtc->base.dev;
8707 struct drm_i915_private *dev_priv = to_i915(dev);
8708 enum intel_display_power_domain power_domain;
8709 uint32_t tmp;
8710 bool ret;
8711
8712 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8713 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8714 return false;
8715
8716 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8717 pipe_config->shared_dpll = NULL;
8718
8719 ret = false;
8720 tmp = I915_READ(PIPECONF(crtc->pipe));
8721 if (!(tmp & PIPECONF_ENABLE))
8722 goto out;
8723
8724 switch (tmp & PIPECONF_BPC_MASK) {
8725 case PIPECONF_6BPC:
8726 pipe_config->pipe_bpp = 18;
8727 break;
8728 case PIPECONF_8BPC:
8729 pipe_config->pipe_bpp = 24;
8730 break;
8731 case PIPECONF_10BPC:
8732 pipe_config->pipe_bpp = 30;
8733 break;
8734 case PIPECONF_12BPC:
8735 pipe_config->pipe_bpp = 36;
8736 break;
8737 default:
8738 break;
8739 }
8740
8741 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8742 pipe_config->limited_color_range = true;
8743
8744 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8745 struct intel_shared_dpll *pll;
8746 enum intel_dpll_id pll_id;
8747
8748 pipe_config->has_pch_encoder = true;
8749
8750 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8751 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8752 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8753
8754 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8755
8756 if (HAS_PCH_IBX(dev_priv)) {
8757 /*
8758 * The pipe->pch transcoder and pch transcoder->pll
8759 * mapping is fixed.
8760 */
8761 pll_id = (enum intel_dpll_id) crtc->pipe;
8762 } else {
8763 tmp = I915_READ(PCH_DPLL_SEL);
8764 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8765 pll_id = DPLL_ID_PCH_PLL_B;
8766 else
8767 pll_id= DPLL_ID_PCH_PLL_A;
8768 }
8769
8770 pipe_config->shared_dpll =
8771 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8772 pll = pipe_config->shared_dpll;
8773
8774 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8775 &pipe_config->dpll_hw_state));
8776
8777 tmp = pipe_config->dpll_hw_state.dpll;
8778 pipe_config->pixel_multiplier =
8779 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8780 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8781
8782 ironlake_pch_clock_get(crtc, pipe_config);
8783 } else {
8784 pipe_config->pixel_multiplier = 1;
8785 }
8786
8787 intel_get_pipe_timings(crtc, pipe_config);
8788 intel_get_pipe_src_size(crtc, pipe_config);
8789
8790 ironlake_get_pfit_config(crtc, pipe_config);
8791
8792 ret = true;
8793
8794 out:
8795 intel_display_power_put(dev_priv, power_domain);
8796
8797 return ret;
8798 }
8799
8800 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8801 {
8802 struct drm_device *dev = &dev_priv->drm;
8803 struct intel_crtc *crtc;
8804
8805 for_each_intel_crtc(dev, crtc)
8806 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8807 pipe_name(crtc->pipe));
8808
8809 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8810 "Display power well on\n");
8811 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8812 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8813 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8814 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8815 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8816 "CPU PWM1 enabled\n");
8817 if (IS_HASWELL(dev_priv))
8818 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8819 "CPU PWM2 enabled\n");
8820 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8821 "PCH PWM1 enabled\n");
8822 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8823 "Utility pin enabled\n");
8824 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8825
8826 /*
8827 * In theory we can still leave IRQs enabled, as long as only the HPD
8828 * interrupts remain enabled. We used to check for that, but since it's
8829 * gen-specific and since we only disable LCPLL after we fully disable
8830 * the interrupts, the check below should be enough.
8831 */
8832 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8833 }
8834
8835 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8836 {
8837 if (IS_HASWELL(dev_priv))
8838 return I915_READ(D_COMP_HSW);
8839 else
8840 return I915_READ(D_COMP_BDW);
8841 }
8842
8843 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8844 {
8845 if (IS_HASWELL(dev_priv)) {
8846 mutex_lock(&dev_priv->rps.hw_lock);
8847 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8848 val))
8849 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8850 mutex_unlock(&dev_priv->rps.hw_lock);
8851 } else {
8852 I915_WRITE(D_COMP_BDW, val);
8853 POSTING_READ(D_COMP_BDW);
8854 }
8855 }
8856
8857 /*
8858 * This function implements pieces of two sequences from BSpec:
8859 * - Sequence for display software to disable LCPLL
8860 * - Sequence for display software to allow package C8+
8861 * The steps implemented here are just the steps that actually touch the LCPLL
8862 * register. Callers should take care of disabling all the display engine
8863 * functions, doing the mode unset, fixing interrupts, etc.
8864 */
8865 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8866 bool switch_to_fclk, bool allow_power_down)
8867 {
8868 uint32_t val;
8869
8870 assert_can_disable_lcpll(dev_priv);
8871
8872 val = I915_READ(LCPLL_CTL);
8873
8874 if (switch_to_fclk) {
8875 val |= LCPLL_CD_SOURCE_FCLK;
8876 I915_WRITE(LCPLL_CTL, val);
8877
8878 if (wait_for_us(I915_READ(LCPLL_CTL) &
8879 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8880 DRM_ERROR("Switching to FCLK failed\n");
8881
8882 val = I915_READ(LCPLL_CTL);
8883 }
8884
8885 val |= LCPLL_PLL_DISABLE;
8886 I915_WRITE(LCPLL_CTL, val);
8887 POSTING_READ(LCPLL_CTL);
8888
8889 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8890 DRM_ERROR("LCPLL still locked\n");
8891
8892 val = hsw_read_dcomp(dev_priv);
8893 val |= D_COMP_COMP_DISABLE;
8894 hsw_write_dcomp(dev_priv, val);
8895 ndelay(100);
8896
8897 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8898 1))
8899 DRM_ERROR("D_COMP RCOMP still in progress\n");
8900
8901 if (allow_power_down) {
8902 val = I915_READ(LCPLL_CTL);
8903 val |= LCPLL_POWER_DOWN_ALLOW;
8904 I915_WRITE(LCPLL_CTL, val);
8905 POSTING_READ(LCPLL_CTL);
8906 }
8907 }
8908
8909 /*
8910 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8911 * source.
8912 */
8913 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8914 {
8915 uint32_t val;
8916
8917 val = I915_READ(LCPLL_CTL);
8918
8919 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8920 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8921 return;
8922
8923 /*
8924 * Make sure we're not on PC8 state before disabling PC8, otherwise
8925 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8926 */
8927 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8928
8929 if (val & LCPLL_POWER_DOWN_ALLOW) {
8930 val &= ~LCPLL_POWER_DOWN_ALLOW;
8931 I915_WRITE(LCPLL_CTL, val);
8932 POSTING_READ(LCPLL_CTL);
8933 }
8934
8935 val = hsw_read_dcomp(dev_priv);
8936 val |= D_COMP_COMP_FORCE;
8937 val &= ~D_COMP_COMP_DISABLE;
8938 hsw_write_dcomp(dev_priv, val);
8939
8940 val = I915_READ(LCPLL_CTL);
8941 val &= ~LCPLL_PLL_DISABLE;
8942 I915_WRITE(LCPLL_CTL, val);
8943
8944 if (intel_wait_for_register(dev_priv,
8945 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8946 5))
8947 DRM_ERROR("LCPLL not locked yet\n");
8948
8949 if (val & LCPLL_CD_SOURCE_FCLK) {
8950 val = I915_READ(LCPLL_CTL);
8951 val &= ~LCPLL_CD_SOURCE_FCLK;
8952 I915_WRITE(LCPLL_CTL, val);
8953
8954 if (wait_for_us((I915_READ(LCPLL_CTL) &
8955 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8956 DRM_ERROR("Switching back to LCPLL failed\n");
8957 }
8958
8959 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8960 intel_update_cdclk(dev_priv);
8961 }
8962
8963 /*
8964 * Package states C8 and deeper are really deep PC states that can only be
8965 * reached when all the devices on the system allow it, so even if the graphics
8966 * device allows PC8+, it doesn't mean the system will actually get to these
8967 * states. Our driver only allows PC8+ when going into runtime PM.
8968 *
8969 * The requirements for PC8+ are that all the outputs are disabled, the power
8970 * well is disabled and most interrupts are disabled, and these are also
8971 * requirements for runtime PM. When these conditions are met, we manually do
8972 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8973 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8974 * hang the machine.
8975 *
8976 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8977 * the state of some registers, so when we come back from PC8+ we need to
8978 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8979 * need to take care of the registers kept by RC6. Notice that this happens even
8980 * if we don't put the device in PCI D3 state (which is what currently happens
8981 * because of the runtime PM support).
8982 *
8983 * For more, read "Display Sequences for Package C8" on the hardware
8984 * documentation.
8985 */
8986 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8987 {
8988 uint32_t val;
8989
8990 DRM_DEBUG_KMS("Enabling package C8+\n");
8991
8992 if (HAS_PCH_LPT_LP(dev_priv)) {
8993 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8994 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8995 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8996 }
8997
8998 lpt_disable_clkout_dp(dev_priv);
8999 hsw_disable_lcpll(dev_priv, true, true);
9000 }
9001
9002 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9003 {
9004 uint32_t val;
9005
9006 DRM_DEBUG_KMS("Disabling package C8+\n");
9007
9008 hsw_restore_lcpll(dev_priv);
9009 lpt_init_pch_refclk(dev_priv);
9010
9011 if (HAS_PCH_LPT_LP(dev_priv)) {
9012 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9013 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9014 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9015 }
9016 }
9017
9018 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9019 struct intel_crtc_state *crtc_state)
9020 {
9021 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9022 struct intel_encoder *encoder =
9023 intel_ddi_get_crtc_new_encoder(crtc_state);
9024
9025 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9026 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9027 pipe_name(crtc->pipe));
9028 return -EINVAL;
9029 }
9030 }
9031
9032 crtc->lowfreq_avail = false;
9033
9034 return 0;
9035 }
9036
9037 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9038 enum port port,
9039 struct intel_crtc_state *pipe_config)
9040 {
9041 enum intel_dpll_id id;
9042 u32 temp;
9043
9044 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9045 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9046
9047 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9048 return;
9049
9050 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9051 }
9052
9053 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9054 enum port port,
9055 struct intel_crtc_state *pipe_config)
9056 {
9057 enum intel_dpll_id id;
9058
9059 switch (port) {
9060 case PORT_A:
9061 id = DPLL_ID_SKL_DPLL0;
9062 break;
9063 case PORT_B:
9064 id = DPLL_ID_SKL_DPLL1;
9065 break;
9066 case PORT_C:
9067 id = DPLL_ID_SKL_DPLL2;
9068 break;
9069 default:
9070 DRM_ERROR("Incorrect port type\n");
9071 return;
9072 }
9073
9074 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9075 }
9076
9077 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9078 enum port port,
9079 struct intel_crtc_state *pipe_config)
9080 {
9081 enum intel_dpll_id id;
9082 u32 temp;
9083
9084 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9085 id = temp >> (port * 3 + 1);
9086
9087 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9088 return;
9089
9090 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9091 }
9092
9093 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9094 enum port port,
9095 struct intel_crtc_state *pipe_config)
9096 {
9097 enum intel_dpll_id id;
9098 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9099
9100 switch (ddi_pll_sel) {
9101 case PORT_CLK_SEL_WRPLL1:
9102 id = DPLL_ID_WRPLL1;
9103 break;
9104 case PORT_CLK_SEL_WRPLL2:
9105 id = DPLL_ID_WRPLL2;
9106 break;
9107 case PORT_CLK_SEL_SPLL:
9108 id = DPLL_ID_SPLL;
9109 break;
9110 case PORT_CLK_SEL_LCPLL_810:
9111 id = DPLL_ID_LCPLL_810;
9112 break;
9113 case PORT_CLK_SEL_LCPLL_1350:
9114 id = DPLL_ID_LCPLL_1350;
9115 break;
9116 case PORT_CLK_SEL_LCPLL_2700:
9117 id = DPLL_ID_LCPLL_2700;
9118 break;
9119 default:
9120 MISSING_CASE(ddi_pll_sel);
9121 /* fall through */
9122 case PORT_CLK_SEL_NONE:
9123 return;
9124 }
9125
9126 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9127 }
9128
9129 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9130 struct intel_crtc_state *pipe_config,
9131 u64 *power_domain_mask)
9132 {
9133 struct drm_device *dev = crtc->base.dev;
9134 struct drm_i915_private *dev_priv = to_i915(dev);
9135 enum intel_display_power_domain power_domain;
9136 u32 tmp;
9137
9138 /*
9139 * The pipe->transcoder mapping is fixed with the exception of the eDP
9140 * transcoder handled below.
9141 */
9142 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9143
9144 /*
9145 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9146 * consistency and less surprising code; it's in always on power).
9147 */
9148 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9149 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9150 enum pipe trans_edp_pipe;
9151 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9152 default:
9153 WARN(1, "unknown pipe linked to edp transcoder\n");
9154 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9155 case TRANS_DDI_EDP_INPUT_A_ON:
9156 trans_edp_pipe = PIPE_A;
9157 break;
9158 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9159 trans_edp_pipe = PIPE_B;
9160 break;
9161 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9162 trans_edp_pipe = PIPE_C;
9163 break;
9164 }
9165
9166 if (trans_edp_pipe == crtc->pipe)
9167 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9168 }
9169
9170 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9171 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9172 return false;
9173 *power_domain_mask |= BIT_ULL(power_domain);
9174
9175 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9176
9177 return tmp & PIPECONF_ENABLE;
9178 }
9179
9180 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9181 struct intel_crtc_state *pipe_config,
9182 u64 *power_domain_mask)
9183 {
9184 struct drm_device *dev = crtc->base.dev;
9185 struct drm_i915_private *dev_priv = to_i915(dev);
9186 enum intel_display_power_domain power_domain;
9187 enum port port;
9188 enum transcoder cpu_transcoder;
9189 u32 tmp;
9190
9191 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9192 if (port == PORT_A)
9193 cpu_transcoder = TRANSCODER_DSI_A;
9194 else
9195 cpu_transcoder = TRANSCODER_DSI_C;
9196
9197 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9198 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9199 continue;
9200 *power_domain_mask |= BIT_ULL(power_domain);
9201
9202 /*
9203 * The PLL needs to be enabled with a valid divider
9204 * configuration, otherwise accessing DSI registers will hang
9205 * the machine. See BSpec North Display Engine
9206 * registers/MIPI[BXT]. We can break out here early, since we
9207 * need the same DSI PLL to be enabled for both DSI ports.
9208 */
9209 if (!intel_dsi_pll_is_enabled(dev_priv))
9210 break;
9211
9212 /* XXX: this works for video mode only */
9213 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9214 if (!(tmp & DPI_ENABLE))
9215 continue;
9216
9217 tmp = I915_READ(MIPI_CTRL(port));
9218 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9219 continue;
9220
9221 pipe_config->cpu_transcoder = cpu_transcoder;
9222 break;
9223 }
9224
9225 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9226 }
9227
9228 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9229 struct intel_crtc_state *pipe_config)
9230 {
9231 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9232 struct intel_shared_dpll *pll;
9233 enum port port;
9234 uint32_t tmp;
9235
9236 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9237
9238 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9239
9240 if (IS_CANNONLAKE(dev_priv))
9241 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9242 else if (IS_GEN9_BC(dev_priv))
9243 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9244 else if (IS_GEN9_LP(dev_priv))
9245 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9246 else
9247 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9248
9249 pll = pipe_config->shared_dpll;
9250 if (pll) {
9251 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9252 &pipe_config->dpll_hw_state));
9253 }
9254
9255 /*
9256 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9257 * DDI E. So just check whether this pipe is wired to DDI E and whether
9258 * the PCH transcoder is on.
9259 */
9260 if (INTEL_GEN(dev_priv) < 9 &&
9261 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9262 pipe_config->has_pch_encoder = true;
9263
9264 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9265 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9266 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9267
9268 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9269 }
9270 }
9271
9272 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9273 struct intel_crtc_state *pipe_config)
9274 {
9275 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9276 enum intel_display_power_domain power_domain;
9277 u64 power_domain_mask;
9278 bool active;
9279
9280 intel_crtc_init_scalers(crtc, pipe_config);
9281
9282 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9283 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9284 return false;
9285 power_domain_mask = BIT_ULL(power_domain);
9286
9287 pipe_config->shared_dpll = NULL;
9288
9289 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9290
9291 if (IS_GEN9_LP(dev_priv) &&
9292 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9293 WARN_ON(active);
9294 active = true;
9295 }
9296
9297 if (!active)
9298 goto out;
9299
9300 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9301 haswell_get_ddi_port_state(crtc, pipe_config);
9302 intel_get_pipe_timings(crtc, pipe_config);
9303 }
9304
9305 intel_get_pipe_src_size(crtc, pipe_config);
9306
9307 pipe_config->gamma_mode =
9308 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9309
9310 if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) {
9311 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9312 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9313
9314 if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) {
9315 bool blend_mode_420 = tmp &
9316 PIPEMISC_YUV420_MODE_FULL_BLEND;
9317
9318 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9319 if (pipe_config->ycbcr420 != clrspace_yuv ||
9320 pipe_config->ycbcr420 != blend_mode_420)
9321 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9322 } else if (clrspace_yuv) {
9323 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9324 }
9325 }
9326
9327 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9328 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9329 power_domain_mask |= BIT_ULL(power_domain);
9330 if (INTEL_GEN(dev_priv) >= 9)
9331 skylake_get_pfit_config(crtc, pipe_config);
9332 else
9333 ironlake_get_pfit_config(crtc, pipe_config);
9334 }
9335
9336 if (IS_HASWELL(dev_priv))
9337 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9338 (I915_READ(IPS_CTL) & IPS_ENABLE);
9339
9340 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9341 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9342 pipe_config->pixel_multiplier =
9343 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9344 } else {
9345 pipe_config->pixel_multiplier = 1;
9346 }
9347
9348 out:
9349 for_each_power_domain(power_domain, power_domain_mask)
9350 intel_display_power_put(dev_priv, power_domain);
9351
9352 return active;
9353 }
9354
9355 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9356 {
9357 struct drm_i915_private *dev_priv =
9358 to_i915(plane_state->base.plane->dev);
9359 const struct drm_framebuffer *fb = plane_state->base.fb;
9360 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9361 u32 base;
9362
9363 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9364 base = obj->phys_handle->busaddr;
9365 else
9366 base = intel_plane_ggtt_offset(plane_state);
9367
9368 base += plane_state->main.offset;
9369
9370 /* ILK+ do this automagically */
9371 if (HAS_GMCH_DISPLAY(dev_priv) &&
9372 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9373 base += (plane_state->base.crtc_h *
9374 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9375
9376 return base;
9377 }
9378
9379 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9380 {
9381 int x = plane_state->base.crtc_x;
9382 int y = plane_state->base.crtc_y;
9383 u32 pos = 0;
9384
9385 if (x < 0) {
9386 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9387 x = -x;
9388 }
9389 pos |= x << CURSOR_X_SHIFT;
9390
9391 if (y < 0) {
9392 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9393 y = -y;
9394 }
9395 pos |= y << CURSOR_Y_SHIFT;
9396
9397 return pos;
9398 }
9399
9400 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9401 {
9402 const struct drm_mode_config *config =
9403 &plane_state->base.plane->dev->mode_config;
9404 int width = plane_state->base.crtc_w;
9405 int height = plane_state->base.crtc_h;
9406
9407 return width > 0 && width <= config->cursor_width &&
9408 height > 0 && height <= config->cursor_height;
9409 }
9410
9411 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9412 struct intel_plane_state *plane_state)
9413 {
9414 const struct drm_framebuffer *fb = plane_state->base.fb;
9415 int src_x, src_y;
9416 u32 offset;
9417 int ret;
9418
9419 ret = drm_plane_helper_check_state(&plane_state->base,
9420 &plane_state->clip,
9421 DRM_PLANE_HELPER_NO_SCALING,
9422 DRM_PLANE_HELPER_NO_SCALING,
9423 true, true);
9424 if (ret)
9425 return ret;
9426
9427 if (!fb)
9428 return 0;
9429
9430 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9431 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9432 return -EINVAL;
9433 }
9434
9435 src_x = plane_state->base.src_x >> 16;
9436 src_y = plane_state->base.src_y >> 16;
9437
9438 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9439 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9440
9441 if (src_x != 0 || src_y != 0) {
9442 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9443 return -EINVAL;
9444 }
9445
9446 plane_state->main.offset = offset;
9447
9448 return 0;
9449 }
9450
9451 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9452 const struct intel_plane_state *plane_state)
9453 {
9454 const struct drm_framebuffer *fb = plane_state->base.fb;
9455
9456 return CURSOR_ENABLE |
9457 CURSOR_GAMMA_ENABLE |
9458 CURSOR_FORMAT_ARGB |
9459 CURSOR_STRIDE(fb->pitches[0]);
9460 }
9461
9462 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9463 {
9464 int width = plane_state->base.crtc_w;
9465
9466 /*
9467 * 845g/865g are only limited by the width of their cursors,
9468 * the height is arbitrary up to the precision of the register.
9469 */
9470 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9471 }
9472
9473 static int i845_check_cursor(struct intel_plane *plane,
9474 struct intel_crtc_state *crtc_state,
9475 struct intel_plane_state *plane_state)
9476 {
9477 const struct drm_framebuffer *fb = plane_state->base.fb;
9478 int ret;
9479
9480 ret = intel_check_cursor(crtc_state, plane_state);
9481 if (ret)
9482 return ret;
9483
9484 /* if we want to turn off the cursor ignore width and height */
9485 if (!fb)
9486 return 0;
9487
9488 /* Check for which cursor types we support */
9489 if (!i845_cursor_size_ok(plane_state)) {
9490 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9491 plane_state->base.crtc_w,
9492 plane_state->base.crtc_h);
9493 return -EINVAL;
9494 }
9495
9496 switch (fb->pitches[0]) {
9497 case 256:
9498 case 512:
9499 case 1024:
9500 case 2048:
9501 break;
9502 default:
9503 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9504 fb->pitches[0]);
9505 return -EINVAL;
9506 }
9507
9508 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9509
9510 return 0;
9511 }
9512
9513 static void i845_update_cursor(struct intel_plane *plane,
9514 const struct intel_crtc_state *crtc_state,
9515 const struct intel_plane_state *plane_state)
9516 {
9517 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9518 u32 cntl = 0, base = 0, pos = 0, size = 0;
9519 unsigned long irqflags;
9520
9521 if (plane_state && plane_state->base.visible) {
9522 unsigned int width = plane_state->base.crtc_w;
9523 unsigned int height = plane_state->base.crtc_h;
9524
9525 cntl = plane_state->ctl;
9526 size = (height << 12) | width;
9527
9528 base = intel_cursor_base(plane_state);
9529 pos = intel_cursor_position(plane_state);
9530 }
9531
9532 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9533
9534 /* On these chipsets we can only modify the base/size/stride
9535 * whilst the cursor is disabled.
9536 */
9537 if (plane->cursor.base != base ||
9538 plane->cursor.size != size ||
9539 plane->cursor.cntl != cntl) {
9540 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9541 I915_WRITE_FW(CURBASE(PIPE_A), base);
9542 I915_WRITE_FW(CURSIZE, size);
9543 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9544 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9545
9546 plane->cursor.base = base;
9547 plane->cursor.size = size;
9548 plane->cursor.cntl = cntl;
9549 } else {
9550 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9551 }
9552
9553 POSTING_READ_FW(CURCNTR(PIPE_A));
9554
9555 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9556 }
9557
9558 static void i845_disable_cursor(struct intel_plane *plane,
9559 struct intel_crtc *crtc)
9560 {
9561 i845_update_cursor(plane, NULL, NULL);
9562 }
9563
9564 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9565 const struct intel_plane_state *plane_state)
9566 {
9567 struct drm_i915_private *dev_priv =
9568 to_i915(plane_state->base.plane->dev);
9569 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9570 u32 cntl;
9571
9572 cntl = MCURSOR_GAMMA_ENABLE;
9573
9574 if (HAS_DDI(dev_priv))
9575 cntl |= CURSOR_PIPE_CSC_ENABLE;
9576
9577 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9578
9579 switch (plane_state->base.crtc_w) {
9580 case 64:
9581 cntl |= CURSOR_MODE_64_ARGB_AX;
9582 break;
9583 case 128:
9584 cntl |= CURSOR_MODE_128_ARGB_AX;
9585 break;
9586 case 256:
9587 cntl |= CURSOR_MODE_256_ARGB_AX;
9588 break;
9589 default:
9590 MISSING_CASE(plane_state->base.crtc_w);
9591 return 0;
9592 }
9593
9594 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9595 cntl |= CURSOR_ROTATE_180;
9596
9597 return cntl;
9598 }
9599
9600 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9601 {
9602 struct drm_i915_private *dev_priv =
9603 to_i915(plane_state->base.plane->dev);
9604 int width = plane_state->base.crtc_w;
9605 int height = plane_state->base.crtc_h;
9606
9607 if (!intel_cursor_size_ok(plane_state))
9608 return false;
9609
9610 /* Cursor width is limited to a few power-of-two sizes */
9611 switch (width) {
9612 case 256:
9613 case 128:
9614 case 64:
9615 break;
9616 default:
9617 return false;
9618 }
9619
9620 /*
9621 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9622 * height from 8 lines up to the cursor width, when the
9623 * cursor is not rotated. Everything else requires square
9624 * cursors.
9625 */
9626 if (HAS_CUR_FBC(dev_priv) &&
9627 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9628 if (height < 8 || height > width)
9629 return false;
9630 } else {
9631 if (height != width)
9632 return false;
9633 }
9634
9635 return true;
9636 }
9637
9638 static int i9xx_check_cursor(struct intel_plane *plane,
9639 struct intel_crtc_state *crtc_state,
9640 struct intel_plane_state *plane_state)
9641 {
9642 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9643 const struct drm_framebuffer *fb = plane_state->base.fb;
9644 enum pipe pipe = plane->pipe;
9645 int ret;
9646
9647 ret = intel_check_cursor(crtc_state, plane_state);
9648 if (ret)
9649 return ret;
9650
9651 /* if we want to turn off the cursor ignore width and height */
9652 if (!fb)
9653 return 0;
9654
9655 /* Check for which cursor types we support */
9656 if (!i9xx_cursor_size_ok(plane_state)) {
9657 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9658 plane_state->base.crtc_w,
9659 plane_state->base.crtc_h);
9660 return -EINVAL;
9661 }
9662
9663 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9664 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9665 fb->pitches[0], plane_state->base.crtc_w);
9666 return -EINVAL;
9667 }
9668
9669 /*
9670 * There's something wrong with the cursor on CHV pipe C.
9671 * If it straddles the left edge of the screen then
9672 * moving it away from the edge or disabling it often
9673 * results in a pipe underrun, and often that can lead to
9674 * dead pipe (constant underrun reported, and it scans
9675 * out just a solid color). To recover from that, the
9676 * display power well must be turned off and on again.
9677 * Refuse the put the cursor into that compromised position.
9678 */
9679 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9680 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9681 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9682 return -EINVAL;
9683 }
9684
9685 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9686
9687 return 0;
9688 }
9689
9690 static void i9xx_update_cursor(struct intel_plane *plane,
9691 const struct intel_crtc_state *crtc_state,
9692 const struct intel_plane_state *plane_state)
9693 {
9694 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9695 enum pipe pipe = plane->pipe;
9696 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9697 unsigned long irqflags;
9698
9699 if (plane_state && plane_state->base.visible) {
9700 cntl = plane_state->ctl;
9701
9702 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9703 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9704
9705 base = intel_cursor_base(plane_state);
9706 pos = intel_cursor_position(plane_state);
9707 }
9708
9709 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9710
9711 /*
9712 * On some platforms writing CURCNTR first will also
9713 * cause CURPOS to be armed by the CURBASE write.
9714 * Without the CURCNTR write the CURPOS write would
9715 * arm itself. Thus we always start the full update
9716 * with a CURCNTR write.
9717 *
9718 * On other platforms CURPOS always requires the
9719 * CURBASE write to arm the update. Additonally
9720 * a write to any of the cursor register will cancel
9721 * an already armed cursor update. Thus leaving out
9722 * the CURBASE write after CURPOS could lead to a
9723 * cursor that doesn't appear to move, or even change
9724 * shape. Thus we always write CURBASE.
9725 *
9726 * CURCNTR and CUR_FBC_CTL are always
9727 * armed by the CURBASE write only.
9728 */
9729 if (plane->cursor.base != base ||
9730 plane->cursor.size != fbc_ctl ||
9731 plane->cursor.cntl != cntl) {
9732 I915_WRITE_FW(CURCNTR(pipe), cntl);
9733 if (HAS_CUR_FBC(dev_priv))
9734 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9735 I915_WRITE_FW(CURPOS(pipe), pos);
9736 I915_WRITE_FW(CURBASE(pipe), base);
9737
9738 plane->cursor.base = base;
9739 plane->cursor.size = fbc_ctl;
9740 plane->cursor.cntl = cntl;
9741 } else {
9742 I915_WRITE_FW(CURPOS(pipe), pos);
9743 I915_WRITE_FW(CURBASE(pipe), base);
9744 }
9745
9746 POSTING_READ_FW(CURBASE(pipe));
9747
9748 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9749 }
9750
9751 static void i9xx_disable_cursor(struct intel_plane *plane,
9752 struct intel_crtc *crtc)
9753 {
9754 i9xx_update_cursor(plane, NULL, NULL);
9755 }
9756
9757
9758 /* VESA 640x480x72Hz mode to set on the pipe */
9759 static struct drm_display_mode load_detect_mode = {
9760 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9761 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9762 };
9763
9764 struct drm_framebuffer *
9765 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9766 struct drm_mode_fb_cmd2 *mode_cmd)
9767 {
9768 struct intel_framebuffer *intel_fb;
9769 int ret;
9770
9771 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9772 if (!intel_fb)
9773 return ERR_PTR(-ENOMEM);
9774
9775 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9776 if (ret)
9777 goto err;
9778
9779 return &intel_fb->base;
9780
9781 err:
9782 kfree(intel_fb);
9783 return ERR_PTR(ret);
9784 }
9785
9786 static u32
9787 intel_framebuffer_pitch_for_width(int width, int bpp)
9788 {
9789 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9790 return ALIGN(pitch, 64);
9791 }
9792
9793 static u32
9794 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9795 {
9796 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9797 return PAGE_ALIGN(pitch * mode->vdisplay);
9798 }
9799
9800 static struct drm_framebuffer *
9801 intel_framebuffer_create_for_mode(struct drm_device *dev,
9802 struct drm_display_mode *mode,
9803 int depth, int bpp)
9804 {
9805 struct drm_framebuffer *fb;
9806 struct drm_i915_gem_object *obj;
9807 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9808
9809 obj = i915_gem_object_create(to_i915(dev),
9810 intel_framebuffer_size_for_mode(mode, bpp));
9811 if (IS_ERR(obj))
9812 return ERR_CAST(obj);
9813
9814 mode_cmd.width = mode->hdisplay;
9815 mode_cmd.height = mode->vdisplay;
9816 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9817 bpp);
9818 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9819
9820 fb = intel_framebuffer_create(obj, &mode_cmd);
9821 if (IS_ERR(fb))
9822 i915_gem_object_put(obj);
9823
9824 return fb;
9825 }
9826
9827 static struct drm_framebuffer *
9828 mode_fits_in_fbdev(struct drm_device *dev,
9829 struct drm_display_mode *mode)
9830 {
9831 #ifdef CONFIG_DRM_FBDEV_EMULATION
9832 struct drm_i915_private *dev_priv = to_i915(dev);
9833 struct drm_i915_gem_object *obj;
9834 struct drm_framebuffer *fb;
9835
9836 if (!dev_priv->fbdev)
9837 return NULL;
9838
9839 if (!dev_priv->fbdev->fb)
9840 return NULL;
9841
9842 obj = dev_priv->fbdev->fb->obj;
9843 BUG_ON(!obj);
9844
9845 fb = &dev_priv->fbdev->fb->base;
9846 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9847 fb->format->cpp[0] * 8))
9848 return NULL;
9849
9850 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9851 return NULL;
9852
9853 drm_framebuffer_reference(fb);
9854 return fb;
9855 #else
9856 return NULL;
9857 #endif
9858 }
9859
9860 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9861 struct drm_crtc *crtc,
9862 struct drm_display_mode *mode,
9863 struct drm_framebuffer *fb,
9864 int x, int y)
9865 {
9866 struct drm_plane_state *plane_state;
9867 int hdisplay, vdisplay;
9868 int ret;
9869
9870 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9871 if (IS_ERR(plane_state))
9872 return PTR_ERR(plane_state);
9873
9874 if (mode)
9875 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9876 else
9877 hdisplay = vdisplay = 0;
9878
9879 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9880 if (ret)
9881 return ret;
9882 drm_atomic_set_fb_for_plane(plane_state, fb);
9883 plane_state->crtc_x = 0;
9884 plane_state->crtc_y = 0;
9885 plane_state->crtc_w = hdisplay;
9886 plane_state->crtc_h = vdisplay;
9887 plane_state->src_x = x << 16;
9888 plane_state->src_y = y << 16;
9889 plane_state->src_w = hdisplay << 16;
9890 plane_state->src_h = vdisplay << 16;
9891
9892 return 0;
9893 }
9894
9895 int intel_get_load_detect_pipe(struct drm_connector *connector,
9896 struct drm_display_mode *mode,
9897 struct intel_load_detect_pipe *old,
9898 struct drm_modeset_acquire_ctx *ctx)
9899 {
9900 struct intel_crtc *intel_crtc;
9901 struct intel_encoder *intel_encoder =
9902 intel_attached_encoder(connector);
9903 struct drm_crtc *possible_crtc;
9904 struct drm_encoder *encoder = &intel_encoder->base;
9905 struct drm_crtc *crtc = NULL;
9906 struct drm_device *dev = encoder->dev;
9907 struct drm_i915_private *dev_priv = to_i915(dev);
9908 struct drm_framebuffer *fb;
9909 struct drm_mode_config *config = &dev->mode_config;
9910 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9911 struct drm_connector_state *connector_state;
9912 struct intel_crtc_state *crtc_state;
9913 int ret, i = -1;
9914
9915 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9916 connector->base.id, connector->name,
9917 encoder->base.id, encoder->name);
9918
9919 old->restore_state = NULL;
9920
9921 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9922
9923 /*
9924 * Algorithm gets a little messy:
9925 *
9926 * - if the connector already has an assigned crtc, use it (but make
9927 * sure it's on first)
9928 *
9929 * - try to find the first unused crtc that can drive this connector,
9930 * and use that if we find one
9931 */
9932
9933 /* See if we already have a CRTC for this connector */
9934 if (connector->state->crtc) {
9935 crtc = connector->state->crtc;
9936
9937 ret = drm_modeset_lock(&crtc->mutex, ctx);
9938 if (ret)
9939 goto fail;
9940
9941 /* Make sure the crtc and connector are running */
9942 goto found;
9943 }
9944
9945 /* Find an unused one (if possible) */
9946 for_each_crtc(dev, possible_crtc) {
9947 i++;
9948 if (!(encoder->possible_crtcs & (1 << i)))
9949 continue;
9950
9951 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9952 if (ret)
9953 goto fail;
9954
9955 if (possible_crtc->state->enable) {
9956 drm_modeset_unlock(&possible_crtc->mutex);
9957 continue;
9958 }
9959
9960 crtc = possible_crtc;
9961 break;
9962 }
9963
9964 /*
9965 * If we didn't find an unused CRTC, don't use any.
9966 */
9967 if (!crtc) {
9968 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9969 ret = -ENODEV;
9970 goto fail;
9971 }
9972
9973 found:
9974 intel_crtc = to_intel_crtc(crtc);
9975
9976 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9977 if (ret)
9978 goto fail;
9979
9980 state = drm_atomic_state_alloc(dev);
9981 restore_state = drm_atomic_state_alloc(dev);
9982 if (!state || !restore_state) {
9983 ret = -ENOMEM;
9984 goto fail;
9985 }
9986
9987 state->acquire_ctx = ctx;
9988 restore_state->acquire_ctx = ctx;
9989
9990 connector_state = drm_atomic_get_connector_state(state, connector);
9991 if (IS_ERR(connector_state)) {
9992 ret = PTR_ERR(connector_state);
9993 goto fail;
9994 }
9995
9996 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9997 if (ret)
9998 goto fail;
9999
10000 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10001 if (IS_ERR(crtc_state)) {
10002 ret = PTR_ERR(crtc_state);
10003 goto fail;
10004 }
10005
10006 crtc_state->base.active = crtc_state->base.enable = true;
10007
10008 if (!mode)
10009 mode = &load_detect_mode;
10010
10011 /* We need a framebuffer large enough to accommodate all accesses
10012 * that the plane may generate whilst we perform load detection.
10013 * We can not rely on the fbcon either being present (we get called
10014 * during its initialisation to detect all boot displays, or it may
10015 * not even exist) or that it is large enough to satisfy the
10016 * requested mode.
10017 */
10018 fb = mode_fits_in_fbdev(dev, mode);
10019 if (fb == NULL) {
10020 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10021 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10022 } else
10023 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10024 if (IS_ERR(fb)) {
10025 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10026 ret = PTR_ERR(fb);
10027 goto fail;
10028 }
10029
10030 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10031 if (ret)
10032 goto fail;
10033
10034 drm_framebuffer_unreference(fb);
10035
10036 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10037 if (ret)
10038 goto fail;
10039
10040 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10041 if (!ret)
10042 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10043 if (!ret)
10044 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10045 if (ret) {
10046 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10047 goto fail;
10048 }
10049
10050 ret = drm_atomic_commit(state);
10051 if (ret) {
10052 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10053 goto fail;
10054 }
10055
10056 old->restore_state = restore_state;
10057 drm_atomic_state_put(state);
10058
10059 /* let the connector get through one full cycle before testing */
10060 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10061 return true;
10062
10063 fail:
10064 if (state) {
10065 drm_atomic_state_put(state);
10066 state = NULL;
10067 }
10068 if (restore_state) {
10069 drm_atomic_state_put(restore_state);
10070 restore_state = NULL;
10071 }
10072
10073 if (ret == -EDEADLK)
10074 return ret;
10075
10076 return false;
10077 }
10078
10079 void intel_release_load_detect_pipe(struct drm_connector *connector,
10080 struct intel_load_detect_pipe *old,
10081 struct drm_modeset_acquire_ctx *ctx)
10082 {
10083 struct intel_encoder *intel_encoder =
10084 intel_attached_encoder(connector);
10085 struct drm_encoder *encoder = &intel_encoder->base;
10086 struct drm_atomic_state *state = old->restore_state;
10087 int ret;
10088
10089 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10090 connector->base.id, connector->name,
10091 encoder->base.id, encoder->name);
10092
10093 if (!state)
10094 return;
10095
10096 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10097 if (ret)
10098 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10099 drm_atomic_state_put(state);
10100 }
10101
10102 static int i9xx_pll_refclk(struct drm_device *dev,
10103 const struct intel_crtc_state *pipe_config)
10104 {
10105 struct drm_i915_private *dev_priv = to_i915(dev);
10106 u32 dpll = pipe_config->dpll_hw_state.dpll;
10107
10108 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10109 return dev_priv->vbt.lvds_ssc_freq;
10110 else if (HAS_PCH_SPLIT(dev_priv))
10111 return 120000;
10112 else if (!IS_GEN2(dev_priv))
10113 return 96000;
10114 else
10115 return 48000;
10116 }
10117
10118 /* Returns the clock of the currently programmed mode of the given pipe. */
10119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10120 struct intel_crtc_state *pipe_config)
10121 {
10122 struct drm_device *dev = crtc->base.dev;
10123 struct drm_i915_private *dev_priv = to_i915(dev);
10124 int pipe = pipe_config->cpu_transcoder;
10125 u32 dpll = pipe_config->dpll_hw_state.dpll;
10126 u32 fp;
10127 struct dpll clock;
10128 int port_clock;
10129 int refclk = i9xx_pll_refclk(dev, pipe_config);
10130
10131 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10132 fp = pipe_config->dpll_hw_state.fp0;
10133 else
10134 fp = pipe_config->dpll_hw_state.fp1;
10135
10136 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10137 if (IS_PINEVIEW(dev_priv)) {
10138 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10139 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10140 } else {
10141 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10142 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10143 }
10144
10145 if (!IS_GEN2(dev_priv)) {
10146 if (IS_PINEVIEW(dev_priv))
10147 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10148 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10149 else
10150 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10151 DPLL_FPA01_P1_POST_DIV_SHIFT);
10152
10153 switch (dpll & DPLL_MODE_MASK) {
10154 case DPLLB_MODE_DAC_SERIAL:
10155 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10156 5 : 10;
10157 break;
10158 case DPLLB_MODE_LVDS:
10159 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10160 7 : 14;
10161 break;
10162 default:
10163 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10164 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10165 return;
10166 }
10167
10168 if (IS_PINEVIEW(dev_priv))
10169 port_clock = pnv_calc_dpll_params(refclk, &clock);
10170 else
10171 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10172 } else {
10173 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10174 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10175
10176 if (is_lvds) {
10177 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10178 DPLL_FPA01_P1_POST_DIV_SHIFT);
10179
10180 if (lvds & LVDS_CLKB_POWER_UP)
10181 clock.p2 = 7;
10182 else
10183 clock.p2 = 14;
10184 } else {
10185 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10186 clock.p1 = 2;
10187 else {
10188 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10189 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10190 }
10191 if (dpll & PLL_P2_DIVIDE_BY_4)
10192 clock.p2 = 4;
10193 else
10194 clock.p2 = 2;
10195 }
10196
10197 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10198 }
10199
10200 /*
10201 * This value includes pixel_multiplier. We will use
10202 * port_clock to compute adjusted_mode.crtc_clock in the
10203 * encoder's get_config() function.
10204 */
10205 pipe_config->port_clock = port_clock;
10206 }
10207
10208 int intel_dotclock_calculate(int link_freq,
10209 const struct intel_link_m_n *m_n)
10210 {
10211 /*
10212 * The calculation for the data clock is:
10213 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10214 * But we want to avoid losing precison if possible, so:
10215 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10216 *
10217 * and the link clock is simpler:
10218 * link_clock = (m * link_clock) / n
10219 */
10220
10221 if (!m_n->link_n)
10222 return 0;
10223
10224 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10225 }
10226
10227 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10228 struct intel_crtc_state *pipe_config)
10229 {
10230 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10231
10232 /* read out port_clock from the DPLL */
10233 i9xx_crtc_clock_get(crtc, pipe_config);
10234
10235 /*
10236 * In case there is an active pipe without active ports,
10237 * we may need some idea for the dotclock anyway.
10238 * Calculate one based on the FDI configuration.
10239 */
10240 pipe_config->base.adjusted_mode.crtc_clock =
10241 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10242 &pipe_config->fdi_m_n);
10243 }
10244
10245 /** Returns the currently programmed mode of the given pipe. */
10246 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10247 struct drm_crtc *crtc)
10248 {
10249 struct drm_i915_private *dev_priv = to_i915(dev);
10250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10251 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10252 struct drm_display_mode *mode;
10253 struct intel_crtc_state *pipe_config;
10254 int htot = I915_READ(HTOTAL(cpu_transcoder));
10255 int hsync = I915_READ(HSYNC(cpu_transcoder));
10256 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10257 int vsync = I915_READ(VSYNC(cpu_transcoder));
10258 enum pipe pipe = intel_crtc->pipe;
10259
10260 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10261 if (!mode)
10262 return NULL;
10263
10264 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10265 if (!pipe_config) {
10266 kfree(mode);
10267 return NULL;
10268 }
10269
10270 /*
10271 * Construct a pipe_config sufficient for getting the clock info
10272 * back out of crtc_clock_get.
10273 *
10274 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10275 * to use a real value here instead.
10276 */
10277 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10278 pipe_config->pixel_multiplier = 1;
10279 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10280 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10281 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10282 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10283
10284 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10285 mode->hdisplay = (htot & 0xffff) + 1;
10286 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10287 mode->hsync_start = (hsync & 0xffff) + 1;
10288 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10289 mode->vdisplay = (vtot & 0xffff) + 1;
10290 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10291 mode->vsync_start = (vsync & 0xffff) + 1;
10292 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10293
10294 drm_mode_set_name(mode);
10295
10296 kfree(pipe_config);
10297
10298 return mode;
10299 }
10300
10301 static void intel_crtc_destroy(struct drm_crtc *crtc)
10302 {
10303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10304
10305 drm_crtc_cleanup(crtc);
10306 kfree(intel_crtc);
10307 }
10308
10309 /**
10310 * intel_wm_need_update - Check whether watermarks need updating
10311 * @plane: drm plane
10312 * @state: new plane state
10313 *
10314 * Check current plane state versus the new one to determine whether
10315 * watermarks need to be recalculated.
10316 *
10317 * Returns true or false.
10318 */
10319 static bool intel_wm_need_update(struct drm_plane *plane,
10320 struct drm_plane_state *state)
10321 {
10322 struct intel_plane_state *new = to_intel_plane_state(state);
10323 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10324
10325 /* Update watermarks on tiling or size changes. */
10326 if (new->base.visible != cur->base.visible)
10327 return true;
10328
10329 if (!cur->base.fb || !new->base.fb)
10330 return false;
10331
10332 if (cur->base.fb->modifier != new->base.fb->modifier ||
10333 cur->base.rotation != new->base.rotation ||
10334 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10335 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10336 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10337 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10338 return true;
10339
10340 return false;
10341 }
10342
10343 static bool needs_scaling(struct intel_plane_state *state)
10344 {
10345 int src_w = drm_rect_width(&state->base.src) >> 16;
10346 int src_h = drm_rect_height(&state->base.src) >> 16;
10347 int dst_w = drm_rect_width(&state->base.dst);
10348 int dst_h = drm_rect_height(&state->base.dst);
10349
10350 return (src_w != dst_w || src_h != dst_h);
10351 }
10352
10353 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10354 struct drm_plane_state *plane_state)
10355 {
10356 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10357 struct drm_crtc *crtc = crtc_state->crtc;
10358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10359 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10360 struct drm_device *dev = crtc->dev;
10361 struct drm_i915_private *dev_priv = to_i915(dev);
10362 struct intel_plane_state *old_plane_state =
10363 to_intel_plane_state(plane->base.state);
10364 bool mode_changed = needs_modeset(crtc_state);
10365 bool was_crtc_enabled = crtc->state->active;
10366 bool is_crtc_enabled = crtc_state->active;
10367 bool turn_off, turn_on, visible, was_visible;
10368 struct drm_framebuffer *fb = plane_state->fb;
10369 int ret;
10370
10371 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10372 ret = skl_update_scaler_plane(
10373 to_intel_crtc_state(crtc_state),
10374 to_intel_plane_state(plane_state));
10375 if (ret)
10376 return ret;
10377 }
10378
10379 was_visible = old_plane_state->base.visible;
10380 visible = plane_state->visible;
10381
10382 if (!was_crtc_enabled && WARN_ON(was_visible))
10383 was_visible = false;
10384
10385 /*
10386 * Visibility is calculated as if the crtc was on, but
10387 * after scaler setup everything depends on it being off
10388 * when the crtc isn't active.
10389 *
10390 * FIXME this is wrong for watermarks. Watermarks should also
10391 * be computed as if the pipe would be active. Perhaps move
10392 * per-plane wm computation to the .check_plane() hook, and
10393 * only combine the results from all planes in the current place?
10394 */
10395 if (!is_crtc_enabled) {
10396 plane_state->visible = visible = false;
10397 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10398 }
10399
10400 if (!was_visible && !visible)
10401 return 0;
10402
10403 if (fb != old_plane_state->base.fb)
10404 pipe_config->fb_changed = true;
10405
10406 turn_off = was_visible && (!visible || mode_changed);
10407 turn_on = visible && (!was_visible || mode_changed);
10408
10409 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10410 intel_crtc->base.base.id, intel_crtc->base.name,
10411 plane->base.base.id, plane->base.name,
10412 fb ? fb->base.id : -1);
10413
10414 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10415 plane->base.base.id, plane->base.name,
10416 was_visible, visible,
10417 turn_off, turn_on, mode_changed);
10418
10419 if (turn_on) {
10420 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10421 pipe_config->update_wm_pre = true;
10422
10423 /* must disable cxsr around plane enable/disable */
10424 if (plane->id != PLANE_CURSOR)
10425 pipe_config->disable_cxsr = true;
10426 } else if (turn_off) {
10427 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10428 pipe_config->update_wm_post = true;
10429
10430 /* must disable cxsr around plane enable/disable */
10431 if (plane->id != PLANE_CURSOR)
10432 pipe_config->disable_cxsr = true;
10433 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10434 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10435 /* FIXME bollocks */
10436 pipe_config->update_wm_pre = true;
10437 pipe_config->update_wm_post = true;
10438 }
10439 }
10440
10441 if (visible || was_visible)
10442 pipe_config->fb_bits |= plane->frontbuffer_bit;
10443
10444 /*
10445 * WaCxSRDisabledForSpriteScaling:ivb
10446 *
10447 * cstate->update_wm was already set above, so this flag will
10448 * take effect when we commit and program watermarks.
10449 */
10450 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10451 needs_scaling(to_intel_plane_state(plane_state)) &&
10452 !needs_scaling(old_plane_state))
10453 pipe_config->disable_lp_wm = true;
10454
10455 return 0;
10456 }
10457
10458 static bool encoders_cloneable(const struct intel_encoder *a,
10459 const struct intel_encoder *b)
10460 {
10461 /* masks could be asymmetric, so check both ways */
10462 return a == b || (a->cloneable & (1 << b->type) &&
10463 b->cloneable & (1 << a->type));
10464 }
10465
10466 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10467 struct intel_crtc *crtc,
10468 struct intel_encoder *encoder)
10469 {
10470 struct intel_encoder *source_encoder;
10471 struct drm_connector *connector;
10472 struct drm_connector_state *connector_state;
10473 int i;
10474
10475 for_each_new_connector_in_state(state, connector, connector_state, i) {
10476 if (connector_state->crtc != &crtc->base)
10477 continue;
10478
10479 source_encoder =
10480 to_intel_encoder(connector_state->best_encoder);
10481 if (!encoders_cloneable(encoder, source_encoder))
10482 return false;
10483 }
10484
10485 return true;
10486 }
10487
10488 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10489 struct drm_crtc_state *crtc_state)
10490 {
10491 struct drm_device *dev = crtc->dev;
10492 struct drm_i915_private *dev_priv = to_i915(dev);
10493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10494 struct intel_crtc_state *pipe_config =
10495 to_intel_crtc_state(crtc_state);
10496 struct drm_atomic_state *state = crtc_state->state;
10497 int ret;
10498 bool mode_changed = needs_modeset(crtc_state);
10499
10500 if (mode_changed && !crtc_state->active)
10501 pipe_config->update_wm_post = true;
10502
10503 if (mode_changed && crtc_state->enable &&
10504 dev_priv->display.crtc_compute_clock &&
10505 !WARN_ON(pipe_config->shared_dpll)) {
10506 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10507 pipe_config);
10508 if (ret)
10509 return ret;
10510 }
10511
10512 if (crtc_state->color_mgmt_changed) {
10513 ret = intel_color_check(crtc, crtc_state);
10514 if (ret)
10515 return ret;
10516
10517 /*
10518 * Changing color management on Intel hardware is
10519 * handled as part of planes update.
10520 */
10521 crtc_state->planes_changed = true;
10522 }
10523
10524 ret = 0;
10525 if (dev_priv->display.compute_pipe_wm) {
10526 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10527 if (ret) {
10528 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10529 return ret;
10530 }
10531 }
10532
10533 if (dev_priv->display.compute_intermediate_wm &&
10534 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10535 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10536 return 0;
10537
10538 /*
10539 * Calculate 'intermediate' watermarks that satisfy both the
10540 * old state and the new state. We can program these
10541 * immediately.
10542 */
10543 ret = dev_priv->display.compute_intermediate_wm(dev,
10544 intel_crtc,
10545 pipe_config);
10546 if (ret) {
10547 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10548 return ret;
10549 }
10550 } else if (dev_priv->display.compute_intermediate_wm) {
10551 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10552 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10553 }
10554
10555 if (INTEL_GEN(dev_priv) >= 9) {
10556 if (mode_changed)
10557 ret = skl_update_scaler_crtc(pipe_config);
10558
10559 if (!ret)
10560 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10561 pipe_config);
10562 if (!ret)
10563 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10564 pipe_config);
10565 }
10566
10567 return ret;
10568 }
10569
10570 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10571 .atomic_begin = intel_begin_crtc_commit,
10572 .atomic_flush = intel_finish_crtc_commit,
10573 .atomic_check = intel_crtc_atomic_check,
10574 };
10575
10576 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10577 {
10578 struct intel_connector *connector;
10579 struct drm_connector_list_iter conn_iter;
10580
10581 drm_connector_list_iter_begin(dev, &conn_iter);
10582 for_each_intel_connector_iter(connector, &conn_iter) {
10583 if (connector->base.state->crtc)
10584 drm_connector_unreference(&connector->base);
10585
10586 if (connector->base.encoder) {
10587 connector->base.state->best_encoder =
10588 connector->base.encoder;
10589 connector->base.state->crtc =
10590 connector->base.encoder->crtc;
10591
10592 drm_connector_reference(&connector->base);
10593 } else {
10594 connector->base.state->best_encoder = NULL;
10595 connector->base.state->crtc = NULL;
10596 }
10597 }
10598 drm_connector_list_iter_end(&conn_iter);
10599 }
10600
10601 static void
10602 connected_sink_compute_bpp(struct intel_connector *connector,
10603 struct intel_crtc_state *pipe_config)
10604 {
10605 const struct drm_display_info *info = &connector->base.display_info;
10606 int bpp = pipe_config->pipe_bpp;
10607
10608 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10609 connector->base.base.id,
10610 connector->base.name);
10611
10612 /* Don't use an invalid EDID bpc value */
10613 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10614 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10615 bpp, info->bpc * 3);
10616 pipe_config->pipe_bpp = info->bpc * 3;
10617 }
10618
10619 /* Clamp bpp to 8 on screens without EDID 1.4 */
10620 if (info->bpc == 0 && bpp > 24) {
10621 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10622 bpp);
10623 pipe_config->pipe_bpp = 24;
10624 }
10625 }
10626
10627 static int
10628 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10629 struct intel_crtc_state *pipe_config)
10630 {
10631 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10632 struct drm_atomic_state *state;
10633 struct drm_connector *connector;
10634 struct drm_connector_state *connector_state;
10635 int bpp, i;
10636
10637 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10638 IS_CHERRYVIEW(dev_priv)))
10639 bpp = 10*3;
10640 else if (INTEL_GEN(dev_priv) >= 5)
10641 bpp = 12*3;
10642 else
10643 bpp = 8*3;
10644
10645
10646 pipe_config->pipe_bpp = bpp;
10647
10648 state = pipe_config->base.state;
10649
10650 /* Clamp display bpp to EDID value */
10651 for_each_new_connector_in_state(state, connector, connector_state, i) {
10652 if (connector_state->crtc != &crtc->base)
10653 continue;
10654
10655 connected_sink_compute_bpp(to_intel_connector(connector),
10656 pipe_config);
10657 }
10658
10659 return bpp;
10660 }
10661
10662 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10663 {
10664 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10665 "type: 0x%x flags: 0x%x\n",
10666 mode->crtc_clock,
10667 mode->crtc_hdisplay, mode->crtc_hsync_start,
10668 mode->crtc_hsync_end, mode->crtc_htotal,
10669 mode->crtc_vdisplay, mode->crtc_vsync_start,
10670 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10671 }
10672
10673 static inline void
10674 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10675 unsigned int lane_count, struct intel_link_m_n *m_n)
10676 {
10677 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10678 id, lane_count,
10679 m_n->gmch_m, m_n->gmch_n,
10680 m_n->link_m, m_n->link_n, m_n->tu);
10681 }
10682
10683 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10684 struct intel_crtc_state *pipe_config,
10685 const char *context)
10686 {
10687 struct drm_device *dev = crtc->base.dev;
10688 struct drm_i915_private *dev_priv = to_i915(dev);
10689 struct drm_plane *plane;
10690 struct intel_plane *intel_plane;
10691 struct intel_plane_state *state;
10692 struct drm_framebuffer *fb;
10693
10694 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10695 crtc->base.base.id, crtc->base.name, context);
10696
10697 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10698 transcoder_name(pipe_config->cpu_transcoder),
10699 pipe_config->pipe_bpp, pipe_config->dither);
10700
10701 if (pipe_config->has_pch_encoder)
10702 intel_dump_m_n_config(pipe_config, "fdi",
10703 pipe_config->fdi_lanes,
10704 &pipe_config->fdi_m_n);
10705
10706 if (pipe_config->ycbcr420)
10707 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10708
10709 if (intel_crtc_has_dp_encoder(pipe_config)) {
10710 intel_dump_m_n_config(pipe_config, "dp m_n",
10711 pipe_config->lane_count, &pipe_config->dp_m_n);
10712 if (pipe_config->has_drrs)
10713 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10714 pipe_config->lane_count,
10715 &pipe_config->dp_m2_n2);
10716 }
10717
10718 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10719 pipe_config->has_audio, pipe_config->has_infoframe);
10720
10721 DRM_DEBUG_KMS("requested mode:\n");
10722 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10723 DRM_DEBUG_KMS("adjusted mode:\n");
10724 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10725 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10726 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10727 pipe_config->port_clock,
10728 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10729 pipe_config->pixel_rate);
10730
10731 if (INTEL_GEN(dev_priv) >= 9)
10732 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10733 crtc->num_scalers,
10734 pipe_config->scaler_state.scaler_users,
10735 pipe_config->scaler_state.scaler_id);
10736
10737 if (HAS_GMCH_DISPLAY(dev_priv))
10738 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10739 pipe_config->gmch_pfit.control,
10740 pipe_config->gmch_pfit.pgm_ratios,
10741 pipe_config->gmch_pfit.lvds_border_bits);
10742 else
10743 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10744 pipe_config->pch_pfit.pos,
10745 pipe_config->pch_pfit.size,
10746 enableddisabled(pipe_config->pch_pfit.enabled));
10747
10748 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10749 pipe_config->ips_enabled, pipe_config->double_wide);
10750
10751 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10752
10753 DRM_DEBUG_KMS("planes on this crtc\n");
10754 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10755 struct drm_format_name_buf format_name;
10756 intel_plane = to_intel_plane(plane);
10757 if (intel_plane->pipe != crtc->pipe)
10758 continue;
10759
10760 state = to_intel_plane_state(plane->state);
10761 fb = state->base.fb;
10762 if (!fb) {
10763 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10764 plane->base.id, plane->name, state->scaler_id);
10765 continue;
10766 }
10767
10768 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10769 plane->base.id, plane->name,
10770 fb->base.id, fb->width, fb->height,
10771 drm_get_format_name(fb->format->format, &format_name));
10772 if (INTEL_GEN(dev_priv) >= 9)
10773 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10774 state->scaler_id,
10775 state->base.src.x1 >> 16,
10776 state->base.src.y1 >> 16,
10777 drm_rect_width(&state->base.src) >> 16,
10778 drm_rect_height(&state->base.src) >> 16,
10779 state->base.dst.x1, state->base.dst.y1,
10780 drm_rect_width(&state->base.dst),
10781 drm_rect_height(&state->base.dst));
10782 }
10783 }
10784
10785 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10786 {
10787 struct drm_device *dev = state->dev;
10788 struct drm_connector *connector;
10789 struct drm_connector_list_iter conn_iter;
10790 unsigned int used_ports = 0;
10791 unsigned int used_mst_ports = 0;
10792
10793 /*
10794 * Walk the connector list instead of the encoder
10795 * list to detect the problem on ddi platforms
10796 * where there's just one encoder per digital port.
10797 */
10798 drm_connector_list_iter_begin(dev, &conn_iter);
10799 drm_for_each_connector_iter(connector, &conn_iter) {
10800 struct drm_connector_state *connector_state;
10801 struct intel_encoder *encoder;
10802
10803 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10804 if (!connector_state)
10805 connector_state = connector->state;
10806
10807 if (!connector_state->best_encoder)
10808 continue;
10809
10810 encoder = to_intel_encoder(connector_state->best_encoder);
10811
10812 WARN_ON(!connector_state->crtc);
10813
10814 switch (encoder->type) {
10815 unsigned int port_mask;
10816 case INTEL_OUTPUT_UNKNOWN:
10817 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10818 break;
10819 case INTEL_OUTPUT_DP:
10820 case INTEL_OUTPUT_HDMI:
10821 case INTEL_OUTPUT_EDP:
10822 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10823
10824 /* the same port mustn't appear more than once */
10825 if (used_ports & port_mask)
10826 return false;
10827
10828 used_ports |= port_mask;
10829 break;
10830 case INTEL_OUTPUT_DP_MST:
10831 used_mst_ports |=
10832 1 << enc_to_mst(&encoder->base)->primary->port;
10833 break;
10834 default:
10835 break;
10836 }
10837 }
10838 drm_connector_list_iter_end(&conn_iter);
10839
10840 /* can't mix MST and SST/HDMI on the same port */
10841 if (used_ports & used_mst_ports)
10842 return false;
10843
10844 return true;
10845 }
10846
10847 static void
10848 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10849 {
10850 struct drm_i915_private *dev_priv =
10851 to_i915(crtc_state->base.crtc->dev);
10852 struct intel_crtc_scaler_state scaler_state;
10853 struct intel_dpll_hw_state dpll_hw_state;
10854 struct intel_shared_dpll *shared_dpll;
10855 struct intel_crtc_wm_state wm_state;
10856 bool force_thru, ips_force_disable;
10857
10858 /* FIXME: before the switch to atomic started, a new pipe_config was
10859 * kzalloc'd. Code that depends on any field being zero should be
10860 * fixed, so that the crtc_state can be safely duplicated. For now,
10861 * only fields that are know to not cause problems are preserved. */
10862
10863 scaler_state = crtc_state->scaler_state;
10864 shared_dpll = crtc_state->shared_dpll;
10865 dpll_hw_state = crtc_state->dpll_hw_state;
10866 force_thru = crtc_state->pch_pfit.force_thru;
10867 ips_force_disable = crtc_state->ips_force_disable;
10868 if (IS_G4X(dev_priv) ||
10869 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10870 wm_state = crtc_state->wm;
10871
10872 /* Keep base drm_crtc_state intact, only clear our extended struct */
10873 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10874 memset(&crtc_state->base + 1, 0,
10875 sizeof(*crtc_state) - sizeof(crtc_state->base));
10876
10877 crtc_state->scaler_state = scaler_state;
10878 crtc_state->shared_dpll = shared_dpll;
10879 crtc_state->dpll_hw_state = dpll_hw_state;
10880 crtc_state->pch_pfit.force_thru = force_thru;
10881 crtc_state->ips_force_disable = ips_force_disable;
10882 if (IS_G4X(dev_priv) ||
10883 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10884 crtc_state->wm = wm_state;
10885 }
10886
10887 static int
10888 intel_modeset_pipe_config(struct drm_crtc *crtc,
10889 struct intel_crtc_state *pipe_config)
10890 {
10891 struct drm_atomic_state *state = pipe_config->base.state;
10892 struct intel_encoder *encoder;
10893 struct drm_connector *connector;
10894 struct drm_connector_state *connector_state;
10895 int base_bpp, ret = -EINVAL;
10896 int i;
10897 bool retry = true;
10898
10899 clear_intel_crtc_state(pipe_config);
10900
10901 pipe_config->cpu_transcoder =
10902 (enum transcoder) to_intel_crtc(crtc)->pipe;
10903
10904 /*
10905 * Sanitize sync polarity flags based on requested ones. If neither
10906 * positive or negative polarity is requested, treat this as meaning
10907 * negative polarity.
10908 */
10909 if (!(pipe_config->base.adjusted_mode.flags &
10910 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10911 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10912
10913 if (!(pipe_config->base.adjusted_mode.flags &
10914 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10915 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10916
10917 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10918 pipe_config);
10919 if (base_bpp < 0)
10920 goto fail;
10921
10922 /*
10923 * Determine the real pipe dimensions. Note that stereo modes can
10924 * increase the actual pipe size due to the frame doubling and
10925 * insertion of additional space for blanks between the frame. This
10926 * is stored in the crtc timings. We use the requested mode to do this
10927 * computation to clearly distinguish it from the adjusted mode, which
10928 * can be changed by the connectors in the below retry loop.
10929 */
10930 drm_mode_get_hv_timing(&pipe_config->base.mode,
10931 &pipe_config->pipe_src_w,
10932 &pipe_config->pipe_src_h);
10933
10934 for_each_new_connector_in_state(state, connector, connector_state, i) {
10935 if (connector_state->crtc != crtc)
10936 continue;
10937
10938 encoder = to_intel_encoder(connector_state->best_encoder);
10939
10940 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10941 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10942 goto fail;
10943 }
10944
10945 /*
10946 * Determine output_types before calling the .compute_config()
10947 * hooks so that the hooks can use this information safely.
10948 */
10949 pipe_config->output_types |= 1 << encoder->type;
10950 }
10951
10952 encoder_retry:
10953 /* Ensure the port clock defaults are reset when retrying. */
10954 pipe_config->port_clock = 0;
10955 pipe_config->pixel_multiplier = 1;
10956
10957 /* Fill in default crtc timings, allow encoders to overwrite them. */
10958 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10959 CRTC_STEREO_DOUBLE);
10960
10961 /* Pass our mode to the connectors and the CRTC to give them a chance to
10962 * adjust it according to limitations or connector properties, and also
10963 * a chance to reject the mode entirely.
10964 */
10965 for_each_new_connector_in_state(state, connector, connector_state, i) {
10966 if (connector_state->crtc != crtc)
10967 continue;
10968
10969 encoder = to_intel_encoder(connector_state->best_encoder);
10970
10971 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10972 DRM_DEBUG_KMS("Encoder config failure\n");
10973 goto fail;
10974 }
10975 }
10976
10977 /* Set default port clock if not overwritten by the encoder. Needs to be
10978 * done afterwards in case the encoder adjusts the mode. */
10979 if (!pipe_config->port_clock)
10980 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10981 * pipe_config->pixel_multiplier;
10982
10983 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10984 if (ret < 0) {
10985 DRM_DEBUG_KMS("CRTC fixup failed\n");
10986 goto fail;
10987 }
10988
10989 if (ret == RETRY) {
10990 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10991 ret = -EINVAL;
10992 goto fail;
10993 }
10994
10995 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10996 retry = false;
10997 goto encoder_retry;
10998 }
10999
11000 /* Dithering seems to not pass-through bits correctly when it should, so
11001 * only enable it on 6bpc panels and when its not a compliance
11002 * test requesting 6bpc video pattern.
11003 */
11004 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11005 !pipe_config->dither_force_disable;
11006 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11007 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11008
11009 fail:
11010 return ret;
11011 }
11012
11013 static void
11014 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11015 {
11016 struct drm_crtc *crtc;
11017 struct drm_crtc_state *new_crtc_state;
11018 int i;
11019
11020 /* Double check state. */
11021 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11022 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11023
11024 /*
11025 * Update legacy state to satisfy fbc code. This can
11026 * be removed when fbc uses the atomic state.
11027 */
11028 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11029 struct drm_plane_state *plane_state = crtc->primary->state;
11030
11031 crtc->primary->fb = plane_state->fb;
11032 crtc->x = plane_state->src_x >> 16;
11033 crtc->y = plane_state->src_y >> 16;
11034 }
11035 }
11036 }
11037
11038 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11039 {
11040 int diff;
11041
11042 if (clock1 == clock2)
11043 return true;
11044
11045 if (!clock1 || !clock2)
11046 return false;
11047
11048 diff = abs(clock1 - clock2);
11049
11050 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11051 return true;
11052
11053 return false;
11054 }
11055
11056 static bool
11057 intel_compare_m_n(unsigned int m, unsigned int n,
11058 unsigned int m2, unsigned int n2,
11059 bool exact)
11060 {
11061 if (m == m2 && n == n2)
11062 return true;
11063
11064 if (exact || !m || !n || !m2 || !n2)
11065 return false;
11066
11067 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11068
11069 if (n > n2) {
11070 while (n > n2) {
11071 m2 <<= 1;
11072 n2 <<= 1;
11073 }
11074 } else if (n < n2) {
11075 while (n < n2) {
11076 m <<= 1;
11077 n <<= 1;
11078 }
11079 }
11080
11081 if (n != n2)
11082 return false;
11083
11084 return intel_fuzzy_clock_check(m, m2);
11085 }
11086
11087 static bool
11088 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11089 struct intel_link_m_n *m2_n2,
11090 bool adjust)
11091 {
11092 if (m_n->tu == m2_n2->tu &&
11093 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11094 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11095 intel_compare_m_n(m_n->link_m, m_n->link_n,
11096 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11097 if (adjust)
11098 *m2_n2 = *m_n;
11099
11100 return true;
11101 }
11102
11103 return false;
11104 }
11105
11106 static void __printf(3, 4)
11107 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11108 {
11109 char *level;
11110 unsigned int category;
11111 struct va_format vaf;
11112 va_list args;
11113
11114 if (adjust) {
11115 level = KERN_DEBUG;
11116 category = DRM_UT_KMS;
11117 } else {
11118 level = KERN_ERR;
11119 category = DRM_UT_NONE;
11120 }
11121
11122 va_start(args, format);
11123 vaf.fmt = format;
11124 vaf.va = &args;
11125
11126 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11127
11128 va_end(args);
11129 }
11130
11131 static bool
11132 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11133 struct intel_crtc_state *current_config,
11134 struct intel_crtc_state *pipe_config,
11135 bool adjust)
11136 {
11137 bool ret = true;
11138
11139 #define PIPE_CONF_CHECK_X(name) \
11140 if (current_config->name != pipe_config->name) { \
11141 pipe_config_err(adjust, __stringify(name), \
11142 "(expected 0x%08x, found 0x%08x)\n", \
11143 current_config->name, \
11144 pipe_config->name); \
11145 ret = false; \
11146 }
11147
11148 #define PIPE_CONF_CHECK_I(name) \
11149 if (current_config->name != pipe_config->name) { \
11150 pipe_config_err(adjust, __stringify(name), \
11151 "(expected %i, found %i)\n", \
11152 current_config->name, \
11153 pipe_config->name); \
11154 ret = false; \
11155 }
11156
11157 #define PIPE_CONF_CHECK_P(name) \
11158 if (current_config->name != pipe_config->name) { \
11159 pipe_config_err(adjust, __stringify(name), \
11160 "(expected %p, found %p)\n", \
11161 current_config->name, \
11162 pipe_config->name); \
11163 ret = false; \
11164 }
11165
11166 #define PIPE_CONF_CHECK_M_N(name) \
11167 if (!intel_compare_link_m_n(&current_config->name, \
11168 &pipe_config->name,\
11169 adjust)) { \
11170 pipe_config_err(adjust, __stringify(name), \
11171 "(expected tu %i gmch %i/%i link %i/%i, " \
11172 "found tu %i, gmch %i/%i link %i/%i)\n", \
11173 current_config->name.tu, \
11174 current_config->name.gmch_m, \
11175 current_config->name.gmch_n, \
11176 current_config->name.link_m, \
11177 current_config->name.link_n, \
11178 pipe_config->name.tu, \
11179 pipe_config->name.gmch_m, \
11180 pipe_config->name.gmch_n, \
11181 pipe_config->name.link_m, \
11182 pipe_config->name.link_n); \
11183 ret = false; \
11184 }
11185
11186 /* This is required for BDW+ where there is only one set of registers for
11187 * switching between high and low RR.
11188 * This macro can be used whenever a comparison has to be made between one
11189 * hw state and multiple sw state variables.
11190 */
11191 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11192 if (!intel_compare_link_m_n(&current_config->name, \
11193 &pipe_config->name, adjust) && \
11194 !intel_compare_link_m_n(&current_config->alt_name, \
11195 &pipe_config->name, adjust)) { \
11196 pipe_config_err(adjust, __stringify(name), \
11197 "(expected tu %i gmch %i/%i link %i/%i, " \
11198 "or tu %i gmch %i/%i link %i/%i, " \
11199 "found tu %i, gmch %i/%i link %i/%i)\n", \
11200 current_config->name.tu, \
11201 current_config->name.gmch_m, \
11202 current_config->name.gmch_n, \
11203 current_config->name.link_m, \
11204 current_config->name.link_n, \
11205 current_config->alt_name.tu, \
11206 current_config->alt_name.gmch_m, \
11207 current_config->alt_name.gmch_n, \
11208 current_config->alt_name.link_m, \
11209 current_config->alt_name.link_n, \
11210 pipe_config->name.tu, \
11211 pipe_config->name.gmch_m, \
11212 pipe_config->name.gmch_n, \
11213 pipe_config->name.link_m, \
11214 pipe_config->name.link_n); \
11215 ret = false; \
11216 }
11217
11218 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11219 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11220 pipe_config_err(adjust, __stringify(name), \
11221 "(%x) (expected %i, found %i)\n", \
11222 (mask), \
11223 current_config->name & (mask), \
11224 pipe_config->name & (mask)); \
11225 ret = false; \
11226 }
11227
11228 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11229 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11230 pipe_config_err(adjust, __stringify(name), \
11231 "(expected %i, found %i)\n", \
11232 current_config->name, \
11233 pipe_config->name); \
11234 ret = false; \
11235 }
11236
11237 #define PIPE_CONF_QUIRK(quirk) \
11238 ((current_config->quirks | pipe_config->quirks) & (quirk))
11239
11240 PIPE_CONF_CHECK_I(cpu_transcoder);
11241
11242 PIPE_CONF_CHECK_I(has_pch_encoder);
11243 PIPE_CONF_CHECK_I(fdi_lanes);
11244 PIPE_CONF_CHECK_M_N(fdi_m_n);
11245
11246 PIPE_CONF_CHECK_I(lane_count);
11247 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11248
11249 if (INTEL_GEN(dev_priv) < 8) {
11250 PIPE_CONF_CHECK_M_N(dp_m_n);
11251
11252 if (current_config->has_drrs)
11253 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11254 } else
11255 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11256
11257 PIPE_CONF_CHECK_X(output_types);
11258
11259 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11260 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11261 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11262 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11263 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11264 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11265
11266 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11267 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11268 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11269 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11270 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11271 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11272
11273 PIPE_CONF_CHECK_I(pixel_multiplier);
11274 PIPE_CONF_CHECK_I(has_hdmi_sink);
11275 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11276 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11277 PIPE_CONF_CHECK_I(limited_color_range);
11278
11279 PIPE_CONF_CHECK_I(hdmi_scrambling);
11280 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11281 PIPE_CONF_CHECK_I(has_infoframe);
11282 PIPE_CONF_CHECK_I(ycbcr420);
11283
11284 PIPE_CONF_CHECK_I(has_audio);
11285
11286 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11287 DRM_MODE_FLAG_INTERLACE);
11288
11289 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11290 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11291 DRM_MODE_FLAG_PHSYNC);
11292 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11293 DRM_MODE_FLAG_NHSYNC);
11294 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11295 DRM_MODE_FLAG_PVSYNC);
11296 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11297 DRM_MODE_FLAG_NVSYNC);
11298 }
11299
11300 PIPE_CONF_CHECK_X(gmch_pfit.control);
11301 /* pfit ratios are autocomputed by the hw on gen4+ */
11302 if (INTEL_GEN(dev_priv) < 4)
11303 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11304 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11305
11306 if (!adjust) {
11307 PIPE_CONF_CHECK_I(pipe_src_w);
11308 PIPE_CONF_CHECK_I(pipe_src_h);
11309
11310 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11311 if (current_config->pch_pfit.enabled) {
11312 PIPE_CONF_CHECK_X(pch_pfit.pos);
11313 PIPE_CONF_CHECK_X(pch_pfit.size);
11314 }
11315
11316 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11317 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11318 }
11319
11320 /* BDW+ don't expose a synchronous way to read the state */
11321 if (IS_HASWELL(dev_priv))
11322 PIPE_CONF_CHECK_I(ips_enabled);
11323
11324 PIPE_CONF_CHECK_I(double_wide);
11325
11326 PIPE_CONF_CHECK_P(shared_dpll);
11327 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11328 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11329 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11330 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11331 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11332 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11333 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11334 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11335 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11336
11337 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11338 PIPE_CONF_CHECK_X(dsi_pll.div);
11339
11340 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11341 PIPE_CONF_CHECK_I(pipe_bpp);
11342
11343 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11344 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11345
11346 #undef PIPE_CONF_CHECK_X
11347 #undef PIPE_CONF_CHECK_I
11348 #undef PIPE_CONF_CHECK_P
11349 #undef PIPE_CONF_CHECK_FLAGS
11350 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11351 #undef PIPE_CONF_QUIRK
11352
11353 return ret;
11354 }
11355
11356 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11357 const struct intel_crtc_state *pipe_config)
11358 {
11359 if (pipe_config->has_pch_encoder) {
11360 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11361 &pipe_config->fdi_m_n);
11362 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11363
11364 /*
11365 * FDI already provided one idea for the dotclock.
11366 * Yell if the encoder disagrees.
11367 */
11368 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11369 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11370 fdi_dotclock, dotclock);
11371 }
11372 }
11373
11374 static void verify_wm_state(struct drm_crtc *crtc,
11375 struct drm_crtc_state *new_state)
11376 {
11377 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11378 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11379 struct skl_pipe_wm hw_wm, *sw_wm;
11380 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11381 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11383 const enum pipe pipe = intel_crtc->pipe;
11384 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11385
11386 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11387 return;
11388
11389 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11390 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11391
11392 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11393 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11394
11395 /* planes */
11396 for_each_universal_plane(dev_priv, pipe, plane) {
11397 hw_plane_wm = &hw_wm.planes[plane];
11398 sw_plane_wm = &sw_wm->planes[plane];
11399
11400 /* Watermarks */
11401 for (level = 0; level <= max_level; level++) {
11402 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11403 &sw_plane_wm->wm[level]))
11404 continue;
11405
11406 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11407 pipe_name(pipe), plane + 1, level,
11408 sw_plane_wm->wm[level].plane_en,
11409 sw_plane_wm->wm[level].plane_res_b,
11410 sw_plane_wm->wm[level].plane_res_l,
11411 hw_plane_wm->wm[level].plane_en,
11412 hw_plane_wm->wm[level].plane_res_b,
11413 hw_plane_wm->wm[level].plane_res_l);
11414 }
11415
11416 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11417 &sw_plane_wm->trans_wm)) {
11418 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11419 pipe_name(pipe), plane + 1,
11420 sw_plane_wm->trans_wm.plane_en,
11421 sw_plane_wm->trans_wm.plane_res_b,
11422 sw_plane_wm->trans_wm.plane_res_l,
11423 hw_plane_wm->trans_wm.plane_en,
11424 hw_plane_wm->trans_wm.plane_res_b,
11425 hw_plane_wm->trans_wm.plane_res_l);
11426 }
11427
11428 /* DDB */
11429 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11430 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11431
11432 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11433 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11434 pipe_name(pipe), plane + 1,
11435 sw_ddb_entry->start, sw_ddb_entry->end,
11436 hw_ddb_entry->start, hw_ddb_entry->end);
11437 }
11438 }
11439
11440 /*
11441 * cursor
11442 * If the cursor plane isn't active, we may not have updated it's ddb
11443 * allocation. In that case since the ddb allocation will be updated
11444 * once the plane becomes visible, we can skip this check
11445 */
11446 if (1) {
11447 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11448 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11449
11450 /* Watermarks */
11451 for (level = 0; level <= max_level; level++) {
11452 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11453 &sw_plane_wm->wm[level]))
11454 continue;
11455
11456 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11457 pipe_name(pipe), level,
11458 sw_plane_wm->wm[level].plane_en,
11459 sw_plane_wm->wm[level].plane_res_b,
11460 sw_plane_wm->wm[level].plane_res_l,
11461 hw_plane_wm->wm[level].plane_en,
11462 hw_plane_wm->wm[level].plane_res_b,
11463 hw_plane_wm->wm[level].plane_res_l);
11464 }
11465
11466 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11467 &sw_plane_wm->trans_wm)) {
11468 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11469 pipe_name(pipe),
11470 sw_plane_wm->trans_wm.plane_en,
11471 sw_plane_wm->trans_wm.plane_res_b,
11472 sw_plane_wm->trans_wm.plane_res_l,
11473 hw_plane_wm->trans_wm.plane_en,
11474 hw_plane_wm->trans_wm.plane_res_b,
11475 hw_plane_wm->trans_wm.plane_res_l);
11476 }
11477
11478 /* DDB */
11479 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11480 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11481
11482 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11483 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11484 pipe_name(pipe),
11485 sw_ddb_entry->start, sw_ddb_entry->end,
11486 hw_ddb_entry->start, hw_ddb_entry->end);
11487 }
11488 }
11489 }
11490
11491 static void
11492 verify_connector_state(struct drm_device *dev,
11493 struct drm_atomic_state *state,
11494 struct drm_crtc *crtc)
11495 {
11496 struct drm_connector *connector;
11497 struct drm_connector_state *new_conn_state;
11498 int i;
11499
11500 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11501 struct drm_encoder *encoder = connector->encoder;
11502 struct drm_crtc_state *crtc_state = NULL;
11503
11504 if (new_conn_state->crtc != crtc)
11505 continue;
11506
11507 if (crtc)
11508 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11509
11510 intel_connector_verify_state(crtc_state, new_conn_state);
11511
11512 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11513 "connector's atomic encoder doesn't match legacy encoder\n");
11514 }
11515 }
11516
11517 static void
11518 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11519 {
11520 struct intel_encoder *encoder;
11521 struct drm_connector *connector;
11522 struct drm_connector_state *old_conn_state, *new_conn_state;
11523 int i;
11524
11525 for_each_intel_encoder(dev, encoder) {
11526 bool enabled = false, found = false;
11527 enum pipe pipe;
11528
11529 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11530 encoder->base.base.id,
11531 encoder->base.name);
11532
11533 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11534 new_conn_state, i) {
11535 if (old_conn_state->best_encoder == &encoder->base)
11536 found = true;
11537
11538 if (new_conn_state->best_encoder != &encoder->base)
11539 continue;
11540 found = enabled = true;
11541
11542 I915_STATE_WARN(new_conn_state->crtc !=
11543 encoder->base.crtc,
11544 "connector's crtc doesn't match encoder crtc\n");
11545 }
11546
11547 if (!found)
11548 continue;
11549
11550 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11551 "encoder's enabled state mismatch "
11552 "(expected %i, found %i)\n",
11553 !!encoder->base.crtc, enabled);
11554
11555 if (!encoder->base.crtc) {
11556 bool active;
11557
11558 active = encoder->get_hw_state(encoder, &pipe);
11559 I915_STATE_WARN(active,
11560 "encoder detached but still enabled on pipe %c.\n",
11561 pipe_name(pipe));
11562 }
11563 }
11564 }
11565
11566 static void
11567 verify_crtc_state(struct drm_crtc *crtc,
11568 struct drm_crtc_state *old_crtc_state,
11569 struct drm_crtc_state *new_crtc_state)
11570 {
11571 struct drm_device *dev = crtc->dev;
11572 struct drm_i915_private *dev_priv = to_i915(dev);
11573 struct intel_encoder *encoder;
11574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11575 struct intel_crtc_state *pipe_config, *sw_config;
11576 struct drm_atomic_state *old_state;
11577 bool active;
11578
11579 old_state = old_crtc_state->state;
11580 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11581 pipe_config = to_intel_crtc_state(old_crtc_state);
11582 memset(pipe_config, 0, sizeof(*pipe_config));
11583 pipe_config->base.crtc = crtc;
11584 pipe_config->base.state = old_state;
11585
11586 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11587
11588 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11589
11590 /* we keep both pipes enabled on 830 */
11591 if (IS_I830(dev_priv))
11592 active = new_crtc_state->active;
11593
11594 I915_STATE_WARN(new_crtc_state->active != active,
11595 "crtc active state doesn't match with hw state "
11596 "(expected %i, found %i)\n", new_crtc_state->active, active);
11597
11598 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11599 "transitional active state does not match atomic hw state "
11600 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11601
11602 for_each_encoder_on_crtc(dev, crtc, encoder) {
11603 enum pipe pipe;
11604
11605 active = encoder->get_hw_state(encoder, &pipe);
11606 I915_STATE_WARN(active != new_crtc_state->active,
11607 "[ENCODER:%i] active %i with crtc active %i\n",
11608 encoder->base.base.id, active, new_crtc_state->active);
11609
11610 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11611 "Encoder connected to wrong pipe %c\n",
11612 pipe_name(pipe));
11613
11614 if (active) {
11615 pipe_config->output_types |= 1 << encoder->type;
11616 encoder->get_config(encoder, pipe_config);
11617 }
11618 }
11619
11620 intel_crtc_compute_pixel_rate(pipe_config);
11621
11622 if (!new_crtc_state->active)
11623 return;
11624
11625 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11626
11627 sw_config = to_intel_crtc_state(new_crtc_state);
11628 if (!intel_pipe_config_compare(dev_priv, sw_config,
11629 pipe_config, false)) {
11630 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11631 intel_dump_pipe_config(intel_crtc, pipe_config,
11632 "[hw state]");
11633 intel_dump_pipe_config(intel_crtc, sw_config,
11634 "[sw state]");
11635 }
11636 }
11637
11638 static void
11639 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11640 struct intel_shared_dpll *pll,
11641 struct drm_crtc *crtc,
11642 struct drm_crtc_state *new_state)
11643 {
11644 struct intel_dpll_hw_state dpll_hw_state;
11645 unsigned crtc_mask;
11646 bool active;
11647
11648 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11649
11650 DRM_DEBUG_KMS("%s\n", pll->name);
11651
11652 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11653
11654 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11655 I915_STATE_WARN(!pll->on && pll->active_mask,
11656 "pll in active use but not on in sw tracking\n");
11657 I915_STATE_WARN(pll->on && !pll->active_mask,
11658 "pll is on but not used by any active crtc\n");
11659 I915_STATE_WARN(pll->on != active,
11660 "pll on state mismatch (expected %i, found %i)\n",
11661 pll->on, active);
11662 }
11663
11664 if (!crtc) {
11665 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11666 "more active pll users than references: %x vs %x\n",
11667 pll->active_mask, pll->state.crtc_mask);
11668
11669 return;
11670 }
11671
11672 crtc_mask = 1 << drm_crtc_index(crtc);
11673
11674 if (new_state->active)
11675 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11676 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11677 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11678 else
11679 I915_STATE_WARN(pll->active_mask & crtc_mask,
11680 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11681 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11682
11683 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11684 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11685 crtc_mask, pll->state.crtc_mask);
11686
11687 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11688 &dpll_hw_state,
11689 sizeof(dpll_hw_state)),
11690 "pll hw state mismatch\n");
11691 }
11692
11693 static void
11694 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11695 struct drm_crtc_state *old_crtc_state,
11696 struct drm_crtc_state *new_crtc_state)
11697 {
11698 struct drm_i915_private *dev_priv = to_i915(dev);
11699 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11700 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11701
11702 if (new_state->shared_dpll)
11703 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11704
11705 if (old_state->shared_dpll &&
11706 old_state->shared_dpll != new_state->shared_dpll) {
11707 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11708 struct intel_shared_dpll *pll = old_state->shared_dpll;
11709
11710 I915_STATE_WARN(pll->active_mask & crtc_mask,
11711 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11712 pipe_name(drm_crtc_index(crtc)));
11713 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11714 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11715 pipe_name(drm_crtc_index(crtc)));
11716 }
11717 }
11718
11719 static void
11720 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11721 struct drm_atomic_state *state,
11722 struct drm_crtc_state *old_state,
11723 struct drm_crtc_state *new_state)
11724 {
11725 if (!needs_modeset(new_state) &&
11726 !to_intel_crtc_state(new_state)->update_pipe)
11727 return;
11728
11729 verify_wm_state(crtc, new_state);
11730 verify_connector_state(crtc->dev, state, crtc);
11731 verify_crtc_state(crtc, old_state, new_state);
11732 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11733 }
11734
11735 static void
11736 verify_disabled_dpll_state(struct drm_device *dev)
11737 {
11738 struct drm_i915_private *dev_priv = to_i915(dev);
11739 int i;
11740
11741 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11742 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11743 }
11744
11745 static void
11746 intel_modeset_verify_disabled(struct drm_device *dev,
11747 struct drm_atomic_state *state)
11748 {
11749 verify_encoder_state(dev, state);
11750 verify_connector_state(dev, state, NULL);
11751 verify_disabled_dpll_state(dev);
11752 }
11753
11754 static void update_scanline_offset(struct intel_crtc *crtc)
11755 {
11756 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11757
11758 /*
11759 * The scanline counter increments at the leading edge of hsync.
11760 *
11761 * On most platforms it starts counting from vtotal-1 on the
11762 * first active line. That means the scanline counter value is
11763 * always one less than what we would expect. Ie. just after
11764 * start of vblank, which also occurs at start of hsync (on the
11765 * last active line), the scanline counter will read vblank_start-1.
11766 *
11767 * On gen2 the scanline counter starts counting from 1 instead
11768 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11769 * to keep the value positive), instead of adding one.
11770 *
11771 * On HSW+ the behaviour of the scanline counter depends on the output
11772 * type. For DP ports it behaves like most other platforms, but on HDMI
11773 * there's an extra 1 line difference. So we need to add two instead of
11774 * one to the value.
11775 *
11776 * On VLV/CHV DSI the scanline counter would appear to increment
11777 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11778 * that means we can't tell whether we're in vblank or not while
11779 * we're on that particular line. We must still set scanline_offset
11780 * to 1 so that the vblank timestamps come out correct when we query
11781 * the scanline counter from within the vblank interrupt handler.
11782 * However if queried just before the start of vblank we'll get an
11783 * answer that's slightly in the future.
11784 */
11785 if (IS_GEN2(dev_priv)) {
11786 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11787 int vtotal;
11788
11789 vtotal = adjusted_mode->crtc_vtotal;
11790 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11791 vtotal /= 2;
11792
11793 crtc->scanline_offset = vtotal - 1;
11794 } else if (HAS_DDI(dev_priv) &&
11795 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11796 crtc->scanline_offset = 2;
11797 } else
11798 crtc->scanline_offset = 1;
11799 }
11800
11801 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11802 {
11803 struct drm_device *dev = state->dev;
11804 struct drm_i915_private *dev_priv = to_i915(dev);
11805 struct drm_crtc *crtc;
11806 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11807 int i;
11808
11809 if (!dev_priv->display.crtc_compute_clock)
11810 return;
11811
11812 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11814 struct intel_shared_dpll *old_dpll =
11815 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11816
11817 if (!needs_modeset(new_crtc_state))
11818 continue;
11819
11820 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11821
11822 if (!old_dpll)
11823 continue;
11824
11825 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11826 }
11827 }
11828
11829 /*
11830 * This implements the workaround described in the "notes" section of the mode
11831 * set sequence documentation. When going from no pipes or single pipe to
11832 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11833 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11834 */
11835 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11836 {
11837 struct drm_crtc_state *crtc_state;
11838 struct intel_crtc *intel_crtc;
11839 struct drm_crtc *crtc;
11840 struct intel_crtc_state *first_crtc_state = NULL;
11841 struct intel_crtc_state *other_crtc_state = NULL;
11842 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11843 int i;
11844
11845 /* look at all crtc's that are going to be enabled in during modeset */
11846 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11847 intel_crtc = to_intel_crtc(crtc);
11848
11849 if (!crtc_state->active || !needs_modeset(crtc_state))
11850 continue;
11851
11852 if (first_crtc_state) {
11853 other_crtc_state = to_intel_crtc_state(crtc_state);
11854 break;
11855 } else {
11856 first_crtc_state = to_intel_crtc_state(crtc_state);
11857 first_pipe = intel_crtc->pipe;
11858 }
11859 }
11860
11861 /* No workaround needed? */
11862 if (!first_crtc_state)
11863 return 0;
11864
11865 /* w/a possibly needed, check how many crtc's are already enabled. */
11866 for_each_intel_crtc(state->dev, intel_crtc) {
11867 struct intel_crtc_state *pipe_config;
11868
11869 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11870 if (IS_ERR(pipe_config))
11871 return PTR_ERR(pipe_config);
11872
11873 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11874
11875 if (!pipe_config->base.active ||
11876 needs_modeset(&pipe_config->base))
11877 continue;
11878
11879 /* 2 or more enabled crtcs means no need for w/a */
11880 if (enabled_pipe != INVALID_PIPE)
11881 return 0;
11882
11883 enabled_pipe = intel_crtc->pipe;
11884 }
11885
11886 if (enabled_pipe != INVALID_PIPE)
11887 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11888 else if (other_crtc_state)
11889 other_crtc_state->hsw_workaround_pipe = first_pipe;
11890
11891 return 0;
11892 }
11893
11894 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11895 {
11896 struct drm_crtc *crtc;
11897
11898 /* Add all pipes to the state */
11899 for_each_crtc(state->dev, crtc) {
11900 struct drm_crtc_state *crtc_state;
11901
11902 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11903 if (IS_ERR(crtc_state))
11904 return PTR_ERR(crtc_state);
11905 }
11906
11907 return 0;
11908 }
11909
11910 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11911 {
11912 struct drm_crtc *crtc;
11913
11914 /*
11915 * Add all pipes to the state, and force
11916 * a modeset on all the active ones.
11917 */
11918 for_each_crtc(state->dev, crtc) {
11919 struct drm_crtc_state *crtc_state;
11920 int ret;
11921
11922 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11923 if (IS_ERR(crtc_state))
11924 return PTR_ERR(crtc_state);
11925
11926 if (!crtc_state->active || needs_modeset(crtc_state))
11927 continue;
11928
11929 crtc_state->mode_changed = true;
11930
11931 ret = drm_atomic_add_affected_connectors(state, crtc);
11932 if (ret)
11933 return ret;
11934
11935 ret = drm_atomic_add_affected_planes(state, crtc);
11936 if (ret)
11937 return ret;
11938 }
11939
11940 return 0;
11941 }
11942
11943 static int intel_modeset_checks(struct drm_atomic_state *state)
11944 {
11945 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11946 struct drm_i915_private *dev_priv = to_i915(state->dev);
11947 struct drm_crtc *crtc;
11948 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11949 int ret = 0, i;
11950
11951 if (!check_digital_port_conflicts(state)) {
11952 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11953 return -EINVAL;
11954 }
11955
11956 intel_state->modeset = true;
11957 intel_state->active_crtcs = dev_priv->active_crtcs;
11958 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11959 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11960
11961 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11962 if (new_crtc_state->active)
11963 intel_state->active_crtcs |= 1 << i;
11964 else
11965 intel_state->active_crtcs &= ~(1 << i);
11966
11967 if (old_crtc_state->active != new_crtc_state->active)
11968 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11969 }
11970
11971 /*
11972 * See if the config requires any additional preparation, e.g.
11973 * to adjust global state with pipes off. We need to do this
11974 * here so we can get the modeset_pipe updated config for the new
11975 * mode set on this crtc. For other crtcs we need to use the
11976 * adjusted_mode bits in the crtc directly.
11977 */
11978 if (dev_priv->display.modeset_calc_cdclk) {
11979 ret = dev_priv->display.modeset_calc_cdclk(state);
11980 if (ret < 0)
11981 return ret;
11982
11983 /*
11984 * Writes to dev_priv->cdclk.logical must protected by
11985 * holding all the crtc locks, even if we don't end up
11986 * touching the hardware
11987 */
11988 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11989 &intel_state->cdclk.logical)) {
11990 ret = intel_lock_all_pipes(state);
11991 if (ret < 0)
11992 return ret;
11993 }
11994
11995 /* All pipes must be switched off while we change the cdclk. */
11996 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
11997 &intel_state->cdclk.actual)) {
11998 ret = intel_modeset_all_pipes(state);
11999 if (ret < 0)
12000 return ret;
12001 }
12002
12003 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12004 intel_state->cdclk.logical.cdclk,
12005 intel_state->cdclk.actual.cdclk);
12006 } else {
12007 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12008 }
12009
12010 intel_modeset_clear_plls(state);
12011
12012 if (IS_HASWELL(dev_priv))
12013 return haswell_mode_set_planes_workaround(state);
12014
12015 return 0;
12016 }
12017
12018 /*
12019 * Handle calculation of various watermark data at the end of the atomic check
12020 * phase. The code here should be run after the per-crtc and per-plane 'check'
12021 * handlers to ensure that all derived state has been updated.
12022 */
12023 static int calc_watermark_data(struct drm_atomic_state *state)
12024 {
12025 struct drm_device *dev = state->dev;
12026 struct drm_i915_private *dev_priv = to_i915(dev);
12027
12028 /* Is there platform-specific watermark information to calculate? */
12029 if (dev_priv->display.compute_global_watermarks)
12030 return dev_priv->display.compute_global_watermarks(state);
12031
12032 return 0;
12033 }
12034
12035 /**
12036 * intel_atomic_check - validate state object
12037 * @dev: drm device
12038 * @state: state to validate
12039 */
12040 static int intel_atomic_check(struct drm_device *dev,
12041 struct drm_atomic_state *state)
12042 {
12043 struct drm_i915_private *dev_priv = to_i915(dev);
12044 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12045 struct drm_crtc *crtc;
12046 struct drm_crtc_state *old_crtc_state, *crtc_state;
12047 int ret, i;
12048 bool any_ms = false;
12049
12050 ret = drm_atomic_helper_check_modeset(dev, state);
12051 if (ret)
12052 return ret;
12053
12054 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12055 struct intel_crtc_state *pipe_config =
12056 to_intel_crtc_state(crtc_state);
12057
12058 /* Catch I915_MODE_FLAG_INHERITED */
12059 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12060 crtc_state->mode_changed = true;
12061
12062 if (!needs_modeset(crtc_state))
12063 continue;
12064
12065 if (!crtc_state->enable) {
12066 any_ms = true;
12067 continue;
12068 }
12069
12070 /* FIXME: For only active_changed we shouldn't need to do any
12071 * state recomputation at all. */
12072
12073 ret = drm_atomic_add_affected_connectors(state, crtc);
12074 if (ret)
12075 return ret;
12076
12077 ret = intel_modeset_pipe_config(crtc, pipe_config);
12078 if (ret) {
12079 intel_dump_pipe_config(to_intel_crtc(crtc),
12080 pipe_config, "[failed]");
12081 return ret;
12082 }
12083
12084 if (i915.fastboot &&
12085 intel_pipe_config_compare(dev_priv,
12086 to_intel_crtc_state(old_crtc_state),
12087 pipe_config, true)) {
12088 crtc_state->mode_changed = false;
12089 pipe_config->update_pipe = true;
12090 }
12091
12092 if (needs_modeset(crtc_state))
12093 any_ms = true;
12094
12095 ret = drm_atomic_add_affected_planes(state, crtc);
12096 if (ret)
12097 return ret;
12098
12099 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12100 needs_modeset(crtc_state) ?
12101 "[modeset]" : "[fastset]");
12102 }
12103
12104 if (any_ms) {
12105 ret = intel_modeset_checks(state);
12106
12107 if (ret)
12108 return ret;
12109 } else {
12110 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12111 }
12112
12113 ret = drm_atomic_helper_check_planes(dev, state);
12114 if (ret)
12115 return ret;
12116
12117 intel_fbc_choose_crtc(dev_priv, state);
12118 return calc_watermark_data(state);
12119 }
12120
12121 static int intel_atomic_prepare_commit(struct drm_device *dev,
12122 struct drm_atomic_state *state)
12123 {
12124 return drm_atomic_helper_prepare_planes(dev, state);
12125 }
12126
12127 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12128 {
12129 struct drm_device *dev = crtc->base.dev;
12130
12131 if (!dev->max_vblank_count)
12132 return drm_crtc_accurate_vblank_count(&crtc->base);
12133
12134 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12135 }
12136
12137 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12138 struct drm_i915_private *dev_priv,
12139 unsigned crtc_mask)
12140 {
12141 unsigned last_vblank_count[I915_MAX_PIPES];
12142 enum pipe pipe;
12143 int ret;
12144
12145 if (!crtc_mask)
12146 return;
12147
12148 for_each_pipe(dev_priv, pipe) {
12149 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12150 pipe);
12151
12152 if (!((1 << pipe) & crtc_mask))
12153 continue;
12154
12155 ret = drm_crtc_vblank_get(&crtc->base);
12156 if (WARN_ON(ret != 0)) {
12157 crtc_mask &= ~(1 << pipe);
12158 continue;
12159 }
12160
12161 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12162 }
12163
12164 for_each_pipe(dev_priv, pipe) {
12165 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12166 pipe);
12167 long lret;
12168
12169 if (!((1 << pipe) & crtc_mask))
12170 continue;
12171
12172 lret = wait_event_timeout(dev->vblank[pipe].queue,
12173 last_vblank_count[pipe] !=
12174 drm_crtc_vblank_count(&crtc->base),
12175 msecs_to_jiffies(50));
12176
12177 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12178
12179 drm_crtc_vblank_put(&crtc->base);
12180 }
12181 }
12182
12183 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12184 {
12185 /* fb updated, need to unpin old fb */
12186 if (crtc_state->fb_changed)
12187 return true;
12188
12189 /* wm changes, need vblank before final wm's */
12190 if (crtc_state->update_wm_post)
12191 return true;
12192
12193 if (crtc_state->wm.need_postvbl_update)
12194 return true;
12195
12196 return false;
12197 }
12198
12199 static void intel_update_crtc(struct drm_crtc *crtc,
12200 struct drm_atomic_state *state,
12201 struct drm_crtc_state *old_crtc_state,
12202 struct drm_crtc_state *new_crtc_state,
12203 unsigned int *crtc_vblank_mask)
12204 {
12205 struct drm_device *dev = crtc->dev;
12206 struct drm_i915_private *dev_priv = to_i915(dev);
12207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12208 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12209 bool modeset = needs_modeset(new_crtc_state);
12210
12211 if (modeset) {
12212 update_scanline_offset(intel_crtc);
12213 dev_priv->display.crtc_enable(pipe_config, state);
12214 } else {
12215 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12216 pipe_config);
12217 }
12218
12219 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12220 intel_fbc_enable(
12221 intel_crtc, pipe_config,
12222 to_intel_plane_state(crtc->primary->state));
12223 }
12224
12225 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12226
12227 if (needs_vblank_wait(pipe_config))
12228 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12229 }
12230
12231 static void intel_update_crtcs(struct drm_atomic_state *state,
12232 unsigned int *crtc_vblank_mask)
12233 {
12234 struct drm_crtc *crtc;
12235 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12236 int i;
12237
12238 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12239 if (!new_crtc_state->active)
12240 continue;
12241
12242 intel_update_crtc(crtc, state, old_crtc_state,
12243 new_crtc_state, crtc_vblank_mask);
12244 }
12245 }
12246
12247 static void skl_update_crtcs(struct drm_atomic_state *state,
12248 unsigned int *crtc_vblank_mask)
12249 {
12250 struct drm_i915_private *dev_priv = to_i915(state->dev);
12251 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12252 struct drm_crtc *crtc;
12253 struct intel_crtc *intel_crtc;
12254 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12255 struct intel_crtc_state *cstate;
12256 unsigned int updated = 0;
12257 bool progress;
12258 enum pipe pipe;
12259 int i;
12260
12261 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12262
12263 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12264 /* ignore allocations for crtc's that have been turned off. */
12265 if (new_crtc_state->active)
12266 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12267
12268 /*
12269 * Whenever the number of active pipes changes, we need to make sure we
12270 * update the pipes in the right order so that their ddb allocations
12271 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12272 * cause pipe underruns and other bad stuff.
12273 */
12274 do {
12275 progress = false;
12276
12277 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12278 bool vbl_wait = false;
12279 unsigned int cmask = drm_crtc_mask(crtc);
12280
12281 intel_crtc = to_intel_crtc(crtc);
12282 cstate = to_intel_crtc_state(crtc->state);
12283 pipe = intel_crtc->pipe;
12284
12285 if (updated & cmask || !cstate->base.active)
12286 continue;
12287
12288 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12289 continue;
12290
12291 updated |= cmask;
12292 entries[i] = &cstate->wm.skl.ddb;
12293
12294 /*
12295 * If this is an already active pipe, it's DDB changed,
12296 * and this isn't the last pipe that needs updating
12297 * then we need to wait for a vblank to pass for the
12298 * new ddb allocation to take effect.
12299 */
12300 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12301 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12302 !new_crtc_state->active_changed &&
12303 intel_state->wm_results.dirty_pipes != updated)
12304 vbl_wait = true;
12305
12306 intel_update_crtc(crtc, state, old_crtc_state,
12307 new_crtc_state, crtc_vblank_mask);
12308
12309 if (vbl_wait)
12310 intel_wait_for_vblank(dev_priv, pipe);
12311
12312 progress = true;
12313 }
12314 } while (progress);
12315 }
12316
12317 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12318 {
12319 struct intel_atomic_state *state, *next;
12320 struct llist_node *freed;
12321
12322 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12323 llist_for_each_entry_safe(state, next, freed, freed)
12324 drm_atomic_state_put(&state->base);
12325 }
12326
12327 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12328 {
12329 struct drm_i915_private *dev_priv =
12330 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12331
12332 intel_atomic_helper_free_state(dev_priv);
12333 }
12334
12335 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12336 {
12337 struct wait_queue_entry wait_fence, wait_reset;
12338 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12339
12340 init_wait_entry(&wait_fence, 0);
12341 init_wait_entry(&wait_reset, 0);
12342 for (;;) {
12343 prepare_to_wait(&intel_state->commit_ready.wait,
12344 &wait_fence, TASK_UNINTERRUPTIBLE);
12345 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12346 &wait_reset, TASK_UNINTERRUPTIBLE);
12347
12348
12349 if (i915_sw_fence_done(&intel_state->commit_ready)
12350 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12351 break;
12352
12353 schedule();
12354 }
12355 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12356 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12357 }
12358
12359 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12360 {
12361 struct drm_device *dev = state->dev;
12362 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12363 struct drm_i915_private *dev_priv = to_i915(dev);
12364 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12365 struct drm_crtc *crtc;
12366 struct intel_crtc_state *intel_cstate;
12367 bool hw_check = intel_state->modeset;
12368 u64 put_domains[I915_MAX_PIPES] = {};
12369 unsigned crtc_vblank_mask = 0;
12370 int i;
12371
12372 intel_atomic_commit_fence_wait(intel_state);
12373
12374 drm_atomic_helper_wait_for_dependencies(state);
12375
12376 if (intel_state->modeset)
12377 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12378
12379 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12381
12382 if (needs_modeset(new_crtc_state) ||
12383 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12384 hw_check = true;
12385
12386 put_domains[to_intel_crtc(crtc)->pipe] =
12387 modeset_get_crtc_power_domains(crtc,
12388 to_intel_crtc_state(new_crtc_state));
12389 }
12390
12391 if (!needs_modeset(new_crtc_state))
12392 continue;
12393
12394 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12395 to_intel_crtc_state(new_crtc_state));
12396
12397 if (old_crtc_state->active) {
12398 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12399 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12400 intel_crtc->active = false;
12401 intel_fbc_disable(intel_crtc);
12402 intel_disable_shared_dpll(intel_crtc);
12403
12404 /*
12405 * Underruns don't always raise
12406 * interrupts, so check manually.
12407 */
12408 intel_check_cpu_fifo_underruns(dev_priv);
12409 intel_check_pch_fifo_underruns(dev_priv);
12410
12411 if (!crtc->state->active) {
12412 /*
12413 * Make sure we don't call initial_watermarks
12414 * for ILK-style watermark updates.
12415 *
12416 * No clue what this is supposed to achieve.
12417 */
12418 if (INTEL_GEN(dev_priv) >= 9)
12419 dev_priv->display.initial_watermarks(intel_state,
12420 to_intel_crtc_state(crtc->state));
12421 }
12422 }
12423 }
12424
12425 /* Only after disabling all output pipelines that will be changed can we
12426 * update the the output configuration. */
12427 intel_modeset_update_crtc_state(state);
12428
12429 if (intel_state->modeset) {
12430 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12431
12432 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12433
12434 /*
12435 * SKL workaround: bspec recommends we disable the SAGV when we
12436 * have more then one pipe enabled
12437 */
12438 if (!intel_can_enable_sagv(state))
12439 intel_disable_sagv(dev_priv);
12440
12441 intel_modeset_verify_disabled(dev, state);
12442 }
12443
12444 /* Complete the events for pipes that have now been disabled */
12445 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12446 bool modeset = needs_modeset(new_crtc_state);
12447
12448 /* Complete events for now disable pipes here. */
12449 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12450 spin_lock_irq(&dev->event_lock);
12451 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12452 spin_unlock_irq(&dev->event_lock);
12453
12454 new_crtc_state->event = NULL;
12455 }
12456 }
12457
12458 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12459 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12460
12461 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12462 * already, but still need the state for the delayed optimization. To
12463 * fix this:
12464 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12465 * - schedule that vblank worker _before_ calling hw_done
12466 * - at the start of commit_tail, cancel it _synchrously
12467 * - switch over to the vblank wait helper in the core after that since
12468 * we don't need out special handling any more.
12469 */
12470 if (!state->legacy_cursor_update)
12471 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12472
12473 /*
12474 * Now that the vblank has passed, we can go ahead and program the
12475 * optimal watermarks on platforms that need two-step watermark
12476 * programming.
12477 *
12478 * TODO: Move this (and other cleanup) to an async worker eventually.
12479 */
12480 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12481 intel_cstate = to_intel_crtc_state(new_crtc_state);
12482
12483 if (dev_priv->display.optimize_watermarks)
12484 dev_priv->display.optimize_watermarks(intel_state,
12485 intel_cstate);
12486 }
12487
12488 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12489 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12490
12491 if (put_domains[i])
12492 modeset_put_power_domains(dev_priv, put_domains[i]);
12493
12494 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12495 }
12496
12497 if (intel_state->modeset && intel_can_enable_sagv(state))
12498 intel_enable_sagv(dev_priv);
12499
12500 drm_atomic_helper_commit_hw_done(state);
12501
12502 if (intel_state->modeset) {
12503 /* As one of the primary mmio accessors, KMS has a high
12504 * likelihood of triggering bugs in unclaimed access. After we
12505 * finish modesetting, see if an error has been flagged, and if
12506 * so enable debugging for the next modeset - and hope we catch
12507 * the culprit.
12508 */
12509 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12510 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12511 }
12512
12513 drm_atomic_helper_cleanup_planes(dev, state);
12514
12515 drm_atomic_helper_commit_cleanup_done(state);
12516
12517 drm_atomic_state_put(state);
12518
12519 intel_atomic_helper_free_state(dev_priv);
12520 }
12521
12522 static void intel_atomic_commit_work(struct work_struct *work)
12523 {
12524 struct drm_atomic_state *state =
12525 container_of(work, struct drm_atomic_state, commit_work);
12526
12527 intel_atomic_commit_tail(state);
12528 }
12529
12530 static int __i915_sw_fence_call
12531 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12532 enum i915_sw_fence_notify notify)
12533 {
12534 struct intel_atomic_state *state =
12535 container_of(fence, struct intel_atomic_state, commit_ready);
12536
12537 switch (notify) {
12538 case FENCE_COMPLETE:
12539 /* we do blocking waits in the worker, nothing to do here */
12540 break;
12541 case FENCE_FREE:
12542 {
12543 struct intel_atomic_helper *helper =
12544 &to_i915(state->base.dev)->atomic_helper;
12545
12546 if (llist_add(&state->freed, &helper->free_list))
12547 schedule_work(&helper->free_work);
12548 break;
12549 }
12550 }
12551
12552 return NOTIFY_DONE;
12553 }
12554
12555 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12556 {
12557 struct drm_plane_state *old_plane_state, *new_plane_state;
12558 struct drm_plane *plane;
12559 int i;
12560
12561 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12562 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12563 intel_fb_obj(new_plane_state->fb),
12564 to_intel_plane(plane)->frontbuffer_bit);
12565 }
12566
12567 /**
12568 * intel_atomic_commit - commit validated state object
12569 * @dev: DRM device
12570 * @state: the top-level driver state object
12571 * @nonblock: nonblocking commit
12572 *
12573 * This function commits a top-level state object that has been validated
12574 * with drm_atomic_helper_check().
12575 *
12576 * RETURNS
12577 * Zero for success or -errno.
12578 */
12579 static int intel_atomic_commit(struct drm_device *dev,
12580 struct drm_atomic_state *state,
12581 bool nonblock)
12582 {
12583 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12584 struct drm_i915_private *dev_priv = to_i915(dev);
12585 int ret = 0;
12586
12587 ret = drm_atomic_helper_setup_commit(state, nonblock);
12588 if (ret)
12589 return ret;
12590
12591 drm_atomic_state_get(state);
12592 i915_sw_fence_init(&intel_state->commit_ready,
12593 intel_atomic_commit_ready);
12594
12595 ret = intel_atomic_prepare_commit(dev, state);
12596 if (ret) {
12597 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12598 i915_sw_fence_commit(&intel_state->commit_ready);
12599 return ret;
12600 }
12601
12602 /*
12603 * The intel_legacy_cursor_update() fast path takes care
12604 * of avoiding the vblank waits for simple cursor
12605 * movement and flips. For cursor on/off and size changes,
12606 * we want to perform the vblank waits so that watermark
12607 * updates happen during the correct frames. Gen9+ have
12608 * double buffered watermarks and so shouldn't need this.
12609 *
12610 * Do this after drm_atomic_helper_setup_commit() and
12611 * intel_atomic_prepare_commit() because we still want
12612 * to skip the flip and fb cleanup waits. Although that
12613 * does risk yanking the mapping from under the display
12614 * engine.
12615 *
12616 * FIXME doing watermarks and fb cleanup from a vblank worker
12617 * (assuming we had any) would solve these problems.
12618 */
12619 if (INTEL_GEN(dev_priv) < 9)
12620 state->legacy_cursor_update = false;
12621
12622 ret = drm_atomic_helper_swap_state(state, true);
12623 if (ret) {
12624 i915_sw_fence_commit(&intel_state->commit_ready);
12625
12626 drm_atomic_helper_cleanup_planes(dev, state);
12627 return ret;
12628 }
12629 dev_priv->wm.distrust_bios_wm = false;
12630 intel_shared_dpll_swap_state(state);
12631 intel_atomic_track_fbs(state);
12632
12633 if (intel_state->modeset) {
12634 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
12635 sizeof(intel_state->min_pixclk));
12636 dev_priv->active_crtcs = intel_state->active_crtcs;
12637 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12638 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12639 }
12640
12641 drm_atomic_state_get(state);
12642 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12643
12644 i915_sw_fence_commit(&intel_state->commit_ready);
12645 if (nonblock)
12646 queue_work(system_unbound_wq, &state->commit_work);
12647 else
12648 intel_atomic_commit_tail(state);
12649
12650
12651 return 0;
12652 }
12653
12654 static const struct drm_crtc_funcs intel_crtc_funcs = {
12655 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12656 .set_config = drm_atomic_helper_set_config,
12657 .destroy = intel_crtc_destroy,
12658 .page_flip = drm_atomic_helper_page_flip,
12659 .atomic_duplicate_state = intel_crtc_duplicate_state,
12660 .atomic_destroy_state = intel_crtc_destroy_state,
12661 .set_crc_source = intel_crtc_set_crc_source,
12662 };
12663
12664 struct wait_rps_boost {
12665 struct wait_queue_entry wait;
12666
12667 struct drm_crtc *crtc;
12668 struct drm_i915_gem_request *request;
12669 };
12670
12671 static int do_rps_boost(struct wait_queue_entry *_wait,
12672 unsigned mode, int sync, void *key)
12673 {
12674 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12675 struct drm_i915_gem_request *rq = wait->request;
12676
12677 gen6_rps_boost(rq, NULL);
12678 i915_gem_request_put(rq);
12679
12680 drm_crtc_vblank_put(wait->crtc);
12681
12682 list_del(&wait->wait.entry);
12683 kfree(wait);
12684 return 1;
12685 }
12686
12687 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12688 struct dma_fence *fence)
12689 {
12690 struct wait_rps_boost *wait;
12691
12692 if (!dma_fence_is_i915(fence))
12693 return;
12694
12695 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12696 return;
12697
12698 if (drm_crtc_vblank_get(crtc))
12699 return;
12700
12701 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12702 if (!wait) {
12703 drm_crtc_vblank_put(crtc);
12704 return;
12705 }
12706
12707 wait->request = to_request(dma_fence_get(fence));
12708 wait->crtc = crtc;
12709
12710 wait->wait.func = do_rps_boost;
12711 wait->wait.flags = 0;
12712
12713 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12714 }
12715
12716 /**
12717 * intel_prepare_plane_fb - Prepare fb for usage on plane
12718 * @plane: drm plane to prepare for
12719 * @fb: framebuffer to prepare for presentation
12720 *
12721 * Prepares a framebuffer for usage on a display plane. Generally this
12722 * involves pinning the underlying object and updating the frontbuffer tracking
12723 * bits. Some older platforms need special physical address handling for
12724 * cursor planes.
12725 *
12726 * Must be called with struct_mutex held.
12727 *
12728 * Returns 0 on success, negative error code on failure.
12729 */
12730 int
12731 intel_prepare_plane_fb(struct drm_plane *plane,
12732 struct drm_plane_state *new_state)
12733 {
12734 struct intel_atomic_state *intel_state =
12735 to_intel_atomic_state(new_state->state);
12736 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12737 struct drm_framebuffer *fb = new_state->fb;
12738 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12739 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12740 int ret;
12741
12742 if (old_obj) {
12743 struct drm_crtc_state *crtc_state =
12744 drm_atomic_get_existing_crtc_state(new_state->state,
12745 plane->state->crtc);
12746
12747 /* Big Hammer, we also need to ensure that any pending
12748 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12749 * current scanout is retired before unpinning the old
12750 * framebuffer. Note that we rely on userspace rendering
12751 * into the buffer attached to the pipe they are waiting
12752 * on. If not, userspace generates a GPU hang with IPEHR
12753 * point to the MI_WAIT_FOR_EVENT.
12754 *
12755 * This should only fail upon a hung GPU, in which case we
12756 * can safely continue.
12757 */
12758 if (needs_modeset(crtc_state)) {
12759 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12760 old_obj->resv, NULL,
12761 false, 0,
12762 GFP_KERNEL);
12763 if (ret < 0)
12764 return ret;
12765 }
12766 }
12767
12768 if (new_state->fence) { /* explicit fencing */
12769 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12770 new_state->fence,
12771 I915_FENCE_TIMEOUT,
12772 GFP_KERNEL);
12773 if (ret < 0)
12774 return ret;
12775 }
12776
12777 if (!obj)
12778 return 0;
12779
12780 ret = i915_gem_object_pin_pages(obj);
12781 if (ret)
12782 return ret;
12783
12784 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12785 if (ret) {
12786 i915_gem_object_unpin_pages(obj);
12787 return ret;
12788 }
12789
12790 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12791 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12792 const int align = intel_cursor_alignment(dev_priv);
12793
12794 ret = i915_gem_object_attach_phys(obj, align);
12795 } else {
12796 struct i915_vma *vma;
12797
12798 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12799 if (!IS_ERR(vma))
12800 to_intel_plane_state(new_state)->vma = vma;
12801 else
12802 ret = PTR_ERR(vma);
12803 }
12804
12805 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12806
12807 mutex_unlock(&dev_priv->drm.struct_mutex);
12808 i915_gem_object_unpin_pages(obj);
12809 if (ret)
12810 return ret;
12811
12812 if (!new_state->fence) { /* implicit fencing */
12813 struct dma_fence *fence;
12814
12815 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12816 obj->resv, NULL,
12817 false, I915_FENCE_TIMEOUT,
12818 GFP_KERNEL);
12819 if (ret < 0)
12820 return ret;
12821
12822 fence = reservation_object_get_excl_rcu(obj->resv);
12823 if (fence) {
12824 add_rps_boost_after_vblank(new_state->crtc, fence);
12825 dma_fence_put(fence);
12826 }
12827 } else {
12828 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12829 }
12830
12831 return 0;
12832 }
12833
12834 /**
12835 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12836 * @plane: drm plane to clean up for
12837 * @fb: old framebuffer that was on plane
12838 *
12839 * Cleans up a framebuffer that has just been removed from a plane.
12840 *
12841 * Must be called with struct_mutex held.
12842 */
12843 void
12844 intel_cleanup_plane_fb(struct drm_plane *plane,
12845 struct drm_plane_state *old_state)
12846 {
12847 struct i915_vma *vma;
12848
12849 /* Should only be called after a successful intel_prepare_plane_fb()! */
12850 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12851 if (vma) {
12852 mutex_lock(&plane->dev->struct_mutex);
12853 intel_unpin_fb_vma(vma);
12854 mutex_unlock(&plane->dev->struct_mutex);
12855 }
12856 }
12857
12858 int
12859 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12860 {
12861 struct drm_i915_private *dev_priv;
12862 int max_scale;
12863 int crtc_clock, max_dotclk;
12864
12865 if (!intel_crtc || !crtc_state->base.enable)
12866 return DRM_PLANE_HELPER_NO_SCALING;
12867
12868 dev_priv = to_i915(intel_crtc->base.dev);
12869
12870 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12871 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12872
12873 if (IS_GEMINILAKE(dev_priv))
12874 max_dotclk *= 2;
12875
12876 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12877 return DRM_PLANE_HELPER_NO_SCALING;
12878
12879 /*
12880 * skl max scale is lower of:
12881 * close to 3 but not 3, -1 is for that purpose
12882 * or
12883 * cdclk/crtc_clock
12884 */
12885 max_scale = min((1 << 16) * 3 - 1,
12886 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12887
12888 return max_scale;
12889 }
12890
12891 static int
12892 intel_check_primary_plane(struct intel_plane *plane,
12893 struct intel_crtc_state *crtc_state,
12894 struct intel_plane_state *state)
12895 {
12896 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12897 struct drm_crtc *crtc = state->base.crtc;
12898 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12899 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12900 bool can_position = false;
12901 int ret;
12902
12903 if (INTEL_GEN(dev_priv) >= 9) {
12904 /* use scaler when colorkey is not required */
12905 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12906 min_scale = 1;
12907 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12908 }
12909 can_position = true;
12910 }
12911
12912 ret = drm_plane_helper_check_state(&state->base,
12913 &state->clip,
12914 min_scale, max_scale,
12915 can_position, true);
12916 if (ret)
12917 return ret;
12918
12919 if (!state->base.fb)
12920 return 0;
12921
12922 if (INTEL_GEN(dev_priv) >= 9) {
12923 ret = skl_check_plane_surface(state);
12924 if (ret)
12925 return ret;
12926
12927 state->ctl = skl_plane_ctl(crtc_state, state);
12928 } else {
12929 ret = i9xx_check_plane_surface(state);
12930 if (ret)
12931 return ret;
12932
12933 state->ctl = i9xx_plane_ctl(crtc_state, state);
12934 }
12935
12936 return 0;
12937 }
12938
12939 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12940 struct drm_crtc_state *old_crtc_state)
12941 {
12942 struct drm_device *dev = crtc->dev;
12943 struct drm_i915_private *dev_priv = to_i915(dev);
12944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12945 struct intel_crtc_state *intel_cstate =
12946 to_intel_crtc_state(crtc->state);
12947 struct intel_crtc_state *old_intel_cstate =
12948 to_intel_crtc_state(old_crtc_state);
12949 struct intel_atomic_state *old_intel_state =
12950 to_intel_atomic_state(old_crtc_state->state);
12951 bool modeset = needs_modeset(crtc->state);
12952
12953 if (!modeset &&
12954 (intel_cstate->base.color_mgmt_changed ||
12955 intel_cstate->update_pipe)) {
12956 intel_color_set_csc(crtc->state);
12957 intel_color_load_luts(crtc->state);
12958 }
12959
12960 /* Perform vblank evasion around commit operation */
12961 intel_pipe_update_start(intel_crtc);
12962
12963 if (modeset)
12964 goto out;
12965
12966 if (intel_cstate->update_pipe)
12967 intel_update_pipe_config(intel_crtc, old_intel_cstate);
12968 else if (INTEL_GEN(dev_priv) >= 9)
12969 skl_detach_scalers(intel_crtc);
12970
12971 out:
12972 if (dev_priv->display.atomic_update_watermarks)
12973 dev_priv->display.atomic_update_watermarks(old_intel_state,
12974 intel_cstate);
12975 }
12976
12977 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12978 struct drm_crtc_state *old_crtc_state)
12979 {
12980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12981
12982 intel_pipe_update_end(intel_crtc);
12983 }
12984
12985 /**
12986 * intel_plane_destroy - destroy a plane
12987 * @plane: plane to destroy
12988 *
12989 * Common destruction function for all types of planes (primary, cursor,
12990 * sprite).
12991 */
12992 void intel_plane_destroy(struct drm_plane *plane)
12993 {
12994 drm_plane_cleanup(plane);
12995 kfree(to_intel_plane(plane));
12996 }
12997
12998 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12999 {
13000 switch (format) {
13001 case DRM_FORMAT_C8:
13002 case DRM_FORMAT_RGB565:
13003 case DRM_FORMAT_XRGB1555:
13004 case DRM_FORMAT_XRGB8888:
13005 return modifier == DRM_FORMAT_MOD_LINEAR ||
13006 modifier == I915_FORMAT_MOD_X_TILED;
13007 default:
13008 return false;
13009 }
13010 }
13011
13012 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
13013 {
13014 switch (format) {
13015 case DRM_FORMAT_C8:
13016 case DRM_FORMAT_RGB565:
13017 case DRM_FORMAT_XRGB8888:
13018 case DRM_FORMAT_XBGR8888:
13019 case DRM_FORMAT_XRGB2101010:
13020 case DRM_FORMAT_XBGR2101010:
13021 return modifier == DRM_FORMAT_MOD_LINEAR ||
13022 modifier == I915_FORMAT_MOD_X_TILED;
13023 default:
13024 return false;
13025 }
13026 }
13027
13028 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
13029 {
13030 switch (format) {
13031 case DRM_FORMAT_XRGB8888:
13032 case DRM_FORMAT_XBGR8888:
13033 case DRM_FORMAT_ARGB8888:
13034 case DRM_FORMAT_ABGR8888:
13035 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13036 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13037 return true;
13038 /* fall through */
13039 case DRM_FORMAT_RGB565:
13040 case DRM_FORMAT_XRGB2101010:
13041 case DRM_FORMAT_XBGR2101010:
13042 case DRM_FORMAT_YUYV:
13043 case DRM_FORMAT_YVYU:
13044 case DRM_FORMAT_UYVY:
13045 case DRM_FORMAT_VYUY:
13046 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13047 return true;
13048 /* fall through */
13049 case DRM_FORMAT_C8:
13050 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13051 modifier == I915_FORMAT_MOD_X_TILED ||
13052 modifier == I915_FORMAT_MOD_Y_TILED)
13053 return true;
13054 /* fall through */
13055 default:
13056 return false;
13057 }
13058 }
13059
13060 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
13061 uint32_t format,
13062 uint64_t modifier)
13063 {
13064 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13065
13066 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13067 return false;
13068
13069 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13070 modifier != DRM_FORMAT_MOD_LINEAR)
13071 return false;
13072
13073 if (INTEL_GEN(dev_priv) >= 9)
13074 return skl_mod_supported(format, modifier);
13075 else if (INTEL_GEN(dev_priv) >= 4)
13076 return i965_mod_supported(format, modifier);
13077 else
13078 return i8xx_mod_supported(format, modifier);
13079
13080 unreachable();
13081 }
13082
13083 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
13084 uint32_t format,
13085 uint64_t modifier)
13086 {
13087 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13088 return false;
13089
13090 return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
13091 }
13092
13093 static struct drm_plane_funcs intel_plane_funcs = {
13094 .update_plane = drm_atomic_helper_update_plane,
13095 .disable_plane = drm_atomic_helper_disable_plane,
13096 .destroy = intel_plane_destroy,
13097 .atomic_get_property = intel_plane_atomic_get_property,
13098 .atomic_set_property = intel_plane_atomic_set_property,
13099 .atomic_duplicate_state = intel_plane_duplicate_state,
13100 .atomic_destroy_state = intel_plane_destroy_state,
13101 .format_mod_supported = intel_primary_plane_format_mod_supported,
13102 };
13103
13104 static int
13105 intel_legacy_cursor_update(struct drm_plane *plane,
13106 struct drm_crtc *crtc,
13107 struct drm_framebuffer *fb,
13108 int crtc_x, int crtc_y,
13109 unsigned int crtc_w, unsigned int crtc_h,
13110 uint32_t src_x, uint32_t src_y,
13111 uint32_t src_w, uint32_t src_h,
13112 struct drm_modeset_acquire_ctx *ctx)
13113 {
13114 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13115 int ret;
13116 struct drm_plane_state *old_plane_state, *new_plane_state;
13117 struct intel_plane *intel_plane = to_intel_plane(plane);
13118 struct drm_framebuffer *old_fb;
13119 struct drm_crtc_state *crtc_state = crtc->state;
13120 struct i915_vma *old_vma, *vma;
13121
13122 /*
13123 * When crtc is inactive or there is a modeset pending,
13124 * wait for it to complete in the slowpath
13125 */
13126 if (!crtc_state->active || needs_modeset(crtc_state) ||
13127 to_intel_crtc_state(crtc_state)->update_pipe)
13128 goto slow;
13129
13130 old_plane_state = plane->state;
13131
13132 /*
13133 * If any parameters change that may affect watermarks,
13134 * take the slowpath. Only changing fb or position should be
13135 * in the fastpath.
13136 */
13137 if (old_plane_state->crtc != crtc ||
13138 old_plane_state->src_w != src_w ||
13139 old_plane_state->src_h != src_h ||
13140 old_plane_state->crtc_w != crtc_w ||
13141 old_plane_state->crtc_h != crtc_h ||
13142 !old_plane_state->fb != !fb)
13143 goto slow;
13144
13145 new_plane_state = intel_plane_duplicate_state(plane);
13146 if (!new_plane_state)
13147 return -ENOMEM;
13148
13149 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13150
13151 new_plane_state->src_x = src_x;
13152 new_plane_state->src_y = src_y;
13153 new_plane_state->src_w = src_w;
13154 new_plane_state->src_h = src_h;
13155 new_plane_state->crtc_x = crtc_x;
13156 new_plane_state->crtc_y = crtc_y;
13157 new_plane_state->crtc_w = crtc_w;
13158 new_plane_state->crtc_h = crtc_h;
13159
13160 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13161 to_intel_plane_state(new_plane_state));
13162 if (ret)
13163 goto out_free;
13164
13165 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13166 if (ret)
13167 goto out_free;
13168
13169 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13170 int align = intel_cursor_alignment(dev_priv);
13171
13172 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13173 if (ret) {
13174 DRM_DEBUG_KMS("failed to attach phys object\n");
13175 goto out_unlock;
13176 }
13177 } else {
13178 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13179 if (IS_ERR(vma)) {
13180 DRM_DEBUG_KMS("failed to pin object\n");
13181
13182 ret = PTR_ERR(vma);
13183 goto out_unlock;
13184 }
13185
13186 to_intel_plane_state(new_plane_state)->vma = vma;
13187 }
13188
13189 old_fb = old_plane_state->fb;
13190 old_vma = to_intel_plane_state(old_plane_state)->vma;
13191
13192 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13193 intel_plane->frontbuffer_bit);
13194
13195 /* Swap plane state */
13196 new_plane_state->fence = old_plane_state->fence;
13197 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13198 new_plane_state->fence = NULL;
13199 new_plane_state->fb = old_fb;
13200 to_intel_plane_state(new_plane_state)->vma = NULL;
13201
13202 if (plane->state->visible) {
13203 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13204 intel_plane->update_plane(intel_plane,
13205 to_intel_crtc_state(crtc->state),
13206 to_intel_plane_state(plane->state));
13207 } else {
13208 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13209 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13210 }
13211
13212 if (old_vma)
13213 intel_unpin_fb_vma(old_vma);
13214
13215 out_unlock:
13216 mutex_unlock(&dev_priv->drm.struct_mutex);
13217 out_free:
13218 intel_plane_destroy_state(plane, new_plane_state);
13219 return ret;
13220
13221 slow:
13222 return drm_atomic_helper_update_plane(plane, crtc, fb,
13223 crtc_x, crtc_y, crtc_w, crtc_h,
13224 src_x, src_y, src_w, src_h, ctx);
13225 }
13226
13227 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13228 .update_plane = intel_legacy_cursor_update,
13229 .disable_plane = drm_atomic_helper_disable_plane,
13230 .destroy = intel_plane_destroy,
13231 .atomic_get_property = intel_plane_atomic_get_property,
13232 .atomic_set_property = intel_plane_atomic_set_property,
13233 .atomic_duplicate_state = intel_plane_duplicate_state,
13234 .atomic_destroy_state = intel_plane_destroy_state,
13235 .format_mod_supported = intel_cursor_plane_format_mod_supported,
13236 };
13237
13238 static struct intel_plane *
13239 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13240 {
13241 struct intel_plane *primary = NULL;
13242 struct intel_plane_state *state = NULL;
13243 const uint32_t *intel_primary_formats;
13244 unsigned int supported_rotations;
13245 unsigned int num_formats;
13246 const uint64_t *modifiers;
13247 int ret;
13248
13249 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13250 if (!primary) {
13251 ret = -ENOMEM;
13252 goto fail;
13253 }
13254
13255 state = intel_create_plane_state(&primary->base);
13256 if (!state) {
13257 ret = -ENOMEM;
13258 goto fail;
13259 }
13260
13261 primary->base.state = &state->base;
13262
13263 primary->can_scale = false;
13264 primary->max_downscale = 1;
13265 if (INTEL_GEN(dev_priv) >= 9) {
13266 primary->can_scale = true;
13267 state->scaler_id = -1;
13268 }
13269 primary->pipe = pipe;
13270 /*
13271 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13272 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13273 */
13274 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13275 primary->plane = (enum plane) !pipe;
13276 else
13277 primary->plane = (enum plane) pipe;
13278 primary->id = PLANE_PRIMARY;
13279 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13280 primary->check_plane = intel_check_primary_plane;
13281
13282 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13283 intel_primary_formats = skl_primary_formats;
13284 num_formats = ARRAY_SIZE(skl_primary_formats);
13285 modifiers = skl_format_modifiers_ccs;
13286
13287 primary->update_plane = skylake_update_primary_plane;
13288 primary->disable_plane = skylake_disable_primary_plane;
13289 } else if (INTEL_GEN(dev_priv) >= 9) {
13290 intel_primary_formats = skl_primary_formats;
13291 num_formats = ARRAY_SIZE(skl_primary_formats);
13292 if (pipe < PIPE_C)
13293 modifiers = skl_format_modifiers_ccs;
13294 else
13295 modifiers = skl_format_modifiers_noccs;
13296
13297 primary->update_plane = skylake_update_primary_plane;
13298 primary->disable_plane = skylake_disable_primary_plane;
13299 } else if (INTEL_GEN(dev_priv) >= 4) {
13300 intel_primary_formats = i965_primary_formats;
13301 num_formats = ARRAY_SIZE(i965_primary_formats);
13302 modifiers = i9xx_format_modifiers;
13303
13304 primary->update_plane = i9xx_update_primary_plane;
13305 primary->disable_plane = i9xx_disable_primary_plane;
13306 } else {
13307 intel_primary_formats = i8xx_primary_formats;
13308 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13309 modifiers = i9xx_format_modifiers;
13310
13311 primary->update_plane = i9xx_update_primary_plane;
13312 primary->disable_plane = i9xx_disable_primary_plane;
13313 }
13314
13315 if (INTEL_GEN(dev_priv) >= 9)
13316 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13317 0, &intel_plane_funcs,
13318 intel_primary_formats, num_formats,
13319 modifiers,
13320 DRM_PLANE_TYPE_PRIMARY,
13321 "plane 1%c", pipe_name(pipe));
13322 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13323 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13324 0, &intel_plane_funcs,
13325 intel_primary_formats, num_formats,
13326 modifiers,
13327 DRM_PLANE_TYPE_PRIMARY,
13328 "primary %c", pipe_name(pipe));
13329 else
13330 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13331 0, &intel_plane_funcs,
13332 intel_primary_formats, num_formats,
13333 modifiers,
13334 DRM_PLANE_TYPE_PRIMARY,
13335 "plane %c", plane_name(primary->plane));
13336 if (ret)
13337 goto fail;
13338
13339 if (INTEL_GEN(dev_priv) >= 9) {
13340 supported_rotations =
13341 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13342 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13343 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13344 supported_rotations =
13345 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13346 DRM_MODE_REFLECT_X;
13347 } else if (INTEL_GEN(dev_priv) >= 4) {
13348 supported_rotations =
13349 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13350 } else {
13351 supported_rotations = DRM_MODE_ROTATE_0;
13352 }
13353
13354 if (INTEL_GEN(dev_priv) >= 4)
13355 drm_plane_create_rotation_property(&primary->base,
13356 DRM_MODE_ROTATE_0,
13357 supported_rotations);
13358
13359 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13360
13361 return primary;
13362
13363 fail:
13364 kfree(state);
13365 kfree(primary);
13366
13367 return ERR_PTR(ret);
13368 }
13369
13370 static struct intel_plane *
13371 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13372 enum pipe pipe)
13373 {
13374 struct intel_plane *cursor = NULL;
13375 struct intel_plane_state *state = NULL;
13376 int ret;
13377
13378 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13379 if (!cursor) {
13380 ret = -ENOMEM;
13381 goto fail;
13382 }
13383
13384 state = intel_create_plane_state(&cursor->base);
13385 if (!state) {
13386 ret = -ENOMEM;
13387 goto fail;
13388 }
13389
13390 cursor->base.state = &state->base;
13391
13392 cursor->can_scale = false;
13393 cursor->max_downscale = 1;
13394 cursor->pipe = pipe;
13395 cursor->plane = pipe;
13396 cursor->id = PLANE_CURSOR;
13397 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13398
13399 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13400 cursor->update_plane = i845_update_cursor;
13401 cursor->disable_plane = i845_disable_cursor;
13402 cursor->check_plane = i845_check_cursor;
13403 } else {
13404 cursor->update_plane = i9xx_update_cursor;
13405 cursor->disable_plane = i9xx_disable_cursor;
13406 cursor->check_plane = i9xx_check_cursor;
13407 }
13408
13409 cursor->cursor.base = ~0;
13410 cursor->cursor.cntl = ~0;
13411
13412 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13413 cursor->cursor.size = ~0;
13414
13415 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13416 0, &intel_cursor_plane_funcs,
13417 intel_cursor_formats,
13418 ARRAY_SIZE(intel_cursor_formats),
13419 cursor_format_modifiers,
13420 DRM_PLANE_TYPE_CURSOR,
13421 "cursor %c", pipe_name(pipe));
13422 if (ret)
13423 goto fail;
13424
13425 if (INTEL_GEN(dev_priv) >= 4)
13426 drm_plane_create_rotation_property(&cursor->base,
13427 DRM_MODE_ROTATE_0,
13428 DRM_MODE_ROTATE_0 |
13429 DRM_MODE_ROTATE_180);
13430
13431 if (INTEL_GEN(dev_priv) >= 9)
13432 state->scaler_id = -1;
13433
13434 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13435
13436 return cursor;
13437
13438 fail:
13439 kfree(state);
13440 kfree(cursor);
13441
13442 return ERR_PTR(ret);
13443 }
13444
13445 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13446 struct intel_crtc_state *crtc_state)
13447 {
13448 struct intel_crtc_scaler_state *scaler_state =
13449 &crtc_state->scaler_state;
13450 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13451 int i;
13452
13453 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13454 if (!crtc->num_scalers)
13455 return;
13456
13457 for (i = 0; i < crtc->num_scalers; i++) {
13458 struct intel_scaler *scaler = &scaler_state->scalers[i];
13459
13460 scaler->in_use = 0;
13461 scaler->mode = PS_SCALER_MODE_DYN;
13462 }
13463
13464 scaler_state->scaler_id = -1;
13465 }
13466
13467 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13468 {
13469 struct intel_crtc *intel_crtc;
13470 struct intel_crtc_state *crtc_state = NULL;
13471 struct intel_plane *primary = NULL;
13472 struct intel_plane *cursor = NULL;
13473 int sprite, ret;
13474
13475 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13476 if (!intel_crtc)
13477 return -ENOMEM;
13478
13479 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13480 if (!crtc_state) {
13481 ret = -ENOMEM;
13482 goto fail;
13483 }
13484 intel_crtc->config = crtc_state;
13485 intel_crtc->base.state = &crtc_state->base;
13486 crtc_state->base.crtc = &intel_crtc->base;
13487
13488 primary = intel_primary_plane_create(dev_priv, pipe);
13489 if (IS_ERR(primary)) {
13490 ret = PTR_ERR(primary);
13491 goto fail;
13492 }
13493 intel_crtc->plane_ids_mask |= BIT(primary->id);
13494
13495 for_each_sprite(dev_priv, pipe, sprite) {
13496 struct intel_plane *plane;
13497
13498 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13499 if (IS_ERR(plane)) {
13500 ret = PTR_ERR(plane);
13501 goto fail;
13502 }
13503 intel_crtc->plane_ids_mask |= BIT(plane->id);
13504 }
13505
13506 cursor = intel_cursor_plane_create(dev_priv, pipe);
13507 if (IS_ERR(cursor)) {
13508 ret = PTR_ERR(cursor);
13509 goto fail;
13510 }
13511 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13512
13513 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13514 &primary->base, &cursor->base,
13515 &intel_crtc_funcs,
13516 "pipe %c", pipe_name(pipe));
13517 if (ret)
13518 goto fail;
13519
13520 intel_crtc->pipe = pipe;
13521 intel_crtc->plane = primary->plane;
13522
13523 /* initialize shared scalers */
13524 intel_crtc_init_scalers(intel_crtc, crtc_state);
13525
13526 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13527 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13528 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13529 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13530
13531 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13532
13533 intel_color_init(&intel_crtc->base);
13534
13535 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13536
13537 return 0;
13538
13539 fail:
13540 /*
13541 * drm_mode_config_cleanup() will free up any
13542 * crtcs/planes already initialized.
13543 */
13544 kfree(crtc_state);
13545 kfree(intel_crtc);
13546
13547 return ret;
13548 }
13549
13550 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13551 {
13552 struct drm_device *dev = connector->base.dev;
13553
13554 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13555
13556 if (!connector->base.state->crtc)
13557 return INVALID_PIPE;
13558
13559 return to_intel_crtc(connector->base.state->crtc)->pipe;
13560 }
13561
13562 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13563 struct drm_file *file)
13564 {
13565 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13566 struct drm_crtc *drmmode_crtc;
13567 struct intel_crtc *crtc;
13568
13569 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13570 if (!drmmode_crtc)
13571 return -ENOENT;
13572
13573 crtc = to_intel_crtc(drmmode_crtc);
13574 pipe_from_crtc_id->pipe = crtc->pipe;
13575
13576 return 0;
13577 }
13578
13579 static int intel_encoder_clones(struct intel_encoder *encoder)
13580 {
13581 struct drm_device *dev = encoder->base.dev;
13582 struct intel_encoder *source_encoder;
13583 int index_mask = 0;
13584 int entry = 0;
13585
13586 for_each_intel_encoder(dev, source_encoder) {
13587 if (encoders_cloneable(encoder, source_encoder))
13588 index_mask |= (1 << entry);
13589
13590 entry++;
13591 }
13592
13593 return index_mask;
13594 }
13595
13596 static bool has_edp_a(struct drm_i915_private *dev_priv)
13597 {
13598 if (!IS_MOBILE(dev_priv))
13599 return false;
13600
13601 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13602 return false;
13603
13604 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13605 return false;
13606
13607 return true;
13608 }
13609
13610 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13611 {
13612 if (INTEL_GEN(dev_priv) >= 9)
13613 return false;
13614
13615 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13616 return false;
13617
13618 if (IS_CHERRYVIEW(dev_priv))
13619 return false;
13620
13621 if (HAS_PCH_LPT_H(dev_priv) &&
13622 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13623 return false;
13624
13625 /* DDI E can't be used if DDI A requires 4 lanes */
13626 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13627 return false;
13628
13629 if (!dev_priv->vbt.int_crt_support)
13630 return false;
13631
13632 return true;
13633 }
13634
13635 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13636 {
13637 int pps_num;
13638 int pps_idx;
13639
13640 if (HAS_DDI(dev_priv))
13641 return;
13642 /*
13643 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13644 * everywhere where registers can be write protected.
13645 */
13646 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13647 pps_num = 2;
13648 else
13649 pps_num = 1;
13650
13651 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13652 u32 val = I915_READ(PP_CONTROL(pps_idx));
13653
13654 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13655 I915_WRITE(PP_CONTROL(pps_idx), val);
13656 }
13657 }
13658
13659 static void intel_pps_init(struct drm_i915_private *dev_priv)
13660 {
13661 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13662 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13663 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13664 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13665 else
13666 dev_priv->pps_mmio_base = PPS_BASE;
13667
13668 intel_pps_unlock_regs_wa(dev_priv);
13669 }
13670
13671 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13672 {
13673 struct intel_encoder *encoder;
13674 bool dpd_is_edp = false;
13675
13676 intel_pps_init(dev_priv);
13677
13678 /*
13679 * intel_edp_init_connector() depends on this completing first, to
13680 * prevent the registeration of both eDP and LVDS and the incorrect
13681 * sharing of the PPS.
13682 */
13683 intel_lvds_init(dev_priv);
13684
13685 if (intel_crt_present(dev_priv))
13686 intel_crt_init(dev_priv);
13687
13688 if (IS_GEN9_LP(dev_priv)) {
13689 /*
13690 * FIXME: Broxton doesn't support port detection via the
13691 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13692 * detect the ports.
13693 */
13694 intel_ddi_init(dev_priv, PORT_A);
13695 intel_ddi_init(dev_priv, PORT_B);
13696 intel_ddi_init(dev_priv, PORT_C);
13697
13698 intel_dsi_init(dev_priv);
13699 } else if (HAS_DDI(dev_priv)) {
13700 int found;
13701
13702 /*
13703 * Haswell uses DDI functions to detect digital outputs.
13704 * On SKL pre-D0 the strap isn't connected, so we assume
13705 * it's there.
13706 */
13707 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13708 /* WaIgnoreDDIAStrap: skl */
13709 if (found || IS_GEN9_BC(dev_priv))
13710 intel_ddi_init(dev_priv, PORT_A);
13711
13712 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13713 * register */
13714 found = I915_READ(SFUSE_STRAP);
13715
13716 if (found & SFUSE_STRAP_DDIB_DETECTED)
13717 intel_ddi_init(dev_priv, PORT_B);
13718 if (found & SFUSE_STRAP_DDIC_DETECTED)
13719 intel_ddi_init(dev_priv, PORT_C);
13720 if (found & SFUSE_STRAP_DDID_DETECTED)
13721 intel_ddi_init(dev_priv, PORT_D);
13722 /*
13723 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13724 */
13725 if (IS_GEN9_BC(dev_priv) &&
13726 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13727 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13728 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13729 intel_ddi_init(dev_priv, PORT_E);
13730
13731 } else if (HAS_PCH_SPLIT(dev_priv)) {
13732 int found;
13733 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13734
13735 if (has_edp_a(dev_priv))
13736 intel_dp_init(dev_priv, DP_A, PORT_A);
13737
13738 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13739 /* PCH SDVOB multiplex with HDMIB */
13740 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13741 if (!found)
13742 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13743 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13744 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13745 }
13746
13747 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13748 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13749
13750 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13751 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13752
13753 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13754 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13755
13756 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13757 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13758 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13759 bool has_edp, has_port;
13760
13761 /*
13762 * The DP_DETECTED bit is the latched state of the DDC
13763 * SDA pin at boot. However since eDP doesn't require DDC
13764 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13765 * eDP ports may have been muxed to an alternate function.
13766 * Thus we can't rely on the DP_DETECTED bit alone to detect
13767 * eDP ports. Consult the VBT as well as DP_DETECTED to
13768 * detect eDP ports.
13769 *
13770 * Sadly the straps seem to be missing sometimes even for HDMI
13771 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13772 * and VBT for the presence of the port. Additionally we can't
13773 * trust the port type the VBT declares as we've seen at least
13774 * HDMI ports that the VBT claim are DP or eDP.
13775 */
13776 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13777 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13778 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13779 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13780 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13781 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13782
13783 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13784 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13785 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13786 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13787 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13788 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13789
13790 if (IS_CHERRYVIEW(dev_priv)) {
13791 /*
13792 * eDP not supported on port D,
13793 * so no need to worry about it
13794 */
13795 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13796 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13797 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13798 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13799 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13800 }
13801
13802 intel_dsi_init(dev_priv);
13803 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13804 bool found = false;
13805
13806 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13807 DRM_DEBUG_KMS("probing SDVOB\n");
13808 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13809 if (!found && IS_G4X(dev_priv)) {
13810 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13811 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13812 }
13813
13814 if (!found && IS_G4X(dev_priv))
13815 intel_dp_init(dev_priv, DP_B, PORT_B);
13816 }
13817
13818 /* Before G4X SDVOC doesn't have its own detect register */
13819
13820 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13821 DRM_DEBUG_KMS("probing SDVOC\n");
13822 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13823 }
13824
13825 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13826
13827 if (IS_G4X(dev_priv)) {
13828 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13829 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13830 }
13831 if (IS_G4X(dev_priv))
13832 intel_dp_init(dev_priv, DP_C, PORT_C);
13833 }
13834
13835 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13836 intel_dp_init(dev_priv, DP_D, PORT_D);
13837 } else if (IS_GEN2(dev_priv))
13838 intel_dvo_init(dev_priv);
13839
13840 if (SUPPORTS_TV(dev_priv))
13841 intel_tv_init(dev_priv);
13842
13843 intel_psr_init(dev_priv);
13844
13845 for_each_intel_encoder(&dev_priv->drm, encoder) {
13846 encoder->base.possible_crtcs = encoder->crtc_mask;
13847 encoder->base.possible_clones =
13848 intel_encoder_clones(encoder);
13849 }
13850
13851 intel_init_pch_refclk(dev_priv);
13852
13853 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13854 }
13855
13856 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13857 {
13858 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13859
13860 drm_framebuffer_cleanup(fb);
13861
13862 i915_gem_object_lock(intel_fb->obj);
13863 WARN_ON(!intel_fb->obj->framebuffer_references--);
13864 i915_gem_object_unlock(intel_fb->obj);
13865
13866 i915_gem_object_put(intel_fb->obj);
13867
13868 kfree(intel_fb);
13869 }
13870
13871 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13872 struct drm_file *file,
13873 unsigned int *handle)
13874 {
13875 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13876 struct drm_i915_gem_object *obj = intel_fb->obj;
13877
13878 if (obj->userptr.mm) {
13879 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13880 return -EINVAL;
13881 }
13882
13883 return drm_gem_handle_create(file, &obj->base, handle);
13884 }
13885
13886 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13887 struct drm_file *file,
13888 unsigned flags, unsigned color,
13889 struct drm_clip_rect *clips,
13890 unsigned num_clips)
13891 {
13892 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13893
13894 i915_gem_object_flush_if_display(obj);
13895 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13896
13897 return 0;
13898 }
13899
13900 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13901 .destroy = intel_user_framebuffer_destroy,
13902 .create_handle = intel_user_framebuffer_create_handle,
13903 .dirty = intel_user_framebuffer_dirty,
13904 };
13905
13906 static
13907 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13908 uint64_t fb_modifier, uint32_t pixel_format)
13909 {
13910 u32 gen = INTEL_GEN(dev_priv);
13911
13912 if (gen >= 9) {
13913 int cpp = drm_format_plane_cpp(pixel_format, 0);
13914
13915 /* "The stride in bytes must not exceed the of the size of 8K
13916 * pixels and 32K bytes."
13917 */
13918 return min(8192 * cpp, 32768);
13919 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13920 return 32*1024;
13921 } else if (gen >= 4) {
13922 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13923 return 16*1024;
13924 else
13925 return 32*1024;
13926 } else if (gen >= 3) {
13927 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13928 return 8*1024;
13929 else
13930 return 16*1024;
13931 } else {
13932 /* XXX DSPC is limited to 4k tiled */
13933 return 8*1024;
13934 }
13935 }
13936
13937 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13938 struct drm_i915_gem_object *obj,
13939 struct drm_mode_fb_cmd2 *mode_cmd)
13940 {
13941 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13942 struct drm_framebuffer *fb = &intel_fb->base;
13943 struct drm_format_name_buf format_name;
13944 u32 pitch_limit;
13945 unsigned int tiling, stride;
13946 int ret = -EINVAL;
13947 int i;
13948
13949 i915_gem_object_lock(obj);
13950 obj->framebuffer_references++;
13951 tiling = i915_gem_object_get_tiling(obj);
13952 stride = i915_gem_object_get_stride(obj);
13953 i915_gem_object_unlock(obj);
13954
13955 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13956 /*
13957 * If there's a fence, enforce that
13958 * the fb modifier and tiling mode match.
13959 */
13960 if (tiling != I915_TILING_NONE &&
13961 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13962 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13963 goto err;
13964 }
13965 } else {
13966 if (tiling == I915_TILING_X) {
13967 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13968 } else if (tiling == I915_TILING_Y) {
13969 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13970 goto err;
13971 }
13972 }
13973
13974 /* Passed in modifier sanity checking. */
13975 switch (mode_cmd->modifier[0]) {
13976 case I915_FORMAT_MOD_Y_TILED_CCS:
13977 case I915_FORMAT_MOD_Yf_TILED_CCS:
13978 switch (mode_cmd->pixel_format) {
13979 case DRM_FORMAT_XBGR8888:
13980 case DRM_FORMAT_ABGR8888:
13981 case DRM_FORMAT_XRGB8888:
13982 case DRM_FORMAT_ARGB8888:
13983 break;
13984 default:
13985 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13986 goto err;
13987 }
13988 /* fall through */
13989 case I915_FORMAT_MOD_Y_TILED:
13990 case I915_FORMAT_MOD_Yf_TILED:
13991 if (INTEL_GEN(dev_priv) < 9) {
13992 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13993 mode_cmd->modifier[0]);
13994 goto err;
13995 }
13996 case DRM_FORMAT_MOD_LINEAR:
13997 case I915_FORMAT_MOD_X_TILED:
13998 break;
13999 default:
14000 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14001 mode_cmd->modifier[0]);
14002 goto err;
14003 }
14004
14005 /*
14006 * gen2/3 display engine uses the fence if present,
14007 * so the tiling mode must match the fb modifier exactly.
14008 */
14009 if (INTEL_INFO(dev_priv)->gen < 4 &&
14010 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14011 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14012 goto err;
14013 }
14014
14015 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14016 mode_cmd->pixel_format);
14017 if (mode_cmd->pitches[0] > pitch_limit) {
14018 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14019 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14020 "tiled" : "linear",
14021 mode_cmd->pitches[0], pitch_limit);
14022 goto err;
14023 }
14024
14025 /*
14026 * If there's a fence, enforce that
14027 * the fb pitch and fence stride match.
14028 */
14029 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14030 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14031 mode_cmd->pitches[0], stride);
14032 goto err;
14033 }
14034
14035 /* Reject formats not supported by any plane early. */
14036 switch (mode_cmd->pixel_format) {
14037 case DRM_FORMAT_C8:
14038 case DRM_FORMAT_RGB565:
14039 case DRM_FORMAT_XRGB8888:
14040 case DRM_FORMAT_ARGB8888:
14041 break;
14042 case DRM_FORMAT_XRGB1555:
14043 if (INTEL_GEN(dev_priv) > 3) {
14044 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14045 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14046 goto err;
14047 }
14048 break;
14049 case DRM_FORMAT_ABGR8888:
14050 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14051 INTEL_GEN(dev_priv) < 9) {
14052 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14053 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14054 goto err;
14055 }
14056 break;
14057 case DRM_FORMAT_XBGR8888:
14058 case DRM_FORMAT_XRGB2101010:
14059 case DRM_FORMAT_XBGR2101010:
14060 if (INTEL_GEN(dev_priv) < 4) {
14061 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14062 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14063 goto err;
14064 }
14065 break;
14066 case DRM_FORMAT_ABGR2101010:
14067 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14068 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14069 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14070 goto err;
14071 }
14072 break;
14073 case DRM_FORMAT_YUYV:
14074 case DRM_FORMAT_UYVY:
14075 case DRM_FORMAT_YVYU:
14076 case DRM_FORMAT_VYUY:
14077 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14078 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14079 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14080 goto err;
14081 }
14082 break;
14083 default:
14084 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14085 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14086 goto err;
14087 }
14088
14089 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14090 if (mode_cmd->offsets[0] != 0)
14091 goto err;
14092
14093 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14094
14095 for (i = 0; i < fb->format->num_planes; i++) {
14096 u32 stride_alignment;
14097
14098 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14099 DRM_DEBUG_KMS("bad plane %d handle\n", i);
14100 return -EINVAL;
14101 }
14102
14103 stride_alignment = intel_fb_stride_alignment(fb, i);
14104
14105 /*
14106 * Display WA #0531: skl,bxt,kbl,glk
14107 *
14108 * Render decompression and plane width > 3840
14109 * combined with horizontal panning requires the
14110 * plane stride to be a multiple of 4. We'll just
14111 * require the entire fb to accommodate that to avoid
14112 * potential runtime errors at plane configuration time.
14113 */
14114 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14115 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14116 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14117 stride_alignment *= 4;
14118
14119 if (fb->pitches[i] & (stride_alignment - 1)) {
14120 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14121 i, fb->pitches[i], stride_alignment);
14122 goto err;
14123 }
14124 }
14125
14126 intel_fb->obj = obj;
14127
14128 ret = intel_fill_fb_info(dev_priv, fb);
14129 if (ret)
14130 goto err;
14131
14132 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14133 if (ret) {
14134 DRM_ERROR("framebuffer init failed %d\n", ret);
14135 goto err;
14136 }
14137
14138 return 0;
14139
14140 err:
14141 i915_gem_object_lock(obj);
14142 obj->framebuffer_references--;
14143 i915_gem_object_unlock(obj);
14144 return ret;
14145 }
14146
14147 static struct drm_framebuffer *
14148 intel_user_framebuffer_create(struct drm_device *dev,
14149 struct drm_file *filp,
14150 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14151 {
14152 struct drm_framebuffer *fb;
14153 struct drm_i915_gem_object *obj;
14154 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14155
14156 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14157 if (!obj)
14158 return ERR_PTR(-ENOENT);
14159
14160 fb = intel_framebuffer_create(obj, &mode_cmd);
14161 if (IS_ERR(fb))
14162 i915_gem_object_put(obj);
14163
14164 return fb;
14165 }
14166
14167 static void intel_atomic_state_free(struct drm_atomic_state *state)
14168 {
14169 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14170
14171 drm_atomic_state_default_release(state);
14172
14173 i915_sw_fence_fini(&intel_state->commit_ready);
14174
14175 kfree(state);
14176 }
14177
14178 static const struct drm_mode_config_funcs intel_mode_funcs = {
14179 .fb_create = intel_user_framebuffer_create,
14180 .get_format_info = intel_get_format_info,
14181 .output_poll_changed = intel_fbdev_output_poll_changed,
14182 .atomic_check = intel_atomic_check,
14183 .atomic_commit = intel_atomic_commit,
14184 .atomic_state_alloc = intel_atomic_state_alloc,
14185 .atomic_state_clear = intel_atomic_state_clear,
14186 .atomic_state_free = intel_atomic_state_free,
14187 };
14188
14189 /**
14190 * intel_init_display_hooks - initialize the display modesetting hooks
14191 * @dev_priv: device private
14192 */
14193 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14194 {
14195 intel_init_cdclk_hooks(dev_priv);
14196
14197 if (INTEL_INFO(dev_priv)->gen >= 9) {
14198 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14199 dev_priv->display.get_initial_plane_config =
14200 skylake_get_initial_plane_config;
14201 dev_priv->display.crtc_compute_clock =
14202 haswell_crtc_compute_clock;
14203 dev_priv->display.crtc_enable = haswell_crtc_enable;
14204 dev_priv->display.crtc_disable = haswell_crtc_disable;
14205 } else if (HAS_DDI(dev_priv)) {
14206 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14207 dev_priv->display.get_initial_plane_config =
14208 ironlake_get_initial_plane_config;
14209 dev_priv->display.crtc_compute_clock =
14210 haswell_crtc_compute_clock;
14211 dev_priv->display.crtc_enable = haswell_crtc_enable;
14212 dev_priv->display.crtc_disable = haswell_crtc_disable;
14213 } else if (HAS_PCH_SPLIT(dev_priv)) {
14214 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14215 dev_priv->display.get_initial_plane_config =
14216 ironlake_get_initial_plane_config;
14217 dev_priv->display.crtc_compute_clock =
14218 ironlake_crtc_compute_clock;
14219 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14220 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14221 } else if (IS_CHERRYVIEW(dev_priv)) {
14222 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14223 dev_priv->display.get_initial_plane_config =
14224 i9xx_get_initial_plane_config;
14225 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14226 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14227 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14228 } else if (IS_VALLEYVIEW(dev_priv)) {
14229 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14230 dev_priv->display.get_initial_plane_config =
14231 i9xx_get_initial_plane_config;
14232 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14233 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14234 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14235 } else if (IS_G4X(dev_priv)) {
14236 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14237 dev_priv->display.get_initial_plane_config =
14238 i9xx_get_initial_plane_config;
14239 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14240 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14241 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14242 } else if (IS_PINEVIEW(dev_priv)) {
14243 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14244 dev_priv->display.get_initial_plane_config =
14245 i9xx_get_initial_plane_config;
14246 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14247 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14248 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14249 } else if (!IS_GEN2(dev_priv)) {
14250 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14251 dev_priv->display.get_initial_plane_config =
14252 i9xx_get_initial_plane_config;
14253 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14254 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14255 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14256 } else {
14257 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14258 dev_priv->display.get_initial_plane_config =
14259 i9xx_get_initial_plane_config;
14260 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14261 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14262 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14263 }
14264
14265 if (IS_GEN5(dev_priv)) {
14266 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14267 } else if (IS_GEN6(dev_priv)) {
14268 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14269 } else if (IS_IVYBRIDGE(dev_priv)) {
14270 /* FIXME: detect B0+ stepping and use auto training */
14271 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14272 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14273 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14274 }
14275
14276 if (dev_priv->info.gen >= 9)
14277 dev_priv->display.update_crtcs = skl_update_crtcs;
14278 else
14279 dev_priv->display.update_crtcs = intel_update_crtcs;
14280 }
14281
14282 /*
14283 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14284 */
14285 static void quirk_ssc_force_disable(struct drm_device *dev)
14286 {
14287 struct drm_i915_private *dev_priv = to_i915(dev);
14288 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14289 DRM_INFO("applying lvds SSC disable quirk\n");
14290 }
14291
14292 /*
14293 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14294 * brightness value
14295 */
14296 static void quirk_invert_brightness(struct drm_device *dev)
14297 {
14298 struct drm_i915_private *dev_priv = to_i915(dev);
14299 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14300 DRM_INFO("applying inverted panel brightness quirk\n");
14301 }
14302
14303 /* Some VBT's incorrectly indicate no backlight is present */
14304 static void quirk_backlight_present(struct drm_device *dev)
14305 {
14306 struct drm_i915_private *dev_priv = to_i915(dev);
14307 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14308 DRM_INFO("applying backlight present quirk\n");
14309 }
14310
14311 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14312 * which is 300 ms greater than eDP spec T12 min.
14313 */
14314 static void quirk_increase_t12_delay(struct drm_device *dev)
14315 {
14316 struct drm_i915_private *dev_priv = to_i915(dev);
14317
14318 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14319 DRM_INFO("Applying T12 delay quirk\n");
14320 }
14321
14322 struct intel_quirk {
14323 int device;
14324 int subsystem_vendor;
14325 int subsystem_device;
14326 void (*hook)(struct drm_device *dev);
14327 };
14328
14329 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14330 struct intel_dmi_quirk {
14331 void (*hook)(struct drm_device *dev);
14332 const struct dmi_system_id (*dmi_id_list)[];
14333 };
14334
14335 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14336 {
14337 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14338 return 1;
14339 }
14340
14341 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14342 {
14343 .dmi_id_list = &(const struct dmi_system_id[]) {
14344 {
14345 .callback = intel_dmi_reverse_brightness,
14346 .ident = "NCR Corporation",
14347 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14348 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14349 },
14350 },
14351 { } /* terminating entry */
14352 },
14353 .hook = quirk_invert_brightness,
14354 },
14355 };
14356
14357 static struct intel_quirk intel_quirks[] = {
14358 /* Lenovo U160 cannot use SSC on LVDS */
14359 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14360
14361 /* Sony Vaio Y cannot use SSC on LVDS */
14362 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14363
14364 /* Acer Aspire 5734Z must invert backlight brightness */
14365 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14366
14367 /* Acer/eMachines G725 */
14368 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14369
14370 /* Acer/eMachines e725 */
14371 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14372
14373 /* Acer/Packard Bell NCL20 */
14374 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14375
14376 /* Acer Aspire 4736Z */
14377 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14378
14379 /* Acer Aspire 5336 */
14380 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14381
14382 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14383 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14384
14385 /* Acer C720 Chromebook (Core i3 4005U) */
14386 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14387
14388 /* Apple Macbook 2,1 (Core 2 T7400) */
14389 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14390
14391 /* Apple Macbook 4,1 */
14392 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14393
14394 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14395 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14396
14397 /* HP Chromebook 14 (Celeron 2955U) */
14398 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14399
14400 /* Dell Chromebook 11 */
14401 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14402
14403 /* Dell Chromebook 11 (2015 version) */
14404 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14405
14406 /* Toshiba Satellite P50-C-18C */
14407 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14408 };
14409
14410 static void intel_init_quirks(struct drm_device *dev)
14411 {
14412 struct pci_dev *d = dev->pdev;
14413 int i;
14414
14415 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14416 struct intel_quirk *q = &intel_quirks[i];
14417
14418 if (d->device == q->device &&
14419 (d->subsystem_vendor == q->subsystem_vendor ||
14420 q->subsystem_vendor == PCI_ANY_ID) &&
14421 (d->subsystem_device == q->subsystem_device ||
14422 q->subsystem_device == PCI_ANY_ID))
14423 q->hook(dev);
14424 }
14425 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14426 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14427 intel_dmi_quirks[i].hook(dev);
14428 }
14429 }
14430
14431 /* Disable the VGA plane that we never use */
14432 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14433 {
14434 struct pci_dev *pdev = dev_priv->drm.pdev;
14435 u8 sr1;
14436 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14437
14438 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14439 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14440 outb(SR01, VGA_SR_INDEX);
14441 sr1 = inb(VGA_SR_DATA);
14442 outb(sr1 | 1<<5, VGA_SR_DATA);
14443 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14444 udelay(300);
14445
14446 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14447 POSTING_READ(vga_reg);
14448 }
14449
14450 void intel_modeset_init_hw(struct drm_device *dev)
14451 {
14452 struct drm_i915_private *dev_priv = to_i915(dev);
14453
14454 intel_update_cdclk(dev_priv);
14455 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14456
14457 intel_init_clock_gating(dev_priv);
14458 }
14459
14460 /*
14461 * Calculate what we think the watermarks should be for the state we've read
14462 * out of the hardware and then immediately program those watermarks so that
14463 * we ensure the hardware settings match our internal state.
14464 *
14465 * We can calculate what we think WM's should be by creating a duplicate of the
14466 * current state (which was constructed during hardware readout) and running it
14467 * through the atomic check code to calculate new watermark values in the
14468 * state object.
14469 */
14470 static void sanitize_watermarks(struct drm_device *dev)
14471 {
14472 struct drm_i915_private *dev_priv = to_i915(dev);
14473 struct drm_atomic_state *state;
14474 struct intel_atomic_state *intel_state;
14475 struct drm_crtc *crtc;
14476 struct drm_crtc_state *cstate;
14477 struct drm_modeset_acquire_ctx ctx;
14478 int ret;
14479 int i;
14480
14481 /* Only supported on platforms that use atomic watermark design */
14482 if (!dev_priv->display.optimize_watermarks)
14483 return;
14484
14485 /*
14486 * We need to hold connection_mutex before calling duplicate_state so
14487 * that the connector loop is protected.
14488 */
14489 drm_modeset_acquire_init(&ctx, 0);
14490 retry:
14491 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14492 if (ret == -EDEADLK) {
14493 drm_modeset_backoff(&ctx);
14494 goto retry;
14495 } else if (WARN_ON(ret)) {
14496 goto fail;
14497 }
14498
14499 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14500 if (WARN_ON(IS_ERR(state)))
14501 goto fail;
14502
14503 intel_state = to_intel_atomic_state(state);
14504
14505 /*
14506 * Hardware readout is the only time we don't want to calculate
14507 * intermediate watermarks (since we don't trust the current
14508 * watermarks).
14509 */
14510 if (!HAS_GMCH_DISPLAY(dev_priv))
14511 intel_state->skip_intermediate_wm = true;
14512
14513 ret = intel_atomic_check(dev, state);
14514 if (ret) {
14515 /*
14516 * If we fail here, it means that the hardware appears to be
14517 * programmed in a way that shouldn't be possible, given our
14518 * understanding of watermark requirements. This might mean a
14519 * mistake in the hardware readout code or a mistake in the
14520 * watermark calculations for a given platform. Raise a WARN
14521 * so that this is noticeable.
14522 *
14523 * If this actually happens, we'll have to just leave the
14524 * BIOS-programmed watermarks untouched and hope for the best.
14525 */
14526 WARN(true, "Could not determine valid watermarks for inherited state\n");
14527 goto put_state;
14528 }
14529
14530 /* Write calculated watermark values back */
14531 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14532 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14533
14534 cs->wm.need_postvbl_update = true;
14535 dev_priv->display.optimize_watermarks(intel_state, cs);
14536 }
14537
14538 put_state:
14539 drm_atomic_state_put(state);
14540 fail:
14541 drm_modeset_drop_locks(&ctx);
14542 drm_modeset_acquire_fini(&ctx);
14543 }
14544
14545 int intel_modeset_init(struct drm_device *dev)
14546 {
14547 struct drm_i915_private *dev_priv = to_i915(dev);
14548 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14549 enum pipe pipe;
14550 struct intel_crtc *crtc;
14551
14552 drm_mode_config_init(dev);
14553
14554 dev->mode_config.min_width = 0;
14555 dev->mode_config.min_height = 0;
14556
14557 dev->mode_config.preferred_depth = 24;
14558 dev->mode_config.prefer_shadow = 1;
14559
14560 dev->mode_config.allow_fb_modifiers = true;
14561
14562 dev->mode_config.funcs = &intel_mode_funcs;
14563
14564 init_llist_head(&dev_priv->atomic_helper.free_list);
14565 INIT_WORK(&dev_priv->atomic_helper.free_work,
14566 intel_atomic_helper_free_state_worker);
14567
14568 intel_init_quirks(dev);
14569
14570 intel_init_pm(dev_priv);
14571
14572 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14573 return 0;
14574
14575 /*
14576 * There may be no VBT; and if the BIOS enabled SSC we can
14577 * just keep using it to avoid unnecessary flicker. Whereas if the
14578 * BIOS isn't using it, don't assume it will work even if the VBT
14579 * indicates as much.
14580 */
14581 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14582 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14583 DREF_SSC1_ENABLE);
14584
14585 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14586 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14587 bios_lvds_use_ssc ? "en" : "dis",
14588 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14589 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14590 }
14591 }
14592
14593 if (IS_GEN2(dev_priv)) {
14594 dev->mode_config.max_width = 2048;
14595 dev->mode_config.max_height = 2048;
14596 } else if (IS_GEN3(dev_priv)) {
14597 dev->mode_config.max_width = 4096;
14598 dev->mode_config.max_height = 4096;
14599 } else {
14600 dev->mode_config.max_width = 8192;
14601 dev->mode_config.max_height = 8192;
14602 }
14603
14604 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14605 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14606 dev->mode_config.cursor_height = 1023;
14607 } else if (IS_GEN2(dev_priv)) {
14608 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14609 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14610 } else {
14611 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14612 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14613 }
14614
14615 dev->mode_config.fb_base = ggtt->mappable_base;
14616
14617 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14618 INTEL_INFO(dev_priv)->num_pipes,
14619 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14620
14621 for_each_pipe(dev_priv, pipe) {
14622 int ret;
14623
14624 ret = intel_crtc_init(dev_priv, pipe);
14625 if (ret) {
14626 drm_mode_config_cleanup(dev);
14627 return ret;
14628 }
14629 }
14630
14631 intel_shared_dpll_init(dev);
14632
14633 intel_update_czclk(dev_priv);
14634 intel_modeset_init_hw(dev);
14635
14636 if (dev_priv->max_cdclk_freq == 0)
14637 intel_update_max_cdclk(dev_priv);
14638
14639 /* Just disable it once at startup */
14640 i915_disable_vga(dev_priv);
14641 intel_setup_outputs(dev_priv);
14642
14643 drm_modeset_lock_all(dev);
14644 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14645 drm_modeset_unlock_all(dev);
14646
14647 for_each_intel_crtc(dev, crtc) {
14648 struct intel_initial_plane_config plane_config = {};
14649
14650 if (!crtc->active)
14651 continue;
14652
14653 /*
14654 * Note that reserving the BIOS fb up front prevents us
14655 * from stuffing other stolen allocations like the ring
14656 * on top. This prevents some ugliness at boot time, and
14657 * can even allow for smooth boot transitions if the BIOS
14658 * fb is large enough for the active pipe configuration.
14659 */
14660 dev_priv->display.get_initial_plane_config(crtc,
14661 &plane_config);
14662
14663 /*
14664 * If the fb is shared between multiple heads, we'll
14665 * just get the first one.
14666 */
14667 intel_find_initial_plane_obj(crtc, &plane_config);
14668 }
14669
14670 /*
14671 * Make sure hardware watermarks really match the state we read out.
14672 * Note that we need to do this after reconstructing the BIOS fb's
14673 * since the watermark calculation done here will use pstate->fb.
14674 */
14675 if (!HAS_GMCH_DISPLAY(dev_priv))
14676 sanitize_watermarks(dev);
14677
14678 return 0;
14679 }
14680
14681 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14682 {
14683 /* 640x480@60Hz, ~25175 kHz */
14684 struct dpll clock = {
14685 .m1 = 18,
14686 .m2 = 7,
14687 .p1 = 13,
14688 .p2 = 4,
14689 .n = 2,
14690 };
14691 u32 dpll, fp;
14692 int i;
14693
14694 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14695
14696 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14697 pipe_name(pipe), clock.vco, clock.dot);
14698
14699 fp = i9xx_dpll_compute_fp(&clock);
14700 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14701 DPLL_VGA_MODE_DIS |
14702 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14703 PLL_P2_DIVIDE_BY_4 |
14704 PLL_REF_INPUT_DREFCLK |
14705 DPLL_VCO_ENABLE;
14706
14707 I915_WRITE(FP0(pipe), fp);
14708 I915_WRITE(FP1(pipe), fp);
14709
14710 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14711 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14712 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14713 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14714 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14715 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14716 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14717
14718 /*
14719 * Apparently we need to have VGA mode enabled prior to changing
14720 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14721 * dividers, even though the register value does change.
14722 */
14723 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14724 I915_WRITE(DPLL(pipe), dpll);
14725
14726 /* Wait for the clocks to stabilize. */
14727 POSTING_READ(DPLL(pipe));
14728 udelay(150);
14729
14730 /* The pixel multiplier can only be updated once the
14731 * DPLL is enabled and the clocks are stable.
14732 *
14733 * So write it again.
14734 */
14735 I915_WRITE(DPLL(pipe), dpll);
14736
14737 /* We do this three times for luck */
14738 for (i = 0; i < 3 ; i++) {
14739 I915_WRITE(DPLL(pipe), dpll);
14740 POSTING_READ(DPLL(pipe));
14741 udelay(150); /* wait for warmup */
14742 }
14743
14744 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14745 POSTING_READ(PIPECONF(pipe));
14746 }
14747
14748 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14749 {
14750 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14751 pipe_name(pipe));
14752
14753 assert_plane_disabled(dev_priv, PLANE_A);
14754 assert_plane_disabled(dev_priv, PLANE_B);
14755
14756 I915_WRITE(PIPECONF(pipe), 0);
14757 POSTING_READ(PIPECONF(pipe));
14758
14759 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14760 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14761
14762 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14763 POSTING_READ(DPLL(pipe));
14764 }
14765
14766 static bool
14767 intel_check_plane_mapping(struct intel_crtc *crtc)
14768 {
14769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14770 u32 val;
14771
14772 if (INTEL_INFO(dev_priv)->num_pipes == 1)
14773 return true;
14774
14775 val = I915_READ(DSPCNTR(!crtc->plane));
14776
14777 if ((val & DISPLAY_PLANE_ENABLE) &&
14778 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14779 return false;
14780
14781 return true;
14782 }
14783
14784 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14785 {
14786 struct drm_device *dev = crtc->base.dev;
14787 struct intel_encoder *encoder;
14788
14789 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14790 return true;
14791
14792 return false;
14793 }
14794
14795 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14796 {
14797 struct drm_device *dev = encoder->base.dev;
14798 struct intel_connector *connector;
14799
14800 for_each_connector_on_encoder(dev, &encoder->base, connector)
14801 return connector;
14802
14803 return NULL;
14804 }
14805
14806 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14807 enum transcoder pch_transcoder)
14808 {
14809 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14810 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
14811 }
14812
14813 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14814 struct drm_modeset_acquire_ctx *ctx)
14815 {
14816 struct drm_device *dev = crtc->base.dev;
14817 struct drm_i915_private *dev_priv = to_i915(dev);
14818 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14819
14820 /* Clear any frame start delays used for debugging left by the BIOS */
14821 if (!transcoder_is_dsi(cpu_transcoder)) {
14822 i915_reg_t reg = PIPECONF(cpu_transcoder);
14823
14824 I915_WRITE(reg,
14825 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14826 }
14827
14828 /* restore vblank interrupts to correct state */
14829 drm_crtc_vblank_reset(&crtc->base);
14830 if (crtc->active) {
14831 struct intel_plane *plane;
14832
14833 drm_crtc_vblank_on(&crtc->base);
14834
14835 /* Disable everything but the primary plane */
14836 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14837 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14838 continue;
14839
14840 trace_intel_disable_plane(&plane->base, crtc);
14841 plane->disable_plane(plane, crtc);
14842 }
14843 }
14844
14845 /* We need to sanitize the plane -> pipe mapping first because this will
14846 * disable the crtc (and hence change the state) if it is wrong. Note
14847 * that gen4+ has a fixed plane -> pipe mapping. */
14848 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14849 bool plane;
14850
14851 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14852 crtc->base.base.id, crtc->base.name);
14853
14854 /* Pipe has the wrong plane attached and the plane is active.
14855 * Temporarily change the plane mapping and disable everything
14856 * ... */
14857 plane = crtc->plane;
14858 crtc->base.primary->state->visible = true;
14859 crtc->plane = !plane;
14860 intel_crtc_disable_noatomic(&crtc->base, ctx);
14861 crtc->plane = plane;
14862 }
14863
14864 /* Adjust the state of the output pipe according to whether we
14865 * have active connectors/encoders. */
14866 if (crtc->active && !intel_crtc_has_encoders(crtc))
14867 intel_crtc_disable_noatomic(&crtc->base, ctx);
14868
14869 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14870 /*
14871 * We start out with underrun reporting disabled to avoid races.
14872 * For correct bookkeeping mark this on active crtcs.
14873 *
14874 * Also on gmch platforms we dont have any hardware bits to
14875 * disable the underrun reporting. Which means we need to start
14876 * out with underrun reporting disabled also on inactive pipes,
14877 * since otherwise we'll complain about the garbage we read when
14878 * e.g. coming up after runtime pm.
14879 *
14880 * No protection against concurrent access is required - at
14881 * worst a fifo underrun happens which also sets this to false.
14882 */
14883 crtc->cpu_fifo_underrun_disabled = true;
14884 /*
14885 * We track the PCH trancoder underrun reporting state
14886 * within the crtc. With crtc for pipe A housing the underrun
14887 * reporting state for PCH transcoder A, crtc for pipe B housing
14888 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14889 * and marking underrun reporting as disabled for the non-existing
14890 * PCH transcoders B and C would prevent enabling the south
14891 * error interrupt (see cpt_can_enable_serr_int()).
14892 */
14893 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
14894 crtc->pch_fifo_underrun_disabled = true;
14895 }
14896 }
14897
14898 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14899 {
14900 struct intel_connector *connector;
14901
14902 /* We need to check both for a crtc link (meaning that the
14903 * encoder is active and trying to read from a pipe) and the
14904 * pipe itself being active. */
14905 bool has_active_crtc = encoder->base.crtc &&
14906 to_intel_crtc(encoder->base.crtc)->active;
14907
14908 connector = intel_encoder_find_connector(encoder);
14909 if (connector && !has_active_crtc) {
14910 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14911 encoder->base.base.id,
14912 encoder->base.name);
14913
14914 /* Connector is active, but has no active pipe. This is
14915 * fallout from our resume register restoring. Disable
14916 * the encoder manually again. */
14917 if (encoder->base.crtc) {
14918 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14919
14920 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14921 encoder->base.base.id,
14922 encoder->base.name);
14923 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14924 if (encoder->post_disable)
14925 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14926 }
14927 encoder->base.crtc = NULL;
14928
14929 /* Inconsistent output/port/pipe state happens presumably due to
14930 * a bug in one of the get_hw_state functions. Or someplace else
14931 * in our code, like the register restore mess on resume. Clamp
14932 * things to off as a safer default. */
14933
14934 connector->base.dpms = DRM_MODE_DPMS_OFF;
14935 connector->base.encoder = NULL;
14936 }
14937 /* Enabled encoders without active connectors will be fixed in
14938 * the crtc fixup. */
14939 }
14940
14941 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14942 {
14943 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14944
14945 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14946 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14947 i915_disable_vga(dev_priv);
14948 }
14949 }
14950
14951 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14952 {
14953 /* This function can be called both from intel_modeset_setup_hw_state or
14954 * at a very early point in our resume sequence, where the power well
14955 * structures are not yet restored. Since this function is at a very
14956 * paranoid "someone might have enabled VGA while we were not looking"
14957 * level, just check if the power well is enabled instead of trying to
14958 * follow the "don't touch the power well if we don't need it" policy
14959 * the rest of the driver uses. */
14960 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14961 return;
14962
14963 i915_redisable_vga_power_on(dev_priv);
14964
14965 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14966 }
14967
14968 static bool primary_get_hw_state(struct intel_plane *plane)
14969 {
14970 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14971
14972 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14973 }
14974
14975 /* FIXME read out full plane state for all planes */
14976 static void readout_plane_state(struct intel_crtc *crtc)
14977 {
14978 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14979 bool visible;
14980
14981 visible = crtc->active && primary_get_hw_state(primary);
14982
14983 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14984 to_intel_plane_state(primary->base.state),
14985 visible);
14986 }
14987
14988 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14989 {
14990 struct drm_i915_private *dev_priv = to_i915(dev);
14991 enum pipe pipe;
14992 struct intel_crtc *crtc;
14993 struct intel_encoder *encoder;
14994 struct intel_connector *connector;
14995 struct drm_connector_list_iter conn_iter;
14996 int i;
14997
14998 dev_priv->active_crtcs = 0;
14999
15000 for_each_intel_crtc(dev, crtc) {
15001 struct intel_crtc_state *crtc_state =
15002 to_intel_crtc_state(crtc->base.state);
15003
15004 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15005 memset(crtc_state, 0, sizeof(*crtc_state));
15006 crtc_state->base.crtc = &crtc->base;
15007
15008 crtc_state->base.active = crtc_state->base.enable =
15009 dev_priv->display.get_pipe_config(crtc, crtc_state);
15010
15011 crtc->base.enabled = crtc_state->base.enable;
15012 crtc->active = crtc_state->base.active;
15013
15014 if (crtc_state->base.active)
15015 dev_priv->active_crtcs |= 1 << crtc->pipe;
15016
15017 readout_plane_state(crtc);
15018
15019 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15020 crtc->base.base.id, crtc->base.name,
15021 enableddisabled(crtc_state->base.active));
15022 }
15023
15024 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15025 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15026
15027 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15028 &pll->state.hw_state);
15029 pll->state.crtc_mask = 0;
15030 for_each_intel_crtc(dev, crtc) {
15031 struct intel_crtc_state *crtc_state =
15032 to_intel_crtc_state(crtc->base.state);
15033
15034 if (crtc_state->base.active &&
15035 crtc_state->shared_dpll == pll)
15036 pll->state.crtc_mask |= 1 << crtc->pipe;
15037 }
15038 pll->active_mask = pll->state.crtc_mask;
15039
15040 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15041 pll->name, pll->state.crtc_mask, pll->on);
15042 }
15043
15044 for_each_intel_encoder(dev, encoder) {
15045 pipe = 0;
15046
15047 if (encoder->get_hw_state(encoder, &pipe)) {
15048 struct intel_crtc_state *crtc_state;
15049
15050 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15051 crtc_state = to_intel_crtc_state(crtc->base.state);
15052
15053 encoder->base.crtc = &crtc->base;
15054 crtc_state->output_types |= 1 << encoder->type;
15055 encoder->get_config(encoder, crtc_state);
15056 } else {
15057 encoder->base.crtc = NULL;
15058 }
15059
15060 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15061 encoder->base.base.id, encoder->base.name,
15062 enableddisabled(encoder->base.crtc),
15063 pipe_name(pipe));
15064 }
15065
15066 drm_connector_list_iter_begin(dev, &conn_iter);
15067 for_each_intel_connector_iter(connector, &conn_iter) {
15068 if (connector->get_hw_state(connector)) {
15069 connector->base.dpms = DRM_MODE_DPMS_ON;
15070
15071 encoder = connector->encoder;
15072 connector->base.encoder = &encoder->base;
15073
15074 if (encoder->base.crtc &&
15075 encoder->base.crtc->state->active) {
15076 /*
15077 * This has to be done during hardware readout
15078 * because anything calling .crtc_disable may
15079 * rely on the connector_mask being accurate.
15080 */
15081 encoder->base.crtc->state->connector_mask |=
15082 1 << drm_connector_index(&connector->base);
15083 encoder->base.crtc->state->encoder_mask |=
15084 1 << drm_encoder_index(&encoder->base);
15085 }
15086
15087 } else {
15088 connector->base.dpms = DRM_MODE_DPMS_OFF;
15089 connector->base.encoder = NULL;
15090 }
15091 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15092 connector->base.base.id, connector->base.name,
15093 enableddisabled(connector->base.encoder));
15094 }
15095 drm_connector_list_iter_end(&conn_iter);
15096
15097 for_each_intel_crtc(dev, crtc) {
15098 struct intel_crtc_state *crtc_state =
15099 to_intel_crtc_state(crtc->base.state);
15100 int pixclk = 0;
15101
15102 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15103 if (crtc_state->base.active) {
15104 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15105 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15106 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15107
15108 /*
15109 * The initial mode needs to be set in order to keep
15110 * the atomic core happy. It wants a valid mode if the
15111 * crtc's enabled, so we do the above call.
15112 *
15113 * But we don't set all the derived state fully, hence
15114 * set a flag to indicate that a full recalculation is
15115 * needed on the next commit.
15116 */
15117 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15118
15119 intel_crtc_compute_pixel_rate(crtc_state);
15120
15121 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15122 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15123 pixclk = crtc_state->pixel_rate;
15124 else
15125 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15126
15127 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15128 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15129 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15130
15131 drm_calc_timestamping_constants(&crtc->base,
15132 &crtc_state->base.adjusted_mode);
15133 update_scanline_offset(crtc);
15134 }
15135
15136 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15137
15138 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15139 }
15140 }
15141
15142 static void
15143 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15144 {
15145 struct intel_encoder *encoder;
15146
15147 for_each_intel_encoder(&dev_priv->drm, encoder) {
15148 u64 get_domains;
15149 enum intel_display_power_domain domain;
15150
15151 if (!encoder->get_power_domains)
15152 continue;
15153
15154 get_domains = encoder->get_power_domains(encoder);
15155 for_each_power_domain(domain, get_domains)
15156 intel_display_power_get(dev_priv, domain);
15157 }
15158 }
15159
15160 /* Scan out the current hw modeset state,
15161 * and sanitizes it to the current state
15162 */
15163 static void
15164 intel_modeset_setup_hw_state(struct drm_device *dev,
15165 struct drm_modeset_acquire_ctx *ctx)
15166 {
15167 struct drm_i915_private *dev_priv = to_i915(dev);
15168 enum pipe pipe;
15169 struct intel_crtc *crtc;
15170 struct intel_encoder *encoder;
15171 int i;
15172
15173 intel_modeset_readout_hw_state(dev);
15174
15175 /* HW state is read out, now we need to sanitize this mess. */
15176 get_encoder_power_domains(dev_priv);
15177
15178 for_each_intel_encoder(dev, encoder) {
15179 intel_sanitize_encoder(encoder);
15180 }
15181
15182 for_each_pipe(dev_priv, pipe) {
15183 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15184
15185 intel_sanitize_crtc(crtc, ctx);
15186 intel_dump_pipe_config(crtc, crtc->config,
15187 "[setup_hw_state]");
15188 }
15189
15190 intel_modeset_update_connector_atomic_state(dev);
15191
15192 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15193 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15194
15195 if (!pll->on || pll->active_mask)
15196 continue;
15197
15198 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15199
15200 pll->funcs.disable(dev_priv, pll);
15201 pll->on = false;
15202 }
15203
15204 if (IS_G4X(dev_priv)) {
15205 g4x_wm_get_hw_state(dev);
15206 g4x_wm_sanitize(dev_priv);
15207 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15208 vlv_wm_get_hw_state(dev);
15209 vlv_wm_sanitize(dev_priv);
15210 } else if (INTEL_GEN(dev_priv) >= 9) {
15211 skl_wm_get_hw_state(dev);
15212 } else if (HAS_PCH_SPLIT(dev_priv)) {
15213 ilk_wm_get_hw_state(dev);
15214 }
15215
15216 for_each_intel_crtc(dev, crtc) {
15217 u64 put_domains;
15218
15219 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15220 if (WARN_ON(put_domains))
15221 modeset_put_power_domains(dev_priv, put_domains);
15222 }
15223 intel_display_set_init_power(dev_priv, false);
15224
15225 intel_power_domains_verify_state(dev_priv);
15226
15227 intel_fbc_init_pipe_state(dev_priv);
15228 }
15229
15230 void intel_display_resume(struct drm_device *dev)
15231 {
15232 struct drm_i915_private *dev_priv = to_i915(dev);
15233 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15234 struct drm_modeset_acquire_ctx ctx;
15235 int ret;
15236
15237 dev_priv->modeset_restore_state = NULL;
15238 if (state)
15239 state->acquire_ctx = &ctx;
15240
15241 drm_modeset_acquire_init(&ctx, 0);
15242
15243 while (1) {
15244 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15245 if (ret != -EDEADLK)
15246 break;
15247
15248 drm_modeset_backoff(&ctx);
15249 }
15250
15251 if (!ret)
15252 ret = __intel_display_resume(dev, state, &ctx);
15253
15254 drm_modeset_drop_locks(&ctx);
15255 drm_modeset_acquire_fini(&ctx);
15256
15257 if (ret)
15258 DRM_ERROR("Restoring old state failed with %i\n", ret);
15259 if (state)
15260 drm_atomic_state_put(state);
15261 }
15262
15263 void intel_modeset_gem_init(struct drm_device *dev)
15264 {
15265 struct drm_i915_private *dev_priv = to_i915(dev);
15266
15267 intel_init_gt_powersave(dev_priv);
15268
15269 intel_setup_overlay(dev_priv);
15270 }
15271
15272 int intel_connector_register(struct drm_connector *connector)
15273 {
15274 struct intel_connector *intel_connector = to_intel_connector(connector);
15275 int ret;
15276
15277 ret = intel_backlight_device_register(intel_connector);
15278 if (ret)
15279 goto err;
15280
15281 return 0;
15282
15283 err:
15284 return ret;
15285 }
15286
15287 void intel_connector_unregister(struct drm_connector *connector)
15288 {
15289 struct intel_connector *intel_connector = to_intel_connector(connector);
15290
15291 intel_backlight_device_unregister(intel_connector);
15292 intel_panel_destroy_backlight(connector);
15293 }
15294
15295 void intel_modeset_cleanup(struct drm_device *dev)
15296 {
15297 struct drm_i915_private *dev_priv = to_i915(dev);
15298
15299 flush_work(&dev_priv->atomic_helper.free_work);
15300 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15301
15302 intel_disable_gt_powersave(dev_priv);
15303
15304 /*
15305 * Interrupts and polling as the first thing to avoid creating havoc.
15306 * Too much stuff here (turning of connectors, ...) would
15307 * experience fancy races otherwise.
15308 */
15309 intel_irq_uninstall(dev_priv);
15310
15311 /*
15312 * Due to the hpd irq storm handling the hotplug work can re-arm the
15313 * poll handlers. Hence disable polling after hpd handling is shut down.
15314 */
15315 drm_kms_helper_poll_fini(dev);
15316
15317 /* poll work can call into fbdev, hence clean that up afterwards */
15318 intel_fbdev_fini(dev_priv);
15319
15320 intel_unregister_dsm_handler();
15321
15322 intel_fbc_global_disable(dev_priv);
15323
15324 /* flush any delayed tasks or pending work */
15325 flush_scheduled_work();
15326
15327 drm_mode_config_cleanup(dev);
15328
15329 intel_cleanup_overlay(dev_priv);
15330
15331 intel_cleanup_gt_powersave(dev_priv);
15332
15333 intel_teardown_gmbus(dev_priv);
15334 }
15335
15336 void intel_connector_attach_encoder(struct intel_connector *connector,
15337 struct intel_encoder *encoder)
15338 {
15339 connector->encoder = encoder;
15340 drm_mode_connector_attach_encoder(&connector->base,
15341 &encoder->base);
15342 }
15343
15344 /*
15345 * set vga decode state - true == enable VGA decode
15346 */
15347 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15348 {
15349 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15350 u16 gmch_ctrl;
15351
15352 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15353 DRM_ERROR("failed to read control word\n");
15354 return -EIO;
15355 }
15356
15357 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15358 return 0;
15359
15360 if (state)
15361 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15362 else
15363 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15364
15365 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15366 DRM_ERROR("failed to write control word\n");
15367 return -EIO;
15368 }
15369
15370 return 0;
15371 }
15372
15373 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15374
15375 struct intel_display_error_state {
15376
15377 u32 power_well_driver;
15378
15379 int num_transcoders;
15380
15381 struct intel_cursor_error_state {
15382 u32 control;
15383 u32 position;
15384 u32 base;
15385 u32 size;
15386 } cursor[I915_MAX_PIPES];
15387
15388 struct intel_pipe_error_state {
15389 bool power_domain_on;
15390 u32 source;
15391 u32 stat;
15392 } pipe[I915_MAX_PIPES];
15393
15394 struct intel_plane_error_state {
15395 u32 control;
15396 u32 stride;
15397 u32 size;
15398 u32 pos;
15399 u32 addr;
15400 u32 surface;
15401 u32 tile_offset;
15402 } plane[I915_MAX_PIPES];
15403
15404 struct intel_transcoder_error_state {
15405 bool power_domain_on;
15406 enum transcoder cpu_transcoder;
15407
15408 u32 conf;
15409
15410 u32 htotal;
15411 u32 hblank;
15412 u32 hsync;
15413 u32 vtotal;
15414 u32 vblank;
15415 u32 vsync;
15416 } transcoder[4];
15417 };
15418
15419 struct intel_display_error_state *
15420 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15421 {
15422 struct intel_display_error_state *error;
15423 int transcoders[] = {
15424 TRANSCODER_A,
15425 TRANSCODER_B,
15426 TRANSCODER_C,
15427 TRANSCODER_EDP,
15428 };
15429 int i;
15430
15431 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15432 return NULL;
15433
15434 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15435 if (error == NULL)
15436 return NULL;
15437
15438 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15439 error->power_well_driver =
15440 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15441
15442 for_each_pipe(dev_priv, i) {
15443 error->pipe[i].power_domain_on =
15444 __intel_display_power_is_enabled(dev_priv,
15445 POWER_DOMAIN_PIPE(i));
15446 if (!error->pipe[i].power_domain_on)
15447 continue;
15448
15449 error->cursor[i].control = I915_READ(CURCNTR(i));
15450 error->cursor[i].position = I915_READ(CURPOS(i));
15451 error->cursor[i].base = I915_READ(CURBASE(i));
15452
15453 error->plane[i].control = I915_READ(DSPCNTR(i));
15454 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15455 if (INTEL_GEN(dev_priv) <= 3) {
15456 error->plane[i].size = I915_READ(DSPSIZE(i));
15457 error->plane[i].pos = I915_READ(DSPPOS(i));
15458 }
15459 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15460 error->plane[i].addr = I915_READ(DSPADDR(i));
15461 if (INTEL_GEN(dev_priv) >= 4) {
15462 error->plane[i].surface = I915_READ(DSPSURF(i));
15463 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15464 }
15465
15466 error->pipe[i].source = I915_READ(PIPESRC(i));
15467
15468 if (HAS_GMCH_DISPLAY(dev_priv))
15469 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15470 }
15471
15472 /* Note: this does not include DSI transcoders. */
15473 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15474 if (HAS_DDI(dev_priv))
15475 error->num_transcoders++; /* Account for eDP. */
15476
15477 for (i = 0; i < error->num_transcoders; i++) {
15478 enum transcoder cpu_transcoder = transcoders[i];
15479
15480 error->transcoder[i].power_domain_on =
15481 __intel_display_power_is_enabled(dev_priv,
15482 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15483 if (!error->transcoder[i].power_domain_on)
15484 continue;
15485
15486 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15487
15488 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15489 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15490 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15491 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15492 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15493 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15494 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15495 }
15496
15497 return error;
15498 }
15499
15500 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15501
15502 void
15503 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15504 struct intel_display_error_state *error)
15505 {
15506 struct drm_i915_private *dev_priv = m->i915;
15507 int i;
15508
15509 if (!error)
15510 return;
15511
15512 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15513 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15514 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15515 error->power_well_driver);
15516 for_each_pipe(dev_priv, i) {
15517 err_printf(m, "Pipe [%d]:\n", i);
15518 err_printf(m, " Power: %s\n",
15519 onoff(error->pipe[i].power_domain_on));
15520 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15521 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15522
15523 err_printf(m, "Plane [%d]:\n", i);
15524 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15525 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15526 if (INTEL_GEN(dev_priv) <= 3) {
15527 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15528 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15529 }
15530 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15531 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15532 if (INTEL_GEN(dev_priv) >= 4) {
15533 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15534 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15535 }
15536
15537 err_printf(m, "Cursor [%d]:\n", i);
15538 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15539 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15540 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15541 }
15542
15543 for (i = 0; i < error->num_transcoders; i++) {
15544 err_printf(m, "CPU transcoder: %s\n",
15545 transcoder_name(error->transcoder[i].cpu_transcoder));
15546 err_printf(m, " Power: %s\n",
15547 onoff(error->transcoder[i].power_domain_on));
15548 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15549 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15550 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15551 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15552 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15553 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15554 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15555 }
15556 }
15557
15558 #endif
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