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[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 int min, max;
50 } intel_range_t;
51
52 typedef struct {
53 int dot_limit;
54 int p2_slow, p2_fast;
55 } intel_p2_t;
56
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
59 struct intel_limit {
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
80 };
81
82 /* FDI */
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
85 int
86 intel_pch_rawclk(struct drm_device *dev)
87 {
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93 }
94
95 static bool
96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99 static bool
100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
103
104 static bool
105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109 static inline u32 /* units of 100MHz */
110 intel_fdi_link_freq(struct drm_device *dev)
111 {
112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
117 }
118
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
130 .find_pll = intel_find_best_PLL,
131 };
132
133 static const intel_limit_t intel_limits_i8xx_lvds = {
134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
144 .find_pll = intel_find_best_PLL,
145 };
146
147 static const intel_limit_t intel_limits_i9xx_sdvo = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
158 .find_pll = intel_find_best_PLL,
159 };
160
161 static const intel_limit_t intel_limits_i9xx_lvds = {
162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
172 .find_pll = intel_find_best_PLL,
173 };
174
175
176 static const intel_limit_t intel_limits_g4x_sdvo = {
177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
188 },
189 .find_pll = intel_g4x_find_best_PLL,
190 };
191
192 static const intel_limit_t intel_limits_g4x_hdmi = {
193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
203 .find_pll = intel_g4x_find_best_PLL,
204 };
205
206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
217 },
218 .find_pll = intel_g4x_find_best_PLL,
219 };
220
221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
232 },
233 .find_pll = intel_g4x_find_best_PLL,
234 };
235
236 static const intel_limit_t intel_limits_pineview_sdvo = {
237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
239 /* Pineview's Ncounter is a ring counter */
240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
242 /* Pineview only has one combined m divider, which we treat as m2. */
243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
249 .find_pll = intel_find_best_PLL,
250 };
251
252 static const intel_limit_t intel_limits_pineview_lvds = {
253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
263 .find_pll = intel_find_best_PLL,
264 };
265
266 /* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
271 static const intel_limit_t intel_limits_ironlake_dac = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
282 .find_pll = intel_g4x_find_best_PLL,
283 };
284
285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
296 .find_pll = intel_g4x_find_best_PLL,
297 };
298
299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 .find_pll = intel_g4x_find_best_PLL,
311 };
312
313 /* LVDS 100mhz refclk limits. */
314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
322 .p1 = { .min = 2, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
325 .find_pll = intel_g4x_find_best_PLL,
326 };
327
328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
336 .p1 = { .min = 2, .max = 6 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 .find_pll = intel_g4x_find_best_PLL,
340 };
341
342 static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354 };
355
356 static const intel_limit_t intel_limits_vlv_hdmi = {
357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368 };
369
370 static const intel_limit_t intel_limits_vlv_dp = {
371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
373 .n = { .min = 1, .max = 7 },
374 .m = { .min = 22, .max = 450 },
375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
378 .p1 = { .min = 1, .max = 3 },
379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382 };
383
384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385 {
386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
387
388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
390 return 0;
391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
398 return 0;
399 }
400
401 return I915_READ(DPIO_DATA);
402 }
403
404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
405 {
406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
407
408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
410 return;
411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
419 }
420
421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
423 {
424 struct drm_device *dev = crtc->dev;
425 const intel_limit_t *limit;
426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
428 if (intel_is_dual_link_lvds(dev)) {
429 if (refclk == 100000)
430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
439 } else
440 limit = &intel_limits_ironlake_dac;
441
442 return limit;
443 }
444
445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446 {
447 struct drm_device *dev = crtc->dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev))
452 limit = &intel_limits_g4x_dual_channel_lvds;
453 else
454 limit = &intel_limits_g4x_single_channel_lvds;
455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
457 limit = &intel_limits_g4x_hdmi;
458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
459 limit = &intel_limits_g4x_sdvo;
460 } else /* The option is for other outputs */
461 limit = &intel_limits_i9xx_sdvo;
462
463 return limit;
464 }
465
466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
467 {
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
471 if (HAS_PCH_SPLIT(dev))
472 limit = intel_ironlake_limit(crtc, refclk);
473 else if (IS_G4X(dev)) {
474 limit = intel_g4x_limit(crtc);
475 } else if (IS_PINEVIEW(dev)) {
476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
477 limit = &intel_limits_pineview_lvds;
478 else
479 limit = &intel_limits_pineview_sdvo;
480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
494 limit = &intel_limits_i8xx_lvds;
495 else
496 limit = &intel_limits_i8xx_dvo;
497 }
498 return limit;
499 }
500
501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
502 static void pineview_clock(int refclk, intel_clock_t *clock)
503 {
504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508 }
509
510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511 {
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513 }
514
515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516 {
517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
519 return;
520 }
521 clock->m = i9xx_dpll_compute_m(clock);
522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525 }
526
527 /**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
531 {
532 struct drm_device *dev = crtc->dev;
533 struct intel_encoder *encoder;
534
535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
537 return true;
538
539 return false;
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
553 INTELPllInvalid("p1 out of range\n");
554 if (clock->p < limit->p.min || limit->p.max < clock->p)
555 INTELPllInvalid("p out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
561 INTELPllInvalid("m1 <= m2\n");
562 if (clock->m < limit->m.min || limit->m.max < clock->m)
563 INTELPllInvalid("m out of range\n");
564 if (clock->n < limit->n.min || limit->n.max < clock->n)
565 INTELPllInvalid("n out of range\n");
566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
567 INTELPllInvalid("vco out of range\n");
568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
572 INTELPllInvalid("dot out of range\n");
573
574 return true;
575 }
576
577 static bool
578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
581
582 {
583 struct drm_device *dev = crtc->dev;
584 intel_clock_t clock;
585 int err = target;
586
587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
588 /*
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
592 */
593 if (intel_is_dual_link_lvds(dev))
594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
604 memset(best_clock, 0, sizeof(*best_clock));
605
606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
617 int this_err;
618
619 intel_clock(dev, refclk, &clock);
620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
622 continue;
623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638 }
639
640 static bool
641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
644 {
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
647 int max_n;
648 bool found;
649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666 max_n = limit->n.max;
667 /* based on hardware requirement, prefer smaller n to precision */
668 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
669 /* based on hardware requirement, prefere larger m1,m2 */
670 for (clock.m1 = limit->m1.max;
671 clock.m1 >= limit->m1.min; clock.m1--) {
672 for (clock.m2 = limit->m2.max;
673 clock.m2 >= limit->m2.min; clock.m2--) {
674 for (clock.p1 = limit->p1.max;
675 clock.p1 >= limit->p1.min; clock.p1--) {
676 int this_err;
677
678 intel_clock(dev, refclk, &clock);
679 if (!intel_PLL_is_valid(dev, limit,
680 &clock))
681 continue;
682
683 this_err = abs(clock.dot - target);
684 if (this_err < err_most) {
685 *best_clock = clock;
686 err_most = this_err;
687 max_n = clock.n;
688 found = true;
689 }
690 }
691 }
692 }
693 }
694 return found;
695 }
696
697 static bool
698 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
699 int target, int refclk, intel_clock_t *match_clock,
700 intel_clock_t *best_clock)
701 {
702 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
703 u32 m, n, fastclk;
704 u32 updrate, minupdate, fracbits, p;
705 unsigned long bestppm, ppm, absppm;
706 int dotclk, flag;
707
708 flag = 0;
709 dotclk = target * 1000;
710 bestppm = 1000000;
711 ppm = absppm = 0;
712 fastclk = dotclk / (2*100);
713 updrate = 0;
714 minupdate = 19200;
715 fracbits = 1;
716 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
717 bestm1 = bestm2 = bestp1 = bestp2 = 0;
718
719 /* based on hardware requirement, prefer smaller n to precision */
720 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
721 updrate = refclk / n;
722 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
723 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
724 if (p2 > 10)
725 p2 = p2 - 1;
726 p = p1 * p2;
727 /* based on hardware requirement, prefer bigger m1,m2 values */
728 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
729 m2 = (((2*(fastclk * p * n / m1 )) +
730 refclk) / (2*refclk));
731 m = m1 * m2;
732 vco = updrate * m;
733 if (vco >= limit->vco.min && vco < limit->vco.max) {
734 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
735 absppm = (ppm > 0) ? ppm : (-ppm);
736 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
737 bestppm = 0;
738 flag = 1;
739 }
740 if (absppm < bestppm - 10) {
741 bestppm = absppm;
742 flag = 1;
743 }
744 if (flag) {
745 bestn = n;
746 bestm1 = m1;
747 bestm2 = m2;
748 bestp1 = p1;
749 bestp2 = p2;
750 flag = 0;
751 }
752 }
753 }
754 }
755 }
756 }
757 best_clock->n = bestn;
758 best_clock->m1 = bestm1;
759 best_clock->m2 = bestm2;
760 best_clock->p1 = bestp1;
761 best_clock->p2 = bestp2;
762
763 return true;
764 }
765
766 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
767 enum pipe pipe)
768 {
769 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
771
772 return intel_crtc->config.cpu_transcoder;
773 }
774
775 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
776 {
777 struct drm_i915_private *dev_priv = dev->dev_private;
778 u32 frame, frame_reg = PIPEFRAME(pipe);
779
780 frame = I915_READ(frame_reg);
781
782 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
783 DRM_DEBUG_KMS("vblank wait timed out\n");
784 }
785
786 /**
787 * intel_wait_for_vblank - wait for vblank on a given pipe
788 * @dev: drm device
789 * @pipe: pipe to wait for
790 *
791 * Wait for vblank to occur on a given pipe. Needed for various bits of
792 * mode setting code.
793 */
794 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
795 {
796 struct drm_i915_private *dev_priv = dev->dev_private;
797 int pipestat_reg = PIPESTAT(pipe);
798
799 if (INTEL_INFO(dev)->gen >= 5) {
800 ironlake_wait_for_vblank(dev, pipe);
801 return;
802 }
803
804 /* Clear existing vblank status. Note this will clear any other
805 * sticky status fields as well.
806 *
807 * This races with i915_driver_irq_handler() with the result
808 * that either function could miss a vblank event. Here it is not
809 * fatal, as we will either wait upon the next vblank interrupt or
810 * timeout. Generally speaking intel_wait_for_vblank() is only
811 * called during modeset at which time the GPU should be idle and
812 * should *not* be performing page flips and thus not waiting on
813 * vblanks...
814 * Currently, the result of us stealing a vblank from the irq
815 * handler is that a single frame will be skipped during swapbuffers.
816 */
817 I915_WRITE(pipestat_reg,
818 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
819
820 /* Wait for vblank interrupt bit to set */
821 if (wait_for(I915_READ(pipestat_reg) &
822 PIPE_VBLANK_INTERRUPT_STATUS,
823 50))
824 DRM_DEBUG_KMS("vblank wait timed out\n");
825 }
826
827 /*
828 * intel_wait_for_pipe_off - wait for pipe to turn off
829 * @dev: drm device
830 * @pipe: pipe to wait for
831 *
832 * After disabling a pipe, we can't wait for vblank in the usual way,
833 * spinning on the vblank interrupt status bit, since we won't actually
834 * see an interrupt when the pipe is disabled.
835 *
836 * On Gen4 and above:
837 * wait for the pipe register state bit to turn off
838 *
839 * Otherwise:
840 * wait for the display line value to settle (it usually
841 * ends up stopping at the start of the next frame).
842 *
843 */
844 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
845 {
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
848 pipe);
849
850 if (INTEL_INFO(dev)->gen >= 4) {
851 int reg = PIPECONF(cpu_transcoder);
852
853 /* Wait for the Pipe State to go off */
854 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
855 100))
856 WARN(1, "pipe_off wait timed out\n");
857 } else {
858 u32 last_line, line_mask;
859 int reg = PIPEDSL(pipe);
860 unsigned long timeout = jiffies + msecs_to_jiffies(100);
861
862 if (IS_GEN2(dev))
863 line_mask = DSL_LINEMASK_GEN2;
864 else
865 line_mask = DSL_LINEMASK_GEN3;
866
867 /* Wait for the display line to settle */
868 do {
869 last_line = I915_READ(reg) & line_mask;
870 mdelay(5);
871 } while (((I915_READ(reg) & line_mask) != last_line) &&
872 time_after(timeout, jiffies));
873 if (time_after(jiffies, timeout))
874 WARN(1, "pipe_off wait timed out\n");
875 }
876 }
877
878 /*
879 * ibx_digital_port_connected - is the specified port connected?
880 * @dev_priv: i915 private structure
881 * @port: the port to test
882 *
883 * Returns true if @port is connected, false otherwise.
884 */
885 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
886 struct intel_digital_port *port)
887 {
888 u32 bit;
889
890 if (HAS_PCH_IBX(dev_priv->dev)) {
891 switch(port->port) {
892 case PORT_B:
893 bit = SDE_PORTB_HOTPLUG;
894 break;
895 case PORT_C:
896 bit = SDE_PORTC_HOTPLUG;
897 break;
898 case PORT_D:
899 bit = SDE_PORTD_HOTPLUG;
900 break;
901 default:
902 return true;
903 }
904 } else {
905 switch(port->port) {
906 case PORT_B:
907 bit = SDE_PORTB_HOTPLUG_CPT;
908 break;
909 case PORT_C:
910 bit = SDE_PORTC_HOTPLUG_CPT;
911 break;
912 case PORT_D:
913 bit = SDE_PORTD_HOTPLUG_CPT;
914 break;
915 default:
916 return true;
917 }
918 }
919
920 return I915_READ(SDEISR) & bit;
921 }
922
923 static const char *state_string(bool enabled)
924 {
925 return enabled ? "on" : "off";
926 }
927
928 /* Only for pre-ILK configs */
929 static void assert_pll(struct drm_i915_private *dev_priv,
930 enum pipe pipe, bool state)
931 {
932 int reg;
933 u32 val;
934 bool cur_state;
935
936 reg = DPLL(pipe);
937 val = I915_READ(reg);
938 cur_state = !!(val & DPLL_VCO_ENABLE);
939 WARN(cur_state != state,
940 "PLL state assertion failure (expected %s, current %s)\n",
941 state_string(state), state_string(cur_state));
942 }
943 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
944 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
945
946 /* For ILK+ */
947 static void assert_pch_pll(struct drm_i915_private *dev_priv,
948 struct intel_pch_pll *pll,
949 struct intel_crtc *crtc,
950 bool state)
951 {
952 u32 val;
953 bool cur_state;
954
955 if (HAS_PCH_LPT(dev_priv->dev)) {
956 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
957 return;
958 }
959
960 if (WARN (!pll,
961 "asserting PCH PLL %s with no PLL\n", state_string(state)))
962 return;
963
964 val = I915_READ(pll->pll_reg);
965 cur_state = !!(val & DPLL_VCO_ENABLE);
966 WARN(cur_state != state,
967 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
968 pll->pll_reg, state_string(state), state_string(cur_state), val);
969
970 /* Make sure the selected PLL is correctly attached to the transcoder */
971 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
972 u32 pch_dpll;
973
974 pch_dpll = I915_READ(PCH_DPLL_SEL);
975 cur_state = pll->pll_reg == _PCH_DPLL_B;
976 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
977 "PLL[%d] not attached to this transcoder %c: %08x\n",
978 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
979 cur_state = !!(val >> (4*crtc->pipe + 3));
980 WARN(cur_state != state,
981 "PLL[%d] not %s on this transcoder %c: %08x\n",
982 pll->pll_reg == _PCH_DPLL_B,
983 state_string(state),
984 pipe_name(crtc->pipe),
985 val);
986 }
987 }
988 }
989 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
990 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
991
992 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994 {
995 int reg;
996 u32 val;
997 bool cur_state;
998 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
999 pipe);
1000
1001 if (HAS_DDI(dev_priv->dev)) {
1002 /* DDI does not have a specific FDI_TX register */
1003 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1004 val = I915_READ(reg);
1005 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1006 } else {
1007 reg = FDI_TX_CTL(pipe);
1008 val = I915_READ(reg);
1009 cur_state = !!(val & FDI_TX_ENABLE);
1010 }
1011 WARN(cur_state != state,
1012 "FDI TX state assertion failure (expected %s, current %s)\n",
1013 state_string(state), state_string(cur_state));
1014 }
1015 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1016 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1017
1018 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1019 enum pipe pipe, bool state)
1020 {
1021 int reg;
1022 u32 val;
1023 bool cur_state;
1024
1025 reg = FDI_RX_CTL(pipe);
1026 val = I915_READ(reg);
1027 cur_state = !!(val & FDI_RX_ENABLE);
1028 WARN(cur_state != state,
1029 "FDI RX state assertion failure (expected %s, current %s)\n",
1030 state_string(state), state_string(cur_state));
1031 }
1032 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1033 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1034
1035 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1036 enum pipe pipe)
1037 {
1038 int reg;
1039 u32 val;
1040
1041 /* ILK FDI PLL is always enabled */
1042 if (dev_priv->info->gen == 5)
1043 return;
1044
1045 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1046 if (HAS_DDI(dev_priv->dev))
1047 return;
1048
1049 reg = FDI_TX_CTL(pipe);
1050 val = I915_READ(reg);
1051 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1052 }
1053
1054 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056 {
1057 int reg;
1058 u32 val;
1059
1060 reg = FDI_RX_CTL(pipe);
1061 val = I915_READ(reg);
1062 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1063 }
1064
1065 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1066 enum pipe pipe)
1067 {
1068 int pp_reg, lvds_reg;
1069 u32 val;
1070 enum pipe panel_pipe = PIPE_A;
1071 bool locked = true;
1072
1073 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1074 pp_reg = PCH_PP_CONTROL;
1075 lvds_reg = PCH_LVDS;
1076 } else {
1077 pp_reg = PP_CONTROL;
1078 lvds_reg = LVDS;
1079 }
1080
1081 val = I915_READ(pp_reg);
1082 if (!(val & PANEL_POWER_ON) ||
1083 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1084 locked = false;
1085
1086 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1087 panel_pipe = PIPE_B;
1088
1089 WARN(panel_pipe == pipe && locked,
1090 "panel assertion failure, pipe %c regs locked\n",
1091 pipe_name(pipe));
1092 }
1093
1094 void assert_pipe(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1096 {
1097 int reg;
1098 u32 val;
1099 bool cur_state;
1100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1101 pipe);
1102
1103 /* if we need the pipe A quirk it must be always on */
1104 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1105 state = true;
1106
1107 if (!intel_display_power_enabled(dev_priv->dev,
1108 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1109 cur_state = false;
1110 } else {
1111 reg = PIPECONF(cpu_transcoder);
1112 val = I915_READ(reg);
1113 cur_state = !!(val & PIPECONF_ENABLE);
1114 }
1115
1116 WARN(cur_state != state,
1117 "pipe %c assertion failure (expected %s, current %s)\n",
1118 pipe_name(pipe), state_string(state), state_string(cur_state));
1119 }
1120
1121 static void assert_plane(struct drm_i915_private *dev_priv,
1122 enum plane plane, bool state)
1123 {
1124 int reg;
1125 u32 val;
1126 bool cur_state;
1127
1128 reg = DSPCNTR(plane);
1129 val = I915_READ(reg);
1130 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1131 WARN(cur_state != state,
1132 "plane %c assertion failure (expected %s, current %s)\n",
1133 plane_name(plane), state_string(state), state_string(cur_state));
1134 }
1135
1136 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1137 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1138
1139 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1140 enum pipe pipe)
1141 {
1142 int reg, i;
1143 u32 val;
1144 int cur_pipe;
1145
1146 /* Planes are fixed to pipes on ILK+ */
1147 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1148 reg = DSPCNTR(pipe);
1149 val = I915_READ(reg);
1150 WARN((val & DISPLAY_PLANE_ENABLE),
1151 "plane %c assertion failure, should be disabled but not\n",
1152 plane_name(pipe));
1153 return;
1154 }
1155
1156 /* Need to check both planes against the pipe */
1157 for (i = 0; i < 2; i++) {
1158 reg = DSPCNTR(i);
1159 val = I915_READ(reg);
1160 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1161 DISPPLANE_SEL_PIPE_SHIFT;
1162 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1163 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1164 plane_name(i), pipe_name(pipe));
1165 }
1166 }
1167
1168 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1169 enum pipe pipe)
1170 {
1171 int reg, i;
1172 u32 val;
1173
1174 if (!IS_VALLEYVIEW(dev_priv->dev))
1175 return;
1176
1177 /* Need to check both planes against the pipe */
1178 for (i = 0; i < dev_priv->num_plane; i++) {
1179 reg = SPCNTR(pipe, i);
1180 val = I915_READ(reg);
1181 WARN((val & SP_ENABLE),
1182 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1183 sprite_name(pipe, i), pipe_name(pipe));
1184 }
1185 }
1186
1187 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1188 {
1189 u32 val;
1190 bool enabled;
1191
1192 if (HAS_PCH_LPT(dev_priv->dev)) {
1193 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1194 return;
1195 }
1196
1197 val = I915_READ(PCH_DREF_CONTROL);
1198 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1199 DREF_SUPERSPREAD_SOURCE_MASK));
1200 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205 {
1206 int reg;
1207 u32 val;
1208 bool enabled;
1209
1210 reg = PCH_TRANSCONF(pipe);
1211 val = I915_READ(reg);
1212 enabled = !!(val & TRANS_ENABLE);
1213 WARN(enabled,
1214 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1215 pipe_name(pipe));
1216 }
1217
1218 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, u32 port_sel, u32 val)
1220 {
1221 if ((val & DP_PORT_EN) == 0)
1222 return false;
1223
1224 if (HAS_PCH_CPT(dev_priv->dev)) {
1225 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1226 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1227 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1228 return false;
1229 } else {
1230 if ((val & DP_PIPE_MASK) != (pipe << 30))
1231 return false;
1232 }
1233 return true;
1234 }
1235
1236 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238 {
1239 if ((val & SDVO_ENABLE) == 0)
1240 return false;
1241
1242 if (HAS_PCH_CPT(dev_priv->dev)) {
1243 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1244 return false;
1245 } else {
1246 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1247 return false;
1248 }
1249 return true;
1250 }
1251
1252 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, u32 val)
1254 {
1255 if ((val & LVDS_PORT_EN) == 0)
1256 return false;
1257
1258 if (HAS_PCH_CPT(dev_priv->dev)) {
1259 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1260 return false;
1261 } else {
1262 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1263 return false;
1264 }
1265 return true;
1266 }
1267
1268 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1269 enum pipe pipe, u32 val)
1270 {
1271 if ((val & ADPA_DAC_ENABLE) == 0)
1272 return false;
1273 if (HAS_PCH_CPT(dev_priv->dev)) {
1274 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1275 return false;
1276 } else {
1277 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1278 return false;
1279 }
1280 return true;
1281 }
1282
1283 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1284 enum pipe pipe, int reg, u32 port_sel)
1285 {
1286 u32 val = I915_READ(reg);
1287 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1288 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1289 reg, pipe_name(pipe));
1290
1291 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1292 && (val & DP_PIPEB_SELECT),
1293 "IBX PCH dp port still using transcoder B\n");
1294 }
1295
1296 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, int reg)
1298 {
1299 u32 val = I915_READ(reg);
1300 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1301 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1302 reg, pipe_name(pipe));
1303
1304 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1305 && (val & SDVO_PIPE_B_SELECT),
1306 "IBX PCH hdmi port still using transcoder B\n");
1307 }
1308
1309 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311 {
1312 int reg;
1313 u32 val;
1314
1315 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1316 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1317 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1318
1319 reg = PCH_ADPA;
1320 val = I915_READ(reg);
1321 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1322 "PCH VGA enabled on transcoder %c, should be disabled\n",
1323 pipe_name(pipe));
1324
1325 reg = PCH_LVDS;
1326 val = I915_READ(reg);
1327 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1328 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1329 pipe_name(pipe));
1330
1331 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1332 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1333 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1334 }
1335
1336 /**
1337 * intel_enable_pll - enable a PLL
1338 * @dev_priv: i915 private structure
1339 * @pipe: pipe PLL to enable
1340 *
1341 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1342 * make sure the PLL reg is writable first though, since the panel write
1343 * protect mechanism may be enabled.
1344 *
1345 * Note! This is for pre-ILK only.
1346 *
1347 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1348 */
1349 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1350 {
1351 int reg;
1352 u32 val;
1353
1354 assert_pipe_disabled(dev_priv, pipe);
1355
1356 /* No really, not for ILK+ */
1357 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1358
1359 /* PLL is protected by panel, make sure we can write it */
1360 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1361 assert_panel_unlocked(dev_priv, pipe);
1362
1363 reg = DPLL(pipe);
1364 val = I915_READ(reg);
1365 val |= DPLL_VCO_ENABLE;
1366
1367 /* We do this three times for luck */
1368 I915_WRITE(reg, val);
1369 POSTING_READ(reg);
1370 udelay(150); /* wait for warmup */
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373 udelay(150); /* wait for warmup */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 }
1378
1379 /**
1380 * intel_disable_pll - disable a PLL
1381 * @dev_priv: i915 private structure
1382 * @pipe: pipe PLL to disable
1383 *
1384 * Disable the PLL for @pipe, making sure the pipe is off first.
1385 *
1386 * Note! This is for pre-ILK only.
1387 */
1388 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1389 {
1390 int reg;
1391 u32 val;
1392
1393 /* Don't disable pipe A or pipe A PLLs if needed */
1394 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1395 return;
1396
1397 /* Make sure the pipe isn't still relying on us */
1398 assert_pipe_disabled(dev_priv, pipe);
1399
1400 reg = DPLL(pipe);
1401 val = I915_READ(reg);
1402 val &= ~DPLL_VCO_ENABLE;
1403 I915_WRITE(reg, val);
1404 POSTING_READ(reg);
1405 }
1406
1407 /* SBI access */
1408 static void
1409 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1410 enum intel_sbi_destination destination)
1411 {
1412 u32 tmp;
1413
1414 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1415
1416 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1417 100)) {
1418 DRM_ERROR("timeout waiting for SBI to become ready\n");
1419 return;
1420 }
1421
1422 I915_WRITE(SBI_ADDR, (reg << 16));
1423 I915_WRITE(SBI_DATA, value);
1424
1425 if (destination == SBI_ICLK)
1426 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1427 else
1428 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1429 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1430
1431 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1432 100)) {
1433 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1434 return;
1435 }
1436 }
1437
1438 static u32
1439 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1440 enum intel_sbi_destination destination)
1441 {
1442 u32 value = 0;
1443 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1444
1445 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1446 100)) {
1447 DRM_ERROR("timeout waiting for SBI to become ready\n");
1448 return 0;
1449 }
1450
1451 I915_WRITE(SBI_ADDR, (reg << 16));
1452
1453 if (destination == SBI_ICLK)
1454 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1455 else
1456 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1457 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1458
1459 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1460 100)) {
1461 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1462 return 0;
1463 }
1464
1465 return I915_READ(SBI_DATA);
1466 }
1467
1468 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1469 {
1470 u32 port_mask;
1471
1472 if (!port)
1473 port_mask = DPLL_PORTB_READY_MASK;
1474 else
1475 port_mask = DPLL_PORTC_READY_MASK;
1476
1477 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1478 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1479 'B' + port, I915_READ(DPLL(0)));
1480 }
1481
1482 /**
1483 * ironlake_enable_pch_pll - enable PCH PLL
1484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to enable
1486 *
1487 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1488 * drives the transcoder clock.
1489 */
1490 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1491 {
1492 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1493 struct intel_pch_pll *pll;
1494 int reg;
1495 u32 val;
1496
1497 /* PCH PLLs only available on ILK, SNB and IVB */
1498 BUG_ON(dev_priv->info->gen < 5);
1499 pll = intel_crtc->pch_pll;
1500 if (pll == NULL)
1501 return;
1502
1503 if (WARN_ON(pll->refcount == 0))
1504 return;
1505
1506 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1507 pll->pll_reg, pll->active, pll->on,
1508 intel_crtc->base.base.id);
1509
1510 /* PCH refclock must be enabled first */
1511 assert_pch_refclk_enabled(dev_priv);
1512
1513 if (pll->active++ && pll->on) {
1514 assert_pch_pll_enabled(dev_priv, pll, NULL);
1515 return;
1516 }
1517
1518 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1519
1520 reg = pll->pll_reg;
1521 val = I915_READ(reg);
1522 val |= DPLL_VCO_ENABLE;
1523 I915_WRITE(reg, val);
1524 POSTING_READ(reg);
1525 udelay(200);
1526
1527 pll->on = true;
1528 }
1529
1530 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1531 {
1532 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1533 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1534 int reg;
1535 u32 val;
1536
1537 /* PCH only available on ILK+ */
1538 BUG_ON(dev_priv->info->gen < 5);
1539 if (pll == NULL)
1540 return;
1541
1542 if (WARN_ON(pll->refcount == 0))
1543 return;
1544
1545 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1546 pll->pll_reg, pll->active, pll->on,
1547 intel_crtc->base.base.id);
1548
1549 if (WARN_ON(pll->active == 0)) {
1550 assert_pch_pll_disabled(dev_priv, pll, NULL);
1551 return;
1552 }
1553
1554 if (--pll->active) {
1555 assert_pch_pll_enabled(dev_priv, pll, NULL);
1556 return;
1557 }
1558
1559 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1560
1561 /* Make sure transcoder isn't still depending on us */
1562 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1563
1564 reg = pll->pll_reg;
1565 val = I915_READ(reg);
1566 val &= ~DPLL_VCO_ENABLE;
1567 I915_WRITE(reg, val);
1568 POSTING_READ(reg);
1569 udelay(200);
1570
1571 pll->on = false;
1572 }
1573
1574 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1575 enum pipe pipe)
1576 {
1577 struct drm_device *dev = dev_priv->dev;
1578 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1579 uint32_t reg, val, pipeconf_val;
1580
1581 /* PCH only available on ILK+ */
1582 BUG_ON(dev_priv->info->gen < 5);
1583
1584 /* Make sure PCH DPLL is enabled */
1585 assert_pch_pll_enabled(dev_priv,
1586 to_intel_crtc(crtc)->pch_pll,
1587 to_intel_crtc(crtc));
1588
1589 /* FDI must be feeding us bits for PCH ports */
1590 assert_fdi_tx_enabled(dev_priv, pipe);
1591 assert_fdi_rx_enabled(dev_priv, pipe);
1592
1593 if (HAS_PCH_CPT(dev)) {
1594 /* Workaround: Set the timing override bit before enabling the
1595 * pch transcoder. */
1596 reg = TRANS_CHICKEN2(pipe);
1597 val = I915_READ(reg);
1598 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1599 I915_WRITE(reg, val);
1600 }
1601
1602 reg = PCH_TRANSCONF(pipe);
1603 val = I915_READ(reg);
1604 pipeconf_val = I915_READ(PIPECONF(pipe));
1605
1606 if (HAS_PCH_IBX(dev_priv->dev)) {
1607 /*
1608 * make the BPC in transcoder be consistent with
1609 * that in pipeconf reg.
1610 */
1611 val &= ~PIPECONF_BPC_MASK;
1612 val |= pipeconf_val & PIPECONF_BPC_MASK;
1613 }
1614
1615 val &= ~TRANS_INTERLACE_MASK;
1616 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1617 if (HAS_PCH_IBX(dev_priv->dev) &&
1618 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1619 val |= TRANS_LEGACY_INTERLACED_ILK;
1620 else
1621 val |= TRANS_INTERLACED;
1622 else
1623 val |= TRANS_PROGRESSIVE;
1624
1625 I915_WRITE(reg, val | TRANS_ENABLE);
1626 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1627 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1628 }
1629
1630 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1631 enum transcoder cpu_transcoder)
1632 {
1633 u32 val, pipeconf_val;
1634
1635 /* PCH only available on ILK+ */
1636 BUG_ON(dev_priv->info->gen < 5);
1637
1638 /* FDI must be feeding us bits for PCH ports */
1639 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1640 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1641
1642 /* Workaround: set timing override bit. */
1643 val = I915_READ(_TRANSA_CHICKEN2);
1644 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1645 I915_WRITE(_TRANSA_CHICKEN2, val);
1646
1647 val = TRANS_ENABLE;
1648 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1649
1650 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1651 PIPECONF_INTERLACED_ILK)
1652 val |= TRANS_INTERLACED;
1653 else
1654 val |= TRANS_PROGRESSIVE;
1655
1656 I915_WRITE(LPT_TRANSCONF, val);
1657 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1658 DRM_ERROR("Failed to enable PCH transcoder\n");
1659 }
1660
1661 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
1663 {
1664 struct drm_device *dev = dev_priv->dev;
1665 uint32_t reg, val;
1666
1667 /* FDI relies on the transcoder */
1668 assert_fdi_tx_disabled(dev_priv, pipe);
1669 assert_fdi_rx_disabled(dev_priv, pipe);
1670
1671 /* Ports must be off as well */
1672 assert_pch_ports_disabled(dev_priv, pipe);
1673
1674 reg = PCH_TRANSCONF(pipe);
1675 val = I915_READ(reg);
1676 val &= ~TRANS_ENABLE;
1677 I915_WRITE(reg, val);
1678 /* wait for PCH transcoder off, transcoder state */
1679 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1680 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1681
1682 if (!HAS_PCH_IBX(dev)) {
1683 /* Workaround: Clear the timing override chicken bit again. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
1688 }
1689 }
1690
1691 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1692 {
1693 u32 val;
1694
1695 val = I915_READ(LPT_TRANSCONF);
1696 val &= ~TRANS_ENABLE;
1697 I915_WRITE(LPT_TRANSCONF, val);
1698 /* wait for PCH transcoder off, transcoder state */
1699 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1700 DRM_ERROR("Failed to disable PCH transcoder\n");
1701
1702 /* Workaround: clear timing override bit. */
1703 val = I915_READ(_TRANSA_CHICKEN2);
1704 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1705 I915_WRITE(_TRANSA_CHICKEN2, val);
1706 }
1707
1708 /**
1709 * intel_enable_pipe - enable a pipe, asserting requirements
1710 * @dev_priv: i915 private structure
1711 * @pipe: pipe to enable
1712 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1713 *
1714 * Enable @pipe, making sure that various hardware specific requirements
1715 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1716 *
1717 * @pipe should be %PIPE_A or %PIPE_B.
1718 *
1719 * Will wait until the pipe is actually running (i.e. first vblank) before
1720 * returning.
1721 */
1722 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1723 bool pch_port)
1724 {
1725 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1726 pipe);
1727 enum pipe pch_transcoder;
1728 int reg;
1729 u32 val;
1730
1731 assert_planes_disabled(dev_priv, pipe);
1732 assert_sprites_disabled(dev_priv, pipe);
1733
1734 if (HAS_PCH_LPT(dev_priv->dev))
1735 pch_transcoder = TRANSCODER_A;
1736 else
1737 pch_transcoder = pipe;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1750 assert_fdi_tx_pll_enabled(dev_priv,
1751 (enum pipe) cpu_transcoder);
1752 }
1753 /* FIXME: assert CPU port conditions for SNB+ */
1754 }
1755
1756 reg = PIPECONF(cpu_transcoder);
1757 val = I915_READ(reg);
1758 if (val & PIPECONF_ENABLE)
1759 return;
1760
1761 I915_WRITE(reg, val | PIPECONF_ENABLE);
1762 intel_wait_for_vblank(dev_priv->dev, pipe);
1763 }
1764
1765 /**
1766 * intel_disable_pipe - disable a pipe, asserting requirements
1767 * @dev_priv: i915 private structure
1768 * @pipe: pipe to disable
1769 *
1770 * Disable @pipe, making sure that various hardware specific requirements
1771 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1772 *
1773 * @pipe should be %PIPE_A or %PIPE_B.
1774 *
1775 * Will wait until the pipe has shut down before returning.
1776 */
1777 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1778 enum pipe pipe)
1779 {
1780 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1781 pipe);
1782 int reg;
1783 u32 val;
1784
1785 /*
1786 * Make sure planes won't keep trying to pump pixels to us,
1787 * or we might hang the display.
1788 */
1789 assert_planes_disabled(dev_priv, pipe);
1790 assert_sprites_disabled(dev_priv, pipe);
1791
1792 /* Don't disable pipe A or pipe A PLLs if needed */
1793 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1794 return;
1795
1796 reg = PIPECONF(cpu_transcoder);
1797 val = I915_READ(reg);
1798 if ((val & PIPECONF_ENABLE) == 0)
1799 return;
1800
1801 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1802 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1803 }
1804
1805 /*
1806 * Plane regs are double buffered, going from enabled->disabled needs a
1807 * trigger in order to latch. The display address reg provides this.
1808 */
1809 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1810 enum plane plane)
1811 {
1812 if (dev_priv->info->gen >= 4)
1813 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1814 else
1815 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1816 }
1817
1818 /**
1819 * intel_enable_plane - enable a display plane on a given pipe
1820 * @dev_priv: i915 private structure
1821 * @plane: plane to enable
1822 * @pipe: pipe being fed
1823 *
1824 * Enable @plane on @pipe, making sure that @pipe is running first.
1825 */
1826 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1827 enum plane plane, enum pipe pipe)
1828 {
1829 int reg;
1830 u32 val;
1831
1832 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1833 assert_pipe_enabled(dev_priv, pipe);
1834
1835 reg = DSPCNTR(plane);
1836 val = I915_READ(reg);
1837 if (val & DISPLAY_PLANE_ENABLE)
1838 return;
1839
1840 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1841 intel_flush_display_plane(dev_priv, plane);
1842 intel_wait_for_vblank(dev_priv->dev, pipe);
1843 }
1844
1845 /**
1846 * intel_disable_plane - disable a display plane
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to disable
1849 * @pipe: pipe consuming the data
1850 *
1851 * Disable @plane; should be an independent operation.
1852 */
1853 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1854 enum plane plane, enum pipe pipe)
1855 {
1856 int reg;
1857 u32 val;
1858
1859 reg = DSPCNTR(plane);
1860 val = I915_READ(reg);
1861 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1862 return;
1863
1864 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1865 intel_flush_display_plane(dev_priv, plane);
1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867 }
1868
1869 static bool need_vtd_wa(struct drm_device *dev)
1870 {
1871 #ifdef CONFIG_INTEL_IOMMU
1872 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1873 return true;
1874 #endif
1875 return false;
1876 }
1877
1878 int
1879 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1880 struct drm_i915_gem_object *obj,
1881 struct intel_ring_buffer *pipelined)
1882 {
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 u32 alignment;
1885 int ret;
1886
1887 switch (obj->tiling_mode) {
1888 case I915_TILING_NONE:
1889 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1890 alignment = 128 * 1024;
1891 else if (INTEL_INFO(dev)->gen >= 4)
1892 alignment = 4 * 1024;
1893 else
1894 alignment = 64 * 1024;
1895 break;
1896 case I915_TILING_X:
1897 /* pin() will align the object as required by fence */
1898 alignment = 0;
1899 break;
1900 case I915_TILING_Y:
1901 /* Despite that we check this in framebuffer_init userspace can
1902 * screw us over and change the tiling after the fact. Only
1903 * pinned buffers can't change their tiling. */
1904 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1905 return -EINVAL;
1906 default:
1907 BUG();
1908 }
1909
1910 /* Note that the w/a also requires 64 PTE of padding following the
1911 * bo. We currently fill all unused PTE with the shadow page and so
1912 * we should always have valid PTE following the scanout preventing
1913 * the VT-d warning.
1914 */
1915 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1916 alignment = 256 * 1024;
1917
1918 dev_priv->mm.interruptible = false;
1919 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1920 if (ret)
1921 goto err_interruptible;
1922
1923 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1924 * fence, whereas 965+ only requires a fence if using
1925 * framebuffer compression. For simplicity, we always install
1926 * a fence as the cost is not that onerous.
1927 */
1928 ret = i915_gem_object_get_fence(obj);
1929 if (ret)
1930 goto err_unpin;
1931
1932 i915_gem_object_pin_fence(obj);
1933
1934 dev_priv->mm.interruptible = true;
1935 return 0;
1936
1937 err_unpin:
1938 i915_gem_object_unpin(obj);
1939 err_interruptible:
1940 dev_priv->mm.interruptible = true;
1941 return ret;
1942 }
1943
1944 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1945 {
1946 i915_gem_object_unpin_fence(obj);
1947 i915_gem_object_unpin(obj);
1948 }
1949
1950 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1951 * is assumed to be a power-of-two. */
1952 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1953 unsigned int tiling_mode,
1954 unsigned int cpp,
1955 unsigned int pitch)
1956 {
1957 if (tiling_mode != I915_TILING_NONE) {
1958 unsigned int tile_rows, tiles;
1959
1960 tile_rows = *y / 8;
1961 *y %= 8;
1962
1963 tiles = *x / (512/cpp);
1964 *x %= 512/cpp;
1965
1966 return tile_rows * pitch * 8 + tiles * 4096;
1967 } else {
1968 unsigned int offset;
1969
1970 offset = *y * pitch + *x * cpp;
1971 *y = 0;
1972 *x = (offset & 4095) / cpp;
1973 return offset & -4096;
1974 }
1975 }
1976
1977 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1978 int x, int y)
1979 {
1980 struct drm_device *dev = crtc->dev;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 struct intel_framebuffer *intel_fb;
1984 struct drm_i915_gem_object *obj;
1985 int plane = intel_crtc->plane;
1986 unsigned long linear_offset;
1987 u32 dspcntr;
1988 u32 reg;
1989
1990 switch (plane) {
1991 case 0:
1992 case 1:
1993 break;
1994 default:
1995 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1996 return -EINVAL;
1997 }
1998
1999 intel_fb = to_intel_framebuffer(fb);
2000 obj = intel_fb->obj;
2001
2002 reg = DSPCNTR(plane);
2003 dspcntr = I915_READ(reg);
2004 /* Mask out pixel format bits in case we change it */
2005 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2006 switch (fb->pixel_format) {
2007 case DRM_FORMAT_C8:
2008 dspcntr |= DISPPLANE_8BPP;
2009 break;
2010 case DRM_FORMAT_XRGB1555:
2011 case DRM_FORMAT_ARGB1555:
2012 dspcntr |= DISPPLANE_BGRX555;
2013 break;
2014 case DRM_FORMAT_RGB565:
2015 dspcntr |= DISPPLANE_BGRX565;
2016 break;
2017 case DRM_FORMAT_XRGB8888:
2018 case DRM_FORMAT_ARGB8888:
2019 dspcntr |= DISPPLANE_BGRX888;
2020 break;
2021 case DRM_FORMAT_XBGR8888:
2022 case DRM_FORMAT_ABGR8888:
2023 dspcntr |= DISPPLANE_RGBX888;
2024 break;
2025 case DRM_FORMAT_XRGB2101010:
2026 case DRM_FORMAT_ARGB2101010:
2027 dspcntr |= DISPPLANE_BGRX101010;
2028 break;
2029 case DRM_FORMAT_XBGR2101010:
2030 case DRM_FORMAT_ABGR2101010:
2031 dspcntr |= DISPPLANE_RGBX101010;
2032 break;
2033 default:
2034 BUG();
2035 }
2036
2037 if (INTEL_INFO(dev)->gen >= 4) {
2038 if (obj->tiling_mode != I915_TILING_NONE)
2039 dspcntr |= DISPPLANE_TILED;
2040 else
2041 dspcntr &= ~DISPPLANE_TILED;
2042 }
2043
2044 I915_WRITE(reg, dspcntr);
2045
2046 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2047
2048 if (INTEL_INFO(dev)->gen >= 4) {
2049 intel_crtc->dspaddr_offset =
2050 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2051 fb->bits_per_pixel / 8,
2052 fb->pitches[0]);
2053 linear_offset -= intel_crtc->dspaddr_offset;
2054 } else {
2055 intel_crtc->dspaddr_offset = linear_offset;
2056 }
2057
2058 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2059 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2060 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2061 if (INTEL_INFO(dev)->gen >= 4) {
2062 I915_MODIFY_DISPBASE(DSPSURF(plane),
2063 obj->gtt_offset + intel_crtc->dspaddr_offset);
2064 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2065 I915_WRITE(DSPLINOFF(plane), linear_offset);
2066 } else
2067 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2068 POSTING_READ(reg);
2069
2070 return 0;
2071 }
2072
2073 static int ironlake_update_plane(struct drm_crtc *crtc,
2074 struct drm_framebuffer *fb, int x, int y)
2075 {
2076 struct drm_device *dev = crtc->dev;
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 struct intel_framebuffer *intel_fb;
2080 struct drm_i915_gem_object *obj;
2081 int plane = intel_crtc->plane;
2082 unsigned long linear_offset;
2083 u32 dspcntr;
2084 u32 reg;
2085
2086 switch (plane) {
2087 case 0:
2088 case 1:
2089 case 2:
2090 break;
2091 default:
2092 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2093 return -EINVAL;
2094 }
2095
2096 intel_fb = to_intel_framebuffer(fb);
2097 obj = intel_fb->obj;
2098
2099 reg = DSPCNTR(plane);
2100 dspcntr = I915_READ(reg);
2101 /* Mask out pixel format bits in case we change it */
2102 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2103 switch (fb->pixel_format) {
2104 case DRM_FORMAT_C8:
2105 dspcntr |= DISPPLANE_8BPP;
2106 break;
2107 case DRM_FORMAT_RGB565:
2108 dspcntr |= DISPPLANE_BGRX565;
2109 break;
2110 case DRM_FORMAT_XRGB8888:
2111 case DRM_FORMAT_ARGB8888:
2112 dspcntr |= DISPPLANE_BGRX888;
2113 break;
2114 case DRM_FORMAT_XBGR8888:
2115 case DRM_FORMAT_ABGR8888:
2116 dspcntr |= DISPPLANE_RGBX888;
2117 break;
2118 case DRM_FORMAT_XRGB2101010:
2119 case DRM_FORMAT_ARGB2101010:
2120 dspcntr |= DISPPLANE_BGRX101010;
2121 break;
2122 case DRM_FORMAT_XBGR2101010:
2123 case DRM_FORMAT_ABGR2101010:
2124 dspcntr |= DISPPLANE_RGBX101010;
2125 break;
2126 default:
2127 BUG();
2128 }
2129
2130 if (obj->tiling_mode != I915_TILING_NONE)
2131 dspcntr |= DISPPLANE_TILED;
2132 else
2133 dspcntr &= ~DISPPLANE_TILED;
2134
2135 /* must disable */
2136 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2137
2138 I915_WRITE(reg, dspcntr);
2139
2140 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2141 intel_crtc->dspaddr_offset =
2142 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2143 fb->bits_per_pixel / 8,
2144 fb->pitches[0]);
2145 linear_offset -= intel_crtc->dspaddr_offset;
2146
2147 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2148 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2149 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2150 I915_MODIFY_DISPBASE(DSPSURF(plane),
2151 obj->gtt_offset + intel_crtc->dspaddr_offset);
2152 if (IS_HASWELL(dev)) {
2153 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2154 } else {
2155 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2156 I915_WRITE(DSPLINOFF(plane), linear_offset);
2157 }
2158 POSTING_READ(reg);
2159
2160 return 0;
2161 }
2162
2163 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2164 static int
2165 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2166 int x, int y, enum mode_set_atomic state)
2167 {
2168 struct drm_device *dev = crtc->dev;
2169 struct drm_i915_private *dev_priv = dev->dev_private;
2170
2171 if (dev_priv->display.disable_fbc)
2172 dev_priv->display.disable_fbc(dev);
2173 intel_increase_pllclock(crtc);
2174
2175 return dev_priv->display.update_plane(crtc, fb, x, y);
2176 }
2177
2178 void intel_display_handle_reset(struct drm_device *dev)
2179 {
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct drm_crtc *crtc;
2182
2183 /*
2184 * Flips in the rings have been nuked by the reset,
2185 * so complete all pending flips so that user space
2186 * will get its events and not get stuck.
2187 *
2188 * Also update the base address of all primary
2189 * planes to the the last fb to make sure we're
2190 * showing the correct fb after a reset.
2191 *
2192 * Need to make two loops over the crtcs so that we
2193 * don't try to grab a crtc mutex before the
2194 * pending_flip_queue really got woken up.
2195 */
2196
2197 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199 enum plane plane = intel_crtc->plane;
2200
2201 intel_prepare_page_flip(dev, plane);
2202 intel_finish_page_flip_plane(dev, plane);
2203 }
2204
2205 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2207
2208 mutex_lock(&crtc->mutex);
2209 if (intel_crtc->active)
2210 dev_priv->display.update_plane(crtc, crtc->fb,
2211 crtc->x, crtc->y);
2212 mutex_unlock(&crtc->mutex);
2213 }
2214 }
2215
2216 static int
2217 intel_finish_fb(struct drm_framebuffer *old_fb)
2218 {
2219 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2220 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2221 bool was_interruptible = dev_priv->mm.interruptible;
2222 int ret;
2223
2224 /* Big Hammer, we also need to ensure that any pending
2225 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2226 * current scanout is retired before unpinning the old
2227 * framebuffer.
2228 *
2229 * This should only fail upon a hung GPU, in which case we
2230 * can safely continue.
2231 */
2232 dev_priv->mm.interruptible = false;
2233 ret = i915_gem_object_finish_gpu(obj);
2234 dev_priv->mm.interruptible = was_interruptible;
2235
2236 return ret;
2237 }
2238
2239 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2240 {
2241 struct drm_device *dev = crtc->dev;
2242 struct drm_i915_master_private *master_priv;
2243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244
2245 if (!dev->primary->master)
2246 return;
2247
2248 master_priv = dev->primary->master->driver_priv;
2249 if (!master_priv->sarea_priv)
2250 return;
2251
2252 switch (intel_crtc->pipe) {
2253 case 0:
2254 master_priv->sarea_priv->pipeA_x = x;
2255 master_priv->sarea_priv->pipeA_y = y;
2256 break;
2257 case 1:
2258 master_priv->sarea_priv->pipeB_x = x;
2259 master_priv->sarea_priv->pipeB_y = y;
2260 break;
2261 default:
2262 break;
2263 }
2264 }
2265
2266 static int
2267 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2268 struct drm_framebuffer *fb)
2269 {
2270 struct drm_device *dev = crtc->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2273 struct drm_framebuffer *old_fb;
2274 int ret;
2275
2276 /* no fb bound */
2277 if (!fb) {
2278 DRM_ERROR("No FB bound\n");
2279 return 0;
2280 }
2281
2282 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2283 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2284 plane_name(intel_crtc->plane),
2285 INTEL_INFO(dev)->num_pipes);
2286 return -EINVAL;
2287 }
2288
2289 mutex_lock(&dev->struct_mutex);
2290 ret = intel_pin_and_fence_fb_obj(dev,
2291 to_intel_framebuffer(fb)->obj,
2292 NULL);
2293 if (ret != 0) {
2294 mutex_unlock(&dev->struct_mutex);
2295 DRM_ERROR("pin & fence failed\n");
2296 return ret;
2297 }
2298
2299 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2300 if (ret) {
2301 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2302 mutex_unlock(&dev->struct_mutex);
2303 DRM_ERROR("failed to update base address\n");
2304 return ret;
2305 }
2306
2307 old_fb = crtc->fb;
2308 crtc->fb = fb;
2309 crtc->x = x;
2310 crtc->y = y;
2311
2312 if (old_fb) {
2313 intel_wait_for_vblank(dev, intel_crtc->pipe);
2314 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2315 }
2316
2317 intel_update_fbc(dev);
2318 mutex_unlock(&dev->struct_mutex);
2319
2320 intel_crtc_update_sarea_pos(crtc, x, y);
2321
2322 return 0;
2323 }
2324
2325 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2326 {
2327 struct drm_device *dev = crtc->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2330 int pipe = intel_crtc->pipe;
2331 u32 reg, temp;
2332
2333 /* enable normal train */
2334 reg = FDI_TX_CTL(pipe);
2335 temp = I915_READ(reg);
2336 if (IS_IVYBRIDGE(dev)) {
2337 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2338 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2339 } else {
2340 temp &= ~FDI_LINK_TRAIN_NONE;
2341 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2342 }
2343 I915_WRITE(reg, temp);
2344
2345 reg = FDI_RX_CTL(pipe);
2346 temp = I915_READ(reg);
2347 if (HAS_PCH_CPT(dev)) {
2348 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2350 } else {
2351 temp &= ~FDI_LINK_TRAIN_NONE;
2352 temp |= FDI_LINK_TRAIN_NONE;
2353 }
2354 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2355
2356 /* wait one idle pattern time */
2357 POSTING_READ(reg);
2358 udelay(1000);
2359
2360 /* IVB wants error correction enabled */
2361 if (IS_IVYBRIDGE(dev))
2362 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2363 FDI_FE_ERRC_ENABLE);
2364 }
2365
2366 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2367 {
2368 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2369 }
2370
2371 static void ivb_modeset_global_resources(struct drm_device *dev)
2372 {
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct intel_crtc *pipe_B_crtc =
2375 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2376 struct intel_crtc *pipe_C_crtc =
2377 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2378 uint32_t temp;
2379
2380 /*
2381 * When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. Note that we don't care about enabled pipes without
2383 * an enabled pch encoder.
2384 */
2385 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2386 !pipe_has_enabled_pch(pipe_C_crtc)) {
2387 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2389
2390 temp = I915_READ(SOUTH_CHICKEN1);
2391 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393 I915_WRITE(SOUTH_CHICKEN1, temp);
2394 }
2395 }
2396
2397 /* The FDI link training functions for ILK/Ibexpeak. */
2398 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2399 {
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
2404 int plane = intel_crtc->plane;
2405 u32 reg, temp, tries;
2406
2407 /* FDI needs bits from pipe & plane first */
2408 assert_pipe_enabled(dev_priv, pipe);
2409 assert_plane_enabled(dev_priv, plane);
2410
2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412 for train result */
2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
2417 I915_WRITE(reg, temp);
2418 I915_READ(reg);
2419 udelay(150);
2420
2421 /* enable CPU FDI TX and PCH FDI RX */
2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2425 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1;
2428 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2429
2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2435
2436 POSTING_READ(reg);
2437 udelay(150);
2438
2439 /* Ironlake workaround, enable clock pointer after FDI enable*/
2440 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442 FDI_RX_PHASE_SYNC_POINTER_EN);
2443
2444 reg = FDI_RX_IIR(pipe);
2445 for (tries = 0; tries < 5; tries++) {
2446 temp = I915_READ(reg);
2447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2448
2449 if ((temp & FDI_RX_BIT_LOCK)) {
2450 DRM_DEBUG_KMS("FDI train 1 done.\n");
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452 break;
2453 }
2454 }
2455 if (tries == 5)
2456 DRM_ERROR("FDI train 1 fail!\n");
2457
2458 /* Train 2 */
2459 reg = FDI_TX_CTL(pipe);
2460 temp = I915_READ(reg);
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_2;
2463 I915_WRITE(reg, temp);
2464
2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 I915_WRITE(reg, temp);
2470
2471 POSTING_READ(reg);
2472 udelay(150);
2473
2474 reg = FDI_RX_IIR(pipe);
2475 for (tries = 0; tries < 5; tries++) {
2476 temp = I915_READ(reg);
2477 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2478
2479 if (temp & FDI_RX_SYMBOL_LOCK) {
2480 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2481 DRM_DEBUG_KMS("FDI train 2 done.\n");
2482 break;
2483 }
2484 }
2485 if (tries == 5)
2486 DRM_ERROR("FDI train 2 fail!\n");
2487
2488 DRM_DEBUG_KMS("FDI train done\n");
2489
2490 }
2491
2492 static const int snb_b_fdi_train_param[] = {
2493 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2497 };
2498
2499 /* The FDI link training functions for SNB/Cougarpoint. */
2500 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2501 {
2502 struct drm_device *dev = crtc->dev;
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505 int pipe = intel_crtc->pipe;
2506 u32 reg, temp, i, retry;
2507
2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509 for train result */
2510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
2512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
2517 udelay(150);
2518
2519 /* enable CPU FDI TX and PCH FDI RX */
2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
2522 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2523 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_1;
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 /* SNB-B */
2528 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2530
2531 I915_WRITE(FDI_RX_MISC(pipe),
2532 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2533
2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2539 } else {
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1;
2542 }
2543 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2544
2545 POSTING_READ(reg);
2546 udelay(150);
2547
2548 for (i = 0; i < 4; i++) {
2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
2553 I915_WRITE(reg, temp);
2554
2555 POSTING_READ(reg);
2556 udelay(500);
2557
2558 for (retry = 0; retry < 5; retry++) {
2559 reg = FDI_RX_IIR(pipe);
2560 temp = I915_READ(reg);
2561 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562 if (temp & FDI_RX_BIT_LOCK) {
2563 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564 DRM_DEBUG_KMS("FDI train 1 done.\n");
2565 break;
2566 }
2567 udelay(50);
2568 }
2569 if (retry < 5)
2570 break;
2571 }
2572 if (i == 4)
2573 DRM_ERROR("FDI train 1 fail!\n");
2574
2575 /* Train 2 */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580 if (IS_GEN6(dev)) {
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 /* SNB-B */
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584 }
2585 I915_WRITE(reg, temp);
2586
2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2592 } else {
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_2;
2595 }
2596 I915_WRITE(reg, temp);
2597
2598 POSTING_READ(reg);
2599 udelay(150);
2600
2601 for (i = 0; i < 4; i++) {
2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(500);
2610
2611 for (retry = 0; retry < 5; retry++) {
2612 reg = FDI_RX_IIR(pipe);
2613 temp = I915_READ(reg);
2614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615 if (temp & FDI_RX_SYMBOL_LOCK) {
2616 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617 DRM_DEBUG_KMS("FDI train 2 done.\n");
2618 break;
2619 }
2620 udelay(50);
2621 }
2622 if (retry < 5)
2623 break;
2624 }
2625 if (i == 4)
2626 DRM_ERROR("FDI train 2 fail!\n");
2627
2628 DRM_DEBUG_KMS("FDI train done.\n");
2629 }
2630
2631 /* Manual link training for Ivy Bridge A0 parts */
2632 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2633 {
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
2638 u32 reg, temp, i;
2639
2640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2641 for train result */
2642 reg = FDI_RX_IMR(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_RX_SYMBOL_LOCK;
2645 temp &= ~FDI_RX_BIT_LOCK;
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(150);
2650
2651 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652 I915_READ(FDI_RX_IIR(pipe)));
2653
2654 /* enable CPU FDI TX and PCH FDI RX */
2655 reg = FDI_TX_CTL(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2658 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2659 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2663 temp |= FDI_COMPOSITE_SYNC;
2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2665
2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2668
2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2674 temp |= FDI_COMPOSITE_SYNC;
2675 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2676
2677 POSTING_READ(reg);
2678 udelay(150);
2679
2680 for (i = 0; i < 4; i++) {
2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684 temp |= snb_b_fdi_train_param[i];
2685 I915_WRITE(reg, temp);
2686
2687 POSTING_READ(reg);
2688 udelay(500);
2689
2690 reg = FDI_RX_IIR(pipe);
2691 temp = I915_READ(reg);
2692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693
2694 if (temp & FDI_RX_BIT_LOCK ||
2695 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2697 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2698 break;
2699 }
2700 }
2701 if (i == 4)
2702 DRM_ERROR("FDI train 1 fail!\n");
2703
2704 /* Train 2 */
2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711 I915_WRITE(reg, temp);
2712
2713 reg = FDI_RX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717 I915_WRITE(reg, temp);
2718
2719 POSTING_READ(reg);
2720 udelay(150);
2721
2722 for (i = 0; i < 4; i++) {
2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= snb_b_fdi_train_param[i];
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(500);
2731
2732 reg = FDI_RX_IIR(pipe);
2733 temp = I915_READ(reg);
2734 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2735
2736 if (temp & FDI_RX_SYMBOL_LOCK) {
2737 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2738 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2739 break;
2740 }
2741 }
2742 if (i == 4)
2743 DRM_ERROR("FDI train 2 fail!\n");
2744
2745 DRM_DEBUG_KMS("FDI train done.\n");
2746 }
2747
2748 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2749 {
2750 struct drm_device *dev = intel_crtc->base.dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 int pipe = intel_crtc->pipe;
2753 u32 reg, temp;
2754
2755
2756 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2760 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2761 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2762 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2763
2764 POSTING_READ(reg);
2765 udelay(200);
2766
2767 /* Switch from Rawclk to PCDclk */
2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp | FDI_PCDCLK);
2770
2771 POSTING_READ(reg);
2772 udelay(200);
2773
2774 /* Enable CPU FDI TX PLL, always on for Ironlake */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2779
2780 POSTING_READ(reg);
2781 udelay(100);
2782 }
2783 }
2784
2785 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2786 {
2787 struct drm_device *dev = intel_crtc->base.dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 int pipe = intel_crtc->pipe;
2790 u32 reg, temp;
2791
2792 /* Switch from PCDclk to Rawclk */
2793 reg = FDI_RX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2796
2797 /* Disable CPU FDI TX PLL */
2798 reg = FDI_TX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2801
2802 POSTING_READ(reg);
2803 udelay(100);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2808
2809 /* Wait for the clocks to turn off. */
2810 POSTING_READ(reg);
2811 udelay(100);
2812 }
2813
2814 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2815 {
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2820 u32 reg, temp;
2821
2822 /* disable CPU FDI tx and PCH FDI rx */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2826 POSTING_READ(reg);
2827
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 temp &= ~(0x7 << 16);
2831 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2832 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2833
2834 POSTING_READ(reg);
2835 udelay(100);
2836
2837 /* Ironlake workaround, disable clock pointer after downing FDI */
2838 if (HAS_PCH_IBX(dev)) {
2839 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2840 }
2841
2842 /* still set train pattern 1 */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 I915_WRITE(reg, temp);
2848
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if (HAS_PCH_CPT(dev)) {
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2854 } else {
2855 temp &= ~FDI_LINK_TRAIN_NONE;
2856 temp |= FDI_LINK_TRAIN_PATTERN_1;
2857 }
2858 /* BPC in FDI rx is consistent with that in PIPECONF */
2859 temp &= ~(0x07 << 16);
2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861 I915_WRITE(reg, temp);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865 }
2866
2867 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2868 {
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2872 unsigned long flags;
2873 bool pending;
2874
2875 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2876 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2877 return false;
2878
2879 spin_lock_irqsave(&dev->event_lock, flags);
2880 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2881 spin_unlock_irqrestore(&dev->event_lock, flags);
2882
2883 return pending;
2884 }
2885
2886 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2887 {
2888 struct drm_device *dev = crtc->dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890
2891 if (crtc->fb == NULL)
2892 return;
2893
2894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2895
2896 wait_event(dev_priv->pending_flip_queue,
2897 !intel_crtc_has_pending_flip(crtc));
2898
2899 mutex_lock(&dev->struct_mutex);
2900 intel_finish_fb(crtc->fb);
2901 mutex_unlock(&dev->struct_mutex);
2902 }
2903
2904 /* Program iCLKIP clock to the desired frequency */
2905 static void lpt_program_iclkip(struct drm_crtc *crtc)
2906 {
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
2912 mutex_lock(&dev_priv->dpio_lock);
2913
2914 /* It is necessary to ungate the pixclk gate prior to programming
2915 * the divisors, and gate it back when it is done.
2916 */
2917 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2918
2919 /* Disable SSCCTL */
2920 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2921 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2922 SBI_SSCCTL_DISABLE,
2923 SBI_ICLK);
2924
2925 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2926 if (crtc->mode.clock == 20000) {
2927 auxdiv = 1;
2928 divsel = 0x41;
2929 phaseinc = 0x20;
2930 } else {
2931 /* The iCLK virtual clock root frequency is in MHz,
2932 * but the crtc->mode.clock in in KHz. To get the divisors,
2933 * it is necessary to divide one by another, so we
2934 * convert the virtual clock precision to KHz here for higher
2935 * precision.
2936 */
2937 u32 iclk_virtual_root_freq = 172800 * 1000;
2938 u32 iclk_pi_range = 64;
2939 u32 desired_divisor, msb_divisor_value, pi_value;
2940
2941 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2942 msb_divisor_value = desired_divisor / iclk_pi_range;
2943 pi_value = desired_divisor % iclk_pi_range;
2944
2945 auxdiv = 0;
2946 divsel = msb_divisor_value - 2;
2947 phaseinc = pi_value;
2948 }
2949
2950 /* This should not happen with any sane values */
2951 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2952 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2953 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2954 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2955
2956 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2957 crtc->mode.clock,
2958 auxdiv,
2959 divsel,
2960 phasedir,
2961 phaseinc);
2962
2963 /* Program SSCDIVINTPHASE6 */
2964 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2965 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2966 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2967 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2968 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2969 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2970 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2971 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2972
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2978
2979 /* Enable modulator and associated divider */
2980 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2981 temp &= ~SBI_SSCCTL_DISABLE;
2982 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2983
2984 /* Wait for initialization time */
2985 udelay(24);
2986
2987 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2988
2989 mutex_unlock(&dev_priv->dpio_lock);
2990 }
2991
2992 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2993 enum pipe pch_transcoder)
2994 {
2995 struct drm_device *dev = crtc->base.dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2998
2999 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3000 I915_READ(HTOTAL(cpu_transcoder)));
3001 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3002 I915_READ(HBLANK(cpu_transcoder)));
3003 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3004 I915_READ(HSYNC(cpu_transcoder)));
3005
3006 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3007 I915_READ(VTOTAL(cpu_transcoder)));
3008 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3009 I915_READ(VBLANK(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3011 I915_READ(VSYNC(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3013 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3014 }
3015
3016 /*
3017 * Enable PCH resources required for PCH ports:
3018 * - PCH PLLs
3019 * - FDI training & RX/TX
3020 * - update transcoder timings
3021 * - DP transcoding bits
3022 * - transcoder
3023 */
3024 static void ironlake_pch_enable(struct drm_crtc *crtc)
3025 {
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 int pipe = intel_crtc->pipe;
3030 u32 reg, temp;
3031
3032 assert_pch_transcoder_disabled(dev_priv, pipe);
3033
3034 /* Write the TU size bits before fdi link training, so that error
3035 * detection works. */
3036 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3037 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3038
3039 /* For PCH output, training FDI link */
3040 dev_priv->display.fdi_link_train(crtc);
3041
3042 /* XXX: pch pll's can be enabled any time before we enable the PCH
3043 * transcoder, and we actually should do this to not upset any PCH
3044 * transcoder that already use the clock when we share it.
3045 *
3046 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3047 * unconditionally resets the pll - we need that to have the right LVDS
3048 * enable sequence. */
3049 ironlake_enable_pch_pll(intel_crtc);
3050
3051 if (HAS_PCH_CPT(dev)) {
3052 u32 sel;
3053
3054 temp = I915_READ(PCH_DPLL_SEL);
3055 switch (pipe) {
3056 default:
3057 case 0:
3058 temp |= TRANSA_DPLL_ENABLE;
3059 sel = TRANSA_DPLLB_SEL;
3060 break;
3061 case 1:
3062 temp |= TRANSB_DPLL_ENABLE;
3063 sel = TRANSB_DPLLB_SEL;
3064 break;
3065 case 2:
3066 temp |= TRANSC_DPLL_ENABLE;
3067 sel = TRANSC_DPLLB_SEL;
3068 break;
3069 }
3070 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3071 temp |= sel;
3072 else
3073 temp &= ~sel;
3074 I915_WRITE(PCH_DPLL_SEL, temp);
3075 }
3076
3077 /* set transcoder timing, panel must allow it */
3078 assert_panel_unlocked(dev_priv, pipe);
3079 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3080
3081 intel_fdi_normal_train(crtc);
3082
3083 /* For PCH DP, enable TRANS_DP_CTL */
3084 if (HAS_PCH_CPT(dev) &&
3085 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3086 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3087 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3088 reg = TRANS_DP_CTL(pipe);
3089 temp = I915_READ(reg);
3090 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3091 TRANS_DP_SYNC_MASK |
3092 TRANS_DP_BPC_MASK);
3093 temp |= (TRANS_DP_OUTPUT_ENABLE |
3094 TRANS_DP_ENH_FRAMING);
3095 temp |= bpc << 9; /* same format but at 11:9 */
3096
3097 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3098 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3099 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3100 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3101
3102 switch (intel_trans_dp_port_sel(crtc)) {
3103 case PCH_DP_B:
3104 temp |= TRANS_DP_PORT_SEL_B;
3105 break;
3106 case PCH_DP_C:
3107 temp |= TRANS_DP_PORT_SEL_C;
3108 break;
3109 case PCH_DP_D:
3110 temp |= TRANS_DP_PORT_SEL_D;
3111 break;
3112 default:
3113 BUG();
3114 }
3115
3116 I915_WRITE(reg, temp);
3117 }
3118
3119 ironlake_enable_pch_transcoder(dev_priv, pipe);
3120 }
3121
3122 static void lpt_pch_enable(struct drm_crtc *crtc)
3123 {
3124 struct drm_device *dev = crtc->dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3127 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3128
3129 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3130
3131 lpt_program_iclkip(crtc);
3132
3133 /* Set transcoder timing. */
3134 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3135
3136 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3137 }
3138
3139 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3140 {
3141 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3142
3143 if (pll == NULL)
3144 return;
3145
3146 if (pll->refcount == 0) {
3147 WARN(1, "bad PCH PLL refcount\n");
3148 return;
3149 }
3150
3151 --pll->refcount;
3152 intel_crtc->pch_pll = NULL;
3153 }
3154
3155 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3156 {
3157 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3158 struct intel_pch_pll *pll;
3159 int i;
3160
3161 pll = intel_crtc->pch_pll;
3162 if (pll) {
3163 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto prepare;
3166 }
3167
3168 if (HAS_PCH_IBX(dev_priv->dev)) {
3169 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3170 i = intel_crtc->pipe;
3171 pll = &dev_priv->pch_plls[i];
3172
3173 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3174 intel_crtc->base.base.id, pll->pll_reg);
3175
3176 goto found;
3177 }
3178
3179 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3180 pll = &dev_priv->pch_plls[i];
3181
3182 /* Only want to check enabled timings first */
3183 if (pll->refcount == 0)
3184 continue;
3185
3186 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3187 fp == I915_READ(pll->fp0_reg)) {
3188 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3189 intel_crtc->base.base.id,
3190 pll->pll_reg, pll->refcount, pll->active);
3191
3192 goto found;
3193 }
3194 }
3195
3196 /* Ok no matching timings, maybe there's a free one? */
3197 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3198 pll = &dev_priv->pch_plls[i];
3199 if (pll->refcount == 0) {
3200 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3201 intel_crtc->base.base.id, pll->pll_reg);
3202 goto found;
3203 }
3204 }
3205
3206 return NULL;
3207
3208 found:
3209 intel_crtc->pch_pll = pll;
3210 pll->refcount++;
3211 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3212 prepare: /* separate function? */
3213 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3214
3215 /* Wait for the clocks to stabilize before rewriting the regs */
3216 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3217 POSTING_READ(pll->pll_reg);
3218 udelay(150);
3219
3220 I915_WRITE(pll->fp0_reg, fp);
3221 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3222 pll->on = false;
3223 return pll;
3224 }
3225
3226 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3227 {
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 int dslreg = PIPEDSL(pipe);
3230 u32 temp;
3231
3232 temp = I915_READ(dslreg);
3233 udelay(500);
3234 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3235 if (wait_for(I915_READ(dslreg) != temp, 5))
3236 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3237 }
3238 }
3239
3240 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3241 {
3242 struct drm_device *dev = crtc->base.dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 int pipe = crtc->pipe;
3245
3246 if (crtc->config.pch_pfit.size) {
3247 /* Force use of hard-coded filter coefficients
3248 * as some pre-programmed values are broken,
3249 * e.g. x201.
3250 */
3251 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3253 PF_PIPE_SEL_IVB(pipe));
3254 else
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3256 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3257 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3258 }
3259 }
3260
3261 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3262 {
3263 struct drm_device *dev = crtc->dev;
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3266 struct intel_encoder *encoder;
3267 int pipe = intel_crtc->pipe;
3268 int plane = intel_crtc->plane;
3269 u32 temp;
3270
3271 WARN_ON(!crtc->enabled);
3272
3273 if (intel_crtc->active)
3274 return;
3275
3276 intel_crtc->active = true;
3277
3278 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3279 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3280
3281 intel_update_watermarks(dev);
3282
3283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3284 temp = I915_READ(PCH_LVDS);
3285 if ((temp & LVDS_PORT_EN) == 0)
3286 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3287 }
3288
3289
3290 if (intel_crtc->config.has_pch_encoder) {
3291 /* Note: FDI PLL enabling _must_ be done before we enable the
3292 * cpu pipes, hence this is separate from all the other fdi/pch
3293 * enabling. */
3294 ironlake_fdi_pll_enable(intel_crtc);
3295 } else {
3296 assert_fdi_tx_disabled(dev_priv, pipe);
3297 assert_fdi_rx_disabled(dev_priv, pipe);
3298 }
3299
3300 for_each_encoder_on_crtc(dev, crtc, encoder)
3301 if (encoder->pre_enable)
3302 encoder->pre_enable(encoder);
3303
3304 /* Enable panel fitting for LVDS */
3305 ironlake_pfit_enable(intel_crtc);
3306
3307 /*
3308 * On ILK+ LUT must be loaded before the pipe is running but with
3309 * clocks enabled
3310 */
3311 intel_crtc_load_lut(crtc);
3312
3313 intel_enable_pipe(dev_priv, pipe,
3314 intel_crtc->config.has_pch_encoder);
3315 intel_enable_plane(dev_priv, plane, pipe);
3316
3317 if (intel_crtc->config.has_pch_encoder)
3318 ironlake_pch_enable(crtc);
3319
3320 mutex_lock(&dev->struct_mutex);
3321 intel_update_fbc(dev);
3322 mutex_unlock(&dev->struct_mutex);
3323
3324 intel_crtc_update_cursor(crtc, true);
3325
3326 for_each_encoder_on_crtc(dev, crtc, encoder)
3327 encoder->enable(encoder);
3328
3329 if (HAS_PCH_CPT(dev))
3330 cpt_verify_modeset(dev, intel_crtc->pipe);
3331
3332 /*
3333 * There seems to be a race in PCH platform hw (at least on some
3334 * outputs) where an enabled pipe still completes any pageflip right
3335 * away (as if the pipe is off) instead of waiting for vblank. As soon
3336 * as the first vblank happend, everything works as expected. Hence just
3337 * wait for one vblank before returning to avoid strange things
3338 * happening.
3339 */
3340 intel_wait_for_vblank(dev, intel_crtc->pipe);
3341 }
3342
3343 static void haswell_crtc_enable(struct drm_crtc *crtc)
3344 {
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 struct intel_encoder *encoder;
3349 int pipe = intel_crtc->pipe;
3350 int plane = intel_crtc->plane;
3351
3352 WARN_ON(!crtc->enabled);
3353
3354 if (intel_crtc->active)
3355 return;
3356
3357 intel_crtc->active = true;
3358
3359 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3360 if (intel_crtc->config.has_pch_encoder)
3361 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3362
3363 intel_update_watermarks(dev);
3364
3365 if (intel_crtc->config.has_pch_encoder)
3366 dev_priv->display.fdi_link_train(crtc);
3367
3368 for_each_encoder_on_crtc(dev, crtc, encoder)
3369 if (encoder->pre_enable)
3370 encoder->pre_enable(encoder);
3371
3372 intel_ddi_enable_pipe_clock(intel_crtc);
3373
3374 /* Enable panel fitting for eDP */
3375 ironlake_pfit_enable(intel_crtc);
3376
3377 /*
3378 * On ILK+ LUT must be loaded before the pipe is running but with
3379 * clocks enabled
3380 */
3381 intel_crtc_load_lut(crtc);
3382
3383 intel_ddi_set_pipe_settings(crtc);
3384 intel_ddi_enable_transcoder_func(crtc);
3385
3386 intel_enable_pipe(dev_priv, pipe,
3387 intel_crtc->config.has_pch_encoder);
3388 intel_enable_plane(dev_priv, plane, pipe);
3389
3390 if (intel_crtc->config.has_pch_encoder)
3391 lpt_pch_enable(crtc);
3392
3393 mutex_lock(&dev->struct_mutex);
3394 intel_update_fbc(dev);
3395 mutex_unlock(&dev->struct_mutex);
3396
3397 intel_crtc_update_cursor(crtc, true);
3398
3399 for_each_encoder_on_crtc(dev, crtc, encoder)
3400 encoder->enable(encoder);
3401
3402 /*
3403 * There seems to be a race in PCH platform hw (at least on some
3404 * outputs) where an enabled pipe still completes any pageflip right
3405 * away (as if the pipe is off) instead of waiting for vblank. As soon
3406 * as the first vblank happend, everything works as expected. Hence just
3407 * wait for one vblank before returning to avoid strange things
3408 * happening.
3409 */
3410 intel_wait_for_vblank(dev, intel_crtc->pipe);
3411 }
3412
3413 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3414 {
3415 struct drm_device *dev = crtc->base.dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 int pipe = crtc->pipe;
3418
3419 /* To avoid upsetting the power well on haswell only disable the pfit if
3420 * it's in use. The hw state code will make sure we get this right. */
3421 if (crtc->config.pch_pfit.size) {
3422 I915_WRITE(PF_CTL(pipe), 0);
3423 I915_WRITE(PF_WIN_POS(pipe), 0);
3424 I915_WRITE(PF_WIN_SZ(pipe), 0);
3425 }
3426 }
3427
3428 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3429 {
3430 struct drm_device *dev = crtc->dev;
3431 struct drm_i915_private *dev_priv = dev->dev_private;
3432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3433 struct intel_encoder *encoder;
3434 int pipe = intel_crtc->pipe;
3435 int plane = intel_crtc->plane;
3436 u32 reg, temp;
3437
3438
3439 if (!intel_crtc->active)
3440 return;
3441
3442 for_each_encoder_on_crtc(dev, crtc, encoder)
3443 encoder->disable(encoder);
3444
3445 intel_crtc_wait_for_pending_flips(crtc);
3446 drm_vblank_off(dev, pipe);
3447 intel_crtc_update_cursor(crtc, false);
3448
3449 intel_disable_plane(dev_priv, plane, pipe);
3450
3451 if (dev_priv->cfb_plane == plane)
3452 intel_disable_fbc(dev);
3453
3454 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3455 intel_disable_pipe(dev_priv, pipe);
3456
3457 ironlake_pfit_disable(intel_crtc);
3458
3459 for_each_encoder_on_crtc(dev, crtc, encoder)
3460 if (encoder->post_disable)
3461 encoder->post_disable(encoder);
3462
3463 ironlake_fdi_disable(crtc);
3464
3465 ironlake_disable_pch_transcoder(dev_priv, pipe);
3466 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3467
3468 if (HAS_PCH_CPT(dev)) {
3469 /* disable TRANS_DP_CTL */
3470 reg = TRANS_DP_CTL(pipe);
3471 temp = I915_READ(reg);
3472 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3473 temp |= TRANS_DP_PORT_SEL_NONE;
3474 I915_WRITE(reg, temp);
3475
3476 /* disable DPLL_SEL */
3477 temp = I915_READ(PCH_DPLL_SEL);
3478 switch (pipe) {
3479 case 0:
3480 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3481 break;
3482 case 1:
3483 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3484 break;
3485 case 2:
3486 /* C shares PLL A or B */
3487 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3488 break;
3489 default:
3490 BUG(); /* wtf */
3491 }
3492 I915_WRITE(PCH_DPLL_SEL, temp);
3493 }
3494
3495 /* disable PCH DPLL */
3496 intel_disable_pch_pll(intel_crtc);
3497
3498 ironlake_fdi_pll_disable(intel_crtc);
3499
3500 intel_crtc->active = false;
3501 intel_update_watermarks(dev);
3502
3503 mutex_lock(&dev->struct_mutex);
3504 intel_update_fbc(dev);
3505 mutex_unlock(&dev->struct_mutex);
3506 }
3507
3508 static void haswell_crtc_disable(struct drm_crtc *crtc)
3509 {
3510 struct drm_device *dev = crtc->dev;
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513 struct intel_encoder *encoder;
3514 int pipe = intel_crtc->pipe;
3515 int plane = intel_crtc->plane;
3516 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3517
3518 if (!intel_crtc->active)
3519 return;
3520
3521 for_each_encoder_on_crtc(dev, crtc, encoder)
3522 encoder->disable(encoder);
3523
3524 intel_crtc_wait_for_pending_flips(crtc);
3525 drm_vblank_off(dev, pipe);
3526 intel_crtc_update_cursor(crtc, false);
3527
3528 /* FBC must be disabled before disabling the plane on HSW. */
3529 if (dev_priv->cfb_plane == plane)
3530 intel_disable_fbc(dev);
3531
3532 intel_disable_plane(dev_priv, plane, pipe);
3533
3534 if (intel_crtc->config.has_pch_encoder)
3535 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3536 intel_disable_pipe(dev_priv, pipe);
3537
3538 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3539
3540 ironlake_pfit_disable(intel_crtc);
3541
3542 intel_ddi_disable_pipe_clock(intel_crtc);
3543
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3547
3548 if (intel_crtc->config.has_pch_encoder) {
3549 lpt_disable_pch_transcoder(dev_priv);
3550 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3551 intel_ddi_fdi_disable(crtc);
3552 }
3553
3554 intel_crtc->active = false;
3555 intel_update_watermarks(dev);
3556
3557 mutex_lock(&dev->struct_mutex);
3558 intel_update_fbc(dev);
3559 mutex_unlock(&dev->struct_mutex);
3560 }
3561
3562 static void ironlake_crtc_off(struct drm_crtc *crtc)
3563 {
3564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565 intel_put_pch_pll(intel_crtc);
3566 }
3567
3568 static void haswell_crtc_off(struct drm_crtc *crtc)
3569 {
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571
3572 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3573 * start using it. */
3574 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3575
3576 intel_ddi_put_crtc_pll(crtc);
3577 }
3578
3579 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3580 {
3581 if (!enable && intel_crtc->overlay) {
3582 struct drm_device *dev = intel_crtc->base.dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584
3585 mutex_lock(&dev->struct_mutex);
3586 dev_priv->mm.interruptible = false;
3587 (void) intel_overlay_switch_off(intel_crtc->overlay);
3588 dev_priv->mm.interruptible = true;
3589 mutex_unlock(&dev->struct_mutex);
3590 }
3591
3592 /* Let userspace switch the overlay on again. In most cases userspace
3593 * has to recompute where to put it anyway.
3594 */
3595 }
3596
3597 /**
3598 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3599 * cursor plane briefly if not already running after enabling the display
3600 * plane.
3601 * This workaround avoids occasional blank screens when self refresh is
3602 * enabled.
3603 */
3604 static void
3605 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3606 {
3607 u32 cntl = I915_READ(CURCNTR(pipe));
3608
3609 if ((cntl & CURSOR_MODE) == 0) {
3610 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3611
3612 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3613 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3614 intel_wait_for_vblank(dev_priv->dev, pipe);
3615 I915_WRITE(CURCNTR(pipe), cntl);
3616 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3617 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3618 }
3619 }
3620
3621 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3622 {
3623 struct drm_device *dev = crtc->base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_crtc_config *pipe_config = &crtc->config;
3626
3627 if (!crtc->config.gmch_pfit.control)
3628 return;
3629
3630 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3631 assert_pipe_disabled(dev_priv, crtc->pipe);
3632
3633 /*
3634 * Enable automatic panel scaling so that non-native modes
3635 * fill the screen. The panel fitter should only be
3636 * adjusted whilst the pipe is disabled, according to
3637 * register description and PRM.
3638 */
3639 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3640 pipe_config->gmch_pfit.control,
3641 pipe_config->gmch_pfit.pgm_ratios);
3642
3643 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3644 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3645
3646 /* Border color in case we don't scale up to the full screen. Black by
3647 * default, change to something else for debugging. */
3648 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3649 }
3650
3651 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3652 {
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 struct intel_encoder *encoder;
3657 int pipe = intel_crtc->pipe;
3658 int plane = intel_crtc->plane;
3659
3660 WARN_ON(!crtc->enabled);
3661
3662 if (intel_crtc->active)
3663 return;
3664
3665 intel_crtc->active = true;
3666 intel_update_watermarks(dev);
3667
3668 mutex_lock(&dev_priv->dpio_lock);
3669
3670 for_each_encoder_on_crtc(dev, crtc, encoder)
3671 if (encoder->pre_pll_enable)
3672 encoder->pre_pll_enable(encoder);
3673
3674 intel_enable_pll(dev_priv, pipe);
3675
3676 for_each_encoder_on_crtc(dev, crtc, encoder)
3677 if (encoder->pre_enable)
3678 encoder->pre_enable(encoder);
3679
3680 /* VLV wants encoder enabling _before_ the pipe is up. */
3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3682 encoder->enable(encoder);
3683
3684 /* Enable panel fitting for eDP */
3685 i9xx_pfit_enable(intel_crtc);
3686
3687 intel_enable_pipe(dev_priv, pipe, false);
3688 intel_enable_plane(dev_priv, plane, pipe);
3689
3690 intel_crtc_load_lut(crtc);
3691 intel_update_fbc(dev);
3692
3693 /* Give the overlay scaler a chance to enable if it's on this pipe */
3694 intel_crtc_dpms_overlay(intel_crtc, true);
3695 intel_crtc_update_cursor(crtc, true);
3696
3697 mutex_unlock(&dev_priv->dpio_lock);
3698 }
3699
3700 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3701 {
3702 struct drm_device *dev = crtc->dev;
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705 struct intel_encoder *encoder;
3706 int pipe = intel_crtc->pipe;
3707 int plane = intel_crtc->plane;
3708
3709 WARN_ON(!crtc->enabled);
3710
3711 if (intel_crtc->active)
3712 return;
3713
3714 intel_crtc->active = true;
3715 intel_update_watermarks(dev);
3716
3717 intel_enable_pll(dev_priv, pipe);
3718
3719 for_each_encoder_on_crtc(dev, crtc, encoder)
3720 if (encoder->pre_enable)
3721 encoder->pre_enable(encoder);
3722
3723 /* Enable panel fitting for LVDS */
3724 i9xx_pfit_enable(intel_crtc);
3725
3726 intel_enable_pipe(dev_priv, pipe, false);
3727 intel_enable_plane(dev_priv, plane, pipe);
3728 if (IS_G4X(dev))
3729 g4x_fixup_plane(dev_priv, pipe);
3730
3731 intel_crtc_load_lut(crtc);
3732 intel_update_fbc(dev);
3733
3734 /* Give the overlay scaler a chance to enable if it's on this pipe */
3735 intel_crtc_dpms_overlay(intel_crtc, true);
3736 intel_crtc_update_cursor(crtc, true);
3737
3738 for_each_encoder_on_crtc(dev, crtc, encoder)
3739 encoder->enable(encoder);
3740 }
3741
3742 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3743 {
3744 struct drm_device *dev = crtc->base.dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746
3747 if (!crtc->config.gmch_pfit.control)
3748 return;
3749
3750 assert_pipe_disabled(dev_priv, crtc->pipe);
3751
3752 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3753 I915_READ(PFIT_CONTROL));
3754 I915_WRITE(PFIT_CONTROL, 0);
3755 }
3756
3757 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3758 {
3759 struct drm_device *dev = crtc->dev;
3760 struct drm_i915_private *dev_priv = dev->dev_private;
3761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3762 struct intel_encoder *encoder;
3763 int pipe = intel_crtc->pipe;
3764 int plane = intel_crtc->plane;
3765
3766 if (!intel_crtc->active)
3767 return;
3768
3769 for_each_encoder_on_crtc(dev, crtc, encoder)
3770 encoder->disable(encoder);
3771
3772 /* Give the overlay scaler a chance to disable if it's on this pipe */
3773 intel_crtc_wait_for_pending_flips(crtc);
3774 drm_vblank_off(dev, pipe);
3775 intel_crtc_dpms_overlay(intel_crtc, false);
3776 intel_crtc_update_cursor(crtc, false);
3777
3778 if (dev_priv->cfb_plane == plane)
3779 intel_disable_fbc(dev);
3780
3781 intel_disable_plane(dev_priv, plane, pipe);
3782 intel_disable_pipe(dev_priv, pipe);
3783
3784 i9xx_pfit_disable(intel_crtc);
3785
3786 for_each_encoder_on_crtc(dev, crtc, encoder)
3787 if (encoder->post_disable)
3788 encoder->post_disable(encoder);
3789
3790 intel_disable_pll(dev_priv, pipe);
3791
3792 intel_crtc->active = false;
3793 intel_update_fbc(dev);
3794 intel_update_watermarks(dev);
3795 }
3796
3797 static void i9xx_crtc_off(struct drm_crtc *crtc)
3798 {
3799 }
3800
3801 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3802 bool enabled)
3803 {
3804 struct drm_device *dev = crtc->dev;
3805 struct drm_i915_master_private *master_priv;
3806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3807 int pipe = intel_crtc->pipe;
3808
3809 if (!dev->primary->master)
3810 return;
3811
3812 master_priv = dev->primary->master->driver_priv;
3813 if (!master_priv->sarea_priv)
3814 return;
3815
3816 switch (pipe) {
3817 case 0:
3818 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3819 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3820 break;
3821 case 1:
3822 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3823 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3824 break;
3825 default:
3826 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3827 break;
3828 }
3829 }
3830
3831 /**
3832 * Sets the power management mode of the pipe and plane.
3833 */
3834 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3835 {
3836 struct drm_device *dev = crtc->dev;
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3838 struct intel_encoder *intel_encoder;
3839 bool enable = false;
3840
3841 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3842 enable |= intel_encoder->connectors_active;
3843
3844 if (enable)
3845 dev_priv->display.crtc_enable(crtc);
3846 else
3847 dev_priv->display.crtc_disable(crtc);
3848
3849 intel_crtc_update_sarea(crtc, enable);
3850 }
3851
3852 static void intel_crtc_disable(struct drm_crtc *crtc)
3853 {
3854 struct drm_device *dev = crtc->dev;
3855 struct drm_connector *connector;
3856 struct drm_i915_private *dev_priv = dev->dev_private;
3857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3858
3859 /* crtc should still be enabled when we disable it. */
3860 WARN_ON(!crtc->enabled);
3861
3862 dev_priv->display.crtc_disable(crtc);
3863 intel_crtc->eld_vld = false;
3864 intel_crtc_update_sarea(crtc, false);
3865 dev_priv->display.off(crtc);
3866
3867 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3868 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3869
3870 if (crtc->fb) {
3871 mutex_lock(&dev->struct_mutex);
3872 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3873 mutex_unlock(&dev->struct_mutex);
3874 crtc->fb = NULL;
3875 }
3876
3877 /* Update computed state. */
3878 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3879 if (!connector->encoder || !connector->encoder->crtc)
3880 continue;
3881
3882 if (connector->encoder->crtc != crtc)
3883 continue;
3884
3885 connector->dpms = DRM_MODE_DPMS_OFF;
3886 to_intel_encoder(connector->encoder)->connectors_active = false;
3887 }
3888 }
3889
3890 void intel_modeset_disable(struct drm_device *dev)
3891 {
3892 struct drm_crtc *crtc;
3893
3894 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3895 if (crtc->enabled)
3896 intel_crtc_disable(crtc);
3897 }
3898 }
3899
3900 void intel_encoder_destroy(struct drm_encoder *encoder)
3901 {
3902 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3903
3904 drm_encoder_cleanup(encoder);
3905 kfree(intel_encoder);
3906 }
3907
3908 /* Simple dpms helper for encodres with just one connector, no cloning and only
3909 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3910 * state of the entire output pipe. */
3911 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3912 {
3913 if (mode == DRM_MODE_DPMS_ON) {
3914 encoder->connectors_active = true;
3915
3916 intel_crtc_update_dpms(encoder->base.crtc);
3917 } else {
3918 encoder->connectors_active = false;
3919
3920 intel_crtc_update_dpms(encoder->base.crtc);
3921 }
3922 }
3923
3924 /* Cross check the actual hw state with our own modeset state tracking (and it's
3925 * internal consistency). */
3926 static void intel_connector_check_state(struct intel_connector *connector)
3927 {
3928 if (connector->get_hw_state(connector)) {
3929 struct intel_encoder *encoder = connector->encoder;
3930 struct drm_crtc *crtc;
3931 bool encoder_enabled;
3932 enum pipe pipe;
3933
3934 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3935 connector->base.base.id,
3936 drm_get_connector_name(&connector->base));
3937
3938 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3939 "wrong connector dpms state\n");
3940 WARN(connector->base.encoder != &encoder->base,
3941 "active connector not linked to encoder\n");
3942 WARN(!encoder->connectors_active,
3943 "encoder->connectors_active not set\n");
3944
3945 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3946 WARN(!encoder_enabled, "encoder not enabled\n");
3947 if (WARN_ON(!encoder->base.crtc))
3948 return;
3949
3950 crtc = encoder->base.crtc;
3951
3952 WARN(!crtc->enabled, "crtc not enabled\n");
3953 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3954 WARN(pipe != to_intel_crtc(crtc)->pipe,
3955 "encoder active on the wrong pipe\n");
3956 }
3957 }
3958
3959 /* Even simpler default implementation, if there's really no special case to
3960 * consider. */
3961 void intel_connector_dpms(struct drm_connector *connector, int mode)
3962 {
3963 struct intel_encoder *encoder = intel_attached_encoder(connector);
3964
3965 /* All the simple cases only support two dpms states. */
3966 if (mode != DRM_MODE_DPMS_ON)
3967 mode = DRM_MODE_DPMS_OFF;
3968
3969 if (mode == connector->dpms)
3970 return;
3971
3972 connector->dpms = mode;
3973
3974 /* Only need to change hw state when actually enabled */
3975 if (encoder->base.crtc)
3976 intel_encoder_dpms(encoder, mode);
3977 else
3978 WARN_ON(encoder->connectors_active != false);
3979
3980 intel_modeset_check_state(connector->dev);
3981 }
3982
3983 /* Simple connector->get_hw_state implementation for encoders that support only
3984 * one connector and no cloning and hence the encoder state determines the state
3985 * of the connector. */
3986 bool intel_connector_get_hw_state(struct intel_connector *connector)
3987 {
3988 enum pipe pipe = 0;
3989 struct intel_encoder *encoder = connector->encoder;
3990
3991 return encoder->get_hw_state(encoder, &pipe);
3992 }
3993
3994 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3995 struct intel_crtc_config *pipe_config)
3996 {
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 struct intel_crtc *pipe_B_crtc =
3999 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4000
4001 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4002 pipe_name(pipe), pipe_config->fdi_lanes);
4003 if (pipe_config->fdi_lanes > 4) {
4004 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4005 pipe_name(pipe), pipe_config->fdi_lanes);
4006 return false;
4007 }
4008
4009 if (IS_HASWELL(dev)) {
4010 if (pipe_config->fdi_lanes > 2) {
4011 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4012 pipe_config->fdi_lanes);
4013 return false;
4014 } else {
4015 return true;
4016 }
4017 }
4018
4019 if (INTEL_INFO(dev)->num_pipes == 2)
4020 return true;
4021
4022 /* Ivybridge 3 pipe is really complicated */
4023 switch (pipe) {
4024 case PIPE_A:
4025 return true;
4026 case PIPE_B:
4027 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4028 pipe_config->fdi_lanes > 2) {
4029 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4030 pipe_name(pipe), pipe_config->fdi_lanes);
4031 return false;
4032 }
4033 return true;
4034 case PIPE_C:
4035 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4036 pipe_B_crtc->config.fdi_lanes <= 2) {
4037 if (pipe_config->fdi_lanes > 2) {
4038 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4039 pipe_name(pipe), pipe_config->fdi_lanes);
4040 return false;
4041 }
4042 } else {
4043 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4044 return false;
4045 }
4046 return true;
4047 default:
4048 BUG();
4049 }
4050 }
4051
4052 #define RETRY 1
4053 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4054 struct intel_crtc_config *pipe_config)
4055 {
4056 struct drm_device *dev = intel_crtc->base.dev;
4057 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4058 int target_clock, lane, link_bw;
4059 bool setup_ok, needs_recompute = false;
4060
4061 retry:
4062 /* FDI is a binary signal running at ~2.7GHz, encoding
4063 * each output octet as 10 bits. The actual frequency
4064 * is stored as a divider into a 100MHz clock, and the
4065 * mode pixel clock is stored in units of 1KHz.
4066 * Hence the bw of each lane in terms of the mode signal
4067 * is:
4068 */
4069 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4070
4071 if (pipe_config->pixel_target_clock)
4072 target_clock = pipe_config->pixel_target_clock;
4073 else
4074 target_clock = adjusted_mode->clock;
4075
4076 lane = ironlake_get_lanes_required(target_clock, link_bw,
4077 pipe_config->pipe_bpp);
4078
4079 pipe_config->fdi_lanes = lane;
4080
4081 if (pipe_config->pixel_multiplier > 1)
4082 link_bw *= pipe_config->pixel_multiplier;
4083 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4084 link_bw, &pipe_config->fdi_m_n);
4085
4086 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4087 intel_crtc->pipe, pipe_config);
4088 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4089 pipe_config->pipe_bpp -= 2*3;
4090 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4091 pipe_config->pipe_bpp);
4092 needs_recompute = true;
4093 pipe_config->bw_constrained = true;
4094
4095 goto retry;
4096 }
4097
4098 if (needs_recompute)
4099 return RETRY;
4100
4101 return setup_ok ? 0 : -EINVAL;
4102 }
4103
4104 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4105 struct intel_crtc_config *pipe_config)
4106 {
4107 struct drm_device *dev = crtc->dev;
4108 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4109
4110 if (HAS_PCH_SPLIT(dev)) {
4111 /* FDI link clock is fixed at 2.7G */
4112 if (pipe_config->requested_mode.clock * 3
4113 > IRONLAKE_FDI_FREQ * 4)
4114 return -EINVAL;
4115 }
4116
4117 /* All interlaced capable intel hw wants timings in frames. Note though
4118 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4119 * timings, so we need to be careful not to clobber these.*/
4120 if (!pipe_config->timings_set)
4121 drm_mode_set_crtcinfo(adjusted_mode, 0);
4122
4123 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4124 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4125 */
4126 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4127 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4128 return -EINVAL;
4129
4130 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4131 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4132 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4133 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4134 * for lvds. */
4135 pipe_config->pipe_bpp = 8*3;
4136 }
4137
4138 if (pipe_config->has_pch_encoder)
4139 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4140
4141 return 0;
4142 }
4143
4144 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4145 {
4146 return 400000; /* FIXME */
4147 }
4148
4149 static int i945_get_display_clock_speed(struct drm_device *dev)
4150 {
4151 return 400000;
4152 }
4153
4154 static int i915_get_display_clock_speed(struct drm_device *dev)
4155 {
4156 return 333000;
4157 }
4158
4159 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4160 {
4161 return 200000;
4162 }
4163
4164 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4165 {
4166 u16 gcfgc = 0;
4167
4168 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4169
4170 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4171 return 133000;
4172 else {
4173 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4174 case GC_DISPLAY_CLOCK_333_MHZ:
4175 return 333000;
4176 default:
4177 case GC_DISPLAY_CLOCK_190_200_MHZ:
4178 return 190000;
4179 }
4180 }
4181 }
4182
4183 static int i865_get_display_clock_speed(struct drm_device *dev)
4184 {
4185 return 266000;
4186 }
4187
4188 static int i855_get_display_clock_speed(struct drm_device *dev)
4189 {
4190 u16 hpllcc = 0;
4191 /* Assume that the hardware is in the high speed state. This
4192 * should be the default.
4193 */
4194 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4195 case GC_CLOCK_133_200:
4196 case GC_CLOCK_100_200:
4197 return 200000;
4198 case GC_CLOCK_166_250:
4199 return 250000;
4200 case GC_CLOCK_100_133:
4201 return 133000;
4202 }
4203
4204 /* Shouldn't happen */
4205 return 0;
4206 }
4207
4208 static int i830_get_display_clock_speed(struct drm_device *dev)
4209 {
4210 return 133000;
4211 }
4212
4213 static void
4214 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4215 {
4216 while (*num > 0xffffff || *den > 0xffffff) {
4217 *num >>= 1;
4218 *den >>= 1;
4219 }
4220 }
4221
4222 void
4223 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4224 int pixel_clock, int link_clock,
4225 struct intel_link_m_n *m_n)
4226 {
4227 m_n->tu = 64;
4228 m_n->gmch_m = bits_per_pixel * pixel_clock;
4229 m_n->gmch_n = link_clock * nlanes * 8;
4230 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4231 m_n->link_m = pixel_clock;
4232 m_n->link_n = link_clock;
4233 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4234 }
4235
4236 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4237 {
4238 if (i915_panel_use_ssc >= 0)
4239 return i915_panel_use_ssc != 0;
4240 return dev_priv->vbt.lvds_use_ssc
4241 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4242 }
4243
4244 static int vlv_get_refclk(struct drm_crtc *crtc)
4245 {
4246 struct drm_device *dev = crtc->dev;
4247 struct drm_i915_private *dev_priv = dev->dev_private;
4248 int refclk = 27000; /* for DP & HDMI */
4249
4250 return 100000; /* only one validated so far */
4251
4252 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4253 refclk = 96000;
4254 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4255 if (intel_panel_use_ssc(dev_priv))
4256 refclk = 100000;
4257 else
4258 refclk = 96000;
4259 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4260 refclk = 100000;
4261 }
4262
4263 return refclk;
4264 }
4265
4266 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4267 {
4268 struct drm_device *dev = crtc->dev;
4269 struct drm_i915_private *dev_priv = dev->dev_private;
4270 int refclk;
4271
4272 if (IS_VALLEYVIEW(dev)) {
4273 refclk = vlv_get_refclk(crtc);
4274 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4275 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4276 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4277 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4278 refclk / 1000);
4279 } else if (!IS_GEN2(dev)) {
4280 refclk = 96000;
4281 } else {
4282 refclk = 48000;
4283 }
4284
4285 return refclk;
4286 }
4287
4288 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4289 {
4290 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4291 }
4292
4293 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4294 {
4295 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4296 }
4297
4298 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4299 intel_clock_t *reduced_clock)
4300 {
4301 struct drm_device *dev = crtc->base.dev;
4302 struct drm_i915_private *dev_priv = dev->dev_private;
4303 int pipe = crtc->pipe;
4304 u32 fp, fp2 = 0;
4305
4306 if (IS_PINEVIEW(dev)) {
4307 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4308 if (reduced_clock)
4309 fp2 = pnv_dpll_compute_fp(reduced_clock);
4310 } else {
4311 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4312 if (reduced_clock)
4313 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4314 }
4315
4316 I915_WRITE(FP0(pipe), fp);
4317
4318 crtc->lowfreq_avail = false;
4319 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4320 reduced_clock && i915_powersave) {
4321 I915_WRITE(FP1(pipe), fp2);
4322 crtc->lowfreq_avail = true;
4323 } else {
4324 I915_WRITE(FP1(pipe), fp);
4325 }
4326 }
4327
4328 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4329 {
4330 u32 reg_val;
4331
4332 /*
4333 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4334 * and set it to a reasonable value instead.
4335 */
4336 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4337 reg_val &= 0xffffff00;
4338 reg_val |= 0x00000030;
4339 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4340
4341 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4342 reg_val &= 0x8cffffff;
4343 reg_val = 0x8c000000;
4344 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4345
4346 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4347 reg_val &= 0xffffff00;
4348 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4349
4350 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4351 reg_val &= 0x00ffffff;
4352 reg_val |= 0xb0000000;
4353 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4354 }
4355
4356 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4357 struct intel_link_m_n *m_n)
4358 {
4359 struct drm_device *dev = crtc->base.dev;
4360 struct drm_i915_private *dev_priv = dev->dev_private;
4361 int pipe = crtc->pipe;
4362
4363 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4364 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4365 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4366 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4367 }
4368
4369 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4370 struct intel_link_m_n *m_n)
4371 {
4372 struct drm_device *dev = crtc->base.dev;
4373 struct drm_i915_private *dev_priv = dev->dev_private;
4374 int pipe = crtc->pipe;
4375 enum transcoder transcoder = crtc->config.cpu_transcoder;
4376
4377 if (INTEL_INFO(dev)->gen >= 5) {
4378 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4379 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4380 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4381 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4382 } else {
4383 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4384 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4385 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4386 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4387 }
4388 }
4389
4390 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4391 {
4392 if (crtc->config.has_pch_encoder)
4393 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4394 else
4395 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4396 }
4397
4398 static void vlv_update_pll(struct intel_crtc *crtc)
4399 {
4400 struct drm_device *dev = crtc->base.dev;
4401 struct drm_i915_private *dev_priv = dev->dev_private;
4402 struct drm_display_mode *adjusted_mode =
4403 &crtc->config.adjusted_mode;
4404 struct intel_encoder *encoder;
4405 int pipe = crtc->pipe;
4406 u32 dpll, mdiv;
4407 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4408 bool is_hdmi;
4409 u32 coreclk, reg_val, dpll_md;
4410
4411 mutex_lock(&dev_priv->dpio_lock);
4412
4413 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4414
4415 bestn = crtc->config.dpll.n;
4416 bestm1 = crtc->config.dpll.m1;
4417 bestm2 = crtc->config.dpll.m2;
4418 bestp1 = crtc->config.dpll.p1;
4419 bestp2 = crtc->config.dpll.p2;
4420
4421 /* See eDP HDMI DPIO driver vbios notes doc */
4422
4423 /* PLL B needs special handling */
4424 if (pipe)
4425 vlv_pllb_recal_opamp(dev_priv);
4426
4427 /* Set up Tx target for periodic Rcomp update */
4428 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4429
4430 /* Disable target IRef on PLL */
4431 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4432 reg_val &= 0x00ffffff;
4433 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4434
4435 /* Disable fast lock */
4436 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4437
4438 /* Set idtafcrecal before PLL is enabled */
4439 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4440 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4441 mdiv |= ((bestn << DPIO_N_SHIFT));
4442 mdiv |= (1 << DPIO_K_SHIFT);
4443
4444 /*
4445 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4446 * but we don't support that).
4447 * Note: don't use the DAC post divider as it seems unstable.
4448 */
4449 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4450 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4451
4452 mdiv |= DPIO_ENABLE_CALIBRATION;
4453 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4454
4455 /* Set HBR and RBR LPF coefficients */
4456 if (adjusted_mode->clock == 162000 ||
4457 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4458 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4459 0x005f0021);
4460 else
4461 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4462 0x00d0000f);
4463
4464 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4465 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4466 /* Use SSC source */
4467 if (!pipe)
4468 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4469 0x0df40000);
4470 else
4471 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4472 0x0df70000);
4473 } else { /* HDMI or VGA */
4474 /* Use bend source */
4475 if (!pipe)
4476 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4477 0x0df70000);
4478 else
4479 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4480 0x0df40000);
4481 }
4482
4483 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4484 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4485 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4486 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4487 coreclk |= 0x01000000;
4488 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4489
4490 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4491
4492 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4493 if (encoder->pre_pll_enable)
4494 encoder->pre_pll_enable(encoder);
4495
4496 /* Enable DPIO clock input */
4497 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4498 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4499 if (pipe)
4500 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4501
4502 dpll |= DPLL_VCO_ENABLE;
4503 I915_WRITE(DPLL(pipe), dpll);
4504 POSTING_READ(DPLL(pipe));
4505 udelay(150);
4506
4507 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4508 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4509
4510 dpll_md = 0;
4511 if (crtc->config.pixel_multiplier > 1) {
4512 dpll_md = (crtc->config.pixel_multiplier - 1)
4513 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4514 }
4515 I915_WRITE(DPLL_MD(pipe), dpll_md);
4516 POSTING_READ(DPLL_MD(pipe));
4517
4518 if (crtc->config.has_dp_encoder)
4519 intel_dp_set_m_n(crtc);
4520
4521 mutex_unlock(&dev_priv->dpio_lock);
4522 }
4523
4524 static void i9xx_update_pll(struct intel_crtc *crtc,
4525 intel_clock_t *reduced_clock,
4526 int num_connectors)
4527 {
4528 struct drm_device *dev = crtc->base.dev;
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 struct intel_encoder *encoder;
4531 int pipe = crtc->pipe;
4532 u32 dpll;
4533 bool is_sdvo;
4534 struct dpll *clock = &crtc->config.dpll;
4535
4536 i9xx_update_pll_dividers(crtc, reduced_clock);
4537
4538 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4539 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4540
4541 dpll = DPLL_VGA_MODE_DIS;
4542
4543 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4544 dpll |= DPLLB_MODE_LVDS;
4545 else
4546 dpll |= DPLLB_MODE_DAC_SERIAL;
4547
4548 if ((crtc->config.pixel_multiplier > 1) &&
4549 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4550 dpll |= (crtc->config.pixel_multiplier - 1)
4551 << SDVO_MULTIPLIER_SHIFT_HIRES;
4552 }
4553
4554 if (is_sdvo)
4555 dpll |= DPLL_DVO_HIGH_SPEED;
4556
4557 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4558 dpll |= DPLL_DVO_HIGH_SPEED;
4559
4560 /* compute bitmask from p1 value */
4561 if (IS_PINEVIEW(dev))
4562 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4563 else {
4564 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4565 if (IS_G4X(dev) && reduced_clock)
4566 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4567 }
4568 switch (clock->p2) {
4569 case 5:
4570 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4571 break;
4572 case 7:
4573 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4574 break;
4575 case 10:
4576 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4577 break;
4578 case 14:
4579 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4580 break;
4581 }
4582 if (INTEL_INFO(dev)->gen >= 4)
4583 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4584
4585 if (crtc->config.sdvo_tv_clock)
4586 dpll |= PLL_REF_INPUT_TVCLKINBC;
4587 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4588 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4589 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4590 else
4591 dpll |= PLL_REF_INPUT_DREFCLK;
4592
4593 dpll |= DPLL_VCO_ENABLE;
4594 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4595 POSTING_READ(DPLL(pipe));
4596 udelay(150);
4597
4598 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4599 if (encoder->pre_pll_enable)
4600 encoder->pre_pll_enable(encoder);
4601
4602 if (crtc->config.has_dp_encoder)
4603 intel_dp_set_m_n(crtc);
4604
4605 I915_WRITE(DPLL(pipe), dpll);
4606
4607 /* Wait for the clocks to stabilize. */
4608 POSTING_READ(DPLL(pipe));
4609 udelay(150);
4610
4611 if (INTEL_INFO(dev)->gen >= 4) {
4612 u32 dpll_md = 0;
4613 if (crtc->config.pixel_multiplier > 1) {
4614 dpll_md = (crtc->config.pixel_multiplier - 1)
4615 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4616 }
4617 I915_WRITE(DPLL_MD(pipe), dpll_md);
4618 } else {
4619 /* The pixel multiplier can only be updated once the
4620 * DPLL is enabled and the clocks are stable.
4621 *
4622 * So write it again.
4623 */
4624 I915_WRITE(DPLL(pipe), dpll);
4625 }
4626 }
4627
4628 static void i8xx_update_pll(struct intel_crtc *crtc,
4629 struct drm_display_mode *adjusted_mode,
4630 intel_clock_t *reduced_clock,
4631 int num_connectors)
4632 {
4633 struct drm_device *dev = crtc->base.dev;
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4635 struct intel_encoder *encoder;
4636 int pipe = crtc->pipe;
4637 u32 dpll;
4638 struct dpll *clock = &crtc->config.dpll;
4639
4640 i9xx_update_pll_dividers(crtc, reduced_clock);
4641
4642 dpll = DPLL_VGA_MODE_DIS;
4643
4644 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4645 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4646 } else {
4647 if (clock->p1 == 2)
4648 dpll |= PLL_P1_DIVIDE_BY_TWO;
4649 else
4650 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4651 if (clock->p2 == 4)
4652 dpll |= PLL_P2_DIVIDE_BY_4;
4653 }
4654
4655 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4656 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4657 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4658 else
4659 dpll |= PLL_REF_INPUT_DREFCLK;
4660
4661 dpll |= DPLL_VCO_ENABLE;
4662 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4663 POSTING_READ(DPLL(pipe));
4664 udelay(150);
4665
4666 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4667 if (encoder->pre_pll_enable)
4668 encoder->pre_pll_enable(encoder);
4669
4670 I915_WRITE(DPLL(pipe), dpll);
4671
4672 /* Wait for the clocks to stabilize. */
4673 POSTING_READ(DPLL(pipe));
4674 udelay(150);
4675
4676 /* The pixel multiplier can only be updated once the
4677 * DPLL is enabled and the clocks are stable.
4678 *
4679 * So write it again.
4680 */
4681 I915_WRITE(DPLL(pipe), dpll);
4682 }
4683
4684 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4685 struct drm_display_mode *mode,
4686 struct drm_display_mode *adjusted_mode)
4687 {
4688 struct drm_device *dev = intel_crtc->base.dev;
4689 struct drm_i915_private *dev_priv = dev->dev_private;
4690 enum pipe pipe = intel_crtc->pipe;
4691 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4692 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4693
4694 /* We need to be careful not to changed the adjusted mode, for otherwise
4695 * the hw state checker will get angry at the mismatch. */
4696 crtc_vtotal = adjusted_mode->crtc_vtotal;
4697 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4698
4699 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4700 /* the chip adds 2 halflines automatically */
4701 crtc_vtotal -= 1;
4702 crtc_vblank_end -= 1;
4703 vsyncshift = adjusted_mode->crtc_hsync_start
4704 - adjusted_mode->crtc_htotal / 2;
4705 } else {
4706 vsyncshift = 0;
4707 }
4708
4709 if (INTEL_INFO(dev)->gen > 3)
4710 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4711
4712 I915_WRITE(HTOTAL(cpu_transcoder),
4713 (adjusted_mode->crtc_hdisplay - 1) |
4714 ((adjusted_mode->crtc_htotal - 1) << 16));
4715 I915_WRITE(HBLANK(cpu_transcoder),
4716 (adjusted_mode->crtc_hblank_start - 1) |
4717 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4718 I915_WRITE(HSYNC(cpu_transcoder),
4719 (adjusted_mode->crtc_hsync_start - 1) |
4720 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4721
4722 I915_WRITE(VTOTAL(cpu_transcoder),
4723 (adjusted_mode->crtc_vdisplay - 1) |
4724 ((crtc_vtotal - 1) << 16));
4725 I915_WRITE(VBLANK(cpu_transcoder),
4726 (adjusted_mode->crtc_vblank_start - 1) |
4727 ((crtc_vblank_end - 1) << 16));
4728 I915_WRITE(VSYNC(cpu_transcoder),
4729 (adjusted_mode->crtc_vsync_start - 1) |
4730 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4731
4732 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4733 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4734 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4735 * bits. */
4736 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4737 (pipe == PIPE_B || pipe == PIPE_C))
4738 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4739
4740 /* pipesrc controls the size that is scaled from, which should
4741 * always be the user's requested size.
4742 */
4743 I915_WRITE(PIPESRC(pipe),
4744 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4745 }
4746
4747 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4748 struct intel_crtc_config *pipe_config)
4749 {
4750 struct drm_device *dev = crtc->base.dev;
4751 struct drm_i915_private *dev_priv = dev->dev_private;
4752 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4753 uint32_t tmp;
4754
4755 tmp = I915_READ(HTOTAL(cpu_transcoder));
4756 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4757 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4758 tmp = I915_READ(HBLANK(cpu_transcoder));
4759 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4760 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4761 tmp = I915_READ(HSYNC(cpu_transcoder));
4762 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4764
4765 tmp = I915_READ(VTOTAL(cpu_transcoder));
4766 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4767 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4768 tmp = I915_READ(VBLANK(cpu_transcoder));
4769 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4770 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4771 tmp = I915_READ(VSYNC(cpu_transcoder));
4772 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4773 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4774
4775 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4776 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4777 pipe_config->adjusted_mode.crtc_vtotal += 1;
4778 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4779 }
4780
4781 tmp = I915_READ(PIPESRC(crtc->pipe));
4782 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4783 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4784 }
4785
4786 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4787 {
4788 struct drm_device *dev = intel_crtc->base.dev;
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 uint32_t pipeconf;
4791
4792 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4793
4794 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4795 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4796 * core speed.
4797 *
4798 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4799 * pipe == 0 check?
4800 */
4801 if (intel_crtc->config.requested_mode.clock >
4802 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4803 pipeconf |= PIPECONF_DOUBLE_WIDE;
4804 else
4805 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4806 }
4807
4808 /* only g4x and later have fancy bpc/dither controls */
4809 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4810 pipeconf &= ~(PIPECONF_BPC_MASK |
4811 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4812
4813 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4814 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4815 pipeconf |= PIPECONF_DITHER_EN |
4816 PIPECONF_DITHER_TYPE_SP;
4817
4818 switch (intel_crtc->config.pipe_bpp) {
4819 case 18:
4820 pipeconf |= PIPECONF_6BPC;
4821 break;
4822 case 24:
4823 pipeconf |= PIPECONF_8BPC;
4824 break;
4825 case 30:
4826 pipeconf |= PIPECONF_10BPC;
4827 break;
4828 default:
4829 /* Case prevented by intel_choose_pipe_bpp_dither. */
4830 BUG();
4831 }
4832 }
4833
4834 if (HAS_PIPE_CXSR(dev)) {
4835 if (intel_crtc->lowfreq_avail) {
4836 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4837 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4838 } else {
4839 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4840 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4841 }
4842 }
4843
4844 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4845 if (!IS_GEN2(dev) &&
4846 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4847 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4848 else
4849 pipeconf |= PIPECONF_PROGRESSIVE;
4850
4851 if (IS_VALLEYVIEW(dev)) {
4852 if (intel_crtc->config.limited_color_range)
4853 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4854 else
4855 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4856 }
4857
4858 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4859 POSTING_READ(PIPECONF(intel_crtc->pipe));
4860 }
4861
4862 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4863 int x, int y,
4864 struct drm_framebuffer *fb)
4865 {
4866 struct drm_device *dev = crtc->dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4869 struct drm_display_mode *adjusted_mode =
4870 &intel_crtc->config.adjusted_mode;
4871 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4872 int pipe = intel_crtc->pipe;
4873 int plane = intel_crtc->plane;
4874 int refclk, num_connectors = 0;
4875 intel_clock_t clock, reduced_clock;
4876 u32 dspcntr;
4877 bool ok, has_reduced_clock = false;
4878 bool is_lvds = false;
4879 struct intel_encoder *encoder;
4880 const intel_limit_t *limit;
4881 int ret;
4882
4883 for_each_encoder_on_crtc(dev, crtc, encoder) {
4884 switch (encoder->type) {
4885 case INTEL_OUTPUT_LVDS:
4886 is_lvds = true;
4887 break;
4888 }
4889
4890 num_connectors++;
4891 }
4892
4893 refclk = i9xx_get_refclk(crtc, num_connectors);
4894
4895 /*
4896 * Returns a set of divisors for the desired target clock with the given
4897 * refclk, or FALSE. The returned values represent the clock equation:
4898 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4899 */
4900 limit = intel_limit(crtc, refclk);
4901 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4902 &clock);
4903 if (!ok) {
4904 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4905 return -EINVAL;
4906 }
4907
4908 /* Ensure that the cursor is valid for the new mode before changing... */
4909 intel_crtc_update_cursor(crtc, true);
4910
4911 if (is_lvds && dev_priv->lvds_downclock_avail) {
4912 /*
4913 * Ensure we match the reduced clock's P to the target clock.
4914 * If the clocks don't match, we can't switch the display clock
4915 * by using the FP0/FP1. In such case we will disable the LVDS
4916 * downclock feature.
4917 */
4918 has_reduced_clock = limit->find_pll(limit, crtc,
4919 dev_priv->lvds_downclock,
4920 refclk,
4921 &clock,
4922 &reduced_clock);
4923 }
4924 /* Compat-code for transition, will disappear. */
4925 if (!intel_crtc->config.clock_set) {
4926 intel_crtc->config.dpll.n = clock.n;
4927 intel_crtc->config.dpll.m1 = clock.m1;
4928 intel_crtc->config.dpll.m2 = clock.m2;
4929 intel_crtc->config.dpll.p1 = clock.p1;
4930 intel_crtc->config.dpll.p2 = clock.p2;
4931 }
4932
4933 if (IS_GEN2(dev))
4934 i8xx_update_pll(intel_crtc, adjusted_mode,
4935 has_reduced_clock ? &reduced_clock : NULL,
4936 num_connectors);
4937 else if (IS_VALLEYVIEW(dev))
4938 vlv_update_pll(intel_crtc);
4939 else
4940 i9xx_update_pll(intel_crtc,
4941 has_reduced_clock ? &reduced_clock : NULL,
4942 num_connectors);
4943
4944 /* Set up the display plane register */
4945 dspcntr = DISPPLANE_GAMMA_ENABLE;
4946
4947 if (!IS_VALLEYVIEW(dev)) {
4948 if (pipe == 0)
4949 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4950 else
4951 dspcntr |= DISPPLANE_SEL_PIPE_B;
4952 }
4953
4954 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4955 drm_mode_debug_printmodeline(mode);
4956
4957 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4958
4959 /* pipesrc and dspsize control the size that is scaled from,
4960 * which should always be the user's requested size.
4961 */
4962 I915_WRITE(DSPSIZE(plane),
4963 ((mode->vdisplay - 1) << 16) |
4964 (mode->hdisplay - 1));
4965 I915_WRITE(DSPPOS(plane), 0);
4966
4967 i9xx_set_pipeconf(intel_crtc);
4968
4969 I915_WRITE(DSPCNTR(plane), dspcntr);
4970 POSTING_READ(DSPCNTR(plane));
4971
4972 ret = intel_pipe_set_base(crtc, x, y, fb);
4973
4974 intel_update_watermarks(dev);
4975
4976 return ret;
4977 }
4978
4979 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4980 struct intel_crtc_config *pipe_config)
4981 {
4982 struct drm_device *dev = crtc->base.dev;
4983 struct drm_i915_private *dev_priv = dev->dev_private;
4984 uint32_t tmp;
4985
4986 tmp = I915_READ(PFIT_CONTROL);
4987
4988 if (INTEL_INFO(dev)->gen < 4) {
4989 if (crtc->pipe != PIPE_B)
4990 return;
4991
4992 /* gen2/3 store dither state in pfit control, needs to match */
4993 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4994 } else {
4995 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4996 return;
4997 }
4998
4999 if (!(tmp & PFIT_ENABLE))
5000 return;
5001
5002 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
5003 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5004 if (INTEL_INFO(dev)->gen < 5)
5005 pipe_config->gmch_pfit.lvds_border_bits =
5006 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5007 }
5008
5009 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5010 struct intel_crtc_config *pipe_config)
5011 {
5012 struct drm_device *dev = crtc->base.dev;
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014 uint32_t tmp;
5015
5016 tmp = I915_READ(PIPECONF(crtc->pipe));
5017 if (!(tmp & PIPECONF_ENABLE))
5018 return false;
5019
5020 intel_get_pipe_timings(crtc, pipe_config);
5021
5022 i9xx_get_pfit_config(crtc, pipe_config);
5023
5024 return true;
5025 }
5026
5027 static void ironlake_init_pch_refclk(struct drm_device *dev)
5028 {
5029 struct drm_i915_private *dev_priv = dev->dev_private;
5030 struct drm_mode_config *mode_config = &dev->mode_config;
5031 struct intel_encoder *encoder;
5032 u32 val, final;
5033 bool has_lvds = false;
5034 bool has_cpu_edp = false;
5035 bool has_panel = false;
5036 bool has_ck505 = false;
5037 bool can_ssc = false;
5038
5039 /* We need to take the global config into account */
5040 list_for_each_entry(encoder, &mode_config->encoder_list,
5041 base.head) {
5042 switch (encoder->type) {
5043 case INTEL_OUTPUT_LVDS:
5044 has_panel = true;
5045 has_lvds = true;
5046 break;
5047 case INTEL_OUTPUT_EDP:
5048 has_panel = true;
5049 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5050 has_cpu_edp = true;
5051 break;
5052 }
5053 }
5054
5055 if (HAS_PCH_IBX(dev)) {
5056 has_ck505 = dev_priv->vbt.display_clock_mode;
5057 can_ssc = has_ck505;
5058 } else {
5059 has_ck505 = false;
5060 can_ssc = true;
5061 }
5062
5063 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5064 has_panel, has_lvds, has_ck505);
5065
5066 /* Ironlake: try to setup display ref clock before DPLL
5067 * enabling. This is only under driver's control after
5068 * PCH B stepping, previous chipset stepping should be
5069 * ignoring this setting.
5070 */
5071 val = I915_READ(PCH_DREF_CONTROL);
5072
5073 /* As we must carefully and slowly disable/enable each source in turn,
5074 * compute the final state we want first and check if we need to
5075 * make any changes at all.
5076 */
5077 final = val;
5078 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5079 if (has_ck505)
5080 final |= DREF_NONSPREAD_CK505_ENABLE;
5081 else
5082 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5083
5084 final &= ~DREF_SSC_SOURCE_MASK;
5085 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5086 final &= ~DREF_SSC1_ENABLE;
5087
5088 if (has_panel) {
5089 final |= DREF_SSC_SOURCE_ENABLE;
5090
5091 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5092 final |= DREF_SSC1_ENABLE;
5093
5094 if (has_cpu_edp) {
5095 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5096 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5097 else
5098 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5099 } else
5100 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5101 } else {
5102 final |= DREF_SSC_SOURCE_DISABLE;
5103 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5104 }
5105
5106 if (final == val)
5107 return;
5108
5109 /* Always enable nonspread source */
5110 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5111
5112 if (has_ck505)
5113 val |= DREF_NONSPREAD_CK505_ENABLE;
5114 else
5115 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5116
5117 if (has_panel) {
5118 val &= ~DREF_SSC_SOURCE_MASK;
5119 val |= DREF_SSC_SOURCE_ENABLE;
5120
5121 /* SSC must be turned on before enabling the CPU output */
5122 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5123 DRM_DEBUG_KMS("Using SSC on panel\n");
5124 val |= DREF_SSC1_ENABLE;
5125 } else
5126 val &= ~DREF_SSC1_ENABLE;
5127
5128 /* Get SSC going before enabling the outputs */
5129 I915_WRITE(PCH_DREF_CONTROL, val);
5130 POSTING_READ(PCH_DREF_CONTROL);
5131 udelay(200);
5132
5133 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5134
5135 /* Enable CPU source on CPU attached eDP */
5136 if (has_cpu_edp) {
5137 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5138 DRM_DEBUG_KMS("Using SSC on eDP\n");
5139 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5140 }
5141 else
5142 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5143 } else
5144 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5145
5146 I915_WRITE(PCH_DREF_CONTROL, val);
5147 POSTING_READ(PCH_DREF_CONTROL);
5148 udelay(200);
5149 } else {
5150 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5151
5152 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5153
5154 /* Turn off CPU output */
5155 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5156
5157 I915_WRITE(PCH_DREF_CONTROL, val);
5158 POSTING_READ(PCH_DREF_CONTROL);
5159 udelay(200);
5160
5161 /* Turn off the SSC source */
5162 val &= ~DREF_SSC_SOURCE_MASK;
5163 val |= DREF_SSC_SOURCE_DISABLE;
5164
5165 /* Turn off SSC1 */
5166 val &= ~DREF_SSC1_ENABLE;
5167
5168 I915_WRITE(PCH_DREF_CONTROL, val);
5169 POSTING_READ(PCH_DREF_CONTROL);
5170 udelay(200);
5171 }
5172
5173 BUG_ON(val != final);
5174 }
5175
5176 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5177 static void lpt_init_pch_refclk(struct drm_device *dev)
5178 {
5179 struct drm_i915_private *dev_priv = dev->dev_private;
5180 struct drm_mode_config *mode_config = &dev->mode_config;
5181 struct intel_encoder *encoder;
5182 bool has_vga = false;
5183 bool is_sdv = false;
5184 u32 tmp;
5185
5186 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5187 switch (encoder->type) {
5188 case INTEL_OUTPUT_ANALOG:
5189 has_vga = true;
5190 break;
5191 }
5192 }
5193
5194 if (!has_vga)
5195 return;
5196
5197 mutex_lock(&dev_priv->dpio_lock);
5198
5199 /* XXX: Rip out SDV support once Haswell ships for real. */
5200 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5201 is_sdv = true;
5202
5203 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5204 tmp &= ~SBI_SSCCTL_DISABLE;
5205 tmp |= SBI_SSCCTL_PATHALT;
5206 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5207
5208 udelay(24);
5209
5210 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5211 tmp &= ~SBI_SSCCTL_PATHALT;
5212 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5213
5214 if (!is_sdv) {
5215 tmp = I915_READ(SOUTH_CHICKEN2);
5216 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5217 I915_WRITE(SOUTH_CHICKEN2, tmp);
5218
5219 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5220 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5221 DRM_ERROR("FDI mPHY reset assert timeout\n");
5222
5223 tmp = I915_READ(SOUTH_CHICKEN2);
5224 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5225 I915_WRITE(SOUTH_CHICKEN2, tmp);
5226
5227 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5228 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5229 100))
5230 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5231 }
5232
5233 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5234 tmp &= ~(0xFF << 24);
5235 tmp |= (0x12 << 24);
5236 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5237
5238 if (is_sdv) {
5239 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5240 tmp |= 0x7FFF;
5241 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5242 }
5243
5244 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5245 tmp |= (1 << 11);
5246 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5247
5248 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5249 tmp |= (1 << 11);
5250 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5251
5252 if (is_sdv) {
5253 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5254 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5255 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5256
5257 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5258 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5259 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5260
5261 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5262 tmp |= (0x3F << 8);
5263 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5266 tmp |= (0x3F << 8);
5267 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5268 }
5269
5270 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5271 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5272 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5273
5274 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5275 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5276 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5277
5278 if (!is_sdv) {
5279 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5280 tmp &= ~(7 << 13);
5281 tmp |= (5 << 13);
5282 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5283
5284 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5285 tmp &= ~(7 << 13);
5286 tmp |= (5 << 13);
5287 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5288 }
5289
5290 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5291 tmp &= ~0xFF;
5292 tmp |= 0x1C;
5293 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5294
5295 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5296 tmp &= ~0xFF;
5297 tmp |= 0x1C;
5298 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5299
5300 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5301 tmp &= ~(0xFF << 16);
5302 tmp |= (0x1C << 16);
5303 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5304
5305 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5306 tmp &= ~(0xFF << 16);
5307 tmp |= (0x1C << 16);
5308 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5309
5310 if (!is_sdv) {
5311 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5312 tmp |= (1 << 27);
5313 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5314
5315 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5316 tmp |= (1 << 27);
5317 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5318
5319 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5320 tmp &= ~(0xF << 28);
5321 tmp |= (4 << 28);
5322 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5323
5324 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5325 tmp &= ~(0xF << 28);
5326 tmp |= (4 << 28);
5327 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5328 }
5329
5330 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5331 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5332 tmp |= SBI_DBUFF0_ENABLE;
5333 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5334
5335 mutex_unlock(&dev_priv->dpio_lock);
5336 }
5337
5338 /*
5339 * Initialize reference clocks when the driver loads
5340 */
5341 void intel_init_pch_refclk(struct drm_device *dev)
5342 {
5343 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5344 ironlake_init_pch_refclk(dev);
5345 else if (HAS_PCH_LPT(dev))
5346 lpt_init_pch_refclk(dev);
5347 }
5348
5349 static int ironlake_get_refclk(struct drm_crtc *crtc)
5350 {
5351 struct drm_device *dev = crtc->dev;
5352 struct drm_i915_private *dev_priv = dev->dev_private;
5353 struct intel_encoder *encoder;
5354 int num_connectors = 0;
5355 bool is_lvds = false;
5356
5357 for_each_encoder_on_crtc(dev, crtc, encoder) {
5358 switch (encoder->type) {
5359 case INTEL_OUTPUT_LVDS:
5360 is_lvds = true;
5361 break;
5362 }
5363 num_connectors++;
5364 }
5365
5366 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5367 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5368 dev_priv->vbt.lvds_ssc_freq);
5369 return dev_priv->vbt.lvds_ssc_freq * 1000;
5370 }
5371
5372 return 120000;
5373 }
5374
5375 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5376 {
5377 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5379 int pipe = intel_crtc->pipe;
5380 uint32_t val;
5381
5382 val = I915_READ(PIPECONF(pipe));
5383
5384 val &= ~PIPECONF_BPC_MASK;
5385 switch (intel_crtc->config.pipe_bpp) {
5386 case 18:
5387 val |= PIPECONF_6BPC;
5388 break;
5389 case 24:
5390 val |= PIPECONF_8BPC;
5391 break;
5392 case 30:
5393 val |= PIPECONF_10BPC;
5394 break;
5395 case 36:
5396 val |= PIPECONF_12BPC;
5397 break;
5398 default:
5399 /* Case prevented by intel_choose_pipe_bpp_dither. */
5400 BUG();
5401 }
5402
5403 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5404 if (intel_crtc->config.dither)
5405 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5406
5407 val &= ~PIPECONF_INTERLACE_MASK;
5408 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5409 val |= PIPECONF_INTERLACED_ILK;
5410 else
5411 val |= PIPECONF_PROGRESSIVE;
5412
5413 if (intel_crtc->config.limited_color_range)
5414 val |= PIPECONF_COLOR_RANGE_SELECT;
5415 else
5416 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5417
5418 I915_WRITE(PIPECONF(pipe), val);
5419 POSTING_READ(PIPECONF(pipe));
5420 }
5421
5422 /*
5423 * Set up the pipe CSC unit.
5424 *
5425 * Currently only full range RGB to limited range RGB conversion
5426 * is supported, but eventually this should handle various
5427 * RGB<->YCbCr scenarios as well.
5428 */
5429 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5430 {
5431 struct drm_device *dev = crtc->dev;
5432 struct drm_i915_private *dev_priv = dev->dev_private;
5433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5434 int pipe = intel_crtc->pipe;
5435 uint16_t coeff = 0x7800; /* 1.0 */
5436
5437 /*
5438 * TODO: Check what kind of values actually come out of the pipe
5439 * with these coeff/postoff values and adjust to get the best
5440 * accuracy. Perhaps we even need to take the bpc value into
5441 * consideration.
5442 */
5443
5444 if (intel_crtc->config.limited_color_range)
5445 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5446
5447 /*
5448 * GY/GU and RY/RU should be the other way around according
5449 * to BSpec, but reality doesn't agree. Just set them up in
5450 * a way that results in the correct picture.
5451 */
5452 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5453 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5454
5455 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5456 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5457
5458 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5459 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5460
5461 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5462 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5463 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5464
5465 if (INTEL_INFO(dev)->gen > 6) {
5466 uint16_t postoff = 0;
5467
5468 if (intel_crtc->config.limited_color_range)
5469 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5470
5471 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5472 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5473 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5474
5475 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5476 } else {
5477 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5478
5479 if (intel_crtc->config.limited_color_range)
5480 mode |= CSC_BLACK_SCREEN_OFFSET;
5481
5482 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5483 }
5484 }
5485
5486 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5487 {
5488 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5490 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5491 uint32_t val;
5492
5493 val = I915_READ(PIPECONF(cpu_transcoder));
5494
5495 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5496 if (intel_crtc->config.dither)
5497 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5498
5499 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5500 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5501 val |= PIPECONF_INTERLACED_ILK;
5502 else
5503 val |= PIPECONF_PROGRESSIVE;
5504
5505 I915_WRITE(PIPECONF(cpu_transcoder), val);
5506 POSTING_READ(PIPECONF(cpu_transcoder));
5507 }
5508
5509 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5510 struct drm_display_mode *adjusted_mode,
5511 intel_clock_t *clock,
5512 bool *has_reduced_clock,
5513 intel_clock_t *reduced_clock)
5514 {
5515 struct drm_device *dev = crtc->dev;
5516 struct drm_i915_private *dev_priv = dev->dev_private;
5517 struct intel_encoder *intel_encoder;
5518 int refclk;
5519 const intel_limit_t *limit;
5520 bool ret, is_lvds = false;
5521
5522 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5523 switch (intel_encoder->type) {
5524 case INTEL_OUTPUT_LVDS:
5525 is_lvds = true;
5526 break;
5527 }
5528 }
5529
5530 refclk = ironlake_get_refclk(crtc);
5531
5532 /*
5533 * Returns a set of divisors for the desired target clock with the given
5534 * refclk, or FALSE. The returned values represent the clock equation:
5535 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5536 */
5537 limit = intel_limit(crtc, refclk);
5538 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5539 clock);
5540 if (!ret)
5541 return false;
5542
5543 if (is_lvds && dev_priv->lvds_downclock_avail) {
5544 /*
5545 * Ensure we match the reduced clock's P to the target clock.
5546 * If the clocks don't match, we can't switch the display clock
5547 * by using the FP0/FP1. In such case we will disable the LVDS
5548 * downclock feature.
5549 */
5550 *has_reduced_clock = limit->find_pll(limit, crtc,
5551 dev_priv->lvds_downclock,
5552 refclk,
5553 clock,
5554 reduced_clock);
5555 }
5556
5557 return true;
5558 }
5559
5560 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5561 {
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563 uint32_t temp;
5564
5565 temp = I915_READ(SOUTH_CHICKEN1);
5566 if (temp & FDI_BC_BIFURCATION_SELECT)
5567 return;
5568
5569 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5570 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5571
5572 temp |= FDI_BC_BIFURCATION_SELECT;
5573 DRM_DEBUG_KMS("enabling fdi C rx\n");
5574 I915_WRITE(SOUTH_CHICKEN1, temp);
5575 POSTING_READ(SOUTH_CHICKEN1);
5576 }
5577
5578 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5579 {
5580 struct drm_device *dev = intel_crtc->base.dev;
5581 struct drm_i915_private *dev_priv = dev->dev_private;
5582
5583 switch (intel_crtc->pipe) {
5584 case PIPE_A:
5585 break;
5586 case PIPE_B:
5587 if (intel_crtc->config.fdi_lanes > 2)
5588 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5589 else
5590 cpt_enable_fdi_bc_bifurcation(dev);
5591
5592 break;
5593 case PIPE_C:
5594 cpt_enable_fdi_bc_bifurcation(dev);
5595
5596 break;
5597 default:
5598 BUG();
5599 }
5600 }
5601
5602 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5603 {
5604 /*
5605 * Account for spread spectrum to avoid
5606 * oversubscribing the link. Max center spread
5607 * is 2.5%; use 5% for safety's sake.
5608 */
5609 u32 bps = target_clock * bpp * 21 / 20;
5610 return bps / (link_bw * 8) + 1;
5611 }
5612
5613 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5614 {
5615 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5616 }
5617
5618 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5619 u32 *fp,
5620 intel_clock_t *reduced_clock, u32 *fp2)
5621 {
5622 struct drm_crtc *crtc = &intel_crtc->base;
5623 struct drm_device *dev = crtc->dev;
5624 struct drm_i915_private *dev_priv = dev->dev_private;
5625 struct intel_encoder *intel_encoder;
5626 uint32_t dpll;
5627 int factor, num_connectors = 0;
5628 bool is_lvds = false, is_sdvo = false;
5629
5630 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5631 switch (intel_encoder->type) {
5632 case INTEL_OUTPUT_LVDS:
5633 is_lvds = true;
5634 break;
5635 case INTEL_OUTPUT_SDVO:
5636 case INTEL_OUTPUT_HDMI:
5637 is_sdvo = true;
5638 break;
5639 }
5640
5641 num_connectors++;
5642 }
5643
5644 /* Enable autotuning of the PLL clock (if permissible) */
5645 factor = 21;
5646 if (is_lvds) {
5647 if ((intel_panel_use_ssc(dev_priv) &&
5648 dev_priv->vbt.lvds_ssc_freq == 100) ||
5649 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5650 factor = 25;
5651 } else if (intel_crtc->config.sdvo_tv_clock)
5652 factor = 20;
5653
5654 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5655 *fp |= FP_CB_TUNE;
5656
5657 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5658 *fp2 |= FP_CB_TUNE;
5659
5660 dpll = 0;
5661
5662 if (is_lvds)
5663 dpll |= DPLLB_MODE_LVDS;
5664 else
5665 dpll |= DPLLB_MODE_DAC_SERIAL;
5666
5667 if (intel_crtc->config.pixel_multiplier > 1) {
5668 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5669 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5670 }
5671
5672 if (is_sdvo)
5673 dpll |= DPLL_DVO_HIGH_SPEED;
5674 if (intel_crtc->config.has_dp_encoder)
5675 dpll |= DPLL_DVO_HIGH_SPEED;
5676
5677 /* compute bitmask from p1 value */
5678 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5679 /* also FPA1 */
5680 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5681
5682 switch (intel_crtc->config.dpll.p2) {
5683 case 5:
5684 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5685 break;
5686 case 7:
5687 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5688 break;
5689 case 10:
5690 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5691 break;
5692 case 14:
5693 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5694 break;
5695 }
5696
5697 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5698 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5699 else
5700 dpll |= PLL_REF_INPUT_DREFCLK;
5701
5702 return dpll;
5703 }
5704
5705 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5706 int x, int y,
5707 struct drm_framebuffer *fb)
5708 {
5709 struct drm_device *dev = crtc->dev;
5710 struct drm_i915_private *dev_priv = dev->dev_private;
5711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5712 struct drm_display_mode *adjusted_mode =
5713 &intel_crtc->config.adjusted_mode;
5714 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5715 int pipe = intel_crtc->pipe;
5716 int plane = intel_crtc->plane;
5717 int num_connectors = 0;
5718 intel_clock_t clock, reduced_clock;
5719 u32 dpll = 0, fp = 0, fp2 = 0;
5720 bool ok, has_reduced_clock = false;
5721 bool is_lvds = false;
5722 struct intel_encoder *encoder;
5723 int ret;
5724
5725 for_each_encoder_on_crtc(dev, crtc, encoder) {
5726 switch (encoder->type) {
5727 case INTEL_OUTPUT_LVDS:
5728 is_lvds = true;
5729 break;
5730 }
5731
5732 num_connectors++;
5733 }
5734
5735 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5736 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5737
5738 intel_crtc->config.cpu_transcoder = pipe;
5739
5740 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5741 &has_reduced_clock, &reduced_clock);
5742 if (!ok) {
5743 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5744 return -EINVAL;
5745 }
5746 /* Compat-code for transition, will disappear. */
5747 if (!intel_crtc->config.clock_set) {
5748 intel_crtc->config.dpll.n = clock.n;
5749 intel_crtc->config.dpll.m1 = clock.m1;
5750 intel_crtc->config.dpll.m2 = clock.m2;
5751 intel_crtc->config.dpll.p1 = clock.p1;
5752 intel_crtc->config.dpll.p2 = clock.p2;
5753 }
5754
5755 /* Ensure that the cursor is valid for the new mode before changing... */
5756 intel_crtc_update_cursor(crtc, true);
5757
5758 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5759 drm_mode_debug_printmodeline(mode);
5760
5761 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5762 if (intel_crtc->config.has_pch_encoder) {
5763 struct intel_pch_pll *pll;
5764
5765 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5766 if (has_reduced_clock)
5767 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5768
5769 dpll = ironlake_compute_dpll(intel_crtc,
5770 &fp, &reduced_clock,
5771 has_reduced_clock ? &fp2 : NULL);
5772
5773 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5774 if (pll == NULL) {
5775 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5776 pipe_name(pipe));
5777 return -EINVAL;
5778 }
5779 } else
5780 intel_put_pch_pll(intel_crtc);
5781
5782 if (intel_crtc->config.has_dp_encoder)
5783 intel_dp_set_m_n(intel_crtc);
5784
5785 for_each_encoder_on_crtc(dev, crtc, encoder)
5786 if (encoder->pre_pll_enable)
5787 encoder->pre_pll_enable(encoder);
5788
5789 if (intel_crtc->pch_pll) {
5790 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5791
5792 /* Wait for the clocks to stabilize. */
5793 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5794 udelay(150);
5795
5796 /* The pixel multiplier can only be updated once the
5797 * DPLL is enabled and the clocks are stable.
5798 *
5799 * So write it again.
5800 */
5801 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5802 }
5803
5804 intel_crtc->lowfreq_avail = false;
5805 if (intel_crtc->pch_pll) {
5806 if (is_lvds && has_reduced_clock && i915_powersave) {
5807 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5808 intel_crtc->lowfreq_avail = true;
5809 } else {
5810 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5811 }
5812 }
5813
5814 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5815
5816 if (intel_crtc->config.has_pch_encoder) {
5817 intel_cpu_transcoder_set_m_n(intel_crtc,
5818 &intel_crtc->config.fdi_m_n);
5819 }
5820
5821 if (IS_IVYBRIDGE(dev))
5822 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5823
5824 ironlake_set_pipeconf(crtc);
5825
5826 /* Set up the display plane register */
5827 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5828 POSTING_READ(DSPCNTR(plane));
5829
5830 ret = intel_pipe_set_base(crtc, x, y, fb);
5831
5832 intel_update_watermarks(dev);
5833
5834 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5835
5836 return ret;
5837 }
5838
5839 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5840 struct intel_crtc_config *pipe_config)
5841 {
5842 struct drm_device *dev = crtc->base.dev;
5843 struct drm_i915_private *dev_priv = dev->dev_private;
5844 enum transcoder transcoder = pipe_config->cpu_transcoder;
5845
5846 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5847 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5848 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5849 & ~TU_SIZE_MASK;
5850 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5851 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5852 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5853 }
5854
5855 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5856 struct intel_crtc_config *pipe_config)
5857 {
5858 struct drm_device *dev = crtc->base.dev;
5859 struct drm_i915_private *dev_priv = dev->dev_private;
5860 uint32_t tmp;
5861
5862 tmp = I915_READ(PF_CTL(crtc->pipe));
5863
5864 if (tmp & PF_ENABLE) {
5865 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5866 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5867 }
5868 }
5869
5870 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5871 struct intel_crtc_config *pipe_config)
5872 {
5873 struct drm_device *dev = crtc->base.dev;
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875 uint32_t tmp;
5876
5877 tmp = I915_READ(PIPECONF(crtc->pipe));
5878 if (!(tmp & PIPECONF_ENABLE))
5879 return false;
5880
5881 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5882 pipe_config->has_pch_encoder = true;
5883
5884 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5885 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5886 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5887
5888 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5889 }
5890
5891 intel_get_pipe_timings(crtc, pipe_config);
5892
5893 ironlake_get_pfit_config(crtc, pipe_config);
5894
5895 return true;
5896 }
5897
5898 static void haswell_modeset_global_resources(struct drm_device *dev)
5899 {
5900 bool enable = false;
5901 struct intel_crtc *crtc;
5902 struct intel_encoder *encoder;
5903
5904 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5905 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5906 enable = true;
5907 /* XXX: Should check for edp transcoder here, but thanks to init
5908 * sequence that's not yet available. Just in case desktop eDP
5909 * on PORT D is possible on haswell, too. */
5910 /* Even the eDP panel fitter is outside the always-on well. */
5911 if (crtc->config.pch_pfit.size && crtc->base.enabled)
5912 enable = true;
5913 }
5914
5915 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5916 base.head) {
5917 if (encoder->type != INTEL_OUTPUT_EDP &&
5918 encoder->connectors_active)
5919 enable = true;
5920 }
5921
5922 intel_set_power_well(dev, enable);
5923 }
5924
5925 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5926 int x, int y,
5927 struct drm_framebuffer *fb)
5928 {
5929 struct drm_device *dev = crtc->dev;
5930 struct drm_i915_private *dev_priv = dev->dev_private;
5931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5932 struct drm_display_mode *adjusted_mode =
5933 &intel_crtc->config.adjusted_mode;
5934 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5935 int pipe = intel_crtc->pipe;
5936 int plane = intel_crtc->plane;
5937 int num_connectors = 0;
5938 bool is_cpu_edp = false;
5939 struct intel_encoder *encoder;
5940 int ret;
5941
5942 for_each_encoder_on_crtc(dev, crtc, encoder) {
5943 switch (encoder->type) {
5944 case INTEL_OUTPUT_EDP:
5945 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5946 is_cpu_edp = true;
5947 break;
5948 }
5949
5950 num_connectors++;
5951 }
5952
5953 if (is_cpu_edp)
5954 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5955 else
5956 intel_crtc->config.cpu_transcoder = pipe;
5957
5958 /* We are not sure yet this won't happen. */
5959 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5960 INTEL_PCH_TYPE(dev));
5961
5962 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5963 num_connectors, pipe_name(pipe));
5964
5965 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5966 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5967
5968 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5969
5970 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5971 return -EINVAL;
5972
5973 /* Ensure that the cursor is valid for the new mode before changing... */
5974 intel_crtc_update_cursor(crtc, true);
5975
5976 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5977 drm_mode_debug_printmodeline(mode);
5978
5979 if (intel_crtc->config.has_dp_encoder)
5980 intel_dp_set_m_n(intel_crtc);
5981
5982 intel_crtc->lowfreq_avail = false;
5983
5984 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5985
5986 if (intel_crtc->config.has_pch_encoder) {
5987 intel_cpu_transcoder_set_m_n(intel_crtc,
5988 &intel_crtc->config.fdi_m_n);
5989 }
5990
5991 haswell_set_pipeconf(crtc);
5992
5993 intel_set_pipe_csc(crtc);
5994
5995 /* Set up the display plane register */
5996 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5997 POSTING_READ(DSPCNTR(plane));
5998
5999 ret = intel_pipe_set_base(crtc, x, y, fb);
6000
6001 intel_update_watermarks(dev);
6002
6003 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
6004
6005 return ret;
6006 }
6007
6008 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6009 struct intel_crtc_config *pipe_config)
6010 {
6011 struct drm_device *dev = crtc->base.dev;
6012 struct drm_i915_private *dev_priv = dev->dev_private;
6013 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
6014 enum intel_display_power_domain pfit_domain;
6015 uint32_t tmp;
6016
6017 if (!intel_display_power_enabled(dev,
6018 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6019 return false;
6020
6021 tmp = I915_READ(PIPECONF(cpu_transcoder));
6022 if (!(tmp & PIPECONF_ENABLE))
6023 return false;
6024
6025 /*
6026 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6027 * DDI E. So just check whether this pipe is wired to DDI E and whether
6028 * the PCH transcoder is on.
6029 */
6030 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
6031 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6032 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6033 pipe_config->has_pch_encoder = true;
6034
6035 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6036 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6037 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6038
6039 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6040 }
6041
6042 intel_get_pipe_timings(crtc, pipe_config);
6043
6044 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6045 if (intel_display_power_enabled(dev, pfit_domain))
6046 ironlake_get_pfit_config(crtc, pipe_config);
6047
6048 return true;
6049 }
6050
6051 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6052 int x, int y,
6053 struct drm_framebuffer *fb)
6054 {
6055 struct drm_device *dev = crtc->dev;
6056 struct drm_i915_private *dev_priv = dev->dev_private;
6057 struct drm_encoder_helper_funcs *encoder_funcs;
6058 struct intel_encoder *encoder;
6059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6060 struct drm_display_mode *adjusted_mode =
6061 &intel_crtc->config.adjusted_mode;
6062 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6063 int pipe = intel_crtc->pipe;
6064 int ret;
6065
6066 drm_vblank_pre_modeset(dev, pipe);
6067
6068 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6069
6070 drm_vblank_post_modeset(dev, pipe);
6071
6072 if (ret != 0)
6073 return ret;
6074
6075 for_each_encoder_on_crtc(dev, crtc, encoder) {
6076 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6077 encoder->base.base.id,
6078 drm_get_encoder_name(&encoder->base),
6079 mode->base.id, mode->name);
6080 if (encoder->mode_set) {
6081 encoder->mode_set(encoder);
6082 } else {
6083 encoder_funcs = encoder->base.helper_private;
6084 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6085 }
6086 }
6087
6088 return 0;
6089 }
6090
6091 static bool intel_eld_uptodate(struct drm_connector *connector,
6092 int reg_eldv, uint32_t bits_eldv,
6093 int reg_elda, uint32_t bits_elda,
6094 int reg_edid)
6095 {
6096 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6097 uint8_t *eld = connector->eld;
6098 uint32_t i;
6099
6100 i = I915_READ(reg_eldv);
6101 i &= bits_eldv;
6102
6103 if (!eld[0])
6104 return !i;
6105
6106 if (!i)
6107 return false;
6108
6109 i = I915_READ(reg_elda);
6110 i &= ~bits_elda;
6111 I915_WRITE(reg_elda, i);
6112
6113 for (i = 0; i < eld[2]; i++)
6114 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6115 return false;
6116
6117 return true;
6118 }
6119
6120 static void g4x_write_eld(struct drm_connector *connector,
6121 struct drm_crtc *crtc)
6122 {
6123 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6124 uint8_t *eld = connector->eld;
6125 uint32_t eldv;
6126 uint32_t len;
6127 uint32_t i;
6128
6129 i = I915_READ(G4X_AUD_VID_DID);
6130
6131 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6132 eldv = G4X_ELDV_DEVCL_DEVBLC;
6133 else
6134 eldv = G4X_ELDV_DEVCTG;
6135
6136 if (intel_eld_uptodate(connector,
6137 G4X_AUD_CNTL_ST, eldv,
6138 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6139 G4X_HDMIW_HDMIEDID))
6140 return;
6141
6142 i = I915_READ(G4X_AUD_CNTL_ST);
6143 i &= ~(eldv | G4X_ELD_ADDR);
6144 len = (i >> 9) & 0x1f; /* ELD buffer size */
6145 I915_WRITE(G4X_AUD_CNTL_ST, i);
6146
6147 if (!eld[0])
6148 return;
6149
6150 len = min_t(uint8_t, eld[2], len);
6151 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6152 for (i = 0; i < len; i++)
6153 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6154
6155 i = I915_READ(G4X_AUD_CNTL_ST);
6156 i |= eldv;
6157 I915_WRITE(G4X_AUD_CNTL_ST, i);
6158 }
6159
6160 static void haswell_write_eld(struct drm_connector *connector,
6161 struct drm_crtc *crtc)
6162 {
6163 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6164 uint8_t *eld = connector->eld;
6165 struct drm_device *dev = crtc->dev;
6166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6167 uint32_t eldv;
6168 uint32_t i;
6169 int len;
6170 int pipe = to_intel_crtc(crtc)->pipe;
6171 int tmp;
6172
6173 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6174 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6175 int aud_config = HSW_AUD_CFG(pipe);
6176 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6177
6178
6179 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6180
6181 /* Audio output enable */
6182 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6183 tmp = I915_READ(aud_cntrl_st2);
6184 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6185 I915_WRITE(aud_cntrl_st2, tmp);
6186
6187 /* Wait for 1 vertical blank */
6188 intel_wait_for_vblank(dev, pipe);
6189
6190 /* Set ELD valid state */
6191 tmp = I915_READ(aud_cntrl_st2);
6192 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6193 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6194 I915_WRITE(aud_cntrl_st2, tmp);
6195 tmp = I915_READ(aud_cntrl_st2);
6196 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6197
6198 /* Enable HDMI mode */
6199 tmp = I915_READ(aud_config);
6200 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6201 /* clear N_programing_enable and N_value_index */
6202 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6203 I915_WRITE(aud_config, tmp);
6204
6205 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6206
6207 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6208 intel_crtc->eld_vld = true;
6209
6210 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6211 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6212 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6213 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6214 } else
6215 I915_WRITE(aud_config, 0);
6216
6217 if (intel_eld_uptodate(connector,
6218 aud_cntrl_st2, eldv,
6219 aud_cntl_st, IBX_ELD_ADDRESS,
6220 hdmiw_hdmiedid))
6221 return;
6222
6223 i = I915_READ(aud_cntrl_st2);
6224 i &= ~eldv;
6225 I915_WRITE(aud_cntrl_st2, i);
6226
6227 if (!eld[0])
6228 return;
6229
6230 i = I915_READ(aud_cntl_st);
6231 i &= ~IBX_ELD_ADDRESS;
6232 I915_WRITE(aud_cntl_st, i);
6233 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6234 DRM_DEBUG_DRIVER("port num:%d\n", i);
6235
6236 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6237 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6238 for (i = 0; i < len; i++)
6239 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6240
6241 i = I915_READ(aud_cntrl_st2);
6242 i |= eldv;
6243 I915_WRITE(aud_cntrl_st2, i);
6244
6245 }
6246
6247 static void ironlake_write_eld(struct drm_connector *connector,
6248 struct drm_crtc *crtc)
6249 {
6250 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6251 uint8_t *eld = connector->eld;
6252 uint32_t eldv;
6253 uint32_t i;
6254 int len;
6255 int hdmiw_hdmiedid;
6256 int aud_config;
6257 int aud_cntl_st;
6258 int aud_cntrl_st2;
6259 int pipe = to_intel_crtc(crtc)->pipe;
6260
6261 if (HAS_PCH_IBX(connector->dev)) {
6262 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6263 aud_config = IBX_AUD_CFG(pipe);
6264 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6265 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6266 } else {
6267 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6268 aud_config = CPT_AUD_CFG(pipe);
6269 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6270 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6271 }
6272
6273 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6274
6275 i = I915_READ(aud_cntl_st);
6276 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6277 if (!i) {
6278 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6279 /* operate blindly on all ports */
6280 eldv = IBX_ELD_VALIDB;
6281 eldv |= IBX_ELD_VALIDB << 4;
6282 eldv |= IBX_ELD_VALIDB << 8;
6283 } else {
6284 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6285 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6286 }
6287
6288 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6289 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6290 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6291 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6292 } else
6293 I915_WRITE(aud_config, 0);
6294
6295 if (intel_eld_uptodate(connector,
6296 aud_cntrl_st2, eldv,
6297 aud_cntl_st, IBX_ELD_ADDRESS,
6298 hdmiw_hdmiedid))
6299 return;
6300
6301 i = I915_READ(aud_cntrl_st2);
6302 i &= ~eldv;
6303 I915_WRITE(aud_cntrl_st2, i);
6304
6305 if (!eld[0])
6306 return;
6307
6308 i = I915_READ(aud_cntl_st);
6309 i &= ~IBX_ELD_ADDRESS;
6310 I915_WRITE(aud_cntl_st, i);
6311
6312 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6313 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6314 for (i = 0; i < len; i++)
6315 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6316
6317 i = I915_READ(aud_cntrl_st2);
6318 i |= eldv;
6319 I915_WRITE(aud_cntrl_st2, i);
6320 }
6321
6322 void intel_write_eld(struct drm_encoder *encoder,
6323 struct drm_display_mode *mode)
6324 {
6325 struct drm_crtc *crtc = encoder->crtc;
6326 struct drm_connector *connector;
6327 struct drm_device *dev = encoder->dev;
6328 struct drm_i915_private *dev_priv = dev->dev_private;
6329
6330 connector = drm_select_eld(encoder, mode);
6331 if (!connector)
6332 return;
6333
6334 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6335 connector->base.id,
6336 drm_get_connector_name(connector),
6337 connector->encoder->base.id,
6338 drm_get_encoder_name(connector->encoder));
6339
6340 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6341
6342 if (dev_priv->display.write_eld)
6343 dev_priv->display.write_eld(connector, crtc);
6344 }
6345
6346 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6347 void intel_crtc_load_lut(struct drm_crtc *crtc)
6348 {
6349 struct drm_device *dev = crtc->dev;
6350 struct drm_i915_private *dev_priv = dev->dev_private;
6351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6352 int palreg = PALETTE(intel_crtc->pipe);
6353 int i;
6354
6355 /* The clocks have to be on to load the palette. */
6356 if (!crtc->enabled || !intel_crtc->active)
6357 return;
6358
6359 /* use legacy palette for Ironlake */
6360 if (HAS_PCH_SPLIT(dev))
6361 palreg = LGC_PALETTE(intel_crtc->pipe);
6362
6363 for (i = 0; i < 256; i++) {
6364 I915_WRITE(palreg + 4 * i,
6365 (intel_crtc->lut_r[i] << 16) |
6366 (intel_crtc->lut_g[i] << 8) |
6367 intel_crtc->lut_b[i]);
6368 }
6369 }
6370
6371 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6372 {
6373 struct drm_device *dev = crtc->dev;
6374 struct drm_i915_private *dev_priv = dev->dev_private;
6375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6376 bool visible = base != 0;
6377 u32 cntl;
6378
6379 if (intel_crtc->cursor_visible == visible)
6380 return;
6381
6382 cntl = I915_READ(_CURACNTR);
6383 if (visible) {
6384 /* On these chipsets we can only modify the base whilst
6385 * the cursor is disabled.
6386 */
6387 I915_WRITE(_CURABASE, base);
6388
6389 cntl &= ~(CURSOR_FORMAT_MASK);
6390 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6391 cntl |= CURSOR_ENABLE |
6392 CURSOR_GAMMA_ENABLE |
6393 CURSOR_FORMAT_ARGB;
6394 } else
6395 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6396 I915_WRITE(_CURACNTR, cntl);
6397
6398 intel_crtc->cursor_visible = visible;
6399 }
6400
6401 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6402 {
6403 struct drm_device *dev = crtc->dev;
6404 struct drm_i915_private *dev_priv = dev->dev_private;
6405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406 int pipe = intel_crtc->pipe;
6407 bool visible = base != 0;
6408
6409 if (intel_crtc->cursor_visible != visible) {
6410 uint32_t cntl = I915_READ(CURCNTR(pipe));
6411 if (base) {
6412 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6413 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6414 cntl |= pipe << 28; /* Connect to correct pipe */
6415 } else {
6416 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6417 cntl |= CURSOR_MODE_DISABLE;
6418 }
6419 I915_WRITE(CURCNTR(pipe), cntl);
6420
6421 intel_crtc->cursor_visible = visible;
6422 }
6423 /* and commit changes on next vblank */
6424 I915_WRITE(CURBASE(pipe), base);
6425 }
6426
6427 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6428 {
6429 struct drm_device *dev = crtc->dev;
6430 struct drm_i915_private *dev_priv = dev->dev_private;
6431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6432 int pipe = intel_crtc->pipe;
6433 bool visible = base != 0;
6434
6435 if (intel_crtc->cursor_visible != visible) {
6436 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6437 if (base) {
6438 cntl &= ~CURSOR_MODE;
6439 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6440 } else {
6441 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6442 cntl |= CURSOR_MODE_DISABLE;
6443 }
6444 if (IS_HASWELL(dev))
6445 cntl |= CURSOR_PIPE_CSC_ENABLE;
6446 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6447
6448 intel_crtc->cursor_visible = visible;
6449 }
6450 /* and commit changes on next vblank */
6451 I915_WRITE(CURBASE_IVB(pipe), base);
6452 }
6453
6454 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6455 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6456 bool on)
6457 {
6458 struct drm_device *dev = crtc->dev;
6459 struct drm_i915_private *dev_priv = dev->dev_private;
6460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6461 int pipe = intel_crtc->pipe;
6462 int x = intel_crtc->cursor_x;
6463 int y = intel_crtc->cursor_y;
6464 u32 base, pos;
6465 bool visible;
6466
6467 pos = 0;
6468
6469 if (on && crtc->enabled && crtc->fb) {
6470 base = intel_crtc->cursor_addr;
6471 if (x > (int) crtc->fb->width)
6472 base = 0;
6473
6474 if (y > (int) crtc->fb->height)
6475 base = 0;
6476 } else
6477 base = 0;
6478
6479 if (x < 0) {
6480 if (x + intel_crtc->cursor_width < 0)
6481 base = 0;
6482
6483 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6484 x = -x;
6485 }
6486 pos |= x << CURSOR_X_SHIFT;
6487
6488 if (y < 0) {
6489 if (y + intel_crtc->cursor_height < 0)
6490 base = 0;
6491
6492 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6493 y = -y;
6494 }
6495 pos |= y << CURSOR_Y_SHIFT;
6496
6497 visible = base != 0;
6498 if (!visible && !intel_crtc->cursor_visible)
6499 return;
6500
6501 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6502 I915_WRITE(CURPOS_IVB(pipe), pos);
6503 ivb_update_cursor(crtc, base);
6504 } else {
6505 I915_WRITE(CURPOS(pipe), pos);
6506 if (IS_845G(dev) || IS_I865G(dev))
6507 i845_update_cursor(crtc, base);
6508 else
6509 i9xx_update_cursor(crtc, base);
6510 }
6511 }
6512
6513 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6514 struct drm_file *file,
6515 uint32_t handle,
6516 uint32_t width, uint32_t height)
6517 {
6518 struct drm_device *dev = crtc->dev;
6519 struct drm_i915_private *dev_priv = dev->dev_private;
6520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6521 struct drm_i915_gem_object *obj;
6522 uint32_t addr;
6523 int ret;
6524
6525 /* if we want to turn off the cursor ignore width and height */
6526 if (!handle) {
6527 DRM_DEBUG_KMS("cursor off\n");
6528 addr = 0;
6529 obj = NULL;
6530 mutex_lock(&dev->struct_mutex);
6531 goto finish;
6532 }
6533
6534 /* Currently we only support 64x64 cursors */
6535 if (width != 64 || height != 64) {
6536 DRM_ERROR("we currently only support 64x64 cursors\n");
6537 return -EINVAL;
6538 }
6539
6540 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6541 if (&obj->base == NULL)
6542 return -ENOENT;
6543
6544 if (obj->base.size < width * height * 4) {
6545 DRM_ERROR("buffer is to small\n");
6546 ret = -ENOMEM;
6547 goto fail;
6548 }
6549
6550 /* we only need to pin inside GTT if cursor is non-phy */
6551 mutex_lock(&dev->struct_mutex);
6552 if (!dev_priv->info->cursor_needs_physical) {
6553 unsigned alignment;
6554
6555 if (obj->tiling_mode) {
6556 DRM_ERROR("cursor cannot be tiled\n");
6557 ret = -EINVAL;
6558 goto fail_locked;
6559 }
6560
6561 /* Note that the w/a also requires 2 PTE of padding following
6562 * the bo. We currently fill all unused PTE with the shadow
6563 * page and so we should always have valid PTE following the
6564 * cursor preventing the VT-d warning.
6565 */
6566 alignment = 0;
6567 if (need_vtd_wa(dev))
6568 alignment = 64*1024;
6569
6570 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6571 if (ret) {
6572 DRM_ERROR("failed to move cursor bo into the GTT\n");
6573 goto fail_locked;
6574 }
6575
6576 ret = i915_gem_object_put_fence(obj);
6577 if (ret) {
6578 DRM_ERROR("failed to release fence for cursor");
6579 goto fail_unpin;
6580 }
6581
6582 addr = obj->gtt_offset;
6583 } else {
6584 int align = IS_I830(dev) ? 16 * 1024 : 256;
6585 ret = i915_gem_attach_phys_object(dev, obj,
6586 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6587 align);
6588 if (ret) {
6589 DRM_ERROR("failed to attach phys object\n");
6590 goto fail_locked;
6591 }
6592 addr = obj->phys_obj->handle->busaddr;
6593 }
6594
6595 if (IS_GEN2(dev))
6596 I915_WRITE(CURSIZE, (height << 12) | width);
6597
6598 finish:
6599 if (intel_crtc->cursor_bo) {
6600 if (dev_priv->info->cursor_needs_physical) {
6601 if (intel_crtc->cursor_bo != obj)
6602 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6603 } else
6604 i915_gem_object_unpin(intel_crtc->cursor_bo);
6605 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6606 }
6607
6608 mutex_unlock(&dev->struct_mutex);
6609
6610 intel_crtc->cursor_addr = addr;
6611 intel_crtc->cursor_bo = obj;
6612 intel_crtc->cursor_width = width;
6613 intel_crtc->cursor_height = height;
6614
6615 intel_crtc_update_cursor(crtc, true);
6616
6617 return 0;
6618 fail_unpin:
6619 i915_gem_object_unpin(obj);
6620 fail_locked:
6621 mutex_unlock(&dev->struct_mutex);
6622 fail:
6623 drm_gem_object_unreference_unlocked(&obj->base);
6624 return ret;
6625 }
6626
6627 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6628 {
6629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6630
6631 intel_crtc->cursor_x = x;
6632 intel_crtc->cursor_y = y;
6633
6634 intel_crtc_update_cursor(crtc, true);
6635
6636 return 0;
6637 }
6638
6639 /** Sets the color ramps on behalf of RandR */
6640 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6641 u16 blue, int regno)
6642 {
6643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6644
6645 intel_crtc->lut_r[regno] = red >> 8;
6646 intel_crtc->lut_g[regno] = green >> 8;
6647 intel_crtc->lut_b[regno] = blue >> 8;
6648 }
6649
6650 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6651 u16 *blue, int regno)
6652 {
6653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654
6655 *red = intel_crtc->lut_r[regno] << 8;
6656 *green = intel_crtc->lut_g[regno] << 8;
6657 *blue = intel_crtc->lut_b[regno] << 8;
6658 }
6659
6660 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6661 u16 *blue, uint32_t start, uint32_t size)
6662 {
6663 int end = (start + size > 256) ? 256 : start + size, i;
6664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6665
6666 for (i = start; i < end; i++) {
6667 intel_crtc->lut_r[i] = red[i] >> 8;
6668 intel_crtc->lut_g[i] = green[i] >> 8;
6669 intel_crtc->lut_b[i] = blue[i] >> 8;
6670 }
6671
6672 intel_crtc_load_lut(crtc);
6673 }
6674
6675 /* VESA 640x480x72Hz mode to set on the pipe */
6676 static struct drm_display_mode load_detect_mode = {
6677 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6678 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6679 };
6680
6681 static struct drm_framebuffer *
6682 intel_framebuffer_create(struct drm_device *dev,
6683 struct drm_mode_fb_cmd2 *mode_cmd,
6684 struct drm_i915_gem_object *obj)
6685 {
6686 struct intel_framebuffer *intel_fb;
6687 int ret;
6688
6689 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6690 if (!intel_fb) {
6691 drm_gem_object_unreference_unlocked(&obj->base);
6692 return ERR_PTR(-ENOMEM);
6693 }
6694
6695 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6696 if (ret) {
6697 drm_gem_object_unreference_unlocked(&obj->base);
6698 kfree(intel_fb);
6699 return ERR_PTR(ret);
6700 }
6701
6702 return &intel_fb->base;
6703 }
6704
6705 static u32
6706 intel_framebuffer_pitch_for_width(int width, int bpp)
6707 {
6708 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6709 return ALIGN(pitch, 64);
6710 }
6711
6712 static u32
6713 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6714 {
6715 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6716 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6717 }
6718
6719 static struct drm_framebuffer *
6720 intel_framebuffer_create_for_mode(struct drm_device *dev,
6721 struct drm_display_mode *mode,
6722 int depth, int bpp)
6723 {
6724 struct drm_i915_gem_object *obj;
6725 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6726
6727 obj = i915_gem_alloc_object(dev,
6728 intel_framebuffer_size_for_mode(mode, bpp));
6729 if (obj == NULL)
6730 return ERR_PTR(-ENOMEM);
6731
6732 mode_cmd.width = mode->hdisplay;
6733 mode_cmd.height = mode->vdisplay;
6734 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6735 bpp);
6736 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6737
6738 return intel_framebuffer_create(dev, &mode_cmd, obj);
6739 }
6740
6741 static struct drm_framebuffer *
6742 mode_fits_in_fbdev(struct drm_device *dev,
6743 struct drm_display_mode *mode)
6744 {
6745 struct drm_i915_private *dev_priv = dev->dev_private;
6746 struct drm_i915_gem_object *obj;
6747 struct drm_framebuffer *fb;
6748
6749 if (dev_priv->fbdev == NULL)
6750 return NULL;
6751
6752 obj = dev_priv->fbdev->ifb.obj;
6753 if (obj == NULL)
6754 return NULL;
6755
6756 fb = &dev_priv->fbdev->ifb.base;
6757 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6758 fb->bits_per_pixel))
6759 return NULL;
6760
6761 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6762 return NULL;
6763
6764 return fb;
6765 }
6766
6767 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6768 struct drm_display_mode *mode,
6769 struct intel_load_detect_pipe *old)
6770 {
6771 struct intel_crtc *intel_crtc;
6772 struct intel_encoder *intel_encoder =
6773 intel_attached_encoder(connector);
6774 struct drm_crtc *possible_crtc;
6775 struct drm_encoder *encoder = &intel_encoder->base;
6776 struct drm_crtc *crtc = NULL;
6777 struct drm_device *dev = encoder->dev;
6778 struct drm_framebuffer *fb;
6779 int i = -1;
6780
6781 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6782 connector->base.id, drm_get_connector_name(connector),
6783 encoder->base.id, drm_get_encoder_name(encoder));
6784
6785 /*
6786 * Algorithm gets a little messy:
6787 *
6788 * - if the connector already has an assigned crtc, use it (but make
6789 * sure it's on first)
6790 *
6791 * - try to find the first unused crtc that can drive this connector,
6792 * and use that if we find one
6793 */
6794
6795 /* See if we already have a CRTC for this connector */
6796 if (encoder->crtc) {
6797 crtc = encoder->crtc;
6798
6799 mutex_lock(&crtc->mutex);
6800
6801 old->dpms_mode = connector->dpms;
6802 old->load_detect_temp = false;
6803
6804 /* Make sure the crtc and connector are running */
6805 if (connector->dpms != DRM_MODE_DPMS_ON)
6806 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6807
6808 return true;
6809 }
6810
6811 /* Find an unused one (if possible) */
6812 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6813 i++;
6814 if (!(encoder->possible_crtcs & (1 << i)))
6815 continue;
6816 if (!possible_crtc->enabled) {
6817 crtc = possible_crtc;
6818 break;
6819 }
6820 }
6821
6822 /*
6823 * If we didn't find an unused CRTC, don't use any.
6824 */
6825 if (!crtc) {
6826 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6827 return false;
6828 }
6829
6830 mutex_lock(&crtc->mutex);
6831 intel_encoder->new_crtc = to_intel_crtc(crtc);
6832 to_intel_connector(connector)->new_encoder = intel_encoder;
6833
6834 intel_crtc = to_intel_crtc(crtc);
6835 old->dpms_mode = connector->dpms;
6836 old->load_detect_temp = true;
6837 old->release_fb = NULL;
6838
6839 if (!mode)
6840 mode = &load_detect_mode;
6841
6842 /* We need a framebuffer large enough to accommodate all accesses
6843 * that the plane may generate whilst we perform load detection.
6844 * We can not rely on the fbcon either being present (we get called
6845 * during its initialisation to detect all boot displays, or it may
6846 * not even exist) or that it is large enough to satisfy the
6847 * requested mode.
6848 */
6849 fb = mode_fits_in_fbdev(dev, mode);
6850 if (fb == NULL) {
6851 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6852 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6853 old->release_fb = fb;
6854 } else
6855 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6856 if (IS_ERR(fb)) {
6857 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6858 mutex_unlock(&crtc->mutex);
6859 return false;
6860 }
6861
6862 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6863 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6864 if (old->release_fb)
6865 old->release_fb->funcs->destroy(old->release_fb);
6866 mutex_unlock(&crtc->mutex);
6867 return false;
6868 }
6869
6870 /* let the connector get through one full cycle before testing */
6871 intel_wait_for_vblank(dev, intel_crtc->pipe);
6872 return true;
6873 }
6874
6875 void intel_release_load_detect_pipe(struct drm_connector *connector,
6876 struct intel_load_detect_pipe *old)
6877 {
6878 struct intel_encoder *intel_encoder =
6879 intel_attached_encoder(connector);
6880 struct drm_encoder *encoder = &intel_encoder->base;
6881 struct drm_crtc *crtc = encoder->crtc;
6882
6883 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6884 connector->base.id, drm_get_connector_name(connector),
6885 encoder->base.id, drm_get_encoder_name(encoder));
6886
6887 if (old->load_detect_temp) {
6888 to_intel_connector(connector)->new_encoder = NULL;
6889 intel_encoder->new_crtc = NULL;
6890 intel_set_mode(crtc, NULL, 0, 0, NULL);
6891
6892 if (old->release_fb) {
6893 drm_framebuffer_unregister_private(old->release_fb);
6894 drm_framebuffer_unreference(old->release_fb);
6895 }
6896
6897 mutex_unlock(&crtc->mutex);
6898 return;
6899 }
6900
6901 /* Switch crtc and encoder back off if necessary */
6902 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6903 connector->funcs->dpms(connector, old->dpms_mode);
6904
6905 mutex_unlock(&crtc->mutex);
6906 }
6907
6908 /* Returns the clock of the currently programmed mode of the given pipe. */
6909 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6910 {
6911 struct drm_i915_private *dev_priv = dev->dev_private;
6912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6913 int pipe = intel_crtc->pipe;
6914 u32 dpll = I915_READ(DPLL(pipe));
6915 u32 fp;
6916 intel_clock_t clock;
6917
6918 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6919 fp = I915_READ(FP0(pipe));
6920 else
6921 fp = I915_READ(FP1(pipe));
6922
6923 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6924 if (IS_PINEVIEW(dev)) {
6925 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6926 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6927 } else {
6928 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6929 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6930 }
6931
6932 if (!IS_GEN2(dev)) {
6933 if (IS_PINEVIEW(dev))
6934 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6935 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6936 else
6937 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6938 DPLL_FPA01_P1_POST_DIV_SHIFT);
6939
6940 switch (dpll & DPLL_MODE_MASK) {
6941 case DPLLB_MODE_DAC_SERIAL:
6942 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6943 5 : 10;
6944 break;
6945 case DPLLB_MODE_LVDS:
6946 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6947 7 : 14;
6948 break;
6949 default:
6950 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6951 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6952 return 0;
6953 }
6954
6955 /* XXX: Handle the 100Mhz refclk */
6956 intel_clock(dev, 96000, &clock);
6957 } else {
6958 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6959
6960 if (is_lvds) {
6961 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6962 DPLL_FPA01_P1_POST_DIV_SHIFT);
6963 clock.p2 = 14;
6964
6965 if ((dpll & PLL_REF_INPUT_MASK) ==
6966 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6967 /* XXX: might not be 66MHz */
6968 intel_clock(dev, 66000, &clock);
6969 } else
6970 intel_clock(dev, 48000, &clock);
6971 } else {
6972 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6973 clock.p1 = 2;
6974 else {
6975 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6976 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6977 }
6978 if (dpll & PLL_P2_DIVIDE_BY_4)
6979 clock.p2 = 4;
6980 else
6981 clock.p2 = 2;
6982
6983 intel_clock(dev, 48000, &clock);
6984 }
6985 }
6986
6987 /* XXX: It would be nice to validate the clocks, but we can't reuse
6988 * i830PllIsValid() because it relies on the xf86_config connector
6989 * configuration being accurate, which it isn't necessarily.
6990 */
6991
6992 return clock.dot;
6993 }
6994
6995 /** Returns the currently programmed mode of the given pipe. */
6996 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6997 struct drm_crtc *crtc)
6998 {
6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7001 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7002 struct drm_display_mode *mode;
7003 int htot = I915_READ(HTOTAL(cpu_transcoder));
7004 int hsync = I915_READ(HSYNC(cpu_transcoder));
7005 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7006 int vsync = I915_READ(VSYNC(cpu_transcoder));
7007
7008 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7009 if (!mode)
7010 return NULL;
7011
7012 mode->clock = intel_crtc_clock_get(dev, crtc);
7013 mode->hdisplay = (htot & 0xffff) + 1;
7014 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7015 mode->hsync_start = (hsync & 0xffff) + 1;
7016 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7017 mode->vdisplay = (vtot & 0xffff) + 1;
7018 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7019 mode->vsync_start = (vsync & 0xffff) + 1;
7020 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7021
7022 drm_mode_set_name(mode);
7023
7024 return mode;
7025 }
7026
7027 static void intel_increase_pllclock(struct drm_crtc *crtc)
7028 {
7029 struct drm_device *dev = crtc->dev;
7030 drm_i915_private_t *dev_priv = dev->dev_private;
7031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7032 int pipe = intel_crtc->pipe;
7033 int dpll_reg = DPLL(pipe);
7034 int dpll;
7035
7036 if (HAS_PCH_SPLIT(dev))
7037 return;
7038
7039 if (!dev_priv->lvds_downclock_avail)
7040 return;
7041
7042 dpll = I915_READ(dpll_reg);
7043 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7044 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7045
7046 assert_panel_unlocked(dev_priv, pipe);
7047
7048 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7049 I915_WRITE(dpll_reg, dpll);
7050 intel_wait_for_vblank(dev, pipe);
7051
7052 dpll = I915_READ(dpll_reg);
7053 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7054 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7055 }
7056 }
7057
7058 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7059 {
7060 struct drm_device *dev = crtc->dev;
7061 drm_i915_private_t *dev_priv = dev->dev_private;
7062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7063
7064 if (HAS_PCH_SPLIT(dev))
7065 return;
7066
7067 if (!dev_priv->lvds_downclock_avail)
7068 return;
7069
7070 /*
7071 * Since this is called by a timer, we should never get here in
7072 * the manual case.
7073 */
7074 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7075 int pipe = intel_crtc->pipe;
7076 int dpll_reg = DPLL(pipe);
7077 int dpll;
7078
7079 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7080
7081 assert_panel_unlocked(dev_priv, pipe);
7082
7083 dpll = I915_READ(dpll_reg);
7084 dpll |= DISPLAY_RATE_SELECT_FPA1;
7085 I915_WRITE(dpll_reg, dpll);
7086 intel_wait_for_vblank(dev, pipe);
7087 dpll = I915_READ(dpll_reg);
7088 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7089 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7090 }
7091
7092 }
7093
7094 void intel_mark_busy(struct drm_device *dev)
7095 {
7096 i915_update_gfx_val(dev->dev_private);
7097 }
7098
7099 void intel_mark_idle(struct drm_device *dev)
7100 {
7101 struct drm_crtc *crtc;
7102
7103 if (!i915_powersave)
7104 return;
7105
7106 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7107 if (!crtc->fb)
7108 continue;
7109
7110 intel_decrease_pllclock(crtc);
7111 }
7112 }
7113
7114 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7115 {
7116 struct drm_device *dev = obj->base.dev;
7117 struct drm_crtc *crtc;
7118
7119 if (!i915_powersave)
7120 return;
7121
7122 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7123 if (!crtc->fb)
7124 continue;
7125
7126 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7127 intel_increase_pllclock(crtc);
7128 }
7129 }
7130
7131 static void intel_crtc_destroy(struct drm_crtc *crtc)
7132 {
7133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7134 struct drm_device *dev = crtc->dev;
7135 struct intel_unpin_work *work;
7136 unsigned long flags;
7137
7138 spin_lock_irqsave(&dev->event_lock, flags);
7139 work = intel_crtc->unpin_work;
7140 intel_crtc->unpin_work = NULL;
7141 spin_unlock_irqrestore(&dev->event_lock, flags);
7142
7143 if (work) {
7144 cancel_work_sync(&work->work);
7145 kfree(work);
7146 }
7147
7148 drm_crtc_cleanup(crtc);
7149
7150 kfree(intel_crtc);
7151 }
7152
7153 static void intel_unpin_work_fn(struct work_struct *__work)
7154 {
7155 struct intel_unpin_work *work =
7156 container_of(__work, struct intel_unpin_work, work);
7157 struct drm_device *dev = work->crtc->dev;
7158
7159 mutex_lock(&dev->struct_mutex);
7160 intel_unpin_fb_obj(work->old_fb_obj);
7161 drm_gem_object_unreference(&work->pending_flip_obj->base);
7162 drm_gem_object_unreference(&work->old_fb_obj->base);
7163
7164 intel_update_fbc(dev);
7165 mutex_unlock(&dev->struct_mutex);
7166
7167 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7168 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7169
7170 kfree(work);
7171 }
7172
7173 static void do_intel_finish_page_flip(struct drm_device *dev,
7174 struct drm_crtc *crtc)
7175 {
7176 drm_i915_private_t *dev_priv = dev->dev_private;
7177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7178 struct intel_unpin_work *work;
7179 unsigned long flags;
7180
7181 /* Ignore early vblank irqs */
7182 if (intel_crtc == NULL)
7183 return;
7184
7185 spin_lock_irqsave(&dev->event_lock, flags);
7186 work = intel_crtc->unpin_work;
7187
7188 /* Ensure we don't miss a work->pending update ... */
7189 smp_rmb();
7190
7191 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7192 spin_unlock_irqrestore(&dev->event_lock, flags);
7193 return;
7194 }
7195
7196 /* and that the unpin work is consistent wrt ->pending. */
7197 smp_rmb();
7198
7199 intel_crtc->unpin_work = NULL;
7200
7201 if (work->event)
7202 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7203
7204 drm_vblank_put(dev, intel_crtc->pipe);
7205
7206 spin_unlock_irqrestore(&dev->event_lock, flags);
7207
7208 wake_up_all(&dev_priv->pending_flip_queue);
7209
7210 queue_work(dev_priv->wq, &work->work);
7211
7212 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7213 }
7214
7215 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7216 {
7217 drm_i915_private_t *dev_priv = dev->dev_private;
7218 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7219
7220 do_intel_finish_page_flip(dev, crtc);
7221 }
7222
7223 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7224 {
7225 drm_i915_private_t *dev_priv = dev->dev_private;
7226 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7227
7228 do_intel_finish_page_flip(dev, crtc);
7229 }
7230
7231 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7232 {
7233 drm_i915_private_t *dev_priv = dev->dev_private;
7234 struct intel_crtc *intel_crtc =
7235 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7236 unsigned long flags;
7237
7238 /* NB: An MMIO update of the plane base pointer will also
7239 * generate a page-flip completion irq, i.e. every modeset
7240 * is also accompanied by a spurious intel_prepare_page_flip().
7241 */
7242 spin_lock_irqsave(&dev->event_lock, flags);
7243 if (intel_crtc->unpin_work)
7244 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7245 spin_unlock_irqrestore(&dev->event_lock, flags);
7246 }
7247
7248 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7249 {
7250 /* Ensure that the work item is consistent when activating it ... */
7251 smp_wmb();
7252 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7253 /* and that it is marked active as soon as the irq could fire. */
7254 smp_wmb();
7255 }
7256
7257 static int intel_gen2_queue_flip(struct drm_device *dev,
7258 struct drm_crtc *crtc,
7259 struct drm_framebuffer *fb,
7260 struct drm_i915_gem_object *obj)
7261 {
7262 struct drm_i915_private *dev_priv = dev->dev_private;
7263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7264 u32 flip_mask;
7265 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7266 int ret;
7267
7268 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7269 if (ret)
7270 goto err;
7271
7272 ret = intel_ring_begin(ring, 6);
7273 if (ret)
7274 goto err_unpin;
7275
7276 /* Can't queue multiple flips, so wait for the previous
7277 * one to finish before executing the next.
7278 */
7279 if (intel_crtc->plane)
7280 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7281 else
7282 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7283 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7284 intel_ring_emit(ring, MI_NOOP);
7285 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7286 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7287 intel_ring_emit(ring, fb->pitches[0]);
7288 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7289 intel_ring_emit(ring, 0); /* aux display base address, unused */
7290
7291 intel_mark_page_flip_active(intel_crtc);
7292 intel_ring_advance(ring);
7293 return 0;
7294
7295 err_unpin:
7296 intel_unpin_fb_obj(obj);
7297 err:
7298 return ret;
7299 }
7300
7301 static int intel_gen3_queue_flip(struct drm_device *dev,
7302 struct drm_crtc *crtc,
7303 struct drm_framebuffer *fb,
7304 struct drm_i915_gem_object *obj)
7305 {
7306 struct drm_i915_private *dev_priv = dev->dev_private;
7307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7308 u32 flip_mask;
7309 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7310 int ret;
7311
7312 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7313 if (ret)
7314 goto err;
7315
7316 ret = intel_ring_begin(ring, 6);
7317 if (ret)
7318 goto err_unpin;
7319
7320 if (intel_crtc->plane)
7321 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7322 else
7323 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7324 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7325 intel_ring_emit(ring, MI_NOOP);
7326 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7327 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7328 intel_ring_emit(ring, fb->pitches[0]);
7329 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7330 intel_ring_emit(ring, MI_NOOP);
7331
7332 intel_mark_page_flip_active(intel_crtc);
7333 intel_ring_advance(ring);
7334 return 0;
7335
7336 err_unpin:
7337 intel_unpin_fb_obj(obj);
7338 err:
7339 return ret;
7340 }
7341
7342 static int intel_gen4_queue_flip(struct drm_device *dev,
7343 struct drm_crtc *crtc,
7344 struct drm_framebuffer *fb,
7345 struct drm_i915_gem_object *obj)
7346 {
7347 struct drm_i915_private *dev_priv = dev->dev_private;
7348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7349 uint32_t pf, pipesrc;
7350 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7351 int ret;
7352
7353 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7354 if (ret)
7355 goto err;
7356
7357 ret = intel_ring_begin(ring, 4);
7358 if (ret)
7359 goto err_unpin;
7360
7361 /* i965+ uses the linear or tiled offsets from the
7362 * Display Registers (which do not change across a page-flip)
7363 * so we need only reprogram the base address.
7364 */
7365 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7366 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7367 intel_ring_emit(ring, fb->pitches[0]);
7368 intel_ring_emit(ring,
7369 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7370 obj->tiling_mode);
7371
7372 /* XXX Enabling the panel-fitter across page-flip is so far
7373 * untested on non-native modes, so ignore it for now.
7374 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7375 */
7376 pf = 0;
7377 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7378 intel_ring_emit(ring, pf | pipesrc);
7379
7380 intel_mark_page_flip_active(intel_crtc);
7381 intel_ring_advance(ring);
7382 return 0;
7383
7384 err_unpin:
7385 intel_unpin_fb_obj(obj);
7386 err:
7387 return ret;
7388 }
7389
7390 static int intel_gen6_queue_flip(struct drm_device *dev,
7391 struct drm_crtc *crtc,
7392 struct drm_framebuffer *fb,
7393 struct drm_i915_gem_object *obj)
7394 {
7395 struct drm_i915_private *dev_priv = dev->dev_private;
7396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7397 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7398 uint32_t pf, pipesrc;
7399 int ret;
7400
7401 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7402 if (ret)
7403 goto err;
7404
7405 ret = intel_ring_begin(ring, 4);
7406 if (ret)
7407 goto err_unpin;
7408
7409 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7410 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7411 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7412 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7413
7414 /* Contrary to the suggestions in the documentation,
7415 * "Enable Panel Fitter" does not seem to be required when page
7416 * flipping with a non-native mode, and worse causes a normal
7417 * modeset to fail.
7418 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7419 */
7420 pf = 0;
7421 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7422 intel_ring_emit(ring, pf | pipesrc);
7423
7424 intel_mark_page_flip_active(intel_crtc);
7425 intel_ring_advance(ring);
7426 return 0;
7427
7428 err_unpin:
7429 intel_unpin_fb_obj(obj);
7430 err:
7431 return ret;
7432 }
7433
7434 /*
7435 * On gen7 we currently use the blit ring because (in early silicon at least)
7436 * the render ring doesn't give us interrpts for page flip completion, which
7437 * means clients will hang after the first flip is queued. Fortunately the
7438 * blit ring generates interrupts properly, so use it instead.
7439 */
7440 static int intel_gen7_queue_flip(struct drm_device *dev,
7441 struct drm_crtc *crtc,
7442 struct drm_framebuffer *fb,
7443 struct drm_i915_gem_object *obj)
7444 {
7445 struct drm_i915_private *dev_priv = dev->dev_private;
7446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7447 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7448 uint32_t plane_bit = 0;
7449 int ret;
7450
7451 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7452 if (ret)
7453 goto err;
7454
7455 switch(intel_crtc->plane) {
7456 case PLANE_A:
7457 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7458 break;
7459 case PLANE_B:
7460 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7461 break;
7462 case PLANE_C:
7463 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7464 break;
7465 default:
7466 WARN_ONCE(1, "unknown plane in flip command\n");
7467 ret = -ENODEV;
7468 goto err_unpin;
7469 }
7470
7471 ret = intel_ring_begin(ring, 4);
7472 if (ret)
7473 goto err_unpin;
7474
7475 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7476 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7477 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7478 intel_ring_emit(ring, (MI_NOOP));
7479
7480 intel_mark_page_flip_active(intel_crtc);
7481 intel_ring_advance(ring);
7482 return 0;
7483
7484 err_unpin:
7485 intel_unpin_fb_obj(obj);
7486 err:
7487 return ret;
7488 }
7489
7490 static int intel_default_queue_flip(struct drm_device *dev,
7491 struct drm_crtc *crtc,
7492 struct drm_framebuffer *fb,
7493 struct drm_i915_gem_object *obj)
7494 {
7495 return -ENODEV;
7496 }
7497
7498 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7499 struct drm_framebuffer *fb,
7500 struct drm_pending_vblank_event *event)
7501 {
7502 struct drm_device *dev = crtc->dev;
7503 struct drm_i915_private *dev_priv = dev->dev_private;
7504 struct drm_framebuffer *old_fb = crtc->fb;
7505 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7507 struct intel_unpin_work *work;
7508 unsigned long flags;
7509 int ret;
7510
7511 /* Can't change pixel format via MI display flips. */
7512 if (fb->pixel_format != crtc->fb->pixel_format)
7513 return -EINVAL;
7514
7515 /*
7516 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7517 * Note that pitch changes could also affect these register.
7518 */
7519 if (INTEL_INFO(dev)->gen > 3 &&
7520 (fb->offsets[0] != crtc->fb->offsets[0] ||
7521 fb->pitches[0] != crtc->fb->pitches[0]))
7522 return -EINVAL;
7523
7524 work = kzalloc(sizeof *work, GFP_KERNEL);
7525 if (work == NULL)
7526 return -ENOMEM;
7527
7528 work->event = event;
7529 work->crtc = crtc;
7530 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7531 INIT_WORK(&work->work, intel_unpin_work_fn);
7532
7533 ret = drm_vblank_get(dev, intel_crtc->pipe);
7534 if (ret)
7535 goto free_work;
7536
7537 /* We borrow the event spin lock for protecting unpin_work */
7538 spin_lock_irqsave(&dev->event_lock, flags);
7539 if (intel_crtc->unpin_work) {
7540 spin_unlock_irqrestore(&dev->event_lock, flags);
7541 kfree(work);
7542 drm_vblank_put(dev, intel_crtc->pipe);
7543
7544 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7545 return -EBUSY;
7546 }
7547 intel_crtc->unpin_work = work;
7548 spin_unlock_irqrestore(&dev->event_lock, flags);
7549
7550 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7551 flush_workqueue(dev_priv->wq);
7552
7553 ret = i915_mutex_lock_interruptible(dev);
7554 if (ret)
7555 goto cleanup;
7556
7557 /* Reference the objects for the scheduled work. */
7558 drm_gem_object_reference(&work->old_fb_obj->base);
7559 drm_gem_object_reference(&obj->base);
7560
7561 crtc->fb = fb;
7562
7563 work->pending_flip_obj = obj;
7564
7565 work->enable_stall_check = true;
7566
7567 atomic_inc(&intel_crtc->unpin_work_count);
7568 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7569
7570 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7571 if (ret)
7572 goto cleanup_pending;
7573
7574 intel_disable_fbc(dev);
7575 intel_mark_fb_busy(obj);
7576 mutex_unlock(&dev->struct_mutex);
7577
7578 trace_i915_flip_request(intel_crtc->plane, obj);
7579
7580 return 0;
7581
7582 cleanup_pending:
7583 atomic_dec(&intel_crtc->unpin_work_count);
7584 crtc->fb = old_fb;
7585 drm_gem_object_unreference(&work->old_fb_obj->base);
7586 drm_gem_object_unreference(&obj->base);
7587 mutex_unlock(&dev->struct_mutex);
7588
7589 cleanup:
7590 spin_lock_irqsave(&dev->event_lock, flags);
7591 intel_crtc->unpin_work = NULL;
7592 spin_unlock_irqrestore(&dev->event_lock, flags);
7593
7594 drm_vblank_put(dev, intel_crtc->pipe);
7595 free_work:
7596 kfree(work);
7597
7598 return ret;
7599 }
7600
7601 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7602 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7603 .load_lut = intel_crtc_load_lut,
7604 };
7605
7606 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7607 {
7608 struct intel_encoder *other_encoder;
7609 struct drm_crtc *crtc = &encoder->new_crtc->base;
7610
7611 if (WARN_ON(!crtc))
7612 return false;
7613
7614 list_for_each_entry(other_encoder,
7615 &crtc->dev->mode_config.encoder_list,
7616 base.head) {
7617
7618 if (&other_encoder->new_crtc->base != crtc ||
7619 encoder == other_encoder)
7620 continue;
7621 else
7622 return true;
7623 }
7624
7625 return false;
7626 }
7627
7628 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7629 struct drm_crtc *crtc)
7630 {
7631 struct drm_device *dev;
7632 struct drm_crtc *tmp;
7633 int crtc_mask = 1;
7634
7635 WARN(!crtc, "checking null crtc?\n");
7636
7637 dev = crtc->dev;
7638
7639 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7640 if (tmp == crtc)
7641 break;
7642 crtc_mask <<= 1;
7643 }
7644
7645 if (encoder->possible_crtcs & crtc_mask)
7646 return true;
7647 return false;
7648 }
7649
7650 /**
7651 * intel_modeset_update_staged_output_state
7652 *
7653 * Updates the staged output configuration state, e.g. after we've read out the
7654 * current hw state.
7655 */
7656 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7657 {
7658 struct intel_encoder *encoder;
7659 struct intel_connector *connector;
7660
7661 list_for_each_entry(connector, &dev->mode_config.connector_list,
7662 base.head) {
7663 connector->new_encoder =
7664 to_intel_encoder(connector->base.encoder);
7665 }
7666
7667 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7668 base.head) {
7669 encoder->new_crtc =
7670 to_intel_crtc(encoder->base.crtc);
7671 }
7672 }
7673
7674 /**
7675 * intel_modeset_commit_output_state
7676 *
7677 * This function copies the stage display pipe configuration to the real one.
7678 */
7679 static void intel_modeset_commit_output_state(struct drm_device *dev)
7680 {
7681 struct intel_encoder *encoder;
7682 struct intel_connector *connector;
7683
7684 list_for_each_entry(connector, &dev->mode_config.connector_list,
7685 base.head) {
7686 connector->base.encoder = &connector->new_encoder->base;
7687 }
7688
7689 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7690 base.head) {
7691 encoder->base.crtc = &encoder->new_crtc->base;
7692 }
7693 }
7694
7695 static int
7696 pipe_config_set_bpp(struct drm_crtc *crtc,
7697 struct drm_framebuffer *fb,
7698 struct intel_crtc_config *pipe_config)
7699 {
7700 struct drm_device *dev = crtc->dev;
7701 struct drm_connector *connector;
7702 int bpp;
7703
7704 switch (fb->pixel_format) {
7705 case DRM_FORMAT_C8:
7706 bpp = 8*3; /* since we go through a colormap */
7707 break;
7708 case DRM_FORMAT_XRGB1555:
7709 case DRM_FORMAT_ARGB1555:
7710 /* checked in intel_framebuffer_init already */
7711 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7712 return -EINVAL;
7713 case DRM_FORMAT_RGB565:
7714 bpp = 6*3; /* min is 18bpp */
7715 break;
7716 case DRM_FORMAT_XBGR8888:
7717 case DRM_FORMAT_ABGR8888:
7718 /* checked in intel_framebuffer_init already */
7719 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7720 return -EINVAL;
7721 case DRM_FORMAT_XRGB8888:
7722 case DRM_FORMAT_ARGB8888:
7723 bpp = 8*3;
7724 break;
7725 case DRM_FORMAT_XRGB2101010:
7726 case DRM_FORMAT_ARGB2101010:
7727 case DRM_FORMAT_XBGR2101010:
7728 case DRM_FORMAT_ABGR2101010:
7729 /* checked in intel_framebuffer_init already */
7730 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7731 return -EINVAL;
7732 bpp = 10*3;
7733 break;
7734 /* TODO: gen4+ supports 16 bpc floating point, too. */
7735 default:
7736 DRM_DEBUG_KMS("unsupported depth\n");
7737 return -EINVAL;
7738 }
7739
7740 pipe_config->pipe_bpp = bpp;
7741
7742 /* Clamp display bpp to EDID value */
7743 list_for_each_entry(connector, &dev->mode_config.connector_list,
7744 head) {
7745 if (connector->encoder && connector->encoder->crtc != crtc)
7746 continue;
7747
7748 /* Don't use an invalid EDID bpc value */
7749 if (connector->display_info.bpc &&
7750 connector->display_info.bpc * 3 < bpp) {
7751 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7752 bpp, connector->display_info.bpc*3);
7753 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7754 }
7755
7756 /* Clamp bpp to 8 on screens without EDID 1.4 */
7757 if (connector->display_info.bpc == 0 && bpp > 24) {
7758 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7759 bpp);
7760 pipe_config->pipe_bpp = 24;
7761 }
7762 }
7763
7764 return bpp;
7765 }
7766
7767 static struct intel_crtc_config *
7768 intel_modeset_pipe_config(struct drm_crtc *crtc,
7769 struct drm_framebuffer *fb,
7770 struct drm_display_mode *mode)
7771 {
7772 struct drm_device *dev = crtc->dev;
7773 struct drm_encoder_helper_funcs *encoder_funcs;
7774 struct intel_encoder *encoder;
7775 struct intel_crtc_config *pipe_config;
7776 int plane_bpp, ret = -EINVAL;
7777 bool retry = true;
7778
7779 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7780 if (!pipe_config)
7781 return ERR_PTR(-ENOMEM);
7782
7783 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7784 drm_mode_copy(&pipe_config->requested_mode, mode);
7785
7786 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7787 if (plane_bpp < 0)
7788 goto fail;
7789
7790 encoder_retry:
7791 /* Pass our mode to the connectors and the CRTC to give them a chance to
7792 * adjust it according to limitations or connector properties, and also
7793 * a chance to reject the mode entirely.
7794 */
7795 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7796 base.head) {
7797
7798 if (&encoder->new_crtc->base != crtc)
7799 continue;
7800
7801 if (encoder->compute_config) {
7802 if (!(encoder->compute_config(encoder, pipe_config))) {
7803 DRM_DEBUG_KMS("Encoder config failure\n");
7804 goto fail;
7805 }
7806
7807 continue;
7808 }
7809
7810 encoder_funcs = encoder->base.helper_private;
7811 if (!(encoder_funcs->mode_fixup(&encoder->base,
7812 &pipe_config->requested_mode,
7813 &pipe_config->adjusted_mode))) {
7814 DRM_DEBUG_KMS("Encoder fixup failed\n");
7815 goto fail;
7816 }
7817 }
7818
7819 ret = intel_crtc_compute_config(crtc, pipe_config);
7820 if (ret < 0) {
7821 DRM_DEBUG_KMS("CRTC fixup failed\n");
7822 goto fail;
7823 }
7824
7825 if (ret == RETRY) {
7826 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7827 ret = -EINVAL;
7828 goto fail;
7829 }
7830
7831 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7832 retry = false;
7833 goto encoder_retry;
7834 }
7835
7836 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7837
7838 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7839 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7840 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7841
7842 return pipe_config;
7843 fail:
7844 kfree(pipe_config);
7845 return ERR_PTR(ret);
7846 }
7847
7848 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7849 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7850 static void
7851 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7852 unsigned *prepare_pipes, unsigned *disable_pipes)
7853 {
7854 struct intel_crtc *intel_crtc;
7855 struct drm_device *dev = crtc->dev;
7856 struct intel_encoder *encoder;
7857 struct intel_connector *connector;
7858 struct drm_crtc *tmp_crtc;
7859
7860 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7861
7862 /* Check which crtcs have changed outputs connected to them, these need
7863 * to be part of the prepare_pipes mask. We don't (yet) support global
7864 * modeset across multiple crtcs, so modeset_pipes will only have one
7865 * bit set at most. */
7866 list_for_each_entry(connector, &dev->mode_config.connector_list,
7867 base.head) {
7868 if (connector->base.encoder == &connector->new_encoder->base)
7869 continue;
7870
7871 if (connector->base.encoder) {
7872 tmp_crtc = connector->base.encoder->crtc;
7873
7874 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7875 }
7876
7877 if (connector->new_encoder)
7878 *prepare_pipes |=
7879 1 << connector->new_encoder->new_crtc->pipe;
7880 }
7881
7882 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7883 base.head) {
7884 if (encoder->base.crtc == &encoder->new_crtc->base)
7885 continue;
7886
7887 if (encoder->base.crtc) {
7888 tmp_crtc = encoder->base.crtc;
7889
7890 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7891 }
7892
7893 if (encoder->new_crtc)
7894 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7895 }
7896
7897 /* Check for any pipes that will be fully disabled ... */
7898 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7899 base.head) {
7900 bool used = false;
7901
7902 /* Don't try to disable disabled crtcs. */
7903 if (!intel_crtc->base.enabled)
7904 continue;
7905
7906 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7907 base.head) {
7908 if (encoder->new_crtc == intel_crtc)
7909 used = true;
7910 }
7911
7912 if (!used)
7913 *disable_pipes |= 1 << intel_crtc->pipe;
7914 }
7915
7916
7917 /* set_mode is also used to update properties on life display pipes. */
7918 intel_crtc = to_intel_crtc(crtc);
7919 if (crtc->enabled)
7920 *prepare_pipes |= 1 << intel_crtc->pipe;
7921
7922 /*
7923 * For simplicity do a full modeset on any pipe where the output routing
7924 * changed. We could be more clever, but that would require us to be
7925 * more careful with calling the relevant encoder->mode_set functions.
7926 */
7927 if (*prepare_pipes)
7928 *modeset_pipes = *prepare_pipes;
7929
7930 /* ... and mask these out. */
7931 *modeset_pipes &= ~(*disable_pipes);
7932 *prepare_pipes &= ~(*disable_pipes);
7933
7934 /*
7935 * HACK: We don't (yet) fully support global modesets. intel_set_config
7936 * obies this rule, but the modeset restore mode of
7937 * intel_modeset_setup_hw_state does not.
7938 */
7939 *modeset_pipes &= 1 << intel_crtc->pipe;
7940 *prepare_pipes &= 1 << intel_crtc->pipe;
7941
7942 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7943 *modeset_pipes, *prepare_pipes, *disable_pipes);
7944 }
7945
7946 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7947 {
7948 struct drm_encoder *encoder;
7949 struct drm_device *dev = crtc->dev;
7950
7951 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7952 if (encoder->crtc == crtc)
7953 return true;
7954
7955 return false;
7956 }
7957
7958 static void
7959 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7960 {
7961 struct intel_encoder *intel_encoder;
7962 struct intel_crtc *intel_crtc;
7963 struct drm_connector *connector;
7964
7965 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7966 base.head) {
7967 if (!intel_encoder->base.crtc)
7968 continue;
7969
7970 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7971
7972 if (prepare_pipes & (1 << intel_crtc->pipe))
7973 intel_encoder->connectors_active = false;
7974 }
7975
7976 intel_modeset_commit_output_state(dev);
7977
7978 /* Update computed state. */
7979 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7980 base.head) {
7981 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7982 }
7983
7984 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7985 if (!connector->encoder || !connector->encoder->crtc)
7986 continue;
7987
7988 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7989
7990 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7991 struct drm_property *dpms_property =
7992 dev->mode_config.dpms_property;
7993
7994 connector->dpms = DRM_MODE_DPMS_ON;
7995 drm_object_property_set_value(&connector->base,
7996 dpms_property,
7997 DRM_MODE_DPMS_ON);
7998
7999 intel_encoder = to_intel_encoder(connector->encoder);
8000 intel_encoder->connectors_active = true;
8001 }
8002 }
8003
8004 }
8005
8006 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8007 list_for_each_entry((intel_crtc), \
8008 &(dev)->mode_config.crtc_list, \
8009 base.head) \
8010 if (mask & (1 <<(intel_crtc)->pipe))
8011
8012 static bool
8013 intel_pipe_config_compare(struct drm_device *dev,
8014 struct intel_crtc_config *current_config,
8015 struct intel_crtc_config *pipe_config)
8016 {
8017 #define PIPE_CONF_CHECK_I(name) \
8018 if (current_config->name != pipe_config->name) { \
8019 DRM_ERROR("mismatch in " #name " " \
8020 "(expected %i, found %i)\n", \
8021 current_config->name, \
8022 pipe_config->name); \
8023 return false; \
8024 }
8025
8026 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8027 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8028 DRM_ERROR("mismatch in " #name " " \
8029 "(expected %i, found %i)\n", \
8030 current_config->name & (mask), \
8031 pipe_config->name & (mask)); \
8032 return false; \
8033 }
8034
8035 PIPE_CONF_CHECK_I(has_pch_encoder);
8036 PIPE_CONF_CHECK_I(fdi_lanes);
8037 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8038 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8039 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8040 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8041 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8042
8043 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8044 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8045 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8046 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8047 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8048 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8049
8050 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8051 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8052 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8053 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8054 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8055 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8056
8057 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8058 DRM_MODE_FLAG_INTERLACE);
8059
8060 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8061 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8062
8063 PIPE_CONF_CHECK_I(gmch_pfit.control);
8064 /* pfit ratios are autocomputed by the hw on gen4+ */
8065 if (INTEL_INFO(dev)->gen < 4)
8066 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8067 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8068 PIPE_CONF_CHECK_I(pch_pfit.pos);
8069 PIPE_CONF_CHECK_I(pch_pfit.size);
8070
8071 #undef PIPE_CONF_CHECK_I
8072 #undef PIPE_CONF_CHECK_FLAGS
8073
8074 return true;
8075 }
8076
8077 void
8078 intel_modeset_check_state(struct drm_device *dev)
8079 {
8080 drm_i915_private_t *dev_priv = dev->dev_private;
8081 struct intel_crtc *crtc;
8082 struct intel_encoder *encoder;
8083 struct intel_connector *connector;
8084 struct intel_crtc_config pipe_config;
8085
8086 list_for_each_entry(connector, &dev->mode_config.connector_list,
8087 base.head) {
8088 /* This also checks the encoder/connector hw state with the
8089 * ->get_hw_state callbacks. */
8090 intel_connector_check_state(connector);
8091
8092 WARN(&connector->new_encoder->base != connector->base.encoder,
8093 "connector's staged encoder doesn't match current encoder\n");
8094 }
8095
8096 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8097 base.head) {
8098 bool enabled = false;
8099 bool active = false;
8100 enum pipe pipe, tracked_pipe;
8101
8102 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8103 encoder->base.base.id,
8104 drm_get_encoder_name(&encoder->base));
8105
8106 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8107 "encoder's stage crtc doesn't match current crtc\n");
8108 WARN(encoder->connectors_active && !encoder->base.crtc,
8109 "encoder's active_connectors set, but no crtc\n");
8110
8111 list_for_each_entry(connector, &dev->mode_config.connector_list,
8112 base.head) {
8113 if (connector->base.encoder != &encoder->base)
8114 continue;
8115 enabled = true;
8116 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8117 active = true;
8118 }
8119 WARN(!!encoder->base.crtc != enabled,
8120 "encoder's enabled state mismatch "
8121 "(expected %i, found %i)\n",
8122 !!encoder->base.crtc, enabled);
8123 WARN(active && !encoder->base.crtc,
8124 "active encoder with no crtc\n");
8125
8126 WARN(encoder->connectors_active != active,
8127 "encoder's computed active state doesn't match tracked active state "
8128 "(expected %i, found %i)\n", active, encoder->connectors_active);
8129
8130 active = encoder->get_hw_state(encoder, &pipe);
8131 WARN(active != encoder->connectors_active,
8132 "encoder's hw state doesn't match sw tracking "
8133 "(expected %i, found %i)\n",
8134 encoder->connectors_active, active);
8135
8136 if (!encoder->base.crtc)
8137 continue;
8138
8139 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8140 WARN(active && pipe != tracked_pipe,
8141 "active encoder's pipe doesn't match"
8142 "(expected %i, found %i)\n",
8143 tracked_pipe, pipe);
8144
8145 }
8146
8147 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8148 base.head) {
8149 bool enabled = false;
8150 bool active = false;
8151
8152 DRM_DEBUG_KMS("[CRTC:%d]\n",
8153 crtc->base.base.id);
8154
8155 WARN(crtc->active && !crtc->base.enabled,
8156 "active crtc, but not enabled in sw tracking\n");
8157
8158 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8159 base.head) {
8160 if (encoder->base.crtc != &crtc->base)
8161 continue;
8162 enabled = true;
8163 if (encoder->connectors_active)
8164 active = true;
8165 }
8166 WARN(active != crtc->active,
8167 "crtc's computed active state doesn't match tracked active state "
8168 "(expected %i, found %i)\n", active, crtc->active);
8169 WARN(enabled != crtc->base.enabled,
8170 "crtc's computed enabled state doesn't match tracked enabled state "
8171 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8172
8173 memset(&pipe_config, 0, sizeof(pipe_config));
8174 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8175 active = dev_priv->display.get_pipe_config(crtc,
8176 &pipe_config);
8177 WARN(crtc->active != active,
8178 "crtc active state doesn't match with hw state "
8179 "(expected %i, found %i)\n", crtc->active, active);
8180
8181 WARN(active &&
8182 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config),
8183 "pipe state doesn't match!\n");
8184 }
8185 }
8186
8187 static int __intel_set_mode(struct drm_crtc *crtc,
8188 struct drm_display_mode *mode,
8189 int x, int y, struct drm_framebuffer *fb)
8190 {
8191 struct drm_device *dev = crtc->dev;
8192 drm_i915_private_t *dev_priv = dev->dev_private;
8193 struct drm_display_mode *saved_mode, *saved_hwmode;
8194 struct intel_crtc_config *pipe_config = NULL;
8195 struct intel_crtc *intel_crtc;
8196 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8197 int ret = 0;
8198
8199 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8200 if (!saved_mode)
8201 return -ENOMEM;
8202 saved_hwmode = saved_mode + 1;
8203
8204 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8205 &prepare_pipes, &disable_pipes);
8206
8207 *saved_hwmode = crtc->hwmode;
8208 *saved_mode = crtc->mode;
8209
8210 /* Hack: Because we don't (yet) support global modeset on multiple
8211 * crtcs, we don't keep track of the new mode for more than one crtc.
8212 * Hence simply check whether any bit is set in modeset_pipes in all the
8213 * pieces of code that are not yet converted to deal with mutliple crtcs
8214 * changing their mode at the same time. */
8215 if (modeset_pipes) {
8216 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8217 if (IS_ERR(pipe_config)) {
8218 ret = PTR_ERR(pipe_config);
8219 pipe_config = NULL;
8220
8221 goto out;
8222 }
8223 }
8224
8225 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8226 intel_crtc_disable(&intel_crtc->base);
8227
8228 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8229 if (intel_crtc->base.enabled)
8230 dev_priv->display.crtc_disable(&intel_crtc->base);
8231 }
8232
8233 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8234 * to set it here already despite that we pass it down the callchain.
8235 */
8236 if (modeset_pipes) {
8237 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8238 crtc->mode = *mode;
8239 /* mode_set/enable/disable functions rely on a correct pipe
8240 * config. */
8241 to_intel_crtc(crtc)->config = *pipe_config;
8242 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8243 }
8244
8245 /* Only after disabling all output pipelines that will be changed can we
8246 * update the the output configuration. */
8247 intel_modeset_update_state(dev, prepare_pipes);
8248
8249 if (dev_priv->display.modeset_global_resources)
8250 dev_priv->display.modeset_global_resources(dev);
8251
8252 /* Set up the DPLL and any encoders state that needs to adjust or depend
8253 * on the DPLL.
8254 */
8255 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8256 ret = intel_crtc_mode_set(&intel_crtc->base,
8257 x, y, fb);
8258 if (ret)
8259 goto done;
8260 }
8261
8262 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8263 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8264 dev_priv->display.crtc_enable(&intel_crtc->base);
8265
8266 if (modeset_pipes) {
8267 /* Store real post-adjustment hardware mode. */
8268 crtc->hwmode = pipe_config->adjusted_mode;
8269
8270 /* Calculate and store various constants which
8271 * are later needed by vblank and swap-completion
8272 * timestamping. They are derived from true hwmode.
8273 */
8274 drm_calc_timestamping_constants(crtc);
8275 }
8276
8277 /* FIXME: add subpixel order */
8278 done:
8279 if (ret && crtc->enabled) {
8280 crtc->hwmode = *saved_hwmode;
8281 crtc->mode = *saved_mode;
8282 }
8283
8284 out:
8285 kfree(pipe_config);
8286 kfree(saved_mode);
8287 return ret;
8288 }
8289
8290 int intel_set_mode(struct drm_crtc *crtc,
8291 struct drm_display_mode *mode,
8292 int x, int y, struct drm_framebuffer *fb)
8293 {
8294 int ret;
8295
8296 ret = __intel_set_mode(crtc, mode, x, y, fb);
8297
8298 if (ret == 0)
8299 intel_modeset_check_state(crtc->dev);
8300
8301 return ret;
8302 }
8303
8304 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8305 {
8306 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8307 }
8308
8309 #undef for_each_intel_crtc_masked
8310
8311 static void intel_set_config_free(struct intel_set_config *config)
8312 {
8313 if (!config)
8314 return;
8315
8316 kfree(config->save_connector_encoders);
8317 kfree(config->save_encoder_crtcs);
8318 kfree(config);
8319 }
8320
8321 static int intel_set_config_save_state(struct drm_device *dev,
8322 struct intel_set_config *config)
8323 {
8324 struct drm_encoder *encoder;
8325 struct drm_connector *connector;
8326 int count;
8327
8328 config->save_encoder_crtcs =
8329 kcalloc(dev->mode_config.num_encoder,
8330 sizeof(struct drm_crtc *), GFP_KERNEL);
8331 if (!config->save_encoder_crtcs)
8332 return -ENOMEM;
8333
8334 config->save_connector_encoders =
8335 kcalloc(dev->mode_config.num_connector,
8336 sizeof(struct drm_encoder *), GFP_KERNEL);
8337 if (!config->save_connector_encoders)
8338 return -ENOMEM;
8339
8340 /* Copy data. Note that driver private data is not affected.
8341 * Should anything bad happen only the expected state is
8342 * restored, not the drivers personal bookkeeping.
8343 */
8344 count = 0;
8345 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8346 config->save_encoder_crtcs[count++] = encoder->crtc;
8347 }
8348
8349 count = 0;
8350 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8351 config->save_connector_encoders[count++] = connector->encoder;
8352 }
8353
8354 return 0;
8355 }
8356
8357 static void intel_set_config_restore_state(struct drm_device *dev,
8358 struct intel_set_config *config)
8359 {
8360 struct intel_encoder *encoder;
8361 struct intel_connector *connector;
8362 int count;
8363
8364 count = 0;
8365 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8366 encoder->new_crtc =
8367 to_intel_crtc(config->save_encoder_crtcs[count++]);
8368 }
8369
8370 count = 0;
8371 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8372 connector->new_encoder =
8373 to_intel_encoder(config->save_connector_encoders[count++]);
8374 }
8375 }
8376
8377 static void
8378 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8379 struct intel_set_config *config)
8380 {
8381
8382 /* We should be able to check here if the fb has the same properties
8383 * and then just flip_or_move it */
8384 if (set->crtc->fb != set->fb) {
8385 /* If we have no fb then treat it as a full mode set */
8386 if (set->crtc->fb == NULL) {
8387 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8388 config->mode_changed = true;
8389 } else if (set->fb == NULL) {
8390 config->mode_changed = true;
8391 } else if (set->fb->pixel_format !=
8392 set->crtc->fb->pixel_format) {
8393 config->mode_changed = true;
8394 } else
8395 config->fb_changed = true;
8396 }
8397
8398 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8399 config->fb_changed = true;
8400
8401 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8402 DRM_DEBUG_KMS("modes are different, full mode set\n");
8403 drm_mode_debug_printmodeline(&set->crtc->mode);
8404 drm_mode_debug_printmodeline(set->mode);
8405 config->mode_changed = true;
8406 }
8407 }
8408
8409 static int
8410 intel_modeset_stage_output_state(struct drm_device *dev,
8411 struct drm_mode_set *set,
8412 struct intel_set_config *config)
8413 {
8414 struct drm_crtc *new_crtc;
8415 struct intel_connector *connector;
8416 struct intel_encoder *encoder;
8417 int count, ro;
8418
8419 /* The upper layers ensure that we either disable a crtc or have a list
8420 * of connectors. For paranoia, double-check this. */
8421 WARN_ON(!set->fb && (set->num_connectors != 0));
8422 WARN_ON(set->fb && (set->num_connectors == 0));
8423
8424 count = 0;
8425 list_for_each_entry(connector, &dev->mode_config.connector_list,
8426 base.head) {
8427 /* Otherwise traverse passed in connector list and get encoders
8428 * for them. */
8429 for (ro = 0; ro < set->num_connectors; ro++) {
8430 if (set->connectors[ro] == &connector->base) {
8431 connector->new_encoder = connector->encoder;
8432 break;
8433 }
8434 }
8435
8436 /* If we disable the crtc, disable all its connectors. Also, if
8437 * the connector is on the changing crtc but not on the new
8438 * connector list, disable it. */
8439 if ((!set->fb || ro == set->num_connectors) &&
8440 connector->base.encoder &&
8441 connector->base.encoder->crtc == set->crtc) {
8442 connector->new_encoder = NULL;
8443
8444 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8445 connector->base.base.id,
8446 drm_get_connector_name(&connector->base));
8447 }
8448
8449
8450 if (&connector->new_encoder->base != connector->base.encoder) {
8451 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8452 config->mode_changed = true;
8453 }
8454 }
8455 /* connector->new_encoder is now updated for all connectors. */
8456
8457 /* Update crtc of enabled connectors. */
8458 count = 0;
8459 list_for_each_entry(connector, &dev->mode_config.connector_list,
8460 base.head) {
8461 if (!connector->new_encoder)
8462 continue;
8463
8464 new_crtc = connector->new_encoder->base.crtc;
8465
8466 for (ro = 0; ro < set->num_connectors; ro++) {
8467 if (set->connectors[ro] == &connector->base)
8468 new_crtc = set->crtc;
8469 }
8470
8471 /* Make sure the new CRTC will work with the encoder */
8472 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8473 new_crtc)) {
8474 return -EINVAL;
8475 }
8476 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8477
8478 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8479 connector->base.base.id,
8480 drm_get_connector_name(&connector->base),
8481 new_crtc->base.id);
8482 }
8483
8484 /* Check for any encoders that needs to be disabled. */
8485 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8486 base.head) {
8487 list_for_each_entry(connector,
8488 &dev->mode_config.connector_list,
8489 base.head) {
8490 if (connector->new_encoder == encoder) {
8491 WARN_ON(!connector->new_encoder->new_crtc);
8492
8493 goto next_encoder;
8494 }
8495 }
8496 encoder->new_crtc = NULL;
8497 next_encoder:
8498 /* Only now check for crtc changes so we don't miss encoders
8499 * that will be disabled. */
8500 if (&encoder->new_crtc->base != encoder->base.crtc) {
8501 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8502 config->mode_changed = true;
8503 }
8504 }
8505 /* Now we've also updated encoder->new_crtc for all encoders. */
8506
8507 return 0;
8508 }
8509
8510 static int intel_crtc_set_config(struct drm_mode_set *set)
8511 {
8512 struct drm_device *dev;
8513 struct drm_mode_set save_set;
8514 struct intel_set_config *config;
8515 int ret;
8516
8517 BUG_ON(!set);
8518 BUG_ON(!set->crtc);
8519 BUG_ON(!set->crtc->helper_private);
8520
8521 /* Enforce sane interface api - has been abused by the fb helper. */
8522 BUG_ON(!set->mode && set->fb);
8523 BUG_ON(set->fb && set->num_connectors == 0);
8524
8525 if (set->fb) {
8526 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8527 set->crtc->base.id, set->fb->base.id,
8528 (int)set->num_connectors, set->x, set->y);
8529 } else {
8530 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8531 }
8532
8533 dev = set->crtc->dev;
8534
8535 ret = -ENOMEM;
8536 config = kzalloc(sizeof(*config), GFP_KERNEL);
8537 if (!config)
8538 goto out_config;
8539
8540 ret = intel_set_config_save_state(dev, config);
8541 if (ret)
8542 goto out_config;
8543
8544 save_set.crtc = set->crtc;
8545 save_set.mode = &set->crtc->mode;
8546 save_set.x = set->crtc->x;
8547 save_set.y = set->crtc->y;
8548 save_set.fb = set->crtc->fb;
8549
8550 /* Compute whether we need a full modeset, only an fb base update or no
8551 * change at all. In the future we might also check whether only the
8552 * mode changed, e.g. for LVDS where we only change the panel fitter in
8553 * such cases. */
8554 intel_set_config_compute_mode_changes(set, config);
8555
8556 ret = intel_modeset_stage_output_state(dev, set, config);
8557 if (ret)
8558 goto fail;
8559
8560 if (config->mode_changed) {
8561 if (set->mode) {
8562 DRM_DEBUG_KMS("attempting to set mode from"
8563 " userspace\n");
8564 drm_mode_debug_printmodeline(set->mode);
8565 }
8566
8567 ret = intel_set_mode(set->crtc, set->mode,
8568 set->x, set->y, set->fb);
8569 if (ret) {
8570 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8571 set->crtc->base.id, ret);
8572 goto fail;
8573 }
8574 } else if (config->fb_changed) {
8575 intel_crtc_wait_for_pending_flips(set->crtc);
8576
8577 ret = intel_pipe_set_base(set->crtc,
8578 set->x, set->y, set->fb);
8579 }
8580
8581 intel_set_config_free(config);
8582
8583 return 0;
8584
8585 fail:
8586 intel_set_config_restore_state(dev, config);
8587
8588 /* Try to restore the config */
8589 if (config->mode_changed &&
8590 intel_set_mode(save_set.crtc, save_set.mode,
8591 save_set.x, save_set.y, save_set.fb))
8592 DRM_ERROR("failed to restore config after modeset failure\n");
8593
8594 out_config:
8595 intel_set_config_free(config);
8596 return ret;
8597 }
8598
8599 static const struct drm_crtc_funcs intel_crtc_funcs = {
8600 .cursor_set = intel_crtc_cursor_set,
8601 .cursor_move = intel_crtc_cursor_move,
8602 .gamma_set = intel_crtc_gamma_set,
8603 .set_config = intel_crtc_set_config,
8604 .destroy = intel_crtc_destroy,
8605 .page_flip = intel_crtc_page_flip,
8606 };
8607
8608 static void intel_cpu_pll_init(struct drm_device *dev)
8609 {
8610 if (HAS_DDI(dev))
8611 intel_ddi_pll_init(dev);
8612 }
8613
8614 static void intel_pch_pll_init(struct drm_device *dev)
8615 {
8616 drm_i915_private_t *dev_priv = dev->dev_private;
8617 int i;
8618
8619 if (dev_priv->num_pch_pll == 0) {
8620 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8621 return;
8622 }
8623
8624 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8625 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8626 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8627 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8628 }
8629 }
8630
8631 static void intel_crtc_init(struct drm_device *dev, int pipe)
8632 {
8633 drm_i915_private_t *dev_priv = dev->dev_private;
8634 struct intel_crtc *intel_crtc;
8635 int i;
8636
8637 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8638 if (intel_crtc == NULL)
8639 return;
8640
8641 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8642
8643 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8644 for (i = 0; i < 256; i++) {
8645 intel_crtc->lut_r[i] = i;
8646 intel_crtc->lut_g[i] = i;
8647 intel_crtc->lut_b[i] = i;
8648 }
8649
8650 /* Swap pipes & planes for FBC on pre-965 */
8651 intel_crtc->pipe = pipe;
8652 intel_crtc->plane = pipe;
8653 intel_crtc->config.cpu_transcoder = pipe;
8654 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8655 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8656 intel_crtc->plane = !pipe;
8657 }
8658
8659 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8660 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8661 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8662 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8663
8664 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8665 }
8666
8667 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8668 struct drm_file *file)
8669 {
8670 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8671 struct drm_mode_object *drmmode_obj;
8672 struct intel_crtc *crtc;
8673
8674 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8675 return -ENODEV;
8676
8677 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8678 DRM_MODE_OBJECT_CRTC);
8679
8680 if (!drmmode_obj) {
8681 DRM_ERROR("no such CRTC id\n");
8682 return -EINVAL;
8683 }
8684
8685 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8686 pipe_from_crtc_id->pipe = crtc->pipe;
8687
8688 return 0;
8689 }
8690
8691 static int intel_encoder_clones(struct intel_encoder *encoder)
8692 {
8693 struct drm_device *dev = encoder->base.dev;
8694 struct intel_encoder *source_encoder;
8695 int index_mask = 0;
8696 int entry = 0;
8697
8698 list_for_each_entry(source_encoder,
8699 &dev->mode_config.encoder_list, base.head) {
8700
8701 if (encoder == source_encoder)
8702 index_mask |= (1 << entry);
8703
8704 /* Intel hw has only one MUX where enocoders could be cloned. */
8705 if (encoder->cloneable && source_encoder->cloneable)
8706 index_mask |= (1 << entry);
8707
8708 entry++;
8709 }
8710
8711 return index_mask;
8712 }
8713
8714 static bool has_edp_a(struct drm_device *dev)
8715 {
8716 struct drm_i915_private *dev_priv = dev->dev_private;
8717
8718 if (!IS_MOBILE(dev))
8719 return false;
8720
8721 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8722 return false;
8723
8724 if (IS_GEN5(dev) &&
8725 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8726 return false;
8727
8728 return true;
8729 }
8730
8731 static void intel_setup_outputs(struct drm_device *dev)
8732 {
8733 struct drm_i915_private *dev_priv = dev->dev_private;
8734 struct intel_encoder *encoder;
8735 bool dpd_is_edp = false;
8736 bool has_lvds;
8737
8738 has_lvds = intel_lvds_init(dev);
8739 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8740 /* disable the panel fitter on everything but LVDS */
8741 I915_WRITE(PFIT_CONTROL, 0);
8742 }
8743
8744 if (!IS_ULT(dev))
8745 intel_crt_init(dev);
8746
8747 if (HAS_DDI(dev)) {
8748 int found;
8749
8750 /* Haswell uses DDI functions to detect digital outputs */
8751 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8752 /* DDI A only supports eDP */
8753 if (found)
8754 intel_ddi_init(dev, PORT_A);
8755
8756 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8757 * register */
8758 found = I915_READ(SFUSE_STRAP);
8759
8760 if (found & SFUSE_STRAP_DDIB_DETECTED)
8761 intel_ddi_init(dev, PORT_B);
8762 if (found & SFUSE_STRAP_DDIC_DETECTED)
8763 intel_ddi_init(dev, PORT_C);
8764 if (found & SFUSE_STRAP_DDID_DETECTED)
8765 intel_ddi_init(dev, PORT_D);
8766 } else if (HAS_PCH_SPLIT(dev)) {
8767 int found;
8768 dpd_is_edp = intel_dpd_is_edp(dev);
8769
8770 if (has_edp_a(dev))
8771 intel_dp_init(dev, DP_A, PORT_A);
8772
8773 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8774 /* PCH SDVOB multiplex with HDMIB */
8775 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8776 if (!found)
8777 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8778 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8779 intel_dp_init(dev, PCH_DP_B, PORT_B);
8780 }
8781
8782 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8783 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8784
8785 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8786 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8787
8788 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8789 intel_dp_init(dev, PCH_DP_C, PORT_C);
8790
8791 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8792 intel_dp_init(dev, PCH_DP_D, PORT_D);
8793 } else if (IS_VALLEYVIEW(dev)) {
8794 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8795 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8796 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8797
8798 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8799 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8800 PORT_B);
8801 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8802 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8803 }
8804 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8805 bool found = false;
8806
8807 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8808 DRM_DEBUG_KMS("probing SDVOB\n");
8809 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8810 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8811 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8812 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8813 }
8814
8815 if (!found && SUPPORTS_INTEGRATED_DP(dev))
8816 intel_dp_init(dev, DP_B, PORT_B);
8817 }
8818
8819 /* Before G4X SDVOC doesn't have its own detect register */
8820
8821 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8822 DRM_DEBUG_KMS("probing SDVOC\n");
8823 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8824 }
8825
8826 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8827
8828 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8829 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8830 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8831 }
8832 if (SUPPORTS_INTEGRATED_DP(dev))
8833 intel_dp_init(dev, DP_C, PORT_C);
8834 }
8835
8836 if (SUPPORTS_INTEGRATED_DP(dev) &&
8837 (I915_READ(DP_D) & DP_DETECTED))
8838 intel_dp_init(dev, DP_D, PORT_D);
8839 } else if (IS_GEN2(dev))
8840 intel_dvo_init(dev);
8841
8842 if (SUPPORTS_TV(dev))
8843 intel_tv_init(dev);
8844
8845 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8846 encoder->base.possible_crtcs = encoder->crtc_mask;
8847 encoder->base.possible_clones =
8848 intel_encoder_clones(encoder);
8849 }
8850
8851 intel_init_pch_refclk(dev);
8852
8853 drm_helper_move_panel_connectors_to_head(dev);
8854 }
8855
8856 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8857 {
8858 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8859
8860 drm_framebuffer_cleanup(fb);
8861 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8862
8863 kfree(intel_fb);
8864 }
8865
8866 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8867 struct drm_file *file,
8868 unsigned int *handle)
8869 {
8870 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8871 struct drm_i915_gem_object *obj = intel_fb->obj;
8872
8873 return drm_gem_handle_create(file, &obj->base, handle);
8874 }
8875
8876 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8877 .destroy = intel_user_framebuffer_destroy,
8878 .create_handle = intel_user_framebuffer_create_handle,
8879 };
8880
8881 int intel_framebuffer_init(struct drm_device *dev,
8882 struct intel_framebuffer *intel_fb,
8883 struct drm_mode_fb_cmd2 *mode_cmd,
8884 struct drm_i915_gem_object *obj)
8885 {
8886 int ret;
8887
8888 if (obj->tiling_mode == I915_TILING_Y) {
8889 DRM_DEBUG("hardware does not support tiling Y\n");
8890 return -EINVAL;
8891 }
8892
8893 if (mode_cmd->pitches[0] & 63) {
8894 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8895 mode_cmd->pitches[0]);
8896 return -EINVAL;
8897 }
8898
8899 /* FIXME <= Gen4 stride limits are bit unclear */
8900 if (mode_cmd->pitches[0] > 32768) {
8901 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8902 mode_cmd->pitches[0]);
8903 return -EINVAL;
8904 }
8905
8906 if (obj->tiling_mode != I915_TILING_NONE &&
8907 mode_cmd->pitches[0] != obj->stride) {
8908 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8909 mode_cmd->pitches[0], obj->stride);
8910 return -EINVAL;
8911 }
8912
8913 /* Reject formats not supported by any plane early. */
8914 switch (mode_cmd->pixel_format) {
8915 case DRM_FORMAT_C8:
8916 case DRM_FORMAT_RGB565:
8917 case DRM_FORMAT_XRGB8888:
8918 case DRM_FORMAT_ARGB8888:
8919 break;
8920 case DRM_FORMAT_XRGB1555:
8921 case DRM_FORMAT_ARGB1555:
8922 if (INTEL_INFO(dev)->gen > 3) {
8923 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8924 return -EINVAL;
8925 }
8926 break;
8927 case DRM_FORMAT_XBGR8888:
8928 case DRM_FORMAT_ABGR8888:
8929 case DRM_FORMAT_XRGB2101010:
8930 case DRM_FORMAT_ARGB2101010:
8931 case DRM_FORMAT_XBGR2101010:
8932 case DRM_FORMAT_ABGR2101010:
8933 if (INTEL_INFO(dev)->gen < 4) {
8934 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8935 return -EINVAL;
8936 }
8937 break;
8938 case DRM_FORMAT_YUYV:
8939 case DRM_FORMAT_UYVY:
8940 case DRM_FORMAT_YVYU:
8941 case DRM_FORMAT_VYUY:
8942 if (INTEL_INFO(dev)->gen < 5) {
8943 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8944 return -EINVAL;
8945 }
8946 break;
8947 default:
8948 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8949 return -EINVAL;
8950 }
8951
8952 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8953 if (mode_cmd->offsets[0] != 0)
8954 return -EINVAL;
8955
8956 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8957 intel_fb->obj = obj;
8958
8959 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8960 if (ret) {
8961 DRM_ERROR("framebuffer init failed %d\n", ret);
8962 return ret;
8963 }
8964
8965 return 0;
8966 }
8967
8968 static struct drm_framebuffer *
8969 intel_user_framebuffer_create(struct drm_device *dev,
8970 struct drm_file *filp,
8971 struct drm_mode_fb_cmd2 *mode_cmd)
8972 {
8973 struct drm_i915_gem_object *obj;
8974
8975 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8976 mode_cmd->handles[0]));
8977 if (&obj->base == NULL)
8978 return ERR_PTR(-ENOENT);
8979
8980 return intel_framebuffer_create(dev, mode_cmd, obj);
8981 }
8982
8983 static const struct drm_mode_config_funcs intel_mode_funcs = {
8984 .fb_create = intel_user_framebuffer_create,
8985 .output_poll_changed = intel_fb_output_poll_changed,
8986 };
8987
8988 /* Set up chip specific display functions */
8989 static void intel_init_display(struct drm_device *dev)
8990 {
8991 struct drm_i915_private *dev_priv = dev->dev_private;
8992
8993 if (HAS_DDI(dev)) {
8994 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8995 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8996 dev_priv->display.crtc_enable = haswell_crtc_enable;
8997 dev_priv->display.crtc_disable = haswell_crtc_disable;
8998 dev_priv->display.off = haswell_crtc_off;
8999 dev_priv->display.update_plane = ironlake_update_plane;
9000 } else if (HAS_PCH_SPLIT(dev)) {
9001 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9002 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9003 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9004 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9005 dev_priv->display.off = ironlake_crtc_off;
9006 dev_priv->display.update_plane = ironlake_update_plane;
9007 } else if (IS_VALLEYVIEW(dev)) {
9008 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9009 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9010 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9011 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9012 dev_priv->display.off = i9xx_crtc_off;
9013 dev_priv->display.update_plane = i9xx_update_plane;
9014 } else {
9015 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9016 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9017 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9018 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9019 dev_priv->display.off = i9xx_crtc_off;
9020 dev_priv->display.update_plane = i9xx_update_plane;
9021 }
9022
9023 /* Returns the core display clock speed */
9024 if (IS_VALLEYVIEW(dev))
9025 dev_priv->display.get_display_clock_speed =
9026 valleyview_get_display_clock_speed;
9027 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9028 dev_priv->display.get_display_clock_speed =
9029 i945_get_display_clock_speed;
9030 else if (IS_I915G(dev))
9031 dev_priv->display.get_display_clock_speed =
9032 i915_get_display_clock_speed;
9033 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9034 dev_priv->display.get_display_clock_speed =
9035 i9xx_misc_get_display_clock_speed;
9036 else if (IS_I915GM(dev))
9037 dev_priv->display.get_display_clock_speed =
9038 i915gm_get_display_clock_speed;
9039 else if (IS_I865G(dev))
9040 dev_priv->display.get_display_clock_speed =
9041 i865_get_display_clock_speed;
9042 else if (IS_I85X(dev))
9043 dev_priv->display.get_display_clock_speed =
9044 i855_get_display_clock_speed;
9045 else /* 852, 830 */
9046 dev_priv->display.get_display_clock_speed =
9047 i830_get_display_clock_speed;
9048
9049 if (HAS_PCH_SPLIT(dev)) {
9050 if (IS_GEN5(dev)) {
9051 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9052 dev_priv->display.write_eld = ironlake_write_eld;
9053 } else if (IS_GEN6(dev)) {
9054 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9055 dev_priv->display.write_eld = ironlake_write_eld;
9056 } else if (IS_IVYBRIDGE(dev)) {
9057 /* FIXME: detect B0+ stepping and use auto training */
9058 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9059 dev_priv->display.write_eld = ironlake_write_eld;
9060 dev_priv->display.modeset_global_resources =
9061 ivb_modeset_global_resources;
9062 } else if (IS_HASWELL(dev)) {
9063 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9064 dev_priv->display.write_eld = haswell_write_eld;
9065 dev_priv->display.modeset_global_resources =
9066 haswell_modeset_global_resources;
9067 }
9068 } else if (IS_G4X(dev)) {
9069 dev_priv->display.write_eld = g4x_write_eld;
9070 }
9071
9072 /* Default just returns -ENODEV to indicate unsupported */
9073 dev_priv->display.queue_flip = intel_default_queue_flip;
9074
9075 switch (INTEL_INFO(dev)->gen) {
9076 case 2:
9077 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9078 break;
9079
9080 case 3:
9081 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9082 break;
9083
9084 case 4:
9085 case 5:
9086 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9087 break;
9088
9089 case 6:
9090 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9091 break;
9092 case 7:
9093 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9094 break;
9095 }
9096 }
9097
9098 /*
9099 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9100 * resume, or other times. This quirk makes sure that's the case for
9101 * affected systems.
9102 */
9103 static void quirk_pipea_force(struct drm_device *dev)
9104 {
9105 struct drm_i915_private *dev_priv = dev->dev_private;
9106
9107 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9108 DRM_INFO("applying pipe a force quirk\n");
9109 }
9110
9111 /*
9112 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9113 */
9114 static void quirk_ssc_force_disable(struct drm_device *dev)
9115 {
9116 struct drm_i915_private *dev_priv = dev->dev_private;
9117 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9118 DRM_INFO("applying lvds SSC disable quirk\n");
9119 }
9120
9121 /*
9122 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9123 * brightness value
9124 */
9125 static void quirk_invert_brightness(struct drm_device *dev)
9126 {
9127 struct drm_i915_private *dev_priv = dev->dev_private;
9128 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9129 DRM_INFO("applying inverted panel brightness quirk\n");
9130 }
9131
9132 struct intel_quirk {
9133 int device;
9134 int subsystem_vendor;
9135 int subsystem_device;
9136 void (*hook)(struct drm_device *dev);
9137 };
9138
9139 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9140 struct intel_dmi_quirk {
9141 void (*hook)(struct drm_device *dev);
9142 const struct dmi_system_id (*dmi_id_list)[];
9143 };
9144
9145 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9146 {
9147 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9148 return 1;
9149 }
9150
9151 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9152 {
9153 .dmi_id_list = &(const struct dmi_system_id[]) {
9154 {
9155 .callback = intel_dmi_reverse_brightness,
9156 .ident = "NCR Corporation",
9157 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9158 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9159 },
9160 },
9161 { } /* terminating entry */
9162 },
9163 .hook = quirk_invert_brightness,
9164 },
9165 };
9166
9167 static struct intel_quirk intel_quirks[] = {
9168 /* HP Mini needs pipe A force quirk (LP: #322104) */
9169 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9170
9171 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9172 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9173
9174 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9175 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9176
9177 /* 830/845 need to leave pipe A & dpll A up */
9178 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9179 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9180
9181 /* Lenovo U160 cannot use SSC on LVDS */
9182 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9183
9184 /* Sony Vaio Y cannot use SSC on LVDS */
9185 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9186
9187 /* Acer Aspire 5734Z must invert backlight brightness */
9188 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9189
9190 /* Acer/eMachines G725 */
9191 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9192
9193 /* Acer/eMachines e725 */
9194 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9195
9196 /* Acer/Packard Bell NCL20 */
9197 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9198
9199 /* Acer Aspire 4736Z */
9200 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9201 };
9202
9203 static void intel_init_quirks(struct drm_device *dev)
9204 {
9205 struct pci_dev *d = dev->pdev;
9206 int i;
9207
9208 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9209 struct intel_quirk *q = &intel_quirks[i];
9210
9211 if (d->device == q->device &&
9212 (d->subsystem_vendor == q->subsystem_vendor ||
9213 q->subsystem_vendor == PCI_ANY_ID) &&
9214 (d->subsystem_device == q->subsystem_device ||
9215 q->subsystem_device == PCI_ANY_ID))
9216 q->hook(dev);
9217 }
9218 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9219 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9220 intel_dmi_quirks[i].hook(dev);
9221 }
9222 }
9223
9224 /* Disable the VGA plane that we never use */
9225 static void i915_disable_vga(struct drm_device *dev)
9226 {
9227 struct drm_i915_private *dev_priv = dev->dev_private;
9228 u8 sr1;
9229 u32 vga_reg = i915_vgacntrl_reg(dev);
9230
9231 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9232 outb(SR01, VGA_SR_INDEX);
9233 sr1 = inb(VGA_SR_DATA);
9234 outb(sr1 | 1<<5, VGA_SR_DATA);
9235 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9236 udelay(300);
9237
9238 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9239 POSTING_READ(vga_reg);
9240 }
9241
9242 void intel_modeset_init_hw(struct drm_device *dev)
9243 {
9244 intel_init_power_well(dev);
9245
9246 intel_prepare_ddi(dev);
9247
9248 intel_init_clock_gating(dev);
9249
9250 mutex_lock(&dev->struct_mutex);
9251 intel_enable_gt_powersave(dev);
9252 mutex_unlock(&dev->struct_mutex);
9253 }
9254
9255 void intel_modeset_suspend_hw(struct drm_device *dev)
9256 {
9257 intel_suspend_hw(dev);
9258 }
9259
9260 void intel_modeset_init(struct drm_device *dev)
9261 {
9262 struct drm_i915_private *dev_priv = dev->dev_private;
9263 int i, j, ret;
9264
9265 drm_mode_config_init(dev);
9266
9267 dev->mode_config.min_width = 0;
9268 dev->mode_config.min_height = 0;
9269
9270 dev->mode_config.preferred_depth = 24;
9271 dev->mode_config.prefer_shadow = 1;
9272
9273 dev->mode_config.funcs = &intel_mode_funcs;
9274
9275 intel_init_quirks(dev);
9276
9277 intel_init_pm(dev);
9278
9279 if (INTEL_INFO(dev)->num_pipes == 0)
9280 return;
9281
9282 intel_init_display(dev);
9283
9284 if (IS_GEN2(dev)) {
9285 dev->mode_config.max_width = 2048;
9286 dev->mode_config.max_height = 2048;
9287 } else if (IS_GEN3(dev)) {
9288 dev->mode_config.max_width = 4096;
9289 dev->mode_config.max_height = 4096;
9290 } else {
9291 dev->mode_config.max_width = 8192;
9292 dev->mode_config.max_height = 8192;
9293 }
9294 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9295
9296 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9297 INTEL_INFO(dev)->num_pipes,
9298 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9299
9300 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9301 intel_crtc_init(dev, i);
9302 for (j = 0; j < dev_priv->num_plane; j++) {
9303 ret = intel_plane_init(dev, i, j);
9304 if (ret)
9305 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9306 pipe_name(i), sprite_name(i, j), ret);
9307 }
9308 }
9309
9310 intel_cpu_pll_init(dev);
9311 intel_pch_pll_init(dev);
9312
9313 /* Just disable it once at startup */
9314 i915_disable_vga(dev);
9315 intel_setup_outputs(dev);
9316
9317 /* Just in case the BIOS is doing something questionable. */
9318 intel_disable_fbc(dev);
9319 }
9320
9321 static void
9322 intel_connector_break_all_links(struct intel_connector *connector)
9323 {
9324 connector->base.dpms = DRM_MODE_DPMS_OFF;
9325 connector->base.encoder = NULL;
9326 connector->encoder->connectors_active = false;
9327 connector->encoder->base.crtc = NULL;
9328 }
9329
9330 static void intel_enable_pipe_a(struct drm_device *dev)
9331 {
9332 struct intel_connector *connector;
9333 struct drm_connector *crt = NULL;
9334 struct intel_load_detect_pipe load_detect_temp;
9335
9336 /* We can't just switch on the pipe A, we need to set things up with a
9337 * proper mode and output configuration. As a gross hack, enable pipe A
9338 * by enabling the load detect pipe once. */
9339 list_for_each_entry(connector,
9340 &dev->mode_config.connector_list,
9341 base.head) {
9342 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9343 crt = &connector->base;
9344 break;
9345 }
9346 }
9347
9348 if (!crt)
9349 return;
9350
9351 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9352 intel_release_load_detect_pipe(crt, &load_detect_temp);
9353
9354
9355 }
9356
9357 static bool
9358 intel_check_plane_mapping(struct intel_crtc *crtc)
9359 {
9360 struct drm_device *dev = crtc->base.dev;
9361 struct drm_i915_private *dev_priv = dev->dev_private;
9362 u32 reg, val;
9363
9364 if (INTEL_INFO(dev)->num_pipes == 1)
9365 return true;
9366
9367 reg = DSPCNTR(!crtc->plane);
9368 val = I915_READ(reg);
9369
9370 if ((val & DISPLAY_PLANE_ENABLE) &&
9371 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9372 return false;
9373
9374 return true;
9375 }
9376
9377 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9378 {
9379 struct drm_device *dev = crtc->base.dev;
9380 struct drm_i915_private *dev_priv = dev->dev_private;
9381 u32 reg;
9382
9383 /* Clear any frame start delays used for debugging left by the BIOS */
9384 reg = PIPECONF(crtc->config.cpu_transcoder);
9385 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9386
9387 /* We need to sanitize the plane -> pipe mapping first because this will
9388 * disable the crtc (and hence change the state) if it is wrong. Note
9389 * that gen4+ has a fixed plane -> pipe mapping. */
9390 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9391 struct intel_connector *connector;
9392 bool plane;
9393
9394 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9395 crtc->base.base.id);
9396
9397 /* Pipe has the wrong plane attached and the plane is active.
9398 * Temporarily change the plane mapping and disable everything
9399 * ... */
9400 plane = crtc->plane;
9401 crtc->plane = !plane;
9402 dev_priv->display.crtc_disable(&crtc->base);
9403 crtc->plane = plane;
9404
9405 /* ... and break all links. */
9406 list_for_each_entry(connector, &dev->mode_config.connector_list,
9407 base.head) {
9408 if (connector->encoder->base.crtc != &crtc->base)
9409 continue;
9410
9411 intel_connector_break_all_links(connector);
9412 }
9413
9414 WARN_ON(crtc->active);
9415 crtc->base.enabled = false;
9416 }
9417
9418 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9419 crtc->pipe == PIPE_A && !crtc->active) {
9420 /* BIOS forgot to enable pipe A, this mostly happens after
9421 * resume. Force-enable the pipe to fix this, the update_dpms
9422 * call below we restore the pipe to the right state, but leave
9423 * the required bits on. */
9424 intel_enable_pipe_a(dev);
9425 }
9426
9427 /* Adjust the state of the output pipe according to whether we
9428 * have active connectors/encoders. */
9429 intel_crtc_update_dpms(&crtc->base);
9430
9431 if (crtc->active != crtc->base.enabled) {
9432 struct intel_encoder *encoder;
9433
9434 /* This can happen either due to bugs in the get_hw_state
9435 * functions or because the pipe is force-enabled due to the
9436 * pipe A quirk. */
9437 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9438 crtc->base.base.id,
9439 crtc->base.enabled ? "enabled" : "disabled",
9440 crtc->active ? "enabled" : "disabled");
9441
9442 crtc->base.enabled = crtc->active;
9443
9444 /* Because we only establish the connector -> encoder ->
9445 * crtc links if something is active, this means the
9446 * crtc is now deactivated. Break the links. connector
9447 * -> encoder links are only establish when things are
9448 * actually up, hence no need to break them. */
9449 WARN_ON(crtc->active);
9450
9451 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9452 WARN_ON(encoder->connectors_active);
9453 encoder->base.crtc = NULL;
9454 }
9455 }
9456 }
9457
9458 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9459 {
9460 struct intel_connector *connector;
9461 struct drm_device *dev = encoder->base.dev;
9462
9463 /* We need to check both for a crtc link (meaning that the
9464 * encoder is active and trying to read from a pipe) and the
9465 * pipe itself being active. */
9466 bool has_active_crtc = encoder->base.crtc &&
9467 to_intel_crtc(encoder->base.crtc)->active;
9468
9469 if (encoder->connectors_active && !has_active_crtc) {
9470 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9471 encoder->base.base.id,
9472 drm_get_encoder_name(&encoder->base));
9473
9474 /* Connector is active, but has no active pipe. This is
9475 * fallout from our resume register restoring. Disable
9476 * the encoder manually again. */
9477 if (encoder->base.crtc) {
9478 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9479 encoder->base.base.id,
9480 drm_get_encoder_name(&encoder->base));
9481 encoder->disable(encoder);
9482 }
9483
9484 /* Inconsistent output/port/pipe state happens presumably due to
9485 * a bug in one of the get_hw_state functions. Or someplace else
9486 * in our code, like the register restore mess on resume. Clamp
9487 * things to off as a safer default. */
9488 list_for_each_entry(connector,
9489 &dev->mode_config.connector_list,
9490 base.head) {
9491 if (connector->encoder != encoder)
9492 continue;
9493
9494 intel_connector_break_all_links(connector);
9495 }
9496 }
9497 /* Enabled encoders without active connectors will be fixed in
9498 * the crtc fixup. */
9499 }
9500
9501 void i915_redisable_vga(struct drm_device *dev)
9502 {
9503 struct drm_i915_private *dev_priv = dev->dev_private;
9504 u32 vga_reg = i915_vgacntrl_reg(dev);
9505
9506 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9507 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9508 i915_disable_vga(dev);
9509 }
9510 }
9511
9512 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9513 * and i915 state tracking structures. */
9514 void intel_modeset_setup_hw_state(struct drm_device *dev,
9515 bool force_restore)
9516 {
9517 struct drm_i915_private *dev_priv = dev->dev_private;
9518 enum pipe pipe;
9519 u32 tmp;
9520 struct drm_plane *plane;
9521 struct intel_crtc *crtc;
9522 struct intel_encoder *encoder;
9523 struct intel_connector *connector;
9524
9525 if (HAS_DDI(dev)) {
9526 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9527
9528 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9529 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9530 case TRANS_DDI_EDP_INPUT_A_ON:
9531 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9532 pipe = PIPE_A;
9533 break;
9534 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9535 pipe = PIPE_B;
9536 break;
9537 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9538 pipe = PIPE_C;
9539 break;
9540 default:
9541 /* A bogus value has been programmed, disable
9542 * the transcoder */
9543 WARN(1, "Bogus eDP source %08x\n", tmp);
9544 intel_ddi_disable_transcoder_func(dev_priv,
9545 TRANSCODER_EDP);
9546 goto setup_pipes;
9547 }
9548
9549 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9550 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9551
9552 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9553 pipe_name(pipe));
9554 }
9555 }
9556
9557 setup_pipes:
9558 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9559 base.head) {
9560 enum transcoder tmp = crtc->config.cpu_transcoder;
9561 memset(&crtc->config, 0, sizeof(crtc->config));
9562 crtc->config.cpu_transcoder = tmp;
9563
9564 crtc->active = dev_priv->display.get_pipe_config(crtc,
9565 &crtc->config);
9566
9567 crtc->base.enabled = crtc->active;
9568
9569 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9570 crtc->base.base.id,
9571 crtc->active ? "enabled" : "disabled");
9572 }
9573
9574 if (HAS_DDI(dev))
9575 intel_ddi_setup_hw_pll_state(dev);
9576
9577 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9578 base.head) {
9579 pipe = 0;
9580
9581 if (encoder->get_hw_state(encoder, &pipe)) {
9582 encoder->base.crtc =
9583 dev_priv->pipe_to_crtc_mapping[pipe];
9584 } else {
9585 encoder->base.crtc = NULL;
9586 }
9587
9588 encoder->connectors_active = false;
9589 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9590 encoder->base.base.id,
9591 drm_get_encoder_name(&encoder->base),
9592 encoder->base.crtc ? "enabled" : "disabled",
9593 pipe);
9594 }
9595
9596 list_for_each_entry(connector, &dev->mode_config.connector_list,
9597 base.head) {
9598 if (connector->get_hw_state(connector)) {
9599 connector->base.dpms = DRM_MODE_DPMS_ON;
9600 connector->encoder->connectors_active = true;
9601 connector->base.encoder = &connector->encoder->base;
9602 } else {
9603 connector->base.dpms = DRM_MODE_DPMS_OFF;
9604 connector->base.encoder = NULL;
9605 }
9606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9607 connector->base.base.id,
9608 drm_get_connector_name(&connector->base),
9609 connector->base.encoder ? "enabled" : "disabled");
9610 }
9611
9612 /* HW state is read out, now we need to sanitize this mess. */
9613 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9614 base.head) {
9615 intel_sanitize_encoder(encoder);
9616 }
9617
9618 for_each_pipe(pipe) {
9619 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9620 intel_sanitize_crtc(crtc);
9621 }
9622
9623 if (force_restore) {
9624 /*
9625 * We need to use raw interfaces for restoring state to avoid
9626 * checking (bogus) intermediate states.
9627 */
9628 for_each_pipe(pipe) {
9629 struct drm_crtc *crtc =
9630 dev_priv->pipe_to_crtc_mapping[pipe];
9631
9632 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9633 crtc->fb);
9634 }
9635 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9636 intel_plane_restore(plane);
9637
9638 i915_redisable_vga(dev);
9639 } else {
9640 intel_modeset_update_staged_output_state(dev);
9641 }
9642
9643 intel_modeset_check_state(dev);
9644
9645 drm_mode_config_reset(dev);
9646 }
9647
9648 void intel_modeset_gem_init(struct drm_device *dev)
9649 {
9650 intel_modeset_init_hw(dev);
9651
9652 intel_setup_overlay(dev);
9653
9654 intel_modeset_setup_hw_state(dev, false);
9655 }
9656
9657 void intel_modeset_cleanup(struct drm_device *dev)
9658 {
9659 struct drm_i915_private *dev_priv = dev->dev_private;
9660 struct drm_crtc *crtc;
9661 struct intel_crtc *intel_crtc;
9662
9663 /*
9664 * Interrupts and polling as the first thing to avoid creating havoc.
9665 * Too much stuff here (turning of rps, connectors, ...) would
9666 * experience fancy races otherwise.
9667 */
9668 drm_irq_uninstall(dev);
9669 cancel_work_sync(&dev_priv->hotplug_work);
9670 /*
9671 * Due to the hpd irq storm handling the hotplug work can re-arm the
9672 * poll handlers. Hence disable polling after hpd handling is shut down.
9673 */
9674 drm_kms_helper_poll_fini(dev);
9675
9676 mutex_lock(&dev->struct_mutex);
9677
9678 intel_unregister_dsm_handler();
9679
9680 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9681 /* Skip inactive CRTCs */
9682 if (!crtc->fb)
9683 continue;
9684
9685 intel_crtc = to_intel_crtc(crtc);
9686 intel_increase_pllclock(crtc);
9687 }
9688
9689 intel_disable_fbc(dev);
9690
9691 intel_disable_gt_powersave(dev);
9692
9693 ironlake_teardown_rc6(dev);
9694
9695 mutex_unlock(&dev->struct_mutex);
9696
9697 /* flush any delayed tasks or pending work */
9698 flush_scheduled_work();
9699
9700 /* destroy backlight, if any, before the connectors */
9701 intel_panel_destroy_backlight(dev);
9702
9703 drm_mode_config_cleanup(dev);
9704
9705 intel_cleanup_overlay(dev);
9706 }
9707
9708 /*
9709 * Return which encoder is currently attached for connector.
9710 */
9711 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9712 {
9713 return &intel_attached_encoder(connector)->base;
9714 }
9715
9716 void intel_connector_attach_encoder(struct intel_connector *connector,
9717 struct intel_encoder *encoder)
9718 {
9719 connector->encoder = encoder;
9720 drm_mode_connector_attach_encoder(&connector->base,
9721 &encoder->base);
9722 }
9723
9724 /*
9725 * set vga decode state - true == enable VGA decode
9726 */
9727 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9728 {
9729 struct drm_i915_private *dev_priv = dev->dev_private;
9730 u16 gmch_ctrl;
9731
9732 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9733 if (state)
9734 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9735 else
9736 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9737 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9738 return 0;
9739 }
9740
9741 #ifdef CONFIG_DEBUG_FS
9742 #include <linux/seq_file.h>
9743
9744 struct intel_display_error_state {
9745
9746 u32 power_well_driver;
9747
9748 struct intel_cursor_error_state {
9749 u32 control;
9750 u32 position;
9751 u32 base;
9752 u32 size;
9753 } cursor[I915_MAX_PIPES];
9754
9755 struct intel_pipe_error_state {
9756 enum transcoder cpu_transcoder;
9757 u32 conf;
9758 u32 source;
9759
9760 u32 htotal;
9761 u32 hblank;
9762 u32 hsync;
9763 u32 vtotal;
9764 u32 vblank;
9765 u32 vsync;
9766 } pipe[I915_MAX_PIPES];
9767
9768 struct intel_plane_error_state {
9769 u32 control;
9770 u32 stride;
9771 u32 size;
9772 u32 pos;
9773 u32 addr;
9774 u32 surface;
9775 u32 tile_offset;
9776 } plane[I915_MAX_PIPES];
9777 };
9778
9779 struct intel_display_error_state *
9780 intel_display_capture_error_state(struct drm_device *dev)
9781 {
9782 drm_i915_private_t *dev_priv = dev->dev_private;
9783 struct intel_display_error_state *error;
9784 enum transcoder cpu_transcoder;
9785 int i;
9786
9787 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9788 if (error == NULL)
9789 return NULL;
9790
9791 if (HAS_POWER_WELL(dev))
9792 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9793
9794 for_each_pipe(i) {
9795 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9796 error->pipe[i].cpu_transcoder = cpu_transcoder;
9797
9798 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9799 error->cursor[i].control = I915_READ(CURCNTR(i));
9800 error->cursor[i].position = I915_READ(CURPOS(i));
9801 error->cursor[i].base = I915_READ(CURBASE(i));
9802 } else {
9803 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9804 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9805 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9806 }
9807
9808 error->plane[i].control = I915_READ(DSPCNTR(i));
9809 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9810 if (INTEL_INFO(dev)->gen <= 3) {
9811 error->plane[i].size = I915_READ(DSPSIZE(i));
9812 error->plane[i].pos = I915_READ(DSPPOS(i));
9813 }
9814 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9815 error->plane[i].addr = I915_READ(DSPADDR(i));
9816 if (INTEL_INFO(dev)->gen >= 4) {
9817 error->plane[i].surface = I915_READ(DSPSURF(i));
9818 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9819 }
9820
9821 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9822 error->pipe[i].source = I915_READ(PIPESRC(i));
9823 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9824 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9825 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9826 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9827 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9828 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9829 }
9830
9831 /* In the code above we read the registers without checking if the power
9832 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9833 * prevent the next I915_WRITE from detecting it and printing an error
9834 * message. */
9835 if (HAS_POWER_WELL(dev))
9836 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9837
9838 return error;
9839 }
9840
9841 void
9842 intel_display_print_error_state(struct seq_file *m,
9843 struct drm_device *dev,
9844 struct intel_display_error_state *error)
9845 {
9846 int i;
9847
9848 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9849 if (HAS_POWER_WELL(dev))
9850 seq_printf(m, "PWR_WELL_CTL2: %08x\n",
9851 error->power_well_driver);
9852 for_each_pipe(i) {
9853 seq_printf(m, "Pipe [%d]:\n", i);
9854 seq_printf(m, " CPU transcoder: %c\n",
9855 transcoder_name(error->pipe[i].cpu_transcoder));
9856 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9857 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9858 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9859 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9860 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9861 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9862 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9863 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9864
9865 seq_printf(m, "Plane [%d]:\n", i);
9866 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9867 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9868 if (INTEL_INFO(dev)->gen <= 3) {
9869 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9870 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9871 }
9872 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9873 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9874 if (INTEL_INFO(dev)->gen >= 4) {
9875 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9876 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9877 }
9878
9879 seq_printf(m, "Cursor [%d]:\n", i);
9880 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9881 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9882 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9883 }
9884 }
9885 #endif
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