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Merge tag 'drm-amdkfd-next-2017-10-18' of git://people.freedesktop.org/~gabbayo/linux...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
51
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
54 DRM_FORMAT_C8,
55 DRM_FORMAT_RGB565,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_XRGB8888,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_C8,
63 DRM_FORMAT_RGB565,
64 DRM_FORMAT_XRGB8888,
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 };
69
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
74 };
75
76 static const uint32_t skl_primary_formats[] = {
77 DRM_FORMAT_C8,
78 DRM_FORMAT_RGB565,
79 DRM_FORMAT_XRGB8888,
80 DRM_FORMAT_XBGR8888,
81 DRM_FORMAT_ARGB8888,
82 DRM_FORMAT_ABGR8888,
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
85 DRM_FORMAT_YUYV,
86 DRM_FORMAT_YVYU,
87 DRM_FORMAT_UYVY,
88 DRM_FORMAT_VYUY,
89 };
90
91 static const uint64_t skl_format_modifiers_noccs[] = {
92 I915_FORMAT_MOD_Yf_TILED,
93 I915_FORMAT_MOD_Y_TILED,
94 I915_FORMAT_MOD_X_TILED,
95 DRM_FORMAT_MOD_LINEAR,
96 DRM_FORMAT_MOD_INVALID
97 };
98
99 static const uint64_t skl_format_modifiers_ccs[] = {
100 I915_FORMAT_MOD_Yf_TILED_CCS,
101 I915_FORMAT_MOD_Y_TILED_CCS,
102 I915_FORMAT_MOD_Yf_TILED,
103 I915_FORMAT_MOD_Y_TILED,
104 I915_FORMAT_MOD_X_TILED,
105 DRM_FORMAT_MOD_LINEAR,
106 DRM_FORMAT_MOD_INVALID
107 };
108
109 /* Cursor formats */
110 static const uint32_t intel_cursor_formats[] = {
111 DRM_FORMAT_ARGB8888,
112 };
113
114 static const uint64_t cursor_format_modifiers[] = {
115 DRM_FORMAT_MOD_LINEAR,
116 DRM_FORMAT_MOD_INVALID
117 };
118
119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
120 struct intel_crtc_state *pipe_config);
121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
122 struct intel_crtc_state *pipe_config);
123
124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
125 struct drm_i915_gem_object *obj,
126 struct drm_mode_fb_cmd2 *mode_cmd);
127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
131 struct intel_link_m_n *m_n,
132 struct intel_link_m_n *m2_n2);
133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
136 static void vlv_prepare_pll(struct intel_crtc *crtc,
137 const struct intel_crtc_state *pipe_config);
138 static void chv_prepare_pll(struct intel_crtc *crtc,
139 const struct intel_crtc_state *pipe_config);
140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
143 struct intel_crtc_state *crtc_state);
144 static void skylake_pfit_enable(struct intel_crtc *crtc);
145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
148 struct drm_modeset_acquire_ctx *ctx);
149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
150
151 struct intel_limit {
152 struct {
153 int min, max;
154 } dot, vco, n, m, m1, m2, p, p1;
155
156 struct {
157 int dot_limit;
158 int p2_slow, p2_fast;
159 } p2;
160 };
161
162 /* returns HPLL frequency in kHz */
163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
164 {
165 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
166
167 /* Obtain SKU information */
168 mutex_lock(&dev_priv->sb_lock);
169 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
170 CCK_FUSE_HPLL_FREQ_MASK;
171 mutex_unlock(&dev_priv->sb_lock);
172
173 return vco_freq[hpll_freq] * 1000;
174 }
175
176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
177 const char *name, u32 reg, int ref_freq)
178 {
179 u32 val;
180 int divider;
181
182 mutex_lock(&dev_priv->sb_lock);
183 val = vlv_cck_read(dev_priv, reg);
184 mutex_unlock(&dev_priv->sb_lock);
185
186 divider = val & CCK_FREQUENCY_VALUES;
187
188 WARN((val & CCK_FREQUENCY_STATUS) !=
189 (divider << CCK_FREQUENCY_STATUS_SHIFT),
190 "%s change in progress\n", name);
191
192 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
193 }
194
195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
196 const char *name, u32 reg)
197 {
198 if (dev_priv->hpll_freq == 0)
199 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
200
201 return vlv_get_cck_clock(dev_priv, name, reg,
202 dev_priv->hpll_freq);
203 }
204
205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
206 {
207 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
208 return;
209
210 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
211 CCK_CZ_CLOCK_CONTROL);
212
213 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
214 }
215
216 static inline u32 /* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
218 const struct intel_crtc_state *pipe_config)
219 {
220 if (HAS_DDI(dev_priv))
221 return pipe_config->port_clock; /* SPLL */
222 else if (IS_GEN5(dev_priv))
223 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
224 else
225 return 270000;
226 }
227
228 static const struct intel_limit intel_limits_i8xx_dac = {
229 .dot = { .min = 25000, .max = 350000 },
230 .vco = { .min = 908000, .max = 1512000 },
231 .n = { .min = 2, .max = 16 },
232 .m = { .min = 96, .max = 140 },
233 .m1 = { .min = 18, .max = 26 },
234 .m2 = { .min = 6, .max = 16 },
235 .p = { .min = 4, .max = 128 },
236 .p1 = { .min = 2, .max = 33 },
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 4, .p2_fast = 2 },
239 };
240
241 static const struct intel_limit intel_limits_i8xx_dvo = {
242 .dot = { .min = 25000, .max = 350000 },
243 .vco = { .min = 908000, .max = 1512000 },
244 .n = { .min = 2, .max = 16 },
245 .m = { .min = 96, .max = 140 },
246 .m1 = { .min = 18, .max = 26 },
247 .m2 = { .min = 6, .max = 16 },
248 .p = { .min = 4, .max = 128 },
249 .p1 = { .min = 2, .max = 33 },
250 .p2 = { .dot_limit = 165000,
251 .p2_slow = 4, .p2_fast = 4 },
252 };
253
254 static const struct intel_limit intel_limits_i8xx_lvds = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 1, .max = 6 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 14, .p2_fast = 7 },
265 };
266
267 static const struct intel_limit intel_limits_i9xx_sdvo = {
268 .dot = { .min = 20000, .max = 400000 },
269 .vco = { .min = 1400000, .max = 2800000 },
270 .n = { .min = 1, .max = 6 },
271 .m = { .min = 70, .max = 120 },
272 .m1 = { .min = 8, .max = 18 },
273 .m2 = { .min = 3, .max = 7 },
274 .p = { .min = 5, .max = 80 },
275 .p1 = { .min = 1, .max = 8 },
276 .p2 = { .dot_limit = 200000,
277 .p2_slow = 10, .p2_fast = 5 },
278 };
279
280 static const struct intel_limit intel_limits_i9xx_lvds = {
281 .dot = { .min = 20000, .max = 400000 },
282 .vco = { .min = 1400000, .max = 2800000 },
283 .n = { .min = 1, .max = 6 },
284 .m = { .min = 70, .max = 120 },
285 .m1 = { .min = 8, .max = 18 },
286 .m2 = { .min = 3, .max = 7 },
287 .p = { .min = 7, .max = 98 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 112000,
290 .p2_slow = 14, .p2_fast = 7 },
291 };
292
293
294 static const struct intel_limit intel_limits_g4x_sdvo = {
295 .dot = { .min = 25000, .max = 270000 },
296 .vco = { .min = 1750000, .max = 3500000},
297 .n = { .min = 1, .max = 4 },
298 .m = { .min = 104, .max = 138 },
299 .m1 = { .min = 17, .max = 23 },
300 .m2 = { .min = 5, .max = 11 },
301 .p = { .min = 10, .max = 30 },
302 .p1 = { .min = 1, .max = 3},
303 .p2 = { .dot_limit = 270000,
304 .p2_slow = 10,
305 .p2_fast = 10
306 },
307 };
308
309 static const struct intel_limit intel_limits_g4x_hdmi = {
310 .dot = { .min = 22000, .max = 400000 },
311 .vco = { .min = 1750000, .max = 3500000},
312 .n = { .min = 1, .max = 4 },
313 .m = { .min = 104, .max = 138 },
314 .m1 = { .min = 16, .max = 23 },
315 .m2 = { .min = 5, .max = 11 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8},
318 .p2 = { .dot_limit = 165000,
319 .p2_slow = 10, .p2_fast = 5 },
320 };
321
322 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
323 .dot = { .min = 20000, .max = 115000 },
324 .vco = { .min = 1750000, .max = 3500000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 104, .max = 138 },
327 .m1 = { .min = 17, .max = 23 },
328 .m2 = { .min = 5, .max = 11 },
329 .p = { .min = 28, .max = 112 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 0,
332 .p2_slow = 14, .p2_fast = 14
333 },
334 };
335
336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
337 .dot = { .min = 80000, .max = 224000 },
338 .vco = { .min = 1750000, .max = 3500000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 104, .max = 138 },
341 .m1 = { .min = 17, .max = 23 },
342 .m2 = { .min = 5, .max = 11 },
343 .p = { .min = 14, .max = 42 },
344 .p1 = { .min = 2, .max = 6 },
345 .p2 = { .dot_limit = 0,
346 .p2_slow = 7, .p2_fast = 7
347 },
348 };
349
350 static const struct intel_limit intel_limits_pineview_sdvo = {
351 .dot = { .min = 20000, .max = 400000},
352 .vco = { .min = 1700000, .max = 3500000 },
353 /* Pineview's Ncounter is a ring counter */
354 .n = { .min = 3, .max = 6 },
355 .m = { .min = 2, .max = 256 },
356 /* Pineview only has one combined m divider, which we treat as m2. */
357 .m1 = { .min = 0, .max = 0 },
358 .m2 = { .min = 0, .max = 254 },
359 .p = { .min = 5, .max = 80 },
360 .p1 = { .min = 1, .max = 8 },
361 .p2 = { .dot_limit = 200000,
362 .p2_slow = 10, .p2_fast = 5 },
363 };
364
365 static const struct intel_limit intel_limits_pineview_lvds = {
366 .dot = { .min = 20000, .max = 400000 },
367 .vco = { .min = 1700000, .max = 3500000 },
368 .n = { .min = 3, .max = 6 },
369 .m = { .min = 2, .max = 256 },
370 .m1 = { .min = 0, .max = 0 },
371 .m2 = { .min = 0, .max = 254 },
372 .p = { .min = 7, .max = 112 },
373 .p1 = { .min = 1, .max = 8 },
374 .p2 = { .dot_limit = 112000,
375 .p2_slow = 14, .p2_fast = 14 },
376 };
377
378 /* Ironlake / Sandybridge
379 *
380 * We calculate clock using (register_value + 2) for N/M1/M2, so here
381 * the range value for them is (actual_value - 2).
382 */
383 static const struct intel_limit intel_limits_ironlake_dac = {
384 .dot = { .min = 25000, .max = 350000 },
385 .vco = { .min = 1760000, .max = 3510000 },
386 .n = { .min = 1, .max = 5 },
387 .m = { .min = 79, .max = 127 },
388 .m1 = { .min = 12, .max = 22 },
389 .m2 = { .min = 5, .max = 9 },
390 .p = { .min = 5, .max = 80 },
391 .p1 = { .min = 1, .max = 8 },
392 .p2 = { .dot_limit = 225000,
393 .p2_slow = 10, .p2_fast = 5 },
394 };
395
396 static const struct intel_limit intel_limits_ironlake_single_lvds = {
397 .dot = { .min = 25000, .max = 350000 },
398 .vco = { .min = 1760000, .max = 3510000 },
399 .n = { .min = 1, .max = 3 },
400 .m = { .min = 79, .max = 118 },
401 .m1 = { .min = 12, .max = 22 },
402 .m2 = { .min = 5, .max = 9 },
403 .p = { .min = 28, .max = 112 },
404 .p1 = { .min = 2, .max = 8 },
405 .p2 = { .dot_limit = 225000,
406 .p2_slow = 14, .p2_fast = 14 },
407 };
408
409 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 3 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 14, .max = 56 },
417 .p1 = { .min = 2, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 7, .p2_fast = 7 },
420 };
421
422 /* LVDS 100mhz refclk limits. */
423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
424 .dot = { .min = 25000, .max = 350000 },
425 .vco = { .min = 1760000, .max = 3510000 },
426 .n = { .min = 1, .max = 2 },
427 .m = { .min = 79, .max = 126 },
428 .m1 = { .min = 12, .max = 22 },
429 .m2 = { .min = 5, .max = 9 },
430 .p = { .min = 28, .max = 112 },
431 .p1 = { .min = 2, .max = 8 },
432 .p2 = { .dot_limit = 225000,
433 .p2_slow = 14, .p2_fast = 14 },
434 };
435
436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
437 .dot = { .min = 25000, .max = 350000 },
438 .vco = { .min = 1760000, .max = 3510000 },
439 .n = { .min = 1, .max = 3 },
440 .m = { .min = 79, .max = 126 },
441 .m1 = { .min = 12, .max = 22 },
442 .m2 = { .min = 5, .max = 9 },
443 .p = { .min = 14, .max = 42 },
444 .p1 = { .min = 2, .max = 6 },
445 .p2 = { .dot_limit = 225000,
446 .p2_slow = 7, .p2_fast = 7 },
447 };
448
449 static const struct intel_limit intel_limits_vlv = {
450 /*
451 * These are the data rate limits (measured in fast clocks)
452 * since those are the strictest limits we have. The fast
453 * clock and actual rate limits are more relaxed, so checking
454 * them would make no difference.
455 */
456 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
457 .vco = { .min = 4000000, .max = 6000000 },
458 .n = { .min = 1, .max = 7 },
459 .m1 = { .min = 2, .max = 3 },
460 .m2 = { .min = 11, .max = 156 },
461 .p1 = { .min = 2, .max = 3 },
462 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
463 };
464
465 static const struct intel_limit intel_limits_chv = {
466 /*
467 * These are the data rate limits (measured in fast clocks)
468 * since those are the strictest limits we have. The fast
469 * clock and actual rate limits are more relaxed, so checking
470 * them would make no difference.
471 */
472 .dot = { .min = 25000 * 5, .max = 540000 * 5},
473 .vco = { .min = 4800000, .max = 6480000 },
474 .n = { .min = 1, .max = 1 },
475 .m1 = { .min = 2, .max = 2 },
476 .m2 = { .min = 24 << 22, .max = 175 << 22 },
477 .p1 = { .min = 2, .max = 4 },
478 .p2 = { .p2_slow = 1, .p2_fast = 14 },
479 };
480
481 static const struct intel_limit intel_limits_bxt = {
482 /* FIXME: find real dot limits */
483 .dot = { .min = 0, .max = INT_MAX },
484 .vco = { .min = 4800000, .max = 6700000 },
485 .n = { .min = 1, .max = 1 },
486 .m1 = { .min = 2, .max = 2 },
487 /* FIXME: find real m2 limits */
488 .m2 = { .min = 2 << 22, .max = 255 << 22 },
489 .p1 = { .min = 2, .max = 4 },
490 .p2 = { .p2_slow = 1, .p2_fast = 20 },
491 };
492
493 static bool
494 needs_modeset(struct drm_crtc_state *state)
495 {
496 return drm_atomic_crtc_needs_modeset(state);
497 }
498
499 /*
500 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
501 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
502 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
503 * The helpers' return value is the rate of the clock that is fed to the
504 * display engine's pipe which can be the above fast dot clock rate or a
505 * divided-down version of it.
506 */
507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
508 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
509 {
510 clock->m = clock->m2 + 2;
511 clock->p = clock->p1 * clock->p2;
512 if (WARN_ON(clock->n == 0 || clock->p == 0))
513 return 0;
514 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
515 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
516
517 return clock->dot;
518 }
519
520 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
521 {
522 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
523 }
524
525 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
526 {
527 clock->m = i9xx_dpll_compute_m(clock);
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
530 return 0;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534 return clock->dot;
535 }
536
537 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
538 {
539 clock->m = clock->m1 * clock->m2;
540 clock->p = clock->p1 * clock->p2;
541 if (WARN_ON(clock->n == 0 || clock->p == 0))
542 return 0;
543 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
544 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
545
546 return clock->dot / 5;
547 }
548
549 int chv_calc_dpll_params(int refclk, struct dpll *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return 0;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558
559 return clock->dot / 5;
560 }
561
562 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
563 /**
564 * Returns whether the given set of divisors are valid for a given refclk with
565 * the given connectors.
566 */
567
568 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
569 const struct intel_limit *limit,
570 const struct dpll *clock)
571 {
572 if (clock->n < limit->n.min || limit->n.max < clock->n)
573 INTELPllInvalid("n out of range\n");
574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
577 INTELPllInvalid("m2 out of range\n");
578 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
579 INTELPllInvalid("m1 out of range\n");
580
581 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
582 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
583 if (clock->m1 <= clock->m2)
584 INTELPllInvalid("m1 <= m2\n");
585
586 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
587 !IS_GEN9_LP(dev_priv)) {
588 if (clock->p < limit->p.min || limit->p.max < clock->p)
589 INTELPllInvalid("p out of range\n");
590 if (clock->m < limit->m.min || limit->m.max < clock->m)
591 INTELPllInvalid("m out of range\n");
592 }
593
594 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
595 INTELPllInvalid("vco out of range\n");
596 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
597 * connector, etc., rather than just a single range.
598 */
599 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
600 INTELPllInvalid("dot out of range\n");
601
602 return true;
603 }
604
605 static int
606 i9xx_select_p2_div(const struct intel_limit *limit,
607 const struct intel_crtc_state *crtc_state,
608 int target)
609 {
610 struct drm_device *dev = crtc_state->base.crtc->dev;
611
612 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
613 /*
614 * For LVDS just rely on its current settings for dual-channel.
615 * We haven't figured out how to reliably set up different
616 * single/dual channel state, if we even can.
617 */
618 if (intel_is_dual_link_lvds(dev))
619 return limit->p2.p2_fast;
620 else
621 return limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 return limit->p2.p2_slow;
625 else
626 return limit->p2.p2_fast;
627 }
628 }
629
630 /*
631 * Returns a set of divisors for the desired target clock with the given
632 * refclk, or FALSE. The returned values represent the clock equation:
633 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
634 *
635 * Target and reference clocks are specified in kHz.
636 *
637 * If match_clock is provided, then best_clock P divider must match the P
638 * divider from @match_clock used for LVDS downclocking.
639 */
640 static bool
641 i9xx_find_best_dpll(const struct intel_limit *limit,
642 struct intel_crtc_state *crtc_state,
643 int target, int refclk, struct dpll *match_clock,
644 struct dpll *best_clock)
645 {
646 struct drm_device *dev = crtc_state->base.crtc->dev;
647 struct dpll clock;
648 int err = target;
649
650 memset(best_clock, 0, sizeof(*best_clock));
651
652 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
653
654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
658 if (clock.m2 >= clock.m1)
659 break;
660 for (clock.n = limit->n.min;
661 clock.n <= limit->n.max; clock.n++) {
662 for (clock.p1 = limit->p1.min;
663 clock.p1 <= limit->p1.max; clock.p1++) {
664 int this_err;
665
666 i9xx_calc_dpll_params(refclk, &clock);
667 if (!intel_PLL_is_valid(to_i915(dev),
668 limit,
669 &clock))
670 continue;
671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686 }
687
688 /*
689 * Returns a set of divisors for the desired target clock with the given
690 * refclk, or FALSE. The returned values represent the clock equation:
691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
692 *
693 * Target and reference clocks are specified in kHz.
694 *
695 * If match_clock is provided, then best_clock P divider must match the P
696 * divider from @match_clock used for LVDS downclocking.
697 */
698 static bool
699 pnv_find_best_dpll(const struct intel_limit *limit,
700 struct intel_crtc_state *crtc_state,
701 int target, int refclk, struct dpll *match_clock,
702 struct dpll *best_clock)
703 {
704 struct drm_device *dev = crtc_state->base.crtc->dev;
705 struct dpll clock;
706 int err = target;
707
708 memset(best_clock, 0, sizeof(*best_clock));
709
710 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
711
712 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
713 clock.m1++) {
714 for (clock.m2 = limit->m2.min;
715 clock.m2 <= limit->m2.max; clock.m2++) {
716 for (clock.n = limit->n.min;
717 clock.n <= limit->n.max; clock.n++) {
718 for (clock.p1 = limit->p1.min;
719 clock.p1 <= limit->p1.max; clock.p1++) {
720 int this_err;
721
722 pnv_calc_dpll_params(refclk, &clock);
723 if (!intel_PLL_is_valid(to_i915(dev),
724 limit,
725 &clock))
726 continue;
727 if (match_clock &&
728 clock.p != match_clock->p)
729 continue;
730
731 this_err = abs(clock.dot - target);
732 if (this_err < err) {
733 *best_clock = clock;
734 err = this_err;
735 }
736 }
737 }
738 }
739 }
740
741 return (err != target);
742 }
743
744 /*
745 * Returns a set of divisors for the desired target clock with the given
746 * refclk, or FALSE. The returned values represent the clock equation:
747 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
748 *
749 * Target and reference clocks are specified in kHz.
750 *
751 * If match_clock is provided, then best_clock P divider must match the P
752 * divider from @match_clock used for LVDS downclocking.
753 */
754 static bool
755 g4x_find_best_dpll(const struct intel_limit *limit,
756 struct intel_crtc_state *crtc_state,
757 int target, int refclk, struct dpll *match_clock,
758 struct dpll *best_clock)
759 {
760 struct drm_device *dev = crtc_state->base.crtc->dev;
761 struct dpll clock;
762 int max_n;
763 bool found = false;
764 /* approximately equals target * 0.00585 */
765 int err_most = (target >> 8) + (target >> 9);
766
767 memset(best_clock, 0, sizeof(*best_clock));
768
769 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
770
771 max_n = limit->n.max;
772 /* based on hardware requirement, prefer smaller n to precision */
773 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
774 /* based on hardware requirement, prefere larger m1,m2 */
775 for (clock.m1 = limit->m1.max;
776 clock.m1 >= limit->m1.min; clock.m1--) {
777 for (clock.m2 = limit->m2.max;
778 clock.m2 >= limit->m2.min; clock.m2--) {
779 for (clock.p1 = limit->p1.max;
780 clock.p1 >= limit->p1.min; clock.p1--) {
781 int this_err;
782
783 i9xx_calc_dpll_params(refclk, &clock);
784 if (!intel_PLL_is_valid(to_i915(dev),
785 limit,
786 &clock))
787 continue;
788
789 this_err = abs(clock.dot - target);
790 if (this_err < err_most) {
791 *best_clock = clock;
792 err_most = this_err;
793 max_n = clock.n;
794 found = true;
795 }
796 }
797 }
798 }
799 }
800 return found;
801 }
802
803 /*
804 * Check if the calculated PLL configuration is more optimal compared to the
805 * best configuration and error found so far. Return the calculated error.
806 */
807 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
808 const struct dpll *calculated_clock,
809 const struct dpll *best_clock,
810 unsigned int best_error_ppm,
811 unsigned int *error_ppm)
812 {
813 /*
814 * For CHV ignore the error and consider only the P value.
815 * Prefer a bigger P value based on HW requirements.
816 */
817 if (IS_CHERRYVIEW(to_i915(dev))) {
818 *error_ppm = 0;
819
820 return calculated_clock->p > best_clock->p;
821 }
822
823 if (WARN_ON_ONCE(!target_freq))
824 return false;
825
826 *error_ppm = div_u64(1000000ULL *
827 abs(target_freq - calculated_clock->dot),
828 target_freq);
829 /*
830 * Prefer a better P value over a better (smaller) error if the error
831 * is small. Ensure this preference for future configurations too by
832 * setting the error to 0.
833 */
834 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
835 *error_ppm = 0;
836
837 return true;
838 }
839
840 return *error_ppm + 10 < best_error_ppm;
841 }
842
843 /*
844 * Returns a set of divisors for the desired target clock with the given
845 * refclk, or FALSE. The returned values represent the clock equation:
846 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
847 */
848 static bool
849 vlv_find_best_dpll(const struct intel_limit *limit,
850 struct intel_crtc_state *crtc_state,
851 int target, int refclk, struct dpll *match_clock,
852 struct dpll *best_clock)
853 {
854 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
855 struct drm_device *dev = crtc->base.dev;
856 struct dpll clock;
857 unsigned int bestppm = 1000000;
858 /* min update 19.2 MHz */
859 int max_n = min(limit->n.max, refclk / 19200);
860 bool found = false;
861
862 target *= 5; /* fast clock */
863
864 memset(best_clock, 0, sizeof(*best_clock));
865
866 /* based on hardware requirement, prefer smaller n to precision */
867 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
868 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
869 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
870 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
871 clock.p = clock.p1 * clock.p2;
872 /* based on hardware requirement, prefer bigger m1,m2 values */
873 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
874 unsigned int ppm;
875
876 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
877 refclk * clock.m1);
878
879 vlv_calc_dpll_params(refclk, &clock);
880
881 if (!intel_PLL_is_valid(to_i915(dev),
882 limit,
883 &clock))
884 continue;
885
886 if (!vlv_PLL_is_optimal(dev, target,
887 &clock,
888 best_clock,
889 bestppm, &ppm))
890 continue;
891
892 *best_clock = clock;
893 bestppm = ppm;
894 found = true;
895 }
896 }
897 }
898 }
899
900 return found;
901 }
902
903 /*
904 * Returns a set of divisors for the desired target clock with the given
905 * refclk, or FALSE. The returned values represent the clock equation:
906 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
907 */
908 static bool
909 chv_find_best_dpll(const struct intel_limit *limit,
910 struct intel_crtc_state *crtc_state,
911 int target, int refclk, struct dpll *match_clock,
912 struct dpll *best_clock)
913 {
914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
915 struct drm_device *dev = crtc->base.dev;
916 unsigned int best_error_ppm;
917 struct dpll clock;
918 uint64_t m2;
919 int found = false;
920
921 memset(best_clock, 0, sizeof(*best_clock));
922 best_error_ppm = 1000000;
923
924 /*
925 * Based on hardware doc, the n always set to 1, and m1 always
926 * set to 2. If requires to support 200Mhz refclk, we need to
927 * revisit this because n may not 1 anymore.
928 */
929 clock.n = 1, clock.m1 = 2;
930 target *= 5; /* fast clock */
931
932 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
933 for (clock.p2 = limit->p2.p2_fast;
934 clock.p2 >= limit->p2.p2_slow;
935 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
936 unsigned int error_ppm;
937
938 clock.p = clock.p1 * clock.p2;
939
940 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
941 clock.n) << 22, refclk * clock.m1);
942
943 if (m2 > INT_MAX/clock.m1)
944 continue;
945
946 clock.m2 = m2;
947
948 chv_calc_dpll_params(refclk, &clock);
949
950 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
951 continue;
952
953 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
954 best_error_ppm, &error_ppm))
955 continue;
956
957 *best_clock = clock;
958 best_error_ppm = error_ppm;
959 found = true;
960 }
961 }
962
963 return found;
964 }
965
966 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
967 struct dpll *best_clock)
968 {
969 int refclk = 100000;
970 const struct intel_limit *limit = &intel_limits_bxt;
971
972 return chv_find_best_dpll(limit, crtc_state,
973 target_clock, refclk, NULL, best_clock);
974 }
975
976 bool intel_crtc_active(struct intel_crtc *crtc)
977 {
978 /* Be paranoid as we can arrive here with only partial
979 * state retrieved from the hardware during setup.
980 *
981 * We can ditch the adjusted_mode.crtc_clock check as soon
982 * as Haswell has gained clock readout/fastboot support.
983 *
984 * We can ditch the crtc->primary->fb check as soon as we can
985 * properly reconstruct framebuffers.
986 *
987 * FIXME: The intel_crtc->active here should be switched to
988 * crtc->state->active once we have proper CRTC states wired up
989 * for atomic.
990 */
991 return crtc->active && crtc->base.primary->state->fb &&
992 crtc->config->base.adjusted_mode.crtc_clock;
993 }
994
995 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
996 enum pipe pipe)
997 {
998 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
999
1000 return crtc->config->cpu_transcoder;
1001 }
1002
1003 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1004 {
1005 i915_reg_t reg = PIPEDSL(pipe);
1006 u32 line1, line2;
1007 u32 line_mask;
1008
1009 if (IS_GEN2(dev_priv))
1010 line_mask = DSL_LINEMASK_GEN2;
1011 else
1012 line_mask = DSL_LINEMASK_GEN3;
1013
1014 line1 = I915_READ(reg) & line_mask;
1015 msleep(5);
1016 line2 = I915_READ(reg) & line_mask;
1017
1018 return line1 == line2;
1019 }
1020
1021 /*
1022 * intel_wait_for_pipe_off - wait for pipe to turn off
1023 * @crtc: crtc whose pipe to wait for
1024 *
1025 * After disabling a pipe, we can't wait for vblank in the usual way,
1026 * spinning on the vblank interrupt status bit, since we won't actually
1027 * see an interrupt when the pipe is disabled.
1028 *
1029 * On Gen4 and above:
1030 * wait for the pipe register state bit to turn off
1031 *
1032 * Otherwise:
1033 * wait for the display line value to settle (it usually
1034 * ends up stopping at the start of the next frame).
1035 *
1036 */
1037 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1038 {
1039 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1041 enum pipe pipe = crtc->pipe;
1042
1043 if (INTEL_GEN(dev_priv) >= 4) {
1044 i915_reg_t reg = PIPECONF(cpu_transcoder);
1045
1046 /* Wait for the Pipe State to go off */
1047 if (intel_wait_for_register(dev_priv,
1048 reg, I965_PIPECONF_ACTIVE, 0,
1049 100))
1050 WARN(1, "pipe_off wait timed out\n");
1051 } else {
1052 /* Wait for the display line to settle */
1053 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1054 WARN(1, "pipe_off wait timed out\n");
1055 }
1056 }
1057
1058 /* Only for pre-ILK configs */
1059 void assert_pll(struct drm_i915_private *dev_priv,
1060 enum pipe pipe, bool state)
1061 {
1062 u32 val;
1063 bool cur_state;
1064
1065 val = I915_READ(DPLL(pipe));
1066 cur_state = !!(val & DPLL_VCO_ENABLE);
1067 I915_STATE_WARN(cur_state != state,
1068 "PLL state assertion failure (expected %s, current %s)\n",
1069 onoff(state), onoff(cur_state));
1070 }
1071
1072 /* XXX: the dsi pll is shared between MIPI DSI ports */
1073 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1074 {
1075 u32 val;
1076 bool cur_state;
1077
1078 mutex_lock(&dev_priv->sb_lock);
1079 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1080 mutex_unlock(&dev_priv->sb_lock);
1081
1082 cur_state = val & DSI_PLL_VCO_EN;
1083 I915_STATE_WARN(cur_state != state,
1084 "DSI PLL state assertion failure (expected %s, current %s)\n",
1085 onoff(state), onoff(cur_state));
1086 }
1087
1088 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1089 enum pipe pipe, bool state)
1090 {
1091 bool cur_state;
1092 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093 pipe);
1094
1095 if (HAS_DDI(dev_priv)) {
1096 /* DDI does not have a specific FDI_TX register */
1097 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1098 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1099 } else {
1100 u32 val = I915_READ(FDI_TX_CTL(pipe));
1101 cur_state = !!(val & FDI_TX_ENABLE);
1102 }
1103 I915_STATE_WARN(cur_state != state,
1104 "FDI TX state assertion failure (expected %s, current %s)\n",
1105 onoff(state), onoff(cur_state));
1106 }
1107 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1108 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1109
1110 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1111 enum pipe pipe, bool state)
1112 {
1113 u32 val;
1114 bool cur_state;
1115
1116 val = I915_READ(FDI_RX_CTL(pipe));
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 u32 val;
1129
1130 /* ILK FDI PLL is always enabled */
1131 if (IS_GEN5(dev_priv))
1132 return;
1133
1134 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135 if (HAS_DDI(dev_priv))
1136 return;
1137
1138 val = I915_READ(FDI_TX_CTL(pipe));
1139 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1140 }
1141
1142 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, bool state)
1144 {
1145 u32 val;
1146 bool cur_state;
1147
1148 val = I915_READ(FDI_RX_CTL(pipe));
1149 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1150 I915_STATE_WARN(cur_state != state,
1151 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1152 onoff(state), onoff(cur_state));
1153 }
1154
1155 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157 i915_reg_t pp_reg;
1158 u32 val;
1159 enum pipe panel_pipe = PIPE_A;
1160 bool locked = true;
1161
1162 if (WARN_ON(HAS_DDI(dev_priv)))
1163 return;
1164
1165 if (HAS_PCH_SPLIT(dev_priv)) {
1166 u32 port_sel;
1167
1168 pp_reg = PP_CONTROL(0);
1169 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1170
1171 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1172 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1173 panel_pipe = PIPE_B;
1174 /* XXX: else fix for eDP */
1175 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1176 /* presumably write lock depends on pipe, not port select */
1177 pp_reg = PP_CONTROL(pipe);
1178 panel_pipe = pipe;
1179 } else {
1180 pp_reg = PP_CONTROL(0);
1181 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1182 panel_pipe = PIPE_B;
1183 }
1184
1185 val = I915_READ(pp_reg);
1186 if (!(val & PANEL_POWER_ON) ||
1187 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1188 locked = false;
1189
1190 I915_STATE_WARN(panel_pipe == pipe && locked,
1191 "panel assertion failure, pipe %c regs locked\n",
1192 pipe_name(pipe));
1193 }
1194
1195 static void assert_cursor(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1197 {
1198 bool cur_state;
1199
1200 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1201 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1202 else
1203 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1204
1205 I915_STATE_WARN(cur_state != state,
1206 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1207 pipe_name(pipe), onoff(state), onoff(cur_state));
1208 }
1209 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1210 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1211
1212 void assert_pipe(struct drm_i915_private *dev_priv,
1213 enum pipe pipe, bool state)
1214 {
1215 bool cur_state;
1216 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1217 pipe);
1218 enum intel_display_power_domain power_domain;
1219
1220 /* we keep both pipes enabled on 830 */
1221 if (IS_I830(dev_priv))
1222 state = true;
1223
1224 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1225 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1226 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1227 cur_state = !!(val & PIPECONF_ENABLE);
1228
1229 intel_display_power_put(dev_priv, power_domain);
1230 } else {
1231 cur_state = false;
1232 }
1233
1234 I915_STATE_WARN(cur_state != state,
1235 "pipe %c assertion failure (expected %s, current %s)\n",
1236 pipe_name(pipe), onoff(state), onoff(cur_state));
1237 }
1238
1239 static void assert_plane(struct drm_i915_private *dev_priv,
1240 enum plane plane, bool state)
1241 {
1242 u32 val;
1243 bool cur_state;
1244
1245 val = I915_READ(DSPCNTR(plane));
1246 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "plane %c assertion failure (expected %s, current %s)\n",
1249 plane_name(plane), onoff(state), onoff(cur_state));
1250 }
1251
1252 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1253 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1254
1255 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1256 enum pipe pipe)
1257 {
1258 int i;
1259
1260 /* Primary planes are fixed to pipes on gen4+ */
1261 if (INTEL_GEN(dev_priv) >= 4) {
1262 u32 val = I915_READ(DSPCNTR(pipe));
1263 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1264 "plane %c assertion failure, should be disabled but not\n",
1265 plane_name(pipe));
1266 return;
1267 }
1268
1269 /* Need to check both planes against the pipe */
1270 for_each_pipe(dev_priv, i) {
1271 u32 val = I915_READ(DSPCNTR(i));
1272 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1273 DISPPLANE_SEL_PIPE_SHIFT;
1274 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1275 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1276 plane_name(i), pipe_name(pipe));
1277 }
1278 }
1279
1280 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1281 enum pipe pipe)
1282 {
1283 int sprite;
1284
1285 if (INTEL_GEN(dev_priv) >= 9) {
1286 for_each_sprite(dev_priv, pipe, sprite) {
1287 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1288 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1289 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1290 sprite, pipe_name(pipe));
1291 }
1292 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1293 for_each_sprite(dev_priv, pipe, sprite) {
1294 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1295 I915_STATE_WARN(val & SP_ENABLE,
1296 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297 sprite_name(pipe, sprite), pipe_name(pipe));
1298 }
1299 } else if (INTEL_GEN(dev_priv) >= 7) {
1300 u32 val = I915_READ(SPRCTL(pipe));
1301 I915_STATE_WARN(val & SPRITE_ENABLE,
1302 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303 plane_name(pipe), pipe_name(pipe));
1304 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1305 u32 val = I915_READ(DVSCNTR(pipe));
1306 I915_STATE_WARN(val & DVS_ENABLE,
1307 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1308 plane_name(pipe), pipe_name(pipe));
1309 }
1310 }
1311
1312 static void assert_vblank_disabled(struct drm_crtc *crtc)
1313 {
1314 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1315 drm_crtc_vblank_put(crtc);
1316 }
1317
1318 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1319 enum pipe pipe)
1320 {
1321 u32 val;
1322 bool enabled;
1323
1324 val = I915_READ(PCH_TRANSCONF(pipe));
1325 enabled = !!(val & TRANS_ENABLE);
1326 I915_STATE_WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv)) {
1338 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1339 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1340 return false;
1341 } else if (IS_CHERRYVIEW(dev_priv)) {
1342 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1343 return false;
1344 } else {
1345 if ((val & DP_PIPE_MASK) != (pipe << 30))
1346 return false;
1347 }
1348 return true;
1349 }
1350
1351 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe, u32 val)
1353 {
1354 if ((val & SDVO_ENABLE) == 0)
1355 return false;
1356
1357 if (HAS_PCH_CPT(dev_priv)) {
1358 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1359 return false;
1360 } else if (IS_CHERRYVIEW(dev_priv)) {
1361 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1362 return false;
1363 } else {
1364 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1365 return false;
1366 }
1367 return true;
1368 }
1369
1370 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1372 {
1373 if ((val & LVDS_PORT_EN) == 0)
1374 return false;
1375
1376 if (HAS_PCH_CPT(dev_priv)) {
1377 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1378 return false;
1379 } else {
1380 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1381 return false;
1382 }
1383 return true;
1384 }
1385
1386 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1387 enum pipe pipe, u32 val)
1388 {
1389 if ((val & ADPA_DAC_ENABLE) == 0)
1390 return false;
1391 if (HAS_PCH_CPT(dev_priv)) {
1392 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1393 return false;
1394 } else {
1395 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1396 return false;
1397 }
1398 return true;
1399 }
1400
1401 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1402 enum pipe pipe, i915_reg_t reg,
1403 u32 port_sel)
1404 {
1405 u32 val = I915_READ(reg);
1406 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1407 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1408 i915_mmio_reg_offset(reg), pipe_name(pipe));
1409
1410 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1411 && (val & DP_PIPEB_SELECT),
1412 "IBX PCH dp port still using transcoder B\n");
1413 }
1414
1415 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1416 enum pipe pipe, i915_reg_t reg)
1417 {
1418 u32 val = I915_READ(reg);
1419 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1420 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1421 i915_mmio_reg_offset(reg), pipe_name(pipe));
1422
1423 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1424 && (val & SDVO_PIPE_B_SELECT),
1425 "IBX PCH hdmi port still using transcoder B\n");
1426 }
1427
1428 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1429 enum pipe pipe)
1430 {
1431 u32 val;
1432
1433 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1434 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1435 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1436
1437 val = I915_READ(PCH_ADPA);
1438 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439 "PCH VGA enabled on transcoder %c, should be disabled\n",
1440 pipe_name(pipe));
1441
1442 val = I915_READ(PCH_LVDS);
1443 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1444 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1445 pipe_name(pipe));
1446
1447 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1448 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1449 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1450 }
1451
1452 static void _vlv_enable_pll(struct intel_crtc *crtc,
1453 const struct intel_crtc_state *pipe_config)
1454 {
1455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1456 enum pipe pipe = crtc->pipe;
1457
1458 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1459 POSTING_READ(DPLL(pipe));
1460 udelay(150);
1461
1462 if (intel_wait_for_register(dev_priv,
1463 DPLL(pipe),
1464 DPLL_LOCK_VLV,
1465 DPLL_LOCK_VLV,
1466 1))
1467 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1468 }
1469
1470 static void vlv_enable_pll(struct intel_crtc *crtc,
1471 const struct intel_crtc_state *pipe_config)
1472 {
1473 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1474 enum pipe pipe = crtc->pipe;
1475
1476 assert_pipe_disabled(dev_priv, pipe);
1477
1478 /* PLL is protected by panel, make sure we can write it */
1479 assert_panel_unlocked(dev_priv, pipe);
1480
1481 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1482 _vlv_enable_pll(crtc, pipe_config);
1483
1484 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1485 POSTING_READ(DPLL_MD(pipe));
1486 }
1487
1488
1489 static void _chv_enable_pll(struct intel_crtc *crtc,
1490 const struct intel_crtc_state *pipe_config)
1491 {
1492 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1493 enum pipe pipe = crtc->pipe;
1494 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1495 u32 tmp;
1496
1497 mutex_lock(&dev_priv->sb_lock);
1498
1499 /* Enable back the 10bit clock to display controller */
1500 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1501 tmp |= DPIO_DCLKP_EN;
1502 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1503
1504 mutex_unlock(&dev_priv->sb_lock);
1505
1506 /*
1507 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1508 */
1509 udelay(1);
1510
1511 /* Enable PLL */
1512 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1513
1514 /* Check PLL is locked */
1515 if (intel_wait_for_register(dev_priv,
1516 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1517 1))
1518 DRM_ERROR("PLL %d failed to lock\n", pipe);
1519 }
1520
1521 static void chv_enable_pll(struct intel_crtc *crtc,
1522 const struct intel_crtc_state *pipe_config)
1523 {
1524 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1525 enum pipe pipe = crtc->pipe;
1526
1527 assert_pipe_disabled(dev_priv, pipe);
1528
1529 /* PLL is protected by panel, make sure we can write it */
1530 assert_panel_unlocked(dev_priv, pipe);
1531
1532 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1533 _chv_enable_pll(crtc, pipe_config);
1534
1535 if (pipe != PIPE_A) {
1536 /*
1537 * WaPixelRepeatModeFixForC0:chv
1538 *
1539 * DPLLCMD is AWOL. Use chicken bits to propagate
1540 * the value from DPLLBMD to either pipe B or C.
1541 */
1542 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1543 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1544 I915_WRITE(CBR4_VLV, 0);
1545 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1546
1547 /*
1548 * DPLLB VGA mode also seems to cause problems.
1549 * We should always have it disabled.
1550 */
1551 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1552 } else {
1553 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1554 POSTING_READ(DPLL_MD(pipe));
1555 }
1556 }
1557
1558 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1559 {
1560 struct intel_crtc *crtc;
1561 int count = 0;
1562
1563 for_each_intel_crtc(&dev_priv->drm, crtc) {
1564 count += crtc->base.state->active &&
1565 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1566 }
1567
1568 return count;
1569 }
1570
1571 static void i9xx_enable_pll(struct intel_crtc *crtc,
1572 const struct intel_crtc_state *crtc_state)
1573 {
1574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1575 i915_reg_t reg = DPLL(crtc->pipe);
1576 u32 dpll = crtc_state->dpll_hw_state.dpll;
1577 int i;
1578
1579 assert_pipe_disabled(dev_priv, crtc->pipe);
1580
1581 /* PLL is protected by panel, make sure we can write it */
1582 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1583 assert_panel_unlocked(dev_priv, crtc->pipe);
1584
1585 /* Enable DVO 2x clock on both PLLs if necessary */
1586 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1587 /*
1588 * It appears to be important that we don't enable this
1589 * for the current pipe before otherwise configuring the
1590 * PLL. No idea how this should be handled if multiple
1591 * DVO outputs are enabled simultaneosly.
1592 */
1593 dpll |= DPLL_DVO_2X_MODE;
1594 I915_WRITE(DPLL(!crtc->pipe),
1595 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1596 }
1597
1598 /*
1599 * Apparently we need to have VGA mode enabled prior to changing
1600 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1601 * dividers, even though the register value does change.
1602 */
1603 I915_WRITE(reg, 0);
1604
1605 I915_WRITE(reg, dpll);
1606
1607 /* Wait for the clocks to stabilize. */
1608 POSTING_READ(reg);
1609 udelay(150);
1610
1611 if (INTEL_GEN(dev_priv) >= 4) {
1612 I915_WRITE(DPLL_MD(crtc->pipe),
1613 crtc_state->dpll_hw_state.dpll_md);
1614 } else {
1615 /* The pixel multiplier can only be updated once the
1616 * DPLL is enabled and the clocks are stable.
1617 *
1618 * So write it again.
1619 */
1620 I915_WRITE(reg, dpll);
1621 }
1622
1623 /* We do this three times for luck */
1624 for (i = 0; i < 3; i++) {
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 }
1629 }
1630
1631 static void i9xx_disable_pll(struct intel_crtc *crtc)
1632 {
1633 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1634 enum pipe pipe = crtc->pipe;
1635
1636 /* Disable DVO 2x clock on both PLLs if necessary */
1637 if (IS_I830(dev_priv) &&
1638 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1639 !intel_num_dvo_pipes(dev_priv)) {
1640 I915_WRITE(DPLL(PIPE_B),
1641 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1642 I915_WRITE(DPLL(PIPE_A),
1643 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1644 }
1645
1646 /* Don't disable pipe or pipe PLLs if needed */
1647 if (IS_I830(dev_priv))
1648 return;
1649
1650 /* Make sure the pipe isn't still relying on us */
1651 assert_pipe_disabled(dev_priv, pipe);
1652
1653 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1654 POSTING_READ(DPLL(pipe));
1655 }
1656
1657 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1658 {
1659 u32 val;
1660
1661 /* Make sure the pipe isn't still relying on us */
1662 assert_pipe_disabled(dev_priv, pipe);
1663
1664 val = DPLL_INTEGRATED_REF_CLK_VLV |
1665 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1666 if (pipe != PIPE_A)
1667 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1668
1669 I915_WRITE(DPLL(pipe), val);
1670 POSTING_READ(DPLL(pipe));
1671 }
1672
1673 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1674 {
1675 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1676 u32 val;
1677
1678 /* Make sure the pipe isn't still relying on us */
1679 assert_pipe_disabled(dev_priv, pipe);
1680
1681 val = DPLL_SSC_REF_CLK_CHV |
1682 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1683 if (pipe != PIPE_A)
1684 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1685
1686 I915_WRITE(DPLL(pipe), val);
1687 POSTING_READ(DPLL(pipe));
1688
1689 mutex_lock(&dev_priv->sb_lock);
1690
1691 /* Disable 10bit clock to display controller */
1692 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1693 val &= ~DPIO_DCLKP_EN;
1694 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1695
1696 mutex_unlock(&dev_priv->sb_lock);
1697 }
1698
1699 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1700 struct intel_digital_port *dport,
1701 unsigned int expected_mask)
1702 {
1703 u32 port_mask;
1704 i915_reg_t dpll_reg;
1705
1706 switch (dport->port) {
1707 case PORT_B:
1708 port_mask = DPLL_PORTB_READY_MASK;
1709 dpll_reg = DPLL(0);
1710 break;
1711 case PORT_C:
1712 port_mask = DPLL_PORTC_READY_MASK;
1713 dpll_reg = DPLL(0);
1714 expected_mask <<= 4;
1715 break;
1716 case PORT_D:
1717 port_mask = DPLL_PORTD_READY_MASK;
1718 dpll_reg = DPIO_PHY_STATUS;
1719 break;
1720 default:
1721 BUG();
1722 }
1723
1724 if (intel_wait_for_register(dev_priv,
1725 dpll_reg, port_mask, expected_mask,
1726 1000))
1727 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1728 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1729 }
1730
1731 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1732 enum pipe pipe)
1733 {
1734 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1735 pipe);
1736 i915_reg_t reg;
1737 uint32_t val, pipeconf_val;
1738
1739 /* Make sure PCH DPLL is enabled */
1740 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1741
1742 /* FDI must be feeding us bits for PCH ports */
1743 assert_fdi_tx_enabled(dev_priv, pipe);
1744 assert_fdi_rx_enabled(dev_priv, pipe);
1745
1746 if (HAS_PCH_CPT(dev_priv)) {
1747 /* Workaround: Set the timing override bit before enabling the
1748 * pch transcoder. */
1749 reg = TRANS_CHICKEN2(pipe);
1750 val = I915_READ(reg);
1751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1752 I915_WRITE(reg, val);
1753 }
1754
1755 reg = PCH_TRANSCONF(pipe);
1756 val = I915_READ(reg);
1757 pipeconf_val = I915_READ(PIPECONF(pipe));
1758
1759 if (HAS_PCH_IBX(dev_priv)) {
1760 /*
1761 * Make the BPC in transcoder be consistent with
1762 * that in pipeconf reg. For HDMI we must use 8bpc
1763 * here for both 8bpc and 12bpc.
1764 */
1765 val &= ~PIPECONF_BPC_MASK;
1766 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1767 val |= PIPECONF_8BPC;
1768 else
1769 val |= pipeconf_val & PIPECONF_BPC_MASK;
1770 }
1771
1772 val &= ~TRANS_INTERLACE_MASK;
1773 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1774 if (HAS_PCH_IBX(dev_priv) &&
1775 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1776 val |= TRANS_LEGACY_INTERLACED_ILK;
1777 else
1778 val |= TRANS_INTERLACED;
1779 else
1780 val |= TRANS_PROGRESSIVE;
1781
1782 I915_WRITE(reg, val | TRANS_ENABLE);
1783 if (intel_wait_for_register(dev_priv,
1784 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1785 100))
1786 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1787 }
1788
1789 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1790 enum transcoder cpu_transcoder)
1791 {
1792 u32 val, pipeconf_val;
1793
1794 /* FDI must be feeding us bits for PCH ports */
1795 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1796 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1797
1798 /* Workaround: set timing override bit. */
1799 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1800 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1801 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1802
1803 val = TRANS_ENABLE;
1804 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1805
1806 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1807 PIPECONF_INTERLACED_ILK)
1808 val |= TRANS_INTERLACED;
1809 else
1810 val |= TRANS_PROGRESSIVE;
1811
1812 I915_WRITE(LPT_TRANSCONF, val);
1813 if (intel_wait_for_register(dev_priv,
1814 LPT_TRANSCONF,
1815 TRANS_STATE_ENABLE,
1816 TRANS_STATE_ENABLE,
1817 100))
1818 DRM_ERROR("Failed to enable PCH transcoder\n");
1819 }
1820
1821 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1822 enum pipe pipe)
1823 {
1824 i915_reg_t reg;
1825 uint32_t val;
1826
1827 /* FDI relies on the transcoder */
1828 assert_fdi_tx_disabled(dev_priv, pipe);
1829 assert_fdi_rx_disabled(dev_priv, pipe);
1830
1831 /* Ports must be off as well */
1832 assert_pch_ports_disabled(dev_priv, pipe);
1833
1834 reg = PCH_TRANSCONF(pipe);
1835 val = I915_READ(reg);
1836 val &= ~TRANS_ENABLE;
1837 I915_WRITE(reg, val);
1838 /* wait for PCH transcoder off, transcoder state */
1839 if (intel_wait_for_register(dev_priv,
1840 reg, TRANS_STATE_ENABLE, 0,
1841 50))
1842 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1843
1844 if (HAS_PCH_CPT(dev_priv)) {
1845 /* Workaround: Clear the timing override chicken bit again. */
1846 reg = TRANS_CHICKEN2(pipe);
1847 val = I915_READ(reg);
1848 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1849 I915_WRITE(reg, val);
1850 }
1851 }
1852
1853 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1854 {
1855 u32 val;
1856
1857 val = I915_READ(LPT_TRANSCONF);
1858 val &= ~TRANS_ENABLE;
1859 I915_WRITE(LPT_TRANSCONF, val);
1860 /* wait for PCH transcoder off, transcoder state */
1861 if (intel_wait_for_register(dev_priv,
1862 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1863 50))
1864 DRM_ERROR("Failed to disable PCH transcoder\n");
1865
1866 /* Workaround: clear timing override bit. */
1867 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1868 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1869 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1870 }
1871
1872 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1873 {
1874 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1875
1876 WARN_ON(!crtc->config->has_pch_encoder);
1877
1878 if (HAS_PCH_LPT(dev_priv))
1879 return PIPE_A;
1880 else
1881 return crtc->pipe;
1882 }
1883
1884 /**
1885 * intel_enable_pipe - enable a pipe, asserting requirements
1886 * @crtc: crtc responsible for the pipe
1887 *
1888 * Enable @crtc's pipe, making sure that various hardware specific requirements
1889 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1890 */
1891 static void intel_enable_pipe(struct intel_crtc *crtc)
1892 {
1893 struct drm_device *dev = crtc->base.dev;
1894 struct drm_i915_private *dev_priv = to_i915(dev);
1895 enum pipe pipe = crtc->pipe;
1896 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1897 i915_reg_t reg;
1898 u32 val;
1899
1900 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1901
1902 assert_planes_disabled(dev_priv, pipe);
1903 assert_cursor_disabled(dev_priv, pipe);
1904 assert_sprites_disabled(dev_priv, pipe);
1905
1906 /*
1907 * A pipe without a PLL won't actually be able to drive bits from
1908 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1909 * need the check.
1910 */
1911 if (HAS_GMCH_DISPLAY(dev_priv)) {
1912 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1913 assert_dsi_pll_enabled(dev_priv);
1914 else
1915 assert_pll_enabled(dev_priv, pipe);
1916 } else {
1917 if (crtc->config->has_pch_encoder) {
1918 /* if driving the PCH, we need FDI enabled */
1919 assert_fdi_rx_pll_enabled(dev_priv,
1920 intel_crtc_pch_transcoder(crtc));
1921 assert_fdi_tx_pll_enabled(dev_priv,
1922 (enum pipe) cpu_transcoder);
1923 }
1924 /* FIXME: assert CPU port conditions for SNB+ */
1925 }
1926
1927 reg = PIPECONF(cpu_transcoder);
1928 val = I915_READ(reg);
1929 if (val & PIPECONF_ENABLE) {
1930 /* we keep both pipes enabled on 830 */
1931 WARN_ON(!IS_I830(dev_priv));
1932 return;
1933 }
1934
1935 I915_WRITE(reg, val | PIPECONF_ENABLE);
1936 POSTING_READ(reg);
1937
1938 /*
1939 * Until the pipe starts DSL will read as 0, which would cause
1940 * an apparent vblank timestamp jump, which messes up also the
1941 * frame count when it's derived from the timestamps. So let's
1942 * wait for the pipe to start properly before we call
1943 * drm_crtc_vblank_on()
1944 */
1945 if (dev->max_vblank_count == 0 &&
1946 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1947 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1948 }
1949
1950 /**
1951 * intel_disable_pipe - disable a pipe, asserting requirements
1952 * @crtc: crtc whose pipes is to be disabled
1953 *
1954 * Disable the pipe of @crtc, making sure that various hardware
1955 * specific requirements are met, if applicable, e.g. plane
1956 * disabled, panel fitter off, etc.
1957 *
1958 * Will wait until the pipe has shut down before returning.
1959 */
1960 static void intel_disable_pipe(struct intel_crtc *crtc)
1961 {
1962 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1963 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1964 enum pipe pipe = crtc->pipe;
1965 i915_reg_t reg;
1966 u32 val;
1967
1968 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1969
1970 /*
1971 * Make sure planes won't keep trying to pump pixels to us,
1972 * or we might hang the display.
1973 */
1974 assert_planes_disabled(dev_priv, pipe);
1975 assert_cursor_disabled(dev_priv, pipe);
1976 assert_sprites_disabled(dev_priv, pipe);
1977
1978 reg = PIPECONF(cpu_transcoder);
1979 val = I915_READ(reg);
1980 if ((val & PIPECONF_ENABLE) == 0)
1981 return;
1982
1983 /*
1984 * Double wide has implications for planes
1985 * so best keep it disabled when not needed.
1986 */
1987 if (crtc->config->double_wide)
1988 val &= ~PIPECONF_DOUBLE_WIDE;
1989
1990 /* Don't disable pipe or pipe PLLs if needed */
1991 if (!IS_I830(dev_priv))
1992 val &= ~PIPECONF_ENABLE;
1993
1994 I915_WRITE(reg, val);
1995 if ((val & PIPECONF_ENABLE) == 0)
1996 intel_wait_for_pipe_off(crtc);
1997 }
1998
1999 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2000 {
2001 return IS_GEN2(dev_priv) ? 2048 : 4096;
2002 }
2003
2004 static unsigned int
2005 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2006 {
2007 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2008 unsigned int cpp = fb->format->cpp[plane];
2009
2010 switch (fb->modifier) {
2011 case DRM_FORMAT_MOD_LINEAR:
2012 return cpp;
2013 case I915_FORMAT_MOD_X_TILED:
2014 if (IS_GEN2(dev_priv))
2015 return 128;
2016 else
2017 return 512;
2018 case I915_FORMAT_MOD_Y_TILED_CCS:
2019 if (plane == 1)
2020 return 128;
2021 /* fall through */
2022 case I915_FORMAT_MOD_Y_TILED:
2023 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2024 return 128;
2025 else
2026 return 512;
2027 case I915_FORMAT_MOD_Yf_TILED_CCS:
2028 if (plane == 1)
2029 return 128;
2030 /* fall through */
2031 case I915_FORMAT_MOD_Yf_TILED:
2032 switch (cpp) {
2033 case 1:
2034 return 64;
2035 case 2:
2036 case 4:
2037 return 128;
2038 case 8:
2039 case 16:
2040 return 256;
2041 default:
2042 MISSING_CASE(cpp);
2043 return cpp;
2044 }
2045 break;
2046 default:
2047 MISSING_CASE(fb->modifier);
2048 return cpp;
2049 }
2050 }
2051
2052 static unsigned int
2053 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2054 {
2055 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2056 return 1;
2057 else
2058 return intel_tile_size(to_i915(fb->dev)) /
2059 intel_tile_width_bytes(fb, plane);
2060 }
2061
2062 /* Return the tile dimensions in pixel units */
2063 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2064 unsigned int *tile_width,
2065 unsigned int *tile_height)
2066 {
2067 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2068 unsigned int cpp = fb->format->cpp[plane];
2069
2070 *tile_width = tile_width_bytes / cpp;
2071 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2072 }
2073
2074 unsigned int
2075 intel_fb_align_height(const struct drm_framebuffer *fb,
2076 int plane, unsigned int height)
2077 {
2078 unsigned int tile_height = intel_tile_height(fb, plane);
2079
2080 return ALIGN(height, tile_height);
2081 }
2082
2083 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2084 {
2085 unsigned int size = 0;
2086 int i;
2087
2088 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2089 size += rot_info->plane[i].width * rot_info->plane[i].height;
2090
2091 return size;
2092 }
2093
2094 static void
2095 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2096 const struct drm_framebuffer *fb,
2097 unsigned int rotation)
2098 {
2099 view->type = I915_GGTT_VIEW_NORMAL;
2100 if (drm_rotation_90_or_270(rotation)) {
2101 view->type = I915_GGTT_VIEW_ROTATED;
2102 view->rotated = to_intel_framebuffer(fb)->rot_info;
2103 }
2104 }
2105
2106 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2107 {
2108 if (IS_I830(dev_priv))
2109 return 16 * 1024;
2110 else if (IS_I85X(dev_priv))
2111 return 256;
2112 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2113 return 32;
2114 else
2115 return 4 * 1024;
2116 }
2117
2118 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2119 {
2120 if (INTEL_INFO(dev_priv)->gen >= 9)
2121 return 256 * 1024;
2122 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2123 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2124 return 128 * 1024;
2125 else if (INTEL_INFO(dev_priv)->gen >= 4)
2126 return 4 * 1024;
2127 else
2128 return 0;
2129 }
2130
2131 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2132 int plane)
2133 {
2134 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2135
2136 /* AUX_DIST needs only 4K alignment */
2137 if (plane == 1)
2138 return 4096;
2139
2140 switch (fb->modifier) {
2141 case DRM_FORMAT_MOD_LINEAR:
2142 return intel_linear_alignment(dev_priv);
2143 case I915_FORMAT_MOD_X_TILED:
2144 if (INTEL_GEN(dev_priv) >= 9)
2145 return 256 * 1024;
2146 return 0;
2147 case I915_FORMAT_MOD_Y_TILED_CCS:
2148 case I915_FORMAT_MOD_Yf_TILED_CCS:
2149 case I915_FORMAT_MOD_Y_TILED:
2150 case I915_FORMAT_MOD_Yf_TILED:
2151 return 1 * 1024 * 1024;
2152 default:
2153 MISSING_CASE(fb->modifier);
2154 return 0;
2155 }
2156 }
2157
2158 struct i915_vma *
2159 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2160 {
2161 struct drm_device *dev = fb->dev;
2162 struct drm_i915_private *dev_priv = to_i915(dev);
2163 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2164 struct i915_ggtt_view view;
2165 struct i915_vma *vma;
2166 u32 alignment;
2167
2168 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2169
2170 alignment = intel_surf_alignment(fb, 0);
2171
2172 intel_fill_fb_ggtt_view(&view, fb, rotation);
2173
2174 /* Note that the w/a also requires 64 PTE of padding following the
2175 * bo. We currently fill all unused PTE with the shadow page and so
2176 * we should always have valid PTE following the scanout preventing
2177 * the VT-d warning.
2178 */
2179 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2180 alignment = 256 * 1024;
2181
2182 /*
2183 * Global gtt pte registers are special registers which actually forward
2184 * writes to a chunk of system memory. Which means that there is no risk
2185 * that the register values disappear as soon as we call
2186 * intel_runtime_pm_put(), so it is correct to wrap only the
2187 * pin/unpin/fence and not more.
2188 */
2189 intel_runtime_pm_get(dev_priv);
2190
2191 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2192
2193 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2194 if (IS_ERR(vma))
2195 goto err;
2196
2197 if (i915_vma_is_map_and_fenceable(vma)) {
2198 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2199 * fence, whereas 965+ only requires a fence if using
2200 * framebuffer compression. For simplicity, we always, when
2201 * possible, install a fence as the cost is not that onerous.
2202 *
2203 * If we fail to fence the tiled scanout, then either the
2204 * modeset will reject the change (which is highly unlikely as
2205 * the affected systems, all but one, do not have unmappable
2206 * space) or we will not be able to enable full powersaving
2207 * techniques (also likely not to apply due to various limits
2208 * FBC and the like impose on the size of the buffer, which
2209 * presumably we violated anyway with this unmappable buffer).
2210 * Anyway, it is presumably better to stumble onwards with
2211 * something and try to run the system in a "less than optimal"
2212 * mode that matches the user configuration.
2213 */
2214 i915_vma_pin_fence(vma);
2215 }
2216
2217 i915_vma_get(vma);
2218 err:
2219 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2220
2221 intel_runtime_pm_put(dev_priv);
2222 return vma;
2223 }
2224
2225 void intel_unpin_fb_vma(struct i915_vma *vma)
2226 {
2227 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2228
2229 i915_vma_unpin_fence(vma);
2230 i915_gem_object_unpin_from_display_plane(vma);
2231 i915_vma_put(vma);
2232 }
2233
2234 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2235 unsigned int rotation)
2236 {
2237 if (drm_rotation_90_or_270(rotation))
2238 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2239 else
2240 return fb->pitches[plane];
2241 }
2242
2243 /*
2244 * Convert the x/y offsets into a linear offset.
2245 * Only valid with 0/180 degree rotation, which is fine since linear
2246 * offset is only used with linear buffers on pre-hsw and tiled buffers
2247 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2248 */
2249 u32 intel_fb_xy_to_linear(int x, int y,
2250 const struct intel_plane_state *state,
2251 int plane)
2252 {
2253 const struct drm_framebuffer *fb = state->base.fb;
2254 unsigned int cpp = fb->format->cpp[plane];
2255 unsigned int pitch = fb->pitches[plane];
2256
2257 return y * pitch + x * cpp;
2258 }
2259
2260 /*
2261 * Add the x/y offsets derived from fb->offsets[] to the user
2262 * specified plane src x/y offsets. The resulting x/y offsets
2263 * specify the start of scanout from the beginning of the gtt mapping.
2264 */
2265 void intel_add_fb_offsets(int *x, int *y,
2266 const struct intel_plane_state *state,
2267 int plane)
2268
2269 {
2270 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2271 unsigned int rotation = state->base.rotation;
2272
2273 if (drm_rotation_90_or_270(rotation)) {
2274 *x += intel_fb->rotated[plane].x;
2275 *y += intel_fb->rotated[plane].y;
2276 } else {
2277 *x += intel_fb->normal[plane].x;
2278 *y += intel_fb->normal[plane].y;
2279 }
2280 }
2281
2282 static u32 __intel_adjust_tile_offset(int *x, int *y,
2283 unsigned int tile_width,
2284 unsigned int tile_height,
2285 unsigned int tile_size,
2286 unsigned int pitch_tiles,
2287 u32 old_offset,
2288 u32 new_offset)
2289 {
2290 unsigned int pitch_pixels = pitch_tiles * tile_width;
2291 unsigned int tiles;
2292
2293 WARN_ON(old_offset & (tile_size - 1));
2294 WARN_ON(new_offset & (tile_size - 1));
2295 WARN_ON(new_offset > old_offset);
2296
2297 tiles = (old_offset - new_offset) / tile_size;
2298
2299 *y += tiles / pitch_tiles * tile_height;
2300 *x += tiles % pitch_tiles * tile_width;
2301
2302 /* minimize x in case it got needlessly big */
2303 *y += *x / pitch_pixels * tile_height;
2304 *x %= pitch_pixels;
2305
2306 return new_offset;
2307 }
2308
2309 static u32 _intel_adjust_tile_offset(int *x, int *y,
2310 const struct drm_framebuffer *fb, int plane,
2311 unsigned int rotation,
2312 u32 old_offset, u32 new_offset)
2313 {
2314 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2315 unsigned int cpp = fb->format->cpp[plane];
2316 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2317
2318 WARN_ON(new_offset > old_offset);
2319
2320 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2321 unsigned int tile_size, tile_width, tile_height;
2322 unsigned int pitch_tiles;
2323
2324 tile_size = intel_tile_size(dev_priv);
2325 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2326
2327 if (drm_rotation_90_or_270(rotation)) {
2328 pitch_tiles = pitch / tile_height;
2329 swap(tile_width, tile_height);
2330 } else {
2331 pitch_tiles = pitch / (tile_width * cpp);
2332 }
2333
2334 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2335 tile_size, pitch_tiles,
2336 old_offset, new_offset);
2337 } else {
2338 old_offset += *y * pitch + *x * cpp;
2339
2340 *y = (old_offset - new_offset) / pitch;
2341 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2342 }
2343
2344 return new_offset;
2345 }
2346
2347 /*
2348 * Adjust the tile offset by moving the difference into
2349 * the x/y offsets.
2350 */
2351 static u32 intel_adjust_tile_offset(int *x, int *y,
2352 const struct intel_plane_state *state, int plane,
2353 u32 old_offset, u32 new_offset)
2354 {
2355 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2356 state->base.rotation,
2357 old_offset, new_offset);
2358 }
2359
2360 /*
2361 * Computes the linear offset to the base tile and adjusts
2362 * x, y. bytes per pixel is assumed to be a power-of-two.
2363 *
2364 * In the 90/270 rotated case, x and y are assumed
2365 * to be already rotated to match the rotated GTT view, and
2366 * pitch is the tile_height aligned framebuffer height.
2367 *
2368 * This function is used when computing the derived information
2369 * under intel_framebuffer, so using any of that information
2370 * here is not allowed. Anything under drm_framebuffer can be
2371 * used. This is why the user has to pass in the pitch since it
2372 * is specified in the rotated orientation.
2373 */
2374 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2375 int *x, int *y,
2376 const struct drm_framebuffer *fb, int plane,
2377 unsigned int pitch,
2378 unsigned int rotation,
2379 u32 alignment)
2380 {
2381 uint64_t fb_modifier = fb->modifier;
2382 unsigned int cpp = fb->format->cpp[plane];
2383 u32 offset, offset_aligned;
2384
2385 if (alignment)
2386 alignment--;
2387
2388 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2389 unsigned int tile_size, tile_width, tile_height;
2390 unsigned int tile_rows, tiles, pitch_tiles;
2391
2392 tile_size = intel_tile_size(dev_priv);
2393 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2394
2395 if (drm_rotation_90_or_270(rotation)) {
2396 pitch_tiles = pitch / tile_height;
2397 swap(tile_width, tile_height);
2398 } else {
2399 pitch_tiles = pitch / (tile_width * cpp);
2400 }
2401
2402 tile_rows = *y / tile_height;
2403 *y %= tile_height;
2404
2405 tiles = *x / tile_width;
2406 *x %= tile_width;
2407
2408 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2409 offset_aligned = offset & ~alignment;
2410
2411 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2412 tile_size, pitch_tiles,
2413 offset, offset_aligned);
2414 } else {
2415 offset = *y * pitch + *x * cpp;
2416 offset_aligned = offset & ~alignment;
2417
2418 *y = (offset & alignment) / pitch;
2419 *x = ((offset & alignment) - *y * pitch) / cpp;
2420 }
2421
2422 return offset_aligned;
2423 }
2424
2425 u32 intel_compute_tile_offset(int *x, int *y,
2426 const struct intel_plane_state *state,
2427 int plane)
2428 {
2429 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2430 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2431 const struct drm_framebuffer *fb = state->base.fb;
2432 unsigned int rotation = state->base.rotation;
2433 int pitch = intel_fb_pitch(fb, plane, rotation);
2434 u32 alignment;
2435
2436 if (intel_plane->id == PLANE_CURSOR)
2437 alignment = intel_cursor_alignment(dev_priv);
2438 else
2439 alignment = intel_surf_alignment(fb, plane);
2440
2441 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2442 rotation, alignment);
2443 }
2444
2445 /* Convert the fb->offset[] into x/y offsets */
2446 static int intel_fb_offset_to_xy(int *x, int *y,
2447 const struct drm_framebuffer *fb, int plane)
2448 {
2449 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2450
2451 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2452 fb->offsets[plane] % intel_tile_size(dev_priv))
2453 return -EINVAL;
2454
2455 *x = 0;
2456 *y = 0;
2457
2458 _intel_adjust_tile_offset(x, y,
2459 fb, plane, DRM_MODE_ROTATE_0,
2460 fb->offsets[plane], 0);
2461
2462 return 0;
2463 }
2464
2465 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2466 {
2467 switch (fb_modifier) {
2468 case I915_FORMAT_MOD_X_TILED:
2469 return I915_TILING_X;
2470 case I915_FORMAT_MOD_Y_TILED:
2471 case I915_FORMAT_MOD_Y_TILED_CCS:
2472 return I915_TILING_Y;
2473 default:
2474 return I915_TILING_NONE;
2475 }
2476 }
2477
2478 static const struct drm_format_info ccs_formats[] = {
2479 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2480 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2481 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2482 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2483 };
2484
2485 static const struct drm_format_info *
2486 lookup_format_info(const struct drm_format_info formats[],
2487 int num_formats, u32 format)
2488 {
2489 int i;
2490
2491 for (i = 0; i < num_formats; i++) {
2492 if (formats[i].format == format)
2493 return &formats[i];
2494 }
2495
2496 return NULL;
2497 }
2498
2499 static const struct drm_format_info *
2500 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2501 {
2502 switch (cmd->modifier[0]) {
2503 case I915_FORMAT_MOD_Y_TILED_CCS:
2504 case I915_FORMAT_MOD_Yf_TILED_CCS:
2505 return lookup_format_info(ccs_formats,
2506 ARRAY_SIZE(ccs_formats),
2507 cmd->pixel_format);
2508 default:
2509 return NULL;
2510 }
2511 }
2512
2513 static int
2514 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2515 struct drm_framebuffer *fb)
2516 {
2517 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2518 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2519 u32 gtt_offset_rotated = 0;
2520 unsigned int max_size = 0;
2521 int i, num_planes = fb->format->num_planes;
2522 unsigned int tile_size = intel_tile_size(dev_priv);
2523
2524 for (i = 0; i < num_planes; i++) {
2525 unsigned int width, height;
2526 unsigned int cpp, size;
2527 u32 offset;
2528 int x, y;
2529 int ret;
2530
2531 cpp = fb->format->cpp[i];
2532 width = drm_framebuffer_plane_width(fb->width, fb, i);
2533 height = drm_framebuffer_plane_height(fb->height, fb, i);
2534
2535 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2536 if (ret) {
2537 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2538 i, fb->offsets[i]);
2539 return ret;
2540 }
2541
2542 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2543 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2544 int hsub = fb->format->hsub;
2545 int vsub = fb->format->vsub;
2546 int tile_width, tile_height;
2547 int main_x, main_y;
2548 int ccs_x, ccs_y;
2549
2550 intel_tile_dims(fb, i, &tile_width, &tile_height);
2551 tile_width *= hsub;
2552 tile_height *= vsub;
2553
2554 ccs_x = (x * hsub) % tile_width;
2555 ccs_y = (y * vsub) % tile_height;
2556 main_x = intel_fb->normal[0].x % tile_width;
2557 main_y = intel_fb->normal[0].y % tile_height;
2558
2559 /*
2560 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2561 * x/y offsets must match between CCS and the main surface.
2562 */
2563 if (main_x != ccs_x || main_y != ccs_y) {
2564 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2565 main_x, main_y,
2566 ccs_x, ccs_y,
2567 intel_fb->normal[0].x,
2568 intel_fb->normal[0].y,
2569 x, y);
2570 return -EINVAL;
2571 }
2572 }
2573
2574 /*
2575 * The fence (if used) is aligned to the start of the object
2576 * so having the framebuffer wrap around across the edge of the
2577 * fenced region doesn't really work. We have no API to configure
2578 * the fence start offset within the object (nor could we probably
2579 * on gen2/3). So it's just easier if we just require that the
2580 * fb layout agrees with the fence layout. We already check that the
2581 * fb stride matches the fence stride elsewhere.
2582 */
2583 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2584 (x + width) * cpp > fb->pitches[i]) {
2585 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2586 i, fb->offsets[i]);
2587 return -EINVAL;
2588 }
2589
2590 /*
2591 * First pixel of the framebuffer from
2592 * the start of the normal gtt mapping.
2593 */
2594 intel_fb->normal[i].x = x;
2595 intel_fb->normal[i].y = y;
2596
2597 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2598 fb, i, fb->pitches[i],
2599 DRM_MODE_ROTATE_0, tile_size);
2600 offset /= tile_size;
2601
2602 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2603 unsigned int tile_width, tile_height;
2604 unsigned int pitch_tiles;
2605 struct drm_rect r;
2606
2607 intel_tile_dims(fb, i, &tile_width, &tile_height);
2608
2609 rot_info->plane[i].offset = offset;
2610 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2611 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2612 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2613
2614 intel_fb->rotated[i].pitch =
2615 rot_info->plane[i].height * tile_height;
2616
2617 /* how many tiles does this plane need */
2618 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2619 /*
2620 * If the plane isn't horizontally tile aligned,
2621 * we need one more tile.
2622 */
2623 if (x != 0)
2624 size++;
2625
2626 /* rotate the x/y offsets to match the GTT view */
2627 r.x1 = x;
2628 r.y1 = y;
2629 r.x2 = x + width;
2630 r.y2 = y + height;
2631 drm_rect_rotate(&r,
2632 rot_info->plane[i].width * tile_width,
2633 rot_info->plane[i].height * tile_height,
2634 DRM_MODE_ROTATE_270);
2635 x = r.x1;
2636 y = r.y1;
2637
2638 /* rotate the tile dimensions to match the GTT view */
2639 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2640 swap(tile_width, tile_height);
2641
2642 /*
2643 * We only keep the x/y offsets, so push all of the
2644 * gtt offset into the x/y offsets.
2645 */
2646 __intel_adjust_tile_offset(&x, &y,
2647 tile_width, tile_height,
2648 tile_size, pitch_tiles,
2649 gtt_offset_rotated * tile_size, 0);
2650
2651 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2652
2653 /*
2654 * First pixel of the framebuffer from
2655 * the start of the rotated gtt mapping.
2656 */
2657 intel_fb->rotated[i].x = x;
2658 intel_fb->rotated[i].y = y;
2659 } else {
2660 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2661 x * cpp, tile_size);
2662 }
2663
2664 /* how many tiles in total needed in the bo */
2665 max_size = max(max_size, offset + size);
2666 }
2667
2668 if (max_size * tile_size > intel_fb->obj->base.size) {
2669 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2670 max_size * tile_size, intel_fb->obj->base.size);
2671 return -EINVAL;
2672 }
2673
2674 return 0;
2675 }
2676
2677 static int i9xx_format_to_fourcc(int format)
2678 {
2679 switch (format) {
2680 case DISPPLANE_8BPP:
2681 return DRM_FORMAT_C8;
2682 case DISPPLANE_BGRX555:
2683 return DRM_FORMAT_XRGB1555;
2684 case DISPPLANE_BGRX565:
2685 return DRM_FORMAT_RGB565;
2686 default:
2687 case DISPPLANE_BGRX888:
2688 return DRM_FORMAT_XRGB8888;
2689 case DISPPLANE_RGBX888:
2690 return DRM_FORMAT_XBGR8888;
2691 case DISPPLANE_BGRX101010:
2692 return DRM_FORMAT_XRGB2101010;
2693 case DISPPLANE_RGBX101010:
2694 return DRM_FORMAT_XBGR2101010;
2695 }
2696 }
2697
2698 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2699 {
2700 switch (format) {
2701 case PLANE_CTL_FORMAT_RGB_565:
2702 return DRM_FORMAT_RGB565;
2703 default:
2704 case PLANE_CTL_FORMAT_XRGB_8888:
2705 if (rgb_order) {
2706 if (alpha)
2707 return DRM_FORMAT_ABGR8888;
2708 else
2709 return DRM_FORMAT_XBGR8888;
2710 } else {
2711 if (alpha)
2712 return DRM_FORMAT_ARGB8888;
2713 else
2714 return DRM_FORMAT_XRGB8888;
2715 }
2716 case PLANE_CTL_FORMAT_XRGB_2101010:
2717 if (rgb_order)
2718 return DRM_FORMAT_XBGR2101010;
2719 else
2720 return DRM_FORMAT_XRGB2101010;
2721 }
2722 }
2723
2724 static bool
2725 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2726 struct intel_initial_plane_config *plane_config)
2727 {
2728 struct drm_device *dev = crtc->base.dev;
2729 struct drm_i915_private *dev_priv = to_i915(dev);
2730 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2731 struct drm_i915_gem_object *obj = NULL;
2732 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2733 struct drm_framebuffer *fb = &plane_config->fb->base;
2734 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2735 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2736 PAGE_SIZE);
2737
2738 size_aligned -= base_aligned;
2739
2740 if (plane_config->size == 0)
2741 return false;
2742
2743 /* If the FB is too big, just don't use it since fbdev is not very
2744 * important and we should probably use that space with FBC or other
2745 * features. */
2746 if (size_aligned * 2 > ggtt->stolen_usable_size)
2747 return false;
2748
2749 mutex_lock(&dev->struct_mutex);
2750 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2751 base_aligned,
2752 base_aligned,
2753 size_aligned);
2754 mutex_unlock(&dev->struct_mutex);
2755 if (!obj)
2756 return false;
2757
2758 if (plane_config->tiling == I915_TILING_X)
2759 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2760
2761 mode_cmd.pixel_format = fb->format->format;
2762 mode_cmd.width = fb->width;
2763 mode_cmd.height = fb->height;
2764 mode_cmd.pitches[0] = fb->pitches[0];
2765 mode_cmd.modifier[0] = fb->modifier;
2766 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2767
2768 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2769 DRM_DEBUG_KMS("intel fb init failed\n");
2770 goto out_unref_obj;
2771 }
2772
2773
2774 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2775 return true;
2776
2777 out_unref_obj:
2778 i915_gem_object_put(obj);
2779 return false;
2780 }
2781
2782 static void
2783 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2784 struct intel_plane_state *plane_state,
2785 bool visible)
2786 {
2787 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2788
2789 plane_state->base.visible = visible;
2790
2791 /* FIXME pre-g4x don't work like this */
2792 if (visible) {
2793 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2794 crtc_state->active_planes |= BIT(plane->id);
2795 } else {
2796 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2797 crtc_state->active_planes &= ~BIT(plane->id);
2798 }
2799
2800 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2801 crtc_state->base.crtc->name,
2802 crtc_state->active_planes);
2803 }
2804
2805 static void
2806 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2807 struct intel_initial_plane_config *plane_config)
2808 {
2809 struct drm_device *dev = intel_crtc->base.dev;
2810 struct drm_i915_private *dev_priv = to_i915(dev);
2811 struct drm_crtc *c;
2812 struct drm_i915_gem_object *obj;
2813 struct drm_plane *primary = intel_crtc->base.primary;
2814 struct drm_plane_state *plane_state = primary->state;
2815 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2816 struct intel_plane *intel_plane = to_intel_plane(primary);
2817 struct intel_plane_state *intel_state =
2818 to_intel_plane_state(plane_state);
2819 struct drm_framebuffer *fb;
2820
2821 if (!plane_config->fb)
2822 return;
2823
2824 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2825 fb = &plane_config->fb->base;
2826 goto valid_fb;
2827 }
2828
2829 kfree(plane_config->fb);
2830
2831 /*
2832 * Failed to alloc the obj, check to see if we should share
2833 * an fb with another CRTC instead
2834 */
2835 for_each_crtc(dev, c) {
2836 struct intel_plane_state *state;
2837
2838 if (c == &intel_crtc->base)
2839 continue;
2840
2841 if (!to_intel_crtc(c)->active)
2842 continue;
2843
2844 state = to_intel_plane_state(c->primary->state);
2845 if (!state->vma)
2846 continue;
2847
2848 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2849 fb = c->primary->fb;
2850 drm_framebuffer_reference(fb);
2851 goto valid_fb;
2852 }
2853 }
2854
2855 /*
2856 * We've failed to reconstruct the BIOS FB. Current display state
2857 * indicates that the primary plane is visible, but has a NULL FB,
2858 * which will lead to problems later if we don't fix it up. The
2859 * simplest solution is to just disable the primary plane now and
2860 * pretend the BIOS never had it enabled.
2861 */
2862 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2863 to_intel_plane_state(plane_state),
2864 false);
2865 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2866 trace_intel_disable_plane(primary, intel_crtc);
2867 intel_plane->disable_plane(intel_plane, intel_crtc);
2868
2869 return;
2870
2871 valid_fb:
2872 mutex_lock(&dev->struct_mutex);
2873 intel_state->vma =
2874 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2875 mutex_unlock(&dev->struct_mutex);
2876 if (IS_ERR(intel_state->vma)) {
2877 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2878 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2879
2880 intel_state->vma = NULL;
2881 drm_framebuffer_unreference(fb);
2882 return;
2883 }
2884
2885 plane_state->src_x = 0;
2886 plane_state->src_y = 0;
2887 plane_state->src_w = fb->width << 16;
2888 plane_state->src_h = fb->height << 16;
2889
2890 plane_state->crtc_x = 0;
2891 plane_state->crtc_y = 0;
2892 plane_state->crtc_w = fb->width;
2893 plane_state->crtc_h = fb->height;
2894
2895 intel_state->base.src = drm_plane_state_src(plane_state);
2896 intel_state->base.dst = drm_plane_state_dest(plane_state);
2897
2898 obj = intel_fb_obj(fb);
2899 if (i915_gem_object_is_tiled(obj))
2900 dev_priv->preserve_bios_swizzle = true;
2901
2902 drm_framebuffer_reference(fb);
2903 primary->fb = primary->state->fb = fb;
2904 primary->crtc = primary->state->crtc = &intel_crtc->base;
2905
2906 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2907 to_intel_plane_state(plane_state),
2908 true);
2909
2910 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2911 &obj->frontbuffer_bits);
2912 }
2913
2914 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2915 unsigned int rotation)
2916 {
2917 int cpp = fb->format->cpp[plane];
2918
2919 switch (fb->modifier) {
2920 case DRM_FORMAT_MOD_LINEAR:
2921 case I915_FORMAT_MOD_X_TILED:
2922 switch (cpp) {
2923 case 8:
2924 return 4096;
2925 case 4:
2926 case 2:
2927 case 1:
2928 return 8192;
2929 default:
2930 MISSING_CASE(cpp);
2931 break;
2932 }
2933 break;
2934 case I915_FORMAT_MOD_Y_TILED_CCS:
2935 case I915_FORMAT_MOD_Yf_TILED_CCS:
2936 /* FIXME AUX plane? */
2937 case I915_FORMAT_MOD_Y_TILED:
2938 case I915_FORMAT_MOD_Yf_TILED:
2939 switch (cpp) {
2940 case 8:
2941 return 2048;
2942 case 4:
2943 return 4096;
2944 case 2:
2945 case 1:
2946 return 8192;
2947 default:
2948 MISSING_CASE(cpp);
2949 break;
2950 }
2951 break;
2952 default:
2953 MISSING_CASE(fb->modifier);
2954 }
2955
2956 return 2048;
2957 }
2958
2959 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2960 int main_x, int main_y, u32 main_offset)
2961 {
2962 const struct drm_framebuffer *fb = plane_state->base.fb;
2963 int hsub = fb->format->hsub;
2964 int vsub = fb->format->vsub;
2965 int aux_x = plane_state->aux.x;
2966 int aux_y = plane_state->aux.y;
2967 u32 aux_offset = plane_state->aux.offset;
2968 u32 alignment = intel_surf_alignment(fb, 1);
2969
2970 while (aux_offset >= main_offset && aux_y <= main_y) {
2971 int x, y;
2972
2973 if (aux_x == main_x && aux_y == main_y)
2974 break;
2975
2976 if (aux_offset == 0)
2977 break;
2978
2979 x = aux_x / hsub;
2980 y = aux_y / vsub;
2981 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2982 aux_offset, aux_offset - alignment);
2983 aux_x = x * hsub + aux_x % hsub;
2984 aux_y = y * vsub + aux_y % vsub;
2985 }
2986
2987 if (aux_x != main_x || aux_y != main_y)
2988 return false;
2989
2990 plane_state->aux.offset = aux_offset;
2991 plane_state->aux.x = aux_x;
2992 plane_state->aux.y = aux_y;
2993
2994 return true;
2995 }
2996
2997 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2998 {
2999 const struct drm_framebuffer *fb = plane_state->base.fb;
3000 unsigned int rotation = plane_state->base.rotation;
3001 int x = plane_state->base.src.x1 >> 16;
3002 int y = plane_state->base.src.y1 >> 16;
3003 int w = drm_rect_width(&plane_state->base.src) >> 16;
3004 int h = drm_rect_height(&plane_state->base.src) >> 16;
3005 int max_width = skl_max_plane_width(fb, 0, rotation);
3006 int max_height = 4096;
3007 u32 alignment, offset, aux_offset = plane_state->aux.offset;
3008
3009 if (w > max_width || h > max_height) {
3010 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3011 w, h, max_width, max_height);
3012 return -EINVAL;
3013 }
3014
3015 intel_add_fb_offsets(&x, &y, plane_state, 0);
3016 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3017 alignment = intel_surf_alignment(fb, 0);
3018
3019 /*
3020 * AUX surface offset is specified as the distance from the
3021 * main surface offset, and it must be non-negative. Make
3022 * sure that is what we will get.
3023 */
3024 if (offset > aux_offset)
3025 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3026 offset, aux_offset & ~(alignment - 1));
3027
3028 /*
3029 * When using an X-tiled surface, the plane blows up
3030 * if the x offset + width exceed the stride.
3031 *
3032 * TODO: linear and Y-tiled seem fine, Yf untested,
3033 */
3034 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3035 int cpp = fb->format->cpp[0];
3036
3037 while ((x + w) * cpp > fb->pitches[0]) {
3038 if (offset == 0) {
3039 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3040 return -EINVAL;
3041 }
3042
3043 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3044 offset, offset - alignment);
3045 }
3046 }
3047
3048 /*
3049 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3050 * they match with the main surface x/y offsets.
3051 */
3052 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3053 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3054 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3055 if (offset == 0)
3056 break;
3057
3058 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3059 offset, offset - alignment);
3060 }
3061
3062 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3063 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3064 return -EINVAL;
3065 }
3066 }
3067
3068 plane_state->main.offset = offset;
3069 plane_state->main.x = x;
3070 plane_state->main.y = y;
3071
3072 return 0;
3073 }
3074
3075 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3076 {
3077 const struct drm_framebuffer *fb = plane_state->base.fb;
3078 unsigned int rotation = plane_state->base.rotation;
3079 int max_width = skl_max_plane_width(fb, 1, rotation);
3080 int max_height = 4096;
3081 int x = plane_state->base.src.x1 >> 17;
3082 int y = plane_state->base.src.y1 >> 17;
3083 int w = drm_rect_width(&plane_state->base.src) >> 17;
3084 int h = drm_rect_height(&plane_state->base.src) >> 17;
3085 u32 offset;
3086
3087 intel_add_fb_offsets(&x, &y, plane_state, 1);
3088 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3089
3090 /* FIXME not quite sure how/if these apply to the chroma plane */
3091 if (w > max_width || h > max_height) {
3092 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3093 w, h, max_width, max_height);
3094 return -EINVAL;
3095 }
3096
3097 plane_state->aux.offset = offset;
3098 plane_state->aux.x = x;
3099 plane_state->aux.y = y;
3100
3101 return 0;
3102 }
3103
3104 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3105 {
3106 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3107 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3108 const struct drm_framebuffer *fb = plane_state->base.fb;
3109 int src_x = plane_state->base.src.x1 >> 16;
3110 int src_y = plane_state->base.src.y1 >> 16;
3111 int hsub = fb->format->hsub;
3112 int vsub = fb->format->vsub;
3113 int x = src_x / hsub;
3114 int y = src_y / vsub;
3115 u32 offset;
3116
3117 switch (plane->id) {
3118 case PLANE_PRIMARY:
3119 case PLANE_SPRITE0:
3120 break;
3121 default:
3122 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3123 return -EINVAL;
3124 }
3125
3126 if (crtc->pipe == PIPE_C) {
3127 DRM_DEBUG_KMS("No RC support on pipe C\n");
3128 return -EINVAL;
3129 }
3130
3131 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3132 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3133 plane_state->base.rotation);
3134 return -EINVAL;
3135 }
3136
3137 intel_add_fb_offsets(&x, &y, plane_state, 1);
3138 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3139
3140 plane_state->aux.offset = offset;
3141 plane_state->aux.x = x * hsub + src_x % hsub;
3142 plane_state->aux.y = y * vsub + src_y % vsub;
3143
3144 return 0;
3145 }
3146
3147 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3148 {
3149 const struct drm_framebuffer *fb = plane_state->base.fb;
3150 unsigned int rotation = plane_state->base.rotation;
3151 int ret;
3152
3153 if (!plane_state->base.visible)
3154 return 0;
3155
3156 /* Rotate src coordinates to match rotated GTT view */
3157 if (drm_rotation_90_or_270(rotation))
3158 drm_rect_rotate(&plane_state->base.src,
3159 fb->width << 16, fb->height << 16,
3160 DRM_MODE_ROTATE_270);
3161
3162 /*
3163 * Handle the AUX surface first since
3164 * the main surface setup depends on it.
3165 */
3166 if (fb->format->format == DRM_FORMAT_NV12) {
3167 ret = skl_check_nv12_aux_surface(plane_state);
3168 if (ret)
3169 return ret;
3170 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3171 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3172 ret = skl_check_ccs_aux_surface(plane_state);
3173 if (ret)
3174 return ret;
3175 } else {
3176 plane_state->aux.offset = ~0xfff;
3177 plane_state->aux.x = 0;
3178 plane_state->aux.y = 0;
3179 }
3180
3181 ret = skl_check_main_surface(plane_state);
3182 if (ret)
3183 return ret;
3184
3185 return 0;
3186 }
3187
3188 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3189 const struct intel_plane_state *plane_state)
3190 {
3191 struct drm_i915_private *dev_priv =
3192 to_i915(plane_state->base.plane->dev);
3193 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3194 const struct drm_framebuffer *fb = plane_state->base.fb;
3195 unsigned int rotation = plane_state->base.rotation;
3196 u32 dspcntr;
3197
3198 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3199
3200 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3201 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3202 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3203
3204 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3205 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3206
3207 if (INTEL_GEN(dev_priv) < 4)
3208 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3209
3210 switch (fb->format->format) {
3211 case DRM_FORMAT_C8:
3212 dspcntr |= DISPPLANE_8BPP;
3213 break;
3214 case DRM_FORMAT_XRGB1555:
3215 dspcntr |= DISPPLANE_BGRX555;
3216 break;
3217 case DRM_FORMAT_RGB565:
3218 dspcntr |= DISPPLANE_BGRX565;
3219 break;
3220 case DRM_FORMAT_XRGB8888:
3221 dspcntr |= DISPPLANE_BGRX888;
3222 break;
3223 case DRM_FORMAT_XBGR8888:
3224 dspcntr |= DISPPLANE_RGBX888;
3225 break;
3226 case DRM_FORMAT_XRGB2101010:
3227 dspcntr |= DISPPLANE_BGRX101010;
3228 break;
3229 case DRM_FORMAT_XBGR2101010:
3230 dspcntr |= DISPPLANE_RGBX101010;
3231 break;
3232 default:
3233 MISSING_CASE(fb->format->format);
3234 return 0;
3235 }
3236
3237 if (INTEL_GEN(dev_priv) >= 4 &&
3238 fb->modifier == I915_FORMAT_MOD_X_TILED)
3239 dspcntr |= DISPPLANE_TILED;
3240
3241 if (rotation & DRM_MODE_ROTATE_180)
3242 dspcntr |= DISPPLANE_ROTATE_180;
3243
3244 if (rotation & DRM_MODE_REFLECT_X)
3245 dspcntr |= DISPPLANE_MIRROR;
3246
3247 return dspcntr;
3248 }
3249
3250 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3251 {
3252 struct drm_i915_private *dev_priv =
3253 to_i915(plane_state->base.plane->dev);
3254 int src_x = plane_state->base.src.x1 >> 16;
3255 int src_y = plane_state->base.src.y1 >> 16;
3256 u32 offset;
3257
3258 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3259
3260 if (INTEL_GEN(dev_priv) >= 4)
3261 offset = intel_compute_tile_offset(&src_x, &src_y,
3262 plane_state, 0);
3263 else
3264 offset = 0;
3265
3266 /* HSW/BDW do this automagically in hardware */
3267 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3268 unsigned int rotation = plane_state->base.rotation;
3269 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3270 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3271
3272 if (rotation & DRM_MODE_ROTATE_180) {
3273 src_x += src_w - 1;
3274 src_y += src_h - 1;
3275 } else if (rotation & DRM_MODE_REFLECT_X) {
3276 src_x += src_w - 1;
3277 }
3278 }
3279
3280 plane_state->main.offset = offset;
3281 plane_state->main.x = src_x;
3282 plane_state->main.y = src_y;
3283
3284 return 0;
3285 }
3286
3287 static void i9xx_update_primary_plane(struct intel_plane *primary,
3288 const struct intel_crtc_state *crtc_state,
3289 const struct intel_plane_state *plane_state)
3290 {
3291 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3292 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3293 const struct drm_framebuffer *fb = plane_state->base.fb;
3294 enum plane plane = primary->plane;
3295 u32 linear_offset;
3296 u32 dspcntr = plane_state->ctl;
3297 i915_reg_t reg = DSPCNTR(plane);
3298 int x = plane_state->main.x;
3299 int y = plane_state->main.y;
3300 unsigned long irqflags;
3301
3302 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3303
3304 if (INTEL_GEN(dev_priv) >= 4)
3305 crtc->dspaddr_offset = plane_state->main.offset;
3306 else
3307 crtc->dspaddr_offset = linear_offset;
3308
3309 crtc->adjusted_x = x;
3310 crtc->adjusted_y = y;
3311
3312 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3313
3314 if (INTEL_GEN(dev_priv) < 4) {
3315 /* pipesrc and dspsize control the size that is scaled from,
3316 * which should always be the user's requested size.
3317 */
3318 I915_WRITE_FW(DSPSIZE(plane),
3319 ((crtc_state->pipe_src_h - 1) << 16) |
3320 (crtc_state->pipe_src_w - 1));
3321 I915_WRITE_FW(DSPPOS(plane), 0);
3322 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3323 I915_WRITE_FW(PRIMSIZE(plane),
3324 ((crtc_state->pipe_src_h - 1) << 16) |
3325 (crtc_state->pipe_src_w - 1));
3326 I915_WRITE_FW(PRIMPOS(plane), 0);
3327 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3328 }
3329
3330 I915_WRITE_FW(reg, dspcntr);
3331
3332 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3333 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3334 I915_WRITE_FW(DSPSURF(plane),
3335 intel_plane_ggtt_offset(plane_state) +
3336 crtc->dspaddr_offset);
3337 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3338 } else if (INTEL_GEN(dev_priv) >= 4) {
3339 I915_WRITE_FW(DSPSURF(plane),
3340 intel_plane_ggtt_offset(plane_state) +
3341 crtc->dspaddr_offset);
3342 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3343 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3344 } else {
3345 I915_WRITE_FW(DSPADDR(plane),
3346 intel_plane_ggtt_offset(plane_state) +
3347 crtc->dspaddr_offset);
3348 }
3349 POSTING_READ_FW(reg);
3350
3351 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3352 }
3353
3354 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3355 struct intel_crtc *crtc)
3356 {
3357 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3358 enum plane plane = primary->plane;
3359 unsigned long irqflags;
3360
3361 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3362
3363 I915_WRITE_FW(DSPCNTR(plane), 0);
3364 if (INTEL_INFO(dev_priv)->gen >= 4)
3365 I915_WRITE_FW(DSPSURF(plane), 0);
3366 else
3367 I915_WRITE_FW(DSPADDR(plane), 0);
3368 POSTING_READ_FW(DSPCNTR(plane));
3369
3370 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3371 }
3372
3373 static u32
3374 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3375 {
3376 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3377 return 64;
3378 else
3379 return intel_tile_width_bytes(fb, plane);
3380 }
3381
3382 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3383 {
3384 struct drm_device *dev = intel_crtc->base.dev;
3385 struct drm_i915_private *dev_priv = to_i915(dev);
3386
3387 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3388 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3389 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3390 }
3391
3392 /*
3393 * This function detaches (aka. unbinds) unused scalers in hardware
3394 */
3395 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3396 {
3397 struct intel_crtc_scaler_state *scaler_state;
3398 int i;
3399
3400 scaler_state = &intel_crtc->config->scaler_state;
3401
3402 /* loop through and disable scalers that aren't in use */
3403 for (i = 0; i < intel_crtc->num_scalers; i++) {
3404 if (!scaler_state->scalers[i].in_use)
3405 skl_detach_scaler(intel_crtc, i);
3406 }
3407 }
3408
3409 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3410 unsigned int rotation)
3411 {
3412 u32 stride;
3413
3414 if (plane >= fb->format->num_planes)
3415 return 0;
3416
3417 stride = intel_fb_pitch(fb, plane, rotation);
3418
3419 /*
3420 * The stride is either expressed as a multiple of 64 bytes chunks for
3421 * linear buffers or in number of tiles for tiled buffers.
3422 */
3423 if (drm_rotation_90_or_270(rotation))
3424 stride /= intel_tile_height(fb, plane);
3425 else
3426 stride /= intel_fb_stride_alignment(fb, plane);
3427
3428 return stride;
3429 }
3430
3431 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3432 {
3433 switch (pixel_format) {
3434 case DRM_FORMAT_C8:
3435 return PLANE_CTL_FORMAT_INDEXED;
3436 case DRM_FORMAT_RGB565:
3437 return PLANE_CTL_FORMAT_RGB_565;
3438 case DRM_FORMAT_XBGR8888:
3439 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3440 case DRM_FORMAT_XRGB8888:
3441 return PLANE_CTL_FORMAT_XRGB_8888;
3442 /*
3443 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3444 * to be already pre-multiplied. We need to add a knob (or a different
3445 * DRM_FORMAT) for user-space to configure that.
3446 */
3447 case DRM_FORMAT_ABGR8888:
3448 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3449 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3450 case DRM_FORMAT_ARGB8888:
3451 return PLANE_CTL_FORMAT_XRGB_8888 |
3452 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3453 case DRM_FORMAT_XRGB2101010:
3454 return PLANE_CTL_FORMAT_XRGB_2101010;
3455 case DRM_FORMAT_XBGR2101010:
3456 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3457 case DRM_FORMAT_YUYV:
3458 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3459 case DRM_FORMAT_YVYU:
3460 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3461 case DRM_FORMAT_UYVY:
3462 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3463 case DRM_FORMAT_VYUY:
3464 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3465 default:
3466 MISSING_CASE(pixel_format);
3467 }
3468
3469 return 0;
3470 }
3471
3472 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3473 {
3474 switch (fb_modifier) {
3475 case DRM_FORMAT_MOD_LINEAR:
3476 break;
3477 case I915_FORMAT_MOD_X_TILED:
3478 return PLANE_CTL_TILED_X;
3479 case I915_FORMAT_MOD_Y_TILED:
3480 return PLANE_CTL_TILED_Y;
3481 case I915_FORMAT_MOD_Y_TILED_CCS:
3482 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3483 case I915_FORMAT_MOD_Yf_TILED:
3484 return PLANE_CTL_TILED_YF;
3485 case I915_FORMAT_MOD_Yf_TILED_CCS:
3486 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3487 default:
3488 MISSING_CASE(fb_modifier);
3489 }
3490
3491 return 0;
3492 }
3493
3494 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3495 {
3496 switch (rotation) {
3497 case DRM_MODE_ROTATE_0:
3498 break;
3499 /*
3500 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3501 * while i915 HW rotation is clockwise, thats why this swapping.
3502 */
3503 case DRM_MODE_ROTATE_90:
3504 return PLANE_CTL_ROTATE_270;
3505 case DRM_MODE_ROTATE_180:
3506 return PLANE_CTL_ROTATE_180;
3507 case DRM_MODE_ROTATE_270:
3508 return PLANE_CTL_ROTATE_90;
3509 default:
3510 MISSING_CASE(rotation);
3511 }
3512
3513 return 0;
3514 }
3515
3516 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3517 const struct intel_plane_state *plane_state)
3518 {
3519 struct drm_i915_private *dev_priv =
3520 to_i915(plane_state->base.plane->dev);
3521 const struct drm_framebuffer *fb = plane_state->base.fb;
3522 unsigned int rotation = plane_state->base.rotation;
3523 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3524 u32 plane_ctl;
3525
3526 plane_ctl = PLANE_CTL_ENABLE;
3527
3528 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3529 plane_ctl |=
3530 PLANE_CTL_PIPE_GAMMA_ENABLE |
3531 PLANE_CTL_PIPE_CSC_ENABLE |
3532 PLANE_CTL_PLANE_GAMMA_DISABLE;
3533 }
3534
3535 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3536 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3537 plane_ctl |= skl_plane_ctl_rotation(rotation);
3538
3539 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3540 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3541 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3542 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3543
3544 return plane_ctl;
3545 }
3546
3547 static void skylake_update_primary_plane(struct intel_plane *plane,
3548 const struct intel_crtc_state *crtc_state,
3549 const struct intel_plane_state *plane_state)
3550 {
3551 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3552 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3553 const struct drm_framebuffer *fb = plane_state->base.fb;
3554 enum plane_id plane_id = plane->id;
3555 enum pipe pipe = plane->pipe;
3556 u32 plane_ctl = plane_state->ctl;
3557 unsigned int rotation = plane_state->base.rotation;
3558 u32 stride = skl_plane_stride(fb, 0, rotation);
3559 u32 aux_stride = skl_plane_stride(fb, 1, rotation);
3560 u32 surf_addr = plane_state->main.offset;
3561 int scaler_id = plane_state->scaler_id;
3562 int src_x = plane_state->main.x;
3563 int src_y = plane_state->main.y;
3564 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3565 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3566 int dst_x = plane_state->base.dst.x1;
3567 int dst_y = plane_state->base.dst.y1;
3568 int dst_w = drm_rect_width(&plane_state->base.dst);
3569 int dst_h = drm_rect_height(&plane_state->base.dst);
3570 unsigned long irqflags;
3571
3572 /* Sizes are 0 based */
3573 src_w--;
3574 src_h--;
3575 dst_w--;
3576 dst_h--;
3577
3578 crtc->dspaddr_offset = surf_addr;
3579
3580 crtc->adjusted_x = src_x;
3581 crtc->adjusted_y = src_y;
3582
3583 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3584
3585 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3586 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3587 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3588 PLANE_COLOR_PIPE_CSC_ENABLE |
3589 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3590 }
3591
3592 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3593 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3594 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3595 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3596 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
3597 (plane_state->aux.offset - surf_addr) | aux_stride);
3598 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
3599 (plane_state->aux.y << 16) | plane_state->aux.x);
3600
3601 if (scaler_id >= 0) {
3602 uint32_t ps_ctrl = 0;
3603
3604 WARN_ON(!dst_w || !dst_h);
3605 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3606 crtc_state->scaler_state.scalers[scaler_id].mode;
3607 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3608 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3609 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3610 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3611 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3612 } else {
3613 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3614 }
3615
3616 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3617 intel_plane_ggtt_offset(plane_state) + surf_addr);
3618
3619 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3620
3621 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3622 }
3623
3624 static void skylake_disable_primary_plane(struct intel_plane *primary,
3625 struct intel_crtc *crtc)
3626 {
3627 struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3628 enum plane_id plane_id = primary->id;
3629 enum pipe pipe = primary->pipe;
3630 unsigned long irqflags;
3631
3632 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3633
3634 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3635 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3636 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3637
3638 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3639 }
3640
3641 static int
3642 __intel_display_resume(struct drm_device *dev,
3643 struct drm_atomic_state *state,
3644 struct drm_modeset_acquire_ctx *ctx)
3645 {
3646 struct drm_crtc_state *crtc_state;
3647 struct drm_crtc *crtc;
3648 int i, ret;
3649
3650 intel_modeset_setup_hw_state(dev, ctx);
3651 i915_redisable_vga(to_i915(dev));
3652
3653 if (!state)
3654 return 0;
3655
3656 /*
3657 * We've duplicated the state, pointers to the old state are invalid.
3658 *
3659 * Don't attempt to use the old state until we commit the duplicated state.
3660 */
3661 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3662 /*
3663 * Force recalculation even if we restore
3664 * current state. With fast modeset this may not result
3665 * in a modeset when the state is compatible.
3666 */
3667 crtc_state->mode_changed = true;
3668 }
3669
3670 /* ignore any reset values/BIOS leftovers in the WM registers */
3671 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3672 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3673
3674 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3675
3676 WARN_ON(ret == -EDEADLK);
3677 return ret;
3678 }
3679
3680 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3681 {
3682 return intel_has_gpu_reset(dev_priv) &&
3683 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3684 }
3685
3686 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3687 {
3688 struct drm_device *dev = &dev_priv->drm;
3689 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3690 struct drm_atomic_state *state;
3691 int ret;
3692
3693
3694 /* reset doesn't touch the display */
3695 if (!i915_modparams.force_reset_modeset_test &&
3696 !gpu_reset_clobbers_display(dev_priv))
3697 return;
3698
3699 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3700 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3701 wake_up_all(&dev_priv->gpu_error.wait_queue);
3702
3703 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3704 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3705 i915_gem_set_wedged(dev_priv);
3706 }
3707
3708 /*
3709 * Need mode_config.mutex so that we don't
3710 * trample ongoing ->detect() and whatnot.
3711 */
3712 mutex_lock(&dev->mode_config.mutex);
3713 drm_modeset_acquire_init(ctx, 0);
3714 while (1) {
3715 ret = drm_modeset_lock_all_ctx(dev, ctx);
3716 if (ret != -EDEADLK)
3717 break;
3718
3719 drm_modeset_backoff(ctx);
3720 }
3721 /*
3722 * Disabling the crtcs gracefully seems nicer. Also the
3723 * g33 docs say we should at least disable all the planes.
3724 */
3725 state = drm_atomic_helper_duplicate_state(dev, ctx);
3726 if (IS_ERR(state)) {
3727 ret = PTR_ERR(state);
3728 DRM_ERROR("Duplicating state failed with %i\n", ret);
3729 return;
3730 }
3731
3732 ret = drm_atomic_helper_disable_all(dev, ctx);
3733 if (ret) {
3734 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3735 drm_atomic_state_put(state);
3736 return;
3737 }
3738
3739 dev_priv->modeset_restore_state = state;
3740 state->acquire_ctx = ctx;
3741 }
3742
3743 void intel_finish_reset(struct drm_i915_private *dev_priv)
3744 {
3745 struct drm_device *dev = &dev_priv->drm;
3746 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3747 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3748 int ret;
3749
3750 /* reset doesn't touch the display */
3751 if (!i915_modparams.force_reset_modeset_test &&
3752 !gpu_reset_clobbers_display(dev_priv))
3753 return;
3754
3755 if (!state)
3756 goto unlock;
3757
3758 dev_priv->modeset_restore_state = NULL;
3759
3760 /* reset doesn't touch the display */
3761 if (!gpu_reset_clobbers_display(dev_priv)) {
3762 /* for testing only restore the display */
3763 ret = __intel_display_resume(dev, state, ctx);
3764 if (ret)
3765 DRM_ERROR("Restoring old state failed with %i\n", ret);
3766 } else {
3767 /*
3768 * The display has been reset as well,
3769 * so need a full re-initialization.
3770 */
3771 intel_runtime_pm_disable_interrupts(dev_priv);
3772 intel_runtime_pm_enable_interrupts(dev_priv);
3773
3774 intel_pps_unlock_regs_wa(dev_priv);
3775 intel_modeset_init_hw(dev);
3776
3777 spin_lock_irq(&dev_priv->irq_lock);
3778 if (dev_priv->display.hpd_irq_setup)
3779 dev_priv->display.hpd_irq_setup(dev_priv);
3780 spin_unlock_irq(&dev_priv->irq_lock);
3781
3782 ret = __intel_display_resume(dev, state, ctx);
3783 if (ret)
3784 DRM_ERROR("Restoring old state failed with %i\n", ret);
3785
3786 intel_hpd_init(dev_priv);
3787 }
3788
3789 drm_atomic_state_put(state);
3790 unlock:
3791 drm_modeset_drop_locks(ctx);
3792 drm_modeset_acquire_fini(ctx);
3793 mutex_unlock(&dev->mode_config.mutex);
3794
3795 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3796 }
3797
3798 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3799 const struct intel_crtc_state *new_crtc_state)
3800 {
3801 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3802 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3803
3804 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3805 crtc->base.mode = new_crtc_state->base.mode;
3806
3807 /*
3808 * Update pipe size and adjust fitter if needed: the reason for this is
3809 * that in compute_mode_changes we check the native mode (not the pfit
3810 * mode) to see if we can flip rather than do a full mode set. In the
3811 * fastboot case, we'll flip, but if we don't update the pipesrc and
3812 * pfit state, we'll end up with a big fb scanned out into the wrong
3813 * sized surface.
3814 */
3815
3816 I915_WRITE(PIPESRC(crtc->pipe),
3817 ((new_crtc_state->pipe_src_w - 1) << 16) |
3818 (new_crtc_state->pipe_src_h - 1));
3819
3820 /* on skylake this is done by detaching scalers */
3821 if (INTEL_GEN(dev_priv) >= 9) {
3822 skl_detach_scalers(crtc);
3823
3824 if (new_crtc_state->pch_pfit.enabled)
3825 skylake_pfit_enable(crtc);
3826 } else if (HAS_PCH_SPLIT(dev_priv)) {
3827 if (new_crtc_state->pch_pfit.enabled)
3828 ironlake_pfit_enable(crtc);
3829 else if (old_crtc_state->pch_pfit.enabled)
3830 ironlake_pfit_disable(crtc, true);
3831 }
3832 }
3833
3834 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3835 {
3836 struct drm_device *dev = crtc->base.dev;
3837 struct drm_i915_private *dev_priv = to_i915(dev);
3838 int pipe = crtc->pipe;
3839 i915_reg_t reg;
3840 u32 temp;
3841
3842 /* enable normal train */
3843 reg = FDI_TX_CTL(pipe);
3844 temp = I915_READ(reg);
3845 if (IS_IVYBRIDGE(dev_priv)) {
3846 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3847 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3848 } else {
3849 temp &= ~FDI_LINK_TRAIN_NONE;
3850 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3851 }
3852 I915_WRITE(reg, temp);
3853
3854 reg = FDI_RX_CTL(pipe);
3855 temp = I915_READ(reg);
3856 if (HAS_PCH_CPT(dev_priv)) {
3857 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3858 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3859 } else {
3860 temp &= ~FDI_LINK_TRAIN_NONE;
3861 temp |= FDI_LINK_TRAIN_NONE;
3862 }
3863 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3864
3865 /* wait one idle pattern time */
3866 POSTING_READ(reg);
3867 udelay(1000);
3868
3869 /* IVB wants error correction enabled */
3870 if (IS_IVYBRIDGE(dev_priv))
3871 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3872 FDI_FE_ERRC_ENABLE);
3873 }
3874
3875 /* The FDI link training functions for ILK/Ibexpeak. */
3876 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3877 const struct intel_crtc_state *crtc_state)
3878 {
3879 struct drm_device *dev = crtc->base.dev;
3880 struct drm_i915_private *dev_priv = to_i915(dev);
3881 int pipe = crtc->pipe;
3882 i915_reg_t reg;
3883 u32 temp, tries;
3884
3885 /* FDI needs bits from pipe first */
3886 assert_pipe_enabled(dev_priv, pipe);
3887
3888 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3889 for train result */
3890 reg = FDI_RX_IMR(pipe);
3891 temp = I915_READ(reg);
3892 temp &= ~FDI_RX_SYMBOL_LOCK;
3893 temp &= ~FDI_RX_BIT_LOCK;
3894 I915_WRITE(reg, temp);
3895 I915_READ(reg);
3896 udelay(150);
3897
3898 /* enable CPU FDI TX and PCH FDI RX */
3899 reg = FDI_TX_CTL(pipe);
3900 temp = I915_READ(reg);
3901 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3902 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3903 temp &= ~FDI_LINK_TRAIN_NONE;
3904 temp |= FDI_LINK_TRAIN_PATTERN_1;
3905 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3906
3907 reg = FDI_RX_CTL(pipe);
3908 temp = I915_READ(reg);
3909 temp &= ~FDI_LINK_TRAIN_NONE;
3910 temp |= FDI_LINK_TRAIN_PATTERN_1;
3911 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3912
3913 POSTING_READ(reg);
3914 udelay(150);
3915
3916 /* Ironlake workaround, enable clock pointer after FDI enable*/
3917 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3918 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3919 FDI_RX_PHASE_SYNC_POINTER_EN);
3920
3921 reg = FDI_RX_IIR(pipe);
3922 for (tries = 0; tries < 5; tries++) {
3923 temp = I915_READ(reg);
3924 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3925
3926 if ((temp & FDI_RX_BIT_LOCK)) {
3927 DRM_DEBUG_KMS("FDI train 1 done.\n");
3928 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3929 break;
3930 }
3931 }
3932 if (tries == 5)
3933 DRM_ERROR("FDI train 1 fail!\n");
3934
3935 /* Train 2 */
3936 reg = FDI_TX_CTL(pipe);
3937 temp = I915_READ(reg);
3938 temp &= ~FDI_LINK_TRAIN_NONE;
3939 temp |= FDI_LINK_TRAIN_PATTERN_2;
3940 I915_WRITE(reg, temp);
3941
3942 reg = FDI_RX_CTL(pipe);
3943 temp = I915_READ(reg);
3944 temp &= ~FDI_LINK_TRAIN_NONE;
3945 temp |= FDI_LINK_TRAIN_PATTERN_2;
3946 I915_WRITE(reg, temp);
3947
3948 POSTING_READ(reg);
3949 udelay(150);
3950
3951 reg = FDI_RX_IIR(pipe);
3952 for (tries = 0; tries < 5; tries++) {
3953 temp = I915_READ(reg);
3954 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3955
3956 if (temp & FDI_RX_SYMBOL_LOCK) {
3957 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3958 DRM_DEBUG_KMS("FDI train 2 done.\n");
3959 break;
3960 }
3961 }
3962 if (tries == 5)
3963 DRM_ERROR("FDI train 2 fail!\n");
3964
3965 DRM_DEBUG_KMS("FDI train done\n");
3966
3967 }
3968
3969 static const int snb_b_fdi_train_param[] = {
3970 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3971 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3972 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3973 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3974 };
3975
3976 /* The FDI link training functions for SNB/Cougarpoint. */
3977 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3978 const struct intel_crtc_state *crtc_state)
3979 {
3980 struct drm_device *dev = crtc->base.dev;
3981 struct drm_i915_private *dev_priv = to_i915(dev);
3982 int pipe = crtc->pipe;
3983 i915_reg_t reg;
3984 u32 temp, i, retry;
3985
3986 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3987 for train result */
3988 reg = FDI_RX_IMR(pipe);
3989 temp = I915_READ(reg);
3990 temp &= ~FDI_RX_SYMBOL_LOCK;
3991 temp &= ~FDI_RX_BIT_LOCK;
3992 I915_WRITE(reg, temp);
3993
3994 POSTING_READ(reg);
3995 udelay(150);
3996
3997 /* enable CPU FDI TX and PCH FDI RX */
3998 reg = FDI_TX_CTL(pipe);
3999 temp = I915_READ(reg);
4000 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4001 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4002 temp &= ~FDI_LINK_TRAIN_NONE;
4003 temp |= FDI_LINK_TRAIN_PATTERN_1;
4004 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4005 /* SNB-B */
4006 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4007 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4008
4009 I915_WRITE(FDI_RX_MISC(pipe),
4010 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4011
4012 reg = FDI_RX_CTL(pipe);
4013 temp = I915_READ(reg);
4014 if (HAS_PCH_CPT(dev_priv)) {
4015 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4016 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4017 } else {
4018 temp &= ~FDI_LINK_TRAIN_NONE;
4019 temp |= FDI_LINK_TRAIN_PATTERN_1;
4020 }
4021 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4022
4023 POSTING_READ(reg);
4024 udelay(150);
4025
4026 for (i = 0; i < 4; i++) {
4027 reg = FDI_TX_CTL(pipe);
4028 temp = I915_READ(reg);
4029 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4030 temp |= snb_b_fdi_train_param[i];
4031 I915_WRITE(reg, temp);
4032
4033 POSTING_READ(reg);
4034 udelay(500);
4035
4036 for (retry = 0; retry < 5; retry++) {
4037 reg = FDI_RX_IIR(pipe);
4038 temp = I915_READ(reg);
4039 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4040 if (temp & FDI_RX_BIT_LOCK) {
4041 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4042 DRM_DEBUG_KMS("FDI train 1 done.\n");
4043 break;
4044 }
4045 udelay(50);
4046 }
4047 if (retry < 5)
4048 break;
4049 }
4050 if (i == 4)
4051 DRM_ERROR("FDI train 1 fail!\n");
4052
4053 /* Train 2 */
4054 reg = FDI_TX_CTL(pipe);
4055 temp = I915_READ(reg);
4056 temp &= ~FDI_LINK_TRAIN_NONE;
4057 temp |= FDI_LINK_TRAIN_PATTERN_2;
4058 if (IS_GEN6(dev_priv)) {
4059 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4060 /* SNB-B */
4061 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4062 }
4063 I915_WRITE(reg, temp);
4064
4065 reg = FDI_RX_CTL(pipe);
4066 temp = I915_READ(reg);
4067 if (HAS_PCH_CPT(dev_priv)) {
4068 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4069 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4070 } else {
4071 temp &= ~FDI_LINK_TRAIN_NONE;
4072 temp |= FDI_LINK_TRAIN_PATTERN_2;
4073 }
4074 I915_WRITE(reg, temp);
4075
4076 POSTING_READ(reg);
4077 udelay(150);
4078
4079 for (i = 0; i < 4; i++) {
4080 reg = FDI_TX_CTL(pipe);
4081 temp = I915_READ(reg);
4082 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4083 temp |= snb_b_fdi_train_param[i];
4084 I915_WRITE(reg, temp);
4085
4086 POSTING_READ(reg);
4087 udelay(500);
4088
4089 for (retry = 0; retry < 5; retry++) {
4090 reg = FDI_RX_IIR(pipe);
4091 temp = I915_READ(reg);
4092 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4093 if (temp & FDI_RX_SYMBOL_LOCK) {
4094 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4095 DRM_DEBUG_KMS("FDI train 2 done.\n");
4096 break;
4097 }
4098 udelay(50);
4099 }
4100 if (retry < 5)
4101 break;
4102 }
4103 if (i == 4)
4104 DRM_ERROR("FDI train 2 fail!\n");
4105
4106 DRM_DEBUG_KMS("FDI train done.\n");
4107 }
4108
4109 /* Manual link training for Ivy Bridge A0 parts */
4110 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4111 const struct intel_crtc_state *crtc_state)
4112 {
4113 struct drm_device *dev = crtc->base.dev;
4114 struct drm_i915_private *dev_priv = to_i915(dev);
4115 int pipe = crtc->pipe;
4116 i915_reg_t reg;
4117 u32 temp, i, j;
4118
4119 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4120 for train result */
4121 reg = FDI_RX_IMR(pipe);
4122 temp = I915_READ(reg);
4123 temp &= ~FDI_RX_SYMBOL_LOCK;
4124 temp &= ~FDI_RX_BIT_LOCK;
4125 I915_WRITE(reg, temp);
4126
4127 POSTING_READ(reg);
4128 udelay(150);
4129
4130 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4131 I915_READ(FDI_RX_IIR(pipe)));
4132
4133 /* Try each vswing and preemphasis setting twice before moving on */
4134 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4135 /* disable first in case we need to retry */
4136 reg = FDI_TX_CTL(pipe);
4137 temp = I915_READ(reg);
4138 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4139 temp &= ~FDI_TX_ENABLE;
4140 I915_WRITE(reg, temp);
4141
4142 reg = FDI_RX_CTL(pipe);
4143 temp = I915_READ(reg);
4144 temp &= ~FDI_LINK_TRAIN_AUTO;
4145 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4146 temp &= ~FDI_RX_ENABLE;
4147 I915_WRITE(reg, temp);
4148
4149 /* enable CPU FDI TX and PCH FDI RX */
4150 reg = FDI_TX_CTL(pipe);
4151 temp = I915_READ(reg);
4152 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4153 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4154 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4155 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4156 temp |= snb_b_fdi_train_param[j/2];
4157 temp |= FDI_COMPOSITE_SYNC;
4158 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4159
4160 I915_WRITE(FDI_RX_MISC(pipe),
4161 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4162
4163 reg = FDI_RX_CTL(pipe);
4164 temp = I915_READ(reg);
4165 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4166 temp |= FDI_COMPOSITE_SYNC;
4167 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4168
4169 POSTING_READ(reg);
4170 udelay(1); /* should be 0.5us */
4171
4172 for (i = 0; i < 4; i++) {
4173 reg = FDI_RX_IIR(pipe);
4174 temp = I915_READ(reg);
4175 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4176
4177 if (temp & FDI_RX_BIT_LOCK ||
4178 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4179 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4180 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4181 i);
4182 break;
4183 }
4184 udelay(1); /* should be 0.5us */
4185 }
4186 if (i == 4) {
4187 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4188 continue;
4189 }
4190
4191 /* Train 2 */
4192 reg = FDI_TX_CTL(pipe);
4193 temp = I915_READ(reg);
4194 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4195 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4196 I915_WRITE(reg, temp);
4197
4198 reg = FDI_RX_CTL(pipe);
4199 temp = I915_READ(reg);
4200 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4201 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4202 I915_WRITE(reg, temp);
4203
4204 POSTING_READ(reg);
4205 udelay(2); /* should be 1.5us */
4206
4207 for (i = 0; i < 4; i++) {
4208 reg = FDI_RX_IIR(pipe);
4209 temp = I915_READ(reg);
4210 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4211
4212 if (temp & FDI_RX_SYMBOL_LOCK ||
4213 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4214 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4215 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4216 i);
4217 goto train_done;
4218 }
4219 udelay(2); /* should be 1.5us */
4220 }
4221 if (i == 4)
4222 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4223 }
4224
4225 train_done:
4226 DRM_DEBUG_KMS("FDI train done.\n");
4227 }
4228
4229 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4230 {
4231 struct drm_device *dev = intel_crtc->base.dev;
4232 struct drm_i915_private *dev_priv = to_i915(dev);
4233 int pipe = intel_crtc->pipe;
4234 i915_reg_t reg;
4235 u32 temp;
4236
4237 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4238 reg = FDI_RX_CTL(pipe);
4239 temp = I915_READ(reg);
4240 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4241 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4242 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4243 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4244
4245 POSTING_READ(reg);
4246 udelay(200);
4247
4248 /* Switch from Rawclk to PCDclk */
4249 temp = I915_READ(reg);
4250 I915_WRITE(reg, temp | FDI_PCDCLK);
4251
4252 POSTING_READ(reg);
4253 udelay(200);
4254
4255 /* Enable CPU FDI TX PLL, always on for Ironlake */
4256 reg = FDI_TX_CTL(pipe);
4257 temp = I915_READ(reg);
4258 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4259 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4260
4261 POSTING_READ(reg);
4262 udelay(100);
4263 }
4264 }
4265
4266 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4267 {
4268 struct drm_device *dev = intel_crtc->base.dev;
4269 struct drm_i915_private *dev_priv = to_i915(dev);
4270 int pipe = intel_crtc->pipe;
4271 i915_reg_t reg;
4272 u32 temp;
4273
4274 /* Switch from PCDclk to Rawclk */
4275 reg = FDI_RX_CTL(pipe);
4276 temp = I915_READ(reg);
4277 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4278
4279 /* Disable CPU FDI TX PLL */
4280 reg = FDI_TX_CTL(pipe);
4281 temp = I915_READ(reg);
4282 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4283
4284 POSTING_READ(reg);
4285 udelay(100);
4286
4287 reg = FDI_RX_CTL(pipe);
4288 temp = I915_READ(reg);
4289 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4290
4291 /* Wait for the clocks to turn off. */
4292 POSTING_READ(reg);
4293 udelay(100);
4294 }
4295
4296 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4297 {
4298 struct drm_device *dev = crtc->dev;
4299 struct drm_i915_private *dev_priv = to_i915(dev);
4300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4301 int pipe = intel_crtc->pipe;
4302 i915_reg_t reg;
4303 u32 temp;
4304
4305 /* disable CPU FDI tx and PCH FDI rx */
4306 reg = FDI_TX_CTL(pipe);
4307 temp = I915_READ(reg);
4308 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4309 POSTING_READ(reg);
4310
4311 reg = FDI_RX_CTL(pipe);
4312 temp = I915_READ(reg);
4313 temp &= ~(0x7 << 16);
4314 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4315 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4316
4317 POSTING_READ(reg);
4318 udelay(100);
4319
4320 /* Ironlake workaround, disable clock pointer after downing FDI */
4321 if (HAS_PCH_IBX(dev_priv))
4322 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4323
4324 /* still set train pattern 1 */
4325 reg = FDI_TX_CTL(pipe);
4326 temp = I915_READ(reg);
4327 temp &= ~FDI_LINK_TRAIN_NONE;
4328 temp |= FDI_LINK_TRAIN_PATTERN_1;
4329 I915_WRITE(reg, temp);
4330
4331 reg = FDI_RX_CTL(pipe);
4332 temp = I915_READ(reg);
4333 if (HAS_PCH_CPT(dev_priv)) {
4334 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4335 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4336 } else {
4337 temp &= ~FDI_LINK_TRAIN_NONE;
4338 temp |= FDI_LINK_TRAIN_PATTERN_1;
4339 }
4340 /* BPC in FDI rx is consistent with that in PIPECONF */
4341 temp &= ~(0x07 << 16);
4342 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4343 I915_WRITE(reg, temp);
4344
4345 POSTING_READ(reg);
4346 udelay(100);
4347 }
4348
4349 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4350 {
4351 struct drm_crtc *crtc;
4352 bool cleanup_done;
4353
4354 drm_for_each_crtc(crtc, &dev_priv->drm) {
4355 struct drm_crtc_commit *commit;
4356 spin_lock(&crtc->commit_lock);
4357 commit = list_first_entry_or_null(&crtc->commit_list,
4358 struct drm_crtc_commit, commit_entry);
4359 cleanup_done = commit ?
4360 try_wait_for_completion(&commit->cleanup_done) : true;
4361 spin_unlock(&crtc->commit_lock);
4362
4363 if (cleanup_done)
4364 continue;
4365
4366 drm_crtc_wait_one_vblank(crtc);
4367
4368 return true;
4369 }
4370
4371 return false;
4372 }
4373
4374 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4375 {
4376 u32 temp;
4377
4378 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4379
4380 mutex_lock(&dev_priv->sb_lock);
4381
4382 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4383 temp |= SBI_SSCCTL_DISABLE;
4384 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4385
4386 mutex_unlock(&dev_priv->sb_lock);
4387 }
4388
4389 /* Program iCLKIP clock to the desired frequency */
4390 static void lpt_program_iclkip(struct intel_crtc *crtc)
4391 {
4392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4393 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4394 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4395 u32 temp;
4396
4397 lpt_disable_iclkip(dev_priv);
4398
4399 /* The iCLK virtual clock root frequency is in MHz,
4400 * but the adjusted_mode->crtc_clock in in KHz. To get the
4401 * divisors, it is necessary to divide one by another, so we
4402 * convert the virtual clock precision to KHz here for higher
4403 * precision.
4404 */
4405 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4406 u32 iclk_virtual_root_freq = 172800 * 1000;
4407 u32 iclk_pi_range = 64;
4408 u32 desired_divisor;
4409
4410 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4411 clock << auxdiv);
4412 divsel = (desired_divisor / iclk_pi_range) - 2;
4413 phaseinc = desired_divisor % iclk_pi_range;
4414
4415 /*
4416 * Near 20MHz is a corner case which is
4417 * out of range for the 7-bit divisor
4418 */
4419 if (divsel <= 0x7f)
4420 break;
4421 }
4422
4423 /* This should not happen with any sane values */
4424 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4425 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4426 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4427 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4428
4429 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4430 clock,
4431 auxdiv,
4432 divsel,
4433 phasedir,
4434 phaseinc);
4435
4436 mutex_lock(&dev_priv->sb_lock);
4437
4438 /* Program SSCDIVINTPHASE6 */
4439 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4440 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4441 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4442 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4443 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4444 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4445 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4446 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4447
4448 /* Program SSCAUXDIV */
4449 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4450 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4451 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4452 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4453
4454 /* Enable modulator and associated divider */
4455 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4456 temp &= ~SBI_SSCCTL_DISABLE;
4457 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4458
4459 mutex_unlock(&dev_priv->sb_lock);
4460
4461 /* Wait for initialization time */
4462 udelay(24);
4463
4464 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4465 }
4466
4467 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4468 {
4469 u32 divsel, phaseinc, auxdiv;
4470 u32 iclk_virtual_root_freq = 172800 * 1000;
4471 u32 iclk_pi_range = 64;
4472 u32 desired_divisor;
4473 u32 temp;
4474
4475 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4476 return 0;
4477
4478 mutex_lock(&dev_priv->sb_lock);
4479
4480 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4481 if (temp & SBI_SSCCTL_DISABLE) {
4482 mutex_unlock(&dev_priv->sb_lock);
4483 return 0;
4484 }
4485
4486 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4487 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4488 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4489 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4490 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4491
4492 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4493 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4494 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4495
4496 mutex_unlock(&dev_priv->sb_lock);
4497
4498 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4499
4500 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4501 desired_divisor << auxdiv);
4502 }
4503
4504 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4505 enum pipe pch_transcoder)
4506 {
4507 struct drm_device *dev = crtc->base.dev;
4508 struct drm_i915_private *dev_priv = to_i915(dev);
4509 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4510
4511 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4512 I915_READ(HTOTAL(cpu_transcoder)));
4513 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4514 I915_READ(HBLANK(cpu_transcoder)));
4515 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4516 I915_READ(HSYNC(cpu_transcoder)));
4517
4518 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4519 I915_READ(VTOTAL(cpu_transcoder)));
4520 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4521 I915_READ(VBLANK(cpu_transcoder)));
4522 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4523 I915_READ(VSYNC(cpu_transcoder)));
4524 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4525 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4526 }
4527
4528 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4529 {
4530 struct drm_i915_private *dev_priv = to_i915(dev);
4531 uint32_t temp;
4532
4533 temp = I915_READ(SOUTH_CHICKEN1);
4534 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4535 return;
4536
4537 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4538 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4539
4540 temp &= ~FDI_BC_BIFURCATION_SELECT;
4541 if (enable)
4542 temp |= FDI_BC_BIFURCATION_SELECT;
4543
4544 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4545 I915_WRITE(SOUTH_CHICKEN1, temp);
4546 POSTING_READ(SOUTH_CHICKEN1);
4547 }
4548
4549 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4550 {
4551 struct drm_device *dev = intel_crtc->base.dev;
4552
4553 switch (intel_crtc->pipe) {
4554 case PIPE_A:
4555 break;
4556 case PIPE_B:
4557 if (intel_crtc->config->fdi_lanes > 2)
4558 cpt_set_fdi_bc_bifurcation(dev, false);
4559 else
4560 cpt_set_fdi_bc_bifurcation(dev, true);
4561
4562 break;
4563 case PIPE_C:
4564 cpt_set_fdi_bc_bifurcation(dev, true);
4565
4566 break;
4567 default:
4568 BUG();
4569 }
4570 }
4571
4572 /* Return which DP Port should be selected for Transcoder DP control */
4573 static enum port
4574 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4575 {
4576 struct drm_device *dev = crtc->base.dev;
4577 struct intel_encoder *encoder;
4578
4579 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4580 if (encoder->type == INTEL_OUTPUT_DP ||
4581 encoder->type == INTEL_OUTPUT_EDP)
4582 return enc_to_dig_port(&encoder->base)->port;
4583 }
4584
4585 return -1;
4586 }
4587
4588 /*
4589 * Enable PCH resources required for PCH ports:
4590 * - PCH PLLs
4591 * - FDI training & RX/TX
4592 * - update transcoder timings
4593 * - DP transcoding bits
4594 * - transcoder
4595 */
4596 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4597 {
4598 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4599 struct drm_device *dev = crtc->base.dev;
4600 struct drm_i915_private *dev_priv = to_i915(dev);
4601 int pipe = crtc->pipe;
4602 u32 temp;
4603
4604 assert_pch_transcoder_disabled(dev_priv, pipe);
4605
4606 if (IS_IVYBRIDGE(dev_priv))
4607 ivybridge_update_fdi_bc_bifurcation(crtc);
4608
4609 /* Write the TU size bits before fdi link training, so that error
4610 * detection works. */
4611 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4612 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4613
4614 /* For PCH output, training FDI link */
4615 dev_priv->display.fdi_link_train(crtc, crtc_state);
4616
4617 /* We need to program the right clock selection before writing the pixel
4618 * mutliplier into the DPLL. */
4619 if (HAS_PCH_CPT(dev_priv)) {
4620 u32 sel;
4621
4622 temp = I915_READ(PCH_DPLL_SEL);
4623 temp |= TRANS_DPLL_ENABLE(pipe);
4624 sel = TRANS_DPLLB_SEL(pipe);
4625 if (crtc_state->shared_dpll ==
4626 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4627 temp |= sel;
4628 else
4629 temp &= ~sel;
4630 I915_WRITE(PCH_DPLL_SEL, temp);
4631 }
4632
4633 /* XXX: pch pll's can be enabled any time before we enable the PCH
4634 * transcoder, and we actually should do this to not upset any PCH
4635 * transcoder that already use the clock when we share it.
4636 *
4637 * Note that enable_shared_dpll tries to do the right thing, but
4638 * get_shared_dpll unconditionally resets the pll - we need that to have
4639 * the right LVDS enable sequence. */
4640 intel_enable_shared_dpll(crtc);
4641
4642 /* set transcoder timing, panel must allow it */
4643 assert_panel_unlocked(dev_priv, pipe);
4644 ironlake_pch_transcoder_set_timings(crtc, pipe);
4645
4646 intel_fdi_normal_train(crtc);
4647
4648 /* For PCH DP, enable TRANS_DP_CTL */
4649 if (HAS_PCH_CPT(dev_priv) &&
4650 intel_crtc_has_dp_encoder(crtc_state)) {
4651 const struct drm_display_mode *adjusted_mode =
4652 &crtc_state->base.adjusted_mode;
4653 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4654 i915_reg_t reg = TRANS_DP_CTL(pipe);
4655 temp = I915_READ(reg);
4656 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4657 TRANS_DP_SYNC_MASK |
4658 TRANS_DP_BPC_MASK);
4659 temp |= TRANS_DP_OUTPUT_ENABLE;
4660 temp |= bpc << 9; /* same format but at 11:9 */
4661
4662 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4663 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4664 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4665 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4666
4667 switch (intel_trans_dp_port_sel(crtc)) {
4668 case PORT_B:
4669 temp |= TRANS_DP_PORT_SEL_B;
4670 break;
4671 case PORT_C:
4672 temp |= TRANS_DP_PORT_SEL_C;
4673 break;
4674 case PORT_D:
4675 temp |= TRANS_DP_PORT_SEL_D;
4676 break;
4677 default:
4678 BUG();
4679 }
4680
4681 I915_WRITE(reg, temp);
4682 }
4683
4684 ironlake_enable_pch_transcoder(dev_priv, pipe);
4685 }
4686
4687 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4688 {
4689 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4690 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4691 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4692
4693 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4694
4695 lpt_program_iclkip(crtc);
4696
4697 /* Set transcoder timing. */
4698 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4699
4700 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4701 }
4702
4703 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4704 {
4705 struct drm_i915_private *dev_priv = to_i915(dev);
4706 i915_reg_t dslreg = PIPEDSL(pipe);
4707 u32 temp;
4708
4709 temp = I915_READ(dslreg);
4710 udelay(500);
4711 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4712 if (wait_for(I915_READ(dslreg) != temp, 5))
4713 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4714 }
4715 }
4716
4717 static int
4718 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4719 unsigned int scaler_user, int *scaler_id,
4720 int src_w, int src_h, int dst_w, int dst_h)
4721 {
4722 struct intel_crtc_scaler_state *scaler_state =
4723 &crtc_state->scaler_state;
4724 struct intel_crtc *intel_crtc =
4725 to_intel_crtc(crtc_state->base.crtc);
4726 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4727 const struct drm_display_mode *adjusted_mode =
4728 &crtc_state->base.adjusted_mode;
4729 int need_scaling;
4730
4731 /*
4732 * Src coordinates are already rotated by 270 degrees for
4733 * the 90/270 degree plane rotation cases (to match the
4734 * GTT mapping), hence no need to account for rotation here.
4735 */
4736 need_scaling = src_w != dst_w || src_h != dst_h;
4737
4738 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4739 need_scaling = true;
4740
4741 /*
4742 * Scaling/fitting not supported in IF-ID mode in GEN9+
4743 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4744 * Once NV12 is enabled, handle it here while allocating scaler
4745 * for NV12.
4746 */
4747 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4748 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4749 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4750 return -EINVAL;
4751 }
4752
4753 /*
4754 * if plane is being disabled or scaler is no more required or force detach
4755 * - free scaler binded to this plane/crtc
4756 * - in order to do this, update crtc->scaler_usage
4757 *
4758 * Here scaler state in crtc_state is set free so that
4759 * scaler can be assigned to other user. Actual register
4760 * update to free the scaler is done in plane/panel-fit programming.
4761 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4762 */
4763 if (force_detach || !need_scaling) {
4764 if (*scaler_id >= 0) {
4765 scaler_state->scaler_users &= ~(1 << scaler_user);
4766 scaler_state->scalers[*scaler_id].in_use = 0;
4767
4768 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4769 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4770 intel_crtc->pipe, scaler_user, *scaler_id,
4771 scaler_state->scaler_users);
4772 *scaler_id = -1;
4773 }
4774 return 0;
4775 }
4776
4777 /* range checks */
4778 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4779 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4780
4781 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4782 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4783 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4784 "size is out of scaler range\n",
4785 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4786 return -EINVAL;
4787 }
4788
4789 /* mark this plane as a scaler user in crtc_state */
4790 scaler_state->scaler_users |= (1 << scaler_user);
4791 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4792 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4793 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4794 scaler_state->scaler_users);
4795
4796 return 0;
4797 }
4798
4799 /**
4800 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4801 *
4802 * @state: crtc's scaler state
4803 *
4804 * Return
4805 * 0 - scaler_usage updated successfully
4806 * error - requested scaling cannot be supported or other error condition
4807 */
4808 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4809 {
4810 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4811
4812 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4813 &state->scaler_state.scaler_id,
4814 state->pipe_src_w, state->pipe_src_h,
4815 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4816 }
4817
4818 /**
4819 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4820 *
4821 * @state: crtc's scaler state
4822 * @plane_state: atomic plane state to update
4823 *
4824 * Return
4825 * 0 - scaler_usage updated successfully
4826 * error - requested scaling cannot be supported or other error condition
4827 */
4828 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4829 struct intel_plane_state *plane_state)
4830 {
4831
4832 struct intel_plane *intel_plane =
4833 to_intel_plane(plane_state->base.plane);
4834 struct drm_framebuffer *fb = plane_state->base.fb;
4835 int ret;
4836
4837 bool force_detach = !fb || !plane_state->base.visible;
4838
4839 ret = skl_update_scaler(crtc_state, force_detach,
4840 drm_plane_index(&intel_plane->base),
4841 &plane_state->scaler_id,
4842 drm_rect_width(&plane_state->base.src) >> 16,
4843 drm_rect_height(&plane_state->base.src) >> 16,
4844 drm_rect_width(&plane_state->base.dst),
4845 drm_rect_height(&plane_state->base.dst));
4846
4847 if (ret || plane_state->scaler_id < 0)
4848 return ret;
4849
4850 /* check colorkey */
4851 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4852 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4853 intel_plane->base.base.id,
4854 intel_plane->base.name);
4855 return -EINVAL;
4856 }
4857
4858 /* Check src format */
4859 switch (fb->format->format) {
4860 case DRM_FORMAT_RGB565:
4861 case DRM_FORMAT_XBGR8888:
4862 case DRM_FORMAT_XRGB8888:
4863 case DRM_FORMAT_ABGR8888:
4864 case DRM_FORMAT_ARGB8888:
4865 case DRM_FORMAT_XRGB2101010:
4866 case DRM_FORMAT_XBGR2101010:
4867 case DRM_FORMAT_YUYV:
4868 case DRM_FORMAT_YVYU:
4869 case DRM_FORMAT_UYVY:
4870 case DRM_FORMAT_VYUY:
4871 break;
4872 default:
4873 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4874 intel_plane->base.base.id, intel_plane->base.name,
4875 fb->base.id, fb->format->format);
4876 return -EINVAL;
4877 }
4878
4879 return 0;
4880 }
4881
4882 static void skylake_scaler_disable(struct intel_crtc *crtc)
4883 {
4884 int i;
4885
4886 for (i = 0; i < crtc->num_scalers; i++)
4887 skl_detach_scaler(crtc, i);
4888 }
4889
4890 static void skylake_pfit_enable(struct intel_crtc *crtc)
4891 {
4892 struct drm_device *dev = crtc->base.dev;
4893 struct drm_i915_private *dev_priv = to_i915(dev);
4894 int pipe = crtc->pipe;
4895 struct intel_crtc_scaler_state *scaler_state =
4896 &crtc->config->scaler_state;
4897
4898 if (crtc->config->pch_pfit.enabled) {
4899 int id;
4900
4901 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4902 return;
4903
4904 id = scaler_state->scaler_id;
4905 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4906 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4907 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4908 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4909 }
4910 }
4911
4912 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4913 {
4914 struct drm_device *dev = crtc->base.dev;
4915 struct drm_i915_private *dev_priv = to_i915(dev);
4916 int pipe = crtc->pipe;
4917
4918 if (crtc->config->pch_pfit.enabled) {
4919 /* Force use of hard-coded filter coefficients
4920 * as some pre-programmed values are broken,
4921 * e.g. x201.
4922 */
4923 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4924 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4925 PF_PIPE_SEL_IVB(pipe));
4926 else
4927 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4928 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4929 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4930 }
4931 }
4932
4933 void hsw_enable_ips(struct intel_crtc *crtc)
4934 {
4935 struct drm_device *dev = crtc->base.dev;
4936 struct drm_i915_private *dev_priv = to_i915(dev);
4937
4938 if (!crtc->config->ips_enabled)
4939 return;
4940
4941 /*
4942 * We can only enable IPS after we enable a plane and wait for a vblank
4943 * This function is called from post_plane_update, which is run after
4944 * a vblank wait.
4945 */
4946
4947 assert_plane_enabled(dev_priv, crtc->plane);
4948 if (IS_BROADWELL(dev_priv)) {
4949 mutex_lock(&dev_priv->pcu_lock);
4950 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4951 IPS_ENABLE | IPS_PCODE_CONTROL));
4952 mutex_unlock(&dev_priv->pcu_lock);
4953 /* Quoting Art Runyan: "its not safe to expect any particular
4954 * value in IPS_CTL bit 31 after enabling IPS through the
4955 * mailbox." Moreover, the mailbox may return a bogus state,
4956 * so we need to just enable it and continue on.
4957 */
4958 } else {
4959 I915_WRITE(IPS_CTL, IPS_ENABLE);
4960 /* The bit only becomes 1 in the next vblank, so this wait here
4961 * is essentially intel_wait_for_vblank. If we don't have this
4962 * and don't wait for vblanks until the end of crtc_enable, then
4963 * the HW state readout code will complain that the expected
4964 * IPS_CTL value is not the one we read. */
4965 if (intel_wait_for_register(dev_priv,
4966 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4967 50))
4968 DRM_ERROR("Timed out waiting for IPS enable\n");
4969 }
4970 }
4971
4972 void hsw_disable_ips(struct intel_crtc *crtc)
4973 {
4974 struct drm_device *dev = crtc->base.dev;
4975 struct drm_i915_private *dev_priv = to_i915(dev);
4976
4977 if (!crtc->config->ips_enabled)
4978 return;
4979
4980 assert_plane_enabled(dev_priv, crtc->plane);
4981 if (IS_BROADWELL(dev_priv)) {
4982 mutex_lock(&dev_priv->pcu_lock);
4983 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4984 mutex_unlock(&dev_priv->pcu_lock);
4985 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4986 if (intel_wait_for_register(dev_priv,
4987 IPS_CTL, IPS_ENABLE, 0,
4988 42))
4989 DRM_ERROR("Timed out waiting for IPS disable\n");
4990 } else {
4991 I915_WRITE(IPS_CTL, 0);
4992 POSTING_READ(IPS_CTL);
4993 }
4994
4995 /* We need to wait for a vblank before we can disable the plane. */
4996 intel_wait_for_vblank(dev_priv, crtc->pipe);
4997 }
4998
4999 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5000 {
5001 if (intel_crtc->overlay) {
5002 struct drm_device *dev = intel_crtc->base.dev;
5003
5004 mutex_lock(&dev->struct_mutex);
5005 (void) intel_overlay_switch_off(intel_crtc->overlay);
5006 mutex_unlock(&dev->struct_mutex);
5007 }
5008
5009 /* Let userspace switch the overlay on again. In most cases userspace
5010 * has to recompute where to put it anyway.
5011 */
5012 }
5013
5014 /**
5015 * intel_post_enable_primary - Perform operations after enabling primary plane
5016 * @crtc: the CRTC whose primary plane was just enabled
5017 *
5018 * Performs potentially sleeping operations that must be done after the primary
5019 * plane is enabled, such as updating FBC and IPS. Note that this may be
5020 * called due to an explicit primary plane update, or due to an implicit
5021 * re-enable that is caused when a sprite plane is updated to no longer
5022 * completely hide the primary plane.
5023 */
5024 static void
5025 intel_post_enable_primary(struct drm_crtc *crtc)
5026 {
5027 struct drm_device *dev = crtc->dev;
5028 struct drm_i915_private *dev_priv = to_i915(dev);
5029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5030 int pipe = intel_crtc->pipe;
5031
5032 /*
5033 * FIXME IPS should be fine as long as one plane is
5034 * enabled, but in practice it seems to have problems
5035 * when going from primary only to sprite only and vice
5036 * versa.
5037 */
5038 hsw_enable_ips(intel_crtc);
5039
5040 /*
5041 * Gen2 reports pipe underruns whenever all planes are disabled.
5042 * So don't enable underrun reporting before at least some planes
5043 * are enabled.
5044 * FIXME: Need to fix the logic to work when we turn off all planes
5045 * but leave the pipe running.
5046 */
5047 if (IS_GEN2(dev_priv))
5048 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5049
5050 /* Underruns don't always raise interrupts, so check manually. */
5051 intel_check_cpu_fifo_underruns(dev_priv);
5052 intel_check_pch_fifo_underruns(dev_priv);
5053 }
5054
5055 /* FIXME move all this to pre_plane_update() with proper state tracking */
5056 static void
5057 intel_pre_disable_primary(struct drm_crtc *crtc)
5058 {
5059 struct drm_device *dev = crtc->dev;
5060 struct drm_i915_private *dev_priv = to_i915(dev);
5061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5062 int pipe = intel_crtc->pipe;
5063
5064 /*
5065 * Gen2 reports pipe underruns whenever all planes are disabled.
5066 * So diasble underrun reporting before all the planes get disabled.
5067 * FIXME: Need to fix the logic to work when we turn off all planes
5068 * but leave the pipe running.
5069 */
5070 if (IS_GEN2(dev_priv))
5071 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5072
5073 /*
5074 * FIXME IPS should be fine as long as one plane is
5075 * enabled, but in practice it seems to have problems
5076 * when going from primary only to sprite only and vice
5077 * versa.
5078 */
5079 hsw_disable_ips(intel_crtc);
5080 }
5081
5082 /* FIXME get rid of this and use pre_plane_update */
5083 static void
5084 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5085 {
5086 struct drm_device *dev = crtc->dev;
5087 struct drm_i915_private *dev_priv = to_i915(dev);
5088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5089 int pipe = intel_crtc->pipe;
5090
5091 intel_pre_disable_primary(crtc);
5092
5093 /*
5094 * Vblank time updates from the shadow to live plane control register
5095 * are blocked if the memory self-refresh mode is active at that
5096 * moment. So to make sure the plane gets truly disabled, disable
5097 * first the self-refresh mode. The self-refresh enable bit in turn
5098 * will be checked/applied by the HW only at the next frame start
5099 * event which is after the vblank start event, so we need to have a
5100 * wait-for-vblank between disabling the plane and the pipe.
5101 */
5102 if (HAS_GMCH_DISPLAY(dev_priv) &&
5103 intel_set_memory_cxsr(dev_priv, false))
5104 intel_wait_for_vblank(dev_priv, pipe);
5105 }
5106
5107 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5108 {
5109 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5110 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5111 struct intel_crtc_state *pipe_config =
5112 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5113 crtc);
5114 struct drm_plane *primary = crtc->base.primary;
5115 struct drm_plane_state *old_pri_state =
5116 drm_atomic_get_existing_plane_state(old_state, primary);
5117
5118 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5119
5120 if (pipe_config->update_wm_post && pipe_config->base.active)
5121 intel_update_watermarks(crtc);
5122
5123 if (old_pri_state) {
5124 struct intel_plane_state *primary_state =
5125 intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5126 to_intel_plane(primary));
5127 struct intel_plane_state *old_primary_state =
5128 to_intel_plane_state(old_pri_state);
5129
5130 intel_fbc_post_update(crtc);
5131
5132 if (primary_state->base.visible &&
5133 (needs_modeset(&pipe_config->base) ||
5134 !old_primary_state->base.visible))
5135 intel_post_enable_primary(&crtc->base);
5136 }
5137 }
5138
5139 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5140 struct intel_crtc_state *pipe_config)
5141 {
5142 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5143 struct drm_device *dev = crtc->base.dev;
5144 struct drm_i915_private *dev_priv = to_i915(dev);
5145 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5146 struct drm_plane *primary = crtc->base.primary;
5147 struct drm_plane_state *old_pri_state =
5148 drm_atomic_get_existing_plane_state(old_state, primary);
5149 bool modeset = needs_modeset(&pipe_config->base);
5150 struct intel_atomic_state *old_intel_state =
5151 to_intel_atomic_state(old_state);
5152
5153 if (old_pri_state) {
5154 struct intel_plane_state *primary_state =
5155 intel_atomic_get_new_plane_state(old_intel_state,
5156 to_intel_plane(primary));
5157 struct intel_plane_state *old_primary_state =
5158 to_intel_plane_state(old_pri_state);
5159
5160 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5161
5162 if (old_primary_state->base.visible &&
5163 (modeset || !primary_state->base.visible))
5164 intel_pre_disable_primary(&crtc->base);
5165 }
5166
5167 /*
5168 * Vblank time updates from the shadow to live plane control register
5169 * are blocked if the memory self-refresh mode is active at that
5170 * moment. So to make sure the plane gets truly disabled, disable
5171 * first the self-refresh mode. The self-refresh enable bit in turn
5172 * will be checked/applied by the HW only at the next frame start
5173 * event which is after the vblank start event, so we need to have a
5174 * wait-for-vblank between disabling the plane and the pipe.
5175 */
5176 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5177 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5178 intel_wait_for_vblank(dev_priv, crtc->pipe);
5179
5180 /*
5181 * IVB workaround: must disable low power watermarks for at least
5182 * one frame before enabling scaling. LP watermarks can be re-enabled
5183 * when scaling is disabled.
5184 *
5185 * WaCxSRDisabledForSpriteScaling:ivb
5186 */
5187 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5188 intel_wait_for_vblank(dev_priv, crtc->pipe);
5189
5190 /*
5191 * If we're doing a modeset, we're done. No need to do any pre-vblank
5192 * watermark programming here.
5193 */
5194 if (needs_modeset(&pipe_config->base))
5195 return;
5196
5197 /*
5198 * For platforms that support atomic watermarks, program the
5199 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5200 * will be the intermediate values that are safe for both pre- and
5201 * post- vblank; when vblank happens, the 'active' values will be set
5202 * to the final 'target' values and we'll do this again to get the
5203 * optimal watermarks. For gen9+ platforms, the values we program here
5204 * will be the final target values which will get automatically latched
5205 * at vblank time; no further programming will be necessary.
5206 *
5207 * If a platform hasn't been transitioned to atomic watermarks yet,
5208 * we'll continue to update watermarks the old way, if flags tell
5209 * us to.
5210 */
5211 if (dev_priv->display.initial_watermarks != NULL)
5212 dev_priv->display.initial_watermarks(old_intel_state,
5213 pipe_config);
5214 else if (pipe_config->update_wm_pre)
5215 intel_update_watermarks(crtc);
5216 }
5217
5218 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5219 {
5220 struct drm_device *dev = crtc->dev;
5221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5222 struct drm_plane *p;
5223 int pipe = intel_crtc->pipe;
5224
5225 intel_crtc_dpms_overlay_disable(intel_crtc);
5226
5227 drm_for_each_plane_mask(p, dev, plane_mask)
5228 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5229
5230 /*
5231 * FIXME: Once we grow proper nuclear flip support out of this we need
5232 * to compute the mask of flip planes precisely. For the time being
5233 * consider this a flip to a NULL plane.
5234 */
5235 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5236 }
5237
5238 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5239 struct intel_crtc_state *crtc_state,
5240 struct drm_atomic_state *old_state)
5241 {
5242 struct drm_connector_state *conn_state;
5243 struct drm_connector *conn;
5244 int i;
5245
5246 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5247 struct intel_encoder *encoder =
5248 to_intel_encoder(conn_state->best_encoder);
5249
5250 if (conn_state->crtc != crtc)
5251 continue;
5252
5253 if (encoder->pre_pll_enable)
5254 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5255 }
5256 }
5257
5258 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5259 struct intel_crtc_state *crtc_state,
5260 struct drm_atomic_state *old_state)
5261 {
5262 struct drm_connector_state *conn_state;
5263 struct drm_connector *conn;
5264 int i;
5265
5266 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5267 struct intel_encoder *encoder =
5268 to_intel_encoder(conn_state->best_encoder);
5269
5270 if (conn_state->crtc != crtc)
5271 continue;
5272
5273 if (encoder->pre_enable)
5274 encoder->pre_enable(encoder, crtc_state, conn_state);
5275 }
5276 }
5277
5278 static void intel_encoders_enable(struct drm_crtc *crtc,
5279 struct intel_crtc_state *crtc_state,
5280 struct drm_atomic_state *old_state)
5281 {
5282 struct drm_connector_state *conn_state;
5283 struct drm_connector *conn;
5284 int i;
5285
5286 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5287 struct intel_encoder *encoder =
5288 to_intel_encoder(conn_state->best_encoder);
5289
5290 if (conn_state->crtc != crtc)
5291 continue;
5292
5293 encoder->enable(encoder, crtc_state, conn_state);
5294 intel_opregion_notify_encoder(encoder, true);
5295 }
5296 }
5297
5298 static void intel_encoders_disable(struct drm_crtc *crtc,
5299 struct intel_crtc_state *old_crtc_state,
5300 struct drm_atomic_state *old_state)
5301 {
5302 struct drm_connector_state *old_conn_state;
5303 struct drm_connector *conn;
5304 int i;
5305
5306 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5307 struct intel_encoder *encoder =
5308 to_intel_encoder(old_conn_state->best_encoder);
5309
5310 if (old_conn_state->crtc != crtc)
5311 continue;
5312
5313 intel_opregion_notify_encoder(encoder, false);
5314 encoder->disable(encoder, old_crtc_state, old_conn_state);
5315 }
5316 }
5317
5318 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5319 struct intel_crtc_state *old_crtc_state,
5320 struct drm_atomic_state *old_state)
5321 {
5322 struct drm_connector_state *old_conn_state;
5323 struct drm_connector *conn;
5324 int i;
5325
5326 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5327 struct intel_encoder *encoder =
5328 to_intel_encoder(old_conn_state->best_encoder);
5329
5330 if (old_conn_state->crtc != crtc)
5331 continue;
5332
5333 if (encoder->post_disable)
5334 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5335 }
5336 }
5337
5338 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5339 struct intel_crtc_state *old_crtc_state,
5340 struct drm_atomic_state *old_state)
5341 {
5342 struct drm_connector_state *old_conn_state;
5343 struct drm_connector *conn;
5344 int i;
5345
5346 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5347 struct intel_encoder *encoder =
5348 to_intel_encoder(old_conn_state->best_encoder);
5349
5350 if (old_conn_state->crtc != crtc)
5351 continue;
5352
5353 if (encoder->post_pll_disable)
5354 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5355 }
5356 }
5357
5358 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5359 struct drm_atomic_state *old_state)
5360 {
5361 struct drm_crtc *crtc = pipe_config->base.crtc;
5362 struct drm_device *dev = crtc->dev;
5363 struct drm_i915_private *dev_priv = to_i915(dev);
5364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5365 int pipe = intel_crtc->pipe;
5366 struct intel_atomic_state *old_intel_state =
5367 to_intel_atomic_state(old_state);
5368
5369 if (WARN_ON(intel_crtc->active))
5370 return;
5371
5372 /*
5373 * Sometimes spurious CPU pipe underruns happen during FDI
5374 * training, at least with VGA+HDMI cloning. Suppress them.
5375 *
5376 * On ILK we get an occasional spurious CPU pipe underruns
5377 * between eDP port A enable and vdd enable. Also PCH port
5378 * enable seems to result in the occasional CPU pipe underrun.
5379 *
5380 * Spurious PCH underruns also occur during PCH enabling.
5381 */
5382 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5383 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5384 if (intel_crtc->config->has_pch_encoder)
5385 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5386
5387 if (intel_crtc->config->has_pch_encoder)
5388 intel_prepare_shared_dpll(intel_crtc);
5389
5390 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5391 intel_dp_set_m_n(intel_crtc, M1_N1);
5392
5393 intel_set_pipe_timings(intel_crtc);
5394 intel_set_pipe_src_size(intel_crtc);
5395
5396 if (intel_crtc->config->has_pch_encoder) {
5397 intel_cpu_transcoder_set_m_n(intel_crtc,
5398 &intel_crtc->config->fdi_m_n, NULL);
5399 }
5400
5401 ironlake_set_pipeconf(crtc);
5402
5403 intel_crtc->active = true;
5404
5405 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5406
5407 if (intel_crtc->config->has_pch_encoder) {
5408 /* Note: FDI PLL enabling _must_ be done before we enable the
5409 * cpu pipes, hence this is separate from all the other fdi/pch
5410 * enabling. */
5411 ironlake_fdi_pll_enable(intel_crtc);
5412 } else {
5413 assert_fdi_tx_disabled(dev_priv, pipe);
5414 assert_fdi_rx_disabled(dev_priv, pipe);
5415 }
5416
5417 ironlake_pfit_enable(intel_crtc);
5418
5419 /*
5420 * On ILK+ LUT must be loaded before the pipe is running but with
5421 * clocks enabled
5422 */
5423 intel_color_load_luts(&pipe_config->base);
5424
5425 if (dev_priv->display.initial_watermarks != NULL)
5426 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5427 intel_enable_pipe(intel_crtc);
5428
5429 if (intel_crtc->config->has_pch_encoder)
5430 ironlake_pch_enable(pipe_config);
5431
5432 assert_vblank_disabled(crtc);
5433 drm_crtc_vblank_on(crtc);
5434
5435 intel_encoders_enable(crtc, pipe_config, old_state);
5436
5437 if (HAS_PCH_CPT(dev_priv))
5438 cpt_verify_modeset(dev, intel_crtc->pipe);
5439
5440 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5441 if (intel_crtc->config->has_pch_encoder)
5442 intel_wait_for_vblank(dev_priv, pipe);
5443 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5444 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5445 }
5446
5447 /* IPS only exists on ULT machines and is tied to pipe A. */
5448 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5449 {
5450 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5451 }
5452
5453 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5454 enum pipe pipe, bool apply)
5455 {
5456 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5457 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5458
5459 if (apply)
5460 val |= mask;
5461 else
5462 val &= ~mask;
5463
5464 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5465 }
5466
5467 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5468 struct drm_atomic_state *old_state)
5469 {
5470 struct drm_crtc *crtc = pipe_config->base.crtc;
5471 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5473 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5474 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5475 struct intel_atomic_state *old_intel_state =
5476 to_intel_atomic_state(old_state);
5477 bool psl_clkgate_wa;
5478
5479 if (WARN_ON(intel_crtc->active))
5480 return;
5481
5482 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5483
5484 if (intel_crtc->config->shared_dpll)
5485 intel_enable_shared_dpll(intel_crtc);
5486
5487 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5488 intel_dp_set_m_n(intel_crtc, M1_N1);
5489
5490 if (!transcoder_is_dsi(cpu_transcoder))
5491 intel_set_pipe_timings(intel_crtc);
5492
5493 intel_set_pipe_src_size(intel_crtc);
5494
5495 if (cpu_transcoder != TRANSCODER_EDP &&
5496 !transcoder_is_dsi(cpu_transcoder)) {
5497 I915_WRITE(PIPE_MULT(cpu_transcoder),
5498 intel_crtc->config->pixel_multiplier - 1);
5499 }
5500
5501 if (intel_crtc->config->has_pch_encoder) {
5502 intel_cpu_transcoder_set_m_n(intel_crtc,
5503 &intel_crtc->config->fdi_m_n, NULL);
5504 }
5505
5506 if (!transcoder_is_dsi(cpu_transcoder))
5507 haswell_set_pipeconf(crtc);
5508
5509 haswell_set_pipemisc(crtc);
5510
5511 intel_color_set_csc(&pipe_config->base);
5512
5513 intel_crtc->active = true;
5514
5515 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5516
5517 if (!transcoder_is_dsi(cpu_transcoder))
5518 intel_ddi_enable_pipe_clock(pipe_config);
5519
5520 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5521 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5522 intel_crtc->config->pch_pfit.enabled;
5523 if (psl_clkgate_wa)
5524 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5525
5526 if (INTEL_GEN(dev_priv) >= 9)
5527 skylake_pfit_enable(intel_crtc);
5528 else
5529 ironlake_pfit_enable(intel_crtc);
5530
5531 /*
5532 * On ILK+ LUT must be loaded before the pipe is running but with
5533 * clocks enabled
5534 */
5535 intel_color_load_luts(&pipe_config->base);
5536
5537 intel_ddi_set_pipe_settings(pipe_config);
5538 if (!transcoder_is_dsi(cpu_transcoder))
5539 intel_ddi_enable_transcoder_func(pipe_config);
5540
5541 if (dev_priv->display.initial_watermarks != NULL)
5542 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5543
5544 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5545 if (!transcoder_is_dsi(cpu_transcoder))
5546 intel_enable_pipe(intel_crtc);
5547
5548 if (intel_crtc->config->has_pch_encoder)
5549 lpt_pch_enable(pipe_config);
5550
5551 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5552 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5553
5554 assert_vblank_disabled(crtc);
5555 drm_crtc_vblank_on(crtc);
5556
5557 intel_encoders_enable(crtc, pipe_config, old_state);
5558
5559 if (psl_clkgate_wa) {
5560 intel_wait_for_vblank(dev_priv, pipe);
5561 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5562 }
5563
5564 /* If we change the relative order between pipe/planes enabling, we need
5565 * to change the workaround. */
5566 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5567 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5568 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5569 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5570 }
5571 }
5572
5573 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5574 {
5575 struct drm_device *dev = crtc->base.dev;
5576 struct drm_i915_private *dev_priv = to_i915(dev);
5577 int pipe = crtc->pipe;
5578
5579 /* To avoid upsetting the power well on haswell only disable the pfit if
5580 * it's in use. The hw state code will make sure we get this right. */
5581 if (force || crtc->config->pch_pfit.enabled) {
5582 I915_WRITE(PF_CTL(pipe), 0);
5583 I915_WRITE(PF_WIN_POS(pipe), 0);
5584 I915_WRITE(PF_WIN_SZ(pipe), 0);
5585 }
5586 }
5587
5588 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5589 struct drm_atomic_state *old_state)
5590 {
5591 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5592 struct drm_device *dev = crtc->dev;
5593 struct drm_i915_private *dev_priv = to_i915(dev);
5594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5595 int pipe = intel_crtc->pipe;
5596
5597 /*
5598 * Sometimes spurious CPU pipe underruns happen when the
5599 * pipe is already disabled, but FDI RX/TX is still enabled.
5600 * Happens at least with VGA+HDMI cloning. Suppress them.
5601 */
5602 if (intel_crtc->config->has_pch_encoder) {
5603 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5604 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5605 }
5606
5607 intel_encoders_disable(crtc, old_crtc_state, old_state);
5608
5609 drm_crtc_vblank_off(crtc);
5610 assert_vblank_disabled(crtc);
5611
5612 intel_disable_pipe(intel_crtc);
5613
5614 ironlake_pfit_disable(intel_crtc, false);
5615
5616 if (intel_crtc->config->has_pch_encoder)
5617 ironlake_fdi_disable(crtc);
5618
5619 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5620
5621 if (intel_crtc->config->has_pch_encoder) {
5622 ironlake_disable_pch_transcoder(dev_priv, pipe);
5623
5624 if (HAS_PCH_CPT(dev_priv)) {
5625 i915_reg_t reg;
5626 u32 temp;
5627
5628 /* disable TRANS_DP_CTL */
5629 reg = TRANS_DP_CTL(pipe);
5630 temp = I915_READ(reg);
5631 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5632 TRANS_DP_PORT_SEL_MASK);
5633 temp |= TRANS_DP_PORT_SEL_NONE;
5634 I915_WRITE(reg, temp);
5635
5636 /* disable DPLL_SEL */
5637 temp = I915_READ(PCH_DPLL_SEL);
5638 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5639 I915_WRITE(PCH_DPLL_SEL, temp);
5640 }
5641
5642 ironlake_fdi_pll_disable(intel_crtc);
5643 }
5644
5645 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5646 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5647 }
5648
5649 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5650 struct drm_atomic_state *old_state)
5651 {
5652 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5653 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5655 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5656
5657 intel_encoders_disable(crtc, old_crtc_state, old_state);
5658
5659 drm_crtc_vblank_off(crtc);
5660 assert_vblank_disabled(crtc);
5661
5662 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5663 if (!transcoder_is_dsi(cpu_transcoder))
5664 intel_disable_pipe(intel_crtc);
5665
5666 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5667 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5668
5669 if (!transcoder_is_dsi(cpu_transcoder))
5670 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5671
5672 if (INTEL_GEN(dev_priv) >= 9)
5673 skylake_scaler_disable(intel_crtc);
5674 else
5675 ironlake_pfit_disable(intel_crtc, false);
5676
5677 if (!transcoder_is_dsi(cpu_transcoder))
5678 intel_ddi_disable_pipe_clock(intel_crtc->config);
5679
5680 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5681 }
5682
5683 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5684 {
5685 struct drm_device *dev = crtc->base.dev;
5686 struct drm_i915_private *dev_priv = to_i915(dev);
5687 struct intel_crtc_state *pipe_config = crtc->config;
5688
5689 if (!pipe_config->gmch_pfit.control)
5690 return;
5691
5692 /*
5693 * The panel fitter should only be adjusted whilst the pipe is disabled,
5694 * according to register description and PRM.
5695 */
5696 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5697 assert_pipe_disabled(dev_priv, crtc->pipe);
5698
5699 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5700 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5701
5702 /* Border color in case we don't scale up to the full screen. Black by
5703 * default, change to something else for debugging. */
5704 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5705 }
5706
5707 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5708 {
5709 switch (port) {
5710 case PORT_A:
5711 return POWER_DOMAIN_PORT_DDI_A_LANES;
5712 case PORT_B:
5713 return POWER_DOMAIN_PORT_DDI_B_LANES;
5714 case PORT_C:
5715 return POWER_DOMAIN_PORT_DDI_C_LANES;
5716 case PORT_D:
5717 return POWER_DOMAIN_PORT_DDI_D_LANES;
5718 case PORT_E:
5719 return POWER_DOMAIN_PORT_DDI_E_LANES;
5720 default:
5721 MISSING_CASE(port);
5722 return POWER_DOMAIN_PORT_OTHER;
5723 }
5724 }
5725
5726 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5727 struct intel_crtc_state *crtc_state)
5728 {
5729 struct drm_device *dev = crtc->dev;
5730 struct drm_i915_private *dev_priv = to_i915(dev);
5731 struct drm_encoder *encoder;
5732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5733 enum pipe pipe = intel_crtc->pipe;
5734 u64 mask;
5735 enum transcoder transcoder = crtc_state->cpu_transcoder;
5736
5737 if (!crtc_state->base.active)
5738 return 0;
5739
5740 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5741 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5742 if (crtc_state->pch_pfit.enabled ||
5743 crtc_state->pch_pfit.force_thru)
5744 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5745
5746 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5747 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5748
5749 mask |= BIT_ULL(intel_encoder->power_domain);
5750 }
5751
5752 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5753 mask |= BIT(POWER_DOMAIN_AUDIO);
5754
5755 if (crtc_state->shared_dpll)
5756 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5757
5758 return mask;
5759 }
5760
5761 static u64
5762 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5763 struct intel_crtc_state *crtc_state)
5764 {
5765 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5767 enum intel_display_power_domain domain;
5768 u64 domains, new_domains, old_domains;
5769
5770 old_domains = intel_crtc->enabled_power_domains;
5771 intel_crtc->enabled_power_domains = new_domains =
5772 get_crtc_power_domains(crtc, crtc_state);
5773
5774 domains = new_domains & ~old_domains;
5775
5776 for_each_power_domain(domain, domains)
5777 intel_display_power_get(dev_priv, domain);
5778
5779 return old_domains & ~new_domains;
5780 }
5781
5782 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5783 u64 domains)
5784 {
5785 enum intel_display_power_domain domain;
5786
5787 for_each_power_domain(domain, domains)
5788 intel_display_power_put(dev_priv, domain);
5789 }
5790
5791 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5792 struct drm_atomic_state *old_state)
5793 {
5794 struct intel_atomic_state *old_intel_state =
5795 to_intel_atomic_state(old_state);
5796 struct drm_crtc *crtc = pipe_config->base.crtc;
5797 struct drm_device *dev = crtc->dev;
5798 struct drm_i915_private *dev_priv = to_i915(dev);
5799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5800 int pipe = intel_crtc->pipe;
5801
5802 if (WARN_ON(intel_crtc->active))
5803 return;
5804
5805 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5806 intel_dp_set_m_n(intel_crtc, M1_N1);
5807
5808 intel_set_pipe_timings(intel_crtc);
5809 intel_set_pipe_src_size(intel_crtc);
5810
5811 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5812 struct drm_i915_private *dev_priv = to_i915(dev);
5813
5814 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5815 I915_WRITE(CHV_CANVAS(pipe), 0);
5816 }
5817
5818 i9xx_set_pipeconf(intel_crtc);
5819
5820 intel_crtc->active = true;
5821
5822 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5823
5824 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5825
5826 if (IS_CHERRYVIEW(dev_priv)) {
5827 chv_prepare_pll(intel_crtc, intel_crtc->config);
5828 chv_enable_pll(intel_crtc, intel_crtc->config);
5829 } else {
5830 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5831 vlv_enable_pll(intel_crtc, intel_crtc->config);
5832 }
5833
5834 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5835
5836 i9xx_pfit_enable(intel_crtc);
5837
5838 intel_color_load_luts(&pipe_config->base);
5839
5840 dev_priv->display.initial_watermarks(old_intel_state,
5841 pipe_config);
5842 intel_enable_pipe(intel_crtc);
5843
5844 assert_vblank_disabled(crtc);
5845 drm_crtc_vblank_on(crtc);
5846
5847 intel_encoders_enable(crtc, pipe_config, old_state);
5848 }
5849
5850 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5851 {
5852 struct drm_device *dev = crtc->base.dev;
5853 struct drm_i915_private *dev_priv = to_i915(dev);
5854
5855 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5856 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5857 }
5858
5859 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5860 struct drm_atomic_state *old_state)
5861 {
5862 struct intel_atomic_state *old_intel_state =
5863 to_intel_atomic_state(old_state);
5864 struct drm_crtc *crtc = pipe_config->base.crtc;
5865 struct drm_device *dev = crtc->dev;
5866 struct drm_i915_private *dev_priv = to_i915(dev);
5867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5868 enum pipe pipe = intel_crtc->pipe;
5869
5870 if (WARN_ON(intel_crtc->active))
5871 return;
5872
5873 i9xx_set_pll_dividers(intel_crtc);
5874
5875 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5876 intel_dp_set_m_n(intel_crtc, M1_N1);
5877
5878 intel_set_pipe_timings(intel_crtc);
5879 intel_set_pipe_src_size(intel_crtc);
5880
5881 i9xx_set_pipeconf(intel_crtc);
5882
5883 intel_crtc->active = true;
5884
5885 if (!IS_GEN2(dev_priv))
5886 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5887
5888 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5889
5890 i9xx_enable_pll(intel_crtc, pipe_config);
5891
5892 i9xx_pfit_enable(intel_crtc);
5893
5894 intel_color_load_luts(&pipe_config->base);
5895
5896 if (dev_priv->display.initial_watermarks != NULL)
5897 dev_priv->display.initial_watermarks(old_intel_state,
5898 intel_crtc->config);
5899 else
5900 intel_update_watermarks(intel_crtc);
5901 intel_enable_pipe(intel_crtc);
5902
5903 assert_vblank_disabled(crtc);
5904 drm_crtc_vblank_on(crtc);
5905
5906 intel_encoders_enable(crtc, pipe_config, old_state);
5907 }
5908
5909 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5910 {
5911 struct drm_device *dev = crtc->base.dev;
5912 struct drm_i915_private *dev_priv = to_i915(dev);
5913
5914 if (!crtc->config->gmch_pfit.control)
5915 return;
5916
5917 assert_pipe_disabled(dev_priv, crtc->pipe);
5918
5919 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5920 I915_READ(PFIT_CONTROL));
5921 I915_WRITE(PFIT_CONTROL, 0);
5922 }
5923
5924 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5925 struct drm_atomic_state *old_state)
5926 {
5927 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5928 struct drm_device *dev = crtc->dev;
5929 struct drm_i915_private *dev_priv = to_i915(dev);
5930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5931 int pipe = intel_crtc->pipe;
5932
5933 /*
5934 * On gen2 planes are double buffered but the pipe isn't, so we must
5935 * wait for planes to fully turn off before disabling the pipe.
5936 */
5937 if (IS_GEN2(dev_priv))
5938 intel_wait_for_vblank(dev_priv, pipe);
5939
5940 intel_encoders_disable(crtc, old_crtc_state, old_state);
5941
5942 drm_crtc_vblank_off(crtc);
5943 assert_vblank_disabled(crtc);
5944
5945 intel_disable_pipe(intel_crtc);
5946
5947 i9xx_pfit_disable(intel_crtc);
5948
5949 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5950
5951 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5952 if (IS_CHERRYVIEW(dev_priv))
5953 chv_disable_pll(dev_priv, pipe);
5954 else if (IS_VALLEYVIEW(dev_priv))
5955 vlv_disable_pll(dev_priv, pipe);
5956 else
5957 i9xx_disable_pll(intel_crtc);
5958 }
5959
5960 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5961
5962 if (!IS_GEN2(dev_priv))
5963 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5964
5965 if (!dev_priv->display.initial_watermarks)
5966 intel_update_watermarks(intel_crtc);
5967
5968 /* clock the pipe down to 640x480@60 to potentially save power */
5969 if (IS_I830(dev_priv))
5970 i830_enable_pipe(dev_priv, pipe);
5971 }
5972
5973 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5974 struct drm_modeset_acquire_ctx *ctx)
5975 {
5976 struct intel_encoder *encoder;
5977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5978 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5979 enum intel_display_power_domain domain;
5980 u64 domains;
5981 struct drm_atomic_state *state;
5982 struct intel_crtc_state *crtc_state;
5983 int ret;
5984
5985 if (!intel_crtc->active)
5986 return;
5987
5988 if (crtc->primary->state->visible) {
5989 intel_pre_disable_primary_noatomic(crtc);
5990
5991 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5992 crtc->primary->state->visible = false;
5993 }
5994
5995 state = drm_atomic_state_alloc(crtc->dev);
5996 if (!state) {
5997 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5998 crtc->base.id, crtc->name);
5999 return;
6000 }
6001
6002 state->acquire_ctx = ctx;
6003
6004 /* Everything's already locked, -EDEADLK can't happen. */
6005 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6006 ret = drm_atomic_add_affected_connectors(state, crtc);
6007
6008 WARN_ON(IS_ERR(crtc_state) || ret);
6009
6010 dev_priv->display.crtc_disable(crtc_state, state);
6011
6012 drm_atomic_state_put(state);
6013
6014 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6015 crtc->base.id, crtc->name);
6016
6017 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6018 crtc->state->active = false;
6019 intel_crtc->active = false;
6020 crtc->enabled = false;
6021 crtc->state->connector_mask = 0;
6022 crtc->state->encoder_mask = 0;
6023
6024 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6025 encoder->base.crtc = NULL;
6026
6027 intel_fbc_disable(intel_crtc);
6028 intel_update_watermarks(intel_crtc);
6029 intel_disable_shared_dpll(intel_crtc);
6030
6031 domains = intel_crtc->enabled_power_domains;
6032 for_each_power_domain(domain, domains)
6033 intel_display_power_put(dev_priv, domain);
6034 intel_crtc->enabled_power_domains = 0;
6035
6036 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6037 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6038 }
6039
6040 /*
6041 * turn all crtc's off, but do not adjust state
6042 * This has to be paired with a call to intel_modeset_setup_hw_state.
6043 */
6044 int intel_display_suspend(struct drm_device *dev)
6045 {
6046 struct drm_i915_private *dev_priv = to_i915(dev);
6047 struct drm_atomic_state *state;
6048 int ret;
6049
6050 state = drm_atomic_helper_suspend(dev);
6051 ret = PTR_ERR_OR_ZERO(state);
6052 if (ret)
6053 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6054 else
6055 dev_priv->modeset_restore_state = state;
6056 return ret;
6057 }
6058
6059 void intel_encoder_destroy(struct drm_encoder *encoder)
6060 {
6061 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6062
6063 drm_encoder_cleanup(encoder);
6064 kfree(intel_encoder);
6065 }
6066
6067 /* Cross check the actual hw state with our own modeset state tracking (and it's
6068 * internal consistency). */
6069 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6070 struct drm_connector_state *conn_state)
6071 {
6072 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6073
6074 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6075 connector->base.base.id,
6076 connector->base.name);
6077
6078 if (connector->get_hw_state(connector)) {
6079 struct intel_encoder *encoder = connector->encoder;
6080
6081 I915_STATE_WARN(!crtc_state,
6082 "connector enabled without attached crtc\n");
6083
6084 if (!crtc_state)
6085 return;
6086
6087 I915_STATE_WARN(!crtc_state->active,
6088 "connector is active, but attached crtc isn't\n");
6089
6090 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6091 return;
6092
6093 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6094 "atomic encoder doesn't match attached encoder\n");
6095
6096 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6097 "attached encoder crtc differs from connector crtc\n");
6098 } else {
6099 I915_STATE_WARN(crtc_state && crtc_state->active,
6100 "attached crtc is active, but connector isn't\n");
6101 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6102 "best encoder set without crtc!\n");
6103 }
6104 }
6105
6106 int intel_connector_init(struct intel_connector *connector)
6107 {
6108 struct intel_digital_connector_state *conn_state;
6109
6110 /*
6111 * Allocate enough memory to hold intel_digital_connector_state,
6112 * This might be a few bytes too many, but for connectors that don't
6113 * need it we'll free the state and allocate a smaller one on the first
6114 * succesful commit anyway.
6115 */
6116 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6117 if (!conn_state)
6118 return -ENOMEM;
6119
6120 __drm_atomic_helper_connector_reset(&connector->base,
6121 &conn_state->base);
6122
6123 return 0;
6124 }
6125
6126 struct intel_connector *intel_connector_alloc(void)
6127 {
6128 struct intel_connector *connector;
6129
6130 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6131 if (!connector)
6132 return NULL;
6133
6134 if (intel_connector_init(connector) < 0) {
6135 kfree(connector);
6136 return NULL;
6137 }
6138
6139 return connector;
6140 }
6141
6142 /* Simple connector->get_hw_state implementation for encoders that support only
6143 * one connector and no cloning and hence the encoder state determines the state
6144 * of the connector. */
6145 bool intel_connector_get_hw_state(struct intel_connector *connector)
6146 {
6147 enum pipe pipe = 0;
6148 struct intel_encoder *encoder = connector->encoder;
6149
6150 return encoder->get_hw_state(encoder, &pipe);
6151 }
6152
6153 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6154 {
6155 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6156 return crtc_state->fdi_lanes;
6157
6158 return 0;
6159 }
6160
6161 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6162 struct intel_crtc_state *pipe_config)
6163 {
6164 struct drm_i915_private *dev_priv = to_i915(dev);
6165 struct drm_atomic_state *state = pipe_config->base.state;
6166 struct intel_crtc *other_crtc;
6167 struct intel_crtc_state *other_crtc_state;
6168
6169 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6170 pipe_name(pipe), pipe_config->fdi_lanes);
6171 if (pipe_config->fdi_lanes > 4) {
6172 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6173 pipe_name(pipe), pipe_config->fdi_lanes);
6174 return -EINVAL;
6175 }
6176
6177 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6178 if (pipe_config->fdi_lanes > 2) {
6179 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6180 pipe_config->fdi_lanes);
6181 return -EINVAL;
6182 } else {
6183 return 0;
6184 }
6185 }
6186
6187 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6188 return 0;
6189
6190 /* Ivybridge 3 pipe is really complicated */
6191 switch (pipe) {
6192 case PIPE_A:
6193 return 0;
6194 case PIPE_B:
6195 if (pipe_config->fdi_lanes <= 2)
6196 return 0;
6197
6198 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6199 other_crtc_state =
6200 intel_atomic_get_crtc_state(state, other_crtc);
6201 if (IS_ERR(other_crtc_state))
6202 return PTR_ERR(other_crtc_state);
6203
6204 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6205 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6206 pipe_name(pipe), pipe_config->fdi_lanes);
6207 return -EINVAL;
6208 }
6209 return 0;
6210 case PIPE_C:
6211 if (pipe_config->fdi_lanes > 2) {
6212 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6213 pipe_name(pipe), pipe_config->fdi_lanes);
6214 return -EINVAL;
6215 }
6216
6217 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6218 other_crtc_state =
6219 intel_atomic_get_crtc_state(state, other_crtc);
6220 if (IS_ERR(other_crtc_state))
6221 return PTR_ERR(other_crtc_state);
6222
6223 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6224 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6225 return -EINVAL;
6226 }
6227 return 0;
6228 default:
6229 BUG();
6230 }
6231 }
6232
6233 #define RETRY 1
6234 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6235 struct intel_crtc_state *pipe_config)
6236 {
6237 struct drm_device *dev = intel_crtc->base.dev;
6238 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6239 int lane, link_bw, fdi_dotclock, ret;
6240 bool needs_recompute = false;
6241
6242 retry:
6243 /* FDI is a binary signal running at ~2.7GHz, encoding
6244 * each output octet as 10 bits. The actual frequency
6245 * is stored as a divider into a 100MHz clock, and the
6246 * mode pixel clock is stored in units of 1KHz.
6247 * Hence the bw of each lane in terms of the mode signal
6248 * is:
6249 */
6250 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6251
6252 fdi_dotclock = adjusted_mode->crtc_clock;
6253
6254 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6255 pipe_config->pipe_bpp);
6256
6257 pipe_config->fdi_lanes = lane;
6258
6259 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6260 link_bw, &pipe_config->fdi_m_n, false);
6261
6262 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6263 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6264 pipe_config->pipe_bpp -= 2*3;
6265 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6266 pipe_config->pipe_bpp);
6267 needs_recompute = true;
6268 pipe_config->bw_constrained = true;
6269
6270 goto retry;
6271 }
6272
6273 if (needs_recompute)
6274 return RETRY;
6275
6276 return ret;
6277 }
6278
6279 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6280 struct intel_crtc_state *pipe_config)
6281 {
6282 if (pipe_config->ips_force_disable)
6283 return false;
6284
6285 if (pipe_config->pipe_bpp > 24)
6286 return false;
6287
6288 /* HSW can handle pixel rate up to cdclk? */
6289 if (IS_HASWELL(dev_priv))
6290 return true;
6291
6292 /*
6293 * We compare against max which means we must take
6294 * the increased cdclk requirement into account when
6295 * calculating the new cdclk.
6296 *
6297 * Should measure whether using a lower cdclk w/o IPS
6298 */
6299 return pipe_config->pixel_rate <=
6300 dev_priv->max_cdclk_freq * 95 / 100;
6301 }
6302
6303 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6304 struct intel_crtc_state *pipe_config)
6305 {
6306 struct drm_device *dev = crtc->base.dev;
6307 struct drm_i915_private *dev_priv = to_i915(dev);
6308
6309 pipe_config->ips_enabled = i915_modparams.enable_ips &&
6310 hsw_crtc_supports_ips(crtc) &&
6311 pipe_config_supports_ips(dev_priv, pipe_config);
6312 }
6313
6314 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6315 {
6316 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6317
6318 /* GDG double wide on either pipe, otherwise pipe A only */
6319 return INTEL_INFO(dev_priv)->gen < 4 &&
6320 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6321 }
6322
6323 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6324 {
6325 uint32_t pixel_rate;
6326
6327 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6328
6329 /*
6330 * We only use IF-ID interlacing. If we ever use
6331 * PF-ID we'll need to adjust the pixel_rate here.
6332 */
6333
6334 if (pipe_config->pch_pfit.enabled) {
6335 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6336 uint32_t pfit_size = pipe_config->pch_pfit.size;
6337
6338 pipe_w = pipe_config->pipe_src_w;
6339 pipe_h = pipe_config->pipe_src_h;
6340
6341 pfit_w = (pfit_size >> 16) & 0xFFFF;
6342 pfit_h = pfit_size & 0xFFFF;
6343 if (pipe_w < pfit_w)
6344 pipe_w = pfit_w;
6345 if (pipe_h < pfit_h)
6346 pipe_h = pfit_h;
6347
6348 if (WARN_ON(!pfit_w || !pfit_h))
6349 return pixel_rate;
6350
6351 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6352 pfit_w * pfit_h);
6353 }
6354
6355 return pixel_rate;
6356 }
6357
6358 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6359 {
6360 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6361
6362 if (HAS_GMCH_DISPLAY(dev_priv))
6363 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6364 crtc_state->pixel_rate =
6365 crtc_state->base.adjusted_mode.crtc_clock;
6366 else
6367 crtc_state->pixel_rate =
6368 ilk_pipe_pixel_rate(crtc_state);
6369 }
6370
6371 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6372 struct intel_crtc_state *pipe_config)
6373 {
6374 struct drm_device *dev = crtc->base.dev;
6375 struct drm_i915_private *dev_priv = to_i915(dev);
6376 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6377 int clock_limit = dev_priv->max_dotclk_freq;
6378
6379 if (INTEL_GEN(dev_priv) < 4) {
6380 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6381
6382 /*
6383 * Enable double wide mode when the dot clock
6384 * is > 90% of the (display) core speed.
6385 */
6386 if (intel_crtc_supports_double_wide(crtc) &&
6387 adjusted_mode->crtc_clock > clock_limit) {
6388 clock_limit = dev_priv->max_dotclk_freq;
6389 pipe_config->double_wide = true;
6390 }
6391 }
6392
6393 if (adjusted_mode->crtc_clock > clock_limit) {
6394 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6395 adjusted_mode->crtc_clock, clock_limit,
6396 yesno(pipe_config->double_wide));
6397 return -EINVAL;
6398 }
6399
6400 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6401 /*
6402 * There is only one pipe CSC unit per pipe, and we need that
6403 * for output conversion from RGB->YCBCR. So if CTM is already
6404 * applied we can't support YCBCR420 output.
6405 */
6406 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6407 return -EINVAL;
6408 }
6409
6410 /*
6411 * Pipe horizontal size must be even in:
6412 * - DVO ganged mode
6413 * - LVDS dual channel mode
6414 * - Double wide pipe
6415 */
6416 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6417 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6418 pipe_config->pipe_src_w &= ~1;
6419
6420 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6421 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6422 */
6423 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6424 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6425 return -EINVAL;
6426
6427 intel_crtc_compute_pixel_rate(pipe_config);
6428
6429 if (HAS_IPS(dev_priv))
6430 hsw_compute_ips_config(crtc, pipe_config);
6431
6432 if (pipe_config->has_pch_encoder)
6433 return ironlake_fdi_compute_config(crtc, pipe_config);
6434
6435 return 0;
6436 }
6437
6438 static void
6439 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6440 {
6441 while (*num > DATA_LINK_M_N_MASK ||
6442 *den > DATA_LINK_M_N_MASK) {
6443 *num >>= 1;
6444 *den >>= 1;
6445 }
6446 }
6447
6448 static void compute_m_n(unsigned int m, unsigned int n,
6449 uint32_t *ret_m, uint32_t *ret_n,
6450 bool reduce_m_n)
6451 {
6452 /*
6453 * Reduce M/N as much as possible without loss in precision. Several DP
6454 * dongles in particular seem to be fussy about too large *link* M/N
6455 * values. The passed in values are more likely to have the least
6456 * significant bits zero than M after rounding below, so do this first.
6457 */
6458 if (reduce_m_n) {
6459 while ((m & 1) == 0 && (n & 1) == 0) {
6460 m >>= 1;
6461 n >>= 1;
6462 }
6463 }
6464
6465 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6466 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6467 intel_reduce_m_n_ratio(ret_m, ret_n);
6468 }
6469
6470 void
6471 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6472 int pixel_clock, int link_clock,
6473 struct intel_link_m_n *m_n,
6474 bool reduce_m_n)
6475 {
6476 m_n->tu = 64;
6477
6478 compute_m_n(bits_per_pixel * pixel_clock,
6479 link_clock * nlanes * 8,
6480 &m_n->gmch_m, &m_n->gmch_n,
6481 reduce_m_n);
6482
6483 compute_m_n(pixel_clock, link_clock,
6484 &m_n->link_m, &m_n->link_n,
6485 reduce_m_n);
6486 }
6487
6488 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6489 {
6490 if (i915_modparams.panel_use_ssc >= 0)
6491 return i915_modparams.panel_use_ssc != 0;
6492 return dev_priv->vbt.lvds_use_ssc
6493 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6494 }
6495
6496 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6497 {
6498 return (1 << dpll->n) << 16 | dpll->m2;
6499 }
6500
6501 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6502 {
6503 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6504 }
6505
6506 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6507 struct intel_crtc_state *crtc_state,
6508 struct dpll *reduced_clock)
6509 {
6510 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6511 u32 fp, fp2 = 0;
6512
6513 if (IS_PINEVIEW(dev_priv)) {
6514 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6515 if (reduced_clock)
6516 fp2 = pnv_dpll_compute_fp(reduced_clock);
6517 } else {
6518 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6519 if (reduced_clock)
6520 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6521 }
6522
6523 crtc_state->dpll_hw_state.fp0 = fp;
6524
6525 crtc->lowfreq_avail = false;
6526 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6527 reduced_clock) {
6528 crtc_state->dpll_hw_state.fp1 = fp2;
6529 crtc->lowfreq_avail = true;
6530 } else {
6531 crtc_state->dpll_hw_state.fp1 = fp;
6532 }
6533 }
6534
6535 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6536 pipe)
6537 {
6538 u32 reg_val;
6539
6540 /*
6541 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6542 * and set it to a reasonable value instead.
6543 */
6544 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6545 reg_val &= 0xffffff00;
6546 reg_val |= 0x00000030;
6547 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6548
6549 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6550 reg_val &= 0x00ffffff;
6551 reg_val |= 0x8c000000;
6552 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6553
6554 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6555 reg_val &= 0xffffff00;
6556 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6557
6558 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6559 reg_val &= 0x00ffffff;
6560 reg_val |= 0xb0000000;
6561 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6562 }
6563
6564 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6565 struct intel_link_m_n *m_n)
6566 {
6567 struct drm_device *dev = crtc->base.dev;
6568 struct drm_i915_private *dev_priv = to_i915(dev);
6569 int pipe = crtc->pipe;
6570
6571 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6572 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6573 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6574 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6575 }
6576
6577 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6578 struct intel_link_m_n *m_n,
6579 struct intel_link_m_n *m2_n2)
6580 {
6581 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6582 int pipe = crtc->pipe;
6583 enum transcoder transcoder = crtc->config->cpu_transcoder;
6584
6585 if (INTEL_GEN(dev_priv) >= 5) {
6586 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6587 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6588 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6589 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6590 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6591 * for gen < 8) and if DRRS is supported (to make sure the
6592 * registers are not unnecessarily accessed).
6593 */
6594 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6595 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6596 I915_WRITE(PIPE_DATA_M2(transcoder),
6597 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6598 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6599 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6600 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6601 }
6602 } else {
6603 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6604 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6605 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6606 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6607 }
6608 }
6609
6610 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6611 {
6612 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6613
6614 if (m_n == M1_N1) {
6615 dp_m_n = &crtc->config->dp_m_n;
6616 dp_m2_n2 = &crtc->config->dp_m2_n2;
6617 } else if (m_n == M2_N2) {
6618
6619 /*
6620 * M2_N2 registers are not supported. Hence m2_n2 divider value
6621 * needs to be programmed into M1_N1.
6622 */
6623 dp_m_n = &crtc->config->dp_m2_n2;
6624 } else {
6625 DRM_ERROR("Unsupported divider value\n");
6626 return;
6627 }
6628
6629 if (crtc->config->has_pch_encoder)
6630 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6631 else
6632 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6633 }
6634
6635 static void vlv_compute_dpll(struct intel_crtc *crtc,
6636 struct intel_crtc_state *pipe_config)
6637 {
6638 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6639 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6640 if (crtc->pipe != PIPE_A)
6641 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6642
6643 /* DPLL not used with DSI, but still need the rest set up */
6644 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6645 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6646 DPLL_EXT_BUFFER_ENABLE_VLV;
6647
6648 pipe_config->dpll_hw_state.dpll_md =
6649 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6650 }
6651
6652 static void chv_compute_dpll(struct intel_crtc *crtc,
6653 struct intel_crtc_state *pipe_config)
6654 {
6655 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6656 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6657 if (crtc->pipe != PIPE_A)
6658 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6659
6660 /* DPLL not used with DSI, but still need the rest set up */
6661 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6662 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6663
6664 pipe_config->dpll_hw_state.dpll_md =
6665 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6666 }
6667
6668 static void vlv_prepare_pll(struct intel_crtc *crtc,
6669 const struct intel_crtc_state *pipe_config)
6670 {
6671 struct drm_device *dev = crtc->base.dev;
6672 struct drm_i915_private *dev_priv = to_i915(dev);
6673 enum pipe pipe = crtc->pipe;
6674 u32 mdiv;
6675 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6676 u32 coreclk, reg_val;
6677
6678 /* Enable Refclk */
6679 I915_WRITE(DPLL(pipe),
6680 pipe_config->dpll_hw_state.dpll &
6681 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6682
6683 /* No need to actually set up the DPLL with DSI */
6684 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6685 return;
6686
6687 mutex_lock(&dev_priv->sb_lock);
6688
6689 bestn = pipe_config->dpll.n;
6690 bestm1 = pipe_config->dpll.m1;
6691 bestm2 = pipe_config->dpll.m2;
6692 bestp1 = pipe_config->dpll.p1;
6693 bestp2 = pipe_config->dpll.p2;
6694
6695 /* See eDP HDMI DPIO driver vbios notes doc */
6696
6697 /* PLL B needs special handling */
6698 if (pipe == PIPE_B)
6699 vlv_pllb_recal_opamp(dev_priv, pipe);
6700
6701 /* Set up Tx target for periodic Rcomp update */
6702 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6703
6704 /* Disable target IRef on PLL */
6705 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6706 reg_val &= 0x00ffffff;
6707 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6708
6709 /* Disable fast lock */
6710 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6711
6712 /* Set idtafcrecal before PLL is enabled */
6713 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6714 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6715 mdiv |= ((bestn << DPIO_N_SHIFT));
6716 mdiv |= (1 << DPIO_K_SHIFT);
6717
6718 /*
6719 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6720 * but we don't support that).
6721 * Note: don't use the DAC post divider as it seems unstable.
6722 */
6723 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6724 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6725
6726 mdiv |= DPIO_ENABLE_CALIBRATION;
6727 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6728
6729 /* Set HBR and RBR LPF coefficients */
6730 if (pipe_config->port_clock == 162000 ||
6731 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6732 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6733 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6734 0x009f0003);
6735 else
6736 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6737 0x00d0000f);
6738
6739 if (intel_crtc_has_dp_encoder(pipe_config)) {
6740 /* Use SSC source */
6741 if (pipe == PIPE_A)
6742 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6743 0x0df40000);
6744 else
6745 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6746 0x0df70000);
6747 } else { /* HDMI or VGA */
6748 /* Use bend source */
6749 if (pipe == PIPE_A)
6750 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6751 0x0df70000);
6752 else
6753 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6754 0x0df40000);
6755 }
6756
6757 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6758 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6759 if (intel_crtc_has_dp_encoder(crtc->config))
6760 coreclk |= 0x01000000;
6761 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6762
6763 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6764 mutex_unlock(&dev_priv->sb_lock);
6765 }
6766
6767 static void chv_prepare_pll(struct intel_crtc *crtc,
6768 const struct intel_crtc_state *pipe_config)
6769 {
6770 struct drm_device *dev = crtc->base.dev;
6771 struct drm_i915_private *dev_priv = to_i915(dev);
6772 enum pipe pipe = crtc->pipe;
6773 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6774 u32 loopfilter, tribuf_calcntr;
6775 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6776 u32 dpio_val;
6777 int vco;
6778
6779 /* Enable Refclk and SSC */
6780 I915_WRITE(DPLL(pipe),
6781 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6782
6783 /* No need to actually set up the DPLL with DSI */
6784 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6785 return;
6786
6787 bestn = pipe_config->dpll.n;
6788 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6789 bestm1 = pipe_config->dpll.m1;
6790 bestm2 = pipe_config->dpll.m2 >> 22;
6791 bestp1 = pipe_config->dpll.p1;
6792 bestp2 = pipe_config->dpll.p2;
6793 vco = pipe_config->dpll.vco;
6794 dpio_val = 0;
6795 loopfilter = 0;
6796
6797 mutex_lock(&dev_priv->sb_lock);
6798
6799 /* p1 and p2 divider */
6800 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6801 5 << DPIO_CHV_S1_DIV_SHIFT |
6802 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6803 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6804 1 << DPIO_CHV_K_DIV_SHIFT);
6805
6806 /* Feedback post-divider - m2 */
6807 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6808
6809 /* Feedback refclk divider - n and m1 */
6810 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6811 DPIO_CHV_M1_DIV_BY_2 |
6812 1 << DPIO_CHV_N_DIV_SHIFT);
6813
6814 /* M2 fraction division */
6815 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6816
6817 /* M2 fraction division enable */
6818 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6819 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6820 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6821 if (bestm2_frac)
6822 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6823 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6824
6825 /* Program digital lock detect threshold */
6826 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6827 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6828 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6829 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6830 if (!bestm2_frac)
6831 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6832 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6833
6834 /* Loop filter */
6835 if (vco == 5400000) {
6836 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6837 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6838 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6839 tribuf_calcntr = 0x9;
6840 } else if (vco <= 6200000) {
6841 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6842 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6843 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6844 tribuf_calcntr = 0x9;
6845 } else if (vco <= 6480000) {
6846 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6847 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6848 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6849 tribuf_calcntr = 0x8;
6850 } else {
6851 /* Not supported. Apply the same limits as in the max case */
6852 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6853 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6854 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6855 tribuf_calcntr = 0;
6856 }
6857 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6858
6859 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6860 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6861 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6862 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6863
6864 /* AFC Recal */
6865 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6866 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6867 DPIO_AFC_RECAL);
6868
6869 mutex_unlock(&dev_priv->sb_lock);
6870 }
6871
6872 /**
6873 * vlv_force_pll_on - forcibly enable just the PLL
6874 * @dev_priv: i915 private structure
6875 * @pipe: pipe PLL to enable
6876 * @dpll: PLL configuration
6877 *
6878 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6879 * in cases where we need the PLL enabled even when @pipe is not going to
6880 * be enabled.
6881 */
6882 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6883 const struct dpll *dpll)
6884 {
6885 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6886 struct intel_crtc_state *pipe_config;
6887
6888 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6889 if (!pipe_config)
6890 return -ENOMEM;
6891
6892 pipe_config->base.crtc = &crtc->base;
6893 pipe_config->pixel_multiplier = 1;
6894 pipe_config->dpll = *dpll;
6895
6896 if (IS_CHERRYVIEW(dev_priv)) {
6897 chv_compute_dpll(crtc, pipe_config);
6898 chv_prepare_pll(crtc, pipe_config);
6899 chv_enable_pll(crtc, pipe_config);
6900 } else {
6901 vlv_compute_dpll(crtc, pipe_config);
6902 vlv_prepare_pll(crtc, pipe_config);
6903 vlv_enable_pll(crtc, pipe_config);
6904 }
6905
6906 kfree(pipe_config);
6907
6908 return 0;
6909 }
6910
6911 /**
6912 * vlv_force_pll_off - forcibly disable just the PLL
6913 * @dev_priv: i915 private structure
6914 * @pipe: pipe PLL to disable
6915 *
6916 * Disable the PLL for @pipe. To be used in cases where we need
6917 * the PLL enabled even when @pipe is not going to be enabled.
6918 */
6919 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6920 {
6921 if (IS_CHERRYVIEW(dev_priv))
6922 chv_disable_pll(dev_priv, pipe);
6923 else
6924 vlv_disable_pll(dev_priv, pipe);
6925 }
6926
6927 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6928 struct intel_crtc_state *crtc_state,
6929 struct dpll *reduced_clock)
6930 {
6931 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6932 u32 dpll;
6933 struct dpll *clock = &crtc_state->dpll;
6934
6935 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6936
6937 dpll = DPLL_VGA_MODE_DIS;
6938
6939 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6940 dpll |= DPLLB_MODE_LVDS;
6941 else
6942 dpll |= DPLLB_MODE_DAC_SERIAL;
6943
6944 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6945 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6946 dpll |= (crtc_state->pixel_multiplier - 1)
6947 << SDVO_MULTIPLIER_SHIFT_HIRES;
6948 }
6949
6950 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6951 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6952 dpll |= DPLL_SDVO_HIGH_SPEED;
6953
6954 if (intel_crtc_has_dp_encoder(crtc_state))
6955 dpll |= DPLL_SDVO_HIGH_SPEED;
6956
6957 /* compute bitmask from p1 value */
6958 if (IS_PINEVIEW(dev_priv))
6959 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6960 else {
6961 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6962 if (IS_G4X(dev_priv) && reduced_clock)
6963 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6964 }
6965 switch (clock->p2) {
6966 case 5:
6967 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6968 break;
6969 case 7:
6970 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6971 break;
6972 case 10:
6973 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6974 break;
6975 case 14:
6976 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6977 break;
6978 }
6979 if (INTEL_GEN(dev_priv) >= 4)
6980 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6981
6982 if (crtc_state->sdvo_tv_clock)
6983 dpll |= PLL_REF_INPUT_TVCLKINBC;
6984 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6985 intel_panel_use_ssc(dev_priv))
6986 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6987 else
6988 dpll |= PLL_REF_INPUT_DREFCLK;
6989
6990 dpll |= DPLL_VCO_ENABLE;
6991 crtc_state->dpll_hw_state.dpll = dpll;
6992
6993 if (INTEL_GEN(dev_priv) >= 4) {
6994 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6995 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6996 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6997 }
6998 }
6999
7000 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7001 struct intel_crtc_state *crtc_state,
7002 struct dpll *reduced_clock)
7003 {
7004 struct drm_device *dev = crtc->base.dev;
7005 struct drm_i915_private *dev_priv = to_i915(dev);
7006 u32 dpll;
7007 struct dpll *clock = &crtc_state->dpll;
7008
7009 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7010
7011 dpll = DPLL_VGA_MODE_DIS;
7012
7013 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7014 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7015 } else {
7016 if (clock->p1 == 2)
7017 dpll |= PLL_P1_DIVIDE_BY_TWO;
7018 else
7019 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7020 if (clock->p2 == 4)
7021 dpll |= PLL_P2_DIVIDE_BY_4;
7022 }
7023
7024 if (!IS_I830(dev_priv) &&
7025 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7026 dpll |= DPLL_DVO_2X_MODE;
7027
7028 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7029 intel_panel_use_ssc(dev_priv))
7030 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7031 else
7032 dpll |= PLL_REF_INPUT_DREFCLK;
7033
7034 dpll |= DPLL_VCO_ENABLE;
7035 crtc_state->dpll_hw_state.dpll = dpll;
7036 }
7037
7038 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7039 {
7040 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7041 enum pipe pipe = intel_crtc->pipe;
7042 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7043 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7044 uint32_t crtc_vtotal, crtc_vblank_end;
7045 int vsyncshift = 0;
7046
7047 /* We need to be careful not to changed the adjusted mode, for otherwise
7048 * the hw state checker will get angry at the mismatch. */
7049 crtc_vtotal = adjusted_mode->crtc_vtotal;
7050 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7051
7052 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7053 /* the chip adds 2 halflines automatically */
7054 crtc_vtotal -= 1;
7055 crtc_vblank_end -= 1;
7056
7057 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7058 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7059 else
7060 vsyncshift = adjusted_mode->crtc_hsync_start -
7061 adjusted_mode->crtc_htotal / 2;
7062 if (vsyncshift < 0)
7063 vsyncshift += adjusted_mode->crtc_htotal;
7064 }
7065
7066 if (INTEL_GEN(dev_priv) > 3)
7067 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7068
7069 I915_WRITE(HTOTAL(cpu_transcoder),
7070 (adjusted_mode->crtc_hdisplay - 1) |
7071 ((adjusted_mode->crtc_htotal - 1) << 16));
7072 I915_WRITE(HBLANK(cpu_transcoder),
7073 (adjusted_mode->crtc_hblank_start - 1) |
7074 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7075 I915_WRITE(HSYNC(cpu_transcoder),
7076 (adjusted_mode->crtc_hsync_start - 1) |
7077 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7078
7079 I915_WRITE(VTOTAL(cpu_transcoder),
7080 (adjusted_mode->crtc_vdisplay - 1) |
7081 ((crtc_vtotal - 1) << 16));
7082 I915_WRITE(VBLANK(cpu_transcoder),
7083 (adjusted_mode->crtc_vblank_start - 1) |
7084 ((crtc_vblank_end - 1) << 16));
7085 I915_WRITE(VSYNC(cpu_transcoder),
7086 (adjusted_mode->crtc_vsync_start - 1) |
7087 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7088
7089 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7090 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7091 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7092 * bits. */
7093 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7094 (pipe == PIPE_B || pipe == PIPE_C))
7095 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7096
7097 }
7098
7099 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7100 {
7101 struct drm_device *dev = intel_crtc->base.dev;
7102 struct drm_i915_private *dev_priv = to_i915(dev);
7103 enum pipe pipe = intel_crtc->pipe;
7104
7105 /* pipesrc controls the size that is scaled from, which should
7106 * always be the user's requested size.
7107 */
7108 I915_WRITE(PIPESRC(pipe),
7109 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7110 (intel_crtc->config->pipe_src_h - 1));
7111 }
7112
7113 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7114 struct intel_crtc_state *pipe_config)
7115 {
7116 struct drm_device *dev = crtc->base.dev;
7117 struct drm_i915_private *dev_priv = to_i915(dev);
7118 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7119 uint32_t tmp;
7120
7121 tmp = I915_READ(HTOTAL(cpu_transcoder));
7122 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7123 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7124 tmp = I915_READ(HBLANK(cpu_transcoder));
7125 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7126 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7127 tmp = I915_READ(HSYNC(cpu_transcoder));
7128 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7129 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7130
7131 tmp = I915_READ(VTOTAL(cpu_transcoder));
7132 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7133 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7134 tmp = I915_READ(VBLANK(cpu_transcoder));
7135 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7136 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7137 tmp = I915_READ(VSYNC(cpu_transcoder));
7138 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7139 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7140
7141 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7142 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7143 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7144 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7145 }
7146 }
7147
7148 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7149 struct intel_crtc_state *pipe_config)
7150 {
7151 struct drm_device *dev = crtc->base.dev;
7152 struct drm_i915_private *dev_priv = to_i915(dev);
7153 u32 tmp;
7154
7155 tmp = I915_READ(PIPESRC(crtc->pipe));
7156 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7157 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7158
7159 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7160 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7161 }
7162
7163 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7164 struct intel_crtc_state *pipe_config)
7165 {
7166 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7167 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7168 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7169 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7170
7171 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7172 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7173 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7174 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7175
7176 mode->flags = pipe_config->base.adjusted_mode.flags;
7177 mode->type = DRM_MODE_TYPE_DRIVER;
7178
7179 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7180
7181 mode->hsync = drm_mode_hsync(mode);
7182 mode->vrefresh = drm_mode_vrefresh(mode);
7183 drm_mode_set_name(mode);
7184 }
7185
7186 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7187 {
7188 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7189 uint32_t pipeconf;
7190
7191 pipeconf = 0;
7192
7193 /* we keep both pipes enabled on 830 */
7194 if (IS_I830(dev_priv))
7195 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7196
7197 if (intel_crtc->config->double_wide)
7198 pipeconf |= PIPECONF_DOUBLE_WIDE;
7199
7200 /* only g4x and later have fancy bpc/dither controls */
7201 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7202 IS_CHERRYVIEW(dev_priv)) {
7203 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7204 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7205 pipeconf |= PIPECONF_DITHER_EN |
7206 PIPECONF_DITHER_TYPE_SP;
7207
7208 switch (intel_crtc->config->pipe_bpp) {
7209 case 18:
7210 pipeconf |= PIPECONF_6BPC;
7211 break;
7212 case 24:
7213 pipeconf |= PIPECONF_8BPC;
7214 break;
7215 case 30:
7216 pipeconf |= PIPECONF_10BPC;
7217 break;
7218 default:
7219 /* Case prevented by intel_choose_pipe_bpp_dither. */
7220 BUG();
7221 }
7222 }
7223
7224 if (HAS_PIPE_CXSR(dev_priv)) {
7225 if (intel_crtc->lowfreq_avail) {
7226 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7227 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7228 } else {
7229 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7230 }
7231 }
7232
7233 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7234 if (INTEL_GEN(dev_priv) < 4 ||
7235 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7236 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7237 else
7238 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7239 } else
7240 pipeconf |= PIPECONF_PROGRESSIVE;
7241
7242 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7243 intel_crtc->config->limited_color_range)
7244 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7245
7246 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7247 POSTING_READ(PIPECONF(intel_crtc->pipe));
7248 }
7249
7250 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7251 struct intel_crtc_state *crtc_state)
7252 {
7253 struct drm_device *dev = crtc->base.dev;
7254 struct drm_i915_private *dev_priv = to_i915(dev);
7255 const struct intel_limit *limit;
7256 int refclk = 48000;
7257
7258 memset(&crtc_state->dpll_hw_state, 0,
7259 sizeof(crtc_state->dpll_hw_state));
7260
7261 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7262 if (intel_panel_use_ssc(dev_priv)) {
7263 refclk = dev_priv->vbt.lvds_ssc_freq;
7264 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7265 }
7266
7267 limit = &intel_limits_i8xx_lvds;
7268 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7269 limit = &intel_limits_i8xx_dvo;
7270 } else {
7271 limit = &intel_limits_i8xx_dac;
7272 }
7273
7274 if (!crtc_state->clock_set &&
7275 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7276 refclk, NULL, &crtc_state->dpll)) {
7277 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7278 return -EINVAL;
7279 }
7280
7281 i8xx_compute_dpll(crtc, crtc_state, NULL);
7282
7283 return 0;
7284 }
7285
7286 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7287 struct intel_crtc_state *crtc_state)
7288 {
7289 struct drm_device *dev = crtc->base.dev;
7290 struct drm_i915_private *dev_priv = to_i915(dev);
7291 const struct intel_limit *limit;
7292 int refclk = 96000;
7293
7294 memset(&crtc_state->dpll_hw_state, 0,
7295 sizeof(crtc_state->dpll_hw_state));
7296
7297 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7298 if (intel_panel_use_ssc(dev_priv)) {
7299 refclk = dev_priv->vbt.lvds_ssc_freq;
7300 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7301 }
7302
7303 if (intel_is_dual_link_lvds(dev))
7304 limit = &intel_limits_g4x_dual_channel_lvds;
7305 else
7306 limit = &intel_limits_g4x_single_channel_lvds;
7307 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7308 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7309 limit = &intel_limits_g4x_hdmi;
7310 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7311 limit = &intel_limits_g4x_sdvo;
7312 } else {
7313 /* The option is for other outputs */
7314 limit = &intel_limits_i9xx_sdvo;
7315 }
7316
7317 if (!crtc_state->clock_set &&
7318 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7319 refclk, NULL, &crtc_state->dpll)) {
7320 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7321 return -EINVAL;
7322 }
7323
7324 i9xx_compute_dpll(crtc, crtc_state, NULL);
7325
7326 return 0;
7327 }
7328
7329 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7330 struct intel_crtc_state *crtc_state)
7331 {
7332 struct drm_device *dev = crtc->base.dev;
7333 struct drm_i915_private *dev_priv = to_i915(dev);
7334 const struct intel_limit *limit;
7335 int refclk = 96000;
7336
7337 memset(&crtc_state->dpll_hw_state, 0,
7338 sizeof(crtc_state->dpll_hw_state));
7339
7340 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7341 if (intel_panel_use_ssc(dev_priv)) {
7342 refclk = dev_priv->vbt.lvds_ssc_freq;
7343 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7344 }
7345
7346 limit = &intel_limits_pineview_lvds;
7347 } else {
7348 limit = &intel_limits_pineview_sdvo;
7349 }
7350
7351 if (!crtc_state->clock_set &&
7352 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7353 refclk, NULL, &crtc_state->dpll)) {
7354 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7355 return -EINVAL;
7356 }
7357
7358 i9xx_compute_dpll(crtc, crtc_state, NULL);
7359
7360 return 0;
7361 }
7362
7363 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7364 struct intel_crtc_state *crtc_state)
7365 {
7366 struct drm_device *dev = crtc->base.dev;
7367 struct drm_i915_private *dev_priv = to_i915(dev);
7368 const struct intel_limit *limit;
7369 int refclk = 96000;
7370
7371 memset(&crtc_state->dpll_hw_state, 0,
7372 sizeof(crtc_state->dpll_hw_state));
7373
7374 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7375 if (intel_panel_use_ssc(dev_priv)) {
7376 refclk = dev_priv->vbt.lvds_ssc_freq;
7377 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7378 }
7379
7380 limit = &intel_limits_i9xx_lvds;
7381 } else {
7382 limit = &intel_limits_i9xx_sdvo;
7383 }
7384
7385 if (!crtc_state->clock_set &&
7386 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7387 refclk, NULL, &crtc_state->dpll)) {
7388 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7389 return -EINVAL;
7390 }
7391
7392 i9xx_compute_dpll(crtc, crtc_state, NULL);
7393
7394 return 0;
7395 }
7396
7397 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7398 struct intel_crtc_state *crtc_state)
7399 {
7400 int refclk = 100000;
7401 const struct intel_limit *limit = &intel_limits_chv;
7402
7403 memset(&crtc_state->dpll_hw_state, 0,
7404 sizeof(crtc_state->dpll_hw_state));
7405
7406 if (!crtc_state->clock_set &&
7407 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7408 refclk, NULL, &crtc_state->dpll)) {
7409 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7410 return -EINVAL;
7411 }
7412
7413 chv_compute_dpll(crtc, crtc_state);
7414
7415 return 0;
7416 }
7417
7418 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7419 struct intel_crtc_state *crtc_state)
7420 {
7421 int refclk = 100000;
7422 const struct intel_limit *limit = &intel_limits_vlv;
7423
7424 memset(&crtc_state->dpll_hw_state, 0,
7425 sizeof(crtc_state->dpll_hw_state));
7426
7427 if (!crtc_state->clock_set &&
7428 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7429 refclk, NULL, &crtc_state->dpll)) {
7430 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7431 return -EINVAL;
7432 }
7433
7434 vlv_compute_dpll(crtc, crtc_state);
7435
7436 return 0;
7437 }
7438
7439 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7440 struct intel_crtc_state *pipe_config)
7441 {
7442 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7443 uint32_t tmp;
7444
7445 if (INTEL_GEN(dev_priv) <= 3 &&
7446 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7447 return;
7448
7449 tmp = I915_READ(PFIT_CONTROL);
7450 if (!(tmp & PFIT_ENABLE))
7451 return;
7452
7453 /* Check whether the pfit is attached to our pipe. */
7454 if (INTEL_GEN(dev_priv) < 4) {
7455 if (crtc->pipe != PIPE_B)
7456 return;
7457 } else {
7458 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7459 return;
7460 }
7461
7462 pipe_config->gmch_pfit.control = tmp;
7463 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7464 }
7465
7466 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7467 struct intel_crtc_state *pipe_config)
7468 {
7469 struct drm_device *dev = crtc->base.dev;
7470 struct drm_i915_private *dev_priv = to_i915(dev);
7471 int pipe = pipe_config->cpu_transcoder;
7472 struct dpll clock;
7473 u32 mdiv;
7474 int refclk = 100000;
7475
7476 /* In case of DSI, DPLL will not be used */
7477 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7478 return;
7479
7480 mutex_lock(&dev_priv->sb_lock);
7481 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7482 mutex_unlock(&dev_priv->sb_lock);
7483
7484 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7485 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7486 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7487 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7488 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7489
7490 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7491 }
7492
7493 static void
7494 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7495 struct intel_initial_plane_config *plane_config)
7496 {
7497 struct drm_device *dev = crtc->base.dev;
7498 struct drm_i915_private *dev_priv = to_i915(dev);
7499 u32 val, base, offset;
7500 int pipe = crtc->pipe, plane = crtc->plane;
7501 int fourcc, pixel_format;
7502 unsigned int aligned_height;
7503 struct drm_framebuffer *fb;
7504 struct intel_framebuffer *intel_fb;
7505
7506 val = I915_READ(DSPCNTR(plane));
7507 if (!(val & DISPLAY_PLANE_ENABLE))
7508 return;
7509
7510 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7511 if (!intel_fb) {
7512 DRM_DEBUG_KMS("failed to alloc fb\n");
7513 return;
7514 }
7515
7516 fb = &intel_fb->base;
7517
7518 fb->dev = dev;
7519
7520 if (INTEL_GEN(dev_priv) >= 4) {
7521 if (val & DISPPLANE_TILED) {
7522 plane_config->tiling = I915_TILING_X;
7523 fb->modifier = I915_FORMAT_MOD_X_TILED;
7524 }
7525 }
7526
7527 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7528 fourcc = i9xx_format_to_fourcc(pixel_format);
7529 fb->format = drm_format_info(fourcc);
7530
7531 if (INTEL_GEN(dev_priv) >= 4) {
7532 if (plane_config->tiling)
7533 offset = I915_READ(DSPTILEOFF(plane));
7534 else
7535 offset = I915_READ(DSPLINOFF(plane));
7536 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7537 } else {
7538 base = I915_READ(DSPADDR(plane));
7539 }
7540 plane_config->base = base;
7541
7542 val = I915_READ(PIPESRC(pipe));
7543 fb->width = ((val >> 16) & 0xfff) + 1;
7544 fb->height = ((val >> 0) & 0xfff) + 1;
7545
7546 val = I915_READ(DSPSTRIDE(pipe));
7547 fb->pitches[0] = val & 0xffffffc0;
7548
7549 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7550
7551 plane_config->size = fb->pitches[0] * aligned_height;
7552
7553 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7554 pipe_name(pipe), plane, fb->width, fb->height,
7555 fb->format->cpp[0] * 8, base, fb->pitches[0],
7556 plane_config->size);
7557
7558 plane_config->fb = intel_fb;
7559 }
7560
7561 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7562 struct intel_crtc_state *pipe_config)
7563 {
7564 struct drm_device *dev = crtc->base.dev;
7565 struct drm_i915_private *dev_priv = to_i915(dev);
7566 int pipe = pipe_config->cpu_transcoder;
7567 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7568 struct dpll clock;
7569 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7570 int refclk = 100000;
7571
7572 /* In case of DSI, DPLL will not be used */
7573 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7574 return;
7575
7576 mutex_lock(&dev_priv->sb_lock);
7577 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7578 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7579 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7580 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7581 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7582 mutex_unlock(&dev_priv->sb_lock);
7583
7584 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7585 clock.m2 = (pll_dw0 & 0xff) << 22;
7586 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7587 clock.m2 |= pll_dw2 & 0x3fffff;
7588 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7589 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7590 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7591
7592 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7593 }
7594
7595 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7596 struct intel_crtc_state *pipe_config)
7597 {
7598 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7599 enum intel_display_power_domain power_domain;
7600 uint32_t tmp;
7601 bool ret;
7602
7603 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7604 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7605 return false;
7606
7607 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7608 pipe_config->shared_dpll = NULL;
7609
7610 ret = false;
7611
7612 tmp = I915_READ(PIPECONF(crtc->pipe));
7613 if (!(tmp & PIPECONF_ENABLE))
7614 goto out;
7615
7616 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7617 IS_CHERRYVIEW(dev_priv)) {
7618 switch (tmp & PIPECONF_BPC_MASK) {
7619 case PIPECONF_6BPC:
7620 pipe_config->pipe_bpp = 18;
7621 break;
7622 case PIPECONF_8BPC:
7623 pipe_config->pipe_bpp = 24;
7624 break;
7625 case PIPECONF_10BPC:
7626 pipe_config->pipe_bpp = 30;
7627 break;
7628 default:
7629 break;
7630 }
7631 }
7632
7633 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7634 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7635 pipe_config->limited_color_range = true;
7636
7637 if (INTEL_GEN(dev_priv) < 4)
7638 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7639
7640 intel_get_pipe_timings(crtc, pipe_config);
7641 intel_get_pipe_src_size(crtc, pipe_config);
7642
7643 i9xx_get_pfit_config(crtc, pipe_config);
7644
7645 if (INTEL_GEN(dev_priv) >= 4) {
7646 /* No way to read it out on pipes B and C */
7647 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7648 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7649 else
7650 tmp = I915_READ(DPLL_MD(crtc->pipe));
7651 pipe_config->pixel_multiplier =
7652 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7653 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7654 pipe_config->dpll_hw_state.dpll_md = tmp;
7655 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7656 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7657 tmp = I915_READ(DPLL(crtc->pipe));
7658 pipe_config->pixel_multiplier =
7659 ((tmp & SDVO_MULTIPLIER_MASK)
7660 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7661 } else {
7662 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7663 * port and will be fixed up in the encoder->get_config
7664 * function. */
7665 pipe_config->pixel_multiplier = 1;
7666 }
7667 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7668 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7669 /*
7670 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7671 * on 830. Filter it out here so that we don't
7672 * report errors due to that.
7673 */
7674 if (IS_I830(dev_priv))
7675 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7676
7677 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7678 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7679 } else {
7680 /* Mask out read-only status bits. */
7681 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7682 DPLL_PORTC_READY_MASK |
7683 DPLL_PORTB_READY_MASK);
7684 }
7685
7686 if (IS_CHERRYVIEW(dev_priv))
7687 chv_crtc_clock_get(crtc, pipe_config);
7688 else if (IS_VALLEYVIEW(dev_priv))
7689 vlv_crtc_clock_get(crtc, pipe_config);
7690 else
7691 i9xx_crtc_clock_get(crtc, pipe_config);
7692
7693 /*
7694 * Normally the dotclock is filled in by the encoder .get_config()
7695 * but in case the pipe is enabled w/o any ports we need a sane
7696 * default.
7697 */
7698 pipe_config->base.adjusted_mode.crtc_clock =
7699 pipe_config->port_clock / pipe_config->pixel_multiplier;
7700
7701 ret = true;
7702
7703 out:
7704 intel_display_power_put(dev_priv, power_domain);
7705
7706 return ret;
7707 }
7708
7709 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7710 {
7711 struct intel_encoder *encoder;
7712 int i;
7713 u32 val, final;
7714 bool has_lvds = false;
7715 bool has_cpu_edp = false;
7716 bool has_panel = false;
7717 bool has_ck505 = false;
7718 bool can_ssc = false;
7719 bool using_ssc_source = false;
7720
7721 /* We need to take the global config into account */
7722 for_each_intel_encoder(&dev_priv->drm, encoder) {
7723 switch (encoder->type) {
7724 case INTEL_OUTPUT_LVDS:
7725 has_panel = true;
7726 has_lvds = true;
7727 break;
7728 case INTEL_OUTPUT_EDP:
7729 has_panel = true;
7730 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7731 has_cpu_edp = true;
7732 break;
7733 default:
7734 break;
7735 }
7736 }
7737
7738 if (HAS_PCH_IBX(dev_priv)) {
7739 has_ck505 = dev_priv->vbt.display_clock_mode;
7740 can_ssc = has_ck505;
7741 } else {
7742 has_ck505 = false;
7743 can_ssc = true;
7744 }
7745
7746 /* Check if any DPLLs are using the SSC source */
7747 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7748 u32 temp = I915_READ(PCH_DPLL(i));
7749
7750 if (!(temp & DPLL_VCO_ENABLE))
7751 continue;
7752
7753 if ((temp & PLL_REF_INPUT_MASK) ==
7754 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7755 using_ssc_source = true;
7756 break;
7757 }
7758 }
7759
7760 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7761 has_panel, has_lvds, has_ck505, using_ssc_source);
7762
7763 /* Ironlake: try to setup display ref clock before DPLL
7764 * enabling. This is only under driver's control after
7765 * PCH B stepping, previous chipset stepping should be
7766 * ignoring this setting.
7767 */
7768 val = I915_READ(PCH_DREF_CONTROL);
7769
7770 /* As we must carefully and slowly disable/enable each source in turn,
7771 * compute the final state we want first and check if we need to
7772 * make any changes at all.
7773 */
7774 final = val;
7775 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7776 if (has_ck505)
7777 final |= DREF_NONSPREAD_CK505_ENABLE;
7778 else
7779 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7780
7781 final &= ~DREF_SSC_SOURCE_MASK;
7782 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7783 final &= ~DREF_SSC1_ENABLE;
7784
7785 if (has_panel) {
7786 final |= DREF_SSC_SOURCE_ENABLE;
7787
7788 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7789 final |= DREF_SSC1_ENABLE;
7790
7791 if (has_cpu_edp) {
7792 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7793 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7794 else
7795 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7796 } else
7797 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7798 } else if (using_ssc_source) {
7799 final |= DREF_SSC_SOURCE_ENABLE;
7800 final |= DREF_SSC1_ENABLE;
7801 }
7802
7803 if (final == val)
7804 return;
7805
7806 /* Always enable nonspread source */
7807 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7808
7809 if (has_ck505)
7810 val |= DREF_NONSPREAD_CK505_ENABLE;
7811 else
7812 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7813
7814 if (has_panel) {
7815 val &= ~DREF_SSC_SOURCE_MASK;
7816 val |= DREF_SSC_SOURCE_ENABLE;
7817
7818 /* SSC must be turned on before enabling the CPU output */
7819 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7820 DRM_DEBUG_KMS("Using SSC on panel\n");
7821 val |= DREF_SSC1_ENABLE;
7822 } else
7823 val &= ~DREF_SSC1_ENABLE;
7824
7825 /* Get SSC going before enabling the outputs */
7826 I915_WRITE(PCH_DREF_CONTROL, val);
7827 POSTING_READ(PCH_DREF_CONTROL);
7828 udelay(200);
7829
7830 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7831
7832 /* Enable CPU source on CPU attached eDP */
7833 if (has_cpu_edp) {
7834 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7835 DRM_DEBUG_KMS("Using SSC on eDP\n");
7836 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7837 } else
7838 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7839 } else
7840 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7841
7842 I915_WRITE(PCH_DREF_CONTROL, val);
7843 POSTING_READ(PCH_DREF_CONTROL);
7844 udelay(200);
7845 } else {
7846 DRM_DEBUG_KMS("Disabling CPU source output\n");
7847
7848 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7849
7850 /* Turn off CPU output */
7851 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7852
7853 I915_WRITE(PCH_DREF_CONTROL, val);
7854 POSTING_READ(PCH_DREF_CONTROL);
7855 udelay(200);
7856
7857 if (!using_ssc_source) {
7858 DRM_DEBUG_KMS("Disabling SSC source\n");
7859
7860 /* Turn off the SSC source */
7861 val &= ~DREF_SSC_SOURCE_MASK;
7862 val |= DREF_SSC_SOURCE_DISABLE;
7863
7864 /* Turn off SSC1 */
7865 val &= ~DREF_SSC1_ENABLE;
7866
7867 I915_WRITE(PCH_DREF_CONTROL, val);
7868 POSTING_READ(PCH_DREF_CONTROL);
7869 udelay(200);
7870 }
7871 }
7872
7873 BUG_ON(val != final);
7874 }
7875
7876 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7877 {
7878 uint32_t tmp;
7879
7880 tmp = I915_READ(SOUTH_CHICKEN2);
7881 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7882 I915_WRITE(SOUTH_CHICKEN2, tmp);
7883
7884 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7885 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7886 DRM_ERROR("FDI mPHY reset assert timeout\n");
7887
7888 tmp = I915_READ(SOUTH_CHICKEN2);
7889 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7890 I915_WRITE(SOUTH_CHICKEN2, tmp);
7891
7892 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7893 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7894 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7895 }
7896
7897 /* WaMPhyProgramming:hsw */
7898 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7899 {
7900 uint32_t tmp;
7901
7902 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7903 tmp &= ~(0xFF << 24);
7904 tmp |= (0x12 << 24);
7905 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7906
7907 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7908 tmp |= (1 << 11);
7909 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7910
7911 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7912 tmp |= (1 << 11);
7913 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7914
7915 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7916 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7917 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7918
7919 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7920 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7921 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7922
7923 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7924 tmp &= ~(7 << 13);
7925 tmp |= (5 << 13);
7926 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7927
7928 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7929 tmp &= ~(7 << 13);
7930 tmp |= (5 << 13);
7931 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7932
7933 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7934 tmp &= ~0xFF;
7935 tmp |= 0x1C;
7936 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7937
7938 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7939 tmp &= ~0xFF;
7940 tmp |= 0x1C;
7941 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7942
7943 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7944 tmp &= ~(0xFF << 16);
7945 tmp |= (0x1C << 16);
7946 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7947
7948 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7949 tmp &= ~(0xFF << 16);
7950 tmp |= (0x1C << 16);
7951 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7952
7953 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7954 tmp |= (1 << 27);
7955 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7956
7957 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7958 tmp |= (1 << 27);
7959 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7960
7961 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7962 tmp &= ~(0xF << 28);
7963 tmp |= (4 << 28);
7964 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7965
7966 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7967 tmp &= ~(0xF << 28);
7968 tmp |= (4 << 28);
7969 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7970 }
7971
7972 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7973 * Programming" based on the parameters passed:
7974 * - Sequence to enable CLKOUT_DP
7975 * - Sequence to enable CLKOUT_DP without spread
7976 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7977 */
7978 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7979 bool with_spread, bool with_fdi)
7980 {
7981 uint32_t reg, tmp;
7982
7983 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7984 with_spread = true;
7985 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7986 with_fdi, "LP PCH doesn't have FDI\n"))
7987 with_fdi = false;
7988
7989 mutex_lock(&dev_priv->sb_lock);
7990
7991 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7992 tmp &= ~SBI_SSCCTL_DISABLE;
7993 tmp |= SBI_SSCCTL_PATHALT;
7994 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7995
7996 udelay(24);
7997
7998 if (with_spread) {
7999 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8000 tmp &= ~SBI_SSCCTL_PATHALT;
8001 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8002
8003 if (with_fdi) {
8004 lpt_reset_fdi_mphy(dev_priv);
8005 lpt_program_fdi_mphy(dev_priv);
8006 }
8007 }
8008
8009 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8010 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8011 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8012 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8013
8014 mutex_unlock(&dev_priv->sb_lock);
8015 }
8016
8017 /* Sequence to disable CLKOUT_DP */
8018 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8019 {
8020 uint32_t reg, tmp;
8021
8022 mutex_lock(&dev_priv->sb_lock);
8023
8024 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8025 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8026 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8027 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8028
8029 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8030 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8031 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8032 tmp |= SBI_SSCCTL_PATHALT;
8033 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8034 udelay(32);
8035 }
8036 tmp |= SBI_SSCCTL_DISABLE;
8037 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8038 }
8039
8040 mutex_unlock(&dev_priv->sb_lock);
8041 }
8042
8043 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8044
8045 static const uint16_t sscdivintphase[] = {
8046 [BEND_IDX( 50)] = 0x3B23,
8047 [BEND_IDX( 45)] = 0x3B23,
8048 [BEND_IDX( 40)] = 0x3C23,
8049 [BEND_IDX( 35)] = 0x3C23,
8050 [BEND_IDX( 30)] = 0x3D23,
8051 [BEND_IDX( 25)] = 0x3D23,
8052 [BEND_IDX( 20)] = 0x3E23,
8053 [BEND_IDX( 15)] = 0x3E23,
8054 [BEND_IDX( 10)] = 0x3F23,
8055 [BEND_IDX( 5)] = 0x3F23,
8056 [BEND_IDX( 0)] = 0x0025,
8057 [BEND_IDX( -5)] = 0x0025,
8058 [BEND_IDX(-10)] = 0x0125,
8059 [BEND_IDX(-15)] = 0x0125,
8060 [BEND_IDX(-20)] = 0x0225,
8061 [BEND_IDX(-25)] = 0x0225,
8062 [BEND_IDX(-30)] = 0x0325,
8063 [BEND_IDX(-35)] = 0x0325,
8064 [BEND_IDX(-40)] = 0x0425,
8065 [BEND_IDX(-45)] = 0x0425,
8066 [BEND_IDX(-50)] = 0x0525,
8067 };
8068
8069 /*
8070 * Bend CLKOUT_DP
8071 * steps -50 to 50 inclusive, in steps of 5
8072 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8073 * change in clock period = -(steps / 10) * 5.787 ps
8074 */
8075 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8076 {
8077 uint32_t tmp;
8078 int idx = BEND_IDX(steps);
8079
8080 if (WARN_ON(steps % 5 != 0))
8081 return;
8082
8083 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8084 return;
8085
8086 mutex_lock(&dev_priv->sb_lock);
8087
8088 if (steps % 10 != 0)
8089 tmp = 0xAAAAAAAB;
8090 else
8091 tmp = 0x00000000;
8092 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8093
8094 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8095 tmp &= 0xffff0000;
8096 tmp |= sscdivintphase[idx];
8097 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8098
8099 mutex_unlock(&dev_priv->sb_lock);
8100 }
8101
8102 #undef BEND_IDX
8103
8104 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8105 {
8106 struct intel_encoder *encoder;
8107 bool has_vga = false;
8108
8109 for_each_intel_encoder(&dev_priv->drm, encoder) {
8110 switch (encoder->type) {
8111 case INTEL_OUTPUT_ANALOG:
8112 has_vga = true;
8113 break;
8114 default:
8115 break;
8116 }
8117 }
8118
8119 if (has_vga) {
8120 lpt_bend_clkout_dp(dev_priv, 0);
8121 lpt_enable_clkout_dp(dev_priv, true, true);
8122 } else {
8123 lpt_disable_clkout_dp(dev_priv);
8124 }
8125 }
8126
8127 /*
8128 * Initialize reference clocks when the driver loads
8129 */
8130 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8131 {
8132 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8133 ironlake_init_pch_refclk(dev_priv);
8134 else if (HAS_PCH_LPT(dev_priv))
8135 lpt_init_pch_refclk(dev_priv);
8136 }
8137
8138 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8139 {
8140 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8142 int pipe = intel_crtc->pipe;
8143 uint32_t val;
8144
8145 val = 0;
8146
8147 switch (intel_crtc->config->pipe_bpp) {
8148 case 18:
8149 val |= PIPECONF_6BPC;
8150 break;
8151 case 24:
8152 val |= PIPECONF_8BPC;
8153 break;
8154 case 30:
8155 val |= PIPECONF_10BPC;
8156 break;
8157 case 36:
8158 val |= PIPECONF_12BPC;
8159 break;
8160 default:
8161 /* Case prevented by intel_choose_pipe_bpp_dither. */
8162 BUG();
8163 }
8164
8165 if (intel_crtc->config->dither)
8166 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8167
8168 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8169 val |= PIPECONF_INTERLACED_ILK;
8170 else
8171 val |= PIPECONF_PROGRESSIVE;
8172
8173 if (intel_crtc->config->limited_color_range)
8174 val |= PIPECONF_COLOR_RANGE_SELECT;
8175
8176 I915_WRITE(PIPECONF(pipe), val);
8177 POSTING_READ(PIPECONF(pipe));
8178 }
8179
8180 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8181 {
8182 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8184 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8185 u32 val = 0;
8186
8187 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8188 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8189
8190 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8191 val |= PIPECONF_INTERLACED_ILK;
8192 else
8193 val |= PIPECONF_PROGRESSIVE;
8194
8195 I915_WRITE(PIPECONF(cpu_transcoder), val);
8196 POSTING_READ(PIPECONF(cpu_transcoder));
8197 }
8198
8199 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8200 {
8201 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8203 struct intel_crtc_state *config = intel_crtc->config;
8204
8205 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8206 u32 val = 0;
8207
8208 switch (intel_crtc->config->pipe_bpp) {
8209 case 18:
8210 val |= PIPEMISC_DITHER_6_BPC;
8211 break;
8212 case 24:
8213 val |= PIPEMISC_DITHER_8_BPC;
8214 break;
8215 case 30:
8216 val |= PIPEMISC_DITHER_10_BPC;
8217 break;
8218 case 36:
8219 val |= PIPEMISC_DITHER_12_BPC;
8220 break;
8221 default:
8222 /* Case prevented by pipe_config_set_bpp. */
8223 BUG();
8224 }
8225
8226 if (intel_crtc->config->dither)
8227 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8228
8229 if (config->ycbcr420) {
8230 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8231 PIPEMISC_YUV420_ENABLE |
8232 PIPEMISC_YUV420_MODE_FULL_BLEND;
8233 }
8234
8235 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8236 }
8237 }
8238
8239 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8240 {
8241 /*
8242 * Account for spread spectrum to avoid
8243 * oversubscribing the link. Max center spread
8244 * is 2.5%; use 5% for safety's sake.
8245 */
8246 u32 bps = target_clock * bpp * 21 / 20;
8247 return DIV_ROUND_UP(bps, link_bw * 8);
8248 }
8249
8250 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8251 {
8252 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8253 }
8254
8255 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8256 struct intel_crtc_state *crtc_state,
8257 struct dpll *reduced_clock)
8258 {
8259 struct drm_crtc *crtc = &intel_crtc->base;
8260 struct drm_device *dev = crtc->dev;
8261 struct drm_i915_private *dev_priv = to_i915(dev);
8262 u32 dpll, fp, fp2;
8263 int factor;
8264
8265 /* Enable autotuning of the PLL clock (if permissible) */
8266 factor = 21;
8267 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8268 if ((intel_panel_use_ssc(dev_priv) &&
8269 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8270 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8271 factor = 25;
8272 } else if (crtc_state->sdvo_tv_clock)
8273 factor = 20;
8274
8275 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8276
8277 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8278 fp |= FP_CB_TUNE;
8279
8280 if (reduced_clock) {
8281 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8282
8283 if (reduced_clock->m < factor * reduced_clock->n)
8284 fp2 |= FP_CB_TUNE;
8285 } else {
8286 fp2 = fp;
8287 }
8288
8289 dpll = 0;
8290
8291 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8292 dpll |= DPLLB_MODE_LVDS;
8293 else
8294 dpll |= DPLLB_MODE_DAC_SERIAL;
8295
8296 dpll |= (crtc_state->pixel_multiplier - 1)
8297 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8298
8299 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8300 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8301 dpll |= DPLL_SDVO_HIGH_SPEED;
8302
8303 if (intel_crtc_has_dp_encoder(crtc_state))
8304 dpll |= DPLL_SDVO_HIGH_SPEED;
8305
8306 /*
8307 * The high speed IO clock is only really required for
8308 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8309 * possible to share the DPLL between CRT and HDMI. Enabling
8310 * the clock needlessly does no real harm, except use up a
8311 * bit of power potentially.
8312 *
8313 * We'll limit this to IVB with 3 pipes, since it has only two
8314 * DPLLs and so DPLL sharing is the only way to get three pipes
8315 * driving PCH ports at the same time. On SNB we could do this,
8316 * and potentially avoid enabling the second DPLL, but it's not
8317 * clear if it''s a win or loss power wise. No point in doing
8318 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8319 */
8320 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8321 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8322 dpll |= DPLL_SDVO_HIGH_SPEED;
8323
8324 /* compute bitmask from p1 value */
8325 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8326 /* also FPA1 */
8327 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8328
8329 switch (crtc_state->dpll.p2) {
8330 case 5:
8331 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8332 break;
8333 case 7:
8334 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8335 break;
8336 case 10:
8337 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8338 break;
8339 case 14:
8340 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8341 break;
8342 }
8343
8344 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8345 intel_panel_use_ssc(dev_priv))
8346 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8347 else
8348 dpll |= PLL_REF_INPUT_DREFCLK;
8349
8350 dpll |= DPLL_VCO_ENABLE;
8351
8352 crtc_state->dpll_hw_state.dpll = dpll;
8353 crtc_state->dpll_hw_state.fp0 = fp;
8354 crtc_state->dpll_hw_state.fp1 = fp2;
8355 }
8356
8357 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8358 struct intel_crtc_state *crtc_state)
8359 {
8360 struct drm_device *dev = crtc->base.dev;
8361 struct drm_i915_private *dev_priv = to_i915(dev);
8362 const struct intel_limit *limit;
8363 int refclk = 120000;
8364
8365 memset(&crtc_state->dpll_hw_state, 0,
8366 sizeof(crtc_state->dpll_hw_state));
8367
8368 crtc->lowfreq_avail = false;
8369
8370 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8371 if (!crtc_state->has_pch_encoder)
8372 return 0;
8373
8374 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8375 if (intel_panel_use_ssc(dev_priv)) {
8376 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8377 dev_priv->vbt.lvds_ssc_freq);
8378 refclk = dev_priv->vbt.lvds_ssc_freq;
8379 }
8380
8381 if (intel_is_dual_link_lvds(dev)) {
8382 if (refclk == 100000)
8383 limit = &intel_limits_ironlake_dual_lvds_100m;
8384 else
8385 limit = &intel_limits_ironlake_dual_lvds;
8386 } else {
8387 if (refclk == 100000)
8388 limit = &intel_limits_ironlake_single_lvds_100m;
8389 else
8390 limit = &intel_limits_ironlake_single_lvds;
8391 }
8392 } else {
8393 limit = &intel_limits_ironlake_dac;
8394 }
8395
8396 if (!crtc_state->clock_set &&
8397 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8398 refclk, NULL, &crtc_state->dpll)) {
8399 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8400 return -EINVAL;
8401 }
8402
8403 ironlake_compute_dpll(crtc, crtc_state, NULL);
8404
8405 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8406 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8407 pipe_name(crtc->pipe));
8408 return -EINVAL;
8409 }
8410
8411 return 0;
8412 }
8413
8414 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8415 struct intel_link_m_n *m_n)
8416 {
8417 struct drm_device *dev = crtc->base.dev;
8418 struct drm_i915_private *dev_priv = to_i915(dev);
8419 enum pipe pipe = crtc->pipe;
8420
8421 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8422 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8423 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8424 & ~TU_SIZE_MASK;
8425 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8426 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8427 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8428 }
8429
8430 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8431 enum transcoder transcoder,
8432 struct intel_link_m_n *m_n,
8433 struct intel_link_m_n *m2_n2)
8434 {
8435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8436 enum pipe pipe = crtc->pipe;
8437
8438 if (INTEL_GEN(dev_priv) >= 5) {
8439 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8440 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8441 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8442 & ~TU_SIZE_MASK;
8443 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8444 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8445 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8446 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8447 * gen < 8) and if DRRS is supported (to make sure the
8448 * registers are not unnecessarily read).
8449 */
8450 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8451 crtc->config->has_drrs) {
8452 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8453 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8454 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8455 & ~TU_SIZE_MASK;
8456 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8457 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8458 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8459 }
8460 } else {
8461 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8462 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8463 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8464 & ~TU_SIZE_MASK;
8465 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8466 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8467 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8468 }
8469 }
8470
8471 void intel_dp_get_m_n(struct intel_crtc *crtc,
8472 struct intel_crtc_state *pipe_config)
8473 {
8474 if (pipe_config->has_pch_encoder)
8475 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8476 else
8477 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8478 &pipe_config->dp_m_n,
8479 &pipe_config->dp_m2_n2);
8480 }
8481
8482 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8483 struct intel_crtc_state *pipe_config)
8484 {
8485 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8486 &pipe_config->fdi_m_n, NULL);
8487 }
8488
8489 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8490 struct intel_crtc_state *pipe_config)
8491 {
8492 struct drm_device *dev = crtc->base.dev;
8493 struct drm_i915_private *dev_priv = to_i915(dev);
8494 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8495 uint32_t ps_ctrl = 0;
8496 int id = -1;
8497 int i;
8498
8499 /* find scaler attached to this pipe */
8500 for (i = 0; i < crtc->num_scalers; i++) {
8501 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8502 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8503 id = i;
8504 pipe_config->pch_pfit.enabled = true;
8505 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8506 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8507 break;
8508 }
8509 }
8510
8511 scaler_state->scaler_id = id;
8512 if (id >= 0) {
8513 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8514 } else {
8515 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8516 }
8517 }
8518
8519 static void
8520 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8521 struct intel_initial_plane_config *plane_config)
8522 {
8523 struct drm_device *dev = crtc->base.dev;
8524 struct drm_i915_private *dev_priv = to_i915(dev);
8525 u32 val, base, offset, stride_mult, tiling;
8526 int pipe = crtc->pipe;
8527 int fourcc, pixel_format;
8528 unsigned int aligned_height;
8529 struct drm_framebuffer *fb;
8530 struct intel_framebuffer *intel_fb;
8531
8532 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8533 if (!intel_fb) {
8534 DRM_DEBUG_KMS("failed to alloc fb\n");
8535 return;
8536 }
8537
8538 fb = &intel_fb->base;
8539
8540 fb->dev = dev;
8541
8542 val = I915_READ(PLANE_CTL(pipe, 0));
8543 if (!(val & PLANE_CTL_ENABLE))
8544 goto error;
8545
8546 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8547 fourcc = skl_format_to_fourcc(pixel_format,
8548 val & PLANE_CTL_ORDER_RGBX,
8549 val & PLANE_CTL_ALPHA_MASK);
8550 fb->format = drm_format_info(fourcc);
8551
8552 tiling = val & PLANE_CTL_TILED_MASK;
8553 switch (tiling) {
8554 case PLANE_CTL_TILED_LINEAR:
8555 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8556 break;
8557 case PLANE_CTL_TILED_X:
8558 plane_config->tiling = I915_TILING_X;
8559 fb->modifier = I915_FORMAT_MOD_X_TILED;
8560 break;
8561 case PLANE_CTL_TILED_Y:
8562 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8563 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8564 else
8565 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8566 break;
8567 case PLANE_CTL_TILED_YF:
8568 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8569 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8570 else
8571 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8572 break;
8573 default:
8574 MISSING_CASE(tiling);
8575 goto error;
8576 }
8577
8578 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8579 plane_config->base = base;
8580
8581 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8582
8583 val = I915_READ(PLANE_SIZE(pipe, 0));
8584 fb->height = ((val >> 16) & 0xfff) + 1;
8585 fb->width = ((val >> 0) & 0x1fff) + 1;
8586
8587 val = I915_READ(PLANE_STRIDE(pipe, 0));
8588 stride_mult = intel_fb_stride_alignment(fb, 0);
8589 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8590
8591 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8592
8593 plane_config->size = fb->pitches[0] * aligned_height;
8594
8595 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8596 pipe_name(pipe), fb->width, fb->height,
8597 fb->format->cpp[0] * 8, base, fb->pitches[0],
8598 plane_config->size);
8599
8600 plane_config->fb = intel_fb;
8601 return;
8602
8603 error:
8604 kfree(intel_fb);
8605 }
8606
8607 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8608 struct intel_crtc_state *pipe_config)
8609 {
8610 struct drm_device *dev = crtc->base.dev;
8611 struct drm_i915_private *dev_priv = to_i915(dev);
8612 uint32_t tmp;
8613
8614 tmp = I915_READ(PF_CTL(crtc->pipe));
8615
8616 if (tmp & PF_ENABLE) {
8617 pipe_config->pch_pfit.enabled = true;
8618 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8619 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8620
8621 /* We currently do not free assignements of panel fitters on
8622 * ivb/hsw (since we don't use the higher upscaling modes which
8623 * differentiates them) so just WARN about this case for now. */
8624 if (IS_GEN7(dev_priv)) {
8625 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8626 PF_PIPE_SEL_IVB(crtc->pipe));
8627 }
8628 }
8629 }
8630
8631 static void
8632 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8633 struct intel_initial_plane_config *plane_config)
8634 {
8635 struct drm_device *dev = crtc->base.dev;
8636 struct drm_i915_private *dev_priv = to_i915(dev);
8637 u32 val, base, offset;
8638 int pipe = crtc->pipe;
8639 int fourcc, pixel_format;
8640 unsigned int aligned_height;
8641 struct drm_framebuffer *fb;
8642 struct intel_framebuffer *intel_fb;
8643
8644 val = I915_READ(DSPCNTR(pipe));
8645 if (!(val & DISPLAY_PLANE_ENABLE))
8646 return;
8647
8648 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8649 if (!intel_fb) {
8650 DRM_DEBUG_KMS("failed to alloc fb\n");
8651 return;
8652 }
8653
8654 fb = &intel_fb->base;
8655
8656 fb->dev = dev;
8657
8658 if (INTEL_GEN(dev_priv) >= 4) {
8659 if (val & DISPPLANE_TILED) {
8660 plane_config->tiling = I915_TILING_X;
8661 fb->modifier = I915_FORMAT_MOD_X_TILED;
8662 }
8663 }
8664
8665 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8666 fourcc = i9xx_format_to_fourcc(pixel_format);
8667 fb->format = drm_format_info(fourcc);
8668
8669 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8670 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8671 offset = I915_READ(DSPOFFSET(pipe));
8672 } else {
8673 if (plane_config->tiling)
8674 offset = I915_READ(DSPTILEOFF(pipe));
8675 else
8676 offset = I915_READ(DSPLINOFF(pipe));
8677 }
8678 plane_config->base = base;
8679
8680 val = I915_READ(PIPESRC(pipe));
8681 fb->width = ((val >> 16) & 0xfff) + 1;
8682 fb->height = ((val >> 0) & 0xfff) + 1;
8683
8684 val = I915_READ(DSPSTRIDE(pipe));
8685 fb->pitches[0] = val & 0xffffffc0;
8686
8687 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8688
8689 plane_config->size = fb->pitches[0] * aligned_height;
8690
8691 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8692 pipe_name(pipe), fb->width, fb->height,
8693 fb->format->cpp[0] * 8, base, fb->pitches[0],
8694 plane_config->size);
8695
8696 plane_config->fb = intel_fb;
8697 }
8698
8699 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8700 struct intel_crtc_state *pipe_config)
8701 {
8702 struct drm_device *dev = crtc->base.dev;
8703 struct drm_i915_private *dev_priv = to_i915(dev);
8704 enum intel_display_power_domain power_domain;
8705 uint32_t tmp;
8706 bool ret;
8707
8708 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8709 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8710 return false;
8711
8712 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8713 pipe_config->shared_dpll = NULL;
8714
8715 ret = false;
8716 tmp = I915_READ(PIPECONF(crtc->pipe));
8717 if (!(tmp & PIPECONF_ENABLE))
8718 goto out;
8719
8720 switch (tmp & PIPECONF_BPC_MASK) {
8721 case PIPECONF_6BPC:
8722 pipe_config->pipe_bpp = 18;
8723 break;
8724 case PIPECONF_8BPC:
8725 pipe_config->pipe_bpp = 24;
8726 break;
8727 case PIPECONF_10BPC:
8728 pipe_config->pipe_bpp = 30;
8729 break;
8730 case PIPECONF_12BPC:
8731 pipe_config->pipe_bpp = 36;
8732 break;
8733 default:
8734 break;
8735 }
8736
8737 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8738 pipe_config->limited_color_range = true;
8739
8740 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8741 struct intel_shared_dpll *pll;
8742 enum intel_dpll_id pll_id;
8743
8744 pipe_config->has_pch_encoder = true;
8745
8746 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8747 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8748 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8749
8750 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8751
8752 if (HAS_PCH_IBX(dev_priv)) {
8753 /*
8754 * The pipe->pch transcoder and pch transcoder->pll
8755 * mapping is fixed.
8756 */
8757 pll_id = (enum intel_dpll_id) crtc->pipe;
8758 } else {
8759 tmp = I915_READ(PCH_DPLL_SEL);
8760 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8761 pll_id = DPLL_ID_PCH_PLL_B;
8762 else
8763 pll_id= DPLL_ID_PCH_PLL_A;
8764 }
8765
8766 pipe_config->shared_dpll =
8767 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8768 pll = pipe_config->shared_dpll;
8769
8770 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8771 &pipe_config->dpll_hw_state));
8772
8773 tmp = pipe_config->dpll_hw_state.dpll;
8774 pipe_config->pixel_multiplier =
8775 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8776 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8777
8778 ironlake_pch_clock_get(crtc, pipe_config);
8779 } else {
8780 pipe_config->pixel_multiplier = 1;
8781 }
8782
8783 intel_get_pipe_timings(crtc, pipe_config);
8784 intel_get_pipe_src_size(crtc, pipe_config);
8785
8786 ironlake_get_pfit_config(crtc, pipe_config);
8787
8788 ret = true;
8789
8790 out:
8791 intel_display_power_put(dev_priv, power_domain);
8792
8793 return ret;
8794 }
8795
8796 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8797 {
8798 struct drm_device *dev = &dev_priv->drm;
8799 struct intel_crtc *crtc;
8800
8801 for_each_intel_crtc(dev, crtc)
8802 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8803 pipe_name(crtc->pipe));
8804
8805 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8806 "Display power well on\n");
8807 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8808 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8809 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8810 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8811 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8812 "CPU PWM1 enabled\n");
8813 if (IS_HASWELL(dev_priv))
8814 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8815 "CPU PWM2 enabled\n");
8816 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8817 "PCH PWM1 enabled\n");
8818 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8819 "Utility pin enabled\n");
8820 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8821
8822 /*
8823 * In theory we can still leave IRQs enabled, as long as only the HPD
8824 * interrupts remain enabled. We used to check for that, but since it's
8825 * gen-specific and since we only disable LCPLL after we fully disable
8826 * the interrupts, the check below should be enough.
8827 */
8828 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8829 }
8830
8831 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8832 {
8833 if (IS_HASWELL(dev_priv))
8834 return I915_READ(D_COMP_HSW);
8835 else
8836 return I915_READ(D_COMP_BDW);
8837 }
8838
8839 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8840 {
8841 if (IS_HASWELL(dev_priv)) {
8842 mutex_lock(&dev_priv->pcu_lock);
8843 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8844 val))
8845 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8846 mutex_unlock(&dev_priv->pcu_lock);
8847 } else {
8848 I915_WRITE(D_COMP_BDW, val);
8849 POSTING_READ(D_COMP_BDW);
8850 }
8851 }
8852
8853 /*
8854 * This function implements pieces of two sequences from BSpec:
8855 * - Sequence for display software to disable LCPLL
8856 * - Sequence for display software to allow package C8+
8857 * The steps implemented here are just the steps that actually touch the LCPLL
8858 * register. Callers should take care of disabling all the display engine
8859 * functions, doing the mode unset, fixing interrupts, etc.
8860 */
8861 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8862 bool switch_to_fclk, bool allow_power_down)
8863 {
8864 uint32_t val;
8865
8866 assert_can_disable_lcpll(dev_priv);
8867
8868 val = I915_READ(LCPLL_CTL);
8869
8870 if (switch_to_fclk) {
8871 val |= LCPLL_CD_SOURCE_FCLK;
8872 I915_WRITE(LCPLL_CTL, val);
8873
8874 if (wait_for_us(I915_READ(LCPLL_CTL) &
8875 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8876 DRM_ERROR("Switching to FCLK failed\n");
8877
8878 val = I915_READ(LCPLL_CTL);
8879 }
8880
8881 val |= LCPLL_PLL_DISABLE;
8882 I915_WRITE(LCPLL_CTL, val);
8883 POSTING_READ(LCPLL_CTL);
8884
8885 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8886 DRM_ERROR("LCPLL still locked\n");
8887
8888 val = hsw_read_dcomp(dev_priv);
8889 val |= D_COMP_COMP_DISABLE;
8890 hsw_write_dcomp(dev_priv, val);
8891 ndelay(100);
8892
8893 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8894 1))
8895 DRM_ERROR("D_COMP RCOMP still in progress\n");
8896
8897 if (allow_power_down) {
8898 val = I915_READ(LCPLL_CTL);
8899 val |= LCPLL_POWER_DOWN_ALLOW;
8900 I915_WRITE(LCPLL_CTL, val);
8901 POSTING_READ(LCPLL_CTL);
8902 }
8903 }
8904
8905 /*
8906 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8907 * source.
8908 */
8909 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8910 {
8911 uint32_t val;
8912
8913 val = I915_READ(LCPLL_CTL);
8914
8915 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8916 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8917 return;
8918
8919 /*
8920 * Make sure we're not on PC8 state before disabling PC8, otherwise
8921 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8922 */
8923 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8924
8925 if (val & LCPLL_POWER_DOWN_ALLOW) {
8926 val &= ~LCPLL_POWER_DOWN_ALLOW;
8927 I915_WRITE(LCPLL_CTL, val);
8928 POSTING_READ(LCPLL_CTL);
8929 }
8930
8931 val = hsw_read_dcomp(dev_priv);
8932 val |= D_COMP_COMP_FORCE;
8933 val &= ~D_COMP_COMP_DISABLE;
8934 hsw_write_dcomp(dev_priv, val);
8935
8936 val = I915_READ(LCPLL_CTL);
8937 val &= ~LCPLL_PLL_DISABLE;
8938 I915_WRITE(LCPLL_CTL, val);
8939
8940 if (intel_wait_for_register(dev_priv,
8941 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8942 5))
8943 DRM_ERROR("LCPLL not locked yet\n");
8944
8945 if (val & LCPLL_CD_SOURCE_FCLK) {
8946 val = I915_READ(LCPLL_CTL);
8947 val &= ~LCPLL_CD_SOURCE_FCLK;
8948 I915_WRITE(LCPLL_CTL, val);
8949
8950 if (wait_for_us((I915_READ(LCPLL_CTL) &
8951 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8952 DRM_ERROR("Switching back to LCPLL failed\n");
8953 }
8954
8955 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8956 intel_update_cdclk(dev_priv);
8957 }
8958
8959 /*
8960 * Package states C8 and deeper are really deep PC states that can only be
8961 * reached when all the devices on the system allow it, so even if the graphics
8962 * device allows PC8+, it doesn't mean the system will actually get to these
8963 * states. Our driver only allows PC8+ when going into runtime PM.
8964 *
8965 * The requirements for PC8+ are that all the outputs are disabled, the power
8966 * well is disabled and most interrupts are disabled, and these are also
8967 * requirements for runtime PM. When these conditions are met, we manually do
8968 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8969 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8970 * hang the machine.
8971 *
8972 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8973 * the state of some registers, so when we come back from PC8+ we need to
8974 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8975 * need to take care of the registers kept by RC6. Notice that this happens even
8976 * if we don't put the device in PCI D3 state (which is what currently happens
8977 * because of the runtime PM support).
8978 *
8979 * For more, read "Display Sequences for Package C8" on the hardware
8980 * documentation.
8981 */
8982 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8983 {
8984 uint32_t val;
8985
8986 DRM_DEBUG_KMS("Enabling package C8+\n");
8987
8988 if (HAS_PCH_LPT_LP(dev_priv)) {
8989 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8990 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8991 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8992 }
8993
8994 lpt_disable_clkout_dp(dev_priv);
8995 hsw_disable_lcpll(dev_priv, true, true);
8996 }
8997
8998 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8999 {
9000 uint32_t val;
9001
9002 DRM_DEBUG_KMS("Disabling package C8+\n");
9003
9004 hsw_restore_lcpll(dev_priv);
9005 lpt_init_pch_refclk(dev_priv);
9006
9007 if (HAS_PCH_LPT_LP(dev_priv)) {
9008 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9009 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9010 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9011 }
9012 }
9013
9014 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9015 struct intel_crtc_state *crtc_state)
9016 {
9017 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9018 struct intel_encoder *encoder =
9019 intel_ddi_get_crtc_new_encoder(crtc_state);
9020
9021 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9022 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9023 pipe_name(crtc->pipe));
9024 return -EINVAL;
9025 }
9026 }
9027
9028 crtc->lowfreq_avail = false;
9029
9030 return 0;
9031 }
9032
9033 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9034 enum port port,
9035 struct intel_crtc_state *pipe_config)
9036 {
9037 enum intel_dpll_id id;
9038 u32 temp;
9039
9040 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9041 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9042
9043 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9044 return;
9045
9046 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9047 }
9048
9049 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9050 enum port port,
9051 struct intel_crtc_state *pipe_config)
9052 {
9053 enum intel_dpll_id id;
9054
9055 switch (port) {
9056 case PORT_A:
9057 id = DPLL_ID_SKL_DPLL0;
9058 break;
9059 case PORT_B:
9060 id = DPLL_ID_SKL_DPLL1;
9061 break;
9062 case PORT_C:
9063 id = DPLL_ID_SKL_DPLL2;
9064 break;
9065 default:
9066 DRM_ERROR("Incorrect port type\n");
9067 return;
9068 }
9069
9070 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9071 }
9072
9073 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9074 enum port port,
9075 struct intel_crtc_state *pipe_config)
9076 {
9077 enum intel_dpll_id id;
9078 u32 temp;
9079
9080 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9081 id = temp >> (port * 3 + 1);
9082
9083 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9084 return;
9085
9086 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9087 }
9088
9089 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9090 enum port port,
9091 struct intel_crtc_state *pipe_config)
9092 {
9093 enum intel_dpll_id id;
9094 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9095
9096 switch (ddi_pll_sel) {
9097 case PORT_CLK_SEL_WRPLL1:
9098 id = DPLL_ID_WRPLL1;
9099 break;
9100 case PORT_CLK_SEL_WRPLL2:
9101 id = DPLL_ID_WRPLL2;
9102 break;
9103 case PORT_CLK_SEL_SPLL:
9104 id = DPLL_ID_SPLL;
9105 break;
9106 case PORT_CLK_SEL_LCPLL_810:
9107 id = DPLL_ID_LCPLL_810;
9108 break;
9109 case PORT_CLK_SEL_LCPLL_1350:
9110 id = DPLL_ID_LCPLL_1350;
9111 break;
9112 case PORT_CLK_SEL_LCPLL_2700:
9113 id = DPLL_ID_LCPLL_2700;
9114 break;
9115 default:
9116 MISSING_CASE(ddi_pll_sel);
9117 /* fall through */
9118 case PORT_CLK_SEL_NONE:
9119 return;
9120 }
9121
9122 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9123 }
9124
9125 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9126 struct intel_crtc_state *pipe_config,
9127 u64 *power_domain_mask)
9128 {
9129 struct drm_device *dev = crtc->base.dev;
9130 struct drm_i915_private *dev_priv = to_i915(dev);
9131 enum intel_display_power_domain power_domain;
9132 u32 tmp;
9133
9134 /*
9135 * The pipe->transcoder mapping is fixed with the exception of the eDP
9136 * transcoder handled below.
9137 */
9138 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9139
9140 /*
9141 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9142 * consistency and less surprising code; it's in always on power).
9143 */
9144 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9145 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9146 enum pipe trans_edp_pipe;
9147 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9148 default:
9149 WARN(1, "unknown pipe linked to edp transcoder\n");
9150 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9151 case TRANS_DDI_EDP_INPUT_A_ON:
9152 trans_edp_pipe = PIPE_A;
9153 break;
9154 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9155 trans_edp_pipe = PIPE_B;
9156 break;
9157 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9158 trans_edp_pipe = PIPE_C;
9159 break;
9160 }
9161
9162 if (trans_edp_pipe == crtc->pipe)
9163 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9164 }
9165
9166 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9167 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9168 return false;
9169 *power_domain_mask |= BIT_ULL(power_domain);
9170
9171 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9172
9173 return tmp & PIPECONF_ENABLE;
9174 }
9175
9176 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9177 struct intel_crtc_state *pipe_config,
9178 u64 *power_domain_mask)
9179 {
9180 struct drm_device *dev = crtc->base.dev;
9181 struct drm_i915_private *dev_priv = to_i915(dev);
9182 enum intel_display_power_domain power_domain;
9183 enum port port;
9184 enum transcoder cpu_transcoder;
9185 u32 tmp;
9186
9187 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9188 if (port == PORT_A)
9189 cpu_transcoder = TRANSCODER_DSI_A;
9190 else
9191 cpu_transcoder = TRANSCODER_DSI_C;
9192
9193 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9194 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9195 continue;
9196 *power_domain_mask |= BIT_ULL(power_domain);
9197
9198 /*
9199 * The PLL needs to be enabled with a valid divider
9200 * configuration, otherwise accessing DSI registers will hang
9201 * the machine. See BSpec North Display Engine
9202 * registers/MIPI[BXT]. We can break out here early, since we
9203 * need the same DSI PLL to be enabled for both DSI ports.
9204 */
9205 if (!intel_dsi_pll_is_enabled(dev_priv))
9206 break;
9207
9208 /* XXX: this works for video mode only */
9209 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9210 if (!(tmp & DPI_ENABLE))
9211 continue;
9212
9213 tmp = I915_READ(MIPI_CTRL(port));
9214 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9215 continue;
9216
9217 pipe_config->cpu_transcoder = cpu_transcoder;
9218 break;
9219 }
9220
9221 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9222 }
9223
9224 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9225 struct intel_crtc_state *pipe_config)
9226 {
9227 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9228 struct intel_shared_dpll *pll;
9229 enum port port;
9230 uint32_t tmp;
9231
9232 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9233
9234 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9235
9236 if (IS_CANNONLAKE(dev_priv))
9237 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9238 else if (IS_GEN9_BC(dev_priv))
9239 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9240 else if (IS_GEN9_LP(dev_priv))
9241 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9242 else
9243 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9244
9245 pll = pipe_config->shared_dpll;
9246 if (pll) {
9247 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9248 &pipe_config->dpll_hw_state));
9249 }
9250
9251 /*
9252 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9253 * DDI E. So just check whether this pipe is wired to DDI E and whether
9254 * the PCH transcoder is on.
9255 */
9256 if (INTEL_GEN(dev_priv) < 9 &&
9257 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9258 pipe_config->has_pch_encoder = true;
9259
9260 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9261 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9262 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9263
9264 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9265 }
9266 }
9267
9268 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9269 struct intel_crtc_state *pipe_config)
9270 {
9271 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9272 enum intel_display_power_domain power_domain;
9273 u64 power_domain_mask;
9274 bool active;
9275
9276 intel_crtc_init_scalers(crtc, pipe_config);
9277
9278 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9279 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9280 return false;
9281 power_domain_mask = BIT_ULL(power_domain);
9282
9283 pipe_config->shared_dpll = NULL;
9284
9285 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9286
9287 if (IS_GEN9_LP(dev_priv) &&
9288 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9289 WARN_ON(active);
9290 active = true;
9291 }
9292
9293 if (!active)
9294 goto out;
9295
9296 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9297 haswell_get_ddi_port_state(crtc, pipe_config);
9298 intel_get_pipe_timings(crtc, pipe_config);
9299 }
9300
9301 intel_get_pipe_src_size(crtc, pipe_config);
9302
9303 pipe_config->gamma_mode =
9304 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9305
9306 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9307 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9308 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9309
9310 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9311 bool blend_mode_420 = tmp &
9312 PIPEMISC_YUV420_MODE_FULL_BLEND;
9313
9314 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9315 if (pipe_config->ycbcr420 != clrspace_yuv ||
9316 pipe_config->ycbcr420 != blend_mode_420)
9317 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9318 } else if (clrspace_yuv) {
9319 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9320 }
9321 }
9322
9323 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9324 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9325 power_domain_mask |= BIT_ULL(power_domain);
9326 if (INTEL_GEN(dev_priv) >= 9)
9327 skylake_get_pfit_config(crtc, pipe_config);
9328 else
9329 ironlake_get_pfit_config(crtc, pipe_config);
9330 }
9331
9332 if (IS_HASWELL(dev_priv))
9333 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9334 (I915_READ(IPS_CTL) & IPS_ENABLE);
9335
9336 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9337 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9338 pipe_config->pixel_multiplier =
9339 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9340 } else {
9341 pipe_config->pixel_multiplier = 1;
9342 }
9343
9344 out:
9345 for_each_power_domain(power_domain, power_domain_mask)
9346 intel_display_power_put(dev_priv, power_domain);
9347
9348 return active;
9349 }
9350
9351 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9352 {
9353 struct drm_i915_private *dev_priv =
9354 to_i915(plane_state->base.plane->dev);
9355 const struct drm_framebuffer *fb = plane_state->base.fb;
9356 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9357 u32 base;
9358
9359 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9360 base = obj->phys_handle->busaddr;
9361 else
9362 base = intel_plane_ggtt_offset(plane_state);
9363
9364 base += plane_state->main.offset;
9365
9366 /* ILK+ do this automagically */
9367 if (HAS_GMCH_DISPLAY(dev_priv) &&
9368 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9369 base += (plane_state->base.crtc_h *
9370 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9371
9372 return base;
9373 }
9374
9375 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9376 {
9377 int x = plane_state->base.crtc_x;
9378 int y = plane_state->base.crtc_y;
9379 u32 pos = 0;
9380
9381 if (x < 0) {
9382 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9383 x = -x;
9384 }
9385 pos |= x << CURSOR_X_SHIFT;
9386
9387 if (y < 0) {
9388 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9389 y = -y;
9390 }
9391 pos |= y << CURSOR_Y_SHIFT;
9392
9393 return pos;
9394 }
9395
9396 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9397 {
9398 const struct drm_mode_config *config =
9399 &plane_state->base.plane->dev->mode_config;
9400 int width = plane_state->base.crtc_w;
9401 int height = plane_state->base.crtc_h;
9402
9403 return width > 0 && width <= config->cursor_width &&
9404 height > 0 && height <= config->cursor_height;
9405 }
9406
9407 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9408 struct intel_plane_state *plane_state)
9409 {
9410 const struct drm_framebuffer *fb = plane_state->base.fb;
9411 int src_x, src_y;
9412 u32 offset;
9413 int ret;
9414
9415 ret = drm_plane_helper_check_state(&plane_state->base,
9416 &plane_state->clip,
9417 DRM_PLANE_HELPER_NO_SCALING,
9418 DRM_PLANE_HELPER_NO_SCALING,
9419 true, true);
9420 if (ret)
9421 return ret;
9422
9423 if (!fb)
9424 return 0;
9425
9426 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9427 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9428 return -EINVAL;
9429 }
9430
9431 src_x = plane_state->base.src_x >> 16;
9432 src_y = plane_state->base.src_y >> 16;
9433
9434 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9435 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9436
9437 if (src_x != 0 || src_y != 0) {
9438 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9439 return -EINVAL;
9440 }
9441
9442 plane_state->main.offset = offset;
9443
9444 return 0;
9445 }
9446
9447 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9448 const struct intel_plane_state *plane_state)
9449 {
9450 const struct drm_framebuffer *fb = plane_state->base.fb;
9451
9452 return CURSOR_ENABLE |
9453 CURSOR_GAMMA_ENABLE |
9454 CURSOR_FORMAT_ARGB |
9455 CURSOR_STRIDE(fb->pitches[0]);
9456 }
9457
9458 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9459 {
9460 int width = plane_state->base.crtc_w;
9461
9462 /*
9463 * 845g/865g are only limited by the width of their cursors,
9464 * the height is arbitrary up to the precision of the register.
9465 */
9466 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9467 }
9468
9469 static int i845_check_cursor(struct intel_plane *plane,
9470 struct intel_crtc_state *crtc_state,
9471 struct intel_plane_state *plane_state)
9472 {
9473 const struct drm_framebuffer *fb = plane_state->base.fb;
9474 int ret;
9475
9476 ret = intel_check_cursor(crtc_state, plane_state);
9477 if (ret)
9478 return ret;
9479
9480 /* if we want to turn off the cursor ignore width and height */
9481 if (!fb)
9482 return 0;
9483
9484 /* Check for which cursor types we support */
9485 if (!i845_cursor_size_ok(plane_state)) {
9486 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9487 plane_state->base.crtc_w,
9488 plane_state->base.crtc_h);
9489 return -EINVAL;
9490 }
9491
9492 switch (fb->pitches[0]) {
9493 case 256:
9494 case 512:
9495 case 1024:
9496 case 2048:
9497 break;
9498 default:
9499 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9500 fb->pitches[0]);
9501 return -EINVAL;
9502 }
9503
9504 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9505
9506 return 0;
9507 }
9508
9509 static void i845_update_cursor(struct intel_plane *plane,
9510 const struct intel_crtc_state *crtc_state,
9511 const struct intel_plane_state *plane_state)
9512 {
9513 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9514 u32 cntl = 0, base = 0, pos = 0, size = 0;
9515 unsigned long irqflags;
9516
9517 if (plane_state && plane_state->base.visible) {
9518 unsigned int width = plane_state->base.crtc_w;
9519 unsigned int height = plane_state->base.crtc_h;
9520
9521 cntl = plane_state->ctl;
9522 size = (height << 12) | width;
9523
9524 base = intel_cursor_base(plane_state);
9525 pos = intel_cursor_position(plane_state);
9526 }
9527
9528 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9529
9530 /* On these chipsets we can only modify the base/size/stride
9531 * whilst the cursor is disabled.
9532 */
9533 if (plane->cursor.base != base ||
9534 plane->cursor.size != size ||
9535 plane->cursor.cntl != cntl) {
9536 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9537 I915_WRITE_FW(CURBASE(PIPE_A), base);
9538 I915_WRITE_FW(CURSIZE, size);
9539 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9540 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9541
9542 plane->cursor.base = base;
9543 plane->cursor.size = size;
9544 plane->cursor.cntl = cntl;
9545 } else {
9546 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9547 }
9548
9549 POSTING_READ_FW(CURCNTR(PIPE_A));
9550
9551 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9552 }
9553
9554 static void i845_disable_cursor(struct intel_plane *plane,
9555 struct intel_crtc *crtc)
9556 {
9557 i845_update_cursor(plane, NULL, NULL);
9558 }
9559
9560 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9561 const struct intel_plane_state *plane_state)
9562 {
9563 struct drm_i915_private *dev_priv =
9564 to_i915(plane_state->base.plane->dev);
9565 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9566 u32 cntl;
9567
9568 cntl = MCURSOR_GAMMA_ENABLE;
9569
9570 if (HAS_DDI(dev_priv))
9571 cntl |= CURSOR_PIPE_CSC_ENABLE;
9572
9573 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9574
9575 switch (plane_state->base.crtc_w) {
9576 case 64:
9577 cntl |= CURSOR_MODE_64_ARGB_AX;
9578 break;
9579 case 128:
9580 cntl |= CURSOR_MODE_128_ARGB_AX;
9581 break;
9582 case 256:
9583 cntl |= CURSOR_MODE_256_ARGB_AX;
9584 break;
9585 default:
9586 MISSING_CASE(plane_state->base.crtc_w);
9587 return 0;
9588 }
9589
9590 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9591 cntl |= CURSOR_ROTATE_180;
9592
9593 return cntl;
9594 }
9595
9596 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9597 {
9598 struct drm_i915_private *dev_priv =
9599 to_i915(plane_state->base.plane->dev);
9600 int width = plane_state->base.crtc_w;
9601 int height = plane_state->base.crtc_h;
9602
9603 if (!intel_cursor_size_ok(plane_state))
9604 return false;
9605
9606 /* Cursor width is limited to a few power-of-two sizes */
9607 switch (width) {
9608 case 256:
9609 case 128:
9610 case 64:
9611 break;
9612 default:
9613 return false;
9614 }
9615
9616 /*
9617 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9618 * height from 8 lines up to the cursor width, when the
9619 * cursor is not rotated. Everything else requires square
9620 * cursors.
9621 */
9622 if (HAS_CUR_FBC(dev_priv) &&
9623 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9624 if (height < 8 || height > width)
9625 return false;
9626 } else {
9627 if (height != width)
9628 return false;
9629 }
9630
9631 return true;
9632 }
9633
9634 static int i9xx_check_cursor(struct intel_plane *plane,
9635 struct intel_crtc_state *crtc_state,
9636 struct intel_plane_state *plane_state)
9637 {
9638 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9639 const struct drm_framebuffer *fb = plane_state->base.fb;
9640 enum pipe pipe = plane->pipe;
9641 int ret;
9642
9643 ret = intel_check_cursor(crtc_state, plane_state);
9644 if (ret)
9645 return ret;
9646
9647 /* if we want to turn off the cursor ignore width and height */
9648 if (!fb)
9649 return 0;
9650
9651 /* Check for which cursor types we support */
9652 if (!i9xx_cursor_size_ok(plane_state)) {
9653 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9654 plane_state->base.crtc_w,
9655 plane_state->base.crtc_h);
9656 return -EINVAL;
9657 }
9658
9659 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9660 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9661 fb->pitches[0], plane_state->base.crtc_w);
9662 return -EINVAL;
9663 }
9664
9665 /*
9666 * There's something wrong with the cursor on CHV pipe C.
9667 * If it straddles the left edge of the screen then
9668 * moving it away from the edge or disabling it often
9669 * results in a pipe underrun, and often that can lead to
9670 * dead pipe (constant underrun reported, and it scans
9671 * out just a solid color). To recover from that, the
9672 * display power well must be turned off and on again.
9673 * Refuse the put the cursor into that compromised position.
9674 */
9675 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9676 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9677 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9678 return -EINVAL;
9679 }
9680
9681 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9682
9683 return 0;
9684 }
9685
9686 static void i9xx_update_cursor(struct intel_plane *plane,
9687 const struct intel_crtc_state *crtc_state,
9688 const struct intel_plane_state *plane_state)
9689 {
9690 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9691 enum pipe pipe = plane->pipe;
9692 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9693 unsigned long irqflags;
9694
9695 if (plane_state && plane_state->base.visible) {
9696 cntl = plane_state->ctl;
9697
9698 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9699 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9700
9701 base = intel_cursor_base(plane_state);
9702 pos = intel_cursor_position(plane_state);
9703 }
9704
9705 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9706
9707 /*
9708 * On some platforms writing CURCNTR first will also
9709 * cause CURPOS to be armed by the CURBASE write.
9710 * Without the CURCNTR write the CURPOS write would
9711 * arm itself. Thus we always start the full update
9712 * with a CURCNTR write.
9713 *
9714 * On other platforms CURPOS always requires the
9715 * CURBASE write to arm the update. Additonally
9716 * a write to any of the cursor register will cancel
9717 * an already armed cursor update. Thus leaving out
9718 * the CURBASE write after CURPOS could lead to a
9719 * cursor that doesn't appear to move, or even change
9720 * shape. Thus we always write CURBASE.
9721 *
9722 * CURCNTR and CUR_FBC_CTL are always
9723 * armed by the CURBASE write only.
9724 */
9725 if (plane->cursor.base != base ||
9726 plane->cursor.size != fbc_ctl ||
9727 plane->cursor.cntl != cntl) {
9728 I915_WRITE_FW(CURCNTR(pipe), cntl);
9729 if (HAS_CUR_FBC(dev_priv))
9730 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9731 I915_WRITE_FW(CURPOS(pipe), pos);
9732 I915_WRITE_FW(CURBASE(pipe), base);
9733
9734 plane->cursor.base = base;
9735 plane->cursor.size = fbc_ctl;
9736 plane->cursor.cntl = cntl;
9737 } else {
9738 I915_WRITE_FW(CURPOS(pipe), pos);
9739 I915_WRITE_FW(CURBASE(pipe), base);
9740 }
9741
9742 POSTING_READ_FW(CURBASE(pipe));
9743
9744 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9745 }
9746
9747 static void i9xx_disable_cursor(struct intel_plane *plane,
9748 struct intel_crtc *crtc)
9749 {
9750 i9xx_update_cursor(plane, NULL, NULL);
9751 }
9752
9753
9754 /* VESA 640x480x72Hz mode to set on the pipe */
9755 static const struct drm_display_mode load_detect_mode = {
9756 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9757 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9758 };
9759
9760 struct drm_framebuffer *
9761 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9762 struct drm_mode_fb_cmd2 *mode_cmd)
9763 {
9764 struct intel_framebuffer *intel_fb;
9765 int ret;
9766
9767 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9768 if (!intel_fb)
9769 return ERR_PTR(-ENOMEM);
9770
9771 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9772 if (ret)
9773 goto err;
9774
9775 return &intel_fb->base;
9776
9777 err:
9778 kfree(intel_fb);
9779 return ERR_PTR(ret);
9780 }
9781
9782 static u32
9783 intel_framebuffer_pitch_for_width(int width, int bpp)
9784 {
9785 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9786 return ALIGN(pitch, 64);
9787 }
9788
9789 static u32
9790 intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9791 {
9792 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9793 return PAGE_ALIGN(pitch * mode->vdisplay);
9794 }
9795
9796 static struct drm_framebuffer *
9797 intel_framebuffer_create_for_mode(struct drm_device *dev,
9798 const struct drm_display_mode *mode,
9799 int depth, int bpp)
9800 {
9801 struct drm_framebuffer *fb;
9802 struct drm_i915_gem_object *obj;
9803 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9804
9805 obj = i915_gem_object_create(to_i915(dev),
9806 intel_framebuffer_size_for_mode(mode, bpp));
9807 if (IS_ERR(obj))
9808 return ERR_CAST(obj);
9809
9810 mode_cmd.width = mode->hdisplay;
9811 mode_cmd.height = mode->vdisplay;
9812 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9813 bpp);
9814 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9815
9816 fb = intel_framebuffer_create(obj, &mode_cmd);
9817 if (IS_ERR(fb))
9818 i915_gem_object_put(obj);
9819
9820 return fb;
9821 }
9822
9823 static struct drm_framebuffer *
9824 mode_fits_in_fbdev(struct drm_device *dev,
9825 const struct drm_display_mode *mode)
9826 {
9827 #ifdef CONFIG_DRM_FBDEV_EMULATION
9828 struct drm_i915_private *dev_priv = to_i915(dev);
9829 struct drm_i915_gem_object *obj;
9830 struct drm_framebuffer *fb;
9831
9832 if (!dev_priv->fbdev)
9833 return NULL;
9834
9835 if (!dev_priv->fbdev->fb)
9836 return NULL;
9837
9838 obj = dev_priv->fbdev->fb->obj;
9839 BUG_ON(!obj);
9840
9841 fb = &dev_priv->fbdev->fb->base;
9842 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9843 fb->format->cpp[0] * 8))
9844 return NULL;
9845
9846 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9847 return NULL;
9848
9849 drm_framebuffer_reference(fb);
9850 return fb;
9851 #else
9852 return NULL;
9853 #endif
9854 }
9855
9856 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9857 struct drm_crtc *crtc,
9858 const struct drm_display_mode *mode,
9859 struct drm_framebuffer *fb,
9860 int x, int y)
9861 {
9862 struct drm_plane_state *plane_state;
9863 int hdisplay, vdisplay;
9864 int ret;
9865
9866 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9867 if (IS_ERR(plane_state))
9868 return PTR_ERR(plane_state);
9869
9870 if (mode)
9871 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9872 else
9873 hdisplay = vdisplay = 0;
9874
9875 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9876 if (ret)
9877 return ret;
9878 drm_atomic_set_fb_for_plane(plane_state, fb);
9879 plane_state->crtc_x = 0;
9880 plane_state->crtc_y = 0;
9881 plane_state->crtc_w = hdisplay;
9882 plane_state->crtc_h = vdisplay;
9883 plane_state->src_x = x << 16;
9884 plane_state->src_y = y << 16;
9885 plane_state->src_w = hdisplay << 16;
9886 plane_state->src_h = vdisplay << 16;
9887
9888 return 0;
9889 }
9890
9891 int intel_get_load_detect_pipe(struct drm_connector *connector,
9892 const struct drm_display_mode *mode,
9893 struct intel_load_detect_pipe *old,
9894 struct drm_modeset_acquire_ctx *ctx)
9895 {
9896 struct intel_crtc *intel_crtc;
9897 struct intel_encoder *intel_encoder =
9898 intel_attached_encoder(connector);
9899 struct drm_crtc *possible_crtc;
9900 struct drm_encoder *encoder = &intel_encoder->base;
9901 struct drm_crtc *crtc = NULL;
9902 struct drm_device *dev = encoder->dev;
9903 struct drm_i915_private *dev_priv = to_i915(dev);
9904 struct drm_framebuffer *fb;
9905 struct drm_mode_config *config = &dev->mode_config;
9906 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9907 struct drm_connector_state *connector_state;
9908 struct intel_crtc_state *crtc_state;
9909 int ret, i = -1;
9910
9911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9912 connector->base.id, connector->name,
9913 encoder->base.id, encoder->name);
9914
9915 old->restore_state = NULL;
9916
9917 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9918
9919 /*
9920 * Algorithm gets a little messy:
9921 *
9922 * - if the connector already has an assigned crtc, use it (but make
9923 * sure it's on first)
9924 *
9925 * - try to find the first unused crtc that can drive this connector,
9926 * and use that if we find one
9927 */
9928
9929 /* See if we already have a CRTC for this connector */
9930 if (connector->state->crtc) {
9931 crtc = connector->state->crtc;
9932
9933 ret = drm_modeset_lock(&crtc->mutex, ctx);
9934 if (ret)
9935 goto fail;
9936
9937 /* Make sure the crtc and connector are running */
9938 goto found;
9939 }
9940
9941 /* Find an unused one (if possible) */
9942 for_each_crtc(dev, possible_crtc) {
9943 i++;
9944 if (!(encoder->possible_crtcs & (1 << i)))
9945 continue;
9946
9947 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9948 if (ret)
9949 goto fail;
9950
9951 if (possible_crtc->state->enable) {
9952 drm_modeset_unlock(&possible_crtc->mutex);
9953 continue;
9954 }
9955
9956 crtc = possible_crtc;
9957 break;
9958 }
9959
9960 /*
9961 * If we didn't find an unused CRTC, don't use any.
9962 */
9963 if (!crtc) {
9964 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9965 ret = -ENODEV;
9966 goto fail;
9967 }
9968
9969 found:
9970 intel_crtc = to_intel_crtc(crtc);
9971
9972 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9973 if (ret)
9974 goto fail;
9975
9976 state = drm_atomic_state_alloc(dev);
9977 restore_state = drm_atomic_state_alloc(dev);
9978 if (!state || !restore_state) {
9979 ret = -ENOMEM;
9980 goto fail;
9981 }
9982
9983 state->acquire_ctx = ctx;
9984 restore_state->acquire_ctx = ctx;
9985
9986 connector_state = drm_atomic_get_connector_state(state, connector);
9987 if (IS_ERR(connector_state)) {
9988 ret = PTR_ERR(connector_state);
9989 goto fail;
9990 }
9991
9992 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9993 if (ret)
9994 goto fail;
9995
9996 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9997 if (IS_ERR(crtc_state)) {
9998 ret = PTR_ERR(crtc_state);
9999 goto fail;
10000 }
10001
10002 crtc_state->base.active = crtc_state->base.enable = true;
10003
10004 if (!mode)
10005 mode = &load_detect_mode;
10006
10007 /* We need a framebuffer large enough to accommodate all accesses
10008 * that the plane may generate whilst we perform load detection.
10009 * We can not rely on the fbcon either being present (we get called
10010 * during its initialisation to detect all boot displays, or it may
10011 * not even exist) or that it is large enough to satisfy the
10012 * requested mode.
10013 */
10014 fb = mode_fits_in_fbdev(dev, mode);
10015 if (fb == NULL) {
10016 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10017 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10018 } else
10019 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10020 if (IS_ERR(fb)) {
10021 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10022 ret = PTR_ERR(fb);
10023 goto fail;
10024 }
10025
10026 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10027 if (ret)
10028 goto fail;
10029
10030 drm_framebuffer_unreference(fb);
10031
10032 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10033 if (ret)
10034 goto fail;
10035
10036 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10037 if (!ret)
10038 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10039 if (!ret)
10040 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10041 if (ret) {
10042 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10043 goto fail;
10044 }
10045
10046 ret = drm_atomic_commit(state);
10047 if (ret) {
10048 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10049 goto fail;
10050 }
10051
10052 old->restore_state = restore_state;
10053 drm_atomic_state_put(state);
10054
10055 /* let the connector get through one full cycle before testing */
10056 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10057 return true;
10058
10059 fail:
10060 if (state) {
10061 drm_atomic_state_put(state);
10062 state = NULL;
10063 }
10064 if (restore_state) {
10065 drm_atomic_state_put(restore_state);
10066 restore_state = NULL;
10067 }
10068
10069 if (ret == -EDEADLK)
10070 return ret;
10071
10072 return false;
10073 }
10074
10075 void intel_release_load_detect_pipe(struct drm_connector *connector,
10076 struct intel_load_detect_pipe *old,
10077 struct drm_modeset_acquire_ctx *ctx)
10078 {
10079 struct intel_encoder *intel_encoder =
10080 intel_attached_encoder(connector);
10081 struct drm_encoder *encoder = &intel_encoder->base;
10082 struct drm_atomic_state *state = old->restore_state;
10083 int ret;
10084
10085 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10086 connector->base.id, connector->name,
10087 encoder->base.id, encoder->name);
10088
10089 if (!state)
10090 return;
10091
10092 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10093 if (ret)
10094 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10095 drm_atomic_state_put(state);
10096 }
10097
10098 static int i9xx_pll_refclk(struct drm_device *dev,
10099 const struct intel_crtc_state *pipe_config)
10100 {
10101 struct drm_i915_private *dev_priv = to_i915(dev);
10102 u32 dpll = pipe_config->dpll_hw_state.dpll;
10103
10104 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10105 return dev_priv->vbt.lvds_ssc_freq;
10106 else if (HAS_PCH_SPLIT(dev_priv))
10107 return 120000;
10108 else if (!IS_GEN2(dev_priv))
10109 return 96000;
10110 else
10111 return 48000;
10112 }
10113
10114 /* Returns the clock of the currently programmed mode of the given pipe. */
10115 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10116 struct intel_crtc_state *pipe_config)
10117 {
10118 struct drm_device *dev = crtc->base.dev;
10119 struct drm_i915_private *dev_priv = to_i915(dev);
10120 int pipe = pipe_config->cpu_transcoder;
10121 u32 dpll = pipe_config->dpll_hw_state.dpll;
10122 u32 fp;
10123 struct dpll clock;
10124 int port_clock;
10125 int refclk = i9xx_pll_refclk(dev, pipe_config);
10126
10127 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10128 fp = pipe_config->dpll_hw_state.fp0;
10129 else
10130 fp = pipe_config->dpll_hw_state.fp1;
10131
10132 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10133 if (IS_PINEVIEW(dev_priv)) {
10134 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10135 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10136 } else {
10137 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10138 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10139 }
10140
10141 if (!IS_GEN2(dev_priv)) {
10142 if (IS_PINEVIEW(dev_priv))
10143 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10144 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10145 else
10146 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10147 DPLL_FPA01_P1_POST_DIV_SHIFT);
10148
10149 switch (dpll & DPLL_MODE_MASK) {
10150 case DPLLB_MODE_DAC_SERIAL:
10151 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10152 5 : 10;
10153 break;
10154 case DPLLB_MODE_LVDS:
10155 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10156 7 : 14;
10157 break;
10158 default:
10159 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10160 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10161 return;
10162 }
10163
10164 if (IS_PINEVIEW(dev_priv))
10165 port_clock = pnv_calc_dpll_params(refclk, &clock);
10166 else
10167 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10168 } else {
10169 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10170 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10171
10172 if (is_lvds) {
10173 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10174 DPLL_FPA01_P1_POST_DIV_SHIFT);
10175
10176 if (lvds & LVDS_CLKB_POWER_UP)
10177 clock.p2 = 7;
10178 else
10179 clock.p2 = 14;
10180 } else {
10181 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10182 clock.p1 = 2;
10183 else {
10184 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10185 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10186 }
10187 if (dpll & PLL_P2_DIVIDE_BY_4)
10188 clock.p2 = 4;
10189 else
10190 clock.p2 = 2;
10191 }
10192
10193 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10194 }
10195
10196 /*
10197 * This value includes pixel_multiplier. We will use
10198 * port_clock to compute adjusted_mode.crtc_clock in the
10199 * encoder's get_config() function.
10200 */
10201 pipe_config->port_clock = port_clock;
10202 }
10203
10204 int intel_dotclock_calculate(int link_freq,
10205 const struct intel_link_m_n *m_n)
10206 {
10207 /*
10208 * The calculation for the data clock is:
10209 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10210 * But we want to avoid losing precison if possible, so:
10211 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10212 *
10213 * and the link clock is simpler:
10214 * link_clock = (m * link_clock) / n
10215 */
10216
10217 if (!m_n->link_n)
10218 return 0;
10219
10220 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10221 }
10222
10223 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10224 struct intel_crtc_state *pipe_config)
10225 {
10226 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10227
10228 /* read out port_clock from the DPLL */
10229 i9xx_crtc_clock_get(crtc, pipe_config);
10230
10231 /*
10232 * In case there is an active pipe without active ports,
10233 * we may need some idea for the dotclock anyway.
10234 * Calculate one based on the FDI configuration.
10235 */
10236 pipe_config->base.adjusted_mode.crtc_clock =
10237 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10238 &pipe_config->fdi_m_n);
10239 }
10240
10241 /* Returns the currently programmed mode of the given encoder. */
10242 struct drm_display_mode *
10243 intel_encoder_current_mode(struct intel_encoder *encoder)
10244 {
10245 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10246 struct intel_crtc_state *crtc_state;
10247 struct drm_display_mode *mode;
10248 struct intel_crtc *crtc;
10249 enum pipe pipe;
10250
10251 if (!encoder->get_hw_state(encoder, &pipe))
10252 return NULL;
10253
10254 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10255
10256 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10257 if (!mode)
10258 return NULL;
10259
10260 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10261 if (!crtc_state) {
10262 kfree(mode);
10263 return NULL;
10264 }
10265
10266 crtc_state->base.crtc = &crtc->base;
10267
10268 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10269 kfree(crtc_state);
10270 kfree(mode);
10271 return NULL;
10272 }
10273
10274 encoder->get_config(encoder, crtc_state);
10275
10276 intel_mode_from_pipe_config(mode, crtc_state);
10277
10278 kfree(crtc_state);
10279
10280 return mode;
10281 }
10282
10283 static void intel_crtc_destroy(struct drm_crtc *crtc)
10284 {
10285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10286
10287 drm_crtc_cleanup(crtc);
10288 kfree(intel_crtc);
10289 }
10290
10291 /**
10292 * intel_wm_need_update - Check whether watermarks need updating
10293 * @plane: drm plane
10294 * @state: new plane state
10295 *
10296 * Check current plane state versus the new one to determine whether
10297 * watermarks need to be recalculated.
10298 *
10299 * Returns true or false.
10300 */
10301 static bool intel_wm_need_update(struct drm_plane *plane,
10302 struct drm_plane_state *state)
10303 {
10304 struct intel_plane_state *new = to_intel_plane_state(state);
10305 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10306
10307 /* Update watermarks on tiling or size changes. */
10308 if (new->base.visible != cur->base.visible)
10309 return true;
10310
10311 if (!cur->base.fb || !new->base.fb)
10312 return false;
10313
10314 if (cur->base.fb->modifier != new->base.fb->modifier ||
10315 cur->base.rotation != new->base.rotation ||
10316 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10317 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10318 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10319 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10320 return true;
10321
10322 return false;
10323 }
10324
10325 static bool needs_scaling(const struct intel_plane_state *state)
10326 {
10327 int src_w = drm_rect_width(&state->base.src) >> 16;
10328 int src_h = drm_rect_height(&state->base.src) >> 16;
10329 int dst_w = drm_rect_width(&state->base.dst);
10330 int dst_h = drm_rect_height(&state->base.dst);
10331
10332 return (src_w != dst_w || src_h != dst_h);
10333 }
10334
10335 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10336 struct drm_crtc_state *crtc_state,
10337 const struct intel_plane_state *old_plane_state,
10338 struct drm_plane_state *plane_state)
10339 {
10340 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10341 struct drm_crtc *crtc = crtc_state->crtc;
10342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10343 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10344 struct drm_device *dev = crtc->dev;
10345 struct drm_i915_private *dev_priv = to_i915(dev);
10346 bool mode_changed = needs_modeset(crtc_state);
10347 bool was_crtc_enabled = old_crtc_state->base.active;
10348 bool is_crtc_enabled = crtc_state->active;
10349 bool turn_off, turn_on, visible, was_visible;
10350 struct drm_framebuffer *fb = plane_state->fb;
10351 int ret;
10352
10353 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10354 ret = skl_update_scaler_plane(
10355 to_intel_crtc_state(crtc_state),
10356 to_intel_plane_state(plane_state));
10357 if (ret)
10358 return ret;
10359 }
10360
10361 was_visible = old_plane_state->base.visible;
10362 visible = plane_state->visible;
10363
10364 if (!was_crtc_enabled && WARN_ON(was_visible))
10365 was_visible = false;
10366
10367 /*
10368 * Visibility is calculated as if the crtc was on, but
10369 * after scaler setup everything depends on it being off
10370 * when the crtc isn't active.
10371 *
10372 * FIXME this is wrong for watermarks. Watermarks should also
10373 * be computed as if the pipe would be active. Perhaps move
10374 * per-plane wm computation to the .check_plane() hook, and
10375 * only combine the results from all planes in the current place?
10376 */
10377 if (!is_crtc_enabled) {
10378 plane_state->visible = visible = false;
10379 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10380 }
10381
10382 if (!was_visible && !visible)
10383 return 0;
10384
10385 if (fb != old_plane_state->base.fb)
10386 pipe_config->fb_changed = true;
10387
10388 turn_off = was_visible && (!visible || mode_changed);
10389 turn_on = visible && (!was_visible || mode_changed);
10390
10391 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10392 intel_crtc->base.base.id, intel_crtc->base.name,
10393 plane->base.base.id, plane->base.name,
10394 fb ? fb->base.id : -1);
10395
10396 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10397 plane->base.base.id, plane->base.name,
10398 was_visible, visible,
10399 turn_off, turn_on, mode_changed);
10400
10401 if (turn_on) {
10402 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10403 pipe_config->update_wm_pre = true;
10404
10405 /* must disable cxsr around plane enable/disable */
10406 if (plane->id != PLANE_CURSOR)
10407 pipe_config->disable_cxsr = true;
10408 } else if (turn_off) {
10409 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10410 pipe_config->update_wm_post = true;
10411
10412 /* must disable cxsr around plane enable/disable */
10413 if (plane->id != PLANE_CURSOR)
10414 pipe_config->disable_cxsr = true;
10415 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10416 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10417 /* FIXME bollocks */
10418 pipe_config->update_wm_pre = true;
10419 pipe_config->update_wm_post = true;
10420 }
10421 }
10422
10423 if (visible || was_visible)
10424 pipe_config->fb_bits |= plane->frontbuffer_bit;
10425
10426 /*
10427 * WaCxSRDisabledForSpriteScaling:ivb
10428 *
10429 * cstate->update_wm was already set above, so this flag will
10430 * take effect when we commit and program watermarks.
10431 */
10432 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10433 needs_scaling(to_intel_plane_state(plane_state)) &&
10434 !needs_scaling(old_plane_state))
10435 pipe_config->disable_lp_wm = true;
10436
10437 return 0;
10438 }
10439
10440 static bool encoders_cloneable(const struct intel_encoder *a,
10441 const struct intel_encoder *b)
10442 {
10443 /* masks could be asymmetric, so check both ways */
10444 return a == b || (a->cloneable & (1 << b->type) &&
10445 b->cloneable & (1 << a->type));
10446 }
10447
10448 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10449 struct intel_crtc *crtc,
10450 struct intel_encoder *encoder)
10451 {
10452 struct intel_encoder *source_encoder;
10453 struct drm_connector *connector;
10454 struct drm_connector_state *connector_state;
10455 int i;
10456
10457 for_each_new_connector_in_state(state, connector, connector_state, i) {
10458 if (connector_state->crtc != &crtc->base)
10459 continue;
10460
10461 source_encoder =
10462 to_intel_encoder(connector_state->best_encoder);
10463 if (!encoders_cloneable(encoder, source_encoder))
10464 return false;
10465 }
10466
10467 return true;
10468 }
10469
10470 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10471 struct drm_crtc_state *crtc_state)
10472 {
10473 struct drm_device *dev = crtc->dev;
10474 struct drm_i915_private *dev_priv = to_i915(dev);
10475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10476 struct intel_crtc_state *pipe_config =
10477 to_intel_crtc_state(crtc_state);
10478 struct drm_atomic_state *state = crtc_state->state;
10479 int ret;
10480 bool mode_changed = needs_modeset(crtc_state);
10481
10482 if (mode_changed && !crtc_state->active)
10483 pipe_config->update_wm_post = true;
10484
10485 if (mode_changed && crtc_state->enable &&
10486 dev_priv->display.crtc_compute_clock &&
10487 !WARN_ON(pipe_config->shared_dpll)) {
10488 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10489 pipe_config);
10490 if (ret)
10491 return ret;
10492 }
10493
10494 if (crtc_state->color_mgmt_changed) {
10495 ret = intel_color_check(crtc, crtc_state);
10496 if (ret)
10497 return ret;
10498
10499 /*
10500 * Changing color management on Intel hardware is
10501 * handled as part of planes update.
10502 */
10503 crtc_state->planes_changed = true;
10504 }
10505
10506 ret = 0;
10507 if (dev_priv->display.compute_pipe_wm) {
10508 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10509 if (ret) {
10510 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10511 return ret;
10512 }
10513 }
10514
10515 if (dev_priv->display.compute_intermediate_wm &&
10516 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10517 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10518 return 0;
10519
10520 /*
10521 * Calculate 'intermediate' watermarks that satisfy both the
10522 * old state and the new state. We can program these
10523 * immediately.
10524 */
10525 ret = dev_priv->display.compute_intermediate_wm(dev,
10526 intel_crtc,
10527 pipe_config);
10528 if (ret) {
10529 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10530 return ret;
10531 }
10532 } else if (dev_priv->display.compute_intermediate_wm) {
10533 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10534 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10535 }
10536
10537 if (INTEL_GEN(dev_priv) >= 9) {
10538 if (mode_changed)
10539 ret = skl_update_scaler_crtc(pipe_config);
10540
10541 if (!ret)
10542 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10543 pipe_config);
10544 if (!ret)
10545 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10546 pipe_config);
10547 }
10548
10549 return ret;
10550 }
10551
10552 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10553 .atomic_begin = intel_begin_crtc_commit,
10554 .atomic_flush = intel_finish_crtc_commit,
10555 .atomic_check = intel_crtc_atomic_check,
10556 };
10557
10558 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10559 {
10560 struct intel_connector *connector;
10561 struct drm_connector_list_iter conn_iter;
10562
10563 drm_connector_list_iter_begin(dev, &conn_iter);
10564 for_each_intel_connector_iter(connector, &conn_iter) {
10565 if (connector->base.state->crtc)
10566 drm_connector_unreference(&connector->base);
10567
10568 if (connector->base.encoder) {
10569 connector->base.state->best_encoder =
10570 connector->base.encoder;
10571 connector->base.state->crtc =
10572 connector->base.encoder->crtc;
10573
10574 drm_connector_reference(&connector->base);
10575 } else {
10576 connector->base.state->best_encoder = NULL;
10577 connector->base.state->crtc = NULL;
10578 }
10579 }
10580 drm_connector_list_iter_end(&conn_iter);
10581 }
10582
10583 static void
10584 connected_sink_compute_bpp(struct intel_connector *connector,
10585 struct intel_crtc_state *pipe_config)
10586 {
10587 const struct drm_display_info *info = &connector->base.display_info;
10588 int bpp = pipe_config->pipe_bpp;
10589
10590 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10591 connector->base.base.id,
10592 connector->base.name);
10593
10594 /* Don't use an invalid EDID bpc value */
10595 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10596 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10597 bpp, info->bpc * 3);
10598 pipe_config->pipe_bpp = info->bpc * 3;
10599 }
10600
10601 /* Clamp bpp to 8 on screens without EDID 1.4 */
10602 if (info->bpc == 0 && bpp > 24) {
10603 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10604 bpp);
10605 pipe_config->pipe_bpp = 24;
10606 }
10607 }
10608
10609 static int
10610 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10611 struct intel_crtc_state *pipe_config)
10612 {
10613 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10614 struct drm_atomic_state *state;
10615 struct drm_connector *connector;
10616 struct drm_connector_state *connector_state;
10617 int bpp, i;
10618
10619 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10620 IS_CHERRYVIEW(dev_priv)))
10621 bpp = 10*3;
10622 else if (INTEL_GEN(dev_priv) >= 5)
10623 bpp = 12*3;
10624 else
10625 bpp = 8*3;
10626
10627
10628 pipe_config->pipe_bpp = bpp;
10629
10630 state = pipe_config->base.state;
10631
10632 /* Clamp display bpp to EDID value */
10633 for_each_new_connector_in_state(state, connector, connector_state, i) {
10634 if (connector_state->crtc != &crtc->base)
10635 continue;
10636
10637 connected_sink_compute_bpp(to_intel_connector(connector),
10638 pipe_config);
10639 }
10640
10641 return bpp;
10642 }
10643
10644 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10645 {
10646 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10647 "type: 0x%x flags: 0x%x\n",
10648 mode->crtc_clock,
10649 mode->crtc_hdisplay, mode->crtc_hsync_start,
10650 mode->crtc_hsync_end, mode->crtc_htotal,
10651 mode->crtc_vdisplay, mode->crtc_vsync_start,
10652 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10653 }
10654
10655 static inline void
10656 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10657 unsigned int lane_count, struct intel_link_m_n *m_n)
10658 {
10659 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10660 id, lane_count,
10661 m_n->gmch_m, m_n->gmch_n,
10662 m_n->link_m, m_n->link_n, m_n->tu);
10663 }
10664
10665 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10666 struct intel_crtc_state *pipe_config,
10667 const char *context)
10668 {
10669 struct drm_device *dev = crtc->base.dev;
10670 struct drm_i915_private *dev_priv = to_i915(dev);
10671 struct drm_plane *plane;
10672 struct intel_plane *intel_plane;
10673 struct intel_plane_state *state;
10674 struct drm_framebuffer *fb;
10675
10676 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10677 crtc->base.base.id, crtc->base.name, context);
10678
10679 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10680 transcoder_name(pipe_config->cpu_transcoder),
10681 pipe_config->pipe_bpp, pipe_config->dither);
10682
10683 if (pipe_config->has_pch_encoder)
10684 intel_dump_m_n_config(pipe_config, "fdi",
10685 pipe_config->fdi_lanes,
10686 &pipe_config->fdi_m_n);
10687
10688 if (pipe_config->ycbcr420)
10689 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10690
10691 if (intel_crtc_has_dp_encoder(pipe_config)) {
10692 intel_dump_m_n_config(pipe_config, "dp m_n",
10693 pipe_config->lane_count, &pipe_config->dp_m_n);
10694 if (pipe_config->has_drrs)
10695 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10696 pipe_config->lane_count,
10697 &pipe_config->dp_m2_n2);
10698 }
10699
10700 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10701 pipe_config->has_audio, pipe_config->has_infoframe);
10702
10703 DRM_DEBUG_KMS("requested mode:\n");
10704 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10705 DRM_DEBUG_KMS("adjusted mode:\n");
10706 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10707 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10708 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10709 pipe_config->port_clock,
10710 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10711 pipe_config->pixel_rate);
10712
10713 if (INTEL_GEN(dev_priv) >= 9)
10714 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10715 crtc->num_scalers,
10716 pipe_config->scaler_state.scaler_users,
10717 pipe_config->scaler_state.scaler_id);
10718
10719 if (HAS_GMCH_DISPLAY(dev_priv))
10720 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10721 pipe_config->gmch_pfit.control,
10722 pipe_config->gmch_pfit.pgm_ratios,
10723 pipe_config->gmch_pfit.lvds_border_bits);
10724 else
10725 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10726 pipe_config->pch_pfit.pos,
10727 pipe_config->pch_pfit.size,
10728 enableddisabled(pipe_config->pch_pfit.enabled));
10729
10730 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10731 pipe_config->ips_enabled, pipe_config->double_wide);
10732
10733 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10734
10735 DRM_DEBUG_KMS("planes on this crtc\n");
10736 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10737 struct drm_format_name_buf format_name;
10738 intel_plane = to_intel_plane(plane);
10739 if (intel_plane->pipe != crtc->pipe)
10740 continue;
10741
10742 state = to_intel_plane_state(plane->state);
10743 fb = state->base.fb;
10744 if (!fb) {
10745 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10746 plane->base.id, plane->name, state->scaler_id);
10747 continue;
10748 }
10749
10750 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10751 plane->base.id, plane->name,
10752 fb->base.id, fb->width, fb->height,
10753 drm_get_format_name(fb->format->format, &format_name));
10754 if (INTEL_GEN(dev_priv) >= 9)
10755 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10756 state->scaler_id,
10757 state->base.src.x1 >> 16,
10758 state->base.src.y1 >> 16,
10759 drm_rect_width(&state->base.src) >> 16,
10760 drm_rect_height(&state->base.src) >> 16,
10761 state->base.dst.x1, state->base.dst.y1,
10762 drm_rect_width(&state->base.dst),
10763 drm_rect_height(&state->base.dst));
10764 }
10765 }
10766
10767 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10768 {
10769 struct drm_device *dev = state->dev;
10770 struct drm_connector *connector;
10771 struct drm_connector_list_iter conn_iter;
10772 unsigned int used_ports = 0;
10773 unsigned int used_mst_ports = 0;
10774
10775 /*
10776 * Walk the connector list instead of the encoder
10777 * list to detect the problem on ddi platforms
10778 * where there's just one encoder per digital port.
10779 */
10780 drm_connector_list_iter_begin(dev, &conn_iter);
10781 drm_for_each_connector_iter(connector, &conn_iter) {
10782 struct drm_connector_state *connector_state;
10783 struct intel_encoder *encoder;
10784
10785 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10786 if (!connector_state)
10787 connector_state = connector->state;
10788
10789 if (!connector_state->best_encoder)
10790 continue;
10791
10792 encoder = to_intel_encoder(connector_state->best_encoder);
10793
10794 WARN_ON(!connector_state->crtc);
10795
10796 switch (encoder->type) {
10797 unsigned int port_mask;
10798 case INTEL_OUTPUT_UNKNOWN:
10799 if (WARN_ON(!HAS_DDI(to_i915(dev))))
10800 break;
10801 case INTEL_OUTPUT_DP:
10802 case INTEL_OUTPUT_HDMI:
10803 case INTEL_OUTPUT_EDP:
10804 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10805
10806 /* the same port mustn't appear more than once */
10807 if (used_ports & port_mask)
10808 return false;
10809
10810 used_ports |= port_mask;
10811 break;
10812 case INTEL_OUTPUT_DP_MST:
10813 used_mst_ports |=
10814 1 << enc_to_mst(&encoder->base)->primary->port;
10815 break;
10816 default:
10817 break;
10818 }
10819 }
10820 drm_connector_list_iter_end(&conn_iter);
10821
10822 /* can't mix MST and SST/HDMI on the same port */
10823 if (used_ports & used_mst_ports)
10824 return false;
10825
10826 return true;
10827 }
10828
10829 static void
10830 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10831 {
10832 struct drm_i915_private *dev_priv =
10833 to_i915(crtc_state->base.crtc->dev);
10834 struct intel_crtc_scaler_state scaler_state;
10835 struct intel_dpll_hw_state dpll_hw_state;
10836 struct intel_shared_dpll *shared_dpll;
10837 struct intel_crtc_wm_state wm_state;
10838 bool force_thru, ips_force_disable;
10839
10840 /* FIXME: before the switch to atomic started, a new pipe_config was
10841 * kzalloc'd. Code that depends on any field being zero should be
10842 * fixed, so that the crtc_state can be safely duplicated. For now,
10843 * only fields that are know to not cause problems are preserved. */
10844
10845 scaler_state = crtc_state->scaler_state;
10846 shared_dpll = crtc_state->shared_dpll;
10847 dpll_hw_state = crtc_state->dpll_hw_state;
10848 force_thru = crtc_state->pch_pfit.force_thru;
10849 ips_force_disable = crtc_state->ips_force_disable;
10850 if (IS_G4X(dev_priv) ||
10851 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10852 wm_state = crtc_state->wm;
10853
10854 /* Keep base drm_crtc_state intact, only clear our extended struct */
10855 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10856 memset(&crtc_state->base + 1, 0,
10857 sizeof(*crtc_state) - sizeof(crtc_state->base));
10858
10859 crtc_state->scaler_state = scaler_state;
10860 crtc_state->shared_dpll = shared_dpll;
10861 crtc_state->dpll_hw_state = dpll_hw_state;
10862 crtc_state->pch_pfit.force_thru = force_thru;
10863 crtc_state->ips_force_disable = ips_force_disable;
10864 if (IS_G4X(dev_priv) ||
10865 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10866 crtc_state->wm = wm_state;
10867 }
10868
10869 static int
10870 intel_modeset_pipe_config(struct drm_crtc *crtc,
10871 struct intel_crtc_state *pipe_config)
10872 {
10873 struct drm_atomic_state *state = pipe_config->base.state;
10874 struct intel_encoder *encoder;
10875 struct drm_connector *connector;
10876 struct drm_connector_state *connector_state;
10877 int base_bpp, ret = -EINVAL;
10878 int i;
10879 bool retry = true;
10880
10881 clear_intel_crtc_state(pipe_config);
10882
10883 pipe_config->cpu_transcoder =
10884 (enum transcoder) to_intel_crtc(crtc)->pipe;
10885
10886 /*
10887 * Sanitize sync polarity flags based on requested ones. If neither
10888 * positive or negative polarity is requested, treat this as meaning
10889 * negative polarity.
10890 */
10891 if (!(pipe_config->base.adjusted_mode.flags &
10892 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10893 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10894
10895 if (!(pipe_config->base.adjusted_mode.flags &
10896 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10897 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10898
10899 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10900 pipe_config);
10901 if (base_bpp < 0)
10902 goto fail;
10903
10904 /*
10905 * Determine the real pipe dimensions. Note that stereo modes can
10906 * increase the actual pipe size due to the frame doubling and
10907 * insertion of additional space for blanks between the frame. This
10908 * is stored in the crtc timings. We use the requested mode to do this
10909 * computation to clearly distinguish it from the adjusted mode, which
10910 * can be changed by the connectors in the below retry loop.
10911 */
10912 drm_mode_get_hv_timing(&pipe_config->base.mode,
10913 &pipe_config->pipe_src_w,
10914 &pipe_config->pipe_src_h);
10915
10916 for_each_new_connector_in_state(state, connector, connector_state, i) {
10917 if (connector_state->crtc != crtc)
10918 continue;
10919
10920 encoder = to_intel_encoder(connector_state->best_encoder);
10921
10922 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10923 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10924 goto fail;
10925 }
10926
10927 /*
10928 * Determine output_types before calling the .compute_config()
10929 * hooks so that the hooks can use this information safely.
10930 */
10931 pipe_config->output_types |= 1 << encoder->type;
10932 }
10933
10934 encoder_retry:
10935 /* Ensure the port clock defaults are reset when retrying. */
10936 pipe_config->port_clock = 0;
10937 pipe_config->pixel_multiplier = 1;
10938
10939 /* Fill in default crtc timings, allow encoders to overwrite them. */
10940 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10941 CRTC_STEREO_DOUBLE);
10942
10943 /* Pass our mode to the connectors and the CRTC to give them a chance to
10944 * adjust it according to limitations or connector properties, and also
10945 * a chance to reject the mode entirely.
10946 */
10947 for_each_new_connector_in_state(state, connector, connector_state, i) {
10948 if (connector_state->crtc != crtc)
10949 continue;
10950
10951 encoder = to_intel_encoder(connector_state->best_encoder);
10952
10953 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10954 DRM_DEBUG_KMS("Encoder config failure\n");
10955 goto fail;
10956 }
10957 }
10958
10959 /* Set default port clock if not overwritten by the encoder. Needs to be
10960 * done afterwards in case the encoder adjusts the mode. */
10961 if (!pipe_config->port_clock)
10962 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10963 * pipe_config->pixel_multiplier;
10964
10965 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10966 if (ret < 0) {
10967 DRM_DEBUG_KMS("CRTC fixup failed\n");
10968 goto fail;
10969 }
10970
10971 if (ret == RETRY) {
10972 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10973 ret = -EINVAL;
10974 goto fail;
10975 }
10976
10977 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10978 retry = false;
10979 goto encoder_retry;
10980 }
10981
10982 /* Dithering seems to not pass-through bits correctly when it should, so
10983 * only enable it on 6bpc panels and when its not a compliance
10984 * test requesting 6bpc video pattern.
10985 */
10986 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10987 !pipe_config->dither_force_disable;
10988 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10989 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10990
10991 fail:
10992 return ret;
10993 }
10994
10995 static void
10996 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10997 {
10998 struct drm_crtc *crtc;
10999 struct drm_crtc_state *new_crtc_state;
11000 int i;
11001
11002 /* Double check state. */
11003 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11004 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11005
11006 /*
11007 * Update legacy state to satisfy fbc code. This can
11008 * be removed when fbc uses the atomic state.
11009 */
11010 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11011 struct drm_plane_state *plane_state = crtc->primary->state;
11012
11013 crtc->primary->fb = plane_state->fb;
11014 crtc->x = plane_state->src_x >> 16;
11015 crtc->y = plane_state->src_y >> 16;
11016 }
11017 }
11018 }
11019
11020 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11021 {
11022 int diff;
11023
11024 if (clock1 == clock2)
11025 return true;
11026
11027 if (!clock1 || !clock2)
11028 return false;
11029
11030 diff = abs(clock1 - clock2);
11031
11032 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11033 return true;
11034
11035 return false;
11036 }
11037
11038 static bool
11039 intel_compare_m_n(unsigned int m, unsigned int n,
11040 unsigned int m2, unsigned int n2,
11041 bool exact)
11042 {
11043 if (m == m2 && n == n2)
11044 return true;
11045
11046 if (exact || !m || !n || !m2 || !n2)
11047 return false;
11048
11049 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11050
11051 if (n > n2) {
11052 while (n > n2) {
11053 m2 <<= 1;
11054 n2 <<= 1;
11055 }
11056 } else if (n < n2) {
11057 while (n < n2) {
11058 m <<= 1;
11059 n <<= 1;
11060 }
11061 }
11062
11063 if (n != n2)
11064 return false;
11065
11066 return intel_fuzzy_clock_check(m, m2);
11067 }
11068
11069 static bool
11070 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11071 struct intel_link_m_n *m2_n2,
11072 bool adjust)
11073 {
11074 if (m_n->tu == m2_n2->tu &&
11075 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11076 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11077 intel_compare_m_n(m_n->link_m, m_n->link_n,
11078 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11079 if (adjust)
11080 *m2_n2 = *m_n;
11081
11082 return true;
11083 }
11084
11085 return false;
11086 }
11087
11088 static void __printf(3, 4)
11089 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11090 {
11091 char *level;
11092 unsigned int category;
11093 struct va_format vaf;
11094 va_list args;
11095
11096 if (adjust) {
11097 level = KERN_DEBUG;
11098 category = DRM_UT_KMS;
11099 } else {
11100 level = KERN_ERR;
11101 category = DRM_UT_NONE;
11102 }
11103
11104 va_start(args, format);
11105 vaf.fmt = format;
11106 vaf.va = &args;
11107
11108 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11109
11110 va_end(args);
11111 }
11112
11113 static bool
11114 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11115 struct intel_crtc_state *current_config,
11116 struct intel_crtc_state *pipe_config,
11117 bool adjust)
11118 {
11119 bool ret = true;
11120
11121 #define PIPE_CONF_CHECK_X(name) \
11122 if (current_config->name != pipe_config->name) { \
11123 pipe_config_err(adjust, __stringify(name), \
11124 "(expected 0x%08x, found 0x%08x)\n", \
11125 current_config->name, \
11126 pipe_config->name); \
11127 ret = false; \
11128 }
11129
11130 #define PIPE_CONF_CHECK_I(name) \
11131 if (current_config->name != pipe_config->name) { \
11132 pipe_config_err(adjust, __stringify(name), \
11133 "(expected %i, found %i)\n", \
11134 current_config->name, \
11135 pipe_config->name); \
11136 ret = false; \
11137 }
11138
11139 #define PIPE_CONF_CHECK_P(name) \
11140 if (current_config->name != pipe_config->name) { \
11141 pipe_config_err(adjust, __stringify(name), \
11142 "(expected %p, found %p)\n", \
11143 current_config->name, \
11144 pipe_config->name); \
11145 ret = false; \
11146 }
11147
11148 #define PIPE_CONF_CHECK_M_N(name) \
11149 if (!intel_compare_link_m_n(&current_config->name, \
11150 &pipe_config->name,\
11151 adjust)) { \
11152 pipe_config_err(adjust, __stringify(name), \
11153 "(expected tu %i gmch %i/%i link %i/%i, " \
11154 "found tu %i, gmch %i/%i link %i/%i)\n", \
11155 current_config->name.tu, \
11156 current_config->name.gmch_m, \
11157 current_config->name.gmch_n, \
11158 current_config->name.link_m, \
11159 current_config->name.link_n, \
11160 pipe_config->name.tu, \
11161 pipe_config->name.gmch_m, \
11162 pipe_config->name.gmch_n, \
11163 pipe_config->name.link_m, \
11164 pipe_config->name.link_n); \
11165 ret = false; \
11166 }
11167
11168 /* This is required for BDW+ where there is only one set of registers for
11169 * switching between high and low RR.
11170 * This macro can be used whenever a comparison has to be made between one
11171 * hw state and multiple sw state variables.
11172 */
11173 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11174 if (!intel_compare_link_m_n(&current_config->name, \
11175 &pipe_config->name, adjust) && \
11176 !intel_compare_link_m_n(&current_config->alt_name, \
11177 &pipe_config->name, adjust)) { \
11178 pipe_config_err(adjust, __stringify(name), \
11179 "(expected tu %i gmch %i/%i link %i/%i, " \
11180 "or tu %i gmch %i/%i link %i/%i, " \
11181 "found tu %i, gmch %i/%i link %i/%i)\n", \
11182 current_config->name.tu, \
11183 current_config->name.gmch_m, \
11184 current_config->name.gmch_n, \
11185 current_config->name.link_m, \
11186 current_config->name.link_n, \
11187 current_config->alt_name.tu, \
11188 current_config->alt_name.gmch_m, \
11189 current_config->alt_name.gmch_n, \
11190 current_config->alt_name.link_m, \
11191 current_config->alt_name.link_n, \
11192 pipe_config->name.tu, \
11193 pipe_config->name.gmch_m, \
11194 pipe_config->name.gmch_n, \
11195 pipe_config->name.link_m, \
11196 pipe_config->name.link_n); \
11197 ret = false; \
11198 }
11199
11200 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11201 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11202 pipe_config_err(adjust, __stringify(name), \
11203 "(%x) (expected %i, found %i)\n", \
11204 (mask), \
11205 current_config->name & (mask), \
11206 pipe_config->name & (mask)); \
11207 ret = false; \
11208 }
11209
11210 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11211 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11212 pipe_config_err(adjust, __stringify(name), \
11213 "(expected %i, found %i)\n", \
11214 current_config->name, \
11215 pipe_config->name); \
11216 ret = false; \
11217 }
11218
11219 #define PIPE_CONF_QUIRK(quirk) \
11220 ((current_config->quirks | pipe_config->quirks) & (quirk))
11221
11222 PIPE_CONF_CHECK_I(cpu_transcoder);
11223
11224 PIPE_CONF_CHECK_I(has_pch_encoder);
11225 PIPE_CONF_CHECK_I(fdi_lanes);
11226 PIPE_CONF_CHECK_M_N(fdi_m_n);
11227
11228 PIPE_CONF_CHECK_I(lane_count);
11229 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11230
11231 if (INTEL_GEN(dev_priv) < 8) {
11232 PIPE_CONF_CHECK_M_N(dp_m_n);
11233
11234 if (current_config->has_drrs)
11235 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11236 } else
11237 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11238
11239 PIPE_CONF_CHECK_X(output_types);
11240
11241 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11242 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11243 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11244 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11245 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11246 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11247
11248 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11249 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11250 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11251 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11252 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11253 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11254
11255 PIPE_CONF_CHECK_I(pixel_multiplier);
11256 PIPE_CONF_CHECK_I(has_hdmi_sink);
11257 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11258 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11259 PIPE_CONF_CHECK_I(limited_color_range);
11260
11261 PIPE_CONF_CHECK_I(hdmi_scrambling);
11262 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11263 PIPE_CONF_CHECK_I(has_infoframe);
11264 PIPE_CONF_CHECK_I(ycbcr420);
11265
11266 PIPE_CONF_CHECK_I(has_audio);
11267
11268 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11269 DRM_MODE_FLAG_INTERLACE);
11270
11271 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11272 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11273 DRM_MODE_FLAG_PHSYNC);
11274 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11275 DRM_MODE_FLAG_NHSYNC);
11276 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11277 DRM_MODE_FLAG_PVSYNC);
11278 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11279 DRM_MODE_FLAG_NVSYNC);
11280 }
11281
11282 PIPE_CONF_CHECK_X(gmch_pfit.control);
11283 /* pfit ratios are autocomputed by the hw on gen4+ */
11284 if (INTEL_GEN(dev_priv) < 4)
11285 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11286 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11287
11288 if (!adjust) {
11289 PIPE_CONF_CHECK_I(pipe_src_w);
11290 PIPE_CONF_CHECK_I(pipe_src_h);
11291
11292 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11293 if (current_config->pch_pfit.enabled) {
11294 PIPE_CONF_CHECK_X(pch_pfit.pos);
11295 PIPE_CONF_CHECK_X(pch_pfit.size);
11296 }
11297
11298 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11299 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11300 }
11301
11302 /* BDW+ don't expose a synchronous way to read the state */
11303 if (IS_HASWELL(dev_priv))
11304 PIPE_CONF_CHECK_I(ips_enabled);
11305
11306 PIPE_CONF_CHECK_I(double_wide);
11307
11308 PIPE_CONF_CHECK_P(shared_dpll);
11309 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11310 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11311 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11312 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11313 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11314 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11315 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11316 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11317 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11318 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11319 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11320 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11321 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11322 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11323 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11324 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11325 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11326 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11327 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11328 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11329 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11330
11331 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11332 PIPE_CONF_CHECK_X(dsi_pll.div);
11333
11334 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11335 PIPE_CONF_CHECK_I(pipe_bpp);
11336
11337 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11338 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11339
11340 #undef PIPE_CONF_CHECK_X
11341 #undef PIPE_CONF_CHECK_I
11342 #undef PIPE_CONF_CHECK_P
11343 #undef PIPE_CONF_CHECK_FLAGS
11344 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11345 #undef PIPE_CONF_QUIRK
11346
11347 return ret;
11348 }
11349
11350 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11351 const struct intel_crtc_state *pipe_config)
11352 {
11353 if (pipe_config->has_pch_encoder) {
11354 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11355 &pipe_config->fdi_m_n);
11356 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11357
11358 /*
11359 * FDI already provided one idea for the dotclock.
11360 * Yell if the encoder disagrees.
11361 */
11362 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11363 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11364 fdi_dotclock, dotclock);
11365 }
11366 }
11367
11368 static void verify_wm_state(struct drm_crtc *crtc,
11369 struct drm_crtc_state *new_state)
11370 {
11371 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11372 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11373 struct skl_pipe_wm hw_wm, *sw_wm;
11374 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11375 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11377 const enum pipe pipe = intel_crtc->pipe;
11378 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11379
11380 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11381 return;
11382
11383 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11384 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11385
11386 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11387 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11388
11389 /* planes */
11390 for_each_universal_plane(dev_priv, pipe, plane) {
11391 hw_plane_wm = &hw_wm.planes[plane];
11392 sw_plane_wm = &sw_wm->planes[plane];
11393
11394 /* Watermarks */
11395 for (level = 0; level <= max_level; level++) {
11396 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11397 &sw_plane_wm->wm[level]))
11398 continue;
11399
11400 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11401 pipe_name(pipe), plane + 1, level,
11402 sw_plane_wm->wm[level].plane_en,
11403 sw_plane_wm->wm[level].plane_res_b,
11404 sw_plane_wm->wm[level].plane_res_l,
11405 hw_plane_wm->wm[level].plane_en,
11406 hw_plane_wm->wm[level].plane_res_b,
11407 hw_plane_wm->wm[level].plane_res_l);
11408 }
11409
11410 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11411 &sw_plane_wm->trans_wm)) {
11412 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11413 pipe_name(pipe), plane + 1,
11414 sw_plane_wm->trans_wm.plane_en,
11415 sw_plane_wm->trans_wm.plane_res_b,
11416 sw_plane_wm->trans_wm.plane_res_l,
11417 hw_plane_wm->trans_wm.plane_en,
11418 hw_plane_wm->trans_wm.plane_res_b,
11419 hw_plane_wm->trans_wm.plane_res_l);
11420 }
11421
11422 /* DDB */
11423 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11424 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11425
11426 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11427 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11428 pipe_name(pipe), plane + 1,
11429 sw_ddb_entry->start, sw_ddb_entry->end,
11430 hw_ddb_entry->start, hw_ddb_entry->end);
11431 }
11432 }
11433
11434 /*
11435 * cursor
11436 * If the cursor plane isn't active, we may not have updated it's ddb
11437 * allocation. In that case since the ddb allocation will be updated
11438 * once the plane becomes visible, we can skip this check
11439 */
11440 if (1) {
11441 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11442 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11443
11444 /* Watermarks */
11445 for (level = 0; level <= max_level; level++) {
11446 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11447 &sw_plane_wm->wm[level]))
11448 continue;
11449
11450 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11451 pipe_name(pipe), level,
11452 sw_plane_wm->wm[level].plane_en,
11453 sw_plane_wm->wm[level].plane_res_b,
11454 sw_plane_wm->wm[level].plane_res_l,
11455 hw_plane_wm->wm[level].plane_en,
11456 hw_plane_wm->wm[level].plane_res_b,
11457 hw_plane_wm->wm[level].plane_res_l);
11458 }
11459
11460 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11461 &sw_plane_wm->trans_wm)) {
11462 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11463 pipe_name(pipe),
11464 sw_plane_wm->trans_wm.plane_en,
11465 sw_plane_wm->trans_wm.plane_res_b,
11466 sw_plane_wm->trans_wm.plane_res_l,
11467 hw_plane_wm->trans_wm.plane_en,
11468 hw_plane_wm->trans_wm.plane_res_b,
11469 hw_plane_wm->trans_wm.plane_res_l);
11470 }
11471
11472 /* DDB */
11473 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11474 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11475
11476 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11477 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11478 pipe_name(pipe),
11479 sw_ddb_entry->start, sw_ddb_entry->end,
11480 hw_ddb_entry->start, hw_ddb_entry->end);
11481 }
11482 }
11483 }
11484
11485 static void
11486 verify_connector_state(struct drm_device *dev,
11487 struct drm_atomic_state *state,
11488 struct drm_crtc *crtc)
11489 {
11490 struct drm_connector *connector;
11491 struct drm_connector_state *new_conn_state;
11492 int i;
11493
11494 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11495 struct drm_encoder *encoder = connector->encoder;
11496 struct drm_crtc_state *crtc_state = NULL;
11497
11498 if (new_conn_state->crtc != crtc)
11499 continue;
11500
11501 if (crtc)
11502 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11503
11504 intel_connector_verify_state(crtc_state, new_conn_state);
11505
11506 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11507 "connector's atomic encoder doesn't match legacy encoder\n");
11508 }
11509 }
11510
11511 static void
11512 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11513 {
11514 struct intel_encoder *encoder;
11515 struct drm_connector *connector;
11516 struct drm_connector_state *old_conn_state, *new_conn_state;
11517 int i;
11518
11519 for_each_intel_encoder(dev, encoder) {
11520 bool enabled = false, found = false;
11521 enum pipe pipe;
11522
11523 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11524 encoder->base.base.id,
11525 encoder->base.name);
11526
11527 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11528 new_conn_state, i) {
11529 if (old_conn_state->best_encoder == &encoder->base)
11530 found = true;
11531
11532 if (new_conn_state->best_encoder != &encoder->base)
11533 continue;
11534 found = enabled = true;
11535
11536 I915_STATE_WARN(new_conn_state->crtc !=
11537 encoder->base.crtc,
11538 "connector's crtc doesn't match encoder crtc\n");
11539 }
11540
11541 if (!found)
11542 continue;
11543
11544 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11545 "encoder's enabled state mismatch "
11546 "(expected %i, found %i)\n",
11547 !!encoder->base.crtc, enabled);
11548
11549 if (!encoder->base.crtc) {
11550 bool active;
11551
11552 active = encoder->get_hw_state(encoder, &pipe);
11553 I915_STATE_WARN(active,
11554 "encoder detached but still enabled on pipe %c.\n",
11555 pipe_name(pipe));
11556 }
11557 }
11558 }
11559
11560 static void
11561 verify_crtc_state(struct drm_crtc *crtc,
11562 struct drm_crtc_state *old_crtc_state,
11563 struct drm_crtc_state *new_crtc_state)
11564 {
11565 struct drm_device *dev = crtc->dev;
11566 struct drm_i915_private *dev_priv = to_i915(dev);
11567 struct intel_encoder *encoder;
11568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11569 struct intel_crtc_state *pipe_config, *sw_config;
11570 struct drm_atomic_state *old_state;
11571 bool active;
11572
11573 old_state = old_crtc_state->state;
11574 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11575 pipe_config = to_intel_crtc_state(old_crtc_state);
11576 memset(pipe_config, 0, sizeof(*pipe_config));
11577 pipe_config->base.crtc = crtc;
11578 pipe_config->base.state = old_state;
11579
11580 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11581
11582 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11583
11584 /* we keep both pipes enabled on 830 */
11585 if (IS_I830(dev_priv))
11586 active = new_crtc_state->active;
11587
11588 I915_STATE_WARN(new_crtc_state->active != active,
11589 "crtc active state doesn't match with hw state "
11590 "(expected %i, found %i)\n", new_crtc_state->active, active);
11591
11592 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11593 "transitional active state does not match atomic hw state "
11594 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11595
11596 for_each_encoder_on_crtc(dev, crtc, encoder) {
11597 enum pipe pipe;
11598
11599 active = encoder->get_hw_state(encoder, &pipe);
11600 I915_STATE_WARN(active != new_crtc_state->active,
11601 "[ENCODER:%i] active %i with crtc active %i\n",
11602 encoder->base.base.id, active, new_crtc_state->active);
11603
11604 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11605 "Encoder connected to wrong pipe %c\n",
11606 pipe_name(pipe));
11607
11608 if (active) {
11609 pipe_config->output_types |= 1 << encoder->type;
11610 encoder->get_config(encoder, pipe_config);
11611 }
11612 }
11613
11614 intel_crtc_compute_pixel_rate(pipe_config);
11615
11616 if (!new_crtc_state->active)
11617 return;
11618
11619 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11620
11621 sw_config = to_intel_crtc_state(new_crtc_state);
11622 if (!intel_pipe_config_compare(dev_priv, sw_config,
11623 pipe_config, false)) {
11624 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11625 intel_dump_pipe_config(intel_crtc, pipe_config,
11626 "[hw state]");
11627 intel_dump_pipe_config(intel_crtc, sw_config,
11628 "[sw state]");
11629 }
11630 }
11631
11632 static void
11633 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11634 struct intel_shared_dpll *pll,
11635 struct drm_crtc *crtc,
11636 struct drm_crtc_state *new_state)
11637 {
11638 struct intel_dpll_hw_state dpll_hw_state;
11639 unsigned crtc_mask;
11640 bool active;
11641
11642 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11643
11644 DRM_DEBUG_KMS("%s\n", pll->name);
11645
11646 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11647
11648 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11649 I915_STATE_WARN(!pll->on && pll->active_mask,
11650 "pll in active use but not on in sw tracking\n");
11651 I915_STATE_WARN(pll->on && !pll->active_mask,
11652 "pll is on but not used by any active crtc\n");
11653 I915_STATE_WARN(pll->on != active,
11654 "pll on state mismatch (expected %i, found %i)\n",
11655 pll->on, active);
11656 }
11657
11658 if (!crtc) {
11659 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11660 "more active pll users than references: %x vs %x\n",
11661 pll->active_mask, pll->state.crtc_mask);
11662
11663 return;
11664 }
11665
11666 crtc_mask = 1 << drm_crtc_index(crtc);
11667
11668 if (new_state->active)
11669 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11670 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11671 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11672 else
11673 I915_STATE_WARN(pll->active_mask & crtc_mask,
11674 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11675 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11676
11677 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11678 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11679 crtc_mask, pll->state.crtc_mask);
11680
11681 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11682 &dpll_hw_state,
11683 sizeof(dpll_hw_state)),
11684 "pll hw state mismatch\n");
11685 }
11686
11687 static void
11688 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11689 struct drm_crtc_state *old_crtc_state,
11690 struct drm_crtc_state *new_crtc_state)
11691 {
11692 struct drm_i915_private *dev_priv = to_i915(dev);
11693 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11694 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11695
11696 if (new_state->shared_dpll)
11697 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11698
11699 if (old_state->shared_dpll &&
11700 old_state->shared_dpll != new_state->shared_dpll) {
11701 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11702 struct intel_shared_dpll *pll = old_state->shared_dpll;
11703
11704 I915_STATE_WARN(pll->active_mask & crtc_mask,
11705 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11706 pipe_name(drm_crtc_index(crtc)));
11707 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11708 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11709 pipe_name(drm_crtc_index(crtc)));
11710 }
11711 }
11712
11713 static void
11714 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11715 struct drm_atomic_state *state,
11716 struct drm_crtc_state *old_state,
11717 struct drm_crtc_state *new_state)
11718 {
11719 if (!needs_modeset(new_state) &&
11720 !to_intel_crtc_state(new_state)->update_pipe)
11721 return;
11722
11723 verify_wm_state(crtc, new_state);
11724 verify_connector_state(crtc->dev, state, crtc);
11725 verify_crtc_state(crtc, old_state, new_state);
11726 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11727 }
11728
11729 static void
11730 verify_disabled_dpll_state(struct drm_device *dev)
11731 {
11732 struct drm_i915_private *dev_priv = to_i915(dev);
11733 int i;
11734
11735 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11736 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11737 }
11738
11739 static void
11740 intel_modeset_verify_disabled(struct drm_device *dev,
11741 struct drm_atomic_state *state)
11742 {
11743 verify_encoder_state(dev, state);
11744 verify_connector_state(dev, state, NULL);
11745 verify_disabled_dpll_state(dev);
11746 }
11747
11748 static void update_scanline_offset(struct intel_crtc *crtc)
11749 {
11750 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11751
11752 /*
11753 * The scanline counter increments at the leading edge of hsync.
11754 *
11755 * On most platforms it starts counting from vtotal-1 on the
11756 * first active line. That means the scanline counter value is
11757 * always one less than what we would expect. Ie. just after
11758 * start of vblank, which also occurs at start of hsync (on the
11759 * last active line), the scanline counter will read vblank_start-1.
11760 *
11761 * On gen2 the scanline counter starts counting from 1 instead
11762 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11763 * to keep the value positive), instead of adding one.
11764 *
11765 * On HSW+ the behaviour of the scanline counter depends on the output
11766 * type. For DP ports it behaves like most other platforms, but on HDMI
11767 * there's an extra 1 line difference. So we need to add two instead of
11768 * one to the value.
11769 *
11770 * On VLV/CHV DSI the scanline counter would appear to increment
11771 * approx. 1/3 of a scanline before start of vblank. Unfortunately
11772 * that means we can't tell whether we're in vblank or not while
11773 * we're on that particular line. We must still set scanline_offset
11774 * to 1 so that the vblank timestamps come out correct when we query
11775 * the scanline counter from within the vblank interrupt handler.
11776 * However if queried just before the start of vblank we'll get an
11777 * answer that's slightly in the future.
11778 */
11779 if (IS_GEN2(dev_priv)) {
11780 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11781 int vtotal;
11782
11783 vtotal = adjusted_mode->crtc_vtotal;
11784 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11785 vtotal /= 2;
11786
11787 crtc->scanline_offset = vtotal - 1;
11788 } else if (HAS_DDI(dev_priv) &&
11789 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11790 crtc->scanline_offset = 2;
11791 } else
11792 crtc->scanline_offset = 1;
11793 }
11794
11795 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11796 {
11797 struct drm_device *dev = state->dev;
11798 struct drm_i915_private *dev_priv = to_i915(dev);
11799 struct drm_crtc *crtc;
11800 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11801 int i;
11802
11803 if (!dev_priv->display.crtc_compute_clock)
11804 return;
11805
11806 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11808 struct intel_shared_dpll *old_dpll =
11809 to_intel_crtc_state(old_crtc_state)->shared_dpll;
11810
11811 if (!needs_modeset(new_crtc_state))
11812 continue;
11813
11814 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11815
11816 if (!old_dpll)
11817 continue;
11818
11819 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11820 }
11821 }
11822
11823 /*
11824 * This implements the workaround described in the "notes" section of the mode
11825 * set sequence documentation. When going from no pipes or single pipe to
11826 * multiple pipes, and planes are enabled after the pipe, we need to wait at
11827 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11828 */
11829 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11830 {
11831 struct drm_crtc_state *crtc_state;
11832 struct intel_crtc *intel_crtc;
11833 struct drm_crtc *crtc;
11834 struct intel_crtc_state *first_crtc_state = NULL;
11835 struct intel_crtc_state *other_crtc_state = NULL;
11836 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11837 int i;
11838
11839 /* look at all crtc's that are going to be enabled in during modeset */
11840 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11841 intel_crtc = to_intel_crtc(crtc);
11842
11843 if (!crtc_state->active || !needs_modeset(crtc_state))
11844 continue;
11845
11846 if (first_crtc_state) {
11847 other_crtc_state = to_intel_crtc_state(crtc_state);
11848 break;
11849 } else {
11850 first_crtc_state = to_intel_crtc_state(crtc_state);
11851 first_pipe = intel_crtc->pipe;
11852 }
11853 }
11854
11855 /* No workaround needed? */
11856 if (!first_crtc_state)
11857 return 0;
11858
11859 /* w/a possibly needed, check how many crtc's are already enabled. */
11860 for_each_intel_crtc(state->dev, intel_crtc) {
11861 struct intel_crtc_state *pipe_config;
11862
11863 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11864 if (IS_ERR(pipe_config))
11865 return PTR_ERR(pipe_config);
11866
11867 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11868
11869 if (!pipe_config->base.active ||
11870 needs_modeset(&pipe_config->base))
11871 continue;
11872
11873 /* 2 or more enabled crtcs means no need for w/a */
11874 if (enabled_pipe != INVALID_PIPE)
11875 return 0;
11876
11877 enabled_pipe = intel_crtc->pipe;
11878 }
11879
11880 if (enabled_pipe != INVALID_PIPE)
11881 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11882 else if (other_crtc_state)
11883 other_crtc_state->hsw_workaround_pipe = first_pipe;
11884
11885 return 0;
11886 }
11887
11888 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11889 {
11890 struct drm_crtc *crtc;
11891
11892 /* Add all pipes to the state */
11893 for_each_crtc(state->dev, crtc) {
11894 struct drm_crtc_state *crtc_state;
11895
11896 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11897 if (IS_ERR(crtc_state))
11898 return PTR_ERR(crtc_state);
11899 }
11900
11901 return 0;
11902 }
11903
11904 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11905 {
11906 struct drm_crtc *crtc;
11907
11908 /*
11909 * Add all pipes to the state, and force
11910 * a modeset on all the active ones.
11911 */
11912 for_each_crtc(state->dev, crtc) {
11913 struct drm_crtc_state *crtc_state;
11914 int ret;
11915
11916 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11917 if (IS_ERR(crtc_state))
11918 return PTR_ERR(crtc_state);
11919
11920 if (!crtc_state->active || needs_modeset(crtc_state))
11921 continue;
11922
11923 crtc_state->mode_changed = true;
11924
11925 ret = drm_atomic_add_affected_connectors(state, crtc);
11926 if (ret)
11927 return ret;
11928
11929 ret = drm_atomic_add_affected_planes(state, crtc);
11930 if (ret)
11931 return ret;
11932 }
11933
11934 return 0;
11935 }
11936
11937 static int intel_modeset_checks(struct drm_atomic_state *state)
11938 {
11939 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11940 struct drm_i915_private *dev_priv = to_i915(state->dev);
11941 struct drm_crtc *crtc;
11942 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11943 int ret = 0, i;
11944
11945 if (!check_digital_port_conflicts(state)) {
11946 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11947 return -EINVAL;
11948 }
11949
11950 intel_state->modeset = true;
11951 intel_state->active_crtcs = dev_priv->active_crtcs;
11952 intel_state->cdclk.logical = dev_priv->cdclk.logical;
11953 intel_state->cdclk.actual = dev_priv->cdclk.actual;
11954
11955 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11956 if (new_crtc_state->active)
11957 intel_state->active_crtcs |= 1 << i;
11958 else
11959 intel_state->active_crtcs &= ~(1 << i);
11960
11961 if (old_crtc_state->active != new_crtc_state->active)
11962 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11963 }
11964
11965 /*
11966 * See if the config requires any additional preparation, e.g.
11967 * to adjust global state with pipes off. We need to do this
11968 * here so we can get the modeset_pipe updated config for the new
11969 * mode set on this crtc. For other crtcs we need to use the
11970 * adjusted_mode bits in the crtc directly.
11971 */
11972 if (dev_priv->display.modeset_calc_cdclk) {
11973 ret = dev_priv->display.modeset_calc_cdclk(state);
11974 if (ret < 0)
11975 return ret;
11976
11977 /*
11978 * Writes to dev_priv->cdclk.logical must protected by
11979 * holding all the crtc locks, even if we don't end up
11980 * touching the hardware
11981 */
11982 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11983 &intel_state->cdclk.logical)) {
11984 ret = intel_lock_all_pipes(state);
11985 if (ret < 0)
11986 return ret;
11987 }
11988
11989 /* All pipes must be switched off while we change the cdclk. */
11990 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
11991 &intel_state->cdclk.actual)) {
11992 ret = intel_modeset_all_pipes(state);
11993 if (ret < 0)
11994 return ret;
11995 }
11996
11997 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11998 intel_state->cdclk.logical.cdclk,
11999 intel_state->cdclk.actual.cdclk);
12000 } else {
12001 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12002 }
12003
12004 intel_modeset_clear_plls(state);
12005
12006 if (IS_HASWELL(dev_priv))
12007 return haswell_mode_set_planes_workaround(state);
12008
12009 return 0;
12010 }
12011
12012 /*
12013 * Handle calculation of various watermark data at the end of the atomic check
12014 * phase. The code here should be run after the per-crtc and per-plane 'check'
12015 * handlers to ensure that all derived state has been updated.
12016 */
12017 static int calc_watermark_data(struct drm_atomic_state *state)
12018 {
12019 struct drm_device *dev = state->dev;
12020 struct drm_i915_private *dev_priv = to_i915(dev);
12021
12022 /* Is there platform-specific watermark information to calculate? */
12023 if (dev_priv->display.compute_global_watermarks)
12024 return dev_priv->display.compute_global_watermarks(state);
12025
12026 return 0;
12027 }
12028
12029 /**
12030 * intel_atomic_check - validate state object
12031 * @dev: drm device
12032 * @state: state to validate
12033 */
12034 static int intel_atomic_check(struct drm_device *dev,
12035 struct drm_atomic_state *state)
12036 {
12037 struct drm_i915_private *dev_priv = to_i915(dev);
12038 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12039 struct drm_crtc *crtc;
12040 struct drm_crtc_state *old_crtc_state, *crtc_state;
12041 int ret, i;
12042 bool any_ms = false;
12043
12044 ret = drm_atomic_helper_check_modeset(dev, state);
12045 if (ret)
12046 return ret;
12047
12048 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12049 struct intel_crtc_state *pipe_config =
12050 to_intel_crtc_state(crtc_state);
12051
12052 /* Catch I915_MODE_FLAG_INHERITED */
12053 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12054 crtc_state->mode_changed = true;
12055
12056 if (!needs_modeset(crtc_state))
12057 continue;
12058
12059 if (!crtc_state->enable) {
12060 any_ms = true;
12061 continue;
12062 }
12063
12064 /* FIXME: For only active_changed we shouldn't need to do any
12065 * state recomputation at all. */
12066
12067 ret = drm_atomic_add_affected_connectors(state, crtc);
12068 if (ret)
12069 return ret;
12070
12071 ret = intel_modeset_pipe_config(crtc, pipe_config);
12072 if (ret) {
12073 intel_dump_pipe_config(to_intel_crtc(crtc),
12074 pipe_config, "[failed]");
12075 return ret;
12076 }
12077
12078 if (i915_modparams.fastboot &&
12079 intel_pipe_config_compare(dev_priv,
12080 to_intel_crtc_state(old_crtc_state),
12081 pipe_config, true)) {
12082 crtc_state->mode_changed = false;
12083 pipe_config->update_pipe = true;
12084 }
12085
12086 if (needs_modeset(crtc_state))
12087 any_ms = true;
12088
12089 ret = drm_atomic_add_affected_planes(state, crtc);
12090 if (ret)
12091 return ret;
12092
12093 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12094 needs_modeset(crtc_state) ?
12095 "[modeset]" : "[fastset]");
12096 }
12097
12098 if (any_ms) {
12099 ret = intel_modeset_checks(state);
12100
12101 if (ret)
12102 return ret;
12103 } else {
12104 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12105 }
12106
12107 ret = drm_atomic_helper_check_planes(dev, state);
12108 if (ret)
12109 return ret;
12110
12111 intel_fbc_choose_crtc(dev_priv, state);
12112 return calc_watermark_data(state);
12113 }
12114
12115 static int intel_atomic_prepare_commit(struct drm_device *dev,
12116 struct drm_atomic_state *state)
12117 {
12118 return drm_atomic_helper_prepare_planes(dev, state);
12119 }
12120
12121 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12122 {
12123 struct drm_device *dev = crtc->base.dev;
12124
12125 if (!dev->max_vblank_count)
12126 return drm_crtc_accurate_vblank_count(&crtc->base);
12127
12128 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12129 }
12130
12131 static void intel_update_crtc(struct drm_crtc *crtc,
12132 struct drm_atomic_state *state,
12133 struct drm_crtc_state *old_crtc_state,
12134 struct drm_crtc_state *new_crtc_state)
12135 {
12136 struct drm_device *dev = crtc->dev;
12137 struct drm_i915_private *dev_priv = to_i915(dev);
12138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12139 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12140 bool modeset = needs_modeset(new_crtc_state);
12141
12142 if (modeset) {
12143 update_scanline_offset(intel_crtc);
12144 dev_priv->display.crtc_enable(pipe_config, state);
12145 } else {
12146 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12147 pipe_config);
12148 }
12149
12150 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12151 intel_fbc_enable(
12152 intel_crtc, pipe_config,
12153 to_intel_plane_state(crtc->primary->state));
12154 }
12155
12156 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12157 }
12158
12159 static void intel_update_crtcs(struct drm_atomic_state *state)
12160 {
12161 struct drm_crtc *crtc;
12162 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12163 int i;
12164
12165 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12166 if (!new_crtc_state->active)
12167 continue;
12168
12169 intel_update_crtc(crtc, state, old_crtc_state,
12170 new_crtc_state);
12171 }
12172 }
12173
12174 static void skl_update_crtcs(struct drm_atomic_state *state)
12175 {
12176 struct drm_i915_private *dev_priv = to_i915(state->dev);
12177 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12178 struct drm_crtc *crtc;
12179 struct intel_crtc *intel_crtc;
12180 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12181 struct intel_crtc_state *cstate;
12182 unsigned int updated = 0;
12183 bool progress;
12184 enum pipe pipe;
12185 int i;
12186
12187 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12188
12189 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12190 /* ignore allocations for crtc's that have been turned off. */
12191 if (new_crtc_state->active)
12192 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12193
12194 /*
12195 * Whenever the number of active pipes changes, we need to make sure we
12196 * update the pipes in the right order so that their ddb allocations
12197 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12198 * cause pipe underruns and other bad stuff.
12199 */
12200 do {
12201 progress = false;
12202
12203 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12204 bool vbl_wait = false;
12205 unsigned int cmask = drm_crtc_mask(crtc);
12206
12207 intel_crtc = to_intel_crtc(crtc);
12208 cstate = to_intel_crtc_state(new_crtc_state);
12209 pipe = intel_crtc->pipe;
12210
12211 if (updated & cmask || !cstate->base.active)
12212 continue;
12213
12214 if (skl_ddb_allocation_overlaps(dev_priv,
12215 entries,
12216 &cstate->wm.skl.ddb,
12217 i))
12218 continue;
12219
12220 updated |= cmask;
12221 entries[i] = &cstate->wm.skl.ddb;
12222
12223 /*
12224 * If this is an already active pipe, it's DDB changed,
12225 * and this isn't the last pipe that needs updating
12226 * then we need to wait for a vblank to pass for the
12227 * new ddb allocation to take effect.
12228 */
12229 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12230 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12231 !new_crtc_state->active_changed &&
12232 intel_state->wm_results.dirty_pipes != updated)
12233 vbl_wait = true;
12234
12235 intel_update_crtc(crtc, state, old_crtc_state,
12236 new_crtc_state);
12237
12238 if (vbl_wait)
12239 intel_wait_for_vblank(dev_priv, pipe);
12240
12241 progress = true;
12242 }
12243 } while (progress);
12244 }
12245
12246 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12247 {
12248 struct intel_atomic_state *state, *next;
12249 struct llist_node *freed;
12250
12251 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12252 llist_for_each_entry_safe(state, next, freed, freed)
12253 drm_atomic_state_put(&state->base);
12254 }
12255
12256 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12257 {
12258 struct drm_i915_private *dev_priv =
12259 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12260
12261 intel_atomic_helper_free_state(dev_priv);
12262 }
12263
12264 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12265 {
12266 struct wait_queue_entry wait_fence, wait_reset;
12267 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12268
12269 init_wait_entry(&wait_fence, 0);
12270 init_wait_entry(&wait_reset, 0);
12271 for (;;) {
12272 prepare_to_wait(&intel_state->commit_ready.wait,
12273 &wait_fence, TASK_UNINTERRUPTIBLE);
12274 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12275 &wait_reset, TASK_UNINTERRUPTIBLE);
12276
12277
12278 if (i915_sw_fence_done(&intel_state->commit_ready)
12279 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12280 break;
12281
12282 schedule();
12283 }
12284 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12285 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12286 }
12287
12288 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12289 {
12290 struct drm_device *dev = state->dev;
12291 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12292 struct drm_i915_private *dev_priv = to_i915(dev);
12293 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12294 struct drm_crtc *crtc;
12295 struct intel_crtc_state *intel_cstate;
12296 u64 put_domains[I915_MAX_PIPES] = {};
12297 int i;
12298
12299 intel_atomic_commit_fence_wait(intel_state);
12300
12301 drm_atomic_helper_wait_for_dependencies(state);
12302
12303 if (intel_state->modeset)
12304 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12305
12306 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12308
12309 if (needs_modeset(new_crtc_state) ||
12310 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12311
12312 put_domains[to_intel_crtc(crtc)->pipe] =
12313 modeset_get_crtc_power_domains(crtc,
12314 to_intel_crtc_state(new_crtc_state));
12315 }
12316
12317 if (!needs_modeset(new_crtc_state))
12318 continue;
12319
12320 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12321 to_intel_crtc_state(new_crtc_state));
12322
12323 if (old_crtc_state->active) {
12324 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12325 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12326 intel_crtc->active = false;
12327 intel_fbc_disable(intel_crtc);
12328 intel_disable_shared_dpll(intel_crtc);
12329
12330 /*
12331 * Underruns don't always raise
12332 * interrupts, so check manually.
12333 */
12334 intel_check_cpu_fifo_underruns(dev_priv);
12335 intel_check_pch_fifo_underruns(dev_priv);
12336
12337 if (!new_crtc_state->active) {
12338 /*
12339 * Make sure we don't call initial_watermarks
12340 * for ILK-style watermark updates.
12341 *
12342 * No clue what this is supposed to achieve.
12343 */
12344 if (INTEL_GEN(dev_priv) >= 9)
12345 dev_priv->display.initial_watermarks(intel_state,
12346 to_intel_crtc_state(new_crtc_state));
12347 }
12348 }
12349 }
12350
12351 /* Only after disabling all output pipelines that will be changed can we
12352 * update the the output configuration. */
12353 intel_modeset_update_crtc_state(state);
12354
12355 if (intel_state->modeset) {
12356 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12357
12358 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12359
12360 /*
12361 * SKL workaround: bspec recommends we disable the SAGV when we
12362 * have more then one pipe enabled
12363 */
12364 if (!intel_can_enable_sagv(state))
12365 intel_disable_sagv(dev_priv);
12366
12367 intel_modeset_verify_disabled(dev, state);
12368 }
12369
12370 /* Complete the events for pipes that have now been disabled */
12371 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12372 bool modeset = needs_modeset(new_crtc_state);
12373
12374 /* Complete events for now disable pipes here. */
12375 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12376 spin_lock_irq(&dev->event_lock);
12377 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12378 spin_unlock_irq(&dev->event_lock);
12379
12380 new_crtc_state->event = NULL;
12381 }
12382 }
12383
12384 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12385 dev_priv->display.update_crtcs(state);
12386
12387 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12388 * already, but still need the state for the delayed optimization. To
12389 * fix this:
12390 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12391 * - schedule that vblank worker _before_ calling hw_done
12392 * - at the start of commit_tail, cancel it _synchrously
12393 * - switch over to the vblank wait helper in the core after that since
12394 * we don't need out special handling any more.
12395 */
12396 drm_atomic_helper_wait_for_flip_done(dev, state);
12397
12398 /*
12399 * Now that the vblank has passed, we can go ahead and program the
12400 * optimal watermarks on platforms that need two-step watermark
12401 * programming.
12402 *
12403 * TODO: Move this (and other cleanup) to an async worker eventually.
12404 */
12405 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12406 intel_cstate = to_intel_crtc_state(new_crtc_state);
12407
12408 if (dev_priv->display.optimize_watermarks)
12409 dev_priv->display.optimize_watermarks(intel_state,
12410 intel_cstate);
12411 }
12412
12413 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12414 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12415
12416 if (put_domains[i])
12417 modeset_put_power_domains(dev_priv, put_domains[i]);
12418
12419 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12420 }
12421
12422 if (intel_state->modeset && intel_can_enable_sagv(state))
12423 intel_enable_sagv(dev_priv);
12424
12425 drm_atomic_helper_commit_hw_done(state);
12426
12427 if (intel_state->modeset) {
12428 /* As one of the primary mmio accessors, KMS has a high
12429 * likelihood of triggering bugs in unclaimed access. After we
12430 * finish modesetting, see if an error has been flagged, and if
12431 * so enable debugging for the next modeset - and hope we catch
12432 * the culprit.
12433 */
12434 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12435 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12436 }
12437
12438 drm_atomic_helper_cleanup_planes(dev, state);
12439
12440 drm_atomic_helper_commit_cleanup_done(state);
12441
12442 drm_atomic_state_put(state);
12443
12444 intel_atomic_helper_free_state(dev_priv);
12445 }
12446
12447 static void intel_atomic_commit_work(struct work_struct *work)
12448 {
12449 struct drm_atomic_state *state =
12450 container_of(work, struct drm_atomic_state, commit_work);
12451
12452 intel_atomic_commit_tail(state);
12453 }
12454
12455 static int __i915_sw_fence_call
12456 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12457 enum i915_sw_fence_notify notify)
12458 {
12459 struct intel_atomic_state *state =
12460 container_of(fence, struct intel_atomic_state, commit_ready);
12461
12462 switch (notify) {
12463 case FENCE_COMPLETE:
12464 /* we do blocking waits in the worker, nothing to do here */
12465 break;
12466 case FENCE_FREE:
12467 {
12468 struct intel_atomic_helper *helper =
12469 &to_i915(state->base.dev)->atomic_helper;
12470
12471 if (llist_add(&state->freed, &helper->free_list))
12472 schedule_work(&helper->free_work);
12473 break;
12474 }
12475 }
12476
12477 return NOTIFY_DONE;
12478 }
12479
12480 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12481 {
12482 struct drm_plane_state *old_plane_state, *new_plane_state;
12483 struct drm_plane *plane;
12484 int i;
12485
12486 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12487 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12488 intel_fb_obj(new_plane_state->fb),
12489 to_intel_plane(plane)->frontbuffer_bit);
12490 }
12491
12492 /**
12493 * intel_atomic_commit - commit validated state object
12494 * @dev: DRM device
12495 * @state: the top-level driver state object
12496 * @nonblock: nonblocking commit
12497 *
12498 * This function commits a top-level state object that has been validated
12499 * with drm_atomic_helper_check().
12500 *
12501 * RETURNS
12502 * Zero for success or -errno.
12503 */
12504 static int intel_atomic_commit(struct drm_device *dev,
12505 struct drm_atomic_state *state,
12506 bool nonblock)
12507 {
12508 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12509 struct drm_i915_private *dev_priv = to_i915(dev);
12510 int ret = 0;
12511
12512 drm_atomic_state_get(state);
12513 i915_sw_fence_init(&intel_state->commit_ready,
12514 intel_atomic_commit_ready);
12515
12516 /*
12517 * The intel_legacy_cursor_update() fast path takes care
12518 * of avoiding the vblank waits for simple cursor
12519 * movement and flips. For cursor on/off and size changes,
12520 * we want to perform the vblank waits so that watermark
12521 * updates happen during the correct frames. Gen9+ have
12522 * double buffered watermarks and so shouldn't need this.
12523 *
12524 * Unset state->legacy_cursor_update before the call to
12525 * drm_atomic_helper_setup_commit() because otherwise
12526 * drm_atomic_helper_wait_for_flip_done() is a noop and
12527 * we get FIFO underruns because we didn't wait
12528 * for vblank.
12529 *
12530 * FIXME doing watermarks and fb cleanup from a vblank worker
12531 * (assuming we had any) would solve these problems.
12532 */
12533 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12534 struct intel_crtc_state *new_crtc_state;
12535 struct intel_crtc *crtc;
12536 int i;
12537
12538 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12539 if (new_crtc_state->wm.need_postvbl_update ||
12540 new_crtc_state->update_wm_post)
12541 state->legacy_cursor_update = false;
12542 }
12543
12544 ret = intel_atomic_prepare_commit(dev, state);
12545 if (ret) {
12546 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12547 i915_sw_fence_commit(&intel_state->commit_ready);
12548 return ret;
12549 }
12550
12551 ret = drm_atomic_helper_setup_commit(state, nonblock);
12552 if (!ret)
12553 ret = drm_atomic_helper_swap_state(state, true);
12554
12555 if (ret) {
12556 i915_sw_fence_commit(&intel_state->commit_ready);
12557
12558 drm_atomic_helper_cleanup_planes(dev, state);
12559 return ret;
12560 }
12561 dev_priv->wm.distrust_bios_wm = false;
12562 intel_shared_dpll_swap_state(state);
12563 intel_atomic_track_fbs(state);
12564
12565 if (intel_state->modeset) {
12566 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12567 sizeof(intel_state->min_cdclk));
12568 dev_priv->active_crtcs = intel_state->active_crtcs;
12569 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12570 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12571 }
12572
12573 drm_atomic_state_get(state);
12574 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12575
12576 i915_sw_fence_commit(&intel_state->commit_ready);
12577 if (nonblock)
12578 queue_work(system_unbound_wq, &state->commit_work);
12579 else
12580 intel_atomic_commit_tail(state);
12581
12582
12583 return 0;
12584 }
12585
12586 static const struct drm_crtc_funcs intel_crtc_funcs = {
12587 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12588 .set_config = drm_atomic_helper_set_config,
12589 .destroy = intel_crtc_destroy,
12590 .page_flip = drm_atomic_helper_page_flip,
12591 .atomic_duplicate_state = intel_crtc_duplicate_state,
12592 .atomic_destroy_state = intel_crtc_destroy_state,
12593 .set_crc_source = intel_crtc_set_crc_source,
12594 };
12595
12596 struct wait_rps_boost {
12597 struct wait_queue_entry wait;
12598
12599 struct drm_crtc *crtc;
12600 struct drm_i915_gem_request *request;
12601 };
12602
12603 static int do_rps_boost(struct wait_queue_entry *_wait,
12604 unsigned mode, int sync, void *key)
12605 {
12606 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12607 struct drm_i915_gem_request *rq = wait->request;
12608
12609 gen6_rps_boost(rq, NULL);
12610 i915_gem_request_put(rq);
12611
12612 drm_crtc_vblank_put(wait->crtc);
12613
12614 list_del(&wait->wait.entry);
12615 kfree(wait);
12616 return 1;
12617 }
12618
12619 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12620 struct dma_fence *fence)
12621 {
12622 struct wait_rps_boost *wait;
12623
12624 if (!dma_fence_is_i915(fence))
12625 return;
12626
12627 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12628 return;
12629
12630 if (drm_crtc_vblank_get(crtc))
12631 return;
12632
12633 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12634 if (!wait) {
12635 drm_crtc_vblank_put(crtc);
12636 return;
12637 }
12638
12639 wait->request = to_request(dma_fence_get(fence));
12640 wait->crtc = crtc;
12641
12642 wait->wait.func = do_rps_boost;
12643 wait->wait.flags = 0;
12644
12645 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12646 }
12647
12648 /**
12649 * intel_prepare_plane_fb - Prepare fb for usage on plane
12650 * @plane: drm plane to prepare for
12651 * @fb: framebuffer to prepare for presentation
12652 *
12653 * Prepares a framebuffer for usage on a display plane. Generally this
12654 * involves pinning the underlying object and updating the frontbuffer tracking
12655 * bits. Some older platforms need special physical address handling for
12656 * cursor planes.
12657 *
12658 * Must be called with struct_mutex held.
12659 *
12660 * Returns 0 on success, negative error code on failure.
12661 */
12662 int
12663 intel_prepare_plane_fb(struct drm_plane *plane,
12664 struct drm_plane_state *new_state)
12665 {
12666 struct intel_atomic_state *intel_state =
12667 to_intel_atomic_state(new_state->state);
12668 struct drm_i915_private *dev_priv = to_i915(plane->dev);
12669 struct drm_framebuffer *fb = new_state->fb;
12670 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12671 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12672 int ret;
12673
12674 if (old_obj) {
12675 struct drm_crtc_state *crtc_state =
12676 drm_atomic_get_existing_crtc_state(new_state->state,
12677 plane->state->crtc);
12678
12679 /* Big Hammer, we also need to ensure that any pending
12680 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12681 * current scanout is retired before unpinning the old
12682 * framebuffer. Note that we rely on userspace rendering
12683 * into the buffer attached to the pipe they are waiting
12684 * on. If not, userspace generates a GPU hang with IPEHR
12685 * point to the MI_WAIT_FOR_EVENT.
12686 *
12687 * This should only fail upon a hung GPU, in which case we
12688 * can safely continue.
12689 */
12690 if (needs_modeset(crtc_state)) {
12691 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12692 old_obj->resv, NULL,
12693 false, 0,
12694 GFP_KERNEL);
12695 if (ret < 0)
12696 return ret;
12697 }
12698 }
12699
12700 if (new_state->fence) { /* explicit fencing */
12701 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12702 new_state->fence,
12703 I915_FENCE_TIMEOUT,
12704 GFP_KERNEL);
12705 if (ret < 0)
12706 return ret;
12707 }
12708
12709 if (!obj)
12710 return 0;
12711
12712 ret = i915_gem_object_pin_pages(obj);
12713 if (ret)
12714 return ret;
12715
12716 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12717 if (ret) {
12718 i915_gem_object_unpin_pages(obj);
12719 return ret;
12720 }
12721
12722 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12723 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12724 const int align = intel_cursor_alignment(dev_priv);
12725
12726 ret = i915_gem_object_attach_phys(obj, align);
12727 } else {
12728 struct i915_vma *vma;
12729
12730 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12731 if (!IS_ERR(vma))
12732 to_intel_plane_state(new_state)->vma = vma;
12733 else
12734 ret = PTR_ERR(vma);
12735 }
12736
12737 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12738
12739 mutex_unlock(&dev_priv->drm.struct_mutex);
12740 i915_gem_object_unpin_pages(obj);
12741 if (ret)
12742 return ret;
12743
12744 if (!new_state->fence) { /* implicit fencing */
12745 struct dma_fence *fence;
12746
12747 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12748 obj->resv, NULL,
12749 false, I915_FENCE_TIMEOUT,
12750 GFP_KERNEL);
12751 if (ret < 0)
12752 return ret;
12753
12754 fence = reservation_object_get_excl_rcu(obj->resv);
12755 if (fence) {
12756 add_rps_boost_after_vblank(new_state->crtc, fence);
12757 dma_fence_put(fence);
12758 }
12759 } else {
12760 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12761 }
12762
12763 return 0;
12764 }
12765
12766 /**
12767 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12768 * @plane: drm plane to clean up for
12769 * @fb: old framebuffer that was on plane
12770 *
12771 * Cleans up a framebuffer that has just been removed from a plane.
12772 *
12773 * Must be called with struct_mutex held.
12774 */
12775 void
12776 intel_cleanup_plane_fb(struct drm_plane *plane,
12777 struct drm_plane_state *old_state)
12778 {
12779 struct i915_vma *vma;
12780
12781 /* Should only be called after a successful intel_prepare_plane_fb()! */
12782 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12783 if (vma) {
12784 mutex_lock(&plane->dev->struct_mutex);
12785 intel_unpin_fb_vma(vma);
12786 mutex_unlock(&plane->dev->struct_mutex);
12787 }
12788 }
12789
12790 int
12791 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12792 {
12793 struct drm_i915_private *dev_priv;
12794 int max_scale;
12795 int crtc_clock, max_dotclk;
12796
12797 if (!intel_crtc || !crtc_state->base.enable)
12798 return DRM_PLANE_HELPER_NO_SCALING;
12799
12800 dev_priv = to_i915(intel_crtc->base.dev);
12801
12802 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12803 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12804
12805 if (IS_GEMINILAKE(dev_priv))
12806 max_dotclk *= 2;
12807
12808 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12809 return DRM_PLANE_HELPER_NO_SCALING;
12810
12811 /*
12812 * skl max scale is lower of:
12813 * close to 3 but not 3, -1 is for that purpose
12814 * or
12815 * cdclk/crtc_clock
12816 */
12817 max_scale = min((1 << 16) * 3 - 1,
12818 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12819
12820 return max_scale;
12821 }
12822
12823 static int
12824 intel_check_primary_plane(struct intel_plane *plane,
12825 struct intel_crtc_state *crtc_state,
12826 struct intel_plane_state *state)
12827 {
12828 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12829 struct drm_crtc *crtc = state->base.crtc;
12830 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12831 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12832 bool can_position = false;
12833 int ret;
12834
12835 if (INTEL_GEN(dev_priv) >= 9) {
12836 /* use scaler when colorkey is not required */
12837 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12838 min_scale = 1;
12839 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12840 }
12841 can_position = true;
12842 }
12843
12844 ret = drm_plane_helper_check_state(&state->base,
12845 &state->clip,
12846 min_scale, max_scale,
12847 can_position, true);
12848 if (ret)
12849 return ret;
12850
12851 if (!state->base.fb)
12852 return 0;
12853
12854 if (INTEL_GEN(dev_priv) >= 9) {
12855 ret = skl_check_plane_surface(state);
12856 if (ret)
12857 return ret;
12858
12859 state->ctl = skl_plane_ctl(crtc_state, state);
12860 } else {
12861 ret = i9xx_check_plane_surface(state);
12862 if (ret)
12863 return ret;
12864
12865 state->ctl = i9xx_plane_ctl(crtc_state, state);
12866 }
12867
12868 return 0;
12869 }
12870
12871 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12872 struct drm_crtc_state *old_crtc_state)
12873 {
12874 struct drm_device *dev = crtc->dev;
12875 struct drm_i915_private *dev_priv = to_i915(dev);
12876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12877 struct intel_crtc_state *old_intel_cstate =
12878 to_intel_crtc_state(old_crtc_state);
12879 struct intel_atomic_state *old_intel_state =
12880 to_intel_atomic_state(old_crtc_state->state);
12881 struct intel_crtc_state *intel_cstate =
12882 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12883 bool modeset = needs_modeset(&intel_cstate->base);
12884
12885 if (!modeset &&
12886 (intel_cstate->base.color_mgmt_changed ||
12887 intel_cstate->update_pipe)) {
12888 intel_color_set_csc(&intel_cstate->base);
12889 intel_color_load_luts(&intel_cstate->base);
12890 }
12891
12892 /* Perform vblank evasion around commit operation */
12893 intel_pipe_update_start(intel_cstate);
12894
12895 if (modeset)
12896 goto out;
12897
12898 if (intel_cstate->update_pipe)
12899 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12900 else if (INTEL_GEN(dev_priv) >= 9)
12901 skl_detach_scalers(intel_crtc);
12902
12903 out:
12904 if (dev_priv->display.atomic_update_watermarks)
12905 dev_priv->display.atomic_update_watermarks(old_intel_state,
12906 intel_cstate);
12907 }
12908
12909 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12910 struct drm_crtc_state *old_crtc_state)
12911 {
12912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12913 struct intel_atomic_state *old_intel_state =
12914 to_intel_atomic_state(old_crtc_state->state);
12915 struct intel_crtc_state *new_crtc_state =
12916 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12917
12918 intel_pipe_update_end(new_crtc_state);
12919 }
12920
12921 /**
12922 * intel_plane_destroy - destroy a plane
12923 * @plane: plane to destroy
12924 *
12925 * Common destruction function for all types of planes (primary, cursor,
12926 * sprite).
12927 */
12928 void intel_plane_destroy(struct drm_plane *plane)
12929 {
12930 drm_plane_cleanup(plane);
12931 kfree(to_intel_plane(plane));
12932 }
12933
12934 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12935 {
12936 switch (format) {
12937 case DRM_FORMAT_C8:
12938 case DRM_FORMAT_RGB565:
12939 case DRM_FORMAT_XRGB1555:
12940 case DRM_FORMAT_XRGB8888:
12941 return modifier == DRM_FORMAT_MOD_LINEAR ||
12942 modifier == I915_FORMAT_MOD_X_TILED;
12943 default:
12944 return false;
12945 }
12946 }
12947
12948 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
12949 {
12950 switch (format) {
12951 case DRM_FORMAT_C8:
12952 case DRM_FORMAT_RGB565:
12953 case DRM_FORMAT_XRGB8888:
12954 case DRM_FORMAT_XBGR8888:
12955 case DRM_FORMAT_XRGB2101010:
12956 case DRM_FORMAT_XBGR2101010:
12957 return modifier == DRM_FORMAT_MOD_LINEAR ||
12958 modifier == I915_FORMAT_MOD_X_TILED;
12959 default:
12960 return false;
12961 }
12962 }
12963
12964 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
12965 {
12966 switch (format) {
12967 case DRM_FORMAT_XRGB8888:
12968 case DRM_FORMAT_XBGR8888:
12969 case DRM_FORMAT_ARGB8888:
12970 case DRM_FORMAT_ABGR8888:
12971 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
12972 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
12973 return true;
12974 /* fall through */
12975 case DRM_FORMAT_RGB565:
12976 case DRM_FORMAT_XRGB2101010:
12977 case DRM_FORMAT_XBGR2101010:
12978 case DRM_FORMAT_YUYV:
12979 case DRM_FORMAT_YVYU:
12980 case DRM_FORMAT_UYVY:
12981 case DRM_FORMAT_VYUY:
12982 if (modifier == I915_FORMAT_MOD_Yf_TILED)
12983 return true;
12984 /* fall through */
12985 case DRM_FORMAT_C8:
12986 if (modifier == DRM_FORMAT_MOD_LINEAR ||
12987 modifier == I915_FORMAT_MOD_X_TILED ||
12988 modifier == I915_FORMAT_MOD_Y_TILED)
12989 return true;
12990 /* fall through */
12991 default:
12992 return false;
12993 }
12994 }
12995
12996 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
12997 uint32_t format,
12998 uint64_t modifier)
12999 {
13000 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13001
13002 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13003 return false;
13004
13005 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13006 modifier != DRM_FORMAT_MOD_LINEAR)
13007 return false;
13008
13009 if (INTEL_GEN(dev_priv) >= 9)
13010 return skl_mod_supported(format, modifier);
13011 else if (INTEL_GEN(dev_priv) >= 4)
13012 return i965_mod_supported(format, modifier);
13013 else
13014 return i8xx_mod_supported(format, modifier);
13015
13016 unreachable();
13017 }
13018
13019 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
13020 uint32_t format,
13021 uint64_t modifier)
13022 {
13023 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13024 return false;
13025
13026 return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
13027 }
13028
13029 static struct drm_plane_funcs intel_plane_funcs = {
13030 .update_plane = drm_atomic_helper_update_plane,
13031 .disable_plane = drm_atomic_helper_disable_plane,
13032 .destroy = intel_plane_destroy,
13033 .atomic_get_property = intel_plane_atomic_get_property,
13034 .atomic_set_property = intel_plane_atomic_set_property,
13035 .atomic_duplicate_state = intel_plane_duplicate_state,
13036 .atomic_destroy_state = intel_plane_destroy_state,
13037 .format_mod_supported = intel_primary_plane_format_mod_supported,
13038 };
13039
13040 static int
13041 intel_legacy_cursor_update(struct drm_plane *plane,
13042 struct drm_crtc *crtc,
13043 struct drm_framebuffer *fb,
13044 int crtc_x, int crtc_y,
13045 unsigned int crtc_w, unsigned int crtc_h,
13046 uint32_t src_x, uint32_t src_y,
13047 uint32_t src_w, uint32_t src_h,
13048 struct drm_modeset_acquire_ctx *ctx)
13049 {
13050 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13051 int ret;
13052 struct drm_plane_state *old_plane_state, *new_plane_state;
13053 struct intel_plane *intel_plane = to_intel_plane(plane);
13054 struct drm_framebuffer *old_fb;
13055 struct drm_crtc_state *crtc_state = crtc->state;
13056 struct i915_vma *old_vma, *vma;
13057
13058 /*
13059 * When crtc is inactive or there is a modeset pending,
13060 * wait for it to complete in the slowpath
13061 */
13062 if (!crtc_state->active || needs_modeset(crtc_state) ||
13063 to_intel_crtc_state(crtc_state)->update_pipe)
13064 goto slow;
13065
13066 old_plane_state = plane->state;
13067 /*
13068 * Don't do an async update if there is an outstanding commit modifying
13069 * the plane. This prevents our async update's changes from getting
13070 * overridden by a previous synchronous update's state.
13071 */
13072 if (old_plane_state->commit &&
13073 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13074 goto slow;
13075
13076 /*
13077 * If any parameters change that may affect watermarks,
13078 * take the slowpath. Only changing fb or position should be
13079 * in the fastpath.
13080 */
13081 if (old_plane_state->crtc != crtc ||
13082 old_plane_state->src_w != src_w ||
13083 old_plane_state->src_h != src_h ||
13084 old_plane_state->crtc_w != crtc_w ||
13085 old_plane_state->crtc_h != crtc_h ||
13086 !old_plane_state->fb != !fb)
13087 goto slow;
13088
13089 new_plane_state = intel_plane_duplicate_state(plane);
13090 if (!new_plane_state)
13091 return -ENOMEM;
13092
13093 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13094
13095 new_plane_state->src_x = src_x;
13096 new_plane_state->src_y = src_y;
13097 new_plane_state->src_w = src_w;
13098 new_plane_state->src_h = src_h;
13099 new_plane_state->crtc_x = crtc_x;
13100 new_plane_state->crtc_y = crtc_y;
13101 new_plane_state->crtc_w = crtc_w;
13102 new_plane_state->crtc_h = crtc_h;
13103
13104 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13105 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13106 to_intel_plane_state(plane->state),
13107 to_intel_plane_state(new_plane_state));
13108 if (ret)
13109 goto out_free;
13110
13111 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13112 if (ret)
13113 goto out_free;
13114
13115 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13116 int align = intel_cursor_alignment(dev_priv);
13117
13118 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13119 if (ret) {
13120 DRM_DEBUG_KMS("failed to attach phys object\n");
13121 goto out_unlock;
13122 }
13123 } else {
13124 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13125 if (IS_ERR(vma)) {
13126 DRM_DEBUG_KMS("failed to pin object\n");
13127
13128 ret = PTR_ERR(vma);
13129 goto out_unlock;
13130 }
13131
13132 to_intel_plane_state(new_plane_state)->vma = vma;
13133 }
13134
13135 old_fb = old_plane_state->fb;
13136
13137 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13138 intel_plane->frontbuffer_bit);
13139
13140 /* Swap plane state */
13141 plane->state = new_plane_state;
13142
13143 if (plane->state->visible) {
13144 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13145 intel_plane->update_plane(intel_plane,
13146 to_intel_crtc_state(crtc->state),
13147 to_intel_plane_state(plane->state));
13148 } else {
13149 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13150 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13151 }
13152
13153 old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13154 if (old_vma)
13155 intel_unpin_fb_vma(old_vma);
13156
13157 out_unlock:
13158 mutex_unlock(&dev_priv->drm.struct_mutex);
13159 out_free:
13160 if (ret)
13161 intel_plane_destroy_state(plane, new_plane_state);
13162 else
13163 intel_plane_destroy_state(plane, old_plane_state);
13164 return ret;
13165
13166 slow:
13167 return drm_atomic_helper_update_plane(plane, crtc, fb,
13168 crtc_x, crtc_y, crtc_w, crtc_h,
13169 src_x, src_y, src_w, src_h, ctx);
13170 }
13171
13172 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13173 .update_plane = intel_legacy_cursor_update,
13174 .disable_plane = drm_atomic_helper_disable_plane,
13175 .destroy = intel_plane_destroy,
13176 .atomic_get_property = intel_plane_atomic_get_property,
13177 .atomic_set_property = intel_plane_atomic_set_property,
13178 .atomic_duplicate_state = intel_plane_duplicate_state,
13179 .atomic_destroy_state = intel_plane_destroy_state,
13180 .format_mod_supported = intel_cursor_plane_format_mod_supported,
13181 };
13182
13183 static struct intel_plane *
13184 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13185 {
13186 struct intel_plane *primary = NULL;
13187 struct intel_plane_state *state = NULL;
13188 const uint32_t *intel_primary_formats;
13189 unsigned int supported_rotations;
13190 unsigned int num_formats;
13191 const uint64_t *modifiers;
13192 int ret;
13193
13194 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13195 if (!primary) {
13196 ret = -ENOMEM;
13197 goto fail;
13198 }
13199
13200 state = intel_create_plane_state(&primary->base);
13201 if (!state) {
13202 ret = -ENOMEM;
13203 goto fail;
13204 }
13205
13206 primary->base.state = &state->base;
13207
13208 primary->can_scale = false;
13209 primary->max_downscale = 1;
13210 if (INTEL_GEN(dev_priv) >= 9) {
13211 primary->can_scale = true;
13212 state->scaler_id = -1;
13213 }
13214 primary->pipe = pipe;
13215 /*
13216 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13217 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13218 */
13219 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13220 primary->plane = (enum plane) !pipe;
13221 else
13222 primary->plane = (enum plane) pipe;
13223 primary->id = PLANE_PRIMARY;
13224 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13225 primary->check_plane = intel_check_primary_plane;
13226
13227 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13228 intel_primary_formats = skl_primary_formats;
13229 num_formats = ARRAY_SIZE(skl_primary_formats);
13230 modifiers = skl_format_modifiers_ccs;
13231
13232 primary->update_plane = skylake_update_primary_plane;
13233 primary->disable_plane = skylake_disable_primary_plane;
13234 } else if (INTEL_GEN(dev_priv) >= 9) {
13235 intel_primary_formats = skl_primary_formats;
13236 num_formats = ARRAY_SIZE(skl_primary_formats);
13237 if (pipe < PIPE_C)
13238 modifiers = skl_format_modifiers_ccs;
13239 else
13240 modifiers = skl_format_modifiers_noccs;
13241
13242 primary->update_plane = skylake_update_primary_plane;
13243 primary->disable_plane = skylake_disable_primary_plane;
13244 } else if (INTEL_GEN(dev_priv) >= 4) {
13245 intel_primary_formats = i965_primary_formats;
13246 num_formats = ARRAY_SIZE(i965_primary_formats);
13247 modifiers = i9xx_format_modifiers;
13248
13249 primary->update_plane = i9xx_update_primary_plane;
13250 primary->disable_plane = i9xx_disable_primary_plane;
13251 } else {
13252 intel_primary_formats = i8xx_primary_formats;
13253 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13254 modifiers = i9xx_format_modifiers;
13255
13256 primary->update_plane = i9xx_update_primary_plane;
13257 primary->disable_plane = i9xx_disable_primary_plane;
13258 }
13259
13260 if (INTEL_GEN(dev_priv) >= 9)
13261 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13262 0, &intel_plane_funcs,
13263 intel_primary_formats, num_formats,
13264 modifiers,
13265 DRM_PLANE_TYPE_PRIMARY,
13266 "plane 1%c", pipe_name(pipe));
13267 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13268 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13269 0, &intel_plane_funcs,
13270 intel_primary_formats, num_formats,
13271 modifiers,
13272 DRM_PLANE_TYPE_PRIMARY,
13273 "primary %c", pipe_name(pipe));
13274 else
13275 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13276 0, &intel_plane_funcs,
13277 intel_primary_formats, num_formats,
13278 modifiers,
13279 DRM_PLANE_TYPE_PRIMARY,
13280 "plane %c", plane_name(primary->plane));
13281 if (ret)
13282 goto fail;
13283
13284 if (INTEL_GEN(dev_priv) >= 9) {
13285 supported_rotations =
13286 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13287 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13288 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13289 supported_rotations =
13290 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13291 DRM_MODE_REFLECT_X;
13292 } else if (INTEL_GEN(dev_priv) >= 4) {
13293 supported_rotations =
13294 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13295 } else {
13296 supported_rotations = DRM_MODE_ROTATE_0;
13297 }
13298
13299 if (INTEL_GEN(dev_priv) >= 4)
13300 drm_plane_create_rotation_property(&primary->base,
13301 DRM_MODE_ROTATE_0,
13302 supported_rotations);
13303
13304 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13305
13306 return primary;
13307
13308 fail:
13309 kfree(state);
13310 kfree(primary);
13311
13312 return ERR_PTR(ret);
13313 }
13314
13315 static struct intel_plane *
13316 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13317 enum pipe pipe)
13318 {
13319 struct intel_plane *cursor = NULL;
13320 struct intel_plane_state *state = NULL;
13321 int ret;
13322
13323 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13324 if (!cursor) {
13325 ret = -ENOMEM;
13326 goto fail;
13327 }
13328
13329 state = intel_create_plane_state(&cursor->base);
13330 if (!state) {
13331 ret = -ENOMEM;
13332 goto fail;
13333 }
13334
13335 cursor->base.state = &state->base;
13336
13337 cursor->can_scale = false;
13338 cursor->max_downscale = 1;
13339 cursor->pipe = pipe;
13340 cursor->plane = pipe;
13341 cursor->id = PLANE_CURSOR;
13342 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13343
13344 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13345 cursor->update_plane = i845_update_cursor;
13346 cursor->disable_plane = i845_disable_cursor;
13347 cursor->check_plane = i845_check_cursor;
13348 } else {
13349 cursor->update_plane = i9xx_update_cursor;
13350 cursor->disable_plane = i9xx_disable_cursor;
13351 cursor->check_plane = i9xx_check_cursor;
13352 }
13353
13354 cursor->cursor.base = ~0;
13355 cursor->cursor.cntl = ~0;
13356
13357 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13358 cursor->cursor.size = ~0;
13359
13360 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13361 0, &intel_cursor_plane_funcs,
13362 intel_cursor_formats,
13363 ARRAY_SIZE(intel_cursor_formats),
13364 cursor_format_modifiers,
13365 DRM_PLANE_TYPE_CURSOR,
13366 "cursor %c", pipe_name(pipe));
13367 if (ret)
13368 goto fail;
13369
13370 if (INTEL_GEN(dev_priv) >= 4)
13371 drm_plane_create_rotation_property(&cursor->base,
13372 DRM_MODE_ROTATE_0,
13373 DRM_MODE_ROTATE_0 |
13374 DRM_MODE_ROTATE_180);
13375
13376 if (INTEL_GEN(dev_priv) >= 9)
13377 state->scaler_id = -1;
13378
13379 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13380
13381 return cursor;
13382
13383 fail:
13384 kfree(state);
13385 kfree(cursor);
13386
13387 return ERR_PTR(ret);
13388 }
13389
13390 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13391 struct intel_crtc_state *crtc_state)
13392 {
13393 struct intel_crtc_scaler_state *scaler_state =
13394 &crtc_state->scaler_state;
13395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13396 int i;
13397
13398 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13399 if (!crtc->num_scalers)
13400 return;
13401
13402 for (i = 0; i < crtc->num_scalers; i++) {
13403 struct intel_scaler *scaler = &scaler_state->scalers[i];
13404
13405 scaler->in_use = 0;
13406 scaler->mode = PS_SCALER_MODE_DYN;
13407 }
13408
13409 scaler_state->scaler_id = -1;
13410 }
13411
13412 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13413 {
13414 struct intel_crtc *intel_crtc;
13415 struct intel_crtc_state *crtc_state = NULL;
13416 struct intel_plane *primary = NULL;
13417 struct intel_plane *cursor = NULL;
13418 int sprite, ret;
13419
13420 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13421 if (!intel_crtc)
13422 return -ENOMEM;
13423
13424 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13425 if (!crtc_state) {
13426 ret = -ENOMEM;
13427 goto fail;
13428 }
13429 intel_crtc->config = crtc_state;
13430 intel_crtc->base.state = &crtc_state->base;
13431 crtc_state->base.crtc = &intel_crtc->base;
13432
13433 primary = intel_primary_plane_create(dev_priv, pipe);
13434 if (IS_ERR(primary)) {
13435 ret = PTR_ERR(primary);
13436 goto fail;
13437 }
13438 intel_crtc->plane_ids_mask |= BIT(primary->id);
13439
13440 for_each_sprite(dev_priv, pipe, sprite) {
13441 struct intel_plane *plane;
13442
13443 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13444 if (IS_ERR(plane)) {
13445 ret = PTR_ERR(plane);
13446 goto fail;
13447 }
13448 intel_crtc->plane_ids_mask |= BIT(plane->id);
13449 }
13450
13451 cursor = intel_cursor_plane_create(dev_priv, pipe);
13452 if (IS_ERR(cursor)) {
13453 ret = PTR_ERR(cursor);
13454 goto fail;
13455 }
13456 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13457
13458 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13459 &primary->base, &cursor->base,
13460 &intel_crtc_funcs,
13461 "pipe %c", pipe_name(pipe));
13462 if (ret)
13463 goto fail;
13464
13465 intel_crtc->pipe = pipe;
13466 intel_crtc->plane = primary->plane;
13467
13468 /* initialize shared scalers */
13469 intel_crtc_init_scalers(intel_crtc, crtc_state);
13470
13471 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13472 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13473 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13474 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13475
13476 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13477
13478 intel_color_init(&intel_crtc->base);
13479
13480 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13481
13482 return 0;
13483
13484 fail:
13485 /*
13486 * drm_mode_config_cleanup() will free up any
13487 * crtcs/planes already initialized.
13488 */
13489 kfree(crtc_state);
13490 kfree(intel_crtc);
13491
13492 return ret;
13493 }
13494
13495 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13496 {
13497 struct drm_device *dev = connector->base.dev;
13498
13499 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13500
13501 if (!connector->base.state->crtc)
13502 return INVALID_PIPE;
13503
13504 return to_intel_crtc(connector->base.state->crtc)->pipe;
13505 }
13506
13507 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13508 struct drm_file *file)
13509 {
13510 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13511 struct drm_crtc *drmmode_crtc;
13512 struct intel_crtc *crtc;
13513
13514 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13515 if (!drmmode_crtc)
13516 return -ENOENT;
13517
13518 crtc = to_intel_crtc(drmmode_crtc);
13519 pipe_from_crtc_id->pipe = crtc->pipe;
13520
13521 return 0;
13522 }
13523
13524 static int intel_encoder_clones(struct intel_encoder *encoder)
13525 {
13526 struct drm_device *dev = encoder->base.dev;
13527 struct intel_encoder *source_encoder;
13528 int index_mask = 0;
13529 int entry = 0;
13530
13531 for_each_intel_encoder(dev, source_encoder) {
13532 if (encoders_cloneable(encoder, source_encoder))
13533 index_mask |= (1 << entry);
13534
13535 entry++;
13536 }
13537
13538 return index_mask;
13539 }
13540
13541 static bool has_edp_a(struct drm_i915_private *dev_priv)
13542 {
13543 if (!IS_MOBILE(dev_priv))
13544 return false;
13545
13546 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13547 return false;
13548
13549 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13550 return false;
13551
13552 return true;
13553 }
13554
13555 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13556 {
13557 if (INTEL_GEN(dev_priv) >= 9)
13558 return false;
13559
13560 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13561 return false;
13562
13563 if (IS_CHERRYVIEW(dev_priv))
13564 return false;
13565
13566 if (HAS_PCH_LPT_H(dev_priv) &&
13567 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13568 return false;
13569
13570 /* DDI E can't be used if DDI A requires 4 lanes */
13571 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13572 return false;
13573
13574 if (!dev_priv->vbt.int_crt_support)
13575 return false;
13576
13577 return true;
13578 }
13579
13580 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13581 {
13582 int pps_num;
13583 int pps_idx;
13584
13585 if (HAS_DDI(dev_priv))
13586 return;
13587 /*
13588 * This w/a is needed at least on CPT/PPT, but to be sure apply it
13589 * everywhere where registers can be write protected.
13590 */
13591 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13592 pps_num = 2;
13593 else
13594 pps_num = 1;
13595
13596 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13597 u32 val = I915_READ(PP_CONTROL(pps_idx));
13598
13599 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13600 I915_WRITE(PP_CONTROL(pps_idx), val);
13601 }
13602 }
13603
13604 static void intel_pps_init(struct drm_i915_private *dev_priv)
13605 {
13606 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13607 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13608 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13609 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13610 else
13611 dev_priv->pps_mmio_base = PPS_BASE;
13612
13613 intel_pps_unlock_regs_wa(dev_priv);
13614 }
13615
13616 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13617 {
13618 struct intel_encoder *encoder;
13619 bool dpd_is_edp = false;
13620
13621 intel_pps_init(dev_priv);
13622
13623 /*
13624 * intel_edp_init_connector() depends on this completing first, to
13625 * prevent the registeration of both eDP and LVDS and the incorrect
13626 * sharing of the PPS.
13627 */
13628 intel_lvds_init(dev_priv);
13629
13630 if (intel_crt_present(dev_priv))
13631 intel_crt_init(dev_priv);
13632
13633 if (IS_GEN9_LP(dev_priv)) {
13634 /*
13635 * FIXME: Broxton doesn't support port detection via the
13636 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13637 * detect the ports.
13638 */
13639 intel_ddi_init(dev_priv, PORT_A);
13640 intel_ddi_init(dev_priv, PORT_B);
13641 intel_ddi_init(dev_priv, PORT_C);
13642
13643 intel_dsi_init(dev_priv);
13644 } else if (HAS_DDI(dev_priv)) {
13645 int found;
13646
13647 /*
13648 * Haswell uses DDI functions to detect digital outputs.
13649 * On SKL pre-D0 the strap isn't connected, so we assume
13650 * it's there.
13651 */
13652 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13653 /* WaIgnoreDDIAStrap: skl */
13654 if (found || IS_GEN9_BC(dev_priv))
13655 intel_ddi_init(dev_priv, PORT_A);
13656
13657 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13658 * register */
13659 found = I915_READ(SFUSE_STRAP);
13660
13661 if (found & SFUSE_STRAP_DDIB_DETECTED)
13662 intel_ddi_init(dev_priv, PORT_B);
13663 if (found & SFUSE_STRAP_DDIC_DETECTED)
13664 intel_ddi_init(dev_priv, PORT_C);
13665 if (found & SFUSE_STRAP_DDID_DETECTED)
13666 intel_ddi_init(dev_priv, PORT_D);
13667 /*
13668 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13669 */
13670 if (IS_GEN9_BC(dev_priv) &&
13671 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13672 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13673 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13674 intel_ddi_init(dev_priv, PORT_E);
13675
13676 } else if (HAS_PCH_SPLIT(dev_priv)) {
13677 int found;
13678 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13679
13680 if (has_edp_a(dev_priv))
13681 intel_dp_init(dev_priv, DP_A, PORT_A);
13682
13683 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13684 /* PCH SDVOB multiplex with HDMIB */
13685 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13686 if (!found)
13687 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13688 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13689 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13690 }
13691
13692 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13693 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13694
13695 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13696 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13697
13698 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13699 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13700
13701 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13702 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13703 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13704 bool has_edp, has_port;
13705
13706 /*
13707 * The DP_DETECTED bit is the latched state of the DDC
13708 * SDA pin at boot. However since eDP doesn't require DDC
13709 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13710 * eDP ports may have been muxed to an alternate function.
13711 * Thus we can't rely on the DP_DETECTED bit alone to detect
13712 * eDP ports. Consult the VBT as well as DP_DETECTED to
13713 * detect eDP ports.
13714 *
13715 * Sadly the straps seem to be missing sometimes even for HDMI
13716 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13717 * and VBT for the presence of the port. Additionally we can't
13718 * trust the port type the VBT declares as we've seen at least
13719 * HDMI ports that the VBT claim are DP or eDP.
13720 */
13721 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13722 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13723 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13724 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13725 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13726 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13727
13728 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13729 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13730 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13731 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13732 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13733 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13734
13735 if (IS_CHERRYVIEW(dev_priv)) {
13736 /*
13737 * eDP not supported on port D,
13738 * so no need to worry about it
13739 */
13740 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13741 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13742 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13743 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13744 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13745 }
13746
13747 intel_dsi_init(dev_priv);
13748 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13749 bool found = false;
13750
13751 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13752 DRM_DEBUG_KMS("probing SDVOB\n");
13753 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13754 if (!found && IS_G4X(dev_priv)) {
13755 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13756 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13757 }
13758
13759 if (!found && IS_G4X(dev_priv))
13760 intel_dp_init(dev_priv, DP_B, PORT_B);
13761 }
13762
13763 /* Before G4X SDVOC doesn't have its own detect register */
13764
13765 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13766 DRM_DEBUG_KMS("probing SDVOC\n");
13767 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13768 }
13769
13770 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13771
13772 if (IS_G4X(dev_priv)) {
13773 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13774 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13775 }
13776 if (IS_G4X(dev_priv))
13777 intel_dp_init(dev_priv, DP_C, PORT_C);
13778 }
13779
13780 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13781 intel_dp_init(dev_priv, DP_D, PORT_D);
13782 } else if (IS_GEN2(dev_priv))
13783 intel_dvo_init(dev_priv);
13784
13785 if (SUPPORTS_TV(dev_priv))
13786 intel_tv_init(dev_priv);
13787
13788 intel_psr_init(dev_priv);
13789
13790 for_each_intel_encoder(&dev_priv->drm, encoder) {
13791 encoder->base.possible_crtcs = encoder->crtc_mask;
13792 encoder->base.possible_clones =
13793 intel_encoder_clones(encoder);
13794 }
13795
13796 intel_init_pch_refclk(dev_priv);
13797
13798 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13799 }
13800
13801 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13802 {
13803 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13804
13805 drm_framebuffer_cleanup(fb);
13806
13807 i915_gem_object_lock(intel_fb->obj);
13808 WARN_ON(!intel_fb->obj->framebuffer_references--);
13809 i915_gem_object_unlock(intel_fb->obj);
13810
13811 i915_gem_object_put(intel_fb->obj);
13812
13813 kfree(intel_fb);
13814 }
13815
13816 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13817 struct drm_file *file,
13818 unsigned int *handle)
13819 {
13820 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13821 struct drm_i915_gem_object *obj = intel_fb->obj;
13822
13823 if (obj->userptr.mm) {
13824 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13825 return -EINVAL;
13826 }
13827
13828 return drm_gem_handle_create(file, &obj->base, handle);
13829 }
13830
13831 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13832 struct drm_file *file,
13833 unsigned flags, unsigned color,
13834 struct drm_clip_rect *clips,
13835 unsigned num_clips)
13836 {
13837 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13838
13839 i915_gem_object_flush_if_display(obj);
13840 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13841
13842 return 0;
13843 }
13844
13845 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13846 .destroy = intel_user_framebuffer_destroy,
13847 .create_handle = intel_user_framebuffer_create_handle,
13848 .dirty = intel_user_framebuffer_dirty,
13849 };
13850
13851 static
13852 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13853 uint64_t fb_modifier, uint32_t pixel_format)
13854 {
13855 u32 gen = INTEL_GEN(dev_priv);
13856
13857 if (gen >= 9) {
13858 int cpp = drm_format_plane_cpp(pixel_format, 0);
13859
13860 /* "The stride in bytes must not exceed the of the size of 8K
13861 * pixels and 32K bytes."
13862 */
13863 return min(8192 * cpp, 32768);
13864 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13865 return 32*1024;
13866 } else if (gen >= 4) {
13867 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13868 return 16*1024;
13869 else
13870 return 32*1024;
13871 } else if (gen >= 3) {
13872 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13873 return 8*1024;
13874 else
13875 return 16*1024;
13876 } else {
13877 /* XXX DSPC is limited to 4k tiled */
13878 return 8*1024;
13879 }
13880 }
13881
13882 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13883 struct drm_i915_gem_object *obj,
13884 struct drm_mode_fb_cmd2 *mode_cmd)
13885 {
13886 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13887 struct drm_framebuffer *fb = &intel_fb->base;
13888 struct drm_format_name_buf format_name;
13889 u32 pitch_limit;
13890 unsigned int tiling, stride;
13891 int ret = -EINVAL;
13892 int i;
13893
13894 i915_gem_object_lock(obj);
13895 obj->framebuffer_references++;
13896 tiling = i915_gem_object_get_tiling(obj);
13897 stride = i915_gem_object_get_stride(obj);
13898 i915_gem_object_unlock(obj);
13899
13900 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13901 /*
13902 * If there's a fence, enforce that
13903 * the fb modifier and tiling mode match.
13904 */
13905 if (tiling != I915_TILING_NONE &&
13906 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13907 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13908 goto err;
13909 }
13910 } else {
13911 if (tiling == I915_TILING_X) {
13912 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13913 } else if (tiling == I915_TILING_Y) {
13914 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13915 goto err;
13916 }
13917 }
13918
13919 /* Passed in modifier sanity checking. */
13920 switch (mode_cmd->modifier[0]) {
13921 case I915_FORMAT_MOD_Y_TILED_CCS:
13922 case I915_FORMAT_MOD_Yf_TILED_CCS:
13923 switch (mode_cmd->pixel_format) {
13924 case DRM_FORMAT_XBGR8888:
13925 case DRM_FORMAT_ABGR8888:
13926 case DRM_FORMAT_XRGB8888:
13927 case DRM_FORMAT_ARGB8888:
13928 break;
13929 default:
13930 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13931 goto err;
13932 }
13933 /* fall through */
13934 case I915_FORMAT_MOD_Y_TILED:
13935 case I915_FORMAT_MOD_Yf_TILED:
13936 if (INTEL_GEN(dev_priv) < 9) {
13937 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13938 mode_cmd->modifier[0]);
13939 goto err;
13940 }
13941 case DRM_FORMAT_MOD_LINEAR:
13942 case I915_FORMAT_MOD_X_TILED:
13943 break;
13944 default:
13945 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13946 mode_cmd->modifier[0]);
13947 goto err;
13948 }
13949
13950 /*
13951 * gen2/3 display engine uses the fence if present,
13952 * so the tiling mode must match the fb modifier exactly.
13953 */
13954 if (INTEL_INFO(dev_priv)->gen < 4 &&
13955 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13956 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13957 goto err;
13958 }
13959
13960 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13961 mode_cmd->pixel_format);
13962 if (mode_cmd->pitches[0] > pitch_limit) {
13963 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13964 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13965 "tiled" : "linear",
13966 mode_cmd->pitches[0], pitch_limit);
13967 goto err;
13968 }
13969
13970 /*
13971 * If there's a fence, enforce that
13972 * the fb pitch and fence stride match.
13973 */
13974 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13975 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13976 mode_cmd->pitches[0], stride);
13977 goto err;
13978 }
13979
13980 /* Reject formats not supported by any plane early. */
13981 switch (mode_cmd->pixel_format) {
13982 case DRM_FORMAT_C8:
13983 case DRM_FORMAT_RGB565:
13984 case DRM_FORMAT_XRGB8888:
13985 case DRM_FORMAT_ARGB8888:
13986 break;
13987 case DRM_FORMAT_XRGB1555:
13988 if (INTEL_GEN(dev_priv) > 3) {
13989 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13990 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13991 goto err;
13992 }
13993 break;
13994 case DRM_FORMAT_ABGR8888:
13995 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13996 INTEL_GEN(dev_priv) < 9) {
13997 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13998 drm_get_format_name(mode_cmd->pixel_format, &format_name));
13999 goto err;
14000 }
14001 break;
14002 case DRM_FORMAT_XBGR8888:
14003 case DRM_FORMAT_XRGB2101010:
14004 case DRM_FORMAT_XBGR2101010:
14005 if (INTEL_GEN(dev_priv) < 4) {
14006 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14007 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14008 goto err;
14009 }
14010 break;
14011 case DRM_FORMAT_ABGR2101010:
14012 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14013 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14014 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14015 goto err;
14016 }
14017 break;
14018 case DRM_FORMAT_YUYV:
14019 case DRM_FORMAT_UYVY:
14020 case DRM_FORMAT_YVYU:
14021 case DRM_FORMAT_VYUY:
14022 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14023 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14024 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14025 goto err;
14026 }
14027 break;
14028 default:
14029 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14030 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14031 goto err;
14032 }
14033
14034 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14035 if (mode_cmd->offsets[0] != 0)
14036 goto err;
14037
14038 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14039
14040 for (i = 0; i < fb->format->num_planes; i++) {
14041 u32 stride_alignment;
14042
14043 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14044 DRM_DEBUG_KMS("bad plane %d handle\n", i);
14045 goto err;
14046 }
14047
14048 stride_alignment = intel_fb_stride_alignment(fb, i);
14049
14050 /*
14051 * Display WA #0531: skl,bxt,kbl,glk
14052 *
14053 * Render decompression and plane width > 3840
14054 * combined with horizontal panning requires the
14055 * plane stride to be a multiple of 4. We'll just
14056 * require the entire fb to accommodate that to avoid
14057 * potential runtime errors at plane configuration time.
14058 */
14059 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14060 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14061 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14062 stride_alignment *= 4;
14063
14064 if (fb->pitches[i] & (stride_alignment - 1)) {
14065 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14066 i, fb->pitches[i], stride_alignment);
14067 goto err;
14068 }
14069 }
14070
14071 intel_fb->obj = obj;
14072
14073 ret = intel_fill_fb_info(dev_priv, fb);
14074 if (ret)
14075 goto err;
14076
14077 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14078 if (ret) {
14079 DRM_ERROR("framebuffer init failed %d\n", ret);
14080 goto err;
14081 }
14082
14083 return 0;
14084
14085 err:
14086 i915_gem_object_lock(obj);
14087 obj->framebuffer_references--;
14088 i915_gem_object_unlock(obj);
14089 return ret;
14090 }
14091
14092 static struct drm_framebuffer *
14093 intel_user_framebuffer_create(struct drm_device *dev,
14094 struct drm_file *filp,
14095 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14096 {
14097 struct drm_framebuffer *fb;
14098 struct drm_i915_gem_object *obj;
14099 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14100
14101 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14102 if (!obj)
14103 return ERR_PTR(-ENOENT);
14104
14105 fb = intel_framebuffer_create(obj, &mode_cmd);
14106 if (IS_ERR(fb))
14107 i915_gem_object_put(obj);
14108
14109 return fb;
14110 }
14111
14112 static void intel_atomic_state_free(struct drm_atomic_state *state)
14113 {
14114 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14115
14116 drm_atomic_state_default_release(state);
14117
14118 i915_sw_fence_fini(&intel_state->commit_ready);
14119
14120 kfree(state);
14121 }
14122
14123 static const struct drm_mode_config_funcs intel_mode_funcs = {
14124 .fb_create = intel_user_framebuffer_create,
14125 .get_format_info = intel_get_format_info,
14126 .output_poll_changed = intel_fbdev_output_poll_changed,
14127 .atomic_check = intel_atomic_check,
14128 .atomic_commit = intel_atomic_commit,
14129 .atomic_state_alloc = intel_atomic_state_alloc,
14130 .atomic_state_clear = intel_atomic_state_clear,
14131 .atomic_state_free = intel_atomic_state_free,
14132 };
14133
14134 /**
14135 * intel_init_display_hooks - initialize the display modesetting hooks
14136 * @dev_priv: device private
14137 */
14138 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14139 {
14140 intel_init_cdclk_hooks(dev_priv);
14141
14142 if (INTEL_INFO(dev_priv)->gen >= 9) {
14143 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14144 dev_priv->display.get_initial_plane_config =
14145 skylake_get_initial_plane_config;
14146 dev_priv->display.crtc_compute_clock =
14147 haswell_crtc_compute_clock;
14148 dev_priv->display.crtc_enable = haswell_crtc_enable;
14149 dev_priv->display.crtc_disable = haswell_crtc_disable;
14150 } else if (HAS_DDI(dev_priv)) {
14151 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14152 dev_priv->display.get_initial_plane_config =
14153 ironlake_get_initial_plane_config;
14154 dev_priv->display.crtc_compute_clock =
14155 haswell_crtc_compute_clock;
14156 dev_priv->display.crtc_enable = haswell_crtc_enable;
14157 dev_priv->display.crtc_disable = haswell_crtc_disable;
14158 } else if (HAS_PCH_SPLIT(dev_priv)) {
14159 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14160 dev_priv->display.get_initial_plane_config =
14161 ironlake_get_initial_plane_config;
14162 dev_priv->display.crtc_compute_clock =
14163 ironlake_crtc_compute_clock;
14164 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14165 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14166 } else if (IS_CHERRYVIEW(dev_priv)) {
14167 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14168 dev_priv->display.get_initial_plane_config =
14169 i9xx_get_initial_plane_config;
14170 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14171 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14172 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14173 } else if (IS_VALLEYVIEW(dev_priv)) {
14174 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14175 dev_priv->display.get_initial_plane_config =
14176 i9xx_get_initial_plane_config;
14177 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14178 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14179 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14180 } else if (IS_G4X(dev_priv)) {
14181 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14182 dev_priv->display.get_initial_plane_config =
14183 i9xx_get_initial_plane_config;
14184 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14185 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14186 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14187 } else if (IS_PINEVIEW(dev_priv)) {
14188 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14189 dev_priv->display.get_initial_plane_config =
14190 i9xx_get_initial_plane_config;
14191 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14192 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14193 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14194 } else if (!IS_GEN2(dev_priv)) {
14195 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14196 dev_priv->display.get_initial_plane_config =
14197 i9xx_get_initial_plane_config;
14198 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14199 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14200 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14201 } else {
14202 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14203 dev_priv->display.get_initial_plane_config =
14204 i9xx_get_initial_plane_config;
14205 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14206 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14207 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14208 }
14209
14210 if (IS_GEN5(dev_priv)) {
14211 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14212 } else if (IS_GEN6(dev_priv)) {
14213 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14214 } else if (IS_IVYBRIDGE(dev_priv)) {
14215 /* FIXME: detect B0+ stepping and use auto training */
14216 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14217 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14218 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14219 }
14220
14221 if (INTEL_GEN(dev_priv) >= 9)
14222 dev_priv->display.update_crtcs = skl_update_crtcs;
14223 else
14224 dev_priv->display.update_crtcs = intel_update_crtcs;
14225 }
14226
14227 /*
14228 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14229 */
14230 static void quirk_ssc_force_disable(struct drm_device *dev)
14231 {
14232 struct drm_i915_private *dev_priv = to_i915(dev);
14233 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14234 DRM_INFO("applying lvds SSC disable quirk\n");
14235 }
14236
14237 /*
14238 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14239 * brightness value
14240 */
14241 static void quirk_invert_brightness(struct drm_device *dev)
14242 {
14243 struct drm_i915_private *dev_priv = to_i915(dev);
14244 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14245 DRM_INFO("applying inverted panel brightness quirk\n");
14246 }
14247
14248 /* Some VBT's incorrectly indicate no backlight is present */
14249 static void quirk_backlight_present(struct drm_device *dev)
14250 {
14251 struct drm_i915_private *dev_priv = to_i915(dev);
14252 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14253 DRM_INFO("applying backlight present quirk\n");
14254 }
14255
14256 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14257 * which is 300 ms greater than eDP spec T12 min.
14258 */
14259 static void quirk_increase_t12_delay(struct drm_device *dev)
14260 {
14261 struct drm_i915_private *dev_priv = to_i915(dev);
14262
14263 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14264 DRM_INFO("Applying T12 delay quirk\n");
14265 }
14266
14267 struct intel_quirk {
14268 int device;
14269 int subsystem_vendor;
14270 int subsystem_device;
14271 void (*hook)(struct drm_device *dev);
14272 };
14273
14274 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14275 struct intel_dmi_quirk {
14276 void (*hook)(struct drm_device *dev);
14277 const struct dmi_system_id (*dmi_id_list)[];
14278 };
14279
14280 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14281 {
14282 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14283 return 1;
14284 }
14285
14286 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14287 {
14288 .dmi_id_list = &(const struct dmi_system_id[]) {
14289 {
14290 .callback = intel_dmi_reverse_brightness,
14291 .ident = "NCR Corporation",
14292 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14293 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14294 },
14295 },
14296 { } /* terminating entry */
14297 },
14298 .hook = quirk_invert_brightness,
14299 },
14300 };
14301
14302 static struct intel_quirk intel_quirks[] = {
14303 /* Lenovo U160 cannot use SSC on LVDS */
14304 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14305
14306 /* Sony Vaio Y cannot use SSC on LVDS */
14307 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14308
14309 /* Acer Aspire 5734Z must invert backlight brightness */
14310 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14311
14312 /* Acer/eMachines G725 */
14313 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14314
14315 /* Acer/eMachines e725 */
14316 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14317
14318 /* Acer/Packard Bell NCL20 */
14319 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14320
14321 /* Acer Aspire 4736Z */
14322 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14323
14324 /* Acer Aspire 5336 */
14325 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14326
14327 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14328 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14329
14330 /* Acer C720 Chromebook (Core i3 4005U) */
14331 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14332
14333 /* Apple Macbook 2,1 (Core 2 T7400) */
14334 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14335
14336 /* Apple Macbook 4,1 */
14337 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14338
14339 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14340 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14341
14342 /* HP Chromebook 14 (Celeron 2955U) */
14343 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14344
14345 /* Dell Chromebook 11 */
14346 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14347
14348 /* Dell Chromebook 11 (2015 version) */
14349 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14350
14351 /* Toshiba Satellite P50-C-18C */
14352 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14353 };
14354
14355 static void intel_init_quirks(struct drm_device *dev)
14356 {
14357 struct pci_dev *d = dev->pdev;
14358 int i;
14359
14360 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14361 struct intel_quirk *q = &intel_quirks[i];
14362
14363 if (d->device == q->device &&
14364 (d->subsystem_vendor == q->subsystem_vendor ||
14365 q->subsystem_vendor == PCI_ANY_ID) &&
14366 (d->subsystem_device == q->subsystem_device ||
14367 q->subsystem_device == PCI_ANY_ID))
14368 q->hook(dev);
14369 }
14370 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14371 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14372 intel_dmi_quirks[i].hook(dev);
14373 }
14374 }
14375
14376 /* Disable the VGA plane that we never use */
14377 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14378 {
14379 struct pci_dev *pdev = dev_priv->drm.pdev;
14380 u8 sr1;
14381 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14382
14383 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14384 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14385 outb(SR01, VGA_SR_INDEX);
14386 sr1 = inb(VGA_SR_DATA);
14387 outb(sr1 | 1<<5, VGA_SR_DATA);
14388 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14389 udelay(300);
14390
14391 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14392 POSTING_READ(vga_reg);
14393 }
14394
14395 void intel_modeset_init_hw(struct drm_device *dev)
14396 {
14397 struct drm_i915_private *dev_priv = to_i915(dev);
14398
14399 intel_update_cdclk(dev_priv);
14400 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14401
14402 intel_init_clock_gating(dev_priv);
14403 }
14404
14405 /*
14406 * Calculate what we think the watermarks should be for the state we've read
14407 * out of the hardware and then immediately program those watermarks so that
14408 * we ensure the hardware settings match our internal state.
14409 *
14410 * We can calculate what we think WM's should be by creating a duplicate of the
14411 * current state (which was constructed during hardware readout) and running it
14412 * through the atomic check code to calculate new watermark values in the
14413 * state object.
14414 */
14415 static void sanitize_watermarks(struct drm_device *dev)
14416 {
14417 struct drm_i915_private *dev_priv = to_i915(dev);
14418 struct drm_atomic_state *state;
14419 struct intel_atomic_state *intel_state;
14420 struct drm_crtc *crtc;
14421 struct drm_crtc_state *cstate;
14422 struct drm_modeset_acquire_ctx ctx;
14423 int ret;
14424 int i;
14425
14426 /* Only supported on platforms that use atomic watermark design */
14427 if (!dev_priv->display.optimize_watermarks)
14428 return;
14429
14430 /*
14431 * We need to hold connection_mutex before calling duplicate_state so
14432 * that the connector loop is protected.
14433 */
14434 drm_modeset_acquire_init(&ctx, 0);
14435 retry:
14436 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14437 if (ret == -EDEADLK) {
14438 drm_modeset_backoff(&ctx);
14439 goto retry;
14440 } else if (WARN_ON(ret)) {
14441 goto fail;
14442 }
14443
14444 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14445 if (WARN_ON(IS_ERR(state)))
14446 goto fail;
14447
14448 intel_state = to_intel_atomic_state(state);
14449
14450 /*
14451 * Hardware readout is the only time we don't want to calculate
14452 * intermediate watermarks (since we don't trust the current
14453 * watermarks).
14454 */
14455 if (!HAS_GMCH_DISPLAY(dev_priv))
14456 intel_state->skip_intermediate_wm = true;
14457
14458 ret = intel_atomic_check(dev, state);
14459 if (ret) {
14460 /*
14461 * If we fail here, it means that the hardware appears to be
14462 * programmed in a way that shouldn't be possible, given our
14463 * understanding of watermark requirements. This might mean a
14464 * mistake in the hardware readout code or a mistake in the
14465 * watermark calculations for a given platform. Raise a WARN
14466 * so that this is noticeable.
14467 *
14468 * If this actually happens, we'll have to just leave the
14469 * BIOS-programmed watermarks untouched and hope for the best.
14470 */
14471 WARN(true, "Could not determine valid watermarks for inherited state\n");
14472 goto put_state;
14473 }
14474
14475 /* Write calculated watermark values back */
14476 for_each_new_crtc_in_state(state, crtc, cstate, i) {
14477 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14478
14479 cs->wm.need_postvbl_update = true;
14480 dev_priv->display.optimize_watermarks(intel_state, cs);
14481 }
14482
14483 put_state:
14484 drm_atomic_state_put(state);
14485 fail:
14486 drm_modeset_drop_locks(&ctx);
14487 drm_modeset_acquire_fini(&ctx);
14488 }
14489
14490 int intel_modeset_init(struct drm_device *dev)
14491 {
14492 struct drm_i915_private *dev_priv = to_i915(dev);
14493 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14494 enum pipe pipe;
14495 struct intel_crtc *crtc;
14496
14497 drm_mode_config_init(dev);
14498
14499 dev->mode_config.min_width = 0;
14500 dev->mode_config.min_height = 0;
14501
14502 dev->mode_config.preferred_depth = 24;
14503 dev->mode_config.prefer_shadow = 1;
14504
14505 dev->mode_config.allow_fb_modifiers = true;
14506
14507 dev->mode_config.funcs = &intel_mode_funcs;
14508
14509 init_llist_head(&dev_priv->atomic_helper.free_list);
14510 INIT_WORK(&dev_priv->atomic_helper.free_work,
14511 intel_atomic_helper_free_state_worker);
14512
14513 intel_init_quirks(dev);
14514
14515 intel_init_pm(dev_priv);
14516
14517 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14518 return 0;
14519
14520 /*
14521 * There may be no VBT; and if the BIOS enabled SSC we can
14522 * just keep using it to avoid unnecessary flicker. Whereas if the
14523 * BIOS isn't using it, don't assume it will work even if the VBT
14524 * indicates as much.
14525 */
14526 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14527 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14528 DREF_SSC1_ENABLE);
14529
14530 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14531 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14532 bios_lvds_use_ssc ? "en" : "dis",
14533 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14534 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14535 }
14536 }
14537
14538 if (IS_GEN2(dev_priv)) {
14539 dev->mode_config.max_width = 2048;
14540 dev->mode_config.max_height = 2048;
14541 } else if (IS_GEN3(dev_priv)) {
14542 dev->mode_config.max_width = 4096;
14543 dev->mode_config.max_height = 4096;
14544 } else {
14545 dev->mode_config.max_width = 8192;
14546 dev->mode_config.max_height = 8192;
14547 }
14548
14549 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14550 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14551 dev->mode_config.cursor_height = 1023;
14552 } else if (IS_GEN2(dev_priv)) {
14553 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14554 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14555 } else {
14556 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14557 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14558 }
14559
14560 dev->mode_config.fb_base = ggtt->mappable_base;
14561
14562 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14563 INTEL_INFO(dev_priv)->num_pipes,
14564 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14565
14566 for_each_pipe(dev_priv, pipe) {
14567 int ret;
14568
14569 ret = intel_crtc_init(dev_priv, pipe);
14570 if (ret) {
14571 drm_mode_config_cleanup(dev);
14572 return ret;
14573 }
14574 }
14575
14576 intel_shared_dpll_init(dev);
14577
14578 intel_update_czclk(dev_priv);
14579 intel_modeset_init_hw(dev);
14580
14581 if (dev_priv->max_cdclk_freq == 0)
14582 intel_update_max_cdclk(dev_priv);
14583
14584 /* Just disable it once at startup */
14585 i915_disable_vga(dev_priv);
14586 intel_setup_outputs(dev_priv);
14587
14588 drm_modeset_lock_all(dev);
14589 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14590 drm_modeset_unlock_all(dev);
14591
14592 for_each_intel_crtc(dev, crtc) {
14593 struct intel_initial_plane_config plane_config = {};
14594
14595 if (!crtc->active)
14596 continue;
14597
14598 /*
14599 * Note that reserving the BIOS fb up front prevents us
14600 * from stuffing other stolen allocations like the ring
14601 * on top. This prevents some ugliness at boot time, and
14602 * can even allow for smooth boot transitions if the BIOS
14603 * fb is large enough for the active pipe configuration.
14604 */
14605 dev_priv->display.get_initial_plane_config(crtc,
14606 &plane_config);
14607
14608 /*
14609 * If the fb is shared between multiple heads, we'll
14610 * just get the first one.
14611 */
14612 intel_find_initial_plane_obj(crtc, &plane_config);
14613 }
14614
14615 /*
14616 * Make sure hardware watermarks really match the state we read out.
14617 * Note that we need to do this after reconstructing the BIOS fb's
14618 * since the watermark calculation done here will use pstate->fb.
14619 */
14620 if (!HAS_GMCH_DISPLAY(dev_priv))
14621 sanitize_watermarks(dev);
14622
14623 return 0;
14624 }
14625
14626 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14627 {
14628 /* 640x480@60Hz, ~25175 kHz */
14629 struct dpll clock = {
14630 .m1 = 18,
14631 .m2 = 7,
14632 .p1 = 13,
14633 .p2 = 4,
14634 .n = 2,
14635 };
14636 u32 dpll, fp;
14637 int i;
14638
14639 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14640
14641 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14642 pipe_name(pipe), clock.vco, clock.dot);
14643
14644 fp = i9xx_dpll_compute_fp(&clock);
14645 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14646 DPLL_VGA_MODE_DIS |
14647 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14648 PLL_P2_DIVIDE_BY_4 |
14649 PLL_REF_INPUT_DREFCLK |
14650 DPLL_VCO_ENABLE;
14651
14652 I915_WRITE(FP0(pipe), fp);
14653 I915_WRITE(FP1(pipe), fp);
14654
14655 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14656 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14657 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14658 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14659 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14660 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14661 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14662
14663 /*
14664 * Apparently we need to have VGA mode enabled prior to changing
14665 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14666 * dividers, even though the register value does change.
14667 */
14668 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14669 I915_WRITE(DPLL(pipe), dpll);
14670
14671 /* Wait for the clocks to stabilize. */
14672 POSTING_READ(DPLL(pipe));
14673 udelay(150);
14674
14675 /* The pixel multiplier can only be updated once the
14676 * DPLL is enabled and the clocks are stable.
14677 *
14678 * So write it again.
14679 */
14680 I915_WRITE(DPLL(pipe), dpll);
14681
14682 /* We do this three times for luck */
14683 for (i = 0; i < 3 ; i++) {
14684 I915_WRITE(DPLL(pipe), dpll);
14685 POSTING_READ(DPLL(pipe));
14686 udelay(150); /* wait for warmup */
14687 }
14688
14689 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14690 POSTING_READ(PIPECONF(pipe));
14691 }
14692
14693 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14694 {
14695 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14696 pipe_name(pipe));
14697
14698 assert_plane_disabled(dev_priv, PLANE_A);
14699 assert_plane_disabled(dev_priv, PLANE_B);
14700
14701 I915_WRITE(PIPECONF(pipe), 0);
14702 POSTING_READ(PIPECONF(pipe));
14703
14704 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14705 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14706
14707 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14708 POSTING_READ(DPLL(pipe));
14709 }
14710
14711 static bool
14712 intel_check_plane_mapping(struct intel_crtc *crtc)
14713 {
14714 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14715 u32 val;
14716
14717 if (INTEL_INFO(dev_priv)->num_pipes == 1)
14718 return true;
14719
14720 val = I915_READ(DSPCNTR(!crtc->plane));
14721
14722 if ((val & DISPLAY_PLANE_ENABLE) &&
14723 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14724 return false;
14725
14726 return true;
14727 }
14728
14729 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14730 {
14731 struct drm_device *dev = crtc->base.dev;
14732 struct intel_encoder *encoder;
14733
14734 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14735 return true;
14736
14737 return false;
14738 }
14739
14740 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14741 {
14742 struct drm_device *dev = encoder->base.dev;
14743 struct intel_connector *connector;
14744
14745 for_each_connector_on_encoder(dev, &encoder->base, connector)
14746 return connector;
14747
14748 return NULL;
14749 }
14750
14751 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14752 enum pipe pch_transcoder)
14753 {
14754 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14755 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
14756 }
14757
14758 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14759 struct drm_modeset_acquire_ctx *ctx)
14760 {
14761 struct drm_device *dev = crtc->base.dev;
14762 struct drm_i915_private *dev_priv = to_i915(dev);
14763 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14764
14765 /* Clear any frame start delays used for debugging left by the BIOS */
14766 if (!transcoder_is_dsi(cpu_transcoder)) {
14767 i915_reg_t reg = PIPECONF(cpu_transcoder);
14768
14769 I915_WRITE(reg,
14770 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14771 }
14772
14773 /* restore vblank interrupts to correct state */
14774 drm_crtc_vblank_reset(&crtc->base);
14775 if (crtc->active) {
14776 struct intel_plane *plane;
14777
14778 drm_crtc_vblank_on(&crtc->base);
14779
14780 /* Disable everything but the primary plane */
14781 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14782 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14783 continue;
14784
14785 trace_intel_disable_plane(&plane->base, crtc);
14786 plane->disable_plane(plane, crtc);
14787 }
14788 }
14789
14790 /* We need to sanitize the plane -> pipe mapping first because this will
14791 * disable the crtc (and hence change the state) if it is wrong. Note
14792 * that gen4+ has a fixed plane -> pipe mapping. */
14793 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14794 bool plane;
14795
14796 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14797 crtc->base.base.id, crtc->base.name);
14798
14799 /* Pipe has the wrong plane attached and the plane is active.
14800 * Temporarily change the plane mapping and disable everything
14801 * ... */
14802 plane = crtc->plane;
14803 crtc->base.primary->state->visible = true;
14804 crtc->plane = !plane;
14805 intel_crtc_disable_noatomic(&crtc->base, ctx);
14806 crtc->plane = plane;
14807 }
14808
14809 /* Adjust the state of the output pipe according to whether we
14810 * have active connectors/encoders. */
14811 if (crtc->active && !intel_crtc_has_encoders(crtc))
14812 intel_crtc_disable_noatomic(&crtc->base, ctx);
14813
14814 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14815 /*
14816 * We start out with underrun reporting disabled to avoid races.
14817 * For correct bookkeeping mark this on active crtcs.
14818 *
14819 * Also on gmch platforms we dont have any hardware bits to
14820 * disable the underrun reporting. Which means we need to start
14821 * out with underrun reporting disabled also on inactive pipes,
14822 * since otherwise we'll complain about the garbage we read when
14823 * e.g. coming up after runtime pm.
14824 *
14825 * No protection against concurrent access is required - at
14826 * worst a fifo underrun happens which also sets this to false.
14827 */
14828 crtc->cpu_fifo_underrun_disabled = true;
14829 /*
14830 * We track the PCH trancoder underrun reporting state
14831 * within the crtc. With crtc for pipe A housing the underrun
14832 * reporting state for PCH transcoder A, crtc for pipe B housing
14833 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14834 * and marking underrun reporting as disabled for the non-existing
14835 * PCH transcoders B and C would prevent enabling the south
14836 * error interrupt (see cpt_can_enable_serr_int()).
14837 */
14838 if (has_pch_trancoder(dev_priv, crtc->pipe))
14839 crtc->pch_fifo_underrun_disabled = true;
14840 }
14841 }
14842
14843 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14844 {
14845 struct intel_connector *connector;
14846
14847 /* We need to check both for a crtc link (meaning that the
14848 * encoder is active and trying to read from a pipe) and the
14849 * pipe itself being active. */
14850 bool has_active_crtc = encoder->base.crtc &&
14851 to_intel_crtc(encoder->base.crtc)->active;
14852
14853 connector = intel_encoder_find_connector(encoder);
14854 if (connector && !has_active_crtc) {
14855 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14856 encoder->base.base.id,
14857 encoder->base.name);
14858
14859 /* Connector is active, but has no active pipe. This is
14860 * fallout from our resume register restoring. Disable
14861 * the encoder manually again. */
14862 if (encoder->base.crtc) {
14863 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14864
14865 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14866 encoder->base.base.id,
14867 encoder->base.name);
14868 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14869 if (encoder->post_disable)
14870 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14871 }
14872 encoder->base.crtc = NULL;
14873
14874 /* Inconsistent output/port/pipe state happens presumably due to
14875 * a bug in one of the get_hw_state functions. Or someplace else
14876 * in our code, like the register restore mess on resume. Clamp
14877 * things to off as a safer default. */
14878
14879 connector->base.dpms = DRM_MODE_DPMS_OFF;
14880 connector->base.encoder = NULL;
14881 }
14882 /* Enabled encoders without active connectors will be fixed in
14883 * the crtc fixup. */
14884 }
14885
14886 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14887 {
14888 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14889
14890 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14891 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14892 i915_disable_vga(dev_priv);
14893 }
14894 }
14895
14896 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14897 {
14898 /* This function can be called both from intel_modeset_setup_hw_state or
14899 * at a very early point in our resume sequence, where the power well
14900 * structures are not yet restored. Since this function is at a very
14901 * paranoid "someone might have enabled VGA while we were not looking"
14902 * level, just check if the power well is enabled instead of trying to
14903 * follow the "don't touch the power well if we don't need it" policy
14904 * the rest of the driver uses. */
14905 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14906 return;
14907
14908 i915_redisable_vga_power_on(dev_priv);
14909
14910 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14911 }
14912
14913 static bool primary_get_hw_state(struct intel_plane *plane)
14914 {
14915 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14916
14917 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14918 }
14919
14920 /* FIXME read out full plane state for all planes */
14921 static void readout_plane_state(struct intel_crtc *crtc)
14922 {
14923 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14924 bool visible;
14925
14926 visible = crtc->active && primary_get_hw_state(primary);
14927
14928 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14929 to_intel_plane_state(primary->base.state),
14930 visible);
14931 }
14932
14933 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14934 {
14935 struct drm_i915_private *dev_priv = to_i915(dev);
14936 enum pipe pipe;
14937 struct intel_crtc *crtc;
14938 struct intel_encoder *encoder;
14939 struct intel_connector *connector;
14940 struct drm_connector_list_iter conn_iter;
14941 int i;
14942
14943 dev_priv->active_crtcs = 0;
14944
14945 for_each_intel_crtc(dev, crtc) {
14946 struct intel_crtc_state *crtc_state =
14947 to_intel_crtc_state(crtc->base.state);
14948
14949 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14950 memset(crtc_state, 0, sizeof(*crtc_state));
14951 crtc_state->base.crtc = &crtc->base;
14952
14953 crtc_state->base.active = crtc_state->base.enable =
14954 dev_priv->display.get_pipe_config(crtc, crtc_state);
14955
14956 crtc->base.enabled = crtc_state->base.enable;
14957 crtc->active = crtc_state->base.active;
14958
14959 if (crtc_state->base.active)
14960 dev_priv->active_crtcs |= 1 << crtc->pipe;
14961
14962 readout_plane_state(crtc);
14963
14964 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14965 crtc->base.base.id, crtc->base.name,
14966 enableddisabled(crtc_state->base.active));
14967 }
14968
14969 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14970 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14971
14972 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14973 &pll->state.hw_state);
14974 pll->state.crtc_mask = 0;
14975 for_each_intel_crtc(dev, crtc) {
14976 struct intel_crtc_state *crtc_state =
14977 to_intel_crtc_state(crtc->base.state);
14978
14979 if (crtc_state->base.active &&
14980 crtc_state->shared_dpll == pll)
14981 pll->state.crtc_mask |= 1 << crtc->pipe;
14982 }
14983 pll->active_mask = pll->state.crtc_mask;
14984
14985 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14986 pll->name, pll->state.crtc_mask, pll->on);
14987 }
14988
14989 for_each_intel_encoder(dev, encoder) {
14990 pipe = 0;
14991
14992 if (encoder->get_hw_state(encoder, &pipe)) {
14993 struct intel_crtc_state *crtc_state;
14994
14995 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14996 crtc_state = to_intel_crtc_state(crtc->base.state);
14997
14998 encoder->base.crtc = &crtc->base;
14999 crtc_state->output_types |= 1 << encoder->type;
15000 encoder->get_config(encoder, crtc_state);
15001 } else {
15002 encoder->base.crtc = NULL;
15003 }
15004
15005 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15006 encoder->base.base.id, encoder->base.name,
15007 enableddisabled(encoder->base.crtc),
15008 pipe_name(pipe));
15009 }
15010
15011 drm_connector_list_iter_begin(dev, &conn_iter);
15012 for_each_intel_connector_iter(connector, &conn_iter) {
15013 if (connector->get_hw_state(connector)) {
15014 connector->base.dpms = DRM_MODE_DPMS_ON;
15015
15016 encoder = connector->encoder;
15017 connector->base.encoder = &encoder->base;
15018
15019 if (encoder->base.crtc &&
15020 encoder->base.crtc->state->active) {
15021 /*
15022 * This has to be done during hardware readout
15023 * because anything calling .crtc_disable may
15024 * rely on the connector_mask being accurate.
15025 */
15026 encoder->base.crtc->state->connector_mask |=
15027 1 << drm_connector_index(&connector->base);
15028 encoder->base.crtc->state->encoder_mask |=
15029 1 << drm_encoder_index(&encoder->base);
15030 }
15031
15032 } else {
15033 connector->base.dpms = DRM_MODE_DPMS_OFF;
15034 connector->base.encoder = NULL;
15035 }
15036 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15037 connector->base.base.id, connector->base.name,
15038 enableddisabled(connector->base.encoder));
15039 }
15040 drm_connector_list_iter_end(&conn_iter);
15041
15042 for_each_intel_crtc(dev, crtc) {
15043 struct intel_crtc_state *crtc_state =
15044 to_intel_crtc_state(crtc->base.state);
15045 int min_cdclk = 0;
15046
15047 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15048 if (crtc_state->base.active) {
15049 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15050 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15051 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15052
15053 /*
15054 * The initial mode needs to be set in order to keep
15055 * the atomic core happy. It wants a valid mode if the
15056 * crtc's enabled, so we do the above call.
15057 *
15058 * But we don't set all the derived state fully, hence
15059 * set a flag to indicate that a full recalculation is
15060 * needed on the next commit.
15061 */
15062 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15063
15064 intel_crtc_compute_pixel_rate(crtc_state);
15065
15066 if (dev_priv->display.modeset_calc_cdclk) {
15067 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15068 if (WARN_ON(min_cdclk < 0))
15069 min_cdclk = 0;
15070 }
15071
15072 drm_calc_timestamping_constants(&crtc->base,
15073 &crtc_state->base.adjusted_mode);
15074 update_scanline_offset(crtc);
15075 }
15076
15077 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15078
15079 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15080 }
15081 }
15082
15083 static void
15084 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15085 {
15086 struct intel_encoder *encoder;
15087
15088 for_each_intel_encoder(&dev_priv->drm, encoder) {
15089 u64 get_domains;
15090 enum intel_display_power_domain domain;
15091
15092 if (!encoder->get_power_domains)
15093 continue;
15094
15095 get_domains = encoder->get_power_domains(encoder);
15096 for_each_power_domain(domain, get_domains)
15097 intel_display_power_get(dev_priv, domain);
15098 }
15099 }
15100
15101 /* Scan out the current hw modeset state,
15102 * and sanitizes it to the current state
15103 */
15104 static void
15105 intel_modeset_setup_hw_state(struct drm_device *dev,
15106 struct drm_modeset_acquire_ctx *ctx)
15107 {
15108 struct drm_i915_private *dev_priv = to_i915(dev);
15109 enum pipe pipe;
15110 struct intel_crtc *crtc;
15111 struct intel_encoder *encoder;
15112 int i;
15113
15114 intel_modeset_readout_hw_state(dev);
15115
15116 /* HW state is read out, now we need to sanitize this mess. */
15117 get_encoder_power_domains(dev_priv);
15118
15119 for_each_intel_encoder(dev, encoder) {
15120 intel_sanitize_encoder(encoder);
15121 }
15122
15123 for_each_pipe(dev_priv, pipe) {
15124 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15125
15126 intel_sanitize_crtc(crtc, ctx);
15127 intel_dump_pipe_config(crtc, crtc->config,
15128 "[setup_hw_state]");
15129 }
15130
15131 intel_modeset_update_connector_atomic_state(dev);
15132
15133 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15134 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15135
15136 if (!pll->on || pll->active_mask)
15137 continue;
15138
15139 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15140
15141 pll->funcs.disable(dev_priv, pll);
15142 pll->on = false;
15143 }
15144
15145 if (IS_G4X(dev_priv)) {
15146 g4x_wm_get_hw_state(dev);
15147 g4x_wm_sanitize(dev_priv);
15148 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15149 vlv_wm_get_hw_state(dev);
15150 vlv_wm_sanitize(dev_priv);
15151 } else if (INTEL_GEN(dev_priv) >= 9) {
15152 skl_wm_get_hw_state(dev);
15153 } else if (HAS_PCH_SPLIT(dev_priv)) {
15154 ilk_wm_get_hw_state(dev);
15155 }
15156
15157 for_each_intel_crtc(dev, crtc) {
15158 u64 put_domains;
15159
15160 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15161 if (WARN_ON(put_domains))
15162 modeset_put_power_domains(dev_priv, put_domains);
15163 }
15164 intel_display_set_init_power(dev_priv, false);
15165
15166 intel_power_domains_verify_state(dev_priv);
15167
15168 intel_fbc_init_pipe_state(dev_priv);
15169 }
15170
15171 void intel_display_resume(struct drm_device *dev)
15172 {
15173 struct drm_i915_private *dev_priv = to_i915(dev);
15174 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15175 struct drm_modeset_acquire_ctx ctx;
15176 int ret;
15177
15178 dev_priv->modeset_restore_state = NULL;
15179 if (state)
15180 state->acquire_ctx = &ctx;
15181
15182 drm_modeset_acquire_init(&ctx, 0);
15183
15184 while (1) {
15185 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15186 if (ret != -EDEADLK)
15187 break;
15188
15189 drm_modeset_backoff(&ctx);
15190 }
15191
15192 if (!ret)
15193 ret = __intel_display_resume(dev, state, &ctx);
15194
15195 intel_enable_ipc(dev_priv);
15196 drm_modeset_drop_locks(&ctx);
15197 drm_modeset_acquire_fini(&ctx);
15198
15199 if (ret)
15200 DRM_ERROR("Restoring old state failed with %i\n", ret);
15201 if (state)
15202 drm_atomic_state_put(state);
15203 }
15204
15205 void intel_modeset_gem_init(struct drm_device *dev)
15206 {
15207 struct drm_i915_private *dev_priv = to_i915(dev);
15208
15209 intel_init_gt_powersave(dev_priv);
15210
15211 intel_setup_overlay(dev_priv);
15212 }
15213
15214 int intel_connector_register(struct drm_connector *connector)
15215 {
15216 struct intel_connector *intel_connector = to_intel_connector(connector);
15217 int ret;
15218
15219 ret = intel_backlight_device_register(intel_connector);
15220 if (ret)
15221 goto err;
15222
15223 return 0;
15224
15225 err:
15226 return ret;
15227 }
15228
15229 void intel_connector_unregister(struct drm_connector *connector)
15230 {
15231 struct intel_connector *intel_connector = to_intel_connector(connector);
15232
15233 intel_backlight_device_unregister(intel_connector);
15234 intel_panel_destroy_backlight(connector);
15235 }
15236
15237 void intel_modeset_cleanup(struct drm_device *dev)
15238 {
15239 struct drm_i915_private *dev_priv = to_i915(dev);
15240
15241 flush_work(&dev_priv->atomic_helper.free_work);
15242 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15243
15244 intel_disable_gt_powersave(dev_priv);
15245
15246 /*
15247 * Interrupts and polling as the first thing to avoid creating havoc.
15248 * Too much stuff here (turning of connectors, ...) would
15249 * experience fancy races otherwise.
15250 */
15251 intel_irq_uninstall(dev_priv);
15252
15253 /*
15254 * Due to the hpd irq storm handling the hotplug work can re-arm the
15255 * poll handlers. Hence disable polling after hpd handling is shut down.
15256 */
15257 drm_kms_helper_poll_fini(dev);
15258
15259 /* poll work can call into fbdev, hence clean that up afterwards */
15260 intel_fbdev_fini(dev_priv);
15261
15262 intel_unregister_dsm_handler();
15263
15264 intel_fbc_global_disable(dev_priv);
15265
15266 /* flush any delayed tasks or pending work */
15267 flush_scheduled_work();
15268
15269 drm_mode_config_cleanup(dev);
15270
15271 intel_cleanup_overlay(dev_priv);
15272
15273 intel_cleanup_gt_powersave(dev_priv);
15274
15275 intel_teardown_gmbus(dev_priv);
15276 }
15277
15278 void intel_connector_attach_encoder(struct intel_connector *connector,
15279 struct intel_encoder *encoder)
15280 {
15281 connector->encoder = encoder;
15282 drm_mode_connector_attach_encoder(&connector->base,
15283 &encoder->base);
15284 }
15285
15286 /*
15287 * set vga decode state - true == enable VGA decode
15288 */
15289 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15290 {
15291 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15292 u16 gmch_ctrl;
15293
15294 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15295 DRM_ERROR("failed to read control word\n");
15296 return -EIO;
15297 }
15298
15299 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15300 return 0;
15301
15302 if (state)
15303 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15304 else
15305 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15306
15307 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15308 DRM_ERROR("failed to write control word\n");
15309 return -EIO;
15310 }
15311
15312 return 0;
15313 }
15314
15315 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15316
15317 struct intel_display_error_state {
15318
15319 u32 power_well_driver;
15320
15321 int num_transcoders;
15322
15323 struct intel_cursor_error_state {
15324 u32 control;
15325 u32 position;
15326 u32 base;
15327 u32 size;
15328 } cursor[I915_MAX_PIPES];
15329
15330 struct intel_pipe_error_state {
15331 bool power_domain_on;
15332 u32 source;
15333 u32 stat;
15334 } pipe[I915_MAX_PIPES];
15335
15336 struct intel_plane_error_state {
15337 u32 control;
15338 u32 stride;
15339 u32 size;
15340 u32 pos;
15341 u32 addr;
15342 u32 surface;
15343 u32 tile_offset;
15344 } plane[I915_MAX_PIPES];
15345
15346 struct intel_transcoder_error_state {
15347 bool power_domain_on;
15348 enum transcoder cpu_transcoder;
15349
15350 u32 conf;
15351
15352 u32 htotal;
15353 u32 hblank;
15354 u32 hsync;
15355 u32 vtotal;
15356 u32 vblank;
15357 u32 vsync;
15358 } transcoder[4];
15359 };
15360
15361 struct intel_display_error_state *
15362 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15363 {
15364 struct intel_display_error_state *error;
15365 int transcoders[] = {
15366 TRANSCODER_A,
15367 TRANSCODER_B,
15368 TRANSCODER_C,
15369 TRANSCODER_EDP,
15370 };
15371 int i;
15372
15373 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15374 return NULL;
15375
15376 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15377 if (error == NULL)
15378 return NULL;
15379
15380 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15381 error->power_well_driver =
15382 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15383
15384 for_each_pipe(dev_priv, i) {
15385 error->pipe[i].power_domain_on =
15386 __intel_display_power_is_enabled(dev_priv,
15387 POWER_DOMAIN_PIPE(i));
15388 if (!error->pipe[i].power_domain_on)
15389 continue;
15390
15391 error->cursor[i].control = I915_READ(CURCNTR(i));
15392 error->cursor[i].position = I915_READ(CURPOS(i));
15393 error->cursor[i].base = I915_READ(CURBASE(i));
15394
15395 error->plane[i].control = I915_READ(DSPCNTR(i));
15396 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15397 if (INTEL_GEN(dev_priv) <= 3) {
15398 error->plane[i].size = I915_READ(DSPSIZE(i));
15399 error->plane[i].pos = I915_READ(DSPPOS(i));
15400 }
15401 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15402 error->plane[i].addr = I915_READ(DSPADDR(i));
15403 if (INTEL_GEN(dev_priv) >= 4) {
15404 error->plane[i].surface = I915_READ(DSPSURF(i));
15405 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15406 }
15407
15408 error->pipe[i].source = I915_READ(PIPESRC(i));
15409
15410 if (HAS_GMCH_DISPLAY(dev_priv))
15411 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15412 }
15413
15414 /* Note: this does not include DSI transcoders. */
15415 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15416 if (HAS_DDI(dev_priv))
15417 error->num_transcoders++; /* Account for eDP. */
15418
15419 for (i = 0; i < error->num_transcoders; i++) {
15420 enum transcoder cpu_transcoder = transcoders[i];
15421
15422 error->transcoder[i].power_domain_on =
15423 __intel_display_power_is_enabled(dev_priv,
15424 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15425 if (!error->transcoder[i].power_domain_on)
15426 continue;
15427
15428 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15429
15430 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15431 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15432 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15433 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15434 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15435 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15436 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15437 }
15438
15439 return error;
15440 }
15441
15442 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15443
15444 void
15445 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15446 struct intel_display_error_state *error)
15447 {
15448 struct drm_i915_private *dev_priv = m->i915;
15449 int i;
15450
15451 if (!error)
15452 return;
15453
15454 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15455 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15456 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15457 error->power_well_driver);
15458 for_each_pipe(dev_priv, i) {
15459 err_printf(m, "Pipe [%d]:\n", i);
15460 err_printf(m, " Power: %s\n",
15461 onoff(error->pipe[i].power_domain_on));
15462 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15463 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15464
15465 err_printf(m, "Plane [%d]:\n", i);
15466 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15467 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15468 if (INTEL_GEN(dev_priv) <= 3) {
15469 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15470 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15471 }
15472 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15473 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15474 if (INTEL_GEN(dev_priv) >= 4) {
15475 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15476 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15477 }
15478
15479 err_printf(m, "Cursor [%d]:\n", i);
15480 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15481 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15482 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15483 }
15484
15485 for (i = 0; i < error->num_transcoders; i++) {
15486 err_printf(m, "CPU transcoder: %s\n",
15487 transcoder_name(error->transcoder[i].cpu_transcoder));
15488 err_printf(m, " Power: %s\n",
15489 onoff(error->transcoder[i].power_domain_on));
15490 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15491 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15492 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15493 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15494 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15495 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15496 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15497 }
15498 }
15499
15500 #endif
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