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Merge tag 'topic/drm-misc-2016-02-12' into drm-intel-next-queued
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47 #include <linux/reservation.h>
48 #include <linux/dma-buf.h>
49
50 /* Primary plane formats for gen <= 3 */
51 static const uint32_t i8xx_primary_formats[] = {
52 DRM_FORMAT_C8,
53 DRM_FORMAT_RGB565,
54 DRM_FORMAT_XRGB1555,
55 DRM_FORMAT_XRGB8888,
56 };
57
58 /* Primary plane formats for gen >= 4 */
59 static const uint32_t i965_primary_formats[] = {
60 DRM_FORMAT_C8,
61 DRM_FORMAT_RGB565,
62 DRM_FORMAT_XRGB8888,
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_XRGB2101010,
65 DRM_FORMAT_XBGR2101010,
66 };
67
68 static const uint32_t skl_primary_formats[] = {
69 DRM_FORMAT_C8,
70 DRM_FORMAT_RGB565,
71 DRM_FORMAT_XRGB8888,
72 DRM_FORMAT_XBGR8888,
73 DRM_FORMAT_ARGB8888,
74 DRM_FORMAT_ABGR8888,
75 DRM_FORMAT_XRGB2101010,
76 DRM_FORMAT_XBGR2101010,
77 DRM_FORMAT_YUYV,
78 DRM_FORMAT_YVYU,
79 DRM_FORMAT_UYVY,
80 DRM_FORMAT_VYUY,
81 };
82
83 /* Cursor formats */
84 static const uint32_t intel_cursor_formats[] = {
85 DRM_FORMAT_ARGB8888,
86 };
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg)
152 {
153 u32 val;
154 int divider;
155
156 if (dev_priv->hpll_freq == 0)
157 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
170 }
171
172 int
173 intel_pch_rawclk(struct drm_device *dev)
174 {
175 struct drm_i915_private *dev_priv = dev->dev_private;
176
177 WARN_ON(!HAS_PCH_SPLIT(dev));
178
179 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
180 }
181
182 /* hrawclock is 1/4 the FSB frequency */
183 int intel_hrawclk(struct drm_device *dev)
184 {
185 struct drm_i915_private *dev_priv = dev->dev_private;
186 uint32_t clkcfg;
187
188 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
189 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
190 return 200;
191
192 clkcfg = I915_READ(CLKCFG);
193 switch (clkcfg & CLKCFG_FSB_MASK) {
194 case CLKCFG_FSB_400:
195 return 100;
196 case CLKCFG_FSB_533:
197 return 133;
198 case CLKCFG_FSB_667:
199 return 166;
200 case CLKCFG_FSB_800:
201 return 200;
202 case CLKCFG_FSB_1067:
203 return 266;
204 case CLKCFG_FSB_1333:
205 return 333;
206 /* these two are just a guess; one of them might be right */
207 case CLKCFG_FSB_1600:
208 case CLKCFG_FSB_1600_ALT:
209 return 400;
210 default:
211 return 133;
212 }
213 }
214
215 static void intel_update_czclk(struct drm_i915_private *dev_priv)
216 {
217 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
218 return;
219
220 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
221 CCK_CZ_CLOCK_CONTROL);
222
223 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
224 }
225
226 static inline u32 /* units of 100MHz */
227 intel_fdi_link_freq(struct drm_device *dev)
228 {
229 if (IS_GEN5(dev)) {
230 struct drm_i915_private *dev_priv = dev->dev_private;
231 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
232 } else
233 return 27;
234 }
235
236 static const intel_limit_t intel_limits_i8xx_dac = {
237 .dot = { .min = 25000, .max = 350000 },
238 .vco = { .min = 908000, .max = 1512000 },
239 .n = { .min = 2, .max = 16 },
240 .m = { .min = 96, .max = 140 },
241 .m1 = { .min = 18, .max = 26 },
242 .m2 = { .min = 6, .max = 16 },
243 .p = { .min = 4, .max = 128 },
244 .p1 = { .min = 2, .max = 33 },
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 4, .p2_fast = 2 },
247 };
248
249 static const intel_limit_t intel_limits_i8xx_dvo = {
250 .dot = { .min = 25000, .max = 350000 },
251 .vco = { .min = 908000, .max = 1512000 },
252 .n = { .min = 2, .max = 16 },
253 .m = { .min = 96, .max = 140 },
254 .m1 = { .min = 18, .max = 26 },
255 .m2 = { .min = 6, .max = 16 },
256 .p = { .min = 4, .max = 128 },
257 .p1 = { .min = 2, .max = 33 },
258 .p2 = { .dot_limit = 165000,
259 .p2_slow = 4, .p2_fast = 4 },
260 };
261
262 static const intel_limit_t intel_limits_i8xx_lvds = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 908000, .max = 1512000 },
265 .n = { .min = 2, .max = 16 },
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 1, .max = 6 },
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 14, .p2_fast = 7 },
273 };
274
275 static const intel_limit_t intel_limits_i9xx_sdvo = {
276 .dot = { .min = 20000, .max = 400000 },
277 .vco = { .min = 1400000, .max = 2800000 },
278 .n = { .min = 1, .max = 6 },
279 .m = { .min = 70, .max = 120 },
280 .m1 = { .min = 8, .max = 18 },
281 .m2 = { .min = 3, .max = 7 },
282 .p = { .min = 5, .max = 80 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 200000,
285 .p2_slow = 10, .p2_fast = 5 },
286 };
287
288 static const intel_limit_t intel_limits_i9xx_lvds = {
289 .dot = { .min = 20000, .max = 400000 },
290 .vco = { .min = 1400000, .max = 2800000 },
291 .n = { .min = 1, .max = 6 },
292 .m = { .min = 70, .max = 120 },
293 .m1 = { .min = 8, .max = 18 },
294 .m2 = { .min = 3, .max = 7 },
295 .p = { .min = 7, .max = 98 },
296 .p1 = { .min = 1, .max = 8 },
297 .p2 = { .dot_limit = 112000,
298 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301
302 static const intel_limit_t intel_limits_g4x_sdvo = {
303 .dot = { .min = 25000, .max = 270000 },
304 .vco = { .min = 1750000, .max = 3500000},
305 .n = { .min = 1, .max = 4 },
306 .m = { .min = 104, .max = 138 },
307 .m1 = { .min = 17, .max = 23 },
308 .m2 = { .min = 5, .max = 11 },
309 .p = { .min = 10, .max = 30 },
310 .p1 = { .min = 1, .max = 3},
311 .p2 = { .dot_limit = 270000,
312 .p2_slow = 10,
313 .p2_fast = 10
314 },
315 };
316
317 static const intel_limit_t intel_limits_g4x_hdmi = {
318 .dot = { .min = 22000, .max = 400000 },
319 .vco = { .min = 1750000, .max = 3500000},
320 .n = { .min = 1, .max = 4 },
321 .m = { .min = 104, .max = 138 },
322 .m1 = { .min = 16, .max = 23 },
323 .m2 = { .min = 5, .max = 11 },
324 .p = { .min = 5, .max = 80 },
325 .p1 = { .min = 1, .max = 8},
326 .p2 = { .dot_limit = 165000,
327 .p2_slow = 10, .p2_fast = 5 },
328 };
329
330 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
331 .dot = { .min = 20000, .max = 115000 },
332 .vco = { .min = 1750000, .max = 3500000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 104, .max = 138 },
335 .m1 = { .min = 17, .max = 23 },
336 .m2 = { .min = 5, .max = 11 },
337 .p = { .min = 28, .max = 112 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 0,
340 .p2_slow = 14, .p2_fast = 14
341 },
342 };
343
344 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
345 .dot = { .min = 80000, .max = 224000 },
346 .vco = { .min = 1750000, .max = 3500000 },
347 .n = { .min = 1, .max = 3 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 17, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 14, .max = 42 },
352 .p1 = { .min = 2, .max = 6 },
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 7, .p2_fast = 7
355 },
356 };
357
358 static const intel_limit_t intel_limits_pineview_sdvo = {
359 .dot = { .min = 20000, .max = 400000},
360 .vco = { .min = 1700000, .max = 3500000 },
361 /* Pineview's Ncounter is a ring counter */
362 .n = { .min = 3, .max = 6 },
363 .m = { .min = 2, .max = 256 },
364 /* Pineview only has one combined m divider, which we treat as m2. */
365 .m1 = { .min = 0, .max = 0 },
366 .m2 = { .min = 0, .max = 254 },
367 .p = { .min = 5, .max = 80 },
368 .p1 = { .min = 1, .max = 8 },
369 .p2 = { .dot_limit = 200000,
370 .p2_slow = 10, .p2_fast = 5 },
371 };
372
373 static const intel_limit_t intel_limits_pineview_lvds = {
374 .dot = { .min = 20000, .max = 400000 },
375 .vco = { .min = 1700000, .max = 3500000 },
376 .n = { .min = 3, .max = 6 },
377 .m = { .min = 2, .max = 256 },
378 .m1 = { .min = 0, .max = 0 },
379 .m2 = { .min = 0, .max = 254 },
380 .p = { .min = 7, .max = 112 },
381 .p1 = { .min = 1, .max = 8 },
382 .p2 = { .dot_limit = 112000,
383 .p2_slow = 14, .p2_fast = 14 },
384 };
385
386 /* Ironlake / Sandybridge
387 *
388 * We calculate clock using (register_value + 2) for N/M1/M2, so here
389 * the range value for them is (actual_value - 2).
390 */
391 static const intel_limit_t intel_limits_ironlake_dac = {
392 .dot = { .min = 25000, .max = 350000 },
393 .vco = { .min = 1760000, .max = 3510000 },
394 .n = { .min = 1, .max = 5 },
395 .m = { .min = 79, .max = 127 },
396 .m1 = { .min = 12, .max = 22 },
397 .m2 = { .min = 5, .max = 9 },
398 .p = { .min = 5, .max = 80 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 225000,
401 .p2_slow = 10, .p2_fast = 5 },
402 };
403
404 static const intel_limit_t intel_limits_ironlake_single_lvds = {
405 .dot = { .min = 25000, .max = 350000 },
406 .vco = { .min = 1760000, .max = 3510000 },
407 .n = { .min = 1, .max = 3 },
408 .m = { .min = 79, .max = 118 },
409 .m1 = { .min = 12, .max = 22 },
410 .m2 = { .min = 5, .max = 9 },
411 .p = { .min = 28, .max = 112 },
412 .p1 = { .min = 2, .max = 8 },
413 .p2 = { .dot_limit = 225000,
414 .p2_slow = 14, .p2_fast = 14 },
415 };
416
417 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 3 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 14, .max = 56 },
425 .p1 = { .min = 2, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 7, .p2_fast = 7 },
428 };
429
430 /* LVDS 100mhz refclk limits. */
431 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 2 },
435 .m = { .min = 79, .max = 126 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 126 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 42 },
452 .p1 = { .min = 2, .max = 6 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 static const intel_limit_t intel_limits_vlv = {
458 /*
459 * These are the data rate limits (measured in fast clocks)
460 * since those are the strictest limits we have. The fast
461 * clock and actual rate limits are more relaxed, so checking
462 * them would make no difference.
463 */
464 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
465 .vco = { .min = 4000000, .max = 6000000 },
466 .n = { .min = 1, .max = 7 },
467 .m1 = { .min = 2, .max = 3 },
468 .m2 = { .min = 11, .max = 156 },
469 .p1 = { .min = 2, .max = 3 },
470 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
471 };
472
473 static const intel_limit_t intel_limits_chv = {
474 /*
475 * These are the data rate limits (measured in fast clocks)
476 * since those are the strictest limits we have. The fast
477 * clock and actual rate limits are more relaxed, so checking
478 * them would make no difference.
479 */
480 .dot = { .min = 25000 * 5, .max = 540000 * 5},
481 .vco = { .min = 4800000, .max = 6480000 },
482 .n = { .min = 1, .max = 1 },
483 .m1 = { .min = 2, .max = 2 },
484 .m2 = { .min = 24 << 22, .max = 175 << 22 },
485 .p1 = { .min = 2, .max = 4 },
486 .p2 = { .p2_slow = 1, .p2_fast = 14 },
487 };
488
489 static const intel_limit_t intel_limits_bxt = {
490 /* FIXME: find real dot limits */
491 .dot = { .min = 0, .max = INT_MAX },
492 .vco = { .min = 4800000, .max = 6700000 },
493 .n = { .min = 1, .max = 1 },
494 .m1 = { .min = 2, .max = 2 },
495 /* FIXME: find real m2 limits */
496 .m2 = { .min = 2 << 22, .max = 255 << 22 },
497 .p1 = { .min = 2, .max = 4 },
498 .p2 = { .p2_slow = 1, .p2_fast = 20 },
499 };
500
501 static bool
502 needs_modeset(struct drm_crtc_state *state)
503 {
504 return drm_atomic_crtc_needs_modeset(state);
505 }
506
507 /**
508 * Returns whether any output on the specified pipe is of the specified type
509 */
510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
511 {
512 struct drm_device *dev = crtc->base.dev;
513 struct intel_encoder *encoder;
514
515 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
516 if (encoder->type == type)
517 return true;
518
519 return false;
520 }
521
522 /**
523 * Returns whether any output on the specified pipe will have the specified
524 * type after a staged modeset is complete, i.e., the same as
525 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
526 * encoder->crtc.
527 */
528 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
529 int type)
530 {
531 struct drm_atomic_state *state = crtc_state->base.state;
532 struct drm_connector *connector;
533 struct drm_connector_state *connector_state;
534 struct intel_encoder *encoder;
535 int i, num_connectors = 0;
536
537 for_each_connector_in_state(state, connector, connector_state, i) {
538 if (connector_state->crtc != crtc_state->base.crtc)
539 continue;
540
541 num_connectors++;
542
543 encoder = to_intel_encoder(connector_state->best_encoder);
544 if (encoder->type == type)
545 return true;
546 }
547
548 WARN_ON(num_connectors == 0);
549
550 return false;
551 }
552
553 static const intel_limit_t *
554 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
555 {
556 struct drm_device *dev = crtc_state->base.crtc->dev;
557 const intel_limit_t *limit;
558
559 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
560 if (intel_is_dual_link_lvds(dev)) {
561 if (refclk == 100000)
562 limit = &intel_limits_ironlake_dual_lvds_100m;
563 else
564 limit = &intel_limits_ironlake_dual_lvds;
565 } else {
566 if (refclk == 100000)
567 limit = &intel_limits_ironlake_single_lvds_100m;
568 else
569 limit = &intel_limits_ironlake_single_lvds;
570 }
571 } else
572 limit = &intel_limits_ironlake_dac;
573
574 return limit;
575 }
576
577 static const intel_limit_t *
578 intel_g4x_limit(struct intel_crtc_state *crtc_state)
579 {
580 struct drm_device *dev = crtc_state->base.crtc->dev;
581 const intel_limit_t *limit;
582
583 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
584 if (intel_is_dual_link_lvds(dev))
585 limit = &intel_limits_g4x_dual_channel_lvds;
586 else
587 limit = &intel_limits_g4x_single_channel_lvds;
588 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
589 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
590 limit = &intel_limits_g4x_hdmi;
591 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
592 limit = &intel_limits_g4x_sdvo;
593 } else /* The option is for other outputs */
594 limit = &intel_limits_i9xx_sdvo;
595
596 return limit;
597 }
598
599 static const intel_limit_t *
600 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
601 {
602 struct drm_device *dev = crtc_state->base.crtc->dev;
603 const intel_limit_t *limit;
604
605 if (IS_BROXTON(dev))
606 limit = &intel_limits_bxt;
607 else if (HAS_PCH_SPLIT(dev))
608 limit = intel_ironlake_limit(crtc_state, refclk);
609 else if (IS_G4X(dev)) {
610 limit = intel_g4x_limit(crtc_state);
611 } else if (IS_PINEVIEW(dev)) {
612 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
613 limit = &intel_limits_pineview_lvds;
614 else
615 limit = &intel_limits_pineview_sdvo;
616 } else if (IS_CHERRYVIEW(dev)) {
617 limit = &intel_limits_chv;
618 } else if (IS_VALLEYVIEW(dev)) {
619 limit = &intel_limits_vlv;
620 } else if (!IS_GEN2(dev)) {
621 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
622 limit = &intel_limits_i9xx_lvds;
623 else
624 limit = &intel_limits_i9xx_sdvo;
625 } else {
626 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
627 limit = &intel_limits_i8xx_lvds;
628 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
629 limit = &intel_limits_i8xx_dvo;
630 else
631 limit = &intel_limits_i8xx_dac;
632 }
633 return limit;
634 }
635
636 /*
637 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
638 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
639 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
640 * The helpers' return value is the rate of the clock that is fed to the
641 * display engine's pipe which can be the above fast dot clock rate or a
642 * divided-down version of it.
643 */
644 /* m1 is reserved as 0 in Pineview, n is a ring counter */
645 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
646 {
647 clock->m = clock->m2 + 2;
648 clock->p = clock->p1 * clock->p2;
649 if (WARN_ON(clock->n == 0 || clock->p == 0))
650 return 0;
651 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
652 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
653
654 return clock->dot;
655 }
656
657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
658 {
659 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
660 }
661
662 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
663 {
664 clock->m = i9xx_dpll_compute_m(clock);
665 clock->p = clock->p1 * clock->p2;
666 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
667 return 0;
668 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
669 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
670
671 return clock->dot;
672 }
673
674 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
675 {
676 clock->m = clock->m1 * clock->m2;
677 clock->p = clock->p1 * clock->p2;
678 if (WARN_ON(clock->n == 0 || clock->p == 0))
679 return 0;
680 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
681 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
682
683 return clock->dot / 5;
684 }
685
686 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
687 {
688 clock->m = clock->m1 * clock->m2;
689 clock->p = clock->p1 * clock->p2;
690 if (WARN_ON(clock->n == 0 || clock->p == 0))
691 return 0;
692 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
693 clock->n << 22);
694 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
695
696 return clock->dot / 5;
697 }
698
699 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
700 /**
701 * Returns whether the given set of divisors are valid for a given refclk with
702 * the given connectors.
703 */
704
705 static bool intel_PLL_is_valid(struct drm_device *dev,
706 const intel_limit_t *limit,
707 const intel_clock_t *clock)
708 {
709 if (clock->n < limit->n.min || limit->n.max < clock->n)
710 INTELPllInvalid("n out of range\n");
711 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
712 INTELPllInvalid("p1 out of range\n");
713 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
714 INTELPllInvalid("m2 out of range\n");
715 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
716 INTELPllInvalid("m1 out of range\n");
717
718 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
719 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
720 if (clock->m1 <= clock->m2)
721 INTELPllInvalid("m1 <= m2\n");
722
723 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
724 if (clock->p < limit->p.min || limit->p.max < clock->p)
725 INTELPllInvalid("p out of range\n");
726 if (clock->m < limit->m.min || limit->m.max < clock->m)
727 INTELPllInvalid("m out of range\n");
728 }
729
730 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
731 INTELPllInvalid("vco out of range\n");
732 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
733 * connector, etc., rather than just a single range.
734 */
735 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
736 INTELPllInvalid("dot out of range\n");
737
738 return true;
739 }
740
741 static int
742 i9xx_select_p2_div(const intel_limit_t *limit,
743 const struct intel_crtc_state *crtc_state,
744 int target)
745 {
746 struct drm_device *dev = crtc_state->base.crtc->dev;
747
748 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
749 /*
750 * For LVDS just rely on its current settings for dual-channel.
751 * We haven't figured out how to reliably set up different
752 * single/dual channel state, if we even can.
753 */
754 if (intel_is_dual_link_lvds(dev))
755 return limit->p2.p2_fast;
756 else
757 return limit->p2.p2_slow;
758 } else {
759 if (target < limit->p2.dot_limit)
760 return limit->p2.p2_slow;
761 else
762 return limit->p2.p2_fast;
763 }
764 }
765
766 static bool
767 i9xx_find_best_dpll(const intel_limit_t *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
771 {
772 struct drm_device *dev = crtc_state->base.crtc->dev;
773 intel_clock_t clock;
774 int err = target;
775
776 memset(best_clock, 0, sizeof(*best_clock));
777
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
779
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
781 clock.m1++) {
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 if (clock.m2 >= clock.m1)
785 break;
786 for (clock.n = limit->n.min;
787 clock.n <= limit->n.max; clock.n++) {
788 for (clock.p1 = limit->p1.min;
789 clock.p1 <= limit->p1.max; clock.p1++) {
790 int this_err;
791
792 i9xx_calc_dpll_params(refclk, &clock);
793 if (!intel_PLL_is_valid(dev, limit,
794 &clock))
795 continue;
796 if (match_clock &&
797 clock.p != match_clock->p)
798 continue;
799
800 this_err = abs(clock.dot - target);
801 if (this_err < err) {
802 *best_clock = clock;
803 err = this_err;
804 }
805 }
806 }
807 }
808 }
809
810 return (err != target);
811 }
812
813 static bool
814 pnv_find_best_dpll(const intel_limit_t *limit,
815 struct intel_crtc_state *crtc_state,
816 int target, int refclk, intel_clock_t *match_clock,
817 intel_clock_t *best_clock)
818 {
819 struct drm_device *dev = crtc_state->base.crtc->dev;
820 intel_clock_t clock;
821 int err = target;
822
823 memset(best_clock, 0, sizeof(*best_clock));
824
825 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
826
827 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
828 clock.m1++) {
829 for (clock.m2 = limit->m2.min;
830 clock.m2 <= limit->m2.max; clock.m2++) {
831 for (clock.n = limit->n.min;
832 clock.n <= limit->n.max; clock.n++) {
833 for (clock.p1 = limit->p1.min;
834 clock.p1 <= limit->p1.max; clock.p1++) {
835 int this_err;
836
837 pnv_calc_dpll_params(refclk, &clock);
838 if (!intel_PLL_is_valid(dev, limit,
839 &clock))
840 continue;
841 if (match_clock &&
842 clock.p != match_clock->p)
843 continue;
844
845 this_err = abs(clock.dot - target);
846 if (this_err < err) {
847 *best_clock = clock;
848 err = this_err;
849 }
850 }
851 }
852 }
853 }
854
855 return (err != target);
856 }
857
858 static bool
859 g4x_find_best_dpll(const intel_limit_t *limit,
860 struct intel_crtc_state *crtc_state,
861 int target, int refclk, intel_clock_t *match_clock,
862 intel_clock_t *best_clock)
863 {
864 struct drm_device *dev = crtc_state->base.crtc->dev;
865 intel_clock_t clock;
866 int max_n;
867 bool found = false;
868 /* approximately equals target * 0.00585 */
869 int err_most = (target >> 8) + (target >> 9);
870
871 memset(best_clock, 0, sizeof(*best_clock));
872
873 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
874
875 max_n = limit->n.max;
876 /* based on hardware requirement, prefer smaller n to precision */
877 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
878 /* based on hardware requirement, prefere larger m1,m2 */
879 for (clock.m1 = limit->m1.max;
880 clock.m1 >= limit->m1.min; clock.m1--) {
881 for (clock.m2 = limit->m2.max;
882 clock.m2 >= limit->m2.min; clock.m2--) {
883 for (clock.p1 = limit->p1.max;
884 clock.p1 >= limit->p1.min; clock.p1--) {
885 int this_err;
886
887 i9xx_calc_dpll_params(refclk, &clock);
888 if (!intel_PLL_is_valid(dev, limit,
889 &clock))
890 continue;
891
892 this_err = abs(clock.dot - target);
893 if (this_err < err_most) {
894 *best_clock = clock;
895 err_most = this_err;
896 max_n = clock.n;
897 found = true;
898 }
899 }
900 }
901 }
902 }
903 return found;
904 }
905
906 /*
907 * Check if the calculated PLL configuration is more optimal compared to the
908 * best configuration and error found so far. Return the calculated error.
909 */
910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
911 const intel_clock_t *calculated_clock,
912 const intel_clock_t *best_clock,
913 unsigned int best_error_ppm,
914 unsigned int *error_ppm)
915 {
916 /*
917 * For CHV ignore the error and consider only the P value.
918 * Prefer a bigger P value based on HW requirements.
919 */
920 if (IS_CHERRYVIEW(dev)) {
921 *error_ppm = 0;
922
923 return calculated_clock->p > best_clock->p;
924 }
925
926 if (WARN_ON_ONCE(!target_freq))
927 return false;
928
929 *error_ppm = div_u64(1000000ULL *
930 abs(target_freq - calculated_clock->dot),
931 target_freq);
932 /*
933 * Prefer a better P value over a better (smaller) error if the error
934 * is small. Ensure this preference for future configurations too by
935 * setting the error to 0.
936 */
937 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
938 *error_ppm = 0;
939
940 return true;
941 }
942
943 return *error_ppm + 10 < best_error_ppm;
944 }
945
946 static bool
947 vlv_find_best_dpll(const intel_limit_t *limit,
948 struct intel_crtc_state *crtc_state,
949 int target, int refclk, intel_clock_t *match_clock,
950 intel_clock_t *best_clock)
951 {
952 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
953 struct drm_device *dev = crtc->base.dev;
954 intel_clock_t clock;
955 unsigned int bestppm = 1000000;
956 /* min update 19.2 MHz */
957 int max_n = min(limit->n.max, refclk / 19200);
958 bool found = false;
959
960 target *= 5; /* fast clock */
961
962 memset(best_clock, 0, sizeof(*best_clock));
963
964 /* based on hardware requirement, prefer smaller n to precision */
965 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
966 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
967 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
968 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
969 clock.p = clock.p1 * clock.p2;
970 /* based on hardware requirement, prefer bigger m1,m2 values */
971 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
972 unsigned int ppm;
973
974 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
975 refclk * clock.m1);
976
977 vlv_calc_dpll_params(refclk, &clock);
978
979 if (!intel_PLL_is_valid(dev, limit,
980 &clock))
981 continue;
982
983 if (!vlv_PLL_is_optimal(dev, target,
984 &clock,
985 best_clock,
986 bestppm, &ppm))
987 continue;
988
989 *best_clock = clock;
990 bestppm = ppm;
991 found = true;
992 }
993 }
994 }
995 }
996
997 return found;
998 }
999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002 struct intel_crtc_state *crtc_state,
1003 int target, int refclk, intel_clock_t *match_clock,
1004 intel_clock_t *best_clock)
1005 {
1006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007 struct drm_device *dev = crtc->base.dev;
1008 unsigned int best_error_ppm;
1009 intel_clock_t clock;
1010 uint64_t m2;
1011 int found = false;
1012
1013 memset(best_clock, 0, sizeof(*best_clock));
1014 best_error_ppm = 1000000;
1015
1016 /*
1017 * Based on hardware doc, the n always set to 1, and m1 always
1018 * set to 2. If requires to support 200Mhz refclk, we need to
1019 * revisit this because n may not 1 anymore.
1020 */
1021 clock.n = 1, clock.m1 = 2;
1022 target *= 5; /* fast clock */
1023
1024 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025 for (clock.p2 = limit->p2.p2_fast;
1026 clock.p2 >= limit->p2.p2_slow;
1027 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028 unsigned int error_ppm;
1029
1030 clock.p = clock.p1 * clock.p2;
1031
1032 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033 clock.n) << 22, refclk * clock.m1);
1034
1035 if (m2 > INT_MAX/clock.m1)
1036 continue;
1037
1038 clock.m2 = m2;
1039
1040 chv_calc_dpll_params(refclk, &clock);
1041
1042 if (!intel_PLL_is_valid(dev, limit, &clock))
1043 continue;
1044
1045 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046 best_error_ppm, &error_ppm))
1047 continue;
1048
1049 *best_clock = clock;
1050 best_error_ppm = error_ppm;
1051 found = true;
1052 }
1053 }
1054
1055 return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059 intel_clock_t *best_clock)
1060 {
1061 int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064 target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071 /* Be paranoid as we can arrive here with only partial
1072 * state retrieved from the hardware during setup.
1073 *
1074 * We can ditch the adjusted_mode.crtc_clock check as soon
1075 * as Haswell has gained clock readout/fastboot support.
1076 *
1077 * We can ditch the crtc->primary->fb check as soon as we can
1078 * properly reconstruct framebuffers.
1079 *
1080 * FIXME: The intel_crtc->active here should be switched to
1081 * crtc->state->active once we have proper CRTC states wired up
1082 * for atomic.
1083 */
1084 return intel_crtc->active && crtc->primary->state->fb &&
1085 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089 enum pipe pipe)
1090 {
1091 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094 return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099 struct drm_i915_private *dev_priv = dev->dev_private;
1100 i915_reg_t reg = PIPEDSL(pipe);
1101 u32 line1, line2;
1102 u32 line_mask;
1103
1104 if (IS_GEN2(dev))
1105 line_mask = DSL_LINEMASK_GEN2;
1106 else
1107 line_mask = DSL_LINEMASK_GEN3;
1108
1109 line1 = I915_READ(reg) & line_mask;
1110 msleep(5);
1111 line2 = I915_READ(reg) & line_mask;
1112
1113 return line1 == line2;
1114 }
1115
1116 /*
1117 * intel_wait_for_pipe_off - wait for pipe to turn off
1118 * @crtc: crtc whose pipe to wait for
1119 *
1120 * After disabling a pipe, we can't wait for vblank in the usual way,
1121 * spinning on the vblank interrupt status bit, since we won't actually
1122 * see an interrupt when the pipe is disabled.
1123 *
1124 * On Gen4 and above:
1125 * wait for the pipe register state bit to turn off
1126 *
1127 * Otherwise:
1128 * wait for the display line value to settle (it usually
1129 * ends up stopping at the start of the next frame).
1130 *
1131 */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134 struct drm_device *dev = crtc->base.dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137 enum pipe pipe = crtc->pipe;
1138
1139 if (INTEL_INFO(dev)->gen >= 4) {
1140 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142 /* Wait for the Pipe State to go off */
1143 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144 100))
1145 WARN(1, "pipe_off wait timed out\n");
1146 } else {
1147 /* Wait for the display line to settle */
1148 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149 WARN(1, "pipe_off wait timed out\n");
1150 }
1151 }
1152
1153 /* Only for pre-ILK configs */
1154 void assert_pll(struct drm_i915_private *dev_priv,
1155 enum pipe pipe, bool state)
1156 {
1157 u32 val;
1158 bool cur_state;
1159
1160 val = I915_READ(DPLL(pipe));
1161 cur_state = !!(val & DPLL_VCO_ENABLE);
1162 I915_STATE_WARN(cur_state != state,
1163 "PLL state assertion failure (expected %s, current %s)\n",
1164 onoff(state), onoff(cur_state));
1165 }
1166
1167 /* XXX: the dsi pll is shared between MIPI DSI ports */
1168 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1169 {
1170 u32 val;
1171 bool cur_state;
1172
1173 mutex_lock(&dev_priv->sb_lock);
1174 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1175 mutex_unlock(&dev_priv->sb_lock);
1176
1177 cur_state = val & DSI_PLL_VCO_EN;
1178 I915_STATE_WARN(cur_state != state,
1179 "DSI PLL state assertion failure (expected %s, current %s)\n",
1180 onoff(state), onoff(cur_state));
1181 }
1182 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1183 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1184
1185 struct intel_shared_dpll *
1186 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1187 {
1188 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1189
1190 if (crtc->config->shared_dpll < 0)
1191 return NULL;
1192
1193 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1194 }
1195
1196 /* For ILK+ */
1197 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1198 struct intel_shared_dpll *pll,
1199 bool state)
1200 {
1201 bool cur_state;
1202 struct intel_dpll_hw_state hw_state;
1203
1204 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
1205 return;
1206
1207 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1208 I915_STATE_WARN(cur_state != state,
1209 "%s assertion failure (expected %s, current %s)\n",
1210 pll->name, onoff(state), onoff(cur_state));
1211 }
1212
1213 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, bool state)
1215 {
1216 bool cur_state;
1217 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1218 pipe);
1219
1220 if (HAS_DDI(dev_priv->dev)) {
1221 /* DDI does not have a specific FDI_TX register */
1222 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1223 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1224 } else {
1225 u32 val = I915_READ(FDI_TX_CTL(pipe));
1226 cur_state = !!(val & FDI_TX_ENABLE);
1227 }
1228 I915_STATE_WARN(cur_state != state,
1229 "FDI TX state assertion failure (expected %s, current %s)\n",
1230 onoff(state), onoff(cur_state));
1231 }
1232 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1233 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1234
1235 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1236 enum pipe pipe, bool state)
1237 {
1238 u32 val;
1239 bool cur_state;
1240
1241 val = I915_READ(FDI_RX_CTL(pipe));
1242 cur_state = !!(val & FDI_RX_ENABLE);
1243 I915_STATE_WARN(cur_state != state,
1244 "FDI RX state assertion failure (expected %s, current %s)\n",
1245 onoff(state), onoff(cur_state));
1246 }
1247 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1248 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1249
1250 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1251 enum pipe pipe)
1252 {
1253 u32 val;
1254
1255 /* ILK FDI PLL is always enabled */
1256 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1257 return;
1258
1259 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1260 if (HAS_DDI(dev_priv->dev))
1261 return;
1262
1263 val = I915_READ(FDI_TX_CTL(pipe));
1264 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1265 }
1266
1267 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1268 enum pipe pipe, bool state)
1269 {
1270 u32 val;
1271 bool cur_state;
1272
1273 val = I915_READ(FDI_RX_CTL(pipe));
1274 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1275 I915_STATE_WARN(cur_state != state,
1276 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1277 onoff(state), onoff(cur_state));
1278 }
1279
1280 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1281 enum pipe pipe)
1282 {
1283 struct drm_device *dev = dev_priv->dev;
1284 i915_reg_t pp_reg;
1285 u32 val;
1286 enum pipe panel_pipe = PIPE_A;
1287 bool locked = true;
1288
1289 if (WARN_ON(HAS_DDI(dev)))
1290 return;
1291
1292 if (HAS_PCH_SPLIT(dev)) {
1293 u32 port_sel;
1294
1295 pp_reg = PCH_PP_CONTROL;
1296 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1297
1298 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1299 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1300 panel_pipe = PIPE_B;
1301 /* XXX: else fix for eDP */
1302 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1303 /* presumably write lock depends on pipe, not port select */
1304 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1305 panel_pipe = pipe;
1306 } else {
1307 pp_reg = PP_CONTROL;
1308 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1309 panel_pipe = PIPE_B;
1310 }
1311
1312 val = I915_READ(pp_reg);
1313 if (!(val & PANEL_POWER_ON) ||
1314 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1315 locked = false;
1316
1317 I915_STATE_WARN(panel_pipe == pipe && locked,
1318 "panel assertion failure, pipe %c regs locked\n",
1319 pipe_name(pipe));
1320 }
1321
1322 static void assert_cursor(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
1324 {
1325 struct drm_device *dev = dev_priv->dev;
1326 bool cur_state;
1327
1328 if (IS_845G(dev) || IS_I865G(dev))
1329 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1330 else
1331 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1332
1333 I915_STATE_WARN(cur_state != state,
1334 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1335 pipe_name(pipe), onoff(state), onoff(cur_state));
1336 }
1337 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1338 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1339
1340 void assert_pipe(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, bool state)
1342 {
1343 bool cur_state;
1344 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1345 pipe);
1346
1347 /* if we need the pipe quirk it must be always on */
1348 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1349 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1350 state = true;
1351
1352 if (!intel_display_power_is_enabled(dev_priv,
1353 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1354 cur_state = false;
1355 } else {
1356 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1357 cur_state = !!(val & PIPECONF_ENABLE);
1358 }
1359
1360 I915_STATE_WARN(cur_state != state,
1361 "pipe %c assertion failure (expected %s, current %s)\n",
1362 pipe_name(pipe), onoff(state), onoff(cur_state));
1363 }
1364
1365 static void assert_plane(struct drm_i915_private *dev_priv,
1366 enum plane plane, bool state)
1367 {
1368 u32 val;
1369 bool cur_state;
1370
1371 val = I915_READ(DSPCNTR(plane));
1372 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1373 I915_STATE_WARN(cur_state != state,
1374 "plane %c assertion failure (expected %s, current %s)\n",
1375 plane_name(plane), onoff(state), onoff(cur_state));
1376 }
1377
1378 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1379 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1380
1381 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe)
1383 {
1384 struct drm_device *dev = dev_priv->dev;
1385 int i;
1386
1387 /* Primary planes are fixed to pipes on gen4+ */
1388 if (INTEL_INFO(dev)->gen >= 4) {
1389 u32 val = I915_READ(DSPCNTR(pipe));
1390 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1391 "plane %c assertion failure, should be disabled but not\n",
1392 plane_name(pipe));
1393 return;
1394 }
1395
1396 /* Need to check both planes against the pipe */
1397 for_each_pipe(dev_priv, i) {
1398 u32 val = I915_READ(DSPCNTR(i));
1399 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1400 DISPPLANE_SEL_PIPE_SHIFT;
1401 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1402 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1403 plane_name(i), pipe_name(pipe));
1404 }
1405 }
1406
1407 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe)
1409 {
1410 struct drm_device *dev = dev_priv->dev;
1411 int sprite;
1412
1413 if (INTEL_INFO(dev)->gen >= 9) {
1414 for_each_sprite(dev_priv, pipe, sprite) {
1415 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1416 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1417 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1418 sprite, pipe_name(pipe));
1419 }
1420 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1421 for_each_sprite(dev_priv, pipe, sprite) {
1422 u32 val = I915_READ(SPCNTR(pipe, sprite));
1423 I915_STATE_WARN(val & SP_ENABLE,
1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425 sprite_name(pipe, sprite), pipe_name(pipe));
1426 }
1427 } else if (INTEL_INFO(dev)->gen >= 7) {
1428 u32 val = I915_READ(SPRCTL(pipe));
1429 I915_STATE_WARN(val & SPRITE_ENABLE,
1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431 plane_name(pipe), pipe_name(pipe));
1432 } else if (INTEL_INFO(dev)->gen >= 5) {
1433 u32 val = I915_READ(DVSCNTR(pipe));
1434 I915_STATE_WARN(val & DVS_ENABLE,
1435 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1436 plane_name(pipe), pipe_name(pipe));
1437 }
1438 }
1439
1440 static void assert_vblank_disabled(struct drm_crtc *crtc)
1441 {
1442 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1443 drm_crtc_vblank_put(crtc);
1444 }
1445
1446 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1447 {
1448 u32 val;
1449 bool enabled;
1450
1451 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1452
1453 val = I915_READ(PCH_DREF_CONTROL);
1454 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1455 DREF_SUPERSPREAD_SOURCE_MASK));
1456 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1457 }
1458
1459 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1460 enum pipe pipe)
1461 {
1462 u32 val;
1463 bool enabled;
1464
1465 val = I915_READ(PCH_TRANSCONF(pipe));
1466 enabled = !!(val & TRANS_ENABLE);
1467 I915_STATE_WARN(enabled,
1468 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1469 pipe_name(pipe));
1470 }
1471
1472 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1473 enum pipe pipe, u32 port_sel, u32 val)
1474 {
1475 if ((val & DP_PORT_EN) == 0)
1476 return false;
1477
1478 if (HAS_PCH_CPT(dev_priv->dev)) {
1479 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1480 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1481 return false;
1482 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1483 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1484 return false;
1485 } else {
1486 if ((val & DP_PIPE_MASK) != (pipe << 30))
1487 return false;
1488 }
1489 return true;
1490 }
1491
1492 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1493 enum pipe pipe, u32 val)
1494 {
1495 if ((val & SDVO_ENABLE) == 0)
1496 return false;
1497
1498 if (HAS_PCH_CPT(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1500 return false;
1501 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1502 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1503 return false;
1504 } else {
1505 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1506 return false;
1507 }
1508 return true;
1509 }
1510
1511 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1512 enum pipe pipe, u32 val)
1513 {
1514 if ((val & LVDS_PORT_EN) == 0)
1515 return false;
1516
1517 if (HAS_PCH_CPT(dev_priv->dev)) {
1518 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519 return false;
1520 } else {
1521 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1522 return false;
1523 }
1524 return true;
1525 }
1526
1527 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1528 enum pipe pipe, u32 val)
1529 {
1530 if ((val & ADPA_DAC_ENABLE) == 0)
1531 return false;
1532 if (HAS_PCH_CPT(dev_priv->dev)) {
1533 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1534 return false;
1535 } else {
1536 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1537 return false;
1538 }
1539 return true;
1540 }
1541
1542 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1543 enum pipe pipe, i915_reg_t reg,
1544 u32 port_sel)
1545 {
1546 u32 val = I915_READ(reg);
1547 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1548 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1549 i915_mmio_reg_offset(reg), pipe_name(pipe));
1550
1551 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1552 && (val & DP_PIPEB_SELECT),
1553 "IBX PCH dp port still using transcoder B\n");
1554 }
1555
1556 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1557 enum pipe pipe, i915_reg_t reg)
1558 {
1559 u32 val = I915_READ(reg);
1560 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1561 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1562 i915_mmio_reg_offset(reg), pipe_name(pipe));
1563
1564 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1565 && (val & SDVO_PIPE_B_SELECT),
1566 "IBX PCH hdmi port still using transcoder B\n");
1567 }
1568
1569 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1570 enum pipe pipe)
1571 {
1572 u32 val;
1573
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1575 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1577
1578 val = I915_READ(PCH_ADPA);
1579 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1580 "PCH VGA enabled on transcoder %c, should be disabled\n",
1581 pipe_name(pipe));
1582
1583 val = I915_READ(PCH_LVDS);
1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1586 pipe_name(pipe));
1587
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1591 }
1592
1593 static void vlv_enable_pll(struct intel_crtc *crtc,
1594 const struct intel_crtc_state *pipe_config)
1595 {
1596 struct drm_device *dev = crtc->base.dev;
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 i915_reg_t reg = DPLL(crtc->pipe);
1599 u32 dpll = pipe_config->dpll_hw_state.dpll;
1600
1601 assert_pipe_disabled(dev_priv, crtc->pipe);
1602
1603 /* PLL is protected by panel, make sure we can write it */
1604 if (IS_MOBILE(dev_priv->dev))
1605 assert_panel_unlocked(dev_priv, crtc->pipe);
1606
1607 I915_WRITE(reg, dpll);
1608 POSTING_READ(reg);
1609 udelay(150);
1610
1611 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1612 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1613
1614 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1615 POSTING_READ(DPLL_MD(crtc->pipe));
1616
1617 /* We do this three times for luck */
1618 I915_WRITE(reg, dpll);
1619 POSTING_READ(reg);
1620 udelay(150); /* wait for warmup */
1621 I915_WRITE(reg, dpll);
1622 POSTING_READ(reg);
1623 udelay(150); /* wait for warmup */
1624 I915_WRITE(reg, dpll);
1625 POSTING_READ(reg);
1626 udelay(150); /* wait for warmup */
1627 }
1628
1629 static void chv_enable_pll(struct intel_crtc *crtc,
1630 const struct intel_crtc_state *pipe_config)
1631 {
1632 struct drm_device *dev = crtc->base.dev;
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 int pipe = crtc->pipe;
1635 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1636 u32 tmp;
1637
1638 assert_pipe_disabled(dev_priv, crtc->pipe);
1639
1640 mutex_lock(&dev_priv->sb_lock);
1641
1642 /* Enable back the 10bit clock to display controller */
1643 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1644 tmp |= DPIO_DCLKP_EN;
1645 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1646
1647 mutex_unlock(&dev_priv->sb_lock);
1648
1649 /*
1650 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1651 */
1652 udelay(1);
1653
1654 /* Enable PLL */
1655 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1656
1657 /* Check PLL is locked */
1658 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1659 DRM_ERROR("PLL %d failed to lock\n", pipe);
1660
1661 /* not sure when this should be written */
1662 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1663 POSTING_READ(DPLL_MD(pipe));
1664 }
1665
1666 static int intel_num_dvo_pipes(struct drm_device *dev)
1667 {
1668 struct intel_crtc *crtc;
1669 int count = 0;
1670
1671 for_each_intel_crtc(dev, crtc)
1672 count += crtc->base.state->active &&
1673 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1674
1675 return count;
1676 }
1677
1678 static void i9xx_enable_pll(struct intel_crtc *crtc)
1679 {
1680 struct drm_device *dev = crtc->base.dev;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 i915_reg_t reg = DPLL(crtc->pipe);
1683 u32 dpll = crtc->config->dpll_hw_state.dpll;
1684
1685 assert_pipe_disabled(dev_priv, crtc->pipe);
1686
1687 /* No really, not for ILK+ */
1688 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1689
1690 /* PLL is protected by panel, make sure we can write it */
1691 if (IS_MOBILE(dev) && !IS_I830(dev))
1692 assert_panel_unlocked(dev_priv, crtc->pipe);
1693
1694 /* Enable DVO 2x clock on both PLLs if necessary */
1695 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1696 /*
1697 * It appears to be important that we don't enable this
1698 * for the current pipe before otherwise configuring the
1699 * PLL. No idea how this should be handled if multiple
1700 * DVO outputs are enabled simultaneosly.
1701 */
1702 dpll |= DPLL_DVO_2X_MODE;
1703 I915_WRITE(DPLL(!crtc->pipe),
1704 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1705 }
1706
1707 /*
1708 * Apparently we need to have VGA mode enabled prior to changing
1709 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1710 * dividers, even though the register value does change.
1711 */
1712 I915_WRITE(reg, 0);
1713
1714 I915_WRITE(reg, dpll);
1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
1722 crtc->config->dpll_hw_state.dpll_md);
1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
1731
1732 /* We do this three times for luck */
1733 I915_WRITE(reg, dpll);
1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
1736 I915_WRITE(reg, dpll);
1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
1739 I915_WRITE(reg, dpll);
1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745 * i9xx_disable_pll - disable a PLL
1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762 !intel_num_dvo_pipes(dev)) {
1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1778 POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783 u32 val;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
1792 val = DPLL_VGA_MODE_DIS;
1793 if (pipe == PIPE_B)
1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
1797
1798 }
1799
1800 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801 {
1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1803 u32 val;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
1808 /* Set PLL en = 0 */
1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1811 if (pipe != PIPE_A)
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
1815
1816 mutex_lock(&dev_priv->sb_lock);
1817
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
1823 mutex_unlock(&dev_priv->sb_lock);
1824 }
1825
1826 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
1829 {
1830 u32 port_mask;
1831 i915_reg_t dpll_reg;
1832
1833 switch (dport->port) {
1834 case PORT_B:
1835 port_mask = DPLL_PORTB_READY_MASK;
1836 dpll_reg = DPLL(0);
1837 break;
1838 case PORT_C:
1839 port_mask = DPLL_PORTC_READY_MASK;
1840 dpll_reg = DPLL(0);
1841 expected_mask <<= 4;
1842 break;
1843 case PORT_D:
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
1846 break;
1847 default:
1848 BUG();
1849 }
1850
1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1854 }
1855
1856 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857 {
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
1862 if (WARN_ON(pll == NULL))
1863 return;
1864
1865 WARN_ON(!pll->config.crtc_mask);
1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868 WARN_ON(pll->on);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871 pll->mode_set(dev_priv, pll);
1872 }
1873 }
1874
1875 /**
1876 * intel_enable_shared_dpll - enable PCH PLL
1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1879 *
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1882 */
1883 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1884 {
1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889 if (WARN_ON(pll == NULL))
1890 return;
1891
1892 if (WARN_ON(pll->config.crtc_mask == 0))
1893 return;
1894
1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1896 pll->name, pll->active, pll->on,
1897 crtc->base.base.id);
1898
1899 if (pll->active++) {
1900 WARN_ON(!pll->on);
1901 assert_shared_dpll_enabled(dev_priv, pll);
1902 return;
1903 }
1904 WARN_ON(pll->on);
1905
1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1909 pll->enable(dev_priv, pll);
1910 pll->on = true;
1911 }
1912
1913 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919 /* PCH only available on ILK+ */
1920 if (INTEL_INFO(dev)->gen < 5)
1921 return;
1922
1923 if (pll == NULL)
1924 return;
1925
1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1927 return;
1928
1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
1931 crtc->base.base.id);
1932
1933 if (WARN_ON(pll->active == 0)) {
1934 assert_shared_dpll_disabled(dev_priv, pll);
1935 return;
1936 }
1937
1938 assert_shared_dpll_enabled(dev_priv, pll);
1939 WARN_ON(!pll->on);
1940 if (--pll->active)
1941 return;
1942
1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1944 pll->disable(dev_priv, pll);
1945 pll->on = false;
1946
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1948 }
1949
1950 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951 enum pipe pipe)
1952 {
1953 struct drm_device *dev = dev_priv->dev;
1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956 i915_reg_t reg;
1957 uint32_t val, pipeconf_val;
1958
1959 /* PCH only available on ILK+ */
1960 BUG_ON(!HAS_PCH_SPLIT(dev));
1961
1962 /* Make sure PCH DPLL is enabled */
1963 assert_shared_dpll_enabled(dev_priv,
1964 intel_crtc_to_shared_dpll(intel_crtc));
1965
1966 /* FDI must be feeding us bits for PCH ports */
1967 assert_fdi_tx_enabled(dev_priv, pipe);
1968 assert_fdi_rx_enabled(dev_priv, pipe);
1969
1970 if (HAS_PCH_CPT(dev)) {
1971 /* Workaround: Set the timing override bit before enabling the
1972 * pch transcoder. */
1973 reg = TRANS_CHICKEN2(pipe);
1974 val = I915_READ(reg);
1975 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1976 I915_WRITE(reg, val);
1977 }
1978
1979 reg = PCH_TRANSCONF(pipe);
1980 val = I915_READ(reg);
1981 pipeconf_val = I915_READ(PIPECONF(pipe));
1982
1983 if (HAS_PCH_IBX(dev_priv->dev)) {
1984 /*
1985 * Make the BPC in transcoder be consistent with
1986 * that in pipeconf reg. For HDMI we must use 8bpc
1987 * here for both 8bpc and 12bpc.
1988 */
1989 val &= ~PIPECONF_BPC_MASK;
1990 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1991 val |= PIPECONF_8BPC;
1992 else
1993 val |= pipeconf_val & PIPECONF_BPC_MASK;
1994 }
1995
1996 val &= ~TRANS_INTERLACE_MASK;
1997 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1998 if (HAS_PCH_IBX(dev_priv->dev) &&
1999 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2000 val |= TRANS_LEGACY_INTERLACED_ILK;
2001 else
2002 val |= TRANS_INTERLACED;
2003 else
2004 val |= TRANS_PROGRESSIVE;
2005
2006 I915_WRITE(reg, val | TRANS_ENABLE);
2007 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2008 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2009 }
2010
2011 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2012 enum transcoder cpu_transcoder)
2013 {
2014 u32 val, pipeconf_val;
2015
2016 /* PCH only available on ILK+ */
2017 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2018
2019 /* FDI must be feeding us bits for PCH ports */
2020 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2021 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2022
2023 /* Workaround: set timing override bit. */
2024 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2025 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2026 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2027
2028 val = TRANS_ENABLE;
2029 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2030
2031 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2032 PIPECONF_INTERLACED_ILK)
2033 val |= TRANS_INTERLACED;
2034 else
2035 val |= TRANS_PROGRESSIVE;
2036
2037 I915_WRITE(LPT_TRANSCONF, val);
2038 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2039 DRM_ERROR("Failed to enable PCH transcoder\n");
2040 }
2041
2042 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2043 enum pipe pipe)
2044 {
2045 struct drm_device *dev = dev_priv->dev;
2046 i915_reg_t reg;
2047 uint32_t val;
2048
2049 /* FDI relies on the transcoder */
2050 assert_fdi_tx_disabled(dev_priv, pipe);
2051 assert_fdi_rx_disabled(dev_priv, pipe);
2052
2053 /* Ports must be off as well */
2054 assert_pch_ports_disabled(dev_priv, pipe);
2055
2056 reg = PCH_TRANSCONF(pipe);
2057 val = I915_READ(reg);
2058 val &= ~TRANS_ENABLE;
2059 I915_WRITE(reg, val);
2060 /* wait for PCH transcoder off, transcoder state */
2061 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2062 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2063
2064 if (HAS_PCH_CPT(dev)) {
2065 /* Workaround: Clear the timing override chicken bit again. */
2066 reg = TRANS_CHICKEN2(pipe);
2067 val = I915_READ(reg);
2068 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2069 I915_WRITE(reg, val);
2070 }
2071 }
2072
2073 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2074 {
2075 u32 val;
2076
2077 val = I915_READ(LPT_TRANSCONF);
2078 val &= ~TRANS_ENABLE;
2079 I915_WRITE(LPT_TRANSCONF, val);
2080 /* wait for PCH transcoder off, transcoder state */
2081 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2082 DRM_ERROR("Failed to disable PCH transcoder\n");
2083
2084 /* Workaround: clear timing override bit. */
2085 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2086 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2087 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2088 }
2089
2090 /**
2091 * intel_enable_pipe - enable a pipe, asserting requirements
2092 * @crtc: crtc responsible for the pipe
2093 *
2094 * Enable @crtc's pipe, making sure that various hardware specific requirements
2095 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2096 */
2097 static void intel_enable_pipe(struct intel_crtc *crtc)
2098 {
2099 struct drm_device *dev = crtc->base.dev;
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 enum pipe pipe = crtc->pipe;
2102 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2103 enum pipe pch_transcoder;
2104 i915_reg_t reg;
2105 u32 val;
2106
2107 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2108
2109 assert_planes_disabled(dev_priv, pipe);
2110 assert_cursor_disabled(dev_priv, pipe);
2111 assert_sprites_disabled(dev_priv, pipe);
2112
2113 if (HAS_PCH_LPT(dev_priv->dev))
2114 pch_transcoder = TRANSCODER_A;
2115 else
2116 pch_transcoder = pipe;
2117
2118 /*
2119 * A pipe without a PLL won't actually be able to drive bits from
2120 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2121 * need the check.
2122 */
2123 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2124 if (crtc->config->has_dsi_encoder)
2125 assert_dsi_pll_enabled(dev_priv);
2126 else
2127 assert_pll_enabled(dev_priv, pipe);
2128 else {
2129 if (crtc->config->has_pch_encoder) {
2130 /* if driving the PCH, we need FDI enabled */
2131 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2132 assert_fdi_tx_pll_enabled(dev_priv,
2133 (enum pipe) cpu_transcoder);
2134 }
2135 /* FIXME: assert CPU port conditions for SNB+ */
2136 }
2137
2138 reg = PIPECONF(cpu_transcoder);
2139 val = I915_READ(reg);
2140 if (val & PIPECONF_ENABLE) {
2141 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2142 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2143 return;
2144 }
2145
2146 I915_WRITE(reg, val | PIPECONF_ENABLE);
2147 POSTING_READ(reg);
2148
2149 /*
2150 * Until the pipe starts DSL will read as 0, which would cause
2151 * an apparent vblank timestamp jump, which messes up also the
2152 * frame count when it's derived from the timestamps. So let's
2153 * wait for the pipe to start properly before we call
2154 * drm_crtc_vblank_on()
2155 */
2156 if (dev->max_vblank_count == 0 &&
2157 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2158 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2159 }
2160
2161 /**
2162 * intel_disable_pipe - disable a pipe, asserting requirements
2163 * @crtc: crtc whose pipes is to be disabled
2164 *
2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175 enum pipe pipe = crtc->pipe;
2176 i915_reg_t reg;
2177 u32 val;
2178
2179 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2180
2181 /*
2182 * Make sure planes won't keep trying to pump pixels to us,
2183 * or we might hang the display.
2184 */
2185 assert_planes_disabled(dev_priv, pipe);
2186 assert_cursor_disabled(dev_priv, pipe);
2187 assert_sprites_disabled(dev_priv, pipe);
2188
2189 reg = PIPECONF(cpu_transcoder);
2190 val = I915_READ(reg);
2191 if ((val & PIPECONF_ENABLE) == 0)
2192 return;
2193
2194 /*
2195 * Double wide has implications for planes
2196 * so best keep it disabled when not needed.
2197 */
2198 if (crtc->config->double_wide)
2199 val &= ~PIPECONF_DOUBLE_WIDE;
2200
2201 /* Don't disable pipe or pipe PLLs if needed */
2202 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2203 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2204 val &= ~PIPECONF_ENABLE;
2205
2206 I915_WRITE(reg, val);
2207 if ((val & PIPECONF_ENABLE) == 0)
2208 intel_wait_for_pipe_off(crtc);
2209 }
2210
2211 static bool need_vtd_wa(struct drm_device *dev)
2212 {
2213 #ifdef CONFIG_INTEL_IOMMU
2214 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2215 return true;
2216 #endif
2217 return false;
2218 }
2219
2220 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2221 {
2222 return IS_GEN2(dev_priv) ? 2048 : 4096;
2223 }
2224
2225 static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv,
2226 uint64_t fb_modifier, unsigned int cpp)
2227 {
2228 switch (fb_modifier) {
2229 case DRM_FORMAT_MOD_NONE:
2230 return cpp;
2231 case I915_FORMAT_MOD_X_TILED:
2232 if (IS_GEN2(dev_priv))
2233 return 128;
2234 else
2235 return 512;
2236 case I915_FORMAT_MOD_Y_TILED:
2237 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2238 return 128;
2239 else
2240 return 512;
2241 case I915_FORMAT_MOD_Yf_TILED:
2242 switch (cpp) {
2243 case 1:
2244 return 64;
2245 case 2:
2246 case 4:
2247 return 128;
2248 case 8:
2249 case 16:
2250 return 256;
2251 default:
2252 MISSING_CASE(cpp);
2253 return cpp;
2254 }
2255 break;
2256 default:
2257 MISSING_CASE(fb_modifier);
2258 return cpp;
2259 }
2260 }
2261
2262 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2263 uint64_t fb_modifier, unsigned int cpp)
2264 {
2265 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2266 return 1;
2267 else
2268 return intel_tile_size(dev_priv) /
2269 intel_tile_width(dev_priv, fb_modifier, cpp);
2270 }
2271
2272 unsigned int
2273 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2274 uint32_t pixel_format, uint64_t fb_modifier)
2275 {
2276 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2277 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2278
2279 return ALIGN(height, tile_height);
2280 }
2281
2282 static void
2283 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284 const struct drm_plane_state *plane_state)
2285 {
2286 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2287 struct intel_rotation_info *info = &view->params.rotated;
2288 unsigned int tile_size, tile_width, tile_height, cpp;
2289
2290 *view = i915_ggtt_view_normal;
2291
2292 if (!plane_state)
2293 return;
2294
2295 if (!intel_rotation_90_or_270(plane_state->rotation))
2296 return;
2297
2298 *view = i915_ggtt_view_rotated;
2299
2300 info->height = fb->height;
2301 info->pixel_format = fb->pixel_format;
2302 info->pitch = fb->pitches[0];
2303 info->uv_offset = fb->offsets[1];
2304 info->fb_modifier = fb->modifier[0];
2305
2306 tile_size = intel_tile_size(dev_priv);
2307
2308 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2309 tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
2310 tile_height = tile_size / tile_width;
2311
2312 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
2313 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2314 info->size = info->width_pages * info->height_pages * tile_size;
2315
2316 if (info->pixel_format == DRM_FORMAT_NV12) {
2317 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2318 tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
2319 tile_height = tile_size / tile_width;
2320
2321 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
2322 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
2323 info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
2324 }
2325 }
2326
2327 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2328 {
2329 if (INTEL_INFO(dev_priv)->gen >= 9)
2330 return 256 * 1024;
2331 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2332 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2333 return 128 * 1024;
2334 else if (INTEL_INFO(dev_priv)->gen >= 4)
2335 return 4 * 1024;
2336 else
2337 return 0;
2338 }
2339
2340 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2341 uint64_t fb_modifier)
2342 {
2343 switch (fb_modifier) {
2344 case DRM_FORMAT_MOD_NONE:
2345 return intel_linear_alignment(dev_priv);
2346 case I915_FORMAT_MOD_X_TILED:
2347 if (INTEL_INFO(dev_priv)->gen >= 9)
2348 return 256 * 1024;
2349 return 0;
2350 case I915_FORMAT_MOD_Y_TILED:
2351 case I915_FORMAT_MOD_Yf_TILED:
2352 return 1 * 1024 * 1024;
2353 default:
2354 MISSING_CASE(fb_modifier);
2355 return 0;
2356 }
2357 }
2358
2359 int
2360 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2361 struct drm_framebuffer *fb,
2362 const struct drm_plane_state *plane_state)
2363 {
2364 struct drm_device *dev = fb->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2367 struct i915_ggtt_view view;
2368 u32 alignment;
2369 int ret;
2370
2371 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2372
2373 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2374
2375 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2376
2377 /* Note that the w/a also requires 64 PTE of padding following the
2378 * bo. We currently fill all unused PTE with the shadow page and so
2379 * we should always have valid PTE following the scanout preventing
2380 * the VT-d warning.
2381 */
2382 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2383 alignment = 256 * 1024;
2384
2385 /*
2386 * Global gtt pte registers are special registers which actually forward
2387 * writes to a chunk of system memory. Which means that there is no risk
2388 * that the register values disappear as soon as we call
2389 * intel_runtime_pm_put(), so it is correct to wrap only the
2390 * pin/unpin/fence and not more.
2391 */
2392 intel_runtime_pm_get(dev_priv);
2393
2394 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2395 &view);
2396 if (ret)
2397 goto err_pm;
2398
2399 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2400 * fence, whereas 965+ only requires a fence if using
2401 * framebuffer compression. For simplicity, we always install
2402 * a fence as the cost is not that onerous.
2403 */
2404 if (view.type == I915_GGTT_VIEW_NORMAL) {
2405 ret = i915_gem_object_get_fence(obj);
2406 if (ret == -EDEADLK) {
2407 /*
2408 * -EDEADLK means there are no free fences
2409 * no pending flips.
2410 *
2411 * This is propagated to atomic, but it uses
2412 * -EDEADLK to force a locking recovery, so
2413 * change the returned error to -EBUSY.
2414 */
2415 ret = -EBUSY;
2416 goto err_unpin;
2417 } else if (ret)
2418 goto err_unpin;
2419
2420 i915_gem_object_pin_fence(obj);
2421 }
2422
2423 intel_runtime_pm_put(dev_priv);
2424 return 0;
2425
2426 err_unpin:
2427 i915_gem_object_unpin_from_display_plane(obj, &view);
2428 err_pm:
2429 intel_runtime_pm_put(dev_priv);
2430 return ret;
2431 }
2432
2433 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434 const struct drm_plane_state *plane_state)
2435 {
2436 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2437 struct i915_ggtt_view view;
2438
2439 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2440
2441 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2442
2443 if (view.type == I915_GGTT_VIEW_NORMAL)
2444 i915_gem_object_unpin_fence(obj);
2445
2446 i915_gem_object_unpin_from_display_plane(obj, &view);
2447 }
2448
2449 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450 * is assumed to be a power-of-two. */
2451 u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
2452 int *x, int *y,
2453 uint64_t fb_modifier,
2454 unsigned int cpp,
2455 unsigned int pitch)
2456 {
2457 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2458 unsigned int tile_size, tile_width, tile_height;
2459 unsigned int tile_rows, tiles;
2460
2461 tile_size = intel_tile_size(dev_priv);
2462 tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
2463 tile_height = tile_size / tile_width;
2464
2465 tile_rows = *y / tile_height;
2466 *y %= tile_height;
2467
2468 tiles = *x / (tile_width/cpp);
2469 *x %= tile_width/cpp;
2470
2471 return tile_rows * pitch * tile_height + tiles * tile_size;
2472 } else {
2473 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2474 unsigned int offset;
2475
2476 offset = *y * pitch + *x * cpp;
2477 *y = (offset & alignment) / pitch;
2478 *x = ((offset & alignment) - *y * pitch) / cpp;
2479 return offset & ~alignment;
2480 }
2481 }
2482
2483 static int i9xx_format_to_fourcc(int format)
2484 {
2485 switch (format) {
2486 case DISPPLANE_8BPP:
2487 return DRM_FORMAT_C8;
2488 case DISPPLANE_BGRX555:
2489 return DRM_FORMAT_XRGB1555;
2490 case DISPPLANE_BGRX565:
2491 return DRM_FORMAT_RGB565;
2492 default:
2493 case DISPPLANE_BGRX888:
2494 return DRM_FORMAT_XRGB8888;
2495 case DISPPLANE_RGBX888:
2496 return DRM_FORMAT_XBGR8888;
2497 case DISPPLANE_BGRX101010:
2498 return DRM_FORMAT_XRGB2101010;
2499 case DISPPLANE_RGBX101010:
2500 return DRM_FORMAT_XBGR2101010;
2501 }
2502 }
2503
2504 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2505 {
2506 switch (format) {
2507 case PLANE_CTL_FORMAT_RGB_565:
2508 return DRM_FORMAT_RGB565;
2509 default:
2510 case PLANE_CTL_FORMAT_XRGB_8888:
2511 if (rgb_order) {
2512 if (alpha)
2513 return DRM_FORMAT_ABGR8888;
2514 else
2515 return DRM_FORMAT_XBGR8888;
2516 } else {
2517 if (alpha)
2518 return DRM_FORMAT_ARGB8888;
2519 else
2520 return DRM_FORMAT_XRGB8888;
2521 }
2522 case PLANE_CTL_FORMAT_XRGB_2101010:
2523 if (rgb_order)
2524 return DRM_FORMAT_XBGR2101010;
2525 else
2526 return DRM_FORMAT_XRGB2101010;
2527 }
2528 }
2529
2530 static bool
2531 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2532 struct intel_initial_plane_config *plane_config)
2533 {
2534 struct drm_device *dev = crtc->base.dev;
2535 struct drm_i915_private *dev_priv = to_i915(dev);
2536 struct drm_i915_gem_object *obj = NULL;
2537 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2538 struct drm_framebuffer *fb = &plane_config->fb->base;
2539 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2540 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2541 PAGE_SIZE);
2542
2543 size_aligned -= base_aligned;
2544
2545 if (plane_config->size == 0)
2546 return false;
2547
2548 /* If the FB is too big, just don't use it since fbdev is not very
2549 * important and we should probably use that space with FBC or other
2550 * features. */
2551 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2552 return false;
2553
2554 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2555 base_aligned,
2556 base_aligned,
2557 size_aligned);
2558 if (!obj)
2559 return false;
2560
2561 obj->tiling_mode = plane_config->tiling;
2562 if (obj->tiling_mode == I915_TILING_X)
2563 obj->stride = fb->pitches[0];
2564
2565 mode_cmd.pixel_format = fb->pixel_format;
2566 mode_cmd.width = fb->width;
2567 mode_cmd.height = fb->height;
2568 mode_cmd.pitches[0] = fb->pitches[0];
2569 mode_cmd.modifier[0] = fb->modifier[0];
2570 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2571
2572 mutex_lock(&dev->struct_mutex);
2573 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2574 &mode_cmd, obj)) {
2575 DRM_DEBUG_KMS("intel fb init failed\n");
2576 goto out_unref_obj;
2577 }
2578 mutex_unlock(&dev->struct_mutex);
2579
2580 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2581 return true;
2582
2583 out_unref_obj:
2584 drm_gem_object_unreference(&obj->base);
2585 mutex_unlock(&dev->struct_mutex);
2586 return false;
2587 }
2588
2589 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2590 static void
2591 update_state_fb(struct drm_plane *plane)
2592 {
2593 if (plane->fb == plane->state->fb)
2594 return;
2595
2596 if (plane->state->fb)
2597 drm_framebuffer_unreference(plane->state->fb);
2598 plane->state->fb = plane->fb;
2599 if (plane->state->fb)
2600 drm_framebuffer_reference(plane->state->fb);
2601 }
2602
2603 static void
2604 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2605 struct intel_initial_plane_config *plane_config)
2606 {
2607 struct drm_device *dev = intel_crtc->base.dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 struct drm_crtc *c;
2610 struct intel_crtc *i;
2611 struct drm_i915_gem_object *obj;
2612 struct drm_plane *primary = intel_crtc->base.primary;
2613 struct drm_plane_state *plane_state = primary->state;
2614 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2615 struct intel_plane *intel_plane = to_intel_plane(primary);
2616 struct intel_plane_state *intel_state =
2617 to_intel_plane_state(plane_state);
2618 struct drm_framebuffer *fb;
2619
2620 if (!plane_config->fb)
2621 return;
2622
2623 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2624 fb = &plane_config->fb->base;
2625 goto valid_fb;
2626 }
2627
2628 kfree(plane_config->fb);
2629
2630 /*
2631 * Failed to alloc the obj, check to see if we should share
2632 * an fb with another CRTC instead
2633 */
2634 for_each_crtc(dev, c) {
2635 i = to_intel_crtc(c);
2636
2637 if (c == &intel_crtc->base)
2638 continue;
2639
2640 if (!i->active)
2641 continue;
2642
2643 fb = c->primary->fb;
2644 if (!fb)
2645 continue;
2646
2647 obj = intel_fb_obj(fb);
2648 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2649 drm_framebuffer_reference(fb);
2650 goto valid_fb;
2651 }
2652 }
2653
2654 /*
2655 * We've failed to reconstruct the BIOS FB. Current display state
2656 * indicates that the primary plane is visible, but has a NULL FB,
2657 * which will lead to problems later if we don't fix it up. The
2658 * simplest solution is to just disable the primary plane now and
2659 * pretend the BIOS never had it enabled.
2660 */
2661 to_intel_plane_state(plane_state)->visible = false;
2662 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2663 intel_pre_disable_primary(&intel_crtc->base);
2664 intel_plane->disable_plane(primary, &intel_crtc->base);
2665
2666 return;
2667
2668 valid_fb:
2669 plane_state->src_x = 0;
2670 plane_state->src_y = 0;
2671 plane_state->src_w = fb->width << 16;
2672 plane_state->src_h = fb->height << 16;
2673
2674 plane_state->crtc_x = 0;
2675 plane_state->crtc_y = 0;
2676 plane_state->crtc_w = fb->width;
2677 plane_state->crtc_h = fb->height;
2678
2679 intel_state->src.x1 = plane_state->src_x;
2680 intel_state->src.y1 = plane_state->src_y;
2681 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2682 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2683 intel_state->dst.x1 = plane_state->crtc_x;
2684 intel_state->dst.y1 = plane_state->crtc_y;
2685 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2686 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2687
2688 obj = intel_fb_obj(fb);
2689 if (obj->tiling_mode != I915_TILING_NONE)
2690 dev_priv->preserve_bios_swizzle = true;
2691
2692 drm_framebuffer_reference(fb);
2693 primary->fb = primary->state->fb = fb;
2694 primary->crtc = primary->state->crtc = &intel_crtc->base;
2695 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2696 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2697 }
2698
2699 static void i9xx_update_primary_plane(struct drm_plane *primary,
2700 const struct intel_crtc_state *crtc_state,
2701 const struct intel_plane_state *plane_state)
2702 {
2703 struct drm_device *dev = primary->dev;
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2706 struct drm_framebuffer *fb = plane_state->base.fb;
2707 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2708 int plane = intel_crtc->plane;
2709 u32 linear_offset;
2710 u32 dspcntr;
2711 i915_reg_t reg = DSPCNTR(plane);
2712 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2713 int x = plane_state->src.x1 >> 16;
2714 int y = plane_state->src.y1 >> 16;
2715
2716 dspcntr = DISPPLANE_GAMMA_ENABLE;
2717
2718 dspcntr |= DISPLAY_PLANE_ENABLE;
2719
2720 if (INTEL_INFO(dev)->gen < 4) {
2721 if (intel_crtc->pipe == PIPE_B)
2722 dspcntr |= DISPPLANE_SEL_PIPE_B;
2723
2724 /* pipesrc and dspsize control the size that is scaled from,
2725 * which should always be the user's requested size.
2726 */
2727 I915_WRITE(DSPSIZE(plane),
2728 ((crtc_state->pipe_src_h - 1) << 16) |
2729 (crtc_state->pipe_src_w - 1));
2730 I915_WRITE(DSPPOS(plane), 0);
2731 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2732 I915_WRITE(PRIMSIZE(plane),
2733 ((crtc_state->pipe_src_h - 1) << 16) |
2734 (crtc_state->pipe_src_w - 1));
2735 I915_WRITE(PRIMPOS(plane), 0);
2736 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2737 }
2738
2739 switch (fb->pixel_format) {
2740 case DRM_FORMAT_C8:
2741 dspcntr |= DISPPLANE_8BPP;
2742 break;
2743 case DRM_FORMAT_XRGB1555:
2744 dspcntr |= DISPPLANE_BGRX555;
2745 break;
2746 case DRM_FORMAT_RGB565:
2747 dspcntr |= DISPPLANE_BGRX565;
2748 break;
2749 case DRM_FORMAT_XRGB8888:
2750 dspcntr |= DISPPLANE_BGRX888;
2751 break;
2752 case DRM_FORMAT_XBGR8888:
2753 dspcntr |= DISPPLANE_RGBX888;
2754 break;
2755 case DRM_FORMAT_XRGB2101010:
2756 dspcntr |= DISPPLANE_BGRX101010;
2757 break;
2758 case DRM_FORMAT_XBGR2101010:
2759 dspcntr |= DISPPLANE_RGBX101010;
2760 break;
2761 default:
2762 BUG();
2763 }
2764
2765 if (INTEL_INFO(dev)->gen >= 4 &&
2766 obj->tiling_mode != I915_TILING_NONE)
2767 dspcntr |= DISPPLANE_TILED;
2768
2769 if (IS_G4X(dev))
2770 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2771
2772 linear_offset = y * fb->pitches[0] + x * cpp;
2773
2774 if (INTEL_INFO(dev)->gen >= 4) {
2775 intel_crtc->dspaddr_offset =
2776 intel_compute_tile_offset(dev_priv, &x, &y,
2777 fb->modifier[0], cpp,
2778 fb->pitches[0]);
2779 linear_offset -= intel_crtc->dspaddr_offset;
2780 } else {
2781 intel_crtc->dspaddr_offset = linear_offset;
2782 }
2783
2784 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2785 dspcntr |= DISPPLANE_ROTATE_180;
2786
2787 x += (crtc_state->pipe_src_w - 1);
2788 y += (crtc_state->pipe_src_h - 1);
2789
2790 /* Finding the last pixel of the last line of the display
2791 data and adding to linear_offset*/
2792 linear_offset +=
2793 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2794 (crtc_state->pipe_src_w - 1) * cpp;
2795 }
2796
2797 intel_crtc->adjusted_x = x;
2798 intel_crtc->adjusted_y = y;
2799
2800 I915_WRITE(reg, dspcntr);
2801
2802 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2803 if (INTEL_INFO(dev)->gen >= 4) {
2804 I915_WRITE(DSPSURF(plane),
2805 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2806 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2807 I915_WRITE(DSPLINOFF(plane), linear_offset);
2808 } else
2809 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2810 POSTING_READ(reg);
2811 }
2812
2813 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2814 struct drm_crtc *crtc)
2815 {
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int plane = intel_crtc->plane;
2820
2821 I915_WRITE(DSPCNTR(plane), 0);
2822 if (INTEL_INFO(dev_priv)->gen >= 4)
2823 I915_WRITE(DSPSURF(plane), 0);
2824 else
2825 I915_WRITE(DSPADDR(plane), 0);
2826 POSTING_READ(DSPCNTR(plane));
2827 }
2828
2829 static void ironlake_update_primary_plane(struct drm_plane *primary,
2830 const struct intel_crtc_state *crtc_state,
2831 const struct intel_plane_state *plane_state)
2832 {
2833 struct drm_device *dev = primary->dev;
2834 struct drm_i915_private *dev_priv = dev->dev_private;
2835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2836 struct drm_framebuffer *fb = plane_state->base.fb;
2837 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2838 int plane = intel_crtc->plane;
2839 u32 linear_offset;
2840 u32 dspcntr;
2841 i915_reg_t reg = DSPCNTR(plane);
2842 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2843 int x = plane_state->src.x1 >> 16;
2844 int y = plane_state->src.y1 >> 16;
2845
2846 dspcntr = DISPPLANE_GAMMA_ENABLE;
2847 dspcntr |= DISPLAY_PLANE_ENABLE;
2848
2849 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2850 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2851
2852 switch (fb->pixel_format) {
2853 case DRM_FORMAT_C8:
2854 dspcntr |= DISPPLANE_8BPP;
2855 break;
2856 case DRM_FORMAT_RGB565:
2857 dspcntr |= DISPPLANE_BGRX565;
2858 break;
2859 case DRM_FORMAT_XRGB8888:
2860 dspcntr |= DISPPLANE_BGRX888;
2861 break;
2862 case DRM_FORMAT_XBGR8888:
2863 dspcntr |= DISPPLANE_RGBX888;
2864 break;
2865 case DRM_FORMAT_XRGB2101010:
2866 dspcntr |= DISPPLANE_BGRX101010;
2867 break;
2868 case DRM_FORMAT_XBGR2101010:
2869 dspcntr |= DISPPLANE_RGBX101010;
2870 break;
2871 default:
2872 BUG();
2873 }
2874
2875 if (obj->tiling_mode != I915_TILING_NONE)
2876 dspcntr |= DISPPLANE_TILED;
2877
2878 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2879 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2880
2881 linear_offset = y * fb->pitches[0] + x * cpp;
2882 intel_crtc->dspaddr_offset =
2883 intel_compute_tile_offset(dev_priv, &x, &y,
2884 fb->modifier[0], cpp,
2885 fb->pitches[0]);
2886 linear_offset -= intel_crtc->dspaddr_offset;
2887 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2888 dspcntr |= DISPPLANE_ROTATE_180;
2889
2890 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2891 x += (crtc_state->pipe_src_w - 1);
2892 y += (crtc_state->pipe_src_h - 1);
2893
2894 /* Finding the last pixel of the last line of the display
2895 data and adding to linear_offset*/
2896 linear_offset +=
2897 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2898 (crtc_state->pipe_src_w - 1) * cpp;
2899 }
2900 }
2901
2902 intel_crtc->adjusted_x = x;
2903 intel_crtc->adjusted_y = y;
2904
2905 I915_WRITE(reg, dspcntr);
2906
2907 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2908 I915_WRITE(DSPSURF(plane),
2909 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2910 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2911 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2912 } else {
2913 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2914 I915_WRITE(DSPLINOFF(plane), linear_offset);
2915 }
2916 POSTING_READ(reg);
2917 }
2918
2919 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2920 uint64_t fb_modifier, uint32_t pixel_format)
2921 {
2922 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2923 return 64;
2924 } else {
2925 int cpp = drm_format_plane_cpp(pixel_format, 0);
2926
2927 return intel_tile_width(dev_priv, fb_modifier, cpp);
2928 }
2929 }
2930
2931 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2932 struct drm_i915_gem_object *obj,
2933 unsigned int plane)
2934 {
2935 struct i915_ggtt_view view;
2936 struct i915_vma *vma;
2937 u64 offset;
2938
2939 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2940 intel_plane->base.state);
2941
2942 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2943 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2944 view.type))
2945 return -1;
2946
2947 offset = vma->node.start;
2948
2949 if (plane == 1) {
2950 offset += vma->ggtt_view.params.rotated.uv_start_page *
2951 PAGE_SIZE;
2952 }
2953
2954 WARN_ON(upper_32_bits(offset));
2955
2956 return lower_32_bits(offset);
2957 }
2958
2959 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2960 {
2961 struct drm_device *dev = intel_crtc->base.dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963
2964 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2965 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2966 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2967 }
2968
2969 /*
2970 * This function detaches (aka. unbinds) unused scalers in hardware
2971 */
2972 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2973 {
2974 struct intel_crtc_scaler_state *scaler_state;
2975 int i;
2976
2977 scaler_state = &intel_crtc->config->scaler_state;
2978
2979 /* loop through and disable scalers that aren't in use */
2980 for (i = 0; i < intel_crtc->num_scalers; i++) {
2981 if (!scaler_state->scalers[i].in_use)
2982 skl_detach_scaler(intel_crtc, i);
2983 }
2984 }
2985
2986 u32 skl_plane_ctl_format(uint32_t pixel_format)
2987 {
2988 switch (pixel_format) {
2989 case DRM_FORMAT_C8:
2990 return PLANE_CTL_FORMAT_INDEXED;
2991 case DRM_FORMAT_RGB565:
2992 return PLANE_CTL_FORMAT_RGB_565;
2993 case DRM_FORMAT_XBGR8888:
2994 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2995 case DRM_FORMAT_XRGB8888:
2996 return PLANE_CTL_FORMAT_XRGB_8888;
2997 /*
2998 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2999 * to be already pre-multiplied. We need to add a knob (or a different
3000 * DRM_FORMAT) for user-space to configure that.
3001 */
3002 case DRM_FORMAT_ABGR8888:
3003 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3004 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3005 case DRM_FORMAT_ARGB8888:
3006 return PLANE_CTL_FORMAT_XRGB_8888 |
3007 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3008 case DRM_FORMAT_XRGB2101010:
3009 return PLANE_CTL_FORMAT_XRGB_2101010;
3010 case DRM_FORMAT_XBGR2101010:
3011 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3012 case DRM_FORMAT_YUYV:
3013 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3014 case DRM_FORMAT_YVYU:
3015 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3016 case DRM_FORMAT_UYVY:
3017 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3018 case DRM_FORMAT_VYUY:
3019 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3020 default:
3021 MISSING_CASE(pixel_format);
3022 }
3023
3024 return 0;
3025 }
3026
3027 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3028 {
3029 switch (fb_modifier) {
3030 case DRM_FORMAT_MOD_NONE:
3031 break;
3032 case I915_FORMAT_MOD_X_TILED:
3033 return PLANE_CTL_TILED_X;
3034 case I915_FORMAT_MOD_Y_TILED:
3035 return PLANE_CTL_TILED_Y;
3036 case I915_FORMAT_MOD_Yf_TILED:
3037 return PLANE_CTL_TILED_YF;
3038 default:
3039 MISSING_CASE(fb_modifier);
3040 }
3041
3042 return 0;
3043 }
3044
3045 u32 skl_plane_ctl_rotation(unsigned int rotation)
3046 {
3047 switch (rotation) {
3048 case BIT(DRM_ROTATE_0):
3049 break;
3050 /*
3051 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3052 * while i915 HW rotation is clockwise, thats why this swapping.
3053 */
3054 case BIT(DRM_ROTATE_90):
3055 return PLANE_CTL_ROTATE_270;
3056 case BIT(DRM_ROTATE_180):
3057 return PLANE_CTL_ROTATE_180;
3058 case BIT(DRM_ROTATE_270):
3059 return PLANE_CTL_ROTATE_90;
3060 default:
3061 MISSING_CASE(rotation);
3062 }
3063
3064 return 0;
3065 }
3066
3067 static void skylake_update_primary_plane(struct drm_plane *plane,
3068 const struct intel_crtc_state *crtc_state,
3069 const struct intel_plane_state *plane_state)
3070 {
3071 struct drm_device *dev = plane->dev;
3072 struct drm_i915_private *dev_priv = dev->dev_private;
3073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3074 struct drm_framebuffer *fb = plane_state->base.fb;
3075 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3076 int pipe = intel_crtc->pipe;
3077 u32 plane_ctl, stride_div, stride;
3078 u32 tile_height, plane_offset, plane_size;
3079 unsigned int rotation = plane_state->base.rotation;
3080 int x_offset, y_offset;
3081 u32 surf_addr;
3082 int scaler_id = plane_state->scaler_id;
3083 int src_x = plane_state->src.x1 >> 16;
3084 int src_y = plane_state->src.y1 >> 16;
3085 int src_w = drm_rect_width(&plane_state->src) >> 16;
3086 int src_h = drm_rect_height(&plane_state->src) >> 16;
3087 int dst_x = plane_state->dst.x1;
3088 int dst_y = plane_state->dst.y1;
3089 int dst_w = drm_rect_width(&plane_state->dst);
3090 int dst_h = drm_rect_height(&plane_state->dst);
3091
3092 plane_ctl = PLANE_CTL_ENABLE |
3093 PLANE_CTL_PIPE_GAMMA_ENABLE |
3094 PLANE_CTL_PIPE_CSC_ENABLE;
3095
3096 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3097 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3098 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3099 plane_ctl |= skl_plane_ctl_rotation(rotation);
3100
3101 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3102 fb->pixel_format);
3103 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3104
3105 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3106
3107 if (intel_rotation_90_or_270(rotation)) {
3108 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3109
3110 /* stride = Surface height in tiles */
3111 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3112 stride = DIV_ROUND_UP(fb->height, tile_height);
3113 x_offset = stride * tile_height - src_y - src_h;
3114 y_offset = src_x;
3115 plane_size = (src_w - 1) << 16 | (src_h - 1);
3116 } else {
3117 stride = fb->pitches[0] / stride_div;
3118 x_offset = src_x;
3119 y_offset = src_y;
3120 plane_size = (src_h - 1) << 16 | (src_w - 1);
3121 }
3122 plane_offset = y_offset << 16 | x_offset;
3123
3124 intel_crtc->adjusted_x = x_offset;
3125 intel_crtc->adjusted_y = y_offset;
3126
3127 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3128 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3129 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3130 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3131
3132 if (scaler_id >= 0) {
3133 uint32_t ps_ctrl = 0;
3134
3135 WARN_ON(!dst_w || !dst_h);
3136 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3137 crtc_state->scaler_state.scalers[scaler_id].mode;
3138 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3139 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3140 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3141 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3142 I915_WRITE(PLANE_POS(pipe, 0), 0);
3143 } else {
3144 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3145 }
3146
3147 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3148
3149 POSTING_READ(PLANE_SURF(pipe, 0));
3150 }
3151
3152 static void skylake_disable_primary_plane(struct drm_plane *primary,
3153 struct drm_crtc *crtc)
3154 {
3155 struct drm_device *dev = crtc->dev;
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 int pipe = to_intel_crtc(crtc)->pipe;
3158
3159 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3160 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3161 POSTING_READ(PLANE_SURF(pipe, 0));
3162 }
3163
3164 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3165 static int
3166 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3167 int x, int y, enum mode_set_atomic state)
3168 {
3169 /* Support for kgdboc is disabled, this needs a major rework. */
3170 DRM_ERROR("legacy panic handler not supported any more.\n");
3171
3172 return -ENODEV;
3173 }
3174
3175 static void intel_complete_page_flips(struct drm_device *dev)
3176 {
3177 struct drm_crtc *crtc;
3178
3179 for_each_crtc(dev, crtc) {
3180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3181 enum plane plane = intel_crtc->plane;
3182
3183 intel_prepare_page_flip(dev, plane);
3184 intel_finish_page_flip_plane(dev, plane);
3185 }
3186 }
3187
3188 static void intel_update_primary_planes(struct drm_device *dev)
3189 {
3190 struct drm_crtc *crtc;
3191
3192 for_each_crtc(dev, crtc) {
3193 struct intel_plane *plane = to_intel_plane(crtc->primary);
3194 struct intel_plane_state *plane_state;
3195
3196 drm_modeset_lock_crtc(crtc, &plane->base);
3197 plane_state = to_intel_plane_state(plane->base.state);
3198
3199 if (plane_state->visible)
3200 plane->update_plane(&plane->base,
3201 to_intel_crtc_state(crtc->state),
3202 plane_state);
3203
3204 drm_modeset_unlock_crtc(crtc);
3205 }
3206 }
3207
3208 void intel_prepare_reset(struct drm_device *dev)
3209 {
3210 /* no reset support for gen2 */
3211 if (IS_GEN2(dev))
3212 return;
3213
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3216 return;
3217
3218 drm_modeset_lock_all(dev);
3219 /*
3220 * Disabling the crtcs gracefully seems nicer. Also the
3221 * g33 docs say we should at least disable all the planes.
3222 */
3223 intel_display_suspend(dev);
3224 }
3225
3226 void intel_finish_reset(struct drm_device *dev)
3227 {
3228 struct drm_i915_private *dev_priv = to_i915(dev);
3229
3230 /*
3231 * Flips in the rings will be nuked by the reset,
3232 * so complete all pending flips so that user space
3233 * will get its events and not get stuck.
3234 */
3235 intel_complete_page_flips(dev);
3236
3237 /* no reset support for gen2 */
3238 if (IS_GEN2(dev))
3239 return;
3240
3241 /* reset doesn't touch the display */
3242 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3243 /*
3244 * Flips in the rings have been nuked by the reset,
3245 * so update the base address of all primary
3246 * planes to the the last fb to make sure we're
3247 * showing the correct fb after a reset.
3248 *
3249 * FIXME: Atomic will make this obsolete since we won't schedule
3250 * CS-based flips (which might get lost in gpu resets) any more.
3251 */
3252 intel_update_primary_planes(dev);
3253 return;
3254 }
3255
3256 /*
3257 * The display has been reset as well,
3258 * so need a full re-initialization.
3259 */
3260 intel_runtime_pm_disable_interrupts(dev_priv);
3261 intel_runtime_pm_enable_interrupts(dev_priv);
3262
3263 intel_modeset_init_hw(dev);
3264
3265 spin_lock_irq(&dev_priv->irq_lock);
3266 if (dev_priv->display.hpd_irq_setup)
3267 dev_priv->display.hpd_irq_setup(dev);
3268 spin_unlock_irq(&dev_priv->irq_lock);
3269
3270 intel_display_resume(dev);
3271
3272 intel_hpd_init(dev_priv);
3273
3274 drm_modeset_unlock_all(dev);
3275 }
3276
3277 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3278 {
3279 struct drm_device *dev = crtc->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282 bool pending;
3283
3284 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3285 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3286 return false;
3287
3288 spin_lock_irq(&dev->event_lock);
3289 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3290 spin_unlock_irq(&dev->event_lock);
3291
3292 return pending;
3293 }
3294
3295 static void intel_update_pipe_config(struct intel_crtc *crtc,
3296 struct intel_crtc_state *old_crtc_state)
3297 {
3298 struct drm_device *dev = crtc->base.dev;
3299 struct drm_i915_private *dev_priv = dev->dev_private;
3300 struct intel_crtc_state *pipe_config =
3301 to_intel_crtc_state(crtc->base.state);
3302
3303 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3304 crtc->base.mode = crtc->base.state->mode;
3305
3306 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3307 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3308 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3309
3310 if (HAS_DDI(dev))
3311 intel_set_pipe_csc(&crtc->base);
3312
3313 /*
3314 * Update pipe size and adjust fitter if needed: the reason for this is
3315 * that in compute_mode_changes we check the native mode (not the pfit
3316 * mode) to see if we can flip rather than do a full mode set. In the
3317 * fastboot case, we'll flip, but if we don't update the pipesrc and
3318 * pfit state, we'll end up with a big fb scanned out into the wrong
3319 * sized surface.
3320 */
3321
3322 I915_WRITE(PIPESRC(crtc->pipe),
3323 ((pipe_config->pipe_src_w - 1) << 16) |
3324 (pipe_config->pipe_src_h - 1));
3325
3326 /* on skylake this is done by detaching scalers */
3327 if (INTEL_INFO(dev)->gen >= 9) {
3328 skl_detach_scalers(crtc);
3329
3330 if (pipe_config->pch_pfit.enabled)
3331 skylake_pfit_enable(crtc);
3332 } else if (HAS_PCH_SPLIT(dev)) {
3333 if (pipe_config->pch_pfit.enabled)
3334 ironlake_pfit_enable(crtc);
3335 else if (old_crtc_state->pch_pfit.enabled)
3336 ironlake_pfit_disable(crtc, true);
3337 }
3338 }
3339
3340 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3341 {
3342 struct drm_device *dev = crtc->dev;
3343 struct drm_i915_private *dev_priv = dev->dev_private;
3344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3345 int pipe = intel_crtc->pipe;
3346 i915_reg_t reg;
3347 u32 temp;
3348
3349 /* enable normal train */
3350 reg = FDI_TX_CTL(pipe);
3351 temp = I915_READ(reg);
3352 if (IS_IVYBRIDGE(dev)) {
3353 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3354 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3355 } else {
3356 temp &= ~FDI_LINK_TRAIN_NONE;
3357 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3358 }
3359 I915_WRITE(reg, temp);
3360
3361 reg = FDI_RX_CTL(pipe);
3362 temp = I915_READ(reg);
3363 if (HAS_PCH_CPT(dev)) {
3364 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3365 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3366 } else {
3367 temp &= ~FDI_LINK_TRAIN_NONE;
3368 temp |= FDI_LINK_TRAIN_NONE;
3369 }
3370 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3371
3372 /* wait one idle pattern time */
3373 POSTING_READ(reg);
3374 udelay(1000);
3375
3376 /* IVB wants error correction enabled */
3377 if (IS_IVYBRIDGE(dev))
3378 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3379 FDI_FE_ERRC_ENABLE);
3380 }
3381
3382 /* The FDI link training functions for ILK/Ibexpeak. */
3383 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3384 {
3385 struct drm_device *dev = crtc->dev;
3386 struct drm_i915_private *dev_priv = dev->dev_private;
3387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3388 int pipe = intel_crtc->pipe;
3389 i915_reg_t reg;
3390 u32 temp, tries;
3391
3392 /* FDI needs bits from pipe first */
3393 assert_pipe_enabled(dev_priv, pipe);
3394
3395 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3396 for train result */
3397 reg = FDI_RX_IMR(pipe);
3398 temp = I915_READ(reg);
3399 temp &= ~FDI_RX_SYMBOL_LOCK;
3400 temp &= ~FDI_RX_BIT_LOCK;
3401 I915_WRITE(reg, temp);
3402 I915_READ(reg);
3403 udelay(150);
3404
3405 /* enable CPU FDI TX and PCH FDI RX */
3406 reg = FDI_TX_CTL(pipe);
3407 temp = I915_READ(reg);
3408 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3409 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3410 temp &= ~FDI_LINK_TRAIN_NONE;
3411 temp |= FDI_LINK_TRAIN_PATTERN_1;
3412 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3413
3414 reg = FDI_RX_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp &= ~FDI_LINK_TRAIN_NONE;
3417 temp |= FDI_LINK_TRAIN_PATTERN_1;
3418 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3419
3420 POSTING_READ(reg);
3421 udelay(150);
3422
3423 /* Ironlake workaround, enable clock pointer after FDI enable*/
3424 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3425 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3426 FDI_RX_PHASE_SYNC_POINTER_EN);
3427
3428 reg = FDI_RX_IIR(pipe);
3429 for (tries = 0; tries < 5; tries++) {
3430 temp = I915_READ(reg);
3431 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3432
3433 if ((temp & FDI_RX_BIT_LOCK)) {
3434 DRM_DEBUG_KMS("FDI train 1 done.\n");
3435 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3436 break;
3437 }
3438 }
3439 if (tries == 5)
3440 DRM_ERROR("FDI train 1 fail!\n");
3441
3442 /* Train 2 */
3443 reg = FDI_TX_CTL(pipe);
3444 temp = I915_READ(reg);
3445 temp &= ~FDI_LINK_TRAIN_NONE;
3446 temp |= FDI_LINK_TRAIN_PATTERN_2;
3447 I915_WRITE(reg, temp);
3448
3449 reg = FDI_RX_CTL(pipe);
3450 temp = I915_READ(reg);
3451 temp &= ~FDI_LINK_TRAIN_NONE;
3452 temp |= FDI_LINK_TRAIN_PATTERN_2;
3453 I915_WRITE(reg, temp);
3454
3455 POSTING_READ(reg);
3456 udelay(150);
3457
3458 reg = FDI_RX_IIR(pipe);
3459 for (tries = 0; tries < 5; tries++) {
3460 temp = I915_READ(reg);
3461 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3462
3463 if (temp & FDI_RX_SYMBOL_LOCK) {
3464 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3465 DRM_DEBUG_KMS("FDI train 2 done.\n");
3466 break;
3467 }
3468 }
3469 if (tries == 5)
3470 DRM_ERROR("FDI train 2 fail!\n");
3471
3472 DRM_DEBUG_KMS("FDI train done\n");
3473
3474 }
3475
3476 static const int snb_b_fdi_train_param[] = {
3477 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3478 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3479 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3480 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3481 };
3482
3483 /* The FDI link training functions for SNB/Cougarpoint. */
3484 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3485 {
3486 struct drm_device *dev = crtc->dev;
3487 struct drm_i915_private *dev_priv = dev->dev_private;
3488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3489 int pipe = intel_crtc->pipe;
3490 i915_reg_t reg;
3491 u32 temp, i, retry;
3492
3493 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3494 for train result */
3495 reg = FDI_RX_IMR(pipe);
3496 temp = I915_READ(reg);
3497 temp &= ~FDI_RX_SYMBOL_LOCK;
3498 temp &= ~FDI_RX_BIT_LOCK;
3499 I915_WRITE(reg, temp);
3500
3501 POSTING_READ(reg);
3502 udelay(150);
3503
3504 /* enable CPU FDI TX and PCH FDI RX */
3505 reg = FDI_TX_CTL(pipe);
3506 temp = I915_READ(reg);
3507 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3508 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3509 temp &= ~FDI_LINK_TRAIN_NONE;
3510 temp |= FDI_LINK_TRAIN_PATTERN_1;
3511 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3512 /* SNB-B */
3513 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3514 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3515
3516 I915_WRITE(FDI_RX_MISC(pipe),
3517 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3518
3519 reg = FDI_RX_CTL(pipe);
3520 temp = I915_READ(reg);
3521 if (HAS_PCH_CPT(dev)) {
3522 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3523 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3524 } else {
3525 temp &= ~FDI_LINK_TRAIN_NONE;
3526 temp |= FDI_LINK_TRAIN_PATTERN_1;
3527 }
3528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3529
3530 POSTING_READ(reg);
3531 udelay(150);
3532
3533 for (i = 0; i < 4; i++) {
3534 reg = FDI_TX_CTL(pipe);
3535 temp = I915_READ(reg);
3536 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3537 temp |= snb_b_fdi_train_param[i];
3538 I915_WRITE(reg, temp);
3539
3540 POSTING_READ(reg);
3541 udelay(500);
3542
3543 for (retry = 0; retry < 5; retry++) {
3544 reg = FDI_RX_IIR(pipe);
3545 temp = I915_READ(reg);
3546 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3547 if (temp & FDI_RX_BIT_LOCK) {
3548 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3549 DRM_DEBUG_KMS("FDI train 1 done.\n");
3550 break;
3551 }
3552 udelay(50);
3553 }
3554 if (retry < 5)
3555 break;
3556 }
3557 if (i == 4)
3558 DRM_ERROR("FDI train 1 fail!\n");
3559
3560 /* Train 2 */
3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 temp &= ~FDI_LINK_TRAIN_NONE;
3564 temp |= FDI_LINK_TRAIN_PATTERN_2;
3565 if (IS_GEN6(dev)) {
3566 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3567 /* SNB-B */
3568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3569 }
3570 I915_WRITE(reg, temp);
3571
3572 reg = FDI_RX_CTL(pipe);
3573 temp = I915_READ(reg);
3574 if (HAS_PCH_CPT(dev)) {
3575 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3576 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3577 } else {
3578 temp &= ~FDI_LINK_TRAIN_NONE;
3579 temp |= FDI_LINK_TRAIN_PATTERN_2;
3580 }
3581 I915_WRITE(reg, temp);
3582
3583 POSTING_READ(reg);
3584 udelay(150);
3585
3586 for (i = 0; i < 4; i++) {
3587 reg = FDI_TX_CTL(pipe);
3588 temp = I915_READ(reg);
3589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3590 temp |= snb_b_fdi_train_param[i];
3591 I915_WRITE(reg, temp);
3592
3593 POSTING_READ(reg);
3594 udelay(500);
3595
3596 for (retry = 0; retry < 5; retry++) {
3597 reg = FDI_RX_IIR(pipe);
3598 temp = I915_READ(reg);
3599 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3600 if (temp & FDI_RX_SYMBOL_LOCK) {
3601 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3602 DRM_DEBUG_KMS("FDI train 2 done.\n");
3603 break;
3604 }
3605 udelay(50);
3606 }
3607 if (retry < 5)
3608 break;
3609 }
3610 if (i == 4)
3611 DRM_ERROR("FDI train 2 fail!\n");
3612
3613 DRM_DEBUG_KMS("FDI train done.\n");
3614 }
3615
3616 /* Manual link training for Ivy Bridge A0 parts */
3617 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3618 {
3619 struct drm_device *dev = crtc->dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 int pipe = intel_crtc->pipe;
3623 i915_reg_t reg;
3624 u32 temp, i, j;
3625
3626 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3627 for train result */
3628 reg = FDI_RX_IMR(pipe);
3629 temp = I915_READ(reg);
3630 temp &= ~FDI_RX_SYMBOL_LOCK;
3631 temp &= ~FDI_RX_BIT_LOCK;
3632 I915_WRITE(reg, temp);
3633
3634 POSTING_READ(reg);
3635 udelay(150);
3636
3637 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3638 I915_READ(FDI_RX_IIR(pipe)));
3639
3640 /* Try each vswing and preemphasis setting twice before moving on */
3641 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3642 /* disable first in case we need to retry */
3643 reg = FDI_TX_CTL(pipe);
3644 temp = I915_READ(reg);
3645 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3646 temp &= ~FDI_TX_ENABLE;
3647 I915_WRITE(reg, temp);
3648
3649 reg = FDI_RX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~FDI_LINK_TRAIN_AUTO;
3652 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3653 temp &= ~FDI_RX_ENABLE;
3654 I915_WRITE(reg, temp);
3655
3656 /* enable CPU FDI TX and PCH FDI RX */
3657 reg = FDI_TX_CTL(pipe);
3658 temp = I915_READ(reg);
3659 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3660 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3661 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3662 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3663 temp |= snb_b_fdi_train_param[j/2];
3664 temp |= FDI_COMPOSITE_SYNC;
3665 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3666
3667 I915_WRITE(FDI_RX_MISC(pipe),
3668 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3669
3670 reg = FDI_RX_CTL(pipe);
3671 temp = I915_READ(reg);
3672 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3673 temp |= FDI_COMPOSITE_SYNC;
3674 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3675
3676 POSTING_READ(reg);
3677 udelay(1); /* should be 0.5us */
3678
3679 for (i = 0; i < 4; i++) {
3680 reg = FDI_RX_IIR(pipe);
3681 temp = I915_READ(reg);
3682 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3683
3684 if (temp & FDI_RX_BIT_LOCK ||
3685 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3686 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3687 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3688 i);
3689 break;
3690 }
3691 udelay(1); /* should be 0.5us */
3692 }
3693 if (i == 4) {
3694 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3695 continue;
3696 }
3697
3698 /* Train 2 */
3699 reg = FDI_TX_CTL(pipe);
3700 temp = I915_READ(reg);
3701 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3702 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3703 I915_WRITE(reg, temp);
3704
3705 reg = FDI_RX_CTL(pipe);
3706 temp = I915_READ(reg);
3707 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3709 I915_WRITE(reg, temp);
3710
3711 POSTING_READ(reg);
3712 udelay(2); /* should be 1.5us */
3713
3714 for (i = 0; i < 4; i++) {
3715 reg = FDI_RX_IIR(pipe);
3716 temp = I915_READ(reg);
3717 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3718
3719 if (temp & FDI_RX_SYMBOL_LOCK ||
3720 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3721 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3722 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3723 i);
3724 goto train_done;
3725 }
3726 udelay(2); /* should be 1.5us */
3727 }
3728 if (i == 4)
3729 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3730 }
3731
3732 train_done:
3733 DRM_DEBUG_KMS("FDI train done.\n");
3734 }
3735
3736 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3737 {
3738 struct drm_device *dev = intel_crtc->base.dev;
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 int pipe = intel_crtc->pipe;
3741 i915_reg_t reg;
3742 u32 temp;
3743
3744 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3745 reg = FDI_RX_CTL(pipe);
3746 temp = I915_READ(reg);
3747 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3748 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3749 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3750 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3751
3752 POSTING_READ(reg);
3753 udelay(200);
3754
3755 /* Switch from Rawclk to PCDclk */
3756 temp = I915_READ(reg);
3757 I915_WRITE(reg, temp | FDI_PCDCLK);
3758
3759 POSTING_READ(reg);
3760 udelay(200);
3761
3762 /* Enable CPU FDI TX PLL, always on for Ironlake */
3763 reg = FDI_TX_CTL(pipe);
3764 temp = I915_READ(reg);
3765 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3766 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3767
3768 POSTING_READ(reg);
3769 udelay(100);
3770 }
3771 }
3772
3773 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3774 {
3775 struct drm_device *dev = intel_crtc->base.dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 int pipe = intel_crtc->pipe;
3778 i915_reg_t reg;
3779 u32 temp;
3780
3781 /* Switch from PCDclk to Rawclk */
3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
3784 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3785
3786 /* Disable CPU FDI TX PLL */
3787 reg = FDI_TX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3790
3791 POSTING_READ(reg);
3792 udelay(100);
3793
3794 reg = FDI_RX_CTL(pipe);
3795 temp = I915_READ(reg);
3796 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3797
3798 /* Wait for the clocks to turn off. */
3799 POSTING_READ(reg);
3800 udelay(100);
3801 }
3802
3803 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3804 {
3805 struct drm_device *dev = crtc->dev;
3806 struct drm_i915_private *dev_priv = dev->dev_private;
3807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3808 int pipe = intel_crtc->pipe;
3809 i915_reg_t reg;
3810 u32 temp;
3811
3812 /* disable CPU FDI tx and PCH FDI rx */
3813 reg = FDI_TX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3816 POSTING_READ(reg);
3817
3818 reg = FDI_RX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 temp &= ~(0x7 << 16);
3821 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3822 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3823
3824 POSTING_READ(reg);
3825 udelay(100);
3826
3827 /* Ironlake workaround, disable clock pointer after downing FDI */
3828 if (HAS_PCH_IBX(dev))
3829 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3830
3831 /* still set train pattern 1 */
3832 reg = FDI_TX_CTL(pipe);
3833 temp = I915_READ(reg);
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3836 I915_WRITE(reg, temp);
3837
3838 reg = FDI_RX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 if (HAS_PCH_CPT(dev)) {
3841 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3842 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3843 } else {
3844 temp &= ~FDI_LINK_TRAIN_NONE;
3845 temp |= FDI_LINK_TRAIN_PATTERN_1;
3846 }
3847 /* BPC in FDI rx is consistent with that in PIPECONF */
3848 temp &= ~(0x07 << 16);
3849 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3850 I915_WRITE(reg, temp);
3851
3852 POSTING_READ(reg);
3853 udelay(100);
3854 }
3855
3856 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3857 {
3858 struct intel_crtc *crtc;
3859
3860 /* Note that we don't need to be called with mode_config.lock here
3861 * as our list of CRTC objects is static for the lifetime of the
3862 * device and so cannot disappear as we iterate. Similarly, we can
3863 * happily treat the predicates as racy, atomic checks as userspace
3864 * cannot claim and pin a new fb without at least acquring the
3865 * struct_mutex and so serialising with us.
3866 */
3867 for_each_intel_crtc(dev, crtc) {
3868 if (atomic_read(&crtc->unpin_work_count) == 0)
3869 continue;
3870
3871 if (crtc->unpin_work)
3872 intel_wait_for_vblank(dev, crtc->pipe);
3873
3874 return true;
3875 }
3876
3877 return false;
3878 }
3879
3880 static void page_flip_completed(struct intel_crtc *intel_crtc)
3881 {
3882 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3883 struct intel_unpin_work *work = intel_crtc->unpin_work;
3884
3885 /* ensure that the unpin work is consistent wrt ->pending. */
3886 smp_rmb();
3887 intel_crtc->unpin_work = NULL;
3888
3889 if (work->event)
3890 drm_send_vblank_event(intel_crtc->base.dev,
3891 intel_crtc->pipe,
3892 work->event);
3893
3894 drm_crtc_vblank_put(&intel_crtc->base);
3895
3896 wake_up_all(&dev_priv->pending_flip_queue);
3897 queue_work(dev_priv->wq, &work->work);
3898
3899 trace_i915_flip_complete(intel_crtc->plane,
3900 work->pending_flip_obj);
3901 }
3902
3903 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3904 {
3905 struct drm_device *dev = crtc->dev;
3906 struct drm_i915_private *dev_priv = dev->dev_private;
3907 long ret;
3908
3909 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3910
3911 ret = wait_event_interruptible_timeout(
3912 dev_priv->pending_flip_queue,
3913 !intel_crtc_has_pending_flip(crtc),
3914 60*HZ);
3915
3916 if (ret < 0)
3917 return ret;
3918
3919 if (ret == 0) {
3920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3921
3922 spin_lock_irq(&dev->event_lock);
3923 if (intel_crtc->unpin_work) {
3924 WARN_ONCE(1, "Removing stuck page flip\n");
3925 page_flip_completed(intel_crtc);
3926 }
3927 spin_unlock_irq(&dev->event_lock);
3928 }
3929
3930 return 0;
3931 }
3932
3933 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3934 {
3935 u32 temp;
3936
3937 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3938
3939 mutex_lock(&dev_priv->sb_lock);
3940
3941 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3942 temp |= SBI_SSCCTL_DISABLE;
3943 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3944
3945 mutex_unlock(&dev_priv->sb_lock);
3946 }
3947
3948 /* Program iCLKIP clock to the desired frequency */
3949 static void lpt_program_iclkip(struct drm_crtc *crtc)
3950 {
3951 struct drm_device *dev = crtc->dev;
3952 struct drm_i915_private *dev_priv = dev->dev_private;
3953 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3954 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3955 u32 temp;
3956
3957 lpt_disable_iclkip(dev_priv);
3958
3959 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3960 if (clock == 20000) {
3961 auxdiv = 1;
3962 divsel = 0x41;
3963 phaseinc = 0x20;
3964 } else {
3965 /* The iCLK virtual clock root frequency is in MHz,
3966 * but the adjusted_mode->crtc_clock in in KHz. To get the
3967 * divisors, it is necessary to divide one by another, so we
3968 * convert the virtual clock precision to KHz here for higher
3969 * precision.
3970 */
3971 u32 iclk_virtual_root_freq = 172800 * 1000;
3972 u32 iclk_pi_range = 64;
3973 u32 desired_divisor, msb_divisor_value, pi_value;
3974
3975 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
3976 msb_divisor_value = desired_divisor / iclk_pi_range;
3977 pi_value = desired_divisor % iclk_pi_range;
3978
3979 auxdiv = 0;
3980 divsel = msb_divisor_value - 2;
3981 phaseinc = pi_value;
3982 }
3983
3984 /* This should not happen with any sane values */
3985 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3986 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3987 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3988 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3989
3990 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3991 clock,
3992 auxdiv,
3993 divsel,
3994 phasedir,
3995 phaseinc);
3996
3997 mutex_lock(&dev_priv->sb_lock);
3998
3999 /* Program SSCDIVINTPHASE6 */
4000 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4001 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4002 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4003 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4004 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4005 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4006 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4007 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4008
4009 /* Program SSCAUXDIV */
4010 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4011 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4012 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4013 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4014
4015 /* Enable modulator and associated divider */
4016 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4017 temp &= ~SBI_SSCCTL_DISABLE;
4018 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4019
4020 mutex_unlock(&dev_priv->sb_lock);
4021
4022 /* Wait for initialization time */
4023 udelay(24);
4024
4025 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4026 }
4027
4028 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4029 enum pipe pch_transcoder)
4030 {
4031 struct drm_device *dev = crtc->base.dev;
4032 struct drm_i915_private *dev_priv = dev->dev_private;
4033 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4034
4035 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4036 I915_READ(HTOTAL(cpu_transcoder)));
4037 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4038 I915_READ(HBLANK(cpu_transcoder)));
4039 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4040 I915_READ(HSYNC(cpu_transcoder)));
4041
4042 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4043 I915_READ(VTOTAL(cpu_transcoder)));
4044 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4045 I915_READ(VBLANK(cpu_transcoder)));
4046 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4047 I915_READ(VSYNC(cpu_transcoder)));
4048 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4049 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4050 }
4051
4052 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4053 {
4054 struct drm_i915_private *dev_priv = dev->dev_private;
4055 uint32_t temp;
4056
4057 temp = I915_READ(SOUTH_CHICKEN1);
4058 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4059 return;
4060
4061 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4062 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4063
4064 temp &= ~FDI_BC_BIFURCATION_SELECT;
4065 if (enable)
4066 temp |= FDI_BC_BIFURCATION_SELECT;
4067
4068 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4069 I915_WRITE(SOUTH_CHICKEN1, temp);
4070 POSTING_READ(SOUTH_CHICKEN1);
4071 }
4072
4073 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4074 {
4075 struct drm_device *dev = intel_crtc->base.dev;
4076
4077 switch (intel_crtc->pipe) {
4078 case PIPE_A:
4079 break;
4080 case PIPE_B:
4081 if (intel_crtc->config->fdi_lanes > 2)
4082 cpt_set_fdi_bc_bifurcation(dev, false);
4083 else
4084 cpt_set_fdi_bc_bifurcation(dev, true);
4085
4086 break;
4087 case PIPE_C:
4088 cpt_set_fdi_bc_bifurcation(dev, true);
4089
4090 break;
4091 default:
4092 BUG();
4093 }
4094 }
4095
4096 /* Return which DP Port should be selected for Transcoder DP control */
4097 static enum port
4098 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4099 {
4100 struct drm_device *dev = crtc->dev;
4101 struct intel_encoder *encoder;
4102
4103 for_each_encoder_on_crtc(dev, crtc, encoder) {
4104 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4105 encoder->type == INTEL_OUTPUT_EDP)
4106 return enc_to_dig_port(&encoder->base)->port;
4107 }
4108
4109 return -1;
4110 }
4111
4112 /*
4113 * Enable PCH resources required for PCH ports:
4114 * - PCH PLLs
4115 * - FDI training & RX/TX
4116 * - update transcoder timings
4117 * - DP transcoding bits
4118 * - transcoder
4119 */
4120 static void ironlake_pch_enable(struct drm_crtc *crtc)
4121 {
4122 struct drm_device *dev = crtc->dev;
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4125 int pipe = intel_crtc->pipe;
4126 u32 temp;
4127
4128 assert_pch_transcoder_disabled(dev_priv, pipe);
4129
4130 if (IS_IVYBRIDGE(dev))
4131 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4132
4133 /* Write the TU size bits before fdi link training, so that error
4134 * detection works. */
4135 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4136 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4137
4138 /*
4139 * Sometimes spurious CPU pipe underruns happen during FDI
4140 * training, at least with VGA+HDMI cloning. Suppress them.
4141 */
4142 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4143
4144 /* For PCH output, training FDI link */
4145 dev_priv->display.fdi_link_train(crtc);
4146
4147 /* We need to program the right clock selection before writing the pixel
4148 * mutliplier into the DPLL. */
4149 if (HAS_PCH_CPT(dev)) {
4150 u32 sel;
4151
4152 temp = I915_READ(PCH_DPLL_SEL);
4153 temp |= TRANS_DPLL_ENABLE(pipe);
4154 sel = TRANS_DPLLB_SEL(pipe);
4155 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4156 temp |= sel;
4157 else
4158 temp &= ~sel;
4159 I915_WRITE(PCH_DPLL_SEL, temp);
4160 }
4161
4162 /* XXX: pch pll's can be enabled any time before we enable the PCH
4163 * transcoder, and we actually should do this to not upset any PCH
4164 * transcoder that already use the clock when we share it.
4165 *
4166 * Note that enable_shared_dpll tries to do the right thing, but
4167 * get_shared_dpll unconditionally resets the pll - we need that to have
4168 * the right LVDS enable sequence. */
4169 intel_enable_shared_dpll(intel_crtc);
4170
4171 /* set transcoder timing, panel must allow it */
4172 assert_panel_unlocked(dev_priv, pipe);
4173 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4174
4175 intel_fdi_normal_train(crtc);
4176
4177 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4178
4179 /* For PCH DP, enable TRANS_DP_CTL */
4180 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4181 const struct drm_display_mode *adjusted_mode =
4182 &intel_crtc->config->base.adjusted_mode;
4183 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4184 i915_reg_t reg = TRANS_DP_CTL(pipe);
4185 temp = I915_READ(reg);
4186 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4187 TRANS_DP_SYNC_MASK |
4188 TRANS_DP_BPC_MASK);
4189 temp |= TRANS_DP_OUTPUT_ENABLE;
4190 temp |= bpc << 9; /* same format but at 11:9 */
4191
4192 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4193 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4194 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4195 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4196
4197 switch (intel_trans_dp_port_sel(crtc)) {
4198 case PORT_B:
4199 temp |= TRANS_DP_PORT_SEL_B;
4200 break;
4201 case PORT_C:
4202 temp |= TRANS_DP_PORT_SEL_C;
4203 break;
4204 case PORT_D:
4205 temp |= TRANS_DP_PORT_SEL_D;
4206 break;
4207 default:
4208 BUG();
4209 }
4210
4211 I915_WRITE(reg, temp);
4212 }
4213
4214 ironlake_enable_pch_transcoder(dev_priv, pipe);
4215 }
4216
4217 static void lpt_pch_enable(struct drm_crtc *crtc)
4218 {
4219 struct drm_device *dev = crtc->dev;
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4222 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4223
4224 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4225
4226 lpt_program_iclkip(crtc);
4227
4228 /* Set transcoder timing. */
4229 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4230
4231 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4232 }
4233
4234 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4235 struct intel_crtc_state *crtc_state)
4236 {
4237 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4238 struct intel_shared_dpll *pll;
4239 struct intel_shared_dpll_config *shared_dpll;
4240 enum intel_dpll_id i;
4241 int max = dev_priv->num_shared_dpll;
4242
4243 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4244
4245 if (HAS_PCH_IBX(dev_priv->dev)) {
4246 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4247 i = (enum intel_dpll_id) crtc->pipe;
4248 pll = &dev_priv->shared_dplls[i];
4249
4250 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4251 crtc->base.base.id, pll->name);
4252
4253 WARN_ON(shared_dpll[i].crtc_mask);
4254
4255 goto found;
4256 }
4257
4258 if (IS_BROXTON(dev_priv->dev)) {
4259 /* PLL is attached to port in bxt */
4260 struct intel_encoder *encoder;
4261 struct intel_digital_port *intel_dig_port;
4262
4263 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4264 if (WARN_ON(!encoder))
4265 return NULL;
4266
4267 intel_dig_port = enc_to_dig_port(&encoder->base);
4268 /* 1:1 mapping between ports and PLLs */
4269 i = (enum intel_dpll_id)intel_dig_port->port;
4270 pll = &dev_priv->shared_dplls[i];
4271 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4272 crtc->base.base.id, pll->name);
4273 WARN_ON(shared_dpll[i].crtc_mask);
4274
4275 goto found;
4276 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4277 /* Do not consider SPLL */
4278 max = 2;
4279
4280 for (i = 0; i < max; i++) {
4281 pll = &dev_priv->shared_dplls[i];
4282
4283 /* Only want to check enabled timings first */
4284 if (shared_dpll[i].crtc_mask == 0)
4285 continue;
4286
4287 if (memcmp(&crtc_state->dpll_hw_state,
4288 &shared_dpll[i].hw_state,
4289 sizeof(crtc_state->dpll_hw_state)) == 0) {
4290 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4291 crtc->base.base.id, pll->name,
4292 shared_dpll[i].crtc_mask,
4293 pll->active);
4294 goto found;
4295 }
4296 }
4297
4298 /* Ok no matching timings, maybe there's a free one? */
4299 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4300 pll = &dev_priv->shared_dplls[i];
4301 if (shared_dpll[i].crtc_mask == 0) {
4302 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4303 crtc->base.base.id, pll->name);
4304 goto found;
4305 }
4306 }
4307
4308 return NULL;
4309
4310 found:
4311 if (shared_dpll[i].crtc_mask == 0)
4312 shared_dpll[i].hw_state =
4313 crtc_state->dpll_hw_state;
4314
4315 crtc_state->shared_dpll = i;
4316 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4317 pipe_name(crtc->pipe));
4318
4319 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4320
4321 return pll;
4322 }
4323
4324 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4325 {
4326 struct drm_i915_private *dev_priv = to_i915(state->dev);
4327 struct intel_shared_dpll_config *shared_dpll;
4328 struct intel_shared_dpll *pll;
4329 enum intel_dpll_id i;
4330
4331 if (!to_intel_atomic_state(state)->dpll_set)
4332 return;
4333
4334 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4335 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4336 pll = &dev_priv->shared_dplls[i];
4337 pll->config = shared_dpll[i];
4338 }
4339 }
4340
4341 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4342 {
4343 struct drm_i915_private *dev_priv = dev->dev_private;
4344 i915_reg_t dslreg = PIPEDSL(pipe);
4345 u32 temp;
4346
4347 temp = I915_READ(dslreg);
4348 udelay(500);
4349 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4350 if (wait_for(I915_READ(dslreg) != temp, 5))
4351 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4352 }
4353 }
4354
4355 static int
4356 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4357 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4358 int src_w, int src_h, int dst_w, int dst_h)
4359 {
4360 struct intel_crtc_scaler_state *scaler_state =
4361 &crtc_state->scaler_state;
4362 struct intel_crtc *intel_crtc =
4363 to_intel_crtc(crtc_state->base.crtc);
4364 int need_scaling;
4365
4366 need_scaling = intel_rotation_90_or_270(rotation) ?
4367 (src_h != dst_w || src_w != dst_h):
4368 (src_w != dst_w || src_h != dst_h);
4369
4370 /*
4371 * if plane is being disabled or scaler is no more required or force detach
4372 * - free scaler binded to this plane/crtc
4373 * - in order to do this, update crtc->scaler_usage
4374 *
4375 * Here scaler state in crtc_state is set free so that
4376 * scaler can be assigned to other user. Actual register
4377 * update to free the scaler is done in plane/panel-fit programming.
4378 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4379 */
4380 if (force_detach || !need_scaling) {
4381 if (*scaler_id >= 0) {
4382 scaler_state->scaler_users &= ~(1 << scaler_user);
4383 scaler_state->scalers[*scaler_id].in_use = 0;
4384
4385 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4386 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4387 intel_crtc->pipe, scaler_user, *scaler_id,
4388 scaler_state->scaler_users);
4389 *scaler_id = -1;
4390 }
4391 return 0;
4392 }
4393
4394 /* range checks */
4395 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4396 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4397
4398 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4399 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4400 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4401 "size is out of scaler range\n",
4402 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4403 return -EINVAL;
4404 }
4405
4406 /* mark this plane as a scaler user in crtc_state */
4407 scaler_state->scaler_users |= (1 << scaler_user);
4408 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4409 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4410 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4411 scaler_state->scaler_users);
4412
4413 return 0;
4414 }
4415
4416 /**
4417 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4418 *
4419 * @state: crtc's scaler state
4420 *
4421 * Return
4422 * 0 - scaler_usage updated successfully
4423 * error - requested scaling cannot be supported or other error condition
4424 */
4425 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4426 {
4427 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4428 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4429
4430 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4431 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4432
4433 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4434 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4435 state->pipe_src_w, state->pipe_src_h,
4436 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4437 }
4438
4439 /**
4440 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4441 *
4442 * @state: crtc's scaler state
4443 * @plane_state: atomic plane state to update
4444 *
4445 * Return
4446 * 0 - scaler_usage updated successfully
4447 * error - requested scaling cannot be supported or other error condition
4448 */
4449 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4450 struct intel_plane_state *plane_state)
4451 {
4452
4453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4454 struct intel_plane *intel_plane =
4455 to_intel_plane(plane_state->base.plane);
4456 struct drm_framebuffer *fb = plane_state->base.fb;
4457 int ret;
4458
4459 bool force_detach = !fb || !plane_state->visible;
4460
4461 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4462 intel_plane->base.base.id, intel_crtc->pipe,
4463 drm_plane_index(&intel_plane->base));
4464
4465 ret = skl_update_scaler(crtc_state, force_detach,
4466 drm_plane_index(&intel_plane->base),
4467 &plane_state->scaler_id,
4468 plane_state->base.rotation,
4469 drm_rect_width(&plane_state->src) >> 16,
4470 drm_rect_height(&plane_state->src) >> 16,
4471 drm_rect_width(&plane_state->dst),
4472 drm_rect_height(&plane_state->dst));
4473
4474 if (ret || plane_state->scaler_id < 0)
4475 return ret;
4476
4477 /* check colorkey */
4478 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4479 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4480 intel_plane->base.base.id);
4481 return -EINVAL;
4482 }
4483
4484 /* Check src format */
4485 switch (fb->pixel_format) {
4486 case DRM_FORMAT_RGB565:
4487 case DRM_FORMAT_XBGR8888:
4488 case DRM_FORMAT_XRGB8888:
4489 case DRM_FORMAT_ABGR8888:
4490 case DRM_FORMAT_ARGB8888:
4491 case DRM_FORMAT_XRGB2101010:
4492 case DRM_FORMAT_XBGR2101010:
4493 case DRM_FORMAT_YUYV:
4494 case DRM_FORMAT_YVYU:
4495 case DRM_FORMAT_UYVY:
4496 case DRM_FORMAT_VYUY:
4497 break;
4498 default:
4499 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4500 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4501 return -EINVAL;
4502 }
4503
4504 return 0;
4505 }
4506
4507 static void skylake_scaler_disable(struct intel_crtc *crtc)
4508 {
4509 int i;
4510
4511 for (i = 0; i < crtc->num_scalers; i++)
4512 skl_detach_scaler(crtc, i);
4513 }
4514
4515 static void skylake_pfit_enable(struct intel_crtc *crtc)
4516 {
4517 struct drm_device *dev = crtc->base.dev;
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4519 int pipe = crtc->pipe;
4520 struct intel_crtc_scaler_state *scaler_state =
4521 &crtc->config->scaler_state;
4522
4523 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4524
4525 if (crtc->config->pch_pfit.enabled) {
4526 int id;
4527
4528 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4529 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4530 return;
4531 }
4532
4533 id = scaler_state->scaler_id;
4534 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4535 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4536 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4537 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4538
4539 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4540 }
4541 }
4542
4543 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4544 {
4545 struct drm_device *dev = crtc->base.dev;
4546 struct drm_i915_private *dev_priv = dev->dev_private;
4547 int pipe = crtc->pipe;
4548
4549 if (crtc->config->pch_pfit.enabled) {
4550 /* Force use of hard-coded filter coefficients
4551 * as some pre-programmed values are broken,
4552 * e.g. x201.
4553 */
4554 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4555 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4556 PF_PIPE_SEL_IVB(pipe));
4557 else
4558 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4559 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4560 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4561 }
4562 }
4563
4564 void hsw_enable_ips(struct intel_crtc *crtc)
4565 {
4566 struct drm_device *dev = crtc->base.dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568
4569 if (!crtc->config->ips_enabled)
4570 return;
4571
4572 /* We can only enable IPS after we enable a plane and wait for a vblank */
4573 intel_wait_for_vblank(dev, crtc->pipe);
4574
4575 assert_plane_enabled(dev_priv, crtc->plane);
4576 if (IS_BROADWELL(dev)) {
4577 mutex_lock(&dev_priv->rps.hw_lock);
4578 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4579 mutex_unlock(&dev_priv->rps.hw_lock);
4580 /* Quoting Art Runyan: "its not safe to expect any particular
4581 * value in IPS_CTL bit 31 after enabling IPS through the
4582 * mailbox." Moreover, the mailbox may return a bogus state,
4583 * so we need to just enable it and continue on.
4584 */
4585 } else {
4586 I915_WRITE(IPS_CTL, IPS_ENABLE);
4587 /* The bit only becomes 1 in the next vblank, so this wait here
4588 * is essentially intel_wait_for_vblank. If we don't have this
4589 * and don't wait for vblanks until the end of crtc_enable, then
4590 * the HW state readout code will complain that the expected
4591 * IPS_CTL value is not the one we read. */
4592 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4593 DRM_ERROR("Timed out waiting for IPS enable\n");
4594 }
4595 }
4596
4597 void hsw_disable_ips(struct intel_crtc *crtc)
4598 {
4599 struct drm_device *dev = crtc->base.dev;
4600 struct drm_i915_private *dev_priv = dev->dev_private;
4601
4602 if (!crtc->config->ips_enabled)
4603 return;
4604
4605 assert_plane_enabled(dev_priv, crtc->plane);
4606 if (IS_BROADWELL(dev)) {
4607 mutex_lock(&dev_priv->rps.hw_lock);
4608 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4609 mutex_unlock(&dev_priv->rps.hw_lock);
4610 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4611 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4612 DRM_ERROR("Timed out waiting for IPS disable\n");
4613 } else {
4614 I915_WRITE(IPS_CTL, 0);
4615 POSTING_READ(IPS_CTL);
4616 }
4617
4618 /* We need to wait for a vblank before we can disable the plane. */
4619 intel_wait_for_vblank(dev, crtc->pipe);
4620 }
4621
4622 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4623 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4624 {
4625 struct drm_device *dev = crtc->dev;
4626 struct drm_i915_private *dev_priv = dev->dev_private;
4627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4628 enum pipe pipe = intel_crtc->pipe;
4629 int i;
4630 bool reenable_ips = false;
4631
4632 /* The clocks have to be on to load the palette. */
4633 if (!crtc->state->active)
4634 return;
4635
4636 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4637 if (intel_crtc->config->has_dsi_encoder)
4638 assert_dsi_pll_enabled(dev_priv);
4639 else
4640 assert_pll_enabled(dev_priv, pipe);
4641 }
4642
4643 /* Workaround : Do not read or write the pipe palette/gamma data while
4644 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4645 */
4646 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4647 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4648 GAMMA_MODE_MODE_SPLIT)) {
4649 hsw_disable_ips(intel_crtc);
4650 reenable_ips = true;
4651 }
4652
4653 for (i = 0; i < 256; i++) {
4654 i915_reg_t palreg;
4655
4656 if (HAS_GMCH_DISPLAY(dev))
4657 palreg = PALETTE(pipe, i);
4658 else
4659 palreg = LGC_PALETTE(pipe, i);
4660
4661 I915_WRITE(palreg,
4662 (intel_crtc->lut_r[i] << 16) |
4663 (intel_crtc->lut_g[i] << 8) |
4664 intel_crtc->lut_b[i]);
4665 }
4666
4667 if (reenable_ips)
4668 hsw_enable_ips(intel_crtc);
4669 }
4670
4671 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4672 {
4673 if (intel_crtc->overlay) {
4674 struct drm_device *dev = intel_crtc->base.dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676
4677 mutex_lock(&dev->struct_mutex);
4678 dev_priv->mm.interruptible = false;
4679 (void) intel_overlay_switch_off(intel_crtc->overlay);
4680 dev_priv->mm.interruptible = true;
4681 mutex_unlock(&dev->struct_mutex);
4682 }
4683
4684 /* Let userspace switch the overlay on again. In most cases userspace
4685 * has to recompute where to put it anyway.
4686 */
4687 }
4688
4689 /**
4690 * intel_post_enable_primary - Perform operations after enabling primary plane
4691 * @crtc: the CRTC whose primary plane was just enabled
4692 *
4693 * Performs potentially sleeping operations that must be done after the primary
4694 * plane is enabled, such as updating FBC and IPS. Note that this may be
4695 * called due to an explicit primary plane update, or due to an implicit
4696 * re-enable that is caused when a sprite plane is updated to no longer
4697 * completely hide the primary plane.
4698 */
4699 static void
4700 intel_post_enable_primary(struct drm_crtc *crtc)
4701 {
4702 struct drm_device *dev = crtc->dev;
4703 struct drm_i915_private *dev_priv = dev->dev_private;
4704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4705 int pipe = intel_crtc->pipe;
4706
4707 /*
4708 * FIXME IPS should be fine as long as one plane is
4709 * enabled, but in practice it seems to have problems
4710 * when going from primary only to sprite only and vice
4711 * versa.
4712 */
4713 hsw_enable_ips(intel_crtc);
4714
4715 /*
4716 * Gen2 reports pipe underruns whenever all planes are disabled.
4717 * So don't enable underrun reporting before at least some planes
4718 * are enabled.
4719 * FIXME: Need to fix the logic to work when we turn off all planes
4720 * but leave the pipe running.
4721 */
4722 if (IS_GEN2(dev))
4723 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4724
4725 /* Underruns don't always raise interrupts, so check manually. */
4726 intel_check_cpu_fifo_underruns(dev_priv);
4727 intel_check_pch_fifo_underruns(dev_priv);
4728 }
4729
4730 /**
4731 * intel_pre_disable_primary - Perform operations before disabling primary plane
4732 * @crtc: the CRTC whose primary plane is to be disabled
4733 *
4734 * Performs potentially sleeping operations that must be done before the
4735 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4736 * be called due to an explicit primary plane update, or due to an implicit
4737 * disable that is caused when a sprite plane completely hides the primary
4738 * plane.
4739 */
4740 static void
4741 intel_pre_disable_primary(struct drm_crtc *crtc)
4742 {
4743 struct drm_device *dev = crtc->dev;
4744 struct drm_i915_private *dev_priv = dev->dev_private;
4745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4746 int pipe = intel_crtc->pipe;
4747
4748 /*
4749 * Gen2 reports pipe underruns whenever all planes are disabled.
4750 * So diasble underrun reporting before all the planes get disabled.
4751 * FIXME: Need to fix the logic to work when we turn off all planes
4752 * but leave the pipe running.
4753 */
4754 if (IS_GEN2(dev))
4755 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4756
4757 /*
4758 * Vblank time updates from the shadow to live plane control register
4759 * are blocked if the memory self-refresh mode is active at that
4760 * moment. So to make sure the plane gets truly disabled, disable
4761 * first the self-refresh mode. The self-refresh enable bit in turn
4762 * will be checked/applied by the HW only at the next frame start
4763 * event which is after the vblank start event, so we need to have a
4764 * wait-for-vblank between disabling the plane and the pipe.
4765 */
4766 if (HAS_GMCH_DISPLAY(dev)) {
4767 intel_set_memory_cxsr(dev_priv, false);
4768 dev_priv->wm.vlv.cxsr = false;
4769 intel_wait_for_vblank(dev, pipe);
4770 }
4771
4772 /*
4773 * FIXME IPS should be fine as long as one plane is
4774 * enabled, but in practice it seems to have problems
4775 * when going from primary only to sprite only and vice
4776 * versa.
4777 */
4778 hsw_disable_ips(intel_crtc);
4779 }
4780
4781 static void intel_post_plane_update(struct intel_crtc *crtc)
4782 {
4783 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4784 struct intel_crtc_state *pipe_config =
4785 to_intel_crtc_state(crtc->base.state);
4786 struct drm_device *dev = crtc->base.dev;
4787
4788 if (atomic->wait_vblank)
4789 intel_wait_for_vblank(dev, crtc->pipe);
4790
4791 intel_frontbuffer_flip(dev, atomic->fb_bits);
4792
4793 crtc->wm.cxsr_allowed = true;
4794
4795 if (pipe_config->wm_changed && pipe_config->base.active)
4796 intel_update_watermarks(&crtc->base);
4797
4798 if (atomic->update_fbc)
4799 intel_fbc_post_update(crtc);
4800
4801 if (atomic->post_enable_primary)
4802 intel_post_enable_primary(&crtc->base);
4803
4804 memset(atomic, 0, sizeof(*atomic));
4805 }
4806
4807 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4808 {
4809 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4810 struct drm_device *dev = crtc->base.dev;
4811 struct drm_i915_private *dev_priv = dev->dev_private;
4812 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4813 struct intel_crtc_state *pipe_config =
4814 to_intel_crtc_state(crtc->base.state);
4815 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4816 struct drm_plane *primary = crtc->base.primary;
4817 struct drm_plane_state *old_pri_state =
4818 drm_atomic_get_existing_plane_state(old_state, primary);
4819 bool modeset = needs_modeset(&pipe_config->base);
4820
4821 if (atomic->update_fbc)
4822 intel_fbc_pre_update(crtc);
4823
4824 if (old_pri_state) {
4825 struct intel_plane_state *primary_state =
4826 to_intel_plane_state(primary->state);
4827 struct intel_plane_state *old_primary_state =
4828 to_intel_plane_state(old_pri_state);
4829
4830 if (old_primary_state->visible &&
4831 (modeset || !primary_state->visible))
4832 intel_pre_disable_primary(&crtc->base);
4833 }
4834
4835 if (pipe_config->disable_cxsr) {
4836 crtc->wm.cxsr_allowed = false;
4837
4838 if (old_crtc_state->base.active)
4839 intel_set_memory_cxsr(dev_priv, false);
4840 }
4841
4842 if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4843 intel_update_watermarks(&crtc->base);
4844 }
4845
4846 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4847 {
4848 struct drm_device *dev = crtc->dev;
4849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4850 struct drm_plane *p;
4851 int pipe = intel_crtc->pipe;
4852
4853 intel_crtc_dpms_overlay_disable(intel_crtc);
4854
4855 drm_for_each_plane_mask(p, dev, plane_mask)
4856 to_intel_plane(p)->disable_plane(p, crtc);
4857
4858 /*
4859 * FIXME: Once we grow proper nuclear flip support out of this we need
4860 * to compute the mask of flip planes precisely. For the time being
4861 * consider this a flip to a NULL plane.
4862 */
4863 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4864 }
4865
4866 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4867 {
4868 struct drm_device *dev = crtc->dev;
4869 struct drm_i915_private *dev_priv = dev->dev_private;
4870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4871 struct intel_encoder *encoder;
4872 int pipe = intel_crtc->pipe;
4873
4874 if (WARN_ON(intel_crtc->active))
4875 return;
4876
4877 if (intel_crtc->config->has_pch_encoder)
4878 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4879
4880 if (intel_crtc->config->has_pch_encoder)
4881 intel_prepare_shared_dpll(intel_crtc);
4882
4883 if (intel_crtc->config->has_dp_encoder)
4884 intel_dp_set_m_n(intel_crtc, M1_N1);
4885
4886 intel_set_pipe_timings(intel_crtc);
4887
4888 if (intel_crtc->config->has_pch_encoder) {
4889 intel_cpu_transcoder_set_m_n(intel_crtc,
4890 &intel_crtc->config->fdi_m_n, NULL);
4891 }
4892
4893 ironlake_set_pipeconf(crtc);
4894
4895 intel_crtc->active = true;
4896
4897 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4898
4899 for_each_encoder_on_crtc(dev, crtc, encoder)
4900 if (encoder->pre_enable)
4901 encoder->pre_enable(encoder);
4902
4903 if (intel_crtc->config->has_pch_encoder) {
4904 /* Note: FDI PLL enabling _must_ be done before we enable the
4905 * cpu pipes, hence this is separate from all the other fdi/pch
4906 * enabling. */
4907 ironlake_fdi_pll_enable(intel_crtc);
4908 } else {
4909 assert_fdi_tx_disabled(dev_priv, pipe);
4910 assert_fdi_rx_disabled(dev_priv, pipe);
4911 }
4912
4913 ironlake_pfit_enable(intel_crtc);
4914
4915 /*
4916 * On ILK+ LUT must be loaded before the pipe is running but with
4917 * clocks enabled
4918 */
4919 intel_crtc_load_lut(crtc);
4920
4921 intel_update_watermarks(crtc);
4922 intel_enable_pipe(intel_crtc);
4923
4924 if (intel_crtc->config->has_pch_encoder)
4925 ironlake_pch_enable(crtc);
4926
4927 assert_vblank_disabled(crtc);
4928 drm_crtc_vblank_on(crtc);
4929
4930 for_each_encoder_on_crtc(dev, crtc, encoder)
4931 encoder->enable(encoder);
4932
4933 if (HAS_PCH_CPT(dev))
4934 cpt_verify_modeset(dev, intel_crtc->pipe);
4935
4936 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4937 if (intel_crtc->config->has_pch_encoder)
4938 intel_wait_for_vblank(dev, pipe);
4939 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4940 }
4941
4942 /* IPS only exists on ULT machines and is tied to pipe A. */
4943 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4944 {
4945 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4946 }
4947
4948 static void haswell_crtc_enable(struct drm_crtc *crtc)
4949 {
4950 struct drm_device *dev = crtc->dev;
4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4953 struct intel_encoder *encoder;
4954 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4955 struct intel_crtc_state *pipe_config =
4956 to_intel_crtc_state(crtc->state);
4957
4958 if (WARN_ON(intel_crtc->active))
4959 return;
4960
4961 if (intel_crtc->config->has_pch_encoder)
4962 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4963 false);
4964
4965 if (intel_crtc_to_shared_dpll(intel_crtc))
4966 intel_enable_shared_dpll(intel_crtc);
4967
4968 if (intel_crtc->config->has_dp_encoder)
4969 intel_dp_set_m_n(intel_crtc, M1_N1);
4970
4971 intel_set_pipe_timings(intel_crtc);
4972
4973 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4974 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4975 intel_crtc->config->pixel_multiplier - 1);
4976 }
4977
4978 if (intel_crtc->config->has_pch_encoder) {
4979 intel_cpu_transcoder_set_m_n(intel_crtc,
4980 &intel_crtc->config->fdi_m_n, NULL);
4981 }
4982
4983 haswell_set_pipeconf(crtc);
4984
4985 intel_set_pipe_csc(crtc);
4986
4987 intel_crtc->active = true;
4988
4989 if (intel_crtc->config->has_pch_encoder)
4990 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4991 else
4992 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4993
4994 for_each_encoder_on_crtc(dev, crtc, encoder) {
4995 if (encoder->pre_enable)
4996 encoder->pre_enable(encoder);
4997 }
4998
4999 if (intel_crtc->config->has_pch_encoder)
5000 dev_priv->display.fdi_link_train(crtc);
5001
5002 if (!intel_crtc->config->has_dsi_encoder)
5003 intel_ddi_enable_pipe_clock(intel_crtc);
5004
5005 if (INTEL_INFO(dev)->gen >= 9)
5006 skylake_pfit_enable(intel_crtc);
5007 else
5008 ironlake_pfit_enable(intel_crtc);
5009
5010 /*
5011 * On ILK+ LUT must be loaded before the pipe is running but with
5012 * clocks enabled
5013 */
5014 intel_crtc_load_lut(crtc);
5015
5016 intel_ddi_set_pipe_settings(crtc);
5017 if (!intel_crtc->config->has_dsi_encoder)
5018 intel_ddi_enable_transcoder_func(crtc);
5019
5020 intel_update_watermarks(crtc);
5021 intel_enable_pipe(intel_crtc);
5022
5023 if (intel_crtc->config->has_pch_encoder)
5024 lpt_pch_enable(crtc);
5025
5026 if (intel_crtc->config->dp_encoder_is_mst)
5027 intel_ddi_set_vc_payload_alloc(crtc, true);
5028
5029 assert_vblank_disabled(crtc);
5030 drm_crtc_vblank_on(crtc);
5031
5032 for_each_encoder_on_crtc(dev, crtc, encoder) {
5033 encoder->enable(encoder);
5034 intel_opregion_notify_encoder(encoder, true);
5035 }
5036
5037 if (intel_crtc->config->has_pch_encoder) {
5038 intel_wait_for_vblank(dev, pipe);
5039 intel_wait_for_vblank(dev, pipe);
5040 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5041 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5042 true);
5043 }
5044
5045 /* If we change the relative order between pipe/planes enabling, we need
5046 * to change the workaround. */
5047 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5048 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5049 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5050 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5051 }
5052 }
5053
5054 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5055 {
5056 struct drm_device *dev = crtc->base.dev;
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 int pipe = crtc->pipe;
5059
5060 /* To avoid upsetting the power well on haswell only disable the pfit if
5061 * it's in use. The hw state code will make sure we get this right. */
5062 if (force || crtc->config->pch_pfit.enabled) {
5063 I915_WRITE(PF_CTL(pipe), 0);
5064 I915_WRITE(PF_WIN_POS(pipe), 0);
5065 I915_WRITE(PF_WIN_SZ(pipe), 0);
5066 }
5067 }
5068
5069 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5070 {
5071 struct drm_device *dev = crtc->dev;
5072 struct drm_i915_private *dev_priv = dev->dev_private;
5073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5074 struct intel_encoder *encoder;
5075 int pipe = intel_crtc->pipe;
5076
5077 if (intel_crtc->config->has_pch_encoder)
5078 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5079
5080 for_each_encoder_on_crtc(dev, crtc, encoder)
5081 encoder->disable(encoder);
5082
5083 drm_crtc_vblank_off(crtc);
5084 assert_vblank_disabled(crtc);
5085
5086 /*
5087 * Sometimes spurious CPU pipe underruns happen when the
5088 * pipe is already disabled, but FDI RX/TX is still enabled.
5089 * Happens at least with VGA+HDMI cloning. Suppress them.
5090 */
5091 if (intel_crtc->config->has_pch_encoder)
5092 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5093
5094 intel_disable_pipe(intel_crtc);
5095
5096 ironlake_pfit_disable(intel_crtc, false);
5097
5098 if (intel_crtc->config->has_pch_encoder) {
5099 ironlake_fdi_disable(crtc);
5100 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5101 }
5102
5103 for_each_encoder_on_crtc(dev, crtc, encoder)
5104 if (encoder->post_disable)
5105 encoder->post_disable(encoder);
5106
5107 if (intel_crtc->config->has_pch_encoder) {
5108 ironlake_disable_pch_transcoder(dev_priv, pipe);
5109
5110 if (HAS_PCH_CPT(dev)) {
5111 i915_reg_t reg;
5112 u32 temp;
5113
5114 /* disable TRANS_DP_CTL */
5115 reg = TRANS_DP_CTL(pipe);
5116 temp = I915_READ(reg);
5117 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5118 TRANS_DP_PORT_SEL_MASK);
5119 temp |= TRANS_DP_PORT_SEL_NONE;
5120 I915_WRITE(reg, temp);
5121
5122 /* disable DPLL_SEL */
5123 temp = I915_READ(PCH_DPLL_SEL);
5124 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5125 I915_WRITE(PCH_DPLL_SEL, temp);
5126 }
5127
5128 ironlake_fdi_pll_disable(intel_crtc);
5129 }
5130
5131 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5132 }
5133
5134 static void haswell_crtc_disable(struct drm_crtc *crtc)
5135 {
5136 struct drm_device *dev = crtc->dev;
5137 struct drm_i915_private *dev_priv = dev->dev_private;
5138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5139 struct intel_encoder *encoder;
5140 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5141
5142 if (intel_crtc->config->has_pch_encoder)
5143 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5144 false);
5145
5146 for_each_encoder_on_crtc(dev, crtc, encoder) {
5147 intel_opregion_notify_encoder(encoder, false);
5148 encoder->disable(encoder);
5149 }
5150
5151 drm_crtc_vblank_off(crtc);
5152 assert_vblank_disabled(crtc);
5153
5154 intel_disable_pipe(intel_crtc);
5155
5156 if (intel_crtc->config->dp_encoder_is_mst)
5157 intel_ddi_set_vc_payload_alloc(crtc, false);
5158
5159 if (!intel_crtc->config->has_dsi_encoder)
5160 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5161
5162 if (INTEL_INFO(dev)->gen >= 9)
5163 skylake_scaler_disable(intel_crtc);
5164 else
5165 ironlake_pfit_disable(intel_crtc, false);
5166
5167 if (!intel_crtc->config->has_dsi_encoder)
5168 intel_ddi_disable_pipe_clock(intel_crtc);
5169
5170 for_each_encoder_on_crtc(dev, crtc, encoder)
5171 if (encoder->post_disable)
5172 encoder->post_disable(encoder);
5173
5174 if (intel_crtc->config->has_pch_encoder) {
5175 lpt_disable_pch_transcoder(dev_priv);
5176 lpt_disable_iclkip(dev_priv);
5177 intel_ddi_fdi_disable(crtc);
5178
5179 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5180 true);
5181 }
5182 }
5183
5184 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5185 {
5186 struct drm_device *dev = crtc->base.dev;
5187 struct drm_i915_private *dev_priv = dev->dev_private;
5188 struct intel_crtc_state *pipe_config = crtc->config;
5189
5190 if (!pipe_config->gmch_pfit.control)
5191 return;
5192
5193 /*
5194 * The panel fitter should only be adjusted whilst the pipe is disabled,
5195 * according to register description and PRM.
5196 */
5197 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5198 assert_pipe_disabled(dev_priv, crtc->pipe);
5199
5200 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5201 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5202
5203 /* Border color in case we don't scale up to the full screen. Black by
5204 * default, change to something else for debugging. */
5205 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5206 }
5207
5208 static enum intel_display_power_domain port_to_power_domain(enum port port)
5209 {
5210 switch (port) {
5211 case PORT_A:
5212 return POWER_DOMAIN_PORT_DDI_A_LANES;
5213 case PORT_B:
5214 return POWER_DOMAIN_PORT_DDI_B_LANES;
5215 case PORT_C:
5216 return POWER_DOMAIN_PORT_DDI_C_LANES;
5217 case PORT_D:
5218 return POWER_DOMAIN_PORT_DDI_D_LANES;
5219 case PORT_E:
5220 return POWER_DOMAIN_PORT_DDI_E_LANES;
5221 default:
5222 MISSING_CASE(port);
5223 return POWER_DOMAIN_PORT_OTHER;
5224 }
5225 }
5226
5227 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5228 {
5229 switch (port) {
5230 case PORT_A:
5231 return POWER_DOMAIN_AUX_A;
5232 case PORT_B:
5233 return POWER_DOMAIN_AUX_B;
5234 case PORT_C:
5235 return POWER_DOMAIN_AUX_C;
5236 case PORT_D:
5237 return POWER_DOMAIN_AUX_D;
5238 case PORT_E:
5239 /* FIXME: Check VBT for actual wiring of PORT E */
5240 return POWER_DOMAIN_AUX_D;
5241 default:
5242 MISSING_CASE(port);
5243 return POWER_DOMAIN_AUX_A;
5244 }
5245 }
5246
5247 enum intel_display_power_domain
5248 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5249 {
5250 struct drm_device *dev = intel_encoder->base.dev;
5251 struct intel_digital_port *intel_dig_port;
5252
5253 switch (intel_encoder->type) {
5254 case INTEL_OUTPUT_UNKNOWN:
5255 /* Only DDI platforms should ever use this output type */
5256 WARN_ON_ONCE(!HAS_DDI(dev));
5257 case INTEL_OUTPUT_DISPLAYPORT:
5258 case INTEL_OUTPUT_HDMI:
5259 case INTEL_OUTPUT_EDP:
5260 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5261 return port_to_power_domain(intel_dig_port->port);
5262 case INTEL_OUTPUT_DP_MST:
5263 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5264 return port_to_power_domain(intel_dig_port->port);
5265 case INTEL_OUTPUT_ANALOG:
5266 return POWER_DOMAIN_PORT_CRT;
5267 case INTEL_OUTPUT_DSI:
5268 return POWER_DOMAIN_PORT_DSI;
5269 default:
5270 return POWER_DOMAIN_PORT_OTHER;
5271 }
5272 }
5273
5274 enum intel_display_power_domain
5275 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5276 {
5277 struct drm_device *dev = intel_encoder->base.dev;
5278 struct intel_digital_port *intel_dig_port;
5279
5280 switch (intel_encoder->type) {
5281 case INTEL_OUTPUT_UNKNOWN:
5282 case INTEL_OUTPUT_HDMI:
5283 /*
5284 * Only DDI platforms should ever use these output types.
5285 * We can get here after the HDMI detect code has already set
5286 * the type of the shared encoder. Since we can't be sure
5287 * what's the status of the given connectors, play safe and
5288 * run the DP detection too.
5289 */
5290 WARN_ON_ONCE(!HAS_DDI(dev));
5291 case INTEL_OUTPUT_DISPLAYPORT:
5292 case INTEL_OUTPUT_EDP:
5293 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5294 return port_to_aux_power_domain(intel_dig_port->port);
5295 case INTEL_OUTPUT_DP_MST:
5296 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5297 return port_to_aux_power_domain(intel_dig_port->port);
5298 default:
5299 MISSING_CASE(intel_encoder->type);
5300 return POWER_DOMAIN_AUX_A;
5301 }
5302 }
5303
5304 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5305 {
5306 struct drm_device *dev = crtc->dev;
5307 struct intel_encoder *intel_encoder;
5308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5309 enum pipe pipe = intel_crtc->pipe;
5310 unsigned long mask;
5311 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5312
5313 if (!crtc->state->active)
5314 return 0;
5315
5316 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5317 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5318 if (intel_crtc->config->pch_pfit.enabled ||
5319 intel_crtc->config->pch_pfit.force_thru)
5320 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5321
5322 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5323 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5324
5325 return mask;
5326 }
5327
5328 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5329 {
5330 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5332 enum intel_display_power_domain domain;
5333 unsigned long domains, new_domains, old_domains;
5334
5335 old_domains = intel_crtc->enabled_power_domains;
5336 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5337
5338 domains = new_domains & ~old_domains;
5339
5340 for_each_power_domain(domain, domains)
5341 intel_display_power_get(dev_priv, domain);
5342
5343 return old_domains & ~new_domains;
5344 }
5345
5346 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5347 unsigned long domains)
5348 {
5349 enum intel_display_power_domain domain;
5350
5351 for_each_power_domain(domain, domains)
5352 intel_display_power_put(dev_priv, domain);
5353 }
5354
5355 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5356 {
5357 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5358 struct drm_device *dev = state->dev;
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360 unsigned long put_domains[I915_MAX_PIPES] = {};
5361 struct drm_crtc_state *crtc_state;
5362 struct drm_crtc *crtc;
5363 int i;
5364
5365 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5366 if (needs_modeset(crtc->state))
5367 put_domains[to_intel_crtc(crtc)->pipe] =
5368 modeset_get_crtc_power_domains(crtc);
5369 }
5370
5371 if (dev_priv->display.modeset_commit_cdclk &&
5372 intel_state->dev_cdclk != dev_priv->cdclk_freq)
5373 dev_priv->display.modeset_commit_cdclk(state);
5374
5375 for (i = 0; i < I915_MAX_PIPES; i++)
5376 if (put_domains[i])
5377 modeset_put_power_domains(dev_priv, put_domains[i]);
5378 }
5379
5380 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5381 {
5382 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5383
5384 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5385 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5386 return max_cdclk_freq;
5387 else if (IS_CHERRYVIEW(dev_priv))
5388 return max_cdclk_freq*95/100;
5389 else if (INTEL_INFO(dev_priv)->gen < 4)
5390 return 2*max_cdclk_freq*90/100;
5391 else
5392 return max_cdclk_freq*90/100;
5393 }
5394
5395 static void intel_update_max_cdclk(struct drm_device *dev)
5396 {
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5398
5399 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5400 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5401
5402 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5403 dev_priv->max_cdclk_freq = 675000;
5404 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5405 dev_priv->max_cdclk_freq = 540000;
5406 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5407 dev_priv->max_cdclk_freq = 450000;
5408 else
5409 dev_priv->max_cdclk_freq = 337500;
5410 } else if (IS_BROADWELL(dev)) {
5411 /*
5412 * FIXME with extra cooling we can allow
5413 * 540 MHz for ULX and 675 Mhz for ULT.
5414 * How can we know if extra cooling is
5415 * available? PCI ID, VTB, something else?
5416 */
5417 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5418 dev_priv->max_cdclk_freq = 450000;
5419 else if (IS_BDW_ULX(dev))
5420 dev_priv->max_cdclk_freq = 450000;
5421 else if (IS_BDW_ULT(dev))
5422 dev_priv->max_cdclk_freq = 540000;
5423 else
5424 dev_priv->max_cdclk_freq = 675000;
5425 } else if (IS_CHERRYVIEW(dev)) {
5426 dev_priv->max_cdclk_freq = 320000;
5427 } else if (IS_VALLEYVIEW(dev)) {
5428 dev_priv->max_cdclk_freq = 400000;
5429 } else {
5430 /* otherwise assume cdclk is fixed */
5431 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5432 }
5433
5434 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5435
5436 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5437 dev_priv->max_cdclk_freq);
5438
5439 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5440 dev_priv->max_dotclk_freq);
5441 }
5442
5443 static void intel_update_cdclk(struct drm_device *dev)
5444 {
5445 struct drm_i915_private *dev_priv = dev->dev_private;
5446
5447 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5448 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5449 dev_priv->cdclk_freq);
5450
5451 /*
5452 * Program the gmbus_freq based on the cdclk frequency.
5453 * BSpec erroneously claims we should aim for 4MHz, but
5454 * in fact 1MHz is the correct frequency.
5455 */
5456 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5457 /*
5458 * Program the gmbus_freq based on the cdclk frequency.
5459 * BSpec erroneously claims we should aim for 4MHz, but
5460 * in fact 1MHz is the correct frequency.
5461 */
5462 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5463 }
5464
5465 if (dev_priv->max_cdclk_freq == 0)
5466 intel_update_max_cdclk(dev);
5467 }
5468
5469 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5470 {
5471 struct drm_i915_private *dev_priv = dev->dev_private;
5472 uint32_t divider;
5473 uint32_t ratio;
5474 uint32_t current_freq;
5475 int ret;
5476
5477 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5478 switch (frequency) {
5479 case 144000:
5480 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5481 ratio = BXT_DE_PLL_RATIO(60);
5482 break;
5483 case 288000:
5484 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5485 ratio = BXT_DE_PLL_RATIO(60);
5486 break;
5487 case 384000:
5488 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5489 ratio = BXT_DE_PLL_RATIO(60);
5490 break;
5491 case 576000:
5492 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5493 ratio = BXT_DE_PLL_RATIO(60);
5494 break;
5495 case 624000:
5496 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5497 ratio = BXT_DE_PLL_RATIO(65);
5498 break;
5499 case 19200:
5500 /*
5501 * Bypass frequency with DE PLL disabled. Init ratio, divider
5502 * to suppress GCC warning.
5503 */
5504 ratio = 0;
5505 divider = 0;
5506 break;
5507 default:
5508 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5509
5510 return;
5511 }
5512
5513 mutex_lock(&dev_priv->rps.hw_lock);
5514 /* Inform power controller of upcoming frequency change */
5515 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5516 0x80000000);
5517 mutex_unlock(&dev_priv->rps.hw_lock);
5518
5519 if (ret) {
5520 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5521 ret, frequency);
5522 return;
5523 }
5524
5525 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5526 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5527 current_freq = current_freq * 500 + 1000;
5528
5529 /*
5530 * DE PLL has to be disabled when
5531 * - setting to 19.2MHz (bypass, PLL isn't used)
5532 * - before setting to 624MHz (PLL needs toggling)
5533 * - before setting to any frequency from 624MHz (PLL needs toggling)
5534 */
5535 if (frequency == 19200 || frequency == 624000 ||
5536 current_freq == 624000) {
5537 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5538 /* Timeout 200us */
5539 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5540 1))
5541 DRM_ERROR("timout waiting for DE PLL unlock\n");
5542 }
5543
5544 if (frequency != 19200) {
5545 uint32_t val;
5546
5547 val = I915_READ(BXT_DE_PLL_CTL);
5548 val &= ~BXT_DE_PLL_RATIO_MASK;
5549 val |= ratio;
5550 I915_WRITE(BXT_DE_PLL_CTL, val);
5551
5552 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5553 /* Timeout 200us */
5554 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5555 DRM_ERROR("timeout waiting for DE PLL lock\n");
5556
5557 val = I915_READ(CDCLK_CTL);
5558 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5559 val |= divider;
5560 /*
5561 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5562 * enable otherwise.
5563 */
5564 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5565 if (frequency >= 500000)
5566 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5567
5568 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5569 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5570 val |= (frequency - 1000) / 500;
5571 I915_WRITE(CDCLK_CTL, val);
5572 }
5573
5574 mutex_lock(&dev_priv->rps.hw_lock);
5575 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5576 DIV_ROUND_UP(frequency, 25000));
5577 mutex_unlock(&dev_priv->rps.hw_lock);
5578
5579 if (ret) {
5580 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5581 ret, frequency);
5582 return;
5583 }
5584
5585 intel_update_cdclk(dev);
5586 }
5587
5588 void broxton_init_cdclk(struct drm_device *dev)
5589 {
5590 struct drm_i915_private *dev_priv = dev->dev_private;
5591 uint32_t val;
5592
5593 /*
5594 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5595 * or else the reset will hang because there is no PCH to respond.
5596 * Move the handshake programming to initialization sequence.
5597 * Previously was left up to BIOS.
5598 */
5599 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5600 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5601 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5602
5603 /* Enable PG1 for cdclk */
5604 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5605
5606 /* check if cd clock is enabled */
5607 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5608 DRM_DEBUG_KMS("Display already initialized\n");
5609 return;
5610 }
5611
5612 /*
5613 * FIXME:
5614 * - The initial CDCLK needs to be read from VBT.
5615 * Need to make this change after VBT has changes for BXT.
5616 * - check if setting the max (or any) cdclk freq is really necessary
5617 * here, it belongs to modeset time
5618 */
5619 broxton_set_cdclk(dev, 624000);
5620
5621 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5622 POSTING_READ(DBUF_CTL);
5623
5624 udelay(10);
5625
5626 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5627 DRM_ERROR("DBuf power enable timeout!\n");
5628 }
5629
5630 void broxton_uninit_cdclk(struct drm_device *dev)
5631 {
5632 struct drm_i915_private *dev_priv = dev->dev_private;
5633
5634 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5635 POSTING_READ(DBUF_CTL);
5636
5637 udelay(10);
5638
5639 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5640 DRM_ERROR("DBuf power disable timeout!\n");
5641
5642 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5643 broxton_set_cdclk(dev, 19200);
5644
5645 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5646 }
5647
5648 static const struct skl_cdclk_entry {
5649 unsigned int freq;
5650 unsigned int vco;
5651 } skl_cdclk_frequencies[] = {
5652 { .freq = 308570, .vco = 8640 },
5653 { .freq = 337500, .vco = 8100 },
5654 { .freq = 432000, .vco = 8640 },
5655 { .freq = 450000, .vco = 8100 },
5656 { .freq = 540000, .vco = 8100 },
5657 { .freq = 617140, .vco = 8640 },
5658 { .freq = 675000, .vco = 8100 },
5659 };
5660
5661 static unsigned int skl_cdclk_decimal(unsigned int freq)
5662 {
5663 return (freq - 1000) / 500;
5664 }
5665
5666 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5667 {
5668 unsigned int i;
5669
5670 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5671 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5672
5673 if (e->freq == freq)
5674 return e->vco;
5675 }
5676
5677 return 8100;
5678 }
5679
5680 static void
5681 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5682 {
5683 unsigned int min_freq;
5684 u32 val;
5685
5686 /* select the minimum CDCLK before enabling DPLL 0 */
5687 val = I915_READ(CDCLK_CTL);
5688 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5689 val |= CDCLK_FREQ_337_308;
5690
5691 if (required_vco == 8640)
5692 min_freq = 308570;
5693 else
5694 min_freq = 337500;
5695
5696 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5697
5698 I915_WRITE(CDCLK_CTL, val);
5699 POSTING_READ(CDCLK_CTL);
5700
5701 /*
5702 * We always enable DPLL0 with the lowest link rate possible, but still
5703 * taking into account the VCO required to operate the eDP panel at the
5704 * desired frequency. The usual DP link rates operate with a VCO of
5705 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5706 * The modeset code is responsible for the selection of the exact link
5707 * rate later on, with the constraint of choosing a frequency that
5708 * works with required_vco.
5709 */
5710 val = I915_READ(DPLL_CTRL1);
5711
5712 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5713 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5714 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5715 if (required_vco == 8640)
5716 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5717 SKL_DPLL0);
5718 else
5719 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5720 SKL_DPLL0);
5721
5722 I915_WRITE(DPLL_CTRL1, val);
5723 POSTING_READ(DPLL_CTRL1);
5724
5725 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5726
5727 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5728 DRM_ERROR("DPLL0 not locked\n");
5729 }
5730
5731 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5732 {
5733 int ret;
5734 u32 val;
5735
5736 /* inform PCU we want to change CDCLK */
5737 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5738 mutex_lock(&dev_priv->rps.hw_lock);
5739 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5740 mutex_unlock(&dev_priv->rps.hw_lock);
5741
5742 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5743 }
5744
5745 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5746 {
5747 unsigned int i;
5748
5749 for (i = 0; i < 15; i++) {
5750 if (skl_cdclk_pcu_ready(dev_priv))
5751 return true;
5752 udelay(10);
5753 }
5754
5755 return false;
5756 }
5757
5758 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5759 {
5760 struct drm_device *dev = dev_priv->dev;
5761 u32 freq_select, pcu_ack;
5762
5763 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5764
5765 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5766 DRM_ERROR("failed to inform PCU about cdclk change\n");
5767 return;
5768 }
5769
5770 /* set CDCLK_CTL */
5771 switch(freq) {
5772 case 450000:
5773 case 432000:
5774 freq_select = CDCLK_FREQ_450_432;
5775 pcu_ack = 1;
5776 break;
5777 case 540000:
5778 freq_select = CDCLK_FREQ_540;
5779 pcu_ack = 2;
5780 break;
5781 case 308570:
5782 case 337500:
5783 default:
5784 freq_select = CDCLK_FREQ_337_308;
5785 pcu_ack = 0;
5786 break;
5787 case 617140:
5788 case 675000:
5789 freq_select = CDCLK_FREQ_675_617;
5790 pcu_ack = 3;
5791 break;
5792 }
5793
5794 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5795 POSTING_READ(CDCLK_CTL);
5796
5797 /* inform PCU of the change */
5798 mutex_lock(&dev_priv->rps.hw_lock);
5799 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5800 mutex_unlock(&dev_priv->rps.hw_lock);
5801
5802 intel_update_cdclk(dev);
5803 }
5804
5805 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5806 {
5807 /* disable DBUF power */
5808 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5809 POSTING_READ(DBUF_CTL);
5810
5811 udelay(10);
5812
5813 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5814 DRM_ERROR("DBuf power disable timeout\n");
5815
5816 /* disable DPLL0 */
5817 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5818 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5819 DRM_ERROR("Couldn't disable DPLL0\n");
5820 }
5821
5822 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5823 {
5824 unsigned int required_vco;
5825
5826 /* DPLL0 not enabled (happens on early BIOS versions) */
5827 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5828 /* enable DPLL0 */
5829 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5830 skl_dpll0_enable(dev_priv, required_vco);
5831 }
5832
5833 /* set CDCLK to the frequency the BIOS chose */
5834 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5835
5836 /* enable DBUF power */
5837 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5838 POSTING_READ(DBUF_CTL);
5839
5840 udelay(10);
5841
5842 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5843 DRM_ERROR("DBuf power enable timeout\n");
5844 }
5845
5846 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5847 {
5848 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5849 uint32_t cdctl = I915_READ(CDCLK_CTL);
5850 int freq = dev_priv->skl_boot_cdclk;
5851
5852 /*
5853 * check if the pre-os intialized the display
5854 * There is SWF18 scratchpad register defined which is set by the
5855 * pre-os which can be used by the OS drivers to check the status
5856 */
5857 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5858 goto sanitize;
5859
5860 /* Is PLL enabled and locked ? */
5861 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5862 goto sanitize;
5863
5864 /* DPLL okay; verify the cdclock
5865 *
5866 * Noticed in some instances that the freq selection is correct but
5867 * decimal part is programmed wrong from BIOS where pre-os does not
5868 * enable display. Verify the same as well.
5869 */
5870 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5871 /* All well; nothing to sanitize */
5872 return false;
5873 sanitize:
5874 /*
5875 * As of now initialize with max cdclk till
5876 * we get dynamic cdclk support
5877 * */
5878 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5879 skl_init_cdclk(dev_priv);
5880
5881 /* we did have to sanitize */
5882 return true;
5883 }
5884
5885 /* Adjust CDclk dividers to allow high res or save power if possible */
5886 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5887 {
5888 struct drm_i915_private *dev_priv = dev->dev_private;
5889 u32 val, cmd;
5890
5891 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5892 != dev_priv->cdclk_freq);
5893
5894 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5895 cmd = 2;
5896 else if (cdclk == 266667)
5897 cmd = 1;
5898 else
5899 cmd = 0;
5900
5901 mutex_lock(&dev_priv->rps.hw_lock);
5902 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5903 val &= ~DSPFREQGUAR_MASK;
5904 val |= (cmd << DSPFREQGUAR_SHIFT);
5905 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5906 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5907 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5908 50)) {
5909 DRM_ERROR("timed out waiting for CDclk change\n");
5910 }
5911 mutex_unlock(&dev_priv->rps.hw_lock);
5912
5913 mutex_lock(&dev_priv->sb_lock);
5914
5915 if (cdclk == 400000) {
5916 u32 divider;
5917
5918 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5919
5920 /* adjust cdclk divider */
5921 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5922 val &= ~CCK_FREQUENCY_VALUES;
5923 val |= divider;
5924 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5925
5926 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5927 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5928 50))
5929 DRM_ERROR("timed out waiting for CDclk change\n");
5930 }
5931
5932 /* adjust self-refresh exit latency value */
5933 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5934 val &= ~0x7f;
5935
5936 /*
5937 * For high bandwidth configs, we set a higher latency in the bunit
5938 * so that the core display fetch happens in time to avoid underruns.
5939 */
5940 if (cdclk == 400000)
5941 val |= 4500 / 250; /* 4.5 usec */
5942 else
5943 val |= 3000 / 250; /* 3.0 usec */
5944 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5945
5946 mutex_unlock(&dev_priv->sb_lock);
5947
5948 intel_update_cdclk(dev);
5949 }
5950
5951 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5952 {
5953 struct drm_i915_private *dev_priv = dev->dev_private;
5954 u32 val, cmd;
5955
5956 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5957 != dev_priv->cdclk_freq);
5958
5959 switch (cdclk) {
5960 case 333333:
5961 case 320000:
5962 case 266667:
5963 case 200000:
5964 break;
5965 default:
5966 MISSING_CASE(cdclk);
5967 return;
5968 }
5969
5970 /*
5971 * Specs are full of misinformation, but testing on actual
5972 * hardware has shown that we just need to write the desired
5973 * CCK divider into the Punit register.
5974 */
5975 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5976
5977 mutex_lock(&dev_priv->rps.hw_lock);
5978 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5979 val &= ~DSPFREQGUAR_MASK_CHV;
5980 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5981 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5982 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5983 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5984 50)) {
5985 DRM_ERROR("timed out waiting for CDclk change\n");
5986 }
5987 mutex_unlock(&dev_priv->rps.hw_lock);
5988
5989 intel_update_cdclk(dev);
5990 }
5991
5992 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5993 int max_pixclk)
5994 {
5995 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5996 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5997
5998 /*
5999 * Really only a few cases to deal with, as only 4 CDclks are supported:
6000 * 200MHz
6001 * 267MHz
6002 * 320/333MHz (depends on HPLL freq)
6003 * 400MHz (VLV only)
6004 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6005 * of the lower bin and adjust if needed.
6006 *
6007 * We seem to get an unstable or solid color picture at 200MHz.
6008 * Not sure what's wrong. For now use 200MHz only when all pipes
6009 * are off.
6010 */
6011 if (!IS_CHERRYVIEW(dev_priv) &&
6012 max_pixclk > freq_320*limit/100)
6013 return 400000;
6014 else if (max_pixclk > 266667*limit/100)
6015 return freq_320;
6016 else if (max_pixclk > 0)
6017 return 266667;
6018 else
6019 return 200000;
6020 }
6021
6022 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6023 int max_pixclk)
6024 {
6025 /*
6026 * FIXME:
6027 * - remove the guardband, it's not needed on BXT
6028 * - set 19.2MHz bypass frequency if there are no active pipes
6029 */
6030 if (max_pixclk > 576000*9/10)
6031 return 624000;
6032 else if (max_pixclk > 384000*9/10)
6033 return 576000;
6034 else if (max_pixclk > 288000*9/10)
6035 return 384000;
6036 else if (max_pixclk > 144000*9/10)
6037 return 288000;
6038 else
6039 return 144000;
6040 }
6041
6042 /* Compute the max pixel clock for new configuration. Uses atomic state if
6043 * that's non-NULL, look at current state otherwise. */
6044 static int intel_mode_max_pixclk(struct drm_device *dev,
6045 struct drm_atomic_state *state)
6046 {
6047 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6048 struct drm_i915_private *dev_priv = dev->dev_private;
6049 struct drm_crtc *crtc;
6050 struct drm_crtc_state *crtc_state;
6051 unsigned max_pixclk = 0, i;
6052 enum pipe pipe;
6053
6054 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6055 sizeof(intel_state->min_pixclk));
6056
6057 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6058 int pixclk = 0;
6059
6060 if (crtc_state->enable)
6061 pixclk = crtc_state->adjusted_mode.crtc_clock;
6062
6063 intel_state->min_pixclk[i] = pixclk;
6064 }
6065
6066 if (!intel_state->active_crtcs)
6067 return 0;
6068
6069 for_each_pipe(dev_priv, pipe)
6070 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6071
6072 return max_pixclk;
6073 }
6074
6075 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6076 {
6077 struct drm_device *dev = state->dev;
6078 struct drm_i915_private *dev_priv = dev->dev_private;
6079 int max_pixclk = intel_mode_max_pixclk(dev, state);
6080 struct intel_atomic_state *intel_state =
6081 to_intel_atomic_state(state);
6082
6083 if (max_pixclk < 0)
6084 return max_pixclk;
6085
6086 intel_state->cdclk = intel_state->dev_cdclk =
6087 valleyview_calc_cdclk(dev_priv, max_pixclk);
6088
6089 if (!intel_state->active_crtcs)
6090 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6091
6092 return 0;
6093 }
6094
6095 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6096 {
6097 struct drm_device *dev = state->dev;
6098 struct drm_i915_private *dev_priv = dev->dev_private;
6099 int max_pixclk = intel_mode_max_pixclk(dev, state);
6100 struct intel_atomic_state *intel_state =
6101 to_intel_atomic_state(state);
6102
6103 if (max_pixclk < 0)
6104 return max_pixclk;
6105
6106 intel_state->cdclk = intel_state->dev_cdclk =
6107 broxton_calc_cdclk(dev_priv, max_pixclk);
6108
6109 if (!intel_state->active_crtcs)
6110 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6111
6112 return 0;
6113 }
6114
6115 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6116 {
6117 unsigned int credits, default_credits;
6118
6119 if (IS_CHERRYVIEW(dev_priv))
6120 default_credits = PFI_CREDIT(12);
6121 else
6122 default_credits = PFI_CREDIT(8);
6123
6124 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6125 /* CHV suggested value is 31 or 63 */
6126 if (IS_CHERRYVIEW(dev_priv))
6127 credits = PFI_CREDIT_63;
6128 else
6129 credits = PFI_CREDIT(15);
6130 } else {
6131 credits = default_credits;
6132 }
6133
6134 /*
6135 * WA - write default credits before re-programming
6136 * FIXME: should we also set the resend bit here?
6137 */
6138 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6139 default_credits);
6140
6141 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6142 credits | PFI_CREDIT_RESEND);
6143
6144 /*
6145 * FIXME is this guaranteed to clear
6146 * immediately or should we poll for it?
6147 */
6148 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6149 }
6150
6151 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6152 {
6153 struct drm_device *dev = old_state->dev;
6154 struct drm_i915_private *dev_priv = dev->dev_private;
6155 struct intel_atomic_state *old_intel_state =
6156 to_intel_atomic_state(old_state);
6157 unsigned req_cdclk = old_intel_state->dev_cdclk;
6158
6159 /*
6160 * FIXME: We can end up here with all power domains off, yet
6161 * with a CDCLK frequency other than the minimum. To account
6162 * for this take the PIPE-A power domain, which covers the HW
6163 * blocks needed for the following programming. This can be
6164 * removed once it's guaranteed that we get here either with
6165 * the minimum CDCLK set, or the required power domains
6166 * enabled.
6167 */
6168 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6169
6170 if (IS_CHERRYVIEW(dev))
6171 cherryview_set_cdclk(dev, req_cdclk);
6172 else
6173 valleyview_set_cdclk(dev, req_cdclk);
6174
6175 vlv_program_pfi_credits(dev_priv);
6176
6177 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6178 }
6179
6180 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6181 {
6182 struct drm_device *dev = crtc->dev;
6183 struct drm_i915_private *dev_priv = to_i915(dev);
6184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6185 struct intel_encoder *encoder;
6186 int pipe = intel_crtc->pipe;
6187
6188 if (WARN_ON(intel_crtc->active))
6189 return;
6190
6191 if (intel_crtc->config->has_dp_encoder)
6192 intel_dp_set_m_n(intel_crtc, M1_N1);
6193
6194 intel_set_pipe_timings(intel_crtc);
6195
6196 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6197 struct drm_i915_private *dev_priv = dev->dev_private;
6198
6199 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6200 I915_WRITE(CHV_CANVAS(pipe), 0);
6201 }
6202
6203 i9xx_set_pipeconf(intel_crtc);
6204
6205 intel_crtc->active = true;
6206
6207 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6208
6209 for_each_encoder_on_crtc(dev, crtc, encoder)
6210 if (encoder->pre_pll_enable)
6211 encoder->pre_pll_enable(encoder);
6212
6213 if (!intel_crtc->config->has_dsi_encoder) {
6214 if (IS_CHERRYVIEW(dev)) {
6215 chv_prepare_pll(intel_crtc, intel_crtc->config);
6216 chv_enable_pll(intel_crtc, intel_crtc->config);
6217 } else {
6218 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6219 vlv_enable_pll(intel_crtc, intel_crtc->config);
6220 }
6221 }
6222
6223 for_each_encoder_on_crtc(dev, crtc, encoder)
6224 if (encoder->pre_enable)
6225 encoder->pre_enable(encoder);
6226
6227 i9xx_pfit_enable(intel_crtc);
6228
6229 intel_crtc_load_lut(crtc);
6230
6231 intel_enable_pipe(intel_crtc);
6232
6233 assert_vblank_disabled(crtc);
6234 drm_crtc_vblank_on(crtc);
6235
6236 for_each_encoder_on_crtc(dev, crtc, encoder)
6237 encoder->enable(encoder);
6238 }
6239
6240 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6241 {
6242 struct drm_device *dev = crtc->base.dev;
6243 struct drm_i915_private *dev_priv = dev->dev_private;
6244
6245 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6246 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6247 }
6248
6249 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6250 {
6251 struct drm_device *dev = crtc->dev;
6252 struct drm_i915_private *dev_priv = to_i915(dev);
6253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6254 struct intel_encoder *encoder;
6255 int pipe = intel_crtc->pipe;
6256
6257 if (WARN_ON(intel_crtc->active))
6258 return;
6259
6260 i9xx_set_pll_dividers(intel_crtc);
6261
6262 if (intel_crtc->config->has_dp_encoder)
6263 intel_dp_set_m_n(intel_crtc, M1_N1);
6264
6265 intel_set_pipe_timings(intel_crtc);
6266
6267 i9xx_set_pipeconf(intel_crtc);
6268
6269 intel_crtc->active = true;
6270
6271 if (!IS_GEN2(dev))
6272 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6273
6274 for_each_encoder_on_crtc(dev, crtc, encoder)
6275 if (encoder->pre_enable)
6276 encoder->pre_enable(encoder);
6277
6278 i9xx_enable_pll(intel_crtc);
6279
6280 i9xx_pfit_enable(intel_crtc);
6281
6282 intel_crtc_load_lut(crtc);
6283
6284 intel_update_watermarks(crtc);
6285 intel_enable_pipe(intel_crtc);
6286
6287 assert_vblank_disabled(crtc);
6288 drm_crtc_vblank_on(crtc);
6289
6290 for_each_encoder_on_crtc(dev, crtc, encoder)
6291 encoder->enable(encoder);
6292 }
6293
6294 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6295 {
6296 struct drm_device *dev = crtc->base.dev;
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298
6299 if (!crtc->config->gmch_pfit.control)
6300 return;
6301
6302 assert_pipe_disabled(dev_priv, crtc->pipe);
6303
6304 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6305 I915_READ(PFIT_CONTROL));
6306 I915_WRITE(PFIT_CONTROL, 0);
6307 }
6308
6309 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6310 {
6311 struct drm_device *dev = crtc->dev;
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6314 struct intel_encoder *encoder;
6315 int pipe = intel_crtc->pipe;
6316
6317 /*
6318 * On gen2 planes are double buffered but the pipe isn't, so we must
6319 * wait for planes to fully turn off before disabling the pipe.
6320 * We also need to wait on all gmch platforms because of the
6321 * self-refresh mode constraint explained above.
6322 */
6323 intel_wait_for_vblank(dev, pipe);
6324
6325 for_each_encoder_on_crtc(dev, crtc, encoder)
6326 encoder->disable(encoder);
6327
6328 drm_crtc_vblank_off(crtc);
6329 assert_vblank_disabled(crtc);
6330
6331 intel_disable_pipe(intel_crtc);
6332
6333 i9xx_pfit_disable(intel_crtc);
6334
6335 for_each_encoder_on_crtc(dev, crtc, encoder)
6336 if (encoder->post_disable)
6337 encoder->post_disable(encoder);
6338
6339 if (!intel_crtc->config->has_dsi_encoder) {
6340 if (IS_CHERRYVIEW(dev))
6341 chv_disable_pll(dev_priv, pipe);
6342 else if (IS_VALLEYVIEW(dev))
6343 vlv_disable_pll(dev_priv, pipe);
6344 else
6345 i9xx_disable_pll(intel_crtc);
6346 }
6347
6348 for_each_encoder_on_crtc(dev, crtc, encoder)
6349 if (encoder->post_pll_disable)
6350 encoder->post_pll_disable(encoder);
6351
6352 if (!IS_GEN2(dev))
6353 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6354 }
6355
6356 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6357 {
6358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6359 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6360 enum intel_display_power_domain domain;
6361 unsigned long domains;
6362
6363 if (!intel_crtc->active)
6364 return;
6365
6366 if (to_intel_plane_state(crtc->primary->state)->visible) {
6367 WARN_ON(intel_crtc->unpin_work);
6368
6369 intel_pre_disable_primary(crtc);
6370
6371 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6372 to_intel_plane_state(crtc->primary->state)->visible = false;
6373 }
6374
6375 dev_priv->display.crtc_disable(crtc);
6376 intel_crtc->active = false;
6377 intel_fbc_disable(intel_crtc);
6378 intel_update_watermarks(crtc);
6379 intel_disable_shared_dpll(intel_crtc);
6380
6381 domains = intel_crtc->enabled_power_domains;
6382 for_each_power_domain(domain, domains)
6383 intel_display_power_put(dev_priv, domain);
6384 intel_crtc->enabled_power_domains = 0;
6385
6386 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6387 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6388 }
6389
6390 /*
6391 * turn all crtc's off, but do not adjust state
6392 * This has to be paired with a call to intel_modeset_setup_hw_state.
6393 */
6394 int intel_display_suspend(struct drm_device *dev)
6395 {
6396 struct drm_mode_config *config = &dev->mode_config;
6397 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6398 struct drm_atomic_state *state;
6399 struct drm_crtc *crtc;
6400 unsigned crtc_mask = 0;
6401 int ret = 0;
6402
6403 if (WARN_ON(!ctx))
6404 return 0;
6405
6406 lockdep_assert_held(&ctx->ww_ctx);
6407 state = drm_atomic_state_alloc(dev);
6408 if (WARN_ON(!state))
6409 return -ENOMEM;
6410
6411 state->acquire_ctx = ctx;
6412 state->allow_modeset = true;
6413
6414 for_each_crtc(dev, crtc) {
6415 struct drm_crtc_state *crtc_state =
6416 drm_atomic_get_crtc_state(state, crtc);
6417
6418 ret = PTR_ERR_OR_ZERO(crtc_state);
6419 if (ret)
6420 goto free;
6421
6422 if (!crtc_state->active)
6423 continue;
6424
6425 crtc_state->active = false;
6426 crtc_mask |= 1 << drm_crtc_index(crtc);
6427 }
6428
6429 if (crtc_mask) {
6430 ret = drm_atomic_commit(state);
6431
6432 if (!ret) {
6433 for_each_crtc(dev, crtc)
6434 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6435 crtc->state->active = true;
6436
6437 return ret;
6438 }
6439 }
6440
6441 free:
6442 if (ret)
6443 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6444 drm_atomic_state_free(state);
6445 return ret;
6446 }
6447
6448 void intel_encoder_destroy(struct drm_encoder *encoder)
6449 {
6450 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6451
6452 drm_encoder_cleanup(encoder);
6453 kfree(intel_encoder);
6454 }
6455
6456 /* Cross check the actual hw state with our own modeset state tracking (and it's
6457 * internal consistency). */
6458 static void intel_connector_check_state(struct intel_connector *connector)
6459 {
6460 struct drm_crtc *crtc = connector->base.state->crtc;
6461
6462 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6463 connector->base.base.id,
6464 connector->base.name);
6465
6466 if (connector->get_hw_state(connector)) {
6467 struct intel_encoder *encoder = connector->encoder;
6468 struct drm_connector_state *conn_state = connector->base.state;
6469
6470 I915_STATE_WARN(!crtc,
6471 "connector enabled without attached crtc\n");
6472
6473 if (!crtc)
6474 return;
6475
6476 I915_STATE_WARN(!crtc->state->active,
6477 "connector is active, but attached crtc isn't\n");
6478
6479 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6480 return;
6481
6482 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6483 "atomic encoder doesn't match attached encoder\n");
6484
6485 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6486 "attached encoder crtc differs from connector crtc\n");
6487 } else {
6488 I915_STATE_WARN(crtc && crtc->state->active,
6489 "attached crtc is active, but connector isn't\n");
6490 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6491 "best encoder set without crtc!\n");
6492 }
6493 }
6494
6495 int intel_connector_init(struct intel_connector *connector)
6496 {
6497 drm_atomic_helper_connector_reset(&connector->base);
6498
6499 if (!connector->base.state)
6500 return -ENOMEM;
6501
6502 return 0;
6503 }
6504
6505 struct intel_connector *intel_connector_alloc(void)
6506 {
6507 struct intel_connector *connector;
6508
6509 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6510 if (!connector)
6511 return NULL;
6512
6513 if (intel_connector_init(connector) < 0) {
6514 kfree(connector);
6515 return NULL;
6516 }
6517
6518 return connector;
6519 }
6520
6521 /* Simple connector->get_hw_state implementation for encoders that support only
6522 * one connector and no cloning and hence the encoder state determines the state
6523 * of the connector. */
6524 bool intel_connector_get_hw_state(struct intel_connector *connector)
6525 {
6526 enum pipe pipe = 0;
6527 struct intel_encoder *encoder = connector->encoder;
6528
6529 return encoder->get_hw_state(encoder, &pipe);
6530 }
6531
6532 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6533 {
6534 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6535 return crtc_state->fdi_lanes;
6536
6537 return 0;
6538 }
6539
6540 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6541 struct intel_crtc_state *pipe_config)
6542 {
6543 struct drm_atomic_state *state = pipe_config->base.state;
6544 struct intel_crtc *other_crtc;
6545 struct intel_crtc_state *other_crtc_state;
6546
6547 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6548 pipe_name(pipe), pipe_config->fdi_lanes);
6549 if (pipe_config->fdi_lanes > 4) {
6550 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6551 pipe_name(pipe), pipe_config->fdi_lanes);
6552 return -EINVAL;
6553 }
6554
6555 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6556 if (pipe_config->fdi_lanes > 2) {
6557 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6558 pipe_config->fdi_lanes);
6559 return -EINVAL;
6560 } else {
6561 return 0;
6562 }
6563 }
6564
6565 if (INTEL_INFO(dev)->num_pipes == 2)
6566 return 0;
6567
6568 /* Ivybridge 3 pipe is really complicated */
6569 switch (pipe) {
6570 case PIPE_A:
6571 return 0;
6572 case PIPE_B:
6573 if (pipe_config->fdi_lanes <= 2)
6574 return 0;
6575
6576 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6577 other_crtc_state =
6578 intel_atomic_get_crtc_state(state, other_crtc);
6579 if (IS_ERR(other_crtc_state))
6580 return PTR_ERR(other_crtc_state);
6581
6582 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6583 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6584 pipe_name(pipe), pipe_config->fdi_lanes);
6585 return -EINVAL;
6586 }
6587 return 0;
6588 case PIPE_C:
6589 if (pipe_config->fdi_lanes > 2) {
6590 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6591 pipe_name(pipe), pipe_config->fdi_lanes);
6592 return -EINVAL;
6593 }
6594
6595 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6596 other_crtc_state =
6597 intel_atomic_get_crtc_state(state, other_crtc);
6598 if (IS_ERR(other_crtc_state))
6599 return PTR_ERR(other_crtc_state);
6600
6601 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6602 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6603 return -EINVAL;
6604 }
6605 return 0;
6606 default:
6607 BUG();
6608 }
6609 }
6610
6611 #define RETRY 1
6612 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6613 struct intel_crtc_state *pipe_config)
6614 {
6615 struct drm_device *dev = intel_crtc->base.dev;
6616 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6617 int lane, link_bw, fdi_dotclock, ret;
6618 bool needs_recompute = false;
6619
6620 retry:
6621 /* FDI is a binary signal running at ~2.7GHz, encoding
6622 * each output octet as 10 bits. The actual frequency
6623 * is stored as a divider into a 100MHz clock, and the
6624 * mode pixel clock is stored in units of 1KHz.
6625 * Hence the bw of each lane in terms of the mode signal
6626 * is:
6627 */
6628 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6629
6630 fdi_dotclock = adjusted_mode->crtc_clock;
6631
6632 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6633 pipe_config->pipe_bpp);
6634
6635 pipe_config->fdi_lanes = lane;
6636
6637 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6638 link_bw, &pipe_config->fdi_m_n);
6639
6640 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6641 intel_crtc->pipe, pipe_config);
6642 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6643 pipe_config->pipe_bpp -= 2*3;
6644 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6645 pipe_config->pipe_bpp);
6646 needs_recompute = true;
6647 pipe_config->bw_constrained = true;
6648
6649 goto retry;
6650 }
6651
6652 if (needs_recompute)
6653 return RETRY;
6654
6655 return ret;
6656 }
6657
6658 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6659 struct intel_crtc_state *pipe_config)
6660 {
6661 if (pipe_config->pipe_bpp > 24)
6662 return false;
6663
6664 /* HSW can handle pixel rate up to cdclk? */
6665 if (IS_HASWELL(dev_priv->dev))
6666 return true;
6667
6668 /*
6669 * We compare against max which means we must take
6670 * the increased cdclk requirement into account when
6671 * calculating the new cdclk.
6672 *
6673 * Should measure whether using a lower cdclk w/o IPS
6674 */
6675 return ilk_pipe_pixel_rate(pipe_config) <=
6676 dev_priv->max_cdclk_freq * 95 / 100;
6677 }
6678
6679 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6680 struct intel_crtc_state *pipe_config)
6681 {
6682 struct drm_device *dev = crtc->base.dev;
6683 struct drm_i915_private *dev_priv = dev->dev_private;
6684
6685 pipe_config->ips_enabled = i915.enable_ips &&
6686 hsw_crtc_supports_ips(crtc) &&
6687 pipe_config_supports_ips(dev_priv, pipe_config);
6688 }
6689
6690 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6691 {
6692 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6693
6694 /* GDG double wide on either pipe, otherwise pipe A only */
6695 return INTEL_INFO(dev_priv)->gen < 4 &&
6696 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6697 }
6698
6699 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6700 struct intel_crtc_state *pipe_config)
6701 {
6702 struct drm_device *dev = crtc->base.dev;
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6705
6706 /* FIXME should check pixel clock limits on all platforms */
6707 if (INTEL_INFO(dev)->gen < 4) {
6708 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6709
6710 /*
6711 * Enable double wide mode when the dot clock
6712 * is > 90% of the (display) core speed.
6713 */
6714 if (intel_crtc_supports_double_wide(crtc) &&
6715 adjusted_mode->crtc_clock > clock_limit) {
6716 clock_limit *= 2;
6717 pipe_config->double_wide = true;
6718 }
6719
6720 if (adjusted_mode->crtc_clock > clock_limit) {
6721 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6722 adjusted_mode->crtc_clock, clock_limit,
6723 yesno(pipe_config->double_wide));
6724 return -EINVAL;
6725 }
6726 }
6727
6728 /*
6729 * Pipe horizontal size must be even in:
6730 * - DVO ganged mode
6731 * - LVDS dual channel mode
6732 * - Double wide pipe
6733 */
6734 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6735 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6736 pipe_config->pipe_src_w &= ~1;
6737
6738 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6739 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6740 */
6741 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6742 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6743 return -EINVAL;
6744
6745 if (HAS_IPS(dev))
6746 hsw_compute_ips_config(crtc, pipe_config);
6747
6748 if (pipe_config->has_pch_encoder)
6749 return ironlake_fdi_compute_config(crtc, pipe_config);
6750
6751 return 0;
6752 }
6753
6754 static int skylake_get_display_clock_speed(struct drm_device *dev)
6755 {
6756 struct drm_i915_private *dev_priv = to_i915(dev);
6757 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6758 uint32_t cdctl = I915_READ(CDCLK_CTL);
6759 uint32_t linkrate;
6760
6761 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6762 return 24000; /* 24MHz is the cd freq with NSSC ref */
6763
6764 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6765 return 540000;
6766
6767 linkrate = (I915_READ(DPLL_CTRL1) &
6768 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6769
6770 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6771 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6772 /* vco 8640 */
6773 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6774 case CDCLK_FREQ_450_432:
6775 return 432000;
6776 case CDCLK_FREQ_337_308:
6777 return 308570;
6778 case CDCLK_FREQ_675_617:
6779 return 617140;
6780 default:
6781 WARN(1, "Unknown cd freq selection\n");
6782 }
6783 } else {
6784 /* vco 8100 */
6785 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6786 case CDCLK_FREQ_450_432:
6787 return 450000;
6788 case CDCLK_FREQ_337_308:
6789 return 337500;
6790 case CDCLK_FREQ_675_617:
6791 return 675000;
6792 default:
6793 WARN(1, "Unknown cd freq selection\n");
6794 }
6795 }
6796
6797 /* error case, do as if DPLL0 isn't enabled */
6798 return 24000;
6799 }
6800
6801 static int broxton_get_display_clock_speed(struct drm_device *dev)
6802 {
6803 struct drm_i915_private *dev_priv = to_i915(dev);
6804 uint32_t cdctl = I915_READ(CDCLK_CTL);
6805 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6806 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6807 int cdclk;
6808
6809 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6810 return 19200;
6811
6812 cdclk = 19200 * pll_ratio / 2;
6813
6814 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6815 case BXT_CDCLK_CD2X_DIV_SEL_1:
6816 return cdclk; /* 576MHz or 624MHz */
6817 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6818 return cdclk * 2 / 3; /* 384MHz */
6819 case BXT_CDCLK_CD2X_DIV_SEL_2:
6820 return cdclk / 2; /* 288MHz */
6821 case BXT_CDCLK_CD2X_DIV_SEL_4:
6822 return cdclk / 4; /* 144MHz */
6823 }
6824
6825 /* error case, do as if DE PLL isn't enabled */
6826 return 19200;
6827 }
6828
6829 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6830 {
6831 struct drm_i915_private *dev_priv = dev->dev_private;
6832 uint32_t lcpll = I915_READ(LCPLL_CTL);
6833 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6834
6835 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6836 return 800000;
6837 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6838 return 450000;
6839 else if (freq == LCPLL_CLK_FREQ_450)
6840 return 450000;
6841 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6842 return 540000;
6843 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6844 return 337500;
6845 else
6846 return 675000;
6847 }
6848
6849 static int haswell_get_display_clock_speed(struct drm_device *dev)
6850 {
6851 struct drm_i915_private *dev_priv = dev->dev_private;
6852 uint32_t lcpll = I915_READ(LCPLL_CTL);
6853 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6854
6855 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6856 return 800000;
6857 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6858 return 450000;
6859 else if (freq == LCPLL_CLK_FREQ_450)
6860 return 450000;
6861 else if (IS_HSW_ULT(dev))
6862 return 337500;
6863 else
6864 return 540000;
6865 }
6866
6867 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6868 {
6869 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6870 CCK_DISPLAY_CLOCK_CONTROL);
6871 }
6872
6873 static int ilk_get_display_clock_speed(struct drm_device *dev)
6874 {
6875 return 450000;
6876 }
6877
6878 static int i945_get_display_clock_speed(struct drm_device *dev)
6879 {
6880 return 400000;
6881 }
6882
6883 static int i915_get_display_clock_speed(struct drm_device *dev)
6884 {
6885 return 333333;
6886 }
6887
6888 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6889 {
6890 return 200000;
6891 }
6892
6893 static int pnv_get_display_clock_speed(struct drm_device *dev)
6894 {
6895 u16 gcfgc = 0;
6896
6897 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6898
6899 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6900 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6901 return 266667;
6902 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6903 return 333333;
6904 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6905 return 444444;
6906 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6907 return 200000;
6908 default:
6909 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6910 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6911 return 133333;
6912 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6913 return 166667;
6914 }
6915 }
6916
6917 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6918 {
6919 u16 gcfgc = 0;
6920
6921 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6922
6923 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6924 return 133333;
6925 else {
6926 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6927 case GC_DISPLAY_CLOCK_333_MHZ:
6928 return 333333;
6929 default:
6930 case GC_DISPLAY_CLOCK_190_200_MHZ:
6931 return 190000;
6932 }
6933 }
6934 }
6935
6936 static int i865_get_display_clock_speed(struct drm_device *dev)
6937 {
6938 return 266667;
6939 }
6940
6941 static int i85x_get_display_clock_speed(struct drm_device *dev)
6942 {
6943 u16 hpllcc = 0;
6944
6945 /*
6946 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6947 * encoding is different :(
6948 * FIXME is this the right way to detect 852GM/852GMV?
6949 */
6950 if (dev->pdev->revision == 0x1)
6951 return 133333;
6952
6953 pci_bus_read_config_word(dev->pdev->bus,
6954 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6955
6956 /* Assume that the hardware is in the high speed state. This
6957 * should be the default.
6958 */
6959 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6960 case GC_CLOCK_133_200:
6961 case GC_CLOCK_133_200_2:
6962 case GC_CLOCK_100_200:
6963 return 200000;
6964 case GC_CLOCK_166_250:
6965 return 250000;
6966 case GC_CLOCK_100_133:
6967 return 133333;
6968 case GC_CLOCK_133_266:
6969 case GC_CLOCK_133_266_2:
6970 case GC_CLOCK_166_266:
6971 return 266667;
6972 }
6973
6974 /* Shouldn't happen */
6975 return 0;
6976 }
6977
6978 static int i830_get_display_clock_speed(struct drm_device *dev)
6979 {
6980 return 133333;
6981 }
6982
6983 static unsigned int intel_hpll_vco(struct drm_device *dev)
6984 {
6985 struct drm_i915_private *dev_priv = dev->dev_private;
6986 static const unsigned int blb_vco[8] = {
6987 [0] = 3200000,
6988 [1] = 4000000,
6989 [2] = 5333333,
6990 [3] = 4800000,
6991 [4] = 6400000,
6992 };
6993 static const unsigned int pnv_vco[8] = {
6994 [0] = 3200000,
6995 [1] = 4000000,
6996 [2] = 5333333,
6997 [3] = 4800000,
6998 [4] = 2666667,
6999 };
7000 static const unsigned int cl_vco[8] = {
7001 [0] = 3200000,
7002 [1] = 4000000,
7003 [2] = 5333333,
7004 [3] = 6400000,
7005 [4] = 3333333,
7006 [5] = 3566667,
7007 [6] = 4266667,
7008 };
7009 static const unsigned int elk_vco[8] = {
7010 [0] = 3200000,
7011 [1] = 4000000,
7012 [2] = 5333333,
7013 [3] = 4800000,
7014 };
7015 static const unsigned int ctg_vco[8] = {
7016 [0] = 3200000,
7017 [1] = 4000000,
7018 [2] = 5333333,
7019 [3] = 6400000,
7020 [4] = 2666667,
7021 [5] = 4266667,
7022 };
7023 const unsigned int *vco_table;
7024 unsigned int vco;
7025 uint8_t tmp = 0;
7026
7027 /* FIXME other chipsets? */
7028 if (IS_GM45(dev))
7029 vco_table = ctg_vco;
7030 else if (IS_G4X(dev))
7031 vco_table = elk_vco;
7032 else if (IS_CRESTLINE(dev))
7033 vco_table = cl_vco;
7034 else if (IS_PINEVIEW(dev))
7035 vco_table = pnv_vco;
7036 else if (IS_G33(dev))
7037 vco_table = blb_vco;
7038 else
7039 return 0;
7040
7041 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7042
7043 vco = vco_table[tmp & 0x7];
7044 if (vco == 0)
7045 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7046 else
7047 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7048
7049 return vco;
7050 }
7051
7052 static int gm45_get_display_clock_speed(struct drm_device *dev)
7053 {
7054 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7055 uint16_t tmp = 0;
7056
7057 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7058
7059 cdclk_sel = (tmp >> 12) & 0x1;
7060
7061 switch (vco) {
7062 case 2666667:
7063 case 4000000:
7064 case 5333333:
7065 return cdclk_sel ? 333333 : 222222;
7066 case 3200000:
7067 return cdclk_sel ? 320000 : 228571;
7068 default:
7069 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7070 return 222222;
7071 }
7072 }
7073
7074 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7075 {
7076 static const uint8_t div_3200[] = { 16, 10, 8 };
7077 static const uint8_t div_4000[] = { 20, 12, 10 };
7078 static const uint8_t div_5333[] = { 24, 16, 14 };
7079 const uint8_t *div_table;
7080 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7081 uint16_t tmp = 0;
7082
7083 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7084
7085 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7086
7087 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7088 goto fail;
7089
7090 switch (vco) {
7091 case 3200000:
7092 div_table = div_3200;
7093 break;
7094 case 4000000:
7095 div_table = div_4000;
7096 break;
7097 case 5333333:
7098 div_table = div_5333;
7099 break;
7100 default:
7101 goto fail;
7102 }
7103
7104 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7105
7106 fail:
7107 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7108 return 200000;
7109 }
7110
7111 static int g33_get_display_clock_speed(struct drm_device *dev)
7112 {
7113 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7114 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7115 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7116 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7117 const uint8_t *div_table;
7118 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7119 uint16_t tmp = 0;
7120
7121 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7122
7123 cdclk_sel = (tmp >> 4) & 0x7;
7124
7125 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7126 goto fail;
7127
7128 switch (vco) {
7129 case 3200000:
7130 div_table = div_3200;
7131 break;
7132 case 4000000:
7133 div_table = div_4000;
7134 break;
7135 case 4800000:
7136 div_table = div_4800;
7137 break;
7138 case 5333333:
7139 div_table = div_5333;
7140 break;
7141 default:
7142 goto fail;
7143 }
7144
7145 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7146
7147 fail:
7148 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7149 return 190476;
7150 }
7151
7152 static void
7153 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7154 {
7155 while (*num > DATA_LINK_M_N_MASK ||
7156 *den > DATA_LINK_M_N_MASK) {
7157 *num >>= 1;
7158 *den >>= 1;
7159 }
7160 }
7161
7162 static void compute_m_n(unsigned int m, unsigned int n,
7163 uint32_t *ret_m, uint32_t *ret_n)
7164 {
7165 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7166 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7167 intel_reduce_m_n_ratio(ret_m, ret_n);
7168 }
7169
7170 void
7171 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7172 int pixel_clock, int link_clock,
7173 struct intel_link_m_n *m_n)
7174 {
7175 m_n->tu = 64;
7176
7177 compute_m_n(bits_per_pixel * pixel_clock,
7178 link_clock * nlanes * 8,
7179 &m_n->gmch_m, &m_n->gmch_n);
7180
7181 compute_m_n(pixel_clock, link_clock,
7182 &m_n->link_m, &m_n->link_n);
7183 }
7184
7185 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7186 {
7187 if (i915.panel_use_ssc >= 0)
7188 return i915.panel_use_ssc != 0;
7189 return dev_priv->vbt.lvds_use_ssc
7190 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7191 }
7192
7193 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7194 int num_connectors)
7195 {
7196 struct drm_device *dev = crtc_state->base.crtc->dev;
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 int refclk;
7199
7200 WARN_ON(!crtc_state->base.state);
7201
7202 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7203 refclk = 100000;
7204 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7205 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7206 refclk = dev_priv->vbt.lvds_ssc_freq;
7207 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7208 } else if (!IS_GEN2(dev)) {
7209 refclk = 96000;
7210 } else {
7211 refclk = 48000;
7212 }
7213
7214 return refclk;
7215 }
7216
7217 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7218 {
7219 return (1 << dpll->n) << 16 | dpll->m2;
7220 }
7221
7222 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7223 {
7224 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7225 }
7226
7227 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7228 struct intel_crtc_state *crtc_state,
7229 intel_clock_t *reduced_clock)
7230 {
7231 struct drm_device *dev = crtc->base.dev;
7232 u32 fp, fp2 = 0;
7233
7234 if (IS_PINEVIEW(dev)) {
7235 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7236 if (reduced_clock)
7237 fp2 = pnv_dpll_compute_fp(reduced_clock);
7238 } else {
7239 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7240 if (reduced_clock)
7241 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7242 }
7243
7244 crtc_state->dpll_hw_state.fp0 = fp;
7245
7246 crtc->lowfreq_avail = false;
7247 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7248 reduced_clock) {
7249 crtc_state->dpll_hw_state.fp1 = fp2;
7250 crtc->lowfreq_avail = true;
7251 } else {
7252 crtc_state->dpll_hw_state.fp1 = fp;
7253 }
7254 }
7255
7256 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7257 pipe)
7258 {
7259 u32 reg_val;
7260
7261 /*
7262 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7263 * and set it to a reasonable value instead.
7264 */
7265 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7266 reg_val &= 0xffffff00;
7267 reg_val |= 0x00000030;
7268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7269
7270 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7271 reg_val &= 0x8cffffff;
7272 reg_val = 0x8c000000;
7273 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7274
7275 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7276 reg_val &= 0xffffff00;
7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7278
7279 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7280 reg_val &= 0x00ffffff;
7281 reg_val |= 0xb0000000;
7282 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7283 }
7284
7285 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7286 struct intel_link_m_n *m_n)
7287 {
7288 struct drm_device *dev = crtc->base.dev;
7289 struct drm_i915_private *dev_priv = dev->dev_private;
7290 int pipe = crtc->pipe;
7291
7292 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7293 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7294 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7295 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7296 }
7297
7298 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7299 struct intel_link_m_n *m_n,
7300 struct intel_link_m_n *m2_n2)
7301 {
7302 struct drm_device *dev = crtc->base.dev;
7303 struct drm_i915_private *dev_priv = dev->dev_private;
7304 int pipe = crtc->pipe;
7305 enum transcoder transcoder = crtc->config->cpu_transcoder;
7306
7307 if (INTEL_INFO(dev)->gen >= 5) {
7308 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7309 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7310 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7311 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7312 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7313 * for gen < 8) and if DRRS is supported (to make sure the
7314 * registers are not unnecessarily accessed).
7315 */
7316 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7317 crtc->config->has_drrs) {
7318 I915_WRITE(PIPE_DATA_M2(transcoder),
7319 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7320 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7321 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7322 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7323 }
7324 } else {
7325 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7326 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7327 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7328 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7329 }
7330 }
7331
7332 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7333 {
7334 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7335
7336 if (m_n == M1_N1) {
7337 dp_m_n = &crtc->config->dp_m_n;
7338 dp_m2_n2 = &crtc->config->dp_m2_n2;
7339 } else if (m_n == M2_N2) {
7340
7341 /*
7342 * M2_N2 registers are not supported. Hence m2_n2 divider value
7343 * needs to be programmed into M1_N1.
7344 */
7345 dp_m_n = &crtc->config->dp_m2_n2;
7346 } else {
7347 DRM_ERROR("Unsupported divider value\n");
7348 return;
7349 }
7350
7351 if (crtc->config->has_pch_encoder)
7352 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7353 else
7354 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7355 }
7356
7357 static void vlv_compute_dpll(struct intel_crtc *crtc,
7358 struct intel_crtc_state *pipe_config)
7359 {
7360 u32 dpll, dpll_md;
7361
7362 /*
7363 * Enable DPIO clock input. We should never disable the reference
7364 * clock for pipe B, since VGA hotplug / manual detection depends
7365 * on it.
7366 */
7367 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7368 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7369 /* We should never disable this, set it here for state tracking */
7370 if (crtc->pipe == PIPE_B)
7371 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7372 dpll |= DPLL_VCO_ENABLE;
7373 pipe_config->dpll_hw_state.dpll = dpll;
7374
7375 dpll_md = (pipe_config->pixel_multiplier - 1)
7376 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7377 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7378 }
7379
7380 static void vlv_prepare_pll(struct intel_crtc *crtc,
7381 const struct intel_crtc_state *pipe_config)
7382 {
7383 struct drm_device *dev = crtc->base.dev;
7384 struct drm_i915_private *dev_priv = dev->dev_private;
7385 int pipe = crtc->pipe;
7386 u32 mdiv;
7387 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7388 u32 coreclk, reg_val;
7389
7390 mutex_lock(&dev_priv->sb_lock);
7391
7392 bestn = pipe_config->dpll.n;
7393 bestm1 = pipe_config->dpll.m1;
7394 bestm2 = pipe_config->dpll.m2;
7395 bestp1 = pipe_config->dpll.p1;
7396 bestp2 = pipe_config->dpll.p2;
7397
7398 /* See eDP HDMI DPIO driver vbios notes doc */
7399
7400 /* PLL B needs special handling */
7401 if (pipe == PIPE_B)
7402 vlv_pllb_recal_opamp(dev_priv, pipe);
7403
7404 /* Set up Tx target for periodic Rcomp update */
7405 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7406
7407 /* Disable target IRef on PLL */
7408 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7409 reg_val &= 0x00ffffff;
7410 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7411
7412 /* Disable fast lock */
7413 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7414
7415 /* Set idtafcrecal before PLL is enabled */
7416 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7417 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7418 mdiv |= ((bestn << DPIO_N_SHIFT));
7419 mdiv |= (1 << DPIO_K_SHIFT);
7420
7421 /*
7422 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7423 * but we don't support that).
7424 * Note: don't use the DAC post divider as it seems unstable.
7425 */
7426 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7427 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7428
7429 mdiv |= DPIO_ENABLE_CALIBRATION;
7430 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7431
7432 /* Set HBR and RBR LPF coefficients */
7433 if (pipe_config->port_clock == 162000 ||
7434 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7435 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7436 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7437 0x009f0003);
7438 else
7439 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7440 0x00d0000f);
7441
7442 if (pipe_config->has_dp_encoder) {
7443 /* Use SSC source */
7444 if (pipe == PIPE_A)
7445 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7446 0x0df40000);
7447 else
7448 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7449 0x0df70000);
7450 } else { /* HDMI or VGA */
7451 /* Use bend source */
7452 if (pipe == PIPE_A)
7453 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7454 0x0df70000);
7455 else
7456 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7457 0x0df40000);
7458 }
7459
7460 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7461 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7462 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7463 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7464 coreclk |= 0x01000000;
7465 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7466
7467 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7468 mutex_unlock(&dev_priv->sb_lock);
7469 }
7470
7471 static void chv_compute_dpll(struct intel_crtc *crtc,
7472 struct intel_crtc_state *pipe_config)
7473 {
7474 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7475 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7476 DPLL_VCO_ENABLE;
7477 if (crtc->pipe != PIPE_A)
7478 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7479
7480 pipe_config->dpll_hw_state.dpll_md =
7481 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7482 }
7483
7484 static void chv_prepare_pll(struct intel_crtc *crtc,
7485 const struct intel_crtc_state *pipe_config)
7486 {
7487 struct drm_device *dev = crtc->base.dev;
7488 struct drm_i915_private *dev_priv = dev->dev_private;
7489 int pipe = crtc->pipe;
7490 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7491 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7492 u32 loopfilter, tribuf_calcntr;
7493 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7494 u32 dpio_val;
7495 int vco;
7496
7497 bestn = pipe_config->dpll.n;
7498 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7499 bestm1 = pipe_config->dpll.m1;
7500 bestm2 = pipe_config->dpll.m2 >> 22;
7501 bestp1 = pipe_config->dpll.p1;
7502 bestp2 = pipe_config->dpll.p2;
7503 vco = pipe_config->dpll.vco;
7504 dpio_val = 0;
7505 loopfilter = 0;
7506
7507 /*
7508 * Enable Refclk and SSC
7509 */
7510 I915_WRITE(dpll_reg,
7511 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7512
7513 mutex_lock(&dev_priv->sb_lock);
7514
7515 /* p1 and p2 divider */
7516 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7517 5 << DPIO_CHV_S1_DIV_SHIFT |
7518 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7519 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7520 1 << DPIO_CHV_K_DIV_SHIFT);
7521
7522 /* Feedback post-divider - m2 */
7523 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7524
7525 /* Feedback refclk divider - n and m1 */
7526 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7527 DPIO_CHV_M1_DIV_BY_2 |
7528 1 << DPIO_CHV_N_DIV_SHIFT);
7529
7530 /* M2 fraction division */
7531 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7532
7533 /* M2 fraction division enable */
7534 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7535 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7536 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7537 if (bestm2_frac)
7538 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7539 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7540
7541 /* Program digital lock detect threshold */
7542 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7543 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7544 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7545 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7546 if (!bestm2_frac)
7547 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7548 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7549
7550 /* Loop filter */
7551 if (vco == 5400000) {
7552 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7553 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7554 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7555 tribuf_calcntr = 0x9;
7556 } else if (vco <= 6200000) {
7557 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7558 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7559 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7560 tribuf_calcntr = 0x9;
7561 } else if (vco <= 6480000) {
7562 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7563 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7564 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7565 tribuf_calcntr = 0x8;
7566 } else {
7567 /* Not supported. Apply the same limits as in the max case */
7568 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7569 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7570 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7571 tribuf_calcntr = 0;
7572 }
7573 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7574
7575 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7576 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7577 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7578 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7579
7580 /* AFC Recal */
7581 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7582 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7583 DPIO_AFC_RECAL);
7584
7585 mutex_unlock(&dev_priv->sb_lock);
7586 }
7587
7588 /**
7589 * vlv_force_pll_on - forcibly enable just the PLL
7590 * @dev_priv: i915 private structure
7591 * @pipe: pipe PLL to enable
7592 * @dpll: PLL configuration
7593 *
7594 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7595 * in cases where we need the PLL enabled even when @pipe is not going to
7596 * be enabled.
7597 */
7598 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7599 const struct dpll *dpll)
7600 {
7601 struct intel_crtc *crtc =
7602 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7603 struct intel_crtc_state *pipe_config;
7604
7605 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7606 if (!pipe_config)
7607 return -ENOMEM;
7608
7609 pipe_config->base.crtc = &crtc->base;
7610 pipe_config->pixel_multiplier = 1;
7611 pipe_config->dpll = *dpll;
7612
7613 if (IS_CHERRYVIEW(dev)) {
7614 chv_compute_dpll(crtc, pipe_config);
7615 chv_prepare_pll(crtc, pipe_config);
7616 chv_enable_pll(crtc, pipe_config);
7617 } else {
7618 vlv_compute_dpll(crtc, pipe_config);
7619 vlv_prepare_pll(crtc, pipe_config);
7620 vlv_enable_pll(crtc, pipe_config);
7621 }
7622
7623 kfree(pipe_config);
7624
7625 return 0;
7626 }
7627
7628 /**
7629 * vlv_force_pll_off - forcibly disable just the PLL
7630 * @dev_priv: i915 private structure
7631 * @pipe: pipe PLL to disable
7632 *
7633 * Disable the PLL for @pipe. To be used in cases where we need
7634 * the PLL enabled even when @pipe is not going to be enabled.
7635 */
7636 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7637 {
7638 if (IS_CHERRYVIEW(dev))
7639 chv_disable_pll(to_i915(dev), pipe);
7640 else
7641 vlv_disable_pll(to_i915(dev), pipe);
7642 }
7643
7644 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7645 struct intel_crtc_state *crtc_state,
7646 intel_clock_t *reduced_clock,
7647 int num_connectors)
7648 {
7649 struct drm_device *dev = crtc->base.dev;
7650 struct drm_i915_private *dev_priv = dev->dev_private;
7651 u32 dpll;
7652 bool is_sdvo;
7653 struct dpll *clock = &crtc_state->dpll;
7654
7655 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7656
7657 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7658 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7659
7660 dpll = DPLL_VGA_MODE_DIS;
7661
7662 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7663 dpll |= DPLLB_MODE_LVDS;
7664 else
7665 dpll |= DPLLB_MODE_DAC_SERIAL;
7666
7667 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7668 dpll |= (crtc_state->pixel_multiplier - 1)
7669 << SDVO_MULTIPLIER_SHIFT_HIRES;
7670 }
7671
7672 if (is_sdvo)
7673 dpll |= DPLL_SDVO_HIGH_SPEED;
7674
7675 if (crtc_state->has_dp_encoder)
7676 dpll |= DPLL_SDVO_HIGH_SPEED;
7677
7678 /* compute bitmask from p1 value */
7679 if (IS_PINEVIEW(dev))
7680 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7681 else {
7682 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7683 if (IS_G4X(dev) && reduced_clock)
7684 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7685 }
7686 switch (clock->p2) {
7687 case 5:
7688 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7689 break;
7690 case 7:
7691 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7692 break;
7693 case 10:
7694 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7695 break;
7696 case 14:
7697 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7698 break;
7699 }
7700 if (INTEL_INFO(dev)->gen >= 4)
7701 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7702
7703 if (crtc_state->sdvo_tv_clock)
7704 dpll |= PLL_REF_INPUT_TVCLKINBC;
7705 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7706 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7707 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7708 else
7709 dpll |= PLL_REF_INPUT_DREFCLK;
7710
7711 dpll |= DPLL_VCO_ENABLE;
7712 crtc_state->dpll_hw_state.dpll = dpll;
7713
7714 if (INTEL_INFO(dev)->gen >= 4) {
7715 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7716 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7717 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7718 }
7719 }
7720
7721 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7722 struct intel_crtc_state *crtc_state,
7723 intel_clock_t *reduced_clock,
7724 int num_connectors)
7725 {
7726 struct drm_device *dev = crtc->base.dev;
7727 struct drm_i915_private *dev_priv = dev->dev_private;
7728 u32 dpll;
7729 struct dpll *clock = &crtc_state->dpll;
7730
7731 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7732
7733 dpll = DPLL_VGA_MODE_DIS;
7734
7735 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7736 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7737 } else {
7738 if (clock->p1 == 2)
7739 dpll |= PLL_P1_DIVIDE_BY_TWO;
7740 else
7741 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7742 if (clock->p2 == 4)
7743 dpll |= PLL_P2_DIVIDE_BY_4;
7744 }
7745
7746 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7747 dpll |= DPLL_DVO_2X_MODE;
7748
7749 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7750 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7751 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7752 else
7753 dpll |= PLL_REF_INPUT_DREFCLK;
7754
7755 dpll |= DPLL_VCO_ENABLE;
7756 crtc_state->dpll_hw_state.dpll = dpll;
7757 }
7758
7759 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7760 {
7761 struct drm_device *dev = intel_crtc->base.dev;
7762 struct drm_i915_private *dev_priv = dev->dev_private;
7763 enum pipe pipe = intel_crtc->pipe;
7764 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7765 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7766 uint32_t crtc_vtotal, crtc_vblank_end;
7767 int vsyncshift = 0;
7768
7769 /* We need to be careful not to changed the adjusted mode, for otherwise
7770 * the hw state checker will get angry at the mismatch. */
7771 crtc_vtotal = adjusted_mode->crtc_vtotal;
7772 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7773
7774 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7775 /* the chip adds 2 halflines automatically */
7776 crtc_vtotal -= 1;
7777 crtc_vblank_end -= 1;
7778
7779 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7780 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7781 else
7782 vsyncshift = adjusted_mode->crtc_hsync_start -
7783 adjusted_mode->crtc_htotal / 2;
7784 if (vsyncshift < 0)
7785 vsyncshift += adjusted_mode->crtc_htotal;
7786 }
7787
7788 if (INTEL_INFO(dev)->gen > 3)
7789 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7790
7791 I915_WRITE(HTOTAL(cpu_transcoder),
7792 (adjusted_mode->crtc_hdisplay - 1) |
7793 ((adjusted_mode->crtc_htotal - 1) << 16));
7794 I915_WRITE(HBLANK(cpu_transcoder),
7795 (adjusted_mode->crtc_hblank_start - 1) |
7796 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7797 I915_WRITE(HSYNC(cpu_transcoder),
7798 (adjusted_mode->crtc_hsync_start - 1) |
7799 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7800
7801 I915_WRITE(VTOTAL(cpu_transcoder),
7802 (adjusted_mode->crtc_vdisplay - 1) |
7803 ((crtc_vtotal - 1) << 16));
7804 I915_WRITE(VBLANK(cpu_transcoder),
7805 (adjusted_mode->crtc_vblank_start - 1) |
7806 ((crtc_vblank_end - 1) << 16));
7807 I915_WRITE(VSYNC(cpu_transcoder),
7808 (adjusted_mode->crtc_vsync_start - 1) |
7809 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7810
7811 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7812 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7813 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7814 * bits. */
7815 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7816 (pipe == PIPE_B || pipe == PIPE_C))
7817 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7818
7819 /* pipesrc controls the size that is scaled from, which should
7820 * always be the user's requested size.
7821 */
7822 I915_WRITE(PIPESRC(pipe),
7823 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7824 (intel_crtc->config->pipe_src_h - 1));
7825 }
7826
7827 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7828 struct intel_crtc_state *pipe_config)
7829 {
7830 struct drm_device *dev = crtc->base.dev;
7831 struct drm_i915_private *dev_priv = dev->dev_private;
7832 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7833 uint32_t tmp;
7834
7835 tmp = I915_READ(HTOTAL(cpu_transcoder));
7836 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7837 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7838 tmp = I915_READ(HBLANK(cpu_transcoder));
7839 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7840 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7841 tmp = I915_READ(HSYNC(cpu_transcoder));
7842 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7843 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7844
7845 tmp = I915_READ(VTOTAL(cpu_transcoder));
7846 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7847 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7848 tmp = I915_READ(VBLANK(cpu_transcoder));
7849 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7850 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7851 tmp = I915_READ(VSYNC(cpu_transcoder));
7852 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7853 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7854
7855 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7856 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7857 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7858 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7859 }
7860
7861 tmp = I915_READ(PIPESRC(crtc->pipe));
7862 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7863 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7864
7865 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7866 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7867 }
7868
7869 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7870 struct intel_crtc_state *pipe_config)
7871 {
7872 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7873 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7874 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7875 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7876
7877 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7878 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7879 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7880 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7881
7882 mode->flags = pipe_config->base.adjusted_mode.flags;
7883 mode->type = DRM_MODE_TYPE_DRIVER;
7884
7885 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7886 mode->flags |= pipe_config->base.adjusted_mode.flags;
7887
7888 mode->hsync = drm_mode_hsync(mode);
7889 mode->vrefresh = drm_mode_vrefresh(mode);
7890 drm_mode_set_name(mode);
7891 }
7892
7893 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7894 {
7895 struct drm_device *dev = intel_crtc->base.dev;
7896 struct drm_i915_private *dev_priv = dev->dev_private;
7897 uint32_t pipeconf;
7898
7899 pipeconf = 0;
7900
7901 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7902 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7903 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7904
7905 if (intel_crtc->config->double_wide)
7906 pipeconf |= PIPECONF_DOUBLE_WIDE;
7907
7908 /* only g4x and later have fancy bpc/dither controls */
7909 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7910 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7911 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7912 pipeconf |= PIPECONF_DITHER_EN |
7913 PIPECONF_DITHER_TYPE_SP;
7914
7915 switch (intel_crtc->config->pipe_bpp) {
7916 case 18:
7917 pipeconf |= PIPECONF_6BPC;
7918 break;
7919 case 24:
7920 pipeconf |= PIPECONF_8BPC;
7921 break;
7922 case 30:
7923 pipeconf |= PIPECONF_10BPC;
7924 break;
7925 default:
7926 /* Case prevented by intel_choose_pipe_bpp_dither. */
7927 BUG();
7928 }
7929 }
7930
7931 if (HAS_PIPE_CXSR(dev)) {
7932 if (intel_crtc->lowfreq_avail) {
7933 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7934 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7935 } else {
7936 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7937 }
7938 }
7939
7940 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7941 if (INTEL_INFO(dev)->gen < 4 ||
7942 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7943 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7944 else
7945 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7946 } else
7947 pipeconf |= PIPECONF_PROGRESSIVE;
7948
7949 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7950 intel_crtc->config->limited_color_range)
7951 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7952
7953 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7954 POSTING_READ(PIPECONF(intel_crtc->pipe));
7955 }
7956
7957 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7958 struct intel_crtc_state *crtc_state)
7959 {
7960 struct drm_device *dev = crtc->base.dev;
7961 struct drm_i915_private *dev_priv = dev->dev_private;
7962 int refclk, num_connectors = 0;
7963 intel_clock_t clock;
7964 bool ok;
7965 const intel_limit_t *limit;
7966 struct drm_atomic_state *state = crtc_state->base.state;
7967 struct drm_connector *connector;
7968 struct drm_connector_state *connector_state;
7969 int i;
7970
7971 memset(&crtc_state->dpll_hw_state, 0,
7972 sizeof(crtc_state->dpll_hw_state));
7973
7974 if (crtc_state->has_dsi_encoder)
7975 return 0;
7976
7977 for_each_connector_in_state(state, connector, connector_state, i) {
7978 if (connector_state->crtc == &crtc->base)
7979 num_connectors++;
7980 }
7981
7982 if (!crtc_state->clock_set) {
7983 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7984
7985 /*
7986 * Returns a set of divisors for the desired target clock with
7987 * the given refclk, or FALSE. The returned values represent
7988 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7989 * 2) / p1 / p2.
7990 */
7991 limit = intel_limit(crtc_state, refclk);
7992 ok = dev_priv->display.find_dpll(limit, crtc_state,
7993 crtc_state->port_clock,
7994 refclk, NULL, &clock);
7995 if (!ok) {
7996 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7997 return -EINVAL;
7998 }
7999
8000 /* Compat-code for transition, will disappear. */
8001 crtc_state->dpll.n = clock.n;
8002 crtc_state->dpll.m1 = clock.m1;
8003 crtc_state->dpll.m2 = clock.m2;
8004 crtc_state->dpll.p1 = clock.p1;
8005 crtc_state->dpll.p2 = clock.p2;
8006 }
8007
8008 if (IS_GEN2(dev)) {
8009 i8xx_compute_dpll(crtc, crtc_state, NULL,
8010 num_connectors);
8011 } else if (IS_CHERRYVIEW(dev)) {
8012 chv_compute_dpll(crtc, crtc_state);
8013 } else if (IS_VALLEYVIEW(dev)) {
8014 vlv_compute_dpll(crtc, crtc_state);
8015 } else {
8016 i9xx_compute_dpll(crtc, crtc_state, NULL,
8017 num_connectors);
8018 }
8019
8020 return 0;
8021 }
8022
8023 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8024 struct intel_crtc_state *pipe_config)
8025 {
8026 struct drm_device *dev = crtc->base.dev;
8027 struct drm_i915_private *dev_priv = dev->dev_private;
8028 uint32_t tmp;
8029
8030 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8031 return;
8032
8033 tmp = I915_READ(PFIT_CONTROL);
8034 if (!(tmp & PFIT_ENABLE))
8035 return;
8036
8037 /* Check whether the pfit is attached to our pipe. */
8038 if (INTEL_INFO(dev)->gen < 4) {
8039 if (crtc->pipe != PIPE_B)
8040 return;
8041 } else {
8042 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8043 return;
8044 }
8045
8046 pipe_config->gmch_pfit.control = tmp;
8047 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8048 if (INTEL_INFO(dev)->gen < 5)
8049 pipe_config->gmch_pfit.lvds_border_bits =
8050 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8051 }
8052
8053 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8054 struct intel_crtc_state *pipe_config)
8055 {
8056 struct drm_device *dev = crtc->base.dev;
8057 struct drm_i915_private *dev_priv = dev->dev_private;
8058 int pipe = pipe_config->cpu_transcoder;
8059 intel_clock_t clock;
8060 u32 mdiv;
8061 int refclk = 100000;
8062
8063 /* In case of MIPI DPLL will not even be used */
8064 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8065 return;
8066
8067 mutex_lock(&dev_priv->sb_lock);
8068 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8069 mutex_unlock(&dev_priv->sb_lock);
8070
8071 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8072 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8073 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8074 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8075 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8076
8077 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8078 }
8079
8080 static void
8081 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8082 struct intel_initial_plane_config *plane_config)
8083 {
8084 struct drm_device *dev = crtc->base.dev;
8085 struct drm_i915_private *dev_priv = dev->dev_private;
8086 u32 val, base, offset;
8087 int pipe = crtc->pipe, plane = crtc->plane;
8088 int fourcc, pixel_format;
8089 unsigned int aligned_height;
8090 struct drm_framebuffer *fb;
8091 struct intel_framebuffer *intel_fb;
8092
8093 val = I915_READ(DSPCNTR(plane));
8094 if (!(val & DISPLAY_PLANE_ENABLE))
8095 return;
8096
8097 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8098 if (!intel_fb) {
8099 DRM_DEBUG_KMS("failed to alloc fb\n");
8100 return;
8101 }
8102
8103 fb = &intel_fb->base;
8104
8105 if (INTEL_INFO(dev)->gen >= 4) {
8106 if (val & DISPPLANE_TILED) {
8107 plane_config->tiling = I915_TILING_X;
8108 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8109 }
8110 }
8111
8112 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8113 fourcc = i9xx_format_to_fourcc(pixel_format);
8114 fb->pixel_format = fourcc;
8115 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8116
8117 if (INTEL_INFO(dev)->gen >= 4) {
8118 if (plane_config->tiling)
8119 offset = I915_READ(DSPTILEOFF(plane));
8120 else
8121 offset = I915_READ(DSPLINOFF(plane));
8122 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8123 } else {
8124 base = I915_READ(DSPADDR(plane));
8125 }
8126 plane_config->base = base;
8127
8128 val = I915_READ(PIPESRC(pipe));
8129 fb->width = ((val >> 16) & 0xfff) + 1;
8130 fb->height = ((val >> 0) & 0xfff) + 1;
8131
8132 val = I915_READ(DSPSTRIDE(pipe));
8133 fb->pitches[0] = val & 0xffffffc0;
8134
8135 aligned_height = intel_fb_align_height(dev, fb->height,
8136 fb->pixel_format,
8137 fb->modifier[0]);
8138
8139 plane_config->size = fb->pitches[0] * aligned_height;
8140
8141 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8142 pipe_name(pipe), plane, fb->width, fb->height,
8143 fb->bits_per_pixel, base, fb->pitches[0],
8144 plane_config->size);
8145
8146 plane_config->fb = intel_fb;
8147 }
8148
8149 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8150 struct intel_crtc_state *pipe_config)
8151 {
8152 struct drm_device *dev = crtc->base.dev;
8153 struct drm_i915_private *dev_priv = dev->dev_private;
8154 int pipe = pipe_config->cpu_transcoder;
8155 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8156 intel_clock_t clock;
8157 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8158 int refclk = 100000;
8159
8160 mutex_lock(&dev_priv->sb_lock);
8161 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8162 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8163 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8164 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8165 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8166 mutex_unlock(&dev_priv->sb_lock);
8167
8168 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8169 clock.m2 = (pll_dw0 & 0xff) << 22;
8170 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8171 clock.m2 |= pll_dw2 & 0x3fffff;
8172 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8173 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8174 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8175
8176 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8177 }
8178
8179 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8180 struct intel_crtc_state *pipe_config)
8181 {
8182 struct drm_device *dev = crtc->base.dev;
8183 struct drm_i915_private *dev_priv = dev->dev_private;
8184 uint32_t tmp;
8185
8186 if (!intel_display_power_is_enabled(dev_priv,
8187 POWER_DOMAIN_PIPE(crtc->pipe)))
8188 return false;
8189
8190 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8191 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8192
8193 tmp = I915_READ(PIPECONF(crtc->pipe));
8194 if (!(tmp & PIPECONF_ENABLE))
8195 return false;
8196
8197 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8198 switch (tmp & PIPECONF_BPC_MASK) {
8199 case PIPECONF_6BPC:
8200 pipe_config->pipe_bpp = 18;
8201 break;
8202 case PIPECONF_8BPC:
8203 pipe_config->pipe_bpp = 24;
8204 break;
8205 case PIPECONF_10BPC:
8206 pipe_config->pipe_bpp = 30;
8207 break;
8208 default:
8209 break;
8210 }
8211 }
8212
8213 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8214 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8215 pipe_config->limited_color_range = true;
8216
8217 if (INTEL_INFO(dev)->gen < 4)
8218 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8219
8220 intel_get_pipe_timings(crtc, pipe_config);
8221
8222 i9xx_get_pfit_config(crtc, pipe_config);
8223
8224 if (INTEL_INFO(dev)->gen >= 4) {
8225 tmp = I915_READ(DPLL_MD(crtc->pipe));
8226 pipe_config->pixel_multiplier =
8227 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8228 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8229 pipe_config->dpll_hw_state.dpll_md = tmp;
8230 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8231 tmp = I915_READ(DPLL(crtc->pipe));
8232 pipe_config->pixel_multiplier =
8233 ((tmp & SDVO_MULTIPLIER_MASK)
8234 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8235 } else {
8236 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8237 * port and will be fixed up in the encoder->get_config
8238 * function. */
8239 pipe_config->pixel_multiplier = 1;
8240 }
8241 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8242 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8243 /*
8244 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8245 * on 830. Filter it out here so that we don't
8246 * report errors due to that.
8247 */
8248 if (IS_I830(dev))
8249 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8250
8251 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8252 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8253 } else {
8254 /* Mask out read-only status bits. */
8255 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8256 DPLL_PORTC_READY_MASK |
8257 DPLL_PORTB_READY_MASK);
8258 }
8259
8260 if (IS_CHERRYVIEW(dev))
8261 chv_crtc_clock_get(crtc, pipe_config);
8262 else if (IS_VALLEYVIEW(dev))
8263 vlv_crtc_clock_get(crtc, pipe_config);
8264 else
8265 i9xx_crtc_clock_get(crtc, pipe_config);
8266
8267 /*
8268 * Normally the dotclock is filled in by the encoder .get_config()
8269 * but in case the pipe is enabled w/o any ports we need a sane
8270 * default.
8271 */
8272 pipe_config->base.adjusted_mode.crtc_clock =
8273 pipe_config->port_clock / pipe_config->pixel_multiplier;
8274
8275 return true;
8276 }
8277
8278 static void ironlake_init_pch_refclk(struct drm_device *dev)
8279 {
8280 struct drm_i915_private *dev_priv = dev->dev_private;
8281 struct intel_encoder *encoder;
8282 u32 val, final;
8283 bool has_lvds = false;
8284 bool has_cpu_edp = false;
8285 bool has_panel = false;
8286 bool has_ck505 = false;
8287 bool can_ssc = false;
8288
8289 /* We need to take the global config into account */
8290 for_each_intel_encoder(dev, encoder) {
8291 switch (encoder->type) {
8292 case INTEL_OUTPUT_LVDS:
8293 has_panel = true;
8294 has_lvds = true;
8295 break;
8296 case INTEL_OUTPUT_EDP:
8297 has_panel = true;
8298 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8299 has_cpu_edp = true;
8300 break;
8301 default:
8302 break;
8303 }
8304 }
8305
8306 if (HAS_PCH_IBX(dev)) {
8307 has_ck505 = dev_priv->vbt.display_clock_mode;
8308 can_ssc = has_ck505;
8309 } else {
8310 has_ck505 = false;
8311 can_ssc = true;
8312 }
8313
8314 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8315 has_panel, has_lvds, has_ck505);
8316
8317 /* Ironlake: try to setup display ref clock before DPLL
8318 * enabling. This is only under driver's control after
8319 * PCH B stepping, previous chipset stepping should be
8320 * ignoring this setting.
8321 */
8322 val = I915_READ(PCH_DREF_CONTROL);
8323
8324 /* As we must carefully and slowly disable/enable each source in turn,
8325 * compute the final state we want first and check if we need to
8326 * make any changes at all.
8327 */
8328 final = val;
8329 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8330 if (has_ck505)
8331 final |= DREF_NONSPREAD_CK505_ENABLE;
8332 else
8333 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8334
8335 final &= ~DREF_SSC_SOURCE_MASK;
8336 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8337 final &= ~DREF_SSC1_ENABLE;
8338
8339 if (has_panel) {
8340 final |= DREF_SSC_SOURCE_ENABLE;
8341
8342 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8343 final |= DREF_SSC1_ENABLE;
8344
8345 if (has_cpu_edp) {
8346 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8347 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8348 else
8349 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8350 } else
8351 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8352 } else {
8353 final |= DREF_SSC_SOURCE_DISABLE;
8354 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8355 }
8356
8357 if (final == val)
8358 return;
8359
8360 /* Always enable nonspread source */
8361 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8362
8363 if (has_ck505)
8364 val |= DREF_NONSPREAD_CK505_ENABLE;
8365 else
8366 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8367
8368 if (has_panel) {
8369 val &= ~DREF_SSC_SOURCE_MASK;
8370 val |= DREF_SSC_SOURCE_ENABLE;
8371
8372 /* SSC must be turned on before enabling the CPU output */
8373 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8374 DRM_DEBUG_KMS("Using SSC on panel\n");
8375 val |= DREF_SSC1_ENABLE;
8376 } else
8377 val &= ~DREF_SSC1_ENABLE;
8378
8379 /* Get SSC going before enabling the outputs */
8380 I915_WRITE(PCH_DREF_CONTROL, val);
8381 POSTING_READ(PCH_DREF_CONTROL);
8382 udelay(200);
8383
8384 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8385
8386 /* Enable CPU source on CPU attached eDP */
8387 if (has_cpu_edp) {
8388 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8389 DRM_DEBUG_KMS("Using SSC on eDP\n");
8390 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8391 } else
8392 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8393 } else
8394 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8395
8396 I915_WRITE(PCH_DREF_CONTROL, val);
8397 POSTING_READ(PCH_DREF_CONTROL);
8398 udelay(200);
8399 } else {
8400 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8401
8402 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8403
8404 /* Turn off CPU output */
8405 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8406
8407 I915_WRITE(PCH_DREF_CONTROL, val);
8408 POSTING_READ(PCH_DREF_CONTROL);
8409 udelay(200);
8410
8411 /* Turn off the SSC source */
8412 val &= ~DREF_SSC_SOURCE_MASK;
8413 val |= DREF_SSC_SOURCE_DISABLE;
8414
8415 /* Turn off SSC1 */
8416 val &= ~DREF_SSC1_ENABLE;
8417
8418 I915_WRITE(PCH_DREF_CONTROL, val);
8419 POSTING_READ(PCH_DREF_CONTROL);
8420 udelay(200);
8421 }
8422
8423 BUG_ON(val != final);
8424 }
8425
8426 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8427 {
8428 uint32_t tmp;
8429
8430 tmp = I915_READ(SOUTH_CHICKEN2);
8431 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8432 I915_WRITE(SOUTH_CHICKEN2, tmp);
8433
8434 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8435 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8436 DRM_ERROR("FDI mPHY reset assert timeout\n");
8437
8438 tmp = I915_READ(SOUTH_CHICKEN2);
8439 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8440 I915_WRITE(SOUTH_CHICKEN2, tmp);
8441
8442 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8443 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8444 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8445 }
8446
8447 /* WaMPhyProgramming:hsw */
8448 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8449 {
8450 uint32_t tmp;
8451
8452 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8453 tmp &= ~(0xFF << 24);
8454 tmp |= (0x12 << 24);
8455 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8456
8457 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8458 tmp |= (1 << 11);
8459 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8460
8461 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8462 tmp |= (1 << 11);
8463 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8464
8465 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8466 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8467 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8468
8469 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8470 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8471 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8472
8473 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8474 tmp &= ~(7 << 13);
8475 tmp |= (5 << 13);
8476 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8477
8478 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8479 tmp &= ~(7 << 13);
8480 tmp |= (5 << 13);
8481 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8482
8483 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8484 tmp &= ~0xFF;
8485 tmp |= 0x1C;
8486 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8487
8488 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8489 tmp &= ~0xFF;
8490 tmp |= 0x1C;
8491 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8492
8493 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8494 tmp &= ~(0xFF << 16);
8495 tmp |= (0x1C << 16);
8496 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8497
8498 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8499 tmp &= ~(0xFF << 16);
8500 tmp |= (0x1C << 16);
8501 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8502
8503 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8504 tmp |= (1 << 27);
8505 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8506
8507 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8508 tmp |= (1 << 27);
8509 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8510
8511 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8512 tmp &= ~(0xF << 28);
8513 tmp |= (4 << 28);
8514 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8515
8516 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8517 tmp &= ~(0xF << 28);
8518 tmp |= (4 << 28);
8519 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8520 }
8521
8522 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8523 * Programming" based on the parameters passed:
8524 * - Sequence to enable CLKOUT_DP
8525 * - Sequence to enable CLKOUT_DP without spread
8526 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8527 */
8528 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8529 bool with_fdi)
8530 {
8531 struct drm_i915_private *dev_priv = dev->dev_private;
8532 uint32_t reg, tmp;
8533
8534 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8535 with_spread = true;
8536 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8537 with_fdi = false;
8538
8539 mutex_lock(&dev_priv->sb_lock);
8540
8541 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8542 tmp &= ~SBI_SSCCTL_DISABLE;
8543 tmp |= SBI_SSCCTL_PATHALT;
8544 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8545
8546 udelay(24);
8547
8548 if (with_spread) {
8549 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8550 tmp &= ~SBI_SSCCTL_PATHALT;
8551 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8552
8553 if (with_fdi) {
8554 lpt_reset_fdi_mphy(dev_priv);
8555 lpt_program_fdi_mphy(dev_priv);
8556 }
8557 }
8558
8559 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8560 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8561 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8562 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8563
8564 mutex_unlock(&dev_priv->sb_lock);
8565 }
8566
8567 /* Sequence to disable CLKOUT_DP */
8568 static void lpt_disable_clkout_dp(struct drm_device *dev)
8569 {
8570 struct drm_i915_private *dev_priv = dev->dev_private;
8571 uint32_t reg, tmp;
8572
8573 mutex_lock(&dev_priv->sb_lock);
8574
8575 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8576 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8577 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8578 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8579
8580 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8581 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8582 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8583 tmp |= SBI_SSCCTL_PATHALT;
8584 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8585 udelay(32);
8586 }
8587 tmp |= SBI_SSCCTL_DISABLE;
8588 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8589 }
8590
8591 mutex_unlock(&dev_priv->sb_lock);
8592 }
8593
8594 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8595
8596 static const uint16_t sscdivintphase[] = {
8597 [BEND_IDX( 50)] = 0x3B23,
8598 [BEND_IDX( 45)] = 0x3B23,
8599 [BEND_IDX( 40)] = 0x3C23,
8600 [BEND_IDX( 35)] = 0x3C23,
8601 [BEND_IDX( 30)] = 0x3D23,
8602 [BEND_IDX( 25)] = 0x3D23,
8603 [BEND_IDX( 20)] = 0x3E23,
8604 [BEND_IDX( 15)] = 0x3E23,
8605 [BEND_IDX( 10)] = 0x3F23,
8606 [BEND_IDX( 5)] = 0x3F23,
8607 [BEND_IDX( 0)] = 0x0025,
8608 [BEND_IDX( -5)] = 0x0025,
8609 [BEND_IDX(-10)] = 0x0125,
8610 [BEND_IDX(-15)] = 0x0125,
8611 [BEND_IDX(-20)] = 0x0225,
8612 [BEND_IDX(-25)] = 0x0225,
8613 [BEND_IDX(-30)] = 0x0325,
8614 [BEND_IDX(-35)] = 0x0325,
8615 [BEND_IDX(-40)] = 0x0425,
8616 [BEND_IDX(-45)] = 0x0425,
8617 [BEND_IDX(-50)] = 0x0525,
8618 };
8619
8620 /*
8621 * Bend CLKOUT_DP
8622 * steps -50 to 50 inclusive, in steps of 5
8623 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8624 * change in clock period = -(steps / 10) * 5.787 ps
8625 */
8626 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8627 {
8628 uint32_t tmp;
8629 int idx = BEND_IDX(steps);
8630
8631 if (WARN_ON(steps % 5 != 0))
8632 return;
8633
8634 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8635 return;
8636
8637 mutex_lock(&dev_priv->sb_lock);
8638
8639 if (steps % 10 != 0)
8640 tmp = 0xAAAAAAAB;
8641 else
8642 tmp = 0x00000000;
8643 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8644
8645 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8646 tmp &= 0xffff0000;
8647 tmp |= sscdivintphase[idx];
8648 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8649
8650 mutex_unlock(&dev_priv->sb_lock);
8651 }
8652
8653 #undef BEND_IDX
8654
8655 static void lpt_init_pch_refclk(struct drm_device *dev)
8656 {
8657 struct intel_encoder *encoder;
8658 bool has_vga = false;
8659
8660 for_each_intel_encoder(dev, encoder) {
8661 switch (encoder->type) {
8662 case INTEL_OUTPUT_ANALOG:
8663 has_vga = true;
8664 break;
8665 default:
8666 break;
8667 }
8668 }
8669
8670 if (has_vga) {
8671 lpt_bend_clkout_dp(to_i915(dev), 0);
8672 lpt_enable_clkout_dp(dev, true, true);
8673 } else {
8674 lpt_disable_clkout_dp(dev);
8675 }
8676 }
8677
8678 /*
8679 * Initialize reference clocks when the driver loads
8680 */
8681 void intel_init_pch_refclk(struct drm_device *dev)
8682 {
8683 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8684 ironlake_init_pch_refclk(dev);
8685 else if (HAS_PCH_LPT(dev))
8686 lpt_init_pch_refclk(dev);
8687 }
8688
8689 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8690 {
8691 struct drm_device *dev = crtc_state->base.crtc->dev;
8692 struct drm_i915_private *dev_priv = dev->dev_private;
8693 struct drm_atomic_state *state = crtc_state->base.state;
8694 struct drm_connector *connector;
8695 struct drm_connector_state *connector_state;
8696 struct intel_encoder *encoder;
8697 int num_connectors = 0, i;
8698 bool is_lvds = false;
8699
8700 for_each_connector_in_state(state, connector, connector_state, i) {
8701 if (connector_state->crtc != crtc_state->base.crtc)
8702 continue;
8703
8704 encoder = to_intel_encoder(connector_state->best_encoder);
8705
8706 switch (encoder->type) {
8707 case INTEL_OUTPUT_LVDS:
8708 is_lvds = true;
8709 break;
8710 default:
8711 break;
8712 }
8713 num_connectors++;
8714 }
8715
8716 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8717 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8718 dev_priv->vbt.lvds_ssc_freq);
8719 return dev_priv->vbt.lvds_ssc_freq;
8720 }
8721
8722 return 120000;
8723 }
8724
8725 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8726 {
8727 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8729 int pipe = intel_crtc->pipe;
8730 uint32_t val;
8731
8732 val = 0;
8733
8734 switch (intel_crtc->config->pipe_bpp) {
8735 case 18:
8736 val |= PIPECONF_6BPC;
8737 break;
8738 case 24:
8739 val |= PIPECONF_8BPC;
8740 break;
8741 case 30:
8742 val |= PIPECONF_10BPC;
8743 break;
8744 case 36:
8745 val |= PIPECONF_12BPC;
8746 break;
8747 default:
8748 /* Case prevented by intel_choose_pipe_bpp_dither. */
8749 BUG();
8750 }
8751
8752 if (intel_crtc->config->dither)
8753 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8754
8755 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8756 val |= PIPECONF_INTERLACED_ILK;
8757 else
8758 val |= PIPECONF_PROGRESSIVE;
8759
8760 if (intel_crtc->config->limited_color_range)
8761 val |= PIPECONF_COLOR_RANGE_SELECT;
8762
8763 I915_WRITE(PIPECONF(pipe), val);
8764 POSTING_READ(PIPECONF(pipe));
8765 }
8766
8767 /*
8768 * Set up the pipe CSC unit.
8769 *
8770 * Currently only full range RGB to limited range RGB conversion
8771 * is supported, but eventually this should handle various
8772 * RGB<->YCbCr scenarios as well.
8773 */
8774 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8775 {
8776 struct drm_device *dev = crtc->dev;
8777 struct drm_i915_private *dev_priv = dev->dev_private;
8778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8779 int pipe = intel_crtc->pipe;
8780 uint16_t coeff = 0x7800; /* 1.0 */
8781
8782 /*
8783 * TODO: Check what kind of values actually come out of the pipe
8784 * with these coeff/postoff values and adjust to get the best
8785 * accuracy. Perhaps we even need to take the bpc value into
8786 * consideration.
8787 */
8788
8789 if (intel_crtc->config->limited_color_range)
8790 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8791
8792 /*
8793 * GY/GU and RY/RU should be the other way around according
8794 * to BSpec, but reality doesn't agree. Just set them up in
8795 * a way that results in the correct picture.
8796 */
8797 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8798 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8799
8800 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8801 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8802
8803 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8804 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8805
8806 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8807 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8808 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8809
8810 if (INTEL_INFO(dev)->gen > 6) {
8811 uint16_t postoff = 0;
8812
8813 if (intel_crtc->config->limited_color_range)
8814 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8815
8816 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8817 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8818 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8819
8820 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8821 } else {
8822 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8823
8824 if (intel_crtc->config->limited_color_range)
8825 mode |= CSC_BLACK_SCREEN_OFFSET;
8826
8827 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8828 }
8829 }
8830
8831 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8832 {
8833 struct drm_device *dev = crtc->dev;
8834 struct drm_i915_private *dev_priv = dev->dev_private;
8835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8836 enum pipe pipe = intel_crtc->pipe;
8837 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8838 uint32_t val;
8839
8840 val = 0;
8841
8842 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8843 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8844
8845 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8846 val |= PIPECONF_INTERLACED_ILK;
8847 else
8848 val |= PIPECONF_PROGRESSIVE;
8849
8850 I915_WRITE(PIPECONF(cpu_transcoder), val);
8851 POSTING_READ(PIPECONF(cpu_transcoder));
8852
8853 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8854 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8855
8856 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8857 val = 0;
8858
8859 switch (intel_crtc->config->pipe_bpp) {
8860 case 18:
8861 val |= PIPEMISC_DITHER_6_BPC;
8862 break;
8863 case 24:
8864 val |= PIPEMISC_DITHER_8_BPC;
8865 break;
8866 case 30:
8867 val |= PIPEMISC_DITHER_10_BPC;
8868 break;
8869 case 36:
8870 val |= PIPEMISC_DITHER_12_BPC;
8871 break;
8872 default:
8873 /* Case prevented by pipe_config_set_bpp. */
8874 BUG();
8875 }
8876
8877 if (intel_crtc->config->dither)
8878 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8879
8880 I915_WRITE(PIPEMISC(pipe), val);
8881 }
8882 }
8883
8884 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8885 struct intel_crtc_state *crtc_state,
8886 intel_clock_t *clock,
8887 bool *has_reduced_clock,
8888 intel_clock_t *reduced_clock)
8889 {
8890 struct drm_device *dev = crtc->dev;
8891 struct drm_i915_private *dev_priv = dev->dev_private;
8892 int refclk;
8893 const intel_limit_t *limit;
8894 bool ret;
8895
8896 refclk = ironlake_get_refclk(crtc_state);
8897
8898 /*
8899 * Returns a set of divisors for the desired target clock with the given
8900 * refclk, or FALSE. The returned values represent the clock equation:
8901 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8902 */
8903 limit = intel_limit(crtc_state, refclk);
8904 ret = dev_priv->display.find_dpll(limit, crtc_state,
8905 crtc_state->port_clock,
8906 refclk, NULL, clock);
8907 if (!ret)
8908 return false;
8909
8910 return true;
8911 }
8912
8913 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8914 {
8915 /*
8916 * Account for spread spectrum to avoid
8917 * oversubscribing the link. Max center spread
8918 * is 2.5%; use 5% for safety's sake.
8919 */
8920 u32 bps = target_clock * bpp * 21 / 20;
8921 return DIV_ROUND_UP(bps, link_bw * 8);
8922 }
8923
8924 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8925 {
8926 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8927 }
8928
8929 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8930 struct intel_crtc_state *crtc_state,
8931 u32 *fp,
8932 intel_clock_t *reduced_clock, u32 *fp2)
8933 {
8934 struct drm_crtc *crtc = &intel_crtc->base;
8935 struct drm_device *dev = crtc->dev;
8936 struct drm_i915_private *dev_priv = dev->dev_private;
8937 struct drm_atomic_state *state = crtc_state->base.state;
8938 struct drm_connector *connector;
8939 struct drm_connector_state *connector_state;
8940 struct intel_encoder *encoder;
8941 uint32_t dpll;
8942 int factor, num_connectors = 0, i;
8943 bool is_lvds = false, is_sdvo = false;
8944
8945 for_each_connector_in_state(state, connector, connector_state, i) {
8946 if (connector_state->crtc != crtc_state->base.crtc)
8947 continue;
8948
8949 encoder = to_intel_encoder(connector_state->best_encoder);
8950
8951 switch (encoder->type) {
8952 case INTEL_OUTPUT_LVDS:
8953 is_lvds = true;
8954 break;
8955 case INTEL_OUTPUT_SDVO:
8956 case INTEL_OUTPUT_HDMI:
8957 is_sdvo = true;
8958 break;
8959 default:
8960 break;
8961 }
8962
8963 num_connectors++;
8964 }
8965
8966 /* Enable autotuning of the PLL clock (if permissible) */
8967 factor = 21;
8968 if (is_lvds) {
8969 if ((intel_panel_use_ssc(dev_priv) &&
8970 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8971 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8972 factor = 25;
8973 } else if (crtc_state->sdvo_tv_clock)
8974 factor = 20;
8975
8976 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8977 *fp |= FP_CB_TUNE;
8978
8979 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8980 *fp2 |= FP_CB_TUNE;
8981
8982 dpll = 0;
8983
8984 if (is_lvds)
8985 dpll |= DPLLB_MODE_LVDS;
8986 else
8987 dpll |= DPLLB_MODE_DAC_SERIAL;
8988
8989 dpll |= (crtc_state->pixel_multiplier - 1)
8990 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8991
8992 if (is_sdvo)
8993 dpll |= DPLL_SDVO_HIGH_SPEED;
8994 if (crtc_state->has_dp_encoder)
8995 dpll |= DPLL_SDVO_HIGH_SPEED;
8996
8997 /* compute bitmask from p1 value */
8998 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8999 /* also FPA1 */
9000 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9001
9002 switch (crtc_state->dpll.p2) {
9003 case 5:
9004 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9005 break;
9006 case 7:
9007 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9008 break;
9009 case 10:
9010 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9011 break;
9012 case 14:
9013 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9014 break;
9015 }
9016
9017 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
9018 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9019 else
9020 dpll |= PLL_REF_INPUT_DREFCLK;
9021
9022 return dpll | DPLL_VCO_ENABLE;
9023 }
9024
9025 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9026 struct intel_crtc_state *crtc_state)
9027 {
9028 struct drm_device *dev = crtc->base.dev;
9029 intel_clock_t clock, reduced_clock;
9030 u32 dpll = 0, fp = 0, fp2 = 0;
9031 bool ok, has_reduced_clock = false;
9032 bool is_lvds = false;
9033 struct intel_shared_dpll *pll;
9034
9035 memset(&crtc_state->dpll_hw_state, 0,
9036 sizeof(crtc_state->dpll_hw_state));
9037
9038 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9039
9040 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9041 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9042
9043 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9044 &has_reduced_clock, &reduced_clock);
9045 if (!ok && !crtc_state->clock_set) {
9046 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9047 return -EINVAL;
9048 }
9049 /* Compat-code for transition, will disappear. */
9050 if (!crtc_state->clock_set) {
9051 crtc_state->dpll.n = clock.n;
9052 crtc_state->dpll.m1 = clock.m1;
9053 crtc_state->dpll.m2 = clock.m2;
9054 crtc_state->dpll.p1 = clock.p1;
9055 crtc_state->dpll.p2 = clock.p2;
9056 }
9057
9058 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9059 if (crtc_state->has_pch_encoder) {
9060 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9061 if (has_reduced_clock)
9062 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9063
9064 dpll = ironlake_compute_dpll(crtc, crtc_state,
9065 &fp, &reduced_clock,
9066 has_reduced_clock ? &fp2 : NULL);
9067
9068 crtc_state->dpll_hw_state.dpll = dpll;
9069 crtc_state->dpll_hw_state.fp0 = fp;
9070 if (has_reduced_clock)
9071 crtc_state->dpll_hw_state.fp1 = fp2;
9072 else
9073 crtc_state->dpll_hw_state.fp1 = fp;
9074
9075 pll = intel_get_shared_dpll(crtc, crtc_state);
9076 if (pll == NULL) {
9077 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9078 pipe_name(crtc->pipe));
9079 return -EINVAL;
9080 }
9081 }
9082
9083 if (is_lvds && has_reduced_clock)
9084 crtc->lowfreq_avail = true;
9085 else
9086 crtc->lowfreq_avail = false;
9087
9088 return 0;
9089 }
9090
9091 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9092 struct intel_link_m_n *m_n)
9093 {
9094 struct drm_device *dev = crtc->base.dev;
9095 struct drm_i915_private *dev_priv = dev->dev_private;
9096 enum pipe pipe = crtc->pipe;
9097
9098 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9099 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9100 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9101 & ~TU_SIZE_MASK;
9102 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9103 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9104 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9105 }
9106
9107 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9108 enum transcoder transcoder,
9109 struct intel_link_m_n *m_n,
9110 struct intel_link_m_n *m2_n2)
9111 {
9112 struct drm_device *dev = crtc->base.dev;
9113 struct drm_i915_private *dev_priv = dev->dev_private;
9114 enum pipe pipe = crtc->pipe;
9115
9116 if (INTEL_INFO(dev)->gen >= 5) {
9117 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9118 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9119 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9120 & ~TU_SIZE_MASK;
9121 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9122 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9123 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9124 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9125 * gen < 8) and if DRRS is supported (to make sure the
9126 * registers are not unnecessarily read).
9127 */
9128 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9129 crtc->config->has_drrs) {
9130 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9131 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9132 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9133 & ~TU_SIZE_MASK;
9134 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9135 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9136 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9137 }
9138 } else {
9139 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9140 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9141 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9142 & ~TU_SIZE_MASK;
9143 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9144 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9145 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9146 }
9147 }
9148
9149 void intel_dp_get_m_n(struct intel_crtc *crtc,
9150 struct intel_crtc_state *pipe_config)
9151 {
9152 if (pipe_config->has_pch_encoder)
9153 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9154 else
9155 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9156 &pipe_config->dp_m_n,
9157 &pipe_config->dp_m2_n2);
9158 }
9159
9160 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9161 struct intel_crtc_state *pipe_config)
9162 {
9163 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9164 &pipe_config->fdi_m_n, NULL);
9165 }
9166
9167 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9168 struct intel_crtc_state *pipe_config)
9169 {
9170 struct drm_device *dev = crtc->base.dev;
9171 struct drm_i915_private *dev_priv = dev->dev_private;
9172 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9173 uint32_t ps_ctrl = 0;
9174 int id = -1;
9175 int i;
9176
9177 /* find scaler attached to this pipe */
9178 for (i = 0; i < crtc->num_scalers; i++) {
9179 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9180 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9181 id = i;
9182 pipe_config->pch_pfit.enabled = true;
9183 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9184 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9185 break;
9186 }
9187 }
9188
9189 scaler_state->scaler_id = id;
9190 if (id >= 0) {
9191 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9192 } else {
9193 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9194 }
9195 }
9196
9197 static void
9198 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9199 struct intel_initial_plane_config *plane_config)
9200 {
9201 struct drm_device *dev = crtc->base.dev;
9202 struct drm_i915_private *dev_priv = dev->dev_private;
9203 u32 val, base, offset, stride_mult, tiling;
9204 int pipe = crtc->pipe;
9205 int fourcc, pixel_format;
9206 unsigned int aligned_height;
9207 struct drm_framebuffer *fb;
9208 struct intel_framebuffer *intel_fb;
9209
9210 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9211 if (!intel_fb) {
9212 DRM_DEBUG_KMS("failed to alloc fb\n");
9213 return;
9214 }
9215
9216 fb = &intel_fb->base;
9217
9218 val = I915_READ(PLANE_CTL(pipe, 0));
9219 if (!(val & PLANE_CTL_ENABLE))
9220 goto error;
9221
9222 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9223 fourcc = skl_format_to_fourcc(pixel_format,
9224 val & PLANE_CTL_ORDER_RGBX,
9225 val & PLANE_CTL_ALPHA_MASK);
9226 fb->pixel_format = fourcc;
9227 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9228
9229 tiling = val & PLANE_CTL_TILED_MASK;
9230 switch (tiling) {
9231 case PLANE_CTL_TILED_LINEAR:
9232 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9233 break;
9234 case PLANE_CTL_TILED_X:
9235 plane_config->tiling = I915_TILING_X;
9236 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9237 break;
9238 case PLANE_CTL_TILED_Y:
9239 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9240 break;
9241 case PLANE_CTL_TILED_YF:
9242 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9243 break;
9244 default:
9245 MISSING_CASE(tiling);
9246 goto error;
9247 }
9248
9249 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9250 plane_config->base = base;
9251
9252 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9253
9254 val = I915_READ(PLANE_SIZE(pipe, 0));
9255 fb->height = ((val >> 16) & 0xfff) + 1;
9256 fb->width = ((val >> 0) & 0x1fff) + 1;
9257
9258 val = I915_READ(PLANE_STRIDE(pipe, 0));
9259 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9260 fb->pixel_format);
9261 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9262
9263 aligned_height = intel_fb_align_height(dev, fb->height,
9264 fb->pixel_format,
9265 fb->modifier[0]);
9266
9267 plane_config->size = fb->pitches[0] * aligned_height;
9268
9269 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9270 pipe_name(pipe), fb->width, fb->height,
9271 fb->bits_per_pixel, base, fb->pitches[0],
9272 plane_config->size);
9273
9274 plane_config->fb = intel_fb;
9275 return;
9276
9277 error:
9278 kfree(fb);
9279 }
9280
9281 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9282 struct intel_crtc_state *pipe_config)
9283 {
9284 struct drm_device *dev = crtc->base.dev;
9285 struct drm_i915_private *dev_priv = dev->dev_private;
9286 uint32_t tmp;
9287
9288 tmp = I915_READ(PF_CTL(crtc->pipe));
9289
9290 if (tmp & PF_ENABLE) {
9291 pipe_config->pch_pfit.enabled = true;
9292 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9293 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9294
9295 /* We currently do not free assignements of panel fitters on
9296 * ivb/hsw (since we don't use the higher upscaling modes which
9297 * differentiates them) so just WARN about this case for now. */
9298 if (IS_GEN7(dev)) {
9299 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9300 PF_PIPE_SEL_IVB(crtc->pipe));
9301 }
9302 }
9303 }
9304
9305 static void
9306 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9307 struct intel_initial_plane_config *plane_config)
9308 {
9309 struct drm_device *dev = crtc->base.dev;
9310 struct drm_i915_private *dev_priv = dev->dev_private;
9311 u32 val, base, offset;
9312 int pipe = crtc->pipe;
9313 int fourcc, pixel_format;
9314 unsigned int aligned_height;
9315 struct drm_framebuffer *fb;
9316 struct intel_framebuffer *intel_fb;
9317
9318 val = I915_READ(DSPCNTR(pipe));
9319 if (!(val & DISPLAY_PLANE_ENABLE))
9320 return;
9321
9322 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9323 if (!intel_fb) {
9324 DRM_DEBUG_KMS("failed to alloc fb\n");
9325 return;
9326 }
9327
9328 fb = &intel_fb->base;
9329
9330 if (INTEL_INFO(dev)->gen >= 4) {
9331 if (val & DISPPLANE_TILED) {
9332 plane_config->tiling = I915_TILING_X;
9333 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9334 }
9335 }
9336
9337 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9338 fourcc = i9xx_format_to_fourcc(pixel_format);
9339 fb->pixel_format = fourcc;
9340 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9341
9342 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9343 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9344 offset = I915_READ(DSPOFFSET(pipe));
9345 } else {
9346 if (plane_config->tiling)
9347 offset = I915_READ(DSPTILEOFF(pipe));
9348 else
9349 offset = I915_READ(DSPLINOFF(pipe));
9350 }
9351 plane_config->base = base;
9352
9353 val = I915_READ(PIPESRC(pipe));
9354 fb->width = ((val >> 16) & 0xfff) + 1;
9355 fb->height = ((val >> 0) & 0xfff) + 1;
9356
9357 val = I915_READ(DSPSTRIDE(pipe));
9358 fb->pitches[0] = val & 0xffffffc0;
9359
9360 aligned_height = intel_fb_align_height(dev, fb->height,
9361 fb->pixel_format,
9362 fb->modifier[0]);
9363
9364 plane_config->size = fb->pitches[0] * aligned_height;
9365
9366 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9367 pipe_name(pipe), fb->width, fb->height,
9368 fb->bits_per_pixel, base, fb->pitches[0],
9369 plane_config->size);
9370
9371 plane_config->fb = intel_fb;
9372 }
9373
9374 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9375 struct intel_crtc_state *pipe_config)
9376 {
9377 struct drm_device *dev = crtc->base.dev;
9378 struct drm_i915_private *dev_priv = dev->dev_private;
9379 uint32_t tmp;
9380
9381 if (!intel_display_power_is_enabled(dev_priv,
9382 POWER_DOMAIN_PIPE(crtc->pipe)))
9383 return false;
9384
9385 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9386 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9387
9388 tmp = I915_READ(PIPECONF(crtc->pipe));
9389 if (!(tmp & PIPECONF_ENABLE))
9390 return false;
9391
9392 switch (tmp & PIPECONF_BPC_MASK) {
9393 case PIPECONF_6BPC:
9394 pipe_config->pipe_bpp = 18;
9395 break;
9396 case PIPECONF_8BPC:
9397 pipe_config->pipe_bpp = 24;
9398 break;
9399 case PIPECONF_10BPC:
9400 pipe_config->pipe_bpp = 30;
9401 break;
9402 case PIPECONF_12BPC:
9403 pipe_config->pipe_bpp = 36;
9404 break;
9405 default:
9406 break;
9407 }
9408
9409 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9410 pipe_config->limited_color_range = true;
9411
9412 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9413 struct intel_shared_dpll *pll;
9414
9415 pipe_config->has_pch_encoder = true;
9416
9417 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9418 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9419 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9420
9421 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9422
9423 if (HAS_PCH_IBX(dev_priv->dev)) {
9424 pipe_config->shared_dpll =
9425 (enum intel_dpll_id) crtc->pipe;
9426 } else {
9427 tmp = I915_READ(PCH_DPLL_SEL);
9428 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9429 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9430 else
9431 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9432 }
9433
9434 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9435
9436 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9437 &pipe_config->dpll_hw_state));
9438
9439 tmp = pipe_config->dpll_hw_state.dpll;
9440 pipe_config->pixel_multiplier =
9441 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9442 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9443
9444 ironlake_pch_clock_get(crtc, pipe_config);
9445 } else {
9446 pipe_config->pixel_multiplier = 1;
9447 }
9448
9449 intel_get_pipe_timings(crtc, pipe_config);
9450
9451 ironlake_get_pfit_config(crtc, pipe_config);
9452
9453 return true;
9454 }
9455
9456 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9457 {
9458 struct drm_device *dev = dev_priv->dev;
9459 struct intel_crtc *crtc;
9460
9461 for_each_intel_crtc(dev, crtc)
9462 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9463 pipe_name(crtc->pipe));
9464
9465 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9466 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9467 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9468 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9469 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9470 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9471 "CPU PWM1 enabled\n");
9472 if (IS_HASWELL(dev))
9473 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9474 "CPU PWM2 enabled\n");
9475 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9476 "PCH PWM1 enabled\n");
9477 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9478 "Utility pin enabled\n");
9479 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9480
9481 /*
9482 * In theory we can still leave IRQs enabled, as long as only the HPD
9483 * interrupts remain enabled. We used to check for that, but since it's
9484 * gen-specific and since we only disable LCPLL after we fully disable
9485 * the interrupts, the check below should be enough.
9486 */
9487 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9488 }
9489
9490 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9491 {
9492 struct drm_device *dev = dev_priv->dev;
9493
9494 if (IS_HASWELL(dev))
9495 return I915_READ(D_COMP_HSW);
9496 else
9497 return I915_READ(D_COMP_BDW);
9498 }
9499
9500 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9501 {
9502 struct drm_device *dev = dev_priv->dev;
9503
9504 if (IS_HASWELL(dev)) {
9505 mutex_lock(&dev_priv->rps.hw_lock);
9506 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9507 val))
9508 DRM_ERROR("Failed to write to D_COMP\n");
9509 mutex_unlock(&dev_priv->rps.hw_lock);
9510 } else {
9511 I915_WRITE(D_COMP_BDW, val);
9512 POSTING_READ(D_COMP_BDW);
9513 }
9514 }
9515
9516 /*
9517 * This function implements pieces of two sequences from BSpec:
9518 * - Sequence for display software to disable LCPLL
9519 * - Sequence for display software to allow package C8+
9520 * The steps implemented here are just the steps that actually touch the LCPLL
9521 * register. Callers should take care of disabling all the display engine
9522 * functions, doing the mode unset, fixing interrupts, etc.
9523 */
9524 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9525 bool switch_to_fclk, bool allow_power_down)
9526 {
9527 uint32_t val;
9528
9529 assert_can_disable_lcpll(dev_priv);
9530
9531 val = I915_READ(LCPLL_CTL);
9532
9533 if (switch_to_fclk) {
9534 val |= LCPLL_CD_SOURCE_FCLK;
9535 I915_WRITE(LCPLL_CTL, val);
9536
9537 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9538 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9539 DRM_ERROR("Switching to FCLK failed\n");
9540
9541 val = I915_READ(LCPLL_CTL);
9542 }
9543
9544 val |= LCPLL_PLL_DISABLE;
9545 I915_WRITE(LCPLL_CTL, val);
9546 POSTING_READ(LCPLL_CTL);
9547
9548 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9549 DRM_ERROR("LCPLL still locked\n");
9550
9551 val = hsw_read_dcomp(dev_priv);
9552 val |= D_COMP_COMP_DISABLE;
9553 hsw_write_dcomp(dev_priv, val);
9554 ndelay(100);
9555
9556 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9557 1))
9558 DRM_ERROR("D_COMP RCOMP still in progress\n");
9559
9560 if (allow_power_down) {
9561 val = I915_READ(LCPLL_CTL);
9562 val |= LCPLL_POWER_DOWN_ALLOW;
9563 I915_WRITE(LCPLL_CTL, val);
9564 POSTING_READ(LCPLL_CTL);
9565 }
9566 }
9567
9568 /*
9569 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9570 * source.
9571 */
9572 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9573 {
9574 uint32_t val;
9575
9576 val = I915_READ(LCPLL_CTL);
9577
9578 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9579 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9580 return;
9581
9582 /*
9583 * Make sure we're not on PC8 state before disabling PC8, otherwise
9584 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9585 */
9586 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9587
9588 if (val & LCPLL_POWER_DOWN_ALLOW) {
9589 val &= ~LCPLL_POWER_DOWN_ALLOW;
9590 I915_WRITE(LCPLL_CTL, val);
9591 POSTING_READ(LCPLL_CTL);
9592 }
9593
9594 val = hsw_read_dcomp(dev_priv);
9595 val |= D_COMP_COMP_FORCE;
9596 val &= ~D_COMP_COMP_DISABLE;
9597 hsw_write_dcomp(dev_priv, val);
9598
9599 val = I915_READ(LCPLL_CTL);
9600 val &= ~LCPLL_PLL_DISABLE;
9601 I915_WRITE(LCPLL_CTL, val);
9602
9603 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9604 DRM_ERROR("LCPLL not locked yet\n");
9605
9606 if (val & LCPLL_CD_SOURCE_FCLK) {
9607 val = I915_READ(LCPLL_CTL);
9608 val &= ~LCPLL_CD_SOURCE_FCLK;
9609 I915_WRITE(LCPLL_CTL, val);
9610
9611 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9612 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9613 DRM_ERROR("Switching back to LCPLL failed\n");
9614 }
9615
9616 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9617 intel_update_cdclk(dev_priv->dev);
9618 }
9619
9620 /*
9621 * Package states C8 and deeper are really deep PC states that can only be
9622 * reached when all the devices on the system allow it, so even if the graphics
9623 * device allows PC8+, it doesn't mean the system will actually get to these
9624 * states. Our driver only allows PC8+ when going into runtime PM.
9625 *
9626 * The requirements for PC8+ are that all the outputs are disabled, the power
9627 * well is disabled and most interrupts are disabled, and these are also
9628 * requirements for runtime PM. When these conditions are met, we manually do
9629 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9630 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9631 * hang the machine.
9632 *
9633 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9634 * the state of some registers, so when we come back from PC8+ we need to
9635 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9636 * need to take care of the registers kept by RC6. Notice that this happens even
9637 * if we don't put the device in PCI D3 state (which is what currently happens
9638 * because of the runtime PM support).
9639 *
9640 * For more, read "Display Sequences for Package C8" on the hardware
9641 * documentation.
9642 */
9643 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9644 {
9645 struct drm_device *dev = dev_priv->dev;
9646 uint32_t val;
9647
9648 DRM_DEBUG_KMS("Enabling package C8+\n");
9649
9650 if (HAS_PCH_LPT_LP(dev)) {
9651 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9652 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9653 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9654 }
9655
9656 lpt_disable_clkout_dp(dev);
9657 hsw_disable_lcpll(dev_priv, true, true);
9658 }
9659
9660 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9661 {
9662 struct drm_device *dev = dev_priv->dev;
9663 uint32_t val;
9664
9665 DRM_DEBUG_KMS("Disabling package C8+\n");
9666
9667 hsw_restore_lcpll(dev_priv);
9668 lpt_init_pch_refclk(dev);
9669
9670 if (HAS_PCH_LPT_LP(dev)) {
9671 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9672 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9673 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9674 }
9675 }
9676
9677 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9678 {
9679 struct drm_device *dev = old_state->dev;
9680 struct intel_atomic_state *old_intel_state =
9681 to_intel_atomic_state(old_state);
9682 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9683
9684 broxton_set_cdclk(dev, req_cdclk);
9685 }
9686
9687 /* compute the max rate for new configuration */
9688 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9689 {
9690 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9691 struct drm_i915_private *dev_priv = state->dev->dev_private;
9692 struct drm_crtc *crtc;
9693 struct drm_crtc_state *cstate;
9694 struct intel_crtc_state *crtc_state;
9695 unsigned max_pixel_rate = 0, i;
9696 enum pipe pipe;
9697
9698 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9699 sizeof(intel_state->min_pixclk));
9700
9701 for_each_crtc_in_state(state, crtc, cstate, i) {
9702 int pixel_rate;
9703
9704 crtc_state = to_intel_crtc_state(cstate);
9705 if (!crtc_state->base.enable) {
9706 intel_state->min_pixclk[i] = 0;
9707 continue;
9708 }
9709
9710 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9711
9712 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9713 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9714 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9715
9716 intel_state->min_pixclk[i] = pixel_rate;
9717 }
9718
9719 if (!intel_state->active_crtcs)
9720 return 0;
9721
9722 for_each_pipe(dev_priv, pipe)
9723 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9724
9725 return max_pixel_rate;
9726 }
9727
9728 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9729 {
9730 struct drm_i915_private *dev_priv = dev->dev_private;
9731 uint32_t val, data;
9732 int ret;
9733
9734 if (WARN((I915_READ(LCPLL_CTL) &
9735 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9736 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9737 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9738 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9739 "trying to change cdclk frequency with cdclk not enabled\n"))
9740 return;
9741
9742 mutex_lock(&dev_priv->rps.hw_lock);
9743 ret = sandybridge_pcode_write(dev_priv,
9744 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9745 mutex_unlock(&dev_priv->rps.hw_lock);
9746 if (ret) {
9747 DRM_ERROR("failed to inform pcode about cdclk change\n");
9748 return;
9749 }
9750
9751 val = I915_READ(LCPLL_CTL);
9752 val |= LCPLL_CD_SOURCE_FCLK;
9753 I915_WRITE(LCPLL_CTL, val);
9754
9755 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9756 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9757 DRM_ERROR("Switching to FCLK failed\n");
9758
9759 val = I915_READ(LCPLL_CTL);
9760 val &= ~LCPLL_CLK_FREQ_MASK;
9761
9762 switch (cdclk) {
9763 case 450000:
9764 val |= LCPLL_CLK_FREQ_450;
9765 data = 0;
9766 break;
9767 case 540000:
9768 val |= LCPLL_CLK_FREQ_54O_BDW;
9769 data = 1;
9770 break;
9771 case 337500:
9772 val |= LCPLL_CLK_FREQ_337_5_BDW;
9773 data = 2;
9774 break;
9775 case 675000:
9776 val |= LCPLL_CLK_FREQ_675_BDW;
9777 data = 3;
9778 break;
9779 default:
9780 WARN(1, "invalid cdclk frequency\n");
9781 return;
9782 }
9783
9784 I915_WRITE(LCPLL_CTL, val);
9785
9786 val = I915_READ(LCPLL_CTL);
9787 val &= ~LCPLL_CD_SOURCE_FCLK;
9788 I915_WRITE(LCPLL_CTL, val);
9789
9790 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9791 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9792 DRM_ERROR("Switching back to LCPLL failed\n");
9793
9794 mutex_lock(&dev_priv->rps.hw_lock);
9795 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9796 mutex_unlock(&dev_priv->rps.hw_lock);
9797
9798 intel_update_cdclk(dev);
9799
9800 WARN(cdclk != dev_priv->cdclk_freq,
9801 "cdclk requested %d kHz but got %d kHz\n",
9802 cdclk, dev_priv->cdclk_freq);
9803 }
9804
9805 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9806 {
9807 struct drm_i915_private *dev_priv = to_i915(state->dev);
9808 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9809 int max_pixclk = ilk_max_pixel_rate(state);
9810 int cdclk;
9811
9812 /*
9813 * FIXME should also account for plane ratio
9814 * once 64bpp pixel formats are supported.
9815 */
9816 if (max_pixclk > 540000)
9817 cdclk = 675000;
9818 else if (max_pixclk > 450000)
9819 cdclk = 540000;
9820 else if (max_pixclk > 337500)
9821 cdclk = 450000;
9822 else
9823 cdclk = 337500;
9824
9825 if (cdclk > dev_priv->max_cdclk_freq) {
9826 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9827 cdclk, dev_priv->max_cdclk_freq);
9828 return -EINVAL;
9829 }
9830
9831 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9832 if (!intel_state->active_crtcs)
9833 intel_state->dev_cdclk = 337500;
9834
9835 return 0;
9836 }
9837
9838 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9839 {
9840 struct drm_device *dev = old_state->dev;
9841 struct intel_atomic_state *old_intel_state =
9842 to_intel_atomic_state(old_state);
9843 unsigned req_cdclk = old_intel_state->dev_cdclk;
9844
9845 broadwell_set_cdclk(dev, req_cdclk);
9846 }
9847
9848 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9849 struct intel_crtc_state *crtc_state)
9850 {
9851 struct intel_encoder *intel_encoder =
9852 intel_ddi_get_crtc_new_encoder(crtc_state);
9853
9854 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9855 if (!intel_ddi_pll_select(crtc, crtc_state))
9856 return -EINVAL;
9857 }
9858
9859 crtc->lowfreq_avail = false;
9860
9861 return 0;
9862 }
9863
9864 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9865 enum port port,
9866 struct intel_crtc_state *pipe_config)
9867 {
9868 switch (port) {
9869 case PORT_A:
9870 pipe_config->ddi_pll_sel = SKL_DPLL0;
9871 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9872 break;
9873 case PORT_B:
9874 pipe_config->ddi_pll_sel = SKL_DPLL1;
9875 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9876 break;
9877 case PORT_C:
9878 pipe_config->ddi_pll_sel = SKL_DPLL2;
9879 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9880 break;
9881 default:
9882 DRM_ERROR("Incorrect port type\n");
9883 }
9884 }
9885
9886 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9887 enum port port,
9888 struct intel_crtc_state *pipe_config)
9889 {
9890 u32 temp, dpll_ctl1;
9891
9892 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9893 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9894
9895 switch (pipe_config->ddi_pll_sel) {
9896 case SKL_DPLL0:
9897 /*
9898 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9899 * of the shared DPLL framework and thus needs to be read out
9900 * separately
9901 */
9902 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9903 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9904 break;
9905 case SKL_DPLL1:
9906 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9907 break;
9908 case SKL_DPLL2:
9909 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9910 break;
9911 case SKL_DPLL3:
9912 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9913 break;
9914 }
9915 }
9916
9917 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9918 enum port port,
9919 struct intel_crtc_state *pipe_config)
9920 {
9921 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9922
9923 switch (pipe_config->ddi_pll_sel) {
9924 case PORT_CLK_SEL_WRPLL1:
9925 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9926 break;
9927 case PORT_CLK_SEL_WRPLL2:
9928 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9929 break;
9930 case PORT_CLK_SEL_SPLL:
9931 pipe_config->shared_dpll = DPLL_ID_SPLL;
9932 break;
9933 }
9934 }
9935
9936 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9937 struct intel_crtc_state *pipe_config)
9938 {
9939 struct drm_device *dev = crtc->base.dev;
9940 struct drm_i915_private *dev_priv = dev->dev_private;
9941 struct intel_shared_dpll *pll;
9942 enum port port;
9943 uint32_t tmp;
9944
9945 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9946
9947 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9948
9949 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9950 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9951 else if (IS_BROXTON(dev))
9952 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9953 else
9954 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9955
9956 if (pipe_config->shared_dpll >= 0) {
9957 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9958
9959 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9960 &pipe_config->dpll_hw_state));
9961 }
9962
9963 /*
9964 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9965 * DDI E. So just check whether this pipe is wired to DDI E and whether
9966 * the PCH transcoder is on.
9967 */
9968 if (INTEL_INFO(dev)->gen < 9 &&
9969 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9970 pipe_config->has_pch_encoder = true;
9971
9972 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9973 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9974 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9975
9976 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9977 }
9978 }
9979
9980 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9981 struct intel_crtc_state *pipe_config)
9982 {
9983 struct drm_device *dev = crtc->base.dev;
9984 struct drm_i915_private *dev_priv = dev->dev_private;
9985 enum intel_display_power_domain pfit_domain;
9986 uint32_t tmp;
9987
9988 if (!intel_display_power_is_enabled(dev_priv,
9989 POWER_DOMAIN_PIPE(crtc->pipe)))
9990 return false;
9991
9992 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9993 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9994
9995 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9996 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9997 enum pipe trans_edp_pipe;
9998 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9999 default:
10000 WARN(1, "unknown pipe linked to edp transcoder\n");
10001 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10002 case TRANS_DDI_EDP_INPUT_A_ON:
10003 trans_edp_pipe = PIPE_A;
10004 break;
10005 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10006 trans_edp_pipe = PIPE_B;
10007 break;
10008 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10009 trans_edp_pipe = PIPE_C;
10010 break;
10011 }
10012
10013 if (trans_edp_pipe == crtc->pipe)
10014 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10015 }
10016
10017 if (!intel_display_power_is_enabled(dev_priv,
10018 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
10019 return false;
10020
10021 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10022 if (!(tmp & PIPECONF_ENABLE))
10023 return false;
10024
10025 haswell_get_ddi_port_state(crtc, pipe_config);
10026
10027 intel_get_pipe_timings(crtc, pipe_config);
10028
10029 if (INTEL_INFO(dev)->gen >= 9) {
10030 skl_init_scalers(dev, crtc, pipe_config);
10031 }
10032
10033 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10034
10035 if (INTEL_INFO(dev)->gen >= 9) {
10036 pipe_config->scaler_state.scaler_id = -1;
10037 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10038 }
10039
10040 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
10041 if (INTEL_INFO(dev)->gen >= 9)
10042 skylake_get_pfit_config(crtc, pipe_config);
10043 else
10044 ironlake_get_pfit_config(crtc, pipe_config);
10045 }
10046
10047 if (IS_HASWELL(dev))
10048 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10049 (I915_READ(IPS_CTL) & IPS_ENABLE);
10050
10051 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10052 pipe_config->pixel_multiplier =
10053 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10054 } else {
10055 pipe_config->pixel_multiplier = 1;
10056 }
10057
10058 return true;
10059 }
10060
10061 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10062 const struct intel_plane_state *plane_state)
10063 {
10064 struct drm_device *dev = crtc->dev;
10065 struct drm_i915_private *dev_priv = dev->dev_private;
10066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10067 uint32_t cntl = 0, size = 0;
10068
10069 if (plane_state && plane_state->visible) {
10070 unsigned int width = plane_state->base.crtc_w;
10071 unsigned int height = plane_state->base.crtc_h;
10072 unsigned int stride = roundup_pow_of_two(width) * 4;
10073
10074 switch (stride) {
10075 default:
10076 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10077 width, stride);
10078 stride = 256;
10079 /* fallthrough */
10080 case 256:
10081 case 512:
10082 case 1024:
10083 case 2048:
10084 break;
10085 }
10086
10087 cntl |= CURSOR_ENABLE |
10088 CURSOR_GAMMA_ENABLE |
10089 CURSOR_FORMAT_ARGB |
10090 CURSOR_STRIDE(stride);
10091
10092 size = (height << 12) | width;
10093 }
10094
10095 if (intel_crtc->cursor_cntl != 0 &&
10096 (intel_crtc->cursor_base != base ||
10097 intel_crtc->cursor_size != size ||
10098 intel_crtc->cursor_cntl != cntl)) {
10099 /* On these chipsets we can only modify the base/size/stride
10100 * whilst the cursor is disabled.
10101 */
10102 I915_WRITE(CURCNTR(PIPE_A), 0);
10103 POSTING_READ(CURCNTR(PIPE_A));
10104 intel_crtc->cursor_cntl = 0;
10105 }
10106
10107 if (intel_crtc->cursor_base != base) {
10108 I915_WRITE(CURBASE(PIPE_A), base);
10109 intel_crtc->cursor_base = base;
10110 }
10111
10112 if (intel_crtc->cursor_size != size) {
10113 I915_WRITE(CURSIZE, size);
10114 intel_crtc->cursor_size = size;
10115 }
10116
10117 if (intel_crtc->cursor_cntl != cntl) {
10118 I915_WRITE(CURCNTR(PIPE_A), cntl);
10119 POSTING_READ(CURCNTR(PIPE_A));
10120 intel_crtc->cursor_cntl = cntl;
10121 }
10122 }
10123
10124 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10125 const struct intel_plane_state *plane_state)
10126 {
10127 struct drm_device *dev = crtc->dev;
10128 struct drm_i915_private *dev_priv = dev->dev_private;
10129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10130 int pipe = intel_crtc->pipe;
10131 uint32_t cntl = 0;
10132
10133 if (plane_state && plane_state->visible) {
10134 cntl = MCURSOR_GAMMA_ENABLE;
10135 switch (plane_state->base.crtc_w) {
10136 case 64:
10137 cntl |= CURSOR_MODE_64_ARGB_AX;
10138 break;
10139 case 128:
10140 cntl |= CURSOR_MODE_128_ARGB_AX;
10141 break;
10142 case 256:
10143 cntl |= CURSOR_MODE_256_ARGB_AX;
10144 break;
10145 default:
10146 MISSING_CASE(plane_state->base.crtc_w);
10147 return;
10148 }
10149 cntl |= pipe << 28; /* Connect to correct pipe */
10150
10151 if (HAS_DDI(dev))
10152 cntl |= CURSOR_PIPE_CSC_ENABLE;
10153
10154 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10155 cntl |= CURSOR_ROTATE_180;
10156 }
10157
10158 if (intel_crtc->cursor_cntl != cntl) {
10159 I915_WRITE(CURCNTR(pipe), cntl);
10160 POSTING_READ(CURCNTR(pipe));
10161 intel_crtc->cursor_cntl = cntl;
10162 }
10163
10164 /* and commit changes on next vblank */
10165 I915_WRITE(CURBASE(pipe), base);
10166 POSTING_READ(CURBASE(pipe));
10167
10168 intel_crtc->cursor_base = base;
10169 }
10170
10171 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10172 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10173 const struct intel_plane_state *plane_state)
10174 {
10175 struct drm_device *dev = crtc->dev;
10176 struct drm_i915_private *dev_priv = dev->dev_private;
10177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10178 int pipe = intel_crtc->pipe;
10179 u32 base = intel_crtc->cursor_addr;
10180 u32 pos = 0;
10181
10182 if (plane_state) {
10183 int x = plane_state->base.crtc_x;
10184 int y = plane_state->base.crtc_y;
10185
10186 if (x < 0) {
10187 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10188 x = -x;
10189 }
10190 pos |= x << CURSOR_X_SHIFT;
10191
10192 if (y < 0) {
10193 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10194 y = -y;
10195 }
10196 pos |= y << CURSOR_Y_SHIFT;
10197
10198 /* ILK+ do this automagically */
10199 if (HAS_GMCH_DISPLAY(dev) &&
10200 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10201 base += (plane_state->base.crtc_h *
10202 plane_state->base.crtc_w - 1) * 4;
10203 }
10204 }
10205
10206 I915_WRITE(CURPOS(pipe), pos);
10207
10208 if (IS_845G(dev) || IS_I865G(dev))
10209 i845_update_cursor(crtc, base, plane_state);
10210 else
10211 i9xx_update_cursor(crtc, base, plane_state);
10212 }
10213
10214 static bool cursor_size_ok(struct drm_device *dev,
10215 uint32_t width, uint32_t height)
10216 {
10217 if (width == 0 || height == 0)
10218 return false;
10219
10220 /*
10221 * 845g/865g are special in that they are only limited by
10222 * the width of their cursors, the height is arbitrary up to
10223 * the precision of the register. Everything else requires
10224 * square cursors, limited to a few power-of-two sizes.
10225 */
10226 if (IS_845G(dev) || IS_I865G(dev)) {
10227 if ((width & 63) != 0)
10228 return false;
10229
10230 if (width > (IS_845G(dev) ? 64 : 512))
10231 return false;
10232
10233 if (height > 1023)
10234 return false;
10235 } else {
10236 switch (width | height) {
10237 case 256:
10238 case 128:
10239 if (IS_GEN2(dev))
10240 return false;
10241 case 64:
10242 break;
10243 default:
10244 return false;
10245 }
10246 }
10247
10248 return true;
10249 }
10250
10251 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10252 u16 *blue, uint32_t start, uint32_t size)
10253 {
10254 int end = (start + size > 256) ? 256 : start + size, i;
10255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10256
10257 for (i = start; i < end; i++) {
10258 intel_crtc->lut_r[i] = red[i] >> 8;
10259 intel_crtc->lut_g[i] = green[i] >> 8;
10260 intel_crtc->lut_b[i] = blue[i] >> 8;
10261 }
10262
10263 intel_crtc_load_lut(crtc);
10264 }
10265
10266 /* VESA 640x480x72Hz mode to set on the pipe */
10267 static struct drm_display_mode load_detect_mode = {
10268 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10269 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10270 };
10271
10272 struct drm_framebuffer *
10273 __intel_framebuffer_create(struct drm_device *dev,
10274 struct drm_mode_fb_cmd2 *mode_cmd,
10275 struct drm_i915_gem_object *obj)
10276 {
10277 struct intel_framebuffer *intel_fb;
10278 int ret;
10279
10280 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10281 if (!intel_fb)
10282 return ERR_PTR(-ENOMEM);
10283
10284 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10285 if (ret)
10286 goto err;
10287
10288 return &intel_fb->base;
10289
10290 err:
10291 kfree(intel_fb);
10292 return ERR_PTR(ret);
10293 }
10294
10295 static struct drm_framebuffer *
10296 intel_framebuffer_create(struct drm_device *dev,
10297 struct drm_mode_fb_cmd2 *mode_cmd,
10298 struct drm_i915_gem_object *obj)
10299 {
10300 struct drm_framebuffer *fb;
10301 int ret;
10302
10303 ret = i915_mutex_lock_interruptible(dev);
10304 if (ret)
10305 return ERR_PTR(ret);
10306 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10307 mutex_unlock(&dev->struct_mutex);
10308
10309 return fb;
10310 }
10311
10312 static u32
10313 intel_framebuffer_pitch_for_width(int width, int bpp)
10314 {
10315 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10316 return ALIGN(pitch, 64);
10317 }
10318
10319 static u32
10320 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10321 {
10322 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10323 return PAGE_ALIGN(pitch * mode->vdisplay);
10324 }
10325
10326 static struct drm_framebuffer *
10327 intel_framebuffer_create_for_mode(struct drm_device *dev,
10328 struct drm_display_mode *mode,
10329 int depth, int bpp)
10330 {
10331 struct drm_framebuffer *fb;
10332 struct drm_i915_gem_object *obj;
10333 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10334
10335 obj = i915_gem_alloc_object(dev,
10336 intel_framebuffer_size_for_mode(mode, bpp));
10337 if (obj == NULL)
10338 return ERR_PTR(-ENOMEM);
10339
10340 mode_cmd.width = mode->hdisplay;
10341 mode_cmd.height = mode->vdisplay;
10342 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10343 bpp);
10344 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10345
10346 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10347 if (IS_ERR(fb))
10348 drm_gem_object_unreference_unlocked(&obj->base);
10349
10350 return fb;
10351 }
10352
10353 static struct drm_framebuffer *
10354 mode_fits_in_fbdev(struct drm_device *dev,
10355 struct drm_display_mode *mode)
10356 {
10357 #ifdef CONFIG_DRM_FBDEV_EMULATION
10358 struct drm_i915_private *dev_priv = dev->dev_private;
10359 struct drm_i915_gem_object *obj;
10360 struct drm_framebuffer *fb;
10361
10362 if (!dev_priv->fbdev)
10363 return NULL;
10364
10365 if (!dev_priv->fbdev->fb)
10366 return NULL;
10367
10368 obj = dev_priv->fbdev->fb->obj;
10369 BUG_ON(!obj);
10370
10371 fb = &dev_priv->fbdev->fb->base;
10372 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10373 fb->bits_per_pixel))
10374 return NULL;
10375
10376 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10377 return NULL;
10378
10379 return fb;
10380 #else
10381 return NULL;
10382 #endif
10383 }
10384
10385 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10386 struct drm_crtc *crtc,
10387 struct drm_display_mode *mode,
10388 struct drm_framebuffer *fb,
10389 int x, int y)
10390 {
10391 struct drm_plane_state *plane_state;
10392 int hdisplay, vdisplay;
10393 int ret;
10394
10395 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10396 if (IS_ERR(plane_state))
10397 return PTR_ERR(plane_state);
10398
10399 if (mode)
10400 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10401 else
10402 hdisplay = vdisplay = 0;
10403
10404 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10405 if (ret)
10406 return ret;
10407 drm_atomic_set_fb_for_plane(plane_state, fb);
10408 plane_state->crtc_x = 0;
10409 plane_state->crtc_y = 0;
10410 plane_state->crtc_w = hdisplay;
10411 plane_state->crtc_h = vdisplay;
10412 plane_state->src_x = x << 16;
10413 plane_state->src_y = y << 16;
10414 plane_state->src_w = hdisplay << 16;
10415 plane_state->src_h = vdisplay << 16;
10416
10417 return 0;
10418 }
10419
10420 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10421 struct drm_display_mode *mode,
10422 struct intel_load_detect_pipe *old,
10423 struct drm_modeset_acquire_ctx *ctx)
10424 {
10425 struct intel_crtc *intel_crtc;
10426 struct intel_encoder *intel_encoder =
10427 intel_attached_encoder(connector);
10428 struct drm_crtc *possible_crtc;
10429 struct drm_encoder *encoder = &intel_encoder->base;
10430 struct drm_crtc *crtc = NULL;
10431 struct drm_device *dev = encoder->dev;
10432 struct drm_framebuffer *fb;
10433 struct drm_mode_config *config = &dev->mode_config;
10434 struct drm_atomic_state *state = NULL;
10435 struct drm_connector_state *connector_state;
10436 struct intel_crtc_state *crtc_state;
10437 int ret, i = -1;
10438
10439 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10440 connector->base.id, connector->name,
10441 encoder->base.id, encoder->name);
10442
10443 retry:
10444 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10445 if (ret)
10446 goto fail;
10447
10448 /*
10449 * Algorithm gets a little messy:
10450 *
10451 * - if the connector already has an assigned crtc, use it (but make
10452 * sure it's on first)
10453 *
10454 * - try to find the first unused crtc that can drive this connector,
10455 * and use that if we find one
10456 */
10457
10458 /* See if we already have a CRTC for this connector */
10459 if (encoder->crtc) {
10460 crtc = encoder->crtc;
10461
10462 ret = drm_modeset_lock(&crtc->mutex, ctx);
10463 if (ret)
10464 goto fail;
10465 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10466 if (ret)
10467 goto fail;
10468
10469 old->dpms_mode = connector->dpms;
10470 old->load_detect_temp = false;
10471
10472 /* Make sure the crtc and connector are running */
10473 if (connector->dpms != DRM_MODE_DPMS_ON)
10474 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10475
10476 return true;
10477 }
10478
10479 /* Find an unused one (if possible) */
10480 for_each_crtc(dev, possible_crtc) {
10481 i++;
10482 if (!(encoder->possible_crtcs & (1 << i)))
10483 continue;
10484 if (possible_crtc->state->enable)
10485 continue;
10486
10487 crtc = possible_crtc;
10488 break;
10489 }
10490
10491 /*
10492 * If we didn't find an unused CRTC, don't use any.
10493 */
10494 if (!crtc) {
10495 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10496 goto fail;
10497 }
10498
10499 ret = drm_modeset_lock(&crtc->mutex, ctx);
10500 if (ret)
10501 goto fail;
10502 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10503 if (ret)
10504 goto fail;
10505
10506 intel_crtc = to_intel_crtc(crtc);
10507 old->dpms_mode = connector->dpms;
10508 old->load_detect_temp = true;
10509 old->release_fb = NULL;
10510
10511 state = drm_atomic_state_alloc(dev);
10512 if (!state)
10513 return false;
10514
10515 state->acquire_ctx = ctx;
10516
10517 connector_state = drm_atomic_get_connector_state(state, connector);
10518 if (IS_ERR(connector_state)) {
10519 ret = PTR_ERR(connector_state);
10520 goto fail;
10521 }
10522
10523 connector_state->crtc = crtc;
10524
10525 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10526 if (IS_ERR(crtc_state)) {
10527 ret = PTR_ERR(crtc_state);
10528 goto fail;
10529 }
10530
10531 crtc_state->base.active = crtc_state->base.enable = true;
10532
10533 if (!mode)
10534 mode = &load_detect_mode;
10535
10536 /* We need a framebuffer large enough to accommodate all accesses
10537 * that the plane may generate whilst we perform load detection.
10538 * We can not rely on the fbcon either being present (we get called
10539 * during its initialisation to detect all boot displays, or it may
10540 * not even exist) or that it is large enough to satisfy the
10541 * requested mode.
10542 */
10543 fb = mode_fits_in_fbdev(dev, mode);
10544 if (fb == NULL) {
10545 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10546 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10547 old->release_fb = fb;
10548 } else
10549 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10550 if (IS_ERR(fb)) {
10551 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10552 goto fail;
10553 }
10554
10555 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10556 if (ret)
10557 goto fail;
10558
10559 drm_mode_copy(&crtc_state->base.mode, mode);
10560
10561 if (drm_atomic_commit(state)) {
10562 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10563 if (old->release_fb)
10564 old->release_fb->funcs->destroy(old->release_fb);
10565 goto fail;
10566 }
10567 crtc->primary->crtc = crtc;
10568
10569 /* let the connector get through one full cycle before testing */
10570 intel_wait_for_vblank(dev, intel_crtc->pipe);
10571 return true;
10572
10573 fail:
10574 drm_atomic_state_free(state);
10575 state = NULL;
10576
10577 if (ret == -EDEADLK) {
10578 drm_modeset_backoff(ctx);
10579 goto retry;
10580 }
10581
10582 return false;
10583 }
10584
10585 void intel_release_load_detect_pipe(struct drm_connector *connector,
10586 struct intel_load_detect_pipe *old,
10587 struct drm_modeset_acquire_ctx *ctx)
10588 {
10589 struct drm_device *dev = connector->dev;
10590 struct intel_encoder *intel_encoder =
10591 intel_attached_encoder(connector);
10592 struct drm_encoder *encoder = &intel_encoder->base;
10593 struct drm_crtc *crtc = encoder->crtc;
10594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10595 struct drm_atomic_state *state;
10596 struct drm_connector_state *connector_state;
10597 struct intel_crtc_state *crtc_state;
10598 int ret;
10599
10600 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10601 connector->base.id, connector->name,
10602 encoder->base.id, encoder->name);
10603
10604 if (old->load_detect_temp) {
10605 state = drm_atomic_state_alloc(dev);
10606 if (!state)
10607 goto fail;
10608
10609 state->acquire_ctx = ctx;
10610
10611 connector_state = drm_atomic_get_connector_state(state, connector);
10612 if (IS_ERR(connector_state))
10613 goto fail;
10614
10615 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10616 if (IS_ERR(crtc_state))
10617 goto fail;
10618
10619 connector_state->crtc = NULL;
10620
10621 crtc_state->base.enable = crtc_state->base.active = false;
10622
10623 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10624 0, 0);
10625 if (ret)
10626 goto fail;
10627
10628 ret = drm_atomic_commit(state);
10629 if (ret)
10630 goto fail;
10631
10632 if (old->release_fb) {
10633 drm_framebuffer_unregister_private(old->release_fb);
10634 drm_framebuffer_unreference(old->release_fb);
10635 }
10636
10637 return;
10638 }
10639
10640 /* Switch crtc and encoder back off if necessary */
10641 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10642 connector->funcs->dpms(connector, old->dpms_mode);
10643
10644 return;
10645 fail:
10646 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10647 drm_atomic_state_free(state);
10648 }
10649
10650 static int i9xx_pll_refclk(struct drm_device *dev,
10651 const struct intel_crtc_state *pipe_config)
10652 {
10653 struct drm_i915_private *dev_priv = dev->dev_private;
10654 u32 dpll = pipe_config->dpll_hw_state.dpll;
10655
10656 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10657 return dev_priv->vbt.lvds_ssc_freq;
10658 else if (HAS_PCH_SPLIT(dev))
10659 return 120000;
10660 else if (!IS_GEN2(dev))
10661 return 96000;
10662 else
10663 return 48000;
10664 }
10665
10666 /* Returns the clock of the currently programmed mode of the given pipe. */
10667 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10668 struct intel_crtc_state *pipe_config)
10669 {
10670 struct drm_device *dev = crtc->base.dev;
10671 struct drm_i915_private *dev_priv = dev->dev_private;
10672 int pipe = pipe_config->cpu_transcoder;
10673 u32 dpll = pipe_config->dpll_hw_state.dpll;
10674 u32 fp;
10675 intel_clock_t clock;
10676 int port_clock;
10677 int refclk = i9xx_pll_refclk(dev, pipe_config);
10678
10679 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10680 fp = pipe_config->dpll_hw_state.fp0;
10681 else
10682 fp = pipe_config->dpll_hw_state.fp1;
10683
10684 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10685 if (IS_PINEVIEW(dev)) {
10686 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10687 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10688 } else {
10689 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10690 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10691 }
10692
10693 if (!IS_GEN2(dev)) {
10694 if (IS_PINEVIEW(dev))
10695 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10696 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10697 else
10698 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10699 DPLL_FPA01_P1_POST_DIV_SHIFT);
10700
10701 switch (dpll & DPLL_MODE_MASK) {
10702 case DPLLB_MODE_DAC_SERIAL:
10703 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10704 5 : 10;
10705 break;
10706 case DPLLB_MODE_LVDS:
10707 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10708 7 : 14;
10709 break;
10710 default:
10711 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10712 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10713 return;
10714 }
10715
10716 if (IS_PINEVIEW(dev))
10717 port_clock = pnv_calc_dpll_params(refclk, &clock);
10718 else
10719 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10720 } else {
10721 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10722 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10723
10724 if (is_lvds) {
10725 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10726 DPLL_FPA01_P1_POST_DIV_SHIFT);
10727
10728 if (lvds & LVDS_CLKB_POWER_UP)
10729 clock.p2 = 7;
10730 else
10731 clock.p2 = 14;
10732 } else {
10733 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10734 clock.p1 = 2;
10735 else {
10736 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10737 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10738 }
10739 if (dpll & PLL_P2_DIVIDE_BY_4)
10740 clock.p2 = 4;
10741 else
10742 clock.p2 = 2;
10743 }
10744
10745 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10746 }
10747
10748 /*
10749 * This value includes pixel_multiplier. We will use
10750 * port_clock to compute adjusted_mode.crtc_clock in the
10751 * encoder's get_config() function.
10752 */
10753 pipe_config->port_clock = port_clock;
10754 }
10755
10756 int intel_dotclock_calculate(int link_freq,
10757 const struct intel_link_m_n *m_n)
10758 {
10759 /*
10760 * The calculation for the data clock is:
10761 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10762 * But we want to avoid losing precison if possible, so:
10763 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10764 *
10765 * and the link clock is simpler:
10766 * link_clock = (m * link_clock) / n
10767 */
10768
10769 if (!m_n->link_n)
10770 return 0;
10771
10772 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10773 }
10774
10775 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10776 struct intel_crtc_state *pipe_config)
10777 {
10778 struct drm_device *dev = crtc->base.dev;
10779
10780 /* read out port_clock from the DPLL */
10781 i9xx_crtc_clock_get(crtc, pipe_config);
10782
10783 /*
10784 * This value does not include pixel_multiplier.
10785 * We will check that port_clock and adjusted_mode.crtc_clock
10786 * agree once we know their relationship in the encoder's
10787 * get_config() function.
10788 */
10789 pipe_config->base.adjusted_mode.crtc_clock =
10790 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10791 &pipe_config->fdi_m_n);
10792 }
10793
10794 /** Returns the currently programmed mode of the given pipe. */
10795 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10796 struct drm_crtc *crtc)
10797 {
10798 struct drm_i915_private *dev_priv = dev->dev_private;
10799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10800 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10801 struct drm_display_mode *mode;
10802 struct intel_crtc_state *pipe_config;
10803 int htot = I915_READ(HTOTAL(cpu_transcoder));
10804 int hsync = I915_READ(HSYNC(cpu_transcoder));
10805 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10806 int vsync = I915_READ(VSYNC(cpu_transcoder));
10807 enum pipe pipe = intel_crtc->pipe;
10808
10809 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10810 if (!mode)
10811 return NULL;
10812
10813 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10814 if (!pipe_config) {
10815 kfree(mode);
10816 return NULL;
10817 }
10818
10819 /*
10820 * Construct a pipe_config sufficient for getting the clock info
10821 * back out of crtc_clock_get.
10822 *
10823 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10824 * to use a real value here instead.
10825 */
10826 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10827 pipe_config->pixel_multiplier = 1;
10828 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10829 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10830 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10831 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10832
10833 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10834 mode->hdisplay = (htot & 0xffff) + 1;
10835 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10836 mode->hsync_start = (hsync & 0xffff) + 1;
10837 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10838 mode->vdisplay = (vtot & 0xffff) + 1;
10839 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10840 mode->vsync_start = (vsync & 0xffff) + 1;
10841 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10842
10843 drm_mode_set_name(mode);
10844
10845 kfree(pipe_config);
10846
10847 return mode;
10848 }
10849
10850 void intel_mark_busy(struct drm_device *dev)
10851 {
10852 struct drm_i915_private *dev_priv = dev->dev_private;
10853
10854 if (dev_priv->mm.busy)
10855 return;
10856
10857 intel_runtime_pm_get(dev_priv);
10858 i915_update_gfx_val(dev_priv);
10859 if (INTEL_INFO(dev)->gen >= 6)
10860 gen6_rps_busy(dev_priv);
10861 dev_priv->mm.busy = true;
10862 }
10863
10864 void intel_mark_idle(struct drm_device *dev)
10865 {
10866 struct drm_i915_private *dev_priv = dev->dev_private;
10867
10868 if (!dev_priv->mm.busy)
10869 return;
10870
10871 dev_priv->mm.busy = false;
10872
10873 if (INTEL_INFO(dev)->gen >= 6)
10874 gen6_rps_idle(dev->dev_private);
10875
10876 intel_runtime_pm_put(dev_priv);
10877 }
10878
10879 static void intel_crtc_destroy(struct drm_crtc *crtc)
10880 {
10881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10882 struct drm_device *dev = crtc->dev;
10883 struct intel_unpin_work *work;
10884
10885 spin_lock_irq(&dev->event_lock);
10886 work = intel_crtc->unpin_work;
10887 intel_crtc->unpin_work = NULL;
10888 spin_unlock_irq(&dev->event_lock);
10889
10890 if (work) {
10891 cancel_work_sync(&work->work);
10892 kfree(work);
10893 }
10894
10895 drm_crtc_cleanup(crtc);
10896
10897 kfree(intel_crtc);
10898 }
10899
10900 static void intel_unpin_work_fn(struct work_struct *__work)
10901 {
10902 struct intel_unpin_work *work =
10903 container_of(__work, struct intel_unpin_work, work);
10904 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10905 struct drm_device *dev = crtc->base.dev;
10906 struct drm_plane *primary = crtc->base.primary;
10907
10908 mutex_lock(&dev->struct_mutex);
10909 intel_unpin_fb_obj(work->old_fb, primary->state);
10910 drm_gem_object_unreference(&work->pending_flip_obj->base);
10911
10912 if (work->flip_queued_req)
10913 i915_gem_request_assign(&work->flip_queued_req, NULL);
10914 mutex_unlock(&dev->struct_mutex);
10915
10916 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10917 intel_fbc_post_update(crtc);
10918 drm_framebuffer_unreference(work->old_fb);
10919
10920 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10921 atomic_dec(&crtc->unpin_work_count);
10922
10923 kfree(work);
10924 }
10925
10926 static void do_intel_finish_page_flip(struct drm_device *dev,
10927 struct drm_crtc *crtc)
10928 {
10929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10930 struct intel_unpin_work *work;
10931 unsigned long flags;
10932
10933 /* Ignore early vblank irqs */
10934 if (intel_crtc == NULL)
10935 return;
10936
10937 /*
10938 * This is called both by irq handlers and the reset code (to complete
10939 * lost pageflips) so needs the full irqsave spinlocks.
10940 */
10941 spin_lock_irqsave(&dev->event_lock, flags);
10942 work = intel_crtc->unpin_work;
10943
10944 /* Ensure we don't miss a work->pending update ... */
10945 smp_rmb();
10946
10947 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10948 spin_unlock_irqrestore(&dev->event_lock, flags);
10949 return;
10950 }
10951
10952 page_flip_completed(intel_crtc);
10953
10954 spin_unlock_irqrestore(&dev->event_lock, flags);
10955 }
10956
10957 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10958 {
10959 struct drm_i915_private *dev_priv = dev->dev_private;
10960 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10961
10962 do_intel_finish_page_flip(dev, crtc);
10963 }
10964
10965 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10966 {
10967 struct drm_i915_private *dev_priv = dev->dev_private;
10968 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10969
10970 do_intel_finish_page_flip(dev, crtc);
10971 }
10972
10973 /* Is 'a' after or equal to 'b'? */
10974 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10975 {
10976 return !((a - b) & 0x80000000);
10977 }
10978
10979 static bool page_flip_finished(struct intel_crtc *crtc)
10980 {
10981 struct drm_device *dev = crtc->base.dev;
10982 struct drm_i915_private *dev_priv = dev->dev_private;
10983
10984 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10985 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10986 return true;
10987
10988 /*
10989 * The relevant registers doen't exist on pre-ctg.
10990 * As the flip done interrupt doesn't trigger for mmio
10991 * flips on gmch platforms, a flip count check isn't
10992 * really needed there. But since ctg has the registers,
10993 * include it in the check anyway.
10994 */
10995 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10996 return true;
10997
10998 /*
10999 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11000 * used the same base address. In that case the mmio flip might
11001 * have completed, but the CS hasn't even executed the flip yet.
11002 *
11003 * A flip count check isn't enough as the CS might have updated
11004 * the base address just after start of vblank, but before we
11005 * managed to process the interrupt. This means we'd complete the
11006 * CS flip too soon.
11007 *
11008 * Combining both checks should get us a good enough result. It may
11009 * still happen that the CS flip has been executed, but has not
11010 * yet actually completed. But in case the base address is the same
11011 * anyway, we don't really care.
11012 */
11013 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11014 crtc->unpin_work->gtt_offset &&
11015 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11016 crtc->unpin_work->flip_count);
11017 }
11018
11019 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11020 {
11021 struct drm_i915_private *dev_priv = dev->dev_private;
11022 struct intel_crtc *intel_crtc =
11023 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11024 unsigned long flags;
11025
11026
11027 /*
11028 * This is called both by irq handlers and the reset code (to complete
11029 * lost pageflips) so needs the full irqsave spinlocks.
11030 *
11031 * NB: An MMIO update of the plane base pointer will also
11032 * generate a page-flip completion irq, i.e. every modeset
11033 * is also accompanied by a spurious intel_prepare_page_flip().
11034 */
11035 spin_lock_irqsave(&dev->event_lock, flags);
11036 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11037 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11038 spin_unlock_irqrestore(&dev->event_lock, flags);
11039 }
11040
11041 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11042 {
11043 /* Ensure that the work item is consistent when activating it ... */
11044 smp_wmb();
11045 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11046 /* and that it is marked active as soon as the irq could fire. */
11047 smp_wmb();
11048 }
11049
11050 static int intel_gen2_queue_flip(struct drm_device *dev,
11051 struct drm_crtc *crtc,
11052 struct drm_framebuffer *fb,
11053 struct drm_i915_gem_object *obj,
11054 struct drm_i915_gem_request *req,
11055 uint32_t flags)
11056 {
11057 struct intel_engine_cs *ring = req->ring;
11058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11059 u32 flip_mask;
11060 int ret;
11061
11062 ret = intel_ring_begin(req, 6);
11063 if (ret)
11064 return ret;
11065
11066 /* Can't queue multiple flips, so wait for the previous
11067 * one to finish before executing the next.
11068 */
11069 if (intel_crtc->plane)
11070 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11071 else
11072 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11073 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11074 intel_ring_emit(ring, MI_NOOP);
11075 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11076 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11077 intel_ring_emit(ring, fb->pitches[0]);
11078 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11079 intel_ring_emit(ring, 0); /* aux display base address, unused */
11080
11081 intel_mark_page_flip_active(intel_crtc->unpin_work);
11082 return 0;
11083 }
11084
11085 static int intel_gen3_queue_flip(struct drm_device *dev,
11086 struct drm_crtc *crtc,
11087 struct drm_framebuffer *fb,
11088 struct drm_i915_gem_object *obj,
11089 struct drm_i915_gem_request *req,
11090 uint32_t flags)
11091 {
11092 struct intel_engine_cs *ring = req->ring;
11093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11094 u32 flip_mask;
11095 int ret;
11096
11097 ret = intel_ring_begin(req, 6);
11098 if (ret)
11099 return ret;
11100
11101 if (intel_crtc->plane)
11102 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11103 else
11104 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11105 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11106 intel_ring_emit(ring, MI_NOOP);
11107 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11108 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11109 intel_ring_emit(ring, fb->pitches[0]);
11110 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11111 intel_ring_emit(ring, MI_NOOP);
11112
11113 intel_mark_page_flip_active(intel_crtc->unpin_work);
11114 return 0;
11115 }
11116
11117 static int intel_gen4_queue_flip(struct drm_device *dev,
11118 struct drm_crtc *crtc,
11119 struct drm_framebuffer *fb,
11120 struct drm_i915_gem_object *obj,
11121 struct drm_i915_gem_request *req,
11122 uint32_t flags)
11123 {
11124 struct intel_engine_cs *ring = req->ring;
11125 struct drm_i915_private *dev_priv = dev->dev_private;
11126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11127 uint32_t pf, pipesrc;
11128 int ret;
11129
11130 ret = intel_ring_begin(req, 4);
11131 if (ret)
11132 return ret;
11133
11134 /* i965+ uses the linear or tiled offsets from the
11135 * Display Registers (which do not change across a page-flip)
11136 * so we need only reprogram the base address.
11137 */
11138 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11139 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11140 intel_ring_emit(ring, fb->pitches[0]);
11141 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11142 obj->tiling_mode);
11143
11144 /* XXX Enabling the panel-fitter across page-flip is so far
11145 * untested on non-native modes, so ignore it for now.
11146 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11147 */
11148 pf = 0;
11149 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11150 intel_ring_emit(ring, pf | pipesrc);
11151
11152 intel_mark_page_flip_active(intel_crtc->unpin_work);
11153 return 0;
11154 }
11155
11156 static int intel_gen6_queue_flip(struct drm_device *dev,
11157 struct drm_crtc *crtc,
11158 struct drm_framebuffer *fb,
11159 struct drm_i915_gem_object *obj,
11160 struct drm_i915_gem_request *req,
11161 uint32_t flags)
11162 {
11163 struct intel_engine_cs *ring = req->ring;
11164 struct drm_i915_private *dev_priv = dev->dev_private;
11165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11166 uint32_t pf, pipesrc;
11167 int ret;
11168
11169 ret = intel_ring_begin(req, 4);
11170 if (ret)
11171 return ret;
11172
11173 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11174 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11175 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11176 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11177
11178 /* Contrary to the suggestions in the documentation,
11179 * "Enable Panel Fitter" does not seem to be required when page
11180 * flipping with a non-native mode, and worse causes a normal
11181 * modeset to fail.
11182 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11183 */
11184 pf = 0;
11185 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11186 intel_ring_emit(ring, pf | pipesrc);
11187
11188 intel_mark_page_flip_active(intel_crtc->unpin_work);
11189 return 0;
11190 }
11191
11192 static int intel_gen7_queue_flip(struct drm_device *dev,
11193 struct drm_crtc *crtc,
11194 struct drm_framebuffer *fb,
11195 struct drm_i915_gem_object *obj,
11196 struct drm_i915_gem_request *req,
11197 uint32_t flags)
11198 {
11199 struct intel_engine_cs *ring = req->ring;
11200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11201 uint32_t plane_bit = 0;
11202 int len, ret;
11203
11204 switch (intel_crtc->plane) {
11205 case PLANE_A:
11206 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11207 break;
11208 case PLANE_B:
11209 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11210 break;
11211 case PLANE_C:
11212 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11213 break;
11214 default:
11215 WARN_ONCE(1, "unknown plane in flip command\n");
11216 return -ENODEV;
11217 }
11218
11219 len = 4;
11220 if (ring->id == RCS) {
11221 len += 6;
11222 /*
11223 * On Gen 8, SRM is now taking an extra dword to accommodate
11224 * 48bits addresses, and we need a NOOP for the batch size to
11225 * stay even.
11226 */
11227 if (IS_GEN8(dev))
11228 len += 2;
11229 }
11230
11231 /*
11232 * BSpec MI_DISPLAY_FLIP for IVB:
11233 * "The full packet must be contained within the same cache line."
11234 *
11235 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11236 * cacheline, if we ever start emitting more commands before
11237 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11238 * then do the cacheline alignment, and finally emit the
11239 * MI_DISPLAY_FLIP.
11240 */
11241 ret = intel_ring_cacheline_align(req);
11242 if (ret)
11243 return ret;
11244
11245 ret = intel_ring_begin(req, len);
11246 if (ret)
11247 return ret;
11248
11249 /* Unmask the flip-done completion message. Note that the bspec says that
11250 * we should do this for both the BCS and RCS, and that we must not unmask
11251 * more than one flip event at any time (or ensure that one flip message
11252 * can be sent by waiting for flip-done prior to queueing new flips).
11253 * Experimentation says that BCS works despite DERRMR masking all
11254 * flip-done completion events and that unmasking all planes at once
11255 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11256 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11257 */
11258 if (ring->id == RCS) {
11259 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11260 intel_ring_emit_reg(ring, DERRMR);
11261 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11262 DERRMR_PIPEB_PRI_FLIP_DONE |
11263 DERRMR_PIPEC_PRI_FLIP_DONE));
11264 if (IS_GEN8(dev))
11265 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11266 MI_SRM_LRM_GLOBAL_GTT);
11267 else
11268 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11269 MI_SRM_LRM_GLOBAL_GTT);
11270 intel_ring_emit_reg(ring, DERRMR);
11271 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11272 if (IS_GEN8(dev)) {
11273 intel_ring_emit(ring, 0);
11274 intel_ring_emit(ring, MI_NOOP);
11275 }
11276 }
11277
11278 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11279 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11280 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11281 intel_ring_emit(ring, (MI_NOOP));
11282
11283 intel_mark_page_flip_active(intel_crtc->unpin_work);
11284 return 0;
11285 }
11286
11287 static bool use_mmio_flip(struct intel_engine_cs *ring,
11288 struct drm_i915_gem_object *obj)
11289 {
11290 /*
11291 * This is not being used for older platforms, because
11292 * non-availability of flip done interrupt forces us to use
11293 * CS flips. Older platforms derive flip done using some clever
11294 * tricks involving the flip_pending status bits and vblank irqs.
11295 * So using MMIO flips there would disrupt this mechanism.
11296 */
11297
11298 if (ring == NULL)
11299 return true;
11300
11301 if (INTEL_INFO(ring->dev)->gen < 5)
11302 return false;
11303
11304 if (i915.use_mmio_flip < 0)
11305 return false;
11306 else if (i915.use_mmio_flip > 0)
11307 return true;
11308 else if (i915.enable_execlists)
11309 return true;
11310 else if (obj->base.dma_buf &&
11311 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11312 false))
11313 return true;
11314 else
11315 return ring != i915_gem_request_get_ring(obj->last_write_req);
11316 }
11317
11318 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11319 unsigned int rotation,
11320 struct intel_unpin_work *work)
11321 {
11322 struct drm_device *dev = intel_crtc->base.dev;
11323 struct drm_i915_private *dev_priv = dev->dev_private;
11324 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11325 const enum pipe pipe = intel_crtc->pipe;
11326 u32 ctl, stride, tile_height;
11327
11328 ctl = I915_READ(PLANE_CTL(pipe, 0));
11329 ctl &= ~PLANE_CTL_TILED_MASK;
11330 switch (fb->modifier[0]) {
11331 case DRM_FORMAT_MOD_NONE:
11332 break;
11333 case I915_FORMAT_MOD_X_TILED:
11334 ctl |= PLANE_CTL_TILED_X;
11335 break;
11336 case I915_FORMAT_MOD_Y_TILED:
11337 ctl |= PLANE_CTL_TILED_Y;
11338 break;
11339 case I915_FORMAT_MOD_Yf_TILED:
11340 ctl |= PLANE_CTL_TILED_YF;
11341 break;
11342 default:
11343 MISSING_CASE(fb->modifier[0]);
11344 }
11345
11346 /*
11347 * The stride is either expressed as a multiple of 64 bytes chunks for
11348 * linear buffers or in number of tiles for tiled buffers.
11349 */
11350 if (intel_rotation_90_or_270(rotation)) {
11351 /* stride = Surface height in tiles */
11352 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11353 stride = DIV_ROUND_UP(fb->height, tile_height);
11354 } else {
11355 stride = fb->pitches[0] /
11356 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11357 fb->pixel_format);
11358 }
11359
11360 /*
11361 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11362 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11363 */
11364 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11365 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11366
11367 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11368 POSTING_READ(PLANE_SURF(pipe, 0));
11369 }
11370
11371 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11372 struct intel_unpin_work *work)
11373 {
11374 struct drm_device *dev = intel_crtc->base.dev;
11375 struct drm_i915_private *dev_priv = dev->dev_private;
11376 struct intel_framebuffer *intel_fb =
11377 to_intel_framebuffer(intel_crtc->base.primary->fb);
11378 struct drm_i915_gem_object *obj = intel_fb->obj;
11379 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11380 u32 dspcntr;
11381
11382 dspcntr = I915_READ(reg);
11383
11384 if (obj->tiling_mode != I915_TILING_NONE)
11385 dspcntr |= DISPPLANE_TILED;
11386 else
11387 dspcntr &= ~DISPPLANE_TILED;
11388
11389 I915_WRITE(reg, dspcntr);
11390
11391 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11392 POSTING_READ(DSPSURF(intel_crtc->plane));
11393 }
11394
11395 /*
11396 * XXX: This is the temporary way to update the plane registers until we get
11397 * around to using the usual plane update functions for MMIO flips
11398 */
11399 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11400 {
11401 struct intel_crtc *crtc = mmio_flip->crtc;
11402 struct intel_unpin_work *work;
11403
11404 spin_lock_irq(&crtc->base.dev->event_lock);
11405 work = crtc->unpin_work;
11406 spin_unlock_irq(&crtc->base.dev->event_lock);
11407 if (work == NULL)
11408 return;
11409
11410 intel_mark_page_flip_active(work);
11411
11412 intel_pipe_update_start(crtc);
11413
11414 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11415 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11416 else
11417 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11418 ilk_do_mmio_flip(crtc, work);
11419
11420 intel_pipe_update_end(crtc);
11421 }
11422
11423 static void intel_mmio_flip_work_func(struct work_struct *work)
11424 {
11425 struct intel_mmio_flip *mmio_flip =
11426 container_of(work, struct intel_mmio_flip, work);
11427 struct intel_framebuffer *intel_fb =
11428 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11429 struct drm_i915_gem_object *obj = intel_fb->obj;
11430
11431 if (mmio_flip->req) {
11432 WARN_ON(__i915_wait_request(mmio_flip->req,
11433 mmio_flip->crtc->reset_counter,
11434 false, NULL,
11435 &mmio_flip->i915->rps.mmioflips));
11436 i915_gem_request_unreference__unlocked(mmio_flip->req);
11437 }
11438
11439 /* For framebuffer backed by dmabuf, wait for fence */
11440 if (obj->base.dma_buf)
11441 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11442 false, false,
11443 MAX_SCHEDULE_TIMEOUT) < 0);
11444
11445 intel_do_mmio_flip(mmio_flip);
11446 kfree(mmio_flip);
11447 }
11448
11449 static int intel_queue_mmio_flip(struct drm_device *dev,
11450 struct drm_crtc *crtc,
11451 struct drm_i915_gem_object *obj)
11452 {
11453 struct intel_mmio_flip *mmio_flip;
11454
11455 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11456 if (mmio_flip == NULL)
11457 return -ENOMEM;
11458
11459 mmio_flip->i915 = to_i915(dev);
11460 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11461 mmio_flip->crtc = to_intel_crtc(crtc);
11462 mmio_flip->rotation = crtc->primary->state->rotation;
11463
11464 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11465 schedule_work(&mmio_flip->work);
11466
11467 return 0;
11468 }
11469
11470 static int intel_default_queue_flip(struct drm_device *dev,
11471 struct drm_crtc *crtc,
11472 struct drm_framebuffer *fb,
11473 struct drm_i915_gem_object *obj,
11474 struct drm_i915_gem_request *req,
11475 uint32_t flags)
11476 {
11477 return -ENODEV;
11478 }
11479
11480 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11481 struct drm_crtc *crtc)
11482 {
11483 struct drm_i915_private *dev_priv = dev->dev_private;
11484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11485 struct intel_unpin_work *work = intel_crtc->unpin_work;
11486 u32 addr;
11487
11488 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11489 return true;
11490
11491 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11492 return false;
11493
11494 if (!work->enable_stall_check)
11495 return false;
11496
11497 if (work->flip_ready_vblank == 0) {
11498 if (work->flip_queued_req &&
11499 !i915_gem_request_completed(work->flip_queued_req, true))
11500 return false;
11501
11502 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11503 }
11504
11505 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11506 return false;
11507
11508 /* Potential stall - if we see that the flip has happened,
11509 * assume a missed interrupt. */
11510 if (INTEL_INFO(dev)->gen >= 4)
11511 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11512 else
11513 addr = I915_READ(DSPADDR(intel_crtc->plane));
11514
11515 /* There is a potential issue here with a false positive after a flip
11516 * to the same address. We could address this by checking for a
11517 * non-incrementing frame counter.
11518 */
11519 return addr == work->gtt_offset;
11520 }
11521
11522 void intel_check_page_flip(struct drm_device *dev, int pipe)
11523 {
11524 struct drm_i915_private *dev_priv = dev->dev_private;
11525 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11527 struct intel_unpin_work *work;
11528
11529 WARN_ON(!in_interrupt());
11530
11531 if (crtc == NULL)
11532 return;
11533
11534 spin_lock(&dev->event_lock);
11535 work = intel_crtc->unpin_work;
11536 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11537 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11538 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11539 page_flip_completed(intel_crtc);
11540 work = NULL;
11541 }
11542 if (work != NULL &&
11543 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11544 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11545 spin_unlock(&dev->event_lock);
11546 }
11547
11548 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11549 struct drm_framebuffer *fb,
11550 struct drm_pending_vblank_event *event,
11551 uint32_t page_flip_flags)
11552 {
11553 struct drm_device *dev = crtc->dev;
11554 struct drm_i915_private *dev_priv = dev->dev_private;
11555 struct drm_framebuffer *old_fb = crtc->primary->fb;
11556 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11558 struct drm_plane *primary = crtc->primary;
11559 enum pipe pipe = intel_crtc->pipe;
11560 struct intel_unpin_work *work;
11561 struct intel_engine_cs *ring;
11562 bool mmio_flip;
11563 struct drm_i915_gem_request *request = NULL;
11564 int ret;
11565
11566 /*
11567 * drm_mode_page_flip_ioctl() should already catch this, but double
11568 * check to be safe. In the future we may enable pageflipping from
11569 * a disabled primary plane.
11570 */
11571 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11572 return -EBUSY;
11573
11574 /* Can't change pixel format via MI display flips. */
11575 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11576 return -EINVAL;
11577
11578 /*
11579 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11580 * Note that pitch changes could also affect these register.
11581 */
11582 if (INTEL_INFO(dev)->gen > 3 &&
11583 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11584 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11585 return -EINVAL;
11586
11587 if (i915_terminally_wedged(&dev_priv->gpu_error))
11588 goto out_hang;
11589
11590 work = kzalloc(sizeof(*work), GFP_KERNEL);
11591 if (work == NULL)
11592 return -ENOMEM;
11593
11594 work->event = event;
11595 work->crtc = crtc;
11596 work->old_fb = old_fb;
11597 INIT_WORK(&work->work, intel_unpin_work_fn);
11598
11599 ret = drm_crtc_vblank_get(crtc);
11600 if (ret)
11601 goto free_work;
11602
11603 /* We borrow the event spin lock for protecting unpin_work */
11604 spin_lock_irq(&dev->event_lock);
11605 if (intel_crtc->unpin_work) {
11606 /* Before declaring the flip queue wedged, check if
11607 * the hardware completed the operation behind our backs.
11608 */
11609 if (__intel_pageflip_stall_check(dev, crtc)) {
11610 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11611 page_flip_completed(intel_crtc);
11612 } else {
11613 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11614 spin_unlock_irq(&dev->event_lock);
11615
11616 drm_crtc_vblank_put(crtc);
11617 kfree(work);
11618 return -EBUSY;
11619 }
11620 }
11621 intel_crtc->unpin_work = work;
11622 spin_unlock_irq(&dev->event_lock);
11623
11624 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11625 flush_workqueue(dev_priv->wq);
11626
11627 /* Reference the objects for the scheduled work. */
11628 drm_framebuffer_reference(work->old_fb);
11629 drm_gem_object_reference(&obj->base);
11630
11631 crtc->primary->fb = fb;
11632 update_state_fb(crtc->primary);
11633 intel_fbc_pre_update(intel_crtc);
11634
11635 work->pending_flip_obj = obj;
11636
11637 ret = i915_mutex_lock_interruptible(dev);
11638 if (ret)
11639 goto cleanup;
11640
11641 atomic_inc(&intel_crtc->unpin_work_count);
11642 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11643
11644 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11645 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11646
11647 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11648 ring = &dev_priv->ring[BCS];
11649 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11650 /* vlv: DISPLAY_FLIP fails to change tiling */
11651 ring = NULL;
11652 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11653 ring = &dev_priv->ring[BCS];
11654 } else if (INTEL_INFO(dev)->gen >= 7) {
11655 ring = i915_gem_request_get_ring(obj->last_write_req);
11656 if (ring == NULL || ring->id != RCS)
11657 ring = &dev_priv->ring[BCS];
11658 } else {
11659 ring = &dev_priv->ring[RCS];
11660 }
11661
11662 mmio_flip = use_mmio_flip(ring, obj);
11663
11664 /* When using CS flips, we want to emit semaphores between rings.
11665 * However, when using mmio flips we will create a task to do the
11666 * synchronisation, so all we want here is to pin the framebuffer
11667 * into the display plane and skip any waits.
11668 */
11669 if (!mmio_flip) {
11670 ret = i915_gem_object_sync(obj, ring, &request);
11671 if (ret)
11672 goto cleanup_pending;
11673 }
11674
11675 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11676 crtc->primary->state);
11677 if (ret)
11678 goto cleanup_pending;
11679
11680 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11681 obj, 0);
11682 work->gtt_offset += intel_crtc->dspaddr_offset;
11683
11684 if (mmio_flip) {
11685 ret = intel_queue_mmio_flip(dev, crtc, obj);
11686 if (ret)
11687 goto cleanup_unpin;
11688
11689 i915_gem_request_assign(&work->flip_queued_req,
11690 obj->last_write_req);
11691 } else {
11692 if (!request) {
11693 request = i915_gem_request_alloc(ring, NULL);
11694 if (IS_ERR(request)) {
11695 ret = PTR_ERR(request);
11696 goto cleanup_unpin;
11697 }
11698 }
11699
11700 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11701 page_flip_flags);
11702 if (ret)
11703 goto cleanup_unpin;
11704
11705 i915_gem_request_assign(&work->flip_queued_req, request);
11706 }
11707
11708 if (request)
11709 i915_add_request_no_flush(request);
11710
11711 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11712 work->enable_stall_check = true;
11713
11714 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11715 to_intel_plane(primary)->frontbuffer_bit);
11716 mutex_unlock(&dev->struct_mutex);
11717
11718 intel_frontbuffer_flip_prepare(dev,
11719 to_intel_plane(primary)->frontbuffer_bit);
11720
11721 trace_i915_flip_request(intel_crtc->plane, obj);
11722
11723 return 0;
11724
11725 cleanup_unpin:
11726 intel_unpin_fb_obj(fb, crtc->primary->state);
11727 cleanup_pending:
11728 if (!IS_ERR_OR_NULL(request))
11729 i915_gem_request_cancel(request);
11730 atomic_dec(&intel_crtc->unpin_work_count);
11731 mutex_unlock(&dev->struct_mutex);
11732 cleanup:
11733 crtc->primary->fb = old_fb;
11734 update_state_fb(crtc->primary);
11735
11736 drm_gem_object_unreference_unlocked(&obj->base);
11737 drm_framebuffer_unreference(work->old_fb);
11738
11739 spin_lock_irq(&dev->event_lock);
11740 intel_crtc->unpin_work = NULL;
11741 spin_unlock_irq(&dev->event_lock);
11742
11743 drm_crtc_vblank_put(crtc);
11744 free_work:
11745 kfree(work);
11746
11747 if (ret == -EIO) {
11748 struct drm_atomic_state *state;
11749 struct drm_plane_state *plane_state;
11750
11751 out_hang:
11752 state = drm_atomic_state_alloc(dev);
11753 if (!state)
11754 return -ENOMEM;
11755 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11756
11757 retry:
11758 plane_state = drm_atomic_get_plane_state(state, primary);
11759 ret = PTR_ERR_OR_ZERO(plane_state);
11760 if (!ret) {
11761 drm_atomic_set_fb_for_plane(plane_state, fb);
11762
11763 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11764 if (!ret)
11765 ret = drm_atomic_commit(state);
11766 }
11767
11768 if (ret == -EDEADLK) {
11769 drm_modeset_backoff(state->acquire_ctx);
11770 drm_atomic_state_clear(state);
11771 goto retry;
11772 }
11773
11774 if (ret)
11775 drm_atomic_state_free(state);
11776
11777 if (ret == 0 && event) {
11778 spin_lock_irq(&dev->event_lock);
11779 drm_send_vblank_event(dev, pipe, event);
11780 spin_unlock_irq(&dev->event_lock);
11781 }
11782 }
11783 return ret;
11784 }
11785
11786
11787 /**
11788 * intel_wm_need_update - Check whether watermarks need updating
11789 * @plane: drm plane
11790 * @state: new plane state
11791 *
11792 * Check current plane state versus the new one to determine whether
11793 * watermarks need to be recalculated.
11794 *
11795 * Returns true or false.
11796 */
11797 static bool intel_wm_need_update(struct drm_plane *plane,
11798 struct drm_plane_state *state)
11799 {
11800 struct intel_plane_state *new = to_intel_plane_state(state);
11801 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11802
11803 /* Update watermarks on tiling or size changes. */
11804 if (new->visible != cur->visible)
11805 return true;
11806
11807 if (!cur->base.fb || !new->base.fb)
11808 return false;
11809
11810 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11811 cur->base.rotation != new->base.rotation ||
11812 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11813 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11814 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11815 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11816 return true;
11817
11818 return false;
11819 }
11820
11821 static bool needs_scaling(struct intel_plane_state *state)
11822 {
11823 int src_w = drm_rect_width(&state->src) >> 16;
11824 int src_h = drm_rect_height(&state->src) >> 16;
11825 int dst_w = drm_rect_width(&state->dst);
11826 int dst_h = drm_rect_height(&state->dst);
11827
11828 return (src_w != dst_w || src_h != dst_h);
11829 }
11830
11831 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11832 struct drm_plane_state *plane_state)
11833 {
11834 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11835 struct drm_crtc *crtc = crtc_state->crtc;
11836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11837 struct drm_plane *plane = plane_state->plane;
11838 struct drm_device *dev = crtc->dev;
11839 struct intel_plane_state *old_plane_state =
11840 to_intel_plane_state(plane->state);
11841 int idx = intel_crtc->base.base.id, ret;
11842 int i = drm_plane_index(plane);
11843 bool mode_changed = needs_modeset(crtc_state);
11844 bool was_crtc_enabled = crtc->state->active;
11845 bool is_crtc_enabled = crtc_state->active;
11846 bool turn_off, turn_on, visible, was_visible;
11847 struct drm_framebuffer *fb = plane_state->fb;
11848
11849 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11850 plane->type != DRM_PLANE_TYPE_CURSOR) {
11851 ret = skl_update_scaler_plane(
11852 to_intel_crtc_state(crtc_state),
11853 to_intel_plane_state(plane_state));
11854 if (ret)
11855 return ret;
11856 }
11857
11858 was_visible = old_plane_state->visible;
11859 visible = to_intel_plane_state(plane_state)->visible;
11860
11861 if (!was_crtc_enabled && WARN_ON(was_visible))
11862 was_visible = false;
11863
11864 /*
11865 * Visibility is calculated as if the crtc was on, but
11866 * after scaler setup everything depends on it being off
11867 * when the crtc isn't active.
11868 */
11869 if (!is_crtc_enabled)
11870 to_intel_plane_state(plane_state)->visible = visible = false;
11871
11872 if (!was_visible && !visible)
11873 return 0;
11874
11875 turn_off = was_visible && (!visible || mode_changed);
11876 turn_on = visible && (!was_visible || mode_changed);
11877
11878 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11879 plane->base.id, fb ? fb->base.id : -1);
11880
11881 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11882 plane->base.id, was_visible, visible,
11883 turn_off, turn_on, mode_changed);
11884
11885 if (turn_on || turn_off) {
11886 pipe_config->wm_changed = true;
11887
11888 /* must disable cxsr around plane enable/disable */
11889 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11890 if (is_crtc_enabled)
11891 intel_crtc->atomic.wait_vblank = true;
11892 pipe_config->disable_cxsr = true;
11893 }
11894 } else if (intel_wm_need_update(plane, plane_state)) {
11895 pipe_config->wm_changed = true;
11896 }
11897
11898 if (visible || was_visible)
11899 intel_crtc->atomic.fb_bits |=
11900 to_intel_plane(plane)->frontbuffer_bit;
11901
11902 switch (plane->type) {
11903 case DRM_PLANE_TYPE_PRIMARY:
11904 intel_crtc->atomic.post_enable_primary = turn_on;
11905 intel_crtc->atomic.update_fbc = true;
11906
11907 /*
11908 * BDW signals flip done immediately if the plane
11909 * is disabled, even if the plane enable is already
11910 * armed to occur at the next vblank :(
11911 */
11912 if (turn_on && IS_BROADWELL(dev))
11913 intel_crtc->atomic.wait_vblank = true;
11914
11915 break;
11916 case DRM_PLANE_TYPE_CURSOR:
11917 break;
11918 case DRM_PLANE_TYPE_OVERLAY:
11919 /*
11920 * WaCxSRDisabledForSpriteScaling:ivb
11921 *
11922 * cstate->update_wm was already set above, so this flag will
11923 * take effect when we commit and program watermarks.
11924 */
11925 if (IS_IVYBRIDGE(dev) &&
11926 needs_scaling(to_intel_plane_state(plane_state)) &&
11927 !needs_scaling(old_plane_state)) {
11928 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11929 } else if (turn_off && !mode_changed) {
11930 intel_crtc->atomic.wait_vblank = true;
11931 intel_crtc->atomic.update_sprite_watermarks |=
11932 1 << i;
11933 }
11934
11935 break;
11936 }
11937 return 0;
11938 }
11939
11940 static bool encoders_cloneable(const struct intel_encoder *a,
11941 const struct intel_encoder *b)
11942 {
11943 /* masks could be asymmetric, so check both ways */
11944 return a == b || (a->cloneable & (1 << b->type) &&
11945 b->cloneable & (1 << a->type));
11946 }
11947
11948 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11949 struct intel_crtc *crtc,
11950 struct intel_encoder *encoder)
11951 {
11952 struct intel_encoder *source_encoder;
11953 struct drm_connector *connector;
11954 struct drm_connector_state *connector_state;
11955 int i;
11956
11957 for_each_connector_in_state(state, connector, connector_state, i) {
11958 if (connector_state->crtc != &crtc->base)
11959 continue;
11960
11961 source_encoder =
11962 to_intel_encoder(connector_state->best_encoder);
11963 if (!encoders_cloneable(encoder, source_encoder))
11964 return false;
11965 }
11966
11967 return true;
11968 }
11969
11970 static bool check_encoder_cloning(struct drm_atomic_state *state,
11971 struct intel_crtc *crtc)
11972 {
11973 struct intel_encoder *encoder;
11974 struct drm_connector *connector;
11975 struct drm_connector_state *connector_state;
11976 int i;
11977
11978 for_each_connector_in_state(state, connector, connector_state, i) {
11979 if (connector_state->crtc != &crtc->base)
11980 continue;
11981
11982 encoder = to_intel_encoder(connector_state->best_encoder);
11983 if (!check_single_encoder_cloning(state, crtc, encoder))
11984 return false;
11985 }
11986
11987 return true;
11988 }
11989
11990 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11991 struct drm_crtc_state *crtc_state)
11992 {
11993 struct drm_device *dev = crtc->dev;
11994 struct drm_i915_private *dev_priv = dev->dev_private;
11995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11996 struct intel_crtc_state *pipe_config =
11997 to_intel_crtc_state(crtc_state);
11998 struct drm_atomic_state *state = crtc_state->state;
11999 int ret;
12000 bool mode_changed = needs_modeset(crtc_state);
12001
12002 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12003 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12004 return -EINVAL;
12005 }
12006
12007 if (mode_changed && !crtc_state->active)
12008 pipe_config->wm_changed = true;
12009
12010 if (mode_changed && crtc_state->enable &&
12011 dev_priv->display.crtc_compute_clock &&
12012 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12013 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12014 pipe_config);
12015 if (ret)
12016 return ret;
12017 }
12018
12019 ret = 0;
12020 if (dev_priv->display.compute_pipe_wm) {
12021 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12022 if (ret)
12023 return ret;
12024 }
12025
12026 if (INTEL_INFO(dev)->gen >= 9) {
12027 if (mode_changed)
12028 ret = skl_update_scaler_crtc(pipe_config);
12029
12030 if (!ret)
12031 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12032 pipe_config);
12033 }
12034
12035 return ret;
12036 }
12037
12038 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12039 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12040 .load_lut = intel_crtc_load_lut,
12041 .atomic_begin = intel_begin_crtc_commit,
12042 .atomic_flush = intel_finish_crtc_commit,
12043 .atomic_check = intel_crtc_atomic_check,
12044 };
12045
12046 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12047 {
12048 struct intel_connector *connector;
12049
12050 for_each_intel_connector(dev, connector) {
12051 if (connector->base.encoder) {
12052 connector->base.state->best_encoder =
12053 connector->base.encoder;
12054 connector->base.state->crtc =
12055 connector->base.encoder->crtc;
12056 } else {
12057 connector->base.state->best_encoder = NULL;
12058 connector->base.state->crtc = NULL;
12059 }
12060 }
12061 }
12062
12063 static void
12064 connected_sink_compute_bpp(struct intel_connector *connector,
12065 struct intel_crtc_state *pipe_config)
12066 {
12067 int bpp = pipe_config->pipe_bpp;
12068
12069 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12070 connector->base.base.id,
12071 connector->base.name);
12072
12073 /* Don't use an invalid EDID bpc value */
12074 if (connector->base.display_info.bpc &&
12075 connector->base.display_info.bpc * 3 < bpp) {
12076 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12077 bpp, connector->base.display_info.bpc*3);
12078 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12079 }
12080
12081 /* Clamp bpp to default limit on screens without EDID 1.4 */
12082 if (connector->base.display_info.bpc == 0) {
12083 int type = connector->base.connector_type;
12084 int clamp_bpp = 24;
12085
12086 /* Fall back to 18 bpp when DP sink capability is unknown. */
12087 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12088 type == DRM_MODE_CONNECTOR_eDP)
12089 clamp_bpp = 18;
12090
12091 if (bpp > clamp_bpp) {
12092 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12093 bpp, clamp_bpp);
12094 pipe_config->pipe_bpp = clamp_bpp;
12095 }
12096 }
12097 }
12098
12099 static int
12100 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12101 struct intel_crtc_state *pipe_config)
12102 {
12103 struct drm_device *dev = crtc->base.dev;
12104 struct drm_atomic_state *state;
12105 struct drm_connector *connector;
12106 struct drm_connector_state *connector_state;
12107 int bpp, i;
12108
12109 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12110 bpp = 10*3;
12111 else if (INTEL_INFO(dev)->gen >= 5)
12112 bpp = 12*3;
12113 else
12114 bpp = 8*3;
12115
12116
12117 pipe_config->pipe_bpp = bpp;
12118
12119 state = pipe_config->base.state;
12120
12121 /* Clamp display bpp to EDID value */
12122 for_each_connector_in_state(state, connector, connector_state, i) {
12123 if (connector_state->crtc != &crtc->base)
12124 continue;
12125
12126 connected_sink_compute_bpp(to_intel_connector(connector),
12127 pipe_config);
12128 }
12129
12130 return bpp;
12131 }
12132
12133 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12134 {
12135 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12136 "type: 0x%x flags: 0x%x\n",
12137 mode->crtc_clock,
12138 mode->crtc_hdisplay, mode->crtc_hsync_start,
12139 mode->crtc_hsync_end, mode->crtc_htotal,
12140 mode->crtc_vdisplay, mode->crtc_vsync_start,
12141 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12142 }
12143
12144 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12145 struct intel_crtc_state *pipe_config,
12146 const char *context)
12147 {
12148 struct drm_device *dev = crtc->base.dev;
12149 struct drm_plane *plane;
12150 struct intel_plane *intel_plane;
12151 struct intel_plane_state *state;
12152 struct drm_framebuffer *fb;
12153
12154 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12155 context, pipe_config, pipe_name(crtc->pipe));
12156
12157 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12158 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12159 pipe_config->pipe_bpp, pipe_config->dither);
12160 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12161 pipe_config->has_pch_encoder,
12162 pipe_config->fdi_lanes,
12163 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12164 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12165 pipe_config->fdi_m_n.tu);
12166 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12167 pipe_config->has_dp_encoder,
12168 pipe_config->lane_count,
12169 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12170 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12171 pipe_config->dp_m_n.tu);
12172
12173 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12174 pipe_config->has_dp_encoder,
12175 pipe_config->lane_count,
12176 pipe_config->dp_m2_n2.gmch_m,
12177 pipe_config->dp_m2_n2.gmch_n,
12178 pipe_config->dp_m2_n2.link_m,
12179 pipe_config->dp_m2_n2.link_n,
12180 pipe_config->dp_m2_n2.tu);
12181
12182 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12183 pipe_config->has_audio,
12184 pipe_config->has_infoframe);
12185
12186 DRM_DEBUG_KMS("requested mode:\n");
12187 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12188 DRM_DEBUG_KMS("adjusted mode:\n");
12189 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12190 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12191 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12192 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12193 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12194 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12195 crtc->num_scalers,
12196 pipe_config->scaler_state.scaler_users,
12197 pipe_config->scaler_state.scaler_id);
12198 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12199 pipe_config->gmch_pfit.control,
12200 pipe_config->gmch_pfit.pgm_ratios,
12201 pipe_config->gmch_pfit.lvds_border_bits);
12202 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12203 pipe_config->pch_pfit.pos,
12204 pipe_config->pch_pfit.size,
12205 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12206 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12207 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12208
12209 if (IS_BROXTON(dev)) {
12210 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12211 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12212 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12213 pipe_config->ddi_pll_sel,
12214 pipe_config->dpll_hw_state.ebb0,
12215 pipe_config->dpll_hw_state.ebb4,
12216 pipe_config->dpll_hw_state.pll0,
12217 pipe_config->dpll_hw_state.pll1,
12218 pipe_config->dpll_hw_state.pll2,
12219 pipe_config->dpll_hw_state.pll3,
12220 pipe_config->dpll_hw_state.pll6,
12221 pipe_config->dpll_hw_state.pll8,
12222 pipe_config->dpll_hw_state.pll9,
12223 pipe_config->dpll_hw_state.pll10,
12224 pipe_config->dpll_hw_state.pcsdw12);
12225 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12226 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12227 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12228 pipe_config->ddi_pll_sel,
12229 pipe_config->dpll_hw_state.ctrl1,
12230 pipe_config->dpll_hw_state.cfgcr1,
12231 pipe_config->dpll_hw_state.cfgcr2);
12232 } else if (HAS_DDI(dev)) {
12233 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12234 pipe_config->ddi_pll_sel,
12235 pipe_config->dpll_hw_state.wrpll,
12236 pipe_config->dpll_hw_state.spll);
12237 } else {
12238 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12239 "fp0: 0x%x, fp1: 0x%x\n",
12240 pipe_config->dpll_hw_state.dpll,
12241 pipe_config->dpll_hw_state.dpll_md,
12242 pipe_config->dpll_hw_state.fp0,
12243 pipe_config->dpll_hw_state.fp1);
12244 }
12245
12246 DRM_DEBUG_KMS("planes on this crtc\n");
12247 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12248 intel_plane = to_intel_plane(plane);
12249 if (intel_plane->pipe != crtc->pipe)
12250 continue;
12251
12252 state = to_intel_plane_state(plane->state);
12253 fb = state->base.fb;
12254 if (!fb) {
12255 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12256 "disabled, scaler_id = %d\n",
12257 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12258 plane->base.id, intel_plane->pipe,
12259 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12260 drm_plane_index(plane), state->scaler_id);
12261 continue;
12262 }
12263
12264 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12265 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12266 plane->base.id, intel_plane->pipe,
12267 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12268 drm_plane_index(plane));
12269 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12270 fb->base.id, fb->width, fb->height, fb->pixel_format);
12271 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12272 state->scaler_id,
12273 state->src.x1 >> 16, state->src.y1 >> 16,
12274 drm_rect_width(&state->src) >> 16,
12275 drm_rect_height(&state->src) >> 16,
12276 state->dst.x1, state->dst.y1,
12277 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12278 }
12279 }
12280
12281 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12282 {
12283 struct drm_device *dev = state->dev;
12284 struct drm_connector *connector;
12285 unsigned int used_ports = 0;
12286
12287 /*
12288 * Walk the connector list instead of the encoder
12289 * list to detect the problem on ddi platforms
12290 * where there's just one encoder per digital port.
12291 */
12292 drm_for_each_connector(connector, dev) {
12293 struct drm_connector_state *connector_state;
12294 struct intel_encoder *encoder;
12295
12296 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12297 if (!connector_state)
12298 connector_state = connector->state;
12299
12300 if (!connector_state->best_encoder)
12301 continue;
12302
12303 encoder = to_intel_encoder(connector_state->best_encoder);
12304
12305 WARN_ON(!connector_state->crtc);
12306
12307 switch (encoder->type) {
12308 unsigned int port_mask;
12309 case INTEL_OUTPUT_UNKNOWN:
12310 if (WARN_ON(!HAS_DDI(dev)))
12311 break;
12312 case INTEL_OUTPUT_DISPLAYPORT:
12313 case INTEL_OUTPUT_HDMI:
12314 case INTEL_OUTPUT_EDP:
12315 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12316
12317 /* the same port mustn't appear more than once */
12318 if (used_ports & port_mask)
12319 return false;
12320
12321 used_ports |= port_mask;
12322 default:
12323 break;
12324 }
12325 }
12326
12327 return true;
12328 }
12329
12330 static void
12331 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12332 {
12333 struct drm_crtc_state tmp_state;
12334 struct intel_crtc_scaler_state scaler_state;
12335 struct intel_dpll_hw_state dpll_hw_state;
12336 enum intel_dpll_id shared_dpll;
12337 uint32_t ddi_pll_sel;
12338 bool force_thru;
12339
12340 /* FIXME: before the switch to atomic started, a new pipe_config was
12341 * kzalloc'd. Code that depends on any field being zero should be
12342 * fixed, so that the crtc_state can be safely duplicated. For now,
12343 * only fields that are know to not cause problems are preserved. */
12344
12345 tmp_state = crtc_state->base;
12346 scaler_state = crtc_state->scaler_state;
12347 shared_dpll = crtc_state->shared_dpll;
12348 dpll_hw_state = crtc_state->dpll_hw_state;
12349 ddi_pll_sel = crtc_state->ddi_pll_sel;
12350 force_thru = crtc_state->pch_pfit.force_thru;
12351
12352 memset(crtc_state, 0, sizeof *crtc_state);
12353
12354 crtc_state->base = tmp_state;
12355 crtc_state->scaler_state = scaler_state;
12356 crtc_state->shared_dpll = shared_dpll;
12357 crtc_state->dpll_hw_state = dpll_hw_state;
12358 crtc_state->ddi_pll_sel = ddi_pll_sel;
12359 crtc_state->pch_pfit.force_thru = force_thru;
12360 }
12361
12362 static int
12363 intel_modeset_pipe_config(struct drm_crtc *crtc,
12364 struct intel_crtc_state *pipe_config)
12365 {
12366 struct drm_atomic_state *state = pipe_config->base.state;
12367 struct intel_encoder *encoder;
12368 struct drm_connector *connector;
12369 struct drm_connector_state *connector_state;
12370 int base_bpp, ret = -EINVAL;
12371 int i;
12372 bool retry = true;
12373
12374 clear_intel_crtc_state(pipe_config);
12375
12376 pipe_config->cpu_transcoder =
12377 (enum transcoder) to_intel_crtc(crtc)->pipe;
12378
12379 /*
12380 * Sanitize sync polarity flags based on requested ones. If neither
12381 * positive or negative polarity is requested, treat this as meaning
12382 * negative polarity.
12383 */
12384 if (!(pipe_config->base.adjusted_mode.flags &
12385 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12386 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12387
12388 if (!(pipe_config->base.adjusted_mode.flags &
12389 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12390 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12391
12392 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12393 pipe_config);
12394 if (base_bpp < 0)
12395 goto fail;
12396
12397 /*
12398 * Determine the real pipe dimensions. Note that stereo modes can
12399 * increase the actual pipe size due to the frame doubling and
12400 * insertion of additional space for blanks between the frame. This
12401 * is stored in the crtc timings. We use the requested mode to do this
12402 * computation to clearly distinguish it from the adjusted mode, which
12403 * can be changed by the connectors in the below retry loop.
12404 */
12405 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12406 &pipe_config->pipe_src_w,
12407 &pipe_config->pipe_src_h);
12408
12409 encoder_retry:
12410 /* Ensure the port clock defaults are reset when retrying. */
12411 pipe_config->port_clock = 0;
12412 pipe_config->pixel_multiplier = 1;
12413
12414 /* Fill in default crtc timings, allow encoders to overwrite them. */
12415 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12416 CRTC_STEREO_DOUBLE);
12417
12418 /* Pass our mode to the connectors and the CRTC to give them a chance to
12419 * adjust it according to limitations or connector properties, and also
12420 * a chance to reject the mode entirely.
12421 */
12422 for_each_connector_in_state(state, connector, connector_state, i) {
12423 if (connector_state->crtc != crtc)
12424 continue;
12425
12426 encoder = to_intel_encoder(connector_state->best_encoder);
12427
12428 if (!(encoder->compute_config(encoder, pipe_config))) {
12429 DRM_DEBUG_KMS("Encoder config failure\n");
12430 goto fail;
12431 }
12432 }
12433
12434 /* Set default port clock if not overwritten by the encoder. Needs to be
12435 * done afterwards in case the encoder adjusts the mode. */
12436 if (!pipe_config->port_clock)
12437 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12438 * pipe_config->pixel_multiplier;
12439
12440 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12441 if (ret < 0) {
12442 DRM_DEBUG_KMS("CRTC fixup failed\n");
12443 goto fail;
12444 }
12445
12446 if (ret == RETRY) {
12447 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12448 ret = -EINVAL;
12449 goto fail;
12450 }
12451
12452 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12453 retry = false;
12454 goto encoder_retry;
12455 }
12456
12457 /* Dithering seems to not pass-through bits correctly when it should, so
12458 * only enable it on 6bpc panels. */
12459 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12460 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12461 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12462
12463 fail:
12464 return ret;
12465 }
12466
12467 static void
12468 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12469 {
12470 struct drm_crtc *crtc;
12471 struct drm_crtc_state *crtc_state;
12472 int i;
12473
12474 /* Double check state. */
12475 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12476 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12477
12478 /* Update hwmode for vblank functions */
12479 if (crtc->state->active)
12480 crtc->hwmode = crtc->state->adjusted_mode;
12481 else
12482 crtc->hwmode.crtc_clock = 0;
12483
12484 /*
12485 * Update legacy state to satisfy fbc code. This can
12486 * be removed when fbc uses the atomic state.
12487 */
12488 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12489 struct drm_plane_state *plane_state = crtc->primary->state;
12490
12491 crtc->primary->fb = plane_state->fb;
12492 crtc->x = plane_state->src_x >> 16;
12493 crtc->y = plane_state->src_y >> 16;
12494 }
12495 }
12496 }
12497
12498 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12499 {
12500 int diff;
12501
12502 if (clock1 == clock2)
12503 return true;
12504
12505 if (!clock1 || !clock2)
12506 return false;
12507
12508 diff = abs(clock1 - clock2);
12509
12510 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12511 return true;
12512
12513 return false;
12514 }
12515
12516 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12517 list_for_each_entry((intel_crtc), \
12518 &(dev)->mode_config.crtc_list, \
12519 base.head) \
12520 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12521
12522 static bool
12523 intel_compare_m_n(unsigned int m, unsigned int n,
12524 unsigned int m2, unsigned int n2,
12525 bool exact)
12526 {
12527 if (m == m2 && n == n2)
12528 return true;
12529
12530 if (exact || !m || !n || !m2 || !n2)
12531 return false;
12532
12533 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12534
12535 if (n > n2) {
12536 while (n > n2) {
12537 m2 <<= 1;
12538 n2 <<= 1;
12539 }
12540 } else if (n < n2) {
12541 while (n < n2) {
12542 m <<= 1;
12543 n <<= 1;
12544 }
12545 }
12546
12547 if (n != n2)
12548 return false;
12549
12550 return intel_fuzzy_clock_check(m, m2);
12551 }
12552
12553 static bool
12554 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12555 struct intel_link_m_n *m2_n2,
12556 bool adjust)
12557 {
12558 if (m_n->tu == m2_n2->tu &&
12559 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12560 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12561 intel_compare_m_n(m_n->link_m, m_n->link_n,
12562 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12563 if (adjust)
12564 *m2_n2 = *m_n;
12565
12566 return true;
12567 }
12568
12569 return false;
12570 }
12571
12572 static bool
12573 intel_pipe_config_compare(struct drm_device *dev,
12574 struct intel_crtc_state *current_config,
12575 struct intel_crtc_state *pipe_config,
12576 bool adjust)
12577 {
12578 bool ret = true;
12579
12580 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12581 do { \
12582 if (!adjust) \
12583 DRM_ERROR(fmt, ##__VA_ARGS__); \
12584 else \
12585 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12586 } while (0)
12587
12588 #define PIPE_CONF_CHECK_X(name) \
12589 if (current_config->name != pipe_config->name) { \
12590 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12591 "(expected 0x%08x, found 0x%08x)\n", \
12592 current_config->name, \
12593 pipe_config->name); \
12594 ret = false; \
12595 }
12596
12597 #define PIPE_CONF_CHECK_I(name) \
12598 if (current_config->name != pipe_config->name) { \
12599 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12600 "(expected %i, found %i)\n", \
12601 current_config->name, \
12602 pipe_config->name); \
12603 ret = false; \
12604 }
12605
12606 #define PIPE_CONF_CHECK_M_N(name) \
12607 if (!intel_compare_link_m_n(&current_config->name, \
12608 &pipe_config->name,\
12609 adjust)) { \
12610 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12611 "(expected tu %i gmch %i/%i link %i/%i, " \
12612 "found tu %i, gmch %i/%i link %i/%i)\n", \
12613 current_config->name.tu, \
12614 current_config->name.gmch_m, \
12615 current_config->name.gmch_n, \
12616 current_config->name.link_m, \
12617 current_config->name.link_n, \
12618 pipe_config->name.tu, \
12619 pipe_config->name.gmch_m, \
12620 pipe_config->name.gmch_n, \
12621 pipe_config->name.link_m, \
12622 pipe_config->name.link_n); \
12623 ret = false; \
12624 }
12625
12626 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12627 if (!intel_compare_link_m_n(&current_config->name, \
12628 &pipe_config->name, adjust) && \
12629 !intel_compare_link_m_n(&current_config->alt_name, \
12630 &pipe_config->name, adjust)) { \
12631 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12632 "(expected tu %i gmch %i/%i link %i/%i, " \
12633 "or tu %i gmch %i/%i link %i/%i, " \
12634 "found tu %i, gmch %i/%i link %i/%i)\n", \
12635 current_config->name.tu, \
12636 current_config->name.gmch_m, \
12637 current_config->name.gmch_n, \
12638 current_config->name.link_m, \
12639 current_config->name.link_n, \
12640 current_config->alt_name.tu, \
12641 current_config->alt_name.gmch_m, \
12642 current_config->alt_name.gmch_n, \
12643 current_config->alt_name.link_m, \
12644 current_config->alt_name.link_n, \
12645 pipe_config->name.tu, \
12646 pipe_config->name.gmch_m, \
12647 pipe_config->name.gmch_n, \
12648 pipe_config->name.link_m, \
12649 pipe_config->name.link_n); \
12650 ret = false; \
12651 }
12652
12653 /* This is required for BDW+ where there is only one set of registers for
12654 * switching between high and low RR.
12655 * This macro can be used whenever a comparison has to be made between one
12656 * hw state and multiple sw state variables.
12657 */
12658 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12659 if ((current_config->name != pipe_config->name) && \
12660 (current_config->alt_name != pipe_config->name)) { \
12661 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12662 "(expected %i or %i, found %i)\n", \
12663 current_config->name, \
12664 current_config->alt_name, \
12665 pipe_config->name); \
12666 ret = false; \
12667 }
12668
12669 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12670 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12671 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12672 "(expected %i, found %i)\n", \
12673 current_config->name & (mask), \
12674 pipe_config->name & (mask)); \
12675 ret = false; \
12676 }
12677
12678 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12679 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12680 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12681 "(expected %i, found %i)\n", \
12682 current_config->name, \
12683 pipe_config->name); \
12684 ret = false; \
12685 }
12686
12687 #define PIPE_CONF_QUIRK(quirk) \
12688 ((current_config->quirks | pipe_config->quirks) & (quirk))
12689
12690 PIPE_CONF_CHECK_I(cpu_transcoder);
12691
12692 PIPE_CONF_CHECK_I(has_pch_encoder);
12693 PIPE_CONF_CHECK_I(fdi_lanes);
12694 PIPE_CONF_CHECK_M_N(fdi_m_n);
12695
12696 PIPE_CONF_CHECK_I(has_dp_encoder);
12697 PIPE_CONF_CHECK_I(lane_count);
12698
12699 if (INTEL_INFO(dev)->gen < 8) {
12700 PIPE_CONF_CHECK_M_N(dp_m_n);
12701
12702 if (current_config->has_drrs)
12703 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12704 } else
12705 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12706
12707 PIPE_CONF_CHECK_I(has_dsi_encoder);
12708
12709 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12710 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12711 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12712 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12713 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12714 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12715
12716 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12717 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12718 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12719 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12720 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12721 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12722
12723 PIPE_CONF_CHECK_I(pixel_multiplier);
12724 PIPE_CONF_CHECK_I(has_hdmi_sink);
12725 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12726 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12727 PIPE_CONF_CHECK_I(limited_color_range);
12728 PIPE_CONF_CHECK_I(has_infoframe);
12729
12730 PIPE_CONF_CHECK_I(has_audio);
12731
12732 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12733 DRM_MODE_FLAG_INTERLACE);
12734
12735 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12736 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12737 DRM_MODE_FLAG_PHSYNC);
12738 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12739 DRM_MODE_FLAG_NHSYNC);
12740 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12741 DRM_MODE_FLAG_PVSYNC);
12742 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12743 DRM_MODE_FLAG_NVSYNC);
12744 }
12745
12746 PIPE_CONF_CHECK_X(gmch_pfit.control);
12747 /* pfit ratios are autocomputed by the hw on gen4+ */
12748 if (INTEL_INFO(dev)->gen < 4)
12749 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12750 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12751
12752 if (!adjust) {
12753 PIPE_CONF_CHECK_I(pipe_src_w);
12754 PIPE_CONF_CHECK_I(pipe_src_h);
12755
12756 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12757 if (current_config->pch_pfit.enabled) {
12758 PIPE_CONF_CHECK_X(pch_pfit.pos);
12759 PIPE_CONF_CHECK_X(pch_pfit.size);
12760 }
12761
12762 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12763 }
12764
12765 /* BDW+ don't expose a synchronous way to read the state */
12766 if (IS_HASWELL(dev))
12767 PIPE_CONF_CHECK_I(ips_enabled);
12768
12769 PIPE_CONF_CHECK_I(double_wide);
12770
12771 PIPE_CONF_CHECK_X(ddi_pll_sel);
12772
12773 PIPE_CONF_CHECK_I(shared_dpll);
12774 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12775 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12776 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12777 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12778 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12779 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12780 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12781 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12782 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12783
12784 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12785 PIPE_CONF_CHECK_I(pipe_bpp);
12786
12787 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12788 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12789
12790 #undef PIPE_CONF_CHECK_X
12791 #undef PIPE_CONF_CHECK_I
12792 #undef PIPE_CONF_CHECK_I_ALT
12793 #undef PIPE_CONF_CHECK_FLAGS
12794 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12795 #undef PIPE_CONF_QUIRK
12796 #undef INTEL_ERR_OR_DBG_KMS
12797
12798 return ret;
12799 }
12800
12801 static void check_wm_state(struct drm_device *dev)
12802 {
12803 struct drm_i915_private *dev_priv = dev->dev_private;
12804 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12805 struct intel_crtc *intel_crtc;
12806 int plane;
12807
12808 if (INTEL_INFO(dev)->gen < 9)
12809 return;
12810
12811 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12812 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12813
12814 for_each_intel_crtc(dev, intel_crtc) {
12815 struct skl_ddb_entry *hw_entry, *sw_entry;
12816 const enum pipe pipe = intel_crtc->pipe;
12817
12818 if (!intel_crtc->active)
12819 continue;
12820
12821 /* planes */
12822 for_each_plane(dev_priv, pipe, plane) {
12823 hw_entry = &hw_ddb.plane[pipe][plane];
12824 sw_entry = &sw_ddb->plane[pipe][plane];
12825
12826 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12827 continue;
12828
12829 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12830 "(expected (%u,%u), found (%u,%u))\n",
12831 pipe_name(pipe), plane + 1,
12832 sw_entry->start, sw_entry->end,
12833 hw_entry->start, hw_entry->end);
12834 }
12835
12836 /* cursor */
12837 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12838 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12839
12840 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12841 continue;
12842
12843 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12844 "(expected (%u,%u), found (%u,%u))\n",
12845 pipe_name(pipe),
12846 sw_entry->start, sw_entry->end,
12847 hw_entry->start, hw_entry->end);
12848 }
12849 }
12850
12851 static void
12852 check_connector_state(struct drm_device *dev,
12853 struct drm_atomic_state *old_state)
12854 {
12855 struct drm_connector_state *old_conn_state;
12856 struct drm_connector *connector;
12857 int i;
12858
12859 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12860 struct drm_encoder *encoder = connector->encoder;
12861 struct drm_connector_state *state = connector->state;
12862
12863 /* This also checks the encoder/connector hw state with the
12864 * ->get_hw_state callbacks. */
12865 intel_connector_check_state(to_intel_connector(connector));
12866
12867 I915_STATE_WARN(state->best_encoder != encoder,
12868 "connector's atomic encoder doesn't match legacy encoder\n");
12869 }
12870 }
12871
12872 static void
12873 check_encoder_state(struct drm_device *dev)
12874 {
12875 struct intel_encoder *encoder;
12876 struct intel_connector *connector;
12877
12878 for_each_intel_encoder(dev, encoder) {
12879 bool enabled = false;
12880 enum pipe pipe;
12881
12882 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12883 encoder->base.base.id,
12884 encoder->base.name);
12885
12886 for_each_intel_connector(dev, connector) {
12887 if (connector->base.state->best_encoder != &encoder->base)
12888 continue;
12889 enabled = true;
12890
12891 I915_STATE_WARN(connector->base.state->crtc !=
12892 encoder->base.crtc,
12893 "connector's crtc doesn't match encoder crtc\n");
12894 }
12895
12896 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12897 "encoder's enabled state mismatch "
12898 "(expected %i, found %i)\n",
12899 !!encoder->base.crtc, enabled);
12900
12901 if (!encoder->base.crtc) {
12902 bool active;
12903
12904 active = encoder->get_hw_state(encoder, &pipe);
12905 I915_STATE_WARN(active,
12906 "encoder detached but still enabled on pipe %c.\n",
12907 pipe_name(pipe));
12908 }
12909 }
12910 }
12911
12912 static void
12913 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12914 {
12915 struct drm_i915_private *dev_priv = dev->dev_private;
12916 struct intel_encoder *encoder;
12917 struct drm_crtc_state *old_crtc_state;
12918 struct drm_crtc *crtc;
12919 int i;
12920
12921 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12923 struct intel_crtc_state *pipe_config, *sw_config;
12924 bool active;
12925
12926 if (!needs_modeset(crtc->state) &&
12927 !to_intel_crtc_state(crtc->state)->update_pipe)
12928 continue;
12929
12930 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12931 pipe_config = to_intel_crtc_state(old_crtc_state);
12932 memset(pipe_config, 0, sizeof(*pipe_config));
12933 pipe_config->base.crtc = crtc;
12934 pipe_config->base.state = old_state;
12935
12936 DRM_DEBUG_KMS("[CRTC:%d]\n",
12937 crtc->base.id);
12938
12939 active = dev_priv->display.get_pipe_config(intel_crtc,
12940 pipe_config);
12941
12942 /* hw state is inconsistent with the pipe quirk */
12943 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12944 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12945 active = crtc->state->active;
12946
12947 I915_STATE_WARN(crtc->state->active != active,
12948 "crtc active state doesn't match with hw state "
12949 "(expected %i, found %i)\n", crtc->state->active, active);
12950
12951 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12952 "transitional active state does not match atomic hw state "
12953 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12954
12955 for_each_encoder_on_crtc(dev, crtc, encoder) {
12956 enum pipe pipe;
12957
12958 active = encoder->get_hw_state(encoder, &pipe);
12959 I915_STATE_WARN(active != crtc->state->active,
12960 "[ENCODER:%i] active %i with crtc active %i\n",
12961 encoder->base.base.id, active, crtc->state->active);
12962
12963 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12964 "Encoder connected to wrong pipe %c\n",
12965 pipe_name(pipe));
12966
12967 if (active)
12968 encoder->get_config(encoder, pipe_config);
12969 }
12970
12971 if (!crtc->state->active)
12972 continue;
12973
12974 sw_config = to_intel_crtc_state(crtc->state);
12975 if (!intel_pipe_config_compare(dev, sw_config,
12976 pipe_config, false)) {
12977 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12978 intel_dump_pipe_config(intel_crtc, pipe_config,
12979 "[hw state]");
12980 intel_dump_pipe_config(intel_crtc, sw_config,
12981 "[sw state]");
12982 }
12983 }
12984 }
12985
12986 static void
12987 check_shared_dpll_state(struct drm_device *dev)
12988 {
12989 struct drm_i915_private *dev_priv = dev->dev_private;
12990 struct intel_crtc *crtc;
12991 struct intel_dpll_hw_state dpll_hw_state;
12992 int i;
12993
12994 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12995 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12996 int enabled_crtcs = 0, active_crtcs = 0;
12997 bool active;
12998
12999 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13000
13001 DRM_DEBUG_KMS("%s\n", pll->name);
13002
13003 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
13004
13005 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
13006 "more active pll users than references: %i vs %i\n",
13007 pll->active, hweight32(pll->config.crtc_mask));
13008 I915_STATE_WARN(pll->active && !pll->on,
13009 "pll in active use but not on in sw tracking\n");
13010 I915_STATE_WARN(pll->on && !pll->active,
13011 "pll in on but not on in use in sw tracking\n");
13012 I915_STATE_WARN(pll->on != active,
13013 "pll on state mismatch (expected %i, found %i)\n",
13014 pll->on, active);
13015
13016 for_each_intel_crtc(dev, crtc) {
13017 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
13018 enabled_crtcs++;
13019 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13020 active_crtcs++;
13021 }
13022 I915_STATE_WARN(pll->active != active_crtcs,
13023 "pll active crtcs mismatch (expected %i, found %i)\n",
13024 pll->active, active_crtcs);
13025 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
13026 "pll enabled crtcs mismatch (expected %i, found %i)\n",
13027 hweight32(pll->config.crtc_mask), enabled_crtcs);
13028
13029 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13030 sizeof(dpll_hw_state)),
13031 "pll hw state mismatch\n");
13032 }
13033 }
13034
13035 static void
13036 intel_modeset_check_state(struct drm_device *dev,
13037 struct drm_atomic_state *old_state)
13038 {
13039 check_wm_state(dev);
13040 check_connector_state(dev, old_state);
13041 check_encoder_state(dev);
13042 check_crtc_state(dev, old_state);
13043 check_shared_dpll_state(dev);
13044 }
13045
13046 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13047 int dotclock)
13048 {
13049 /*
13050 * FDI already provided one idea for the dotclock.
13051 * Yell if the encoder disagrees.
13052 */
13053 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13054 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13055 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13056 }
13057
13058 static void update_scanline_offset(struct intel_crtc *crtc)
13059 {
13060 struct drm_device *dev = crtc->base.dev;
13061
13062 /*
13063 * The scanline counter increments at the leading edge of hsync.
13064 *
13065 * On most platforms it starts counting from vtotal-1 on the
13066 * first active line. That means the scanline counter value is
13067 * always one less than what we would expect. Ie. just after
13068 * start of vblank, which also occurs at start of hsync (on the
13069 * last active line), the scanline counter will read vblank_start-1.
13070 *
13071 * On gen2 the scanline counter starts counting from 1 instead
13072 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13073 * to keep the value positive), instead of adding one.
13074 *
13075 * On HSW+ the behaviour of the scanline counter depends on the output
13076 * type. For DP ports it behaves like most other platforms, but on HDMI
13077 * there's an extra 1 line difference. So we need to add two instead of
13078 * one to the value.
13079 */
13080 if (IS_GEN2(dev)) {
13081 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13082 int vtotal;
13083
13084 vtotal = adjusted_mode->crtc_vtotal;
13085 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13086 vtotal /= 2;
13087
13088 crtc->scanline_offset = vtotal - 1;
13089 } else if (HAS_DDI(dev) &&
13090 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13091 crtc->scanline_offset = 2;
13092 } else
13093 crtc->scanline_offset = 1;
13094 }
13095
13096 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13097 {
13098 struct drm_device *dev = state->dev;
13099 struct drm_i915_private *dev_priv = to_i915(dev);
13100 struct intel_shared_dpll_config *shared_dpll = NULL;
13101 struct intel_crtc *intel_crtc;
13102 struct intel_crtc_state *intel_crtc_state;
13103 struct drm_crtc *crtc;
13104 struct drm_crtc_state *crtc_state;
13105 int i;
13106
13107 if (!dev_priv->display.crtc_compute_clock)
13108 return;
13109
13110 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13111 int dpll;
13112
13113 intel_crtc = to_intel_crtc(crtc);
13114 intel_crtc_state = to_intel_crtc_state(crtc_state);
13115 dpll = intel_crtc_state->shared_dpll;
13116
13117 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13118 continue;
13119
13120 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13121
13122 if (!shared_dpll)
13123 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13124
13125 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13126 }
13127 }
13128
13129 /*
13130 * This implements the workaround described in the "notes" section of the mode
13131 * set sequence documentation. When going from no pipes or single pipe to
13132 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13133 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13134 */
13135 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13136 {
13137 struct drm_crtc_state *crtc_state;
13138 struct intel_crtc *intel_crtc;
13139 struct drm_crtc *crtc;
13140 struct intel_crtc_state *first_crtc_state = NULL;
13141 struct intel_crtc_state *other_crtc_state = NULL;
13142 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13143 int i;
13144
13145 /* look at all crtc's that are going to be enabled in during modeset */
13146 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13147 intel_crtc = to_intel_crtc(crtc);
13148
13149 if (!crtc_state->active || !needs_modeset(crtc_state))
13150 continue;
13151
13152 if (first_crtc_state) {
13153 other_crtc_state = to_intel_crtc_state(crtc_state);
13154 break;
13155 } else {
13156 first_crtc_state = to_intel_crtc_state(crtc_state);
13157 first_pipe = intel_crtc->pipe;
13158 }
13159 }
13160
13161 /* No workaround needed? */
13162 if (!first_crtc_state)
13163 return 0;
13164
13165 /* w/a possibly needed, check how many crtc's are already enabled. */
13166 for_each_intel_crtc(state->dev, intel_crtc) {
13167 struct intel_crtc_state *pipe_config;
13168
13169 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13170 if (IS_ERR(pipe_config))
13171 return PTR_ERR(pipe_config);
13172
13173 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13174
13175 if (!pipe_config->base.active ||
13176 needs_modeset(&pipe_config->base))
13177 continue;
13178
13179 /* 2 or more enabled crtcs means no need for w/a */
13180 if (enabled_pipe != INVALID_PIPE)
13181 return 0;
13182
13183 enabled_pipe = intel_crtc->pipe;
13184 }
13185
13186 if (enabled_pipe != INVALID_PIPE)
13187 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13188 else if (other_crtc_state)
13189 other_crtc_state->hsw_workaround_pipe = first_pipe;
13190
13191 return 0;
13192 }
13193
13194 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13195 {
13196 struct drm_crtc *crtc;
13197 struct drm_crtc_state *crtc_state;
13198 int ret = 0;
13199
13200 /* add all active pipes to the state */
13201 for_each_crtc(state->dev, crtc) {
13202 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13203 if (IS_ERR(crtc_state))
13204 return PTR_ERR(crtc_state);
13205
13206 if (!crtc_state->active || needs_modeset(crtc_state))
13207 continue;
13208
13209 crtc_state->mode_changed = true;
13210
13211 ret = drm_atomic_add_affected_connectors(state, crtc);
13212 if (ret)
13213 break;
13214
13215 ret = drm_atomic_add_affected_planes(state, crtc);
13216 if (ret)
13217 break;
13218 }
13219
13220 return ret;
13221 }
13222
13223 static int intel_modeset_checks(struct drm_atomic_state *state)
13224 {
13225 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13226 struct drm_i915_private *dev_priv = state->dev->dev_private;
13227 struct drm_crtc *crtc;
13228 struct drm_crtc_state *crtc_state;
13229 int ret = 0, i;
13230
13231 if (!check_digital_port_conflicts(state)) {
13232 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13233 return -EINVAL;
13234 }
13235
13236 intel_state->modeset = true;
13237 intel_state->active_crtcs = dev_priv->active_crtcs;
13238
13239 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13240 if (crtc_state->active)
13241 intel_state->active_crtcs |= 1 << i;
13242 else
13243 intel_state->active_crtcs &= ~(1 << i);
13244 }
13245
13246 /*
13247 * See if the config requires any additional preparation, e.g.
13248 * to adjust global state with pipes off. We need to do this
13249 * here so we can get the modeset_pipe updated config for the new
13250 * mode set on this crtc. For other crtcs we need to use the
13251 * adjusted_mode bits in the crtc directly.
13252 */
13253 if (dev_priv->display.modeset_calc_cdclk) {
13254 ret = dev_priv->display.modeset_calc_cdclk(state);
13255
13256 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13257 ret = intel_modeset_all_pipes(state);
13258
13259 if (ret < 0)
13260 return ret;
13261 } else
13262 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13263
13264 intel_modeset_clear_plls(state);
13265
13266 if (IS_HASWELL(dev_priv))
13267 return haswell_mode_set_planes_workaround(state);
13268
13269 return 0;
13270 }
13271
13272 /*
13273 * Handle calculation of various watermark data at the end of the atomic check
13274 * phase. The code here should be run after the per-crtc and per-plane 'check'
13275 * handlers to ensure that all derived state has been updated.
13276 */
13277 static void calc_watermark_data(struct drm_atomic_state *state)
13278 {
13279 struct drm_device *dev = state->dev;
13280 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13281 struct drm_crtc *crtc;
13282 struct drm_crtc_state *cstate;
13283 struct drm_plane *plane;
13284 struct drm_plane_state *pstate;
13285
13286 /*
13287 * Calculate watermark configuration details now that derived
13288 * plane/crtc state is all properly updated.
13289 */
13290 drm_for_each_crtc(crtc, dev) {
13291 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13292 crtc->state;
13293
13294 if (cstate->active)
13295 intel_state->wm_config.num_pipes_active++;
13296 }
13297 drm_for_each_legacy_plane(plane, dev) {
13298 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13299 plane->state;
13300
13301 if (!to_intel_plane_state(pstate)->visible)
13302 continue;
13303
13304 intel_state->wm_config.sprites_enabled = true;
13305 if (pstate->crtc_w != pstate->src_w >> 16 ||
13306 pstate->crtc_h != pstate->src_h >> 16)
13307 intel_state->wm_config.sprites_scaled = true;
13308 }
13309 }
13310
13311 /**
13312 * intel_atomic_check - validate state object
13313 * @dev: drm device
13314 * @state: state to validate
13315 */
13316 static int intel_atomic_check(struct drm_device *dev,
13317 struct drm_atomic_state *state)
13318 {
13319 struct drm_i915_private *dev_priv = to_i915(dev);
13320 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13321 struct drm_crtc *crtc;
13322 struct drm_crtc_state *crtc_state;
13323 int ret, i;
13324 bool any_ms = false;
13325
13326 ret = drm_atomic_helper_check_modeset(dev, state);
13327 if (ret)
13328 return ret;
13329
13330 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13331 struct intel_crtc_state *pipe_config =
13332 to_intel_crtc_state(crtc_state);
13333
13334 memset(&to_intel_crtc(crtc)->atomic, 0,
13335 sizeof(struct intel_crtc_atomic_commit));
13336
13337 /* Catch I915_MODE_FLAG_INHERITED */
13338 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13339 crtc_state->mode_changed = true;
13340
13341 if (!crtc_state->enable) {
13342 if (needs_modeset(crtc_state))
13343 any_ms = true;
13344 continue;
13345 }
13346
13347 if (!needs_modeset(crtc_state))
13348 continue;
13349
13350 /* FIXME: For only active_changed we shouldn't need to do any
13351 * state recomputation at all. */
13352
13353 ret = drm_atomic_add_affected_connectors(state, crtc);
13354 if (ret)
13355 return ret;
13356
13357 ret = intel_modeset_pipe_config(crtc, pipe_config);
13358 if (ret)
13359 return ret;
13360
13361 if (i915.fastboot &&
13362 intel_pipe_config_compare(dev,
13363 to_intel_crtc_state(crtc->state),
13364 pipe_config, true)) {
13365 crtc_state->mode_changed = false;
13366 to_intel_crtc_state(crtc_state)->update_pipe = true;
13367 }
13368
13369 if (needs_modeset(crtc_state)) {
13370 any_ms = true;
13371
13372 ret = drm_atomic_add_affected_planes(state, crtc);
13373 if (ret)
13374 return ret;
13375 }
13376
13377 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13378 needs_modeset(crtc_state) ?
13379 "[modeset]" : "[fastset]");
13380 }
13381
13382 if (any_ms) {
13383 ret = intel_modeset_checks(state);
13384
13385 if (ret)
13386 return ret;
13387 } else
13388 intel_state->cdclk = dev_priv->cdclk_freq;
13389
13390 ret = drm_atomic_helper_check_planes(dev, state);
13391 if (ret)
13392 return ret;
13393
13394 intel_fbc_choose_crtc(dev_priv, state);
13395 calc_watermark_data(state);
13396
13397 return 0;
13398 }
13399
13400 static int intel_atomic_prepare_commit(struct drm_device *dev,
13401 struct drm_atomic_state *state,
13402 bool async)
13403 {
13404 struct drm_i915_private *dev_priv = dev->dev_private;
13405 struct drm_plane_state *plane_state;
13406 struct drm_crtc_state *crtc_state;
13407 struct drm_plane *plane;
13408 struct drm_crtc *crtc;
13409 int i, ret;
13410
13411 if (async) {
13412 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13413 return -EINVAL;
13414 }
13415
13416 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13417 ret = intel_crtc_wait_for_pending_flips(crtc);
13418 if (ret)
13419 return ret;
13420
13421 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13422 flush_workqueue(dev_priv->wq);
13423 }
13424
13425 ret = mutex_lock_interruptible(&dev->struct_mutex);
13426 if (ret)
13427 return ret;
13428
13429 ret = drm_atomic_helper_prepare_planes(dev, state);
13430 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13431 u32 reset_counter;
13432
13433 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13434 mutex_unlock(&dev->struct_mutex);
13435
13436 for_each_plane_in_state(state, plane, plane_state, i) {
13437 struct intel_plane_state *intel_plane_state =
13438 to_intel_plane_state(plane_state);
13439
13440 if (!intel_plane_state->wait_req)
13441 continue;
13442
13443 ret = __i915_wait_request(intel_plane_state->wait_req,
13444 reset_counter, true,
13445 NULL, NULL);
13446
13447 /* Swallow -EIO errors to allow updates during hw lockup. */
13448 if (ret == -EIO)
13449 ret = 0;
13450
13451 if (ret)
13452 break;
13453 }
13454
13455 if (!ret)
13456 return 0;
13457
13458 mutex_lock(&dev->struct_mutex);
13459 drm_atomic_helper_cleanup_planes(dev, state);
13460 }
13461
13462 mutex_unlock(&dev->struct_mutex);
13463 return ret;
13464 }
13465
13466 /**
13467 * intel_atomic_commit - commit validated state object
13468 * @dev: DRM device
13469 * @state: the top-level driver state object
13470 * @async: asynchronous commit
13471 *
13472 * This function commits a top-level state object that has been validated
13473 * with drm_atomic_helper_check().
13474 *
13475 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13476 * we can only handle plane-related operations and do not yet support
13477 * asynchronous commit.
13478 *
13479 * RETURNS
13480 * Zero for success or -errno.
13481 */
13482 static int intel_atomic_commit(struct drm_device *dev,
13483 struct drm_atomic_state *state,
13484 bool async)
13485 {
13486 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13487 struct drm_i915_private *dev_priv = dev->dev_private;
13488 struct drm_crtc_state *crtc_state;
13489 struct drm_crtc *crtc;
13490 int ret = 0, i;
13491 bool hw_check = intel_state->modeset;
13492
13493 ret = intel_atomic_prepare_commit(dev, state, async);
13494 if (ret) {
13495 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13496 return ret;
13497 }
13498
13499 drm_atomic_helper_swap_state(dev, state);
13500 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13501
13502 if (intel_state->modeset) {
13503 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13504 sizeof(intel_state->min_pixclk));
13505 dev_priv->active_crtcs = intel_state->active_crtcs;
13506 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13507 }
13508
13509 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13511
13512 if (!needs_modeset(crtc->state))
13513 continue;
13514
13515 intel_pre_plane_update(to_intel_crtc_state(crtc_state));
13516
13517 if (crtc_state->active) {
13518 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13519 dev_priv->display.crtc_disable(crtc);
13520 intel_crtc->active = false;
13521 intel_fbc_disable(intel_crtc);
13522 intel_disable_shared_dpll(intel_crtc);
13523
13524 /*
13525 * Underruns don't always raise
13526 * interrupts, so check manually.
13527 */
13528 intel_check_cpu_fifo_underruns(dev_priv);
13529 intel_check_pch_fifo_underruns(dev_priv);
13530
13531 if (!crtc->state->active)
13532 intel_update_watermarks(crtc);
13533 }
13534 }
13535
13536 /* Only after disabling all output pipelines that will be changed can we
13537 * update the the output configuration. */
13538 intel_modeset_update_crtc_state(state);
13539
13540 if (intel_state->modeset) {
13541 intel_shared_dpll_commit(state);
13542
13543 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13544 modeset_update_crtc_power_domains(state);
13545 }
13546
13547 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13548 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13550 bool modeset = needs_modeset(crtc->state);
13551 bool update_pipe = !modeset &&
13552 to_intel_crtc_state(crtc->state)->update_pipe;
13553 unsigned long put_domains = 0;
13554
13555 if (modeset)
13556 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13557
13558 if (modeset && crtc->state->active) {
13559 update_scanline_offset(to_intel_crtc(crtc));
13560 dev_priv->display.crtc_enable(crtc);
13561 }
13562
13563 if (update_pipe) {
13564 put_domains = modeset_get_crtc_power_domains(crtc);
13565
13566 /* make sure intel_modeset_check_state runs */
13567 hw_check = true;
13568 }
13569
13570 if (!modeset)
13571 intel_pre_plane_update(to_intel_crtc_state(crtc_state));
13572
13573 if (crtc->state->active && intel_crtc->atomic.update_fbc)
13574 intel_fbc_enable(intel_crtc);
13575
13576 if (crtc->state->active &&
13577 (crtc->state->planes_changed || update_pipe))
13578 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13579
13580 if (put_domains)
13581 modeset_put_power_domains(dev_priv, put_domains);
13582
13583 intel_post_plane_update(intel_crtc);
13584
13585 if (modeset)
13586 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13587 }
13588
13589 /* FIXME: add subpixel order */
13590
13591 drm_atomic_helper_wait_for_vblanks(dev, state);
13592
13593 mutex_lock(&dev->struct_mutex);
13594 drm_atomic_helper_cleanup_planes(dev, state);
13595 mutex_unlock(&dev->struct_mutex);
13596
13597 if (hw_check)
13598 intel_modeset_check_state(dev, state);
13599
13600 drm_atomic_state_free(state);
13601
13602 /* As one of the primary mmio accessors, KMS has a high likelihood
13603 * of triggering bugs in unclaimed access. After we finish
13604 * modesetting, see if an error has been flagged, and if so
13605 * enable debugging for the next modeset - and hope we catch
13606 * the culprit.
13607 *
13608 * XXX note that we assume display power is on at this point.
13609 * This might hold true now but we need to add pm helper to check
13610 * unclaimed only when the hardware is on, as atomic commits
13611 * can happen also when the device is completely off.
13612 */
13613 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13614
13615 return 0;
13616 }
13617
13618 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13619 {
13620 struct drm_device *dev = crtc->dev;
13621 struct drm_atomic_state *state;
13622 struct drm_crtc_state *crtc_state;
13623 int ret;
13624
13625 state = drm_atomic_state_alloc(dev);
13626 if (!state) {
13627 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13628 crtc->base.id);
13629 return;
13630 }
13631
13632 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13633
13634 retry:
13635 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13636 ret = PTR_ERR_OR_ZERO(crtc_state);
13637 if (!ret) {
13638 if (!crtc_state->active)
13639 goto out;
13640
13641 crtc_state->mode_changed = true;
13642 ret = drm_atomic_commit(state);
13643 }
13644
13645 if (ret == -EDEADLK) {
13646 drm_atomic_state_clear(state);
13647 drm_modeset_backoff(state->acquire_ctx);
13648 goto retry;
13649 }
13650
13651 if (ret)
13652 out:
13653 drm_atomic_state_free(state);
13654 }
13655
13656 #undef for_each_intel_crtc_masked
13657
13658 static const struct drm_crtc_funcs intel_crtc_funcs = {
13659 .gamma_set = intel_crtc_gamma_set,
13660 .set_config = drm_atomic_helper_set_config,
13661 .destroy = intel_crtc_destroy,
13662 .page_flip = intel_crtc_page_flip,
13663 .atomic_duplicate_state = intel_crtc_duplicate_state,
13664 .atomic_destroy_state = intel_crtc_destroy_state,
13665 };
13666
13667 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13668 struct intel_shared_dpll *pll,
13669 struct intel_dpll_hw_state *hw_state)
13670 {
13671 uint32_t val;
13672
13673 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13674 return false;
13675
13676 val = I915_READ(PCH_DPLL(pll->id));
13677 hw_state->dpll = val;
13678 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13679 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13680
13681 return val & DPLL_VCO_ENABLE;
13682 }
13683
13684 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13685 struct intel_shared_dpll *pll)
13686 {
13687 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13688 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13689 }
13690
13691 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13692 struct intel_shared_dpll *pll)
13693 {
13694 /* PCH refclock must be enabled first */
13695 ibx_assert_pch_refclk_enabled(dev_priv);
13696
13697 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13698
13699 /* Wait for the clocks to stabilize. */
13700 POSTING_READ(PCH_DPLL(pll->id));
13701 udelay(150);
13702
13703 /* The pixel multiplier can only be updated once the
13704 * DPLL is enabled and the clocks are stable.
13705 *
13706 * So write it again.
13707 */
13708 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13709 POSTING_READ(PCH_DPLL(pll->id));
13710 udelay(200);
13711 }
13712
13713 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13714 struct intel_shared_dpll *pll)
13715 {
13716 struct drm_device *dev = dev_priv->dev;
13717 struct intel_crtc *crtc;
13718
13719 /* Make sure no transcoder isn't still depending on us. */
13720 for_each_intel_crtc(dev, crtc) {
13721 if (intel_crtc_to_shared_dpll(crtc) == pll)
13722 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13723 }
13724
13725 I915_WRITE(PCH_DPLL(pll->id), 0);
13726 POSTING_READ(PCH_DPLL(pll->id));
13727 udelay(200);
13728 }
13729
13730 static char *ibx_pch_dpll_names[] = {
13731 "PCH DPLL A",
13732 "PCH DPLL B",
13733 };
13734
13735 static void ibx_pch_dpll_init(struct drm_device *dev)
13736 {
13737 struct drm_i915_private *dev_priv = dev->dev_private;
13738 int i;
13739
13740 dev_priv->num_shared_dpll = 2;
13741
13742 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13743 dev_priv->shared_dplls[i].id = i;
13744 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13745 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13746 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13747 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13748 dev_priv->shared_dplls[i].get_hw_state =
13749 ibx_pch_dpll_get_hw_state;
13750 }
13751 }
13752
13753 static void intel_shared_dpll_init(struct drm_device *dev)
13754 {
13755 struct drm_i915_private *dev_priv = dev->dev_private;
13756
13757 if (HAS_DDI(dev))
13758 intel_ddi_pll_init(dev);
13759 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13760 ibx_pch_dpll_init(dev);
13761 else
13762 dev_priv->num_shared_dpll = 0;
13763
13764 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13765 }
13766
13767 /**
13768 * intel_prepare_plane_fb - Prepare fb for usage on plane
13769 * @plane: drm plane to prepare for
13770 * @fb: framebuffer to prepare for presentation
13771 *
13772 * Prepares a framebuffer for usage on a display plane. Generally this
13773 * involves pinning the underlying object and updating the frontbuffer tracking
13774 * bits. Some older platforms need special physical address handling for
13775 * cursor planes.
13776 *
13777 * Must be called with struct_mutex held.
13778 *
13779 * Returns 0 on success, negative error code on failure.
13780 */
13781 int
13782 intel_prepare_plane_fb(struct drm_plane *plane,
13783 const struct drm_plane_state *new_state)
13784 {
13785 struct drm_device *dev = plane->dev;
13786 struct drm_framebuffer *fb = new_state->fb;
13787 struct intel_plane *intel_plane = to_intel_plane(plane);
13788 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13789 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13790 int ret = 0;
13791
13792 if (!obj && !old_obj)
13793 return 0;
13794
13795 if (old_obj) {
13796 struct drm_crtc_state *crtc_state =
13797 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13798
13799 /* Big Hammer, we also need to ensure that any pending
13800 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13801 * current scanout is retired before unpinning the old
13802 * framebuffer. Note that we rely on userspace rendering
13803 * into the buffer attached to the pipe they are waiting
13804 * on. If not, userspace generates a GPU hang with IPEHR
13805 * point to the MI_WAIT_FOR_EVENT.
13806 *
13807 * This should only fail upon a hung GPU, in which case we
13808 * can safely continue.
13809 */
13810 if (needs_modeset(crtc_state))
13811 ret = i915_gem_object_wait_rendering(old_obj, true);
13812
13813 /* Swallow -EIO errors to allow updates during hw lockup. */
13814 if (ret && ret != -EIO)
13815 return ret;
13816 }
13817
13818 /* For framebuffer backed by dmabuf, wait for fence */
13819 if (obj && obj->base.dma_buf) {
13820 long lret;
13821
13822 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13823 false, true,
13824 MAX_SCHEDULE_TIMEOUT);
13825 if (lret == -ERESTARTSYS)
13826 return lret;
13827
13828 WARN(lret < 0, "waiting returns %li\n", lret);
13829 }
13830
13831 if (!obj) {
13832 ret = 0;
13833 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13834 INTEL_INFO(dev)->cursor_needs_physical) {
13835 int align = IS_I830(dev) ? 16 * 1024 : 256;
13836 ret = i915_gem_object_attach_phys(obj, align);
13837 if (ret)
13838 DRM_DEBUG_KMS("failed to attach phys object\n");
13839 } else {
13840 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13841 }
13842
13843 if (ret == 0) {
13844 if (obj) {
13845 struct intel_plane_state *plane_state =
13846 to_intel_plane_state(new_state);
13847
13848 i915_gem_request_assign(&plane_state->wait_req,
13849 obj->last_write_req);
13850 }
13851
13852 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13853 }
13854
13855 return ret;
13856 }
13857
13858 /**
13859 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13860 * @plane: drm plane to clean up for
13861 * @fb: old framebuffer that was on plane
13862 *
13863 * Cleans up a framebuffer that has just been removed from a plane.
13864 *
13865 * Must be called with struct_mutex held.
13866 */
13867 void
13868 intel_cleanup_plane_fb(struct drm_plane *plane,
13869 const struct drm_plane_state *old_state)
13870 {
13871 struct drm_device *dev = plane->dev;
13872 struct intel_plane *intel_plane = to_intel_plane(plane);
13873 struct intel_plane_state *old_intel_state;
13874 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13875 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13876
13877 old_intel_state = to_intel_plane_state(old_state);
13878
13879 if (!obj && !old_obj)
13880 return;
13881
13882 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13883 !INTEL_INFO(dev)->cursor_needs_physical))
13884 intel_unpin_fb_obj(old_state->fb, old_state);
13885
13886 /* prepare_fb aborted? */
13887 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13888 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13889 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13890
13891 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13892
13893 }
13894
13895 int
13896 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13897 {
13898 int max_scale;
13899 struct drm_device *dev;
13900 struct drm_i915_private *dev_priv;
13901 int crtc_clock, cdclk;
13902
13903 if (!intel_crtc || !crtc_state->base.enable)
13904 return DRM_PLANE_HELPER_NO_SCALING;
13905
13906 dev = intel_crtc->base.dev;
13907 dev_priv = dev->dev_private;
13908 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13909 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13910
13911 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13912 return DRM_PLANE_HELPER_NO_SCALING;
13913
13914 /*
13915 * skl max scale is lower of:
13916 * close to 3 but not 3, -1 is for that purpose
13917 * or
13918 * cdclk/crtc_clock
13919 */
13920 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13921
13922 return max_scale;
13923 }
13924
13925 static int
13926 intel_check_primary_plane(struct drm_plane *plane,
13927 struct intel_crtc_state *crtc_state,
13928 struct intel_plane_state *state)
13929 {
13930 struct drm_crtc *crtc = state->base.crtc;
13931 struct drm_framebuffer *fb = state->base.fb;
13932 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13933 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13934 bool can_position = false;
13935
13936 if (INTEL_INFO(plane->dev)->gen >= 9) {
13937 /* use scaler when colorkey is not required */
13938 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13939 min_scale = 1;
13940 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13941 }
13942 can_position = true;
13943 }
13944
13945 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13946 &state->dst, &state->clip,
13947 min_scale, max_scale,
13948 can_position, true,
13949 &state->visible);
13950 }
13951
13952 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13953 struct drm_crtc_state *old_crtc_state)
13954 {
13955 struct drm_device *dev = crtc->dev;
13956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13957 struct intel_crtc_state *old_intel_state =
13958 to_intel_crtc_state(old_crtc_state);
13959 bool modeset = needs_modeset(crtc->state);
13960
13961 /* Perform vblank evasion around commit operation */
13962 intel_pipe_update_start(intel_crtc);
13963
13964 if (modeset)
13965 return;
13966
13967 if (to_intel_crtc_state(crtc->state)->update_pipe)
13968 intel_update_pipe_config(intel_crtc, old_intel_state);
13969 else if (INTEL_INFO(dev)->gen >= 9)
13970 skl_detach_scalers(intel_crtc);
13971 }
13972
13973 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13974 struct drm_crtc_state *old_crtc_state)
13975 {
13976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13977
13978 intel_pipe_update_end(intel_crtc);
13979 }
13980
13981 /**
13982 * intel_plane_destroy - destroy a plane
13983 * @plane: plane to destroy
13984 *
13985 * Common destruction function for all types of planes (primary, cursor,
13986 * sprite).
13987 */
13988 void intel_plane_destroy(struct drm_plane *plane)
13989 {
13990 struct intel_plane *intel_plane = to_intel_plane(plane);
13991 drm_plane_cleanup(plane);
13992 kfree(intel_plane);
13993 }
13994
13995 const struct drm_plane_funcs intel_plane_funcs = {
13996 .update_plane = drm_atomic_helper_update_plane,
13997 .disable_plane = drm_atomic_helper_disable_plane,
13998 .destroy = intel_plane_destroy,
13999 .set_property = drm_atomic_helper_plane_set_property,
14000 .atomic_get_property = intel_plane_atomic_get_property,
14001 .atomic_set_property = intel_plane_atomic_set_property,
14002 .atomic_duplicate_state = intel_plane_duplicate_state,
14003 .atomic_destroy_state = intel_plane_destroy_state,
14004
14005 };
14006
14007 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14008 int pipe)
14009 {
14010 struct intel_plane *primary;
14011 struct intel_plane_state *state;
14012 const uint32_t *intel_primary_formats;
14013 unsigned int num_formats;
14014
14015 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14016 if (primary == NULL)
14017 return NULL;
14018
14019 state = intel_create_plane_state(&primary->base);
14020 if (!state) {
14021 kfree(primary);
14022 return NULL;
14023 }
14024 primary->base.state = &state->base;
14025
14026 primary->can_scale = false;
14027 primary->max_downscale = 1;
14028 if (INTEL_INFO(dev)->gen >= 9) {
14029 primary->can_scale = true;
14030 state->scaler_id = -1;
14031 }
14032 primary->pipe = pipe;
14033 primary->plane = pipe;
14034 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14035 primary->check_plane = intel_check_primary_plane;
14036 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14037 primary->plane = !pipe;
14038
14039 if (INTEL_INFO(dev)->gen >= 9) {
14040 intel_primary_formats = skl_primary_formats;
14041 num_formats = ARRAY_SIZE(skl_primary_formats);
14042
14043 primary->update_plane = skylake_update_primary_plane;
14044 primary->disable_plane = skylake_disable_primary_plane;
14045 } else if (HAS_PCH_SPLIT(dev)) {
14046 intel_primary_formats = i965_primary_formats;
14047 num_formats = ARRAY_SIZE(i965_primary_formats);
14048
14049 primary->update_plane = ironlake_update_primary_plane;
14050 primary->disable_plane = i9xx_disable_primary_plane;
14051 } else if (INTEL_INFO(dev)->gen >= 4) {
14052 intel_primary_formats = i965_primary_formats;
14053 num_formats = ARRAY_SIZE(i965_primary_formats);
14054
14055 primary->update_plane = i9xx_update_primary_plane;
14056 primary->disable_plane = i9xx_disable_primary_plane;
14057 } else {
14058 intel_primary_formats = i8xx_primary_formats;
14059 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14060
14061 primary->update_plane = i9xx_update_primary_plane;
14062 primary->disable_plane = i9xx_disable_primary_plane;
14063 }
14064
14065 drm_universal_plane_init(dev, &primary->base, 0,
14066 &intel_plane_funcs,
14067 intel_primary_formats, num_formats,
14068 DRM_PLANE_TYPE_PRIMARY, NULL);
14069
14070 if (INTEL_INFO(dev)->gen >= 4)
14071 intel_create_rotation_property(dev, primary);
14072
14073 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14074
14075 return &primary->base;
14076 }
14077
14078 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14079 {
14080 if (!dev->mode_config.rotation_property) {
14081 unsigned long flags = BIT(DRM_ROTATE_0) |
14082 BIT(DRM_ROTATE_180);
14083
14084 if (INTEL_INFO(dev)->gen >= 9)
14085 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14086
14087 dev->mode_config.rotation_property =
14088 drm_mode_create_rotation_property(dev, flags);
14089 }
14090 if (dev->mode_config.rotation_property)
14091 drm_object_attach_property(&plane->base.base,
14092 dev->mode_config.rotation_property,
14093 plane->base.state->rotation);
14094 }
14095
14096 static int
14097 intel_check_cursor_plane(struct drm_plane *plane,
14098 struct intel_crtc_state *crtc_state,
14099 struct intel_plane_state *state)
14100 {
14101 struct drm_crtc *crtc = crtc_state->base.crtc;
14102 struct drm_framebuffer *fb = state->base.fb;
14103 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14104 enum pipe pipe = to_intel_plane(plane)->pipe;
14105 unsigned stride;
14106 int ret;
14107
14108 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14109 &state->dst, &state->clip,
14110 DRM_PLANE_HELPER_NO_SCALING,
14111 DRM_PLANE_HELPER_NO_SCALING,
14112 true, true, &state->visible);
14113 if (ret)
14114 return ret;
14115
14116 /* if we want to turn off the cursor ignore width and height */
14117 if (!obj)
14118 return 0;
14119
14120 /* Check for which cursor types we support */
14121 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14122 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14123 state->base.crtc_w, state->base.crtc_h);
14124 return -EINVAL;
14125 }
14126
14127 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14128 if (obj->base.size < stride * state->base.crtc_h) {
14129 DRM_DEBUG_KMS("buffer is too small\n");
14130 return -ENOMEM;
14131 }
14132
14133 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14134 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14135 return -EINVAL;
14136 }
14137
14138 /*
14139 * There's something wrong with the cursor on CHV pipe C.
14140 * If it straddles the left edge of the screen then
14141 * moving it away from the edge or disabling it often
14142 * results in a pipe underrun, and often that can lead to
14143 * dead pipe (constant underrun reported, and it scans
14144 * out just a solid color). To recover from that, the
14145 * display power well must be turned off and on again.
14146 * Refuse the put the cursor into that compromised position.
14147 */
14148 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14149 state->visible && state->base.crtc_x < 0) {
14150 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14151 return -EINVAL;
14152 }
14153
14154 return 0;
14155 }
14156
14157 static void
14158 intel_disable_cursor_plane(struct drm_plane *plane,
14159 struct drm_crtc *crtc)
14160 {
14161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14162
14163 intel_crtc->cursor_addr = 0;
14164 intel_crtc_update_cursor(crtc, NULL);
14165 }
14166
14167 static void
14168 intel_update_cursor_plane(struct drm_plane *plane,
14169 const struct intel_crtc_state *crtc_state,
14170 const struct intel_plane_state *state)
14171 {
14172 struct drm_crtc *crtc = crtc_state->base.crtc;
14173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14174 struct drm_device *dev = plane->dev;
14175 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14176 uint32_t addr;
14177
14178 if (!obj)
14179 addr = 0;
14180 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14181 addr = i915_gem_obj_ggtt_offset(obj);
14182 else
14183 addr = obj->phys_handle->busaddr;
14184
14185 intel_crtc->cursor_addr = addr;
14186 intel_crtc_update_cursor(crtc, state);
14187 }
14188
14189 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14190 int pipe)
14191 {
14192 struct intel_plane *cursor;
14193 struct intel_plane_state *state;
14194
14195 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14196 if (cursor == NULL)
14197 return NULL;
14198
14199 state = intel_create_plane_state(&cursor->base);
14200 if (!state) {
14201 kfree(cursor);
14202 return NULL;
14203 }
14204 cursor->base.state = &state->base;
14205
14206 cursor->can_scale = false;
14207 cursor->max_downscale = 1;
14208 cursor->pipe = pipe;
14209 cursor->plane = pipe;
14210 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14211 cursor->check_plane = intel_check_cursor_plane;
14212 cursor->update_plane = intel_update_cursor_plane;
14213 cursor->disable_plane = intel_disable_cursor_plane;
14214
14215 drm_universal_plane_init(dev, &cursor->base, 0,
14216 &intel_plane_funcs,
14217 intel_cursor_formats,
14218 ARRAY_SIZE(intel_cursor_formats),
14219 DRM_PLANE_TYPE_CURSOR, NULL);
14220
14221 if (INTEL_INFO(dev)->gen >= 4) {
14222 if (!dev->mode_config.rotation_property)
14223 dev->mode_config.rotation_property =
14224 drm_mode_create_rotation_property(dev,
14225 BIT(DRM_ROTATE_0) |
14226 BIT(DRM_ROTATE_180));
14227 if (dev->mode_config.rotation_property)
14228 drm_object_attach_property(&cursor->base.base,
14229 dev->mode_config.rotation_property,
14230 state->base.rotation);
14231 }
14232
14233 if (INTEL_INFO(dev)->gen >=9)
14234 state->scaler_id = -1;
14235
14236 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14237
14238 return &cursor->base;
14239 }
14240
14241 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14242 struct intel_crtc_state *crtc_state)
14243 {
14244 int i;
14245 struct intel_scaler *intel_scaler;
14246 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14247
14248 for (i = 0; i < intel_crtc->num_scalers; i++) {
14249 intel_scaler = &scaler_state->scalers[i];
14250 intel_scaler->in_use = 0;
14251 intel_scaler->mode = PS_SCALER_MODE_DYN;
14252 }
14253
14254 scaler_state->scaler_id = -1;
14255 }
14256
14257 static void intel_crtc_init(struct drm_device *dev, int pipe)
14258 {
14259 struct drm_i915_private *dev_priv = dev->dev_private;
14260 struct intel_crtc *intel_crtc;
14261 struct intel_crtc_state *crtc_state = NULL;
14262 struct drm_plane *primary = NULL;
14263 struct drm_plane *cursor = NULL;
14264 int i, ret;
14265
14266 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14267 if (intel_crtc == NULL)
14268 return;
14269
14270 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14271 if (!crtc_state)
14272 goto fail;
14273 intel_crtc->config = crtc_state;
14274 intel_crtc->base.state = &crtc_state->base;
14275 crtc_state->base.crtc = &intel_crtc->base;
14276
14277 /* initialize shared scalers */
14278 if (INTEL_INFO(dev)->gen >= 9) {
14279 if (pipe == PIPE_C)
14280 intel_crtc->num_scalers = 1;
14281 else
14282 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14283
14284 skl_init_scalers(dev, intel_crtc, crtc_state);
14285 }
14286
14287 primary = intel_primary_plane_create(dev, pipe);
14288 if (!primary)
14289 goto fail;
14290
14291 cursor = intel_cursor_plane_create(dev, pipe);
14292 if (!cursor)
14293 goto fail;
14294
14295 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14296 cursor, &intel_crtc_funcs, NULL);
14297 if (ret)
14298 goto fail;
14299
14300 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14301 for (i = 0; i < 256; i++) {
14302 intel_crtc->lut_r[i] = i;
14303 intel_crtc->lut_g[i] = i;
14304 intel_crtc->lut_b[i] = i;
14305 }
14306
14307 /*
14308 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14309 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14310 */
14311 intel_crtc->pipe = pipe;
14312 intel_crtc->plane = pipe;
14313 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14314 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14315 intel_crtc->plane = !pipe;
14316 }
14317
14318 intel_crtc->cursor_base = ~0;
14319 intel_crtc->cursor_cntl = ~0;
14320 intel_crtc->cursor_size = ~0;
14321
14322 intel_crtc->wm.cxsr_allowed = true;
14323
14324 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14325 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14326 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14327 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14328
14329 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14330
14331 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14332 return;
14333
14334 fail:
14335 if (primary)
14336 drm_plane_cleanup(primary);
14337 if (cursor)
14338 drm_plane_cleanup(cursor);
14339 kfree(crtc_state);
14340 kfree(intel_crtc);
14341 }
14342
14343 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14344 {
14345 struct drm_encoder *encoder = connector->base.encoder;
14346 struct drm_device *dev = connector->base.dev;
14347
14348 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14349
14350 if (!encoder || WARN_ON(!encoder->crtc))
14351 return INVALID_PIPE;
14352
14353 return to_intel_crtc(encoder->crtc)->pipe;
14354 }
14355
14356 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14357 struct drm_file *file)
14358 {
14359 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14360 struct drm_crtc *drmmode_crtc;
14361 struct intel_crtc *crtc;
14362
14363 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14364
14365 if (!drmmode_crtc) {
14366 DRM_ERROR("no such CRTC id\n");
14367 return -ENOENT;
14368 }
14369
14370 crtc = to_intel_crtc(drmmode_crtc);
14371 pipe_from_crtc_id->pipe = crtc->pipe;
14372
14373 return 0;
14374 }
14375
14376 static int intel_encoder_clones(struct intel_encoder *encoder)
14377 {
14378 struct drm_device *dev = encoder->base.dev;
14379 struct intel_encoder *source_encoder;
14380 int index_mask = 0;
14381 int entry = 0;
14382
14383 for_each_intel_encoder(dev, source_encoder) {
14384 if (encoders_cloneable(encoder, source_encoder))
14385 index_mask |= (1 << entry);
14386
14387 entry++;
14388 }
14389
14390 return index_mask;
14391 }
14392
14393 static bool has_edp_a(struct drm_device *dev)
14394 {
14395 struct drm_i915_private *dev_priv = dev->dev_private;
14396
14397 if (!IS_MOBILE(dev))
14398 return false;
14399
14400 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14401 return false;
14402
14403 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14404 return false;
14405
14406 return true;
14407 }
14408
14409 static bool intel_crt_present(struct drm_device *dev)
14410 {
14411 struct drm_i915_private *dev_priv = dev->dev_private;
14412
14413 if (INTEL_INFO(dev)->gen >= 9)
14414 return false;
14415
14416 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14417 return false;
14418
14419 if (IS_CHERRYVIEW(dev))
14420 return false;
14421
14422 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14423 return false;
14424
14425 /* DDI E can't be used if DDI A requires 4 lanes */
14426 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14427 return false;
14428
14429 if (!dev_priv->vbt.int_crt_support)
14430 return false;
14431
14432 return true;
14433 }
14434
14435 static void intel_setup_outputs(struct drm_device *dev)
14436 {
14437 struct drm_i915_private *dev_priv = dev->dev_private;
14438 struct intel_encoder *encoder;
14439 bool dpd_is_edp = false;
14440
14441 intel_lvds_init(dev);
14442
14443 if (intel_crt_present(dev))
14444 intel_crt_init(dev);
14445
14446 if (IS_BROXTON(dev)) {
14447 /*
14448 * FIXME: Broxton doesn't support port detection via the
14449 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14450 * detect the ports.
14451 */
14452 intel_ddi_init(dev, PORT_A);
14453 intel_ddi_init(dev, PORT_B);
14454 intel_ddi_init(dev, PORT_C);
14455 } else if (HAS_DDI(dev)) {
14456 int found;
14457
14458 /*
14459 * Haswell uses DDI functions to detect digital outputs.
14460 * On SKL pre-D0 the strap isn't connected, so we assume
14461 * it's there.
14462 */
14463 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14464 /* WaIgnoreDDIAStrap: skl */
14465 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14466 intel_ddi_init(dev, PORT_A);
14467
14468 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14469 * register */
14470 found = I915_READ(SFUSE_STRAP);
14471
14472 if (found & SFUSE_STRAP_DDIB_DETECTED)
14473 intel_ddi_init(dev, PORT_B);
14474 if (found & SFUSE_STRAP_DDIC_DETECTED)
14475 intel_ddi_init(dev, PORT_C);
14476 if (found & SFUSE_STRAP_DDID_DETECTED)
14477 intel_ddi_init(dev, PORT_D);
14478 /*
14479 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14480 */
14481 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14482 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14483 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14484 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14485 intel_ddi_init(dev, PORT_E);
14486
14487 } else if (HAS_PCH_SPLIT(dev)) {
14488 int found;
14489 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14490
14491 if (has_edp_a(dev))
14492 intel_dp_init(dev, DP_A, PORT_A);
14493
14494 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14495 /* PCH SDVOB multiplex with HDMIB */
14496 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14497 if (!found)
14498 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14499 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14500 intel_dp_init(dev, PCH_DP_B, PORT_B);
14501 }
14502
14503 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14504 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14505
14506 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14507 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14508
14509 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14510 intel_dp_init(dev, PCH_DP_C, PORT_C);
14511
14512 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14513 intel_dp_init(dev, PCH_DP_D, PORT_D);
14514 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14515 /*
14516 * The DP_DETECTED bit is the latched state of the DDC
14517 * SDA pin at boot. However since eDP doesn't require DDC
14518 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14519 * eDP ports may have been muxed to an alternate function.
14520 * Thus we can't rely on the DP_DETECTED bit alone to detect
14521 * eDP ports. Consult the VBT as well as DP_DETECTED to
14522 * detect eDP ports.
14523 */
14524 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14525 !intel_dp_is_edp(dev, PORT_B))
14526 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14527 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14528 intel_dp_is_edp(dev, PORT_B))
14529 intel_dp_init(dev, VLV_DP_B, PORT_B);
14530
14531 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14532 !intel_dp_is_edp(dev, PORT_C))
14533 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14534 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14535 intel_dp_is_edp(dev, PORT_C))
14536 intel_dp_init(dev, VLV_DP_C, PORT_C);
14537
14538 if (IS_CHERRYVIEW(dev)) {
14539 /* eDP not supported on port D, so don't check VBT */
14540 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14541 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14542 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14543 intel_dp_init(dev, CHV_DP_D, PORT_D);
14544 }
14545
14546 intel_dsi_init(dev);
14547 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14548 bool found = false;
14549
14550 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14551 DRM_DEBUG_KMS("probing SDVOB\n");
14552 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14553 if (!found && IS_G4X(dev)) {
14554 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14555 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14556 }
14557
14558 if (!found && IS_G4X(dev))
14559 intel_dp_init(dev, DP_B, PORT_B);
14560 }
14561
14562 /* Before G4X SDVOC doesn't have its own detect register */
14563
14564 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14565 DRM_DEBUG_KMS("probing SDVOC\n");
14566 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14567 }
14568
14569 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14570
14571 if (IS_G4X(dev)) {
14572 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14573 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14574 }
14575 if (IS_G4X(dev))
14576 intel_dp_init(dev, DP_C, PORT_C);
14577 }
14578
14579 if (IS_G4X(dev) &&
14580 (I915_READ(DP_D) & DP_DETECTED))
14581 intel_dp_init(dev, DP_D, PORT_D);
14582 } else if (IS_GEN2(dev))
14583 intel_dvo_init(dev);
14584
14585 if (SUPPORTS_TV(dev))
14586 intel_tv_init(dev);
14587
14588 intel_psr_init(dev);
14589
14590 for_each_intel_encoder(dev, encoder) {
14591 encoder->base.possible_crtcs = encoder->crtc_mask;
14592 encoder->base.possible_clones =
14593 intel_encoder_clones(encoder);
14594 }
14595
14596 intel_init_pch_refclk(dev);
14597
14598 drm_helper_move_panel_connectors_to_head(dev);
14599 }
14600
14601 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14602 {
14603 struct drm_device *dev = fb->dev;
14604 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14605
14606 drm_framebuffer_cleanup(fb);
14607 mutex_lock(&dev->struct_mutex);
14608 WARN_ON(!intel_fb->obj->framebuffer_references--);
14609 drm_gem_object_unreference(&intel_fb->obj->base);
14610 mutex_unlock(&dev->struct_mutex);
14611 kfree(intel_fb);
14612 }
14613
14614 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14615 struct drm_file *file,
14616 unsigned int *handle)
14617 {
14618 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14619 struct drm_i915_gem_object *obj = intel_fb->obj;
14620
14621 if (obj->userptr.mm) {
14622 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14623 return -EINVAL;
14624 }
14625
14626 return drm_gem_handle_create(file, &obj->base, handle);
14627 }
14628
14629 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14630 struct drm_file *file,
14631 unsigned flags, unsigned color,
14632 struct drm_clip_rect *clips,
14633 unsigned num_clips)
14634 {
14635 struct drm_device *dev = fb->dev;
14636 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14637 struct drm_i915_gem_object *obj = intel_fb->obj;
14638
14639 mutex_lock(&dev->struct_mutex);
14640 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14641 mutex_unlock(&dev->struct_mutex);
14642
14643 return 0;
14644 }
14645
14646 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14647 .destroy = intel_user_framebuffer_destroy,
14648 .create_handle = intel_user_framebuffer_create_handle,
14649 .dirty = intel_user_framebuffer_dirty,
14650 };
14651
14652 static
14653 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14654 uint32_t pixel_format)
14655 {
14656 u32 gen = INTEL_INFO(dev)->gen;
14657
14658 if (gen >= 9) {
14659 int cpp = drm_format_plane_cpp(pixel_format, 0);
14660
14661 /* "The stride in bytes must not exceed the of the size of 8K
14662 * pixels and 32K bytes."
14663 */
14664 return min(8192 * cpp, 32768);
14665 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14666 return 32*1024;
14667 } else if (gen >= 4) {
14668 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14669 return 16*1024;
14670 else
14671 return 32*1024;
14672 } else if (gen >= 3) {
14673 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14674 return 8*1024;
14675 else
14676 return 16*1024;
14677 } else {
14678 /* XXX DSPC is limited to 4k tiled */
14679 return 8*1024;
14680 }
14681 }
14682
14683 static int intel_framebuffer_init(struct drm_device *dev,
14684 struct intel_framebuffer *intel_fb,
14685 struct drm_mode_fb_cmd2 *mode_cmd,
14686 struct drm_i915_gem_object *obj)
14687 {
14688 struct drm_i915_private *dev_priv = to_i915(dev);
14689 unsigned int aligned_height;
14690 int ret;
14691 u32 pitch_limit, stride_alignment;
14692
14693 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14694
14695 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14696 /* Enforce that fb modifier and tiling mode match, but only for
14697 * X-tiled. This is needed for FBC. */
14698 if (!!(obj->tiling_mode == I915_TILING_X) !=
14699 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14700 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14701 return -EINVAL;
14702 }
14703 } else {
14704 if (obj->tiling_mode == I915_TILING_X)
14705 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14706 else if (obj->tiling_mode == I915_TILING_Y) {
14707 DRM_DEBUG("No Y tiling for legacy addfb\n");
14708 return -EINVAL;
14709 }
14710 }
14711
14712 /* Passed in modifier sanity checking. */
14713 switch (mode_cmd->modifier[0]) {
14714 case I915_FORMAT_MOD_Y_TILED:
14715 case I915_FORMAT_MOD_Yf_TILED:
14716 if (INTEL_INFO(dev)->gen < 9) {
14717 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14718 mode_cmd->modifier[0]);
14719 return -EINVAL;
14720 }
14721 case DRM_FORMAT_MOD_NONE:
14722 case I915_FORMAT_MOD_X_TILED:
14723 break;
14724 default:
14725 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14726 mode_cmd->modifier[0]);
14727 return -EINVAL;
14728 }
14729
14730 stride_alignment = intel_fb_stride_alignment(dev_priv,
14731 mode_cmd->modifier[0],
14732 mode_cmd->pixel_format);
14733 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14734 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14735 mode_cmd->pitches[0], stride_alignment);
14736 return -EINVAL;
14737 }
14738
14739 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14740 mode_cmd->pixel_format);
14741 if (mode_cmd->pitches[0] > pitch_limit) {
14742 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14743 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14744 "tiled" : "linear",
14745 mode_cmd->pitches[0], pitch_limit);
14746 return -EINVAL;
14747 }
14748
14749 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14750 mode_cmd->pitches[0] != obj->stride) {
14751 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14752 mode_cmd->pitches[0], obj->stride);
14753 return -EINVAL;
14754 }
14755
14756 /* Reject formats not supported by any plane early. */
14757 switch (mode_cmd->pixel_format) {
14758 case DRM_FORMAT_C8:
14759 case DRM_FORMAT_RGB565:
14760 case DRM_FORMAT_XRGB8888:
14761 case DRM_FORMAT_ARGB8888:
14762 break;
14763 case DRM_FORMAT_XRGB1555:
14764 if (INTEL_INFO(dev)->gen > 3) {
14765 DRM_DEBUG("unsupported pixel format: %s\n",
14766 drm_get_format_name(mode_cmd->pixel_format));
14767 return -EINVAL;
14768 }
14769 break;
14770 case DRM_FORMAT_ABGR8888:
14771 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14772 INTEL_INFO(dev)->gen < 9) {
14773 DRM_DEBUG("unsupported pixel format: %s\n",
14774 drm_get_format_name(mode_cmd->pixel_format));
14775 return -EINVAL;
14776 }
14777 break;
14778 case DRM_FORMAT_XBGR8888:
14779 case DRM_FORMAT_XRGB2101010:
14780 case DRM_FORMAT_XBGR2101010:
14781 if (INTEL_INFO(dev)->gen < 4) {
14782 DRM_DEBUG("unsupported pixel format: %s\n",
14783 drm_get_format_name(mode_cmd->pixel_format));
14784 return -EINVAL;
14785 }
14786 break;
14787 case DRM_FORMAT_ABGR2101010:
14788 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14789 DRM_DEBUG("unsupported pixel format: %s\n",
14790 drm_get_format_name(mode_cmd->pixel_format));
14791 return -EINVAL;
14792 }
14793 break;
14794 case DRM_FORMAT_YUYV:
14795 case DRM_FORMAT_UYVY:
14796 case DRM_FORMAT_YVYU:
14797 case DRM_FORMAT_VYUY:
14798 if (INTEL_INFO(dev)->gen < 5) {
14799 DRM_DEBUG("unsupported pixel format: %s\n",
14800 drm_get_format_name(mode_cmd->pixel_format));
14801 return -EINVAL;
14802 }
14803 break;
14804 default:
14805 DRM_DEBUG("unsupported pixel format: %s\n",
14806 drm_get_format_name(mode_cmd->pixel_format));
14807 return -EINVAL;
14808 }
14809
14810 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14811 if (mode_cmd->offsets[0] != 0)
14812 return -EINVAL;
14813
14814 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14815 mode_cmd->pixel_format,
14816 mode_cmd->modifier[0]);
14817 /* FIXME drm helper for size checks (especially planar formats)? */
14818 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14819 return -EINVAL;
14820
14821 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14822 intel_fb->obj = obj;
14823
14824 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14825 if (ret) {
14826 DRM_ERROR("framebuffer init failed %d\n", ret);
14827 return ret;
14828 }
14829
14830 intel_fb->obj->framebuffer_references++;
14831
14832 return 0;
14833 }
14834
14835 static struct drm_framebuffer *
14836 intel_user_framebuffer_create(struct drm_device *dev,
14837 struct drm_file *filp,
14838 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14839 {
14840 struct drm_framebuffer *fb;
14841 struct drm_i915_gem_object *obj;
14842 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14843
14844 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14845 mode_cmd.handles[0]));
14846 if (&obj->base == NULL)
14847 return ERR_PTR(-ENOENT);
14848
14849 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14850 if (IS_ERR(fb))
14851 drm_gem_object_unreference_unlocked(&obj->base);
14852
14853 return fb;
14854 }
14855
14856 #ifndef CONFIG_DRM_FBDEV_EMULATION
14857 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14858 {
14859 }
14860 #endif
14861
14862 static const struct drm_mode_config_funcs intel_mode_funcs = {
14863 .fb_create = intel_user_framebuffer_create,
14864 .output_poll_changed = intel_fbdev_output_poll_changed,
14865 .atomic_check = intel_atomic_check,
14866 .atomic_commit = intel_atomic_commit,
14867 .atomic_state_alloc = intel_atomic_state_alloc,
14868 .atomic_state_clear = intel_atomic_state_clear,
14869 };
14870
14871 /* Set up chip specific display functions */
14872 static void intel_init_display(struct drm_device *dev)
14873 {
14874 struct drm_i915_private *dev_priv = dev->dev_private;
14875
14876 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14877 dev_priv->display.find_dpll = g4x_find_best_dpll;
14878 else if (IS_CHERRYVIEW(dev))
14879 dev_priv->display.find_dpll = chv_find_best_dpll;
14880 else if (IS_VALLEYVIEW(dev))
14881 dev_priv->display.find_dpll = vlv_find_best_dpll;
14882 else if (IS_PINEVIEW(dev))
14883 dev_priv->display.find_dpll = pnv_find_best_dpll;
14884 else
14885 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14886
14887 if (INTEL_INFO(dev)->gen >= 9) {
14888 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14889 dev_priv->display.get_initial_plane_config =
14890 skylake_get_initial_plane_config;
14891 dev_priv->display.crtc_compute_clock =
14892 haswell_crtc_compute_clock;
14893 dev_priv->display.crtc_enable = haswell_crtc_enable;
14894 dev_priv->display.crtc_disable = haswell_crtc_disable;
14895 } else if (HAS_DDI(dev)) {
14896 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14897 dev_priv->display.get_initial_plane_config =
14898 ironlake_get_initial_plane_config;
14899 dev_priv->display.crtc_compute_clock =
14900 haswell_crtc_compute_clock;
14901 dev_priv->display.crtc_enable = haswell_crtc_enable;
14902 dev_priv->display.crtc_disable = haswell_crtc_disable;
14903 } else if (HAS_PCH_SPLIT(dev)) {
14904 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14905 dev_priv->display.get_initial_plane_config =
14906 ironlake_get_initial_plane_config;
14907 dev_priv->display.crtc_compute_clock =
14908 ironlake_crtc_compute_clock;
14909 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14910 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14911 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14912 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14913 dev_priv->display.get_initial_plane_config =
14914 i9xx_get_initial_plane_config;
14915 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14916 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14917 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14918 } else {
14919 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14920 dev_priv->display.get_initial_plane_config =
14921 i9xx_get_initial_plane_config;
14922 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14923 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14924 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14925 }
14926
14927 /* Returns the core display clock speed */
14928 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14929 dev_priv->display.get_display_clock_speed =
14930 skylake_get_display_clock_speed;
14931 else if (IS_BROXTON(dev))
14932 dev_priv->display.get_display_clock_speed =
14933 broxton_get_display_clock_speed;
14934 else if (IS_BROADWELL(dev))
14935 dev_priv->display.get_display_clock_speed =
14936 broadwell_get_display_clock_speed;
14937 else if (IS_HASWELL(dev))
14938 dev_priv->display.get_display_clock_speed =
14939 haswell_get_display_clock_speed;
14940 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14941 dev_priv->display.get_display_clock_speed =
14942 valleyview_get_display_clock_speed;
14943 else if (IS_GEN5(dev))
14944 dev_priv->display.get_display_clock_speed =
14945 ilk_get_display_clock_speed;
14946 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14947 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14948 dev_priv->display.get_display_clock_speed =
14949 i945_get_display_clock_speed;
14950 else if (IS_GM45(dev))
14951 dev_priv->display.get_display_clock_speed =
14952 gm45_get_display_clock_speed;
14953 else if (IS_CRESTLINE(dev))
14954 dev_priv->display.get_display_clock_speed =
14955 i965gm_get_display_clock_speed;
14956 else if (IS_PINEVIEW(dev))
14957 dev_priv->display.get_display_clock_speed =
14958 pnv_get_display_clock_speed;
14959 else if (IS_G33(dev) || IS_G4X(dev))
14960 dev_priv->display.get_display_clock_speed =
14961 g33_get_display_clock_speed;
14962 else if (IS_I915G(dev))
14963 dev_priv->display.get_display_clock_speed =
14964 i915_get_display_clock_speed;
14965 else if (IS_I945GM(dev) || IS_845G(dev))
14966 dev_priv->display.get_display_clock_speed =
14967 i9xx_misc_get_display_clock_speed;
14968 else if (IS_I915GM(dev))
14969 dev_priv->display.get_display_clock_speed =
14970 i915gm_get_display_clock_speed;
14971 else if (IS_I865G(dev))
14972 dev_priv->display.get_display_clock_speed =
14973 i865_get_display_clock_speed;
14974 else if (IS_I85X(dev))
14975 dev_priv->display.get_display_clock_speed =
14976 i85x_get_display_clock_speed;
14977 else { /* 830 */
14978 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14979 dev_priv->display.get_display_clock_speed =
14980 i830_get_display_clock_speed;
14981 }
14982
14983 if (IS_GEN5(dev)) {
14984 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14985 } else if (IS_GEN6(dev)) {
14986 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14987 } else if (IS_IVYBRIDGE(dev)) {
14988 /* FIXME: detect B0+ stepping and use auto training */
14989 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14990 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14991 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14992 if (IS_BROADWELL(dev)) {
14993 dev_priv->display.modeset_commit_cdclk =
14994 broadwell_modeset_commit_cdclk;
14995 dev_priv->display.modeset_calc_cdclk =
14996 broadwell_modeset_calc_cdclk;
14997 }
14998 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14999 dev_priv->display.modeset_commit_cdclk =
15000 valleyview_modeset_commit_cdclk;
15001 dev_priv->display.modeset_calc_cdclk =
15002 valleyview_modeset_calc_cdclk;
15003 } else if (IS_BROXTON(dev)) {
15004 dev_priv->display.modeset_commit_cdclk =
15005 broxton_modeset_commit_cdclk;
15006 dev_priv->display.modeset_calc_cdclk =
15007 broxton_modeset_calc_cdclk;
15008 }
15009
15010 switch (INTEL_INFO(dev)->gen) {
15011 case 2:
15012 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15013 break;
15014
15015 case 3:
15016 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15017 break;
15018
15019 case 4:
15020 case 5:
15021 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15022 break;
15023
15024 case 6:
15025 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15026 break;
15027 case 7:
15028 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15029 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15030 break;
15031 case 9:
15032 /* Drop through - unsupported since execlist only. */
15033 default:
15034 /* Default just returns -ENODEV to indicate unsupported */
15035 dev_priv->display.queue_flip = intel_default_queue_flip;
15036 }
15037
15038 mutex_init(&dev_priv->pps_mutex);
15039 }
15040
15041 /*
15042 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15043 * resume, or other times. This quirk makes sure that's the case for
15044 * affected systems.
15045 */
15046 static void quirk_pipea_force(struct drm_device *dev)
15047 {
15048 struct drm_i915_private *dev_priv = dev->dev_private;
15049
15050 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15051 DRM_INFO("applying pipe a force quirk\n");
15052 }
15053
15054 static void quirk_pipeb_force(struct drm_device *dev)
15055 {
15056 struct drm_i915_private *dev_priv = dev->dev_private;
15057
15058 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15059 DRM_INFO("applying pipe b force quirk\n");
15060 }
15061
15062 /*
15063 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15064 */
15065 static void quirk_ssc_force_disable(struct drm_device *dev)
15066 {
15067 struct drm_i915_private *dev_priv = dev->dev_private;
15068 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15069 DRM_INFO("applying lvds SSC disable quirk\n");
15070 }
15071
15072 /*
15073 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15074 * brightness value
15075 */
15076 static void quirk_invert_brightness(struct drm_device *dev)
15077 {
15078 struct drm_i915_private *dev_priv = dev->dev_private;
15079 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15080 DRM_INFO("applying inverted panel brightness quirk\n");
15081 }
15082
15083 /* Some VBT's incorrectly indicate no backlight is present */
15084 static void quirk_backlight_present(struct drm_device *dev)
15085 {
15086 struct drm_i915_private *dev_priv = dev->dev_private;
15087 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15088 DRM_INFO("applying backlight present quirk\n");
15089 }
15090
15091 struct intel_quirk {
15092 int device;
15093 int subsystem_vendor;
15094 int subsystem_device;
15095 void (*hook)(struct drm_device *dev);
15096 };
15097
15098 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15099 struct intel_dmi_quirk {
15100 void (*hook)(struct drm_device *dev);
15101 const struct dmi_system_id (*dmi_id_list)[];
15102 };
15103
15104 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15105 {
15106 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15107 return 1;
15108 }
15109
15110 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15111 {
15112 .dmi_id_list = &(const struct dmi_system_id[]) {
15113 {
15114 .callback = intel_dmi_reverse_brightness,
15115 .ident = "NCR Corporation",
15116 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15117 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15118 },
15119 },
15120 { } /* terminating entry */
15121 },
15122 .hook = quirk_invert_brightness,
15123 },
15124 };
15125
15126 static struct intel_quirk intel_quirks[] = {
15127 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15128 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15129
15130 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15131 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15132
15133 /* 830 needs to leave pipe A & dpll A up */
15134 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15135
15136 /* 830 needs to leave pipe B & dpll B up */
15137 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15138
15139 /* Lenovo U160 cannot use SSC on LVDS */
15140 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15141
15142 /* Sony Vaio Y cannot use SSC on LVDS */
15143 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15144
15145 /* Acer Aspire 5734Z must invert backlight brightness */
15146 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15147
15148 /* Acer/eMachines G725 */
15149 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15150
15151 /* Acer/eMachines e725 */
15152 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15153
15154 /* Acer/Packard Bell NCL20 */
15155 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15156
15157 /* Acer Aspire 4736Z */
15158 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15159
15160 /* Acer Aspire 5336 */
15161 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15162
15163 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15164 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15165
15166 /* Acer C720 Chromebook (Core i3 4005U) */
15167 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15168
15169 /* Apple Macbook 2,1 (Core 2 T7400) */
15170 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15171
15172 /* Apple Macbook 4,1 */
15173 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15174
15175 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15176 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15177
15178 /* HP Chromebook 14 (Celeron 2955U) */
15179 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15180
15181 /* Dell Chromebook 11 */
15182 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15183
15184 /* Dell Chromebook 11 (2015 version) */
15185 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15186 };
15187
15188 static void intel_init_quirks(struct drm_device *dev)
15189 {
15190 struct pci_dev *d = dev->pdev;
15191 int i;
15192
15193 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15194 struct intel_quirk *q = &intel_quirks[i];
15195
15196 if (d->device == q->device &&
15197 (d->subsystem_vendor == q->subsystem_vendor ||
15198 q->subsystem_vendor == PCI_ANY_ID) &&
15199 (d->subsystem_device == q->subsystem_device ||
15200 q->subsystem_device == PCI_ANY_ID))
15201 q->hook(dev);
15202 }
15203 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15204 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15205 intel_dmi_quirks[i].hook(dev);
15206 }
15207 }
15208
15209 /* Disable the VGA plane that we never use */
15210 static void i915_disable_vga(struct drm_device *dev)
15211 {
15212 struct drm_i915_private *dev_priv = dev->dev_private;
15213 u8 sr1;
15214 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15215
15216 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15217 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15218 outb(SR01, VGA_SR_INDEX);
15219 sr1 = inb(VGA_SR_DATA);
15220 outb(sr1 | 1<<5, VGA_SR_DATA);
15221 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15222 udelay(300);
15223
15224 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15225 POSTING_READ(vga_reg);
15226 }
15227
15228 void intel_modeset_init_hw(struct drm_device *dev)
15229 {
15230 struct drm_i915_private *dev_priv = dev->dev_private;
15231
15232 intel_update_cdclk(dev);
15233
15234 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15235
15236 intel_init_clock_gating(dev);
15237 intel_enable_gt_powersave(dev);
15238 }
15239
15240 /*
15241 * Calculate what we think the watermarks should be for the state we've read
15242 * out of the hardware and then immediately program those watermarks so that
15243 * we ensure the hardware settings match our internal state.
15244 *
15245 * We can calculate what we think WM's should be by creating a duplicate of the
15246 * current state (which was constructed during hardware readout) and running it
15247 * through the atomic check code to calculate new watermark values in the
15248 * state object.
15249 */
15250 static void sanitize_watermarks(struct drm_device *dev)
15251 {
15252 struct drm_i915_private *dev_priv = to_i915(dev);
15253 struct drm_atomic_state *state;
15254 struct drm_crtc *crtc;
15255 struct drm_crtc_state *cstate;
15256 struct drm_modeset_acquire_ctx ctx;
15257 int ret;
15258 int i;
15259
15260 /* Only supported on platforms that use atomic watermark design */
15261 if (!dev_priv->display.program_watermarks)
15262 return;
15263
15264 /*
15265 * We need to hold connection_mutex before calling duplicate_state so
15266 * that the connector loop is protected.
15267 */
15268 drm_modeset_acquire_init(&ctx, 0);
15269 retry:
15270 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15271 if (ret == -EDEADLK) {
15272 drm_modeset_backoff(&ctx);
15273 goto retry;
15274 } else if (WARN_ON(ret)) {
15275 goto fail;
15276 }
15277
15278 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15279 if (WARN_ON(IS_ERR(state)))
15280 goto fail;
15281
15282 ret = intel_atomic_check(dev, state);
15283 if (ret) {
15284 /*
15285 * If we fail here, it means that the hardware appears to be
15286 * programmed in a way that shouldn't be possible, given our
15287 * understanding of watermark requirements. This might mean a
15288 * mistake in the hardware readout code or a mistake in the
15289 * watermark calculations for a given platform. Raise a WARN
15290 * so that this is noticeable.
15291 *
15292 * If this actually happens, we'll have to just leave the
15293 * BIOS-programmed watermarks untouched and hope for the best.
15294 */
15295 WARN(true, "Could not determine valid watermarks for inherited state\n");
15296 goto fail;
15297 }
15298
15299 /* Write calculated watermark values back */
15300 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15301 for_each_crtc_in_state(state, crtc, cstate, i) {
15302 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15303
15304 dev_priv->display.program_watermarks(cs);
15305 }
15306
15307 drm_atomic_state_free(state);
15308 fail:
15309 drm_modeset_drop_locks(&ctx);
15310 drm_modeset_acquire_fini(&ctx);
15311 }
15312
15313 void intel_modeset_init(struct drm_device *dev)
15314 {
15315 struct drm_i915_private *dev_priv = dev->dev_private;
15316 int sprite, ret;
15317 enum pipe pipe;
15318 struct intel_crtc *crtc;
15319
15320 drm_mode_config_init(dev);
15321
15322 dev->mode_config.min_width = 0;
15323 dev->mode_config.min_height = 0;
15324
15325 dev->mode_config.preferred_depth = 24;
15326 dev->mode_config.prefer_shadow = 1;
15327
15328 dev->mode_config.allow_fb_modifiers = true;
15329
15330 dev->mode_config.funcs = &intel_mode_funcs;
15331
15332 intel_init_quirks(dev);
15333
15334 intel_init_pm(dev);
15335
15336 if (INTEL_INFO(dev)->num_pipes == 0)
15337 return;
15338
15339 /*
15340 * There may be no VBT; and if the BIOS enabled SSC we can
15341 * just keep using it to avoid unnecessary flicker. Whereas if the
15342 * BIOS isn't using it, don't assume it will work even if the VBT
15343 * indicates as much.
15344 */
15345 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15346 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15347 DREF_SSC1_ENABLE);
15348
15349 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15350 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15351 bios_lvds_use_ssc ? "en" : "dis",
15352 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15353 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15354 }
15355 }
15356
15357 intel_init_display(dev);
15358 intel_init_audio(dev);
15359
15360 if (IS_GEN2(dev)) {
15361 dev->mode_config.max_width = 2048;
15362 dev->mode_config.max_height = 2048;
15363 } else if (IS_GEN3(dev)) {
15364 dev->mode_config.max_width = 4096;
15365 dev->mode_config.max_height = 4096;
15366 } else {
15367 dev->mode_config.max_width = 8192;
15368 dev->mode_config.max_height = 8192;
15369 }
15370
15371 if (IS_845G(dev) || IS_I865G(dev)) {
15372 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15373 dev->mode_config.cursor_height = 1023;
15374 } else if (IS_GEN2(dev)) {
15375 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15376 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15377 } else {
15378 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15379 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15380 }
15381
15382 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15383
15384 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15385 INTEL_INFO(dev)->num_pipes,
15386 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15387
15388 for_each_pipe(dev_priv, pipe) {
15389 intel_crtc_init(dev, pipe);
15390 for_each_sprite(dev_priv, pipe, sprite) {
15391 ret = intel_plane_init(dev, pipe, sprite);
15392 if (ret)
15393 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15394 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15395 }
15396 }
15397
15398 intel_update_czclk(dev_priv);
15399 intel_update_cdclk(dev);
15400
15401 intel_shared_dpll_init(dev);
15402
15403 /* Just disable it once at startup */
15404 i915_disable_vga(dev);
15405 intel_setup_outputs(dev);
15406
15407 drm_modeset_lock_all(dev);
15408 intel_modeset_setup_hw_state(dev);
15409 drm_modeset_unlock_all(dev);
15410
15411 for_each_intel_crtc(dev, crtc) {
15412 struct intel_initial_plane_config plane_config = {};
15413
15414 if (!crtc->active)
15415 continue;
15416
15417 /*
15418 * Note that reserving the BIOS fb up front prevents us
15419 * from stuffing other stolen allocations like the ring
15420 * on top. This prevents some ugliness at boot time, and
15421 * can even allow for smooth boot transitions if the BIOS
15422 * fb is large enough for the active pipe configuration.
15423 */
15424 dev_priv->display.get_initial_plane_config(crtc,
15425 &plane_config);
15426
15427 /*
15428 * If the fb is shared between multiple heads, we'll
15429 * just get the first one.
15430 */
15431 intel_find_initial_plane_obj(crtc, &plane_config);
15432 }
15433
15434 /*
15435 * Make sure hardware watermarks really match the state we read out.
15436 * Note that we need to do this after reconstructing the BIOS fb's
15437 * since the watermark calculation done here will use pstate->fb.
15438 */
15439 sanitize_watermarks(dev);
15440 }
15441
15442 static void intel_enable_pipe_a(struct drm_device *dev)
15443 {
15444 struct intel_connector *connector;
15445 struct drm_connector *crt = NULL;
15446 struct intel_load_detect_pipe load_detect_temp;
15447 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15448
15449 /* We can't just switch on the pipe A, we need to set things up with a
15450 * proper mode and output configuration. As a gross hack, enable pipe A
15451 * by enabling the load detect pipe once. */
15452 for_each_intel_connector(dev, connector) {
15453 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15454 crt = &connector->base;
15455 break;
15456 }
15457 }
15458
15459 if (!crt)
15460 return;
15461
15462 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15463 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15464 }
15465
15466 static bool
15467 intel_check_plane_mapping(struct intel_crtc *crtc)
15468 {
15469 struct drm_device *dev = crtc->base.dev;
15470 struct drm_i915_private *dev_priv = dev->dev_private;
15471 u32 val;
15472
15473 if (INTEL_INFO(dev)->num_pipes == 1)
15474 return true;
15475
15476 val = I915_READ(DSPCNTR(!crtc->plane));
15477
15478 if ((val & DISPLAY_PLANE_ENABLE) &&
15479 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15480 return false;
15481
15482 return true;
15483 }
15484
15485 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15486 {
15487 struct drm_device *dev = crtc->base.dev;
15488 struct intel_encoder *encoder;
15489
15490 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15491 return true;
15492
15493 return false;
15494 }
15495
15496 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15497 {
15498 struct drm_device *dev = crtc->base.dev;
15499 struct drm_i915_private *dev_priv = dev->dev_private;
15500 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15501
15502 /* Clear any frame start delays used for debugging left by the BIOS */
15503 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15504
15505 /* restore vblank interrupts to correct state */
15506 drm_crtc_vblank_reset(&crtc->base);
15507 if (crtc->active) {
15508 struct intel_plane *plane;
15509
15510 drm_crtc_vblank_on(&crtc->base);
15511
15512 /* Disable everything but the primary plane */
15513 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15514 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15515 continue;
15516
15517 plane->disable_plane(&plane->base, &crtc->base);
15518 }
15519 }
15520
15521 /* We need to sanitize the plane -> pipe mapping first because this will
15522 * disable the crtc (and hence change the state) if it is wrong. Note
15523 * that gen4+ has a fixed plane -> pipe mapping. */
15524 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15525 bool plane;
15526
15527 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15528 crtc->base.base.id);
15529
15530 /* Pipe has the wrong plane attached and the plane is active.
15531 * Temporarily change the plane mapping and disable everything
15532 * ... */
15533 plane = crtc->plane;
15534 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15535 crtc->plane = !plane;
15536 intel_crtc_disable_noatomic(&crtc->base);
15537 crtc->plane = plane;
15538 }
15539
15540 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15541 crtc->pipe == PIPE_A && !crtc->active) {
15542 /* BIOS forgot to enable pipe A, this mostly happens after
15543 * resume. Force-enable the pipe to fix this, the update_dpms
15544 * call below we restore the pipe to the right state, but leave
15545 * the required bits on. */
15546 intel_enable_pipe_a(dev);
15547 }
15548
15549 /* Adjust the state of the output pipe according to whether we
15550 * have active connectors/encoders. */
15551 if (!intel_crtc_has_encoders(crtc))
15552 intel_crtc_disable_noatomic(&crtc->base);
15553
15554 if (crtc->active != crtc->base.state->active) {
15555 struct intel_encoder *encoder;
15556
15557 /* This can happen either due to bugs in the get_hw_state
15558 * functions or because of calls to intel_crtc_disable_noatomic,
15559 * or because the pipe is force-enabled due to the
15560 * pipe A quirk. */
15561 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15562 crtc->base.base.id,
15563 crtc->base.state->enable ? "enabled" : "disabled",
15564 crtc->active ? "enabled" : "disabled");
15565
15566 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15567 crtc->base.state->active = crtc->active;
15568 crtc->base.enabled = crtc->active;
15569 crtc->base.state->connector_mask = 0;
15570 crtc->base.state->encoder_mask = 0;
15571
15572 /* Because we only establish the connector -> encoder ->
15573 * crtc links if something is active, this means the
15574 * crtc is now deactivated. Break the links. connector
15575 * -> encoder links are only establish when things are
15576 * actually up, hence no need to break them. */
15577 WARN_ON(crtc->active);
15578
15579 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15580 encoder->base.crtc = NULL;
15581 }
15582
15583 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15584 /*
15585 * We start out with underrun reporting disabled to avoid races.
15586 * For correct bookkeeping mark this on active crtcs.
15587 *
15588 * Also on gmch platforms we dont have any hardware bits to
15589 * disable the underrun reporting. Which means we need to start
15590 * out with underrun reporting disabled also on inactive pipes,
15591 * since otherwise we'll complain about the garbage we read when
15592 * e.g. coming up after runtime pm.
15593 *
15594 * No protection against concurrent access is required - at
15595 * worst a fifo underrun happens which also sets this to false.
15596 */
15597 crtc->cpu_fifo_underrun_disabled = true;
15598 crtc->pch_fifo_underrun_disabled = true;
15599 }
15600 }
15601
15602 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15603 {
15604 struct intel_connector *connector;
15605 struct drm_device *dev = encoder->base.dev;
15606 bool active = false;
15607
15608 /* We need to check both for a crtc link (meaning that the
15609 * encoder is active and trying to read from a pipe) and the
15610 * pipe itself being active. */
15611 bool has_active_crtc = encoder->base.crtc &&
15612 to_intel_crtc(encoder->base.crtc)->active;
15613
15614 for_each_intel_connector(dev, connector) {
15615 if (connector->base.encoder != &encoder->base)
15616 continue;
15617
15618 active = true;
15619 break;
15620 }
15621
15622 if (active && !has_active_crtc) {
15623 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15624 encoder->base.base.id,
15625 encoder->base.name);
15626
15627 /* Connector is active, but has no active pipe. This is
15628 * fallout from our resume register restoring. Disable
15629 * the encoder manually again. */
15630 if (encoder->base.crtc) {
15631 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15632 encoder->base.base.id,
15633 encoder->base.name);
15634 encoder->disable(encoder);
15635 if (encoder->post_disable)
15636 encoder->post_disable(encoder);
15637 }
15638 encoder->base.crtc = NULL;
15639
15640 /* Inconsistent output/port/pipe state happens presumably due to
15641 * a bug in one of the get_hw_state functions. Or someplace else
15642 * in our code, like the register restore mess on resume. Clamp
15643 * things to off as a safer default. */
15644 for_each_intel_connector(dev, connector) {
15645 if (connector->encoder != encoder)
15646 continue;
15647 connector->base.dpms = DRM_MODE_DPMS_OFF;
15648 connector->base.encoder = NULL;
15649 }
15650 }
15651 /* Enabled encoders without active connectors will be fixed in
15652 * the crtc fixup. */
15653 }
15654
15655 void i915_redisable_vga_power_on(struct drm_device *dev)
15656 {
15657 struct drm_i915_private *dev_priv = dev->dev_private;
15658 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15659
15660 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15661 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15662 i915_disable_vga(dev);
15663 }
15664 }
15665
15666 void i915_redisable_vga(struct drm_device *dev)
15667 {
15668 struct drm_i915_private *dev_priv = dev->dev_private;
15669
15670 /* This function can be called both from intel_modeset_setup_hw_state or
15671 * at a very early point in our resume sequence, where the power well
15672 * structures are not yet restored. Since this function is at a very
15673 * paranoid "someone might have enabled VGA while we were not looking"
15674 * level, just check if the power well is enabled instead of trying to
15675 * follow the "don't touch the power well if we don't need it" policy
15676 * the rest of the driver uses. */
15677 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15678 return;
15679
15680 i915_redisable_vga_power_on(dev);
15681 }
15682
15683 static bool primary_get_hw_state(struct intel_plane *plane)
15684 {
15685 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15686
15687 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15688 }
15689
15690 /* FIXME read out full plane state for all planes */
15691 static void readout_plane_state(struct intel_crtc *crtc)
15692 {
15693 struct drm_plane *primary = crtc->base.primary;
15694 struct intel_plane_state *plane_state =
15695 to_intel_plane_state(primary->state);
15696
15697 plane_state->visible = crtc->active &&
15698 primary_get_hw_state(to_intel_plane(primary));
15699
15700 if (plane_state->visible)
15701 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15702 }
15703
15704 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15705 {
15706 struct drm_i915_private *dev_priv = dev->dev_private;
15707 enum pipe pipe;
15708 struct intel_crtc *crtc;
15709 struct intel_encoder *encoder;
15710 struct intel_connector *connector;
15711 int i;
15712
15713 dev_priv->active_crtcs = 0;
15714
15715 for_each_intel_crtc(dev, crtc) {
15716 struct intel_crtc_state *crtc_state = crtc->config;
15717 int pixclk = 0;
15718
15719 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15720 memset(crtc_state, 0, sizeof(*crtc_state));
15721 crtc_state->base.crtc = &crtc->base;
15722
15723 crtc_state->base.active = crtc_state->base.enable =
15724 dev_priv->display.get_pipe_config(crtc, crtc_state);
15725
15726 crtc->base.enabled = crtc_state->base.enable;
15727 crtc->active = crtc_state->base.active;
15728
15729 if (crtc_state->base.active) {
15730 dev_priv->active_crtcs |= 1 << crtc->pipe;
15731
15732 if (IS_BROADWELL(dev_priv)) {
15733 pixclk = ilk_pipe_pixel_rate(crtc_state);
15734
15735 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15736 if (crtc_state->ips_enabled)
15737 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15738 } else if (IS_VALLEYVIEW(dev_priv) ||
15739 IS_CHERRYVIEW(dev_priv) ||
15740 IS_BROXTON(dev_priv))
15741 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15742 else
15743 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15744 }
15745
15746 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15747
15748 readout_plane_state(crtc);
15749
15750 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15751 crtc->base.base.id,
15752 crtc->active ? "enabled" : "disabled");
15753 }
15754
15755 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15756 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15757
15758 pll->on = pll->get_hw_state(dev_priv, pll,
15759 &pll->config.hw_state);
15760 pll->active = 0;
15761 pll->config.crtc_mask = 0;
15762 for_each_intel_crtc(dev, crtc) {
15763 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15764 pll->active++;
15765 pll->config.crtc_mask |= 1 << crtc->pipe;
15766 }
15767 }
15768
15769 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15770 pll->name, pll->config.crtc_mask, pll->on);
15771
15772 if (pll->config.crtc_mask)
15773 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15774 }
15775
15776 for_each_intel_encoder(dev, encoder) {
15777 pipe = 0;
15778
15779 if (encoder->get_hw_state(encoder, &pipe)) {
15780 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15781 encoder->base.crtc = &crtc->base;
15782 encoder->get_config(encoder, crtc->config);
15783 } else {
15784 encoder->base.crtc = NULL;
15785 }
15786
15787 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15788 encoder->base.base.id,
15789 encoder->base.name,
15790 encoder->base.crtc ? "enabled" : "disabled",
15791 pipe_name(pipe));
15792 }
15793
15794 for_each_intel_connector(dev, connector) {
15795 if (connector->get_hw_state(connector)) {
15796 connector->base.dpms = DRM_MODE_DPMS_ON;
15797
15798 encoder = connector->encoder;
15799 connector->base.encoder = &encoder->base;
15800
15801 if (encoder->base.crtc &&
15802 encoder->base.crtc->state->active) {
15803 /*
15804 * This has to be done during hardware readout
15805 * because anything calling .crtc_disable may
15806 * rely on the connector_mask being accurate.
15807 */
15808 encoder->base.crtc->state->connector_mask |=
15809 1 << drm_connector_index(&connector->base);
15810 encoder->base.crtc->state->encoder_mask |=
15811 1 << drm_encoder_index(&encoder->base);
15812 }
15813
15814 } else {
15815 connector->base.dpms = DRM_MODE_DPMS_OFF;
15816 connector->base.encoder = NULL;
15817 }
15818 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15819 connector->base.base.id,
15820 connector->base.name,
15821 connector->base.encoder ? "enabled" : "disabled");
15822 }
15823
15824 for_each_intel_crtc(dev, crtc) {
15825 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15826
15827 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15828 if (crtc->base.state->active) {
15829 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15830 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15831 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15832
15833 /*
15834 * The initial mode needs to be set in order to keep
15835 * the atomic core happy. It wants a valid mode if the
15836 * crtc's enabled, so we do the above call.
15837 *
15838 * At this point some state updated by the connectors
15839 * in their ->detect() callback has not run yet, so
15840 * no recalculation can be done yet.
15841 *
15842 * Even if we could do a recalculation and modeset
15843 * right now it would cause a double modeset if
15844 * fbdev or userspace chooses a different initial mode.
15845 *
15846 * If that happens, someone indicated they wanted a
15847 * mode change, which means it's safe to do a full
15848 * recalculation.
15849 */
15850 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15851
15852 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15853 update_scanline_offset(crtc);
15854 }
15855 }
15856 }
15857
15858 /* Scan out the current hw modeset state,
15859 * and sanitizes it to the current state
15860 */
15861 static void
15862 intel_modeset_setup_hw_state(struct drm_device *dev)
15863 {
15864 struct drm_i915_private *dev_priv = dev->dev_private;
15865 enum pipe pipe;
15866 struct intel_crtc *crtc;
15867 struct intel_encoder *encoder;
15868 int i;
15869
15870 intel_modeset_readout_hw_state(dev);
15871
15872 /* HW state is read out, now we need to sanitize this mess. */
15873 for_each_intel_encoder(dev, encoder) {
15874 intel_sanitize_encoder(encoder);
15875 }
15876
15877 for_each_pipe(dev_priv, pipe) {
15878 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15879 intel_sanitize_crtc(crtc);
15880 intel_dump_pipe_config(crtc, crtc->config,
15881 "[setup_hw_state]");
15882 }
15883
15884 intel_modeset_update_connector_atomic_state(dev);
15885
15886 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15887 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15888
15889 if (!pll->on || pll->active)
15890 continue;
15891
15892 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15893
15894 pll->disable(dev_priv, pll);
15895 pll->on = false;
15896 }
15897
15898 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15899 vlv_wm_get_hw_state(dev);
15900 else if (IS_GEN9(dev))
15901 skl_wm_get_hw_state(dev);
15902 else if (HAS_PCH_SPLIT(dev))
15903 ilk_wm_get_hw_state(dev);
15904
15905 for_each_intel_crtc(dev, crtc) {
15906 unsigned long put_domains;
15907
15908 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15909 if (WARN_ON(put_domains))
15910 modeset_put_power_domains(dev_priv, put_domains);
15911 }
15912 intel_display_set_init_power(dev_priv, false);
15913
15914 intel_fbc_init_pipe_state(dev_priv);
15915 }
15916
15917 void intel_display_resume(struct drm_device *dev)
15918 {
15919 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15920 struct intel_connector *conn;
15921 struct intel_plane *plane;
15922 struct drm_crtc *crtc;
15923 int ret;
15924
15925 if (!state)
15926 return;
15927
15928 state->acquire_ctx = dev->mode_config.acquire_ctx;
15929
15930 /* preserve complete old state, including dpll */
15931 intel_atomic_get_shared_dpll_state(state);
15932
15933 for_each_crtc(dev, crtc) {
15934 struct drm_crtc_state *crtc_state =
15935 drm_atomic_get_crtc_state(state, crtc);
15936
15937 ret = PTR_ERR_OR_ZERO(crtc_state);
15938 if (ret)
15939 goto err;
15940
15941 /* force a restore */
15942 crtc_state->mode_changed = true;
15943 }
15944
15945 for_each_intel_plane(dev, plane) {
15946 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15947 if (ret)
15948 goto err;
15949 }
15950
15951 for_each_intel_connector(dev, conn) {
15952 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15953 if (ret)
15954 goto err;
15955 }
15956
15957 intel_modeset_setup_hw_state(dev);
15958
15959 i915_redisable_vga(dev);
15960 ret = drm_atomic_commit(state);
15961 if (!ret)
15962 return;
15963
15964 err:
15965 DRM_ERROR("Restoring old state failed with %i\n", ret);
15966 drm_atomic_state_free(state);
15967 }
15968
15969 void intel_modeset_gem_init(struct drm_device *dev)
15970 {
15971 struct drm_crtc *c;
15972 struct drm_i915_gem_object *obj;
15973 int ret;
15974
15975 mutex_lock(&dev->struct_mutex);
15976 intel_init_gt_powersave(dev);
15977 mutex_unlock(&dev->struct_mutex);
15978
15979 intel_modeset_init_hw(dev);
15980
15981 intel_setup_overlay(dev);
15982
15983 /*
15984 * Make sure any fbs we allocated at startup are properly
15985 * pinned & fenced. When we do the allocation it's too early
15986 * for this.
15987 */
15988 for_each_crtc(dev, c) {
15989 obj = intel_fb_obj(c->primary->fb);
15990 if (obj == NULL)
15991 continue;
15992
15993 mutex_lock(&dev->struct_mutex);
15994 ret = intel_pin_and_fence_fb_obj(c->primary,
15995 c->primary->fb,
15996 c->primary->state);
15997 mutex_unlock(&dev->struct_mutex);
15998 if (ret) {
15999 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16000 to_intel_crtc(c)->pipe);
16001 drm_framebuffer_unreference(c->primary->fb);
16002 c->primary->fb = NULL;
16003 c->primary->crtc = c->primary->state->crtc = NULL;
16004 update_state_fb(c->primary);
16005 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16006 }
16007 }
16008
16009 intel_backlight_register(dev);
16010 }
16011
16012 void intel_connector_unregister(struct intel_connector *intel_connector)
16013 {
16014 struct drm_connector *connector = &intel_connector->base;
16015
16016 intel_panel_destroy_backlight(connector);
16017 drm_connector_unregister(connector);
16018 }
16019
16020 void intel_modeset_cleanup(struct drm_device *dev)
16021 {
16022 struct drm_i915_private *dev_priv = dev->dev_private;
16023 struct intel_connector *connector;
16024
16025 intel_disable_gt_powersave(dev);
16026
16027 intel_backlight_unregister(dev);
16028
16029 /*
16030 * Interrupts and polling as the first thing to avoid creating havoc.
16031 * Too much stuff here (turning of connectors, ...) would
16032 * experience fancy races otherwise.
16033 */
16034 intel_irq_uninstall(dev_priv);
16035
16036 /*
16037 * Due to the hpd irq storm handling the hotplug work can re-arm the
16038 * poll handlers. Hence disable polling after hpd handling is shut down.
16039 */
16040 drm_kms_helper_poll_fini(dev);
16041
16042 intel_unregister_dsm_handler();
16043
16044 intel_fbc_global_disable(dev_priv);
16045
16046 /* flush any delayed tasks or pending work */
16047 flush_scheduled_work();
16048
16049 /* destroy the backlight and sysfs files before encoders/connectors */
16050 for_each_intel_connector(dev, connector)
16051 connector->unregister(connector);
16052
16053 drm_mode_config_cleanup(dev);
16054
16055 intel_cleanup_overlay(dev);
16056
16057 mutex_lock(&dev->struct_mutex);
16058 intel_cleanup_gt_powersave(dev);
16059 mutex_unlock(&dev->struct_mutex);
16060
16061 intel_teardown_gmbus(dev);
16062 }
16063
16064 /*
16065 * Return which encoder is currently attached for connector.
16066 */
16067 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16068 {
16069 return &intel_attached_encoder(connector)->base;
16070 }
16071
16072 void intel_connector_attach_encoder(struct intel_connector *connector,
16073 struct intel_encoder *encoder)
16074 {
16075 connector->encoder = encoder;
16076 drm_mode_connector_attach_encoder(&connector->base,
16077 &encoder->base);
16078 }
16079
16080 /*
16081 * set vga decode state - true == enable VGA decode
16082 */
16083 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16084 {
16085 struct drm_i915_private *dev_priv = dev->dev_private;
16086 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16087 u16 gmch_ctrl;
16088
16089 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16090 DRM_ERROR("failed to read control word\n");
16091 return -EIO;
16092 }
16093
16094 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16095 return 0;
16096
16097 if (state)
16098 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16099 else
16100 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16101
16102 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16103 DRM_ERROR("failed to write control word\n");
16104 return -EIO;
16105 }
16106
16107 return 0;
16108 }
16109
16110 struct intel_display_error_state {
16111
16112 u32 power_well_driver;
16113
16114 int num_transcoders;
16115
16116 struct intel_cursor_error_state {
16117 u32 control;
16118 u32 position;
16119 u32 base;
16120 u32 size;
16121 } cursor[I915_MAX_PIPES];
16122
16123 struct intel_pipe_error_state {
16124 bool power_domain_on;
16125 u32 source;
16126 u32 stat;
16127 } pipe[I915_MAX_PIPES];
16128
16129 struct intel_plane_error_state {
16130 u32 control;
16131 u32 stride;
16132 u32 size;
16133 u32 pos;
16134 u32 addr;
16135 u32 surface;
16136 u32 tile_offset;
16137 } plane[I915_MAX_PIPES];
16138
16139 struct intel_transcoder_error_state {
16140 bool power_domain_on;
16141 enum transcoder cpu_transcoder;
16142
16143 u32 conf;
16144
16145 u32 htotal;
16146 u32 hblank;
16147 u32 hsync;
16148 u32 vtotal;
16149 u32 vblank;
16150 u32 vsync;
16151 } transcoder[4];
16152 };
16153
16154 struct intel_display_error_state *
16155 intel_display_capture_error_state(struct drm_device *dev)
16156 {
16157 struct drm_i915_private *dev_priv = dev->dev_private;
16158 struct intel_display_error_state *error;
16159 int transcoders[] = {
16160 TRANSCODER_A,
16161 TRANSCODER_B,
16162 TRANSCODER_C,
16163 TRANSCODER_EDP,
16164 };
16165 int i;
16166
16167 if (INTEL_INFO(dev)->num_pipes == 0)
16168 return NULL;
16169
16170 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16171 if (error == NULL)
16172 return NULL;
16173
16174 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16175 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16176
16177 for_each_pipe(dev_priv, i) {
16178 error->pipe[i].power_domain_on =
16179 __intel_display_power_is_enabled(dev_priv,
16180 POWER_DOMAIN_PIPE(i));
16181 if (!error->pipe[i].power_domain_on)
16182 continue;
16183
16184 error->cursor[i].control = I915_READ(CURCNTR(i));
16185 error->cursor[i].position = I915_READ(CURPOS(i));
16186 error->cursor[i].base = I915_READ(CURBASE(i));
16187
16188 error->plane[i].control = I915_READ(DSPCNTR(i));
16189 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16190 if (INTEL_INFO(dev)->gen <= 3) {
16191 error->plane[i].size = I915_READ(DSPSIZE(i));
16192 error->plane[i].pos = I915_READ(DSPPOS(i));
16193 }
16194 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16195 error->plane[i].addr = I915_READ(DSPADDR(i));
16196 if (INTEL_INFO(dev)->gen >= 4) {
16197 error->plane[i].surface = I915_READ(DSPSURF(i));
16198 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16199 }
16200
16201 error->pipe[i].source = I915_READ(PIPESRC(i));
16202
16203 if (HAS_GMCH_DISPLAY(dev))
16204 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16205 }
16206
16207 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16208 if (HAS_DDI(dev_priv->dev))
16209 error->num_transcoders++; /* Account for eDP. */
16210
16211 for (i = 0; i < error->num_transcoders; i++) {
16212 enum transcoder cpu_transcoder = transcoders[i];
16213
16214 error->transcoder[i].power_domain_on =
16215 __intel_display_power_is_enabled(dev_priv,
16216 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16217 if (!error->transcoder[i].power_domain_on)
16218 continue;
16219
16220 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16221
16222 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16223 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16224 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16225 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16226 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16227 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16228 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16229 }
16230
16231 return error;
16232 }
16233
16234 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16235
16236 void
16237 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16238 struct drm_device *dev,
16239 struct intel_display_error_state *error)
16240 {
16241 struct drm_i915_private *dev_priv = dev->dev_private;
16242 int i;
16243
16244 if (!error)
16245 return;
16246
16247 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16248 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16249 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16250 error->power_well_driver);
16251 for_each_pipe(dev_priv, i) {
16252 err_printf(m, "Pipe [%d]:\n", i);
16253 err_printf(m, " Power: %s\n",
16254 onoff(error->pipe[i].power_domain_on));
16255 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16256 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16257
16258 err_printf(m, "Plane [%d]:\n", i);
16259 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16260 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16261 if (INTEL_INFO(dev)->gen <= 3) {
16262 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16263 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16264 }
16265 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16266 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16267 if (INTEL_INFO(dev)->gen >= 4) {
16268 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16269 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16270 }
16271
16272 err_printf(m, "Cursor [%d]:\n", i);
16273 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16274 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16275 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16276 }
16277
16278 for (i = 0; i < error->num_transcoders; i++) {
16279 err_printf(m, "CPU transcoder: %c\n",
16280 transcoder_name(error->transcoder[i].cpu_transcoder));
16281 err_printf(m, " Power: %s\n",
16282 onoff(error->transcoder[i].power_domain_on));
16283 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16284 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16285 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16286 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16287 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16288 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16289 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16290 }
16291 }
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