2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_gem_dmabuf.h"
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
51 static bool is_mmio_work(struct intel_flip_work
*work
)
53 return work
->mmio_work
.func
;
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats
[] = {
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats
[] = {
70 DRM_FORMAT_XRGB2101010
,
71 DRM_FORMAT_XBGR2101010
,
74 static const uint32_t skl_primary_formats
[] = {
81 DRM_FORMAT_XRGB2101010
,
82 DRM_FORMAT_XBGR2101010
,
90 static const uint32_t intel_cursor_formats
[] = {
94 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
95 struct intel_crtc_state
*pipe_config
);
96 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
97 struct intel_crtc_state
*pipe_config
);
99 static int intel_framebuffer_init(struct drm_device
*dev
,
100 struct intel_framebuffer
*ifb
,
101 struct drm_mode_fb_cmd2
*mode_cmd
,
102 struct drm_i915_gem_object
*obj
);
103 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
104 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
105 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
107 struct intel_link_m_n
*m_n
,
108 struct intel_link_m_n
*m2_n2
);
109 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
110 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
111 static void haswell_set_pipemisc(struct drm_crtc
*crtc
);
112 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
113 const struct intel_crtc_state
*pipe_config
);
114 static void chv_prepare_pll(struct intel_crtc
*crtc
,
115 const struct intel_crtc_state
*pipe_config
);
116 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
117 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
118 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
119 struct intel_crtc_state
*crtc_state
);
120 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
121 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
122 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
123 static void intel_modeset_setup_hw_state(struct drm_device
*dev
);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
125 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
);
126 static int bxt_calc_cdclk(int max_pixclk
);
131 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
135 int p2_slow
, p2_fast
;
139 /* returns HPLL frequency in kHz */
140 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
142 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
144 /* Obtain SKU information */
145 mutex_lock(&dev_priv
->sb_lock
);
146 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
147 CCK_FUSE_HPLL_FREQ_MASK
;
148 mutex_unlock(&dev_priv
->sb_lock
);
150 return vco_freq
[hpll_freq
] * 1000;
153 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
154 const char *name
, u32 reg
, int ref_freq
)
159 mutex_lock(&dev_priv
->sb_lock
);
160 val
= vlv_cck_read(dev_priv
, reg
);
161 mutex_unlock(&dev_priv
->sb_lock
);
163 divider
= val
& CCK_FREQUENCY_VALUES
;
165 WARN((val
& CCK_FREQUENCY_STATUS
) !=
166 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
167 "%s change in progress\n", name
);
169 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
172 static int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
173 const char *name
, u32 reg
)
175 if (dev_priv
->hpll_freq
== 0)
176 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
178 return vlv_get_cck_clock(dev_priv
, name
, reg
,
179 dev_priv
->hpll_freq
);
183 intel_pch_rawclk(struct drm_i915_private
*dev_priv
)
185 return (I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
) * 1000;
189 intel_vlv_hrawclk(struct drm_i915_private
*dev_priv
)
191 /* RAWCLK_FREQ_VLV register updated from power well code */
192 return vlv_get_cck_clock_hpll(dev_priv
, "hrawclk",
193 CCK_DISPLAY_REF_CLOCK_CONTROL
);
197 intel_g4x_hrawclk(struct drm_i915_private
*dev_priv
)
201 /* hrawclock is 1/4 the FSB frequency */
202 clkcfg
= I915_READ(CLKCFG
);
203 switch (clkcfg
& CLKCFG_FSB_MASK
) {
212 case CLKCFG_FSB_1067
:
214 case CLKCFG_FSB_1333
:
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600
:
218 case CLKCFG_FSB_1600_ALT
:
225 void intel_update_rawclk(struct drm_i915_private
*dev_priv
)
227 if (HAS_PCH_SPLIT(dev_priv
))
228 dev_priv
->rawclk_freq
= intel_pch_rawclk(dev_priv
);
229 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
230 dev_priv
->rawclk_freq
= intel_vlv_hrawclk(dev_priv
);
231 else if (IS_G4X(dev_priv
) || IS_PINEVIEW(dev_priv
))
232 dev_priv
->rawclk_freq
= intel_g4x_hrawclk(dev_priv
);
234 return; /* no rawclk on other platforms, or no need to know it */
236 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv
->rawclk_freq
);
239 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
241 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
244 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
245 CCK_CZ_CLOCK_CONTROL
);
247 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
250 static inline u32
/* units of 100MHz */
251 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
252 const struct intel_crtc_state
*pipe_config
)
254 if (HAS_DDI(dev_priv
))
255 return pipe_config
->port_clock
; /* SPLL */
256 else if (IS_GEN5(dev_priv
))
257 return ((I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2) * 10000;
262 static const struct intel_limit intel_limits_i8xx_dac
= {
263 .dot
= { .min
= 25000, .max
= 350000 },
264 .vco
= { .min
= 908000, .max
= 1512000 },
265 .n
= { .min
= 2, .max
= 16 },
266 .m
= { .min
= 96, .max
= 140 },
267 .m1
= { .min
= 18, .max
= 26 },
268 .m2
= { .min
= 6, .max
= 16 },
269 .p
= { .min
= 4, .max
= 128 },
270 .p1
= { .min
= 2, .max
= 33 },
271 .p2
= { .dot_limit
= 165000,
272 .p2_slow
= 4, .p2_fast
= 2 },
275 static const struct intel_limit intel_limits_i8xx_dvo
= {
276 .dot
= { .min
= 25000, .max
= 350000 },
277 .vco
= { .min
= 908000, .max
= 1512000 },
278 .n
= { .min
= 2, .max
= 16 },
279 .m
= { .min
= 96, .max
= 140 },
280 .m1
= { .min
= 18, .max
= 26 },
281 .m2
= { .min
= 6, .max
= 16 },
282 .p
= { .min
= 4, .max
= 128 },
283 .p1
= { .min
= 2, .max
= 33 },
284 .p2
= { .dot_limit
= 165000,
285 .p2_slow
= 4, .p2_fast
= 4 },
288 static const struct intel_limit intel_limits_i8xx_lvds
= {
289 .dot
= { .min
= 25000, .max
= 350000 },
290 .vco
= { .min
= 908000, .max
= 1512000 },
291 .n
= { .min
= 2, .max
= 16 },
292 .m
= { .min
= 96, .max
= 140 },
293 .m1
= { .min
= 18, .max
= 26 },
294 .m2
= { .min
= 6, .max
= 16 },
295 .p
= { .min
= 4, .max
= 128 },
296 .p1
= { .min
= 1, .max
= 6 },
297 .p2
= { .dot_limit
= 165000,
298 .p2_slow
= 14, .p2_fast
= 7 },
301 static const struct intel_limit intel_limits_i9xx_sdvo
= {
302 .dot
= { .min
= 20000, .max
= 400000 },
303 .vco
= { .min
= 1400000, .max
= 2800000 },
304 .n
= { .min
= 1, .max
= 6 },
305 .m
= { .min
= 70, .max
= 120 },
306 .m1
= { .min
= 8, .max
= 18 },
307 .m2
= { .min
= 3, .max
= 7 },
308 .p
= { .min
= 5, .max
= 80 },
309 .p1
= { .min
= 1, .max
= 8 },
310 .p2
= { .dot_limit
= 200000,
311 .p2_slow
= 10, .p2_fast
= 5 },
314 static const struct intel_limit intel_limits_i9xx_lvds
= {
315 .dot
= { .min
= 20000, .max
= 400000 },
316 .vco
= { .min
= 1400000, .max
= 2800000 },
317 .n
= { .min
= 1, .max
= 6 },
318 .m
= { .min
= 70, .max
= 120 },
319 .m1
= { .min
= 8, .max
= 18 },
320 .m2
= { .min
= 3, .max
= 7 },
321 .p
= { .min
= 7, .max
= 98 },
322 .p1
= { .min
= 1, .max
= 8 },
323 .p2
= { .dot_limit
= 112000,
324 .p2_slow
= 14, .p2_fast
= 7 },
328 static const struct intel_limit intel_limits_g4x_sdvo
= {
329 .dot
= { .min
= 25000, .max
= 270000 },
330 .vco
= { .min
= 1750000, .max
= 3500000},
331 .n
= { .min
= 1, .max
= 4 },
332 .m
= { .min
= 104, .max
= 138 },
333 .m1
= { .min
= 17, .max
= 23 },
334 .m2
= { .min
= 5, .max
= 11 },
335 .p
= { .min
= 10, .max
= 30 },
336 .p1
= { .min
= 1, .max
= 3},
337 .p2
= { .dot_limit
= 270000,
343 static const struct intel_limit intel_limits_g4x_hdmi
= {
344 .dot
= { .min
= 22000, .max
= 400000 },
345 .vco
= { .min
= 1750000, .max
= 3500000},
346 .n
= { .min
= 1, .max
= 4 },
347 .m
= { .min
= 104, .max
= 138 },
348 .m1
= { .min
= 16, .max
= 23 },
349 .m2
= { .min
= 5, .max
= 11 },
350 .p
= { .min
= 5, .max
= 80 },
351 .p1
= { .min
= 1, .max
= 8},
352 .p2
= { .dot_limit
= 165000,
353 .p2_slow
= 10, .p2_fast
= 5 },
356 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
357 .dot
= { .min
= 20000, .max
= 115000 },
358 .vco
= { .min
= 1750000, .max
= 3500000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 104, .max
= 138 },
361 .m1
= { .min
= 17, .max
= 23 },
362 .m2
= { .min
= 5, .max
= 11 },
363 .p
= { .min
= 28, .max
= 112 },
364 .p1
= { .min
= 2, .max
= 8 },
365 .p2
= { .dot_limit
= 0,
366 .p2_slow
= 14, .p2_fast
= 14
370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
371 .dot
= { .min
= 80000, .max
= 224000 },
372 .vco
= { .min
= 1750000, .max
= 3500000 },
373 .n
= { .min
= 1, .max
= 3 },
374 .m
= { .min
= 104, .max
= 138 },
375 .m1
= { .min
= 17, .max
= 23 },
376 .m2
= { .min
= 5, .max
= 11 },
377 .p
= { .min
= 14, .max
= 42 },
378 .p1
= { .min
= 2, .max
= 6 },
379 .p2
= { .dot_limit
= 0,
380 .p2_slow
= 7, .p2_fast
= 7
384 static const struct intel_limit intel_limits_pineview_sdvo
= {
385 .dot
= { .min
= 20000, .max
= 400000},
386 .vco
= { .min
= 1700000, .max
= 3500000 },
387 /* Pineview's Ncounter is a ring counter */
388 .n
= { .min
= 3, .max
= 6 },
389 .m
= { .min
= 2, .max
= 256 },
390 /* Pineview only has one combined m divider, which we treat as m2. */
391 .m1
= { .min
= 0, .max
= 0 },
392 .m2
= { .min
= 0, .max
= 254 },
393 .p
= { .min
= 5, .max
= 80 },
394 .p1
= { .min
= 1, .max
= 8 },
395 .p2
= { .dot_limit
= 200000,
396 .p2_slow
= 10, .p2_fast
= 5 },
399 static const struct intel_limit intel_limits_pineview_lvds
= {
400 .dot
= { .min
= 20000, .max
= 400000 },
401 .vco
= { .min
= 1700000, .max
= 3500000 },
402 .n
= { .min
= 3, .max
= 6 },
403 .m
= { .min
= 2, .max
= 256 },
404 .m1
= { .min
= 0, .max
= 0 },
405 .m2
= { .min
= 0, .max
= 254 },
406 .p
= { .min
= 7, .max
= 112 },
407 .p1
= { .min
= 1, .max
= 8 },
408 .p2
= { .dot_limit
= 112000,
409 .p2_slow
= 14, .p2_fast
= 14 },
412 /* Ironlake / Sandybridge
414 * We calculate clock using (register_value + 2) for N/M1/M2, so here
415 * the range value for them is (actual_value - 2).
417 static const struct intel_limit intel_limits_ironlake_dac
= {
418 .dot
= { .min
= 25000, .max
= 350000 },
419 .vco
= { .min
= 1760000, .max
= 3510000 },
420 .n
= { .min
= 1, .max
= 5 },
421 .m
= { .min
= 79, .max
= 127 },
422 .m1
= { .min
= 12, .max
= 22 },
423 .m2
= { .min
= 5, .max
= 9 },
424 .p
= { .min
= 5, .max
= 80 },
425 .p1
= { .min
= 1, .max
= 8 },
426 .p2
= { .dot_limit
= 225000,
427 .p2_slow
= 10, .p2_fast
= 5 },
430 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
431 .dot
= { .min
= 25000, .max
= 350000 },
432 .vco
= { .min
= 1760000, .max
= 3510000 },
433 .n
= { .min
= 1, .max
= 3 },
434 .m
= { .min
= 79, .max
= 118 },
435 .m1
= { .min
= 12, .max
= 22 },
436 .m2
= { .min
= 5, .max
= 9 },
437 .p
= { .min
= 28, .max
= 112 },
438 .p1
= { .min
= 2, .max
= 8 },
439 .p2
= { .dot_limit
= 225000,
440 .p2_slow
= 14, .p2_fast
= 14 },
443 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
444 .dot
= { .min
= 25000, .max
= 350000 },
445 .vco
= { .min
= 1760000, .max
= 3510000 },
446 .n
= { .min
= 1, .max
= 3 },
447 .m
= { .min
= 79, .max
= 127 },
448 .m1
= { .min
= 12, .max
= 22 },
449 .m2
= { .min
= 5, .max
= 9 },
450 .p
= { .min
= 14, .max
= 56 },
451 .p1
= { .min
= 2, .max
= 8 },
452 .p2
= { .dot_limit
= 225000,
453 .p2_slow
= 7, .p2_fast
= 7 },
456 /* LVDS 100mhz refclk limits. */
457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
458 .dot
= { .min
= 25000, .max
= 350000 },
459 .vco
= { .min
= 1760000, .max
= 3510000 },
460 .n
= { .min
= 1, .max
= 2 },
461 .m
= { .min
= 79, .max
= 126 },
462 .m1
= { .min
= 12, .max
= 22 },
463 .m2
= { .min
= 5, .max
= 9 },
464 .p
= { .min
= 28, .max
= 112 },
465 .p1
= { .min
= 2, .max
= 8 },
466 .p2
= { .dot_limit
= 225000,
467 .p2_slow
= 14, .p2_fast
= 14 },
470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
471 .dot
= { .min
= 25000, .max
= 350000 },
472 .vco
= { .min
= 1760000, .max
= 3510000 },
473 .n
= { .min
= 1, .max
= 3 },
474 .m
= { .min
= 79, .max
= 126 },
475 .m1
= { .min
= 12, .max
= 22 },
476 .m2
= { .min
= 5, .max
= 9 },
477 .p
= { .min
= 14, .max
= 42 },
478 .p1
= { .min
= 2, .max
= 6 },
479 .p2
= { .dot_limit
= 225000,
480 .p2_slow
= 7, .p2_fast
= 7 },
483 static const struct intel_limit intel_limits_vlv
= {
485 * These are the data rate limits (measured in fast clocks)
486 * since those are the strictest limits we have. The fast
487 * clock and actual rate limits are more relaxed, so checking
488 * them would make no difference.
490 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
491 .vco
= { .min
= 4000000, .max
= 6000000 },
492 .n
= { .min
= 1, .max
= 7 },
493 .m1
= { .min
= 2, .max
= 3 },
494 .m2
= { .min
= 11, .max
= 156 },
495 .p1
= { .min
= 2, .max
= 3 },
496 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
499 static const struct intel_limit intel_limits_chv
= {
501 * These are the data rate limits (measured in fast clocks)
502 * since those are the strictest limits we have. The fast
503 * clock and actual rate limits are more relaxed, so checking
504 * them would make no difference.
506 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
507 .vco
= { .min
= 4800000, .max
= 6480000 },
508 .n
= { .min
= 1, .max
= 1 },
509 .m1
= { .min
= 2, .max
= 2 },
510 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
511 .p1
= { .min
= 2, .max
= 4 },
512 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
515 static const struct intel_limit intel_limits_bxt
= {
516 /* FIXME: find real dot limits */
517 .dot
= { .min
= 0, .max
= INT_MAX
},
518 .vco
= { .min
= 4800000, .max
= 6700000 },
519 .n
= { .min
= 1, .max
= 1 },
520 .m1
= { .min
= 2, .max
= 2 },
521 /* FIXME: find real m2 limits */
522 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
523 .p1
= { .min
= 2, .max
= 4 },
524 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
528 needs_modeset(struct drm_crtc_state
*state
)
530 return drm_atomic_crtc_needs_modeset(state
);
534 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
535 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
536 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
537 * The helpers' return value is the rate of the clock that is fed to the
538 * display engine's pipe which can be the above fast dot clock rate or a
539 * divided-down version of it.
541 /* m1 is reserved as 0 in Pineview, n is a ring counter */
542 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
544 clock
->m
= clock
->m2
+ 2;
545 clock
->p
= clock
->p1
* clock
->p2
;
546 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
548 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
549 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
554 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
556 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
559 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
561 clock
->m
= i9xx_dpll_compute_m(clock
);
562 clock
->p
= clock
->p1
* clock
->p2
;
563 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
565 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
566 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
571 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
573 clock
->m
= clock
->m1
* clock
->m2
;
574 clock
->p
= clock
->p1
* clock
->p2
;
575 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
577 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
578 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
580 return clock
->dot
/ 5;
583 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
585 clock
->m
= clock
->m1
* clock
->m2
;
586 clock
->p
= clock
->p1
* clock
->p2
;
587 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
589 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
591 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
593 return clock
->dot
/ 5;
596 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
602 static bool intel_PLL_is_valid(struct drm_device
*dev
,
603 const struct intel_limit
*limit
,
604 const struct dpll
*clock
)
606 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
607 INTELPllInvalid("n out of range\n");
608 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
609 INTELPllInvalid("p1 out of range\n");
610 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
611 INTELPllInvalid("m2 out of range\n");
612 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
613 INTELPllInvalid("m1 out of range\n");
615 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) &&
616 !IS_CHERRYVIEW(dev
) && !IS_BROXTON(dev
))
617 if (clock
->m1
<= clock
->m2
)
618 INTELPllInvalid("m1 <= m2\n");
620 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) && !IS_BROXTON(dev
)) {
621 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
622 INTELPllInvalid("p out of range\n");
623 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
624 INTELPllInvalid("m out of range\n");
627 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
632 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
633 INTELPllInvalid("dot out of range\n");
639 i9xx_select_p2_div(const struct intel_limit
*limit
,
640 const struct intel_crtc_state
*crtc_state
,
643 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
645 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
647 * For LVDS just rely on its current settings for dual-channel.
648 * We haven't figured out how to reliably set up different
649 * single/dual channel state, if we even can.
651 if (intel_is_dual_link_lvds(dev
))
652 return limit
->p2
.p2_fast
;
654 return limit
->p2
.p2_slow
;
656 if (target
< limit
->p2
.dot_limit
)
657 return limit
->p2
.p2_slow
;
659 return limit
->p2
.p2_fast
;
664 * Returns a set of divisors for the desired target clock with the given
665 * refclk, or FALSE. The returned values represent the clock equation:
666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
668 * Target and reference clocks are specified in kHz.
670 * If match_clock is provided, then best_clock P divider must match the P
671 * divider from @match_clock used for LVDS downclocking.
674 i9xx_find_best_dpll(const struct intel_limit
*limit
,
675 struct intel_crtc_state
*crtc_state
,
676 int target
, int refclk
, struct dpll
*match_clock
,
677 struct dpll
*best_clock
)
679 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
683 memset(best_clock
, 0, sizeof(*best_clock
));
685 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
687 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
689 for (clock
.m2
= limit
->m2
.min
;
690 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
691 if (clock
.m2
>= clock
.m1
)
693 for (clock
.n
= limit
->n
.min
;
694 clock
.n
<= limit
->n
.max
; clock
.n
++) {
695 for (clock
.p1
= limit
->p1
.min
;
696 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
699 i9xx_calc_dpll_params(refclk
, &clock
);
700 if (!intel_PLL_is_valid(dev
, limit
,
704 clock
.p
!= match_clock
->p
)
707 this_err
= abs(clock
.dot
- target
);
708 if (this_err
< err
) {
717 return (err
!= target
);
721 * Returns a set of divisors for the desired target clock with the given
722 * refclk, or FALSE. The returned values represent the clock equation:
723 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
725 * Target and reference clocks are specified in kHz.
727 * If match_clock is provided, then best_clock P divider must match the P
728 * divider from @match_clock used for LVDS downclocking.
731 pnv_find_best_dpll(const struct intel_limit
*limit
,
732 struct intel_crtc_state
*crtc_state
,
733 int target
, int refclk
, struct dpll
*match_clock
,
734 struct dpll
*best_clock
)
736 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
740 memset(best_clock
, 0, sizeof(*best_clock
));
742 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
744 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
746 for (clock
.m2
= limit
->m2
.min
;
747 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
748 for (clock
.n
= limit
->n
.min
;
749 clock
.n
<= limit
->n
.max
; clock
.n
++) {
750 for (clock
.p1
= limit
->p1
.min
;
751 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
754 pnv_calc_dpll_params(refclk
, &clock
);
755 if (!intel_PLL_is_valid(dev
, limit
,
759 clock
.p
!= match_clock
->p
)
762 this_err
= abs(clock
.dot
- target
);
763 if (this_err
< err
) {
772 return (err
!= target
);
776 * Returns a set of divisors for the desired target clock with the given
777 * refclk, or FALSE. The returned values represent the clock equation:
778 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
780 * Target and reference clocks are specified in kHz.
782 * If match_clock is provided, then best_clock P divider must match the P
783 * divider from @match_clock used for LVDS downclocking.
786 g4x_find_best_dpll(const struct intel_limit
*limit
,
787 struct intel_crtc_state
*crtc_state
,
788 int target
, int refclk
, struct dpll
*match_clock
,
789 struct dpll
*best_clock
)
791 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
795 /* approximately equals target * 0.00585 */
796 int err_most
= (target
>> 8) + (target
>> 9);
798 memset(best_clock
, 0, sizeof(*best_clock
));
800 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
802 max_n
= limit
->n
.max
;
803 /* based on hardware requirement, prefer smaller n to precision */
804 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
805 /* based on hardware requirement, prefere larger m1,m2 */
806 for (clock
.m1
= limit
->m1
.max
;
807 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
808 for (clock
.m2
= limit
->m2
.max
;
809 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
810 for (clock
.p1
= limit
->p1
.max
;
811 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
814 i9xx_calc_dpll_params(refclk
, &clock
);
815 if (!intel_PLL_is_valid(dev
, limit
,
819 this_err
= abs(clock
.dot
- target
);
820 if (this_err
< err_most
) {
834 * Check if the calculated PLL configuration is more optimal compared to the
835 * best configuration and error found so far. Return the calculated error.
837 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
838 const struct dpll
*calculated_clock
,
839 const struct dpll
*best_clock
,
840 unsigned int best_error_ppm
,
841 unsigned int *error_ppm
)
844 * For CHV ignore the error and consider only the P value.
845 * Prefer a bigger P value based on HW requirements.
847 if (IS_CHERRYVIEW(dev
)) {
850 return calculated_clock
->p
> best_clock
->p
;
853 if (WARN_ON_ONCE(!target_freq
))
856 *error_ppm
= div_u64(1000000ULL *
857 abs(target_freq
- calculated_clock
->dot
),
860 * Prefer a better P value over a better (smaller) error if the error
861 * is small. Ensure this preference for future configurations too by
862 * setting the error to 0.
864 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
870 return *error_ppm
+ 10 < best_error_ppm
;
874 * Returns a set of divisors for the desired target clock with the given
875 * refclk, or FALSE. The returned values represent the clock equation:
876 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
879 vlv_find_best_dpll(const struct intel_limit
*limit
,
880 struct intel_crtc_state
*crtc_state
,
881 int target
, int refclk
, struct dpll
*match_clock
,
882 struct dpll
*best_clock
)
884 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
885 struct drm_device
*dev
= crtc
->base
.dev
;
887 unsigned int bestppm
= 1000000;
888 /* min update 19.2 MHz */
889 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
892 target
*= 5; /* fast clock */
894 memset(best_clock
, 0, sizeof(*best_clock
));
896 /* based on hardware requirement, prefer smaller n to precision */
897 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
898 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
899 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
900 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
901 clock
.p
= clock
.p1
* clock
.p2
;
902 /* based on hardware requirement, prefer bigger m1,m2 values */
903 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
906 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
909 vlv_calc_dpll_params(refclk
, &clock
);
911 if (!intel_PLL_is_valid(dev
, limit
,
915 if (!vlv_PLL_is_optimal(dev
, target
,
933 * Returns a set of divisors for the desired target clock with the given
934 * refclk, or FALSE. The returned values represent the clock equation:
935 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
938 chv_find_best_dpll(const struct intel_limit
*limit
,
939 struct intel_crtc_state
*crtc_state
,
940 int target
, int refclk
, struct dpll
*match_clock
,
941 struct dpll
*best_clock
)
943 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
944 struct drm_device
*dev
= crtc
->base
.dev
;
945 unsigned int best_error_ppm
;
950 memset(best_clock
, 0, sizeof(*best_clock
));
951 best_error_ppm
= 1000000;
954 * Based on hardware doc, the n always set to 1, and m1 always
955 * set to 2. If requires to support 200Mhz refclk, we need to
956 * revisit this because n may not 1 anymore.
958 clock
.n
= 1, clock
.m1
= 2;
959 target
*= 5; /* fast clock */
961 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
962 for (clock
.p2
= limit
->p2
.p2_fast
;
963 clock
.p2
>= limit
->p2
.p2_slow
;
964 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
965 unsigned int error_ppm
;
967 clock
.p
= clock
.p1
* clock
.p2
;
969 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
970 clock
.n
) << 22, refclk
* clock
.m1
);
972 if (m2
> INT_MAX
/clock
.m1
)
977 chv_calc_dpll_params(refclk
, &clock
);
979 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
982 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
983 best_error_ppm
, &error_ppm
))
987 best_error_ppm
= error_ppm
;
995 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
996 struct dpll
*best_clock
)
999 const struct intel_limit
*limit
= &intel_limits_bxt
;
1001 return chv_find_best_dpll(limit
, crtc_state
,
1002 target_clock
, refclk
, NULL
, best_clock
);
1005 bool intel_crtc_active(struct drm_crtc
*crtc
)
1007 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1009 /* Be paranoid as we can arrive here with only partial
1010 * state retrieved from the hardware during setup.
1012 * We can ditch the adjusted_mode.crtc_clock check as soon
1013 * as Haswell has gained clock readout/fastboot support.
1015 * We can ditch the crtc->primary->fb check as soon as we can
1016 * properly reconstruct framebuffers.
1018 * FIXME: The intel_crtc->active here should be switched to
1019 * crtc->state->active once we have proper CRTC states wired up
1022 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1023 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1026 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1029 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1030 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1032 return intel_crtc
->config
->cpu_transcoder
;
1035 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1037 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1038 i915_reg_t reg
= PIPEDSL(pipe
);
1043 line_mask
= DSL_LINEMASK_GEN2
;
1045 line_mask
= DSL_LINEMASK_GEN3
;
1047 line1
= I915_READ(reg
) & line_mask
;
1049 line2
= I915_READ(reg
) & line_mask
;
1051 return line1
== line2
;
1055 * intel_wait_for_pipe_off - wait for pipe to turn off
1056 * @crtc: crtc whose pipe to wait for
1058 * After disabling a pipe, we can't wait for vblank in the usual way,
1059 * spinning on the vblank interrupt status bit, since we won't actually
1060 * see an interrupt when the pipe is disabled.
1062 * On Gen4 and above:
1063 * wait for the pipe register state bit to turn off
1066 * wait for the display line value to settle (it usually
1067 * ends up stopping at the start of the next frame).
1070 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1072 struct drm_device
*dev
= crtc
->base
.dev
;
1073 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1074 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1075 enum pipe pipe
= crtc
->pipe
;
1077 if (INTEL_INFO(dev
)->gen
>= 4) {
1078 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1080 /* Wait for the Pipe State to go off */
1081 if (intel_wait_for_register(dev_priv
,
1082 reg
, I965_PIPECONF_ACTIVE
, 0,
1084 WARN(1, "pipe_off wait timed out\n");
1086 /* Wait for the display line to settle */
1087 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1088 WARN(1, "pipe_off wait timed out\n");
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private
*dev_priv
,
1094 enum pipe pipe
, bool state
)
1099 val
= I915_READ(DPLL(pipe
));
1100 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1101 I915_STATE_WARN(cur_state
!= state
,
1102 "PLL state assertion failure (expected %s, current %s)\n",
1103 onoff(state
), onoff(cur_state
));
1106 /* XXX: the dsi pll is shared between MIPI DSI ports */
1107 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1112 mutex_lock(&dev_priv
->sb_lock
);
1113 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1114 mutex_unlock(&dev_priv
->sb_lock
);
1116 cur_state
= val
& DSI_PLL_VCO_EN
;
1117 I915_STATE_WARN(cur_state
!= state
,
1118 "DSI PLL state assertion failure (expected %s, current %s)\n",
1119 onoff(state
), onoff(cur_state
));
1122 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1123 enum pipe pipe
, bool state
)
1126 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1129 if (HAS_DDI(dev_priv
)) {
1130 /* DDI does not have a specific FDI_TX register */
1131 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1132 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1134 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1135 cur_state
= !!(val
& FDI_TX_ENABLE
);
1137 I915_STATE_WARN(cur_state
!= state
,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 onoff(state
), onoff(cur_state
));
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1145 enum pipe pipe
, bool state
)
1150 val
= I915_READ(FDI_RX_CTL(pipe
));
1151 cur_state
= !!(val
& FDI_RX_ENABLE
);
1152 I915_STATE_WARN(cur_state
!= state
,
1153 "FDI RX state assertion failure (expected %s, current %s)\n",
1154 onoff(state
), onoff(cur_state
));
1156 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1164 /* ILK FDI PLL is always enabled */
1165 if (IS_GEN5(dev_priv
))
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv
))
1172 val
= I915_READ(FDI_TX_CTL(pipe
));
1173 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1176 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1177 enum pipe pipe
, bool state
)
1182 val
= I915_READ(FDI_RX_CTL(pipe
));
1183 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1184 I915_STATE_WARN(cur_state
!= state
,
1185 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186 onoff(state
), onoff(cur_state
));
1189 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1192 struct drm_device
*dev
= &dev_priv
->drm
;
1195 enum pipe panel_pipe
= PIPE_A
;
1198 if (WARN_ON(HAS_DDI(dev
)))
1201 if (HAS_PCH_SPLIT(dev
)) {
1204 pp_reg
= PCH_PP_CONTROL
;
1205 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1207 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1208 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1209 panel_pipe
= PIPE_B
;
1210 /* XXX: else fix for eDP */
1211 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1212 /* presumably write lock depends on pipe, not port select */
1213 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1216 pp_reg
= PP_CONTROL
;
1217 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1218 panel_pipe
= PIPE_B
;
1221 val
= I915_READ(pp_reg
);
1222 if (!(val
& PANEL_POWER_ON
) ||
1223 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1226 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1227 "panel assertion failure, pipe %c regs locked\n",
1231 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1232 enum pipe pipe
, bool state
)
1234 struct drm_device
*dev
= &dev_priv
->drm
;
1237 if (IS_845G(dev
) || IS_I865G(dev
))
1238 cur_state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
1240 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1242 I915_STATE_WARN(cur_state
!= state
,
1243 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1246 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1247 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249 void assert_pipe(struct drm_i915_private
*dev_priv
,
1250 enum pipe pipe
, bool state
)
1253 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1255 enum intel_display_power_domain power_domain
;
1257 /* if we need the pipe quirk it must be always on */
1258 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1259 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1262 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1263 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
1264 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1265 cur_state
= !!(val
& PIPECONF_ENABLE
);
1267 intel_display_power_put(dev_priv
, power_domain
);
1272 I915_STATE_WARN(cur_state
!= state
,
1273 "pipe %c assertion failure (expected %s, current %s)\n",
1274 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1277 static void assert_plane(struct drm_i915_private
*dev_priv
,
1278 enum plane plane
, bool state
)
1283 val
= I915_READ(DSPCNTR(plane
));
1284 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1285 I915_STATE_WARN(cur_state
!= state
,
1286 "plane %c assertion failure (expected %s, current %s)\n",
1287 plane_name(plane
), onoff(state
), onoff(cur_state
));
1290 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1291 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1296 struct drm_device
*dev
= &dev_priv
->drm
;
1299 /* Primary planes are fixed to pipes on gen4+ */
1300 if (INTEL_INFO(dev
)->gen
>= 4) {
1301 u32 val
= I915_READ(DSPCNTR(pipe
));
1302 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1303 "plane %c assertion failure, should be disabled but not\n",
1308 /* Need to check both planes against the pipe */
1309 for_each_pipe(dev_priv
, i
) {
1310 u32 val
= I915_READ(DSPCNTR(i
));
1311 enum pipe cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1312 DISPPLANE_SEL_PIPE_SHIFT
;
1313 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1314 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1315 plane_name(i
), pipe_name(pipe
));
1319 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1322 struct drm_device
*dev
= &dev_priv
->drm
;
1325 if (INTEL_INFO(dev
)->gen
>= 9) {
1326 for_each_sprite(dev_priv
, pipe
, sprite
) {
1327 u32 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1328 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1329 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1330 sprite
, pipe_name(pipe
));
1332 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1333 for_each_sprite(dev_priv
, pipe
, sprite
) {
1334 u32 val
= I915_READ(SPCNTR(pipe
, sprite
));
1335 I915_STATE_WARN(val
& SP_ENABLE
,
1336 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1339 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1340 u32 val
= I915_READ(SPRCTL(pipe
));
1341 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1342 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343 plane_name(pipe
), pipe_name(pipe
));
1344 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1345 u32 val
= I915_READ(DVSCNTR(pipe
));
1346 I915_STATE_WARN(val
& DVS_ENABLE
,
1347 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1348 plane_name(pipe
), pipe_name(pipe
));
1352 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1354 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1355 drm_crtc_vblank_put(crtc
);
1358 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1364 val
= I915_READ(PCH_TRANSCONF(pipe
));
1365 enabled
= !!(val
& TRANS_ENABLE
);
1366 I915_STATE_WARN(enabled
,
1367 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1371 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1372 enum pipe pipe
, u32 port_sel
, u32 val
)
1374 if ((val
& DP_PORT_EN
) == 0)
1377 if (HAS_PCH_CPT(dev_priv
)) {
1378 u32 trans_dp_ctl
= I915_READ(TRANS_DP_CTL(pipe
));
1379 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1381 } else if (IS_CHERRYVIEW(dev_priv
)) {
1382 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1385 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1391 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1392 enum pipe pipe
, u32 val
)
1394 if ((val
& SDVO_ENABLE
) == 0)
1397 if (HAS_PCH_CPT(dev_priv
)) {
1398 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1400 } else if (IS_CHERRYVIEW(dev_priv
)) {
1401 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1404 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1410 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1411 enum pipe pipe
, u32 val
)
1413 if ((val
& LVDS_PORT_EN
) == 0)
1416 if (HAS_PCH_CPT(dev_priv
)) {
1417 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1420 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1426 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1427 enum pipe pipe
, u32 val
)
1429 if ((val
& ADPA_DAC_ENABLE
) == 0)
1431 if (HAS_PCH_CPT(dev_priv
)) {
1432 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1435 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1441 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1442 enum pipe pipe
, i915_reg_t reg
,
1445 u32 val
= I915_READ(reg
);
1446 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1447 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1448 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1450 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& DP_PORT_EN
) == 0
1451 && (val
& DP_PIPEB_SELECT
),
1452 "IBX PCH dp port still using transcoder B\n");
1455 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1456 enum pipe pipe
, i915_reg_t reg
)
1458 u32 val
= I915_READ(reg
);
1459 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1460 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1461 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1463 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& SDVO_ENABLE
) == 0
1464 && (val
& SDVO_PIPE_B_SELECT
),
1465 "IBX PCH hdmi port still using transcoder B\n");
1468 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1473 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1474 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1475 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1477 val
= I915_READ(PCH_ADPA
);
1478 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1479 "PCH VGA enabled on transcoder %c, should be disabled\n",
1482 val
= I915_READ(PCH_LVDS
);
1483 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1484 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1487 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1488 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1489 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1492 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1493 const struct intel_crtc_state
*pipe_config
)
1495 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1496 enum pipe pipe
= crtc
->pipe
;
1498 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1499 POSTING_READ(DPLL(pipe
));
1502 if (intel_wait_for_register(dev_priv
,
1507 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1510 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1511 const struct intel_crtc_state
*pipe_config
)
1513 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1514 enum pipe pipe
= crtc
->pipe
;
1516 assert_pipe_disabled(dev_priv
, pipe
);
1518 /* PLL is protected by panel, make sure we can write it */
1519 assert_panel_unlocked(dev_priv
, pipe
);
1521 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1522 _vlv_enable_pll(crtc
, pipe_config
);
1524 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1525 POSTING_READ(DPLL_MD(pipe
));
1529 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1530 const struct intel_crtc_state
*pipe_config
)
1532 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1533 enum pipe pipe
= crtc
->pipe
;
1534 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1537 mutex_lock(&dev_priv
->sb_lock
);
1539 /* Enable back the 10bit clock to display controller */
1540 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1541 tmp
|= DPIO_DCLKP_EN
;
1542 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1544 mutex_unlock(&dev_priv
->sb_lock
);
1547 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1552 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1554 /* Check PLL is locked */
1555 if (intel_wait_for_register(dev_priv
,
1556 DPLL(pipe
), DPLL_LOCK_VLV
, DPLL_LOCK_VLV
,
1558 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1561 static void chv_enable_pll(struct intel_crtc
*crtc
,
1562 const struct intel_crtc_state
*pipe_config
)
1564 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1565 enum pipe pipe
= crtc
->pipe
;
1567 assert_pipe_disabled(dev_priv
, pipe
);
1569 /* PLL is protected by panel, make sure we can write it */
1570 assert_panel_unlocked(dev_priv
, pipe
);
1572 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1573 _chv_enable_pll(crtc
, pipe_config
);
1575 if (pipe
!= PIPE_A
) {
1577 * WaPixelRepeatModeFixForC0:chv
1579 * DPLLCMD is AWOL. Use chicken bits to propagate
1580 * the value from DPLLBMD to either pipe B or C.
1582 I915_WRITE(CBR4_VLV
, pipe
== PIPE_B
? CBR_DPLLBMD_PIPE_B
: CBR_DPLLBMD_PIPE_C
);
1583 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1584 I915_WRITE(CBR4_VLV
, 0);
1585 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1588 * DPLLB VGA mode also seems to cause problems.
1589 * We should always have it disabled.
1591 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1593 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1594 POSTING_READ(DPLL_MD(pipe
));
1598 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1600 struct intel_crtc
*crtc
;
1603 for_each_intel_crtc(dev
, crtc
) {
1604 count
+= crtc
->base
.state
->active
&&
1605 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
);
1611 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1613 struct drm_device
*dev
= crtc
->base
.dev
;
1614 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1615 i915_reg_t reg
= DPLL(crtc
->pipe
);
1616 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1618 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1620 /* PLL is protected by panel, make sure we can write it */
1621 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1622 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1624 /* Enable DVO 2x clock on both PLLs if necessary */
1625 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1627 * It appears to be important that we don't enable this
1628 * for the current pipe before otherwise configuring the
1629 * PLL. No idea how this should be handled if multiple
1630 * DVO outputs are enabled simultaneosly.
1632 dpll
|= DPLL_DVO_2X_MODE
;
1633 I915_WRITE(DPLL(!crtc
->pipe
),
1634 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1638 * Apparently we need to have VGA mode enabled prior to changing
1639 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1640 * dividers, even though the register value does change.
1644 I915_WRITE(reg
, dpll
);
1646 /* Wait for the clocks to stabilize. */
1650 if (INTEL_INFO(dev
)->gen
>= 4) {
1651 I915_WRITE(DPLL_MD(crtc
->pipe
),
1652 crtc
->config
->dpll_hw_state
.dpll_md
);
1654 /* The pixel multiplier can only be updated once the
1655 * DPLL is enabled and the clocks are stable.
1657 * So write it again.
1659 I915_WRITE(reg
, dpll
);
1662 /* We do this three times for luck */
1663 I915_WRITE(reg
, dpll
);
1665 udelay(150); /* wait for warmup */
1666 I915_WRITE(reg
, dpll
);
1668 udelay(150); /* wait for warmup */
1669 I915_WRITE(reg
, dpll
);
1671 udelay(150); /* wait for warmup */
1675 * i9xx_disable_pll - disable a PLL
1676 * @dev_priv: i915 private structure
1677 * @pipe: pipe PLL to disable
1679 * Disable the PLL for @pipe, making sure the pipe is off first.
1681 * Note! This is for pre-ILK only.
1683 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1685 struct drm_device
*dev
= crtc
->base
.dev
;
1686 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1687 enum pipe pipe
= crtc
->pipe
;
1689 /* Disable DVO 2x clock on both PLLs if necessary */
1691 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
) &&
1692 !intel_num_dvo_pipes(dev
)) {
1693 I915_WRITE(DPLL(PIPE_B
),
1694 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1695 I915_WRITE(DPLL(PIPE_A
),
1696 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1699 /* Don't disable pipe or pipe PLLs if needed */
1700 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1701 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1704 /* Make sure the pipe isn't still relying on us */
1705 assert_pipe_disabled(dev_priv
, pipe
);
1707 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1708 POSTING_READ(DPLL(pipe
));
1711 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1715 /* Make sure the pipe isn't still relying on us */
1716 assert_pipe_disabled(dev_priv
, pipe
);
1718 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1719 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1721 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1723 I915_WRITE(DPLL(pipe
), val
);
1724 POSTING_READ(DPLL(pipe
));
1727 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1729 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1732 /* Make sure the pipe isn't still relying on us */
1733 assert_pipe_disabled(dev_priv
, pipe
);
1735 val
= DPLL_SSC_REF_CLK_CHV
|
1736 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1738 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1740 I915_WRITE(DPLL(pipe
), val
);
1741 POSTING_READ(DPLL(pipe
));
1743 mutex_lock(&dev_priv
->sb_lock
);
1745 /* Disable 10bit clock to display controller */
1746 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1747 val
&= ~DPIO_DCLKP_EN
;
1748 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1750 mutex_unlock(&dev_priv
->sb_lock
);
1753 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1754 struct intel_digital_port
*dport
,
1755 unsigned int expected_mask
)
1758 i915_reg_t dpll_reg
;
1760 switch (dport
->port
) {
1762 port_mask
= DPLL_PORTB_READY_MASK
;
1766 port_mask
= DPLL_PORTC_READY_MASK
;
1768 expected_mask
<<= 4;
1771 port_mask
= DPLL_PORTD_READY_MASK
;
1772 dpll_reg
= DPIO_PHY_STATUS
;
1778 if (intel_wait_for_register(dev_priv
,
1779 dpll_reg
, port_mask
, expected_mask
,
1781 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1782 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1785 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1788 struct drm_device
*dev
= &dev_priv
->drm
;
1789 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1790 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1792 uint32_t val
, pipeconf_val
;
1794 /* Make sure PCH DPLL is enabled */
1795 assert_shared_dpll_enabled(dev_priv
, intel_crtc
->config
->shared_dpll
);
1797 /* FDI must be feeding us bits for PCH ports */
1798 assert_fdi_tx_enabled(dev_priv
, pipe
);
1799 assert_fdi_rx_enabled(dev_priv
, pipe
);
1801 if (HAS_PCH_CPT(dev
)) {
1802 /* Workaround: Set the timing override bit before enabling the
1803 * pch transcoder. */
1804 reg
= TRANS_CHICKEN2(pipe
);
1805 val
= I915_READ(reg
);
1806 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1807 I915_WRITE(reg
, val
);
1810 reg
= PCH_TRANSCONF(pipe
);
1811 val
= I915_READ(reg
);
1812 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1814 if (HAS_PCH_IBX(dev_priv
)) {
1816 * Make the BPC in transcoder be consistent with
1817 * that in pipeconf reg. For HDMI we must use 8bpc
1818 * here for both 8bpc and 12bpc.
1820 val
&= ~PIPECONF_BPC_MASK
;
1821 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_HDMI
))
1822 val
|= PIPECONF_8BPC
;
1824 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1827 val
&= ~TRANS_INTERLACE_MASK
;
1828 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1829 if (HAS_PCH_IBX(dev_priv
) &&
1830 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
1831 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1833 val
|= TRANS_INTERLACED
;
1835 val
|= TRANS_PROGRESSIVE
;
1837 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1838 if (intel_wait_for_register(dev_priv
,
1839 reg
, TRANS_STATE_ENABLE
, TRANS_STATE_ENABLE
,
1841 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1844 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1845 enum transcoder cpu_transcoder
)
1847 u32 val
, pipeconf_val
;
1849 /* FDI must be feeding us bits for PCH ports */
1850 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1851 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1853 /* Workaround: set timing override bit. */
1854 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1855 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1856 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1859 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1861 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1862 PIPECONF_INTERLACED_ILK
)
1863 val
|= TRANS_INTERLACED
;
1865 val
|= TRANS_PROGRESSIVE
;
1867 I915_WRITE(LPT_TRANSCONF
, val
);
1868 if (intel_wait_for_register(dev_priv
,
1873 DRM_ERROR("Failed to enable PCH transcoder\n");
1876 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1879 struct drm_device
*dev
= &dev_priv
->drm
;
1883 /* FDI relies on the transcoder */
1884 assert_fdi_tx_disabled(dev_priv
, pipe
);
1885 assert_fdi_rx_disabled(dev_priv
, pipe
);
1887 /* Ports must be off as well */
1888 assert_pch_ports_disabled(dev_priv
, pipe
);
1890 reg
= PCH_TRANSCONF(pipe
);
1891 val
= I915_READ(reg
);
1892 val
&= ~TRANS_ENABLE
;
1893 I915_WRITE(reg
, val
);
1894 /* wait for PCH transcoder off, transcoder state */
1895 if (intel_wait_for_register(dev_priv
,
1896 reg
, TRANS_STATE_ENABLE
, 0,
1898 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1900 if (HAS_PCH_CPT(dev
)) {
1901 /* Workaround: Clear the timing override chicken bit again. */
1902 reg
= TRANS_CHICKEN2(pipe
);
1903 val
= I915_READ(reg
);
1904 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1905 I915_WRITE(reg
, val
);
1909 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1913 val
= I915_READ(LPT_TRANSCONF
);
1914 val
&= ~TRANS_ENABLE
;
1915 I915_WRITE(LPT_TRANSCONF
, val
);
1916 /* wait for PCH transcoder off, transcoder state */
1917 if (intel_wait_for_register(dev_priv
,
1918 LPT_TRANSCONF
, TRANS_STATE_ENABLE
, 0,
1920 DRM_ERROR("Failed to disable PCH transcoder\n");
1922 /* Workaround: clear timing override bit. */
1923 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1924 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1925 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1929 * intel_enable_pipe - enable a pipe, asserting requirements
1930 * @crtc: crtc responsible for the pipe
1932 * Enable @crtc's pipe, making sure that various hardware specific requirements
1933 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1937 struct drm_device
*dev
= crtc
->base
.dev
;
1938 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1939 enum pipe pipe
= crtc
->pipe
;
1940 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1941 enum pipe pch_transcoder
;
1945 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1947 assert_planes_disabled(dev_priv
, pipe
);
1948 assert_cursor_disabled(dev_priv
, pipe
);
1949 assert_sprites_disabled(dev_priv
, pipe
);
1951 if (HAS_PCH_LPT(dev_priv
))
1952 pch_transcoder
= TRANSCODER_A
;
1954 pch_transcoder
= pipe
;
1957 * A pipe without a PLL won't actually be able to drive bits from
1958 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1961 if (HAS_GMCH_DISPLAY(dev_priv
))
1962 if (crtc
->config
->has_dsi_encoder
)
1963 assert_dsi_pll_enabled(dev_priv
);
1965 assert_pll_enabled(dev_priv
, pipe
);
1967 if (crtc
->config
->has_pch_encoder
) {
1968 /* if driving the PCH, we need FDI enabled */
1969 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1970 assert_fdi_tx_pll_enabled(dev_priv
,
1971 (enum pipe
) cpu_transcoder
);
1973 /* FIXME: assert CPU port conditions for SNB+ */
1976 reg
= PIPECONF(cpu_transcoder
);
1977 val
= I915_READ(reg
);
1978 if (val
& PIPECONF_ENABLE
) {
1979 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1980 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
1984 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1988 * Until the pipe starts DSL will read as 0, which would cause
1989 * an apparent vblank timestamp jump, which messes up also the
1990 * frame count when it's derived from the timestamps. So let's
1991 * wait for the pipe to start properly before we call
1992 * drm_crtc_vblank_on()
1994 if (dev
->max_vblank_count
== 0 &&
1995 wait_for(intel_get_crtc_scanline(crtc
) != crtc
->scanline_offset
, 50))
1996 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe
));
2000 * intel_disable_pipe - disable a pipe, asserting requirements
2001 * @crtc: crtc whose pipes is to be disabled
2003 * Disable the pipe of @crtc, making sure that various hardware
2004 * specific requirements are met, if applicable, e.g. plane
2005 * disabled, panel fitter off, etc.
2007 * Will wait until the pipe has shut down before returning.
2009 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2011 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2012 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2013 enum pipe pipe
= crtc
->pipe
;
2017 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
2020 * Make sure planes won't keep trying to pump pixels to us,
2021 * or we might hang the display.
2023 assert_planes_disabled(dev_priv
, pipe
);
2024 assert_cursor_disabled(dev_priv
, pipe
);
2025 assert_sprites_disabled(dev_priv
, pipe
);
2027 reg
= PIPECONF(cpu_transcoder
);
2028 val
= I915_READ(reg
);
2029 if ((val
& PIPECONF_ENABLE
) == 0)
2033 * Double wide has implications for planes
2034 * so best keep it disabled when not needed.
2036 if (crtc
->config
->double_wide
)
2037 val
&= ~PIPECONF_DOUBLE_WIDE
;
2039 /* Don't disable pipe or pipe PLLs if needed */
2040 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2041 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2042 val
&= ~PIPECONF_ENABLE
;
2044 I915_WRITE(reg
, val
);
2045 if ((val
& PIPECONF_ENABLE
) == 0)
2046 intel_wait_for_pipe_off(crtc
);
2049 static bool need_vtd_wa(struct drm_device
*dev
)
2051 #ifdef CONFIG_INTEL_IOMMU
2052 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2058 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
2060 return IS_GEN2(dev_priv
) ? 2048 : 4096;
2063 static unsigned int intel_tile_width_bytes(const struct drm_i915_private
*dev_priv
,
2064 uint64_t fb_modifier
, unsigned int cpp
)
2066 switch (fb_modifier
) {
2067 case DRM_FORMAT_MOD_NONE
:
2069 case I915_FORMAT_MOD_X_TILED
:
2070 if (IS_GEN2(dev_priv
))
2074 case I915_FORMAT_MOD_Y_TILED
:
2075 if (IS_GEN2(dev_priv
) || HAS_128_BYTE_Y_TILING(dev_priv
))
2079 case I915_FORMAT_MOD_Yf_TILED
:
2095 MISSING_CASE(fb_modifier
);
2100 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
2101 uint64_t fb_modifier
, unsigned int cpp
)
2103 if (fb_modifier
== DRM_FORMAT_MOD_NONE
)
2106 return intel_tile_size(dev_priv
) /
2107 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2110 /* Return the tile dimensions in pixel units */
2111 static void intel_tile_dims(const struct drm_i915_private
*dev_priv
,
2112 unsigned int *tile_width
,
2113 unsigned int *tile_height
,
2114 uint64_t fb_modifier
,
2117 unsigned int tile_width_bytes
=
2118 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2120 *tile_width
= tile_width_bytes
/ cpp
;
2121 *tile_height
= intel_tile_size(dev_priv
) / tile_width_bytes
;
2125 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2126 uint32_t pixel_format
, uint64_t fb_modifier
)
2128 unsigned int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2129 unsigned int tile_height
= intel_tile_height(to_i915(dev
), fb_modifier
, cpp
);
2131 return ALIGN(height
, tile_height
);
2134 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
2136 unsigned int size
= 0;
2139 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
2140 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2146 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2147 const struct drm_framebuffer
*fb
,
2148 unsigned int rotation
)
2150 if (intel_rotation_90_or_270(rotation
)) {
2151 *view
= i915_ggtt_view_rotated
;
2152 view
->params
.rotated
= to_intel_framebuffer(fb
)->rot_info
;
2154 *view
= i915_ggtt_view_normal
;
2159 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2160 struct drm_framebuffer
*fb
)
2162 struct intel_rotation_info
*info
= &to_intel_framebuffer(fb
)->rot_info
;
2163 unsigned int tile_size
, tile_width
, tile_height
, cpp
;
2165 tile_size
= intel_tile_size(dev_priv
);
2167 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2168 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2169 fb
->modifier
[0], cpp
);
2171 info
->plane
[0].width
= DIV_ROUND_UP(fb
->pitches
[0], tile_width
* cpp
);
2172 info
->plane
[0].height
= DIV_ROUND_UP(fb
->height
, tile_height
);
2174 if (info
->pixel_format
== DRM_FORMAT_NV12
) {
2175 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 1);
2176 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2177 fb
->modifier
[1], cpp
);
2179 info
->uv_offset
= fb
->offsets
[1];
2180 info
->plane
[1].width
= DIV_ROUND_UP(fb
->pitches
[1], tile_width
* cpp
);
2181 info
->plane
[1].height
= DIV_ROUND_UP(fb
->height
/ 2, tile_height
);
2185 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2187 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2189 else if (IS_BROADWATER(dev_priv
) || IS_CRESTLINE(dev_priv
) ||
2190 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2192 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2198 static unsigned int intel_surf_alignment(const struct drm_i915_private
*dev_priv
,
2199 uint64_t fb_modifier
)
2201 switch (fb_modifier
) {
2202 case DRM_FORMAT_MOD_NONE
:
2203 return intel_linear_alignment(dev_priv
);
2204 case I915_FORMAT_MOD_X_TILED
:
2205 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2208 case I915_FORMAT_MOD_Y_TILED
:
2209 case I915_FORMAT_MOD_Yf_TILED
:
2210 return 1 * 1024 * 1024;
2212 MISSING_CASE(fb_modifier
);
2218 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
2219 unsigned int rotation
)
2221 struct drm_device
*dev
= fb
->dev
;
2222 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2223 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2224 struct i915_ggtt_view view
;
2228 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2230 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
[0]);
2232 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2234 /* Note that the w/a also requires 64 PTE of padding following the
2235 * bo. We currently fill all unused PTE with the shadow page and so
2236 * we should always have valid PTE following the scanout preventing
2239 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2240 alignment
= 256 * 1024;
2243 * Global gtt pte registers are special registers which actually forward
2244 * writes to a chunk of system memory. Which means that there is no risk
2245 * that the register values disappear as soon as we call
2246 * intel_runtime_pm_put(), so it is correct to wrap only the
2247 * pin/unpin/fence and not more.
2249 intel_runtime_pm_get(dev_priv
);
2251 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
,
2256 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2257 * fence, whereas 965+ only requires a fence if using
2258 * framebuffer compression. For simplicity, we always install
2259 * a fence as the cost is not that onerous.
2261 if (view
.type
== I915_GGTT_VIEW_NORMAL
) {
2262 ret
= i915_gem_object_get_fence(obj
);
2263 if (ret
== -EDEADLK
) {
2265 * -EDEADLK means there are no free fences
2268 * This is propagated to atomic, but it uses
2269 * -EDEADLK to force a locking recovery, so
2270 * change the returned error to -EBUSY.
2277 i915_gem_object_pin_fence(obj
);
2280 intel_runtime_pm_put(dev_priv
);
2284 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2286 intel_runtime_pm_put(dev_priv
);
2290 void intel_unpin_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
)
2292 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2293 struct i915_ggtt_view view
;
2295 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2297 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2299 if (view
.type
== I915_GGTT_VIEW_NORMAL
)
2300 i915_gem_object_unpin_fence(obj
);
2302 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2306 * Adjust the tile offset by moving the difference into
2309 * Input tile dimensions and pitch must already be
2310 * rotated to match x and y, and in pixel units.
2312 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2313 unsigned int tile_width
,
2314 unsigned int tile_height
,
2315 unsigned int tile_size
,
2316 unsigned int pitch_tiles
,
2322 WARN_ON(old_offset
& (tile_size
- 1));
2323 WARN_ON(new_offset
& (tile_size
- 1));
2324 WARN_ON(new_offset
> old_offset
);
2326 tiles
= (old_offset
- new_offset
) / tile_size
;
2328 *y
+= tiles
/ pitch_tiles
* tile_height
;
2329 *x
+= tiles
% pitch_tiles
* tile_width
;
2335 * Computes the linear offset to the base tile and adjusts
2336 * x, y. bytes per pixel is assumed to be a power-of-two.
2338 * In the 90/270 rotated case, x and y are assumed
2339 * to be already rotated to match the rotated GTT view, and
2340 * pitch is the tile_height aligned framebuffer height.
2342 u32
intel_compute_tile_offset(int *x
, int *y
,
2343 const struct drm_framebuffer
*fb
, int plane
,
2345 unsigned int rotation
)
2347 const struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
2348 uint64_t fb_modifier
= fb
->modifier
[plane
];
2349 unsigned int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
2350 u32 offset
, offset_aligned
, alignment
;
2352 alignment
= intel_surf_alignment(dev_priv
, fb_modifier
);
2356 if (fb_modifier
!= DRM_FORMAT_MOD_NONE
) {
2357 unsigned int tile_size
, tile_width
, tile_height
;
2358 unsigned int tile_rows
, tiles
, pitch_tiles
;
2360 tile_size
= intel_tile_size(dev_priv
);
2361 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2364 if (intel_rotation_90_or_270(rotation
)) {
2365 pitch_tiles
= pitch
/ tile_height
;
2366 swap(tile_width
, tile_height
);
2368 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2371 tile_rows
= *y
/ tile_height
;
2374 tiles
= *x
/ tile_width
;
2377 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2378 offset_aligned
= offset
& ~alignment
;
2380 intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2381 tile_size
, pitch_tiles
,
2382 offset
, offset_aligned
);
2384 offset
= *y
* pitch
+ *x
* cpp
;
2385 offset_aligned
= offset
& ~alignment
;
2387 *y
= (offset
& alignment
) / pitch
;
2388 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2391 return offset_aligned
;
2394 static int i9xx_format_to_fourcc(int format
)
2397 case DISPPLANE_8BPP
:
2398 return DRM_FORMAT_C8
;
2399 case DISPPLANE_BGRX555
:
2400 return DRM_FORMAT_XRGB1555
;
2401 case DISPPLANE_BGRX565
:
2402 return DRM_FORMAT_RGB565
;
2404 case DISPPLANE_BGRX888
:
2405 return DRM_FORMAT_XRGB8888
;
2406 case DISPPLANE_RGBX888
:
2407 return DRM_FORMAT_XBGR8888
;
2408 case DISPPLANE_BGRX101010
:
2409 return DRM_FORMAT_XRGB2101010
;
2410 case DISPPLANE_RGBX101010
:
2411 return DRM_FORMAT_XBGR2101010
;
2415 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2418 case PLANE_CTL_FORMAT_RGB_565
:
2419 return DRM_FORMAT_RGB565
;
2421 case PLANE_CTL_FORMAT_XRGB_8888
:
2424 return DRM_FORMAT_ABGR8888
;
2426 return DRM_FORMAT_XBGR8888
;
2429 return DRM_FORMAT_ARGB8888
;
2431 return DRM_FORMAT_XRGB8888
;
2433 case PLANE_CTL_FORMAT_XRGB_2101010
:
2435 return DRM_FORMAT_XBGR2101010
;
2437 return DRM_FORMAT_XRGB2101010
;
2442 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2443 struct intel_initial_plane_config
*plane_config
)
2445 struct drm_device
*dev
= crtc
->base
.dev
;
2446 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2447 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2448 struct drm_i915_gem_object
*obj
= NULL
;
2449 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2450 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2451 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2452 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2455 size_aligned
-= base_aligned
;
2457 if (plane_config
->size
== 0)
2460 /* If the FB is too big, just don't use it since fbdev is not very
2461 * important and we should probably use that space with FBC or other
2463 if (size_aligned
* 2 > ggtt
->stolen_usable_size
)
2466 mutex_lock(&dev
->struct_mutex
);
2468 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2473 mutex_unlock(&dev
->struct_mutex
);
2477 obj
->tiling_mode
= plane_config
->tiling
;
2478 if (obj
->tiling_mode
== I915_TILING_X
)
2479 obj
->stride
= fb
->pitches
[0];
2481 mode_cmd
.pixel_format
= fb
->pixel_format
;
2482 mode_cmd
.width
= fb
->width
;
2483 mode_cmd
.height
= fb
->height
;
2484 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2485 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2486 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2488 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2490 DRM_DEBUG_KMS("intel fb init failed\n");
2494 mutex_unlock(&dev
->struct_mutex
);
2496 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2500 drm_gem_object_unreference(&obj
->base
);
2501 mutex_unlock(&dev
->struct_mutex
);
2505 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2507 update_state_fb(struct drm_plane
*plane
)
2509 if (plane
->fb
== plane
->state
->fb
)
2512 if (plane
->state
->fb
)
2513 drm_framebuffer_unreference(plane
->state
->fb
);
2514 plane
->state
->fb
= plane
->fb
;
2515 if (plane
->state
->fb
)
2516 drm_framebuffer_reference(plane
->state
->fb
);
2520 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2521 struct intel_initial_plane_config
*plane_config
)
2523 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2524 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2526 struct intel_crtc
*i
;
2527 struct drm_i915_gem_object
*obj
;
2528 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2529 struct drm_plane_state
*plane_state
= primary
->state
;
2530 struct drm_crtc_state
*crtc_state
= intel_crtc
->base
.state
;
2531 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2532 struct intel_plane_state
*intel_state
=
2533 to_intel_plane_state(plane_state
);
2534 struct drm_framebuffer
*fb
;
2536 if (!plane_config
->fb
)
2539 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2540 fb
= &plane_config
->fb
->base
;
2544 kfree(plane_config
->fb
);
2547 * Failed to alloc the obj, check to see if we should share
2548 * an fb with another CRTC instead
2550 for_each_crtc(dev
, c
) {
2551 i
= to_intel_crtc(c
);
2553 if (c
== &intel_crtc
->base
)
2559 fb
= c
->primary
->fb
;
2563 obj
= intel_fb_obj(fb
);
2564 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2565 drm_framebuffer_reference(fb
);
2571 * We've failed to reconstruct the BIOS FB. Current display state
2572 * indicates that the primary plane is visible, but has a NULL FB,
2573 * which will lead to problems later if we don't fix it up. The
2574 * simplest solution is to just disable the primary plane now and
2575 * pretend the BIOS never had it enabled.
2577 to_intel_plane_state(plane_state
)->visible
= false;
2578 crtc_state
->plane_mask
&= ~(1 << drm_plane_index(primary
));
2579 intel_pre_disable_primary_noatomic(&intel_crtc
->base
);
2580 intel_plane
->disable_plane(primary
, &intel_crtc
->base
);
2585 plane_state
->src_x
= 0;
2586 plane_state
->src_y
= 0;
2587 plane_state
->src_w
= fb
->width
<< 16;
2588 plane_state
->src_h
= fb
->height
<< 16;
2590 plane_state
->crtc_x
= 0;
2591 plane_state
->crtc_y
= 0;
2592 plane_state
->crtc_w
= fb
->width
;
2593 plane_state
->crtc_h
= fb
->height
;
2595 intel_state
->src
.x1
= plane_state
->src_x
;
2596 intel_state
->src
.y1
= plane_state
->src_y
;
2597 intel_state
->src
.x2
= plane_state
->src_x
+ plane_state
->src_w
;
2598 intel_state
->src
.y2
= plane_state
->src_y
+ plane_state
->src_h
;
2599 intel_state
->dst
.x1
= plane_state
->crtc_x
;
2600 intel_state
->dst
.y1
= plane_state
->crtc_y
;
2601 intel_state
->dst
.x2
= plane_state
->crtc_x
+ plane_state
->crtc_w
;
2602 intel_state
->dst
.y2
= plane_state
->crtc_y
+ plane_state
->crtc_h
;
2604 obj
= intel_fb_obj(fb
);
2605 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2606 dev_priv
->preserve_bios_swizzle
= true;
2608 drm_framebuffer_reference(fb
);
2609 primary
->fb
= primary
->state
->fb
= fb
;
2610 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2611 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2612 obj
->frontbuffer_bits
|= to_intel_plane(primary
)->frontbuffer_bit
;
2615 static void i9xx_update_primary_plane(struct drm_plane
*primary
,
2616 const struct intel_crtc_state
*crtc_state
,
2617 const struct intel_plane_state
*plane_state
)
2619 struct drm_device
*dev
= primary
->dev
;
2620 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2621 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2622 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2623 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2624 int plane
= intel_crtc
->plane
;
2627 i915_reg_t reg
= DSPCNTR(plane
);
2628 unsigned int rotation
= plane_state
->base
.rotation
;
2629 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2630 int x
= plane_state
->src
.x1
>> 16;
2631 int y
= plane_state
->src
.y1
>> 16;
2633 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2635 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2637 if (INTEL_INFO(dev
)->gen
< 4) {
2638 if (intel_crtc
->pipe
== PIPE_B
)
2639 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2641 /* pipesrc and dspsize control the size that is scaled from,
2642 * which should always be the user's requested size.
2644 I915_WRITE(DSPSIZE(plane
),
2645 ((crtc_state
->pipe_src_h
- 1) << 16) |
2646 (crtc_state
->pipe_src_w
- 1));
2647 I915_WRITE(DSPPOS(plane
), 0);
2648 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2649 I915_WRITE(PRIMSIZE(plane
),
2650 ((crtc_state
->pipe_src_h
- 1) << 16) |
2651 (crtc_state
->pipe_src_w
- 1));
2652 I915_WRITE(PRIMPOS(plane
), 0);
2653 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2656 switch (fb
->pixel_format
) {
2658 dspcntr
|= DISPPLANE_8BPP
;
2660 case DRM_FORMAT_XRGB1555
:
2661 dspcntr
|= DISPPLANE_BGRX555
;
2663 case DRM_FORMAT_RGB565
:
2664 dspcntr
|= DISPPLANE_BGRX565
;
2666 case DRM_FORMAT_XRGB8888
:
2667 dspcntr
|= DISPPLANE_BGRX888
;
2669 case DRM_FORMAT_XBGR8888
:
2670 dspcntr
|= DISPPLANE_RGBX888
;
2672 case DRM_FORMAT_XRGB2101010
:
2673 dspcntr
|= DISPPLANE_BGRX101010
;
2675 case DRM_FORMAT_XBGR2101010
:
2676 dspcntr
|= DISPPLANE_RGBX101010
;
2682 if (INTEL_INFO(dev
)->gen
>= 4 &&
2683 obj
->tiling_mode
!= I915_TILING_NONE
)
2684 dspcntr
|= DISPPLANE_TILED
;
2687 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2689 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
2691 if (INTEL_INFO(dev
)->gen
>= 4) {
2692 intel_crtc
->dspaddr_offset
=
2693 intel_compute_tile_offset(&x
, &y
, fb
, 0,
2694 fb
->pitches
[0], rotation
);
2695 linear_offset
-= intel_crtc
->dspaddr_offset
;
2697 intel_crtc
->dspaddr_offset
= linear_offset
;
2700 if (rotation
== BIT(DRM_ROTATE_180
)) {
2701 dspcntr
|= DISPPLANE_ROTATE_180
;
2703 x
+= (crtc_state
->pipe_src_w
- 1);
2704 y
+= (crtc_state
->pipe_src_h
- 1);
2706 /* Finding the last pixel of the last line of the display
2707 data and adding to linear_offset*/
2709 (crtc_state
->pipe_src_h
- 1) * fb
->pitches
[0] +
2710 (crtc_state
->pipe_src_w
- 1) * cpp
;
2713 intel_crtc
->adjusted_x
= x
;
2714 intel_crtc
->adjusted_y
= y
;
2716 I915_WRITE(reg
, dspcntr
);
2718 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2719 if (INTEL_INFO(dev
)->gen
>= 4) {
2720 I915_WRITE(DSPSURF(plane
),
2721 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2722 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2723 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2725 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2729 static void i9xx_disable_primary_plane(struct drm_plane
*primary
,
2730 struct drm_crtc
*crtc
)
2732 struct drm_device
*dev
= crtc
->dev
;
2733 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2734 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2735 int plane
= intel_crtc
->plane
;
2737 I915_WRITE(DSPCNTR(plane
), 0);
2738 if (INTEL_INFO(dev_priv
)->gen
>= 4)
2739 I915_WRITE(DSPSURF(plane
), 0);
2741 I915_WRITE(DSPADDR(plane
), 0);
2742 POSTING_READ(DSPCNTR(plane
));
2745 static void ironlake_update_primary_plane(struct drm_plane
*primary
,
2746 const struct intel_crtc_state
*crtc_state
,
2747 const struct intel_plane_state
*plane_state
)
2749 struct drm_device
*dev
= primary
->dev
;
2750 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2751 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2752 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2753 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2754 int plane
= intel_crtc
->plane
;
2757 i915_reg_t reg
= DSPCNTR(plane
);
2758 unsigned int rotation
= plane_state
->base
.rotation
;
2759 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2760 int x
= plane_state
->src
.x1
>> 16;
2761 int y
= plane_state
->src
.y1
>> 16;
2763 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2764 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2766 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2767 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2769 switch (fb
->pixel_format
) {
2771 dspcntr
|= DISPPLANE_8BPP
;
2773 case DRM_FORMAT_RGB565
:
2774 dspcntr
|= DISPPLANE_BGRX565
;
2776 case DRM_FORMAT_XRGB8888
:
2777 dspcntr
|= DISPPLANE_BGRX888
;
2779 case DRM_FORMAT_XBGR8888
:
2780 dspcntr
|= DISPPLANE_RGBX888
;
2782 case DRM_FORMAT_XRGB2101010
:
2783 dspcntr
|= DISPPLANE_BGRX101010
;
2785 case DRM_FORMAT_XBGR2101010
:
2786 dspcntr
|= DISPPLANE_RGBX101010
;
2792 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2793 dspcntr
|= DISPPLANE_TILED
;
2795 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2796 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2798 linear_offset
= y
* fb
->pitches
[0] + x
* cpp
;
2799 intel_crtc
->dspaddr_offset
=
2800 intel_compute_tile_offset(&x
, &y
, fb
, 0,
2801 fb
->pitches
[0], rotation
);
2802 linear_offset
-= intel_crtc
->dspaddr_offset
;
2803 if (rotation
== BIT(DRM_ROTATE_180
)) {
2804 dspcntr
|= DISPPLANE_ROTATE_180
;
2806 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2807 x
+= (crtc_state
->pipe_src_w
- 1);
2808 y
+= (crtc_state
->pipe_src_h
- 1);
2810 /* Finding the last pixel of the last line of the display
2811 data and adding to linear_offset*/
2813 (crtc_state
->pipe_src_h
- 1) * fb
->pitches
[0] +
2814 (crtc_state
->pipe_src_w
- 1) * cpp
;
2818 intel_crtc
->adjusted_x
= x
;
2819 intel_crtc
->adjusted_y
= y
;
2821 I915_WRITE(reg
, dspcntr
);
2823 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2824 I915_WRITE(DSPSURF(plane
),
2825 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2826 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2827 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2829 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2830 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2835 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
2836 uint64_t fb_modifier
, uint32_t pixel_format
)
2838 if (fb_modifier
== DRM_FORMAT_MOD_NONE
) {
2841 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2843 return intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2847 u32
intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2848 struct drm_i915_gem_object
*obj
,
2851 struct i915_ggtt_view view
;
2852 struct i915_vma
*vma
;
2855 intel_fill_fb_ggtt_view(&view
, intel_plane
->base
.state
->fb
,
2856 intel_plane
->base
.state
->rotation
);
2858 vma
= i915_gem_obj_to_ggtt_view(obj
, &view
);
2859 if (WARN(!vma
, "ggtt vma for display object not found! (view=%u)\n",
2863 offset
= vma
->node
.start
;
2866 offset
+= vma
->ggtt_view
.params
.rotated
.uv_start_page
*
2870 WARN_ON(upper_32_bits(offset
));
2872 return lower_32_bits(offset
);
2875 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
2877 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2878 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2880 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
2881 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
2882 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
2886 * This function detaches (aka. unbinds) unused scalers in hardware
2888 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2890 struct intel_crtc_scaler_state
*scaler_state
;
2893 scaler_state
= &intel_crtc
->config
->scaler_state
;
2895 /* loop through and disable scalers that aren't in use */
2896 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2897 if (!scaler_state
->scalers
[i
].in_use
)
2898 skl_detach_scaler(intel_crtc
, i
);
2902 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2904 switch (pixel_format
) {
2906 return PLANE_CTL_FORMAT_INDEXED
;
2907 case DRM_FORMAT_RGB565
:
2908 return PLANE_CTL_FORMAT_RGB_565
;
2909 case DRM_FORMAT_XBGR8888
:
2910 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2911 case DRM_FORMAT_XRGB8888
:
2912 return PLANE_CTL_FORMAT_XRGB_8888
;
2914 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2915 * to be already pre-multiplied. We need to add a knob (or a different
2916 * DRM_FORMAT) for user-space to configure that.
2918 case DRM_FORMAT_ABGR8888
:
2919 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2920 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2921 case DRM_FORMAT_ARGB8888
:
2922 return PLANE_CTL_FORMAT_XRGB_8888
|
2923 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2924 case DRM_FORMAT_XRGB2101010
:
2925 return PLANE_CTL_FORMAT_XRGB_2101010
;
2926 case DRM_FORMAT_XBGR2101010
:
2927 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2928 case DRM_FORMAT_YUYV
:
2929 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2930 case DRM_FORMAT_YVYU
:
2931 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2932 case DRM_FORMAT_UYVY
:
2933 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2934 case DRM_FORMAT_VYUY
:
2935 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2937 MISSING_CASE(pixel_format
);
2943 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2945 switch (fb_modifier
) {
2946 case DRM_FORMAT_MOD_NONE
:
2948 case I915_FORMAT_MOD_X_TILED
:
2949 return PLANE_CTL_TILED_X
;
2950 case I915_FORMAT_MOD_Y_TILED
:
2951 return PLANE_CTL_TILED_Y
;
2952 case I915_FORMAT_MOD_Yf_TILED
:
2953 return PLANE_CTL_TILED_YF
;
2955 MISSING_CASE(fb_modifier
);
2961 u32
skl_plane_ctl_rotation(unsigned int rotation
)
2964 case BIT(DRM_ROTATE_0
):
2967 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2968 * while i915 HW rotation is clockwise, thats why this swapping.
2970 case BIT(DRM_ROTATE_90
):
2971 return PLANE_CTL_ROTATE_270
;
2972 case BIT(DRM_ROTATE_180
):
2973 return PLANE_CTL_ROTATE_180
;
2974 case BIT(DRM_ROTATE_270
):
2975 return PLANE_CTL_ROTATE_90
;
2977 MISSING_CASE(rotation
);
2983 static void skylake_update_primary_plane(struct drm_plane
*plane
,
2984 const struct intel_crtc_state
*crtc_state
,
2985 const struct intel_plane_state
*plane_state
)
2987 struct drm_device
*dev
= plane
->dev
;
2988 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2989 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
2990 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2991 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2992 int pipe
= intel_crtc
->pipe
;
2993 u32 plane_ctl
, stride_div
, stride
;
2994 u32 tile_height
, plane_offset
, plane_size
;
2995 unsigned int rotation
= plane_state
->base
.rotation
;
2996 int x_offset
, y_offset
;
2998 int scaler_id
= plane_state
->scaler_id
;
2999 int src_x
= plane_state
->src
.x1
>> 16;
3000 int src_y
= plane_state
->src
.y1
>> 16;
3001 int src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3002 int src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3003 int dst_x
= plane_state
->dst
.x1
;
3004 int dst_y
= plane_state
->dst
.y1
;
3005 int dst_w
= drm_rect_width(&plane_state
->dst
);
3006 int dst_h
= drm_rect_height(&plane_state
->dst
);
3008 plane_ctl
= PLANE_CTL_ENABLE
|
3009 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3010 PLANE_CTL_PIPE_CSC_ENABLE
;
3012 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3013 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3014 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3015 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3017 stride_div
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
3019 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
, 0);
3021 WARN_ON(drm_rect_width(&plane_state
->src
) == 0);
3023 if (intel_rotation_90_or_270(rotation
)) {
3024 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3026 /* stride = Surface height in tiles */
3027 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], cpp
);
3028 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3029 x_offset
= stride
* tile_height
- src_y
- src_h
;
3031 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3033 stride
= fb
->pitches
[0] / stride_div
;
3036 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3038 plane_offset
= y_offset
<< 16 | x_offset
;
3040 intel_crtc
->adjusted_x
= x_offset
;
3041 intel_crtc
->adjusted_y
= y_offset
;
3043 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3044 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3045 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3046 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3048 if (scaler_id
>= 0) {
3049 uint32_t ps_ctrl
= 0;
3051 WARN_ON(!dst_w
|| !dst_h
);
3052 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3053 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3054 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3055 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3056 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3057 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3058 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3060 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3063 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3065 POSTING_READ(PLANE_SURF(pipe
, 0));
3068 static void skylake_disable_primary_plane(struct drm_plane
*primary
,
3069 struct drm_crtc
*crtc
)
3071 struct drm_device
*dev
= crtc
->dev
;
3072 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3073 int pipe
= to_intel_crtc(crtc
)->pipe
;
3075 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3076 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3077 POSTING_READ(PLANE_SURF(pipe
, 0));
3080 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3082 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3083 int x
, int y
, enum mode_set_atomic state
)
3085 /* Support for kgdboc is disabled, this needs a major rework. */
3086 DRM_ERROR("legacy panic handler not supported any more.\n");
3091 static void intel_complete_page_flips(struct drm_i915_private
*dev_priv
)
3093 struct intel_crtc
*crtc
;
3095 for_each_intel_crtc(&dev_priv
->drm
, crtc
)
3096 intel_finish_page_flip_cs(dev_priv
, crtc
->pipe
);
3099 static void intel_update_primary_planes(struct drm_device
*dev
)
3101 struct drm_crtc
*crtc
;
3103 for_each_crtc(dev
, crtc
) {
3104 struct intel_plane
*plane
= to_intel_plane(crtc
->primary
);
3105 struct intel_plane_state
*plane_state
;
3107 drm_modeset_lock_crtc(crtc
, &plane
->base
);
3108 plane_state
= to_intel_plane_state(plane
->base
.state
);
3110 if (plane_state
->visible
)
3111 plane
->update_plane(&plane
->base
,
3112 to_intel_crtc_state(crtc
->state
),
3115 drm_modeset_unlock_crtc(crtc
);
3119 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
3121 /* no reset support for gen2 */
3122 if (IS_GEN2(dev_priv
))
3125 /* reset doesn't touch the display */
3126 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
3129 drm_modeset_lock_all(&dev_priv
->drm
);
3131 * Disabling the crtcs gracefully seems nicer. Also the
3132 * g33 docs say we should at least disable all the planes.
3134 intel_display_suspend(&dev_priv
->drm
);
3137 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
3140 * Flips in the rings will be nuked by the reset,
3141 * so complete all pending flips so that user space
3142 * will get its events and not get stuck.
3144 intel_complete_page_flips(dev_priv
);
3146 /* no reset support for gen2 */
3147 if (IS_GEN2(dev_priv
))
3150 /* reset doesn't touch the display */
3151 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
)) {
3153 * Flips in the rings have been nuked by the reset,
3154 * so update the base address of all primary
3155 * planes to the the last fb to make sure we're
3156 * showing the correct fb after a reset.
3158 * FIXME: Atomic will make this obsolete since we won't schedule
3159 * CS-based flips (which might get lost in gpu resets) any more.
3161 intel_update_primary_planes(&dev_priv
->drm
);
3166 * The display has been reset as well,
3167 * so need a full re-initialization.
3169 intel_runtime_pm_disable_interrupts(dev_priv
);
3170 intel_runtime_pm_enable_interrupts(dev_priv
);
3172 intel_modeset_init_hw(&dev_priv
->drm
);
3174 spin_lock_irq(&dev_priv
->irq_lock
);
3175 if (dev_priv
->display
.hpd_irq_setup
)
3176 dev_priv
->display
.hpd_irq_setup(dev_priv
);
3177 spin_unlock_irq(&dev_priv
->irq_lock
);
3179 intel_display_resume(&dev_priv
->drm
);
3181 intel_hpd_init(dev_priv
);
3183 drm_modeset_unlock_all(&dev_priv
->drm
);
3186 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3188 struct drm_device
*dev
= crtc
->dev
;
3189 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3190 unsigned reset_counter
;
3193 reset_counter
= i915_reset_counter(&to_i915(dev
)->gpu_error
);
3194 if (intel_crtc
->reset_counter
!= reset_counter
)
3197 spin_lock_irq(&dev
->event_lock
);
3198 pending
= to_intel_crtc(crtc
)->flip_work
!= NULL
;
3199 spin_unlock_irq(&dev
->event_lock
);
3204 static void intel_update_pipe_config(struct intel_crtc
*crtc
,
3205 struct intel_crtc_state
*old_crtc_state
)
3207 struct drm_device
*dev
= crtc
->base
.dev
;
3208 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3209 struct intel_crtc_state
*pipe_config
=
3210 to_intel_crtc_state(crtc
->base
.state
);
3212 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3213 crtc
->base
.mode
= crtc
->base
.state
->mode
;
3215 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3216 old_crtc_state
->pipe_src_w
, old_crtc_state
->pipe_src_h
,
3217 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
3220 * Update pipe size and adjust fitter if needed: the reason for this is
3221 * that in compute_mode_changes we check the native mode (not the pfit
3222 * mode) to see if we can flip rather than do a full mode set. In the
3223 * fastboot case, we'll flip, but if we don't update the pipesrc and
3224 * pfit state, we'll end up with a big fb scanned out into the wrong
3228 I915_WRITE(PIPESRC(crtc
->pipe
),
3229 ((pipe_config
->pipe_src_w
- 1) << 16) |
3230 (pipe_config
->pipe_src_h
- 1));
3232 /* on skylake this is done by detaching scalers */
3233 if (INTEL_INFO(dev
)->gen
>= 9) {
3234 skl_detach_scalers(crtc
);
3236 if (pipe_config
->pch_pfit
.enabled
)
3237 skylake_pfit_enable(crtc
);
3238 } else if (HAS_PCH_SPLIT(dev
)) {
3239 if (pipe_config
->pch_pfit
.enabled
)
3240 ironlake_pfit_enable(crtc
);
3241 else if (old_crtc_state
->pch_pfit
.enabled
)
3242 ironlake_pfit_disable(crtc
, true);
3246 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3248 struct drm_device
*dev
= crtc
->dev
;
3249 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3250 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3251 int pipe
= intel_crtc
->pipe
;
3255 /* enable normal train */
3256 reg
= FDI_TX_CTL(pipe
);
3257 temp
= I915_READ(reg
);
3258 if (IS_IVYBRIDGE(dev
)) {
3259 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3260 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3262 temp
&= ~FDI_LINK_TRAIN_NONE
;
3263 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3265 I915_WRITE(reg
, temp
);
3267 reg
= FDI_RX_CTL(pipe
);
3268 temp
= I915_READ(reg
);
3269 if (HAS_PCH_CPT(dev
)) {
3270 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3271 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3273 temp
&= ~FDI_LINK_TRAIN_NONE
;
3274 temp
|= FDI_LINK_TRAIN_NONE
;
3276 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3278 /* wait one idle pattern time */
3282 /* IVB wants error correction enabled */
3283 if (IS_IVYBRIDGE(dev
))
3284 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3285 FDI_FE_ERRC_ENABLE
);
3288 /* The FDI link training functions for ILK/Ibexpeak. */
3289 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3291 struct drm_device
*dev
= crtc
->dev
;
3292 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3293 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3294 int pipe
= intel_crtc
->pipe
;
3298 /* FDI needs bits from pipe first */
3299 assert_pipe_enabled(dev_priv
, pipe
);
3301 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3303 reg
= FDI_RX_IMR(pipe
);
3304 temp
= I915_READ(reg
);
3305 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3306 temp
&= ~FDI_RX_BIT_LOCK
;
3307 I915_WRITE(reg
, temp
);
3311 /* enable CPU FDI TX and PCH FDI RX */
3312 reg
= FDI_TX_CTL(pipe
);
3313 temp
= I915_READ(reg
);
3314 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3315 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3316 temp
&= ~FDI_LINK_TRAIN_NONE
;
3317 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3318 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3320 reg
= FDI_RX_CTL(pipe
);
3321 temp
= I915_READ(reg
);
3322 temp
&= ~FDI_LINK_TRAIN_NONE
;
3323 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3324 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3329 /* Ironlake workaround, enable clock pointer after FDI enable*/
3330 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3331 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3332 FDI_RX_PHASE_SYNC_POINTER_EN
);
3334 reg
= FDI_RX_IIR(pipe
);
3335 for (tries
= 0; tries
< 5; tries
++) {
3336 temp
= I915_READ(reg
);
3337 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3339 if ((temp
& FDI_RX_BIT_LOCK
)) {
3340 DRM_DEBUG_KMS("FDI train 1 done.\n");
3341 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3346 DRM_ERROR("FDI train 1 fail!\n");
3349 reg
= FDI_TX_CTL(pipe
);
3350 temp
= I915_READ(reg
);
3351 temp
&= ~FDI_LINK_TRAIN_NONE
;
3352 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3353 I915_WRITE(reg
, temp
);
3355 reg
= FDI_RX_CTL(pipe
);
3356 temp
= I915_READ(reg
);
3357 temp
&= ~FDI_LINK_TRAIN_NONE
;
3358 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3359 I915_WRITE(reg
, temp
);
3364 reg
= FDI_RX_IIR(pipe
);
3365 for (tries
= 0; tries
< 5; tries
++) {
3366 temp
= I915_READ(reg
);
3367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3369 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3370 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3371 DRM_DEBUG_KMS("FDI train 2 done.\n");
3376 DRM_ERROR("FDI train 2 fail!\n");
3378 DRM_DEBUG_KMS("FDI train done\n");
3382 static const int snb_b_fdi_train_param
[] = {
3383 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3384 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3385 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3386 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3389 /* The FDI link training functions for SNB/Cougarpoint. */
3390 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3392 struct drm_device
*dev
= crtc
->dev
;
3393 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3394 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3395 int pipe
= intel_crtc
->pipe
;
3399 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3401 reg
= FDI_RX_IMR(pipe
);
3402 temp
= I915_READ(reg
);
3403 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3404 temp
&= ~FDI_RX_BIT_LOCK
;
3405 I915_WRITE(reg
, temp
);
3410 /* enable CPU FDI TX and PCH FDI RX */
3411 reg
= FDI_TX_CTL(pipe
);
3412 temp
= I915_READ(reg
);
3413 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3414 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3415 temp
&= ~FDI_LINK_TRAIN_NONE
;
3416 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3417 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3419 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3420 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3422 I915_WRITE(FDI_RX_MISC(pipe
),
3423 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3425 reg
= FDI_RX_CTL(pipe
);
3426 temp
= I915_READ(reg
);
3427 if (HAS_PCH_CPT(dev
)) {
3428 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3429 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3431 temp
&= ~FDI_LINK_TRAIN_NONE
;
3432 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3434 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3439 for (i
= 0; i
< 4; i
++) {
3440 reg
= FDI_TX_CTL(pipe
);
3441 temp
= I915_READ(reg
);
3442 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3443 temp
|= snb_b_fdi_train_param
[i
];
3444 I915_WRITE(reg
, temp
);
3449 for (retry
= 0; retry
< 5; retry
++) {
3450 reg
= FDI_RX_IIR(pipe
);
3451 temp
= I915_READ(reg
);
3452 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3453 if (temp
& FDI_RX_BIT_LOCK
) {
3454 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3455 DRM_DEBUG_KMS("FDI train 1 done.\n");
3464 DRM_ERROR("FDI train 1 fail!\n");
3467 reg
= FDI_TX_CTL(pipe
);
3468 temp
= I915_READ(reg
);
3469 temp
&= ~FDI_LINK_TRAIN_NONE
;
3470 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3472 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3474 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3476 I915_WRITE(reg
, temp
);
3478 reg
= FDI_RX_CTL(pipe
);
3479 temp
= I915_READ(reg
);
3480 if (HAS_PCH_CPT(dev
)) {
3481 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3482 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3484 temp
&= ~FDI_LINK_TRAIN_NONE
;
3485 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3487 I915_WRITE(reg
, temp
);
3492 for (i
= 0; i
< 4; i
++) {
3493 reg
= FDI_TX_CTL(pipe
);
3494 temp
= I915_READ(reg
);
3495 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3496 temp
|= snb_b_fdi_train_param
[i
];
3497 I915_WRITE(reg
, temp
);
3502 for (retry
= 0; retry
< 5; retry
++) {
3503 reg
= FDI_RX_IIR(pipe
);
3504 temp
= I915_READ(reg
);
3505 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3506 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3507 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3508 DRM_DEBUG_KMS("FDI train 2 done.\n");
3517 DRM_ERROR("FDI train 2 fail!\n");
3519 DRM_DEBUG_KMS("FDI train done.\n");
3522 /* Manual link training for Ivy Bridge A0 parts */
3523 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3525 struct drm_device
*dev
= crtc
->dev
;
3526 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3527 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3528 int pipe
= intel_crtc
->pipe
;
3532 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3534 reg
= FDI_RX_IMR(pipe
);
3535 temp
= I915_READ(reg
);
3536 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3537 temp
&= ~FDI_RX_BIT_LOCK
;
3538 I915_WRITE(reg
, temp
);
3543 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3544 I915_READ(FDI_RX_IIR(pipe
)));
3546 /* Try each vswing and preemphasis setting twice before moving on */
3547 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3548 /* disable first in case we need to retry */
3549 reg
= FDI_TX_CTL(pipe
);
3550 temp
= I915_READ(reg
);
3551 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3552 temp
&= ~FDI_TX_ENABLE
;
3553 I915_WRITE(reg
, temp
);
3555 reg
= FDI_RX_CTL(pipe
);
3556 temp
= I915_READ(reg
);
3557 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3558 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3559 temp
&= ~FDI_RX_ENABLE
;
3560 I915_WRITE(reg
, temp
);
3562 /* enable CPU FDI TX and PCH FDI RX */
3563 reg
= FDI_TX_CTL(pipe
);
3564 temp
= I915_READ(reg
);
3565 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3566 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3567 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3568 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3569 temp
|= snb_b_fdi_train_param
[j
/2];
3570 temp
|= FDI_COMPOSITE_SYNC
;
3571 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3573 I915_WRITE(FDI_RX_MISC(pipe
),
3574 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3576 reg
= FDI_RX_CTL(pipe
);
3577 temp
= I915_READ(reg
);
3578 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3579 temp
|= FDI_COMPOSITE_SYNC
;
3580 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3583 udelay(1); /* should be 0.5us */
3585 for (i
= 0; i
< 4; i
++) {
3586 reg
= FDI_RX_IIR(pipe
);
3587 temp
= I915_READ(reg
);
3588 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3590 if (temp
& FDI_RX_BIT_LOCK
||
3591 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3592 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3593 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3597 udelay(1); /* should be 0.5us */
3600 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3605 reg
= FDI_TX_CTL(pipe
);
3606 temp
= I915_READ(reg
);
3607 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3608 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3609 I915_WRITE(reg
, temp
);
3611 reg
= FDI_RX_CTL(pipe
);
3612 temp
= I915_READ(reg
);
3613 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3614 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3615 I915_WRITE(reg
, temp
);
3618 udelay(2); /* should be 1.5us */
3620 for (i
= 0; i
< 4; i
++) {
3621 reg
= FDI_RX_IIR(pipe
);
3622 temp
= I915_READ(reg
);
3623 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3625 if (temp
& FDI_RX_SYMBOL_LOCK
||
3626 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3627 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3628 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3632 udelay(2); /* should be 1.5us */
3635 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3639 DRM_DEBUG_KMS("FDI train done.\n");
3642 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3644 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3645 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3646 int pipe
= intel_crtc
->pipe
;
3650 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3651 reg
= FDI_RX_CTL(pipe
);
3652 temp
= I915_READ(reg
);
3653 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3654 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3655 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3656 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3661 /* Switch from Rawclk to PCDclk */
3662 temp
= I915_READ(reg
);
3663 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3668 /* Enable CPU FDI TX PLL, always on for Ironlake */
3669 reg
= FDI_TX_CTL(pipe
);
3670 temp
= I915_READ(reg
);
3671 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3672 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3679 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3681 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3682 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3683 int pipe
= intel_crtc
->pipe
;
3687 /* Switch from PCDclk to Rawclk */
3688 reg
= FDI_RX_CTL(pipe
);
3689 temp
= I915_READ(reg
);
3690 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3692 /* Disable CPU FDI TX PLL */
3693 reg
= FDI_TX_CTL(pipe
);
3694 temp
= I915_READ(reg
);
3695 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3700 reg
= FDI_RX_CTL(pipe
);
3701 temp
= I915_READ(reg
);
3702 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3704 /* Wait for the clocks to turn off. */
3709 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3711 struct drm_device
*dev
= crtc
->dev
;
3712 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3713 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3714 int pipe
= intel_crtc
->pipe
;
3718 /* disable CPU FDI tx and PCH FDI rx */
3719 reg
= FDI_TX_CTL(pipe
);
3720 temp
= I915_READ(reg
);
3721 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3724 reg
= FDI_RX_CTL(pipe
);
3725 temp
= I915_READ(reg
);
3726 temp
&= ~(0x7 << 16);
3727 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3728 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3733 /* Ironlake workaround, disable clock pointer after downing FDI */
3734 if (HAS_PCH_IBX(dev
))
3735 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3737 /* still set train pattern 1 */
3738 reg
= FDI_TX_CTL(pipe
);
3739 temp
= I915_READ(reg
);
3740 temp
&= ~FDI_LINK_TRAIN_NONE
;
3741 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3742 I915_WRITE(reg
, temp
);
3744 reg
= FDI_RX_CTL(pipe
);
3745 temp
= I915_READ(reg
);
3746 if (HAS_PCH_CPT(dev
)) {
3747 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3748 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3750 temp
&= ~FDI_LINK_TRAIN_NONE
;
3751 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3753 /* BPC in FDI rx is consistent with that in PIPECONF */
3754 temp
&= ~(0x07 << 16);
3755 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3756 I915_WRITE(reg
, temp
);
3762 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3764 struct intel_crtc
*crtc
;
3766 /* Note that we don't need to be called with mode_config.lock here
3767 * as our list of CRTC objects is static for the lifetime of the
3768 * device and so cannot disappear as we iterate. Similarly, we can
3769 * happily treat the predicates as racy, atomic checks as userspace
3770 * cannot claim and pin a new fb without at least acquring the
3771 * struct_mutex and so serialising with us.
3773 for_each_intel_crtc(dev
, crtc
) {
3774 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3777 if (crtc
->flip_work
)
3778 intel_wait_for_vblank(dev
, crtc
->pipe
);
3786 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3788 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3789 struct intel_flip_work
*work
= intel_crtc
->flip_work
;
3791 intel_crtc
->flip_work
= NULL
;
3794 drm_crtc_send_vblank_event(&intel_crtc
->base
, work
->event
);
3796 drm_crtc_vblank_put(&intel_crtc
->base
);
3798 wake_up_all(&dev_priv
->pending_flip_queue
);
3799 queue_work(dev_priv
->wq
, &work
->unpin_work
);
3801 trace_i915_flip_complete(intel_crtc
->plane
,
3802 work
->pending_flip_obj
);
3805 static int intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3807 struct drm_device
*dev
= crtc
->dev
;
3808 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3811 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3813 ret
= wait_event_interruptible_timeout(
3814 dev_priv
->pending_flip_queue
,
3815 !intel_crtc_has_pending_flip(crtc
),
3822 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3823 struct intel_flip_work
*work
;
3825 spin_lock_irq(&dev
->event_lock
);
3826 work
= intel_crtc
->flip_work
;
3827 if (work
&& !is_mmio_work(work
)) {
3828 WARN_ONCE(1, "Removing stuck page flip\n");
3829 page_flip_completed(intel_crtc
);
3831 spin_unlock_irq(&dev
->event_lock
);
3837 static void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
3841 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3843 mutex_lock(&dev_priv
->sb_lock
);
3845 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3846 temp
|= SBI_SSCCTL_DISABLE
;
3847 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3849 mutex_unlock(&dev_priv
->sb_lock
);
3852 /* Program iCLKIP clock to the desired frequency */
3853 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3855 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
3856 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3857 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3860 lpt_disable_iclkip(dev_priv
);
3862 /* The iCLK virtual clock root frequency is in MHz,
3863 * but the adjusted_mode->crtc_clock in in KHz. To get the
3864 * divisors, it is necessary to divide one by another, so we
3865 * convert the virtual clock precision to KHz here for higher
3868 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
3869 u32 iclk_virtual_root_freq
= 172800 * 1000;
3870 u32 iclk_pi_range
= 64;
3871 u32 desired_divisor
;
3873 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
3875 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
3876 phaseinc
= desired_divisor
% iclk_pi_range
;
3879 * Near 20MHz is a corner case which is
3880 * out of range for the 7-bit divisor
3886 /* This should not happen with any sane values */
3887 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3888 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3889 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3890 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3892 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3899 mutex_lock(&dev_priv
->sb_lock
);
3901 /* Program SSCDIVINTPHASE6 */
3902 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3903 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3904 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3905 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3906 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3907 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3908 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3909 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3911 /* Program SSCAUXDIV */
3912 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3913 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3914 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3915 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3917 /* Enable modulator and associated divider */
3918 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3919 temp
&= ~SBI_SSCCTL_DISABLE
;
3920 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3922 mutex_unlock(&dev_priv
->sb_lock
);
3924 /* Wait for initialization time */
3927 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3930 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
3932 u32 divsel
, phaseinc
, auxdiv
;
3933 u32 iclk_virtual_root_freq
= 172800 * 1000;
3934 u32 iclk_pi_range
= 64;
3935 u32 desired_divisor
;
3938 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
3941 mutex_lock(&dev_priv
->sb_lock
);
3943 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3944 if (temp
& SBI_SSCCTL_DISABLE
) {
3945 mutex_unlock(&dev_priv
->sb_lock
);
3949 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3950 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
3951 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
3952 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
3953 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
3955 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3956 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
3957 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
3959 mutex_unlock(&dev_priv
->sb_lock
);
3961 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
3963 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
3964 desired_divisor
<< auxdiv
);
3967 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3968 enum pipe pch_transcoder
)
3970 struct drm_device
*dev
= crtc
->base
.dev
;
3971 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3972 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
3974 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3975 I915_READ(HTOTAL(cpu_transcoder
)));
3976 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3977 I915_READ(HBLANK(cpu_transcoder
)));
3978 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3979 I915_READ(HSYNC(cpu_transcoder
)));
3981 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3982 I915_READ(VTOTAL(cpu_transcoder
)));
3983 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3984 I915_READ(VBLANK(cpu_transcoder
)));
3985 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3986 I915_READ(VSYNC(cpu_transcoder
)));
3987 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3988 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3991 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
3993 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3996 temp
= I915_READ(SOUTH_CHICKEN1
);
3997 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4000 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4001 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4003 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4005 temp
|= FDI_BC_BIFURCATION_SELECT
;
4007 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4008 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4009 POSTING_READ(SOUTH_CHICKEN1
);
4012 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4014 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4016 switch (intel_crtc
->pipe
) {
4020 if (intel_crtc
->config
->fdi_lanes
> 2)
4021 cpt_set_fdi_bc_bifurcation(dev
, false);
4023 cpt_set_fdi_bc_bifurcation(dev
, true);
4027 cpt_set_fdi_bc_bifurcation(dev
, true);
4035 /* Return which DP Port should be selected for Transcoder DP control */
4037 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4039 struct drm_device
*dev
= crtc
->dev
;
4040 struct intel_encoder
*encoder
;
4042 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4043 if (encoder
->type
== INTEL_OUTPUT_DP
||
4044 encoder
->type
== INTEL_OUTPUT_EDP
)
4045 return enc_to_dig_port(&encoder
->base
)->port
;
4052 * Enable PCH resources required for PCH ports:
4054 * - FDI training & RX/TX
4055 * - update transcoder timings
4056 * - DP transcoding bits
4059 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4061 struct drm_device
*dev
= crtc
->dev
;
4062 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4063 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4064 int pipe
= intel_crtc
->pipe
;
4067 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4069 if (IS_IVYBRIDGE(dev
))
4070 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4072 /* Write the TU size bits before fdi link training, so that error
4073 * detection works. */
4074 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4075 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4077 /* For PCH output, training FDI link */
4078 dev_priv
->display
.fdi_link_train(crtc
);
4080 /* We need to program the right clock selection before writing the pixel
4081 * mutliplier into the DPLL. */
4082 if (HAS_PCH_CPT(dev
)) {
4085 temp
= I915_READ(PCH_DPLL_SEL
);
4086 temp
|= TRANS_DPLL_ENABLE(pipe
);
4087 sel
= TRANS_DPLLB_SEL(pipe
);
4088 if (intel_crtc
->config
->shared_dpll
==
4089 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4093 I915_WRITE(PCH_DPLL_SEL
, temp
);
4096 /* XXX: pch pll's can be enabled any time before we enable the PCH
4097 * transcoder, and we actually should do this to not upset any PCH
4098 * transcoder that already use the clock when we share it.
4100 * Note that enable_shared_dpll tries to do the right thing, but
4101 * get_shared_dpll unconditionally resets the pll - we need that to have
4102 * the right LVDS enable sequence. */
4103 intel_enable_shared_dpll(intel_crtc
);
4105 /* set transcoder timing, panel must allow it */
4106 assert_panel_unlocked(dev_priv
, pipe
);
4107 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4109 intel_fdi_normal_train(crtc
);
4111 /* For PCH DP, enable TRANS_DP_CTL */
4112 if (HAS_PCH_CPT(dev
) && intel_crtc_has_dp_encoder(intel_crtc
->config
)) {
4113 const struct drm_display_mode
*adjusted_mode
=
4114 &intel_crtc
->config
->base
.adjusted_mode
;
4115 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4116 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4117 temp
= I915_READ(reg
);
4118 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4119 TRANS_DP_SYNC_MASK
|
4121 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4122 temp
|= bpc
<< 9; /* same format but at 11:9 */
4124 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4125 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4126 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4127 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4129 switch (intel_trans_dp_port_sel(crtc
)) {
4131 temp
|= TRANS_DP_PORT_SEL_B
;
4134 temp
|= TRANS_DP_PORT_SEL_C
;
4137 temp
|= TRANS_DP_PORT_SEL_D
;
4143 I915_WRITE(reg
, temp
);
4146 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4149 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4151 struct drm_device
*dev
= crtc
->dev
;
4152 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4153 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4154 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4156 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4158 lpt_program_iclkip(crtc
);
4160 /* Set transcoder timing. */
4161 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4163 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4166 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4168 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4169 i915_reg_t dslreg
= PIPEDSL(pipe
);
4172 temp
= I915_READ(dslreg
);
4174 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4175 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4176 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4181 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4182 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4183 int src_w
, int src_h
, int dst_w
, int dst_h
)
4185 struct intel_crtc_scaler_state
*scaler_state
=
4186 &crtc_state
->scaler_state
;
4187 struct intel_crtc
*intel_crtc
=
4188 to_intel_crtc(crtc_state
->base
.crtc
);
4191 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4192 (src_h
!= dst_w
|| src_w
!= dst_h
):
4193 (src_w
!= dst_w
|| src_h
!= dst_h
);
4196 * if plane is being disabled or scaler is no more required or force detach
4197 * - free scaler binded to this plane/crtc
4198 * - in order to do this, update crtc->scaler_usage
4200 * Here scaler state in crtc_state is set free so that
4201 * scaler can be assigned to other user. Actual register
4202 * update to free the scaler is done in plane/panel-fit programming.
4203 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4205 if (force_detach
|| !need_scaling
) {
4206 if (*scaler_id
>= 0) {
4207 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4208 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4210 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4211 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4212 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4213 scaler_state
->scaler_users
);
4220 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4221 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4223 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4224 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4225 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4226 "size is out of scaler range\n",
4227 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4231 /* mark this plane as a scaler user in crtc_state */
4232 scaler_state
->scaler_users
|= (1 << scaler_user
);
4233 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4234 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4235 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4236 scaler_state
->scaler_users
);
4242 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4244 * @state: crtc's scaler state
4247 * 0 - scaler_usage updated successfully
4248 * error - requested scaling cannot be supported or other error condition
4250 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4252 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->base
.crtc
);
4253 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4255 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4256 intel_crtc
->base
.base
.id
, intel_crtc
->base
.name
,
4257 intel_crtc
->pipe
, SKL_CRTC_INDEX
);
4259 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4260 &state
->scaler_state
.scaler_id
, BIT(DRM_ROTATE_0
),
4261 state
->pipe_src_w
, state
->pipe_src_h
,
4262 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4266 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4268 * @state: crtc's scaler state
4269 * @plane_state: atomic plane state to update
4272 * 0 - scaler_usage updated successfully
4273 * error - requested scaling cannot be supported or other error condition
4275 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4276 struct intel_plane_state
*plane_state
)
4279 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4280 struct intel_plane
*intel_plane
=
4281 to_intel_plane(plane_state
->base
.plane
);
4282 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4285 bool force_detach
= !fb
|| !plane_state
->visible
;
4287 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4288 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
4289 intel_crtc
->pipe
, drm_plane_index(&intel_plane
->base
));
4291 ret
= skl_update_scaler(crtc_state
, force_detach
,
4292 drm_plane_index(&intel_plane
->base
),
4293 &plane_state
->scaler_id
,
4294 plane_state
->base
.rotation
,
4295 drm_rect_width(&plane_state
->src
) >> 16,
4296 drm_rect_height(&plane_state
->src
) >> 16,
4297 drm_rect_width(&plane_state
->dst
),
4298 drm_rect_height(&plane_state
->dst
));
4300 if (ret
|| plane_state
->scaler_id
< 0)
4303 /* check colorkey */
4304 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4305 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4306 intel_plane
->base
.base
.id
,
4307 intel_plane
->base
.name
);
4311 /* Check src format */
4312 switch (fb
->pixel_format
) {
4313 case DRM_FORMAT_RGB565
:
4314 case DRM_FORMAT_XBGR8888
:
4315 case DRM_FORMAT_XRGB8888
:
4316 case DRM_FORMAT_ABGR8888
:
4317 case DRM_FORMAT_ARGB8888
:
4318 case DRM_FORMAT_XRGB2101010
:
4319 case DRM_FORMAT_XBGR2101010
:
4320 case DRM_FORMAT_YUYV
:
4321 case DRM_FORMAT_YVYU
:
4322 case DRM_FORMAT_UYVY
:
4323 case DRM_FORMAT_VYUY
:
4326 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4327 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
4328 fb
->base
.id
, fb
->pixel_format
);
4335 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4339 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4340 skl_detach_scaler(crtc
, i
);
4343 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4345 struct drm_device
*dev
= crtc
->base
.dev
;
4346 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4347 int pipe
= crtc
->pipe
;
4348 struct intel_crtc_scaler_state
*scaler_state
=
4349 &crtc
->config
->scaler_state
;
4351 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4353 if (crtc
->config
->pch_pfit
.enabled
) {
4356 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4357 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4361 id
= scaler_state
->scaler_id
;
4362 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4363 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4364 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4365 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4367 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4371 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4373 struct drm_device
*dev
= crtc
->base
.dev
;
4374 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4375 int pipe
= crtc
->pipe
;
4377 if (crtc
->config
->pch_pfit
.enabled
) {
4378 /* Force use of hard-coded filter coefficients
4379 * as some pre-programmed values are broken,
4382 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4383 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4384 PF_PIPE_SEL_IVB(pipe
));
4386 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4387 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4388 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4392 void hsw_enable_ips(struct intel_crtc
*crtc
)
4394 struct drm_device
*dev
= crtc
->base
.dev
;
4395 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4397 if (!crtc
->config
->ips_enabled
)
4401 * We can only enable IPS after we enable a plane and wait for a vblank
4402 * This function is called from post_plane_update, which is run after
4406 assert_plane_enabled(dev_priv
, crtc
->plane
);
4407 if (IS_BROADWELL(dev
)) {
4408 mutex_lock(&dev_priv
->rps
.hw_lock
);
4409 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4410 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4411 /* Quoting Art Runyan: "its not safe to expect any particular
4412 * value in IPS_CTL bit 31 after enabling IPS through the
4413 * mailbox." Moreover, the mailbox may return a bogus state,
4414 * so we need to just enable it and continue on.
4417 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4418 /* The bit only becomes 1 in the next vblank, so this wait here
4419 * is essentially intel_wait_for_vblank. If we don't have this
4420 * and don't wait for vblanks until the end of crtc_enable, then
4421 * the HW state readout code will complain that the expected
4422 * IPS_CTL value is not the one we read. */
4423 if (intel_wait_for_register(dev_priv
,
4424 IPS_CTL
, IPS_ENABLE
, IPS_ENABLE
,
4426 DRM_ERROR("Timed out waiting for IPS enable\n");
4430 void hsw_disable_ips(struct intel_crtc
*crtc
)
4432 struct drm_device
*dev
= crtc
->base
.dev
;
4433 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4435 if (!crtc
->config
->ips_enabled
)
4438 assert_plane_enabled(dev_priv
, crtc
->plane
);
4439 if (IS_BROADWELL(dev
)) {
4440 mutex_lock(&dev_priv
->rps
.hw_lock
);
4441 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4442 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4443 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4444 if (intel_wait_for_register(dev_priv
,
4445 IPS_CTL
, IPS_ENABLE
, 0,
4447 DRM_ERROR("Timed out waiting for IPS disable\n");
4449 I915_WRITE(IPS_CTL
, 0);
4450 POSTING_READ(IPS_CTL
);
4453 /* We need to wait for a vblank before we can disable the plane. */
4454 intel_wait_for_vblank(dev
, crtc
->pipe
);
4457 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4459 if (intel_crtc
->overlay
) {
4460 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4461 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4463 mutex_lock(&dev
->struct_mutex
);
4464 dev_priv
->mm
.interruptible
= false;
4465 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4466 dev_priv
->mm
.interruptible
= true;
4467 mutex_unlock(&dev
->struct_mutex
);
4470 /* Let userspace switch the overlay on again. In most cases userspace
4471 * has to recompute where to put it anyway.
4476 * intel_post_enable_primary - Perform operations after enabling primary plane
4477 * @crtc: the CRTC whose primary plane was just enabled
4479 * Performs potentially sleeping operations that must be done after the primary
4480 * plane is enabled, such as updating FBC and IPS. Note that this may be
4481 * called due to an explicit primary plane update, or due to an implicit
4482 * re-enable that is caused when a sprite plane is updated to no longer
4483 * completely hide the primary plane.
4486 intel_post_enable_primary(struct drm_crtc
*crtc
)
4488 struct drm_device
*dev
= crtc
->dev
;
4489 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4490 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4491 int pipe
= intel_crtc
->pipe
;
4494 * FIXME IPS should be fine as long as one plane is
4495 * enabled, but in practice it seems to have problems
4496 * when going from primary only to sprite only and vice
4499 hsw_enable_ips(intel_crtc
);
4502 * Gen2 reports pipe underruns whenever all planes are disabled.
4503 * So don't enable underrun reporting before at least some planes
4505 * FIXME: Need to fix the logic to work when we turn off all planes
4506 * but leave the pipe running.
4509 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4511 /* Underruns don't always raise interrupts, so check manually. */
4512 intel_check_cpu_fifo_underruns(dev_priv
);
4513 intel_check_pch_fifo_underruns(dev_priv
);
4516 /* FIXME move all this to pre_plane_update() with proper state tracking */
4518 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4520 struct drm_device
*dev
= crtc
->dev
;
4521 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4522 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4523 int pipe
= intel_crtc
->pipe
;
4526 * Gen2 reports pipe underruns whenever all planes are disabled.
4527 * So diasble underrun reporting before all the planes get disabled.
4528 * FIXME: Need to fix the logic to work when we turn off all planes
4529 * but leave the pipe running.
4532 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4535 * FIXME IPS should be fine as long as one plane is
4536 * enabled, but in practice it seems to have problems
4537 * when going from primary only to sprite only and vice
4540 hsw_disable_ips(intel_crtc
);
4543 /* FIXME get rid of this and use pre_plane_update */
4545 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
4547 struct drm_device
*dev
= crtc
->dev
;
4548 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4549 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4550 int pipe
= intel_crtc
->pipe
;
4552 intel_pre_disable_primary(crtc
);
4555 * Vblank time updates from the shadow to live plane control register
4556 * are blocked if the memory self-refresh mode is active at that
4557 * moment. So to make sure the plane gets truly disabled, disable
4558 * first the self-refresh mode. The self-refresh enable bit in turn
4559 * will be checked/applied by the HW only at the next frame start
4560 * event which is after the vblank start event, so we need to have a
4561 * wait-for-vblank between disabling the plane and the pipe.
4563 if (HAS_GMCH_DISPLAY(dev
)) {
4564 intel_set_memory_cxsr(dev_priv
, false);
4565 dev_priv
->wm
.vlv
.cxsr
= false;
4566 intel_wait_for_vblank(dev
, pipe
);
4570 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
4572 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
4573 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
4574 struct intel_crtc_state
*pipe_config
=
4575 to_intel_crtc_state(crtc
->base
.state
);
4576 struct drm_device
*dev
= crtc
->base
.dev
;
4577 struct drm_plane
*primary
= crtc
->base
.primary
;
4578 struct drm_plane_state
*old_pri_state
=
4579 drm_atomic_get_existing_plane_state(old_state
, primary
);
4581 intel_frontbuffer_flip(dev
, pipe_config
->fb_bits
);
4583 crtc
->wm
.cxsr_allowed
= true;
4585 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
4586 intel_update_watermarks(&crtc
->base
);
4588 if (old_pri_state
) {
4589 struct intel_plane_state
*primary_state
=
4590 to_intel_plane_state(primary
->state
);
4591 struct intel_plane_state
*old_primary_state
=
4592 to_intel_plane_state(old_pri_state
);
4594 intel_fbc_post_update(crtc
);
4596 if (primary_state
->visible
&&
4597 (needs_modeset(&pipe_config
->base
) ||
4598 !old_primary_state
->visible
))
4599 intel_post_enable_primary(&crtc
->base
);
4603 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
)
4605 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
4606 struct drm_device
*dev
= crtc
->base
.dev
;
4607 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4608 struct intel_crtc_state
*pipe_config
=
4609 to_intel_crtc_state(crtc
->base
.state
);
4610 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
4611 struct drm_plane
*primary
= crtc
->base
.primary
;
4612 struct drm_plane_state
*old_pri_state
=
4613 drm_atomic_get_existing_plane_state(old_state
, primary
);
4614 bool modeset
= needs_modeset(&pipe_config
->base
);
4616 if (old_pri_state
) {
4617 struct intel_plane_state
*primary_state
=
4618 to_intel_plane_state(primary
->state
);
4619 struct intel_plane_state
*old_primary_state
=
4620 to_intel_plane_state(old_pri_state
);
4622 intel_fbc_pre_update(crtc
, pipe_config
, primary_state
);
4624 if (old_primary_state
->visible
&&
4625 (modeset
|| !primary_state
->visible
))
4626 intel_pre_disable_primary(&crtc
->base
);
4629 if (pipe_config
->disable_cxsr
&& HAS_GMCH_DISPLAY(dev
)) {
4630 crtc
->wm
.cxsr_allowed
= false;
4633 * Vblank time updates from the shadow to live plane control register
4634 * are blocked if the memory self-refresh mode is active at that
4635 * moment. So to make sure the plane gets truly disabled, disable
4636 * first the self-refresh mode. The self-refresh enable bit in turn
4637 * will be checked/applied by the HW only at the next frame start
4638 * event which is after the vblank start event, so we need to have a
4639 * wait-for-vblank between disabling the plane and the pipe.
4641 if (old_crtc_state
->base
.active
) {
4642 intel_set_memory_cxsr(dev_priv
, false);
4643 dev_priv
->wm
.vlv
.cxsr
= false;
4644 intel_wait_for_vblank(dev
, crtc
->pipe
);
4649 * IVB workaround: must disable low power watermarks for at least
4650 * one frame before enabling scaling. LP watermarks can be re-enabled
4651 * when scaling is disabled.
4653 * WaCxSRDisabledForSpriteScaling:ivb
4655 if (pipe_config
->disable_lp_wm
) {
4656 ilk_disable_lp_wm(dev
);
4657 intel_wait_for_vblank(dev
, crtc
->pipe
);
4661 * If we're doing a modeset, we're done. No need to do any pre-vblank
4662 * watermark programming here.
4664 if (needs_modeset(&pipe_config
->base
))
4668 * For platforms that support atomic watermarks, program the
4669 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4670 * will be the intermediate values that are safe for both pre- and
4671 * post- vblank; when vblank happens, the 'active' values will be set
4672 * to the final 'target' values and we'll do this again to get the
4673 * optimal watermarks. For gen9+ platforms, the values we program here
4674 * will be the final target values which will get automatically latched
4675 * at vblank time; no further programming will be necessary.
4677 * If a platform hasn't been transitioned to atomic watermarks yet,
4678 * we'll continue to update watermarks the old way, if flags tell
4681 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4682 dev_priv
->display
.initial_watermarks(pipe_config
);
4683 else if (pipe_config
->update_wm_pre
)
4684 intel_update_watermarks(&crtc
->base
);
4687 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
4689 struct drm_device
*dev
= crtc
->dev
;
4690 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4691 struct drm_plane
*p
;
4692 int pipe
= intel_crtc
->pipe
;
4694 intel_crtc_dpms_overlay_disable(intel_crtc
);
4696 drm_for_each_plane_mask(p
, dev
, plane_mask
)
4697 to_intel_plane(p
)->disable_plane(p
, crtc
);
4700 * FIXME: Once we grow proper nuclear flip support out of this we need
4701 * to compute the mask of flip planes precisely. For the time being
4702 * consider this a flip to a NULL plane.
4704 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4707 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4709 struct drm_device
*dev
= crtc
->dev
;
4710 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4711 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4712 struct intel_encoder
*encoder
;
4713 int pipe
= intel_crtc
->pipe
;
4714 struct intel_crtc_state
*pipe_config
=
4715 to_intel_crtc_state(crtc
->state
);
4717 if (WARN_ON(intel_crtc
->active
))
4721 * Sometimes spurious CPU pipe underruns happen during FDI
4722 * training, at least with VGA+HDMI cloning. Suppress them.
4724 * On ILK we get an occasional spurious CPU pipe underruns
4725 * between eDP port A enable and vdd enable. Also PCH port
4726 * enable seems to result in the occasional CPU pipe underrun.
4728 * Spurious PCH underruns also occur during PCH enabling.
4730 if (intel_crtc
->config
->has_pch_encoder
|| IS_GEN5(dev_priv
))
4731 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4732 if (intel_crtc
->config
->has_pch_encoder
)
4733 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4735 if (intel_crtc
->config
->has_pch_encoder
)
4736 intel_prepare_shared_dpll(intel_crtc
);
4738 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
4739 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4741 intel_set_pipe_timings(intel_crtc
);
4742 intel_set_pipe_src_size(intel_crtc
);
4744 if (intel_crtc
->config
->has_pch_encoder
) {
4745 intel_cpu_transcoder_set_m_n(intel_crtc
,
4746 &intel_crtc
->config
->fdi_m_n
, NULL
);
4749 ironlake_set_pipeconf(crtc
);
4751 intel_crtc
->active
= true;
4753 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4754 if (encoder
->pre_enable
)
4755 encoder
->pre_enable(encoder
);
4757 if (intel_crtc
->config
->has_pch_encoder
) {
4758 /* Note: FDI PLL enabling _must_ be done before we enable the
4759 * cpu pipes, hence this is separate from all the other fdi/pch
4761 ironlake_fdi_pll_enable(intel_crtc
);
4763 assert_fdi_tx_disabled(dev_priv
, pipe
);
4764 assert_fdi_rx_disabled(dev_priv
, pipe
);
4767 ironlake_pfit_enable(intel_crtc
);
4770 * On ILK+ LUT must be loaded before the pipe is running but with
4773 intel_color_load_luts(&pipe_config
->base
);
4775 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4776 dev_priv
->display
.initial_watermarks(intel_crtc
->config
);
4777 intel_enable_pipe(intel_crtc
);
4779 if (intel_crtc
->config
->has_pch_encoder
)
4780 ironlake_pch_enable(crtc
);
4782 assert_vblank_disabled(crtc
);
4783 drm_crtc_vblank_on(crtc
);
4785 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4786 encoder
->enable(encoder
);
4788 if (HAS_PCH_CPT(dev
))
4789 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4791 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4792 if (intel_crtc
->config
->has_pch_encoder
)
4793 intel_wait_for_vblank(dev
, pipe
);
4794 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4795 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4798 /* IPS only exists on ULT machines and is tied to pipe A. */
4799 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4801 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4804 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4806 struct drm_device
*dev
= crtc
->dev
;
4807 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4808 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4809 struct intel_encoder
*encoder
;
4810 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
4811 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4812 struct intel_crtc_state
*pipe_config
=
4813 to_intel_crtc_state(crtc
->state
);
4815 if (WARN_ON(intel_crtc
->active
))
4818 if (intel_crtc
->config
->has_pch_encoder
)
4819 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4822 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4823 if (encoder
->pre_pll_enable
)
4824 encoder
->pre_pll_enable(encoder
);
4826 if (intel_crtc
->config
->shared_dpll
)
4827 intel_enable_shared_dpll(intel_crtc
);
4829 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
4830 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4832 if (!intel_crtc
->config
->has_dsi_encoder
)
4833 intel_set_pipe_timings(intel_crtc
);
4835 intel_set_pipe_src_size(intel_crtc
);
4837 if (cpu_transcoder
!= TRANSCODER_EDP
&&
4838 !transcoder_is_dsi(cpu_transcoder
)) {
4839 I915_WRITE(PIPE_MULT(cpu_transcoder
),
4840 intel_crtc
->config
->pixel_multiplier
- 1);
4843 if (intel_crtc
->config
->has_pch_encoder
) {
4844 intel_cpu_transcoder_set_m_n(intel_crtc
,
4845 &intel_crtc
->config
->fdi_m_n
, NULL
);
4848 if (!intel_crtc
->config
->has_dsi_encoder
)
4849 haswell_set_pipeconf(crtc
);
4851 haswell_set_pipemisc(crtc
);
4853 intel_color_set_csc(&pipe_config
->base
);
4855 intel_crtc
->active
= true;
4857 if (intel_crtc
->config
->has_pch_encoder
)
4858 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4860 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4862 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4863 if (encoder
->pre_enable
)
4864 encoder
->pre_enable(encoder
);
4867 if (intel_crtc
->config
->has_pch_encoder
)
4868 dev_priv
->display
.fdi_link_train(crtc
);
4870 if (!intel_crtc
->config
->has_dsi_encoder
)
4871 intel_ddi_enable_pipe_clock(intel_crtc
);
4873 if (INTEL_INFO(dev
)->gen
>= 9)
4874 skylake_pfit_enable(intel_crtc
);
4876 ironlake_pfit_enable(intel_crtc
);
4879 * On ILK+ LUT must be loaded before the pipe is running but with
4882 intel_color_load_luts(&pipe_config
->base
);
4884 intel_ddi_set_pipe_settings(crtc
);
4885 if (!intel_crtc
->config
->has_dsi_encoder
)
4886 intel_ddi_enable_transcoder_func(crtc
);
4888 if (dev_priv
->display
.initial_watermarks
!= NULL
)
4889 dev_priv
->display
.initial_watermarks(pipe_config
);
4891 intel_update_watermarks(crtc
);
4893 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4894 if (!intel_crtc
->config
->has_dsi_encoder
)
4895 intel_enable_pipe(intel_crtc
);
4897 if (intel_crtc
->config
->has_pch_encoder
)
4898 lpt_pch_enable(crtc
);
4900 if (intel_crtc
->config
->dp_encoder_is_mst
)
4901 intel_ddi_set_vc_payload_alloc(crtc
, true);
4903 assert_vblank_disabled(crtc
);
4904 drm_crtc_vblank_on(crtc
);
4906 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4907 encoder
->enable(encoder
);
4908 intel_opregion_notify_encoder(encoder
, true);
4911 if (intel_crtc
->config
->has_pch_encoder
) {
4912 intel_wait_for_vblank(dev
, pipe
);
4913 intel_wait_for_vblank(dev
, pipe
);
4914 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4915 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4919 /* If we change the relative order between pipe/planes enabling, we need
4920 * to change the workaround. */
4921 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
4922 if (IS_HASWELL(dev
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
4923 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4924 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
4928 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
4930 struct drm_device
*dev
= crtc
->base
.dev
;
4931 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4932 int pipe
= crtc
->pipe
;
4934 /* To avoid upsetting the power well on haswell only disable the pfit if
4935 * it's in use. The hw state code will make sure we get this right. */
4936 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
4937 I915_WRITE(PF_CTL(pipe
), 0);
4938 I915_WRITE(PF_WIN_POS(pipe
), 0);
4939 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4943 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4945 struct drm_device
*dev
= crtc
->dev
;
4946 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4947 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4948 struct intel_encoder
*encoder
;
4949 int pipe
= intel_crtc
->pipe
;
4952 * Sometimes spurious CPU pipe underruns happen when the
4953 * pipe is already disabled, but FDI RX/TX is still enabled.
4954 * Happens at least with VGA+HDMI cloning. Suppress them.
4956 if (intel_crtc
->config
->has_pch_encoder
) {
4957 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4958 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4961 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4962 encoder
->disable(encoder
);
4964 drm_crtc_vblank_off(crtc
);
4965 assert_vblank_disabled(crtc
);
4967 intel_disable_pipe(intel_crtc
);
4969 ironlake_pfit_disable(intel_crtc
, false);
4971 if (intel_crtc
->config
->has_pch_encoder
)
4972 ironlake_fdi_disable(crtc
);
4974 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4975 if (encoder
->post_disable
)
4976 encoder
->post_disable(encoder
);
4978 if (intel_crtc
->config
->has_pch_encoder
) {
4979 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4981 if (HAS_PCH_CPT(dev
)) {
4985 /* disable TRANS_DP_CTL */
4986 reg
= TRANS_DP_CTL(pipe
);
4987 temp
= I915_READ(reg
);
4988 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4989 TRANS_DP_PORT_SEL_MASK
);
4990 temp
|= TRANS_DP_PORT_SEL_NONE
;
4991 I915_WRITE(reg
, temp
);
4993 /* disable DPLL_SEL */
4994 temp
= I915_READ(PCH_DPLL_SEL
);
4995 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4996 I915_WRITE(PCH_DPLL_SEL
, temp
);
4999 ironlake_fdi_pll_disable(intel_crtc
);
5002 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5003 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5006 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5008 struct drm_device
*dev
= crtc
->dev
;
5009 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5011 struct intel_encoder
*encoder
;
5012 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5014 if (intel_crtc
->config
->has_pch_encoder
)
5015 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5018 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5019 intel_opregion_notify_encoder(encoder
, false);
5020 encoder
->disable(encoder
);
5023 drm_crtc_vblank_off(crtc
);
5024 assert_vblank_disabled(crtc
);
5026 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5027 if (!intel_crtc
->config
->has_dsi_encoder
)
5028 intel_disable_pipe(intel_crtc
);
5030 if (intel_crtc
->config
->dp_encoder_is_mst
)
5031 intel_ddi_set_vc_payload_alloc(crtc
, false);
5033 if (!intel_crtc
->config
->has_dsi_encoder
)
5034 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5036 if (INTEL_INFO(dev
)->gen
>= 9)
5037 skylake_scaler_disable(intel_crtc
);
5039 ironlake_pfit_disable(intel_crtc
, false);
5041 if (!intel_crtc
->config
->has_dsi_encoder
)
5042 intel_ddi_disable_pipe_clock(intel_crtc
);
5044 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5045 if (encoder
->post_disable
)
5046 encoder
->post_disable(encoder
);
5048 if (intel_crtc
->config
->has_pch_encoder
) {
5049 lpt_disable_pch_transcoder(dev_priv
);
5050 lpt_disable_iclkip(dev_priv
);
5051 intel_ddi_fdi_disable(crtc
);
5053 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5058 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5060 struct drm_device
*dev
= crtc
->base
.dev
;
5061 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5062 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5064 if (!pipe_config
->gmch_pfit
.control
)
5068 * The panel fitter should only be adjusted whilst the pipe is disabled,
5069 * according to register description and PRM.
5071 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5072 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5074 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5075 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5077 /* Border color in case we don't scale up to the full screen. Black by
5078 * default, change to something else for debugging. */
5079 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5082 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5086 return POWER_DOMAIN_PORT_DDI_A_LANES
;
5088 return POWER_DOMAIN_PORT_DDI_B_LANES
;
5090 return POWER_DOMAIN_PORT_DDI_C_LANES
;
5092 return POWER_DOMAIN_PORT_DDI_D_LANES
;
5094 return POWER_DOMAIN_PORT_DDI_E_LANES
;
5097 return POWER_DOMAIN_PORT_OTHER
;
5101 static enum intel_display_power_domain
port_to_aux_power_domain(enum port port
)
5105 return POWER_DOMAIN_AUX_A
;
5107 return POWER_DOMAIN_AUX_B
;
5109 return POWER_DOMAIN_AUX_C
;
5111 return POWER_DOMAIN_AUX_D
;
5113 /* FIXME: Check VBT for actual wiring of PORT E */
5114 return POWER_DOMAIN_AUX_D
;
5117 return POWER_DOMAIN_AUX_A
;
5121 enum intel_display_power_domain
5122 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5124 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5125 struct intel_digital_port
*intel_dig_port
;
5127 switch (intel_encoder
->type
) {
5128 case INTEL_OUTPUT_UNKNOWN
:
5129 /* Only DDI platforms should ever use this output type */
5130 WARN_ON_ONCE(!HAS_DDI(dev
));
5131 case INTEL_OUTPUT_DP
:
5132 case INTEL_OUTPUT_HDMI
:
5133 case INTEL_OUTPUT_EDP
:
5134 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5135 return port_to_power_domain(intel_dig_port
->port
);
5136 case INTEL_OUTPUT_DP_MST
:
5137 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5138 return port_to_power_domain(intel_dig_port
->port
);
5139 case INTEL_OUTPUT_ANALOG
:
5140 return POWER_DOMAIN_PORT_CRT
;
5141 case INTEL_OUTPUT_DSI
:
5142 return POWER_DOMAIN_PORT_DSI
;
5144 return POWER_DOMAIN_PORT_OTHER
;
5148 enum intel_display_power_domain
5149 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
)
5151 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5152 struct intel_digital_port
*intel_dig_port
;
5154 switch (intel_encoder
->type
) {
5155 case INTEL_OUTPUT_UNKNOWN
:
5156 case INTEL_OUTPUT_HDMI
:
5158 * Only DDI platforms should ever use these output types.
5159 * We can get here after the HDMI detect code has already set
5160 * the type of the shared encoder. Since we can't be sure
5161 * what's the status of the given connectors, play safe and
5162 * run the DP detection too.
5164 WARN_ON_ONCE(!HAS_DDI(dev
));
5165 case INTEL_OUTPUT_DP
:
5166 case INTEL_OUTPUT_EDP
:
5167 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5168 return port_to_aux_power_domain(intel_dig_port
->port
);
5169 case INTEL_OUTPUT_DP_MST
:
5170 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5171 return port_to_aux_power_domain(intel_dig_port
->port
);
5173 MISSING_CASE(intel_encoder
->type
);
5174 return POWER_DOMAIN_AUX_A
;
5178 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
,
5179 struct intel_crtc_state
*crtc_state
)
5181 struct drm_device
*dev
= crtc
->dev
;
5182 struct drm_encoder
*encoder
;
5183 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5184 enum pipe pipe
= intel_crtc
->pipe
;
5186 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
5188 if (!crtc_state
->base
.active
)
5191 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5192 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5193 if (crtc_state
->pch_pfit
.enabled
||
5194 crtc_state
->pch_pfit
.force_thru
)
5195 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5197 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
5198 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5200 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5203 if (crtc_state
->shared_dpll
)
5204 mask
|= BIT(POWER_DOMAIN_PLLS
);
5209 static unsigned long
5210 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
5211 struct intel_crtc_state
*crtc_state
)
5213 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5214 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5215 enum intel_display_power_domain domain
;
5216 unsigned long domains
, new_domains
, old_domains
;
5218 old_domains
= intel_crtc
->enabled_power_domains
;
5219 intel_crtc
->enabled_power_domains
= new_domains
=
5220 get_crtc_power_domains(crtc
, crtc_state
);
5222 domains
= new_domains
& ~old_domains
;
5224 for_each_power_domain(domain
, domains
)
5225 intel_display_power_get(dev_priv
, domain
);
5227 return old_domains
& ~new_domains
;
5230 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5231 unsigned long domains
)
5233 enum intel_display_power_domain domain
;
5235 for_each_power_domain(domain
, domains
)
5236 intel_display_power_put(dev_priv
, domain
);
5239 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
5241 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
5243 if (INTEL_INFO(dev_priv
)->gen
>= 9 ||
5244 IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5245 return max_cdclk_freq
;
5246 else if (IS_CHERRYVIEW(dev_priv
))
5247 return max_cdclk_freq
*95/100;
5248 else if (INTEL_INFO(dev_priv
)->gen
< 4)
5249 return 2*max_cdclk_freq
*90/100;
5251 return max_cdclk_freq
*90/100;
5254 static int skl_calc_cdclk(int max_pixclk
, int vco
);
5256 static void intel_update_max_cdclk(struct drm_device
*dev
)
5258 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5260 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
5261 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5264 vco
= dev_priv
->skl_preferred_vco_freq
;
5265 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
5268 * Use the lower (vco 8640) cdclk values as a
5269 * first guess. skl_calc_cdclk() will correct it
5270 * if the preferred vco is 8100 instead.
5272 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5274 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5276 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5281 dev_priv
->max_cdclk_freq
= skl_calc_cdclk(max_cdclk
, vco
);
5282 } else if (IS_BROXTON(dev
)) {
5283 dev_priv
->max_cdclk_freq
= 624000;
5284 } else if (IS_BROADWELL(dev
)) {
5286 * FIXME with extra cooling we can allow
5287 * 540 MHz for ULX and 675 Mhz for ULT.
5288 * How can we know if extra cooling is
5289 * available? PCI ID, VTB, something else?
5291 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5292 dev_priv
->max_cdclk_freq
= 450000;
5293 else if (IS_BDW_ULX(dev
))
5294 dev_priv
->max_cdclk_freq
= 450000;
5295 else if (IS_BDW_ULT(dev
))
5296 dev_priv
->max_cdclk_freq
= 540000;
5298 dev_priv
->max_cdclk_freq
= 675000;
5299 } else if (IS_CHERRYVIEW(dev
)) {
5300 dev_priv
->max_cdclk_freq
= 320000;
5301 } else if (IS_VALLEYVIEW(dev
)) {
5302 dev_priv
->max_cdclk_freq
= 400000;
5304 /* otherwise assume cdclk is fixed */
5305 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5308 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
5310 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5311 dev_priv
->max_cdclk_freq
);
5313 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5314 dev_priv
->max_dotclk_freq
);
5317 static void intel_update_cdclk(struct drm_device
*dev
)
5319 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5321 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5323 if (INTEL_GEN(dev_priv
) >= 9)
5324 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5325 dev_priv
->cdclk_freq
, dev_priv
->cdclk_pll
.vco
,
5326 dev_priv
->cdclk_pll
.ref
);
5328 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5329 dev_priv
->cdclk_freq
);
5332 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5333 * Programmng [sic] note: bit[9:2] should be programmed to the number
5334 * of cdclk that generates 4MHz reference clock freq which is used to
5335 * generate GMBus clock. This will vary with the cdclk freq.
5337 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5338 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5341 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5342 static int skl_cdclk_decimal(int cdclk
)
5344 return DIV_ROUND_CLOSEST(cdclk
- 1000, 500);
5347 static int bxt_de_pll_vco(struct drm_i915_private
*dev_priv
, int cdclk
)
5351 if (cdclk
== dev_priv
->cdclk_pll
.ref
)
5356 MISSING_CASE(cdclk
);
5368 return dev_priv
->cdclk_pll
.ref
* ratio
;
5371 static void bxt_de_pll_disable(struct drm_i915_private
*dev_priv
)
5373 I915_WRITE(BXT_DE_PLL_ENABLE
, 0);
5376 if (intel_wait_for_register(dev_priv
,
5377 BXT_DE_PLL_ENABLE
, BXT_DE_PLL_LOCK
, 0,
5379 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5381 dev_priv
->cdclk_pll
.vco
= 0;
5384 static void bxt_de_pll_enable(struct drm_i915_private
*dev_priv
, int vco
)
5386 int ratio
= DIV_ROUND_CLOSEST(vco
, dev_priv
->cdclk_pll
.ref
);
5389 val
= I915_READ(BXT_DE_PLL_CTL
);
5390 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5391 val
|= BXT_DE_PLL_RATIO(ratio
);
5392 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5394 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5397 if (intel_wait_for_register(dev_priv
,
5402 DRM_ERROR("timeout waiting for DE PLL lock\n");
5404 dev_priv
->cdclk_pll
.vco
= vco
;
5407 static void bxt_set_cdclk(struct drm_i915_private
*dev_priv
, int cdclk
)
5412 vco
= bxt_de_pll_vco(dev_priv
, cdclk
);
5414 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk
, vco
);
5416 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5417 switch (DIV_ROUND_CLOSEST(vco
, cdclk
)) {
5419 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5422 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5425 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5428 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5431 WARN_ON(cdclk
!= dev_priv
->cdclk_pll
.ref
);
5434 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5438 /* Inform power controller of upcoming frequency change */
5439 mutex_lock(&dev_priv
->rps
.hw_lock
);
5440 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5442 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5445 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5450 if (dev_priv
->cdclk_pll
.vco
!= 0 &&
5451 dev_priv
->cdclk_pll
.vco
!= vco
)
5452 bxt_de_pll_disable(dev_priv
);
5454 if (dev_priv
->cdclk_pll
.vco
!= vco
)
5455 bxt_de_pll_enable(dev_priv
, vco
);
5457 val
= divider
| skl_cdclk_decimal(cdclk
);
5459 * FIXME if only the cd2x divider needs changing, it could be done
5460 * without shutting off the pipe (if only one pipe is active).
5462 val
|= BXT_CDCLK_CD2X_PIPE_NONE
;
5464 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5467 if (cdclk
>= 500000)
5468 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5469 I915_WRITE(CDCLK_CTL
, val
);
5471 mutex_lock(&dev_priv
->rps
.hw_lock
);
5472 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5473 DIV_ROUND_UP(cdclk
, 25000));
5474 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5477 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5482 intel_update_cdclk(&dev_priv
->drm
);
5485 static void bxt_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
5487 u32 cdctl
, expected
;
5489 intel_update_cdclk(&dev_priv
->drm
);
5491 if (dev_priv
->cdclk_pll
.vco
== 0 ||
5492 dev_priv
->cdclk_freq
== dev_priv
->cdclk_pll
.ref
)
5495 /* DPLL okay; verify the cdclock
5497 * Some BIOS versions leave an incorrect decimal frequency value and
5498 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5499 * so sanitize this register.
5501 cdctl
= I915_READ(CDCLK_CTL
);
5503 * Let's ignore the pipe field, since BIOS could have configured the
5504 * dividers both synching to an active pipe, or asynchronously
5507 cdctl
&= ~BXT_CDCLK_CD2X_PIPE_NONE
;
5509 expected
= (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) |
5510 skl_cdclk_decimal(dev_priv
->cdclk_freq
);
5512 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5515 if (dev_priv
->cdclk_freq
>= 500000)
5516 expected
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5518 if (cdctl
== expected
)
5519 /* All well; nothing to sanitize */
5523 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5525 /* force cdclk programming */
5526 dev_priv
->cdclk_freq
= 0;
5528 /* force full PLL disable + enable */
5529 dev_priv
->cdclk_pll
.vco
= -1;
5532 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
)
5534 bxt_sanitize_cdclk(dev_priv
);
5536 if (dev_priv
->cdclk_freq
!= 0 && dev_priv
->cdclk_pll
.vco
!= 0)
5541 * - The initial CDCLK needs to be read from VBT.
5542 * Need to make this change after VBT has changes for BXT.
5544 bxt_set_cdclk(dev_priv
, bxt_calc_cdclk(0));
5547 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5549 bxt_set_cdclk(dev_priv
, dev_priv
->cdclk_pll
.ref
);
5552 static int skl_calc_cdclk(int max_pixclk
, int vco
)
5554 if (vco
== 8640000) {
5555 if (max_pixclk
> 540000)
5557 else if (max_pixclk
> 432000)
5559 else if (max_pixclk
> 308571)
5564 if (max_pixclk
> 540000)
5566 else if (max_pixclk
> 450000)
5568 else if (max_pixclk
> 337500)
5576 skl_dpll0_update(struct drm_i915_private
*dev_priv
)
5580 dev_priv
->cdclk_pll
.ref
= 24000;
5581 dev_priv
->cdclk_pll
.vco
= 0;
5583 val
= I915_READ(LCPLL1_CTL
);
5584 if ((val
& LCPLL_PLL_ENABLE
) == 0)
5587 if (WARN_ON((val
& LCPLL_PLL_LOCK
) == 0))
5590 val
= I915_READ(DPLL_CTRL1
);
5592 if (WARN_ON((val
& (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) |
5593 DPLL_CTRL1_SSC(SKL_DPLL0
) |
5594 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
))) !=
5595 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
)))
5598 switch (val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) {
5599 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, SKL_DPLL0
):
5600 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, SKL_DPLL0
):
5601 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
, SKL_DPLL0
):
5602 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, SKL_DPLL0
):
5603 dev_priv
->cdclk_pll
.vco
= 8100000;
5605 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
, SKL_DPLL0
):
5606 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
, SKL_DPLL0
):
5607 dev_priv
->cdclk_pll
.vco
= 8640000;
5610 MISSING_CASE(val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5615 void skl_set_preferred_cdclk_vco(struct drm_i915_private
*dev_priv
, int vco
)
5617 bool changed
= dev_priv
->skl_preferred_vco_freq
!= vco
;
5619 dev_priv
->skl_preferred_vco_freq
= vco
;
5622 intel_update_max_cdclk(&dev_priv
->drm
);
5626 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, int vco
)
5628 int min_cdclk
= skl_calc_cdclk(0, vco
);
5631 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
5633 /* select the minimum CDCLK before enabling DPLL 0 */
5634 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_cdclk
);
5635 I915_WRITE(CDCLK_CTL
, val
);
5636 POSTING_READ(CDCLK_CTL
);
5639 * We always enable DPLL0 with the lowest link rate possible, but still
5640 * taking into account the VCO required to operate the eDP panel at the
5641 * desired frequency. The usual DP link rates operate with a VCO of
5642 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5643 * The modeset code is responsible for the selection of the exact link
5644 * rate later on, with the constraint of choosing a frequency that
5647 val
= I915_READ(DPLL_CTRL1
);
5649 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5650 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5651 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5653 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5656 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5659 I915_WRITE(DPLL_CTRL1
, val
);
5660 POSTING_READ(DPLL_CTRL1
);
5662 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5664 if (intel_wait_for_register(dev_priv
,
5665 LCPLL1_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
5667 DRM_ERROR("DPLL0 not locked\n");
5669 dev_priv
->cdclk_pll
.vco
= vco
;
5671 /* We'll want to keep using the current vco from now on. */
5672 skl_set_preferred_cdclk_vco(dev_priv
, vco
);
5676 skl_dpll0_disable(struct drm_i915_private
*dev_priv
)
5678 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
5679 if (intel_wait_for_register(dev_priv
,
5680 LCPLL1_CTL
, LCPLL_PLL_LOCK
, 0,
5682 DRM_ERROR("Couldn't disable DPLL0\n");
5684 dev_priv
->cdclk_pll
.vco
= 0;
5687 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5692 /* inform PCU we want to change CDCLK */
5693 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5694 mutex_lock(&dev_priv
->rps
.hw_lock
);
5695 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5696 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5698 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5701 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5705 for (i
= 0; i
< 15; i
++) {
5706 if (skl_cdclk_pcu_ready(dev_priv
))
5714 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, int cdclk
, int vco
)
5716 struct drm_device
*dev
= &dev_priv
->drm
;
5717 u32 freq_select
, pcu_ack
;
5719 WARN_ON((cdclk
== 24000) != (vco
== 0));
5721 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk
, vco
);
5723 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5724 DRM_ERROR("failed to inform PCU about cdclk change\n");
5732 freq_select
= CDCLK_FREQ_450_432
;
5736 freq_select
= CDCLK_FREQ_540
;
5742 freq_select
= CDCLK_FREQ_337_308
;
5747 freq_select
= CDCLK_FREQ_675_617
;
5752 if (dev_priv
->cdclk_pll
.vco
!= 0 &&
5753 dev_priv
->cdclk_pll
.vco
!= vco
)
5754 skl_dpll0_disable(dev_priv
);
5756 if (dev_priv
->cdclk_pll
.vco
!= vco
)
5757 skl_dpll0_enable(dev_priv
, vco
);
5759 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(cdclk
));
5760 POSTING_READ(CDCLK_CTL
);
5762 /* inform PCU of the change */
5763 mutex_lock(&dev_priv
->rps
.hw_lock
);
5764 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5765 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5767 intel_update_cdclk(dev
);
5770 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
);
5772 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5774 skl_set_cdclk(dev_priv
, dev_priv
->cdclk_pll
.ref
, 0);
5777 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5781 skl_sanitize_cdclk(dev_priv
);
5783 if (dev_priv
->cdclk_freq
!= 0 && dev_priv
->cdclk_pll
.vco
!= 0) {
5785 * Use the current vco as our initial
5786 * guess as to what the preferred vco is.
5788 if (dev_priv
->skl_preferred_vco_freq
== 0)
5789 skl_set_preferred_cdclk_vco(dev_priv
,
5790 dev_priv
->cdclk_pll
.vco
);
5794 vco
= dev_priv
->skl_preferred_vco_freq
;
5797 cdclk
= skl_calc_cdclk(0, vco
);
5799 skl_set_cdclk(dev_priv
, cdclk
, vco
);
5802 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
5804 uint32_t cdctl
, expected
;
5807 * check if the pre-os intialized the display
5808 * There is SWF18 scratchpad register defined which is set by the
5809 * pre-os which can be used by the OS drivers to check the status
5811 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5814 intel_update_cdclk(&dev_priv
->drm
);
5815 /* Is PLL enabled and locked ? */
5816 if (dev_priv
->cdclk_pll
.vco
== 0 ||
5817 dev_priv
->cdclk_freq
== dev_priv
->cdclk_pll
.ref
)
5820 /* DPLL okay; verify the cdclock
5822 * Noticed in some instances that the freq selection is correct but
5823 * decimal part is programmed wrong from BIOS where pre-os does not
5824 * enable display. Verify the same as well.
5826 cdctl
= I915_READ(CDCLK_CTL
);
5827 expected
= (cdctl
& CDCLK_FREQ_SEL_MASK
) |
5828 skl_cdclk_decimal(dev_priv
->cdclk_freq
);
5829 if (cdctl
== expected
)
5830 /* All well; nothing to sanitize */
5834 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5836 /* force cdclk programming */
5837 dev_priv
->cdclk_freq
= 0;
5838 /* force full PLL disable + enable */
5839 dev_priv
->cdclk_pll
.vco
= -1;
5842 /* Adjust CDclk dividers to allow high res or save power if possible */
5843 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5845 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5848 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5849 != dev_priv
->cdclk_freq
);
5851 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5853 else if (cdclk
== 266667)
5858 mutex_lock(&dev_priv
->rps
.hw_lock
);
5859 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5860 val
&= ~DSPFREQGUAR_MASK
;
5861 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5862 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5863 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5864 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5866 DRM_ERROR("timed out waiting for CDclk change\n");
5868 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5870 mutex_lock(&dev_priv
->sb_lock
);
5872 if (cdclk
== 400000) {
5875 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5877 /* adjust cdclk divider */
5878 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5879 val
&= ~CCK_FREQUENCY_VALUES
;
5881 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5883 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5884 CCK_FREQUENCY_STATUS
) == (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
5886 DRM_ERROR("timed out waiting for CDclk change\n");
5889 /* adjust self-refresh exit latency value */
5890 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5894 * For high bandwidth configs, we set a higher latency in the bunit
5895 * so that the core display fetch happens in time to avoid underruns.
5897 if (cdclk
== 400000)
5898 val
|= 4500 / 250; /* 4.5 usec */
5900 val
|= 3000 / 250; /* 3.0 usec */
5901 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5903 mutex_unlock(&dev_priv
->sb_lock
);
5905 intel_update_cdclk(dev
);
5908 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5910 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5913 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5914 != dev_priv
->cdclk_freq
);
5923 MISSING_CASE(cdclk
);
5928 * Specs are full of misinformation, but testing on actual
5929 * hardware has shown that we just need to write the desired
5930 * CCK divider into the Punit register.
5932 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5934 mutex_lock(&dev_priv
->rps
.hw_lock
);
5935 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5936 val
&= ~DSPFREQGUAR_MASK_CHV
;
5937 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5938 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5939 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5940 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5942 DRM_ERROR("timed out waiting for CDclk change\n");
5944 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5946 intel_update_cdclk(dev
);
5949 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5952 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5953 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5956 * Really only a few cases to deal with, as only 4 CDclks are supported:
5959 * 320/333MHz (depends on HPLL freq)
5961 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5962 * of the lower bin and adjust if needed.
5964 * We seem to get an unstable or solid color picture at 200MHz.
5965 * Not sure what's wrong. For now use 200MHz only when all pipes
5968 if (!IS_CHERRYVIEW(dev_priv
) &&
5969 max_pixclk
> freq_320
*limit
/100)
5971 else if (max_pixclk
> 266667*limit
/100)
5973 else if (max_pixclk
> 0)
5979 static int bxt_calc_cdclk(int max_pixclk
)
5981 if (max_pixclk
> 576000)
5983 else if (max_pixclk
> 384000)
5985 else if (max_pixclk
> 288000)
5987 else if (max_pixclk
> 144000)
5993 /* Compute the max pixel clock for new configuration. */
5994 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5995 struct drm_atomic_state
*state
)
5997 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
5998 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5999 struct drm_crtc
*crtc
;
6000 struct drm_crtc_state
*crtc_state
;
6001 unsigned max_pixclk
= 0, i
;
6004 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
6005 sizeof(intel_state
->min_pixclk
));
6007 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
6010 if (crtc_state
->enable
)
6011 pixclk
= crtc_state
->adjusted_mode
.crtc_clock
;
6013 intel_state
->min_pixclk
[i
] = pixclk
;
6016 for_each_pipe(dev_priv
, pipe
)
6017 max_pixclk
= max(intel_state
->min_pixclk
[pipe
], max_pixclk
);
6022 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6024 struct drm_device
*dev
= state
->dev
;
6025 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6026 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
6027 struct intel_atomic_state
*intel_state
=
6028 to_intel_atomic_state(state
);
6030 intel_state
->cdclk
= intel_state
->dev_cdclk
=
6031 valleyview_calc_cdclk(dev_priv
, max_pixclk
);
6033 if (!intel_state
->active_crtcs
)
6034 intel_state
->dev_cdclk
= valleyview_calc_cdclk(dev_priv
, 0);
6039 static int bxt_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6041 int max_pixclk
= ilk_max_pixel_rate(state
);
6042 struct intel_atomic_state
*intel_state
=
6043 to_intel_atomic_state(state
);
6045 intel_state
->cdclk
= intel_state
->dev_cdclk
=
6046 bxt_calc_cdclk(max_pixclk
);
6048 if (!intel_state
->active_crtcs
)
6049 intel_state
->dev_cdclk
= bxt_calc_cdclk(0);
6054 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
6056 unsigned int credits
, default_credits
;
6058 if (IS_CHERRYVIEW(dev_priv
))
6059 default_credits
= PFI_CREDIT(12);
6061 default_credits
= PFI_CREDIT(8);
6063 if (dev_priv
->cdclk_freq
>= dev_priv
->czclk_freq
) {
6064 /* CHV suggested value is 31 or 63 */
6065 if (IS_CHERRYVIEW(dev_priv
))
6066 credits
= PFI_CREDIT_63
;
6068 credits
= PFI_CREDIT(15);
6070 credits
= default_credits
;
6074 * WA - write default credits before re-programming
6075 * FIXME: should we also set the resend bit here?
6077 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6080 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6081 credits
| PFI_CREDIT_RESEND
);
6084 * FIXME is this guaranteed to clear
6085 * immediately or should we poll for it?
6087 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6090 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
6092 struct drm_device
*dev
= old_state
->dev
;
6093 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6094 struct intel_atomic_state
*old_intel_state
=
6095 to_intel_atomic_state(old_state
);
6096 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
6099 * FIXME: We can end up here with all power domains off, yet
6100 * with a CDCLK frequency other than the minimum. To account
6101 * for this take the PIPE-A power domain, which covers the HW
6102 * blocks needed for the following programming. This can be
6103 * removed once it's guaranteed that we get here either with
6104 * the minimum CDCLK set, or the required power domains
6107 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6109 if (IS_CHERRYVIEW(dev
))
6110 cherryview_set_cdclk(dev
, req_cdclk
);
6112 valleyview_set_cdclk(dev
, req_cdclk
);
6114 vlv_program_pfi_credits(dev_priv
);
6116 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6119 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
6121 struct drm_device
*dev
= crtc
->dev
;
6122 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6123 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6124 struct intel_encoder
*encoder
;
6125 struct intel_crtc_state
*pipe_config
=
6126 to_intel_crtc_state(crtc
->state
);
6127 int pipe
= intel_crtc
->pipe
;
6129 if (WARN_ON(intel_crtc
->active
))
6132 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
6133 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6135 intel_set_pipe_timings(intel_crtc
);
6136 intel_set_pipe_src_size(intel_crtc
);
6138 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6139 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6141 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6142 I915_WRITE(CHV_CANVAS(pipe
), 0);
6145 i9xx_set_pipeconf(intel_crtc
);
6147 intel_crtc
->active
= true;
6149 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6151 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6152 if (encoder
->pre_pll_enable
)
6153 encoder
->pre_pll_enable(encoder
);
6155 if (IS_CHERRYVIEW(dev
)) {
6156 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6157 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6159 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6160 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6163 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6164 if (encoder
->pre_enable
)
6165 encoder
->pre_enable(encoder
);
6167 i9xx_pfit_enable(intel_crtc
);
6169 intel_color_load_luts(&pipe_config
->base
);
6171 intel_update_watermarks(crtc
);
6172 intel_enable_pipe(intel_crtc
);
6174 assert_vblank_disabled(crtc
);
6175 drm_crtc_vblank_on(crtc
);
6177 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6178 encoder
->enable(encoder
);
6181 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6183 struct drm_device
*dev
= crtc
->base
.dev
;
6184 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6186 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6187 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6190 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6192 struct drm_device
*dev
= crtc
->dev
;
6193 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6195 struct intel_encoder
*encoder
;
6196 struct intel_crtc_state
*pipe_config
=
6197 to_intel_crtc_state(crtc
->state
);
6198 enum pipe pipe
= intel_crtc
->pipe
;
6200 if (WARN_ON(intel_crtc
->active
))
6203 i9xx_set_pll_dividers(intel_crtc
);
6205 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
6206 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6208 intel_set_pipe_timings(intel_crtc
);
6209 intel_set_pipe_src_size(intel_crtc
);
6211 i9xx_set_pipeconf(intel_crtc
);
6213 intel_crtc
->active
= true;
6216 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6218 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6219 if (encoder
->pre_enable
)
6220 encoder
->pre_enable(encoder
);
6222 i9xx_enable_pll(intel_crtc
);
6224 i9xx_pfit_enable(intel_crtc
);
6226 intel_color_load_luts(&pipe_config
->base
);
6228 intel_update_watermarks(crtc
);
6229 intel_enable_pipe(intel_crtc
);
6231 assert_vblank_disabled(crtc
);
6232 drm_crtc_vblank_on(crtc
);
6234 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6235 encoder
->enable(encoder
);
6238 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6240 struct drm_device
*dev
= crtc
->base
.dev
;
6241 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6243 if (!crtc
->config
->gmch_pfit
.control
)
6246 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6248 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6249 I915_READ(PFIT_CONTROL
));
6250 I915_WRITE(PFIT_CONTROL
, 0);
6253 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6255 struct drm_device
*dev
= crtc
->dev
;
6256 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6257 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6258 struct intel_encoder
*encoder
;
6259 int pipe
= intel_crtc
->pipe
;
6262 * On gen2 planes are double buffered but the pipe isn't, so we must
6263 * wait for planes to fully turn off before disabling the pipe.
6266 intel_wait_for_vblank(dev
, pipe
);
6268 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6269 encoder
->disable(encoder
);
6271 drm_crtc_vblank_off(crtc
);
6272 assert_vblank_disabled(crtc
);
6274 intel_disable_pipe(intel_crtc
);
6276 i9xx_pfit_disable(intel_crtc
);
6278 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6279 if (encoder
->post_disable
)
6280 encoder
->post_disable(encoder
);
6282 if (!intel_crtc
->config
->has_dsi_encoder
) {
6283 if (IS_CHERRYVIEW(dev
))
6284 chv_disable_pll(dev_priv
, pipe
);
6285 else if (IS_VALLEYVIEW(dev
))
6286 vlv_disable_pll(dev_priv
, pipe
);
6288 i9xx_disable_pll(intel_crtc
);
6291 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6292 if (encoder
->post_pll_disable
)
6293 encoder
->post_pll_disable(encoder
);
6296 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6299 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6301 struct intel_encoder
*encoder
;
6302 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6303 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6304 enum intel_display_power_domain domain
;
6305 unsigned long domains
;
6307 if (!intel_crtc
->active
)
6310 if (to_intel_plane_state(crtc
->primary
->state
)->visible
) {
6311 WARN_ON(intel_crtc
->flip_work
);
6313 intel_pre_disable_primary_noatomic(crtc
);
6315 intel_crtc_disable_planes(crtc
, 1 << drm_plane_index(crtc
->primary
));
6316 to_intel_plane_state(crtc
->primary
->state
)->visible
= false;
6319 dev_priv
->display
.crtc_disable(crtc
);
6321 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6322 crtc
->base
.id
, crtc
->name
);
6324 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6325 crtc
->state
->active
= false;
6326 intel_crtc
->active
= false;
6327 crtc
->enabled
= false;
6328 crtc
->state
->connector_mask
= 0;
6329 crtc
->state
->encoder_mask
= 0;
6331 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6332 encoder
->base
.crtc
= NULL
;
6334 intel_fbc_disable(intel_crtc
);
6335 intel_update_watermarks(crtc
);
6336 intel_disable_shared_dpll(intel_crtc
);
6338 domains
= intel_crtc
->enabled_power_domains
;
6339 for_each_power_domain(domain
, domains
)
6340 intel_display_power_put(dev_priv
, domain
);
6341 intel_crtc
->enabled_power_domains
= 0;
6343 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6344 dev_priv
->min_pixclk
[intel_crtc
->pipe
] = 0;
6348 * turn all crtc's off, but do not adjust state
6349 * This has to be paired with a call to intel_modeset_setup_hw_state.
6351 int intel_display_suspend(struct drm_device
*dev
)
6353 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6354 struct drm_atomic_state
*state
;
6357 state
= drm_atomic_helper_suspend(dev
);
6358 ret
= PTR_ERR_OR_ZERO(state
);
6360 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6362 dev_priv
->modeset_restore_state
= state
;
6366 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6368 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6370 drm_encoder_cleanup(encoder
);
6371 kfree(intel_encoder
);
6374 /* Cross check the actual hw state with our own modeset state tracking (and it's
6375 * internal consistency). */
6376 static void intel_connector_verify_state(struct intel_connector
*connector
)
6378 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
6380 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6381 connector
->base
.base
.id
,
6382 connector
->base
.name
);
6384 if (connector
->get_hw_state(connector
)) {
6385 struct intel_encoder
*encoder
= connector
->encoder
;
6386 struct drm_connector_state
*conn_state
= connector
->base
.state
;
6388 I915_STATE_WARN(!crtc
,
6389 "connector enabled without attached crtc\n");
6394 I915_STATE_WARN(!crtc
->state
->active
,
6395 "connector is active, but attached crtc isn't\n");
6397 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6400 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6401 "atomic encoder doesn't match attached encoder\n");
6403 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6404 "attached encoder crtc differs from connector crtc\n");
6406 I915_STATE_WARN(crtc
&& crtc
->state
->active
,
6407 "attached crtc is active, but connector isn't\n");
6408 I915_STATE_WARN(!crtc
&& connector
->base
.state
->best_encoder
,
6409 "best encoder set without crtc!\n");
6413 int intel_connector_init(struct intel_connector
*connector
)
6415 drm_atomic_helper_connector_reset(&connector
->base
);
6417 if (!connector
->base
.state
)
6423 struct intel_connector
*intel_connector_alloc(void)
6425 struct intel_connector
*connector
;
6427 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6431 if (intel_connector_init(connector
) < 0) {
6439 /* Simple connector->get_hw_state implementation for encoders that support only
6440 * one connector and no cloning and hence the encoder state determines the state
6441 * of the connector. */
6442 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6445 struct intel_encoder
*encoder
= connector
->encoder
;
6447 return encoder
->get_hw_state(encoder
, &pipe
);
6450 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6452 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6453 return crtc_state
->fdi_lanes
;
6458 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6459 struct intel_crtc_state
*pipe_config
)
6461 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6462 struct intel_crtc
*other_crtc
;
6463 struct intel_crtc_state
*other_crtc_state
;
6465 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6466 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6467 if (pipe_config
->fdi_lanes
> 4) {
6468 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6469 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6473 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6474 if (pipe_config
->fdi_lanes
> 2) {
6475 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6476 pipe_config
->fdi_lanes
);
6483 if (INTEL_INFO(dev
)->num_pipes
== 2)
6486 /* Ivybridge 3 pipe is really complicated */
6491 if (pipe_config
->fdi_lanes
<= 2)
6494 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6496 intel_atomic_get_crtc_state(state
, other_crtc
);
6497 if (IS_ERR(other_crtc_state
))
6498 return PTR_ERR(other_crtc_state
);
6500 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6501 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6502 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6507 if (pipe_config
->fdi_lanes
> 2) {
6508 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6509 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6513 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6515 intel_atomic_get_crtc_state(state
, other_crtc
);
6516 if (IS_ERR(other_crtc_state
))
6517 return PTR_ERR(other_crtc_state
);
6519 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6520 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6530 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6531 struct intel_crtc_state
*pipe_config
)
6533 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6534 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6535 int lane
, link_bw
, fdi_dotclock
, ret
;
6536 bool needs_recompute
= false;
6539 /* FDI is a binary signal running at ~2.7GHz, encoding
6540 * each output octet as 10 bits. The actual frequency
6541 * is stored as a divider into a 100MHz clock, and the
6542 * mode pixel clock is stored in units of 1KHz.
6543 * Hence the bw of each lane in terms of the mode signal
6546 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
6548 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6550 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6551 pipe_config
->pipe_bpp
);
6553 pipe_config
->fdi_lanes
= lane
;
6555 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6556 link_bw
, &pipe_config
->fdi_m_n
);
6558 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
6559 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6560 pipe_config
->pipe_bpp
-= 2*3;
6561 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6562 pipe_config
->pipe_bpp
);
6563 needs_recompute
= true;
6564 pipe_config
->bw_constrained
= true;
6569 if (needs_recompute
)
6575 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6576 struct intel_crtc_state
*pipe_config
)
6578 if (pipe_config
->pipe_bpp
> 24)
6581 /* HSW can handle pixel rate up to cdclk? */
6582 if (IS_HASWELL(dev_priv
))
6586 * We compare against max which means we must take
6587 * the increased cdclk requirement into account when
6588 * calculating the new cdclk.
6590 * Should measure whether using a lower cdclk w/o IPS
6592 return ilk_pipe_pixel_rate(pipe_config
) <=
6593 dev_priv
->max_cdclk_freq
* 95 / 100;
6596 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6597 struct intel_crtc_state
*pipe_config
)
6599 struct drm_device
*dev
= crtc
->base
.dev
;
6600 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6602 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6603 hsw_crtc_supports_ips(crtc
) &&
6604 pipe_config_supports_ips(dev_priv
, pipe_config
);
6607 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
6609 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
6611 /* GDG double wide on either pipe, otherwise pipe A only */
6612 return INTEL_INFO(dev_priv
)->gen
< 4 &&
6613 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
6616 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6617 struct intel_crtc_state
*pipe_config
)
6619 struct drm_device
*dev
= crtc
->base
.dev
;
6620 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6621 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6622 int clock_limit
= dev_priv
->max_dotclk_freq
;
6624 if (INTEL_INFO(dev
)->gen
< 4) {
6625 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
6628 * Enable double wide mode when the dot clock
6629 * is > 90% of the (display) core speed.
6631 if (intel_crtc_supports_double_wide(crtc
) &&
6632 adjusted_mode
->crtc_clock
> clock_limit
) {
6633 clock_limit
= dev_priv
->max_dotclk_freq
;
6634 pipe_config
->double_wide
= true;
6638 if (adjusted_mode
->crtc_clock
> clock_limit
) {
6639 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6640 adjusted_mode
->crtc_clock
, clock_limit
,
6641 yesno(pipe_config
->double_wide
));
6646 * Pipe horizontal size must be even in:
6648 * - LVDS dual channel mode
6649 * - Double wide pipe
6651 if ((intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6652 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6653 pipe_config
->pipe_src_w
&= ~1;
6655 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6656 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6658 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6659 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
6663 hsw_compute_ips_config(crtc
, pipe_config
);
6665 if (pipe_config
->has_pch_encoder
)
6666 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6671 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6673 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6676 skl_dpll0_update(dev_priv
);
6678 if (dev_priv
->cdclk_pll
.vco
== 0)
6679 return dev_priv
->cdclk_pll
.ref
;
6681 cdctl
= I915_READ(CDCLK_CTL
);
6683 if (dev_priv
->cdclk_pll
.vco
== 8640000) {
6684 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6685 case CDCLK_FREQ_450_432
:
6687 case CDCLK_FREQ_337_308
:
6689 case CDCLK_FREQ_540
:
6691 case CDCLK_FREQ_675_617
:
6694 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
6697 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6698 case CDCLK_FREQ_450_432
:
6700 case CDCLK_FREQ_337_308
:
6702 case CDCLK_FREQ_540
:
6704 case CDCLK_FREQ_675_617
:
6707 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
6711 return dev_priv
->cdclk_pll
.ref
;
6714 static void bxt_de_pll_update(struct drm_i915_private
*dev_priv
)
6718 dev_priv
->cdclk_pll
.ref
= 19200;
6719 dev_priv
->cdclk_pll
.vco
= 0;
6721 val
= I915_READ(BXT_DE_PLL_ENABLE
);
6722 if ((val
& BXT_DE_PLL_PLL_ENABLE
) == 0)
6725 if (WARN_ON((val
& BXT_DE_PLL_LOCK
) == 0))
6728 val
= I915_READ(BXT_DE_PLL_CTL
);
6729 dev_priv
->cdclk_pll
.vco
= (val
& BXT_DE_PLL_RATIO_MASK
) *
6730 dev_priv
->cdclk_pll
.ref
;
6733 static int broxton_get_display_clock_speed(struct drm_device
*dev
)
6735 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6739 bxt_de_pll_update(dev_priv
);
6741 vco
= dev_priv
->cdclk_pll
.vco
;
6743 return dev_priv
->cdclk_pll
.ref
;
6745 divider
= I915_READ(CDCLK_CTL
) & BXT_CDCLK_CD2X_DIV_SEL_MASK
;
6748 case BXT_CDCLK_CD2X_DIV_SEL_1
:
6751 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
6754 case BXT_CDCLK_CD2X_DIV_SEL_2
:
6757 case BXT_CDCLK_CD2X_DIV_SEL_4
:
6761 MISSING_CASE(divider
);
6762 return dev_priv
->cdclk_pll
.ref
;
6765 return DIV_ROUND_CLOSEST(vco
, div
);
6768 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6770 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6771 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6772 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6774 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6776 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6778 else if (freq
== LCPLL_CLK_FREQ_450
)
6780 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6782 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6788 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6790 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6791 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6792 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6794 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6796 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6798 else if (freq
== LCPLL_CLK_FREQ_450
)
6800 else if (IS_HSW_ULT(dev
))
6806 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6808 return vlv_get_cck_clock_hpll(to_i915(dev
), "cdclk",
6809 CCK_DISPLAY_CLOCK_CONTROL
);
6812 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6817 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6822 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6827 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6832 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6836 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6838 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6839 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6841 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6843 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6845 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6848 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6849 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6851 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6856 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6860 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6862 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6865 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6866 case GC_DISPLAY_CLOCK_333_MHZ
:
6869 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6875 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6880 static int i85x_get_display_clock_speed(struct drm_device
*dev
)
6885 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6886 * encoding is different :(
6887 * FIXME is this the right way to detect 852GM/852GMV?
6889 if (dev
->pdev
->revision
== 0x1)
6892 pci_bus_read_config_word(dev
->pdev
->bus
,
6893 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
6895 /* Assume that the hardware is in the high speed state. This
6896 * should be the default.
6898 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6899 case GC_CLOCK_133_200
:
6900 case GC_CLOCK_133_200_2
:
6901 case GC_CLOCK_100_200
:
6903 case GC_CLOCK_166_250
:
6905 case GC_CLOCK_100_133
:
6907 case GC_CLOCK_133_266
:
6908 case GC_CLOCK_133_266_2
:
6909 case GC_CLOCK_166_266
:
6913 /* Shouldn't happen */
6917 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6922 static unsigned int intel_hpll_vco(struct drm_device
*dev
)
6924 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6925 static const unsigned int blb_vco
[8] = {
6932 static const unsigned int pnv_vco
[8] = {
6939 static const unsigned int cl_vco
[8] = {
6948 static const unsigned int elk_vco
[8] = {
6954 static const unsigned int ctg_vco
[8] = {
6962 const unsigned int *vco_table
;
6966 /* FIXME other chipsets? */
6968 vco_table
= ctg_vco
;
6969 else if (IS_G4X(dev
))
6970 vco_table
= elk_vco
;
6971 else if (IS_CRESTLINE(dev
))
6973 else if (IS_PINEVIEW(dev
))
6974 vco_table
= pnv_vco
;
6975 else if (IS_G33(dev
))
6976 vco_table
= blb_vco
;
6980 tmp
= I915_READ(IS_MOBILE(dev
) ? HPLLVCO_MOBILE
: HPLLVCO
);
6982 vco
= vco_table
[tmp
& 0x7];
6984 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
6986 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
6991 static int gm45_get_display_clock_speed(struct drm_device
*dev
)
6993 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6996 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6998 cdclk_sel
= (tmp
>> 12) & 0x1;
7004 return cdclk_sel
? 333333 : 222222;
7006 return cdclk_sel
? 320000 : 228571;
7008 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
7013 static int i965gm_get_display_clock_speed(struct drm_device
*dev
)
7015 static const uint8_t div_3200
[] = { 16, 10, 8 };
7016 static const uint8_t div_4000
[] = { 20, 12, 10 };
7017 static const uint8_t div_5333
[] = { 24, 16, 14 };
7018 const uint8_t *div_table
;
7019 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7022 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7024 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
7026 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7031 div_table
= div_3200
;
7034 div_table
= div_4000
;
7037 div_table
= div_5333
;
7043 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7046 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
7050 static int g33_get_display_clock_speed(struct drm_device
*dev
)
7052 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
7053 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
7054 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
7055 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
7056 const uint8_t *div_table
;
7057 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7060 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7062 cdclk_sel
= (tmp
>> 4) & 0x7;
7064 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7069 div_table
= div_3200
;
7072 div_table
= div_4000
;
7075 div_table
= div_4800
;
7078 div_table
= div_5333
;
7084 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7087 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
7092 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
7094 while (*num
> DATA_LINK_M_N_MASK
||
7095 *den
> DATA_LINK_M_N_MASK
) {
7101 static void compute_m_n(unsigned int m
, unsigned int n
,
7102 uint32_t *ret_m
, uint32_t *ret_n
)
7104 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7105 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7106 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7110 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7111 int pixel_clock
, int link_clock
,
7112 struct intel_link_m_n
*m_n
)
7116 compute_m_n(bits_per_pixel
* pixel_clock
,
7117 link_clock
* nlanes
* 8,
7118 &m_n
->gmch_m
, &m_n
->gmch_n
);
7120 compute_m_n(pixel_clock
, link_clock
,
7121 &m_n
->link_m
, &m_n
->link_n
);
7124 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7126 if (i915
.panel_use_ssc
>= 0)
7127 return i915
.panel_use_ssc
!= 0;
7128 return dev_priv
->vbt
.lvds_use_ssc
7129 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7132 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7134 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7137 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7139 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7142 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7143 struct intel_crtc_state
*crtc_state
,
7144 struct dpll
*reduced_clock
)
7146 struct drm_device
*dev
= crtc
->base
.dev
;
7149 if (IS_PINEVIEW(dev
)) {
7150 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7152 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7154 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7156 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7159 crtc_state
->dpll_hw_state
.fp0
= fp
;
7161 crtc
->lowfreq_avail
= false;
7162 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7164 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7165 crtc
->lowfreq_avail
= true;
7167 crtc_state
->dpll_hw_state
.fp1
= fp
;
7171 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7177 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7178 * and set it to a reasonable value instead.
7180 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7181 reg_val
&= 0xffffff00;
7182 reg_val
|= 0x00000030;
7183 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7185 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7186 reg_val
&= 0x8cffffff;
7187 reg_val
= 0x8c000000;
7188 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7190 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7191 reg_val
&= 0xffffff00;
7192 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7194 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7195 reg_val
&= 0x00ffffff;
7196 reg_val
|= 0xb0000000;
7197 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7200 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7201 struct intel_link_m_n
*m_n
)
7203 struct drm_device
*dev
= crtc
->base
.dev
;
7204 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7205 int pipe
= crtc
->pipe
;
7207 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7208 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7209 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7210 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7213 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7214 struct intel_link_m_n
*m_n
,
7215 struct intel_link_m_n
*m2_n2
)
7217 struct drm_device
*dev
= crtc
->base
.dev
;
7218 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7219 int pipe
= crtc
->pipe
;
7220 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7222 if (INTEL_INFO(dev
)->gen
>= 5) {
7223 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7224 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7225 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7226 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7227 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7228 * for gen < 8) and if DRRS is supported (to make sure the
7229 * registers are not unnecessarily accessed).
7231 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7232 crtc
->config
->has_drrs
) {
7233 I915_WRITE(PIPE_DATA_M2(transcoder
),
7234 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7235 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7236 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7237 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7240 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7241 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7242 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7243 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7247 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7249 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7252 dp_m_n
= &crtc
->config
->dp_m_n
;
7253 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7254 } else if (m_n
== M2_N2
) {
7257 * M2_N2 registers are not supported. Hence m2_n2 divider value
7258 * needs to be programmed into M1_N1.
7260 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7262 DRM_ERROR("Unsupported divider value\n");
7266 if (crtc
->config
->has_pch_encoder
)
7267 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7269 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7272 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7273 struct intel_crtc_state
*pipe_config
)
7275 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7276 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7277 if (crtc
->pipe
!= PIPE_A
)
7278 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7280 /* DPLL not used with DSI, but still need the rest set up */
7281 if (!pipe_config
->has_dsi_encoder
)
7282 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
7283 DPLL_EXT_BUFFER_ENABLE_VLV
;
7285 pipe_config
->dpll_hw_state
.dpll_md
=
7286 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7289 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7290 struct intel_crtc_state
*pipe_config
)
7292 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7293 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7294 if (crtc
->pipe
!= PIPE_A
)
7295 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7297 /* DPLL not used with DSI, but still need the rest set up */
7298 if (!pipe_config
->has_dsi_encoder
)
7299 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
7301 pipe_config
->dpll_hw_state
.dpll_md
=
7302 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7305 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7306 const struct intel_crtc_state
*pipe_config
)
7308 struct drm_device
*dev
= crtc
->base
.dev
;
7309 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7310 enum pipe pipe
= crtc
->pipe
;
7312 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7313 u32 coreclk
, reg_val
;
7316 I915_WRITE(DPLL(pipe
),
7317 pipe_config
->dpll_hw_state
.dpll
&
7318 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
7320 /* No need to actually set up the DPLL with DSI */
7321 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7324 mutex_lock(&dev_priv
->sb_lock
);
7326 bestn
= pipe_config
->dpll
.n
;
7327 bestm1
= pipe_config
->dpll
.m1
;
7328 bestm2
= pipe_config
->dpll
.m2
;
7329 bestp1
= pipe_config
->dpll
.p1
;
7330 bestp2
= pipe_config
->dpll
.p2
;
7332 /* See eDP HDMI DPIO driver vbios notes doc */
7334 /* PLL B needs special handling */
7336 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7338 /* Set up Tx target for periodic Rcomp update */
7339 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7341 /* Disable target IRef on PLL */
7342 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7343 reg_val
&= 0x00ffffff;
7344 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7346 /* Disable fast lock */
7347 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7349 /* Set idtafcrecal before PLL is enabled */
7350 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7351 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7352 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7353 mdiv
|= (1 << DPIO_K_SHIFT
);
7356 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7357 * but we don't support that).
7358 * Note: don't use the DAC post divider as it seems unstable.
7360 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7361 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7363 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7364 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7366 /* Set HBR and RBR LPF coefficients */
7367 if (pipe_config
->port_clock
== 162000 ||
7368 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_ANALOG
) ||
7369 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
))
7370 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7373 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7376 if (intel_crtc_has_dp_encoder(pipe_config
)) {
7377 /* Use SSC source */
7379 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7382 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7384 } else { /* HDMI or VGA */
7385 /* Use bend source */
7387 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7390 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7394 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7395 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7396 if (intel_crtc_has_dp_encoder(crtc
->config
))
7397 coreclk
|= 0x01000000;
7398 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7400 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7401 mutex_unlock(&dev_priv
->sb_lock
);
7404 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7405 const struct intel_crtc_state
*pipe_config
)
7407 struct drm_device
*dev
= crtc
->base
.dev
;
7408 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7409 enum pipe pipe
= crtc
->pipe
;
7410 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7411 u32 loopfilter
, tribuf_calcntr
;
7412 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7416 /* Enable Refclk and SSC */
7417 I915_WRITE(DPLL(pipe
),
7418 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7420 /* No need to actually set up the DPLL with DSI */
7421 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7424 bestn
= pipe_config
->dpll
.n
;
7425 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7426 bestm1
= pipe_config
->dpll
.m1
;
7427 bestm2
= pipe_config
->dpll
.m2
>> 22;
7428 bestp1
= pipe_config
->dpll
.p1
;
7429 bestp2
= pipe_config
->dpll
.p2
;
7430 vco
= pipe_config
->dpll
.vco
;
7434 mutex_lock(&dev_priv
->sb_lock
);
7436 /* p1 and p2 divider */
7437 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7438 5 << DPIO_CHV_S1_DIV_SHIFT
|
7439 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7440 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7441 1 << DPIO_CHV_K_DIV_SHIFT
);
7443 /* Feedback post-divider - m2 */
7444 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7446 /* Feedback refclk divider - n and m1 */
7447 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7448 DPIO_CHV_M1_DIV_BY_2
|
7449 1 << DPIO_CHV_N_DIV_SHIFT
);
7451 /* M2 fraction division */
7452 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7454 /* M2 fraction division enable */
7455 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7456 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7457 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7459 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7460 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7462 /* Program digital lock detect threshold */
7463 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7464 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7465 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7466 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7468 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7469 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7472 if (vco
== 5400000) {
7473 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7474 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7475 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7476 tribuf_calcntr
= 0x9;
7477 } else if (vco
<= 6200000) {
7478 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7479 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7480 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7481 tribuf_calcntr
= 0x9;
7482 } else if (vco
<= 6480000) {
7483 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7484 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7485 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7486 tribuf_calcntr
= 0x8;
7488 /* Not supported. Apply the same limits as in the max case */
7489 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7490 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7491 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7494 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7496 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7497 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7498 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7499 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7502 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7503 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7506 mutex_unlock(&dev_priv
->sb_lock
);
7510 * vlv_force_pll_on - forcibly enable just the PLL
7511 * @dev_priv: i915 private structure
7512 * @pipe: pipe PLL to enable
7513 * @dpll: PLL configuration
7515 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7516 * in cases where we need the PLL enabled even when @pipe is not going to
7519 int vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7520 const struct dpll
*dpll
)
7522 struct intel_crtc
*crtc
=
7523 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7524 struct intel_crtc_state
*pipe_config
;
7526 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
7530 pipe_config
->base
.crtc
= &crtc
->base
;
7531 pipe_config
->pixel_multiplier
= 1;
7532 pipe_config
->dpll
= *dpll
;
7534 if (IS_CHERRYVIEW(dev
)) {
7535 chv_compute_dpll(crtc
, pipe_config
);
7536 chv_prepare_pll(crtc
, pipe_config
);
7537 chv_enable_pll(crtc
, pipe_config
);
7539 vlv_compute_dpll(crtc
, pipe_config
);
7540 vlv_prepare_pll(crtc
, pipe_config
);
7541 vlv_enable_pll(crtc
, pipe_config
);
7550 * vlv_force_pll_off - forcibly disable just the PLL
7551 * @dev_priv: i915 private structure
7552 * @pipe: pipe PLL to disable
7554 * Disable the PLL for @pipe. To be used in cases where we need
7555 * the PLL enabled even when @pipe is not going to be enabled.
7557 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7559 if (IS_CHERRYVIEW(dev
))
7560 chv_disable_pll(to_i915(dev
), pipe
);
7562 vlv_disable_pll(to_i915(dev
), pipe
);
7565 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7566 struct intel_crtc_state
*crtc_state
,
7567 struct dpll
*reduced_clock
)
7569 struct drm_device
*dev
= crtc
->base
.dev
;
7570 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7572 struct dpll
*clock
= &crtc_state
->dpll
;
7574 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7576 dpll
= DPLL_VGA_MODE_DIS
;
7578 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7579 dpll
|= DPLLB_MODE_LVDS
;
7581 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7583 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7584 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7585 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7588 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7589 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
7590 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7592 if (intel_crtc_has_dp_encoder(crtc_state
))
7593 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7595 /* compute bitmask from p1 value */
7596 if (IS_PINEVIEW(dev
))
7597 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7599 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7600 if (IS_G4X(dev
) && reduced_clock
)
7601 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7603 switch (clock
->p2
) {
7605 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7608 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7611 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7614 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7617 if (INTEL_INFO(dev
)->gen
>= 4)
7618 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7620 if (crtc_state
->sdvo_tv_clock
)
7621 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7622 else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7623 intel_panel_use_ssc(dev_priv
))
7624 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7626 dpll
|= PLL_REF_INPUT_DREFCLK
;
7628 dpll
|= DPLL_VCO_ENABLE
;
7629 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7631 if (INTEL_INFO(dev
)->gen
>= 4) {
7632 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7633 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7634 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7638 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7639 struct intel_crtc_state
*crtc_state
,
7640 struct dpll
*reduced_clock
)
7642 struct drm_device
*dev
= crtc
->base
.dev
;
7643 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7645 struct dpll
*clock
= &crtc_state
->dpll
;
7647 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7649 dpll
= DPLL_VGA_MODE_DIS
;
7651 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7652 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7655 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7657 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7659 dpll
|= PLL_P2_DIVIDE_BY_4
;
7662 if (!IS_I830(dev
) && intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
))
7663 dpll
|= DPLL_DVO_2X_MODE
;
7665 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7666 intel_panel_use_ssc(dev_priv
))
7667 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7669 dpll
|= PLL_REF_INPUT_DREFCLK
;
7671 dpll
|= DPLL_VCO_ENABLE
;
7672 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7675 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7677 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7678 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7679 enum pipe pipe
= intel_crtc
->pipe
;
7680 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7681 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
7682 uint32_t crtc_vtotal
, crtc_vblank_end
;
7685 /* We need to be careful not to changed the adjusted mode, for otherwise
7686 * the hw state checker will get angry at the mismatch. */
7687 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7688 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7690 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7691 /* the chip adds 2 halflines automatically */
7693 crtc_vblank_end
-= 1;
7695 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
7696 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7698 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7699 adjusted_mode
->crtc_htotal
/ 2;
7701 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7704 if (INTEL_INFO(dev
)->gen
> 3)
7705 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7707 I915_WRITE(HTOTAL(cpu_transcoder
),
7708 (adjusted_mode
->crtc_hdisplay
- 1) |
7709 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7710 I915_WRITE(HBLANK(cpu_transcoder
),
7711 (adjusted_mode
->crtc_hblank_start
- 1) |
7712 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7713 I915_WRITE(HSYNC(cpu_transcoder
),
7714 (adjusted_mode
->crtc_hsync_start
- 1) |
7715 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7717 I915_WRITE(VTOTAL(cpu_transcoder
),
7718 (adjusted_mode
->crtc_vdisplay
- 1) |
7719 ((crtc_vtotal
- 1) << 16));
7720 I915_WRITE(VBLANK(cpu_transcoder
),
7721 (adjusted_mode
->crtc_vblank_start
- 1) |
7722 ((crtc_vblank_end
- 1) << 16));
7723 I915_WRITE(VSYNC(cpu_transcoder
),
7724 (adjusted_mode
->crtc_vsync_start
- 1) |
7725 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7727 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7728 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7729 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7731 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7732 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7733 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7737 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
)
7739 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7740 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7741 enum pipe pipe
= intel_crtc
->pipe
;
7743 /* pipesrc controls the size that is scaled from, which should
7744 * always be the user's requested size.
7746 I915_WRITE(PIPESRC(pipe
),
7747 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7748 (intel_crtc
->config
->pipe_src_h
- 1));
7751 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7752 struct intel_crtc_state
*pipe_config
)
7754 struct drm_device
*dev
= crtc
->base
.dev
;
7755 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7756 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7759 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7760 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7761 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7762 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7763 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7764 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7765 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7766 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7767 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7769 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7770 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7771 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7772 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7773 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7774 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7775 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7776 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7777 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7779 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7780 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7781 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7782 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7786 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
7787 struct intel_crtc_state
*pipe_config
)
7789 struct drm_device
*dev
= crtc
->base
.dev
;
7790 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7793 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7794 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7795 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7797 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7798 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7801 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7802 struct intel_crtc_state
*pipe_config
)
7804 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7805 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7806 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7807 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7809 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7810 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7811 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7812 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7814 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7815 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7817 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7818 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7820 mode
->hsync
= drm_mode_hsync(mode
);
7821 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7822 drm_mode_set_name(mode
);
7825 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7827 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7828 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7833 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7834 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7835 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7837 if (intel_crtc
->config
->double_wide
)
7838 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7840 /* only g4x and later have fancy bpc/dither controls */
7841 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
7842 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7843 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7844 pipeconf
|= PIPECONF_DITHER_EN
|
7845 PIPECONF_DITHER_TYPE_SP
;
7847 switch (intel_crtc
->config
->pipe_bpp
) {
7849 pipeconf
|= PIPECONF_6BPC
;
7852 pipeconf
|= PIPECONF_8BPC
;
7855 pipeconf
|= PIPECONF_10BPC
;
7858 /* Case prevented by intel_choose_pipe_bpp_dither. */
7863 if (HAS_PIPE_CXSR(dev
)) {
7864 if (intel_crtc
->lowfreq_avail
) {
7865 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7866 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7868 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7872 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7873 if (INTEL_INFO(dev
)->gen
< 4 ||
7874 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
7875 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7877 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7879 pipeconf
|= PIPECONF_PROGRESSIVE
;
7881 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
7882 intel_crtc
->config
->limited_color_range
)
7883 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7885 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7886 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7889 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7890 struct intel_crtc_state
*crtc_state
)
7892 struct drm_device
*dev
= crtc
->base
.dev
;
7893 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7894 const struct intel_limit
*limit
;
7897 memset(&crtc_state
->dpll_hw_state
, 0,
7898 sizeof(crtc_state
->dpll_hw_state
));
7900 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7901 if (intel_panel_use_ssc(dev_priv
)) {
7902 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7903 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7906 limit
= &intel_limits_i8xx_lvds
;
7907 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
7908 limit
= &intel_limits_i8xx_dvo
;
7910 limit
= &intel_limits_i8xx_dac
;
7913 if (!crtc_state
->clock_set
&&
7914 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7915 refclk
, NULL
, &crtc_state
->dpll
)) {
7916 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7920 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
7925 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
7926 struct intel_crtc_state
*crtc_state
)
7928 struct drm_device
*dev
= crtc
->base
.dev
;
7929 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7930 const struct intel_limit
*limit
;
7933 memset(&crtc_state
->dpll_hw_state
, 0,
7934 sizeof(crtc_state
->dpll_hw_state
));
7936 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7937 if (intel_panel_use_ssc(dev_priv
)) {
7938 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7939 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7942 if (intel_is_dual_link_lvds(dev
))
7943 limit
= &intel_limits_g4x_dual_channel_lvds
;
7945 limit
= &intel_limits_g4x_single_channel_lvds
;
7946 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
7947 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
7948 limit
= &intel_limits_g4x_hdmi
;
7949 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
7950 limit
= &intel_limits_g4x_sdvo
;
7952 /* The option is for other outputs */
7953 limit
= &intel_limits_i9xx_sdvo
;
7956 if (!crtc_state
->clock_set
&&
7957 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7958 refclk
, NULL
, &crtc_state
->dpll
)) {
7959 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7963 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
7968 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
7969 struct intel_crtc_state
*crtc_state
)
7971 struct drm_device
*dev
= crtc
->base
.dev
;
7972 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7973 const struct intel_limit
*limit
;
7976 memset(&crtc_state
->dpll_hw_state
, 0,
7977 sizeof(crtc_state
->dpll_hw_state
));
7979 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7980 if (intel_panel_use_ssc(dev_priv
)) {
7981 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7982 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7985 limit
= &intel_limits_pineview_lvds
;
7987 limit
= &intel_limits_pineview_sdvo
;
7990 if (!crtc_state
->clock_set
&&
7991 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
7992 refclk
, NULL
, &crtc_state
->dpll
)) {
7993 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7997 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8002 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
8003 struct intel_crtc_state
*crtc_state
)
8005 struct drm_device
*dev
= crtc
->base
.dev
;
8006 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8007 const struct intel_limit
*limit
;
8010 memset(&crtc_state
->dpll_hw_state
, 0,
8011 sizeof(crtc_state
->dpll_hw_state
));
8013 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8014 if (intel_panel_use_ssc(dev_priv
)) {
8015 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8016 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8019 limit
= &intel_limits_i9xx_lvds
;
8021 limit
= &intel_limits_i9xx_sdvo
;
8024 if (!crtc_state
->clock_set
&&
8025 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8026 refclk
, NULL
, &crtc_state
->dpll
)) {
8027 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8031 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8036 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
8037 struct intel_crtc_state
*crtc_state
)
8039 int refclk
= 100000;
8040 const struct intel_limit
*limit
= &intel_limits_chv
;
8042 memset(&crtc_state
->dpll_hw_state
, 0,
8043 sizeof(crtc_state
->dpll_hw_state
));
8045 if (!crtc_state
->clock_set
&&
8046 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8047 refclk
, NULL
, &crtc_state
->dpll
)) {
8048 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8052 chv_compute_dpll(crtc
, crtc_state
);
8057 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
8058 struct intel_crtc_state
*crtc_state
)
8060 int refclk
= 100000;
8061 const struct intel_limit
*limit
= &intel_limits_vlv
;
8063 memset(&crtc_state
->dpll_hw_state
, 0,
8064 sizeof(crtc_state
->dpll_hw_state
));
8066 if (!crtc_state
->clock_set
&&
8067 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8068 refclk
, NULL
, &crtc_state
->dpll
)) {
8069 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8073 vlv_compute_dpll(crtc
, crtc_state
);
8078 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
8079 struct intel_crtc_state
*pipe_config
)
8081 struct drm_device
*dev
= crtc
->base
.dev
;
8082 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8085 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
8088 tmp
= I915_READ(PFIT_CONTROL
);
8089 if (!(tmp
& PFIT_ENABLE
))
8092 /* Check whether the pfit is attached to our pipe. */
8093 if (INTEL_INFO(dev
)->gen
< 4) {
8094 if (crtc
->pipe
!= PIPE_B
)
8097 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8101 pipe_config
->gmch_pfit
.control
= tmp
;
8102 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8105 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8106 struct intel_crtc_state
*pipe_config
)
8108 struct drm_device
*dev
= crtc
->base
.dev
;
8109 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8110 int pipe
= pipe_config
->cpu_transcoder
;
8113 int refclk
= 100000;
8115 /* In case of DSI, DPLL will not be used */
8116 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8119 mutex_lock(&dev_priv
->sb_lock
);
8120 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8121 mutex_unlock(&dev_priv
->sb_lock
);
8123 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8124 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8125 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8126 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8127 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8129 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8133 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8134 struct intel_initial_plane_config
*plane_config
)
8136 struct drm_device
*dev
= crtc
->base
.dev
;
8137 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8138 u32 val
, base
, offset
;
8139 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
8140 int fourcc
, pixel_format
;
8141 unsigned int aligned_height
;
8142 struct drm_framebuffer
*fb
;
8143 struct intel_framebuffer
*intel_fb
;
8145 val
= I915_READ(DSPCNTR(plane
));
8146 if (!(val
& DISPLAY_PLANE_ENABLE
))
8149 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8151 DRM_DEBUG_KMS("failed to alloc fb\n");
8155 fb
= &intel_fb
->base
;
8157 if (INTEL_INFO(dev
)->gen
>= 4) {
8158 if (val
& DISPPLANE_TILED
) {
8159 plane_config
->tiling
= I915_TILING_X
;
8160 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8164 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8165 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8166 fb
->pixel_format
= fourcc
;
8167 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8169 if (INTEL_INFO(dev
)->gen
>= 4) {
8170 if (plane_config
->tiling
)
8171 offset
= I915_READ(DSPTILEOFF(plane
));
8173 offset
= I915_READ(DSPLINOFF(plane
));
8174 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
8176 base
= I915_READ(DSPADDR(plane
));
8178 plane_config
->base
= base
;
8180 val
= I915_READ(PIPESRC(pipe
));
8181 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8182 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8184 val
= I915_READ(DSPSTRIDE(pipe
));
8185 fb
->pitches
[0] = val
& 0xffffffc0;
8187 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8191 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8193 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8194 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8195 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8196 plane_config
->size
);
8198 plane_config
->fb
= intel_fb
;
8201 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8202 struct intel_crtc_state
*pipe_config
)
8204 struct drm_device
*dev
= crtc
->base
.dev
;
8205 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8206 int pipe
= pipe_config
->cpu_transcoder
;
8207 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8209 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8210 int refclk
= 100000;
8212 /* In case of DSI, DPLL will not be used */
8213 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8216 mutex_lock(&dev_priv
->sb_lock
);
8217 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8218 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8219 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8220 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8221 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8222 mutex_unlock(&dev_priv
->sb_lock
);
8224 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8225 clock
.m2
= (pll_dw0
& 0xff) << 22;
8226 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8227 clock
.m2
|= pll_dw2
& 0x3fffff;
8228 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8229 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8230 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8232 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8235 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8236 struct intel_crtc_state
*pipe_config
)
8238 struct drm_device
*dev
= crtc
->base
.dev
;
8239 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8240 enum intel_display_power_domain power_domain
;
8244 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8245 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
8248 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8249 pipe_config
->shared_dpll
= NULL
;
8253 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8254 if (!(tmp
& PIPECONF_ENABLE
))
8257 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
8258 switch (tmp
& PIPECONF_BPC_MASK
) {
8260 pipe_config
->pipe_bpp
= 18;
8263 pipe_config
->pipe_bpp
= 24;
8265 case PIPECONF_10BPC
:
8266 pipe_config
->pipe_bpp
= 30;
8273 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
8274 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8275 pipe_config
->limited_color_range
= true;
8277 if (INTEL_INFO(dev
)->gen
< 4)
8278 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8280 intel_get_pipe_timings(crtc
, pipe_config
);
8281 intel_get_pipe_src_size(crtc
, pipe_config
);
8283 i9xx_get_pfit_config(crtc
, pipe_config
);
8285 if (INTEL_INFO(dev
)->gen
>= 4) {
8286 /* No way to read it out on pipes B and C */
8287 if (IS_CHERRYVIEW(dev
) && crtc
->pipe
!= PIPE_A
)
8288 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8290 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8291 pipe_config
->pixel_multiplier
=
8292 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8293 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8294 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8295 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
8296 tmp
= I915_READ(DPLL(crtc
->pipe
));
8297 pipe_config
->pixel_multiplier
=
8298 ((tmp
& SDVO_MULTIPLIER_MASK
)
8299 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8301 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8302 * port and will be fixed up in the encoder->get_config
8304 pipe_config
->pixel_multiplier
= 1;
8306 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8307 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
8309 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8310 * on 830. Filter it out here so that we don't
8311 * report errors due to that.
8314 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8316 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8317 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8319 /* Mask out read-only status bits. */
8320 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8321 DPLL_PORTC_READY_MASK
|
8322 DPLL_PORTB_READY_MASK
);
8325 if (IS_CHERRYVIEW(dev
))
8326 chv_crtc_clock_get(crtc
, pipe_config
);
8327 else if (IS_VALLEYVIEW(dev
))
8328 vlv_crtc_clock_get(crtc
, pipe_config
);
8330 i9xx_crtc_clock_get(crtc
, pipe_config
);
8333 * Normally the dotclock is filled in by the encoder .get_config()
8334 * but in case the pipe is enabled w/o any ports we need a sane
8337 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8338 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8343 intel_display_power_put(dev_priv
, power_domain
);
8348 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
8350 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8351 struct intel_encoder
*encoder
;
8354 bool has_lvds
= false;
8355 bool has_cpu_edp
= false;
8356 bool has_panel
= false;
8357 bool has_ck505
= false;
8358 bool can_ssc
= false;
8359 bool using_ssc_source
= false;
8361 /* We need to take the global config into account */
8362 for_each_intel_encoder(dev
, encoder
) {
8363 switch (encoder
->type
) {
8364 case INTEL_OUTPUT_LVDS
:
8368 case INTEL_OUTPUT_EDP
:
8370 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8378 if (HAS_PCH_IBX(dev
)) {
8379 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8380 can_ssc
= has_ck505
;
8386 /* Check if any DPLLs are using the SSC source */
8387 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8388 u32 temp
= I915_READ(PCH_DPLL(i
));
8390 if (!(temp
& DPLL_VCO_ENABLE
))
8393 if ((temp
& PLL_REF_INPUT_MASK
) ==
8394 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
8395 using_ssc_source
= true;
8400 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8401 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
8403 /* Ironlake: try to setup display ref clock before DPLL
8404 * enabling. This is only under driver's control after
8405 * PCH B stepping, previous chipset stepping should be
8406 * ignoring this setting.
8408 val
= I915_READ(PCH_DREF_CONTROL
);
8410 /* As we must carefully and slowly disable/enable each source in turn,
8411 * compute the final state we want first and check if we need to
8412 * make any changes at all.
8415 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8417 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8419 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8421 final
&= ~DREF_SSC_SOURCE_MASK
;
8422 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8423 final
&= ~DREF_SSC1_ENABLE
;
8426 final
|= DREF_SSC_SOURCE_ENABLE
;
8428 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8429 final
|= DREF_SSC1_ENABLE
;
8432 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8433 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8435 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8437 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8438 } else if (using_ssc_source
) {
8439 final
|= DREF_SSC_SOURCE_ENABLE
;
8440 final
|= DREF_SSC1_ENABLE
;
8446 /* Always enable nonspread source */
8447 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8450 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8452 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8455 val
&= ~DREF_SSC_SOURCE_MASK
;
8456 val
|= DREF_SSC_SOURCE_ENABLE
;
8458 /* SSC must be turned on before enabling the CPU output */
8459 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8460 DRM_DEBUG_KMS("Using SSC on panel\n");
8461 val
|= DREF_SSC1_ENABLE
;
8463 val
&= ~DREF_SSC1_ENABLE
;
8465 /* Get SSC going before enabling the outputs */
8466 I915_WRITE(PCH_DREF_CONTROL
, val
);
8467 POSTING_READ(PCH_DREF_CONTROL
);
8470 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8472 /* Enable CPU source on CPU attached eDP */
8474 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8475 DRM_DEBUG_KMS("Using SSC on eDP\n");
8476 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8478 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8480 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8482 I915_WRITE(PCH_DREF_CONTROL
, val
);
8483 POSTING_READ(PCH_DREF_CONTROL
);
8486 DRM_DEBUG_KMS("Disabling CPU source output\n");
8488 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8490 /* Turn off CPU output */
8491 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8493 I915_WRITE(PCH_DREF_CONTROL
, val
);
8494 POSTING_READ(PCH_DREF_CONTROL
);
8497 if (!using_ssc_source
) {
8498 DRM_DEBUG_KMS("Disabling SSC source\n");
8500 /* Turn off the SSC source */
8501 val
&= ~DREF_SSC_SOURCE_MASK
;
8502 val
|= DREF_SSC_SOURCE_DISABLE
;
8505 val
&= ~DREF_SSC1_ENABLE
;
8507 I915_WRITE(PCH_DREF_CONTROL
, val
);
8508 POSTING_READ(PCH_DREF_CONTROL
);
8513 BUG_ON(val
!= final
);
8516 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8520 tmp
= I915_READ(SOUTH_CHICKEN2
);
8521 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8522 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8524 if (wait_for_us(I915_READ(SOUTH_CHICKEN2
) &
8525 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8526 DRM_ERROR("FDI mPHY reset assert timeout\n");
8528 tmp
= I915_READ(SOUTH_CHICKEN2
);
8529 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8530 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8532 if (wait_for_us((I915_READ(SOUTH_CHICKEN2
) &
8533 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8534 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8537 /* WaMPhyProgramming:hsw */
8538 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8542 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8543 tmp
&= ~(0xFF << 24);
8544 tmp
|= (0x12 << 24);
8545 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8547 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8549 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8551 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8553 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8555 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8556 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8557 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8559 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8560 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8561 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8563 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8566 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8568 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8571 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8573 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8576 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8578 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8581 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8583 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8584 tmp
&= ~(0xFF << 16);
8585 tmp
|= (0x1C << 16);
8586 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8588 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8589 tmp
&= ~(0xFF << 16);
8590 tmp
|= (0x1C << 16);
8591 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8593 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8595 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8597 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8599 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8601 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8602 tmp
&= ~(0xF << 28);
8604 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8606 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8607 tmp
&= ~(0xF << 28);
8609 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8612 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8613 * Programming" based on the parameters passed:
8614 * - Sequence to enable CLKOUT_DP
8615 * - Sequence to enable CLKOUT_DP without spread
8616 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8618 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8621 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8624 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8626 if (WARN(HAS_PCH_LPT_LP(dev
) && with_fdi
, "LP PCH doesn't have FDI\n"))
8629 mutex_lock(&dev_priv
->sb_lock
);
8631 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8632 tmp
&= ~SBI_SSCCTL_DISABLE
;
8633 tmp
|= SBI_SSCCTL_PATHALT
;
8634 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8639 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8640 tmp
&= ~SBI_SSCCTL_PATHALT
;
8641 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8644 lpt_reset_fdi_mphy(dev_priv
);
8645 lpt_program_fdi_mphy(dev_priv
);
8649 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8650 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8651 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8652 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8654 mutex_unlock(&dev_priv
->sb_lock
);
8657 /* Sequence to disable CLKOUT_DP */
8658 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8660 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8663 mutex_lock(&dev_priv
->sb_lock
);
8665 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8666 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8667 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8668 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8670 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8671 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8672 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8673 tmp
|= SBI_SSCCTL_PATHALT
;
8674 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8677 tmp
|= SBI_SSCCTL_DISABLE
;
8678 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8681 mutex_unlock(&dev_priv
->sb_lock
);
8684 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8686 static const uint16_t sscdivintphase
[] = {
8687 [BEND_IDX( 50)] = 0x3B23,
8688 [BEND_IDX( 45)] = 0x3B23,
8689 [BEND_IDX( 40)] = 0x3C23,
8690 [BEND_IDX( 35)] = 0x3C23,
8691 [BEND_IDX( 30)] = 0x3D23,
8692 [BEND_IDX( 25)] = 0x3D23,
8693 [BEND_IDX( 20)] = 0x3E23,
8694 [BEND_IDX( 15)] = 0x3E23,
8695 [BEND_IDX( 10)] = 0x3F23,
8696 [BEND_IDX( 5)] = 0x3F23,
8697 [BEND_IDX( 0)] = 0x0025,
8698 [BEND_IDX( -5)] = 0x0025,
8699 [BEND_IDX(-10)] = 0x0125,
8700 [BEND_IDX(-15)] = 0x0125,
8701 [BEND_IDX(-20)] = 0x0225,
8702 [BEND_IDX(-25)] = 0x0225,
8703 [BEND_IDX(-30)] = 0x0325,
8704 [BEND_IDX(-35)] = 0x0325,
8705 [BEND_IDX(-40)] = 0x0425,
8706 [BEND_IDX(-45)] = 0x0425,
8707 [BEND_IDX(-50)] = 0x0525,
8712 * steps -50 to 50 inclusive, in steps of 5
8713 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8714 * change in clock period = -(steps / 10) * 5.787 ps
8716 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
8719 int idx
= BEND_IDX(steps
);
8721 if (WARN_ON(steps
% 5 != 0))
8724 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
8727 mutex_lock(&dev_priv
->sb_lock
);
8729 if (steps
% 10 != 0)
8733 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
8735 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
8737 tmp
|= sscdivintphase
[idx
];
8738 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
8740 mutex_unlock(&dev_priv
->sb_lock
);
8745 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8747 struct intel_encoder
*encoder
;
8748 bool has_vga
= false;
8750 for_each_intel_encoder(dev
, encoder
) {
8751 switch (encoder
->type
) {
8752 case INTEL_OUTPUT_ANALOG
:
8761 lpt_bend_clkout_dp(to_i915(dev
), 0);
8762 lpt_enable_clkout_dp(dev
, true, true);
8764 lpt_disable_clkout_dp(dev
);
8769 * Initialize reference clocks when the driver loads
8771 void intel_init_pch_refclk(struct drm_device
*dev
)
8773 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8774 ironlake_init_pch_refclk(dev
);
8775 else if (HAS_PCH_LPT(dev
))
8776 lpt_init_pch_refclk(dev
);
8779 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8781 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8782 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8783 int pipe
= intel_crtc
->pipe
;
8788 switch (intel_crtc
->config
->pipe_bpp
) {
8790 val
|= PIPECONF_6BPC
;
8793 val
|= PIPECONF_8BPC
;
8796 val
|= PIPECONF_10BPC
;
8799 val
|= PIPECONF_12BPC
;
8802 /* Case prevented by intel_choose_pipe_bpp_dither. */
8806 if (intel_crtc
->config
->dither
)
8807 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8809 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8810 val
|= PIPECONF_INTERLACED_ILK
;
8812 val
|= PIPECONF_PROGRESSIVE
;
8814 if (intel_crtc
->config
->limited_color_range
)
8815 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8817 I915_WRITE(PIPECONF(pipe
), val
);
8818 POSTING_READ(PIPECONF(pipe
));
8821 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8823 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8824 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8825 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8828 if (IS_HASWELL(dev_priv
) && intel_crtc
->config
->dither
)
8829 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8831 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8832 val
|= PIPECONF_INTERLACED_ILK
;
8834 val
|= PIPECONF_PROGRESSIVE
;
8836 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8837 POSTING_READ(PIPECONF(cpu_transcoder
));
8840 static void haswell_set_pipemisc(struct drm_crtc
*crtc
)
8842 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
8843 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8845 if (IS_BROADWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 9) {
8848 switch (intel_crtc
->config
->pipe_bpp
) {
8850 val
|= PIPEMISC_DITHER_6_BPC
;
8853 val
|= PIPEMISC_DITHER_8_BPC
;
8856 val
|= PIPEMISC_DITHER_10_BPC
;
8859 val
|= PIPEMISC_DITHER_12_BPC
;
8862 /* Case prevented by pipe_config_set_bpp. */
8866 if (intel_crtc
->config
->dither
)
8867 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8869 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
8873 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8876 * Account for spread spectrum to avoid
8877 * oversubscribing the link. Max center spread
8878 * is 2.5%; use 5% for safety's sake.
8880 u32 bps
= target_clock
* bpp
* 21 / 20;
8881 return DIV_ROUND_UP(bps
, link_bw
* 8);
8884 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8886 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8889 static void ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8890 struct intel_crtc_state
*crtc_state
,
8891 struct dpll
*reduced_clock
)
8893 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8894 struct drm_device
*dev
= crtc
->dev
;
8895 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8899 /* Enable autotuning of the PLL clock (if permissible) */
8901 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8902 if ((intel_panel_use_ssc(dev_priv
) &&
8903 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8904 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8906 } else if (crtc_state
->sdvo_tv_clock
)
8909 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8911 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8914 if (reduced_clock
) {
8915 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
8917 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
8925 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
8926 dpll
|= DPLLB_MODE_LVDS
;
8928 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8930 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8931 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8933 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
8934 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
8935 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8937 if (intel_crtc_has_dp_encoder(crtc_state
))
8938 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8940 /* compute bitmask from p1 value */
8941 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8943 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8945 switch (crtc_state
->dpll
.p2
) {
8947 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8950 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8953 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8956 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8960 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
8961 intel_panel_use_ssc(dev_priv
))
8962 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8964 dpll
|= PLL_REF_INPUT_DREFCLK
;
8966 dpll
|= DPLL_VCO_ENABLE
;
8968 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8969 crtc_state
->dpll_hw_state
.fp0
= fp
;
8970 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8973 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8974 struct intel_crtc_state
*crtc_state
)
8976 struct drm_device
*dev
= crtc
->base
.dev
;
8977 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8978 struct dpll reduced_clock
;
8979 bool has_reduced_clock
= false;
8980 struct intel_shared_dpll
*pll
;
8981 const struct intel_limit
*limit
;
8982 int refclk
= 120000;
8984 memset(&crtc_state
->dpll_hw_state
, 0,
8985 sizeof(crtc_state
->dpll_hw_state
));
8987 crtc
->lowfreq_avail
= false;
8989 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8990 if (!crtc_state
->has_pch_encoder
)
8993 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8994 if (intel_panel_use_ssc(dev_priv
)) {
8995 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8996 dev_priv
->vbt
.lvds_ssc_freq
);
8997 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
9000 if (intel_is_dual_link_lvds(dev
)) {
9001 if (refclk
== 100000)
9002 limit
= &intel_limits_ironlake_dual_lvds_100m
;
9004 limit
= &intel_limits_ironlake_dual_lvds
;
9006 if (refclk
== 100000)
9007 limit
= &intel_limits_ironlake_single_lvds_100m
;
9009 limit
= &intel_limits_ironlake_single_lvds
;
9012 limit
= &intel_limits_ironlake_dac
;
9015 if (!crtc_state
->clock_set
&&
9016 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
9017 refclk
, NULL
, &crtc_state
->dpll
)) {
9018 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9022 ironlake_compute_dpll(crtc
, crtc_state
,
9023 has_reduced_clock
? &reduced_clock
: NULL
);
9025 pll
= intel_get_shared_dpll(crtc
, crtc_state
, NULL
);
9027 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9028 pipe_name(crtc
->pipe
));
9032 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9034 crtc
->lowfreq_avail
= true;
9039 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9040 struct intel_link_m_n
*m_n
)
9042 struct drm_device
*dev
= crtc
->base
.dev
;
9043 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9044 enum pipe pipe
= crtc
->pipe
;
9046 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9047 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9048 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9050 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9051 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9052 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9055 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9056 enum transcoder transcoder
,
9057 struct intel_link_m_n
*m_n
,
9058 struct intel_link_m_n
*m2_n2
)
9060 struct drm_device
*dev
= crtc
->base
.dev
;
9061 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9062 enum pipe pipe
= crtc
->pipe
;
9064 if (INTEL_INFO(dev
)->gen
>= 5) {
9065 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9066 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9067 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9069 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9070 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9071 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9072 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9073 * gen < 8) and if DRRS is supported (to make sure the
9074 * registers are not unnecessarily read).
9076 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
9077 crtc
->config
->has_drrs
) {
9078 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9079 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9080 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9082 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9083 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9084 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9087 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9088 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9089 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9091 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9092 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9093 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9097 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9098 struct intel_crtc_state
*pipe_config
)
9100 if (pipe_config
->has_pch_encoder
)
9101 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9103 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9104 &pipe_config
->dp_m_n
,
9105 &pipe_config
->dp_m2_n2
);
9108 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9109 struct intel_crtc_state
*pipe_config
)
9111 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9112 &pipe_config
->fdi_m_n
, NULL
);
9115 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9116 struct intel_crtc_state
*pipe_config
)
9118 struct drm_device
*dev
= crtc
->base
.dev
;
9119 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9120 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9121 uint32_t ps_ctrl
= 0;
9125 /* find scaler attached to this pipe */
9126 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9127 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9128 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9130 pipe_config
->pch_pfit
.enabled
= true;
9131 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9132 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9137 scaler_state
->scaler_id
= id
;
9139 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9141 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9146 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9147 struct intel_initial_plane_config
*plane_config
)
9149 struct drm_device
*dev
= crtc
->base
.dev
;
9150 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9151 u32 val
, base
, offset
, stride_mult
, tiling
;
9152 int pipe
= crtc
->pipe
;
9153 int fourcc
, pixel_format
;
9154 unsigned int aligned_height
;
9155 struct drm_framebuffer
*fb
;
9156 struct intel_framebuffer
*intel_fb
;
9158 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9160 DRM_DEBUG_KMS("failed to alloc fb\n");
9164 fb
= &intel_fb
->base
;
9166 val
= I915_READ(PLANE_CTL(pipe
, 0));
9167 if (!(val
& PLANE_CTL_ENABLE
))
9170 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9171 fourcc
= skl_format_to_fourcc(pixel_format
,
9172 val
& PLANE_CTL_ORDER_RGBX
,
9173 val
& PLANE_CTL_ALPHA_MASK
);
9174 fb
->pixel_format
= fourcc
;
9175 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9177 tiling
= val
& PLANE_CTL_TILED_MASK
;
9179 case PLANE_CTL_TILED_LINEAR
:
9180 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
9182 case PLANE_CTL_TILED_X
:
9183 plane_config
->tiling
= I915_TILING_X
;
9184 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9186 case PLANE_CTL_TILED_Y
:
9187 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
9189 case PLANE_CTL_TILED_YF
:
9190 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
9193 MISSING_CASE(tiling
);
9197 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9198 plane_config
->base
= base
;
9200 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9202 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9203 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9204 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9206 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9207 stride_mult
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
9209 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9211 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9215 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9217 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9218 pipe_name(pipe
), fb
->width
, fb
->height
,
9219 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9220 plane_config
->size
);
9222 plane_config
->fb
= intel_fb
;
9229 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9230 struct intel_crtc_state
*pipe_config
)
9232 struct drm_device
*dev
= crtc
->base
.dev
;
9233 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9236 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9238 if (tmp
& PF_ENABLE
) {
9239 pipe_config
->pch_pfit
.enabled
= true;
9240 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9241 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9243 /* We currently do not free assignements of panel fitters on
9244 * ivb/hsw (since we don't use the higher upscaling modes which
9245 * differentiates them) so just WARN about this case for now. */
9247 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9248 PF_PIPE_SEL_IVB(crtc
->pipe
));
9254 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9255 struct intel_initial_plane_config
*plane_config
)
9257 struct drm_device
*dev
= crtc
->base
.dev
;
9258 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9259 u32 val
, base
, offset
;
9260 int pipe
= crtc
->pipe
;
9261 int fourcc
, pixel_format
;
9262 unsigned int aligned_height
;
9263 struct drm_framebuffer
*fb
;
9264 struct intel_framebuffer
*intel_fb
;
9266 val
= I915_READ(DSPCNTR(pipe
));
9267 if (!(val
& DISPLAY_PLANE_ENABLE
))
9270 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9272 DRM_DEBUG_KMS("failed to alloc fb\n");
9276 fb
= &intel_fb
->base
;
9278 if (INTEL_INFO(dev
)->gen
>= 4) {
9279 if (val
& DISPPLANE_TILED
) {
9280 plane_config
->tiling
= I915_TILING_X
;
9281 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9285 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9286 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9287 fb
->pixel_format
= fourcc
;
9288 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9290 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9291 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9292 offset
= I915_READ(DSPOFFSET(pipe
));
9294 if (plane_config
->tiling
)
9295 offset
= I915_READ(DSPTILEOFF(pipe
));
9297 offset
= I915_READ(DSPLINOFF(pipe
));
9299 plane_config
->base
= base
;
9301 val
= I915_READ(PIPESRC(pipe
));
9302 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9303 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9305 val
= I915_READ(DSPSTRIDE(pipe
));
9306 fb
->pitches
[0] = val
& 0xffffffc0;
9308 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9312 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9314 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9315 pipe_name(pipe
), fb
->width
, fb
->height
,
9316 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9317 plane_config
->size
);
9319 plane_config
->fb
= intel_fb
;
9322 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9323 struct intel_crtc_state
*pipe_config
)
9325 struct drm_device
*dev
= crtc
->base
.dev
;
9326 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9327 enum intel_display_power_domain power_domain
;
9331 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9332 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9335 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9336 pipe_config
->shared_dpll
= NULL
;
9339 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9340 if (!(tmp
& PIPECONF_ENABLE
))
9343 switch (tmp
& PIPECONF_BPC_MASK
) {
9345 pipe_config
->pipe_bpp
= 18;
9348 pipe_config
->pipe_bpp
= 24;
9350 case PIPECONF_10BPC
:
9351 pipe_config
->pipe_bpp
= 30;
9353 case PIPECONF_12BPC
:
9354 pipe_config
->pipe_bpp
= 36;
9360 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9361 pipe_config
->limited_color_range
= true;
9363 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9364 struct intel_shared_dpll
*pll
;
9365 enum intel_dpll_id pll_id
;
9367 pipe_config
->has_pch_encoder
= true;
9369 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9370 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9371 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9373 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9375 if (HAS_PCH_IBX(dev_priv
)) {
9377 * The pipe->pch transcoder and pch transcoder->pll
9380 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9382 tmp
= I915_READ(PCH_DPLL_SEL
);
9383 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9384 pll_id
= DPLL_ID_PCH_PLL_B
;
9386 pll_id
= DPLL_ID_PCH_PLL_A
;
9389 pipe_config
->shared_dpll
=
9390 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
9391 pll
= pipe_config
->shared_dpll
;
9393 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
9394 &pipe_config
->dpll_hw_state
));
9396 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9397 pipe_config
->pixel_multiplier
=
9398 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9399 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9401 ironlake_pch_clock_get(crtc
, pipe_config
);
9403 pipe_config
->pixel_multiplier
= 1;
9406 intel_get_pipe_timings(crtc
, pipe_config
);
9407 intel_get_pipe_src_size(crtc
, pipe_config
);
9409 ironlake_get_pfit_config(crtc
, pipe_config
);
9414 intel_display_power_put(dev_priv
, power_domain
);
9419 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9421 struct drm_device
*dev
= &dev_priv
->drm
;
9422 struct intel_crtc
*crtc
;
9424 for_each_intel_crtc(dev
, crtc
)
9425 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9426 pipe_name(crtc
->pipe
));
9428 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9429 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9430 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9431 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9432 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9433 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9434 "CPU PWM1 enabled\n");
9435 if (IS_HASWELL(dev
))
9436 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9437 "CPU PWM2 enabled\n");
9438 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9439 "PCH PWM1 enabled\n");
9440 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9441 "Utility pin enabled\n");
9442 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9445 * In theory we can still leave IRQs enabled, as long as only the HPD
9446 * interrupts remain enabled. We used to check for that, but since it's
9447 * gen-specific and since we only disable LCPLL after we fully disable
9448 * the interrupts, the check below should be enough.
9450 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9453 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9455 struct drm_device
*dev
= &dev_priv
->drm
;
9457 if (IS_HASWELL(dev
))
9458 return I915_READ(D_COMP_HSW
);
9460 return I915_READ(D_COMP_BDW
);
9463 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9465 struct drm_device
*dev
= &dev_priv
->drm
;
9467 if (IS_HASWELL(dev
)) {
9468 mutex_lock(&dev_priv
->rps
.hw_lock
);
9469 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9471 DRM_ERROR("Failed to write to D_COMP\n");
9472 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9474 I915_WRITE(D_COMP_BDW
, val
);
9475 POSTING_READ(D_COMP_BDW
);
9480 * This function implements pieces of two sequences from BSpec:
9481 * - Sequence for display software to disable LCPLL
9482 * - Sequence for display software to allow package C8+
9483 * The steps implemented here are just the steps that actually touch the LCPLL
9484 * register. Callers should take care of disabling all the display engine
9485 * functions, doing the mode unset, fixing interrupts, etc.
9487 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9488 bool switch_to_fclk
, bool allow_power_down
)
9492 assert_can_disable_lcpll(dev_priv
);
9494 val
= I915_READ(LCPLL_CTL
);
9496 if (switch_to_fclk
) {
9497 val
|= LCPLL_CD_SOURCE_FCLK
;
9498 I915_WRITE(LCPLL_CTL
, val
);
9500 if (wait_for_us(I915_READ(LCPLL_CTL
) &
9501 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9502 DRM_ERROR("Switching to FCLK failed\n");
9504 val
= I915_READ(LCPLL_CTL
);
9507 val
|= LCPLL_PLL_DISABLE
;
9508 I915_WRITE(LCPLL_CTL
, val
);
9509 POSTING_READ(LCPLL_CTL
);
9511 if (intel_wait_for_register(dev_priv
, LCPLL_CTL
, LCPLL_PLL_LOCK
, 0, 1))
9512 DRM_ERROR("LCPLL still locked\n");
9514 val
= hsw_read_dcomp(dev_priv
);
9515 val
|= D_COMP_COMP_DISABLE
;
9516 hsw_write_dcomp(dev_priv
, val
);
9519 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9521 DRM_ERROR("D_COMP RCOMP still in progress\n");
9523 if (allow_power_down
) {
9524 val
= I915_READ(LCPLL_CTL
);
9525 val
|= LCPLL_POWER_DOWN_ALLOW
;
9526 I915_WRITE(LCPLL_CTL
, val
);
9527 POSTING_READ(LCPLL_CTL
);
9532 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9535 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9539 val
= I915_READ(LCPLL_CTL
);
9541 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9542 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9546 * Make sure we're not on PC8 state before disabling PC8, otherwise
9547 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9549 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9551 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9552 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9553 I915_WRITE(LCPLL_CTL
, val
);
9554 POSTING_READ(LCPLL_CTL
);
9557 val
= hsw_read_dcomp(dev_priv
);
9558 val
|= D_COMP_COMP_FORCE
;
9559 val
&= ~D_COMP_COMP_DISABLE
;
9560 hsw_write_dcomp(dev_priv
, val
);
9562 val
= I915_READ(LCPLL_CTL
);
9563 val
&= ~LCPLL_PLL_DISABLE
;
9564 I915_WRITE(LCPLL_CTL
, val
);
9566 if (intel_wait_for_register(dev_priv
,
9567 LCPLL_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
9569 DRM_ERROR("LCPLL not locked yet\n");
9571 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9572 val
= I915_READ(LCPLL_CTL
);
9573 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9574 I915_WRITE(LCPLL_CTL
, val
);
9576 if (wait_for_us((I915_READ(LCPLL_CTL
) &
9577 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9578 DRM_ERROR("Switching back to LCPLL failed\n");
9581 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9582 intel_update_cdclk(&dev_priv
->drm
);
9586 * Package states C8 and deeper are really deep PC states that can only be
9587 * reached when all the devices on the system allow it, so even if the graphics
9588 * device allows PC8+, it doesn't mean the system will actually get to these
9589 * states. Our driver only allows PC8+ when going into runtime PM.
9591 * The requirements for PC8+ are that all the outputs are disabled, the power
9592 * well is disabled and most interrupts are disabled, and these are also
9593 * requirements for runtime PM. When these conditions are met, we manually do
9594 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9595 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9598 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9599 * the state of some registers, so when we come back from PC8+ we need to
9600 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9601 * need to take care of the registers kept by RC6. Notice that this happens even
9602 * if we don't put the device in PCI D3 state (which is what currently happens
9603 * because of the runtime PM support).
9605 * For more, read "Display Sequences for Package C8" on the hardware
9608 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9610 struct drm_device
*dev
= &dev_priv
->drm
;
9613 DRM_DEBUG_KMS("Enabling package C8+\n");
9615 if (HAS_PCH_LPT_LP(dev
)) {
9616 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9617 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9618 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9621 lpt_disable_clkout_dp(dev
);
9622 hsw_disable_lcpll(dev_priv
, true, true);
9625 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9627 struct drm_device
*dev
= &dev_priv
->drm
;
9630 DRM_DEBUG_KMS("Disabling package C8+\n");
9632 hsw_restore_lcpll(dev_priv
);
9633 lpt_init_pch_refclk(dev
);
9635 if (HAS_PCH_LPT_LP(dev
)) {
9636 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9637 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9638 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9642 static void bxt_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9644 struct drm_device
*dev
= old_state
->dev
;
9645 struct intel_atomic_state
*old_intel_state
=
9646 to_intel_atomic_state(old_state
);
9647 unsigned int req_cdclk
= old_intel_state
->dev_cdclk
;
9649 bxt_set_cdclk(to_i915(dev
), req_cdclk
);
9652 /* compute the max rate for new configuration */
9653 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
)
9655 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9656 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9657 struct drm_crtc
*crtc
;
9658 struct drm_crtc_state
*cstate
;
9659 struct intel_crtc_state
*crtc_state
;
9660 unsigned max_pixel_rate
= 0, i
;
9663 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
9664 sizeof(intel_state
->min_pixclk
));
9666 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
9669 crtc_state
= to_intel_crtc_state(cstate
);
9670 if (!crtc_state
->base
.enable
) {
9671 intel_state
->min_pixclk
[i
] = 0;
9675 pixel_rate
= ilk_pipe_pixel_rate(crtc_state
);
9677 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9678 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
9679 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
9681 intel_state
->min_pixclk
[i
] = pixel_rate
;
9684 for_each_pipe(dev_priv
, pipe
)
9685 max_pixel_rate
= max(intel_state
->min_pixclk
[pipe
], max_pixel_rate
);
9687 return max_pixel_rate
;
9690 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
9692 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9696 if (WARN((I915_READ(LCPLL_CTL
) &
9697 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
9698 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
9699 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
9700 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
9701 "trying to change cdclk frequency with cdclk not enabled\n"))
9704 mutex_lock(&dev_priv
->rps
.hw_lock
);
9705 ret
= sandybridge_pcode_write(dev_priv
,
9706 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
9707 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9709 DRM_ERROR("failed to inform pcode about cdclk change\n");
9713 val
= I915_READ(LCPLL_CTL
);
9714 val
|= LCPLL_CD_SOURCE_FCLK
;
9715 I915_WRITE(LCPLL_CTL
, val
);
9717 if (wait_for_us(I915_READ(LCPLL_CTL
) &
9718 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9719 DRM_ERROR("Switching to FCLK failed\n");
9721 val
= I915_READ(LCPLL_CTL
);
9722 val
&= ~LCPLL_CLK_FREQ_MASK
;
9726 val
|= LCPLL_CLK_FREQ_450
;
9730 val
|= LCPLL_CLK_FREQ_54O_BDW
;
9734 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
9738 val
|= LCPLL_CLK_FREQ_675_BDW
;
9742 WARN(1, "invalid cdclk frequency\n");
9746 I915_WRITE(LCPLL_CTL
, val
);
9748 val
= I915_READ(LCPLL_CTL
);
9749 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9750 I915_WRITE(LCPLL_CTL
, val
);
9752 if (wait_for_us((I915_READ(LCPLL_CTL
) &
9753 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9754 DRM_ERROR("Switching back to LCPLL failed\n");
9756 mutex_lock(&dev_priv
->rps
.hw_lock
);
9757 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
9758 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9760 I915_WRITE(CDCLK_FREQ
, DIV_ROUND_CLOSEST(cdclk
, 1000) - 1);
9762 intel_update_cdclk(dev
);
9764 WARN(cdclk
!= dev_priv
->cdclk_freq
,
9765 "cdclk requested %d kHz but got %d kHz\n",
9766 cdclk
, dev_priv
->cdclk_freq
);
9769 static int broadwell_calc_cdclk(int max_pixclk
)
9771 if (max_pixclk
> 540000)
9773 else if (max_pixclk
> 450000)
9775 else if (max_pixclk
> 337500)
9781 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9783 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9784 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9785 int max_pixclk
= ilk_max_pixel_rate(state
);
9789 * FIXME should also account for plane ratio
9790 * once 64bpp pixel formats are supported.
9792 cdclk
= broadwell_calc_cdclk(max_pixclk
);
9794 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9795 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9796 cdclk
, dev_priv
->max_cdclk_freq
);
9800 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
9801 if (!intel_state
->active_crtcs
)
9802 intel_state
->dev_cdclk
= broadwell_calc_cdclk(0);
9807 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9809 struct drm_device
*dev
= old_state
->dev
;
9810 struct intel_atomic_state
*old_intel_state
=
9811 to_intel_atomic_state(old_state
);
9812 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
9814 broadwell_set_cdclk(dev
, req_cdclk
);
9817 static int skl_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9819 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
9820 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9821 const int max_pixclk
= ilk_max_pixel_rate(state
);
9822 int vco
= intel_state
->cdclk_pll_vco
;
9826 * FIXME should also account for plane ratio
9827 * once 64bpp pixel formats are supported.
9829 cdclk
= skl_calc_cdclk(max_pixclk
, vco
);
9832 * FIXME move the cdclk caclulation to
9833 * compute_config() so we can fail gracegully.
9835 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9836 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9837 cdclk
, dev_priv
->max_cdclk_freq
);
9838 cdclk
= dev_priv
->max_cdclk_freq
;
9841 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
9842 if (!intel_state
->active_crtcs
)
9843 intel_state
->dev_cdclk
= skl_calc_cdclk(0, vco
);
9848 static void skl_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9850 struct drm_i915_private
*dev_priv
= to_i915(old_state
->dev
);
9851 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(old_state
);
9852 unsigned int req_cdclk
= intel_state
->dev_cdclk
;
9853 unsigned int req_vco
= intel_state
->cdclk_pll_vco
;
9855 skl_set_cdclk(dev_priv
, req_cdclk
, req_vco
);
9858 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9859 struct intel_crtc_state
*crtc_state
)
9861 struct intel_encoder
*intel_encoder
=
9862 intel_ddi_get_crtc_new_encoder(crtc_state
);
9864 if (intel_encoder
->type
!= INTEL_OUTPUT_DSI
) {
9865 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9869 crtc
->lowfreq_avail
= false;
9874 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9876 struct intel_crtc_state
*pipe_config
)
9878 enum intel_dpll_id id
;
9882 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9883 id
= DPLL_ID_SKL_DPLL0
;
9886 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9887 id
= DPLL_ID_SKL_DPLL1
;
9890 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9891 id
= DPLL_ID_SKL_DPLL2
;
9894 DRM_ERROR("Incorrect port type\n");
9898 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9901 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9903 struct intel_crtc_state
*pipe_config
)
9905 enum intel_dpll_id id
;
9908 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9909 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9911 switch (pipe_config
->ddi_pll_sel
) {
9913 id
= DPLL_ID_SKL_DPLL0
;
9916 id
= DPLL_ID_SKL_DPLL1
;
9919 id
= DPLL_ID_SKL_DPLL2
;
9922 id
= DPLL_ID_SKL_DPLL3
;
9925 MISSING_CASE(pipe_config
->ddi_pll_sel
);
9929 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9932 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9934 struct intel_crtc_state
*pipe_config
)
9936 enum intel_dpll_id id
;
9938 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9940 switch (pipe_config
->ddi_pll_sel
) {
9941 case PORT_CLK_SEL_WRPLL1
:
9942 id
= DPLL_ID_WRPLL1
;
9944 case PORT_CLK_SEL_WRPLL2
:
9945 id
= DPLL_ID_WRPLL2
;
9947 case PORT_CLK_SEL_SPLL
:
9950 case PORT_CLK_SEL_LCPLL_810
:
9951 id
= DPLL_ID_LCPLL_810
;
9953 case PORT_CLK_SEL_LCPLL_1350
:
9954 id
= DPLL_ID_LCPLL_1350
;
9956 case PORT_CLK_SEL_LCPLL_2700
:
9957 id
= DPLL_ID_LCPLL_2700
;
9960 MISSING_CASE(pipe_config
->ddi_pll_sel
);
9962 case PORT_CLK_SEL_NONE
:
9966 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
9969 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
9970 struct intel_crtc_state
*pipe_config
,
9971 unsigned long *power_domain_mask
)
9973 struct drm_device
*dev
= crtc
->base
.dev
;
9974 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9975 enum intel_display_power_domain power_domain
;
9979 * The pipe->transcoder mapping is fixed with the exception of the eDP
9980 * transcoder handled below.
9982 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9985 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9986 * consistency and less surprising code; it's in always on power).
9988 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9989 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9990 enum pipe trans_edp_pipe
;
9991 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9993 WARN(1, "unknown pipe linked to edp transcoder\n");
9994 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9995 case TRANS_DDI_EDP_INPUT_A_ON
:
9996 trans_edp_pipe
= PIPE_A
;
9998 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9999 trans_edp_pipe
= PIPE_B
;
10001 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
10002 trans_edp_pipe
= PIPE_C
;
10006 if (trans_edp_pipe
== crtc
->pipe
)
10007 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
10010 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
10011 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10013 *power_domain_mask
|= BIT(power_domain
);
10015 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
10017 return tmp
& PIPECONF_ENABLE
;
10020 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
10021 struct intel_crtc_state
*pipe_config
,
10022 unsigned long *power_domain_mask
)
10024 struct drm_device
*dev
= crtc
->base
.dev
;
10025 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10026 enum intel_display_power_domain power_domain
;
10028 enum transcoder cpu_transcoder
;
10031 pipe_config
->has_dsi_encoder
= false;
10033 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
10034 if (port
== PORT_A
)
10035 cpu_transcoder
= TRANSCODER_DSI_A
;
10037 cpu_transcoder
= TRANSCODER_DSI_C
;
10039 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
10040 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10042 *power_domain_mask
|= BIT(power_domain
);
10045 * The PLL needs to be enabled with a valid divider
10046 * configuration, otherwise accessing DSI registers will hang
10047 * the machine. See BSpec North Display Engine
10048 * registers/MIPI[BXT]. We can break out here early, since we
10049 * need the same DSI PLL to be enabled for both DSI ports.
10051 if (!intel_dsi_pll_is_enabled(dev_priv
))
10054 /* XXX: this works for video mode only */
10055 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
10056 if (!(tmp
& DPI_ENABLE
))
10059 tmp
= I915_READ(MIPI_CTRL(port
));
10060 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
10063 pipe_config
->cpu_transcoder
= cpu_transcoder
;
10064 pipe_config
->has_dsi_encoder
= true;
10068 return pipe_config
->has_dsi_encoder
;
10071 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
10072 struct intel_crtc_state
*pipe_config
)
10074 struct drm_device
*dev
= crtc
->base
.dev
;
10075 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10076 struct intel_shared_dpll
*pll
;
10080 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
10082 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
10084 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
10085 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10086 else if (IS_BROXTON(dev
))
10087 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
10089 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
10091 pll
= pipe_config
->shared_dpll
;
10093 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
10094 &pipe_config
->dpll_hw_state
));
10098 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10099 * DDI E. So just check whether this pipe is wired to DDI E and whether
10100 * the PCH transcoder is on.
10102 if (INTEL_INFO(dev
)->gen
< 9 &&
10103 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
10104 pipe_config
->has_pch_encoder
= true;
10106 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
10107 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
10108 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
10110 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
10114 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
10115 struct intel_crtc_state
*pipe_config
)
10117 struct drm_device
*dev
= crtc
->base
.dev
;
10118 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10119 enum intel_display_power_domain power_domain
;
10120 unsigned long power_domain_mask
;
10123 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
10124 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10126 power_domain_mask
= BIT(power_domain
);
10128 pipe_config
->shared_dpll
= NULL
;
10130 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &power_domain_mask
);
10132 if (IS_BROXTON(dev_priv
)) {
10133 bxt_get_dsi_transcoder_state(crtc
, pipe_config
,
10134 &power_domain_mask
);
10135 WARN_ON(active
&& pipe_config
->has_dsi_encoder
);
10136 if (pipe_config
->has_dsi_encoder
)
10143 if (!pipe_config
->has_dsi_encoder
) {
10144 haswell_get_ddi_port_state(crtc
, pipe_config
);
10145 intel_get_pipe_timings(crtc
, pipe_config
);
10148 intel_get_pipe_src_size(crtc
, pipe_config
);
10150 pipe_config
->gamma_mode
=
10151 I915_READ(GAMMA_MODE(crtc
->pipe
)) & GAMMA_MODE_MODE_MASK
;
10153 if (INTEL_INFO(dev
)->gen
>= 9) {
10154 skl_init_scalers(dev
, crtc
, pipe_config
);
10157 if (INTEL_INFO(dev
)->gen
>= 9) {
10158 pipe_config
->scaler_state
.scaler_id
= -1;
10159 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
10162 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
10163 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
10164 power_domain_mask
|= BIT(power_domain
);
10165 if (INTEL_INFO(dev
)->gen
>= 9)
10166 skylake_get_pfit_config(crtc
, pipe_config
);
10168 ironlake_get_pfit_config(crtc
, pipe_config
);
10171 if (IS_HASWELL(dev
))
10172 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
10173 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
10175 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10176 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10177 pipe_config
->pixel_multiplier
=
10178 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10180 pipe_config
->pixel_multiplier
= 1;
10184 for_each_power_domain(power_domain
, power_domain_mask
)
10185 intel_display_power_put(dev_priv
, power_domain
);
10190 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10191 const struct intel_plane_state
*plane_state
)
10193 struct drm_device
*dev
= crtc
->dev
;
10194 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10195 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10196 uint32_t cntl
= 0, size
= 0;
10198 if (plane_state
&& plane_state
->visible
) {
10199 unsigned int width
= plane_state
->base
.crtc_w
;
10200 unsigned int height
= plane_state
->base
.crtc_h
;
10201 unsigned int stride
= roundup_pow_of_two(width
) * 4;
10205 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10216 cntl
|= CURSOR_ENABLE
|
10217 CURSOR_GAMMA_ENABLE
|
10218 CURSOR_FORMAT_ARGB
|
10219 CURSOR_STRIDE(stride
);
10221 size
= (height
<< 12) | width
;
10224 if (intel_crtc
->cursor_cntl
!= 0 &&
10225 (intel_crtc
->cursor_base
!= base
||
10226 intel_crtc
->cursor_size
!= size
||
10227 intel_crtc
->cursor_cntl
!= cntl
)) {
10228 /* On these chipsets we can only modify the base/size/stride
10229 * whilst the cursor is disabled.
10231 I915_WRITE(CURCNTR(PIPE_A
), 0);
10232 POSTING_READ(CURCNTR(PIPE_A
));
10233 intel_crtc
->cursor_cntl
= 0;
10236 if (intel_crtc
->cursor_base
!= base
) {
10237 I915_WRITE(CURBASE(PIPE_A
), base
);
10238 intel_crtc
->cursor_base
= base
;
10241 if (intel_crtc
->cursor_size
!= size
) {
10242 I915_WRITE(CURSIZE
, size
);
10243 intel_crtc
->cursor_size
= size
;
10246 if (intel_crtc
->cursor_cntl
!= cntl
) {
10247 I915_WRITE(CURCNTR(PIPE_A
), cntl
);
10248 POSTING_READ(CURCNTR(PIPE_A
));
10249 intel_crtc
->cursor_cntl
= cntl
;
10253 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10254 const struct intel_plane_state
*plane_state
)
10256 struct drm_device
*dev
= crtc
->dev
;
10257 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10258 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10259 int pipe
= intel_crtc
->pipe
;
10262 if (plane_state
&& plane_state
->visible
) {
10263 cntl
= MCURSOR_GAMMA_ENABLE
;
10264 switch (plane_state
->base
.crtc_w
) {
10266 cntl
|= CURSOR_MODE_64_ARGB_AX
;
10269 cntl
|= CURSOR_MODE_128_ARGB_AX
;
10272 cntl
|= CURSOR_MODE_256_ARGB_AX
;
10275 MISSING_CASE(plane_state
->base
.crtc_w
);
10278 cntl
|= pipe
<< 28; /* Connect to correct pipe */
10281 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
10283 if (plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
))
10284 cntl
|= CURSOR_ROTATE_180
;
10287 if (intel_crtc
->cursor_cntl
!= cntl
) {
10288 I915_WRITE(CURCNTR(pipe
), cntl
);
10289 POSTING_READ(CURCNTR(pipe
));
10290 intel_crtc
->cursor_cntl
= cntl
;
10293 /* and commit changes on next vblank */
10294 I915_WRITE(CURBASE(pipe
), base
);
10295 POSTING_READ(CURBASE(pipe
));
10297 intel_crtc
->cursor_base
= base
;
10300 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10301 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
10302 const struct intel_plane_state
*plane_state
)
10304 struct drm_device
*dev
= crtc
->dev
;
10305 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10306 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10307 int pipe
= intel_crtc
->pipe
;
10308 u32 base
= intel_crtc
->cursor_addr
;
10312 int x
= plane_state
->base
.crtc_x
;
10313 int y
= plane_state
->base
.crtc_y
;
10316 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10319 pos
|= x
<< CURSOR_X_SHIFT
;
10322 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10325 pos
|= y
<< CURSOR_Y_SHIFT
;
10327 /* ILK+ do this automagically */
10328 if (HAS_GMCH_DISPLAY(dev
) &&
10329 plane_state
->base
.rotation
== BIT(DRM_ROTATE_180
)) {
10330 base
+= (plane_state
->base
.crtc_h
*
10331 plane_state
->base
.crtc_w
- 1) * 4;
10335 I915_WRITE(CURPOS(pipe
), pos
);
10337 if (IS_845G(dev
) || IS_I865G(dev
))
10338 i845_update_cursor(crtc
, base
, plane_state
);
10340 i9xx_update_cursor(crtc
, base
, plane_state
);
10343 static bool cursor_size_ok(struct drm_device
*dev
,
10344 uint32_t width
, uint32_t height
)
10346 if (width
== 0 || height
== 0)
10350 * 845g/865g are special in that they are only limited by
10351 * the width of their cursors, the height is arbitrary up to
10352 * the precision of the register. Everything else requires
10353 * square cursors, limited to a few power-of-two sizes.
10355 if (IS_845G(dev
) || IS_I865G(dev
)) {
10356 if ((width
& 63) != 0)
10359 if (width
> (IS_845G(dev
) ? 64 : 512))
10365 switch (width
| height
) {
10380 /* VESA 640x480x72Hz mode to set on the pipe */
10381 static struct drm_display_mode load_detect_mode
= {
10382 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10383 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10386 struct drm_framebuffer
*
10387 __intel_framebuffer_create(struct drm_device
*dev
,
10388 struct drm_mode_fb_cmd2
*mode_cmd
,
10389 struct drm_i915_gem_object
*obj
)
10391 struct intel_framebuffer
*intel_fb
;
10394 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10396 return ERR_PTR(-ENOMEM
);
10398 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10402 return &intel_fb
->base
;
10406 return ERR_PTR(ret
);
10409 static struct drm_framebuffer
*
10410 intel_framebuffer_create(struct drm_device
*dev
,
10411 struct drm_mode_fb_cmd2
*mode_cmd
,
10412 struct drm_i915_gem_object
*obj
)
10414 struct drm_framebuffer
*fb
;
10417 ret
= i915_mutex_lock_interruptible(dev
);
10419 return ERR_PTR(ret
);
10420 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
10421 mutex_unlock(&dev
->struct_mutex
);
10427 intel_framebuffer_pitch_for_width(int width
, int bpp
)
10429 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
10430 return ALIGN(pitch
, 64);
10434 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
10436 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
10437 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
10440 static struct drm_framebuffer
*
10441 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
10442 struct drm_display_mode
*mode
,
10443 int depth
, int bpp
)
10445 struct drm_framebuffer
*fb
;
10446 struct drm_i915_gem_object
*obj
;
10447 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
10449 obj
= i915_gem_object_create(dev
,
10450 intel_framebuffer_size_for_mode(mode
, bpp
));
10452 return ERR_CAST(obj
);
10454 mode_cmd
.width
= mode
->hdisplay
;
10455 mode_cmd
.height
= mode
->vdisplay
;
10456 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
10458 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
10460 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
10462 drm_gem_object_unreference_unlocked(&obj
->base
);
10467 static struct drm_framebuffer
*
10468 mode_fits_in_fbdev(struct drm_device
*dev
,
10469 struct drm_display_mode
*mode
)
10471 #ifdef CONFIG_DRM_FBDEV_EMULATION
10472 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10473 struct drm_i915_gem_object
*obj
;
10474 struct drm_framebuffer
*fb
;
10476 if (!dev_priv
->fbdev
)
10479 if (!dev_priv
->fbdev
->fb
)
10482 obj
= dev_priv
->fbdev
->fb
->obj
;
10485 fb
= &dev_priv
->fbdev
->fb
->base
;
10486 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
10487 fb
->bits_per_pixel
))
10490 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
10493 drm_framebuffer_reference(fb
);
10500 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
10501 struct drm_crtc
*crtc
,
10502 struct drm_display_mode
*mode
,
10503 struct drm_framebuffer
*fb
,
10506 struct drm_plane_state
*plane_state
;
10507 int hdisplay
, vdisplay
;
10510 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
10511 if (IS_ERR(plane_state
))
10512 return PTR_ERR(plane_state
);
10515 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
10517 hdisplay
= vdisplay
= 0;
10519 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
10522 drm_atomic_set_fb_for_plane(plane_state
, fb
);
10523 plane_state
->crtc_x
= 0;
10524 plane_state
->crtc_y
= 0;
10525 plane_state
->crtc_w
= hdisplay
;
10526 plane_state
->crtc_h
= vdisplay
;
10527 plane_state
->src_x
= x
<< 16;
10528 plane_state
->src_y
= y
<< 16;
10529 plane_state
->src_w
= hdisplay
<< 16;
10530 plane_state
->src_h
= vdisplay
<< 16;
10535 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
10536 struct drm_display_mode
*mode
,
10537 struct intel_load_detect_pipe
*old
,
10538 struct drm_modeset_acquire_ctx
*ctx
)
10540 struct intel_crtc
*intel_crtc
;
10541 struct intel_encoder
*intel_encoder
=
10542 intel_attached_encoder(connector
);
10543 struct drm_crtc
*possible_crtc
;
10544 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10545 struct drm_crtc
*crtc
= NULL
;
10546 struct drm_device
*dev
= encoder
->dev
;
10547 struct drm_framebuffer
*fb
;
10548 struct drm_mode_config
*config
= &dev
->mode_config
;
10549 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
10550 struct drm_connector_state
*connector_state
;
10551 struct intel_crtc_state
*crtc_state
;
10554 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10555 connector
->base
.id
, connector
->name
,
10556 encoder
->base
.id
, encoder
->name
);
10558 old
->restore_state
= NULL
;
10561 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
10566 * Algorithm gets a little messy:
10568 * - if the connector already has an assigned crtc, use it (but make
10569 * sure it's on first)
10571 * - try to find the first unused crtc that can drive this connector,
10572 * and use that if we find one
10575 /* See if we already have a CRTC for this connector */
10576 if (connector
->state
->crtc
) {
10577 crtc
= connector
->state
->crtc
;
10579 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10583 /* Make sure the crtc and connector are running */
10587 /* Find an unused one (if possible) */
10588 for_each_crtc(dev
, possible_crtc
) {
10590 if (!(encoder
->possible_crtcs
& (1 << i
)))
10593 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
10597 if (possible_crtc
->state
->enable
) {
10598 drm_modeset_unlock(&possible_crtc
->mutex
);
10602 crtc
= possible_crtc
;
10607 * If we didn't find an unused CRTC, don't use any.
10610 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10615 intel_crtc
= to_intel_crtc(crtc
);
10617 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10621 state
= drm_atomic_state_alloc(dev
);
10622 restore_state
= drm_atomic_state_alloc(dev
);
10623 if (!state
|| !restore_state
) {
10628 state
->acquire_ctx
= ctx
;
10629 restore_state
->acquire_ctx
= ctx
;
10631 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10632 if (IS_ERR(connector_state
)) {
10633 ret
= PTR_ERR(connector_state
);
10637 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
10641 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10642 if (IS_ERR(crtc_state
)) {
10643 ret
= PTR_ERR(crtc_state
);
10647 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10650 mode
= &load_detect_mode
;
10652 /* We need a framebuffer large enough to accommodate all accesses
10653 * that the plane may generate whilst we perform load detection.
10654 * We can not rely on the fbcon either being present (we get called
10655 * during its initialisation to detect all boot displays, or it may
10656 * not even exist) or that it is large enough to satisfy the
10659 fb
= mode_fits_in_fbdev(dev
, mode
);
10661 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10662 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10664 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10666 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10670 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10674 drm_framebuffer_unreference(fb
);
10676 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
10680 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
10682 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
10684 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state
, crtc
->primary
));
10686 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
10690 ret
= drm_atomic_commit(state
);
10692 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10696 old
->restore_state
= restore_state
;
10698 /* let the connector get through one full cycle before testing */
10699 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10703 drm_atomic_state_free(state
);
10704 drm_atomic_state_free(restore_state
);
10705 restore_state
= state
= NULL
;
10707 if (ret
== -EDEADLK
) {
10708 drm_modeset_backoff(ctx
);
10715 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10716 struct intel_load_detect_pipe
*old
,
10717 struct drm_modeset_acquire_ctx
*ctx
)
10719 struct intel_encoder
*intel_encoder
=
10720 intel_attached_encoder(connector
);
10721 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10722 struct drm_atomic_state
*state
= old
->restore_state
;
10725 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10726 connector
->base
.id
, connector
->name
,
10727 encoder
->base
.id
, encoder
->name
);
10732 ret
= drm_atomic_commit(state
);
10734 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
10735 drm_atomic_state_free(state
);
10739 static int i9xx_pll_refclk(struct drm_device
*dev
,
10740 const struct intel_crtc_state
*pipe_config
)
10742 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10743 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10745 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10746 return dev_priv
->vbt
.lvds_ssc_freq
;
10747 else if (HAS_PCH_SPLIT(dev
))
10749 else if (!IS_GEN2(dev
))
10755 /* Returns the clock of the currently programmed mode of the given pipe. */
10756 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10757 struct intel_crtc_state
*pipe_config
)
10759 struct drm_device
*dev
= crtc
->base
.dev
;
10760 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10761 int pipe
= pipe_config
->cpu_transcoder
;
10762 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10766 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10768 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10769 fp
= pipe_config
->dpll_hw_state
.fp0
;
10771 fp
= pipe_config
->dpll_hw_state
.fp1
;
10773 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10774 if (IS_PINEVIEW(dev
)) {
10775 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10776 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10778 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10779 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10782 if (!IS_GEN2(dev
)) {
10783 if (IS_PINEVIEW(dev
))
10784 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10785 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10787 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10788 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10790 switch (dpll
& DPLL_MODE_MASK
) {
10791 case DPLLB_MODE_DAC_SERIAL
:
10792 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10795 case DPLLB_MODE_LVDS
:
10796 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10800 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10801 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10805 if (IS_PINEVIEW(dev
))
10806 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10808 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10810 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10811 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10814 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10815 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10817 if (lvds
& LVDS_CLKB_POWER_UP
)
10822 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10825 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10826 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10828 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10834 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10838 * This value includes pixel_multiplier. We will use
10839 * port_clock to compute adjusted_mode.crtc_clock in the
10840 * encoder's get_config() function.
10842 pipe_config
->port_clock
= port_clock
;
10845 int intel_dotclock_calculate(int link_freq
,
10846 const struct intel_link_m_n
*m_n
)
10849 * The calculation for the data clock is:
10850 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10851 * But we want to avoid losing precison if possible, so:
10852 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10854 * and the link clock is simpler:
10855 * link_clock = (m * link_clock) / n
10861 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10864 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10865 struct intel_crtc_state
*pipe_config
)
10867 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10869 /* read out port_clock from the DPLL */
10870 i9xx_crtc_clock_get(crtc
, pipe_config
);
10873 * In case there is an active pipe without active ports,
10874 * we may need some idea for the dotclock anyway.
10875 * Calculate one based on the FDI configuration.
10877 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10878 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
10879 &pipe_config
->fdi_m_n
);
10882 /** Returns the currently programmed mode of the given pipe. */
10883 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10884 struct drm_crtc
*crtc
)
10886 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10887 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10888 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10889 struct drm_display_mode
*mode
;
10890 struct intel_crtc_state
*pipe_config
;
10891 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10892 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10893 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10894 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10895 enum pipe pipe
= intel_crtc
->pipe
;
10897 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10901 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10902 if (!pipe_config
) {
10908 * Construct a pipe_config sufficient for getting the clock info
10909 * back out of crtc_clock_get.
10911 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10912 * to use a real value here instead.
10914 pipe_config
->cpu_transcoder
= (enum transcoder
) pipe
;
10915 pipe_config
->pixel_multiplier
= 1;
10916 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10917 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10918 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10919 i9xx_crtc_clock_get(intel_crtc
, pipe_config
);
10921 mode
->clock
= pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
10922 mode
->hdisplay
= (htot
& 0xffff) + 1;
10923 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10924 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10925 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10926 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10927 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10928 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10929 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10931 drm_mode_set_name(mode
);
10933 kfree(pipe_config
);
10938 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10940 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10941 struct drm_device
*dev
= crtc
->dev
;
10942 struct intel_flip_work
*work
;
10944 spin_lock_irq(&dev
->event_lock
);
10945 work
= intel_crtc
->flip_work
;
10946 intel_crtc
->flip_work
= NULL
;
10947 spin_unlock_irq(&dev
->event_lock
);
10950 cancel_work_sync(&work
->mmio_work
);
10951 cancel_work_sync(&work
->unpin_work
);
10955 drm_crtc_cleanup(crtc
);
10960 static void intel_unpin_work_fn(struct work_struct
*__work
)
10962 struct intel_flip_work
*work
=
10963 container_of(__work
, struct intel_flip_work
, unpin_work
);
10964 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
10965 struct drm_device
*dev
= crtc
->base
.dev
;
10966 struct drm_plane
*primary
= crtc
->base
.primary
;
10968 if (is_mmio_work(work
))
10969 flush_work(&work
->mmio_work
);
10971 mutex_lock(&dev
->struct_mutex
);
10972 intel_unpin_fb_obj(work
->old_fb
, primary
->state
->rotation
);
10973 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10975 if (work
->flip_queued_req
)
10976 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10977 mutex_unlock(&dev
->struct_mutex
);
10979 intel_frontbuffer_flip_complete(dev
, to_intel_plane(primary
)->frontbuffer_bit
);
10980 intel_fbc_post_update(crtc
);
10981 drm_framebuffer_unreference(work
->old_fb
);
10983 BUG_ON(atomic_read(&crtc
->unpin_work_count
) == 0);
10984 atomic_dec(&crtc
->unpin_work_count
);
10989 /* Is 'a' after or equal to 'b'? */
10990 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10992 return !((a
- b
) & 0x80000000);
10995 static bool __pageflip_finished_cs(struct intel_crtc
*crtc
,
10996 struct intel_flip_work
*work
)
10998 struct drm_device
*dev
= crtc
->base
.dev
;
10999 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11000 unsigned reset_counter
;
11002 reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
11003 if (crtc
->reset_counter
!= reset_counter
)
11007 * The relevant registers doen't exist on pre-ctg.
11008 * As the flip done interrupt doesn't trigger for mmio
11009 * flips on gmch platforms, a flip count check isn't
11010 * really needed there. But since ctg has the registers,
11011 * include it in the check anyway.
11013 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
11017 * BDW signals flip done immediately if the plane
11018 * is disabled, even if the plane enable is already
11019 * armed to occur at the next vblank :(
11023 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11024 * used the same base address. In that case the mmio flip might
11025 * have completed, but the CS hasn't even executed the flip yet.
11027 * A flip count check isn't enough as the CS might have updated
11028 * the base address just after start of vblank, but before we
11029 * managed to process the interrupt. This means we'd complete the
11030 * CS flip too soon.
11032 * Combining both checks should get us a good enough result. It may
11033 * still happen that the CS flip has been executed, but has not
11034 * yet actually completed. But in case the base address is the same
11035 * anyway, we don't really care.
11037 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
11038 crtc
->flip_work
->gtt_offset
&&
11039 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc
->pipe
)),
11040 crtc
->flip_work
->flip_count
);
11044 __pageflip_finished_mmio(struct intel_crtc
*crtc
,
11045 struct intel_flip_work
*work
)
11048 * MMIO work completes when vblank is different from
11049 * flip_queued_vblank.
11051 * Reset counter value doesn't matter, this is handled by
11052 * i915_wait_request finishing early, so no need to handle
11055 return intel_crtc_get_vblank_counter(crtc
) != work
->flip_queued_vblank
;
11059 static bool pageflip_finished(struct intel_crtc
*crtc
,
11060 struct intel_flip_work
*work
)
11062 if (!atomic_read(&work
->pending
))
11067 if (is_mmio_work(work
))
11068 return __pageflip_finished_mmio(crtc
, work
);
11070 return __pageflip_finished_cs(crtc
, work
);
11073 void intel_finish_page_flip_cs(struct drm_i915_private
*dev_priv
, int pipe
)
11075 struct drm_device
*dev
= &dev_priv
->drm
;
11076 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11077 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11078 struct intel_flip_work
*work
;
11079 unsigned long flags
;
11081 /* Ignore early vblank irqs */
11086 * This is called both by irq handlers and the reset code (to complete
11087 * lost pageflips) so needs the full irqsave spinlocks.
11089 spin_lock_irqsave(&dev
->event_lock
, flags
);
11090 work
= intel_crtc
->flip_work
;
11092 if (work
!= NULL
&&
11093 !is_mmio_work(work
) &&
11094 pageflip_finished(intel_crtc
, work
))
11095 page_flip_completed(intel_crtc
);
11097 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11100 void intel_finish_page_flip_mmio(struct drm_i915_private
*dev_priv
, int pipe
)
11102 struct drm_device
*dev
= &dev_priv
->drm
;
11103 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11104 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11105 struct intel_flip_work
*work
;
11106 unsigned long flags
;
11108 /* Ignore early vblank irqs */
11113 * This is called both by irq handlers and the reset code (to complete
11114 * lost pageflips) so needs the full irqsave spinlocks.
11116 spin_lock_irqsave(&dev
->event_lock
, flags
);
11117 work
= intel_crtc
->flip_work
;
11119 if (work
!= NULL
&&
11120 is_mmio_work(work
) &&
11121 pageflip_finished(intel_crtc
, work
))
11122 page_flip_completed(intel_crtc
);
11124 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11127 static inline void intel_mark_page_flip_active(struct intel_crtc
*crtc
,
11128 struct intel_flip_work
*work
)
11130 work
->flip_queued_vblank
= intel_crtc_get_vblank_counter(crtc
);
11132 /* Ensure that the work item is consistent when activating it ... */
11133 smp_mb__before_atomic();
11134 atomic_set(&work
->pending
, 1);
11137 static int intel_gen2_queue_flip(struct drm_device
*dev
,
11138 struct drm_crtc
*crtc
,
11139 struct drm_framebuffer
*fb
,
11140 struct drm_i915_gem_object
*obj
,
11141 struct drm_i915_gem_request
*req
,
11144 struct intel_engine_cs
*engine
= req
->engine
;
11145 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11149 ret
= intel_ring_begin(req
, 6);
11153 /* Can't queue multiple flips, so wait for the previous
11154 * one to finish before executing the next.
11156 if (intel_crtc
->plane
)
11157 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11159 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11160 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| flip_mask
);
11161 intel_ring_emit(engine
, MI_NOOP
);
11162 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11163 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11164 intel_ring_emit(engine
, fb
->pitches
[0]);
11165 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11166 intel_ring_emit(engine
, 0); /* aux display base address, unused */
11171 static int intel_gen3_queue_flip(struct drm_device
*dev
,
11172 struct drm_crtc
*crtc
,
11173 struct drm_framebuffer
*fb
,
11174 struct drm_i915_gem_object
*obj
,
11175 struct drm_i915_gem_request
*req
,
11178 struct intel_engine_cs
*engine
= req
->engine
;
11179 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11183 ret
= intel_ring_begin(req
, 6);
11187 if (intel_crtc
->plane
)
11188 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11190 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11191 intel_ring_emit(engine
, MI_WAIT_FOR_EVENT
| flip_mask
);
11192 intel_ring_emit(engine
, MI_NOOP
);
11193 intel_ring_emit(engine
, MI_DISPLAY_FLIP_I915
|
11194 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11195 intel_ring_emit(engine
, fb
->pitches
[0]);
11196 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11197 intel_ring_emit(engine
, MI_NOOP
);
11202 static int intel_gen4_queue_flip(struct drm_device
*dev
,
11203 struct drm_crtc
*crtc
,
11204 struct drm_framebuffer
*fb
,
11205 struct drm_i915_gem_object
*obj
,
11206 struct drm_i915_gem_request
*req
,
11209 struct intel_engine_cs
*engine
= req
->engine
;
11210 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11211 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11212 uint32_t pf
, pipesrc
;
11215 ret
= intel_ring_begin(req
, 4);
11219 /* i965+ uses the linear or tiled offsets from the
11220 * Display Registers (which do not change across a page-flip)
11221 * so we need only reprogram the base address.
11223 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11224 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11225 intel_ring_emit(engine
, fb
->pitches
[0]);
11226 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
|
11229 /* XXX Enabling the panel-fitter across page-flip is so far
11230 * untested on non-native modes, so ignore it for now.
11231 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11234 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11235 intel_ring_emit(engine
, pf
| pipesrc
);
11240 static int intel_gen6_queue_flip(struct drm_device
*dev
,
11241 struct drm_crtc
*crtc
,
11242 struct drm_framebuffer
*fb
,
11243 struct drm_i915_gem_object
*obj
,
11244 struct drm_i915_gem_request
*req
,
11247 struct intel_engine_cs
*engine
= req
->engine
;
11248 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11249 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11250 uint32_t pf
, pipesrc
;
11253 ret
= intel_ring_begin(req
, 4);
11257 intel_ring_emit(engine
, MI_DISPLAY_FLIP
|
11258 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11259 intel_ring_emit(engine
, fb
->pitches
[0] | obj
->tiling_mode
);
11260 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11262 /* Contrary to the suggestions in the documentation,
11263 * "Enable Panel Fitter" does not seem to be required when page
11264 * flipping with a non-native mode, and worse causes a normal
11266 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11269 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11270 intel_ring_emit(engine
, pf
| pipesrc
);
11275 static int intel_gen7_queue_flip(struct drm_device
*dev
,
11276 struct drm_crtc
*crtc
,
11277 struct drm_framebuffer
*fb
,
11278 struct drm_i915_gem_object
*obj
,
11279 struct drm_i915_gem_request
*req
,
11282 struct intel_engine_cs
*engine
= req
->engine
;
11283 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11284 uint32_t plane_bit
= 0;
11287 switch (intel_crtc
->plane
) {
11289 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11292 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11295 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11298 WARN_ONCE(1, "unknown plane in flip command\n");
11303 if (engine
->id
== RCS
) {
11306 * On Gen 8, SRM is now taking an extra dword to accommodate
11307 * 48bits addresses, and we need a NOOP for the batch size to
11315 * BSpec MI_DISPLAY_FLIP for IVB:
11316 * "The full packet must be contained within the same cache line."
11318 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11319 * cacheline, if we ever start emitting more commands before
11320 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11321 * then do the cacheline alignment, and finally emit the
11324 ret
= intel_ring_cacheline_align(req
);
11328 ret
= intel_ring_begin(req
, len
);
11332 /* Unmask the flip-done completion message. Note that the bspec says that
11333 * we should do this for both the BCS and RCS, and that we must not unmask
11334 * more than one flip event at any time (or ensure that one flip message
11335 * can be sent by waiting for flip-done prior to queueing new flips).
11336 * Experimentation says that BCS works despite DERRMR masking all
11337 * flip-done completion events and that unmasking all planes at once
11338 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11339 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11341 if (engine
->id
== RCS
) {
11342 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
11343 intel_ring_emit_reg(engine
, DERRMR
);
11344 intel_ring_emit(engine
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11345 DERRMR_PIPEB_PRI_FLIP_DONE
|
11346 DERRMR_PIPEC_PRI_FLIP_DONE
));
11348 intel_ring_emit(engine
, MI_STORE_REGISTER_MEM_GEN8
|
11349 MI_SRM_LRM_GLOBAL_GTT
);
11351 intel_ring_emit(engine
, MI_STORE_REGISTER_MEM
|
11352 MI_SRM_LRM_GLOBAL_GTT
);
11353 intel_ring_emit_reg(engine
, DERRMR
);
11354 intel_ring_emit(engine
, engine
->scratch
.gtt_offset
+ 256);
11355 if (IS_GEN8(dev
)) {
11356 intel_ring_emit(engine
, 0);
11357 intel_ring_emit(engine
, MI_NOOP
);
11361 intel_ring_emit(engine
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11362 intel_ring_emit(engine
, (fb
->pitches
[0] | obj
->tiling_mode
));
11363 intel_ring_emit(engine
, intel_crtc
->flip_work
->gtt_offset
);
11364 intel_ring_emit(engine
, (MI_NOOP
));
11369 static bool use_mmio_flip(struct intel_engine_cs
*engine
,
11370 struct drm_i915_gem_object
*obj
)
11372 struct reservation_object
*resv
;
11375 * This is not being used for older platforms, because
11376 * non-availability of flip done interrupt forces us to use
11377 * CS flips. Older platforms derive flip done using some clever
11378 * tricks involving the flip_pending status bits and vblank irqs.
11379 * So using MMIO flips there would disrupt this mechanism.
11382 if (engine
== NULL
)
11385 if (INTEL_GEN(engine
->i915
) < 5)
11388 if (i915
.use_mmio_flip
< 0)
11390 else if (i915
.use_mmio_flip
> 0)
11392 else if (i915
.enable_execlists
)
11395 resv
= i915_gem_object_get_dmabuf_resv(obj
);
11396 if (resv
&& !reservation_object_test_signaled_rcu(resv
, false))
11399 return engine
!= i915_gem_request_get_engine(obj
->last_write_req
);
11402 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11403 unsigned int rotation
,
11404 struct intel_flip_work
*work
)
11406 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11407 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11408 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11409 const enum pipe pipe
= intel_crtc
->pipe
;
11410 u32 ctl
, stride
, tile_height
;
11412 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
11413 ctl
&= ~PLANE_CTL_TILED_MASK
;
11414 switch (fb
->modifier
[0]) {
11415 case DRM_FORMAT_MOD_NONE
:
11417 case I915_FORMAT_MOD_X_TILED
:
11418 ctl
|= PLANE_CTL_TILED_X
;
11420 case I915_FORMAT_MOD_Y_TILED
:
11421 ctl
|= PLANE_CTL_TILED_Y
;
11423 case I915_FORMAT_MOD_Yf_TILED
:
11424 ctl
|= PLANE_CTL_TILED_YF
;
11427 MISSING_CASE(fb
->modifier
[0]);
11431 * The stride is either expressed as a multiple of 64 bytes chunks for
11432 * linear buffers or in number of tiles for tiled buffers.
11434 if (intel_rotation_90_or_270(rotation
)) {
11435 /* stride = Surface height in tiles */
11436 tile_height
= intel_tile_height(dev_priv
, fb
->modifier
[0], 0);
11437 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
11439 stride
= fb
->pitches
[0] /
11440 intel_fb_stride_alignment(dev_priv
, fb
->modifier
[0],
11445 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11446 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11448 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
11449 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
11451 I915_WRITE(PLANE_SURF(pipe
, 0), work
->gtt_offset
);
11452 POSTING_READ(PLANE_SURF(pipe
, 0));
11455 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11456 struct intel_flip_work
*work
)
11458 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11459 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11460 struct intel_framebuffer
*intel_fb
=
11461 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
11462 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11463 i915_reg_t reg
= DSPCNTR(intel_crtc
->plane
);
11466 dspcntr
= I915_READ(reg
);
11468 if (obj
->tiling_mode
!= I915_TILING_NONE
)
11469 dspcntr
|= DISPPLANE_TILED
;
11471 dspcntr
&= ~DISPPLANE_TILED
;
11473 I915_WRITE(reg
, dspcntr
);
11475 I915_WRITE(DSPSURF(intel_crtc
->plane
), work
->gtt_offset
);
11476 POSTING_READ(DSPSURF(intel_crtc
->plane
));
11479 static void intel_mmio_flip_work_func(struct work_struct
*w
)
11481 struct intel_flip_work
*work
=
11482 container_of(w
, struct intel_flip_work
, mmio_work
);
11483 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
11484 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11485 struct intel_framebuffer
*intel_fb
=
11486 to_intel_framebuffer(crtc
->base
.primary
->fb
);
11487 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11488 struct reservation_object
*resv
;
11490 if (work
->flip_queued_req
)
11491 WARN_ON(__i915_wait_request(work
->flip_queued_req
,
11493 &dev_priv
->rps
.mmioflips
));
11495 /* For framebuffer backed by dmabuf, wait for fence */
11496 resv
= i915_gem_object_get_dmabuf_resv(obj
);
11498 WARN_ON(reservation_object_wait_timeout_rcu(resv
, false, false,
11499 MAX_SCHEDULE_TIMEOUT
) < 0);
11501 intel_pipe_update_start(crtc
);
11503 if (INTEL_GEN(dev_priv
) >= 9)
11504 skl_do_mmio_flip(crtc
, work
->rotation
, work
);
11506 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11507 ilk_do_mmio_flip(crtc
, work
);
11509 intel_pipe_update_end(crtc
, work
);
11512 static int intel_default_queue_flip(struct drm_device
*dev
,
11513 struct drm_crtc
*crtc
,
11514 struct drm_framebuffer
*fb
,
11515 struct drm_i915_gem_object
*obj
,
11516 struct drm_i915_gem_request
*req
,
11522 static bool __pageflip_stall_check_cs(struct drm_i915_private
*dev_priv
,
11523 struct intel_crtc
*intel_crtc
,
11524 struct intel_flip_work
*work
)
11528 if (!atomic_read(&work
->pending
))
11533 vblank
= intel_crtc_get_vblank_counter(intel_crtc
);
11534 if (work
->flip_ready_vblank
== 0) {
11535 if (work
->flip_queued_req
&&
11536 !i915_gem_request_completed(work
->flip_queued_req
))
11539 work
->flip_ready_vblank
= vblank
;
11542 if (vblank
- work
->flip_ready_vblank
< 3)
11545 /* Potential stall - if we see that the flip has happened,
11546 * assume a missed interrupt. */
11547 if (INTEL_GEN(dev_priv
) >= 4)
11548 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11550 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11552 /* There is a potential issue here with a false positive after a flip
11553 * to the same address. We could address this by checking for a
11554 * non-incrementing frame counter.
11556 return addr
== work
->gtt_offset
;
11559 void intel_check_page_flip(struct drm_i915_private
*dev_priv
, int pipe
)
11561 struct drm_device
*dev
= &dev_priv
->drm
;
11562 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11563 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11564 struct intel_flip_work
*work
;
11566 WARN_ON(!in_interrupt());
11571 spin_lock(&dev
->event_lock
);
11572 work
= intel_crtc
->flip_work
;
11574 if (work
!= NULL
&& !is_mmio_work(work
) &&
11575 __pageflip_stall_check_cs(dev_priv
, intel_crtc
, work
)) {
11577 "Kicking stuck page flip: queued at %d, now %d\n",
11578 work
->flip_queued_vblank
, intel_crtc_get_vblank_counter(intel_crtc
));
11579 page_flip_completed(intel_crtc
);
11583 if (work
!= NULL
&& !is_mmio_work(work
) &&
11584 intel_crtc_get_vblank_counter(intel_crtc
) - work
->flip_queued_vblank
> 1)
11585 intel_queue_rps_boost_for_request(work
->flip_queued_req
);
11586 spin_unlock(&dev
->event_lock
);
11589 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11590 struct drm_framebuffer
*fb
,
11591 struct drm_pending_vblank_event
*event
,
11592 uint32_t page_flip_flags
)
11594 struct drm_device
*dev
= crtc
->dev
;
11595 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11596 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11597 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11598 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11599 struct drm_plane
*primary
= crtc
->primary
;
11600 enum pipe pipe
= intel_crtc
->pipe
;
11601 struct intel_flip_work
*work
;
11602 struct intel_engine_cs
*engine
;
11604 struct drm_i915_gem_request
*request
= NULL
;
11608 * drm_mode_page_flip_ioctl() should already catch this, but double
11609 * check to be safe. In the future we may enable pageflipping from
11610 * a disabled primary plane.
11612 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11615 /* Can't change pixel format via MI display flips. */
11616 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11620 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11621 * Note that pitch changes could also affect these register.
11623 if (INTEL_INFO(dev
)->gen
> 3 &&
11624 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11625 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11628 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11631 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11635 work
->event
= event
;
11637 work
->old_fb
= old_fb
;
11638 INIT_WORK(&work
->unpin_work
, intel_unpin_work_fn
);
11640 ret
= drm_crtc_vblank_get(crtc
);
11644 /* We borrow the event spin lock for protecting flip_work */
11645 spin_lock_irq(&dev
->event_lock
);
11646 if (intel_crtc
->flip_work
) {
11647 /* Before declaring the flip queue wedged, check if
11648 * the hardware completed the operation behind our backs.
11650 if (pageflip_finished(intel_crtc
, intel_crtc
->flip_work
)) {
11651 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11652 page_flip_completed(intel_crtc
);
11654 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11655 spin_unlock_irq(&dev
->event_lock
);
11657 drm_crtc_vblank_put(crtc
);
11662 intel_crtc
->flip_work
= work
;
11663 spin_unlock_irq(&dev
->event_lock
);
11665 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11666 flush_workqueue(dev_priv
->wq
);
11668 /* Reference the objects for the scheduled work. */
11669 drm_framebuffer_reference(work
->old_fb
);
11670 drm_gem_object_reference(&obj
->base
);
11672 crtc
->primary
->fb
= fb
;
11673 update_state_fb(crtc
->primary
);
11675 intel_fbc_pre_update(intel_crtc
, intel_crtc
->config
,
11676 to_intel_plane_state(primary
->state
));
11678 work
->pending_flip_obj
= obj
;
11680 ret
= i915_mutex_lock_interruptible(dev
);
11684 intel_crtc
->reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
11685 if (__i915_reset_in_progress_or_wedged(intel_crtc
->reset_counter
)) {
11690 atomic_inc(&intel_crtc
->unpin_work_count
);
11692 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11693 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_G4X(pipe
)) + 1;
11695 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
11696 engine
= &dev_priv
->engine
[BCS
];
11697 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11698 /* vlv: DISPLAY_FLIP fails to change tiling */
11700 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11701 engine
= &dev_priv
->engine
[BCS
];
11702 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11703 engine
= i915_gem_request_get_engine(obj
->last_write_req
);
11704 if (engine
== NULL
|| engine
->id
!= RCS
)
11705 engine
= &dev_priv
->engine
[BCS
];
11707 engine
= &dev_priv
->engine
[RCS
];
11710 mmio_flip
= use_mmio_flip(engine
, obj
);
11712 /* When using CS flips, we want to emit semaphores between rings.
11713 * However, when using mmio flips we will create a task to do the
11714 * synchronisation, so all we want here is to pin the framebuffer
11715 * into the display plane and skip any waits.
11718 ret
= i915_gem_object_sync(obj
, engine
, &request
);
11719 if (!ret
&& !request
) {
11720 request
= i915_gem_request_alloc(engine
, NULL
);
11721 ret
= PTR_ERR_OR_ZERO(request
);
11725 goto cleanup_pending
;
11728 ret
= intel_pin_and_fence_fb_obj(fb
, primary
->state
->rotation
);
11730 goto cleanup_pending
;
11732 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
),
11734 work
->gtt_offset
+= intel_crtc
->dspaddr_offset
;
11735 work
->rotation
= crtc
->primary
->state
->rotation
;
11738 INIT_WORK(&work
->mmio_work
, intel_mmio_flip_work_func
);
11740 i915_gem_request_assign(&work
->flip_queued_req
,
11741 obj
->last_write_req
);
11743 schedule_work(&work
->mmio_work
);
11745 i915_gem_request_assign(&work
->flip_queued_req
, request
);
11746 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, request
,
11749 goto cleanup_unpin
;
11751 intel_mark_page_flip_active(intel_crtc
, work
);
11753 i915_add_request_no_flush(request
);
11756 i915_gem_track_fb(intel_fb_obj(old_fb
), obj
,
11757 to_intel_plane(primary
)->frontbuffer_bit
);
11758 mutex_unlock(&dev
->struct_mutex
);
11760 intel_frontbuffer_flip_prepare(dev
,
11761 to_intel_plane(primary
)->frontbuffer_bit
);
11763 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11768 intel_unpin_fb_obj(fb
, crtc
->primary
->state
->rotation
);
11770 if (!IS_ERR_OR_NULL(request
))
11771 i915_add_request_no_flush(request
);
11772 atomic_dec(&intel_crtc
->unpin_work_count
);
11773 mutex_unlock(&dev
->struct_mutex
);
11775 crtc
->primary
->fb
= old_fb
;
11776 update_state_fb(crtc
->primary
);
11778 drm_gem_object_unreference_unlocked(&obj
->base
);
11779 drm_framebuffer_unreference(work
->old_fb
);
11781 spin_lock_irq(&dev
->event_lock
);
11782 intel_crtc
->flip_work
= NULL
;
11783 spin_unlock_irq(&dev
->event_lock
);
11785 drm_crtc_vblank_put(crtc
);
11790 struct drm_atomic_state
*state
;
11791 struct drm_plane_state
*plane_state
;
11794 state
= drm_atomic_state_alloc(dev
);
11797 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
11800 plane_state
= drm_atomic_get_plane_state(state
, primary
);
11801 ret
= PTR_ERR_OR_ZERO(plane_state
);
11803 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11805 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
11807 ret
= drm_atomic_commit(state
);
11810 if (ret
== -EDEADLK
) {
11811 drm_modeset_backoff(state
->acquire_ctx
);
11812 drm_atomic_state_clear(state
);
11817 drm_atomic_state_free(state
);
11819 if (ret
== 0 && event
) {
11820 spin_lock_irq(&dev
->event_lock
);
11821 drm_crtc_send_vblank_event(crtc
, event
);
11822 spin_unlock_irq(&dev
->event_lock
);
11830 * intel_wm_need_update - Check whether watermarks need updating
11831 * @plane: drm plane
11832 * @state: new plane state
11834 * Check current plane state versus the new one to determine whether
11835 * watermarks need to be recalculated.
11837 * Returns true or false.
11839 static bool intel_wm_need_update(struct drm_plane
*plane
,
11840 struct drm_plane_state
*state
)
11842 struct intel_plane_state
*new = to_intel_plane_state(state
);
11843 struct intel_plane_state
*cur
= to_intel_plane_state(plane
->state
);
11845 /* Update watermarks on tiling or size changes. */
11846 if (new->visible
!= cur
->visible
)
11849 if (!cur
->base
.fb
|| !new->base
.fb
)
11852 if (cur
->base
.fb
->modifier
[0] != new->base
.fb
->modifier
[0] ||
11853 cur
->base
.rotation
!= new->base
.rotation
||
11854 drm_rect_width(&new->src
) != drm_rect_width(&cur
->src
) ||
11855 drm_rect_height(&new->src
) != drm_rect_height(&cur
->src
) ||
11856 drm_rect_width(&new->dst
) != drm_rect_width(&cur
->dst
) ||
11857 drm_rect_height(&new->dst
) != drm_rect_height(&cur
->dst
))
11863 static bool needs_scaling(struct intel_plane_state
*state
)
11865 int src_w
= drm_rect_width(&state
->src
) >> 16;
11866 int src_h
= drm_rect_height(&state
->src
) >> 16;
11867 int dst_w
= drm_rect_width(&state
->dst
);
11868 int dst_h
= drm_rect_height(&state
->dst
);
11870 return (src_w
!= dst_w
|| src_h
!= dst_h
);
11873 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
11874 struct drm_plane_state
*plane_state
)
11876 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
11877 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11878 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11879 struct drm_plane
*plane
= plane_state
->plane
;
11880 struct drm_device
*dev
= crtc
->dev
;
11881 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11882 struct intel_plane_state
*old_plane_state
=
11883 to_intel_plane_state(plane
->state
);
11884 bool mode_changed
= needs_modeset(crtc_state
);
11885 bool was_crtc_enabled
= crtc
->state
->active
;
11886 bool is_crtc_enabled
= crtc_state
->active
;
11887 bool turn_off
, turn_on
, visible
, was_visible
;
11888 struct drm_framebuffer
*fb
= plane_state
->fb
;
11891 if (INTEL_GEN(dev
) >= 9 && plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11892 ret
= skl_update_scaler_plane(
11893 to_intel_crtc_state(crtc_state
),
11894 to_intel_plane_state(plane_state
));
11899 was_visible
= old_plane_state
->visible
;
11900 visible
= to_intel_plane_state(plane_state
)->visible
;
11902 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11903 was_visible
= false;
11906 * Visibility is calculated as if the crtc was on, but
11907 * after scaler setup everything depends on it being off
11908 * when the crtc isn't active.
11910 * FIXME this is wrong for watermarks. Watermarks should also
11911 * be computed as if the pipe would be active. Perhaps move
11912 * per-plane wm computation to the .check_plane() hook, and
11913 * only combine the results from all planes in the current place?
11915 if (!is_crtc_enabled
)
11916 to_intel_plane_state(plane_state
)->visible
= visible
= false;
11918 if (!was_visible
&& !visible
)
11921 if (fb
!= old_plane_state
->base
.fb
)
11922 pipe_config
->fb_changed
= true;
11924 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11925 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11927 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11928 intel_crtc
->base
.base
.id
,
11929 intel_crtc
->base
.name
,
11930 plane
->base
.id
, plane
->name
,
11931 fb
? fb
->base
.id
: -1);
11933 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11934 plane
->base
.id
, plane
->name
,
11935 was_visible
, visible
,
11936 turn_off
, turn_on
, mode_changed
);
11939 pipe_config
->update_wm_pre
= true;
11941 /* must disable cxsr around plane enable/disable */
11942 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
11943 pipe_config
->disable_cxsr
= true;
11944 } else if (turn_off
) {
11945 pipe_config
->update_wm_post
= true;
11947 /* must disable cxsr around plane enable/disable */
11948 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
11949 pipe_config
->disable_cxsr
= true;
11950 } else if (intel_wm_need_update(plane
, plane_state
)) {
11951 /* FIXME bollocks */
11952 pipe_config
->update_wm_pre
= true;
11953 pipe_config
->update_wm_post
= true;
11956 /* Pre-gen9 platforms need two-step watermark updates */
11957 if ((pipe_config
->update_wm_pre
|| pipe_config
->update_wm_post
) &&
11958 INTEL_INFO(dev
)->gen
< 9 && dev_priv
->display
.optimize_watermarks
)
11959 to_intel_crtc_state(crtc_state
)->wm
.need_postvbl_update
= true;
11961 if (visible
|| was_visible
)
11962 pipe_config
->fb_bits
|= to_intel_plane(plane
)->frontbuffer_bit
;
11965 * WaCxSRDisabledForSpriteScaling:ivb
11967 * cstate->update_wm was already set above, so this flag will
11968 * take effect when we commit and program watermarks.
11970 if (plane
->type
== DRM_PLANE_TYPE_OVERLAY
&& IS_IVYBRIDGE(dev
) &&
11971 needs_scaling(to_intel_plane_state(plane_state
)) &&
11972 !needs_scaling(old_plane_state
))
11973 pipe_config
->disable_lp_wm
= true;
11978 static bool encoders_cloneable(const struct intel_encoder
*a
,
11979 const struct intel_encoder
*b
)
11981 /* masks could be asymmetric, so check both ways */
11982 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11983 b
->cloneable
& (1 << a
->type
));
11986 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11987 struct intel_crtc
*crtc
,
11988 struct intel_encoder
*encoder
)
11990 struct intel_encoder
*source_encoder
;
11991 struct drm_connector
*connector
;
11992 struct drm_connector_state
*connector_state
;
11995 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11996 if (connector_state
->crtc
!= &crtc
->base
)
12000 to_intel_encoder(connector_state
->best_encoder
);
12001 if (!encoders_cloneable(encoder
, source_encoder
))
12008 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
12009 struct intel_crtc
*crtc
)
12011 struct intel_encoder
*encoder
;
12012 struct drm_connector
*connector
;
12013 struct drm_connector_state
*connector_state
;
12016 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12017 if (connector_state
->crtc
!= &crtc
->base
)
12020 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12021 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
12028 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
12029 struct drm_crtc_state
*crtc_state
)
12031 struct drm_device
*dev
= crtc
->dev
;
12032 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12033 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12034 struct intel_crtc_state
*pipe_config
=
12035 to_intel_crtc_state(crtc_state
);
12036 struct drm_atomic_state
*state
= crtc_state
->state
;
12038 bool mode_changed
= needs_modeset(crtc_state
);
12040 if (mode_changed
&& !check_encoder_cloning(state
, intel_crtc
)) {
12041 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12045 if (mode_changed
&& !crtc_state
->active
)
12046 pipe_config
->update_wm_post
= true;
12048 if (mode_changed
&& crtc_state
->enable
&&
12049 dev_priv
->display
.crtc_compute_clock
&&
12050 !WARN_ON(pipe_config
->shared_dpll
)) {
12051 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12057 if (crtc_state
->color_mgmt_changed
) {
12058 ret
= intel_color_check(crtc
, crtc_state
);
12064 if (dev_priv
->display
.compute_pipe_wm
) {
12065 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
12067 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12072 if (dev_priv
->display
.compute_intermediate_wm
&&
12073 !to_intel_atomic_state(state
)->skip_intermediate_wm
) {
12074 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
12078 * Calculate 'intermediate' watermarks that satisfy both the
12079 * old state and the new state. We can program these
12082 ret
= dev_priv
->display
.compute_intermediate_wm(crtc
->dev
,
12086 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12089 } else if (dev_priv
->display
.compute_intermediate_wm
) {
12090 if (HAS_PCH_SPLIT(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
12091 pipe_config
->wm
.ilk
.intermediate
= pipe_config
->wm
.ilk
.optimal
;
12094 if (INTEL_INFO(dev
)->gen
>= 9) {
12096 ret
= skl_update_scaler_crtc(pipe_config
);
12099 ret
= intel_atomic_setup_scalers(dev
, intel_crtc
,
12106 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
12107 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
12108 .atomic_begin
= intel_begin_crtc_commit
,
12109 .atomic_flush
= intel_finish_crtc_commit
,
12110 .atomic_check
= intel_crtc_atomic_check
,
12113 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
12115 struct intel_connector
*connector
;
12117 for_each_intel_connector(dev
, connector
) {
12118 if (connector
->base
.state
->crtc
)
12119 drm_connector_unreference(&connector
->base
);
12121 if (connector
->base
.encoder
) {
12122 connector
->base
.state
->best_encoder
=
12123 connector
->base
.encoder
;
12124 connector
->base
.state
->crtc
=
12125 connector
->base
.encoder
->crtc
;
12127 drm_connector_reference(&connector
->base
);
12129 connector
->base
.state
->best_encoder
= NULL
;
12130 connector
->base
.state
->crtc
= NULL
;
12136 connected_sink_compute_bpp(struct intel_connector
*connector
,
12137 struct intel_crtc_state
*pipe_config
)
12139 int bpp
= pipe_config
->pipe_bpp
;
12141 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12142 connector
->base
.base
.id
,
12143 connector
->base
.name
);
12145 /* Don't use an invalid EDID bpc value */
12146 if (connector
->base
.display_info
.bpc
&&
12147 connector
->base
.display_info
.bpc
* 3 < bpp
) {
12148 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12149 bpp
, connector
->base
.display_info
.bpc
*3);
12150 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
12153 /* Clamp bpp to default limit on screens without EDID 1.4 */
12154 if (connector
->base
.display_info
.bpc
== 0) {
12155 int type
= connector
->base
.connector_type
;
12156 int clamp_bpp
= 24;
12158 /* Fall back to 18 bpp when DP sink capability is unknown. */
12159 if (type
== DRM_MODE_CONNECTOR_DisplayPort
||
12160 type
== DRM_MODE_CONNECTOR_eDP
)
12163 if (bpp
> clamp_bpp
) {
12164 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12166 pipe_config
->pipe_bpp
= clamp_bpp
;
12172 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
12173 struct intel_crtc_state
*pipe_config
)
12175 struct drm_device
*dev
= crtc
->base
.dev
;
12176 struct drm_atomic_state
*state
;
12177 struct drm_connector
*connector
;
12178 struct drm_connector_state
*connector_state
;
12181 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)))
12183 else if (INTEL_INFO(dev
)->gen
>= 5)
12189 pipe_config
->pipe_bpp
= bpp
;
12191 state
= pipe_config
->base
.state
;
12193 /* Clamp display bpp to EDID value */
12194 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12195 if (connector_state
->crtc
!= &crtc
->base
)
12198 connected_sink_compute_bpp(to_intel_connector(connector
),
12205 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
12207 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12208 "type: 0x%x flags: 0x%x\n",
12210 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
12211 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
12212 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
12213 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
12216 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
12217 struct intel_crtc_state
*pipe_config
,
12218 const char *context
)
12220 struct drm_device
*dev
= crtc
->base
.dev
;
12221 struct drm_plane
*plane
;
12222 struct intel_plane
*intel_plane
;
12223 struct intel_plane_state
*state
;
12224 struct drm_framebuffer
*fb
;
12226 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12227 crtc
->base
.base
.id
, crtc
->base
.name
,
12228 context
, pipe_config
, pipe_name(crtc
->pipe
));
12230 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config
->cpu_transcoder
));
12231 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12232 pipe_config
->pipe_bpp
, pipe_config
->dither
);
12233 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12234 pipe_config
->has_pch_encoder
,
12235 pipe_config
->fdi_lanes
,
12236 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
12237 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
12238 pipe_config
->fdi_m_n
.tu
);
12239 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12240 intel_crtc_has_dp_encoder(pipe_config
),
12241 pipe_config
->lane_count
,
12242 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
12243 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
12244 pipe_config
->dp_m_n
.tu
);
12246 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12247 intel_crtc_has_dp_encoder(pipe_config
),
12248 pipe_config
->lane_count
,
12249 pipe_config
->dp_m2_n2
.gmch_m
,
12250 pipe_config
->dp_m2_n2
.gmch_n
,
12251 pipe_config
->dp_m2_n2
.link_m
,
12252 pipe_config
->dp_m2_n2
.link_n
,
12253 pipe_config
->dp_m2_n2
.tu
);
12255 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12256 pipe_config
->has_audio
,
12257 pipe_config
->has_infoframe
);
12259 DRM_DEBUG_KMS("requested mode:\n");
12260 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
12261 DRM_DEBUG_KMS("adjusted mode:\n");
12262 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
12263 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
12264 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
12265 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12266 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
12267 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12269 pipe_config
->scaler_state
.scaler_users
,
12270 pipe_config
->scaler_state
.scaler_id
);
12271 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12272 pipe_config
->gmch_pfit
.control
,
12273 pipe_config
->gmch_pfit
.pgm_ratios
,
12274 pipe_config
->gmch_pfit
.lvds_border_bits
);
12275 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12276 pipe_config
->pch_pfit
.pos
,
12277 pipe_config
->pch_pfit
.size
,
12278 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
12279 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
12280 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
12282 if (IS_BROXTON(dev
)) {
12283 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12284 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12285 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12286 pipe_config
->ddi_pll_sel
,
12287 pipe_config
->dpll_hw_state
.ebb0
,
12288 pipe_config
->dpll_hw_state
.ebb4
,
12289 pipe_config
->dpll_hw_state
.pll0
,
12290 pipe_config
->dpll_hw_state
.pll1
,
12291 pipe_config
->dpll_hw_state
.pll2
,
12292 pipe_config
->dpll_hw_state
.pll3
,
12293 pipe_config
->dpll_hw_state
.pll6
,
12294 pipe_config
->dpll_hw_state
.pll8
,
12295 pipe_config
->dpll_hw_state
.pll9
,
12296 pipe_config
->dpll_hw_state
.pll10
,
12297 pipe_config
->dpll_hw_state
.pcsdw12
);
12298 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
12299 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12300 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12301 pipe_config
->ddi_pll_sel
,
12302 pipe_config
->dpll_hw_state
.ctrl1
,
12303 pipe_config
->dpll_hw_state
.cfgcr1
,
12304 pipe_config
->dpll_hw_state
.cfgcr2
);
12305 } else if (HAS_DDI(dev
)) {
12306 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12307 pipe_config
->ddi_pll_sel
,
12308 pipe_config
->dpll_hw_state
.wrpll
,
12309 pipe_config
->dpll_hw_state
.spll
);
12311 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12312 "fp0: 0x%x, fp1: 0x%x\n",
12313 pipe_config
->dpll_hw_state
.dpll
,
12314 pipe_config
->dpll_hw_state
.dpll_md
,
12315 pipe_config
->dpll_hw_state
.fp0
,
12316 pipe_config
->dpll_hw_state
.fp1
);
12319 DRM_DEBUG_KMS("planes on this crtc\n");
12320 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12321 intel_plane
= to_intel_plane(plane
);
12322 if (intel_plane
->pipe
!= crtc
->pipe
)
12325 state
= to_intel_plane_state(plane
->state
);
12326 fb
= state
->base
.fb
;
12328 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12329 plane
->base
.id
, plane
->name
, state
->scaler_id
);
12333 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12334 plane
->base
.id
, plane
->name
);
12335 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12336 fb
->base
.id
, fb
->width
, fb
->height
,
12337 drm_get_format_name(fb
->pixel_format
));
12338 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12340 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
12341 drm_rect_width(&state
->src
) >> 16,
12342 drm_rect_height(&state
->src
) >> 16,
12343 state
->dst
.x1
, state
->dst
.y1
,
12344 drm_rect_width(&state
->dst
),
12345 drm_rect_height(&state
->dst
));
12349 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12351 struct drm_device
*dev
= state
->dev
;
12352 struct drm_connector
*connector
;
12353 unsigned int used_ports
= 0;
12356 * Walk the connector list instead of the encoder
12357 * list to detect the problem on ddi platforms
12358 * where there's just one encoder per digital port.
12360 drm_for_each_connector(connector
, dev
) {
12361 struct drm_connector_state
*connector_state
;
12362 struct intel_encoder
*encoder
;
12364 connector_state
= drm_atomic_get_existing_connector_state(state
, connector
);
12365 if (!connector_state
)
12366 connector_state
= connector
->state
;
12368 if (!connector_state
->best_encoder
)
12371 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12373 WARN_ON(!connector_state
->crtc
);
12375 switch (encoder
->type
) {
12376 unsigned int port_mask
;
12377 case INTEL_OUTPUT_UNKNOWN
:
12378 if (WARN_ON(!HAS_DDI(dev
)))
12380 case INTEL_OUTPUT_DP
:
12381 case INTEL_OUTPUT_HDMI
:
12382 case INTEL_OUTPUT_EDP
:
12383 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12385 /* the same port mustn't appear more than once */
12386 if (used_ports
& port_mask
)
12389 used_ports
|= port_mask
;
12399 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12401 struct drm_crtc_state tmp_state
;
12402 struct intel_crtc_scaler_state scaler_state
;
12403 struct intel_dpll_hw_state dpll_hw_state
;
12404 struct intel_shared_dpll
*shared_dpll
;
12405 uint32_t ddi_pll_sel
;
12408 /* FIXME: before the switch to atomic started, a new pipe_config was
12409 * kzalloc'd. Code that depends on any field being zero should be
12410 * fixed, so that the crtc_state can be safely duplicated. For now,
12411 * only fields that are know to not cause problems are preserved. */
12413 tmp_state
= crtc_state
->base
;
12414 scaler_state
= crtc_state
->scaler_state
;
12415 shared_dpll
= crtc_state
->shared_dpll
;
12416 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12417 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
12418 force_thru
= crtc_state
->pch_pfit
.force_thru
;
12420 memset(crtc_state
, 0, sizeof *crtc_state
);
12422 crtc_state
->base
= tmp_state
;
12423 crtc_state
->scaler_state
= scaler_state
;
12424 crtc_state
->shared_dpll
= shared_dpll
;
12425 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12426 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
12427 crtc_state
->pch_pfit
.force_thru
= force_thru
;
12431 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12432 struct intel_crtc_state
*pipe_config
)
12434 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12435 struct intel_encoder
*encoder
;
12436 struct drm_connector
*connector
;
12437 struct drm_connector_state
*connector_state
;
12438 int base_bpp
, ret
= -EINVAL
;
12442 clear_intel_crtc_state(pipe_config
);
12444 pipe_config
->cpu_transcoder
=
12445 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12448 * Sanitize sync polarity flags based on requested ones. If neither
12449 * positive or negative polarity is requested, treat this as meaning
12450 * negative polarity.
12452 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12453 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12454 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12456 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12457 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12458 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12460 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12466 * Determine the real pipe dimensions. Note that stereo modes can
12467 * increase the actual pipe size due to the frame doubling and
12468 * insertion of additional space for blanks between the frame. This
12469 * is stored in the crtc timings. We use the requested mode to do this
12470 * computation to clearly distinguish it from the adjusted mode, which
12471 * can be changed by the connectors in the below retry loop.
12473 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
12474 &pipe_config
->pipe_src_w
,
12475 &pipe_config
->pipe_src_h
);
12477 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12478 if (connector_state
->crtc
!= crtc
)
12481 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12484 * Determine output_types before calling the .compute_config()
12485 * hooks so that the hooks can use this information safely.
12487 pipe_config
->output_types
|= 1 << encoder
->type
;
12491 /* Ensure the port clock defaults are reset when retrying. */
12492 pipe_config
->port_clock
= 0;
12493 pipe_config
->pixel_multiplier
= 1;
12495 /* Fill in default crtc timings, allow encoders to overwrite them. */
12496 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12497 CRTC_STEREO_DOUBLE
);
12499 /* Pass our mode to the connectors and the CRTC to give them a chance to
12500 * adjust it according to limitations or connector properties, and also
12501 * a chance to reject the mode entirely.
12503 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12504 if (connector_state
->crtc
!= crtc
)
12507 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12509 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
12510 DRM_DEBUG_KMS("Encoder config failure\n");
12515 /* Set default port clock if not overwritten by the encoder. Needs to be
12516 * done afterwards in case the encoder adjusts the mode. */
12517 if (!pipe_config
->port_clock
)
12518 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12519 * pipe_config
->pixel_multiplier
;
12521 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12523 DRM_DEBUG_KMS("CRTC fixup failed\n");
12527 if (ret
== RETRY
) {
12528 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
12533 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12535 goto encoder_retry
;
12538 /* Dithering seems to not pass-through bits correctly when it should, so
12539 * only enable it on 6bpc panels. */
12540 pipe_config
->dither
= pipe_config
->pipe_bpp
== 6*3;
12541 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12542 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12549 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
12551 struct drm_crtc
*crtc
;
12552 struct drm_crtc_state
*crtc_state
;
12555 /* Double check state. */
12556 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12557 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
12559 /* Update hwmode for vblank functions */
12560 if (crtc
->state
->active
)
12561 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
12563 crtc
->hwmode
.crtc_clock
= 0;
12566 * Update legacy state to satisfy fbc code. This can
12567 * be removed when fbc uses the atomic state.
12569 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
12570 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
12572 crtc
->primary
->fb
= plane_state
->fb
;
12573 crtc
->x
= plane_state
->src_x
>> 16;
12574 crtc
->y
= plane_state
->src_y
>> 16;
12579 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12583 if (clock1
== clock2
)
12586 if (!clock1
|| !clock2
)
12589 diff
= abs(clock1
- clock2
);
12591 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12597 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12598 list_for_each_entry((intel_crtc), \
12599 &(dev)->mode_config.crtc_list, \
12601 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12604 intel_compare_m_n(unsigned int m
, unsigned int n
,
12605 unsigned int m2
, unsigned int n2
,
12608 if (m
== m2
&& n
== n2
)
12611 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12614 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12621 } else if (n
< n2
) {
12631 return intel_fuzzy_clock_check(m
, m2
);
12635 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12636 struct intel_link_m_n
*m2_n2
,
12639 if (m_n
->tu
== m2_n2
->tu
&&
12640 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12641 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12642 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12643 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12654 intel_pipe_config_compare(struct drm_device
*dev
,
12655 struct intel_crtc_state
*current_config
,
12656 struct intel_crtc_state
*pipe_config
,
12661 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12664 DRM_ERROR(fmt, ##__VA_ARGS__); \
12666 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12669 #define PIPE_CONF_CHECK_X(name) \
12670 if (current_config->name != pipe_config->name) { \
12671 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12672 "(expected 0x%08x, found 0x%08x)\n", \
12673 current_config->name, \
12674 pipe_config->name); \
12678 #define PIPE_CONF_CHECK_I(name) \
12679 if (current_config->name != pipe_config->name) { \
12680 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12681 "(expected %i, found %i)\n", \
12682 current_config->name, \
12683 pipe_config->name); \
12687 #define PIPE_CONF_CHECK_P(name) \
12688 if (current_config->name != pipe_config->name) { \
12689 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12690 "(expected %p, found %p)\n", \
12691 current_config->name, \
12692 pipe_config->name); \
12696 #define PIPE_CONF_CHECK_M_N(name) \
12697 if (!intel_compare_link_m_n(¤t_config->name, \
12698 &pipe_config->name,\
12700 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12701 "(expected tu %i gmch %i/%i link %i/%i, " \
12702 "found tu %i, gmch %i/%i link %i/%i)\n", \
12703 current_config->name.tu, \
12704 current_config->name.gmch_m, \
12705 current_config->name.gmch_n, \
12706 current_config->name.link_m, \
12707 current_config->name.link_n, \
12708 pipe_config->name.tu, \
12709 pipe_config->name.gmch_m, \
12710 pipe_config->name.gmch_n, \
12711 pipe_config->name.link_m, \
12712 pipe_config->name.link_n); \
12716 /* This is required for BDW+ where there is only one set of registers for
12717 * switching between high and low RR.
12718 * This macro can be used whenever a comparison has to be made between one
12719 * hw state and multiple sw state variables.
12721 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12722 if (!intel_compare_link_m_n(¤t_config->name, \
12723 &pipe_config->name, adjust) && \
12724 !intel_compare_link_m_n(¤t_config->alt_name, \
12725 &pipe_config->name, adjust)) { \
12726 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12727 "(expected tu %i gmch %i/%i link %i/%i, " \
12728 "or tu %i gmch %i/%i link %i/%i, " \
12729 "found tu %i, gmch %i/%i link %i/%i)\n", \
12730 current_config->name.tu, \
12731 current_config->name.gmch_m, \
12732 current_config->name.gmch_n, \
12733 current_config->name.link_m, \
12734 current_config->name.link_n, \
12735 current_config->alt_name.tu, \
12736 current_config->alt_name.gmch_m, \
12737 current_config->alt_name.gmch_n, \
12738 current_config->alt_name.link_m, \
12739 current_config->alt_name.link_n, \
12740 pipe_config->name.tu, \
12741 pipe_config->name.gmch_m, \
12742 pipe_config->name.gmch_n, \
12743 pipe_config->name.link_m, \
12744 pipe_config->name.link_n); \
12748 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12749 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12750 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12751 "(expected %i, found %i)\n", \
12752 current_config->name & (mask), \
12753 pipe_config->name & (mask)); \
12757 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12758 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12759 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12760 "(expected %i, found %i)\n", \
12761 current_config->name, \
12762 pipe_config->name); \
12766 #define PIPE_CONF_QUIRK(quirk) \
12767 ((current_config->quirks | pipe_config->quirks) & (quirk))
12769 PIPE_CONF_CHECK_I(cpu_transcoder
);
12771 PIPE_CONF_CHECK_I(has_pch_encoder
);
12772 PIPE_CONF_CHECK_I(fdi_lanes
);
12773 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12775 PIPE_CONF_CHECK_I(lane_count
);
12776 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
12778 if (INTEL_INFO(dev
)->gen
< 8) {
12779 PIPE_CONF_CHECK_M_N(dp_m_n
);
12781 if (current_config
->has_drrs
)
12782 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12784 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12786 PIPE_CONF_CHECK_I(has_dsi_encoder
);
12787 PIPE_CONF_CHECK_X(output_types
);
12789 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12790 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12791 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12792 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12793 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12794 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12796 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12797 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12798 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12799 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12800 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12801 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12803 PIPE_CONF_CHECK_I(pixel_multiplier
);
12804 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12805 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12806 IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
12807 PIPE_CONF_CHECK_I(limited_color_range
);
12808 PIPE_CONF_CHECK_I(has_infoframe
);
12810 PIPE_CONF_CHECK_I(has_audio
);
12812 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12813 DRM_MODE_FLAG_INTERLACE
);
12815 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12816 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12817 DRM_MODE_FLAG_PHSYNC
);
12818 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12819 DRM_MODE_FLAG_NHSYNC
);
12820 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12821 DRM_MODE_FLAG_PVSYNC
);
12822 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12823 DRM_MODE_FLAG_NVSYNC
);
12826 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12827 /* pfit ratios are autocomputed by the hw on gen4+ */
12828 if (INTEL_INFO(dev
)->gen
< 4)
12829 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
12830 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12833 PIPE_CONF_CHECK_I(pipe_src_w
);
12834 PIPE_CONF_CHECK_I(pipe_src_h
);
12836 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12837 if (current_config
->pch_pfit
.enabled
) {
12838 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12839 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12842 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12845 /* BDW+ don't expose a synchronous way to read the state */
12846 if (IS_HASWELL(dev
))
12847 PIPE_CONF_CHECK_I(ips_enabled
);
12849 PIPE_CONF_CHECK_I(double_wide
);
12851 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12853 PIPE_CONF_CHECK_P(shared_dpll
);
12854 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12855 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12856 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12857 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12858 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12859 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
12860 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12861 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12862 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12864 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
12865 PIPE_CONF_CHECK_X(dsi_pll
.div
);
12867 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12868 PIPE_CONF_CHECK_I(pipe_bpp
);
12870 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12871 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12873 #undef PIPE_CONF_CHECK_X
12874 #undef PIPE_CONF_CHECK_I
12875 #undef PIPE_CONF_CHECK_P
12876 #undef PIPE_CONF_CHECK_FLAGS
12877 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12878 #undef PIPE_CONF_QUIRK
12879 #undef INTEL_ERR_OR_DBG_KMS
12884 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
12885 const struct intel_crtc_state
*pipe_config
)
12887 if (pipe_config
->has_pch_encoder
) {
12888 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
12889 &pipe_config
->fdi_m_n
);
12890 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
12893 * FDI already provided one idea for the dotclock.
12894 * Yell if the encoder disagrees.
12896 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
12897 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12898 fdi_dotclock
, dotclock
);
12902 static void verify_wm_state(struct drm_crtc
*crtc
,
12903 struct drm_crtc_state
*new_state
)
12905 struct drm_device
*dev
= crtc
->dev
;
12906 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12907 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12908 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12909 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12910 const enum pipe pipe
= intel_crtc
->pipe
;
12913 if (INTEL_INFO(dev
)->gen
< 9 || !new_state
->active
)
12916 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12917 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12920 for_each_plane(dev_priv
, pipe
, plane
) {
12921 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12922 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12924 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12927 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12928 "(expected (%u,%u), found (%u,%u))\n",
12929 pipe_name(pipe
), plane
+ 1,
12930 sw_entry
->start
, sw_entry
->end
,
12931 hw_entry
->start
, hw_entry
->end
);
12935 hw_entry
= &hw_ddb
.plane
[pipe
][PLANE_CURSOR
];
12936 sw_entry
= &sw_ddb
->plane
[pipe
][PLANE_CURSOR
];
12938 if (!skl_ddb_entry_equal(hw_entry
, sw_entry
)) {
12939 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12940 "(expected (%u,%u), found (%u,%u))\n",
12942 sw_entry
->start
, sw_entry
->end
,
12943 hw_entry
->start
, hw_entry
->end
);
12948 verify_connector_state(struct drm_device
*dev
, struct drm_crtc
*crtc
)
12950 struct drm_connector
*connector
;
12952 drm_for_each_connector(connector
, dev
) {
12953 struct drm_encoder
*encoder
= connector
->encoder
;
12954 struct drm_connector_state
*state
= connector
->state
;
12956 if (state
->crtc
!= crtc
)
12959 intel_connector_verify_state(to_intel_connector(connector
));
12961 I915_STATE_WARN(state
->best_encoder
!= encoder
,
12962 "connector's atomic encoder doesn't match legacy encoder\n");
12967 verify_encoder_state(struct drm_device
*dev
)
12969 struct intel_encoder
*encoder
;
12970 struct intel_connector
*connector
;
12972 for_each_intel_encoder(dev
, encoder
) {
12973 bool enabled
= false;
12976 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12977 encoder
->base
.base
.id
,
12978 encoder
->base
.name
);
12980 for_each_intel_connector(dev
, connector
) {
12981 if (connector
->base
.state
->best_encoder
!= &encoder
->base
)
12985 I915_STATE_WARN(connector
->base
.state
->crtc
!=
12986 encoder
->base
.crtc
,
12987 "connector's crtc doesn't match encoder crtc\n");
12990 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12991 "encoder's enabled state mismatch "
12992 "(expected %i, found %i)\n",
12993 !!encoder
->base
.crtc
, enabled
);
12995 if (!encoder
->base
.crtc
) {
12998 active
= encoder
->get_hw_state(encoder
, &pipe
);
12999 I915_STATE_WARN(active
,
13000 "encoder detached but still enabled on pipe %c.\n",
13007 verify_crtc_state(struct drm_crtc
*crtc
,
13008 struct drm_crtc_state
*old_crtc_state
,
13009 struct drm_crtc_state
*new_crtc_state
)
13011 struct drm_device
*dev
= crtc
->dev
;
13012 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13013 struct intel_encoder
*encoder
;
13014 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13015 struct intel_crtc_state
*pipe_config
, *sw_config
;
13016 struct drm_atomic_state
*old_state
;
13019 old_state
= old_crtc_state
->state
;
13020 __drm_atomic_helper_crtc_destroy_state(old_crtc_state
);
13021 pipe_config
= to_intel_crtc_state(old_crtc_state
);
13022 memset(pipe_config
, 0, sizeof(*pipe_config
));
13023 pipe_config
->base
.crtc
= crtc
;
13024 pipe_config
->base
.state
= old_state
;
13026 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
13028 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
13030 /* hw state is inconsistent with the pipe quirk */
13031 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
13032 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
13033 active
= new_crtc_state
->active
;
13035 I915_STATE_WARN(new_crtc_state
->active
!= active
,
13036 "crtc active state doesn't match with hw state "
13037 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
13039 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
13040 "transitional active state does not match atomic hw state "
13041 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
13043 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
13046 active
= encoder
->get_hw_state(encoder
, &pipe
);
13047 I915_STATE_WARN(active
!= new_crtc_state
->active
,
13048 "[ENCODER:%i] active %i with crtc active %i\n",
13049 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
13051 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
13052 "Encoder connected to wrong pipe %c\n",
13056 pipe_config
->output_types
|= 1 << encoder
->type
;
13057 encoder
->get_config(encoder
, pipe_config
);
13061 if (!new_crtc_state
->active
)
13064 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
13066 sw_config
= to_intel_crtc_state(crtc
->state
);
13067 if (!intel_pipe_config_compare(dev
, sw_config
,
13068 pipe_config
, false)) {
13069 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13070 intel_dump_pipe_config(intel_crtc
, pipe_config
,
13072 intel_dump_pipe_config(intel_crtc
, sw_config
,
13078 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
13079 struct intel_shared_dpll
*pll
,
13080 struct drm_crtc
*crtc
,
13081 struct drm_crtc_state
*new_state
)
13083 struct intel_dpll_hw_state dpll_hw_state
;
13084 unsigned crtc_mask
;
13087 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
13089 DRM_DEBUG_KMS("%s\n", pll
->name
);
13091 active
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
13093 if (!(pll
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
13094 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
13095 "pll in active use but not on in sw tracking\n");
13096 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
13097 "pll is on but not used by any active crtc\n");
13098 I915_STATE_WARN(pll
->on
!= active
,
13099 "pll on state mismatch (expected %i, found %i)\n",
13104 I915_STATE_WARN(pll
->active_mask
& ~pll
->config
.crtc_mask
,
13105 "more active pll users than references: %x vs %x\n",
13106 pll
->active_mask
, pll
->config
.crtc_mask
);
13111 crtc_mask
= 1 << drm_crtc_index(crtc
);
13113 if (new_state
->active
)
13114 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
13115 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13116 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13118 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13119 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13120 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13122 I915_STATE_WARN(!(pll
->config
.crtc_mask
& crtc_mask
),
13123 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13124 crtc_mask
, pll
->config
.crtc_mask
);
13126 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
,
13128 sizeof(dpll_hw_state
)),
13129 "pll hw state mismatch\n");
13133 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
13134 struct drm_crtc_state
*old_crtc_state
,
13135 struct drm_crtc_state
*new_crtc_state
)
13137 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13138 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
13139 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
13141 if (new_state
->shared_dpll
)
13142 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
13144 if (old_state
->shared_dpll
&&
13145 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
13146 unsigned crtc_mask
= 1 << drm_crtc_index(crtc
);
13147 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
13149 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13150 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13151 pipe_name(drm_crtc_index(crtc
)));
13152 I915_STATE_WARN(pll
->config
.crtc_mask
& crtc_mask
,
13153 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13154 pipe_name(drm_crtc_index(crtc
)));
13159 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
13160 struct drm_crtc_state
*old_state
,
13161 struct drm_crtc_state
*new_state
)
13163 if (!needs_modeset(new_state
) &&
13164 !to_intel_crtc_state(new_state
)->update_pipe
)
13167 verify_wm_state(crtc
, new_state
);
13168 verify_connector_state(crtc
->dev
, crtc
);
13169 verify_crtc_state(crtc
, old_state
, new_state
);
13170 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
13174 verify_disabled_dpll_state(struct drm_device
*dev
)
13176 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13179 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
13180 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
13184 intel_modeset_verify_disabled(struct drm_device
*dev
)
13186 verify_encoder_state(dev
);
13187 verify_connector_state(dev
, NULL
);
13188 verify_disabled_dpll_state(dev
);
13191 static void update_scanline_offset(struct intel_crtc
*crtc
)
13193 struct drm_device
*dev
= crtc
->base
.dev
;
13196 * The scanline counter increments at the leading edge of hsync.
13198 * On most platforms it starts counting from vtotal-1 on the
13199 * first active line. That means the scanline counter value is
13200 * always one less than what we would expect. Ie. just after
13201 * start of vblank, which also occurs at start of hsync (on the
13202 * last active line), the scanline counter will read vblank_start-1.
13204 * On gen2 the scanline counter starts counting from 1 instead
13205 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13206 * to keep the value positive), instead of adding one.
13208 * On HSW+ the behaviour of the scanline counter depends on the output
13209 * type. For DP ports it behaves like most other platforms, but on HDMI
13210 * there's an extra 1 line difference. So we need to add two instead of
13211 * one to the value.
13213 if (IS_GEN2(dev
)) {
13214 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
13217 vtotal
= adjusted_mode
->crtc_vtotal
;
13218 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
13221 crtc
->scanline_offset
= vtotal
- 1;
13222 } else if (HAS_DDI(dev
) &&
13223 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
)) {
13224 crtc
->scanline_offset
= 2;
13226 crtc
->scanline_offset
= 1;
13229 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
13231 struct drm_device
*dev
= state
->dev
;
13232 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13233 struct intel_shared_dpll_config
*shared_dpll
= NULL
;
13234 struct drm_crtc
*crtc
;
13235 struct drm_crtc_state
*crtc_state
;
13238 if (!dev_priv
->display
.crtc_compute_clock
)
13241 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13242 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13243 struct intel_shared_dpll
*old_dpll
=
13244 to_intel_crtc_state(crtc
->state
)->shared_dpll
;
13246 if (!needs_modeset(crtc_state
))
13249 to_intel_crtc_state(crtc_state
)->shared_dpll
= NULL
;
13255 shared_dpll
= intel_atomic_get_shared_dpll_state(state
);
13257 intel_shared_dpll_config_put(shared_dpll
, old_dpll
, intel_crtc
);
13262 * This implements the workaround described in the "notes" section of the mode
13263 * set sequence documentation. When going from no pipes or single pipe to
13264 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13265 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13267 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
13269 struct drm_crtc_state
*crtc_state
;
13270 struct intel_crtc
*intel_crtc
;
13271 struct drm_crtc
*crtc
;
13272 struct intel_crtc_state
*first_crtc_state
= NULL
;
13273 struct intel_crtc_state
*other_crtc_state
= NULL
;
13274 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
13277 /* look at all crtc's that are going to be enabled in during modeset */
13278 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13279 intel_crtc
= to_intel_crtc(crtc
);
13281 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
13284 if (first_crtc_state
) {
13285 other_crtc_state
= to_intel_crtc_state(crtc_state
);
13288 first_crtc_state
= to_intel_crtc_state(crtc_state
);
13289 first_pipe
= intel_crtc
->pipe
;
13293 /* No workaround needed? */
13294 if (!first_crtc_state
)
13297 /* w/a possibly needed, check how many crtc's are already enabled. */
13298 for_each_intel_crtc(state
->dev
, intel_crtc
) {
13299 struct intel_crtc_state
*pipe_config
;
13301 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13302 if (IS_ERR(pipe_config
))
13303 return PTR_ERR(pipe_config
);
13305 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
13307 if (!pipe_config
->base
.active
||
13308 needs_modeset(&pipe_config
->base
))
13311 /* 2 or more enabled crtcs means no need for w/a */
13312 if (enabled_pipe
!= INVALID_PIPE
)
13315 enabled_pipe
= intel_crtc
->pipe
;
13318 if (enabled_pipe
!= INVALID_PIPE
)
13319 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13320 else if (other_crtc_state
)
13321 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13326 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13328 struct drm_crtc
*crtc
;
13329 struct drm_crtc_state
*crtc_state
;
13332 /* add all active pipes to the state */
13333 for_each_crtc(state
->dev
, crtc
) {
13334 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13335 if (IS_ERR(crtc_state
))
13336 return PTR_ERR(crtc_state
);
13338 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13341 crtc_state
->mode_changed
= true;
13343 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13347 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13355 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13357 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13358 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
13359 struct drm_crtc
*crtc
;
13360 struct drm_crtc_state
*crtc_state
;
13363 if (!check_digital_port_conflicts(state
)) {
13364 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13368 intel_state
->modeset
= true;
13369 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
13371 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13372 if (crtc_state
->active
)
13373 intel_state
->active_crtcs
|= 1 << i
;
13375 intel_state
->active_crtcs
&= ~(1 << i
);
13377 if (crtc_state
->active
!= crtc
->state
->active
)
13378 intel_state
->active_pipe_changes
|= drm_crtc_mask(crtc
);
13382 * See if the config requires any additional preparation, e.g.
13383 * to adjust global state with pipes off. We need to do this
13384 * here so we can get the modeset_pipe updated config for the new
13385 * mode set on this crtc. For other crtcs we need to use the
13386 * adjusted_mode bits in the crtc directly.
13388 if (dev_priv
->display
.modeset_calc_cdclk
) {
13389 if (!intel_state
->cdclk_pll_vco
)
13390 intel_state
->cdclk_pll_vco
= dev_priv
->cdclk_pll
.vco
;
13391 if (!intel_state
->cdclk_pll_vco
)
13392 intel_state
->cdclk_pll_vco
= dev_priv
->skl_preferred_vco_freq
;
13394 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
13398 if (intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
||
13399 intel_state
->cdclk_pll_vco
!= dev_priv
->cdclk_pll
.vco
)
13400 ret
= intel_modeset_all_pipes(state
);
13405 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13406 intel_state
->cdclk
, intel_state
->dev_cdclk
);
13408 to_intel_atomic_state(state
)->cdclk
= dev_priv
->atomic_cdclk_freq
;
13410 intel_modeset_clear_plls(state
);
13412 if (IS_HASWELL(dev_priv
))
13413 return haswell_mode_set_planes_workaround(state
);
13419 * Handle calculation of various watermark data at the end of the atomic check
13420 * phase. The code here should be run after the per-crtc and per-plane 'check'
13421 * handlers to ensure that all derived state has been updated.
13423 static int calc_watermark_data(struct drm_atomic_state
*state
)
13425 struct drm_device
*dev
= state
->dev
;
13426 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13428 /* Is there platform-specific watermark information to calculate? */
13429 if (dev_priv
->display
.compute_global_watermarks
)
13430 return dev_priv
->display
.compute_global_watermarks(state
);
13436 * intel_atomic_check - validate state object
13438 * @state: state to validate
13440 static int intel_atomic_check(struct drm_device
*dev
,
13441 struct drm_atomic_state
*state
)
13443 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13444 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13445 struct drm_crtc
*crtc
;
13446 struct drm_crtc_state
*crtc_state
;
13448 bool any_ms
= false;
13450 ret
= drm_atomic_helper_check_modeset(dev
, state
);
13454 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13455 struct intel_crtc_state
*pipe_config
=
13456 to_intel_crtc_state(crtc_state
);
13458 /* Catch I915_MODE_FLAG_INHERITED */
13459 if (crtc_state
->mode
.private_flags
!= crtc
->state
->mode
.private_flags
)
13460 crtc_state
->mode_changed
= true;
13462 if (!needs_modeset(crtc_state
))
13465 if (!crtc_state
->enable
) {
13470 /* FIXME: For only active_changed we shouldn't need to do any
13471 * state recomputation at all. */
13473 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13477 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
13479 intel_dump_pipe_config(to_intel_crtc(crtc
),
13480 pipe_config
, "[failed]");
13484 if (i915
.fastboot
&&
13485 intel_pipe_config_compare(dev
,
13486 to_intel_crtc_state(crtc
->state
),
13487 pipe_config
, true)) {
13488 crtc_state
->mode_changed
= false;
13489 to_intel_crtc_state(crtc_state
)->update_pipe
= true;
13492 if (needs_modeset(crtc_state
))
13495 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13499 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13500 needs_modeset(crtc_state
) ?
13501 "[modeset]" : "[fastset]");
13505 ret
= intel_modeset_checks(state
);
13510 intel_state
->cdclk
= dev_priv
->cdclk_freq
;
13512 ret
= drm_atomic_helper_check_planes(dev
, state
);
13516 intel_fbc_choose_crtc(dev_priv
, state
);
13517 return calc_watermark_data(state
);
13520 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
13521 struct drm_atomic_state
*state
,
13524 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13525 struct drm_plane_state
*plane_state
;
13526 struct drm_crtc_state
*crtc_state
;
13527 struct drm_plane
*plane
;
13528 struct drm_crtc
*crtc
;
13531 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13532 if (state
->legacy_cursor_update
)
13535 ret
= intel_crtc_wait_for_pending_flips(crtc
);
13539 if (atomic_read(&to_intel_crtc(crtc
)->unpin_work_count
) >= 2)
13540 flush_workqueue(dev_priv
->wq
);
13543 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
13547 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
13548 mutex_unlock(&dev
->struct_mutex
);
13550 if (!ret
&& !nonblock
) {
13551 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
13552 struct intel_plane_state
*intel_plane_state
=
13553 to_intel_plane_state(plane_state
);
13555 if (!intel_plane_state
->wait_req
)
13558 ret
= __i915_wait_request(intel_plane_state
->wait_req
,
13561 /* Any hang should be swallowed by the wait */
13562 WARN_ON(ret
== -EIO
);
13563 mutex_lock(&dev
->struct_mutex
);
13564 drm_atomic_helper_cleanup_planes(dev
, state
);
13565 mutex_unlock(&dev
->struct_mutex
);
13574 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
13576 struct drm_device
*dev
= crtc
->base
.dev
;
13578 if (!dev
->max_vblank_count
)
13579 return drm_accurate_vblank_count(&crtc
->base
);
13581 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
13584 static void intel_atomic_wait_for_vblanks(struct drm_device
*dev
,
13585 struct drm_i915_private
*dev_priv
,
13586 unsigned crtc_mask
)
13588 unsigned last_vblank_count
[I915_MAX_PIPES
];
13595 for_each_pipe(dev_priv
, pipe
) {
13596 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
13598 if (!((1 << pipe
) & crtc_mask
))
13601 ret
= drm_crtc_vblank_get(crtc
);
13602 if (WARN_ON(ret
!= 0)) {
13603 crtc_mask
&= ~(1 << pipe
);
13607 last_vblank_count
[pipe
] = drm_crtc_vblank_count(crtc
);
13610 for_each_pipe(dev_priv
, pipe
) {
13611 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
13614 if (!((1 << pipe
) & crtc_mask
))
13617 lret
= wait_event_timeout(dev
->vblank
[pipe
].queue
,
13618 last_vblank_count
[pipe
] !=
13619 drm_crtc_vblank_count(crtc
),
13620 msecs_to_jiffies(50));
13622 WARN(!lret
, "pipe %c vblank wait timed out\n", pipe_name(pipe
));
13624 drm_crtc_vblank_put(crtc
);
13628 static bool needs_vblank_wait(struct intel_crtc_state
*crtc_state
)
13630 /* fb updated, need to unpin old fb */
13631 if (crtc_state
->fb_changed
)
13634 /* wm changes, need vblank before final wm's */
13635 if (crtc_state
->update_wm_post
)
13639 * cxsr is re-enabled after vblank.
13640 * This is already handled by crtc_state->update_wm_post,
13641 * but added for clarity.
13643 if (crtc_state
->disable_cxsr
)
13649 static void intel_atomic_commit_tail(struct drm_atomic_state
*state
)
13651 struct drm_device
*dev
= state
->dev
;
13652 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13653 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13654 struct drm_crtc_state
*old_crtc_state
;
13655 struct drm_crtc
*crtc
;
13656 struct intel_crtc_state
*intel_cstate
;
13657 struct drm_plane
*plane
;
13658 struct drm_plane_state
*plane_state
;
13659 bool hw_check
= intel_state
->modeset
;
13660 unsigned long put_domains
[I915_MAX_PIPES
] = {};
13661 unsigned crtc_vblank_mask
= 0;
13664 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
13665 struct intel_plane_state
*intel_plane_state
=
13666 to_intel_plane_state(plane_state
);
13668 if (!intel_plane_state
->wait_req
)
13671 ret
= __i915_wait_request(intel_plane_state
->wait_req
,
13673 /* EIO should be eaten, and we can't get interrupted in the
13674 * worker, and blocking commits have waited already. */
13678 drm_atomic_helper_wait_for_dependencies(state
);
13680 if (intel_state
->modeset
) {
13681 memcpy(dev_priv
->min_pixclk
, intel_state
->min_pixclk
,
13682 sizeof(intel_state
->min_pixclk
));
13683 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
13684 dev_priv
->atomic_cdclk_freq
= intel_state
->cdclk
;
13686 intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
13689 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13690 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13692 if (needs_modeset(crtc
->state
) ||
13693 to_intel_crtc_state(crtc
->state
)->update_pipe
) {
13696 put_domains
[to_intel_crtc(crtc
)->pipe
] =
13697 modeset_get_crtc_power_domains(crtc
,
13698 to_intel_crtc_state(crtc
->state
));
13701 if (!needs_modeset(crtc
->state
))
13704 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
13706 if (old_crtc_state
->active
) {
13707 intel_crtc_disable_planes(crtc
, old_crtc_state
->plane_mask
);
13708 dev_priv
->display
.crtc_disable(crtc
);
13709 intel_crtc
->active
= false;
13710 intel_fbc_disable(intel_crtc
);
13711 intel_disable_shared_dpll(intel_crtc
);
13714 * Underruns don't always raise
13715 * interrupts, so check manually.
13717 intel_check_cpu_fifo_underruns(dev_priv
);
13718 intel_check_pch_fifo_underruns(dev_priv
);
13720 if (!crtc
->state
->active
)
13721 intel_update_watermarks(crtc
);
13725 /* Only after disabling all output pipelines that will be changed can we
13726 * update the the output configuration. */
13727 intel_modeset_update_crtc_state(state
);
13729 if (intel_state
->modeset
) {
13730 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13732 if (dev_priv
->display
.modeset_commit_cdclk
&&
13733 (intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
||
13734 intel_state
->cdclk_pll_vco
!= dev_priv
->cdclk_pll
.vco
))
13735 dev_priv
->display
.modeset_commit_cdclk(state
);
13737 intel_modeset_verify_disabled(dev
);
13740 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13741 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13742 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13743 bool modeset
= needs_modeset(crtc
->state
);
13744 struct intel_crtc_state
*pipe_config
=
13745 to_intel_crtc_state(crtc
->state
);
13747 if (modeset
&& crtc
->state
->active
) {
13748 update_scanline_offset(to_intel_crtc(crtc
));
13749 dev_priv
->display
.crtc_enable(crtc
);
13752 /* Complete events for now disable pipes here. */
13753 if (modeset
&& !crtc
->state
->active
&& crtc
->state
->event
) {
13754 spin_lock_irq(&dev
->event_lock
);
13755 drm_crtc_send_vblank_event(crtc
, crtc
->state
->event
);
13756 spin_unlock_irq(&dev
->event_lock
);
13758 crtc
->state
->event
= NULL
;
13762 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
13764 if (crtc
->state
->active
&&
13765 drm_atomic_get_existing_plane_state(state
, crtc
->primary
))
13766 intel_fbc_enable(intel_crtc
, pipe_config
, to_intel_plane_state(crtc
->primary
->state
));
13768 if (crtc
->state
->active
)
13769 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state
);
13771 if (pipe_config
->base
.active
&& needs_vblank_wait(pipe_config
))
13772 crtc_vblank_mask
|= 1 << i
;
13775 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13776 * already, but still need the state for the delayed optimization. To
13778 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13779 * - schedule that vblank worker _before_ calling hw_done
13780 * - at the start of commit_tail, cancel it _synchrously
13781 * - switch over to the vblank wait helper in the core after that since
13782 * we don't need out special handling any more.
13784 if (!state
->legacy_cursor_update
)
13785 intel_atomic_wait_for_vblanks(dev
, dev_priv
, crtc_vblank_mask
);
13788 * Now that the vblank has passed, we can go ahead and program the
13789 * optimal watermarks on platforms that need two-step watermark
13792 * TODO: Move this (and other cleanup) to an async worker eventually.
13794 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13795 intel_cstate
= to_intel_crtc_state(crtc
->state
);
13797 if (dev_priv
->display
.optimize_watermarks
)
13798 dev_priv
->display
.optimize_watermarks(intel_cstate
);
13801 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
13802 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
13804 if (put_domains
[i
])
13805 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
13807 intel_modeset_verify_crtc(crtc
, old_crtc_state
, crtc
->state
);
13810 drm_atomic_helper_commit_hw_done(state
);
13812 if (intel_state
->modeset
)
13813 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
);
13815 mutex_lock(&dev
->struct_mutex
);
13816 drm_atomic_helper_cleanup_planes(dev
, state
);
13817 mutex_unlock(&dev
->struct_mutex
);
13819 drm_atomic_helper_commit_cleanup_done(state
);
13821 drm_atomic_state_free(state
);
13823 /* As one of the primary mmio accessors, KMS has a high likelihood
13824 * of triggering bugs in unclaimed access. After we finish
13825 * modesetting, see if an error has been flagged, and if so
13826 * enable debugging for the next modeset - and hope we catch
13829 * XXX note that we assume display power is on at this point.
13830 * This might hold true now but we need to add pm helper to check
13831 * unclaimed only when the hardware is on, as atomic commits
13832 * can happen also when the device is completely off.
13834 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
13837 static void intel_atomic_commit_work(struct work_struct
*work
)
13839 struct drm_atomic_state
*state
= container_of(work
,
13840 struct drm_atomic_state
,
13842 intel_atomic_commit_tail(state
);
13845 static void intel_atomic_track_fbs(struct drm_atomic_state
*state
)
13847 struct drm_plane_state
*old_plane_state
;
13848 struct drm_plane
*plane
;
13849 struct drm_i915_gem_object
*obj
, *old_obj
;
13850 struct intel_plane
*intel_plane
;
13853 mutex_lock(&state
->dev
->struct_mutex
);
13854 for_each_plane_in_state(state
, plane
, old_plane_state
, i
) {
13855 obj
= intel_fb_obj(plane
->state
->fb
);
13856 old_obj
= intel_fb_obj(old_plane_state
->fb
);
13857 intel_plane
= to_intel_plane(plane
);
13859 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
13861 mutex_unlock(&state
->dev
->struct_mutex
);
13865 * intel_atomic_commit - commit validated state object
13867 * @state: the top-level driver state object
13868 * @nonblock: nonblocking commit
13870 * This function commits a top-level state object that has been validated
13871 * with drm_atomic_helper_check().
13873 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13874 * nonblocking commits are only safe for pure plane updates. Everything else
13875 * should work though.
13878 * Zero for success or -errno.
13880 static int intel_atomic_commit(struct drm_device
*dev
,
13881 struct drm_atomic_state
*state
,
13884 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13885 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13888 if (intel_state
->modeset
&& nonblock
) {
13889 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
13893 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
13897 INIT_WORK(&state
->commit_work
, intel_atomic_commit_work
);
13899 ret
= intel_atomic_prepare_commit(dev
, state
, nonblock
);
13901 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
13905 drm_atomic_helper_swap_state(state
, true);
13906 dev_priv
->wm
.distrust_bios_wm
= false;
13907 dev_priv
->wm
.skl_results
= intel_state
->wm_results
;
13908 intel_shared_dpll_commit(state
);
13909 intel_atomic_track_fbs(state
);
13912 queue_work(system_unbound_wq
, &state
->commit_work
);
13914 intel_atomic_commit_tail(state
);
13919 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
13921 struct drm_device
*dev
= crtc
->dev
;
13922 struct drm_atomic_state
*state
;
13923 struct drm_crtc_state
*crtc_state
;
13926 state
= drm_atomic_state_alloc(dev
);
13928 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13929 crtc
->base
.id
, crtc
->name
);
13933 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
13936 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13937 ret
= PTR_ERR_OR_ZERO(crtc_state
);
13939 if (!crtc_state
->active
)
13942 crtc_state
->mode_changed
= true;
13943 ret
= drm_atomic_commit(state
);
13946 if (ret
== -EDEADLK
) {
13947 drm_atomic_state_clear(state
);
13948 drm_modeset_backoff(state
->acquire_ctx
);
13954 drm_atomic_state_free(state
);
13957 #undef for_each_intel_crtc_masked
13959 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13960 .gamma_set
= drm_atomic_helper_legacy_gamma_set
,
13961 .set_config
= drm_atomic_helper_set_config
,
13962 .set_property
= drm_atomic_helper_crtc_set_property
,
13963 .destroy
= intel_crtc_destroy
,
13964 .page_flip
= intel_crtc_page_flip
,
13965 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13966 .atomic_destroy_state
= intel_crtc_destroy_state
,
13970 * intel_prepare_plane_fb - Prepare fb for usage on plane
13971 * @plane: drm plane to prepare for
13972 * @fb: framebuffer to prepare for presentation
13974 * Prepares a framebuffer for usage on a display plane. Generally this
13975 * involves pinning the underlying object and updating the frontbuffer tracking
13976 * bits. Some older platforms need special physical address handling for
13979 * Must be called with struct_mutex held.
13981 * Returns 0 on success, negative error code on failure.
13984 intel_prepare_plane_fb(struct drm_plane
*plane
,
13985 const struct drm_plane_state
*new_state
)
13987 struct drm_device
*dev
= plane
->dev
;
13988 struct drm_framebuffer
*fb
= new_state
->fb
;
13989 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13990 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
13991 struct reservation_object
*resv
;
13994 if (!obj
&& !old_obj
)
13998 struct drm_crtc_state
*crtc_state
=
13999 drm_atomic_get_existing_crtc_state(new_state
->state
, plane
->state
->crtc
);
14001 /* Big Hammer, we also need to ensure that any pending
14002 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14003 * current scanout is retired before unpinning the old
14004 * framebuffer. Note that we rely on userspace rendering
14005 * into the buffer attached to the pipe they are waiting
14006 * on. If not, userspace generates a GPU hang with IPEHR
14007 * point to the MI_WAIT_FOR_EVENT.
14009 * This should only fail upon a hung GPU, in which case we
14010 * can safely continue.
14012 if (needs_modeset(crtc_state
))
14013 ret
= i915_gem_object_wait_rendering(old_obj
, true);
14015 /* GPU hangs should have been swallowed by the wait */
14016 WARN_ON(ret
== -EIO
);
14024 /* For framebuffer backed by dmabuf, wait for fence */
14025 resv
= i915_gem_object_get_dmabuf_resv(obj
);
14029 lret
= reservation_object_wait_timeout_rcu(resv
, false, true,
14030 MAX_SCHEDULE_TIMEOUT
);
14031 if (lret
== -ERESTARTSYS
)
14034 WARN(lret
< 0, "waiting returns %li\n", lret
);
14037 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
14038 INTEL_INFO(dev
)->cursor_needs_physical
) {
14039 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
14040 ret
= i915_gem_object_attach_phys(obj
, align
);
14042 DRM_DEBUG_KMS("failed to attach phys object\n");
14044 ret
= intel_pin_and_fence_fb_obj(fb
, new_state
->rotation
);
14048 struct intel_plane_state
*plane_state
=
14049 to_intel_plane_state(new_state
);
14051 i915_gem_request_assign(&plane_state
->wait_req
,
14052 obj
->last_write_req
);
14059 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14060 * @plane: drm plane to clean up for
14061 * @fb: old framebuffer that was on plane
14063 * Cleans up a framebuffer that has just been removed from a plane.
14065 * Must be called with struct_mutex held.
14068 intel_cleanup_plane_fb(struct drm_plane
*plane
,
14069 const struct drm_plane_state
*old_state
)
14071 struct drm_device
*dev
= plane
->dev
;
14072 struct intel_plane_state
*old_intel_state
;
14073 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_state
->fb
);
14074 struct drm_i915_gem_object
*obj
= intel_fb_obj(plane
->state
->fb
);
14076 old_intel_state
= to_intel_plane_state(old_state
);
14078 if (!obj
&& !old_obj
)
14081 if (old_obj
&& (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
14082 !INTEL_INFO(dev
)->cursor_needs_physical
))
14083 intel_unpin_fb_obj(old_state
->fb
, old_state
->rotation
);
14085 i915_gem_request_assign(&old_intel_state
->wait_req
, NULL
);
14089 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
14092 int crtc_clock
, cdclk
;
14094 if (!intel_crtc
|| !crtc_state
->base
.enable
)
14095 return DRM_PLANE_HELPER_NO_SCALING
;
14097 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
14098 cdclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
;
14100 if (WARN_ON_ONCE(!crtc_clock
|| cdclk
< crtc_clock
))
14101 return DRM_PLANE_HELPER_NO_SCALING
;
14104 * skl max scale is lower of:
14105 * close to 3 but not 3, -1 is for that purpose
14109 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
14115 intel_check_primary_plane(struct drm_plane
*plane
,
14116 struct intel_crtc_state
*crtc_state
,
14117 struct intel_plane_state
*state
)
14119 struct drm_crtc
*crtc
= state
->base
.crtc
;
14120 struct drm_framebuffer
*fb
= state
->base
.fb
;
14121 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
14122 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
14123 bool can_position
= false;
14125 if (INTEL_INFO(plane
->dev
)->gen
>= 9) {
14126 /* use scaler when colorkey is not required */
14127 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
14129 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
14131 can_position
= true;
14134 return drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
14135 &state
->dst
, &state
->clip
,
14136 state
->base
.rotation
,
14137 min_scale
, max_scale
,
14138 can_position
, true,
14142 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
14143 struct drm_crtc_state
*old_crtc_state
)
14145 struct drm_device
*dev
= crtc
->dev
;
14146 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14147 struct intel_crtc_state
*old_intel_state
=
14148 to_intel_crtc_state(old_crtc_state
);
14149 bool modeset
= needs_modeset(crtc
->state
);
14151 /* Perform vblank evasion around commit operation */
14152 intel_pipe_update_start(intel_crtc
);
14157 if (crtc
->state
->color_mgmt_changed
|| to_intel_crtc_state(crtc
->state
)->update_pipe
) {
14158 intel_color_set_csc(crtc
->state
);
14159 intel_color_load_luts(crtc
->state
);
14162 if (to_intel_crtc_state(crtc
->state
)->update_pipe
)
14163 intel_update_pipe_config(intel_crtc
, old_intel_state
);
14164 else if (INTEL_INFO(dev
)->gen
>= 9)
14165 skl_detach_scalers(intel_crtc
);
14168 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
14169 struct drm_crtc_state
*old_crtc_state
)
14171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14173 intel_pipe_update_end(intel_crtc
, NULL
);
14177 * intel_plane_destroy - destroy a plane
14178 * @plane: plane to destroy
14180 * Common destruction function for all types of planes (primary, cursor,
14183 void intel_plane_destroy(struct drm_plane
*plane
)
14188 drm_plane_cleanup(plane
);
14189 kfree(to_intel_plane(plane
));
14192 const struct drm_plane_funcs intel_plane_funcs
= {
14193 .update_plane
= drm_atomic_helper_update_plane
,
14194 .disable_plane
= drm_atomic_helper_disable_plane
,
14195 .destroy
= intel_plane_destroy
,
14196 .set_property
= drm_atomic_helper_plane_set_property
,
14197 .atomic_get_property
= intel_plane_atomic_get_property
,
14198 .atomic_set_property
= intel_plane_atomic_set_property
,
14199 .atomic_duplicate_state
= intel_plane_duplicate_state
,
14200 .atomic_destroy_state
= intel_plane_destroy_state
,
14204 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
14207 struct intel_plane
*primary
= NULL
;
14208 struct intel_plane_state
*state
= NULL
;
14209 const uint32_t *intel_primary_formats
;
14210 unsigned int num_formats
;
14213 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
14217 state
= intel_create_plane_state(&primary
->base
);
14220 primary
->base
.state
= &state
->base
;
14222 primary
->can_scale
= false;
14223 primary
->max_downscale
= 1;
14224 if (INTEL_INFO(dev
)->gen
>= 9) {
14225 primary
->can_scale
= true;
14226 state
->scaler_id
= -1;
14228 primary
->pipe
= pipe
;
14229 primary
->plane
= pipe
;
14230 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
14231 primary
->check_plane
= intel_check_primary_plane
;
14232 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
14233 primary
->plane
= !pipe
;
14235 if (INTEL_INFO(dev
)->gen
>= 9) {
14236 intel_primary_formats
= skl_primary_formats
;
14237 num_formats
= ARRAY_SIZE(skl_primary_formats
);
14239 primary
->update_plane
= skylake_update_primary_plane
;
14240 primary
->disable_plane
= skylake_disable_primary_plane
;
14241 } else if (HAS_PCH_SPLIT(dev
)) {
14242 intel_primary_formats
= i965_primary_formats
;
14243 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14245 primary
->update_plane
= ironlake_update_primary_plane
;
14246 primary
->disable_plane
= i9xx_disable_primary_plane
;
14247 } else if (INTEL_INFO(dev
)->gen
>= 4) {
14248 intel_primary_formats
= i965_primary_formats
;
14249 num_formats
= ARRAY_SIZE(i965_primary_formats
);
14251 primary
->update_plane
= i9xx_update_primary_plane
;
14252 primary
->disable_plane
= i9xx_disable_primary_plane
;
14254 intel_primary_formats
= i8xx_primary_formats
;
14255 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
14257 primary
->update_plane
= i9xx_update_primary_plane
;
14258 primary
->disable_plane
= i9xx_disable_primary_plane
;
14261 if (INTEL_INFO(dev
)->gen
>= 9)
14262 ret
= drm_universal_plane_init(dev
, &primary
->base
, 0,
14263 &intel_plane_funcs
,
14264 intel_primary_formats
, num_formats
,
14265 DRM_PLANE_TYPE_PRIMARY
,
14266 "plane 1%c", pipe_name(pipe
));
14267 else if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
14268 ret
= drm_universal_plane_init(dev
, &primary
->base
, 0,
14269 &intel_plane_funcs
,
14270 intel_primary_formats
, num_formats
,
14271 DRM_PLANE_TYPE_PRIMARY
,
14272 "primary %c", pipe_name(pipe
));
14274 ret
= drm_universal_plane_init(dev
, &primary
->base
, 0,
14275 &intel_plane_funcs
,
14276 intel_primary_formats
, num_formats
,
14277 DRM_PLANE_TYPE_PRIMARY
,
14278 "plane %c", plane_name(primary
->plane
));
14282 if (INTEL_INFO(dev
)->gen
>= 4)
14283 intel_create_rotation_property(dev
, primary
);
14285 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
14287 return &primary
->base
;
14296 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
14298 if (!dev
->mode_config
.rotation_property
) {
14299 unsigned long flags
= BIT(DRM_ROTATE_0
) |
14300 BIT(DRM_ROTATE_180
);
14302 if (INTEL_INFO(dev
)->gen
>= 9)
14303 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
14305 dev
->mode_config
.rotation_property
=
14306 drm_mode_create_rotation_property(dev
, flags
);
14308 if (dev
->mode_config
.rotation_property
)
14309 drm_object_attach_property(&plane
->base
.base
,
14310 dev
->mode_config
.rotation_property
,
14311 plane
->base
.state
->rotation
);
14315 intel_check_cursor_plane(struct drm_plane
*plane
,
14316 struct intel_crtc_state
*crtc_state
,
14317 struct intel_plane_state
*state
)
14319 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
14320 struct drm_framebuffer
*fb
= state
->base
.fb
;
14321 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14322 enum pipe pipe
= to_intel_plane(plane
)->pipe
;
14326 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
14327 &state
->dst
, &state
->clip
,
14328 state
->base
.rotation
,
14329 DRM_PLANE_HELPER_NO_SCALING
,
14330 DRM_PLANE_HELPER_NO_SCALING
,
14331 true, true, &state
->visible
);
14335 /* if we want to turn off the cursor ignore width and height */
14339 /* Check for which cursor types we support */
14340 if (!cursor_size_ok(plane
->dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
14341 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14342 state
->base
.crtc_w
, state
->base
.crtc_h
);
14346 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
14347 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
14348 DRM_DEBUG_KMS("buffer is too small\n");
14352 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
14353 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14358 * There's something wrong with the cursor on CHV pipe C.
14359 * If it straddles the left edge of the screen then
14360 * moving it away from the edge or disabling it often
14361 * results in a pipe underrun, and often that can lead to
14362 * dead pipe (constant underrun reported, and it scans
14363 * out just a solid color). To recover from that, the
14364 * display power well must be turned off and on again.
14365 * Refuse the put the cursor into that compromised position.
14367 if (IS_CHERRYVIEW(plane
->dev
) && pipe
== PIPE_C
&&
14368 state
->visible
&& state
->base
.crtc_x
< 0) {
14369 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14377 intel_disable_cursor_plane(struct drm_plane
*plane
,
14378 struct drm_crtc
*crtc
)
14380 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14382 intel_crtc
->cursor_addr
= 0;
14383 intel_crtc_update_cursor(crtc
, NULL
);
14387 intel_update_cursor_plane(struct drm_plane
*plane
,
14388 const struct intel_crtc_state
*crtc_state
,
14389 const struct intel_plane_state
*state
)
14391 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
14392 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14393 struct drm_device
*dev
= plane
->dev
;
14394 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
14399 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
14400 addr
= i915_gem_obj_ggtt_offset(obj
);
14402 addr
= obj
->phys_handle
->busaddr
;
14404 intel_crtc
->cursor_addr
= addr
;
14405 intel_crtc_update_cursor(crtc
, state
);
14408 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
14411 struct intel_plane
*cursor
= NULL
;
14412 struct intel_plane_state
*state
= NULL
;
14415 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
14419 state
= intel_create_plane_state(&cursor
->base
);
14422 cursor
->base
.state
= &state
->base
;
14424 cursor
->can_scale
= false;
14425 cursor
->max_downscale
= 1;
14426 cursor
->pipe
= pipe
;
14427 cursor
->plane
= pipe
;
14428 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
14429 cursor
->check_plane
= intel_check_cursor_plane
;
14430 cursor
->update_plane
= intel_update_cursor_plane
;
14431 cursor
->disable_plane
= intel_disable_cursor_plane
;
14433 ret
= drm_universal_plane_init(dev
, &cursor
->base
, 0,
14434 &intel_plane_funcs
,
14435 intel_cursor_formats
,
14436 ARRAY_SIZE(intel_cursor_formats
),
14437 DRM_PLANE_TYPE_CURSOR
,
14438 "cursor %c", pipe_name(pipe
));
14442 if (INTEL_INFO(dev
)->gen
>= 4) {
14443 if (!dev
->mode_config
.rotation_property
)
14444 dev
->mode_config
.rotation_property
=
14445 drm_mode_create_rotation_property(dev
,
14446 BIT(DRM_ROTATE_0
) |
14447 BIT(DRM_ROTATE_180
));
14448 if (dev
->mode_config
.rotation_property
)
14449 drm_object_attach_property(&cursor
->base
.base
,
14450 dev
->mode_config
.rotation_property
,
14451 state
->base
.rotation
);
14454 if (INTEL_INFO(dev
)->gen
>=9)
14455 state
->scaler_id
= -1;
14457 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14459 return &cursor
->base
;
14468 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
14469 struct intel_crtc_state
*crtc_state
)
14472 struct intel_scaler
*intel_scaler
;
14473 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
14475 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
14476 intel_scaler
= &scaler_state
->scalers
[i
];
14477 intel_scaler
->in_use
= 0;
14478 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
14481 scaler_state
->scaler_id
= -1;
14484 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
14486 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14487 struct intel_crtc
*intel_crtc
;
14488 struct intel_crtc_state
*crtc_state
= NULL
;
14489 struct drm_plane
*primary
= NULL
;
14490 struct drm_plane
*cursor
= NULL
;
14493 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14494 if (intel_crtc
== NULL
)
14497 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14500 intel_crtc
->config
= crtc_state
;
14501 intel_crtc
->base
.state
= &crtc_state
->base
;
14502 crtc_state
->base
.crtc
= &intel_crtc
->base
;
14504 /* initialize shared scalers */
14505 if (INTEL_INFO(dev
)->gen
>= 9) {
14506 if (pipe
== PIPE_C
)
14507 intel_crtc
->num_scalers
= 1;
14509 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
14511 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
14514 primary
= intel_primary_plane_create(dev
, pipe
);
14518 cursor
= intel_cursor_plane_create(dev
, pipe
);
14522 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
14523 cursor
, &intel_crtc_funcs
,
14524 "pipe %c", pipe_name(pipe
));
14529 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14530 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14532 intel_crtc
->pipe
= pipe
;
14533 intel_crtc
->plane
= pipe
;
14534 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
14535 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14536 intel_crtc
->plane
= !pipe
;
14539 intel_crtc
->cursor_base
= ~0;
14540 intel_crtc
->cursor_cntl
= ~0;
14541 intel_crtc
->cursor_size
= ~0;
14543 intel_crtc
->wm
.cxsr_allowed
= true;
14545 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14546 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
14547 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
14548 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
14550 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14552 intel_color_init(&intel_crtc
->base
);
14554 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14558 intel_plane_destroy(primary
);
14559 intel_plane_destroy(cursor
);
14564 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
14566 struct drm_encoder
*encoder
= connector
->base
.encoder
;
14567 struct drm_device
*dev
= connector
->base
.dev
;
14569 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
14571 if (!encoder
|| WARN_ON(!encoder
->crtc
))
14572 return INVALID_PIPE
;
14574 return to_intel_crtc(encoder
->crtc
)->pipe
;
14577 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
14578 struct drm_file
*file
)
14580 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14581 struct drm_crtc
*drmmode_crtc
;
14582 struct intel_crtc
*crtc
;
14584 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
14588 crtc
= to_intel_crtc(drmmode_crtc
);
14589 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14594 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14596 struct drm_device
*dev
= encoder
->base
.dev
;
14597 struct intel_encoder
*source_encoder
;
14598 int index_mask
= 0;
14601 for_each_intel_encoder(dev
, source_encoder
) {
14602 if (encoders_cloneable(encoder
, source_encoder
))
14603 index_mask
|= (1 << entry
);
14611 static bool has_edp_a(struct drm_device
*dev
)
14613 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14615 if (!IS_MOBILE(dev
))
14618 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14621 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14627 static bool intel_crt_present(struct drm_device
*dev
)
14629 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14631 if (INTEL_INFO(dev
)->gen
>= 9)
14634 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
14637 if (IS_CHERRYVIEW(dev
))
14640 if (HAS_PCH_LPT_H(dev
) && I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
14643 /* DDI E can't be used if DDI A requires 4 lanes */
14644 if (HAS_DDI(dev
) && I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
14647 if (!dev_priv
->vbt
.int_crt_support
)
14653 static void intel_setup_outputs(struct drm_device
*dev
)
14655 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14656 struct intel_encoder
*encoder
;
14657 bool dpd_is_edp
= false;
14660 * intel_edp_init_connector() depends on this completing first, to
14661 * prevent the registeration of both eDP and LVDS and the incorrect
14662 * sharing of the PPS.
14664 intel_lvds_init(dev
);
14666 if (intel_crt_present(dev
))
14667 intel_crt_init(dev
);
14669 if (IS_BROXTON(dev
)) {
14671 * FIXME: Broxton doesn't support port detection via the
14672 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14673 * detect the ports.
14675 intel_ddi_init(dev
, PORT_A
);
14676 intel_ddi_init(dev
, PORT_B
);
14677 intel_ddi_init(dev
, PORT_C
);
14679 intel_dsi_init(dev
);
14680 } else if (HAS_DDI(dev
)) {
14684 * Haswell uses DDI functions to detect digital outputs.
14685 * On SKL pre-D0 the strap isn't connected, so we assume
14688 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
14689 /* WaIgnoreDDIAStrap: skl */
14690 if (found
|| IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
14691 intel_ddi_init(dev
, PORT_A
);
14693 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14695 found
= I915_READ(SFUSE_STRAP
);
14697 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14698 intel_ddi_init(dev
, PORT_B
);
14699 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14700 intel_ddi_init(dev
, PORT_C
);
14701 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14702 intel_ddi_init(dev
, PORT_D
);
14704 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14706 if ((IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) &&
14707 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
14708 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
14709 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
14710 intel_ddi_init(dev
, PORT_E
);
14712 } else if (HAS_PCH_SPLIT(dev
)) {
14714 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
14716 if (has_edp_a(dev
))
14717 intel_dp_init(dev
, DP_A
, PORT_A
);
14719 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14720 /* PCH SDVOB multiplex with HDMIB */
14721 found
= intel_sdvo_init(dev
, PCH_SDVOB
, PORT_B
);
14723 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
14724 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14725 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
14728 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14729 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
14731 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14732 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
14734 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14735 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
14737 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14738 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
14739 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
14740 bool has_edp
, has_port
;
14743 * The DP_DETECTED bit is the latched state of the DDC
14744 * SDA pin at boot. However since eDP doesn't require DDC
14745 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14746 * eDP ports may have been muxed to an alternate function.
14747 * Thus we can't rely on the DP_DETECTED bit alone to detect
14748 * eDP ports. Consult the VBT as well as DP_DETECTED to
14749 * detect eDP ports.
14751 * Sadly the straps seem to be missing sometimes even for HDMI
14752 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14753 * and VBT for the presence of the port. Additionally we can't
14754 * trust the port type the VBT declares as we've seen at least
14755 * HDMI ports that the VBT claim are DP or eDP.
14757 has_edp
= intel_dp_is_edp(dev
, PORT_B
);
14758 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
14759 if (I915_READ(VLV_DP_B
) & DP_DETECTED
|| has_port
)
14760 has_edp
&= intel_dp_init(dev
, VLV_DP_B
, PORT_B
);
14761 if ((I915_READ(VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
14762 intel_hdmi_init(dev
, VLV_HDMIB
, PORT_B
);
14764 has_edp
= intel_dp_is_edp(dev
, PORT_C
);
14765 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
14766 if (I915_READ(VLV_DP_C
) & DP_DETECTED
|| has_port
)
14767 has_edp
&= intel_dp_init(dev
, VLV_DP_C
, PORT_C
);
14768 if ((I915_READ(VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
14769 intel_hdmi_init(dev
, VLV_HDMIC
, PORT_C
);
14771 if (IS_CHERRYVIEW(dev
)) {
14773 * eDP not supported on port D,
14774 * so no need to worry about it
14776 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
14777 if (I915_READ(CHV_DP_D
) & DP_DETECTED
|| has_port
)
14778 intel_dp_init(dev
, CHV_DP_D
, PORT_D
);
14779 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
14780 intel_hdmi_init(dev
, CHV_HDMID
, PORT_D
);
14783 intel_dsi_init(dev
);
14784 } else if (!IS_GEN2(dev
) && !IS_PINEVIEW(dev
)) {
14785 bool found
= false;
14787 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14788 DRM_DEBUG_KMS("probing SDVOB\n");
14789 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, PORT_B
);
14790 if (!found
&& IS_G4X(dev
)) {
14791 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14792 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14795 if (!found
&& IS_G4X(dev
))
14796 intel_dp_init(dev
, DP_B
, PORT_B
);
14799 /* Before G4X SDVOC doesn't have its own detect register */
14801 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14802 DRM_DEBUG_KMS("probing SDVOC\n");
14803 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, PORT_C
);
14806 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14809 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14810 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14813 intel_dp_init(dev
, DP_C
, PORT_C
);
14817 (I915_READ(DP_D
) & DP_DETECTED
))
14818 intel_dp_init(dev
, DP_D
, PORT_D
);
14819 } else if (IS_GEN2(dev
))
14820 intel_dvo_init(dev
);
14822 if (SUPPORTS_TV(dev
))
14823 intel_tv_init(dev
);
14825 intel_psr_init(dev
);
14827 for_each_intel_encoder(dev
, encoder
) {
14828 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14829 encoder
->base
.possible_clones
=
14830 intel_encoder_clones(encoder
);
14833 intel_init_pch_refclk(dev
);
14835 drm_helper_move_panel_connectors_to_head(dev
);
14838 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14840 struct drm_device
*dev
= fb
->dev
;
14841 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14843 drm_framebuffer_cleanup(fb
);
14844 mutex_lock(&dev
->struct_mutex
);
14845 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14846 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14847 mutex_unlock(&dev
->struct_mutex
);
14851 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14852 struct drm_file
*file
,
14853 unsigned int *handle
)
14855 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14856 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14858 if (obj
->userptr
.mm
) {
14859 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14863 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14866 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
14867 struct drm_file
*file
,
14868 unsigned flags
, unsigned color
,
14869 struct drm_clip_rect
*clips
,
14870 unsigned num_clips
)
14872 struct drm_device
*dev
= fb
->dev
;
14873 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14874 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14876 mutex_lock(&dev
->struct_mutex
);
14877 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
14878 mutex_unlock(&dev
->struct_mutex
);
14883 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14884 .destroy
= intel_user_framebuffer_destroy
,
14885 .create_handle
= intel_user_framebuffer_create_handle
,
14886 .dirty
= intel_user_framebuffer_dirty
,
14890 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14891 uint32_t pixel_format
)
14893 u32 gen
= INTEL_INFO(dev
)->gen
;
14896 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
14898 /* "The stride in bytes must not exceed the of the size of 8K
14899 * pixels and 32K bytes."
14901 return min(8192 * cpp
, 32768);
14902 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
14904 } else if (gen
>= 4) {
14905 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14909 } else if (gen
>= 3) {
14910 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14915 /* XXX DSPC is limited to 4k tiled */
14920 static int intel_framebuffer_init(struct drm_device
*dev
,
14921 struct intel_framebuffer
*intel_fb
,
14922 struct drm_mode_fb_cmd2
*mode_cmd
,
14923 struct drm_i915_gem_object
*obj
)
14925 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14926 unsigned int aligned_height
;
14928 u32 pitch_limit
, stride_alignment
;
14930 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14932 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14933 /* Enforce that fb modifier and tiling mode match, but only for
14934 * X-tiled. This is needed for FBC. */
14935 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14936 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14937 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14941 if (obj
->tiling_mode
== I915_TILING_X
)
14942 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14943 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14944 DRM_DEBUG("No Y tiling for legacy addfb\n");
14949 /* Passed in modifier sanity checking. */
14950 switch (mode_cmd
->modifier
[0]) {
14951 case I915_FORMAT_MOD_Y_TILED
:
14952 case I915_FORMAT_MOD_Yf_TILED
:
14953 if (INTEL_INFO(dev
)->gen
< 9) {
14954 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14955 mode_cmd
->modifier
[0]);
14958 case DRM_FORMAT_MOD_NONE
:
14959 case I915_FORMAT_MOD_X_TILED
:
14962 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14963 mode_cmd
->modifier
[0]);
14967 stride_alignment
= intel_fb_stride_alignment(dev_priv
,
14968 mode_cmd
->modifier
[0],
14969 mode_cmd
->pixel_format
);
14970 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14971 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14972 mode_cmd
->pitches
[0], stride_alignment
);
14976 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14977 mode_cmd
->pixel_format
);
14978 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14979 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14980 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14981 "tiled" : "linear",
14982 mode_cmd
->pitches
[0], pitch_limit
);
14986 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14987 mode_cmd
->pitches
[0] != obj
->stride
) {
14988 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14989 mode_cmd
->pitches
[0], obj
->stride
);
14993 /* Reject formats not supported by any plane early. */
14994 switch (mode_cmd
->pixel_format
) {
14995 case DRM_FORMAT_C8
:
14996 case DRM_FORMAT_RGB565
:
14997 case DRM_FORMAT_XRGB8888
:
14998 case DRM_FORMAT_ARGB8888
:
15000 case DRM_FORMAT_XRGB1555
:
15001 if (INTEL_INFO(dev
)->gen
> 3) {
15002 DRM_DEBUG("unsupported pixel format: %s\n",
15003 drm_get_format_name(mode_cmd
->pixel_format
));
15007 case DRM_FORMAT_ABGR8888
:
15008 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
15009 INTEL_INFO(dev
)->gen
< 9) {
15010 DRM_DEBUG("unsupported pixel format: %s\n",
15011 drm_get_format_name(mode_cmd
->pixel_format
));
15015 case DRM_FORMAT_XBGR8888
:
15016 case DRM_FORMAT_XRGB2101010
:
15017 case DRM_FORMAT_XBGR2101010
:
15018 if (INTEL_INFO(dev
)->gen
< 4) {
15019 DRM_DEBUG("unsupported pixel format: %s\n",
15020 drm_get_format_name(mode_cmd
->pixel_format
));
15024 case DRM_FORMAT_ABGR2101010
:
15025 if (!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
15026 DRM_DEBUG("unsupported pixel format: %s\n",
15027 drm_get_format_name(mode_cmd
->pixel_format
));
15031 case DRM_FORMAT_YUYV
:
15032 case DRM_FORMAT_UYVY
:
15033 case DRM_FORMAT_YVYU
:
15034 case DRM_FORMAT_VYUY
:
15035 if (INTEL_INFO(dev
)->gen
< 5) {
15036 DRM_DEBUG("unsupported pixel format: %s\n",
15037 drm_get_format_name(mode_cmd
->pixel_format
));
15042 DRM_DEBUG("unsupported pixel format: %s\n",
15043 drm_get_format_name(mode_cmd
->pixel_format
));
15047 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15048 if (mode_cmd
->offsets
[0] != 0)
15051 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
15052 mode_cmd
->pixel_format
,
15053 mode_cmd
->modifier
[0]);
15054 /* FIXME drm helper for size checks (especially planar formats)? */
15055 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
15058 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
15059 intel_fb
->obj
= obj
;
15061 intel_fill_fb_info(dev_priv
, &intel_fb
->base
);
15063 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
15065 DRM_ERROR("framebuffer init failed %d\n", ret
);
15069 intel_fb
->obj
->framebuffer_references
++;
15074 static struct drm_framebuffer
*
15075 intel_user_framebuffer_create(struct drm_device
*dev
,
15076 struct drm_file
*filp
,
15077 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
15079 struct drm_framebuffer
*fb
;
15080 struct drm_i915_gem_object
*obj
;
15081 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
15083 obj
= to_intel_bo(drm_gem_object_lookup(filp
, mode_cmd
.handles
[0]));
15084 if (&obj
->base
== NULL
)
15085 return ERR_PTR(-ENOENT
);
15087 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
15089 drm_gem_object_unreference_unlocked(&obj
->base
);
15094 #ifndef CONFIG_DRM_FBDEV_EMULATION
15095 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
15100 static const struct drm_mode_config_funcs intel_mode_funcs
= {
15101 .fb_create
= intel_user_framebuffer_create
,
15102 .output_poll_changed
= intel_fbdev_output_poll_changed
,
15103 .atomic_check
= intel_atomic_check
,
15104 .atomic_commit
= intel_atomic_commit
,
15105 .atomic_state_alloc
= intel_atomic_state_alloc
,
15106 .atomic_state_clear
= intel_atomic_state_clear
,
15110 * intel_init_display_hooks - initialize the display modesetting hooks
15111 * @dev_priv: device private
15113 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
15115 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
15116 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15117 dev_priv
->display
.get_initial_plane_config
=
15118 skylake_get_initial_plane_config
;
15119 dev_priv
->display
.crtc_compute_clock
=
15120 haswell_crtc_compute_clock
;
15121 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15122 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15123 } else if (HAS_DDI(dev_priv
)) {
15124 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
15125 dev_priv
->display
.get_initial_plane_config
=
15126 ironlake_get_initial_plane_config
;
15127 dev_priv
->display
.crtc_compute_clock
=
15128 haswell_crtc_compute_clock
;
15129 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
15130 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
15131 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15132 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
15133 dev_priv
->display
.get_initial_plane_config
=
15134 ironlake_get_initial_plane_config
;
15135 dev_priv
->display
.crtc_compute_clock
=
15136 ironlake_crtc_compute_clock
;
15137 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
15138 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
15139 } else if (IS_CHERRYVIEW(dev_priv
)) {
15140 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15141 dev_priv
->display
.get_initial_plane_config
=
15142 i9xx_get_initial_plane_config
;
15143 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
15144 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15145 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15146 } else if (IS_VALLEYVIEW(dev_priv
)) {
15147 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15148 dev_priv
->display
.get_initial_plane_config
=
15149 i9xx_get_initial_plane_config
;
15150 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
15151 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
15152 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15153 } else if (IS_G4X(dev_priv
)) {
15154 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15155 dev_priv
->display
.get_initial_plane_config
=
15156 i9xx_get_initial_plane_config
;
15157 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
15158 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15159 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15160 } else if (IS_PINEVIEW(dev_priv
)) {
15161 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15162 dev_priv
->display
.get_initial_plane_config
=
15163 i9xx_get_initial_plane_config
;
15164 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
15165 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15166 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15167 } else if (!IS_GEN2(dev_priv
)) {
15168 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15169 dev_priv
->display
.get_initial_plane_config
=
15170 i9xx_get_initial_plane_config
;
15171 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
15172 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15173 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15175 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
15176 dev_priv
->display
.get_initial_plane_config
=
15177 i9xx_get_initial_plane_config
;
15178 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
15179 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
15180 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
15183 /* Returns the core display clock speed */
15184 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
15185 dev_priv
->display
.get_display_clock_speed
=
15186 skylake_get_display_clock_speed
;
15187 else if (IS_BROXTON(dev_priv
))
15188 dev_priv
->display
.get_display_clock_speed
=
15189 broxton_get_display_clock_speed
;
15190 else if (IS_BROADWELL(dev_priv
))
15191 dev_priv
->display
.get_display_clock_speed
=
15192 broadwell_get_display_clock_speed
;
15193 else if (IS_HASWELL(dev_priv
))
15194 dev_priv
->display
.get_display_clock_speed
=
15195 haswell_get_display_clock_speed
;
15196 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15197 dev_priv
->display
.get_display_clock_speed
=
15198 valleyview_get_display_clock_speed
;
15199 else if (IS_GEN5(dev_priv
))
15200 dev_priv
->display
.get_display_clock_speed
=
15201 ilk_get_display_clock_speed
;
15202 else if (IS_I945G(dev_priv
) || IS_BROADWATER(dev_priv
) ||
15203 IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
))
15204 dev_priv
->display
.get_display_clock_speed
=
15205 i945_get_display_clock_speed
;
15206 else if (IS_GM45(dev_priv
))
15207 dev_priv
->display
.get_display_clock_speed
=
15208 gm45_get_display_clock_speed
;
15209 else if (IS_CRESTLINE(dev_priv
))
15210 dev_priv
->display
.get_display_clock_speed
=
15211 i965gm_get_display_clock_speed
;
15212 else if (IS_PINEVIEW(dev_priv
))
15213 dev_priv
->display
.get_display_clock_speed
=
15214 pnv_get_display_clock_speed
;
15215 else if (IS_G33(dev_priv
) || IS_G4X(dev_priv
))
15216 dev_priv
->display
.get_display_clock_speed
=
15217 g33_get_display_clock_speed
;
15218 else if (IS_I915G(dev_priv
))
15219 dev_priv
->display
.get_display_clock_speed
=
15220 i915_get_display_clock_speed
;
15221 else if (IS_I945GM(dev_priv
) || IS_845G(dev_priv
))
15222 dev_priv
->display
.get_display_clock_speed
=
15223 i9xx_misc_get_display_clock_speed
;
15224 else if (IS_I915GM(dev_priv
))
15225 dev_priv
->display
.get_display_clock_speed
=
15226 i915gm_get_display_clock_speed
;
15227 else if (IS_I865G(dev_priv
))
15228 dev_priv
->display
.get_display_clock_speed
=
15229 i865_get_display_clock_speed
;
15230 else if (IS_I85X(dev_priv
))
15231 dev_priv
->display
.get_display_clock_speed
=
15232 i85x_get_display_clock_speed
;
15234 WARN(!IS_I830(dev_priv
), "Unknown platform. Assuming 133 MHz CDCLK\n");
15235 dev_priv
->display
.get_display_clock_speed
=
15236 i830_get_display_clock_speed
;
15239 if (IS_GEN5(dev_priv
)) {
15240 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
15241 } else if (IS_GEN6(dev_priv
)) {
15242 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
15243 } else if (IS_IVYBRIDGE(dev_priv
)) {
15244 /* FIXME: detect B0+ stepping and use auto training */
15245 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
15246 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
15247 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
15250 if (IS_BROADWELL(dev_priv
)) {
15251 dev_priv
->display
.modeset_commit_cdclk
=
15252 broadwell_modeset_commit_cdclk
;
15253 dev_priv
->display
.modeset_calc_cdclk
=
15254 broadwell_modeset_calc_cdclk
;
15255 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15256 dev_priv
->display
.modeset_commit_cdclk
=
15257 valleyview_modeset_commit_cdclk
;
15258 dev_priv
->display
.modeset_calc_cdclk
=
15259 valleyview_modeset_calc_cdclk
;
15260 } else if (IS_BROXTON(dev_priv
)) {
15261 dev_priv
->display
.modeset_commit_cdclk
=
15262 bxt_modeset_commit_cdclk
;
15263 dev_priv
->display
.modeset_calc_cdclk
=
15264 bxt_modeset_calc_cdclk
;
15265 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
15266 dev_priv
->display
.modeset_commit_cdclk
=
15267 skl_modeset_commit_cdclk
;
15268 dev_priv
->display
.modeset_calc_cdclk
=
15269 skl_modeset_calc_cdclk
;
15272 switch (INTEL_INFO(dev_priv
)->gen
) {
15274 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
15278 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
15283 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
15287 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
15290 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15291 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
15294 /* Drop through - unsupported since execlist only. */
15296 /* Default just returns -ENODEV to indicate unsupported */
15297 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
15302 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15303 * resume, or other times. This quirk makes sure that's the case for
15304 * affected systems.
15306 static void quirk_pipea_force(struct drm_device
*dev
)
15308 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15310 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
15311 DRM_INFO("applying pipe a force quirk\n");
15314 static void quirk_pipeb_force(struct drm_device
*dev
)
15316 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15318 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
15319 DRM_INFO("applying pipe b force quirk\n");
15323 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15325 static void quirk_ssc_force_disable(struct drm_device
*dev
)
15327 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15328 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
15329 DRM_INFO("applying lvds SSC disable quirk\n");
15333 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15336 static void quirk_invert_brightness(struct drm_device
*dev
)
15338 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15339 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
15340 DRM_INFO("applying inverted panel brightness quirk\n");
15343 /* Some VBT's incorrectly indicate no backlight is present */
15344 static void quirk_backlight_present(struct drm_device
*dev
)
15346 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15347 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
15348 DRM_INFO("applying backlight present quirk\n");
15351 struct intel_quirk
{
15353 int subsystem_vendor
;
15354 int subsystem_device
;
15355 void (*hook
)(struct drm_device
*dev
);
15358 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15359 struct intel_dmi_quirk
{
15360 void (*hook
)(struct drm_device
*dev
);
15361 const struct dmi_system_id (*dmi_id_list
)[];
15364 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
15366 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
15370 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
15372 .dmi_id_list
= &(const struct dmi_system_id
[]) {
15374 .callback
= intel_dmi_reverse_brightness
,
15375 .ident
= "NCR Corporation",
15376 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
15377 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
15380 { } /* terminating entry */
15382 .hook
= quirk_invert_brightness
,
15386 static struct intel_quirk intel_quirks
[] = {
15387 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15388 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
15390 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15391 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
15393 /* 830 needs to leave pipe A & dpll A up */
15394 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
15396 /* 830 needs to leave pipe B & dpll B up */
15397 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
15399 /* Lenovo U160 cannot use SSC on LVDS */
15400 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
15402 /* Sony Vaio Y cannot use SSC on LVDS */
15403 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
15405 /* Acer Aspire 5734Z must invert backlight brightness */
15406 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
15408 /* Acer/eMachines G725 */
15409 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
15411 /* Acer/eMachines e725 */
15412 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
15414 /* Acer/Packard Bell NCL20 */
15415 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
15417 /* Acer Aspire 4736Z */
15418 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
15420 /* Acer Aspire 5336 */
15421 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
15423 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15424 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
15426 /* Acer C720 Chromebook (Core i3 4005U) */
15427 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
15429 /* Apple Macbook 2,1 (Core 2 T7400) */
15430 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
15432 /* Apple Macbook 4,1 */
15433 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present
},
15435 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15436 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
15438 /* HP Chromebook 14 (Celeron 2955U) */
15439 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
15441 /* Dell Chromebook 11 */
15442 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
15444 /* Dell Chromebook 11 (2015 version) */
15445 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present
},
15448 static void intel_init_quirks(struct drm_device
*dev
)
15450 struct pci_dev
*d
= dev
->pdev
;
15453 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
15454 struct intel_quirk
*q
= &intel_quirks
[i
];
15456 if (d
->device
== q
->device
&&
15457 (d
->subsystem_vendor
== q
->subsystem_vendor
||
15458 q
->subsystem_vendor
== PCI_ANY_ID
) &&
15459 (d
->subsystem_device
== q
->subsystem_device
||
15460 q
->subsystem_device
== PCI_ANY_ID
))
15463 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
15464 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
15465 intel_dmi_quirks
[i
].hook(dev
);
15469 /* Disable the VGA plane that we never use */
15470 static void i915_disable_vga(struct drm_device
*dev
)
15472 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15474 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev
);
15476 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15477 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15478 outb(SR01
, VGA_SR_INDEX
);
15479 sr1
= inb(VGA_SR_DATA
);
15480 outb(sr1
| 1<<5, VGA_SR_DATA
);
15481 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15484 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15485 POSTING_READ(vga_reg
);
15488 void intel_modeset_init_hw(struct drm_device
*dev
)
15490 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15492 intel_update_cdclk(dev
);
15494 dev_priv
->atomic_cdclk_freq
= dev_priv
->cdclk_freq
;
15496 intel_init_clock_gating(dev
);
15497 intel_enable_gt_powersave(dev_priv
);
15501 * Calculate what we think the watermarks should be for the state we've read
15502 * out of the hardware and then immediately program those watermarks so that
15503 * we ensure the hardware settings match our internal state.
15505 * We can calculate what we think WM's should be by creating a duplicate of the
15506 * current state (which was constructed during hardware readout) and running it
15507 * through the atomic check code to calculate new watermark values in the
15510 static void sanitize_watermarks(struct drm_device
*dev
)
15512 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15513 struct drm_atomic_state
*state
;
15514 struct drm_crtc
*crtc
;
15515 struct drm_crtc_state
*cstate
;
15516 struct drm_modeset_acquire_ctx ctx
;
15520 /* Only supported on platforms that use atomic watermark design */
15521 if (!dev_priv
->display
.optimize_watermarks
)
15525 * We need to hold connection_mutex before calling duplicate_state so
15526 * that the connector loop is protected.
15528 drm_modeset_acquire_init(&ctx
, 0);
15530 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
15531 if (ret
== -EDEADLK
) {
15532 drm_modeset_backoff(&ctx
);
15534 } else if (WARN_ON(ret
)) {
15538 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
15539 if (WARN_ON(IS_ERR(state
)))
15543 * Hardware readout is the only time we don't want to calculate
15544 * intermediate watermarks (since we don't trust the current
15547 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
15549 ret
= intel_atomic_check(dev
, state
);
15552 * If we fail here, it means that the hardware appears to be
15553 * programmed in a way that shouldn't be possible, given our
15554 * understanding of watermark requirements. This might mean a
15555 * mistake in the hardware readout code or a mistake in the
15556 * watermark calculations for a given platform. Raise a WARN
15557 * so that this is noticeable.
15559 * If this actually happens, we'll have to just leave the
15560 * BIOS-programmed watermarks untouched and hope for the best.
15562 WARN(true, "Could not determine valid watermarks for inherited state\n");
15566 /* Write calculated watermark values back */
15567 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
15568 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
15570 cs
->wm
.need_postvbl_update
= true;
15571 dev_priv
->display
.optimize_watermarks(cs
);
15574 drm_atomic_state_free(state
);
15576 drm_modeset_drop_locks(&ctx
);
15577 drm_modeset_acquire_fini(&ctx
);
15580 void intel_modeset_init(struct drm_device
*dev
)
15582 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15583 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
15586 struct intel_crtc
*crtc
;
15588 drm_mode_config_init(dev
);
15590 dev
->mode_config
.min_width
= 0;
15591 dev
->mode_config
.min_height
= 0;
15593 dev
->mode_config
.preferred_depth
= 24;
15594 dev
->mode_config
.prefer_shadow
= 1;
15596 dev
->mode_config
.allow_fb_modifiers
= true;
15598 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15600 intel_init_quirks(dev
);
15602 intel_init_pm(dev
);
15604 if (INTEL_INFO(dev
)->num_pipes
== 0)
15608 * There may be no VBT; and if the BIOS enabled SSC we can
15609 * just keep using it to avoid unnecessary flicker. Whereas if the
15610 * BIOS isn't using it, don't assume it will work even if the VBT
15611 * indicates as much.
15613 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
15614 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15617 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
15618 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15619 bios_lvds_use_ssc
? "en" : "dis",
15620 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
15621 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
15625 if (IS_GEN2(dev
)) {
15626 dev
->mode_config
.max_width
= 2048;
15627 dev
->mode_config
.max_height
= 2048;
15628 } else if (IS_GEN3(dev
)) {
15629 dev
->mode_config
.max_width
= 4096;
15630 dev
->mode_config
.max_height
= 4096;
15632 dev
->mode_config
.max_width
= 8192;
15633 dev
->mode_config
.max_height
= 8192;
15636 if (IS_845G(dev
) || IS_I865G(dev
)) {
15637 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
15638 dev
->mode_config
.cursor_height
= 1023;
15639 } else if (IS_GEN2(dev
)) {
15640 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
15641 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
15643 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
15644 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
15647 dev
->mode_config
.fb_base
= ggtt
->mappable_base
;
15649 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15650 INTEL_INFO(dev
)->num_pipes
,
15651 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
15653 for_each_pipe(dev_priv
, pipe
) {
15654 intel_crtc_init(dev
, pipe
);
15655 for_each_sprite(dev_priv
, pipe
, sprite
) {
15656 ret
= intel_plane_init(dev
, pipe
, sprite
);
15658 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15659 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
15663 intel_update_czclk(dev_priv
);
15664 intel_update_cdclk(dev
);
15666 intel_shared_dpll_init(dev
);
15668 if (dev_priv
->max_cdclk_freq
== 0)
15669 intel_update_max_cdclk(dev
);
15671 /* Just disable it once at startup */
15672 i915_disable_vga(dev
);
15673 intel_setup_outputs(dev
);
15675 drm_modeset_lock_all(dev
);
15676 intel_modeset_setup_hw_state(dev
);
15677 drm_modeset_unlock_all(dev
);
15679 for_each_intel_crtc(dev
, crtc
) {
15680 struct intel_initial_plane_config plane_config
= {};
15686 * Note that reserving the BIOS fb up front prevents us
15687 * from stuffing other stolen allocations like the ring
15688 * on top. This prevents some ugliness at boot time, and
15689 * can even allow for smooth boot transitions if the BIOS
15690 * fb is large enough for the active pipe configuration.
15692 dev_priv
->display
.get_initial_plane_config(crtc
,
15696 * If the fb is shared between multiple heads, we'll
15697 * just get the first one.
15699 intel_find_initial_plane_obj(crtc
, &plane_config
);
15703 * Make sure hardware watermarks really match the state we read out.
15704 * Note that we need to do this after reconstructing the BIOS fb's
15705 * since the watermark calculation done here will use pstate->fb.
15707 sanitize_watermarks(dev
);
15710 static void intel_enable_pipe_a(struct drm_device
*dev
)
15712 struct intel_connector
*connector
;
15713 struct drm_connector
*crt
= NULL
;
15714 struct intel_load_detect_pipe load_detect_temp
;
15715 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
15717 /* We can't just switch on the pipe A, we need to set things up with a
15718 * proper mode and output configuration. As a gross hack, enable pipe A
15719 * by enabling the load detect pipe once. */
15720 for_each_intel_connector(dev
, connector
) {
15721 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
15722 crt
= &connector
->base
;
15730 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
15731 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
15735 intel_check_plane_mapping(struct intel_crtc
*crtc
)
15737 struct drm_device
*dev
= crtc
->base
.dev
;
15738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15741 if (INTEL_INFO(dev
)->num_pipes
== 1)
15744 val
= I915_READ(DSPCNTR(!crtc
->plane
));
15746 if ((val
& DISPLAY_PLANE_ENABLE
) &&
15747 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
15753 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
15755 struct drm_device
*dev
= crtc
->base
.dev
;
15756 struct intel_encoder
*encoder
;
15758 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15764 static bool intel_encoder_has_connectors(struct intel_encoder
*encoder
)
15766 struct drm_device
*dev
= encoder
->base
.dev
;
15767 struct intel_connector
*connector
;
15769 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
15775 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
15777 struct drm_device
*dev
= crtc
->base
.dev
;
15778 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15779 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
15781 /* Clear any frame start delays used for debugging left by the BIOS */
15782 if (!transcoder_is_dsi(cpu_transcoder
)) {
15783 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
15786 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
15789 /* restore vblank interrupts to correct state */
15790 drm_crtc_vblank_reset(&crtc
->base
);
15791 if (crtc
->active
) {
15792 struct intel_plane
*plane
;
15794 drm_crtc_vblank_on(&crtc
->base
);
15796 /* Disable everything but the primary plane */
15797 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
15798 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
15801 plane
->disable_plane(&plane
->base
, &crtc
->base
);
15805 /* We need to sanitize the plane -> pipe mapping first because this will
15806 * disable the crtc (and hence change the state) if it is wrong. Note
15807 * that gen4+ has a fixed plane -> pipe mapping. */
15808 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
15811 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15812 crtc
->base
.base
.id
, crtc
->base
.name
);
15814 /* Pipe has the wrong plane attached and the plane is active.
15815 * Temporarily change the plane mapping and disable everything
15817 plane
= crtc
->plane
;
15818 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
15819 crtc
->plane
= !plane
;
15820 intel_crtc_disable_noatomic(&crtc
->base
);
15821 crtc
->plane
= plane
;
15824 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
15825 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
15826 /* BIOS forgot to enable pipe A, this mostly happens after
15827 * resume. Force-enable the pipe to fix this, the update_dpms
15828 * call below we restore the pipe to the right state, but leave
15829 * the required bits on. */
15830 intel_enable_pipe_a(dev
);
15833 /* Adjust the state of the output pipe according to whether we
15834 * have active connectors/encoders. */
15835 if (crtc
->active
&& !intel_crtc_has_encoders(crtc
))
15836 intel_crtc_disable_noatomic(&crtc
->base
);
15838 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
15840 * We start out with underrun reporting disabled to avoid races.
15841 * For correct bookkeeping mark this on active crtcs.
15843 * Also on gmch platforms we dont have any hardware bits to
15844 * disable the underrun reporting. Which means we need to start
15845 * out with underrun reporting disabled also on inactive pipes,
15846 * since otherwise we'll complain about the garbage we read when
15847 * e.g. coming up after runtime pm.
15849 * No protection against concurrent access is required - at
15850 * worst a fifo underrun happens which also sets this to false.
15852 crtc
->cpu_fifo_underrun_disabled
= true;
15853 crtc
->pch_fifo_underrun_disabled
= true;
15857 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
15859 struct intel_connector
*connector
;
15860 struct drm_device
*dev
= encoder
->base
.dev
;
15862 /* We need to check both for a crtc link (meaning that the
15863 * encoder is active and trying to read from a pipe) and the
15864 * pipe itself being active. */
15865 bool has_active_crtc
= encoder
->base
.crtc
&&
15866 to_intel_crtc(encoder
->base
.crtc
)->active
;
15868 if (intel_encoder_has_connectors(encoder
) && !has_active_crtc
) {
15869 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15870 encoder
->base
.base
.id
,
15871 encoder
->base
.name
);
15873 /* Connector is active, but has no active pipe. This is
15874 * fallout from our resume register restoring. Disable
15875 * the encoder manually again. */
15876 if (encoder
->base
.crtc
) {
15877 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15878 encoder
->base
.base
.id
,
15879 encoder
->base
.name
);
15880 encoder
->disable(encoder
);
15881 if (encoder
->post_disable
)
15882 encoder
->post_disable(encoder
);
15884 encoder
->base
.crtc
= NULL
;
15886 /* Inconsistent output/port/pipe state happens presumably due to
15887 * a bug in one of the get_hw_state functions. Or someplace else
15888 * in our code, like the register restore mess on resume. Clamp
15889 * things to off as a safer default. */
15890 for_each_intel_connector(dev
, connector
) {
15891 if (connector
->encoder
!= encoder
)
15893 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15894 connector
->base
.encoder
= NULL
;
15897 /* Enabled encoders without active connectors will be fixed in
15898 * the crtc fixup. */
15901 void i915_redisable_vga_power_on(struct drm_device
*dev
)
15903 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15904 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev
);
15906 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
15907 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15908 i915_disable_vga(dev
);
15912 void i915_redisable_vga(struct drm_device
*dev
)
15914 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15916 /* This function can be called both from intel_modeset_setup_hw_state or
15917 * at a very early point in our resume sequence, where the power well
15918 * structures are not yet restored. Since this function is at a very
15919 * paranoid "someone might have enabled VGA while we were not looking"
15920 * level, just check if the power well is enabled instead of trying to
15921 * follow the "don't touch the power well if we don't need it" policy
15922 * the rest of the driver uses. */
15923 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_VGA
))
15926 i915_redisable_vga_power_on(dev
);
15928 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
15931 static bool primary_get_hw_state(struct intel_plane
*plane
)
15933 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
15935 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
15938 /* FIXME read out full plane state for all planes */
15939 static void readout_plane_state(struct intel_crtc
*crtc
)
15941 struct drm_plane
*primary
= crtc
->base
.primary
;
15942 struct intel_plane_state
*plane_state
=
15943 to_intel_plane_state(primary
->state
);
15945 plane_state
->visible
= crtc
->active
&&
15946 primary_get_hw_state(to_intel_plane(primary
));
15948 if (plane_state
->visible
)
15949 crtc
->base
.state
->plane_mask
|= 1 << drm_plane_index(primary
);
15952 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15954 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15956 struct intel_crtc
*crtc
;
15957 struct intel_encoder
*encoder
;
15958 struct intel_connector
*connector
;
15961 dev_priv
->active_crtcs
= 0;
15963 for_each_intel_crtc(dev
, crtc
) {
15964 struct intel_crtc_state
*crtc_state
= crtc
->config
;
15967 __drm_atomic_helper_crtc_destroy_state(&crtc_state
->base
);
15968 memset(crtc_state
, 0, sizeof(*crtc_state
));
15969 crtc_state
->base
.crtc
= &crtc
->base
;
15971 crtc_state
->base
.active
= crtc_state
->base
.enable
=
15972 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
15974 crtc
->base
.enabled
= crtc_state
->base
.enable
;
15975 crtc
->active
= crtc_state
->base
.active
;
15977 if (crtc_state
->base
.active
) {
15978 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
15980 if (INTEL_GEN(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
15981 pixclk
= ilk_pipe_pixel_rate(crtc_state
);
15982 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15983 pixclk
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
15985 WARN_ON(dev_priv
->display
.modeset_calc_cdclk
);
15987 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15988 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
15989 pixclk
= DIV_ROUND_UP(pixclk
* 100, 95);
15992 dev_priv
->min_pixclk
[crtc
->pipe
] = pixclk
;
15994 readout_plane_state(crtc
);
15996 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15997 crtc
->base
.base
.id
, crtc
->base
.name
,
15998 crtc
->active
? "enabled" : "disabled");
16001 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16002 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16004 pll
->on
= pll
->funcs
.get_hw_state(dev_priv
, pll
,
16005 &pll
->config
.hw_state
);
16006 pll
->config
.crtc_mask
= 0;
16007 for_each_intel_crtc(dev
, crtc
) {
16008 if (crtc
->active
&& crtc
->config
->shared_dpll
== pll
)
16009 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
16011 pll
->active_mask
= pll
->config
.crtc_mask
;
16013 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16014 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
16017 for_each_intel_encoder(dev
, encoder
) {
16020 if (encoder
->get_hw_state(encoder
, &pipe
)) {
16021 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
16022 encoder
->base
.crtc
= &crtc
->base
;
16023 crtc
->config
->output_types
|= 1 << encoder
->type
;
16024 encoder
->get_config(encoder
, crtc
->config
);
16026 encoder
->base
.crtc
= NULL
;
16029 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16030 encoder
->base
.base
.id
,
16031 encoder
->base
.name
,
16032 encoder
->base
.crtc
? "enabled" : "disabled",
16036 for_each_intel_connector(dev
, connector
) {
16037 if (connector
->get_hw_state(connector
)) {
16038 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
16040 encoder
= connector
->encoder
;
16041 connector
->base
.encoder
= &encoder
->base
;
16043 if (encoder
->base
.crtc
&&
16044 encoder
->base
.crtc
->state
->active
) {
16046 * This has to be done during hardware readout
16047 * because anything calling .crtc_disable may
16048 * rely on the connector_mask being accurate.
16050 encoder
->base
.crtc
->state
->connector_mask
|=
16051 1 << drm_connector_index(&connector
->base
);
16052 encoder
->base
.crtc
->state
->encoder_mask
|=
16053 1 << drm_encoder_index(&encoder
->base
);
16057 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16058 connector
->base
.encoder
= NULL
;
16060 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16061 connector
->base
.base
.id
,
16062 connector
->base
.name
,
16063 connector
->base
.encoder
? "enabled" : "disabled");
16066 for_each_intel_crtc(dev
, crtc
) {
16067 crtc
->base
.hwmode
= crtc
->config
->base
.adjusted_mode
;
16069 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
16070 if (crtc
->base
.state
->active
) {
16071 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc
->config
);
16072 intel_mode_from_pipe_config(&crtc
->base
.state
->adjusted_mode
, crtc
->config
);
16073 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
16076 * The initial mode needs to be set in order to keep
16077 * the atomic core happy. It wants a valid mode if the
16078 * crtc's enabled, so we do the above call.
16080 * At this point some state updated by the connectors
16081 * in their ->detect() callback has not run yet, so
16082 * no recalculation can be done yet.
16084 * Even if we could do a recalculation and modeset
16085 * right now it would cause a double modeset if
16086 * fbdev or userspace chooses a different initial mode.
16088 * If that happens, someone indicated they wanted a
16089 * mode change, which means it's safe to do a full
16092 crtc
->base
.state
->mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
16094 drm_calc_timestamping_constants(&crtc
->base
, &crtc
->base
.hwmode
);
16095 update_scanline_offset(crtc
);
16098 intel_pipe_config_sanity_check(dev_priv
, crtc
->config
);
16102 /* Scan out the current hw modeset state,
16103 * and sanitizes it to the current state
16106 intel_modeset_setup_hw_state(struct drm_device
*dev
)
16108 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16110 struct intel_crtc
*crtc
;
16111 struct intel_encoder
*encoder
;
16114 intel_modeset_readout_hw_state(dev
);
16116 /* HW state is read out, now we need to sanitize this mess. */
16117 for_each_intel_encoder(dev
, encoder
) {
16118 intel_sanitize_encoder(encoder
);
16121 for_each_pipe(dev_priv
, pipe
) {
16122 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
16123 intel_sanitize_crtc(crtc
);
16124 intel_dump_pipe_config(crtc
, crtc
->config
,
16125 "[setup_hw_state]");
16128 intel_modeset_update_connector_atomic_state(dev
);
16130 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16131 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16133 if (!pll
->on
|| pll
->active_mask
)
16136 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
16138 pll
->funcs
.disable(dev_priv
, pll
);
16142 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
16143 vlv_wm_get_hw_state(dev
);
16144 else if (IS_GEN9(dev
))
16145 skl_wm_get_hw_state(dev
);
16146 else if (HAS_PCH_SPLIT(dev
))
16147 ilk_wm_get_hw_state(dev
);
16149 for_each_intel_crtc(dev
, crtc
) {
16150 unsigned long put_domains
;
16152 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc
->config
);
16153 if (WARN_ON(put_domains
))
16154 modeset_put_power_domains(dev_priv
, put_domains
);
16156 intel_display_set_init_power(dev_priv
, false);
16158 intel_fbc_init_pipe_state(dev_priv
);
16161 void intel_display_resume(struct drm_device
*dev
)
16163 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16164 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
16165 struct drm_modeset_acquire_ctx ctx
;
16167 bool setup
= false;
16169 dev_priv
->modeset_restore_state
= NULL
;
16172 * This is a cludge because with real atomic modeset mode_config.mutex
16173 * won't be taken. Unfortunately some probed state like
16174 * audio_codec_enable is still protected by mode_config.mutex, so lock
16177 mutex_lock(&dev
->mode_config
.mutex
);
16178 drm_modeset_acquire_init(&ctx
, 0);
16181 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
16183 if (ret
== 0 && !setup
) {
16186 intel_modeset_setup_hw_state(dev
);
16187 i915_redisable_vga(dev
);
16190 if (ret
== 0 && state
) {
16191 struct drm_crtc_state
*crtc_state
;
16192 struct drm_crtc
*crtc
;
16195 state
->acquire_ctx
= &ctx
;
16197 /* ignore any reset values/BIOS leftovers in the WM registers */
16198 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
16200 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
16202 * Force recalculation even if we restore
16203 * current state. With fast modeset this may not result
16204 * in a modeset when the state is compatible.
16206 crtc_state
->mode_changed
= true;
16209 ret
= drm_atomic_commit(state
);
16212 if (ret
== -EDEADLK
) {
16213 drm_modeset_backoff(&ctx
);
16217 drm_modeset_drop_locks(&ctx
);
16218 drm_modeset_acquire_fini(&ctx
);
16219 mutex_unlock(&dev
->mode_config
.mutex
);
16222 DRM_ERROR("Restoring old state failed with %i\n", ret
);
16223 drm_atomic_state_free(state
);
16227 void intel_modeset_gem_init(struct drm_device
*dev
)
16229 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16230 struct drm_crtc
*c
;
16231 struct drm_i915_gem_object
*obj
;
16234 intel_init_gt_powersave(dev_priv
);
16236 intel_modeset_init_hw(dev
);
16238 intel_setup_overlay(dev_priv
);
16241 * Make sure any fbs we allocated at startup are properly
16242 * pinned & fenced. When we do the allocation it's too early
16245 for_each_crtc(dev
, c
) {
16246 obj
= intel_fb_obj(c
->primary
->fb
);
16250 mutex_lock(&dev
->struct_mutex
);
16251 ret
= intel_pin_and_fence_fb_obj(c
->primary
->fb
,
16252 c
->primary
->state
->rotation
);
16253 mutex_unlock(&dev
->struct_mutex
);
16255 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16256 to_intel_crtc(c
)->pipe
);
16257 drm_framebuffer_unreference(c
->primary
->fb
);
16258 c
->primary
->fb
= NULL
;
16259 c
->primary
->crtc
= c
->primary
->state
->crtc
= NULL
;
16260 update_state_fb(c
->primary
);
16261 c
->state
->plane_mask
&= ~(1 << drm_plane_index(c
->primary
));
16266 int intel_connector_register(struct drm_connector
*connector
)
16268 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
16271 ret
= intel_backlight_device_register(intel_connector
);
16281 void intel_connector_unregister(struct drm_connector
*connector
)
16283 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
16285 intel_backlight_device_unregister(intel_connector
);
16286 intel_panel_destroy_backlight(connector
);
16289 void intel_modeset_cleanup(struct drm_device
*dev
)
16291 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16293 intel_disable_gt_powersave(dev_priv
);
16296 * Interrupts and polling as the first thing to avoid creating havoc.
16297 * Too much stuff here (turning of connectors, ...) would
16298 * experience fancy races otherwise.
16300 intel_irq_uninstall(dev_priv
);
16303 * Due to the hpd irq storm handling the hotplug work can re-arm the
16304 * poll handlers. Hence disable polling after hpd handling is shut down.
16306 drm_kms_helper_poll_fini(dev
);
16308 intel_unregister_dsm_handler();
16310 intel_fbc_global_disable(dev_priv
);
16312 /* flush any delayed tasks or pending work */
16313 flush_scheduled_work();
16315 drm_mode_config_cleanup(dev
);
16317 intel_cleanup_overlay(dev_priv
);
16319 intel_cleanup_gt_powersave(dev_priv
);
16321 intel_teardown_gmbus(dev
);
16324 void intel_connector_attach_encoder(struct intel_connector
*connector
,
16325 struct intel_encoder
*encoder
)
16327 connector
->encoder
= encoder
;
16328 drm_mode_connector_attach_encoder(&connector
->base
,
16333 * set vga decode state - true == enable VGA decode
16335 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
16337 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16338 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
16341 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
16342 DRM_ERROR("failed to read control word\n");
16346 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
16350 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
16352 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
16354 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
16355 DRM_ERROR("failed to write control word\n");
16362 struct intel_display_error_state
{
16364 u32 power_well_driver
;
16366 int num_transcoders
;
16368 struct intel_cursor_error_state
{
16373 } cursor
[I915_MAX_PIPES
];
16375 struct intel_pipe_error_state
{
16376 bool power_domain_on
;
16379 } pipe
[I915_MAX_PIPES
];
16381 struct intel_plane_error_state
{
16389 } plane
[I915_MAX_PIPES
];
16391 struct intel_transcoder_error_state
{
16392 bool power_domain_on
;
16393 enum transcoder cpu_transcoder
;
16406 struct intel_display_error_state
*
16407 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
16409 struct intel_display_error_state
*error
;
16410 int transcoders
[] = {
16418 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
16421 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
16425 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
16426 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
16428 for_each_pipe(dev_priv
, i
) {
16429 error
->pipe
[i
].power_domain_on
=
16430 __intel_display_power_is_enabled(dev_priv
,
16431 POWER_DOMAIN_PIPE(i
));
16432 if (!error
->pipe
[i
].power_domain_on
)
16435 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
16436 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
16437 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
16439 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
16440 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
16441 if (INTEL_GEN(dev_priv
) <= 3) {
16442 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
16443 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
16445 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
16446 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
16447 if (INTEL_GEN(dev_priv
) >= 4) {
16448 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
16449 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
16452 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
16454 if (HAS_GMCH_DISPLAY(dev_priv
))
16455 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
16458 /* Note: this does not include DSI transcoders. */
16459 error
->num_transcoders
= INTEL_INFO(dev_priv
)->num_pipes
;
16460 if (HAS_DDI(dev_priv
))
16461 error
->num_transcoders
++; /* Account for eDP. */
16463 for (i
= 0; i
< error
->num_transcoders
; i
++) {
16464 enum transcoder cpu_transcoder
= transcoders
[i
];
16466 error
->transcoder
[i
].power_domain_on
=
16467 __intel_display_power_is_enabled(dev_priv
,
16468 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
16469 if (!error
->transcoder
[i
].power_domain_on
)
16472 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
16474 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
16475 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
16476 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
16477 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
16478 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
16479 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
16480 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
16486 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16489 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
16490 struct drm_device
*dev
,
16491 struct intel_display_error_state
*error
)
16493 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16499 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
16500 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
16501 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
16502 error
->power_well_driver
);
16503 for_each_pipe(dev_priv
, i
) {
16504 err_printf(m
, "Pipe [%d]:\n", i
);
16505 err_printf(m
, " Power: %s\n",
16506 onoff(error
->pipe
[i
].power_domain_on
));
16507 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
16508 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
16510 err_printf(m
, "Plane [%d]:\n", i
);
16511 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
16512 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
16513 if (INTEL_INFO(dev
)->gen
<= 3) {
16514 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
16515 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
16517 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
16518 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
16519 if (INTEL_INFO(dev
)->gen
>= 4) {
16520 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
16521 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
16524 err_printf(m
, "Cursor [%d]:\n", i
);
16525 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
16526 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
16527 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
16530 for (i
= 0; i
< error
->num_transcoders
; i
++) {
16531 err_printf(m
, "CPU transcoder: %s\n",
16532 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
16533 err_printf(m
, " Power: %s\n",
16534 onoff(error
->transcoder
[i
].power_domain_on
));
16535 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
16536 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
16537 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
16538 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
16539 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
16540 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
16541 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);