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Merge tag 'drm-intel-next-2014-06-20' of git://anongit.freedesktop.org/drm-intel...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103
104 typedef struct {
105 int min, max;
106 } intel_range_t;
107
108 typedef struct {
109 int dot_limit;
110 int p2_slow, p2_fast;
111 } intel_p2_t;
112
113 typedef struct intel_limit intel_limit_t;
114 struct intel_limit {
115 intel_range_t dot, vco, n, m, m1, m2, p, p1;
116 intel_p2_t p2;
117 };
118
119 int
120 intel_pch_rawclk(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 WARN_ON(!HAS_PCH_SPLIT(dev));
125
126 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
127 }
128
129 static inline u32 /* units of 100MHz */
130 intel_fdi_link_freq(struct drm_device *dev)
131 {
132 if (IS_GEN5(dev)) {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
135 } else
136 return 27;
137 }
138
139 static const intel_limit_t intel_limits_i8xx_dac = {
140 .dot = { .min = 25000, .max = 350000 },
141 .vco = { .min = 908000, .max = 1512000 },
142 .n = { .min = 2, .max = 16 },
143 .m = { .min = 96, .max = 140 },
144 .m1 = { .min = 18, .max = 26 },
145 .m2 = { .min = 6, .max = 16 },
146 .p = { .min = 4, .max = 128 },
147 .p1 = { .min = 2, .max = 33 },
148 .p2 = { .dot_limit = 165000,
149 .p2_slow = 4, .p2_fast = 2 },
150 };
151
152 static const intel_limit_t intel_limits_i8xx_dvo = {
153 .dot = { .min = 25000, .max = 350000 },
154 .vco = { .min = 908000, .max = 1512000 },
155 .n = { .min = 2, .max = 16 },
156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 4 },
163 };
164
165 static const intel_limit_t intel_limits_i8xx_lvds = {
166 .dot = { .min = 25000, .max = 350000 },
167 .vco = { .min = 908000, .max = 1512000 },
168 .n = { .min = 2, .max = 16 },
169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 1, .max = 6 },
174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 14, .p2_fast = 7 },
176 };
177
178 static const intel_limit_t intel_limits_i9xx_sdvo = {
179 .dot = { .min = 20000, .max = 400000 },
180 .vco = { .min = 1400000, .max = 2800000 },
181 .n = { .min = 1, .max = 6 },
182 .m = { .min = 70, .max = 120 },
183 .m1 = { .min = 8, .max = 18 },
184 .m2 = { .min = 3, .max = 7 },
185 .p = { .min = 5, .max = 80 },
186 .p1 = { .min = 1, .max = 8 },
187 .p2 = { .dot_limit = 200000,
188 .p2_slow = 10, .p2_fast = 5 },
189 };
190
191 static const intel_limit_t intel_limits_i9xx_lvds = {
192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
198 .p = { .min = 7, .max = 98 },
199 .p1 = { .min = 1, .max = 8 },
200 .p2 = { .dot_limit = 112000,
201 .p2_slow = 14, .p2_fast = 7 },
202 };
203
204
205 static const intel_limit_t intel_limits_g4x_sdvo = {
206 .dot = { .min = 25000, .max = 270000 },
207 .vco = { .min = 1750000, .max = 3500000},
208 .n = { .min = 1, .max = 4 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 10, .max = 30 },
213 .p1 = { .min = 1, .max = 3},
214 .p2 = { .dot_limit = 270000,
215 .p2_slow = 10,
216 .p2_fast = 10
217 },
218 };
219
220 static const intel_limit_t intel_limits_g4x_hdmi = {
221 .dot = { .min = 22000, .max = 400000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 16, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 5, .max = 80 },
228 .p1 = { .min = 1, .max = 8},
229 .p2 = { .dot_limit = 165000,
230 .p2_slow = 10, .p2_fast = 5 },
231 };
232
233 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
234 .dot = { .min = 20000, .max = 115000 },
235 .vco = { .min = 1750000, .max = 3500000 },
236 .n = { .min = 1, .max = 3 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 17, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 28, .max = 112 },
241 .p1 = { .min = 2, .max = 8 },
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 14, .p2_fast = 14
244 },
245 };
246
247 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
248 .dot = { .min = 80000, .max = 224000 },
249 .vco = { .min = 1750000, .max = 3500000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 104, .max = 138 },
252 .m1 = { .min = 17, .max = 23 },
253 .m2 = { .min = 5, .max = 11 },
254 .p = { .min = 14, .max = 42 },
255 .p1 = { .min = 2, .max = 6 },
256 .p2 = { .dot_limit = 0,
257 .p2_slow = 7, .p2_fast = 7
258 },
259 };
260
261 static const intel_limit_t intel_limits_pineview_sdvo = {
262 .dot = { .min = 20000, .max = 400000},
263 .vco = { .min = 1700000, .max = 3500000 },
264 /* Pineview's Ncounter is a ring counter */
265 .n = { .min = 3, .max = 6 },
266 .m = { .min = 2, .max = 256 },
267 /* Pineview only has one combined m divider, which we treat as m2. */
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 5, .max = 80 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 200000,
273 .p2_slow = 10, .p2_fast = 5 },
274 };
275
276 static const intel_limit_t intel_limits_pineview_lvds = {
277 .dot = { .min = 20000, .max = 400000 },
278 .vco = { .min = 1700000, .max = 3500000 },
279 .n = { .min = 3, .max = 6 },
280 .m = { .min = 2, .max = 256 },
281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 7, .max = 112 },
284 .p1 = { .min = 1, .max = 8 },
285 .p2 = { .dot_limit = 112000,
286 .p2_slow = 14, .p2_fast = 14 },
287 };
288
289 /* Ironlake / Sandybridge
290 *
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
293 */
294 static const intel_limit_t intel_limits_ironlake_dac = {
295 .dot = { .min = 25000, .max = 350000 },
296 .vco = { .min = 1760000, .max = 3510000 },
297 .n = { .min = 1, .max = 5 },
298 .m = { .min = 79, .max = 127 },
299 .m1 = { .min = 12, .max = 22 },
300 .m2 = { .min = 5, .max = 9 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 225000,
304 .p2_slow = 10, .p2_fast = 5 },
305 };
306
307 static const intel_limit_t intel_limits_ironlake_single_lvds = {
308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 3 },
311 .m = { .min = 79, .max = 118 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 28, .max = 112 },
315 .p1 = { .min = 2, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 14, .p2_fast = 14 },
318 };
319
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 };
332
333 /* LVDS 100mhz refclk limits. */
334 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 2 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 28, .max = 112 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 14, .p2_fast = 14 },
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 };
359
360 static const intel_limit_t intel_limits_vlv = {
361 /*
362 * These are the data rate limits (measured in fast clocks)
363 * since those are the strictest limits we have. The fast
364 * clock and actual rate limits are more relaxed, so checking
365 * them would make no difference.
366 */
367 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
368 .vco = { .min = 4000000, .max = 6000000 },
369 .n = { .min = 1, .max = 7 },
370 .m1 = { .min = 2, .max = 3 },
371 .m2 = { .min = 11, .max = 156 },
372 .p1 = { .min = 2, .max = 3 },
373 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
374 };
375
376 static const intel_limit_t intel_limits_chv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 540000 * 5},
384 .vco = { .min = 4860000, .max = 6700000 },
385 .n = { .min = 1, .max = 1 },
386 .m1 = { .min = 2, .max = 2 },
387 .m2 = { .min = 24 << 22, .max = 175 << 22 },
388 .p1 = { .min = 2, .max = 4 },
389 .p2 = { .p2_slow = 1, .p2_fast = 14 },
390 };
391
392 static void vlv_clock(int refclk, intel_clock_t *clock)
393 {
394 clock->m = clock->m1 * clock->m2;
395 clock->p = clock->p1 * clock->p2;
396 if (WARN_ON(clock->n == 0 || clock->p == 0))
397 return;
398 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
399 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
400 }
401
402 /**
403 * Returns whether any output on the specified pipe is of the specified type
404 */
405 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
406 {
407 struct drm_device *dev = crtc->dev;
408 struct intel_encoder *encoder;
409
410 for_each_encoder_on_crtc(dev, crtc, encoder)
411 if (encoder->type == type)
412 return true;
413
414 return false;
415 }
416
417 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
418 int refclk)
419 {
420 struct drm_device *dev = crtc->dev;
421 const intel_limit_t *limit;
422
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
424 if (intel_is_dual_link_lvds(dev)) {
425 if (refclk == 100000)
426 limit = &intel_limits_ironlake_dual_lvds_100m;
427 else
428 limit = &intel_limits_ironlake_dual_lvds;
429 } else {
430 if (refclk == 100000)
431 limit = &intel_limits_ironlake_single_lvds_100m;
432 else
433 limit = &intel_limits_ironlake_single_lvds;
434 }
435 } else
436 limit = &intel_limits_ironlake_dac;
437
438 return limit;
439 }
440
441 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
442 {
443 struct drm_device *dev = crtc->dev;
444 const intel_limit_t *limit;
445
446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
447 if (intel_is_dual_link_lvds(dev))
448 limit = &intel_limits_g4x_dual_channel_lvds;
449 else
450 limit = &intel_limits_g4x_single_channel_lvds;
451 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
452 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
453 limit = &intel_limits_g4x_hdmi;
454 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
455 limit = &intel_limits_g4x_sdvo;
456 } else /* The option is for other outputs */
457 limit = &intel_limits_i9xx_sdvo;
458
459 return limit;
460 }
461
462 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
463 {
464 struct drm_device *dev = crtc->dev;
465 const intel_limit_t *limit;
466
467 if (HAS_PCH_SPLIT(dev))
468 limit = intel_ironlake_limit(crtc, refclk);
469 else if (IS_G4X(dev)) {
470 limit = intel_g4x_limit(crtc);
471 } else if (IS_PINEVIEW(dev)) {
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
473 limit = &intel_limits_pineview_lvds;
474 else
475 limit = &intel_limits_pineview_sdvo;
476 } else if (IS_CHERRYVIEW(dev)) {
477 limit = &intel_limits_chv;
478 } else if (IS_VALLEYVIEW(dev)) {
479 limit = &intel_limits_vlv;
480 } else if (!IS_GEN2(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_i9xx_lvds;
483 else
484 limit = &intel_limits_i9xx_sdvo;
485 } else {
486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
487 limit = &intel_limits_i8xx_lvds;
488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
489 limit = &intel_limits_i8xx_dvo;
490 else
491 limit = &intel_limits_i8xx_dac;
492 }
493 return limit;
494 }
495
496 /* m1 is reserved as 0 in Pineview, n is a ring counter */
497 static void pineview_clock(int refclk, intel_clock_t *clock)
498 {
499 clock->m = clock->m2 + 2;
500 clock->p = clock->p1 * clock->p2;
501 if (WARN_ON(clock->n == 0 || clock->p == 0))
502 return;
503 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
504 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
505 }
506
507 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
508 {
509 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
510 }
511
512 static void i9xx_clock(int refclk, intel_clock_t *clock)
513 {
514 clock->m = i9xx_dpll_compute_m(clock);
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
517 return;
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520 }
521
522 static void chv_clock(int refclk, intel_clock_t *clock)
523 {
524 clock->m = clock->m1 * clock->m2;
525 clock->p = clock->p1 * clock->p2;
526 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 return;
528 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
529 clock->n << 22);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 }
532
533 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
534 /**
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
537 */
538
539 static bool intel_PLL_is_valid(struct drm_device *dev,
540 const intel_limit_t *limit,
541 const intel_clock_t *clock)
542 {
543 if (clock->n < limit->n.min || limit->n.max < clock->n)
544 INTELPllInvalid("n out of range\n");
545 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
546 INTELPllInvalid("p1 out of range\n");
547 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
548 INTELPllInvalid("m2 out of range\n");
549 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
550 INTELPllInvalid("m1 out of range\n");
551
552 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
553 if (clock->m1 <= clock->m2)
554 INTELPllInvalid("m1 <= m2\n");
555
556 if (!IS_VALLEYVIEW(dev)) {
557 if (clock->p < limit->p.min || limit->p.max < clock->p)
558 INTELPllInvalid("p out of range\n");
559 if (clock->m < limit->m.min || limit->m.max < clock->m)
560 INTELPllInvalid("m out of range\n");
561 }
562
563 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
564 INTELPllInvalid("vco out of range\n");
565 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
566 * connector, etc., rather than just a single range.
567 */
568 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
569 INTELPllInvalid("dot out of range\n");
570
571 return true;
572 }
573
574 static bool
575 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
576 int target, int refclk, intel_clock_t *match_clock,
577 intel_clock_t *best_clock)
578 {
579 struct drm_device *dev = crtc->dev;
580 intel_clock_t clock;
581 int err = target;
582
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
584 /*
585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
588 */
589 if (intel_is_dual_link_lvds(dev))
590 clock.p2 = limit->p2.p2_fast;
591 else
592 clock.p2 = limit->p2.p2_slow;
593 } else {
594 if (target < limit->p2.dot_limit)
595 clock.p2 = limit->p2.p2_slow;
596 else
597 clock.p2 = limit->p2.p2_fast;
598 }
599
600 memset(best_clock, 0, sizeof(*best_clock));
601
602 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
603 clock.m1++) {
604 for (clock.m2 = limit->m2.min;
605 clock.m2 <= limit->m2.max; clock.m2++) {
606 if (clock.m2 >= clock.m1)
607 break;
608 for (clock.n = limit->n.min;
609 clock.n <= limit->n.max; clock.n++) {
610 for (clock.p1 = limit->p1.min;
611 clock.p1 <= limit->p1.max; clock.p1++) {
612 int this_err;
613
614 i9xx_clock(refclk, &clock);
615 if (!intel_PLL_is_valid(dev, limit,
616 &clock))
617 continue;
618 if (match_clock &&
619 clock.p != match_clock->p)
620 continue;
621
622 this_err = abs(clock.dot - target);
623 if (this_err < err) {
624 *best_clock = clock;
625 err = this_err;
626 }
627 }
628 }
629 }
630 }
631
632 return (err != target);
633 }
634
635 static bool
636 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
637 int target, int refclk, intel_clock_t *match_clock,
638 intel_clock_t *best_clock)
639 {
640 struct drm_device *dev = crtc->dev;
641 intel_clock_t clock;
642 int err = target;
643
644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
645 /*
646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
649 */
650 if (intel_is_dual_link_lvds(dev))
651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
661 memset(best_clock, 0, sizeof(*best_clock));
662
663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
667 for (clock.n = limit->n.min;
668 clock.n <= limit->n.max; clock.n++) {
669 for (clock.p1 = limit->p1.min;
670 clock.p1 <= limit->p1.max; clock.p1++) {
671 int this_err;
672
673 pineview_clock(refclk, &clock);
674 if (!intel_PLL_is_valid(dev, limit,
675 &clock))
676 continue;
677 if (match_clock &&
678 clock.p != match_clock->p)
679 continue;
680
681 this_err = abs(clock.dot - target);
682 if (this_err < err) {
683 *best_clock = clock;
684 err = this_err;
685 }
686 }
687 }
688 }
689 }
690
691 return (err != target);
692 }
693
694 static bool
695 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
696 int target, int refclk, intel_clock_t *match_clock,
697 intel_clock_t *best_clock)
698 {
699 struct drm_device *dev = crtc->dev;
700 intel_clock_t clock;
701 int max_n;
702 bool found;
703 /* approximately equals target * 0.00585 */
704 int err_most = (target >> 8) + (target >> 9);
705 found = false;
706
707 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
708 if (intel_is_dual_link_lvds(dev))
709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
732 i9xx_clock(refclk, &clock);
733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
735 continue;
736
737 this_err = abs(clock.dot - target);
738 if (this_err < err_most) {
739 *best_clock = clock;
740 err_most = this_err;
741 max_n = clock.n;
742 found = true;
743 }
744 }
745 }
746 }
747 }
748 return found;
749 }
750
751 static bool
752 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
753 int target, int refclk, intel_clock_t *match_clock,
754 intel_clock_t *best_clock)
755 {
756 struct drm_device *dev = crtc->dev;
757 intel_clock_t clock;
758 unsigned int bestppm = 1000000;
759 /* min update 19.2 MHz */
760 int max_n = min(limit->n.max, refclk / 19200);
761 bool found = false;
762
763 target *= 5; /* fast clock */
764
765 memset(best_clock, 0, sizeof(*best_clock));
766
767 /* based on hardware requirement, prefer smaller n to precision */
768 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
769 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
770 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
771 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
772 clock.p = clock.p1 * clock.p2;
773 /* based on hardware requirement, prefer bigger m1,m2 values */
774 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
775 unsigned int ppm, diff;
776
777 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
778 refclk * clock.m1);
779
780 vlv_clock(refclk, &clock);
781
782 if (!intel_PLL_is_valid(dev, limit,
783 &clock))
784 continue;
785
786 diff = abs(clock.dot - target);
787 ppm = div_u64(1000000ULL * diff, target);
788
789 if (ppm < 100 && clock.p > best_clock->p) {
790 bestppm = 0;
791 *best_clock = clock;
792 found = true;
793 }
794
795 if (bestppm >= 10 && ppm < bestppm - 10) {
796 bestppm = ppm;
797 *best_clock = clock;
798 found = true;
799 }
800 }
801 }
802 }
803 }
804
805 return found;
806 }
807
808 static bool
809 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815 uint64_t m2;
816 int found = false;
817
818 memset(best_clock, 0, sizeof(*best_clock));
819
820 /*
821 * Based on hardware doc, the n always set to 1, and m1 always
822 * set to 2. If requires to support 200Mhz refclk, we need to
823 * revisit this because n may not 1 anymore.
824 */
825 clock.n = 1, clock.m1 = 2;
826 target *= 5; /* fast clock */
827
828 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
829 for (clock.p2 = limit->p2.p2_fast;
830 clock.p2 >= limit->p2.p2_slow;
831 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
832
833 clock.p = clock.p1 * clock.p2;
834
835 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
836 clock.n) << 22, refclk * clock.m1);
837
838 if (m2 > INT_MAX/clock.m1)
839 continue;
840
841 clock.m2 = m2;
842
843 chv_clock(refclk, &clock);
844
845 if (!intel_PLL_is_valid(dev, limit, &clock))
846 continue;
847
848 /* based on hardware requirement, prefer bigger p
849 */
850 if (clock.p > best_clock->p) {
851 *best_clock = clock;
852 found = true;
853 }
854 }
855 }
856
857 return found;
858 }
859
860 bool intel_crtc_active(struct drm_crtc *crtc)
861 {
862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
863
864 /* Be paranoid as we can arrive here with only partial
865 * state retrieved from the hardware during setup.
866 *
867 * We can ditch the adjusted_mode.crtc_clock check as soon
868 * as Haswell has gained clock readout/fastboot support.
869 *
870 * We can ditch the crtc->primary->fb check as soon as we can
871 * properly reconstruct framebuffers.
872 */
873 return intel_crtc->active && crtc->primary->fb &&
874 intel_crtc->config.adjusted_mode.crtc_clock;
875 }
876
877 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882
883 return intel_crtc->config.cpu_transcoder;
884 }
885
886 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
887 {
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
890
891 frame = I915_READ(frame_reg);
892
893 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
894 WARN(1, "vblank wait timed out\n");
895 }
896
897 /**
898 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @dev: drm device
900 * @pipe: pipe to wait for
901 *
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
903 * mode setting code.
904 */
905 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
906 {
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 int pipestat_reg = PIPESTAT(pipe);
909
910 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
911 g4x_wait_for_vblank(dev, pipe);
912 return;
913 }
914
915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
917 *
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
924 * vblanks...
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
927 */
928 I915_WRITE(pipestat_reg,
929 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
930
931 /* Wait for vblank interrupt bit to set */
932 if (wait_for(I915_READ(pipestat_reg) &
933 PIPE_VBLANK_INTERRUPT_STATUS,
934 50))
935 DRM_DEBUG_KMS("vblank wait timed out\n");
936 }
937
938 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
939 {
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 reg = PIPEDSL(pipe);
942 u32 line1, line2;
943 u32 line_mask;
944
945 if (IS_GEN2(dev))
946 line_mask = DSL_LINEMASK_GEN2;
947 else
948 line_mask = DSL_LINEMASK_GEN3;
949
950 line1 = I915_READ(reg) & line_mask;
951 mdelay(5);
952 line2 = I915_READ(reg) & line_mask;
953
954 return line1 == line2;
955 }
956
957 /*
958 * intel_wait_for_pipe_off - wait for pipe to turn off
959 * @dev: drm device
960 * @pipe: pipe to wait for
961 *
962 * After disabling a pipe, we can't wait for vblank in the usual way,
963 * spinning on the vblank interrupt status bit, since we won't actually
964 * see an interrupt when the pipe is disabled.
965 *
966 * On Gen4 and above:
967 * wait for the pipe register state bit to turn off
968 *
969 * Otherwise:
970 * wait for the display line value to settle (it usually
971 * ends up stopping at the start of the next frame).
972 *
973 */
974 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
975 {
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
978 pipe);
979
980 if (INTEL_INFO(dev)->gen >= 4) {
981 int reg = PIPECONF(cpu_transcoder);
982
983 /* Wait for the Pipe State to go off */
984 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
985 100))
986 WARN(1, "pipe_off wait timed out\n");
987 } else {
988 /* Wait for the display line to settle */
989 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
990 WARN(1, "pipe_off wait timed out\n");
991 }
992 }
993
994 /*
995 * ibx_digital_port_connected - is the specified port connected?
996 * @dev_priv: i915 private structure
997 * @port: the port to test
998 *
999 * Returns true if @port is connected, false otherwise.
1000 */
1001 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1002 struct intel_digital_port *port)
1003 {
1004 u32 bit;
1005
1006 if (HAS_PCH_IBX(dev_priv->dev)) {
1007 switch (port->port) {
1008 case PORT_B:
1009 bit = SDE_PORTB_HOTPLUG;
1010 break;
1011 case PORT_C:
1012 bit = SDE_PORTC_HOTPLUG;
1013 break;
1014 case PORT_D:
1015 bit = SDE_PORTD_HOTPLUG;
1016 break;
1017 default:
1018 return true;
1019 }
1020 } else {
1021 switch (port->port) {
1022 case PORT_B:
1023 bit = SDE_PORTB_HOTPLUG_CPT;
1024 break;
1025 case PORT_C:
1026 bit = SDE_PORTC_HOTPLUG_CPT;
1027 break;
1028 case PORT_D:
1029 bit = SDE_PORTD_HOTPLUG_CPT;
1030 break;
1031 default:
1032 return true;
1033 }
1034 }
1035
1036 return I915_READ(SDEISR) & bit;
1037 }
1038
1039 static const char *state_string(bool enabled)
1040 {
1041 return enabled ? "on" : "off";
1042 }
1043
1044 /* Only for pre-ILK configs */
1045 void assert_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047 {
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = DPLL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & DPLL_VCO_ENABLE);
1055 WARN(cur_state != state,
1056 "PLL state assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058 }
1059
1060 /* XXX: the dsi pll is shared between MIPI DSI ports */
1061 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1062 {
1063 u32 val;
1064 bool cur_state;
1065
1066 mutex_lock(&dev_priv->dpio_lock);
1067 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1068 mutex_unlock(&dev_priv->dpio_lock);
1069
1070 cur_state = val & DSI_PLL_VCO_EN;
1071 WARN(cur_state != state,
1072 "DSI PLL state assertion failure (expected %s, current %s)\n",
1073 state_string(state), state_string(cur_state));
1074 }
1075 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1076 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1077
1078 struct intel_shared_dpll *
1079 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1080 {
1081 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1082
1083 if (crtc->config.shared_dpll < 0)
1084 return NULL;
1085
1086 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1087 }
1088
1089 /* For ILK+ */
1090 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1091 struct intel_shared_dpll *pll,
1092 bool state)
1093 {
1094 bool cur_state;
1095 struct intel_dpll_hw_state hw_state;
1096
1097 if (HAS_PCH_LPT(dev_priv->dev)) {
1098 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1099 return;
1100 }
1101
1102 if (WARN (!pll,
1103 "asserting DPLL %s with no DPLL\n", state_string(state)))
1104 return;
1105
1106 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1107 WARN(cur_state != state,
1108 "%s assertion failure (expected %s, current %s)\n",
1109 pll->name, state_string(state), state_string(cur_state));
1110 }
1111
1112 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119 pipe);
1120
1121 if (HAS_DDI(dev_priv->dev)) {
1122 /* DDI does not have a specific FDI_TX register */
1123 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1124 val = I915_READ(reg);
1125 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1126 } else {
1127 reg = FDI_TX_CTL(pipe);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & FDI_TX_ENABLE);
1130 }
1131 WARN(cur_state != state,
1132 "FDI TX state assertion failure (expected %s, current %s)\n",
1133 state_string(state), state_string(cur_state));
1134 }
1135 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1136 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1137
1138 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, bool state)
1140 {
1141 int reg;
1142 u32 val;
1143 bool cur_state;
1144
1145 reg = FDI_RX_CTL(pipe);
1146 val = I915_READ(reg);
1147 cur_state = !!(val & FDI_RX_ENABLE);
1148 WARN(cur_state != state,
1149 "FDI RX state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151 }
1152 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1153 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1154
1155 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1156 enum pipe pipe)
1157 {
1158 int reg;
1159 u32 val;
1160
1161 /* ILK FDI PLL is always enabled */
1162 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1163 return;
1164
1165 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1166 if (HAS_DDI(dev_priv->dev))
1167 return;
1168
1169 reg = FDI_TX_CTL(pipe);
1170 val = I915_READ(reg);
1171 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1172 }
1173
1174 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1175 enum pipe pipe, bool state)
1176 {
1177 int reg;
1178 u32 val;
1179 bool cur_state;
1180
1181 reg = FDI_RX_CTL(pipe);
1182 val = I915_READ(reg);
1183 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184 WARN(cur_state != state,
1185 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186 state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191 {
1192 int pp_reg, lvds_reg;
1193 u32 val;
1194 enum pipe panel_pipe = PIPE_A;
1195 bool locked = true;
1196
1197 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1198 pp_reg = PCH_PP_CONTROL;
1199 lvds_reg = PCH_LVDS;
1200 } else {
1201 pp_reg = PP_CONTROL;
1202 lvds_reg = LVDS;
1203 }
1204
1205 val = I915_READ(pp_reg);
1206 if (!(val & PANEL_POWER_ON) ||
1207 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1208 locked = false;
1209
1210 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1211 panel_pipe = PIPE_B;
1212
1213 WARN(panel_pipe == pipe && locked,
1214 "panel assertion failure, pipe %c regs locked\n",
1215 pipe_name(pipe));
1216 }
1217
1218 static void assert_cursor(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
1220 {
1221 struct drm_device *dev = dev_priv->dev;
1222 bool cur_state;
1223
1224 if (IS_845G(dev) || IS_I865G(dev))
1225 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1226 else
1227 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1228
1229 WARN(cur_state != state,
1230 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1231 pipe_name(pipe), state_string(state), state_string(cur_state));
1232 }
1233 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1234 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1235
1236 void assert_pipe(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, bool state)
1238 {
1239 int reg;
1240 u32 val;
1241 bool cur_state;
1242 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1243 pipe);
1244
1245 /* if we need the pipe A quirk it must be always on */
1246 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1247 state = true;
1248
1249 if (!intel_display_power_enabled(dev_priv,
1250 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1251 cur_state = false;
1252 } else {
1253 reg = PIPECONF(cpu_transcoder);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & PIPECONF_ENABLE);
1256 }
1257
1258 WARN(cur_state != state,
1259 "pipe %c assertion failure (expected %s, current %s)\n",
1260 pipe_name(pipe), state_string(state), state_string(cur_state));
1261 }
1262
1263 static void assert_plane(struct drm_i915_private *dev_priv,
1264 enum plane plane, bool state)
1265 {
1266 int reg;
1267 u32 val;
1268 bool cur_state;
1269
1270 reg = DSPCNTR(plane);
1271 val = I915_READ(reg);
1272 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1273 WARN(cur_state != state,
1274 "plane %c assertion failure (expected %s, current %s)\n",
1275 plane_name(plane), state_string(state), state_string(cur_state));
1276 }
1277
1278 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1279 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1280
1281 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1282 enum pipe pipe)
1283 {
1284 struct drm_device *dev = dev_priv->dev;
1285 int reg, i;
1286 u32 val;
1287 int cur_pipe;
1288
1289 /* Primary planes are fixed to pipes on gen4+ */
1290 if (INTEL_INFO(dev)->gen >= 4) {
1291 reg = DSPCNTR(pipe);
1292 val = I915_READ(reg);
1293 WARN(val & DISPLAY_PLANE_ENABLE,
1294 "plane %c assertion failure, should be disabled but not\n",
1295 plane_name(pipe));
1296 return;
1297 }
1298
1299 /* Need to check both planes against the pipe */
1300 for_each_pipe(i) {
1301 reg = DSPCNTR(i);
1302 val = I915_READ(reg);
1303 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1304 DISPPLANE_SEL_PIPE_SHIFT;
1305 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1306 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1307 plane_name(i), pipe_name(pipe));
1308 }
1309 }
1310
1311 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1312 enum pipe pipe)
1313 {
1314 struct drm_device *dev = dev_priv->dev;
1315 int reg, sprite;
1316 u32 val;
1317
1318 if (IS_VALLEYVIEW(dev)) {
1319 for_each_sprite(pipe, sprite) {
1320 reg = SPCNTR(pipe, sprite);
1321 val = I915_READ(reg);
1322 WARN(val & SP_ENABLE,
1323 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1324 sprite_name(pipe, sprite), pipe_name(pipe));
1325 }
1326 } else if (INTEL_INFO(dev)->gen >= 7) {
1327 reg = SPRCTL(pipe);
1328 val = I915_READ(reg);
1329 WARN(val & SPRITE_ENABLE,
1330 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1331 plane_name(pipe), pipe_name(pipe));
1332 } else if (INTEL_INFO(dev)->gen >= 5) {
1333 reg = DVSCNTR(pipe);
1334 val = I915_READ(reg);
1335 WARN(val & DVS_ENABLE,
1336 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1337 plane_name(pipe), pipe_name(pipe));
1338 }
1339 }
1340
1341 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1342 {
1343 u32 val;
1344 bool enabled;
1345
1346 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1347
1348 val = I915_READ(PCH_DREF_CONTROL);
1349 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1350 DREF_SUPERSPREAD_SOURCE_MASK));
1351 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1352 }
1353
1354 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe)
1356 {
1357 int reg;
1358 u32 val;
1359 bool enabled;
1360
1361 reg = PCH_TRANSCONF(pipe);
1362 val = I915_READ(reg);
1363 enabled = !!(val & TRANS_ENABLE);
1364 WARN(enabled,
1365 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1366 pipe_name(pipe));
1367 }
1368
1369 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1370 enum pipe pipe, u32 port_sel, u32 val)
1371 {
1372 if ((val & DP_PORT_EN) == 0)
1373 return false;
1374
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1377 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1378 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1379 return false;
1380 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1381 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1382 return false;
1383 } else {
1384 if ((val & DP_PIPE_MASK) != (pipe << 30))
1385 return false;
1386 }
1387 return true;
1388 }
1389
1390 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe, u32 val)
1392 {
1393 if ((val & SDVO_ENABLE) == 0)
1394 return false;
1395
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1398 return false;
1399 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1400 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1401 return false;
1402 } else {
1403 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1404 return false;
1405 }
1406 return true;
1407 }
1408
1409 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, u32 val)
1411 {
1412 if ((val & LVDS_PORT_EN) == 0)
1413 return false;
1414
1415 if (HAS_PCH_CPT(dev_priv->dev)) {
1416 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1417 return false;
1418 } else {
1419 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1420 return false;
1421 }
1422 return true;
1423 }
1424
1425 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1426 enum pipe pipe, u32 val)
1427 {
1428 if ((val & ADPA_DAC_ENABLE) == 0)
1429 return false;
1430 if (HAS_PCH_CPT(dev_priv->dev)) {
1431 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1432 return false;
1433 } else {
1434 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1435 return false;
1436 }
1437 return true;
1438 }
1439
1440 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1441 enum pipe pipe, int reg, u32 port_sel)
1442 {
1443 u32 val = I915_READ(reg);
1444 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1445 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1446 reg, pipe_name(pipe));
1447
1448 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1449 && (val & DP_PIPEB_SELECT),
1450 "IBX PCH dp port still using transcoder B\n");
1451 }
1452
1453 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, int reg)
1455 {
1456 u32 val = I915_READ(reg);
1457 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1458 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1459 reg, pipe_name(pipe));
1460
1461 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1462 && (val & SDVO_PIPE_B_SELECT),
1463 "IBX PCH hdmi port still using transcoder B\n");
1464 }
1465
1466 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe)
1468 {
1469 int reg;
1470 u32 val;
1471
1472 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1475
1476 reg = PCH_ADPA;
1477 val = I915_READ(reg);
1478 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1479 "PCH VGA enabled on transcoder %c, should be disabled\n",
1480 pipe_name(pipe));
1481
1482 reg = PCH_LVDS;
1483 val = I915_READ(reg);
1484 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486 pipe_name(pipe));
1487
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void intel_init_dpio(struct drm_device *dev)
1494 {
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496
1497 if (!IS_VALLEYVIEW(dev))
1498 return;
1499
1500 /*
1501 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1502 * CHV x1 PHY (DP/HDMI D)
1503 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1504 */
1505 if (IS_CHERRYVIEW(dev)) {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1508 } else {
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1510 }
1511 }
1512
1513 static void intel_reset_dpio(struct drm_device *dev)
1514 {
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516
1517 if (!IS_VALLEYVIEW(dev))
1518 return;
1519
1520 if (IS_CHERRYVIEW(dev)) {
1521 enum dpio_phy phy;
1522 u32 val;
1523
1524 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1525 /* Poll for phypwrgood signal */
1526 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1527 PHY_POWERGOOD(phy), 1))
1528 DRM_ERROR("Display PHY %d is not power up\n", phy);
1529
1530 /*
1531 * Deassert common lane reset for PHY.
1532 *
1533 * This should only be done on init and resume from S3
1534 * with both PLLs disabled, or we risk losing DPIO and
1535 * PLL synchronization.
1536 */
1537 val = I915_READ(DISPLAY_PHY_CONTROL);
1538 I915_WRITE(DISPLAY_PHY_CONTROL,
1539 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1540 }
1541
1542 } else {
1543 /*
1544 * If DPIO has already been reset, e.g. by BIOS, just skip all
1545 * this.
1546 */
1547 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1548 return;
1549
1550 /*
1551 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1552 * Need to assert and de-assert PHY SB reset by gating the
1553 * common lane power, then un-gating it.
1554 * Simply ungating isn't enough to reset the PHY enough to get
1555 * ports and lanes running.
1556 */
1557 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1558 false);
1559 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1560 true);
1561 }
1562 }
1563
1564 static void vlv_enable_pll(struct intel_crtc *crtc)
1565 {
1566 struct drm_device *dev = crtc->base.dev;
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1568 int reg = DPLL(crtc->pipe);
1569 u32 dpll = crtc->config.dpll_hw_state.dpll;
1570
1571 assert_pipe_disabled(dev_priv, crtc->pipe);
1572
1573 /* No really, not for ILK+ */
1574 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1575
1576 /* PLL is protected by panel, make sure we can write it */
1577 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1578 assert_panel_unlocked(dev_priv, crtc->pipe);
1579
1580 I915_WRITE(reg, dpll);
1581 POSTING_READ(reg);
1582 udelay(150);
1583
1584 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1585 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1586
1587 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1588 POSTING_READ(DPLL_MD(crtc->pipe));
1589
1590 /* We do this three times for luck */
1591 I915_WRITE(reg, dpll);
1592 POSTING_READ(reg);
1593 udelay(150); /* wait for warmup */
1594 I915_WRITE(reg, dpll);
1595 POSTING_READ(reg);
1596 udelay(150); /* wait for warmup */
1597 I915_WRITE(reg, dpll);
1598 POSTING_READ(reg);
1599 udelay(150); /* wait for warmup */
1600 }
1601
1602 static void chv_enable_pll(struct intel_crtc *crtc)
1603 {
1604 struct drm_device *dev = crtc->base.dev;
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 int pipe = crtc->pipe;
1607 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1608 u32 tmp;
1609
1610 assert_pipe_disabled(dev_priv, crtc->pipe);
1611
1612 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1613
1614 mutex_lock(&dev_priv->dpio_lock);
1615
1616 /* Enable back the 10bit clock to display controller */
1617 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1618 tmp |= DPIO_DCLKP_EN;
1619 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1620
1621 /*
1622 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1623 */
1624 udelay(1);
1625
1626 /* Enable PLL */
1627 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1628
1629 /* Check PLL is locked */
1630 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1631 DRM_ERROR("PLL %d failed to lock\n", pipe);
1632
1633 /* not sure when this should be written */
1634 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1635 POSTING_READ(DPLL_MD(pipe));
1636
1637 mutex_unlock(&dev_priv->dpio_lock);
1638 }
1639
1640 static void i9xx_enable_pll(struct intel_crtc *crtc)
1641 {
1642 struct drm_device *dev = crtc->base.dev;
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644 int reg = DPLL(crtc->pipe);
1645 u32 dpll = crtc->config.dpll_hw_state.dpll;
1646
1647 assert_pipe_disabled(dev_priv, crtc->pipe);
1648
1649 /* No really, not for ILK+ */
1650 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1651
1652 /* PLL is protected by panel, make sure we can write it */
1653 if (IS_MOBILE(dev) && !IS_I830(dev))
1654 assert_panel_unlocked(dev_priv, crtc->pipe);
1655
1656 I915_WRITE(reg, dpll);
1657
1658 /* Wait for the clocks to stabilize. */
1659 POSTING_READ(reg);
1660 udelay(150);
1661
1662 if (INTEL_INFO(dev)->gen >= 4) {
1663 I915_WRITE(DPLL_MD(crtc->pipe),
1664 crtc->config.dpll_hw_state.dpll_md);
1665 } else {
1666 /* The pixel multiplier can only be updated once the
1667 * DPLL is enabled and the clocks are stable.
1668 *
1669 * So write it again.
1670 */
1671 I915_WRITE(reg, dpll);
1672 }
1673
1674 /* We do this three times for luck */
1675 I915_WRITE(reg, dpll);
1676 POSTING_READ(reg);
1677 udelay(150); /* wait for warmup */
1678 I915_WRITE(reg, dpll);
1679 POSTING_READ(reg);
1680 udelay(150); /* wait for warmup */
1681 I915_WRITE(reg, dpll);
1682 POSTING_READ(reg);
1683 udelay(150); /* wait for warmup */
1684 }
1685
1686 /**
1687 * i9xx_disable_pll - disable a PLL
1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe PLL to disable
1690 *
1691 * Disable the PLL for @pipe, making sure the pipe is off first.
1692 *
1693 * Note! This is for pre-ILK only.
1694 */
1695 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1696 {
1697 /* Don't disable pipe A or pipe A PLLs if needed */
1698 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1699 return;
1700
1701 /* Make sure the pipe isn't still relying on us */
1702 assert_pipe_disabled(dev_priv, pipe);
1703
1704 I915_WRITE(DPLL(pipe), 0);
1705 POSTING_READ(DPLL(pipe));
1706 }
1707
1708 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1709 {
1710 u32 val = 0;
1711
1712 /* Make sure the pipe isn't still relying on us */
1713 assert_pipe_disabled(dev_priv, pipe);
1714
1715 /*
1716 * Leave integrated clock source and reference clock enabled for pipe B.
1717 * The latter is needed for VGA hotplug / manual detection.
1718 */
1719 if (pipe == PIPE_B)
1720 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
1723
1724 }
1725
1726 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1727 {
1728 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1729 u32 val;
1730
1731 /* Make sure the pipe isn't still relying on us */
1732 assert_pipe_disabled(dev_priv, pipe);
1733
1734 /* Set PLL en = 0 */
1735 val = DPLL_SSC_REF_CLOCK_CHV;
1736 if (pipe != PIPE_A)
1737 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1738 I915_WRITE(DPLL(pipe), val);
1739 POSTING_READ(DPLL(pipe));
1740
1741 mutex_lock(&dev_priv->dpio_lock);
1742
1743 /* Disable 10bit clock to display controller */
1744 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1745 val &= ~DPIO_DCLKP_EN;
1746 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1747
1748 /* disable left/right clock distribution */
1749 if (pipe != PIPE_B) {
1750 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1751 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1752 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1753 } else {
1754 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1755 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1756 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1757 }
1758
1759 mutex_unlock(&dev_priv->dpio_lock);
1760 }
1761
1762 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1763 struct intel_digital_port *dport)
1764 {
1765 u32 port_mask;
1766 int dpll_reg;
1767
1768 switch (dport->port) {
1769 case PORT_B:
1770 port_mask = DPLL_PORTB_READY_MASK;
1771 dpll_reg = DPLL(0);
1772 break;
1773 case PORT_C:
1774 port_mask = DPLL_PORTC_READY_MASK;
1775 dpll_reg = DPLL(0);
1776 break;
1777 case PORT_D:
1778 port_mask = DPLL_PORTD_READY_MASK;
1779 dpll_reg = DPIO_PHY_STATUS;
1780 break;
1781 default:
1782 BUG();
1783 }
1784
1785 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1786 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1787 port_name(dport->port), I915_READ(dpll_reg));
1788 }
1789
1790 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1791 {
1792 struct drm_device *dev = crtc->base.dev;
1793 struct drm_i915_private *dev_priv = dev->dev_private;
1794 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1795
1796 if (WARN_ON(pll == NULL))
1797 return;
1798
1799 WARN_ON(!pll->refcount);
1800 if (pll->active == 0) {
1801 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1802 WARN_ON(pll->on);
1803 assert_shared_dpll_disabled(dev_priv, pll);
1804
1805 pll->mode_set(dev_priv, pll);
1806 }
1807 }
1808
1809 /**
1810 * intel_enable_shared_dpll - enable PCH PLL
1811 * @dev_priv: i915 private structure
1812 * @pipe: pipe PLL to enable
1813 *
1814 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1815 * drives the transcoder clock.
1816 */
1817 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1818 {
1819 struct drm_device *dev = crtc->base.dev;
1820 struct drm_i915_private *dev_priv = dev->dev_private;
1821 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1822
1823 if (WARN_ON(pll == NULL))
1824 return;
1825
1826 if (WARN_ON(pll->refcount == 0))
1827 return;
1828
1829 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1830 pll->name, pll->active, pll->on,
1831 crtc->base.base.id);
1832
1833 if (pll->active++) {
1834 WARN_ON(!pll->on);
1835 assert_shared_dpll_enabled(dev_priv, pll);
1836 return;
1837 }
1838 WARN_ON(pll->on);
1839
1840 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1841 pll->enable(dev_priv, pll);
1842 pll->on = true;
1843 }
1844
1845 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1846 {
1847 struct drm_device *dev = crtc->base.dev;
1848 struct drm_i915_private *dev_priv = dev->dev_private;
1849 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1850
1851 /* PCH only available on ILK+ */
1852 BUG_ON(INTEL_INFO(dev)->gen < 5);
1853 if (WARN_ON(pll == NULL))
1854 return;
1855
1856 if (WARN_ON(pll->refcount == 0))
1857 return;
1858
1859 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1860 pll->name, pll->active, pll->on,
1861 crtc->base.base.id);
1862
1863 if (WARN_ON(pll->active == 0)) {
1864 assert_shared_dpll_disabled(dev_priv, pll);
1865 return;
1866 }
1867
1868 assert_shared_dpll_enabled(dev_priv, pll);
1869 WARN_ON(!pll->on);
1870 if (--pll->active)
1871 return;
1872
1873 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1874 pll->disable(dev_priv, pll);
1875 pll->on = false;
1876 }
1877
1878 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1879 enum pipe pipe)
1880 {
1881 struct drm_device *dev = dev_priv->dev;
1882 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1884 uint32_t reg, val, pipeconf_val;
1885
1886 /* PCH only available on ILK+ */
1887 BUG_ON(INTEL_INFO(dev)->gen < 5);
1888
1889 /* Make sure PCH DPLL is enabled */
1890 assert_shared_dpll_enabled(dev_priv,
1891 intel_crtc_to_shared_dpll(intel_crtc));
1892
1893 /* FDI must be feeding us bits for PCH ports */
1894 assert_fdi_tx_enabled(dev_priv, pipe);
1895 assert_fdi_rx_enabled(dev_priv, pipe);
1896
1897 if (HAS_PCH_CPT(dev)) {
1898 /* Workaround: Set the timing override bit before enabling the
1899 * pch transcoder. */
1900 reg = TRANS_CHICKEN2(pipe);
1901 val = I915_READ(reg);
1902 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1903 I915_WRITE(reg, val);
1904 }
1905
1906 reg = PCH_TRANSCONF(pipe);
1907 val = I915_READ(reg);
1908 pipeconf_val = I915_READ(PIPECONF(pipe));
1909
1910 if (HAS_PCH_IBX(dev_priv->dev)) {
1911 /*
1912 * make the BPC in transcoder be consistent with
1913 * that in pipeconf reg.
1914 */
1915 val &= ~PIPECONF_BPC_MASK;
1916 val |= pipeconf_val & PIPECONF_BPC_MASK;
1917 }
1918
1919 val &= ~TRANS_INTERLACE_MASK;
1920 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1921 if (HAS_PCH_IBX(dev_priv->dev) &&
1922 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1923 val |= TRANS_LEGACY_INTERLACED_ILK;
1924 else
1925 val |= TRANS_INTERLACED;
1926 else
1927 val |= TRANS_PROGRESSIVE;
1928
1929 I915_WRITE(reg, val | TRANS_ENABLE);
1930 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1931 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1932 }
1933
1934 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1935 enum transcoder cpu_transcoder)
1936 {
1937 u32 val, pipeconf_val;
1938
1939 /* PCH only available on ILK+ */
1940 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1941
1942 /* FDI must be feeding us bits for PCH ports */
1943 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1944 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1945
1946 /* Workaround: set timing override bit. */
1947 val = I915_READ(_TRANSA_CHICKEN2);
1948 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1949 I915_WRITE(_TRANSA_CHICKEN2, val);
1950
1951 val = TRANS_ENABLE;
1952 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1953
1954 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1955 PIPECONF_INTERLACED_ILK)
1956 val |= TRANS_INTERLACED;
1957 else
1958 val |= TRANS_PROGRESSIVE;
1959
1960 I915_WRITE(LPT_TRANSCONF, val);
1961 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1962 DRM_ERROR("Failed to enable PCH transcoder\n");
1963 }
1964
1965 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1966 enum pipe pipe)
1967 {
1968 struct drm_device *dev = dev_priv->dev;
1969 uint32_t reg, val;
1970
1971 /* FDI relies on the transcoder */
1972 assert_fdi_tx_disabled(dev_priv, pipe);
1973 assert_fdi_rx_disabled(dev_priv, pipe);
1974
1975 /* Ports must be off as well */
1976 assert_pch_ports_disabled(dev_priv, pipe);
1977
1978 reg = PCH_TRANSCONF(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_ENABLE;
1981 I915_WRITE(reg, val);
1982 /* wait for PCH transcoder off, transcoder state */
1983 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1984 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1985
1986 if (!HAS_PCH_IBX(dev)) {
1987 /* Workaround: Clear the timing override chicken bit again. */
1988 reg = TRANS_CHICKEN2(pipe);
1989 val = I915_READ(reg);
1990 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1991 I915_WRITE(reg, val);
1992 }
1993 }
1994
1995 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1996 {
1997 u32 val;
1998
1999 val = I915_READ(LPT_TRANSCONF);
2000 val &= ~TRANS_ENABLE;
2001 I915_WRITE(LPT_TRANSCONF, val);
2002 /* wait for PCH transcoder off, transcoder state */
2003 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2004 DRM_ERROR("Failed to disable PCH transcoder\n");
2005
2006 /* Workaround: clear timing override bit. */
2007 val = I915_READ(_TRANSA_CHICKEN2);
2008 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2009 I915_WRITE(_TRANSA_CHICKEN2, val);
2010 }
2011
2012 /**
2013 * intel_enable_pipe - enable a pipe, asserting requirements
2014 * @crtc: crtc responsible for the pipe
2015 *
2016 * Enable @crtc's pipe, making sure that various hardware specific requirements
2017 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2018 */
2019 static void intel_enable_pipe(struct intel_crtc *crtc)
2020 {
2021 struct drm_device *dev = crtc->base.dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 enum pipe pipe = crtc->pipe;
2024 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2025 pipe);
2026 enum pipe pch_transcoder;
2027 int reg;
2028 u32 val;
2029
2030 assert_planes_disabled(dev_priv, pipe);
2031 assert_cursor_disabled(dev_priv, pipe);
2032 assert_sprites_disabled(dev_priv, pipe);
2033
2034 if (HAS_PCH_LPT(dev_priv->dev))
2035 pch_transcoder = TRANSCODER_A;
2036 else
2037 pch_transcoder = pipe;
2038
2039 /*
2040 * A pipe without a PLL won't actually be able to drive bits from
2041 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2042 * need the check.
2043 */
2044 if (!HAS_PCH_SPLIT(dev_priv->dev))
2045 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2046 assert_dsi_pll_enabled(dev_priv);
2047 else
2048 assert_pll_enabled(dev_priv, pipe);
2049 else {
2050 if (crtc->config.has_pch_encoder) {
2051 /* if driving the PCH, we need FDI enabled */
2052 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2053 assert_fdi_tx_pll_enabled(dev_priv,
2054 (enum pipe) cpu_transcoder);
2055 }
2056 /* FIXME: assert CPU port conditions for SNB+ */
2057 }
2058
2059 reg = PIPECONF(cpu_transcoder);
2060 val = I915_READ(reg);
2061 if (val & PIPECONF_ENABLE) {
2062 WARN_ON(!(pipe == PIPE_A &&
2063 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2064 return;
2065 }
2066
2067 I915_WRITE(reg, val | PIPECONF_ENABLE);
2068 POSTING_READ(reg);
2069 }
2070
2071 /**
2072 * intel_disable_pipe - disable a pipe, asserting requirements
2073 * @dev_priv: i915 private structure
2074 * @pipe: pipe to disable
2075 *
2076 * Disable @pipe, making sure that various hardware specific requirements
2077 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2078 *
2079 * @pipe should be %PIPE_A or %PIPE_B.
2080 *
2081 * Will wait until the pipe has shut down before returning.
2082 */
2083 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2084 enum pipe pipe)
2085 {
2086 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2087 pipe);
2088 int reg;
2089 u32 val;
2090
2091 /*
2092 * Make sure planes won't keep trying to pump pixels to us,
2093 * or we might hang the display.
2094 */
2095 assert_planes_disabled(dev_priv, pipe);
2096 assert_cursor_disabled(dev_priv, pipe);
2097 assert_sprites_disabled(dev_priv, pipe);
2098
2099 /* Don't disable pipe A or pipe A PLLs if needed */
2100 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2101 return;
2102
2103 reg = PIPECONF(cpu_transcoder);
2104 val = I915_READ(reg);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 return;
2107
2108 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2109 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2110 }
2111
2112 /*
2113 * Plane regs are double buffered, going from enabled->disabled needs a
2114 * trigger in order to latch. The display address reg provides this.
2115 */
2116 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2117 enum plane plane)
2118 {
2119 struct drm_device *dev = dev_priv->dev;
2120 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2121
2122 I915_WRITE(reg, I915_READ(reg));
2123 POSTING_READ(reg);
2124 }
2125
2126 /**
2127 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2128 * @dev_priv: i915 private structure
2129 * @plane: plane to enable
2130 * @pipe: pipe being fed
2131 *
2132 * Enable @plane on @pipe, making sure that @pipe is running first.
2133 */
2134 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2135 enum plane plane, enum pipe pipe)
2136 {
2137 struct drm_device *dev = dev_priv->dev;
2138 struct intel_crtc *intel_crtc =
2139 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2140 int reg;
2141 u32 val;
2142
2143 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2144 assert_pipe_enabled(dev_priv, pipe);
2145
2146 if (intel_crtc->primary_enabled)
2147 return;
2148
2149 intel_crtc->primary_enabled = true;
2150
2151 reg = DSPCNTR(plane);
2152 val = I915_READ(reg);
2153 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2154
2155 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2156 intel_flush_primary_plane(dev_priv, plane);
2157
2158 /*
2159 * BDW signals flip done immediately if the plane
2160 * is disabled, even if the plane enable is already
2161 * armed to occur at the next vblank :(
2162 */
2163 if (IS_BROADWELL(dev))
2164 intel_wait_for_vblank(dev, intel_crtc->pipe);
2165 }
2166
2167 /**
2168 * intel_disable_primary_hw_plane - disable the primary hardware plane
2169 * @dev_priv: i915 private structure
2170 * @plane: plane to disable
2171 * @pipe: pipe consuming the data
2172 *
2173 * Disable @plane; should be an independent operation.
2174 */
2175 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2176 enum plane plane, enum pipe pipe)
2177 {
2178 struct intel_crtc *intel_crtc =
2179 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2180 int reg;
2181 u32 val;
2182
2183 if (!intel_crtc->primary_enabled)
2184 return;
2185
2186 intel_crtc->primary_enabled = false;
2187
2188 reg = DSPCNTR(plane);
2189 val = I915_READ(reg);
2190 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2191
2192 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2193 intel_flush_primary_plane(dev_priv, plane);
2194 }
2195
2196 static bool need_vtd_wa(struct drm_device *dev)
2197 {
2198 #ifdef CONFIG_INTEL_IOMMU
2199 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2200 return true;
2201 #endif
2202 return false;
2203 }
2204
2205 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2206 {
2207 int tile_height;
2208
2209 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2210 return ALIGN(height, tile_height);
2211 }
2212
2213 int
2214 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2215 struct drm_i915_gem_object *obj,
2216 struct intel_engine_cs *pipelined)
2217 {
2218 struct drm_i915_private *dev_priv = dev->dev_private;
2219 u32 alignment;
2220 int ret;
2221
2222 switch (obj->tiling_mode) {
2223 case I915_TILING_NONE:
2224 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2225 alignment = 128 * 1024;
2226 else if (INTEL_INFO(dev)->gen >= 4)
2227 alignment = 4 * 1024;
2228 else
2229 alignment = 64 * 1024;
2230 break;
2231 case I915_TILING_X:
2232 /* pin() will align the object as required by fence */
2233 alignment = 0;
2234 break;
2235 case I915_TILING_Y:
2236 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2237 return -EINVAL;
2238 default:
2239 BUG();
2240 }
2241
2242 /* Note that the w/a also requires 64 PTE of padding following the
2243 * bo. We currently fill all unused PTE with the shadow page and so
2244 * we should always have valid PTE following the scanout preventing
2245 * the VT-d warning.
2246 */
2247 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2248 alignment = 256 * 1024;
2249
2250 dev_priv->mm.interruptible = false;
2251 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2252 if (ret)
2253 goto err_interruptible;
2254
2255 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2256 * fence, whereas 965+ only requires a fence if using
2257 * framebuffer compression. For simplicity, we always install
2258 * a fence as the cost is not that onerous.
2259 */
2260 ret = i915_gem_object_get_fence(obj);
2261 if (ret)
2262 goto err_unpin;
2263
2264 i915_gem_object_pin_fence(obj);
2265
2266 dev_priv->mm.interruptible = true;
2267 return 0;
2268
2269 err_unpin:
2270 i915_gem_object_unpin_from_display_plane(obj);
2271 err_interruptible:
2272 dev_priv->mm.interruptible = true;
2273 return ret;
2274 }
2275
2276 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2277 {
2278 i915_gem_object_unpin_fence(obj);
2279 i915_gem_object_unpin_from_display_plane(obj);
2280 }
2281
2282 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2283 * is assumed to be a power-of-two. */
2284 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2285 unsigned int tiling_mode,
2286 unsigned int cpp,
2287 unsigned int pitch)
2288 {
2289 if (tiling_mode != I915_TILING_NONE) {
2290 unsigned int tile_rows, tiles;
2291
2292 tile_rows = *y / 8;
2293 *y %= 8;
2294
2295 tiles = *x / (512/cpp);
2296 *x %= 512/cpp;
2297
2298 return tile_rows * pitch * 8 + tiles * 4096;
2299 } else {
2300 unsigned int offset;
2301
2302 offset = *y * pitch + *x * cpp;
2303 *y = 0;
2304 *x = (offset & 4095) / cpp;
2305 return offset & -4096;
2306 }
2307 }
2308
2309 int intel_format_to_fourcc(int format)
2310 {
2311 switch (format) {
2312 case DISPPLANE_8BPP:
2313 return DRM_FORMAT_C8;
2314 case DISPPLANE_BGRX555:
2315 return DRM_FORMAT_XRGB1555;
2316 case DISPPLANE_BGRX565:
2317 return DRM_FORMAT_RGB565;
2318 default:
2319 case DISPPLANE_BGRX888:
2320 return DRM_FORMAT_XRGB8888;
2321 case DISPPLANE_RGBX888:
2322 return DRM_FORMAT_XBGR8888;
2323 case DISPPLANE_BGRX101010:
2324 return DRM_FORMAT_XRGB2101010;
2325 case DISPPLANE_RGBX101010:
2326 return DRM_FORMAT_XBGR2101010;
2327 }
2328 }
2329
2330 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2331 struct intel_plane_config *plane_config)
2332 {
2333 struct drm_device *dev = crtc->base.dev;
2334 struct drm_i915_gem_object *obj = NULL;
2335 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2336 u32 base = plane_config->base;
2337
2338 if (plane_config->size == 0)
2339 return false;
2340
2341 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2342 plane_config->size);
2343 if (!obj)
2344 return false;
2345
2346 if (plane_config->tiled) {
2347 obj->tiling_mode = I915_TILING_X;
2348 obj->stride = crtc->base.primary->fb->pitches[0];
2349 }
2350
2351 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2352 mode_cmd.width = crtc->base.primary->fb->width;
2353 mode_cmd.height = crtc->base.primary->fb->height;
2354 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2355
2356 mutex_lock(&dev->struct_mutex);
2357
2358 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2359 &mode_cmd, obj)) {
2360 DRM_DEBUG_KMS("intel fb init failed\n");
2361 goto out_unref_obj;
2362 }
2363
2364 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2365 mutex_unlock(&dev->struct_mutex);
2366
2367 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2368 return true;
2369
2370 out_unref_obj:
2371 drm_gem_object_unreference(&obj->base);
2372 mutex_unlock(&dev->struct_mutex);
2373 return false;
2374 }
2375
2376 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2377 struct intel_plane_config *plane_config)
2378 {
2379 struct drm_device *dev = intel_crtc->base.dev;
2380 struct drm_crtc *c;
2381 struct intel_crtc *i;
2382 struct intel_framebuffer *fb;
2383
2384 if (!intel_crtc->base.primary->fb)
2385 return;
2386
2387 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2388 return;
2389
2390 kfree(intel_crtc->base.primary->fb);
2391 intel_crtc->base.primary->fb = NULL;
2392
2393 /*
2394 * Failed to alloc the obj, check to see if we should share
2395 * an fb with another CRTC instead
2396 */
2397 for_each_crtc(dev, c) {
2398 i = to_intel_crtc(c);
2399
2400 if (c == &intel_crtc->base)
2401 continue;
2402
2403 if (!i->active || !c->primary->fb)
2404 continue;
2405
2406 fb = to_intel_framebuffer(c->primary->fb);
2407 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2408 drm_framebuffer_reference(c->primary->fb);
2409 intel_crtc->base.primary->fb = c->primary->fb;
2410 fb->obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2411 break;
2412 }
2413 }
2414 }
2415
2416 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2417 struct drm_framebuffer *fb,
2418 int x, int y)
2419 {
2420 struct drm_device *dev = crtc->dev;
2421 struct drm_i915_private *dev_priv = dev->dev_private;
2422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2423 struct intel_framebuffer *intel_fb;
2424 struct drm_i915_gem_object *obj;
2425 int plane = intel_crtc->plane;
2426 unsigned long linear_offset;
2427 u32 dspcntr;
2428 u32 reg;
2429
2430 intel_fb = to_intel_framebuffer(fb);
2431 obj = intel_fb->obj;
2432
2433 reg = DSPCNTR(plane);
2434 dspcntr = I915_READ(reg);
2435 /* Mask out pixel format bits in case we change it */
2436 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2437 switch (fb->pixel_format) {
2438 case DRM_FORMAT_C8:
2439 dspcntr |= DISPPLANE_8BPP;
2440 break;
2441 case DRM_FORMAT_XRGB1555:
2442 case DRM_FORMAT_ARGB1555:
2443 dspcntr |= DISPPLANE_BGRX555;
2444 break;
2445 case DRM_FORMAT_RGB565:
2446 dspcntr |= DISPPLANE_BGRX565;
2447 break;
2448 case DRM_FORMAT_XRGB8888:
2449 case DRM_FORMAT_ARGB8888:
2450 dspcntr |= DISPPLANE_BGRX888;
2451 break;
2452 case DRM_FORMAT_XBGR8888:
2453 case DRM_FORMAT_ABGR8888:
2454 dspcntr |= DISPPLANE_RGBX888;
2455 break;
2456 case DRM_FORMAT_XRGB2101010:
2457 case DRM_FORMAT_ARGB2101010:
2458 dspcntr |= DISPPLANE_BGRX101010;
2459 break;
2460 case DRM_FORMAT_XBGR2101010:
2461 case DRM_FORMAT_ABGR2101010:
2462 dspcntr |= DISPPLANE_RGBX101010;
2463 break;
2464 default:
2465 BUG();
2466 }
2467
2468 if (INTEL_INFO(dev)->gen >= 4) {
2469 if (obj->tiling_mode != I915_TILING_NONE)
2470 dspcntr |= DISPPLANE_TILED;
2471 else
2472 dspcntr &= ~DISPPLANE_TILED;
2473 }
2474
2475 if (IS_G4X(dev))
2476 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2477
2478 I915_WRITE(reg, dspcntr);
2479
2480 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2481
2482 if (INTEL_INFO(dev)->gen >= 4) {
2483 intel_crtc->dspaddr_offset =
2484 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2485 fb->bits_per_pixel / 8,
2486 fb->pitches[0]);
2487 linear_offset -= intel_crtc->dspaddr_offset;
2488 } else {
2489 intel_crtc->dspaddr_offset = linear_offset;
2490 }
2491
2492 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2493 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2494 fb->pitches[0]);
2495 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2496 if (INTEL_INFO(dev)->gen >= 4) {
2497 I915_WRITE(DSPSURF(plane),
2498 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2499 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2500 I915_WRITE(DSPLINOFF(plane), linear_offset);
2501 } else
2502 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2503 POSTING_READ(reg);
2504 }
2505
2506 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2507 struct drm_framebuffer *fb,
2508 int x, int y)
2509 {
2510 struct drm_device *dev = crtc->dev;
2511 struct drm_i915_private *dev_priv = dev->dev_private;
2512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2513 struct intel_framebuffer *intel_fb;
2514 struct drm_i915_gem_object *obj;
2515 int plane = intel_crtc->plane;
2516 unsigned long linear_offset;
2517 u32 dspcntr;
2518 u32 reg;
2519
2520 intel_fb = to_intel_framebuffer(fb);
2521 obj = intel_fb->obj;
2522
2523 reg = DSPCNTR(plane);
2524 dspcntr = I915_READ(reg);
2525 /* Mask out pixel format bits in case we change it */
2526 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2527 switch (fb->pixel_format) {
2528 case DRM_FORMAT_C8:
2529 dspcntr |= DISPPLANE_8BPP;
2530 break;
2531 case DRM_FORMAT_RGB565:
2532 dspcntr |= DISPPLANE_BGRX565;
2533 break;
2534 case DRM_FORMAT_XRGB8888:
2535 case DRM_FORMAT_ARGB8888:
2536 dspcntr |= DISPPLANE_BGRX888;
2537 break;
2538 case DRM_FORMAT_XBGR8888:
2539 case DRM_FORMAT_ABGR8888:
2540 dspcntr |= DISPPLANE_RGBX888;
2541 break;
2542 case DRM_FORMAT_XRGB2101010:
2543 case DRM_FORMAT_ARGB2101010:
2544 dspcntr |= DISPPLANE_BGRX101010;
2545 break;
2546 case DRM_FORMAT_XBGR2101010:
2547 case DRM_FORMAT_ABGR2101010:
2548 dspcntr |= DISPPLANE_RGBX101010;
2549 break;
2550 default:
2551 BUG();
2552 }
2553
2554 if (obj->tiling_mode != I915_TILING_NONE)
2555 dspcntr |= DISPPLANE_TILED;
2556 else
2557 dspcntr &= ~DISPPLANE_TILED;
2558
2559 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2560 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2561 else
2562 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2563
2564 I915_WRITE(reg, dspcntr);
2565
2566 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2567 intel_crtc->dspaddr_offset =
2568 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2569 fb->bits_per_pixel / 8,
2570 fb->pitches[0]);
2571 linear_offset -= intel_crtc->dspaddr_offset;
2572
2573 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2574 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2575 fb->pitches[0]);
2576 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2577 I915_WRITE(DSPSURF(plane),
2578 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2579 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2580 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2581 } else {
2582 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2583 I915_WRITE(DSPLINOFF(plane), linear_offset);
2584 }
2585 POSTING_READ(reg);
2586 }
2587
2588 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2589 static int
2590 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2591 int x, int y, enum mode_set_atomic state)
2592 {
2593 struct drm_device *dev = crtc->dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595
2596 if (dev_priv->display.disable_fbc)
2597 dev_priv->display.disable_fbc(dev);
2598 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2599
2600 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2601
2602 return 0;
2603 }
2604
2605 void intel_display_handle_reset(struct drm_device *dev)
2606 {
2607 struct drm_i915_private *dev_priv = dev->dev_private;
2608 struct drm_crtc *crtc;
2609
2610 /*
2611 * Flips in the rings have been nuked by the reset,
2612 * so complete all pending flips so that user space
2613 * will get its events and not get stuck.
2614 *
2615 * Also update the base address of all primary
2616 * planes to the the last fb to make sure we're
2617 * showing the correct fb after a reset.
2618 *
2619 * Need to make two loops over the crtcs so that we
2620 * don't try to grab a crtc mutex before the
2621 * pending_flip_queue really got woken up.
2622 */
2623
2624 for_each_crtc(dev, crtc) {
2625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2626 enum plane plane = intel_crtc->plane;
2627
2628 intel_prepare_page_flip(dev, plane);
2629 intel_finish_page_flip_plane(dev, plane);
2630 }
2631
2632 for_each_crtc(dev, crtc) {
2633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2634
2635 drm_modeset_lock(&crtc->mutex, NULL);
2636 /*
2637 * FIXME: Once we have proper support for primary planes (and
2638 * disabling them without disabling the entire crtc) allow again
2639 * a NULL crtc->primary->fb.
2640 */
2641 if (intel_crtc->active && crtc->primary->fb)
2642 dev_priv->display.update_primary_plane(crtc,
2643 crtc->primary->fb,
2644 crtc->x,
2645 crtc->y);
2646 drm_modeset_unlock(&crtc->mutex);
2647 }
2648 }
2649
2650 static int
2651 intel_finish_fb(struct drm_framebuffer *old_fb)
2652 {
2653 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2654 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2655 bool was_interruptible = dev_priv->mm.interruptible;
2656 int ret;
2657
2658 /* Big Hammer, we also need to ensure that any pending
2659 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2660 * current scanout is retired before unpinning the old
2661 * framebuffer.
2662 *
2663 * This should only fail upon a hung GPU, in which case we
2664 * can safely continue.
2665 */
2666 dev_priv->mm.interruptible = false;
2667 ret = i915_gem_object_finish_gpu(obj);
2668 dev_priv->mm.interruptible = was_interruptible;
2669
2670 return ret;
2671 }
2672
2673 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2674 {
2675 struct drm_device *dev = crtc->dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2678 unsigned long flags;
2679 bool pending;
2680
2681 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2682 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2683 return false;
2684
2685 spin_lock_irqsave(&dev->event_lock, flags);
2686 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2687 spin_unlock_irqrestore(&dev->event_lock, flags);
2688
2689 return pending;
2690 }
2691
2692 static int
2693 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2694 struct drm_framebuffer *fb)
2695 {
2696 struct drm_device *dev = crtc->dev;
2697 struct drm_i915_private *dev_priv = dev->dev_private;
2698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2699 enum pipe pipe = intel_crtc->pipe;
2700 struct drm_framebuffer *old_fb;
2701 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
2702 int ret;
2703
2704 if (intel_crtc_has_pending_flip(crtc)) {
2705 DRM_ERROR("pipe is still busy with an old pageflip\n");
2706 return -EBUSY;
2707 }
2708
2709 /* no fb bound */
2710 if (!fb) {
2711 DRM_ERROR("No FB bound\n");
2712 return 0;
2713 }
2714
2715 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2716 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2717 plane_name(intel_crtc->plane),
2718 INTEL_INFO(dev)->num_pipes);
2719 return -EINVAL;
2720 }
2721
2722 old_fb = crtc->primary->fb;
2723
2724 mutex_lock(&dev->struct_mutex);
2725 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2726 if (ret == 0)
2727 i915_gem_track_fb(to_intel_framebuffer(old_fb)->obj, obj,
2728 INTEL_FRONTBUFFER_PRIMARY(pipe));
2729 mutex_unlock(&dev->struct_mutex);
2730 if (ret != 0) {
2731 DRM_ERROR("pin & fence failed\n");
2732 return ret;
2733 }
2734
2735 /*
2736 * Update pipe size and adjust fitter if needed: the reason for this is
2737 * that in compute_mode_changes we check the native mode (not the pfit
2738 * mode) to see if we can flip rather than do a full mode set. In the
2739 * fastboot case, we'll flip, but if we don't update the pipesrc and
2740 * pfit state, we'll end up with a big fb scanned out into the wrong
2741 * sized surface.
2742 *
2743 * To fix this properly, we need to hoist the checks up into
2744 * compute_mode_changes (or above), check the actual pfit state and
2745 * whether the platform allows pfit disable with pipe active, and only
2746 * then update the pipesrc and pfit state, even on the flip path.
2747 */
2748 if (i915.fastboot) {
2749 const struct drm_display_mode *adjusted_mode =
2750 &intel_crtc->config.adjusted_mode;
2751
2752 I915_WRITE(PIPESRC(intel_crtc->pipe),
2753 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2754 (adjusted_mode->crtc_vdisplay - 1));
2755 if (!intel_crtc->config.pch_pfit.enabled &&
2756 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2757 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2758 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2759 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2760 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2761 }
2762 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2763 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2764 }
2765
2766 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2767
2768 if (intel_crtc->active)
2769 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2770
2771 crtc->primary->fb = fb;
2772 crtc->x = x;
2773 crtc->y = y;
2774
2775 if (old_fb) {
2776 if (intel_crtc->active && old_fb != fb)
2777 intel_wait_for_vblank(dev, intel_crtc->pipe);
2778 mutex_lock(&dev->struct_mutex);
2779 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2780 mutex_unlock(&dev->struct_mutex);
2781 }
2782
2783 mutex_lock(&dev->struct_mutex);
2784 intel_update_fbc(dev);
2785 mutex_unlock(&dev->struct_mutex);
2786
2787 return 0;
2788 }
2789
2790 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2791 {
2792 struct drm_device *dev = crtc->dev;
2793 struct drm_i915_private *dev_priv = dev->dev_private;
2794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2795 int pipe = intel_crtc->pipe;
2796 u32 reg, temp;
2797
2798 /* enable normal train */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 if (IS_IVYBRIDGE(dev)) {
2802 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2803 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2804 } else {
2805 temp &= ~FDI_LINK_TRAIN_NONE;
2806 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2807 }
2808 I915_WRITE(reg, temp);
2809
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 if (HAS_PCH_CPT(dev)) {
2813 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2814 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2815 } else {
2816 temp &= ~FDI_LINK_TRAIN_NONE;
2817 temp |= FDI_LINK_TRAIN_NONE;
2818 }
2819 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2820
2821 /* wait one idle pattern time */
2822 POSTING_READ(reg);
2823 udelay(1000);
2824
2825 /* IVB wants error correction enabled */
2826 if (IS_IVYBRIDGE(dev))
2827 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2828 FDI_FE_ERRC_ENABLE);
2829 }
2830
2831 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2832 {
2833 return crtc->base.enabled && crtc->active &&
2834 crtc->config.has_pch_encoder;
2835 }
2836
2837 static void ivb_modeset_global_resources(struct drm_device *dev)
2838 {
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_crtc *pipe_B_crtc =
2841 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2842 struct intel_crtc *pipe_C_crtc =
2843 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2844 uint32_t temp;
2845
2846 /*
2847 * When everything is off disable fdi C so that we could enable fdi B
2848 * with all lanes. Note that we don't care about enabled pipes without
2849 * an enabled pch encoder.
2850 */
2851 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2852 !pipe_has_enabled_pch(pipe_C_crtc)) {
2853 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2854 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2855
2856 temp = I915_READ(SOUTH_CHICKEN1);
2857 temp &= ~FDI_BC_BIFURCATION_SELECT;
2858 DRM_DEBUG_KMS("disabling fdi C rx\n");
2859 I915_WRITE(SOUTH_CHICKEN1, temp);
2860 }
2861 }
2862
2863 /* The FDI link training functions for ILK/Ibexpeak. */
2864 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2865 {
2866 struct drm_device *dev = crtc->dev;
2867 struct drm_i915_private *dev_priv = dev->dev_private;
2868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2869 int pipe = intel_crtc->pipe;
2870 u32 reg, temp, tries;
2871
2872 /* FDI needs bits from pipe first */
2873 assert_pipe_enabled(dev_priv, pipe);
2874
2875 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2876 for train result */
2877 reg = FDI_RX_IMR(pipe);
2878 temp = I915_READ(reg);
2879 temp &= ~FDI_RX_SYMBOL_LOCK;
2880 temp &= ~FDI_RX_BIT_LOCK;
2881 I915_WRITE(reg, temp);
2882 I915_READ(reg);
2883 udelay(150);
2884
2885 /* enable CPU FDI TX and PCH FDI RX */
2886 reg = FDI_TX_CTL(pipe);
2887 temp = I915_READ(reg);
2888 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2889 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2890 temp &= ~FDI_LINK_TRAIN_NONE;
2891 temp |= FDI_LINK_TRAIN_PATTERN_1;
2892 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2893
2894 reg = FDI_RX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 temp &= ~FDI_LINK_TRAIN_NONE;
2897 temp |= FDI_LINK_TRAIN_PATTERN_1;
2898 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2899
2900 POSTING_READ(reg);
2901 udelay(150);
2902
2903 /* Ironlake workaround, enable clock pointer after FDI enable*/
2904 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2905 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2906 FDI_RX_PHASE_SYNC_POINTER_EN);
2907
2908 reg = FDI_RX_IIR(pipe);
2909 for (tries = 0; tries < 5; tries++) {
2910 temp = I915_READ(reg);
2911 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2912
2913 if ((temp & FDI_RX_BIT_LOCK)) {
2914 DRM_DEBUG_KMS("FDI train 1 done.\n");
2915 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2916 break;
2917 }
2918 }
2919 if (tries == 5)
2920 DRM_ERROR("FDI train 1 fail!\n");
2921
2922 /* Train 2 */
2923 reg = FDI_TX_CTL(pipe);
2924 temp = I915_READ(reg);
2925 temp &= ~FDI_LINK_TRAIN_NONE;
2926 temp |= FDI_LINK_TRAIN_PATTERN_2;
2927 I915_WRITE(reg, temp);
2928
2929 reg = FDI_RX_CTL(pipe);
2930 temp = I915_READ(reg);
2931 temp &= ~FDI_LINK_TRAIN_NONE;
2932 temp |= FDI_LINK_TRAIN_PATTERN_2;
2933 I915_WRITE(reg, temp);
2934
2935 POSTING_READ(reg);
2936 udelay(150);
2937
2938 reg = FDI_RX_IIR(pipe);
2939 for (tries = 0; tries < 5; tries++) {
2940 temp = I915_READ(reg);
2941 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2942
2943 if (temp & FDI_RX_SYMBOL_LOCK) {
2944 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2945 DRM_DEBUG_KMS("FDI train 2 done.\n");
2946 break;
2947 }
2948 }
2949 if (tries == 5)
2950 DRM_ERROR("FDI train 2 fail!\n");
2951
2952 DRM_DEBUG_KMS("FDI train done\n");
2953
2954 }
2955
2956 static const int snb_b_fdi_train_param[] = {
2957 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2958 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2959 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2960 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2961 };
2962
2963 /* The FDI link training functions for SNB/Cougarpoint. */
2964 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2965 {
2966 struct drm_device *dev = crtc->dev;
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2969 int pipe = intel_crtc->pipe;
2970 u32 reg, temp, i, retry;
2971
2972 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2973 for train result */
2974 reg = FDI_RX_IMR(pipe);
2975 temp = I915_READ(reg);
2976 temp &= ~FDI_RX_SYMBOL_LOCK;
2977 temp &= ~FDI_RX_BIT_LOCK;
2978 I915_WRITE(reg, temp);
2979
2980 POSTING_READ(reg);
2981 udelay(150);
2982
2983 /* enable CPU FDI TX and PCH FDI RX */
2984 reg = FDI_TX_CTL(pipe);
2985 temp = I915_READ(reg);
2986 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2987 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2988 temp &= ~FDI_LINK_TRAIN_NONE;
2989 temp |= FDI_LINK_TRAIN_PATTERN_1;
2990 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2991 /* SNB-B */
2992 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2993 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2994
2995 I915_WRITE(FDI_RX_MISC(pipe),
2996 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2997
2998 reg = FDI_RX_CTL(pipe);
2999 temp = I915_READ(reg);
3000 if (HAS_PCH_CPT(dev)) {
3001 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3002 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3003 } else {
3004 temp &= ~FDI_LINK_TRAIN_NONE;
3005 temp |= FDI_LINK_TRAIN_PATTERN_1;
3006 }
3007 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3008
3009 POSTING_READ(reg);
3010 udelay(150);
3011
3012 for (i = 0; i < 4; i++) {
3013 reg = FDI_TX_CTL(pipe);
3014 temp = I915_READ(reg);
3015 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3016 temp |= snb_b_fdi_train_param[i];
3017 I915_WRITE(reg, temp);
3018
3019 POSTING_READ(reg);
3020 udelay(500);
3021
3022 for (retry = 0; retry < 5; retry++) {
3023 reg = FDI_RX_IIR(pipe);
3024 temp = I915_READ(reg);
3025 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3026 if (temp & FDI_RX_BIT_LOCK) {
3027 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3028 DRM_DEBUG_KMS("FDI train 1 done.\n");
3029 break;
3030 }
3031 udelay(50);
3032 }
3033 if (retry < 5)
3034 break;
3035 }
3036 if (i == 4)
3037 DRM_ERROR("FDI train 1 fail!\n");
3038
3039 /* Train 2 */
3040 reg = FDI_TX_CTL(pipe);
3041 temp = I915_READ(reg);
3042 temp &= ~FDI_LINK_TRAIN_NONE;
3043 temp |= FDI_LINK_TRAIN_PATTERN_2;
3044 if (IS_GEN6(dev)) {
3045 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3046 /* SNB-B */
3047 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3048 }
3049 I915_WRITE(reg, temp);
3050
3051 reg = FDI_RX_CTL(pipe);
3052 temp = I915_READ(reg);
3053 if (HAS_PCH_CPT(dev)) {
3054 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3055 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3056 } else {
3057 temp &= ~FDI_LINK_TRAIN_NONE;
3058 temp |= FDI_LINK_TRAIN_PATTERN_2;
3059 }
3060 I915_WRITE(reg, temp);
3061
3062 POSTING_READ(reg);
3063 udelay(150);
3064
3065 for (i = 0; i < 4; i++) {
3066 reg = FDI_TX_CTL(pipe);
3067 temp = I915_READ(reg);
3068 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3069 temp |= snb_b_fdi_train_param[i];
3070 I915_WRITE(reg, temp);
3071
3072 POSTING_READ(reg);
3073 udelay(500);
3074
3075 for (retry = 0; retry < 5; retry++) {
3076 reg = FDI_RX_IIR(pipe);
3077 temp = I915_READ(reg);
3078 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3079 if (temp & FDI_RX_SYMBOL_LOCK) {
3080 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3081 DRM_DEBUG_KMS("FDI train 2 done.\n");
3082 break;
3083 }
3084 udelay(50);
3085 }
3086 if (retry < 5)
3087 break;
3088 }
3089 if (i == 4)
3090 DRM_ERROR("FDI train 2 fail!\n");
3091
3092 DRM_DEBUG_KMS("FDI train done.\n");
3093 }
3094
3095 /* Manual link training for Ivy Bridge A0 parts */
3096 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3097 {
3098 struct drm_device *dev = crtc->dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101 int pipe = intel_crtc->pipe;
3102 u32 reg, temp, i, j;
3103
3104 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3105 for train result */
3106 reg = FDI_RX_IMR(pipe);
3107 temp = I915_READ(reg);
3108 temp &= ~FDI_RX_SYMBOL_LOCK;
3109 temp &= ~FDI_RX_BIT_LOCK;
3110 I915_WRITE(reg, temp);
3111
3112 POSTING_READ(reg);
3113 udelay(150);
3114
3115 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3116 I915_READ(FDI_RX_IIR(pipe)));
3117
3118 /* Try each vswing and preemphasis setting twice before moving on */
3119 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3120 /* disable first in case we need to retry */
3121 reg = FDI_TX_CTL(pipe);
3122 temp = I915_READ(reg);
3123 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3124 temp &= ~FDI_TX_ENABLE;
3125 I915_WRITE(reg, temp);
3126
3127 reg = FDI_RX_CTL(pipe);
3128 temp = I915_READ(reg);
3129 temp &= ~FDI_LINK_TRAIN_AUTO;
3130 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3131 temp &= ~FDI_RX_ENABLE;
3132 I915_WRITE(reg, temp);
3133
3134 /* enable CPU FDI TX and PCH FDI RX */
3135 reg = FDI_TX_CTL(pipe);
3136 temp = I915_READ(reg);
3137 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3138 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3139 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3140 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3141 temp |= snb_b_fdi_train_param[j/2];
3142 temp |= FDI_COMPOSITE_SYNC;
3143 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3144
3145 I915_WRITE(FDI_RX_MISC(pipe),
3146 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3147
3148 reg = FDI_RX_CTL(pipe);
3149 temp = I915_READ(reg);
3150 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3151 temp |= FDI_COMPOSITE_SYNC;
3152 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3153
3154 POSTING_READ(reg);
3155 udelay(1); /* should be 0.5us */
3156
3157 for (i = 0; i < 4; i++) {
3158 reg = FDI_RX_IIR(pipe);
3159 temp = I915_READ(reg);
3160 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3161
3162 if (temp & FDI_RX_BIT_LOCK ||
3163 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3164 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3165 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3166 i);
3167 break;
3168 }
3169 udelay(1); /* should be 0.5us */
3170 }
3171 if (i == 4) {
3172 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3173 continue;
3174 }
3175
3176 /* Train 2 */
3177 reg = FDI_TX_CTL(pipe);
3178 temp = I915_READ(reg);
3179 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3180 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3181 I915_WRITE(reg, temp);
3182
3183 reg = FDI_RX_CTL(pipe);
3184 temp = I915_READ(reg);
3185 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3186 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3187 I915_WRITE(reg, temp);
3188
3189 POSTING_READ(reg);
3190 udelay(2); /* should be 1.5us */
3191
3192 for (i = 0; i < 4; i++) {
3193 reg = FDI_RX_IIR(pipe);
3194 temp = I915_READ(reg);
3195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3196
3197 if (temp & FDI_RX_SYMBOL_LOCK ||
3198 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3199 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3200 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3201 i);
3202 goto train_done;
3203 }
3204 udelay(2); /* should be 1.5us */
3205 }
3206 if (i == 4)
3207 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3208 }
3209
3210 train_done:
3211 DRM_DEBUG_KMS("FDI train done.\n");
3212 }
3213
3214 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3215 {
3216 struct drm_device *dev = intel_crtc->base.dev;
3217 struct drm_i915_private *dev_priv = dev->dev_private;
3218 int pipe = intel_crtc->pipe;
3219 u32 reg, temp;
3220
3221
3222 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3223 reg = FDI_RX_CTL(pipe);
3224 temp = I915_READ(reg);
3225 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3226 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3227 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3228 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3229
3230 POSTING_READ(reg);
3231 udelay(200);
3232
3233 /* Switch from Rawclk to PCDclk */
3234 temp = I915_READ(reg);
3235 I915_WRITE(reg, temp | FDI_PCDCLK);
3236
3237 POSTING_READ(reg);
3238 udelay(200);
3239
3240 /* Enable CPU FDI TX PLL, always on for Ironlake */
3241 reg = FDI_TX_CTL(pipe);
3242 temp = I915_READ(reg);
3243 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3244 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3245
3246 POSTING_READ(reg);
3247 udelay(100);
3248 }
3249 }
3250
3251 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3252 {
3253 struct drm_device *dev = intel_crtc->base.dev;
3254 struct drm_i915_private *dev_priv = dev->dev_private;
3255 int pipe = intel_crtc->pipe;
3256 u32 reg, temp;
3257
3258 /* Switch from PCDclk to Rawclk */
3259 reg = FDI_RX_CTL(pipe);
3260 temp = I915_READ(reg);
3261 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3262
3263 /* Disable CPU FDI TX PLL */
3264 reg = FDI_TX_CTL(pipe);
3265 temp = I915_READ(reg);
3266 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3267
3268 POSTING_READ(reg);
3269 udelay(100);
3270
3271 reg = FDI_RX_CTL(pipe);
3272 temp = I915_READ(reg);
3273 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3274
3275 /* Wait for the clocks to turn off. */
3276 POSTING_READ(reg);
3277 udelay(100);
3278 }
3279
3280 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3281 {
3282 struct drm_device *dev = crtc->dev;
3283 struct drm_i915_private *dev_priv = dev->dev_private;
3284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3285 int pipe = intel_crtc->pipe;
3286 u32 reg, temp;
3287
3288 /* disable CPU FDI tx and PCH FDI rx */
3289 reg = FDI_TX_CTL(pipe);
3290 temp = I915_READ(reg);
3291 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3292 POSTING_READ(reg);
3293
3294 reg = FDI_RX_CTL(pipe);
3295 temp = I915_READ(reg);
3296 temp &= ~(0x7 << 16);
3297 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3298 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3299
3300 POSTING_READ(reg);
3301 udelay(100);
3302
3303 /* Ironlake workaround, disable clock pointer after downing FDI */
3304 if (HAS_PCH_IBX(dev))
3305 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3306
3307 /* still set train pattern 1 */
3308 reg = FDI_TX_CTL(pipe);
3309 temp = I915_READ(reg);
3310 temp &= ~FDI_LINK_TRAIN_NONE;
3311 temp |= FDI_LINK_TRAIN_PATTERN_1;
3312 I915_WRITE(reg, temp);
3313
3314 reg = FDI_RX_CTL(pipe);
3315 temp = I915_READ(reg);
3316 if (HAS_PCH_CPT(dev)) {
3317 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3318 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3319 } else {
3320 temp &= ~FDI_LINK_TRAIN_NONE;
3321 temp |= FDI_LINK_TRAIN_PATTERN_1;
3322 }
3323 /* BPC in FDI rx is consistent with that in PIPECONF */
3324 temp &= ~(0x07 << 16);
3325 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3326 I915_WRITE(reg, temp);
3327
3328 POSTING_READ(reg);
3329 udelay(100);
3330 }
3331
3332 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3333 {
3334 struct intel_crtc *crtc;
3335
3336 /* Note that we don't need to be called with mode_config.lock here
3337 * as our list of CRTC objects is static for the lifetime of the
3338 * device and so cannot disappear as we iterate. Similarly, we can
3339 * happily treat the predicates as racy, atomic checks as userspace
3340 * cannot claim and pin a new fb without at least acquring the
3341 * struct_mutex and so serialising with us.
3342 */
3343 for_each_intel_crtc(dev, crtc) {
3344 if (atomic_read(&crtc->unpin_work_count) == 0)
3345 continue;
3346
3347 if (crtc->unpin_work)
3348 intel_wait_for_vblank(dev, crtc->pipe);
3349
3350 return true;
3351 }
3352
3353 return false;
3354 }
3355
3356 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3357 {
3358 struct drm_device *dev = crtc->dev;
3359 struct drm_i915_private *dev_priv = dev->dev_private;
3360
3361 if (crtc->primary->fb == NULL)
3362 return;
3363
3364 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3365
3366 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3367 !intel_crtc_has_pending_flip(crtc),
3368 60*HZ) == 0);
3369
3370 mutex_lock(&dev->struct_mutex);
3371 intel_finish_fb(crtc->primary->fb);
3372 mutex_unlock(&dev->struct_mutex);
3373 }
3374
3375 /* Program iCLKIP clock to the desired frequency */
3376 static void lpt_program_iclkip(struct drm_crtc *crtc)
3377 {
3378 struct drm_device *dev = crtc->dev;
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3381 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3382 u32 temp;
3383
3384 mutex_lock(&dev_priv->dpio_lock);
3385
3386 /* It is necessary to ungate the pixclk gate prior to programming
3387 * the divisors, and gate it back when it is done.
3388 */
3389 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3390
3391 /* Disable SSCCTL */
3392 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3393 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3394 SBI_SSCCTL_DISABLE,
3395 SBI_ICLK);
3396
3397 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3398 if (clock == 20000) {
3399 auxdiv = 1;
3400 divsel = 0x41;
3401 phaseinc = 0x20;
3402 } else {
3403 /* The iCLK virtual clock root frequency is in MHz,
3404 * but the adjusted_mode->crtc_clock in in KHz. To get the
3405 * divisors, it is necessary to divide one by another, so we
3406 * convert the virtual clock precision to KHz here for higher
3407 * precision.
3408 */
3409 u32 iclk_virtual_root_freq = 172800 * 1000;
3410 u32 iclk_pi_range = 64;
3411 u32 desired_divisor, msb_divisor_value, pi_value;
3412
3413 desired_divisor = (iclk_virtual_root_freq / clock);
3414 msb_divisor_value = desired_divisor / iclk_pi_range;
3415 pi_value = desired_divisor % iclk_pi_range;
3416
3417 auxdiv = 0;
3418 divsel = msb_divisor_value - 2;
3419 phaseinc = pi_value;
3420 }
3421
3422 /* This should not happen with any sane values */
3423 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3424 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3425 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3426 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3427
3428 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3429 clock,
3430 auxdiv,
3431 divsel,
3432 phasedir,
3433 phaseinc);
3434
3435 /* Program SSCDIVINTPHASE6 */
3436 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3437 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3438 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3439 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3440 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3441 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3442 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3443 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3444
3445 /* Program SSCAUXDIV */
3446 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3447 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3448 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3449 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3450
3451 /* Enable modulator and associated divider */
3452 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3453 temp &= ~SBI_SSCCTL_DISABLE;
3454 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3455
3456 /* Wait for initialization time */
3457 udelay(24);
3458
3459 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3460
3461 mutex_unlock(&dev_priv->dpio_lock);
3462 }
3463
3464 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3465 enum pipe pch_transcoder)
3466 {
3467 struct drm_device *dev = crtc->base.dev;
3468 struct drm_i915_private *dev_priv = dev->dev_private;
3469 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3470
3471 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3472 I915_READ(HTOTAL(cpu_transcoder)));
3473 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3474 I915_READ(HBLANK(cpu_transcoder)));
3475 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3476 I915_READ(HSYNC(cpu_transcoder)));
3477
3478 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3479 I915_READ(VTOTAL(cpu_transcoder)));
3480 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3481 I915_READ(VBLANK(cpu_transcoder)));
3482 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3483 I915_READ(VSYNC(cpu_transcoder)));
3484 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3485 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3486 }
3487
3488 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3489 {
3490 struct drm_i915_private *dev_priv = dev->dev_private;
3491 uint32_t temp;
3492
3493 temp = I915_READ(SOUTH_CHICKEN1);
3494 if (temp & FDI_BC_BIFURCATION_SELECT)
3495 return;
3496
3497 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3498 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3499
3500 temp |= FDI_BC_BIFURCATION_SELECT;
3501 DRM_DEBUG_KMS("enabling fdi C rx\n");
3502 I915_WRITE(SOUTH_CHICKEN1, temp);
3503 POSTING_READ(SOUTH_CHICKEN1);
3504 }
3505
3506 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3507 {
3508 struct drm_device *dev = intel_crtc->base.dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510
3511 switch (intel_crtc->pipe) {
3512 case PIPE_A:
3513 break;
3514 case PIPE_B:
3515 if (intel_crtc->config.fdi_lanes > 2)
3516 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3517 else
3518 cpt_enable_fdi_bc_bifurcation(dev);
3519
3520 break;
3521 case PIPE_C:
3522 cpt_enable_fdi_bc_bifurcation(dev);
3523
3524 break;
3525 default:
3526 BUG();
3527 }
3528 }
3529
3530 /*
3531 * Enable PCH resources required for PCH ports:
3532 * - PCH PLLs
3533 * - FDI training & RX/TX
3534 * - update transcoder timings
3535 * - DP transcoding bits
3536 * - transcoder
3537 */
3538 static void ironlake_pch_enable(struct drm_crtc *crtc)
3539 {
3540 struct drm_device *dev = crtc->dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3543 int pipe = intel_crtc->pipe;
3544 u32 reg, temp;
3545
3546 assert_pch_transcoder_disabled(dev_priv, pipe);
3547
3548 if (IS_IVYBRIDGE(dev))
3549 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3550
3551 /* Write the TU size bits before fdi link training, so that error
3552 * detection works. */
3553 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3554 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3555
3556 /* For PCH output, training FDI link */
3557 dev_priv->display.fdi_link_train(crtc);
3558
3559 /* We need to program the right clock selection before writing the pixel
3560 * mutliplier into the DPLL. */
3561 if (HAS_PCH_CPT(dev)) {
3562 u32 sel;
3563
3564 temp = I915_READ(PCH_DPLL_SEL);
3565 temp |= TRANS_DPLL_ENABLE(pipe);
3566 sel = TRANS_DPLLB_SEL(pipe);
3567 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3568 temp |= sel;
3569 else
3570 temp &= ~sel;
3571 I915_WRITE(PCH_DPLL_SEL, temp);
3572 }
3573
3574 /* XXX: pch pll's can be enabled any time before we enable the PCH
3575 * transcoder, and we actually should do this to not upset any PCH
3576 * transcoder that already use the clock when we share it.
3577 *
3578 * Note that enable_shared_dpll tries to do the right thing, but
3579 * get_shared_dpll unconditionally resets the pll - we need that to have
3580 * the right LVDS enable sequence. */
3581 intel_enable_shared_dpll(intel_crtc);
3582
3583 /* set transcoder timing, panel must allow it */
3584 assert_panel_unlocked(dev_priv, pipe);
3585 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3586
3587 intel_fdi_normal_train(crtc);
3588
3589 /* For PCH DP, enable TRANS_DP_CTL */
3590 if (HAS_PCH_CPT(dev) &&
3591 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3592 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3593 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3594 reg = TRANS_DP_CTL(pipe);
3595 temp = I915_READ(reg);
3596 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3597 TRANS_DP_SYNC_MASK |
3598 TRANS_DP_BPC_MASK);
3599 temp |= (TRANS_DP_OUTPUT_ENABLE |
3600 TRANS_DP_ENH_FRAMING);
3601 temp |= bpc << 9; /* same format but at 11:9 */
3602
3603 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3604 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3605 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3606 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3607
3608 switch (intel_trans_dp_port_sel(crtc)) {
3609 case PCH_DP_B:
3610 temp |= TRANS_DP_PORT_SEL_B;
3611 break;
3612 case PCH_DP_C:
3613 temp |= TRANS_DP_PORT_SEL_C;
3614 break;
3615 case PCH_DP_D:
3616 temp |= TRANS_DP_PORT_SEL_D;
3617 break;
3618 default:
3619 BUG();
3620 }
3621
3622 I915_WRITE(reg, temp);
3623 }
3624
3625 ironlake_enable_pch_transcoder(dev_priv, pipe);
3626 }
3627
3628 static void lpt_pch_enable(struct drm_crtc *crtc)
3629 {
3630 struct drm_device *dev = crtc->dev;
3631 struct drm_i915_private *dev_priv = dev->dev_private;
3632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3633 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3634
3635 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3636
3637 lpt_program_iclkip(crtc);
3638
3639 /* Set transcoder timing. */
3640 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3641
3642 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3643 }
3644
3645 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3646 {
3647 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3648
3649 if (pll == NULL)
3650 return;
3651
3652 if (pll->refcount == 0) {
3653 WARN(1, "bad %s refcount\n", pll->name);
3654 return;
3655 }
3656
3657 if (--pll->refcount == 0) {
3658 WARN_ON(pll->on);
3659 WARN_ON(pll->active);
3660 }
3661
3662 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3663 }
3664
3665 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3666 {
3667 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3668 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3669 enum intel_dpll_id i;
3670
3671 if (pll) {
3672 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3673 crtc->base.base.id, pll->name);
3674 intel_put_shared_dpll(crtc);
3675 }
3676
3677 if (HAS_PCH_IBX(dev_priv->dev)) {
3678 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3679 i = (enum intel_dpll_id) crtc->pipe;
3680 pll = &dev_priv->shared_dplls[i];
3681
3682 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3683 crtc->base.base.id, pll->name);
3684
3685 WARN_ON(pll->refcount);
3686
3687 goto found;
3688 }
3689
3690 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3691 pll = &dev_priv->shared_dplls[i];
3692
3693 /* Only want to check enabled timings first */
3694 if (pll->refcount == 0)
3695 continue;
3696
3697 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3698 sizeof(pll->hw_state)) == 0) {
3699 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3700 crtc->base.base.id,
3701 pll->name, pll->refcount, pll->active);
3702
3703 goto found;
3704 }
3705 }
3706
3707 /* Ok no matching timings, maybe there's a free one? */
3708 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3709 pll = &dev_priv->shared_dplls[i];
3710 if (pll->refcount == 0) {
3711 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3712 crtc->base.base.id, pll->name);
3713 goto found;
3714 }
3715 }
3716
3717 return NULL;
3718
3719 found:
3720 if (pll->refcount == 0)
3721 pll->hw_state = crtc->config.dpll_hw_state;
3722
3723 crtc->config.shared_dpll = i;
3724 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3725 pipe_name(crtc->pipe));
3726
3727 pll->refcount++;
3728
3729 return pll;
3730 }
3731
3732 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3733 {
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735 int dslreg = PIPEDSL(pipe);
3736 u32 temp;
3737
3738 temp = I915_READ(dslreg);
3739 udelay(500);
3740 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3741 if (wait_for(I915_READ(dslreg) != temp, 5))
3742 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3743 }
3744 }
3745
3746 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3747 {
3748 struct drm_device *dev = crtc->base.dev;
3749 struct drm_i915_private *dev_priv = dev->dev_private;
3750 int pipe = crtc->pipe;
3751
3752 if (crtc->config.pch_pfit.enabled) {
3753 /* Force use of hard-coded filter coefficients
3754 * as some pre-programmed values are broken,
3755 * e.g. x201.
3756 */
3757 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3758 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3759 PF_PIPE_SEL_IVB(pipe));
3760 else
3761 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3762 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3763 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3764 }
3765 }
3766
3767 static void intel_enable_planes(struct drm_crtc *crtc)
3768 {
3769 struct drm_device *dev = crtc->dev;
3770 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3771 struct drm_plane *plane;
3772 struct intel_plane *intel_plane;
3773
3774 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3775 intel_plane = to_intel_plane(plane);
3776 if (intel_plane->pipe == pipe)
3777 intel_plane_restore(&intel_plane->base);
3778 }
3779 }
3780
3781 static void intel_disable_planes(struct drm_crtc *crtc)
3782 {
3783 struct drm_device *dev = crtc->dev;
3784 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3785 struct drm_plane *plane;
3786 struct intel_plane *intel_plane;
3787
3788 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3789 intel_plane = to_intel_plane(plane);
3790 if (intel_plane->pipe == pipe)
3791 intel_plane_disable(&intel_plane->base);
3792 }
3793 }
3794
3795 void hsw_enable_ips(struct intel_crtc *crtc)
3796 {
3797 struct drm_device *dev = crtc->base.dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799
3800 if (!crtc->config.ips_enabled)
3801 return;
3802
3803 /* We can only enable IPS after we enable a plane and wait for a vblank */
3804 intel_wait_for_vblank(dev, crtc->pipe);
3805
3806 assert_plane_enabled(dev_priv, crtc->plane);
3807 if (IS_BROADWELL(dev)) {
3808 mutex_lock(&dev_priv->rps.hw_lock);
3809 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3810 mutex_unlock(&dev_priv->rps.hw_lock);
3811 /* Quoting Art Runyan: "its not safe to expect any particular
3812 * value in IPS_CTL bit 31 after enabling IPS through the
3813 * mailbox." Moreover, the mailbox may return a bogus state,
3814 * so we need to just enable it and continue on.
3815 */
3816 } else {
3817 I915_WRITE(IPS_CTL, IPS_ENABLE);
3818 /* The bit only becomes 1 in the next vblank, so this wait here
3819 * is essentially intel_wait_for_vblank. If we don't have this
3820 * and don't wait for vblanks until the end of crtc_enable, then
3821 * the HW state readout code will complain that the expected
3822 * IPS_CTL value is not the one we read. */
3823 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3824 DRM_ERROR("Timed out waiting for IPS enable\n");
3825 }
3826 }
3827
3828 void hsw_disable_ips(struct intel_crtc *crtc)
3829 {
3830 struct drm_device *dev = crtc->base.dev;
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832
3833 if (!crtc->config.ips_enabled)
3834 return;
3835
3836 assert_plane_enabled(dev_priv, crtc->plane);
3837 if (IS_BROADWELL(dev)) {
3838 mutex_lock(&dev_priv->rps.hw_lock);
3839 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3840 mutex_unlock(&dev_priv->rps.hw_lock);
3841 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3842 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3843 DRM_ERROR("Timed out waiting for IPS disable\n");
3844 } else {
3845 I915_WRITE(IPS_CTL, 0);
3846 POSTING_READ(IPS_CTL);
3847 }
3848
3849 /* We need to wait for a vblank before we can disable the plane. */
3850 intel_wait_for_vblank(dev, crtc->pipe);
3851 }
3852
3853 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3854 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3855 {
3856 struct drm_device *dev = crtc->dev;
3857 struct drm_i915_private *dev_priv = dev->dev_private;
3858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3859 enum pipe pipe = intel_crtc->pipe;
3860 int palreg = PALETTE(pipe);
3861 int i;
3862 bool reenable_ips = false;
3863
3864 /* The clocks have to be on to load the palette. */
3865 if (!crtc->enabled || !intel_crtc->active)
3866 return;
3867
3868 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3869 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3870 assert_dsi_pll_enabled(dev_priv);
3871 else
3872 assert_pll_enabled(dev_priv, pipe);
3873 }
3874
3875 /* use legacy palette for Ironlake */
3876 if (HAS_PCH_SPLIT(dev))
3877 palreg = LGC_PALETTE(pipe);
3878
3879 /* Workaround : Do not read or write the pipe palette/gamma data while
3880 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3881 */
3882 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3883 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3884 GAMMA_MODE_MODE_SPLIT)) {
3885 hsw_disable_ips(intel_crtc);
3886 reenable_ips = true;
3887 }
3888
3889 for (i = 0; i < 256; i++) {
3890 I915_WRITE(palreg + 4 * i,
3891 (intel_crtc->lut_r[i] << 16) |
3892 (intel_crtc->lut_g[i] << 8) |
3893 intel_crtc->lut_b[i]);
3894 }
3895
3896 if (reenable_ips)
3897 hsw_enable_ips(intel_crtc);
3898 }
3899
3900 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3901 {
3902 if (!enable && intel_crtc->overlay) {
3903 struct drm_device *dev = intel_crtc->base.dev;
3904 struct drm_i915_private *dev_priv = dev->dev_private;
3905
3906 mutex_lock(&dev->struct_mutex);
3907 dev_priv->mm.interruptible = false;
3908 (void) intel_overlay_switch_off(intel_crtc->overlay);
3909 dev_priv->mm.interruptible = true;
3910 mutex_unlock(&dev->struct_mutex);
3911 }
3912
3913 /* Let userspace switch the overlay on again. In most cases userspace
3914 * has to recompute where to put it anyway.
3915 */
3916 }
3917
3918 /**
3919 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3920 * cursor plane briefly if not already running after enabling the display
3921 * plane.
3922 * This workaround avoids occasional blank screens when self refresh is
3923 * enabled.
3924 */
3925 static void
3926 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3927 {
3928 u32 cntl = I915_READ(CURCNTR(pipe));
3929
3930 if ((cntl & CURSOR_MODE) == 0) {
3931 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3932
3933 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3934 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3935 intel_wait_for_vblank(dev_priv->dev, pipe);
3936 I915_WRITE(CURCNTR(pipe), cntl);
3937 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3938 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3939 }
3940 }
3941
3942 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3943 {
3944 struct drm_device *dev = crtc->dev;
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3947 int pipe = intel_crtc->pipe;
3948 int plane = intel_crtc->plane;
3949
3950 drm_vblank_on(dev, pipe);
3951
3952 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3953 intel_enable_planes(crtc);
3954 /* The fixup needs to happen before cursor is enabled */
3955 if (IS_G4X(dev))
3956 g4x_fixup_plane(dev_priv, pipe);
3957 intel_crtc_update_cursor(crtc, true);
3958 intel_crtc_dpms_overlay(intel_crtc, true);
3959
3960 hsw_enable_ips(intel_crtc);
3961
3962 mutex_lock(&dev->struct_mutex);
3963 intel_update_fbc(dev);
3964 mutex_unlock(&dev->struct_mutex);
3965
3966 /*
3967 * FIXME: Once we grow proper nuclear flip support out of this we need
3968 * to compute the mask of flip planes precisely. For the time being
3969 * consider this a flip from a NULL plane.
3970 */
3971 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3972 }
3973
3974 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3975 {
3976 struct drm_device *dev = crtc->dev;
3977 struct drm_i915_private *dev_priv = dev->dev_private;
3978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3979 int pipe = intel_crtc->pipe;
3980 int plane = intel_crtc->plane;
3981
3982 intel_crtc_wait_for_pending_flips(crtc);
3983
3984 if (dev_priv->fbc.plane == plane)
3985 intel_disable_fbc(dev);
3986
3987 hsw_disable_ips(intel_crtc);
3988
3989 intel_crtc_dpms_overlay(intel_crtc, false);
3990 intel_crtc_update_cursor(crtc, false);
3991 intel_disable_planes(crtc);
3992 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3993
3994 /*
3995 * FIXME: Once we grow proper nuclear flip support out of this we need
3996 * to compute the mask of flip planes precisely. For the time being
3997 * consider this a flip to a NULL plane.
3998 */
3999 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4000
4001 drm_vblank_off(dev, pipe);
4002 }
4003
4004 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4005 {
4006 struct drm_device *dev = crtc->dev;
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4009 struct intel_encoder *encoder;
4010 int pipe = intel_crtc->pipe;
4011 enum plane plane = intel_crtc->plane;
4012
4013 WARN_ON(!crtc->enabled);
4014
4015 if (intel_crtc->active)
4016 return;
4017
4018 if (intel_crtc->config.has_pch_encoder)
4019 intel_prepare_shared_dpll(intel_crtc);
4020
4021 if (intel_crtc->config.has_dp_encoder)
4022 intel_dp_set_m_n(intel_crtc);
4023
4024 intel_set_pipe_timings(intel_crtc);
4025
4026 if (intel_crtc->config.has_pch_encoder) {
4027 intel_cpu_transcoder_set_m_n(intel_crtc,
4028 &intel_crtc->config.fdi_m_n);
4029 }
4030
4031 ironlake_set_pipeconf(crtc);
4032
4033 /* Set up the display plane register */
4034 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
4035 POSTING_READ(DSPCNTR(plane));
4036
4037 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4038 crtc->x, crtc->y);
4039
4040 intel_crtc->active = true;
4041
4042 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4043 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4044
4045 for_each_encoder_on_crtc(dev, crtc, encoder)
4046 if (encoder->pre_enable)
4047 encoder->pre_enable(encoder);
4048
4049 if (intel_crtc->config.has_pch_encoder) {
4050 /* Note: FDI PLL enabling _must_ be done before we enable the
4051 * cpu pipes, hence this is separate from all the other fdi/pch
4052 * enabling. */
4053 ironlake_fdi_pll_enable(intel_crtc);
4054 } else {
4055 assert_fdi_tx_disabled(dev_priv, pipe);
4056 assert_fdi_rx_disabled(dev_priv, pipe);
4057 }
4058
4059 ironlake_pfit_enable(intel_crtc);
4060
4061 /*
4062 * On ILK+ LUT must be loaded before the pipe is running but with
4063 * clocks enabled
4064 */
4065 intel_crtc_load_lut(crtc);
4066
4067 intel_update_watermarks(crtc);
4068 intel_enable_pipe(intel_crtc);
4069
4070 if (intel_crtc->config.has_pch_encoder)
4071 ironlake_pch_enable(crtc);
4072
4073 for_each_encoder_on_crtc(dev, crtc, encoder)
4074 encoder->enable(encoder);
4075
4076 if (HAS_PCH_CPT(dev))
4077 cpt_verify_modeset(dev, intel_crtc->pipe);
4078
4079 intel_crtc_enable_planes(crtc);
4080 }
4081
4082 /* IPS only exists on ULT machines and is tied to pipe A. */
4083 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4084 {
4085 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4086 }
4087
4088 /*
4089 * This implements the workaround described in the "notes" section of the mode
4090 * set sequence documentation. When going from no pipes or single pipe to
4091 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4092 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4093 */
4094 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4095 {
4096 struct drm_device *dev = crtc->base.dev;
4097 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4098
4099 /* We want to get the other_active_crtc only if there's only 1 other
4100 * active crtc. */
4101 for_each_intel_crtc(dev, crtc_it) {
4102 if (!crtc_it->active || crtc_it == crtc)
4103 continue;
4104
4105 if (other_active_crtc)
4106 return;
4107
4108 other_active_crtc = crtc_it;
4109 }
4110 if (!other_active_crtc)
4111 return;
4112
4113 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4114 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4115 }
4116
4117 static void haswell_crtc_enable(struct drm_crtc *crtc)
4118 {
4119 struct drm_device *dev = crtc->dev;
4120 struct drm_i915_private *dev_priv = dev->dev_private;
4121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4122 struct intel_encoder *encoder;
4123 int pipe = intel_crtc->pipe;
4124 enum plane plane = intel_crtc->plane;
4125
4126 WARN_ON(!crtc->enabled);
4127
4128 if (intel_crtc->active)
4129 return;
4130
4131 if (intel_crtc->config.has_dp_encoder)
4132 intel_dp_set_m_n(intel_crtc);
4133
4134 intel_set_pipe_timings(intel_crtc);
4135
4136 if (intel_crtc->config.has_pch_encoder) {
4137 intel_cpu_transcoder_set_m_n(intel_crtc,
4138 &intel_crtc->config.fdi_m_n);
4139 }
4140
4141 haswell_set_pipeconf(crtc);
4142
4143 intel_set_pipe_csc(crtc);
4144
4145 /* Set up the display plane register */
4146 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4147 POSTING_READ(DSPCNTR(plane));
4148
4149 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4150 crtc->x, crtc->y);
4151
4152 intel_crtc->active = true;
4153
4154 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4155 if (intel_crtc->config.has_pch_encoder)
4156 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4157
4158 if (intel_crtc->config.has_pch_encoder)
4159 dev_priv->display.fdi_link_train(crtc);
4160
4161 for_each_encoder_on_crtc(dev, crtc, encoder)
4162 if (encoder->pre_enable)
4163 encoder->pre_enable(encoder);
4164
4165 intel_ddi_enable_pipe_clock(intel_crtc);
4166
4167 ironlake_pfit_enable(intel_crtc);
4168
4169 /*
4170 * On ILK+ LUT must be loaded before the pipe is running but with
4171 * clocks enabled
4172 */
4173 intel_crtc_load_lut(crtc);
4174
4175 intel_ddi_set_pipe_settings(crtc);
4176 intel_ddi_enable_transcoder_func(crtc);
4177
4178 intel_update_watermarks(crtc);
4179 intel_enable_pipe(intel_crtc);
4180
4181 if (intel_crtc->config.has_pch_encoder)
4182 lpt_pch_enable(crtc);
4183
4184 for_each_encoder_on_crtc(dev, crtc, encoder) {
4185 encoder->enable(encoder);
4186 intel_opregion_notify_encoder(encoder, true);
4187 }
4188
4189 /* If we change the relative order between pipe/planes enabling, we need
4190 * to change the workaround. */
4191 haswell_mode_set_planes_workaround(intel_crtc);
4192 intel_crtc_enable_planes(crtc);
4193 }
4194
4195 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4196 {
4197 struct drm_device *dev = crtc->base.dev;
4198 struct drm_i915_private *dev_priv = dev->dev_private;
4199 int pipe = crtc->pipe;
4200
4201 /* To avoid upsetting the power well on haswell only disable the pfit if
4202 * it's in use. The hw state code will make sure we get this right. */
4203 if (crtc->config.pch_pfit.enabled) {
4204 I915_WRITE(PF_CTL(pipe), 0);
4205 I915_WRITE(PF_WIN_POS(pipe), 0);
4206 I915_WRITE(PF_WIN_SZ(pipe), 0);
4207 }
4208 }
4209
4210 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4211 {
4212 struct drm_device *dev = crtc->dev;
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4215 struct intel_encoder *encoder;
4216 int pipe = intel_crtc->pipe;
4217 u32 reg, temp;
4218
4219 if (!intel_crtc->active)
4220 return;
4221
4222 intel_crtc_disable_planes(crtc);
4223
4224 for_each_encoder_on_crtc(dev, crtc, encoder)
4225 encoder->disable(encoder);
4226
4227 if (intel_crtc->config.has_pch_encoder)
4228 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4229
4230 intel_disable_pipe(dev_priv, pipe);
4231
4232 ironlake_pfit_disable(intel_crtc);
4233
4234 for_each_encoder_on_crtc(dev, crtc, encoder)
4235 if (encoder->post_disable)
4236 encoder->post_disable(encoder);
4237
4238 if (intel_crtc->config.has_pch_encoder) {
4239 ironlake_fdi_disable(crtc);
4240
4241 ironlake_disable_pch_transcoder(dev_priv, pipe);
4242 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4243
4244 if (HAS_PCH_CPT(dev)) {
4245 /* disable TRANS_DP_CTL */
4246 reg = TRANS_DP_CTL(pipe);
4247 temp = I915_READ(reg);
4248 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4249 TRANS_DP_PORT_SEL_MASK);
4250 temp |= TRANS_DP_PORT_SEL_NONE;
4251 I915_WRITE(reg, temp);
4252
4253 /* disable DPLL_SEL */
4254 temp = I915_READ(PCH_DPLL_SEL);
4255 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4256 I915_WRITE(PCH_DPLL_SEL, temp);
4257 }
4258
4259 /* disable PCH DPLL */
4260 intel_disable_shared_dpll(intel_crtc);
4261
4262 ironlake_fdi_pll_disable(intel_crtc);
4263 }
4264
4265 intel_crtc->active = false;
4266 intel_update_watermarks(crtc);
4267
4268 mutex_lock(&dev->struct_mutex);
4269 intel_update_fbc(dev);
4270 mutex_unlock(&dev->struct_mutex);
4271 }
4272
4273 static void haswell_crtc_disable(struct drm_crtc *crtc)
4274 {
4275 struct drm_device *dev = crtc->dev;
4276 struct drm_i915_private *dev_priv = dev->dev_private;
4277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4278 struct intel_encoder *encoder;
4279 int pipe = intel_crtc->pipe;
4280 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4281
4282 if (!intel_crtc->active)
4283 return;
4284
4285 intel_crtc_disable_planes(crtc);
4286
4287 for_each_encoder_on_crtc(dev, crtc, encoder) {
4288 intel_opregion_notify_encoder(encoder, false);
4289 encoder->disable(encoder);
4290 }
4291
4292 if (intel_crtc->config.has_pch_encoder)
4293 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4294 intel_disable_pipe(dev_priv, pipe);
4295
4296 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4297
4298 ironlake_pfit_disable(intel_crtc);
4299
4300 intel_ddi_disable_pipe_clock(intel_crtc);
4301
4302 for_each_encoder_on_crtc(dev, crtc, encoder)
4303 if (encoder->post_disable)
4304 encoder->post_disable(encoder);
4305
4306 if (intel_crtc->config.has_pch_encoder) {
4307 lpt_disable_pch_transcoder(dev_priv);
4308 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4309 intel_ddi_fdi_disable(crtc);
4310 }
4311
4312 intel_crtc->active = false;
4313 intel_update_watermarks(crtc);
4314
4315 mutex_lock(&dev->struct_mutex);
4316 intel_update_fbc(dev);
4317 mutex_unlock(&dev->struct_mutex);
4318 }
4319
4320 static void ironlake_crtc_off(struct drm_crtc *crtc)
4321 {
4322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4323 intel_put_shared_dpll(intel_crtc);
4324 }
4325
4326 static void haswell_crtc_off(struct drm_crtc *crtc)
4327 {
4328 intel_ddi_put_crtc_pll(crtc);
4329 }
4330
4331 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4332 {
4333 struct drm_device *dev = crtc->base.dev;
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4335 struct intel_crtc_config *pipe_config = &crtc->config;
4336
4337 if (!crtc->config.gmch_pfit.control)
4338 return;
4339
4340 /*
4341 * The panel fitter should only be adjusted whilst the pipe is disabled,
4342 * according to register description and PRM.
4343 */
4344 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4345 assert_pipe_disabled(dev_priv, crtc->pipe);
4346
4347 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4348 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4349
4350 /* Border color in case we don't scale up to the full screen. Black by
4351 * default, change to something else for debugging. */
4352 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4353 }
4354
4355 #define for_each_power_domain(domain, mask) \
4356 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4357 if ((1 << (domain)) & (mask))
4358
4359 enum intel_display_power_domain
4360 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4361 {
4362 struct drm_device *dev = intel_encoder->base.dev;
4363 struct intel_digital_port *intel_dig_port;
4364
4365 switch (intel_encoder->type) {
4366 case INTEL_OUTPUT_UNKNOWN:
4367 /* Only DDI platforms should ever use this output type */
4368 WARN_ON_ONCE(!HAS_DDI(dev));
4369 case INTEL_OUTPUT_DISPLAYPORT:
4370 case INTEL_OUTPUT_HDMI:
4371 case INTEL_OUTPUT_EDP:
4372 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4373 switch (intel_dig_port->port) {
4374 case PORT_A:
4375 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4376 case PORT_B:
4377 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4378 case PORT_C:
4379 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4380 case PORT_D:
4381 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4382 default:
4383 WARN_ON_ONCE(1);
4384 return POWER_DOMAIN_PORT_OTHER;
4385 }
4386 case INTEL_OUTPUT_ANALOG:
4387 return POWER_DOMAIN_PORT_CRT;
4388 case INTEL_OUTPUT_DSI:
4389 return POWER_DOMAIN_PORT_DSI;
4390 default:
4391 return POWER_DOMAIN_PORT_OTHER;
4392 }
4393 }
4394
4395 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4396 {
4397 struct drm_device *dev = crtc->dev;
4398 struct intel_encoder *intel_encoder;
4399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4400 enum pipe pipe = intel_crtc->pipe;
4401 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4402 unsigned long mask;
4403 enum transcoder transcoder;
4404
4405 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4406
4407 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4408 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4409 if (pfit_enabled)
4410 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4411
4412 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4413 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4414
4415 return mask;
4416 }
4417
4418 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4419 bool enable)
4420 {
4421 if (dev_priv->power_domains.init_power_on == enable)
4422 return;
4423
4424 if (enable)
4425 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4426 else
4427 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4428
4429 dev_priv->power_domains.init_power_on = enable;
4430 }
4431
4432 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4433 {
4434 struct drm_i915_private *dev_priv = dev->dev_private;
4435 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4436 struct intel_crtc *crtc;
4437
4438 /*
4439 * First get all needed power domains, then put all unneeded, to avoid
4440 * any unnecessary toggling of the power wells.
4441 */
4442 for_each_intel_crtc(dev, crtc) {
4443 enum intel_display_power_domain domain;
4444
4445 if (!crtc->base.enabled)
4446 continue;
4447
4448 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4449
4450 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4451 intel_display_power_get(dev_priv, domain);
4452 }
4453
4454 for_each_intel_crtc(dev, crtc) {
4455 enum intel_display_power_domain domain;
4456
4457 for_each_power_domain(domain, crtc->enabled_power_domains)
4458 intel_display_power_put(dev_priv, domain);
4459
4460 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4461 }
4462
4463 intel_display_set_init_power(dev_priv, false);
4464 }
4465
4466 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4467 {
4468 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4469
4470 /* Obtain SKU information */
4471 mutex_lock(&dev_priv->dpio_lock);
4472 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4473 CCK_FUSE_HPLL_FREQ_MASK;
4474 mutex_unlock(&dev_priv->dpio_lock);
4475
4476 return vco_freq[hpll_freq];
4477 }
4478
4479 /* Adjust CDclk dividers to allow high res or save power if possible */
4480 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4481 {
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483 u32 val, cmd;
4484
4485 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4486 dev_priv->vlv_cdclk_freq = cdclk;
4487
4488 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4489 cmd = 2;
4490 else if (cdclk == 266)
4491 cmd = 1;
4492 else
4493 cmd = 0;
4494
4495 mutex_lock(&dev_priv->rps.hw_lock);
4496 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4497 val &= ~DSPFREQGUAR_MASK;
4498 val |= (cmd << DSPFREQGUAR_SHIFT);
4499 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4500 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4501 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4502 50)) {
4503 DRM_ERROR("timed out waiting for CDclk change\n");
4504 }
4505 mutex_unlock(&dev_priv->rps.hw_lock);
4506
4507 if (cdclk == 400) {
4508 u32 divider, vco;
4509
4510 vco = valleyview_get_vco(dev_priv);
4511 divider = ((vco << 1) / cdclk) - 1;
4512
4513 mutex_lock(&dev_priv->dpio_lock);
4514 /* adjust cdclk divider */
4515 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4516 val &= ~0xf;
4517 val |= divider;
4518 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4519 mutex_unlock(&dev_priv->dpio_lock);
4520 }
4521
4522 mutex_lock(&dev_priv->dpio_lock);
4523 /* adjust self-refresh exit latency value */
4524 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4525 val &= ~0x7f;
4526
4527 /*
4528 * For high bandwidth configs, we set a higher latency in the bunit
4529 * so that the core display fetch happens in time to avoid underruns.
4530 */
4531 if (cdclk == 400)
4532 val |= 4500 / 250; /* 4.5 usec */
4533 else
4534 val |= 3000 / 250; /* 3.0 usec */
4535 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4536 mutex_unlock(&dev_priv->dpio_lock);
4537
4538 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4539 intel_i2c_reset(dev);
4540 }
4541
4542 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4543 {
4544 int cur_cdclk, vco;
4545 int divider;
4546
4547 vco = valleyview_get_vco(dev_priv);
4548
4549 mutex_lock(&dev_priv->dpio_lock);
4550 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4551 mutex_unlock(&dev_priv->dpio_lock);
4552
4553 divider &= 0xf;
4554
4555 cur_cdclk = (vco << 1) / (divider + 1);
4556
4557 return cur_cdclk;
4558 }
4559
4560 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4561 int max_pixclk)
4562 {
4563 /*
4564 * Really only a few cases to deal with, as only 4 CDclks are supported:
4565 * 200MHz
4566 * 267MHz
4567 * 320MHz
4568 * 400MHz
4569 * So we check to see whether we're above 90% of the lower bin and
4570 * adjust if needed.
4571 */
4572 if (max_pixclk > 288000) {
4573 return 400;
4574 } else if (max_pixclk > 240000) {
4575 return 320;
4576 } else
4577 return 266;
4578 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4579 }
4580
4581 /* compute the max pixel clock for new configuration */
4582 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4583 {
4584 struct drm_device *dev = dev_priv->dev;
4585 struct intel_crtc *intel_crtc;
4586 int max_pixclk = 0;
4587
4588 for_each_intel_crtc(dev, intel_crtc) {
4589 if (intel_crtc->new_enabled)
4590 max_pixclk = max(max_pixclk,
4591 intel_crtc->new_config->adjusted_mode.crtc_clock);
4592 }
4593
4594 return max_pixclk;
4595 }
4596
4597 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4598 unsigned *prepare_pipes)
4599 {
4600 struct drm_i915_private *dev_priv = dev->dev_private;
4601 struct intel_crtc *intel_crtc;
4602 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4603
4604 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4605 dev_priv->vlv_cdclk_freq)
4606 return;
4607
4608 /* disable/enable all currently active pipes while we change cdclk */
4609 for_each_intel_crtc(dev, intel_crtc)
4610 if (intel_crtc->base.enabled)
4611 *prepare_pipes |= (1 << intel_crtc->pipe);
4612 }
4613
4614 static void valleyview_modeset_global_resources(struct drm_device *dev)
4615 {
4616 struct drm_i915_private *dev_priv = dev->dev_private;
4617 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4618 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4619
4620 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4621 valleyview_set_cdclk(dev, req_cdclk);
4622 modeset_update_crtc_power_domains(dev);
4623 }
4624
4625 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4626 {
4627 struct drm_device *dev = crtc->dev;
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4630 struct intel_encoder *encoder;
4631 int pipe = intel_crtc->pipe;
4632 int plane = intel_crtc->plane;
4633 bool is_dsi;
4634 u32 dspcntr;
4635
4636 WARN_ON(!crtc->enabled);
4637
4638 if (intel_crtc->active)
4639 return;
4640
4641 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4642
4643 if (!is_dsi && !IS_CHERRYVIEW(dev))
4644 vlv_prepare_pll(intel_crtc);
4645
4646 /* Set up the display plane register */
4647 dspcntr = DISPPLANE_GAMMA_ENABLE;
4648
4649 if (intel_crtc->config.has_dp_encoder)
4650 intel_dp_set_m_n(intel_crtc);
4651
4652 intel_set_pipe_timings(intel_crtc);
4653
4654 /* pipesrc and dspsize control the size that is scaled from,
4655 * which should always be the user's requested size.
4656 */
4657 I915_WRITE(DSPSIZE(plane),
4658 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4659 (intel_crtc->config.pipe_src_w - 1));
4660 I915_WRITE(DSPPOS(plane), 0);
4661
4662 i9xx_set_pipeconf(intel_crtc);
4663
4664 I915_WRITE(DSPCNTR(plane), dspcntr);
4665 POSTING_READ(DSPCNTR(plane));
4666
4667 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4668 crtc->x, crtc->y);
4669
4670 intel_crtc->active = true;
4671
4672 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4673
4674 for_each_encoder_on_crtc(dev, crtc, encoder)
4675 if (encoder->pre_pll_enable)
4676 encoder->pre_pll_enable(encoder);
4677
4678 if (!is_dsi) {
4679 if (IS_CHERRYVIEW(dev))
4680 chv_enable_pll(intel_crtc);
4681 else
4682 vlv_enable_pll(intel_crtc);
4683 }
4684
4685 for_each_encoder_on_crtc(dev, crtc, encoder)
4686 if (encoder->pre_enable)
4687 encoder->pre_enable(encoder);
4688
4689 i9xx_pfit_enable(intel_crtc);
4690
4691 intel_crtc_load_lut(crtc);
4692
4693 intel_update_watermarks(crtc);
4694 intel_enable_pipe(intel_crtc);
4695
4696 for_each_encoder_on_crtc(dev, crtc, encoder)
4697 encoder->enable(encoder);
4698
4699 intel_crtc_enable_planes(crtc);
4700
4701 /* Underruns don't raise interrupts, so check manually. */
4702 i9xx_check_fifo_underruns(dev);
4703 }
4704
4705 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4706 {
4707 struct drm_device *dev = crtc->base.dev;
4708 struct drm_i915_private *dev_priv = dev->dev_private;
4709
4710 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4711 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4712 }
4713
4714 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4715 {
4716 struct drm_device *dev = crtc->dev;
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719 struct intel_encoder *encoder;
4720 int pipe = intel_crtc->pipe;
4721 int plane = intel_crtc->plane;
4722 u32 dspcntr;
4723
4724 WARN_ON(!crtc->enabled);
4725
4726 if (intel_crtc->active)
4727 return;
4728
4729 i9xx_set_pll_dividers(intel_crtc);
4730
4731 /* Set up the display plane register */
4732 dspcntr = DISPPLANE_GAMMA_ENABLE;
4733
4734 if (pipe == 0)
4735 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4736 else
4737 dspcntr |= DISPPLANE_SEL_PIPE_B;
4738
4739 if (intel_crtc->config.has_dp_encoder)
4740 intel_dp_set_m_n(intel_crtc);
4741
4742 intel_set_pipe_timings(intel_crtc);
4743
4744 /* pipesrc and dspsize control the size that is scaled from,
4745 * which should always be the user's requested size.
4746 */
4747 I915_WRITE(DSPSIZE(plane),
4748 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4749 (intel_crtc->config.pipe_src_w - 1));
4750 I915_WRITE(DSPPOS(plane), 0);
4751
4752 i9xx_set_pipeconf(intel_crtc);
4753
4754 I915_WRITE(DSPCNTR(plane), dspcntr);
4755 POSTING_READ(DSPCNTR(plane));
4756
4757 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4758 crtc->x, crtc->y);
4759
4760 intel_crtc->active = true;
4761
4762 if (!IS_GEN2(dev))
4763 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4764
4765 for_each_encoder_on_crtc(dev, crtc, encoder)
4766 if (encoder->pre_enable)
4767 encoder->pre_enable(encoder);
4768
4769 i9xx_enable_pll(intel_crtc);
4770
4771 i9xx_pfit_enable(intel_crtc);
4772
4773 intel_crtc_load_lut(crtc);
4774
4775 intel_update_watermarks(crtc);
4776 intel_enable_pipe(intel_crtc);
4777
4778 for_each_encoder_on_crtc(dev, crtc, encoder)
4779 encoder->enable(encoder);
4780
4781 intel_crtc_enable_planes(crtc);
4782
4783 /*
4784 * Gen2 reports pipe underruns whenever all planes are disabled.
4785 * So don't enable underrun reporting before at least some planes
4786 * are enabled.
4787 * FIXME: Need to fix the logic to work when we turn off all planes
4788 * but leave the pipe running.
4789 */
4790 if (IS_GEN2(dev))
4791 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4792
4793 /* Underruns don't raise interrupts, so check manually. */
4794 i9xx_check_fifo_underruns(dev);
4795 }
4796
4797 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4798 {
4799 struct drm_device *dev = crtc->base.dev;
4800 struct drm_i915_private *dev_priv = dev->dev_private;
4801
4802 if (!crtc->config.gmch_pfit.control)
4803 return;
4804
4805 assert_pipe_disabled(dev_priv, crtc->pipe);
4806
4807 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4808 I915_READ(PFIT_CONTROL));
4809 I915_WRITE(PFIT_CONTROL, 0);
4810 }
4811
4812 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4813 {
4814 struct drm_device *dev = crtc->dev;
4815 struct drm_i915_private *dev_priv = dev->dev_private;
4816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4817 struct intel_encoder *encoder;
4818 int pipe = intel_crtc->pipe;
4819
4820 if (!intel_crtc->active)
4821 return;
4822
4823 /*
4824 * Gen2 reports pipe underruns whenever all planes are disabled.
4825 * So diasble underrun reporting before all the planes get disabled.
4826 * FIXME: Need to fix the logic to work when we turn off all planes
4827 * but leave the pipe running.
4828 */
4829 if (IS_GEN2(dev))
4830 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4831
4832 intel_crtc_disable_planes(crtc);
4833
4834 for_each_encoder_on_crtc(dev, crtc, encoder)
4835 encoder->disable(encoder);
4836
4837 /*
4838 * On gen2 planes are double buffered but the pipe isn't, so we must
4839 * wait for planes to fully turn off before disabling the pipe.
4840 */
4841 if (IS_GEN2(dev))
4842 intel_wait_for_vblank(dev, pipe);
4843
4844 intel_disable_pipe(dev_priv, pipe);
4845
4846 i9xx_pfit_disable(intel_crtc);
4847
4848 for_each_encoder_on_crtc(dev, crtc, encoder)
4849 if (encoder->post_disable)
4850 encoder->post_disable(encoder);
4851
4852 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4853 if (IS_CHERRYVIEW(dev))
4854 chv_disable_pll(dev_priv, pipe);
4855 else if (IS_VALLEYVIEW(dev))
4856 vlv_disable_pll(dev_priv, pipe);
4857 else
4858 i9xx_disable_pll(dev_priv, pipe);
4859 }
4860
4861 if (!IS_GEN2(dev))
4862 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4863
4864 intel_crtc->active = false;
4865 intel_update_watermarks(crtc);
4866
4867 mutex_lock(&dev->struct_mutex);
4868 intel_update_fbc(dev);
4869 mutex_unlock(&dev->struct_mutex);
4870 }
4871
4872 static void i9xx_crtc_off(struct drm_crtc *crtc)
4873 {
4874 }
4875
4876 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4877 bool enabled)
4878 {
4879 struct drm_device *dev = crtc->dev;
4880 struct drm_i915_master_private *master_priv;
4881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4882 int pipe = intel_crtc->pipe;
4883
4884 if (!dev->primary->master)
4885 return;
4886
4887 master_priv = dev->primary->master->driver_priv;
4888 if (!master_priv->sarea_priv)
4889 return;
4890
4891 switch (pipe) {
4892 case 0:
4893 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4894 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4895 break;
4896 case 1:
4897 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4898 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4899 break;
4900 default:
4901 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4902 break;
4903 }
4904 }
4905
4906 /**
4907 * Sets the power management mode of the pipe and plane.
4908 */
4909 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4910 {
4911 struct drm_device *dev = crtc->dev;
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4914 struct intel_encoder *intel_encoder;
4915 enum intel_display_power_domain domain;
4916 unsigned long domains;
4917 bool enable = false;
4918
4919 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4920 enable |= intel_encoder->connectors_active;
4921
4922 if (enable) {
4923 if (!intel_crtc->active) {
4924 /*
4925 * FIXME: DDI plls and relevant code isn't converted
4926 * yet, so do runtime PM for DPMS only for all other
4927 * platforms for now.
4928 */
4929 if (!HAS_DDI(dev)) {
4930 domains = get_crtc_power_domains(crtc);
4931 for_each_power_domain(domain, domains)
4932 intel_display_power_get(dev_priv, domain);
4933 intel_crtc->enabled_power_domains = domains;
4934 }
4935
4936 dev_priv->display.crtc_enable(crtc);
4937 }
4938 } else {
4939 if (intel_crtc->active) {
4940 dev_priv->display.crtc_disable(crtc);
4941
4942 if (!HAS_DDI(dev)) {
4943 domains = intel_crtc->enabled_power_domains;
4944 for_each_power_domain(domain, domains)
4945 intel_display_power_put(dev_priv, domain);
4946 intel_crtc->enabled_power_domains = 0;
4947 }
4948 }
4949 }
4950
4951 intel_crtc_update_sarea(crtc, enable);
4952 }
4953
4954 static void intel_crtc_disable(struct drm_crtc *crtc)
4955 {
4956 struct drm_device *dev = crtc->dev;
4957 struct drm_connector *connector;
4958 struct drm_i915_private *dev_priv = dev->dev_private;
4959 struct drm_i915_gem_object *old_obj;
4960 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4961
4962 /* crtc should still be enabled when we disable it. */
4963 WARN_ON(!crtc->enabled);
4964
4965 dev_priv->display.crtc_disable(crtc);
4966 intel_crtc_update_sarea(crtc, false);
4967 dev_priv->display.off(crtc);
4968
4969 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4970 assert_cursor_disabled(dev_priv, pipe);
4971 assert_pipe_disabled(dev->dev_private, pipe);
4972
4973 if (crtc->primary->fb) {
4974 old_obj = to_intel_framebuffer(crtc->primary->fb)->obj;
4975 mutex_lock(&dev->struct_mutex);
4976 intel_unpin_fb_obj(old_obj);
4977 i915_gem_track_fb(old_obj, NULL,
4978 INTEL_FRONTBUFFER_PRIMARY(pipe));
4979 mutex_unlock(&dev->struct_mutex);
4980 crtc->primary->fb = NULL;
4981 }
4982
4983 /* Update computed state. */
4984 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4985 if (!connector->encoder || !connector->encoder->crtc)
4986 continue;
4987
4988 if (connector->encoder->crtc != crtc)
4989 continue;
4990
4991 connector->dpms = DRM_MODE_DPMS_OFF;
4992 to_intel_encoder(connector->encoder)->connectors_active = false;
4993 }
4994 }
4995
4996 void intel_encoder_destroy(struct drm_encoder *encoder)
4997 {
4998 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4999
5000 drm_encoder_cleanup(encoder);
5001 kfree(intel_encoder);
5002 }
5003
5004 /* Simple dpms helper for encoders with just one connector, no cloning and only
5005 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5006 * state of the entire output pipe. */
5007 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5008 {
5009 if (mode == DRM_MODE_DPMS_ON) {
5010 encoder->connectors_active = true;
5011
5012 intel_crtc_update_dpms(encoder->base.crtc);
5013 } else {
5014 encoder->connectors_active = false;
5015
5016 intel_crtc_update_dpms(encoder->base.crtc);
5017 }
5018 }
5019
5020 /* Cross check the actual hw state with our own modeset state tracking (and it's
5021 * internal consistency). */
5022 static void intel_connector_check_state(struct intel_connector *connector)
5023 {
5024 if (connector->get_hw_state(connector)) {
5025 struct intel_encoder *encoder = connector->encoder;
5026 struct drm_crtc *crtc;
5027 bool encoder_enabled;
5028 enum pipe pipe;
5029
5030 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5031 connector->base.base.id,
5032 connector->base.name);
5033
5034 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5035 "wrong connector dpms state\n");
5036 WARN(connector->base.encoder != &encoder->base,
5037 "active connector not linked to encoder\n");
5038 WARN(!encoder->connectors_active,
5039 "encoder->connectors_active not set\n");
5040
5041 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5042 WARN(!encoder_enabled, "encoder not enabled\n");
5043 if (WARN_ON(!encoder->base.crtc))
5044 return;
5045
5046 crtc = encoder->base.crtc;
5047
5048 WARN(!crtc->enabled, "crtc not enabled\n");
5049 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5050 WARN(pipe != to_intel_crtc(crtc)->pipe,
5051 "encoder active on the wrong pipe\n");
5052 }
5053 }
5054
5055 /* Even simpler default implementation, if there's really no special case to
5056 * consider. */
5057 void intel_connector_dpms(struct drm_connector *connector, int mode)
5058 {
5059 /* All the simple cases only support two dpms states. */
5060 if (mode != DRM_MODE_DPMS_ON)
5061 mode = DRM_MODE_DPMS_OFF;
5062
5063 if (mode == connector->dpms)
5064 return;
5065
5066 connector->dpms = mode;
5067
5068 /* Only need to change hw state when actually enabled */
5069 if (connector->encoder)
5070 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5071
5072 intel_modeset_check_state(connector->dev);
5073 }
5074
5075 /* Simple connector->get_hw_state implementation for encoders that support only
5076 * one connector and no cloning and hence the encoder state determines the state
5077 * of the connector. */
5078 bool intel_connector_get_hw_state(struct intel_connector *connector)
5079 {
5080 enum pipe pipe = 0;
5081 struct intel_encoder *encoder = connector->encoder;
5082
5083 return encoder->get_hw_state(encoder, &pipe);
5084 }
5085
5086 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5087 struct intel_crtc_config *pipe_config)
5088 {
5089 struct drm_i915_private *dev_priv = dev->dev_private;
5090 struct intel_crtc *pipe_B_crtc =
5091 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5092
5093 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5094 pipe_name(pipe), pipe_config->fdi_lanes);
5095 if (pipe_config->fdi_lanes > 4) {
5096 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5097 pipe_name(pipe), pipe_config->fdi_lanes);
5098 return false;
5099 }
5100
5101 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5102 if (pipe_config->fdi_lanes > 2) {
5103 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5104 pipe_config->fdi_lanes);
5105 return false;
5106 } else {
5107 return true;
5108 }
5109 }
5110
5111 if (INTEL_INFO(dev)->num_pipes == 2)
5112 return true;
5113
5114 /* Ivybridge 3 pipe is really complicated */
5115 switch (pipe) {
5116 case PIPE_A:
5117 return true;
5118 case PIPE_B:
5119 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5120 pipe_config->fdi_lanes > 2) {
5121 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5122 pipe_name(pipe), pipe_config->fdi_lanes);
5123 return false;
5124 }
5125 return true;
5126 case PIPE_C:
5127 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5128 pipe_B_crtc->config.fdi_lanes <= 2) {
5129 if (pipe_config->fdi_lanes > 2) {
5130 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5131 pipe_name(pipe), pipe_config->fdi_lanes);
5132 return false;
5133 }
5134 } else {
5135 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5136 return false;
5137 }
5138 return true;
5139 default:
5140 BUG();
5141 }
5142 }
5143
5144 #define RETRY 1
5145 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5146 struct intel_crtc_config *pipe_config)
5147 {
5148 struct drm_device *dev = intel_crtc->base.dev;
5149 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5150 int lane, link_bw, fdi_dotclock;
5151 bool setup_ok, needs_recompute = false;
5152
5153 retry:
5154 /* FDI is a binary signal running at ~2.7GHz, encoding
5155 * each output octet as 10 bits. The actual frequency
5156 * is stored as a divider into a 100MHz clock, and the
5157 * mode pixel clock is stored in units of 1KHz.
5158 * Hence the bw of each lane in terms of the mode signal
5159 * is:
5160 */
5161 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5162
5163 fdi_dotclock = adjusted_mode->crtc_clock;
5164
5165 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5166 pipe_config->pipe_bpp);
5167
5168 pipe_config->fdi_lanes = lane;
5169
5170 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5171 link_bw, &pipe_config->fdi_m_n);
5172
5173 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5174 intel_crtc->pipe, pipe_config);
5175 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5176 pipe_config->pipe_bpp -= 2*3;
5177 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5178 pipe_config->pipe_bpp);
5179 needs_recompute = true;
5180 pipe_config->bw_constrained = true;
5181
5182 goto retry;
5183 }
5184
5185 if (needs_recompute)
5186 return RETRY;
5187
5188 return setup_ok ? 0 : -EINVAL;
5189 }
5190
5191 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5192 struct intel_crtc_config *pipe_config)
5193 {
5194 pipe_config->ips_enabled = i915.enable_ips &&
5195 hsw_crtc_supports_ips(crtc) &&
5196 pipe_config->pipe_bpp <= 24;
5197 }
5198
5199 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5200 struct intel_crtc_config *pipe_config)
5201 {
5202 struct drm_device *dev = crtc->base.dev;
5203 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5204
5205 /* FIXME should check pixel clock limits on all platforms */
5206 if (INTEL_INFO(dev)->gen < 4) {
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5208 int clock_limit =
5209 dev_priv->display.get_display_clock_speed(dev);
5210
5211 /*
5212 * Enable pixel doubling when the dot clock
5213 * is > 90% of the (display) core speed.
5214 *
5215 * GDG double wide on either pipe,
5216 * otherwise pipe A only.
5217 */
5218 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5219 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5220 clock_limit *= 2;
5221 pipe_config->double_wide = true;
5222 }
5223
5224 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5225 return -EINVAL;
5226 }
5227
5228 /*
5229 * Pipe horizontal size must be even in:
5230 * - DVO ganged mode
5231 * - LVDS dual channel mode
5232 * - Double wide pipe
5233 */
5234 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5235 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5236 pipe_config->pipe_src_w &= ~1;
5237
5238 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5239 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5240 */
5241 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5242 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5243 return -EINVAL;
5244
5245 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5246 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5247 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5248 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5249 * for lvds. */
5250 pipe_config->pipe_bpp = 8*3;
5251 }
5252
5253 if (HAS_IPS(dev))
5254 hsw_compute_ips_config(crtc, pipe_config);
5255
5256 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5257 * clock survives for now. */
5258 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5259 pipe_config->shared_dpll = crtc->config.shared_dpll;
5260
5261 if (pipe_config->has_pch_encoder)
5262 return ironlake_fdi_compute_config(crtc, pipe_config);
5263
5264 return 0;
5265 }
5266
5267 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5268 {
5269 return 400000; /* FIXME */
5270 }
5271
5272 static int i945_get_display_clock_speed(struct drm_device *dev)
5273 {
5274 return 400000;
5275 }
5276
5277 static int i915_get_display_clock_speed(struct drm_device *dev)
5278 {
5279 return 333000;
5280 }
5281
5282 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5283 {
5284 return 200000;
5285 }
5286
5287 static int pnv_get_display_clock_speed(struct drm_device *dev)
5288 {
5289 u16 gcfgc = 0;
5290
5291 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5292
5293 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5294 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5295 return 267000;
5296 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5297 return 333000;
5298 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5299 return 444000;
5300 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5301 return 200000;
5302 default:
5303 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5304 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5305 return 133000;
5306 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5307 return 167000;
5308 }
5309 }
5310
5311 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5312 {
5313 u16 gcfgc = 0;
5314
5315 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5316
5317 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5318 return 133000;
5319 else {
5320 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5321 case GC_DISPLAY_CLOCK_333_MHZ:
5322 return 333000;
5323 default:
5324 case GC_DISPLAY_CLOCK_190_200_MHZ:
5325 return 190000;
5326 }
5327 }
5328 }
5329
5330 static int i865_get_display_clock_speed(struct drm_device *dev)
5331 {
5332 return 266000;
5333 }
5334
5335 static int i855_get_display_clock_speed(struct drm_device *dev)
5336 {
5337 u16 hpllcc = 0;
5338 /* Assume that the hardware is in the high speed state. This
5339 * should be the default.
5340 */
5341 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5342 case GC_CLOCK_133_200:
5343 case GC_CLOCK_100_200:
5344 return 200000;
5345 case GC_CLOCK_166_250:
5346 return 250000;
5347 case GC_CLOCK_100_133:
5348 return 133000;
5349 }
5350
5351 /* Shouldn't happen */
5352 return 0;
5353 }
5354
5355 static int i830_get_display_clock_speed(struct drm_device *dev)
5356 {
5357 return 133000;
5358 }
5359
5360 static void
5361 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5362 {
5363 while (*num > DATA_LINK_M_N_MASK ||
5364 *den > DATA_LINK_M_N_MASK) {
5365 *num >>= 1;
5366 *den >>= 1;
5367 }
5368 }
5369
5370 static void compute_m_n(unsigned int m, unsigned int n,
5371 uint32_t *ret_m, uint32_t *ret_n)
5372 {
5373 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5374 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5375 intel_reduce_m_n_ratio(ret_m, ret_n);
5376 }
5377
5378 void
5379 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5380 int pixel_clock, int link_clock,
5381 struct intel_link_m_n *m_n)
5382 {
5383 m_n->tu = 64;
5384
5385 compute_m_n(bits_per_pixel * pixel_clock,
5386 link_clock * nlanes * 8,
5387 &m_n->gmch_m, &m_n->gmch_n);
5388
5389 compute_m_n(pixel_clock, link_clock,
5390 &m_n->link_m, &m_n->link_n);
5391 }
5392
5393 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5394 {
5395 if (i915.panel_use_ssc >= 0)
5396 return i915.panel_use_ssc != 0;
5397 return dev_priv->vbt.lvds_use_ssc
5398 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5399 }
5400
5401 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5402 {
5403 struct drm_device *dev = crtc->dev;
5404 struct drm_i915_private *dev_priv = dev->dev_private;
5405 int refclk;
5406
5407 if (IS_VALLEYVIEW(dev)) {
5408 refclk = 100000;
5409 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5410 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5411 refclk = dev_priv->vbt.lvds_ssc_freq;
5412 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5413 } else if (!IS_GEN2(dev)) {
5414 refclk = 96000;
5415 } else {
5416 refclk = 48000;
5417 }
5418
5419 return refclk;
5420 }
5421
5422 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5423 {
5424 return (1 << dpll->n) << 16 | dpll->m2;
5425 }
5426
5427 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5428 {
5429 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5430 }
5431
5432 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5433 intel_clock_t *reduced_clock)
5434 {
5435 struct drm_device *dev = crtc->base.dev;
5436 u32 fp, fp2 = 0;
5437
5438 if (IS_PINEVIEW(dev)) {
5439 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5440 if (reduced_clock)
5441 fp2 = pnv_dpll_compute_fp(reduced_clock);
5442 } else {
5443 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5444 if (reduced_clock)
5445 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5446 }
5447
5448 crtc->config.dpll_hw_state.fp0 = fp;
5449
5450 crtc->lowfreq_avail = false;
5451 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5452 reduced_clock && i915.powersave) {
5453 crtc->config.dpll_hw_state.fp1 = fp2;
5454 crtc->lowfreq_avail = true;
5455 } else {
5456 crtc->config.dpll_hw_state.fp1 = fp;
5457 }
5458 }
5459
5460 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5461 pipe)
5462 {
5463 u32 reg_val;
5464
5465 /*
5466 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5467 * and set it to a reasonable value instead.
5468 */
5469 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5470 reg_val &= 0xffffff00;
5471 reg_val |= 0x00000030;
5472 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5473
5474 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5475 reg_val &= 0x8cffffff;
5476 reg_val = 0x8c000000;
5477 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5478
5479 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5480 reg_val &= 0xffffff00;
5481 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5482
5483 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5484 reg_val &= 0x00ffffff;
5485 reg_val |= 0xb0000000;
5486 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5487 }
5488
5489 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5490 struct intel_link_m_n *m_n)
5491 {
5492 struct drm_device *dev = crtc->base.dev;
5493 struct drm_i915_private *dev_priv = dev->dev_private;
5494 int pipe = crtc->pipe;
5495
5496 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5497 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5498 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5499 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5500 }
5501
5502 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5503 struct intel_link_m_n *m_n)
5504 {
5505 struct drm_device *dev = crtc->base.dev;
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507 int pipe = crtc->pipe;
5508 enum transcoder transcoder = crtc->config.cpu_transcoder;
5509
5510 if (INTEL_INFO(dev)->gen >= 5) {
5511 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5512 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5513 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5514 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5515 } else {
5516 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5517 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5518 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5519 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5520 }
5521 }
5522
5523 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5524 {
5525 if (crtc->config.has_pch_encoder)
5526 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5527 else
5528 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5529 }
5530
5531 static void vlv_update_pll(struct intel_crtc *crtc)
5532 {
5533 u32 dpll, dpll_md;
5534
5535 /*
5536 * Enable DPIO clock input. We should never disable the reference
5537 * clock for pipe B, since VGA hotplug / manual detection depends
5538 * on it.
5539 */
5540 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5541 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5542 /* We should never disable this, set it here for state tracking */
5543 if (crtc->pipe == PIPE_B)
5544 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5545 dpll |= DPLL_VCO_ENABLE;
5546 crtc->config.dpll_hw_state.dpll = dpll;
5547
5548 dpll_md = (crtc->config.pixel_multiplier - 1)
5549 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5550 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5551 }
5552
5553 static void vlv_prepare_pll(struct intel_crtc *crtc)
5554 {
5555 struct drm_device *dev = crtc->base.dev;
5556 struct drm_i915_private *dev_priv = dev->dev_private;
5557 int pipe = crtc->pipe;
5558 u32 mdiv;
5559 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5560 u32 coreclk, reg_val;
5561
5562 mutex_lock(&dev_priv->dpio_lock);
5563
5564 bestn = crtc->config.dpll.n;
5565 bestm1 = crtc->config.dpll.m1;
5566 bestm2 = crtc->config.dpll.m2;
5567 bestp1 = crtc->config.dpll.p1;
5568 bestp2 = crtc->config.dpll.p2;
5569
5570 /* See eDP HDMI DPIO driver vbios notes doc */
5571
5572 /* PLL B needs special handling */
5573 if (pipe == PIPE_B)
5574 vlv_pllb_recal_opamp(dev_priv, pipe);
5575
5576 /* Set up Tx target for periodic Rcomp update */
5577 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5578
5579 /* Disable target IRef on PLL */
5580 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5581 reg_val &= 0x00ffffff;
5582 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5583
5584 /* Disable fast lock */
5585 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5586
5587 /* Set idtafcrecal before PLL is enabled */
5588 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5589 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5590 mdiv |= ((bestn << DPIO_N_SHIFT));
5591 mdiv |= (1 << DPIO_K_SHIFT);
5592
5593 /*
5594 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5595 * but we don't support that).
5596 * Note: don't use the DAC post divider as it seems unstable.
5597 */
5598 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5599 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5600
5601 mdiv |= DPIO_ENABLE_CALIBRATION;
5602 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5603
5604 /* Set HBR and RBR LPF coefficients */
5605 if (crtc->config.port_clock == 162000 ||
5606 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5607 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5608 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5609 0x009f0003);
5610 else
5611 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5612 0x00d0000f);
5613
5614 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5615 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5616 /* Use SSC source */
5617 if (pipe == PIPE_A)
5618 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5619 0x0df40000);
5620 else
5621 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5622 0x0df70000);
5623 } else { /* HDMI or VGA */
5624 /* Use bend source */
5625 if (pipe == PIPE_A)
5626 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5627 0x0df70000);
5628 else
5629 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5630 0x0df40000);
5631 }
5632
5633 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5634 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5635 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5636 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5637 coreclk |= 0x01000000;
5638 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5639
5640 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5641 mutex_unlock(&dev_priv->dpio_lock);
5642 }
5643
5644 static void chv_update_pll(struct intel_crtc *crtc)
5645 {
5646 struct drm_device *dev = crtc->base.dev;
5647 struct drm_i915_private *dev_priv = dev->dev_private;
5648 int pipe = crtc->pipe;
5649 int dpll_reg = DPLL(crtc->pipe);
5650 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5651 u32 loopfilter, intcoeff;
5652 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5653 int refclk;
5654
5655 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5656 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5657 DPLL_VCO_ENABLE;
5658 if (pipe != PIPE_A)
5659 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5660
5661 crtc->config.dpll_hw_state.dpll_md =
5662 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5663
5664 bestn = crtc->config.dpll.n;
5665 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5666 bestm1 = crtc->config.dpll.m1;
5667 bestm2 = crtc->config.dpll.m2 >> 22;
5668 bestp1 = crtc->config.dpll.p1;
5669 bestp2 = crtc->config.dpll.p2;
5670
5671 /*
5672 * Enable Refclk and SSC
5673 */
5674 I915_WRITE(dpll_reg,
5675 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5676
5677 mutex_lock(&dev_priv->dpio_lock);
5678
5679 /* p1 and p2 divider */
5680 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5681 5 << DPIO_CHV_S1_DIV_SHIFT |
5682 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5683 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5684 1 << DPIO_CHV_K_DIV_SHIFT);
5685
5686 /* Feedback post-divider - m2 */
5687 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5688
5689 /* Feedback refclk divider - n and m1 */
5690 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5691 DPIO_CHV_M1_DIV_BY_2 |
5692 1 << DPIO_CHV_N_DIV_SHIFT);
5693
5694 /* M2 fraction division */
5695 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5696
5697 /* M2 fraction division enable */
5698 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5699 DPIO_CHV_FRAC_DIV_EN |
5700 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5701
5702 /* Loop filter */
5703 refclk = i9xx_get_refclk(&crtc->base, 0);
5704 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5705 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5706 if (refclk == 100000)
5707 intcoeff = 11;
5708 else if (refclk == 38400)
5709 intcoeff = 10;
5710 else
5711 intcoeff = 9;
5712 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5713 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5714
5715 /* AFC Recal */
5716 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5717 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5718 DPIO_AFC_RECAL);
5719
5720 mutex_unlock(&dev_priv->dpio_lock);
5721 }
5722
5723 static void i9xx_update_pll(struct intel_crtc *crtc,
5724 intel_clock_t *reduced_clock,
5725 int num_connectors)
5726 {
5727 struct drm_device *dev = crtc->base.dev;
5728 struct drm_i915_private *dev_priv = dev->dev_private;
5729 u32 dpll;
5730 bool is_sdvo;
5731 struct dpll *clock = &crtc->config.dpll;
5732
5733 i9xx_update_pll_dividers(crtc, reduced_clock);
5734
5735 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5736 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5737
5738 dpll = DPLL_VGA_MODE_DIS;
5739
5740 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5741 dpll |= DPLLB_MODE_LVDS;
5742 else
5743 dpll |= DPLLB_MODE_DAC_SERIAL;
5744
5745 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5746 dpll |= (crtc->config.pixel_multiplier - 1)
5747 << SDVO_MULTIPLIER_SHIFT_HIRES;
5748 }
5749
5750 if (is_sdvo)
5751 dpll |= DPLL_SDVO_HIGH_SPEED;
5752
5753 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5754 dpll |= DPLL_SDVO_HIGH_SPEED;
5755
5756 /* compute bitmask from p1 value */
5757 if (IS_PINEVIEW(dev))
5758 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5759 else {
5760 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5761 if (IS_G4X(dev) && reduced_clock)
5762 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5763 }
5764 switch (clock->p2) {
5765 case 5:
5766 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5767 break;
5768 case 7:
5769 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5770 break;
5771 case 10:
5772 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5773 break;
5774 case 14:
5775 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5776 break;
5777 }
5778 if (INTEL_INFO(dev)->gen >= 4)
5779 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5780
5781 if (crtc->config.sdvo_tv_clock)
5782 dpll |= PLL_REF_INPUT_TVCLKINBC;
5783 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5784 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5785 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5786 else
5787 dpll |= PLL_REF_INPUT_DREFCLK;
5788
5789 dpll |= DPLL_VCO_ENABLE;
5790 crtc->config.dpll_hw_state.dpll = dpll;
5791
5792 if (INTEL_INFO(dev)->gen >= 4) {
5793 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5794 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5795 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5796 }
5797 }
5798
5799 static void i8xx_update_pll(struct intel_crtc *crtc,
5800 intel_clock_t *reduced_clock,
5801 int num_connectors)
5802 {
5803 struct drm_device *dev = crtc->base.dev;
5804 struct drm_i915_private *dev_priv = dev->dev_private;
5805 u32 dpll;
5806 struct dpll *clock = &crtc->config.dpll;
5807
5808 i9xx_update_pll_dividers(crtc, reduced_clock);
5809
5810 dpll = DPLL_VGA_MODE_DIS;
5811
5812 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5813 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5814 } else {
5815 if (clock->p1 == 2)
5816 dpll |= PLL_P1_DIVIDE_BY_TWO;
5817 else
5818 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5819 if (clock->p2 == 4)
5820 dpll |= PLL_P2_DIVIDE_BY_4;
5821 }
5822
5823 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5824 dpll |= DPLL_DVO_2X_MODE;
5825
5826 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5827 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5828 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5829 else
5830 dpll |= PLL_REF_INPUT_DREFCLK;
5831
5832 dpll |= DPLL_VCO_ENABLE;
5833 crtc->config.dpll_hw_state.dpll = dpll;
5834 }
5835
5836 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5837 {
5838 struct drm_device *dev = intel_crtc->base.dev;
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840 enum pipe pipe = intel_crtc->pipe;
5841 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5842 struct drm_display_mode *adjusted_mode =
5843 &intel_crtc->config.adjusted_mode;
5844 uint32_t crtc_vtotal, crtc_vblank_end;
5845 int vsyncshift = 0;
5846
5847 /* We need to be careful not to changed the adjusted mode, for otherwise
5848 * the hw state checker will get angry at the mismatch. */
5849 crtc_vtotal = adjusted_mode->crtc_vtotal;
5850 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5851
5852 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5853 /* the chip adds 2 halflines automatically */
5854 crtc_vtotal -= 1;
5855 crtc_vblank_end -= 1;
5856
5857 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5858 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5859 else
5860 vsyncshift = adjusted_mode->crtc_hsync_start -
5861 adjusted_mode->crtc_htotal / 2;
5862 if (vsyncshift < 0)
5863 vsyncshift += adjusted_mode->crtc_htotal;
5864 }
5865
5866 if (INTEL_INFO(dev)->gen > 3)
5867 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5868
5869 I915_WRITE(HTOTAL(cpu_transcoder),
5870 (adjusted_mode->crtc_hdisplay - 1) |
5871 ((adjusted_mode->crtc_htotal - 1) << 16));
5872 I915_WRITE(HBLANK(cpu_transcoder),
5873 (adjusted_mode->crtc_hblank_start - 1) |
5874 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5875 I915_WRITE(HSYNC(cpu_transcoder),
5876 (adjusted_mode->crtc_hsync_start - 1) |
5877 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5878
5879 I915_WRITE(VTOTAL(cpu_transcoder),
5880 (adjusted_mode->crtc_vdisplay - 1) |
5881 ((crtc_vtotal - 1) << 16));
5882 I915_WRITE(VBLANK(cpu_transcoder),
5883 (adjusted_mode->crtc_vblank_start - 1) |
5884 ((crtc_vblank_end - 1) << 16));
5885 I915_WRITE(VSYNC(cpu_transcoder),
5886 (adjusted_mode->crtc_vsync_start - 1) |
5887 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5888
5889 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5890 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5891 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5892 * bits. */
5893 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5894 (pipe == PIPE_B || pipe == PIPE_C))
5895 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5896
5897 /* pipesrc controls the size that is scaled from, which should
5898 * always be the user's requested size.
5899 */
5900 I915_WRITE(PIPESRC(pipe),
5901 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5902 (intel_crtc->config.pipe_src_h - 1));
5903 }
5904
5905 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5906 struct intel_crtc_config *pipe_config)
5907 {
5908 struct drm_device *dev = crtc->base.dev;
5909 struct drm_i915_private *dev_priv = dev->dev_private;
5910 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5911 uint32_t tmp;
5912
5913 tmp = I915_READ(HTOTAL(cpu_transcoder));
5914 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5915 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5916 tmp = I915_READ(HBLANK(cpu_transcoder));
5917 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5918 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5919 tmp = I915_READ(HSYNC(cpu_transcoder));
5920 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5921 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5922
5923 tmp = I915_READ(VTOTAL(cpu_transcoder));
5924 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5925 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5926 tmp = I915_READ(VBLANK(cpu_transcoder));
5927 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5928 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5929 tmp = I915_READ(VSYNC(cpu_transcoder));
5930 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5931 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5932
5933 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5934 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5935 pipe_config->adjusted_mode.crtc_vtotal += 1;
5936 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5937 }
5938
5939 tmp = I915_READ(PIPESRC(crtc->pipe));
5940 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5941 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5942
5943 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5944 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5945 }
5946
5947 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5948 struct intel_crtc_config *pipe_config)
5949 {
5950 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5951 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5952 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5953 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5954
5955 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5956 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5957 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5958 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5959
5960 mode->flags = pipe_config->adjusted_mode.flags;
5961
5962 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5963 mode->flags |= pipe_config->adjusted_mode.flags;
5964 }
5965
5966 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5967 {
5968 struct drm_device *dev = intel_crtc->base.dev;
5969 struct drm_i915_private *dev_priv = dev->dev_private;
5970 uint32_t pipeconf;
5971
5972 pipeconf = 0;
5973
5974 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5975 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5976 pipeconf |= PIPECONF_ENABLE;
5977
5978 if (intel_crtc->config.double_wide)
5979 pipeconf |= PIPECONF_DOUBLE_WIDE;
5980
5981 /* only g4x and later have fancy bpc/dither controls */
5982 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5983 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5984 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5985 pipeconf |= PIPECONF_DITHER_EN |
5986 PIPECONF_DITHER_TYPE_SP;
5987
5988 switch (intel_crtc->config.pipe_bpp) {
5989 case 18:
5990 pipeconf |= PIPECONF_6BPC;
5991 break;
5992 case 24:
5993 pipeconf |= PIPECONF_8BPC;
5994 break;
5995 case 30:
5996 pipeconf |= PIPECONF_10BPC;
5997 break;
5998 default:
5999 /* Case prevented by intel_choose_pipe_bpp_dither. */
6000 BUG();
6001 }
6002 }
6003
6004 if (HAS_PIPE_CXSR(dev)) {
6005 if (intel_crtc->lowfreq_avail) {
6006 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6007 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6008 } else {
6009 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6010 }
6011 }
6012
6013 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6014 if (INTEL_INFO(dev)->gen < 4 ||
6015 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6016 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6017 else
6018 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6019 } else
6020 pipeconf |= PIPECONF_PROGRESSIVE;
6021
6022 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6023 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6024
6025 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6026 POSTING_READ(PIPECONF(intel_crtc->pipe));
6027 }
6028
6029 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6030 int x, int y,
6031 struct drm_framebuffer *fb)
6032 {
6033 struct drm_device *dev = crtc->dev;
6034 struct drm_i915_private *dev_priv = dev->dev_private;
6035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6036 int refclk, num_connectors = 0;
6037 intel_clock_t clock, reduced_clock;
6038 bool ok, has_reduced_clock = false;
6039 bool is_lvds = false, is_dsi = false;
6040 struct intel_encoder *encoder;
6041 const intel_limit_t *limit;
6042
6043 for_each_encoder_on_crtc(dev, crtc, encoder) {
6044 switch (encoder->type) {
6045 case INTEL_OUTPUT_LVDS:
6046 is_lvds = true;
6047 break;
6048 case INTEL_OUTPUT_DSI:
6049 is_dsi = true;
6050 break;
6051 }
6052
6053 num_connectors++;
6054 }
6055
6056 if (is_dsi)
6057 return 0;
6058
6059 if (!intel_crtc->config.clock_set) {
6060 refclk = i9xx_get_refclk(crtc, num_connectors);
6061
6062 /*
6063 * Returns a set of divisors for the desired target clock with
6064 * the given refclk, or FALSE. The returned values represent
6065 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6066 * 2) / p1 / p2.
6067 */
6068 limit = intel_limit(crtc, refclk);
6069 ok = dev_priv->display.find_dpll(limit, crtc,
6070 intel_crtc->config.port_clock,
6071 refclk, NULL, &clock);
6072 if (!ok) {
6073 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6074 return -EINVAL;
6075 }
6076
6077 if (is_lvds && dev_priv->lvds_downclock_avail) {
6078 /*
6079 * Ensure we match the reduced clock's P to the target
6080 * clock. If the clocks don't match, we can't switch
6081 * the display clock by using the FP0/FP1. In such case
6082 * we will disable the LVDS downclock feature.
6083 */
6084 has_reduced_clock =
6085 dev_priv->display.find_dpll(limit, crtc,
6086 dev_priv->lvds_downclock,
6087 refclk, &clock,
6088 &reduced_clock);
6089 }
6090 /* Compat-code for transition, will disappear. */
6091 intel_crtc->config.dpll.n = clock.n;
6092 intel_crtc->config.dpll.m1 = clock.m1;
6093 intel_crtc->config.dpll.m2 = clock.m2;
6094 intel_crtc->config.dpll.p1 = clock.p1;
6095 intel_crtc->config.dpll.p2 = clock.p2;
6096 }
6097
6098 if (IS_GEN2(dev)) {
6099 i8xx_update_pll(intel_crtc,
6100 has_reduced_clock ? &reduced_clock : NULL,
6101 num_connectors);
6102 } else if (IS_CHERRYVIEW(dev)) {
6103 chv_update_pll(intel_crtc);
6104 } else if (IS_VALLEYVIEW(dev)) {
6105 vlv_update_pll(intel_crtc);
6106 } else {
6107 i9xx_update_pll(intel_crtc,
6108 has_reduced_clock ? &reduced_clock : NULL,
6109 num_connectors);
6110 }
6111
6112 return 0;
6113 }
6114
6115 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6116 struct intel_crtc_config *pipe_config)
6117 {
6118 struct drm_device *dev = crtc->base.dev;
6119 struct drm_i915_private *dev_priv = dev->dev_private;
6120 uint32_t tmp;
6121
6122 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6123 return;
6124
6125 tmp = I915_READ(PFIT_CONTROL);
6126 if (!(tmp & PFIT_ENABLE))
6127 return;
6128
6129 /* Check whether the pfit is attached to our pipe. */
6130 if (INTEL_INFO(dev)->gen < 4) {
6131 if (crtc->pipe != PIPE_B)
6132 return;
6133 } else {
6134 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6135 return;
6136 }
6137
6138 pipe_config->gmch_pfit.control = tmp;
6139 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6140 if (INTEL_INFO(dev)->gen < 5)
6141 pipe_config->gmch_pfit.lvds_border_bits =
6142 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6143 }
6144
6145 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6146 struct intel_crtc_config *pipe_config)
6147 {
6148 struct drm_device *dev = crtc->base.dev;
6149 struct drm_i915_private *dev_priv = dev->dev_private;
6150 int pipe = pipe_config->cpu_transcoder;
6151 intel_clock_t clock;
6152 u32 mdiv;
6153 int refclk = 100000;
6154
6155 mutex_lock(&dev_priv->dpio_lock);
6156 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6157 mutex_unlock(&dev_priv->dpio_lock);
6158
6159 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6160 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6161 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6162 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6163 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6164
6165 vlv_clock(refclk, &clock);
6166
6167 /* clock.dot is the fast clock */
6168 pipe_config->port_clock = clock.dot / 5;
6169 }
6170
6171 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6172 struct intel_plane_config *plane_config)
6173 {
6174 struct drm_device *dev = crtc->base.dev;
6175 struct drm_i915_private *dev_priv = dev->dev_private;
6176 u32 val, base, offset;
6177 int pipe = crtc->pipe, plane = crtc->plane;
6178 int fourcc, pixel_format;
6179 int aligned_height;
6180
6181 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6182 if (!crtc->base.primary->fb) {
6183 DRM_DEBUG_KMS("failed to alloc fb\n");
6184 return;
6185 }
6186
6187 val = I915_READ(DSPCNTR(plane));
6188
6189 if (INTEL_INFO(dev)->gen >= 4)
6190 if (val & DISPPLANE_TILED)
6191 plane_config->tiled = true;
6192
6193 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6194 fourcc = intel_format_to_fourcc(pixel_format);
6195 crtc->base.primary->fb->pixel_format = fourcc;
6196 crtc->base.primary->fb->bits_per_pixel =
6197 drm_format_plane_cpp(fourcc, 0) * 8;
6198
6199 if (INTEL_INFO(dev)->gen >= 4) {
6200 if (plane_config->tiled)
6201 offset = I915_READ(DSPTILEOFF(plane));
6202 else
6203 offset = I915_READ(DSPLINOFF(plane));
6204 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6205 } else {
6206 base = I915_READ(DSPADDR(plane));
6207 }
6208 plane_config->base = base;
6209
6210 val = I915_READ(PIPESRC(pipe));
6211 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6212 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6213
6214 val = I915_READ(DSPSTRIDE(pipe));
6215 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6216
6217 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6218 plane_config->tiled);
6219
6220 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6221 aligned_height, PAGE_SIZE);
6222
6223 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6224 pipe, plane, crtc->base.primary->fb->width,
6225 crtc->base.primary->fb->height,
6226 crtc->base.primary->fb->bits_per_pixel, base,
6227 crtc->base.primary->fb->pitches[0],
6228 plane_config->size);
6229
6230 }
6231
6232 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6233 struct intel_crtc_config *pipe_config)
6234 {
6235 struct drm_device *dev = crtc->base.dev;
6236 struct drm_i915_private *dev_priv = dev->dev_private;
6237 int pipe = pipe_config->cpu_transcoder;
6238 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6239 intel_clock_t clock;
6240 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6241 int refclk = 100000;
6242
6243 mutex_lock(&dev_priv->dpio_lock);
6244 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6245 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6246 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6247 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6248 mutex_unlock(&dev_priv->dpio_lock);
6249
6250 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6251 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6252 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6253 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6254 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6255
6256 chv_clock(refclk, &clock);
6257
6258 /* clock.dot is the fast clock */
6259 pipe_config->port_clock = clock.dot / 5;
6260 }
6261
6262 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6263 struct intel_crtc_config *pipe_config)
6264 {
6265 struct drm_device *dev = crtc->base.dev;
6266 struct drm_i915_private *dev_priv = dev->dev_private;
6267 uint32_t tmp;
6268
6269 if (!intel_display_power_enabled(dev_priv,
6270 POWER_DOMAIN_PIPE(crtc->pipe)))
6271 return false;
6272
6273 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6274 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6275
6276 tmp = I915_READ(PIPECONF(crtc->pipe));
6277 if (!(tmp & PIPECONF_ENABLE))
6278 return false;
6279
6280 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6281 switch (tmp & PIPECONF_BPC_MASK) {
6282 case PIPECONF_6BPC:
6283 pipe_config->pipe_bpp = 18;
6284 break;
6285 case PIPECONF_8BPC:
6286 pipe_config->pipe_bpp = 24;
6287 break;
6288 case PIPECONF_10BPC:
6289 pipe_config->pipe_bpp = 30;
6290 break;
6291 default:
6292 break;
6293 }
6294 }
6295
6296 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6297 pipe_config->limited_color_range = true;
6298
6299 if (INTEL_INFO(dev)->gen < 4)
6300 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6301
6302 intel_get_pipe_timings(crtc, pipe_config);
6303
6304 i9xx_get_pfit_config(crtc, pipe_config);
6305
6306 if (INTEL_INFO(dev)->gen >= 4) {
6307 tmp = I915_READ(DPLL_MD(crtc->pipe));
6308 pipe_config->pixel_multiplier =
6309 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6310 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6311 pipe_config->dpll_hw_state.dpll_md = tmp;
6312 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6313 tmp = I915_READ(DPLL(crtc->pipe));
6314 pipe_config->pixel_multiplier =
6315 ((tmp & SDVO_MULTIPLIER_MASK)
6316 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6317 } else {
6318 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6319 * port and will be fixed up in the encoder->get_config
6320 * function. */
6321 pipe_config->pixel_multiplier = 1;
6322 }
6323 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6324 if (!IS_VALLEYVIEW(dev)) {
6325 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6326 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6327 } else {
6328 /* Mask out read-only status bits. */
6329 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6330 DPLL_PORTC_READY_MASK |
6331 DPLL_PORTB_READY_MASK);
6332 }
6333
6334 if (IS_CHERRYVIEW(dev))
6335 chv_crtc_clock_get(crtc, pipe_config);
6336 else if (IS_VALLEYVIEW(dev))
6337 vlv_crtc_clock_get(crtc, pipe_config);
6338 else
6339 i9xx_crtc_clock_get(crtc, pipe_config);
6340
6341 return true;
6342 }
6343
6344 static void ironlake_init_pch_refclk(struct drm_device *dev)
6345 {
6346 struct drm_i915_private *dev_priv = dev->dev_private;
6347 struct drm_mode_config *mode_config = &dev->mode_config;
6348 struct intel_encoder *encoder;
6349 u32 val, final;
6350 bool has_lvds = false;
6351 bool has_cpu_edp = false;
6352 bool has_panel = false;
6353 bool has_ck505 = false;
6354 bool can_ssc = false;
6355
6356 /* We need to take the global config into account */
6357 list_for_each_entry(encoder, &mode_config->encoder_list,
6358 base.head) {
6359 switch (encoder->type) {
6360 case INTEL_OUTPUT_LVDS:
6361 has_panel = true;
6362 has_lvds = true;
6363 break;
6364 case INTEL_OUTPUT_EDP:
6365 has_panel = true;
6366 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6367 has_cpu_edp = true;
6368 break;
6369 }
6370 }
6371
6372 if (HAS_PCH_IBX(dev)) {
6373 has_ck505 = dev_priv->vbt.display_clock_mode;
6374 can_ssc = has_ck505;
6375 } else {
6376 has_ck505 = false;
6377 can_ssc = true;
6378 }
6379
6380 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6381 has_panel, has_lvds, has_ck505);
6382
6383 /* Ironlake: try to setup display ref clock before DPLL
6384 * enabling. This is only under driver's control after
6385 * PCH B stepping, previous chipset stepping should be
6386 * ignoring this setting.
6387 */
6388 val = I915_READ(PCH_DREF_CONTROL);
6389
6390 /* As we must carefully and slowly disable/enable each source in turn,
6391 * compute the final state we want first and check if we need to
6392 * make any changes at all.
6393 */
6394 final = val;
6395 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6396 if (has_ck505)
6397 final |= DREF_NONSPREAD_CK505_ENABLE;
6398 else
6399 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6400
6401 final &= ~DREF_SSC_SOURCE_MASK;
6402 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6403 final &= ~DREF_SSC1_ENABLE;
6404
6405 if (has_panel) {
6406 final |= DREF_SSC_SOURCE_ENABLE;
6407
6408 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6409 final |= DREF_SSC1_ENABLE;
6410
6411 if (has_cpu_edp) {
6412 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6413 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6414 else
6415 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6416 } else
6417 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6418 } else {
6419 final |= DREF_SSC_SOURCE_DISABLE;
6420 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6421 }
6422
6423 if (final == val)
6424 return;
6425
6426 /* Always enable nonspread source */
6427 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6428
6429 if (has_ck505)
6430 val |= DREF_NONSPREAD_CK505_ENABLE;
6431 else
6432 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6433
6434 if (has_panel) {
6435 val &= ~DREF_SSC_SOURCE_MASK;
6436 val |= DREF_SSC_SOURCE_ENABLE;
6437
6438 /* SSC must be turned on before enabling the CPU output */
6439 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6440 DRM_DEBUG_KMS("Using SSC on panel\n");
6441 val |= DREF_SSC1_ENABLE;
6442 } else
6443 val &= ~DREF_SSC1_ENABLE;
6444
6445 /* Get SSC going before enabling the outputs */
6446 I915_WRITE(PCH_DREF_CONTROL, val);
6447 POSTING_READ(PCH_DREF_CONTROL);
6448 udelay(200);
6449
6450 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6451
6452 /* Enable CPU source on CPU attached eDP */
6453 if (has_cpu_edp) {
6454 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6455 DRM_DEBUG_KMS("Using SSC on eDP\n");
6456 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6457 } else
6458 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6459 } else
6460 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6461
6462 I915_WRITE(PCH_DREF_CONTROL, val);
6463 POSTING_READ(PCH_DREF_CONTROL);
6464 udelay(200);
6465 } else {
6466 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6467
6468 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6469
6470 /* Turn off CPU output */
6471 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6472
6473 I915_WRITE(PCH_DREF_CONTROL, val);
6474 POSTING_READ(PCH_DREF_CONTROL);
6475 udelay(200);
6476
6477 /* Turn off the SSC source */
6478 val &= ~DREF_SSC_SOURCE_MASK;
6479 val |= DREF_SSC_SOURCE_DISABLE;
6480
6481 /* Turn off SSC1 */
6482 val &= ~DREF_SSC1_ENABLE;
6483
6484 I915_WRITE(PCH_DREF_CONTROL, val);
6485 POSTING_READ(PCH_DREF_CONTROL);
6486 udelay(200);
6487 }
6488
6489 BUG_ON(val != final);
6490 }
6491
6492 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6493 {
6494 uint32_t tmp;
6495
6496 tmp = I915_READ(SOUTH_CHICKEN2);
6497 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6498 I915_WRITE(SOUTH_CHICKEN2, tmp);
6499
6500 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6501 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6502 DRM_ERROR("FDI mPHY reset assert timeout\n");
6503
6504 tmp = I915_READ(SOUTH_CHICKEN2);
6505 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6506 I915_WRITE(SOUTH_CHICKEN2, tmp);
6507
6508 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6509 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6510 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6511 }
6512
6513 /* WaMPhyProgramming:hsw */
6514 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6515 {
6516 uint32_t tmp;
6517
6518 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6519 tmp &= ~(0xFF << 24);
6520 tmp |= (0x12 << 24);
6521 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6522
6523 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6524 tmp |= (1 << 11);
6525 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6526
6527 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6528 tmp |= (1 << 11);
6529 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6530
6531 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6532 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6533 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6534
6535 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6536 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6537 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6538
6539 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6540 tmp &= ~(7 << 13);
6541 tmp |= (5 << 13);
6542 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6543
6544 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6545 tmp &= ~(7 << 13);
6546 tmp |= (5 << 13);
6547 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6548
6549 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6550 tmp &= ~0xFF;
6551 tmp |= 0x1C;
6552 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6553
6554 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6555 tmp &= ~0xFF;
6556 tmp |= 0x1C;
6557 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6558
6559 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6560 tmp &= ~(0xFF << 16);
6561 tmp |= (0x1C << 16);
6562 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6563
6564 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6565 tmp &= ~(0xFF << 16);
6566 tmp |= (0x1C << 16);
6567 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6568
6569 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6570 tmp |= (1 << 27);
6571 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6572
6573 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6574 tmp |= (1 << 27);
6575 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6576
6577 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6578 tmp &= ~(0xF << 28);
6579 tmp |= (4 << 28);
6580 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6581
6582 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6583 tmp &= ~(0xF << 28);
6584 tmp |= (4 << 28);
6585 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6586 }
6587
6588 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6589 * Programming" based on the parameters passed:
6590 * - Sequence to enable CLKOUT_DP
6591 * - Sequence to enable CLKOUT_DP without spread
6592 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6593 */
6594 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6595 bool with_fdi)
6596 {
6597 struct drm_i915_private *dev_priv = dev->dev_private;
6598 uint32_t reg, tmp;
6599
6600 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6601 with_spread = true;
6602 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6603 with_fdi, "LP PCH doesn't have FDI\n"))
6604 with_fdi = false;
6605
6606 mutex_lock(&dev_priv->dpio_lock);
6607
6608 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6609 tmp &= ~SBI_SSCCTL_DISABLE;
6610 tmp |= SBI_SSCCTL_PATHALT;
6611 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6612
6613 udelay(24);
6614
6615 if (with_spread) {
6616 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6617 tmp &= ~SBI_SSCCTL_PATHALT;
6618 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6619
6620 if (with_fdi) {
6621 lpt_reset_fdi_mphy(dev_priv);
6622 lpt_program_fdi_mphy(dev_priv);
6623 }
6624 }
6625
6626 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6627 SBI_GEN0 : SBI_DBUFF0;
6628 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6629 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6630 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6631
6632 mutex_unlock(&dev_priv->dpio_lock);
6633 }
6634
6635 /* Sequence to disable CLKOUT_DP */
6636 static void lpt_disable_clkout_dp(struct drm_device *dev)
6637 {
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639 uint32_t reg, tmp;
6640
6641 mutex_lock(&dev_priv->dpio_lock);
6642
6643 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6644 SBI_GEN0 : SBI_DBUFF0;
6645 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6646 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6647 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6648
6649 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6650 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6651 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6652 tmp |= SBI_SSCCTL_PATHALT;
6653 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6654 udelay(32);
6655 }
6656 tmp |= SBI_SSCCTL_DISABLE;
6657 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6658 }
6659
6660 mutex_unlock(&dev_priv->dpio_lock);
6661 }
6662
6663 static void lpt_init_pch_refclk(struct drm_device *dev)
6664 {
6665 struct drm_mode_config *mode_config = &dev->mode_config;
6666 struct intel_encoder *encoder;
6667 bool has_vga = false;
6668
6669 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6670 switch (encoder->type) {
6671 case INTEL_OUTPUT_ANALOG:
6672 has_vga = true;
6673 break;
6674 }
6675 }
6676
6677 if (has_vga)
6678 lpt_enable_clkout_dp(dev, true, true);
6679 else
6680 lpt_disable_clkout_dp(dev);
6681 }
6682
6683 /*
6684 * Initialize reference clocks when the driver loads
6685 */
6686 void intel_init_pch_refclk(struct drm_device *dev)
6687 {
6688 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6689 ironlake_init_pch_refclk(dev);
6690 else if (HAS_PCH_LPT(dev))
6691 lpt_init_pch_refclk(dev);
6692 }
6693
6694 static int ironlake_get_refclk(struct drm_crtc *crtc)
6695 {
6696 struct drm_device *dev = crtc->dev;
6697 struct drm_i915_private *dev_priv = dev->dev_private;
6698 struct intel_encoder *encoder;
6699 int num_connectors = 0;
6700 bool is_lvds = false;
6701
6702 for_each_encoder_on_crtc(dev, crtc, encoder) {
6703 switch (encoder->type) {
6704 case INTEL_OUTPUT_LVDS:
6705 is_lvds = true;
6706 break;
6707 }
6708 num_connectors++;
6709 }
6710
6711 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6712 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6713 dev_priv->vbt.lvds_ssc_freq);
6714 return dev_priv->vbt.lvds_ssc_freq;
6715 }
6716
6717 return 120000;
6718 }
6719
6720 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6721 {
6722 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6724 int pipe = intel_crtc->pipe;
6725 uint32_t val;
6726
6727 val = 0;
6728
6729 switch (intel_crtc->config.pipe_bpp) {
6730 case 18:
6731 val |= PIPECONF_6BPC;
6732 break;
6733 case 24:
6734 val |= PIPECONF_8BPC;
6735 break;
6736 case 30:
6737 val |= PIPECONF_10BPC;
6738 break;
6739 case 36:
6740 val |= PIPECONF_12BPC;
6741 break;
6742 default:
6743 /* Case prevented by intel_choose_pipe_bpp_dither. */
6744 BUG();
6745 }
6746
6747 if (intel_crtc->config.dither)
6748 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6749
6750 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6751 val |= PIPECONF_INTERLACED_ILK;
6752 else
6753 val |= PIPECONF_PROGRESSIVE;
6754
6755 if (intel_crtc->config.limited_color_range)
6756 val |= PIPECONF_COLOR_RANGE_SELECT;
6757
6758 I915_WRITE(PIPECONF(pipe), val);
6759 POSTING_READ(PIPECONF(pipe));
6760 }
6761
6762 /*
6763 * Set up the pipe CSC unit.
6764 *
6765 * Currently only full range RGB to limited range RGB conversion
6766 * is supported, but eventually this should handle various
6767 * RGB<->YCbCr scenarios as well.
6768 */
6769 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6770 {
6771 struct drm_device *dev = crtc->dev;
6772 struct drm_i915_private *dev_priv = dev->dev_private;
6773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6774 int pipe = intel_crtc->pipe;
6775 uint16_t coeff = 0x7800; /* 1.0 */
6776
6777 /*
6778 * TODO: Check what kind of values actually come out of the pipe
6779 * with these coeff/postoff values and adjust to get the best
6780 * accuracy. Perhaps we even need to take the bpc value into
6781 * consideration.
6782 */
6783
6784 if (intel_crtc->config.limited_color_range)
6785 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6786
6787 /*
6788 * GY/GU and RY/RU should be the other way around according
6789 * to BSpec, but reality doesn't agree. Just set them up in
6790 * a way that results in the correct picture.
6791 */
6792 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6793 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6794
6795 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6796 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6797
6798 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6799 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6800
6801 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6802 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6803 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6804
6805 if (INTEL_INFO(dev)->gen > 6) {
6806 uint16_t postoff = 0;
6807
6808 if (intel_crtc->config.limited_color_range)
6809 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6810
6811 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6812 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6813 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6814
6815 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6816 } else {
6817 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6818
6819 if (intel_crtc->config.limited_color_range)
6820 mode |= CSC_BLACK_SCREEN_OFFSET;
6821
6822 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6823 }
6824 }
6825
6826 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6827 {
6828 struct drm_device *dev = crtc->dev;
6829 struct drm_i915_private *dev_priv = dev->dev_private;
6830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6831 enum pipe pipe = intel_crtc->pipe;
6832 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6833 uint32_t val;
6834
6835 val = 0;
6836
6837 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6838 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6839
6840 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6841 val |= PIPECONF_INTERLACED_ILK;
6842 else
6843 val |= PIPECONF_PROGRESSIVE;
6844
6845 I915_WRITE(PIPECONF(cpu_transcoder), val);
6846 POSTING_READ(PIPECONF(cpu_transcoder));
6847
6848 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6849 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6850
6851 if (IS_BROADWELL(dev)) {
6852 val = 0;
6853
6854 switch (intel_crtc->config.pipe_bpp) {
6855 case 18:
6856 val |= PIPEMISC_DITHER_6_BPC;
6857 break;
6858 case 24:
6859 val |= PIPEMISC_DITHER_8_BPC;
6860 break;
6861 case 30:
6862 val |= PIPEMISC_DITHER_10_BPC;
6863 break;
6864 case 36:
6865 val |= PIPEMISC_DITHER_12_BPC;
6866 break;
6867 default:
6868 /* Case prevented by pipe_config_set_bpp. */
6869 BUG();
6870 }
6871
6872 if (intel_crtc->config.dither)
6873 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6874
6875 I915_WRITE(PIPEMISC(pipe), val);
6876 }
6877 }
6878
6879 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6880 intel_clock_t *clock,
6881 bool *has_reduced_clock,
6882 intel_clock_t *reduced_clock)
6883 {
6884 struct drm_device *dev = crtc->dev;
6885 struct drm_i915_private *dev_priv = dev->dev_private;
6886 struct intel_encoder *intel_encoder;
6887 int refclk;
6888 const intel_limit_t *limit;
6889 bool ret, is_lvds = false;
6890
6891 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6892 switch (intel_encoder->type) {
6893 case INTEL_OUTPUT_LVDS:
6894 is_lvds = true;
6895 break;
6896 }
6897 }
6898
6899 refclk = ironlake_get_refclk(crtc);
6900
6901 /*
6902 * Returns a set of divisors for the desired target clock with the given
6903 * refclk, or FALSE. The returned values represent the clock equation:
6904 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6905 */
6906 limit = intel_limit(crtc, refclk);
6907 ret = dev_priv->display.find_dpll(limit, crtc,
6908 to_intel_crtc(crtc)->config.port_clock,
6909 refclk, NULL, clock);
6910 if (!ret)
6911 return false;
6912
6913 if (is_lvds && dev_priv->lvds_downclock_avail) {
6914 /*
6915 * Ensure we match the reduced clock's P to the target clock.
6916 * If the clocks don't match, we can't switch the display clock
6917 * by using the FP0/FP1. In such case we will disable the LVDS
6918 * downclock feature.
6919 */
6920 *has_reduced_clock =
6921 dev_priv->display.find_dpll(limit, crtc,
6922 dev_priv->lvds_downclock,
6923 refclk, clock,
6924 reduced_clock);
6925 }
6926
6927 return true;
6928 }
6929
6930 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6931 {
6932 /*
6933 * Account for spread spectrum to avoid
6934 * oversubscribing the link. Max center spread
6935 * is 2.5%; use 5% for safety's sake.
6936 */
6937 u32 bps = target_clock * bpp * 21 / 20;
6938 return DIV_ROUND_UP(bps, link_bw * 8);
6939 }
6940
6941 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6942 {
6943 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6944 }
6945
6946 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6947 u32 *fp,
6948 intel_clock_t *reduced_clock, u32 *fp2)
6949 {
6950 struct drm_crtc *crtc = &intel_crtc->base;
6951 struct drm_device *dev = crtc->dev;
6952 struct drm_i915_private *dev_priv = dev->dev_private;
6953 struct intel_encoder *intel_encoder;
6954 uint32_t dpll;
6955 int factor, num_connectors = 0;
6956 bool is_lvds = false, is_sdvo = false;
6957
6958 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6959 switch (intel_encoder->type) {
6960 case INTEL_OUTPUT_LVDS:
6961 is_lvds = true;
6962 break;
6963 case INTEL_OUTPUT_SDVO:
6964 case INTEL_OUTPUT_HDMI:
6965 is_sdvo = true;
6966 break;
6967 }
6968
6969 num_connectors++;
6970 }
6971
6972 /* Enable autotuning of the PLL clock (if permissible) */
6973 factor = 21;
6974 if (is_lvds) {
6975 if ((intel_panel_use_ssc(dev_priv) &&
6976 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6977 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6978 factor = 25;
6979 } else if (intel_crtc->config.sdvo_tv_clock)
6980 factor = 20;
6981
6982 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6983 *fp |= FP_CB_TUNE;
6984
6985 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6986 *fp2 |= FP_CB_TUNE;
6987
6988 dpll = 0;
6989
6990 if (is_lvds)
6991 dpll |= DPLLB_MODE_LVDS;
6992 else
6993 dpll |= DPLLB_MODE_DAC_SERIAL;
6994
6995 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6996 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6997
6998 if (is_sdvo)
6999 dpll |= DPLL_SDVO_HIGH_SPEED;
7000 if (intel_crtc->config.has_dp_encoder)
7001 dpll |= DPLL_SDVO_HIGH_SPEED;
7002
7003 /* compute bitmask from p1 value */
7004 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7005 /* also FPA1 */
7006 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7007
7008 switch (intel_crtc->config.dpll.p2) {
7009 case 5:
7010 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7011 break;
7012 case 7:
7013 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7014 break;
7015 case 10:
7016 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7017 break;
7018 case 14:
7019 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7020 break;
7021 }
7022
7023 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7024 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7025 else
7026 dpll |= PLL_REF_INPUT_DREFCLK;
7027
7028 return dpll | DPLL_VCO_ENABLE;
7029 }
7030
7031 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7032 int x, int y,
7033 struct drm_framebuffer *fb)
7034 {
7035 struct drm_device *dev = crtc->dev;
7036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7037 int num_connectors = 0;
7038 intel_clock_t clock, reduced_clock;
7039 u32 dpll = 0, fp = 0, fp2 = 0;
7040 bool ok, has_reduced_clock = false;
7041 bool is_lvds = false;
7042 struct intel_encoder *encoder;
7043 struct intel_shared_dpll *pll;
7044
7045 for_each_encoder_on_crtc(dev, crtc, encoder) {
7046 switch (encoder->type) {
7047 case INTEL_OUTPUT_LVDS:
7048 is_lvds = true;
7049 break;
7050 }
7051
7052 num_connectors++;
7053 }
7054
7055 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7056 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7057
7058 ok = ironlake_compute_clocks(crtc, &clock,
7059 &has_reduced_clock, &reduced_clock);
7060 if (!ok && !intel_crtc->config.clock_set) {
7061 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7062 return -EINVAL;
7063 }
7064 /* Compat-code for transition, will disappear. */
7065 if (!intel_crtc->config.clock_set) {
7066 intel_crtc->config.dpll.n = clock.n;
7067 intel_crtc->config.dpll.m1 = clock.m1;
7068 intel_crtc->config.dpll.m2 = clock.m2;
7069 intel_crtc->config.dpll.p1 = clock.p1;
7070 intel_crtc->config.dpll.p2 = clock.p2;
7071 }
7072
7073 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7074 if (intel_crtc->config.has_pch_encoder) {
7075 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7076 if (has_reduced_clock)
7077 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7078
7079 dpll = ironlake_compute_dpll(intel_crtc,
7080 &fp, &reduced_clock,
7081 has_reduced_clock ? &fp2 : NULL);
7082
7083 intel_crtc->config.dpll_hw_state.dpll = dpll;
7084 intel_crtc->config.dpll_hw_state.fp0 = fp;
7085 if (has_reduced_clock)
7086 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7087 else
7088 intel_crtc->config.dpll_hw_state.fp1 = fp;
7089
7090 pll = intel_get_shared_dpll(intel_crtc);
7091 if (pll == NULL) {
7092 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7093 pipe_name(intel_crtc->pipe));
7094 return -EINVAL;
7095 }
7096 } else
7097 intel_put_shared_dpll(intel_crtc);
7098
7099 if (is_lvds && has_reduced_clock && i915.powersave)
7100 intel_crtc->lowfreq_avail = true;
7101 else
7102 intel_crtc->lowfreq_avail = false;
7103
7104 return 0;
7105 }
7106
7107 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7108 struct intel_link_m_n *m_n)
7109 {
7110 struct drm_device *dev = crtc->base.dev;
7111 struct drm_i915_private *dev_priv = dev->dev_private;
7112 enum pipe pipe = crtc->pipe;
7113
7114 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7115 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7116 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7117 & ~TU_SIZE_MASK;
7118 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7119 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7120 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7121 }
7122
7123 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7124 enum transcoder transcoder,
7125 struct intel_link_m_n *m_n)
7126 {
7127 struct drm_device *dev = crtc->base.dev;
7128 struct drm_i915_private *dev_priv = dev->dev_private;
7129 enum pipe pipe = crtc->pipe;
7130
7131 if (INTEL_INFO(dev)->gen >= 5) {
7132 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7133 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7134 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7135 & ~TU_SIZE_MASK;
7136 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7137 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7138 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7139 } else {
7140 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7141 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7142 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7143 & ~TU_SIZE_MASK;
7144 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7145 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7146 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7147 }
7148 }
7149
7150 void intel_dp_get_m_n(struct intel_crtc *crtc,
7151 struct intel_crtc_config *pipe_config)
7152 {
7153 if (crtc->config.has_pch_encoder)
7154 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7155 else
7156 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7157 &pipe_config->dp_m_n);
7158 }
7159
7160 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7161 struct intel_crtc_config *pipe_config)
7162 {
7163 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7164 &pipe_config->fdi_m_n);
7165 }
7166
7167 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7168 struct intel_crtc_config *pipe_config)
7169 {
7170 struct drm_device *dev = crtc->base.dev;
7171 struct drm_i915_private *dev_priv = dev->dev_private;
7172 uint32_t tmp;
7173
7174 tmp = I915_READ(PF_CTL(crtc->pipe));
7175
7176 if (tmp & PF_ENABLE) {
7177 pipe_config->pch_pfit.enabled = true;
7178 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7179 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7180
7181 /* We currently do not free assignements of panel fitters on
7182 * ivb/hsw (since we don't use the higher upscaling modes which
7183 * differentiates them) so just WARN about this case for now. */
7184 if (IS_GEN7(dev)) {
7185 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7186 PF_PIPE_SEL_IVB(crtc->pipe));
7187 }
7188 }
7189 }
7190
7191 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7192 struct intel_plane_config *plane_config)
7193 {
7194 struct drm_device *dev = crtc->base.dev;
7195 struct drm_i915_private *dev_priv = dev->dev_private;
7196 u32 val, base, offset;
7197 int pipe = crtc->pipe, plane = crtc->plane;
7198 int fourcc, pixel_format;
7199 int aligned_height;
7200
7201 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7202 if (!crtc->base.primary->fb) {
7203 DRM_DEBUG_KMS("failed to alloc fb\n");
7204 return;
7205 }
7206
7207 val = I915_READ(DSPCNTR(plane));
7208
7209 if (INTEL_INFO(dev)->gen >= 4)
7210 if (val & DISPPLANE_TILED)
7211 plane_config->tiled = true;
7212
7213 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7214 fourcc = intel_format_to_fourcc(pixel_format);
7215 crtc->base.primary->fb->pixel_format = fourcc;
7216 crtc->base.primary->fb->bits_per_pixel =
7217 drm_format_plane_cpp(fourcc, 0) * 8;
7218
7219 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7220 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7221 offset = I915_READ(DSPOFFSET(plane));
7222 } else {
7223 if (plane_config->tiled)
7224 offset = I915_READ(DSPTILEOFF(plane));
7225 else
7226 offset = I915_READ(DSPLINOFF(plane));
7227 }
7228 plane_config->base = base;
7229
7230 val = I915_READ(PIPESRC(pipe));
7231 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7232 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7233
7234 val = I915_READ(DSPSTRIDE(pipe));
7235 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7236
7237 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7238 plane_config->tiled);
7239
7240 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7241 aligned_height, PAGE_SIZE);
7242
7243 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7244 pipe, plane, crtc->base.primary->fb->width,
7245 crtc->base.primary->fb->height,
7246 crtc->base.primary->fb->bits_per_pixel, base,
7247 crtc->base.primary->fb->pitches[0],
7248 plane_config->size);
7249 }
7250
7251 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7252 struct intel_crtc_config *pipe_config)
7253 {
7254 struct drm_device *dev = crtc->base.dev;
7255 struct drm_i915_private *dev_priv = dev->dev_private;
7256 uint32_t tmp;
7257
7258 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7259 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7260
7261 tmp = I915_READ(PIPECONF(crtc->pipe));
7262 if (!(tmp & PIPECONF_ENABLE))
7263 return false;
7264
7265 switch (tmp & PIPECONF_BPC_MASK) {
7266 case PIPECONF_6BPC:
7267 pipe_config->pipe_bpp = 18;
7268 break;
7269 case PIPECONF_8BPC:
7270 pipe_config->pipe_bpp = 24;
7271 break;
7272 case PIPECONF_10BPC:
7273 pipe_config->pipe_bpp = 30;
7274 break;
7275 case PIPECONF_12BPC:
7276 pipe_config->pipe_bpp = 36;
7277 break;
7278 default:
7279 break;
7280 }
7281
7282 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7283 pipe_config->limited_color_range = true;
7284
7285 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7286 struct intel_shared_dpll *pll;
7287
7288 pipe_config->has_pch_encoder = true;
7289
7290 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7291 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7292 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7293
7294 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7295
7296 if (HAS_PCH_IBX(dev_priv->dev)) {
7297 pipe_config->shared_dpll =
7298 (enum intel_dpll_id) crtc->pipe;
7299 } else {
7300 tmp = I915_READ(PCH_DPLL_SEL);
7301 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7302 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7303 else
7304 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7305 }
7306
7307 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7308
7309 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7310 &pipe_config->dpll_hw_state));
7311
7312 tmp = pipe_config->dpll_hw_state.dpll;
7313 pipe_config->pixel_multiplier =
7314 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7315 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7316
7317 ironlake_pch_clock_get(crtc, pipe_config);
7318 } else {
7319 pipe_config->pixel_multiplier = 1;
7320 }
7321
7322 intel_get_pipe_timings(crtc, pipe_config);
7323
7324 ironlake_get_pfit_config(crtc, pipe_config);
7325
7326 return true;
7327 }
7328
7329 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7330 {
7331 struct drm_device *dev = dev_priv->dev;
7332 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7333 struct intel_crtc *crtc;
7334
7335 for_each_intel_crtc(dev, crtc)
7336 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7337 pipe_name(crtc->pipe));
7338
7339 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7340 WARN(plls->spll_refcount, "SPLL enabled\n");
7341 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7342 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7343 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7344 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7345 "CPU PWM1 enabled\n");
7346 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7347 "CPU PWM2 enabled\n");
7348 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7349 "PCH PWM1 enabled\n");
7350 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7351 "Utility pin enabled\n");
7352 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7353
7354 /*
7355 * In theory we can still leave IRQs enabled, as long as only the HPD
7356 * interrupts remain enabled. We used to check for that, but since it's
7357 * gen-specific and since we only disable LCPLL after we fully disable
7358 * the interrupts, the check below should be enough.
7359 */
7360 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7361 }
7362
7363 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7364 {
7365 struct drm_device *dev = dev_priv->dev;
7366
7367 if (IS_HASWELL(dev)) {
7368 mutex_lock(&dev_priv->rps.hw_lock);
7369 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7370 val))
7371 DRM_ERROR("Failed to disable D_COMP\n");
7372 mutex_unlock(&dev_priv->rps.hw_lock);
7373 } else {
7374 I915_WRITE(D_COMP, val);
7375 }
7376 POSTING_READ(D_COMP);
7377 }
7378
7379 /*
7380 * This function implements pieces of two sequences from BSpec:
7381 * - Sequence for display software to disable LCPLL
7382 * - Sequence for display software to allow package C8+
7383 * The steps implemented here are just the steps that actually touch the LCPLL
7384 * register. Callers should take care of disabling all the display engine
7385 * functions, doing the mode unset, fixing interrupts, etc.
7386 */
7387 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7388 bool switch_to_fclk, bool allow_power_down)
7389 {
7390 uint32_t val;
7391
7392 assert_can_disable_lcpll(dev_priv);
7393
7394 val = I915_READ(LCPLL_CTL);
7395
7396 if (switch_to_fclk) {
7397 val |= LCPLL_CD_SOURCE_FCLK;
7398 I915_WRITE(LCPLL_CTL, val);
7399
7400 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7401 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7402 DRM_ERROR("Switching to FCLK failed\n");
7403
7404 val = I915_READ(LCPLL_CTL);
7405 }
7406
7407 val |= LCPLL_PLL_DISABLE;
7408 I915_WRITE(LCPLL_CTL, val);
7409 POSTING_READ(LCPLL_CTL);
7410
7411 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7412 DRM_ERROR("LCPLL still locked\n");
7413
7414 val = I915_READ(D_COMP);
7415 val |= D_COMP_COMP_DISABLE;
7416 hsw_write_dcomp(dev_priv, val);
7417 ndelay(100);
7418
7419 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7420 DRM_ERROR("D_COMP RCOMP still in progress\n");
7421
7422 if (allow_power_down) {
7423 val = I915_READ(LCPLL_CTL);
7424 val |= LCPLL_POWER_DOWN_ALLOW;
7425 I915_WRITE(LCPLL_CTL, val);
7426 POSTING_READ(LCPLL_CTL);
7427 }
7428 }
7429
7430 /*
7431 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7432 * source.
7433 */
7434 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7435 {
7436 uint32_t val;
7437 unsigned long irqflags;
7438
7439 val = I915_READ(LCPLL_CTL);
7440
7441 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7442 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7443 return;
7444
7445 /*
7446 * Make sure we're not on PC8 state before disabling PC8, otherwise
7447 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7448 *
7449 * The other problem is that hsw_restore_lcpll() is called as part of
7450 * the runtime PM resume sequence, so we can't just call
7451 * gen6_gt_force_wake_get() because that function calls
7452 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7453 * while we are on the resume sequence. So to solve this problem we have
7454 * to call special forcewake code that doesn't touch runtime PM and
7455 * doesn't enable the forcewake delayed work.
7456 */
7457 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7458 if (dev_priv->uncore.forcewake_count++ == 0)
7459 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7460 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7461
7462 if (val & LCPLL_POWER_DOWN_ALLOW) {
7463 val &= ~LCPLL_POWER_DOWN_ALLOW;
7464 I915_WRITE(LCPLL_CTL, val);
7465 POSTING_READ(LCPLL_CTL);
7466 }
7467
7468 val = I915_READ(D_COMP);
7469 val |= D_COMP_COMP_FORCE;
7470 val &= ~D_COMP_COMP_DISABLE;
7471 hsw_write_dcomp(dev_priv, val);
7472
7473 val = I915_READ(LCPLL_CTL);
7474 val &= ~LCPLL_PLL_DISABLE;
7475 I915_WRITE(LCPLL_CTL, val);
7476
7477 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7478 DRM_ERROR("LCPLL not locked yet\n");
7479
7480 if (val & LCPLL_CD_SOURCE_FCLK) {
7481 val = I915_READ(LCPLL_CTL);
7482 val &= ~LCPLL_CD_SOURCE_FCLK;
7483 I915_WRITE(LCPLL_CTL, val);
7484
7485 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7486 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7487 DRM_ERROR("Switching back to LCPLL failed\n");
7488 }
7489
7490 /* See the big comment above. */
7491 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7492 if (--dev_priv->uncore.forcewake_count == 0)
7493 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7494 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7495 }
7496
7497 /*
7498 * Package states C8 and deeper are really deep PC states that can only be
7499 * reached when all the devices on the system allow it, so even if the graphics
7500 * device allows PC8+, it doesn't mean the system will actually get to these
7501 * states. Our driver only allows PC8+ when going into runtime PM.
7502 *
7503 * The requirements for PC8+ are that all the outputs are disabled, the power
7504 * well is disabled and most interrupts are disabled, and these are also
7505 * requirements for runtime PM. When these conditions are met, we manually do
7506 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7507 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7508 * hang the machine.
7509 *
7510 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7511 * the state of some registers, so when we come back from PC8+ we need to
7512 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7513 * need to take care of the registers kept by RC6. Notice that this happens even
7514 * if we don't put the device in PCI D3 state (which is what currently happens
7515 * because of the runtime PM support).
7516 *
7517 * For more, read "Display Sequences for Package C8" on the hardware
7518 * documentation.
7519 */
7520 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7521 {
7522 struct drm_device *dev = dev_priv->dev;
7523 uint32_t val;
7524
7525 DRM_DEBUG_KMS("Enabling package C8+\n");
7526
7527 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7528 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7529 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7530 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7531 }
7532
7533 lpt_disable_clkout_dp(dev);
7534 hsw_disable_lcpll(dev_priv, true, true);
7535 }
7536
7537 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7538 {
7539 struct drm_device *dev = dev_priv->dev;
7540 uint32_t val;
7541
7542 DRM_DEBUG_KMS("Disabling package C8+\n");
7543
7544 hsw_restore_lcpll(dev_priv);
7545 lpt_init_pch_refclk(dev);
7546
7547 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7548 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7549 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7550 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7551 }
7552
7553 intel_prepare_ddi(dev);
7554 }
7555
7556 static void snb_modeset_global_resources(struct drm_device *dev)
7557 {
7558 modeset_update_crtc_power_domains(dev);
7559 }
7560
7561 static void haswell_modeset_global_resources(struct drm_device *dev)
7562 {
7563 modeset_update_crtc_power_domains(dev);
7564 }
7565
7566 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7567 int x, int y,
7568 struct drm_framebuffer *fb)
7569 {
7570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7571
7572 if (!intel_ddi_pll_select(intel_crtc))
7573 return -EINVAL;
7574 intel_ddi_pll_enable(intel_crtc);
7575
7576 intel_crtc->lowfreq_avail = false;
7577
7578 return 0;
7579 }
7580
7581 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7582 struct intel_crtc_config *pipe_config)
7583 {
7584 struct drm_device *dev = crtc->base.dev;
7585 struct drm_i915_private *dev_priv = dev->dev_private;
7586 enum intel_display_power_domain pfit_domain;
7587 uint32_t tmp;
7588
7589 if (!intel_display_power_enabled(dev_priv,
7590 POWER_DOMAIN_PIPE(crtc->pipe)))
7591 return false;
7592
7593 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7594 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7595
7596 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7597 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7598 enum pipe trans_edp_pipe;
7599 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7600 default:
7601 WARN(1, "unknown pipe linked to edp transcoder\n");
7602 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7603 case TRANS_DDI_EDP_INPUT_A_ON:
7604 trans_edp_pipe = PIPE_A;
7605 break;
7606 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7607 trans_edp_pipe = PIPE_B;
7608 break;
7609 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7610 trans_edp_pipe = PIPE_C;
7611 break;
7612 }
7613
7614 if (trans_edp_pipe == crtc->pipe)
7615 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7616 }
7617
7618 if (!intel_display_power_enabled(dev_priv,
7619 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7620 return false;
7621
7622 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7623 if (!(tmp & PIPECONF_ENABLE))
7624 return false;
7625
7626 /*
7627 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7628 * DDI E. So just check whether this pipe is wired to DDI E and whether
7629 * the PCH transcoder is on.
7630 */
7631 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7632 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7633 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7634 pipe_config->has_pch_encoder = true;
7635
7636 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7637 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7638 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7639
7640 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7641 }
7642
7643 intel_get_pipe_timings(crtc, pipe_config);
7644
7645 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7646 if (intel_display_power_enabled(dev_priv, pfit_domain))
7647 ironlake_get_pfit_config(crtc, pipe_config);
7648
7649 if (IS_HASWELL(dev))
7650 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7651 (I915_READ(IPS_CTL) & IPS_ENABLE);
7652
7653 pipe_config->pixel_multiplier = 1;
7654
7655 return true;
7656 }
7657
7658 static struct {
7659 int clock;
7660 u32 config;
7661 } hdmi_audio_clock[] = {
7662 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7663 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7664 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7665 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7666 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7667 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7668 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7669 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7670 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7671 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7672 };
7673
7674 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7675 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7676 {
7677 int i;
7678
7679 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7680 if (mode->clock == hdmi_audio_clock[i].clock)
7681 break;
7682 }
7683
7684 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7685 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7686 i = 1;
7687 }
7688
7689 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7690 hdmi_audio_clock[i].clock,
7691 hdmi_audio_clock[i].config);
7692
7693 return hdmi_audio_clock[i].config;
7694 }
7695
7696 static bool intel_eld_uptodate(struct drm_connector *connector,
7697 int reg_eldv, uint32_t bits_eldv,
7698 int reg_elda, uint32_t bits_elda,
7699 int reg_edid)
7700 {
7701 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7702 uint8_t *eld = connector->eld;
7703 uint32_t i;
7704
7705 i = I915_READ(reg_eldv);
7706 i &= bits_eldv;
7707
7708 if (!eld[0])
7709 return !i;
7710
7711 if (!i)
7712 return false;
7713
7714 i = I915_READ(reg_elda);
7715 i &= ~bits_elda;
7716 I915_WRITE(reg_elda, i);
7717
7718 for (i = 0; i < eld[2]; i++)
7719 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7720 return false;
7721
7722 return true;
7723 }
7724
7725 static void g4x_write_eld(struct drm_connector *connector,
7726 struct drm_crtc *crtc,
7727 struct drm_display_mode *mode)
7728 {
7729 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7730 uint8_t *eld = connector->eld;
7731 uint32_t eldv;
7732 uint32_t len;
7733 uint32_t i;
7734
7735 i = I915_READ(G4X_AUD_VID_DID);
7736
7737 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7738 eldv = G4X_ELDV_DEVCL_DEVBLC;
7739 else
7740 eldv = G4X_ELDV_DEVCTG;
7741
7742 if (intel_eld_uptodate(connector,
7743 G4X_AUD_CNTL_ST, eldv,
7744 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7745 G4X_HDMIW_HDMIEDID))
7746 return;
7747
7748 i = I915_READ(G4X_AUD_CNTL_ST);
7749 i &= ~(eldv | G4X_ELD_ADDR);
7750 len = (i >> 9) & 0x1f; /* ELD buffer size */
7751 I915_WRITE(G4X_AUD_CNTL_ST, i);
7752
7753 if (!eld[0])
7754 return;
7755
7756 len = min_t(uint8_t, eld[2], len);
7757 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7758 for (i = 0; i < len; i++)
7759 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7760
7761 i = I915_READ(G4X_AUD_CNTL_ST);
7762 i |= eldv;
7763 I915_WRITE(G4X_AUD_CNTL_ST, i);
7764 }
7765
7766 static void haswell_write_eld(struct drm_connector *connector,
7767 struct drm_crtc *crtc,
7768 struct drm_display_mode *mode)
7769 {
7770 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7771 uint8_t *eld = connector->eld;
7772 uint32_t eldv;
7773 uint32_t i;
7774 int len;
7775 int pipe = to_intel_crtc(crtc)->pipe;
7776 int tmp;
7777
7778 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7779 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7780 int aud_config = HSW_AUD_CFG(pipe);
7781 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7782
7783 /* Audio output enable */
7784 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7785 tmp = I915_READ(aud_cntrl_st2);
7786 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7787 I915_WRITE(aud_cntrl_st2, tmp);
7788 POSTING_READ(aud_cntrl_st2);
7789
7790 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7791
7792 /* Set ELD valid state */
7793 tmp = I915_READ(aud_cntrl_st2);
7794 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7795 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7796 I915_WRITE(aud_cntrl_st2, tmp);
7797 tmp = I915_READ(aud_cntrl_st2);
7798 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7799
7800 /* Enable HDMI mode */
7801 tmp = I915_READ(aud_config);
7802 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7803 /* clear N_programing_enable and N_value_index */
7804 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7805 I915_WRITE(aud_config, tmp);
7806
7807 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7808
7809 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7810
7811 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7812 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7813 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7814 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7815 } else {
7816 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7817 }
7818
7819 if (intel_eld_uptodate(connector,
7820 aud_cntrl_st2, eldv,
7821 aud_cntl_st, IBX_ELD_ADDRESS,
7822 hdmiw_hdmiedid))
7823 return;
7824
7825 i = I915_READ(aud_cntrl_st2);
7826 i &= ~eldv;
7827 I915_WRITE(aud_cntrl_st2, i);
7828
7829 if (!eld[0])
7830 return;
7831
7832 i = I915_READ(aud_cntl_st);
7833 i &= ~IBX_ELD_ADDRESS;
7834 I915_WRITE(aud_cntl_st, i);
7835 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7836 DRM_DEBUG_DRIVER("port num:%d\n", i);
7837
7838 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7839 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7840 for (i = 0; i < len; i++)
7841 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7842
7843 i = I915_READ(aud_cntrl_st2);
7844 i |= eldv;
7845 I915_WRITE(aud_cntrl_st2, i);
7846
7847 }
7848
7849 static void ironlake_write_eld(struct drm_connector *connector,
7850 struct drm_crtc *crtc,
7851 struct drm_display_mode *mode)
7852 {
7853 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7854 uint8_t *eld = connector->eld;
7855 uint32_t eldv;
7856 uint32_t i;
7857 int len;
7858 int hdmiw_hdmiedid;
7859 int aud_config;
7860 int aud_cntl_st;
7861 int aud_cntrl_st2;
7862 int pipe = to_intel_crtc(crtc)->pipe;
7863
7864 if (HAS_PCH_IBX(connector->dev)) {
7865 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7866 aud_config = IBX_AUD_CFG(pipe);
7867 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7868 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7869 } else if (IS_VALLEYVIEW(connector->dev)) {
7870 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7871 aud_config = VLV_AUD_CFG(pipe);
7872 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7873 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7874 } else {
7875 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7876 aud_config = CPT_AUD_CFG(pipe);
7877 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7878 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7879 }
7880
7881 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7882
7883 if (IS_VALLEYVIEW(connector->dev)) {
7884 struct intel_encoder *intel_encoder;
7885 struct intel_digital_port *intel_dig_port;
7886
7887 intel_encoder = intel_attached_encoder(connector);
7888 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7889 i = intel_dig_port->port;
7890 } else {
7891 i = I915_READ(aud_cntl_st);
7892 i = (i >> 29) & DIP_PORT_SEL_MASK;
7893 /* DIP_Port_Select, 0x1 = PortB */
7894 }
7895
7896 if (!i) {
7897 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7898 /* operate blindly on all ports */
7899 eldv = IBX_ELD_VALIDB;
7900 eldv |= IBX_ELD_VALIDB << 4;
7901 eldv |= IBX_ELD_VALIDB << 8;
7902 } else {
7903 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7904 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7905 }
7906
7907 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7908 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7909 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7910 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7911 } else {
7912 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7913 }
7914
7915 if (intel_eld_uptodate(connector,
7916 aud_cntrl_st2, eldv,
7917 aud_cntl_st, IBX_ELD_ADDRESS,
7918 hdmiw_hdmiedid))
7919 return;
7920
7921 i = I915_READ(aud_cntrl_st2);
7922 i &= ~eldv;
7923 I915_WRITE(aud_cntrl_st2, i);
7924
7925 if (!eld[0])
7926 return;
7927
7928 i = I915_READ(aud_cntl_st);
7929 i &= ~IBX_ELD_ADDRESS;
7930 I915_WRITE(aud_cntl_st, i);
7931
7932 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7933 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7934 for (i = 0; i < len; i++)
7935 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7936
7937 i = I915_READ(aud_cntrl_st2);
7938 i |= eldv;
7939 I915_WRITE(aud_cntrl_st2, i);
7940 }
7941
7942 void intel_write_eld(struct drm_encoder *encoder,
7943 struct drm_display_mode *mode)
7944 {
7945 struct drm_crtc *crtc = encoder->crtc;
7946 struct drm_connector *connector;
7947 struct drm_device *dev = encoder->dev;
7948 struct drm_i915_private *dev_priv = dev->dev_private;
7949
7950 connector = drm_select_eld(encoder, mode);
7951 if (!connector)
7952 return;
7953
7954 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7955 connector->base.id,
7956 connector->name,
7957 connector->encoder->base.id,
7958 connector->encoder->name);
7959
7960 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7961
7962 if (dev_priv->display.write_eld)
7963 dev_priv->display.write_eld(connector, crtc, mode);
7964 }
7965
7966 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7967 {
7968 struct drm_device *dev = crtc->dev;
7969 struct drm_i915_private *dev_priv = dev->dev_private;
7970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7971 uint32_t cntl;
7972
7973 if (base != intel_crtc->cursor_base) {
7974 /* On these chipsets we can only modify the base whilst
7975 * the cursor is disabled.
7976 */
7977 if (intel_crtc->cursor_cntl) {
7978 I915_WRITE(_CURACNTR, 0);
7979 POSTING_READ(_CURACNTR);
7980 intel_crtc->cursor_cntl = 0;
7981 }
7982
7983 I915_WRITE(_CURABASE, base);
7984 POSTING_READ(_CURABASE);
7985 }
7986
7987 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7988 cntl = 0;
7989 if (base)
7990 cntl = (CURSOR_ENABLE |
7991 CURSOR_GAMMA_ENABLE |
7992 CURSOR_FORMAT_ARGB);
7993 if (intel_crtc->cursor_cntl != cntl) {
7994 I915_WRITE(_CURACNTR, cntl);
7995 POSTING_READ(_CURACNTR);
7996 intel_crtc->cursor_cntl = cntl;
7997 }
7998 }
7999
8000 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8001 {
8002 struct drm_device *dev = crtc->dev;
8003 struct drm_i915_private *dev_priv = dev->dev_private;
8004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8005 int pipe = intel_crtc->pipe;
8006 uint32_t cntl;
8007
8008 cntl = 0;
8009 if (base) {
8010 cntl = MCURSOR_GAMMA_ENABLE;
8011 switch (intel_crtc->cursor_width) {
8012 case 64:
8013 cntl |= CURSOR_MODE_64_ARGB_AX;
8014 break;
8015 case 128:
8016 cntl |= CURSOR_MODE_128_ARGB_AX;
8017 break;
8018 case 256:
8019 cntl |= CURSOR_MODE_256_ARGB_AX;
8020 break;
8021 default:
8022 WARN_ON(1);
8023 return;
8024 }
8025 cntl |= pipe << 28; /* Connect to correct pipe */
8026 }
8027 if (intel_crtc->cursor_cntl != cntl) {
8028 I915_WRITE(CURCNTR(pipe), cntl);
8029 POSTING_READ(CURCNTR(pipe));
8030 intel_crtc->cursor_cntl = cntl;
8031 }
8032
8033 /* and commit changes on next vblank */
8034 I915_WRITE(CURBASE(pipe), base);
8035 POSTING_READ(CURBASE(pipe));
8036 }
8037
8038 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8039 {
8040 struct drm_device *dev = crtc->dev;
8041 struct drm_i915_private *dev_priv = dev->dev_private;
8042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8043 int pipe = intel_crtc->pipe;
8044 uint32_t cntl;
8045
8046 cntl = 0;
8047 if (base) {
8048 cntl = MCURSOR_GAMMA_ENABLE;
8049 switch (intel_crtc->cursor_width) {
8050 case 64:
8051 cntl |= CURSOR_MODE_64_ARGB_AX;
8052 break;
8053 case 128:
8054 cntl |= CURSOR_MODE_128_ARGB_AX;
8055 break;
8056 case 256:
8057 cntl |= CURSOR_MODE_256_ARGB_AX;
8058 break;
8059 default:
8060 WARN_ON(1);
8061 return;
8062 }
8063 }
8064 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8065 cntl |= CURSOR_PIPE_CSC_ENABLE;
8066
8067 if (intel_crtc->cursor_cntl != cntl) {
8068 I915_WRITE(CURCNTR(pipe), cntl);
8069 POSTING_READ(CURCNTR(pipe));
8070 intel_crtc->cursor_cntl = cntl;
8071 }
8072
8073 /* and commit changes on next vblank */
8074 I915_WRITE(CURBASE(pipe), base);
8075 POSTING_READ(CURBASE(pipe));
8076 }
8077
8078 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8079 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8080 bool on)
8081 {
8082 struct drm_device *dev = crtc->dev;
8083 struct drm_i915_private *dev_priv = dev->dev_private;
8084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8085 int pipe = intel_crtc->pipe;
8086 int x = crtc->cursor_x;
8087 int y = crtc->cursor_y;
8088 u32 base = 0, pos = 0;
8089
8090 if (on)
8091 base = intel_crtc->cursor_addr;
8092
8093 if (x >= intel_crtc->config.pipe_src_w)
8094 base = 0;
8095
8096 if (y >= intel_crtc->config.pipe_src_h)
8097 base = 0;
8098
8099 if (x < 0) {
8100 if (x + intel_crtc->cursor_width <= 0)
8101 base = 0;
8102
8103 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8104 x = -x;
8105 }
8106 pos |= x << CURSOR_X_SHIFT;
8107
8108 if (y < 0) {
8109 if (y + intel_crtc->cursor_height <= 0)
8110 base = 0;
8111
8112 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8113 y = -y;
8114 }
8115 pos |= y << CURSOR_Y_SHIFT;
8116
8117 if (base == 0 && intel_crtc->cursor_base == 0)
8118 return;
8119
8120 I915_WRITE(CURPOS(pipe), pos);
8121
8122 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8123 ivb_update_cursor(crtc, base);
8124 else if (IS_845G(dev) || IS_I865G(dev))
8125 i845_update_cursor(crtc, base);
8126 else
8127 i9xx_update_cursor(crtc, base);
8128 intel_crtc->cursor_base = base;
8129 }
8130
8131 /*
8132 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8133 *
8134 * Note that the object's reference will be consumed if the update fails. If
8135 * the update succeeds, the reference of the old object (if any) will be
8136 * consumed.
8137 */
8138 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8139 struct drm_i915_gem_object *obj,
8140 uint32_t width, uint32_t height)
8141 {
8142 struct drm_device *dev = crtc->dev;
8143 struct drm_i915_private *dev_priv = dev->dev_private;
8144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8145 enum pipe pipe = intel_crtc->pipe;
8146 unsigned old_width;
8147 uint32_t addr;
8148 int ret;
8149
8150 /* if we want to turn off the cursor ignore width and height */
8151 if (!obj) {
8152 DRM_DEBUG_KMS("cursor off\n");
8153 addr = 0;
8154 obj = NULL;
8155 mutex_lock(&dev->struct_mutex);
8156 goto finish;
8157 }
8158
8159 /* Check for which cursor types we support */
8160 if (!((width == 64 && height == 64) ||
8161 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8162 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8163 DRM_DEBUG("Cursor dimension not supported\n");
8164 return -EINVAL;
8165 }
8166
8167 if (obj->base.size < width * height * 4) {
8168 DRM_DEBUG_KMS("buffer is too small\n");
8169 ret = -ENOMEM;
8170 goto fail;
8171 }
8172
8173 /* we only need to pin inside GTT if cursor is non-phy */
8174 mutex_lock(&dev->struct_mutex);
8175 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8176 unsigned alignment;
8177
8178 if (obj->tiling_mode) {
8179 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8180 ret = -EINVAL;
8181 goto fail_locked;
8182 }
8183
8184 /* Note that the w/a also requires 2 PTE of padding following
8185 * the bo. We currently fill all unused PTE with the shadow
8186 * page and so we should always have valid PTE following the
8187 * cursor preventing the VT-d warning.
8188 */
8189 alignment = 0;
8190 if (need_vtd_wa(dev))
8191 alignment = 64*1024;
8192
8193 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8194 if (ret) {
8195 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8196 goto fail_locked;
8197 }
8198
8199 ret = i915_gem_object_put_fence(obj);
8200 if (ret) {
8201 DRM_DEBUG_KMS("failed to release fence for cursor");
8202 goto fail_unpin;
8203 }
8204
8205 addr = i915_gem_obj_ggtt_offset(obj);
8206 } else {
8207 int align = IS_I830(dev) ? 16 * 1024 : 256;
8208 ret = i915_gem_object_attach_phys(obj, align);
8209 if (ret) {
8210 DRM_DEBUG_KMS("failed to attach phys object\n");
8211 goto fail_locked;
8212 }
8213 addr = obj->phys_handle->busaddr;
8214 }
8215
8216 if (IS_GEN2(dev))
8217 I915_WRITE(CURSIZE, (height << 12) | width);
8218
8219 finish:
8220 if (intel_crtc->cursor_bo) {
8221 if (!INTEL_INFO(dev)->cursor_needs_physical)
8222 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8223 }
8224
8225 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8226 INTEL_FRONTBUFFER_CURSOR(pipe));
8227 mutex_unlock(&dev->struct_mutex);
8228
8229 old_width = intel_crtc->cursor_width;
8230
8231 intel_crtc->cursor_addr = addr;
8232 intel_crtc->cursor_bo = obj;
8233 intel_crtc->cursor_width = width;
8234 intel_crtc->cursor_height = height;
8235
8236 if (intel_crtc->active) {
8237 if (old_width != width)
8238 intel_update_watermarks(crtc);
8239 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8240 }
8241
8242 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8243
8244 return 0;
8245 fail_unpin:
8246 i915_gem_object_unpin_from_display_plane(obj);
8247 fail_locked:
8248 mutex_unlock(&dev->struct_mutex);
8249 fail:
8250 drm_gem_object_unreference_unlocked(&obj->base);
8251 return ret;
8252 }
8253
8254 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8255 u16 *blue, uint32_t start, uint32_t size)
8256 {
8257 int end = (start + size > 256) ? 256 : start + size, i;
8258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8259
8260 for (i = start; i < end; i++) {
8261 intel_crtc->lut_r[i] = red[i] >> 8;
8262 intel_crtc->lut_g[i] = green[i] >> 8;
8263 intel_crtc->lut_b[i] = blue[i] >> 8;
8264 }
8265
8266 intel_crtc_load_lut(crtc);
8267 }
8268
8269 /* VESA 640x480x72Hz mode to set on the pipe */
8270 static struct drm_display_mode load_detect_mode = {
8271 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8272 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8273 };
8274
8275 struct drm_framebuffer *
8276 __intel_framebuffer_create(struct drm_device *dev,
8277 struct drm_mode_fb_cmd2 *mode_cmd,
8278 struct drm_i915_gem_object *obj)
8279 {
8280 struct intel_framebuffer *intel_fb;
8281 int ret;
8282
8283 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8284 if (!intel_fb) {
8285 drm_gem_object_unreference_unlocked(&obj->base);
8286 return ERR_PTR(-ENOMEM);
8287 }
8288
8289 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8290 if (ret)
8291 goto err;
8292
8293 return &intel_fb->base;
8294 err:
8295 drm_gem_object_unreference_unlocked(&obj->base);
8296 kfree(intel_fb);
8297
8298 return ERR_PTR(ret);
8299 }
8300
8301 static struct drm_framebuffer *
8302 intel_framebuffer_create(struct drm_device *dev,
8303 struct drm_mode_fb_cmd2 *mode_cmd,
8304 struct drm_i915_gem_object *obj)
8305 {
8306 struct drm_framebuffer *fb;
8307 int ret;
8308
8309 ret = i915_mutex_lock_interruptible(dev);
8310 if (ret)
8311 return ERR_PTR(ret);
8312 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8313 mutex_unlock(&dev->struct_mutex);
8314
8315 return fb;
8316 }
8317
8318 static u32
8319 intel_framebuffer_pitch_for_width(int width, int bpp)
8320 {
8321 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8322 return ALIGN(pitch, 64);
8323 }
8324
8325 static u32
8326 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8327 {
8328 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8329 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8330 }
8331
8332 static struct drm_framebuffer *
8333 intel_framebuffer_create_for_mode(struct drm_device *dev,
8334 struct drm_display_mode *mode,
8335 int depth, int bpp)
8336 {
8337 struct drm_i915_gem_object *obj;
8338 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8339
8340 obj = i915_gem_alloc_object(dev,
8341 intel_framebuffer_size_for_mode(mode, bpp));
8342 if (obj == NULL)
8343 return ERR_PTR(-ENOMEM);
8344
8345 mode_cmd.width = mode->hdisplay;
8346 mode_cmd.height = mode->vdisplay;
8347 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8348 bpp);
8349 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8350
8351 return intel_framebuffer_create(dev, &mode_cmd, obj);
8352 }
8353
8354 static struct drm_framebuffer *
8355 mode_fits_in_fbdev(struct drm_device *dev,
8356 struct drm_display_mode *mode)
8357 {
8358 #ifdef CONFIG_DRM_I915_FBDEV
8359 struct drm_i915_private *dev_priv = dev->dev_private;
8360 struct drm_i915_gem_object *obj;
8361 struct drm_framebuffer *fb;
8362
8363 if (!dev_priv->fbdev)
8364 return NULL;
8365
8366 if (!dev_priv->fbdev->fb)
8367 return NULL;
8368
8369 obj = dev_priv->fbdev->fb->obj;
8370 BUG_ON(!obj);
8371
8372 fb = &dev_priv->fbdev->fb->base;
8373 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8374 fb->bits_per_pixel))
8375 return NULL;
8376
8377 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8378 return NULL;
8379
8380 return fb;
8381 #else
8382 return NULL;
8383 #endif
8384 }
8385
8386 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8387 struct drm_display_mode *mode,
8388 struct intel_load_detect_pipe *old,
8389 struct drm_modeset_acquire_ctx *ctx)
8390 {
8391 struct intel_crtc *intel_crtc;
8392 struct intel_encoder *intel_encoder =
8393 intel_attached_encoder(connector);
8394 struct drm_crtc *possible_crtc;
8395 struct drm_encoder *encoder = &intel_encoder->base;
8396 struct drm_crtc *crtc = NULL;
8397 struct drm_device *dev = encoder->dev;
8398 struct drm_framebuffer *fb;
8399 struct drm_mode_config *config = &dev->mode_config;
8400 int ret, i = -1;
8401
8402 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8403 connector->base.id, connector->name,
8404 encoder->base.id, encoder->name);
8405
8406 drm_modeset_acquire_init(ctx, 0);
8407
8408 retry:
8409 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8410 if (ret)
8411 goto fail_unlock;
8412
8413 /*
8414 * Algorithm gets a little messy:
8415 *
8416 * - if the connector already has an assigned crtc, use it (but make
8417 * sure it's on first)
8418 *
8419 * - try to find the first unused crtc that can drive this connector,
8420 * and use that if we find one
8421 */
8422
8423 /* See if we already have a CRTC for this connector */
8424 if (encoder->crtc) {
8425 crtc = encoder->crtc;
8426
8427 ret = drm_modeset_lock(&crtc->mutex, ctx);
8428 if (ret)
8429 goto fail_unlock;
8430
8431 old->dpms_mode = connector->dpms;
8432 old->load_detect_temp = false;
8433
8434 /* Make sure the crtc and connector are running */
8435 if (connector->dpms != DRM_MODE_DPMS_ON)
8436 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8437
8438 return true;
8439 }
8440
8441 /* Find an unused one (if possible) */
8442 for_each_crtc(dev, possible_crtc) {
8443 i++;
8444 if (!(encoder->possible_crtcs & (1 << i)))
8445 continue;
8446 if (!possible_crtc->enabled) {
8447 crtc = possible_crtc;
8448 break;
8449 }
8450 }
8451
8452 /*
8453 * If we didn't find an unused CRTC, don't use any.
8454 */
8455 if (!crtc) {
8456 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8457 goto fail_unlock;
8458 }
8459
8460 ret = drm_modeset_lock(&crtc->mutex, ctx);
8461 if (ret)
8462 goto fail_unlock;
8463 intel_encoder->new_crtc = to_intel_crtc(crtc);
8464 to_intel_connector(connector)->new_encoder = intel_encoder;
8465
8466 intel_crtc = to_intel_crtc(crtc);
8467 intel_crtc->new_enabled = true;
8468 intel_crtc->new_config = &intel_crtc->config;
8469 old->dpms_mode = connector->dpms;
8470 old->load_detect_temp = true;
8471 old->release_fb = NULL;
8472
8473 if (!mode)
8474 mode = &load_detect_mode;
8475
8476 /* We need a framebuffer large enough to accommodate all accesses
8477 * that the plane may generate whilst we perform load detection.
8478 * We can not rely on the fbcon either being present (we get called
8479 * during its initialisation to detect all boot displays, or it may
8480 * not even exist) or that it is large enough to satisfy the
8481 * requested mode.
8482 */
8483 fb = mode_fits_in_fbdev(dev, mode);
8484 if (fb == NULL) {
8485 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8486 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8487 old->release_fb = fb;
8488 } else
8489 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8490 if (IS_ERR(fb)) {
8491 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8492 goto fail;
8493 }
8494
8495 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8496 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8497 if (old->release_fb)
8498 old->release_fb->funcs->destroy(old->release_fb);
8499 goto fail;
8500 }
8501
8502 /* let the connector get through one full cycle before testing */
8503 intel_wait_for_vblank(dev, intel_crtc->pipe);
8504 return true;
8505
8506 fail:
8507 intel_crtc->new_enabled = crtc->enabled;
8508 if (intel_crtc->new_enabled)
8509 intel_crtc->new_config = &intel_crtc->config;
8510 else
8511 intel_crtc->new_config = NULL;
8512 fail_unlock:
8513 if (ret == -EDEADLK) {
8514 drm_modeset_backoff(ctx);
8515 goto retry;
8516 }
8517
8518 drm_modeset_drop_locks(ctx);
8519 drm_modeset_acquire_fini(ctx);
8520
8521 return false;
8522 }
8523
8524 void intel_release_load_detect_pipe(struct drm_connector *connector,
8525 struct intel_load_detect_pipe *old,
8526 struct drm_modeset_acquire_ctx *ctx)
8527 {
8528 struct intel_encoder *intel_encoder =
8529 intel_attached_encoder(connector);
8530 struct drm_encoder *encoder = &intel_encoder->base;
8531 struct drm_crtc *crtc = encoder->crtc;
8532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8533
8534 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8535 connector->base.id, connector->name,
8536 encoder->base.id, encoder->name);
8537
8538 if (old->load_detect_temp) {
8539 to_intel_connector(connector)->new_encoder = NULL;
8540 intel_encoder->new_crtc = NULL;
8541 intel_crtc->new_enabled = false;
8542 intel_crtc->new_config = NULL;
8543 intel_set_mode(crtc, NULL, 0, 0, NULL);
8544
8545 if (old->release_fb) {
8546 drm_framebuffer_unregister_private(old->release_fb);
8547 drm_framebuffer_unreference(old->release_fb);
8548 }
8549
8550 goto unlock;
8551 return;
8552 }
8553
8554 /* Switch crtc and encoder back off if necessary */
8555 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8556 connector->funcs->dpms(connector, old->dpms_mode);
8557
8558 unlock:
8559 drm_modeset_drop_locks(ctx);
8560 drm_modeset_acquire_fini(ctx);
8561 }
8562
8563 static int i9xx_pll_refclk(struct drm_device *dev,
8564 const struct intel_crtc_config *pipe_config)
8565 {
8566 struct drm_i915_private *dev_priv = dev->dev_private;
8567 u32 dpll = pipe_config->dpll_hw_state.dpll;
8568
8569 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8570 return dev_priv->vbt.lvds_ssc_freq;
8571 else if (HAS_PCH_SPLIT(dev))
8572 return 120000;
8573 else if (!IS_GEN2(dev))
8574 return 96000;
8575 else
8576 return 48000;
8577 }
8578
8579 /* Returns the clock of the currently programmed mode of the given pipe. */
8580 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8581 struct intel_crtc_config *pipe_config)
8582 {
8583 struct drm_device *dev = crtc->base.dev;
8584 struct drm_i915_private *dev_priv = dev->dev_private;
8585 int pipe = pipe_config->cpu_transcoder;
8586 u32 dpll = pipe_config->dpll_hw_state.dpll;
8587 u32 fp;
8588 intel_clock_t clock;
8589 int refclk = i9xx_pll_refclk(dev, pipe_config);
8590
8591 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8592 fp = pipe_config->dpll_hw_state.fp0;
8593 else
8594 fp = pipe_config->dpll_hw_state.fp1;
8595
8596 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8597 if (IS_PINEVIEW(dev)) {
8598 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8599 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8600 } else {
8601 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8602 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8603 }
8604
8605 if (!IS_GEN2(dev)) {
8606 if (IS_PINEVIEW(dev))
8607 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8608 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8609 else
8610 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8611 DPLL_FPA01_P1_POST_DIV_SHIFT);
8612
8613 switch (dpll & DPLL_MODE_MASK) {
8614 case DPLLB_MODE_DAC_SERIAL:
8615 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8616 5 : 10;
8617 break;
8618 case DPLLB_MODE_LVDS:
8619 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8620 7 : 14;
8621 break;
8622 default:
8623 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8624 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8625 return;
8626 }
8627
8628 if (IS_PINEVIEW(dev))
8629 pineview_clock(refclk, &clock);
8630 else
8631 i9xx_clock(refclk, &clock);
8632 } else {
8633 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8634 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8635
8636 if (is_lvds) {
8637 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8638 DPLL_FPA01_P1_POST_DIV_SHIFT);
8639
8640 if (lvds & LVDS_CLKB_POWER_UP)
8641 clock.p2 = 7;
8642 else
8643 clock.p2 = 14;
8644 } else {
8645 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8646 clock.p1 = 2;
8647 else {
8648 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8649 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8650 }
8651 if (dpll & PLL_P2_DIVIDE_BY_4)
8652 clock.p2 = 4;
8653 else
8654 clock.p2 = 2;
8655 }
8656
8657 i9xx_clock(refclk, &clock);
8658 }
8659
8660 /*
8661 * This value includes pixel_multiplier. We will use
8662 * port_clock to compute adjusted_mode.crtc_clock in the
8663 * encoder's get_config() function.
8664 */
8665 pipe_config->port_clock = clock.dot;
8666 }
8667
8668 int intel_dotclock_calculate(int link_freq,
8669 const struct intel_link_m_n *m_n)
8670 {
8671 /*
8672 * The calculation for the data clock is:
8673 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8674 * But we want to avoid losing precison if possible, so:
8675 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8676 *
8677 * and the link clock is simpler:
8678 * link_clock = (m * link_clock) / n
8679 */
8680
8681 if (!m_n->link_n)
8682 return 0;
8683
8684 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8685 }
8686
8687 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8688 struct intel_crtc_config *pipe_config)
8689 {
8690 struct drm_device *dev = crtc->base.dev;
8691
8692 /* read out port_clock from the DPLL */
8693 i9xx_crtc_clock_get(crtc, pipe_config);
8694
8695 /*
8696 * This value does not include pixel_multiplier.
8697 * We will check that port_clock and adjusted_mode.crtc_clock
8698 * agree once we know their relationship in the encoder's
8699 * get_config() function.
8700 */
8701 pipe_config->adjusted_mode.crtc_clock =
8702 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8703 &pipe_config->fdi_m_n);
8704 }
8705
8706 /** Returns the currently programmed mode of the given pipe. */
8707 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8708 struct drm_crtc *crtc)
8709 {
8710 struct drm_i915_private *dev_priv = dev->dev_private;
8711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8712 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8713 struct drm_display_mode *mode;
8714 struct intel_crtc_config pipe_config;
8715 int htot = I915_READ(HTOTAL(cpu_transcoder));
8716 int hsync = I915_READ(HSYNC(cpu_transcoder));
8717 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8718 int vsync = I915_READ(VSYNC(cpu_transcoder));
8719 enum pipe pipe = intel_crtc->pipe;
8720
8721 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8722 if (!mode)
8723 return NULL;
8724
8725 /*
8726 * Construct a pipe_config sufficient for getting the clock info
8727 * back out of crtc_clock_get.
8728 *
8729 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8730 * to use a real value here instead.
8731 */
8732 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8733 pipe_config.pixel_multiplier = 1;
8734 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8735 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8736 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8737 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8738
8739 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8740 mode->hdisplay = (htot & 0xffff) + 1;
8741 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8742 mode->hsync_start = (hsync & 0xffff) + 1;
8743 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8744 mode->vdisplay = (vtot & 0xffff) + 1;
8745 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8746 mode->vsync_start = (vsync & 0xffff) + 1;
8747 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8748
8749 drm_mode_set_name(mode);
8750
8751 return mode;
8752 }
8753
8754 static void intel_increase_pllclock(struct drm_device *dev,
8755 enum pipe pipe)
8756 {
8757 struct drm_i915_private *dev_priv = dev->dev_private;
8758 int dpll_reg = DPLL(pipe);
8759 int dpll;
8760
8761 if (HAS_PCH_SPLIT(dev))
8762 return;
8763
8764 if (!dev_priv->lvds_downclock_avail)
8765 return;
8766
8767 dpll = I915_READ(dpll_reg);
8768 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8769 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8770
8771 assert_panel_unlocked(dev_priv, pipe);
8772
8773 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8774 I915_WRITE(dpll_reg, dpll);
8775 intel_wait_for_vblank(dev, pipe);
8776
8777 dpll = I915_READ(dpll_reg);
8778 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8779 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8780 }
8781 }
8782
8783 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8784 {
8785 struct drm_device *dev = crtc->dev;
8786 struct drm_i915_private *dev_priv = dev->dev_private;
8787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8788
8789 if (HAS_PCH_SPLIT(dev))
8790 return;
8791
8792 if (!dev_priv->lvds_downclock_avail)
8793 return;
8794
8795 /*
8796 * Since this is called by a timer, we should never get here in
8797 * the manual case.
8798 */
8799 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8800 int pipe = intel_crtc->pipe;
8801 int dpll_reg = DPLL(pipe);
8802 int dpll;
8803
8804 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8805
8806 assert_panel_unlocked(dev_priv, pipe);
8807
8808 dpll = I915_READ(dpll_reg);
8809 dpll |= DISPLAY_RATE_SELECT_FPA1;
8810 I915_WRITE(dpll_reg, dpll);
8811 intel_wait_for_vblank(dev, pipe);
8812 dpll = I915_READ(dpll_reg);
8813 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8814 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8815 }
8816
8817 }
8818
8819 void intel_mark_busy(struct drm_device *dev)
8820 {
8821 struct drm_i915_private *dev_priv = dev->dev_private;
8822
8823 if (dev_priv->mm.busy)
8824 return;
8825
8826 intel_runtime_pm_get(dev_priv);
8827 i915_update_gfx_val(dev_priv);
8828 dev_priv->mm.busy = true;
8829 }
8830
8831 void intel_mark_idle(struct drm_device *dev)
8832 {
8833 struct drm_i915_private *dev_priv = dev->dev_private;
8834 struct drm_crtc *crtc;
8835
8836 if (!dev_priv->mm.busy)
8837 return;
8838
8839 dev_priv->mm.busy = false;
8840
8841 if (!i915.powersave)
8842 goto out;
8843
8844 for_each_crtc(dev, crtc) {
8845 if (!crtc->primary->fb)
8846 continue;
8847
8848 intel_decrease_pllclock(crtc);
8849 }
8850
8851 if (INTEL_INFO(dev)->gen >= 6)
8852 gen6_rps_idle(dev->dev_private);
8853
8854 out:
8855 intel_runtime_pm_put(dev_priv);
8856 }
8857
8858
8859 /**
8860 * intel_mark_fb_busy - mark given planes as busy
8861 * @dev: DRM device
8862 * @frontbuffer_bits: bits for the affected planes
8863 * @ring: optional ring for asynchronous commands
8864 *
8865 * This function gets called every time the screen contents change. It can be
8866 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8867 */
8868 static void intel_mark_fb_busy(struct drm_device *dev,
8869 unsigned frontbuffer_bits,
8870 struct intel_engine_cs *ring)
8871 {
8872 enum pipe pipe;
8873
8874 if (!i915.powersave)
8875 return;
8876
8877 for_each_pipe(pipe) {
8878 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8879 continue;
8880
8881 intel_increase_pllclock(dev, pipe);
8882 if (ring && intel_fbc_enabled(dev))
8883 ring->fbc_dirty = true;
8884 }
8885 }
8886
8887 /**
8888 * intel_fb_obj_invalidate - invalidate frontbuffer object
8889 * @obj: GEM object to invalidate
8890 * @ring: set for asynchronous rendering
8891 *
8892 * This function gets called every time rendering on the given object starts and
8893 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8894 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8895 * until the rendering completes or a flip on this frontbuffer plane is
8896 * scheduled.
8897 */
8898 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8899 struct intel_engine_cs *ring)
8900 {
8901 struct drm_device *dev = obj->base.dev;
8902 struct drm_i915_private *dev_priv = dev->dev_private;
8903
8904 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8905
8906 if (!obj->frontbuffer_bits)
8907 return;
8908
8909 if (ring) {
8910 mutex_lock(&dev_priv->fb_tracking.lock);
8911 dev_priv->fb_tracking.busy_bits
8912 |= obj->frontbuffer_bits;
8913 dev_priv->fb_tracking.flip_bits
8914 &= ~obj->frontbuffer_bits;
8915 mutex_unlock(&dev_priv->fb_tracking.lock);
8916 }
8917
8918 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8919
8920 intel_edp_psr_exit(dev);
8921 }
8922
8923 /**
8924 * intel_frontbuffer_flush - flush frontbuffer
8925 * @dev: DRM device
8926 * @frontbuffer_bits: frontbuffer plane tracking bits
8927 *
8928 * This function gets called every time rendering on the given planes has
8929 * completed and frontbuffer caching can be started again. Flushes will get
8930 * delayed if they're blocked by some oustanding asynchronous rendering.
8931 *
8932 * Can be called without any locks held.
8933 */
8934 void intel_frontbuffer_flush(struct drm_device *dev,
8935 unsigned frontbuffer_bits)
8936 {
8937 struct drm_i915_private *dev_priv = dev->dev_private;
8938
8939 /* Delay flushing when rings are still busy.*/
8940 mutex_lock(&dev_priv->fb_tracking.lock);
8941 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
8942 mutex_unlock(&dev_priv->fb_tracking.lock);
8943
8944 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
8945
8946 intel_edp_psr_exit(dev);
8947 }
8948
8949 /**
8950 * intel_fb_obj_flush - flush frontbuffer object
8951 * @obj: GEM object to flush
8952 * @retire: set when retiring asynchronous rendering
8953 *
8954 * This function gets called every time rendering on the given object has
8955 * completed and frontbuffer caching can be started again. If @retire is true
8956 * then any delayed flushes will be unblocked.
8957 */
8958 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
8959 bool retire)
8960 {
8961 struct drm_device *dev = obj->base.dev;
8962 struct drm_i915_private *dev_priv = dev->dev_private;
8963 unsigned frontbuffer_bits;
8964
8965 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8966
8967 if (!obj->frontbuffer_bits)
8968 return;
8969
8970 frontbuffer_bits = obj->frontbuffer_bits;
8971
8972 if (retire) {
8973 mutex_lock(&dev_priv->fb_tracking.lock);
8974 /* Filter out new bits since rendering started. */
8975 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
8976
8977 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
8978 mutex_unlock(&dev_priv->fb_tracking.lock);
8979 }
8980
8981 intel_frontbuffer_flush(dev, frontbuffer_bits);
8982 }
8983
8984 /**
8985 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
8986 * @dev: DRM device
8987 * @frontbuffer_bits: frontbuffer plane tracking bits
8988 *
8989 * This function gets called after scheduling a flip on @obj. The actual
8990 * frontbuffer flushing will be delayed until completion is signalled with
8991 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
8992 * flush will be cancelled.
8993 *
8994 * Can be called without any locks held.
8995 */
8996 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
8997 unsigned frontbuffer_bits)
8998 {
8999 struct drm_i915_private *dev_priv = dev->dev_private;
9000
9001 mutex_lock(&dev_priv->fb_tracking.lock);
9002 dev_priv->fb_tracking.flip_bits
9003 |= frontbuffer_bits;
9004 mutex_unlock(&dev_priv->fb_tracking.lock);
9005 }
9006
9007 /**
9008 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9009 * @dev: DRM device
9010 * @frontbuffer_bits: frontbuffer plane tracking bits
9011 *
9012 * This function gets called after the flip has been latched and will complete
9013 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9014 *
9015 * Can be called without any locks held.
9016 */
9017 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9018 unsigned frontbuffer_bits)
9019 {
9020 struct drm_i915_private *dev_priv = dev->dev_private;
9021
9022 mutex_lock(&dev_priv->fb_tracking.lock);
9023 /* Mask any cancelled flips. */
9024 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9025 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9026 mutex_unlock(&dev_priv->fb_tracking.lock);
9027
9028 intel_frontbuffer_flush(dev, frontbuffer_bits);
9029 }
9030
9031 static void intel_crtc_destroy(struct drm_crtc *crtc)
9032 {
9033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9034 struct drm_device *dev = crtc->dev;
9035 struct intel_unpin_work *work;
9036 unsigned long flags;
9037
9038 spin_lock_irqsave(&dev->event_lock, flags);
9039 work = intel_crtc->unpin_work;
9040 intel_crtc->unpin_work = NULL;
9041 spin_unlock_irqrestore(&dev->event_lock, flags);
9042
9043 if (work) {
9044 cancel_work_sync(&work->work);
9045 kfree(work);
9046 }
9047
9048 drm_crtc_cleanup(crtc);
9049
9050 kfree(intel_crtc);
9051 }
9052
9053 static void intel_unpin_work_fn(struct work_struct *__work)
9054 {
9055 struct intel_unpin_work *work =
9056 container_of(__work, struct intel_unpin_work, work);
9057 struct drm_device *dev = work->crtc->dev;
9058 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9059
9060 mutex_lock(&dev->struct_mutex);
9061 intel_unpin_fb_obj(work->old_fb_obj);
9062 drm_gem_object_unreference(&work->pending_flip_obj->base);
9063 drm_gem_object_unreference(&work->old_fb_obj->base);
9064
9065 intel_update_fbc(dev);
9066 mutex_unlock(&dev->struct_mutex);
9067
9068 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9069
9070 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9071 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9072
9073 kfree(work);
9074 }
9075
9076 static void do_intel_finish_page_flip(struct drm_device *dev,
9077 struct drm_crtc *crtc)
9078 {
9079 struct drm_i915_private *dev_priv = dev->dev_private;
9080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9081 struct intel_unpin_work *work;
9082 unsigned long flags;
9083
9084 /* Ignore early vblank irqs */
9085 if (intel_crtc == NULL)
9086 return;
9087
9088 spin_lock_irqsave(&dev->event_lock, flags);
9089 work = intel_crtc->unpin_work;
9090
9091 /* Ensure we don't miss a work->pending update ... */
9092 smp_rmb();
9093
9094 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9095 spin_unlock_irqrestore(&dev->event_lock, flags);
9096 return;
9097 }
9098
9099 /* and that the unpin work is consistent wrt ->pending. */
9100 smp_rmb();
9101
9102 intel_crtc->unpin_work = NULL;
9103
9104 if (work->event)
9105 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9106
9107 drm_crtc_vblank_put(crtc);
9108
9109 spin_unlock_irqrestore(&dev->event_lock, flags);
9110
9111 wake_up_all(&dev_priv->pending_flip_queue);
9112
9113 queue_work(dev_priv->wq, &work->work);
9114
9115 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9116 }
9117
9118 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9119 {
9120 struct drm_i915_private *dev_priv = dev->dev_private;
9121 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9122
9123 do_intel_finish_page_flip(dev, crtc);
9124 }
9125
9126 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9127 {
9128 struct drm_i915_private *dev_priv = dev->dev_private;
9129 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9130
9131 do_intel_finish_page_flip(dev, crtc);
9132 }
9133
9134 /* Is 'a' after or equal to 'b'? */
9135 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9136 {
9137 return !((a - b) & 0x80000000);
9138 }
9139
9140 static bool page_flip_finished(struct intel_crtc *crtc)
9141 {
9142 struct drm_device *dev = crtc->base.dev;
9143 struct drm_i915_private *dev_priv = dev->dev_private;
9144
9145 /*
9146 * The relevant registers doen't exist on pre-ctg.
9147 * As the flip done interrupt doesn't trigger for mmio
9148 * flips on gmch platforms, a flip count check isn't
9149 * really needed there. But since ctg has the registers,
9150 * include it in the check anyway.
9151 */
9152 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9153 return true;
9154
9155 /*
9156 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9157 * used the same base address. In that case the mmio flip might
9158 * have completed, but the CS hasn't even executed the flip yet.
9159 *
9160 * A flip count check isn't enough as the CS might have updated
9161 * the base address just after start of vblank, but before we
9162 * managed to process the interrupt. This means we'd complete the
9163 * CS flip too soon.
9164 *
9165 * Combining both checks should get us a good enough result. It may
9166 * still happen that the CS flip has been executed, but has not
9167 * yet actually completed. But in case the base address is the same
9168 * anyway, we don't really care.
9169 */
9170 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9171 crtc->unpin_work->gtt_offset &&
9172 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9173 crtc->unpin_work->flip_count);
9174 }
9175
9176 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9177 {
9178 struct drm_i915_private *dev_priv = dev->dev_private;
9179 struct intel_crtc *intel_crtc =
9180 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9181 unsigned long flags;
9182
9183 /* NB: An MMIO update of the plane base pointer will also
9184 * generate a page-flip completion irq, i.e. every modeset
9185 * is also accompanied by a spurious intel_prepare_page_flip().
9186 */
9187 spin_lock_irqsave(&dev->event_lock, flags);
9188 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9189 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9190 spin_unlock_irqrestore(&dev->event_lock, flags);
9191 }
9192
9193 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9194 {
9195 /* Ensure that the work item is consistent when activating it ... */
9196 smp_wmb();
9197 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9198 /* and that it is marked active as soon as the irq could fire. */
9199 smp_wmb();
9200 }
9201
9202 static int intel_gen2_queue_flip(struct drm_device *dev,
9203 struct drm_crtc *crtc,
9204 struct drm_framebuffer *fb,
9205 struct drm_i915_gem_object *obj,
9206 struct intel_engine_cs *ring,
9207 uint32_t flags)
9208 {
9209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9210 u32 flip_mask;
9211 int ret;
9212
9213 ret = intel_ring_begin(ring, 6);
9214 if (ret)
9215 return ret;
9216
9217 /* Can't queue multiple flips, so wait for the previous
9218 * one to finish before executing the next.
9219 */
9220 if (intel_crtc->plane)
9221 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9222 else
9223 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9224 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9225 intel_ring_emit(ring, MI_NOOP);
9226 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9227 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9228 intel_ring_emit(ring, fb->pitches[0]);
9229 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9230 intel_ring_emit(ring, 0); /* aux display base address, unused */
9231
9232 intel_mark_page_flip_active(intel_crtc);
9233 __intel_ring_advance(ring);
9234 return 0;
9235 }
9236
9237 static int intel_gen3_queue_flip(struct drm_device *dev,
9238 struct drm_crtc *crtc,
9239 struct drm_framebuffer *fb,
9240 struct drm_i915_gem_object *obj,
9241 struct intel_engine_cs *ring,
9242 uint32_t flags)
9243 {
9244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9245 u32 flip_mask;
9246 int ret;
9247
9248 ret = intel_ring_begin(ring, 6);
9249 if (ret)
9250 return ret;
9251
9252 if (intel_crtc->plane)
9253 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9254 else
9255 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9256 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9257 intel_ring_emit(ring, MI_NOOP);
9258 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9259 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9260 intel_ring_emit(ring, fb->pitches[0]);
9261 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9262 intel_ring_emit(ring, MI_NOOP);
9263
9264 intel_mark_page_flip_active(intel_crtc);
9265 __intel_ring_advance(ring);
9266 return 0;
9267 }
9268
9269 static int intel_gen4_queue_flip(struct drm_device *dev,
9270 struct drm_crtc *crtc,
9271 struct drm_framebuffer *fb,
9272 struct drm_i915_gem_object *obj,
9273 struct intel_engine_cs *ring,
9274 uint32_t flags)
9275 {
9276 struct drm_i915_private *dev_priv = dev->dev_private;
9277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9278 uint32_t pf, pipesrc;
9279 int ret;
9280
9281 ret = intel_ring_begin(ring, 4);
9282 if (ret)
9283 return ret;
9284
9285 /* i965+ uses the linear or tiled offsets from the
9286 * Display Registers (which do not change across a page-flip)
9287 * so we need only reprogram the base address.
9288 */
9289 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9291 intel_ring_emit(ring, fb->pitches[0]);
9292 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9293 obj->tiling_mode);
9294
9295 /* XXX Enabling the panel-fitter across page-flip is so far
9296 * untested on non-native modes, so ignore it for now.
9297 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9298 */
9299 pf = 0;
9300 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9301 intel_ring_emit(ring, pf | pipesrc);
9302
9303 intel_mark_page_flip_active(intel_crtc);
9304 __intel_ring_advance(ring);
9305 return 0;
9306 }
9307
9308 static int intel_gen6_queue_flip(struct drm_device *dev,
9309 struct drm_crtc *crtc,
9310 struct drm_framebuffer *fb,
9311 struct drm_i915_gem_object *obj,
9312 struct intel_engine_cs *ring,
9313 uint32_t flags)
9314 {
9315 struct drm_i915_private *dev_priv = dev->dev_private;
9316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9317 uint32_t pf, pipesrc;
9318 int ret;
9319
9320 ret = intel_ring_begin(ring, 4);
9321 if (ret)
9322 return ret;
9323
9324 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9325 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9326 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9327 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9328
9329 /* Contrary to the suggestions in the documentation,
9330 * "Enable Panel Fitter" does not seem to be required when page
9331 * flipping with a non-native mode, and worse causes a normal
9332 * modeset to fail.
9333 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9334 */
9335 pf = 0;
9336 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9337 intel_ring_emit(ring, pf | pipesrc);
9338
9339 intel_mark_page_flip_active(intel_crtc);
9340 __intel_ring_advance(ring);
9341 return 0;
9342 }
9343
9344 static int intel_gen7_queue_flip(struct drm_device *dev,
9345 struct drm_crtc *crtc,
9346 struct drm_framebuffer *fb,
9347 struct drm_i915_gem_object *obj,
9348 struct intel_engine_cs *ring,
9349 uint32_t flags)
9350 {
9351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9352 uint32_t plane_bit = 0;
9353 int len, ret;
9354
9355 switch (intel_crtc->plane) {
9356 case PLANE_A:
9357 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9358 break;
9359 case PLANE_B:
9360 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9361 break;
9362 case PLANE_C:
9363 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9364 break;
9365 default:
9366 WARN_ONCE(1, "unknown plane in flip command\n");
9367 return -ENODEV;
9368 }
9369
9370 len = 4;
9371 if (ring->id == RCS) {
9372 len += 6;
9373 /*
9374 * On Gen 8, SRM is now taking an extra dword to accommodate
9375 * 48bits addresses, and we need a NOOP for the batch size to
9376 * stay even.
9377 */
9378 if (IS_GEN8(dev))
9379 len += 2;
9380 }
9381
9382 /*
9383 * BSpec MI_DISPLAY_FLIP for IVB:
9384 * "The full packet must be contained within the same cache line."
9385 *
9386 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9387 * cacheline, if we ever start emitting more commands before
9388 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9389 * then do the cacheline alignment, and finally emit the
9390 * MI_DISPLAY_FLIP.
9391 */
9392 ret = intel_ring_cacheline_align(ring);
9393 if (ret)
9394 return ret;
9395
9396 ret = intel_ring_begin(ring, len);
9397 if (ret)
9398 return ret;
9399
9400 /* Unmask the flip-done completion message. Note that the bspec says that
9401 * we should do this for both the BCS and RCS, and that we must not unmask
9402 * more than one flip event at any time (or ensure that one flip message
9403 * can be sent by waiting for flip-done prior to queueing new flips).
9404 * Experimentation says that BCS works despite DERRMR masking all
9405 * flip-done completion events and that unmasking all planes at once
9406 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9407 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9408 */
9409 if (ring->id == RCS) {
9410 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9411 intel_ring_emit(ring, DERRMR);
9412 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9413 DERRMR_PIPEB_PRI_FLIP_DONE |
9414 DERRMR_PIPEC_PRI_FLIP_DONE));
9415 if (IS_GEN8(dev))
9416 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9417 MI_SRM_LRM_GLOBAL_GTT);
9418 else
9419 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9420 MI_SRM_LRM_GLOBAL_GTT);
9421 intel_ring_emit(ring, DERRMR);
9422 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9423 if (IS_GEN8(dev)) {
9424 intel_ring_emit(ring, 0);
9425 intel_ring_emit(ring, MI_NOOP);
9426 }
9427 }
9428
9429 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9430 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9431 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9432 intel_ring_emit(ring, (MI_NOOP));
9433
9434 intel_mark_page_flip_active(intel_crtc);
9435 __intel_ring_advance(ring);
9436 return 0;
9437 }
9438
9439 static bool use_mmio_flip(struct intel_engine_cs *ring,
9440 struct drm_i915_gem_object *obj)
9441 {
9442 /*
9443 * This is not being used for older platforms, because
9444 * non-availability of flip done interrupt forces us to use
9445 * CS flips. Older platforms derive flip done using some clever
9446 * tricks involving the flip_pending status bits and vblank irqs.
9447 * So using MMIO flips there would disrupt this mechanism.
9448 */
9449
9450 if (INTEL_INFO(ring->dev)->gen < 5)
9451 return false;
9452
9453 if (i915.use_mmio_flip < 0)
9454 return false;
9455 else if (i915.use_mmio_flip > 0)
9456 return true;
9457 else
9458 return ring != obj->ring;
9459 }
9460
9461 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9462 {
9463 struct drm_device *dev = intel_crtc->base.dev;
9464 struct drm_i915_private *dev_priv = dev->dev_private;
9465 struct intel_framebuffer *intel_fb =
9466 to_intel_framebuffer(intel_crtc->base.primary->fb);
9467 struct drm_i915_gem_object *obj = intel_fb->obj;
9468 u32 dspcntr;
9469 u32 reg;
9470
9471 intel_mark_page_flip_active(intel_crtc);
9472
9473 reg = DSPCNTR(intel_crtc->plane);
9474 dspcntr = I915_READ(reg);
9475
9476 if (INTEL_INFO(dev)->gen >= 4) {
9477 if (obj->tiling_mode != I915_TILING_NONE)
9478 dspcntr |= DISPPLANE_TILED;
9479 else
9480 dspcntr &= ~DISPPLANE_TILED;
9481 }
9482 I915_WRITE(reg, dspcntr);
9483
9484 I915_WRITE(DSPSURF(intel_crtc->plane),
9485 intel_crtc->unpin_work->gtt_offset);
9486 POSTING_READ(DSPSURF(intel_crtc->plane));
9487 }
9488
9489 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9490 {
9491 struct intel_engine_cs *ring;
9492 int ret;
9493
9494 lockdep_assert_held(&obj->base.dev->struct_mutex);
9495
9496 if (!obj->last_write_seqno)
9497 return 0;
9498
9499 ring = obj->ring;
9500
9501 if (i915_seqno_passed(ring->get_seqno(ring, true),
9502 obj->last_write_seqno))
9503 return 0;
9504
9505 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9506 if (ret)
9507 return ret;
9508
9509 if (WARN_ON(!ring->irq_get(ring)))
9510 return 0;
9511
9512 return 1;
9513 }
9514
9515 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9516 {
9517 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9518 struct intel_crtc *intel_crtc;
9519 unsigned long irq_flags;
9520 u32 seqno;
9521
9522 seqno = ring->get_seqno(ring, false);
9523
9524 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9525 for_each_intel_crtc(ring->dev, intel_crtc) {
9526 struct intel_mmio_flip *mmio_flip;
9527
9528 mmio_flip = &intel_crtc->mmio_flip;
9529 if (mmio_flip->seqno == 0)
9530 continue;
9531
9532 if (ring->id != mmio_flip->ring_id)
9533 continue;
9534
9535 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9536 intel_do_mmio_flip(intel_crtc);
9537 mmio_flip->seqno = 0;
9538 ring->irq_put(ring);
9539 }
9540 }
9541 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9542 }
9543
9544 static int intel_queue_mmio_flip(struct drm_device *dev,
9545 struct drm_crtc *crtc,
9546 struct drm_framebuffer *fb,
9547 struct drm_i915_gem_object *obj,
9548 struct intel_engine_cs *ring,
9549 uint32_t flags)
9550 {
9551 struct drm_i915_private *dev_priv = dev->dev_private;
9552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9553 unsigned long irq_flags;
9554 int ret;
9555
9556 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9557 return -EBUSY;
9558
9559 ret = intel_postpone_flip(obj);
9560 if (ret < 0)
9561 return ret;
9562 if (ret == 0) {
9563 intel_do_mmio_flip(intel_crtc);
9564 return 0;
9565 }
9566
9567 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9568 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9569 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9570 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9571
9572 /*
9573 * Double check to catch cases where irq fired before
9574 * mmio flip data was ready
9575 */
9576 intel_notify_mmio_flip(obj->ring);
9577 return 0;
9578 }
9579
9580 static int intel_default_queue_flip(struct drm_device *dev,
9581 struct drm_crtc *crtc,
9582 struct drm_framebuffer *fb,
9583 struct drm_i915_gem_object *obj,
9584 struct intel_engine_cs *ring,
9585 uint32_t flags)
9586 {
9587 return -ENODEV;
9588 }
9589
9590 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9591 struct drm_framebuffer *fb,
9592 struct drm_pending_vblank_event *event,
9593 uint32_t page_flip_flags)
9594 {
9595 struct drm_device *dev = crtc->dev;
9596 struct drm_i915_private *dev_priv = dev->dev_private;
9597 struct drm_framebuffer *old_fb = crtc->primary->fb;
9598 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9600 enum pipe pipe = intel_crtc->pipe;
9601 struct intel_unpin_work *work;
9602 struct intel_engine_cs *ring;
9603 unsigned long flags;
9604 int ret;
9605
9606 /* Can't change pixel format via MI display flips. */
9607 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9608 return -EINVAL;
9609
9610 /*
9611 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9612 * Note that pitch changes could also affect these register.
9613 */
9614 if (INTEL_INFO(dev)->gen > 3 &&
9615 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9616 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9617 return -EINVAL;
9618
9619 if (i915_terminally_wedged(&dev_priv->gpu_error))
9620 goto out_hang;
9621
9622 work = kzalloc(sizeof(*work), GFP_KERNEL);
9623 if (work == NULL)
9624 return -ENOMEM;
9625
9626 work->event = event;
9627 work->crtc = crtc;
9628 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9629 INIT_WORK(&work->work, intel_unpin_work_fn);
9630
9631 ret = drm_crtc_vblank_get(crtc);
9632 if (ret)
9633 goto free_work;
9634
9635 /* We borrow the event spin lock for protecting unpin_work */
9636 spin_lock_irqsave(&dev->event_lock, flags);
9637 if (intel_crtc->unpin_work) {
9638 spin_unlock_irqrestore(&dev->event_lock, flags);
9639 kfree(work);
9640 drm_crtc_vblank_put(crtc);
9641
9642 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9643 return -EBUSY;
9644 }
9645 intel_crtc->unpin_work = work;
9646 spin_unlock_irqrestore(&dev->event_lock, flags);
9647
9648 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9649 flush_workqueue(dev_priv->wq);
9650
9651 ret = i915_mutex_lock_interruptible(dev);
9652 if (ret)
9653 goto cleanup;
9654
9655 /* Reference the objects for the scheduled work. */
9656 drm_gem_object_reference(&work->old_fb_obj->base);
9657 drm_gem_object_reference(&obj->base);
9658
9659 crtc->primary->fb = fb;
9660
9661 work->pending_flip_obj = obj;
9662
9663 work->enable_stall_check = true;
9664
9665 atomic_inc(&intel_crtc->unpin_work_count);
9666 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9667
9668 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9669 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9670
9671 if (IS_VALLEYVIEW(dev)) {
9672 ring = &dev_priv->ring[BCS];
9673 } else if (INTEL_INFO(dev)->gen >= 7) {
9674 ring = obj->ring;
9675 if (ring == NULL || ring->id != RCS)
9676 ring = &dev_priv->ring[BCS];
9677 } else {
9678 ring = &dev_priv->ring[RCS];
9679 }
9680
9681 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9682 if (ret)
9683 goto cleanup_pending;
9684
9685 work->gtt_offset =
9686 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9687
9688 if (use_mmio_flip(ring, obj))
9689 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9690 page_flip_flags);
9691 else
9692 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9693 page_flip_flags);
9694 if (ret)
9695 goto cleanup_unpin;
9696
9697 i915_gem_track_fb(work->old_fb_obj, obj,
9698 INTEL_FRONTBUFFER_PRIMARY(pipe));
9699
9700 intel_disable_fbc(dev);
9701 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9702 mutex_unlock(&dev->struct_mutex);
9703
9704 trace_i915_flip_request(intel_crtc->plane, obj);
9705
9706 return 0;
9707
9708 cleanup_unpin:
9709 intel_unpin_fb_obj(obj);
9710 cleanup_pending:
9711 atomic_dec(&intel_crtc->unpin_work_count);
9712 crtc->primary->fb = old_fb;
9713 drm_gem_object_unreference(&work->old_fb_obj->base);
9714 drm_gem_object_unreference(&obj->base);
9715 mutex_unlock(&dev->struct_mutex);
9716
9717 cleanup:
9718 spin_lock_irqsave(&dev->event_lock, flags);
9719 intel_crtc->unpin_work = NULL;
9720 spin_unlock_irqrestore(&dev->event_lock, flags);
9721
9722 drm_crtc_vblank_put(crtc);
9723 free_work:
9724 kfree(work);
9725
9726 if (ret == -EIO) {
9727 out_hang:
9728 intel_crtc_wait_for_pending_flips(crtc);
9729 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9730 if (ret == 0 && event)
9731 drm_send_vblank_event(dev, pipe, event);
9732 }
9733 return ret;
9734 }
9735
9736 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9737 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9738 .load_lut = intel_crtc_load_lut,
9739 };
9740
9741 /**
9742 * intel_modeset_update_staged_output_state
9743 *
9744 * Updates the staged output configuration state, e.g. after we've read out the
9745 * current hw state.
9746 */
9747 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9748 {
9749 struct intel_crtc *crtc;
9750 struct intel_encoder *encoder;
9751 struct intel_connector *connector;
9752
9753 list_for_each_entry(connector, &dev->mode_config.connector_list,
9754 base.head) {
9755 connector->new_encoder =
9756 to_intel_encoder(connector->base.encoder);
9757 }
9758
9759 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9760 base.head) {
9761 encoder->new_crtc =
9762 to_intel_crtc(encoder->base.crtc);
9763 }
9764
9765 for_each_intel_crtc(dev, crtc) {
9766 crtc->new_enabled = crtc->base.enabled;
9767
9768 if (crtc->new_enabled)
9769 crtc->new_config = &crtc->config;
9770 else
9771 crtc->new_config = NULL;
9772 }
9773 }
9774
9775 /**
9776 * intel_modeset_commit_output_state
9777 *
9778 * This function copies the stage display pipe configuration to the real one.
9779 */
9780 static void intel_modeset_commit_output_state(struct drm_device *dev)
9781 {
9782 struct intel_crtc *crtc;
9783 struct intel_encoder *encoder;
9784 struct intel_connector *connector;
9785
9786 list_for_each_entry(connector, &dev->mode_config.connector_list,
9787 base.head) {
9788 connector->base.encoder = &connector->new_encoder->base;
9789 }
9790
9791 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9792 base.head) {
9793 encoder->base.crtc = &encoder->new_crtc->base;
9794 }
9795
9796 for_each_intel_crtc(dev, crtc) {
9797 crtc->base.enabled = crtc->new_enabled;
9798 }
9799 }
9800
9801 static void
9802 connected_sink_compute_bpp(struct intel_connector *connector,
9803 struct intel_crtc_config *pipe_config)
9804 {
9805 int bpp = pipe_config->pipe_bpp;
9806
9807 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9808 connector->base.base.id,
9809 connector->base.name);
9810
9811 /* Don't use an invalid EDID bpc value */
9812 if (connector->base.display_info.bpc &&
9813 connector->base.display_info.bpc * 3 < bpp) {
9814 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9815 bpp, connector->base.display_info.bpc*3);
9816 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9817 }
9818
9819 /* Clamp bpp to 8 on screens without EDID 1.4 */
9820 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9821 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9822 bpp);
9823 pipe_config->pipe_bpp = 24;
9824 }
9825 }
9826
9827 static int
9828 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9829 struct drm_framebuffer *fb,
9830 struct intel_crtc_config *pipe_config)
9831 {
9832 struct drm_device *dev = crtc->base.dev;
9833 struct intel_connector *connector;
9834 int bpp;
9835
9836 switch (fb->pixel_format) {
9837 case DRM_FORMAT_C8:
9838 bpp = 8*3; /* since we go through a colormap */
9839 break;
9840 case DRM_FORMAT_XRGB1555:
9841 case DRM_FORMAT_ARGB1555:
9842 /* checked in intel_framebuffer_init already */
9843 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9844 return -EINVAL;
9845 case DRM_FORMAT_RGB565:
9846 bpp = 6*3; /* min is 18bpp */
9847 break;
9848 case DRM_FORMAT_XBGR8888:
9849 case DRM_FORMAT_ABGR8888:
9850 /* checked in intel_framebuffer_init already */
9851 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9852 return -EINVAL;
9853 case DRM_FORMAT_XRGB8888:
9854 case DRM_FORMAT_ARGB8888:
9855 bpp = 8*3;
9856 break;
9857 case DRM_FORMAT_XRGB2101010:
9858 case DRM_FORMAT_ARGB2101010:
9859 case DRM_FORMAT_XBGR2101010:
9860 case DRM_FORMAT_ABGR2101010:
9861 /* checked in intel_framebuffer_init already */
9862 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9863 return -EINVAL;
9864 bpp = 10*3;
9865 break;
9866 /* TODO: gen4+ supports 16 bpc floating point, too. */
9867 default:
9868 DRM_DEBUG_KMS("unsupported depth\n");
9869 return -EINVAL;
9870 }
9871
9872 pipe_config->pipe_bpp = bpp;
9873
9874 /* Clamp display bpp to EDID value */
9875 list_for_each_entry(connector, &dev->mode_config.connector_list,
9876 base.head) {
9877 if (!connector->new_encoder ||
9878 connector->new_encoder->new_crtc != crtc)
9879 continue;
9880
9881 connected_sink_compute_bpp(connector, pipe_config);
9882 }
9883
9884 return bpp;
9885 }
9886
9887 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9888 {
9889 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9890 "type: 0x%x flags: 0x%x\n",
9891 mode->crtc_clock,
9892 mode->crtc_hdisplay, mode->crtc_hsync_start,
9893 mode->crtc_hsync_end, mode->crtc_htotal,
9894 mode->crtc_vdisplay, mode->crtc_vsync_start,
9895 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9896 }
9897
9898 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9899 struct intel_crtc_config *pipe_config,
9900 const char *context)
9901 {
9902 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9903 context, pipe_name(crtc->pipe));
9904
9905 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9906 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9907 pipe_config->pipe_bpp, pipe_config->dither);
9908 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9909 pipe_config->has_pch_encoder,
9910 pipe_config->fdi_lanes,
9911 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9912 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9913 pipe_config->fdi_m_n.tu);
9914 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9915 pipe_config->has_dp_encoder,
9916 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9917 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9918 pipe_config->dp_m_n.tu);
9919 DRM_DEBUG_KMS("requested mode:\n");
9920 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9921 DRM_DEBUG_KMS("adjusted mode:\n");
9922 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9923 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9924 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9925 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9926 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9927 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9928 pipe_config->gmch_pfit.control,
9929 pipe_config->gmch_pfit.pgm_ratios,
9930 pipe_config->gmch_pfit.lvds_border_bits);
9931 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9932 pipe_config->pch_pfit.pos,
9933 pipe_config->pch_pfit.size,
9934 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9935 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9936 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9937 }
9938
9939 static bool encoders_cloneable(const struct intel_encoder *a,
9940 const struct intel_encoder *b)
9941 {
9942 /* masks could be asymmetric, so check both ways */
9943 return a == b || (a->cloneable & (1 << b->type) &&
9944 b->cloneable & (1 << a->type));
9945 }
9946
9947 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9948 struct intel_encoder *encoder)
9949 {
9950 struct drm_device *dev = crtc->base.dev;
9951 struct intel_encoder *source_encoder;
9952
9953 list_for_each_entry(source_encoder,
9954 &dev->mode_config.encoder_list, base.head) {
9955 if (source_encoder->new_crtc != crtc)
9956 continue;
9957
9958 if (!encoders_cloneable(encoder, source_encoder))
9959 return false;
9960 }
9961
9962 return true;
9963 }
9964
9965 static bool check_encoder_cloning(struct intel_crtc *crtc)
9966 {
9967 struct drm_device *dev = crtc->base.dev;
9968 struct intel_encoder *encoder;
9969
9970 list_for_each_entry(encoder,
9971 &dev->mode_config.encoder_list, base.head) {
9972 if (encoder->new_crtc != crtc)
9973 continue;
9974
9975 if (!check_single_encoder_cloning(crtc, encoder))
9976 return false;
9977 }
9978
9979 return true;
9980 }
9981
9982 static struct intel_crtc_config *
9983 intel_modeset_pipe_config(struct drm_crtc *crtc,
9984 struct drm_framebuffer *fb,
9985 struct drm_display_mode *mode)
9986 {
9987 struct drm_device *dev = crtc->dev;
9988 struct intel_encoder *encoder;
9989 struct intel_crtc_config *pipe_config;
9990 int plane_bpp, ret = -EINVAL;
9991 bool retry = true;
9992
9993 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9994 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9995 return ERR_PTR(-EINVAL);
9996 }
9997
9998 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9999 if (!pipe_config)
10000 return ERR_PTR(-ENOMEM);
10001
10002 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10003 drm_mode_copy(&pipe_config->requested_mode, mode);
10004
10005 pipe_config->cpu_transcoder =
10006 (enum transcoder) to_intel_crtc(crtc)->pipe;
10007 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10008
10009 /*
10010 * Sanitize sync polarity flags based on requested ones. If neither
10011 * positive or negative polarity is requested, treat this as meaning
10012 * negative polarity.
10013 */
10014 if (!(pipe_config->adjusted_mode.flags &
10015 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10016 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10017
10018 if (!(pipe_config->adjusted_mode.flags &
10019 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10020 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10021
10022 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10023 * plane pixel format and any sink constraints into account. Returns the
10024 * source plane bpp so that dithering can be selected on mismatches
10025 * after encoders and crtc also have had their say. */
10026 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10027 fb, pipe_config);
10028 if (plane_bpp < 0)
10029 goto fail;
10030
10031 /*
10032 * Determine the real pipe dimensions. Note that stereo modes can
10033 * increase the actual pipe size due to the frame doubling and
10034 * insertion of additional space for blanks between the frame. This
10035 * is stored in the crtc timings. We use the requested mode to do this
10036 * computation to clearly distinguish it from the adjusted mode, which
10037 * can be changed by the connectors in the below retry loop.
10038 */
10039 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10040 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10041 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10042
10043 encoder_retry:
10044 /* Ensure the port clock defaults are reset when retrying. */
10045 pipe_config->port_clock = 0;
10046 pipe_config->pixel_multiplier = 1;
10047
10048 /* Fill in default crtc timings, allow encoders to overwrite them. */
10049 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10050
10051 /* Pass our mode to the connectors and the CRTC to give them a chance to
10052 * adjust it according to limitations or connector properties, and also
10053 * a chance to reject the mode entirely.
10054 */
10055 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10056 base.head) {
10057
10058 if (&encoder->new_crtc->base != crtc)
10059 continue;
10060
10061 if (!(encoder->compute_config(encoder, pipe_config))) {
10062 DRM_DEBUG_KMS("Encoder config failure\n");
10063 goto fail;
10064 }
10065 }
10066
10067 /* Set default port clock if not overwritten by the encoder. Needs to be
10068 * done afterwards in case the encoder adjusts the mode. */
10069 if (!pipe_config->port_clock)
10070 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10071 * pipe_config->pixel_multiplier;
10072
10073 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10074 if (ret < 0) {
10075 DRM_DEBUG_KMS("CRTC fixup failed\n");
10076 goto fail;
10077 }
10078
10079 if (ret == RETRY) {
10080 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10081 ret = -EINVAL;
10082 goto fail;
10083 }
10084
10085 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10086 retry = false;
10087 goto encoder_retry;
10088 }
10089
10090 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10091 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10092 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10093
10094 return pipe_config;
10095 fail:
10096 kfree(pipe_config);
10097 return ERR_PTR(ret);
10098 }
10099
10100 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10101 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10102 static void
10103 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10104 unsigned *prepare_pipes, unsigned *disable_pipes)
10105 {
10106 struct intel_crtc *intel_crtc;
10107 struct drm_device *dev = crtc->dev;
10108 struct intel_encoder *encoder;
10109 struct intel_connector *connector;
10110 struct drm_crtc *tmp_crtc;
10111
10112 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10113
10114 /* Check which crtcs have changed outputs connected to them, these need
10115 * to be part of the prepare_pipes mask. We don't (yet) support global
10116 * modeset across multiple crtcs, so modeset_pipes will only have one
10117 * bit set at most. */
10118 list_for_each_entry(connector, &dev->mode_config.connector_list,
10119 base.head) {
10120 if (connector->base.encoder == &connector->new_encoder->base)
10121 continue;
10122
10123 if (connector->base.encoder) {
10124 tmp_crtc = connector->base.encoder->crtc;
10125
10126 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10127 }
10128
10129 if (connector->new_encoder)
10130 *prepare_pipes |=
10131 1 << connector->new_encoder->new_crtc->pipe;
10132 }
10133
10134 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10135 base.head) {
10136 if (encoder->base.crtc == &encoder->new_crtc->base)
10137 continue;
10138
10139 if (encoder->base.crtc) {
10140 tmp_crtc = encoder->base.crtc;
10141
10142 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10143 }
10144
10145 if (encoder->new_crtc)
10146 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10147 }
10148
10149 /* Check for pipes that will be enabled/disabled ... */
10150 for_each_intel_crtc(dev, intel_crtc) {
10151 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10152 continue;
10153
10154 if (!intel_crtc->new_enabled)
10155 *disable_pipes |= 1 << intel_crtc->pipe;
10156 else
10157 *prepare_pipes |= 1 << intel_crtc->pipe;
10158 }
10159
10160
10161 /* set_mode is also used to update properties on life display pipes. */
10162 intel_crtc = to_intel_crtc(crtc);
10163 if (intel_crtc->new_enabled)
10164 *prepare_pipes |= 1 << intel_crtc->pipe;
10165
10166 /*
10167 * For simplicity do a full modeset on any pipe where the output routing
10168 * changed. We could be more clever, but that would require us to be
10169 * more careful with calling the relevant encoder->mode_set functions.
10170 */
10171 if (*prepare_pipes)
10172 *modeset_pipes = *prepare_pipes;
10173
10174 /* ... and mask these out. */
10175 *modeset_pipes &= ~(*disable_pipes);
10176 *prepare_pipes &= ~(*disable_pipes);
10177
10178 /*
10179 * HACK: We don't (yet) fully support global modesets. intel_set_config
10180 * obies this rule, but the modeset restore mode of
10181 * intel_modeset_setup_hw_state does not.
10182 */
10183 *modeset_pipes &= 1 << intel_crtc->pipe;
10184 *prepare_pipes &= 1 << intel_crtc->pipe;
10185
10186 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10187 *modeset_pipes, *prepare_pipes, *disable_pipes);
10188 }
10189
10190 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10191 {
10192 struct drm_encoder *encoder;
10193 struct drm_device *dev = crtc->dev;
10194
10195 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10196 if (encoder->crtc == crtc)
10197 return true;
10198
10199 return false;
10200 }
10201
10202 static void
10203 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10204 {
10205 struct intel_encoder *intel_encoder;
10206 struct intel_crtc *intel_crtc;
10207 struct drm_connector *connector;
10208
10209 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10210 base.head) {
10211 if (!intel_encoder->base.crtc)
10212 continue;
10213
10214 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10215
10216 if (prepare_pipes & (1 << intel_crtc->pipe))
10217 intel_encoder->connectors_active = false;
10218 }
10219
10220 intel_modeset_commit_output_state(dev);
10221
10222 /* Double check state. */
10223 for_each_intel_crtc(dev, intel_crtc) {
10224 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10225 WARN_ON(intel_crtc->new_config &&
10226 intel_crtc->new_config != &intel_crtc->config);
10227 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10228 }
10229
10230 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10231 if (!connector->encoder || !connector->encoder->crtc)
10232 continue;
10233
10234 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10235
10236 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10237 struct drm_property *dpms_property =
10238 dev->mode_config.dpms_property;
10239
10240 connector->dpms = DRM_MODE_DPMS_ON;
10241 drm_object_property_set_value(&connector->base,
10242 dpms_property,
10243 DRM_MODE_DPMS_ON);
10244
10245 intel_encoder = to_intel_encoder(connector->encoder);
10246 intel_encoder->connectors_active = true;
10247 }
10248 }
10249
10250 }
10251
10252 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10253 {
10254 int diff;
10255
10256 if (clock1 == clock2)
10257 return true;
10258
10259 if (!clock1 || !clock2)
10260 return false;
10261
10262 diff = abs(clock1 - clock2);
10263
10264 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10265 return true;
10266
10267 return false;
10268 }
10269
10270 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10271 list_for_each_entry((intel_crtc), \
10272 &(dev)->mode_config.crtc_list, \
10273 base.head) \
10274 if (mask & (1 <<(intel_crtc)->pipe))
10275
10276 static bool
10277 intel_pipe_config_compare(struct drm_device *dev,
10278 struct intel_crtc_config *current_config,
10279 struct intel_crtc_config *pipe_config)
10280 {
10281 #define PIPE_CONF_CHECK_X(name) \
10282 if (current_config->name != pipe_config->name) { \
10283 DRM_ERROR("mismatch in " #name " " \
10284 "(expected 0x%08x, found 0x%08x)\n", \
10285 current_config->name, \
10286 pipe_config->name); \
10287 return false; \
10288 }
10289
10290 #define PIPE_CONF_CHECK_I(name) \
10291 if (current_config->name != pipe_config->name) { \
10292 DRM_ERROR("mismatch in " #name " " \
10293 "(expected %i, found %i)\n", \
10294 current_config->name, \
10295 pipe_config->name); \
10296 return false; \
10297 }
10298
10299 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10300 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10301 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10302 "(expected %i, found %i)\n", \
10303 current_config->name & (mask), \
10304 pipe_config->name & (mask)); \
10305 return false; \
10306 }
10307
10308 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10309 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10310 DRM_ERROR("mismatch in " #name " " \
10311 "(expected %i, found %i)\n", \
10312 current_config->name, \
10313 pipe_config->name); \
10314 return false; \
10315 }
10316
10317 #define PIPE_CONF_QUIRK(quirk) \
10318 ((current_config->quirks | pipe_config->quirks) & (quirk))
10319
10320 PIPE_CONF_CHECK_I(cpu_transcoder);
10321
10322 PIPE_CONF_CHECK_I(has_pch_encoder);
10323 PIPE_CONF_CHECK_I(fdi_lanes);
10324 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10325 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10326 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10327 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10328 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10329
10330 PIPE_CONF_CHECK_I(has_dp_encoder);
10331 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10332 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10333 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10334 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10335 PIPE_CONF_CHECK_I(dp_m_n.tu);
10336
10337 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10338 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10339 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10340 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10341 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10342 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10343
10344 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10345 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10346 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10347 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10348 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10349 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10350
10351 PIPE_CONF_CHECK_I(pixel_multiplier);
10352 PIPE_CONF_CHECK_I(has_hdmi_sink);
10353 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10354 IS_VALLEYVIEW(dev))
10355 PIPE_CONF_CHECK_I(limited_color_range);
10356
10357 PIPE_CONF_CHECK_I(has_audio);
10358
10359 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10360 DRM_MODE_FLAG_INTERLACE);
10361
10362 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10363 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10364 DRM_MODE_FLAG_PHSYNC);
10365 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10366 DRM_MODE_FLAG_NHSYNC);
10367 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10368 DRM_MODE_FLAG_PVSYNC);
10369 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10370 DRM_MODE_FLAG_NVSYNC);
10371 }
10372
10373 PIPE_CONF_CHECK_I(pipe_src_w);
10374 PIPE_CONF_CHECK_I(pipe_src_h);
10375
10376 /*
10377 * FIXME: BIOS likes to set up a cloned config with lvds+external
10378 * screen. Since we don't yet re-compute the pipe config when moving
10379 * just the lvds port away to another pipe the sw tracking won't match.
10380 *
10381 * Proper atomic modesets with recomputed global state will fix this.
10382 * Until then just don't check gmch state for inherited modes.
10383 */
10384 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10385 PIPE_CONF_CHECK_I(gmch_pfit.control);
10386 /* pfit ratios are autocomputed by the hw on gen4+ */
10387 if (INTEL_INFO(dev)->gen < 4)
10388 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10389 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10390 }
10391
10392 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10393 if (current_config->pch_pfit.enabled) {
10394 PIPE_CONF_CHECK_I(pch_pfit.pos);
10395 PIPE_CONF_CHECK_I(pch_pfit.size);
10396 }
10397
10398 /* BDW+ don't expose a synchronous way to read the state */
10399 if (IS_HASWELL(dev))
10400 PIPE_CONF_CHECK_I(ips_enabled);
10401
10402 PIPE_CONF_CHECK_I(double_wide);
10403
10404 PIPE_CONF_CHECK_I(shared_dpll);
10405 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10406 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10407 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10408 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10409
10410 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10411 PIPE_CONF_CHECK_I(pipe_bpp);
10412
10413 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10414 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10415
10416 #undef PIPE_CONF_CHECK_X
10417 #undef PIPE_CONF_CHECK_I
10418 #undef PIPE_CONF_CHECK_FLAGS
10419 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10420 #undef PIPE_CONF_QUIRK
10421
10422 return true;
10423 }
10424
10425 static void
10426 check_connector_state(struct drm_device *dev)
10427 {
10428 struct intel_connector *connector;
10429
10430 list_for_each_entry(connector, &dev->mode_config.connector_list,
10431 base.head) {
10432 /* This also checks the encoder/connector hw state with the
10433 * ->get_hw_state callbacks. */
10434 intel_connector_check_state(connector);
10435
10436 WARN(&connector->new_encoder->base != connector->base.encoder,
10437 "connector's staged encoder doesn't match current encoder\n");
10438 }
10439 }
10440
10441 static void
10442 check_encoder_state(struct drm_device *dev)
10443 {
10444 struct intel_encoder *encoder;
10445 struct intel_connector *connector;
10446
10447 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10448 base.head) {
10449 bool enabled = false;
10450 bool active = false;
10451 enum pipe pipe, tracked_pipe;
10452
10453 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10454 encoder->base.base.id,
10455 encoder->base.name);
10456
10457 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10458 "encoder's stage crtc doesn't match current crtc\n");
10459 WARN(encoder->connectors_active && !encoder->base.crtc,
10460 "encoder's active_connectors set, but no crtc\n");
10461
10462 list_for_each_entry(connector, &dev->mode_config.connector_list,
10463 base.head) {
10464 if (connector->base.encoder != &encoder->base)
10465 continue;
10466 enabled = true;
10467 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10468 active = true;
10469 }
10470 WARN(!!encoder->base.crtc != enabled,
10471 "encoder's enabled state mismatch "
10472 "(expected %i, found %i)\n",
10473 !!encoder->base.crtc, enabled);
10474 WARN(active && !encoder->base.crtc,
10475 "active encoder with no crtc\n");
10476
10477 WARN(encoder->connectors_active != active,
10478 "encoder's computed active state doesn't match tracked active state "
10479 "(expected %i, found %i)\n", active, encoder->connectors_active);
10480
10481 active = encoder->get_hw_state(encoder, &pipe);
10482 WARN(active != encoder->connectors_active,
10483 "encoder's hw state doesn't match sw tracking "
10484 "(expected %i, found %i)\n",
10485 encoder->connectors_active, active);
10486
10487 if (!encoder->base.crtc)
10488 continue;
10489
10490 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10491 WARN(active && pipe != tracked_pipe,
10492 "active encoder's pipe doesn't match"
10493 "(expected %i, found %i)\n",
10494 tracked_pipe, pipe);
10495
10496 }
10497 }
10498
10499 static void
10500 check_crtc_state(struct drm_device *dev)
10501 {
10502 struct drm_i915_private *dev_priv = dev->dev_private;
10503 struct intel_crtc *crtc;
10504 struct intel_encoder *encoder;
10505 struct intel_crtc_config pipe_config;
10506
10507 for_each_intel_crtc(dev, crtc) {
10508 bool enabled = false;
10509 bool active = false;
10510
10511 memset(&pipe_config, 0, sizeof(pipe_config));
10512
10513 DRM_DEBUG_KMS("[CRTC:%d]\n",
10514 crtc->base.base.id);
10515
10516 WARN(crtc->active && !crtc->base.enabled,
10517 "active crtc, but not enabled in sw tracking\n");
10518
10519 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10520 base.head) {
10521 if (encoder->base.crtc != &crtc->base)
10522 continue;
10523 enabled = true;
10524 if (encoder->connectors_active)
10525 active = true;
10526 }
10527
10528 WARN(active != crtc->active,
10529 "crtc's computed active state doesn't match tracked active state "
10530 "(expected %i, found %i)\n", active, crtc->active);
10531 WARN(enabled != crtc->base.enabled,
10532 "crtc's computed enabled state doesn't match tracked enabled state "
10533 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10534
10535 active = dev_priv->display.get_pipe_config(crtc,
10536 &pipe_config);
10537
10538 /* hw state is inconsistent with the pipe A quirk */
10539 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10540 active = crtc->active;
10541
10542 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10543 base.head) {
10544 enum pipe pipe;
10545 if (encoder->base.crtc != &crtc->base)
10546 continue;
10547 if (encoder->get_hw_state(encoder, &pipe))
10548 encoder->get_config(encoder, &pipe_config);
10549 }
10550
10551 WARN(crtc->active != active,
10552 "crtc active state doesn't match with hw state "
10553 "(expected %i, found %i)\n", crtc->active, active);
10554
10555 if (active &&
10556 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10557 WARN(1, "pipe state doesn't match!\n");
10558 intel_dump_pipe_config(crtc, &pipe_config,
10559 "[hw state]");
10560 intel_dump_pipe_config(crtc, &crtc->config,
10561 "[sw state]");
10562 }
10563 }
10564 }
10565
10566 static void
10567 check_shared_dpll_state(struct drm_device *dev)
10568 {
10569 struct drm_i915_private *dev_priv = dev->dev_private;
10570 struct intel_crtc *crtc;
10571 struct intel_dpll_hw_state dpll_hw_state;
10572 int i;
10573
10574 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10575 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10576 int enabled_crtcs = 0, active_crtcs = 0;
10577 bool active;
10578
10579 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10580
10581 DRM_DEBUG_KMS("%s\n", pll->name);
10582
10583 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10584
10585 WARN(pll->active > pll->refcount,
10586 "more active pll users than references: %i vs %i\n",
10587 pll->active, pll->refcount);
10588 WARN(pll->active && !pll->on,
10589 "pll in active use but not on in sw tracking\n");
10590 WARN(pll->on && !pll->active,
10591 "pll in on but not on in use in sw tracking\n");
10592 WARN(pll->on != active,
10593 "pll on state mismatch (expected %i, found %i)\n",
10594 pll->on, active);
10595
10596 for_each_intel_crtc(dev, crtc) {
10597 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10598 enabled_crtcs++;
10599 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10600 active_crtcs++;
10601 }
10602 WARN(pll->active != active_crtcs,
10603 "pll active crtcs mismatch (expected %i, found %i)\n",
10604 pll->active, active_crtcs);
10605 WARN(pll->refcount != enabled_crtcs,
10606 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10607 pll->refcount, enabled_crtcs);
10608
10609 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10610 sizeof(dpll_hw_state)),
10611 "pll hw state mismatch\n");
10612 }
10613 }
10614
10615 void
10616 intel_modeset_check_state(struct drm_device *dev)
10617 {
10618 check_connector_state(dev);
10619 check_encoder_state(dev);
10620 check_crtc_state(dev);
10621 check_shared_dpll_state(dev);
10622 }
10623
10624 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10625 int dotclock)
10626 {
10627 /*
10628 * FDI already provided one idea for the dotclock.
10629 * Yell if the encoder disagrees.
10630 */
10631 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10632 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10633 pipe_config->adjusted_mode.crtc_clock, dotclock);
10634 }
10635
10636 static void update_scanline_offset(struct intel_crtc *crtc)
10637 {
10638 struct drm_device *dev = crtc->base.dev;
10639
10640 /*
10641 * The scanline counter increments at the leading edge of hsync.
10642 *
10643 * On most platforms it starts counting from vtotal-1 on the
10644 * first active line. That means the scanline counter value is
10645 * always one less than what we would expect. Ie. just after
10646 * start of vblank, which also occurs at start of hsync (on the
10647 * last active line), the scanline counter will read vblank_start-1.
10648 *
10649 * On gen2 the scanline counter starts counting from 1 instead
10650 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10651 * to keep the value positive), instead of adding one.
10652 *
10653 * On HSW+ the behaviour of the scanline counter depends on the output
10654 * type. For DP ports it behaves like most other platforms, but on HDMI
10655 * there's an extra 1 line difference. So we need to add two instead of
10656 * one to the value.
10657 */
10658 if (IS_GEN2(dev)) {
10659 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10660 int vtotal;
10661
10662 vtotal = mode->crtc_vtotal;
10663 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10664 vtotal /= 2;
10665
10666 crtc->scanline_offset = vtotal - 1;
10667 } else if (HAS_DDI(dev) &&
10668 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10669 crtc->scanline_offset = 2;
10670 } else
10671 crtc->scanline_offset = 1;
10672 }
10673
10674 static int __intel_set_mode(struct drm_crtc *crtc,
10675 struct drm_display_mode *mode,
10676 int x, int y, struct drm_framebuffer *fb)
10677 {
10678 struct drm_device *dev = crtc->dev;
10679 struct drm_i915_private *dev_priv = dev->dev_private;
10680 struct drm_display_mode *saved_mode;
10681 struct intel_crtc_config *pipe_config = NULL;
10682 struct intel_crtc *intel_crtc;
10683 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10684 int ret = 0;
10685
10686 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10687 if (!saved_mode)
10688 return -ENOMEM;
10689
10690 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10691 &prepare_pipes, &disable_pipes);
10692
10693 *saved_mode = crtc->mode;
10694
10695 /* Hack: Because we don't (yet) support global modeset on multiple
10696 * crtcs, we don't keep track of the new mode for more than one crtc.
10697 * Hence simply check whether any bit is set in modeset_pipes in all the
10698 * pieces of code that are not yet converted to deal with mutliple crtcs
10699 * changing their mode at the same time. */
10700 if (modeset_pipes) {
10701 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10702 if (IS_ERR(pipe_config)) {
10703 ret = PTR_ERR(pipe_config);
10704 pipe_config = NULL;
10705
10706 goto out;
10707 }
10708 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10709 "[modeset]");
10710 to_intel_crtc(crtc)->new_config = pipe_config;
10711 }
10712
10713 /*
10714 * See if the config requires any additional preparation, e.g.
10715 * to adjust global state with pipes off. We need to do this
10716 * here so we can get the modeset_pipe updated config for the new
10717 * mode set on this crtc. For other crtcs we need to use the
10718 * adjusted_mode bits in the crtc directly.
10719 */
10720 if (IS_VALLEYVIEW(dev)) {
10721 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10722
10723 /* may have added more to prepare_pipes than we should */
10724 prepare_pipes &= ~disable_pipes;
10725 }
10726
10727 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10728 intel_crtc_disable(&intel_crtc->base);
10729
10730 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10731 if (intel_crtc->base.enabled)
10732 dev_priv->display.crtc_disable(&intel_crtc->base);
10733 }
10734
10735 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10736 * to set it here already despite that we pass it down the callchain.
10737 */
10738 if (modeset_pipes) {
10739 crtc->mode = *mode;
10740 /* mode_set/enable/disable functions rely on a correct pipe
10741 * config. */
10742 to_intel_crtc(crtc)->config = *pipe_config;
10743 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10744
10745 /*
10746 * Calculate and store various constants which
10747 * are later needed by vblank and swap-completion
10748 * timestamping. They are derived from true hwmode.
10749 */
10750 drm_calc_timestamping_constants(crtc,
10751 &pipe_config->adjusted_mode);
10752 }
10753
10754 /* Only after disabling all output pipelines that will be changed can we
10755 * update the the output configuration. */
10756 intel_modeset_update_state(dev, prepare_pipes);
10757
10758 if (dev_priv->display.modeset_global_resources)
10759 dev_priv->display.modeset_global_resources(dev);
10760
10761 /* Set up the DPLL and any encoders state that needs to adjust or depend
10762 * on the DPLL.
10763 */
10764 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10765 struct drm_framebuffer *old_fb;
10766 struct drm_i915_gem_object *old_obj = NULL;
10767 struct drm_i915_gem_object *obj =
10768 to_intel_framebuffer(fb)->obj;
10769
10770 mutex_lock(&dev->struct_mutex);
10771 ret = intel_pin_and_fence_fb_obj(dev,
10772 obj,
10773 NULL);
10774 if (ret != 0) {
10775 DRM_ERROR("pin & fence failed\n");
10776 mutex_unlock(&dev->struct_mutex);
10777 goto done;
10778 }
10779 old_fb = crtc->primary->fb;
10780 if (old_fb) {
10781 old_obj = to_intel_framebuffer(old_fb)->obj;
10782 intel_unpin_fb_obj(old_obj);
10783 }
10784 i915_gem_track_fb(old_obj, obj,
10785 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10786 mutex_unlock(&dev->struct_mutex);
10787
10788 crtc->primary->fb = fb;
10789 crtc->x = x;
10790 crtc->y = y;
10791
10792 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10793 x, y, fb);
10794 if (ret)
10795 goto done;
10796 }
10797
10798 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10799 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10800 update_scanline_offset(intel_crtc);
10801
10802 dev_priv->display.crtc_enable(&intel_crtc->base);
10803 }
10804
10805 /* FIXME: add subpixel order */
10806 done:
10807 if (ret && crtc->enabled)
10808 crtc->mode = *saved_mode;
10809
10810 out:
10811 kfree(pipe_config);
10812 kfree(saved_mode);
10813 return ret;
10814 }
10815
10816 static int intel_set_mode(struct drm_crtc *crtc,
10817 struct drm_display_mode *mode,
10818 int x, int y, struct drm_framebuffer *fb)
10819 {
10820 int ret;
10821
10822 ret = __intel_set_mode(crtc, mode, x, y, fb);
10823
10824 if (ret == 0)
10825 intel_modeset_check_state(crtc->dev);
10826
10827 return ret;
10828 }
10829
10830 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10831 {
10832 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10833 }
10834
10835 #undef for_each_intel_crtc_masked
10836
10837 static void intel_set_config_free(struct intel_set_config *config)
10838 {
10839 if (!config)
10840 return;
10841
10842 kfree(config->save_connector_encoders);
10843 kfree(config->save_encoder_crtcs);
10844 kfree(config->save_crtc_enabled);
10845 kfree(config);
10846 }
10847
10848 static int intel_set_config_save_state(struct drm_device *dev,
10849 struct intel_set_config *config)
10850 {
10851 struct drm_crtc *crtc;
10852 struct drm_encoder *encoder;
10853 struct drm_connector *connector;
10854 int count;
10855
10856 config->save_crtc_enabled =
10857 kcalloc(dev->mode_config.num_crtc,
10858 sizeof(bool), GFP_KERNEL);
10859 if (!config->save_crtc_enabled)
10860 return -ENOMEM;
10861
10862 config->save_encoder_crtcs =
10863 kcalloc(dev->mode_config.num_encoder,
10864 sizeof(struct drm_crtc *), GFP_KERNEL);
10865 if (!config->save_encoder_crtcs)
10866 return -ENOMEM;
10867
10868 config->save_connector_encoders =
10869 kcalloc(dev->mode_config.num_connector,
10870 sizeof(struct drm_encoder *), GFP_KERNEL);
10871 if (!config->save_connector_encoders)
10872 return -ENOMEM;
10873
10874 /* Copy data. Note that driver private data is not affected.
10875 * Should anything bad happen only the expected state is
10876 * restored, not the drivers personal bookkeeping.
10877 */
10878 count = 0;
10879 for_each_crtc(dev, crtc) {
10880 config->save_crtc_enabled[count++] = crtc->enabled;
10881 }
10882
10883 count = 0;
10884 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10885 config->save_encoder_crtcs[count++] = encoder->crtc;
10886 }
10887
10888 count = 0;
10889 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10890 config->save_connector_encoders[count++] = connector->encoder;
10891 }
10892
10893 return 0;
10894 }
10895
10896 static void intel_set_config_restore_state(struct drm_device *dev,
10897 struct intel_set_config *config)
10898 {
10899 struct intel_crtc *crtc;
10900 struct intel_encoder *encoder;
10901 struct intel_connector *connector;
10902 int count;
10903
10904 count = 0;
10905 for_each_intel_crtc(dev, crtc) {
10906 crtc->new_enabled = config->save_crtc_enabled[count++];
10907
10908 if (crtc->new_enabled)
10909 crtc->new_config = &crtc->config;
10910 else
10911 crtc->new_config = NULL;
10912 }
10913
10914 count = 0;
10915 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10916 encoder->new_crtc =
10917 to_intel_crtc(config->save_encoder_crtcs[count++]);
10918 }
10919
10920 count = 0;
10921 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10922 connector->new_encoder =
10923 to_intel_encoder(config->save_connector_encoders[count++]);
10924 }
10925 }
10926
10927 static bool
10928 is_crtc_connector_off(struct drm_mode_set *set)
10929 {
10930 int i;
10931
10932 if (set->num_connectors == 0)
10933 return false;
10934
10935 if (WARN_ON(set->connectors == NULL))
10936 return false;
10937
10938 for (i = 0; i < set->num_connectors; i++)
10939 if (set->connectors[i]->encoder &&
10940 set->connectors[i]->encoder->crtc == set->crtc &&
10941 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10942 return true;
10943
10944 return false;
10945 }
10946
10947 static void
10948 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10949 struct intel_set_config *config)
10950 {
10951
10952 /* We should be able to check here if the fb has the same properties
10953 * and then just flip_or_move it */
10954 if (is_crtc_connector_off(set)) {
10955 config->mode_changed = true;
10956 } else if (set->crtc->primary->fb != set->fb) {
10957 /*
10958 * If we have no fb, we can only flip as long as the crtc is
10959 * active, otherwise we need a full mode set. The crtc may
10960 * be active if we've only disabled the primary plane, or
10961 * in fastboot situations.
10962 */
10963 if (set->crtc->primary->fb == NULL) {
10964 struct intel_crtc *intel_crtc =
10965 to_intel_crtc(set->crtc);
10966
10967 if (intel_crtc->active) {
10968 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10969 config->fb_changed = true;
10970 } else {
10971 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10972 config->mode_changed = true;
10973 }
10974 } else if (set->fb == NULL) {
10975 config->mode_changed = true;
10976 } else if (set->fb->pixel_format !=
10977 set->crtc->primary->fb->pixel_format) {
10978 config->mode_changed = true;
10979 } else {
10980 config->fb_changed = true;
10981 }
10982 }
10983
10984 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10985 config->fb_changed = true;
10986
10987 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10988 DRM_DEBUG_KMS("modes are different, full mode set\n");
10989 drm_mode_debug_printmodeline(&set->crtc->mode);
10990 drm_mode_debug_printmodeline(set->mode);
10991 config->mode_changed = true;
10992 }
10993
10994 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10995 set->crtc->base.id, config->mode_changed, config->fb_changed);
10996 }
10997
10998 static int
10999 intel_modeset_stage_output_state(struct drm_device *dev,
11000 struct drm_mode_set *set,
11001 struct intel_set_config *config)
11002 {
11003 struct intel_connector *connector;
11004 struct intel_encoder *encoder;
11005 struct intel_crtc *crtc;
11006 int ro;
11007
11008 /* The upper layers ensure that we either disable a crtc or have a list
11009 * of connectors. For paranoia, double-check this. */
11010 WARN_ON(!set->fb && (set->num_connectors != 0));
11011 WARN_ON(set->fb && (set->num_connectors == 0));
11012
11013 list_for_each_entry(connector, &dev->mode_config.connector_list,
11014 base.head) {
11015 /* Otherwise traverse passed in connector list and get encoders
11016 * for them. */
11017 for (ro = 0; ro < set->num_connectors; ro++) {
11018 if (set->connectors[ro] == &connector->base) {
11019 connector->new_encoder = connector->encoder;
11020 break;
11021 }
11022 }
11023
11024 /* If we disable the crtc, disable all its connectors. Also, if
11025 * the connector is on the changing crtc but not on the new
11026 * connector list, disable it. */
11027 if ((!set->fb || ro == set->num_connectors) &&
11028 connector->base.encoder &&
11029 connector->base.encoder->crtc == set->crtc) {
11030 connector->new_encoder = NULL;
11031
11032 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11033 connector->base.base.id,
11034 connector->base.name);
11035 }
11036
11037
11038 if (&connector->new_encoder->base != connector->base.encoder) {
11039 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11040 config->mode_changed = true;
11041 }
11042 }
11043 /* connector->new_encoder is now updated for all connectors. */
11044
11045 /* Update crtc of enabled connectors. */
11046 list_for_each_entry(connector, &dev->mode_config.connector_list,
11047 base.head) {
11048 struct drm_crtc *new_crtc;
11049
11050 if (!connector->new_encoder)
11051 continue;
11052
11053 new_crtc = connector->new_encoder->base.crtc;
11054
11055 for (ro = 0; ro < set->num_connectors; ro++) {
11056 if (set->connectors[ro] == &connector->base)
11057 new_crtc = set->crtc;
11058 }
11059
11060 /* Make sure the new CRTC will work with the encoder */
11061 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11062 new_crtc)) {
11063 return -EINVAL;
11064 }
11065 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
11066
11067 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11068 connector->base.base.id,
11069 connector->base.name,
11070 new_crtc->base.id);
11071 }
11072
11073 /* Check for any encoders that needs to be disabled. */
11074 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11075 base.head) {
11076 int num_connectors = 0;
11077 list_for_each_entry(connector,
11078 &dev->mode_config.connector_list,
11079 base.head) {
11080 if (connector->new_encoder == encoder) {
11081 WARN_ON(!connector->new_encoder->new_crtc);
11082 num_connectors++;
11083 }
11084 }
11085
11086 if (num_connectors == 0)
11087 encoder->new_crtc = NULL;
11088 else if (num_connectors > 1)
11089 return -EINVAL;
11090
11091 /* Only now check for crtc changes so we don't miss encoders
11092 * that will be disabled. */
11093 if (&encoder->new_crtc->base != encoder->base.crtc) {
11094 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11095 config->mode_changed = true;
11096 }
11097 }
11098 /* Now we've also updated encoder->new_crtc for all encoders. */
11099
11100 for_each_intel_crtc(dev, crtc) {
11101 crtc->new_enabled = false;
11102
11103 list_for_each_entry(encoder,
11104 &dev->mode_config.encoder_list,
11105 base.head) {
11106 if (encoder->new_crtc == crtc) {
11107 crtc->new_enabled = true;
11108 break;
11109 }
11110 }
11111
11112 if (crtc->new_enabled != crtc->base.enabled) {
11113 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11114 crtc->new_enabled ? "en" : "dis");
11115 config->mode_changed = true;
11116 }
11117
11118 if (crtc->new_enabled)
11119 crtc->new_config = &crtc->config;
11120 else
11121 crtc->new_config = NULL;
11122 }
11123
11124 return 0;
11125 }
11126
11127 static void disable_crtc_nofb(struct intel_crtc *crtc)
11128 {
11129 struct drm_device *dev = crtc->base.dev;
11130 struct intel_encoder *encoder;
11131 struct intel_connector *connector;
11132
11133 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11134 pipe_name(crtc->pipe));
11135
11136 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11137 if (connector->new_encoder &&
11138 connector->new_encoder->new_crtc == crtc)
11139 connector->new_encoder = NULL;
11140 }
11141
11142 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11143 if (encoder->new_crtc == crtc)
11144 encoder->new_crtc = NULL;
11145 }
11146
11147 crtc->new_enabled = false;
11148 crtc->new_config = NULL;
11149 }
11150
11151 static int intel_crtc_set_config(struct drm_mode_set *set)
11152 {
11153 struct drm_device *dev;
11154 struct drm_mode_set save_set;
11155 struct intel_set_config *config;
11156 int ret;
11157
11158 BUG_ON(!set);
11159 BUG_ON(!set->crtc);
11160 BUG_ON(!set->crtc->helper_private);
11161
11162 /* Enforce sane interface api - has been abused by the fb helper. */
11163 BUG_ON(!set->mode && set->fb);
11164 BUG_ON(set->fb && set->num_connectors == 0);
11165
11166 if (set->fb) {
11167 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11168 set->crtc->base.id, set->fb->base.id,
11169 (int)set->num_connectors, set->x, set->y);
11170 } else {
11171 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11172 }
11173
11174 dev = set->crtc->dev;
11175
11176 ret = -ENOMEM;
11177 config = kzalloc(sizeof(*config), GFP_KERNEL);
11178 if (!config)
11179 goto out_config;
11180
11181 ret = intel_set_config_save_state(dev, config);
11182 if (ret)
11183 goto out_config;
11184
11185 save_set.crtc = set->crtc;
11186 save_set.mode = &set->crtc->mode;
11187 save_set.x = set->crtc->x;
11188 save_set.y = set->crtc->y;
11189 save_set.fb = set->crtc->primary->fb;
11190
11191 /* Compute whether we need a full modeset, only an fb base update or no
11192 * change at all. In the future we might also check whether only the
11193 * mode changed, e.g. for LVDS where we only change the panel fitter in
11194 * such cases. */
11195 intel_set_config_compute_mode_changes(set, config);
11196
11197 ret = intel_modeset_stage_output_state(dev, set, config);
11198 if (ret)
11199 goto fail;
11200
11201 if (config->mode_changed) {
11202 ret = intel_set_mode(set->crtc, set->mode,
11203 set->x, set->y, set->fb);
11204 } else if (config->fb_changed) {
11205 struct drm_i915_private *dev_priv = dev->dev_private;
11206 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11207
11208 intel_crtc_wait_for_pending_flips(set->crtc);
11209
11210 ret = intel_pipe_set_base(set->crtc,
11211 set->x, set->y, set->fb);
11212
11213 /*
11214 * We need to make sure the primary plane is re-enabled if it
11215 * has previously been turned off.
11216 */
11217 if (!intel_crtc->primary_enabled && ret == 0) {
11218 WARN_ON(!intel_crtc->active);
11219 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11220 intel_crtc->pipe);
11221 }
11222
11223 /*
11224 * In the fastboot case this may be our only check of the
11225 * state after boot. It would be better to only do it on
11226 * the first update, but we don't have a nice way of doing that
11227 * (and really, set_config isn't used much for high freq page
11228 * flipping, so increasing its cost here shouldn't be a big
11229 * deal).
11230 */
11231 if (i915.fastboot && ret == 0)
11232 intel_modeset_check_state(set->crtc->dev);
11233 }
11234
11235 if (ret) {
11236 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11237 set->crtc->base.id, ret);
11238 fail:
11239 intel_set_config_restore_state(dev, config);
11240
11241 /*
11242 * HACK: if the pipe was on, but we didn't have a framebuffer,
11243 * force the pipe off to avoid oopsing in the modeset code
11244 * due to fb==NULL. This should only happen during boot since
11245 * we don't yet reconstruct the FB from the hardware state.
11246 */
11247 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11248 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11249
11250 /* Try to restore the config */
11251 if (config->mode_changed &&
11252 intel_set_mode(save_set.crtc, save_set.mode,
11253 save_set.x, save_set.y, save_set.fb))
11254 DRM_ERROR("failed to restore config after modeset failure\n");
11255 }
11256
11257 out_config:
11258 intel_set_config_free(config);
11259 return ret;
11260 }
11261
11262 static const struct drm_crtc_funcs intel_crtc_funcs = {
11263 .gamma_set = intel_crtc_gamma_set,
11264 .set_config = intel_crtc_set_config,
11265 .destroy = intel_crtc_destroy,
11266 .page_flip = intel_crtc_page_flip,
11267 };
11268
11269 static void intel_cpu_pll_init(struct drm_device *dev)
11270 {
11271 if (HAS_DDI(dev))
11272 intel_ddi_pll_init(dev);
11273 }
11274
11275 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11276 struct intel_shared_dpll *pll,
11277 struct intel_dpll_hw_state *hw_state)
11278 {
11279 uint32_t val;
11280
11281 val = I915_READ(PCH_DPLL(pll->id));
11282 hw_state->dpll = val;
11283 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11284 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11285
11286 return val & DPLL_VCO_ENABLE;
11287 }
11288
11289 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11290 struct intel_shared_dpll *pll)
11291 {
11292 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11293 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11294 }
11295
11296 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11297 struct intel_shared_dpll *pll)
11298 {
11299 /* PCH refclock must be enabled first */
11300 ibx_assert_pch_refclk_enabled(dev_priv);
11301
11302 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11303
11304 /* Wait for the clocks to stabilize. */
11305 POSTING_READ(PCH_DPLL(pll->id));
11306 udelay(150);
11307
11308 /* The pixel multiplier can only be updated once the
11309 * DPLL is enabled and the clocks are stable.
11310 *
11311 * So write it again.
11312 */
11313 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11314 POSTING_READ(PCH_DPLL(pll->id));
11315 udelay(200);
11316 }
11317
11318 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11319 struct intel_shared_dpll *pll)
11320 {
11321 struct drm_device *dev = dev_priv->dev;
11322 struct intel_crtc *crtc;
11323
11324 /* Make sure no transcoder isn't still depending on us. */
11325 for_each_intel_crtc(dev, crtc) {
11326 if (intel_crtc_to_shared_dpll(crtc) == pll)
11327 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11328 }
11329
11330 I915_WRITE(PCH_DPLL(pll->id), 0);
11331 POSTING_READ(PCH_DPLL(pll->id));
11332 udelay(200);
11333 }
11334
11335 static char *ibx_pch_dpll_names[] = {
11336 "PCH DPLL A",
11337 "PCH DPLL B",
11338 };
11339
11340 static void ibx_pch_dpll_init(struct drm_device *dev)
11341 {
11342 struct drm_i915_private *dev_priv = dev->dev_private;
11343 int i;
11344
11345 dev_priv->num_shared_dpll = 2;
11346
11347 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11348 dev_priv->shared_dplls[i].id = i;
11349 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11350 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11351 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11352 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11353 dev_priv->shared_dplls[i].get_hw_state =
11354 ibx_pch_dpll_get_hw_state;
11355 }
11356 }
11357
11358 static void intel_shared_dpll_init(struct drm_device *dev)
11359 {
11360 struct drm_i915_private *dev_priv = dev->dev_private;
11361
11362 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11363 ibx_pch_dpll_init(dev);
11364 else
11365 dev_priv->num_shared_dpll = 0;
11366
11367 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11368 }
11369
11370 static int
11371 intel_primary_plane_disable(struct drm_plane *plane)
11372 {
11373 struct drm_device *dev = plane->dev;
11374 struct drm_i915_private *dev_priv = dev->dev_private;
11375 struct intel_plane *intel_plane = to_intel_plane(plane);
11376 struct intel_crtc *intel_crtc;
11377
11378 if (!plane->fb)
11379 return 0;
11380
11381 BUG_ON(!plane->crtc);
11382
11383 intel_crtc = to_intel_crtc(plane->crtc);
11384
11385 /*
11386 * Even though we checked plane->fb above, it's still possible that
11387 * the primary plane has been implicitly disabled because the crtc
11388 * coordinates given weren't visible, or because we detected
11389 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11390 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11391 * In either case, we need to unpin the FB and let the fb pointer get
11392 * updated, but otherwise we don't need to touch the hardware.
11393 */
11394 if (!intel_crtc->primary_enabled)
11395 goto disable_unpin;
11396
11397 intel_crtc_wait_for_pending_flips(plane->crtc);
11398 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11399 intel_plane->pipe);
11400 disable_unpin:
11401 i915_gem_track_fb(to_intel_framebuffer(plane->fb)->obj, NULL,
11402 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11403 intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
11404 plane->fb = NULL;
11405
11406 return 0;
11407 }
11408
11409 static int
11410 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11411 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11412 unsigned int crtc_w, unsigned int crtc_h,
11413 uint32_t src_x, uint32_t src_y,
11414 uint32_t src_w, uint32_t src_h)
11415 {
11416 struct drm_device *dev = crtc->dev;
11417 struct drm_i915_private *dev_priv = dev->dev_private;
11418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11419 struct intel_plane *intel_plane = to_intel_plane(plane);
11420 struct drm_i915_gem_object *obj, *old_obj = NULL;
11421 struct drm_rect dest = {
11422 /* integer pixels */
11423 .x1 = crtc_x,
11424 .y1 = crtc_y,
11425 .x2 = crtc_x + crtc_w,
11426 .y2 = crtc_y + crtc_h,
11427 };
11428 struct drm_rect src = {
11429 /* 16.16 fixed point */
11430 .x1 = src_x,
11431 .y1 = src_y,
11432 .x2 = src_x + src_w,
11433 .y2 = src_y + src_h,
11434 };
11435 const struct drm_rect clip = {
11436 /* integer pixels */
11437 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11438 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11439 };
11440 bool visible;
11441 int ret;
11442
11443 ret = drm_plane_helper_check_update(plane, crtc, fb,
11444 &src, &dest, &clip,
11445 DRM_PLANE_HELPER_NO_SCALING,
11446 DRM_PLANE_HELPER_NO_SCALING,
11447 false, true, &visible);
11448
11449 if (ret)
11450 return ret;
11451
11452 if (plane->fb)
11453 old_obj = to_intel_framebuffer(plane->fb)->obj;
11454 obj = to_intel_framebuffer(fb)->obj;
11455
11456 /*
11457 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11458 * updating the fb pointer, and returning without touching the
11459 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11460 * turn on the display with all planes setup as desired.
11461 */
11462 if (!crtc->enabled) {
11463 /*
11464 * If we already called setplane while the crtc was disabled,
11465 * we may have an fb pinned; unpin it.
11466 */
11467 if (plane->fb)
11468 intel_unpin_fb_obj(old_obj);
11469
11470 i915_gem_track_fb(old_obj, obj,
11471 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11472
11473 /* Pin and return without programming hardware */
11474 return intel_pin_and_fence_fb_obj(dev, obj, NULL);
11475 }
11476
11477 intel_crtc_wait_for_pending_flips(crtc);
11478
11479 /*
11480 * If clipping results in a non-visible primary plane, we'll disable
11481 * the primary plane. Note that this is a bit different than what
11482 * happens if userspace explicitly disables the plane by passing fb=0
11483 * because plane->fb still gets set and pinned.
11484 */
11485 if (!visible) {
11486 /*
11487 * Try to pin the new fb first so that we can bail out if we
11488 * fail.
11489 */
11490 if (plane->fb != fb) {
11491 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11492 if (ret)
11493 return ret;
11494 }
11495
11496 i915_gem_track_fb(old_obj, obj,
11497 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11498
11499 if (intel_crtc->primary_enabled)
11500 intel_disable_primary_hw_plane(dev_priv,
11501 intel_plane->plane,
11502 intel_plane->pipe);
11503
11504
11505 if (plane->fb != fb)
11506 if (plane->fb)
11507 intel_unpin_fb_obj(old_obj);
11508
11509 return 0;
11510 }
11511
11512 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11513 if (ret)
11514 return ret;
11515
11516 if (!intel_crtc->primary_enabled)
11517 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11518 intel_crtc->pipe);
11519
11520 return 0;
11521 }
11522
11523 /* Common destruction function for both primary and cursor planes */
11524 static void intel_plane_destroy(struct drm_plane *plane)
11525 {
11526 struct intel_plane *intel_plane = to_intel_plane(plane);
11527 drm_plane_cleanup(plane);
11528 kfree(intel_plane);
11529 }
11530
11531 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11532 .update_plane = intel_primary_plane_setplane,
11533 .disable_plane = intel_primary_plane_disable,
11534 .destroy = intel_plane_destroy,
11535 };
11536
11537 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11538 int pipe)
11539 {
11540 struct intel_plane *primary;
11541 const uint32_t *intel_primary_formats;
11542 int num_formats;
11543
11544 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11545 if (primary == NULL)
11546 return NULL;
11547
11548 primary->can_scale = false;
11549 primary->max_downscale = 1;
11550 primary->pipe = pipe;
11551 primary->plane = pipe;
11552 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11553 primary->plane = !pipe;
11554
11555 if (INTEL_INFO(dev)->gen <= 3) {
11556 intel_primary_formats = intel_primary_formats_gen2;
11557 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11558 } else {
11559 intel_primary_formats = intel_primary_formats_gen4;
11560 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11561 }
11562
11563 drm_universal_plane_init(dev, &primary->base, 0,
11564 &intel_primary_plane_funcs,
11565 intel_primary_formats, num_formats,
11566 DRM_PLANE_TYPE_PRIMARY);
11567 return &primary->base;
11568 }
11569
11570 static int
11571 intel_cursor_plane_disable(struct drm_plane *plane)
11572 {
11573 if (!plane->fb)
11574 return 0;
11575
11576 BUG_ON(!plane->crtc);
11577
11578 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11579 }
11580
11581 static int
11582 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11583 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11584 unsigned int crtc_w, unsigned int crtc_h,
11585 uint32_t src_x, uint32_t src_y,
11586 uint32_t src_w, uint32_t src_h)
11587 {
11588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11589 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11590 struct drm_i915_gem_object *obj = intel_fb->obj;
11591 struct drm_rect dest = {
11592 /* integer pixels */
11593 .x1 = crtc_x,
11594 .y1 = crtc_y,
11595 .x2 = crtc_x + crtc_w,
11596 .y2 = crtc_y + crtc_h,
11597 };
11598 struct drm_rect src = {
11599 /* 16.16 fixed point */
11600 .x1 = src_x,
11601 .y1 = src_y,
11602 .x2 = src_x + src_w,
11603 .y2 = src_y + src_h,
11604 };
11605 const struct drm_rect clip = {
11606 /* integer pixels */
11607 .x2 = intel_crtc->config.pipe_src_w,
11608 .y2 = intel_crtc->config.pipe_src_h,
11609 };
11610 bool visible;
11611 int ret;
11612
11613 ret = drm_plane_helper_check_update(plane, crtc, fb,
11614 &src, &dest, &clip,
11615 DRM_PLANE_HELPER_NO_SCALING,
11616 DRM_PLANE_HELPER_NO_SCALING,
11617 true, true, &visible);
11618 if (ret)
11619 return ret;
11620
11621 crtc->cursor_x = crtc_x;
11622 crtc->cursor_y = crtc_y;
11623 if (fb != crtc->cursor->fb) {
11624 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11625 } else {
11626 intel_crtc_update_cursor(crtc, visible);
11627 return 0;
11628 }
11629 }
11630 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11631 .update_plane = intel_cursor_plane_update,
11632 .disable_plane = intel_cursor_plane_disable,
11633 .destroy = intel_plane_destroy,
11634 };
11635
11636 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11637 int pipe)
11638 {
11639 struct intel_plane *cursor;
11640
11641 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11642 if (cursor == NULL)
11643 return NULL;
11644
11645 cursor->can_scale = false;
11646 cursor->max_downscale = 1;
11647 cursor->pipe = pipe;
11648 cursor->plane = pipe;
11649
11650 drm_universal_plane_init(dev, &cursor->base, 0,
11651 &intel_cursor_plane_funcs,
11652 intel_cursor_formats,
11653 ARRAY_SIZE(intel_cursor_formats),
11654 DRM_PLANE_TYPE_CURSOR);
11655 return &cursor->base;
11656 }
11657
11658 static void intel_crtc_init(struct drm_device *dev, int pipe)
11659 {
11660 struct drm_i915_private *dev_priv = dev->dev_private;
11661 struct intel_crtc *intel_crtc;
11662 struct drm_plane *primary = NULL;
11663 struct drm_plane *cursor = NULL;
11664 int i, ret;
11665
11666 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11667 if (intel_crtc == NULL)
11668 return;
11669
11670 primary = intel_primary_plane_create(dev, pipe);
11671 if (!primary)
11672 goto fail;
11673
11674 cursor = intel_cursor_plane_create(dev, pipe);
11675 if (!cursor)
11676 goto fail;
11677
11678 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11679 cursor, &intel_crtc_funcs);
11680 if (ret)
11681 goto fail;
11682
11683 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11684 for (i = 0; i < 256; i++) {
11685 intel_crtc->lut_r[i] = i;
11686 intel_crtc->lut_g[i] = i;
11687 intel_crtc->lut_b[i] = i;
11688 }
11689
11690 /*
11691 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11692 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11693 */
11694 intel_crtc->pipe = pipe;
11695 intel_crtc->plane = pipe;
11696 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11697 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11698 intel_crtc->plane = !pipe;
11699 }
11700
11701 intel_crtc->cursor_base = ~0;
11702 intel_crtc->cursor_cntl = ~0;
11703
11704 init_waitqueue_head(&intel_crtc->vbl_wait);
11705
11706 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11707 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11708 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11709 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11710
11711 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11712
11713 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11714 return;
11715
11716 fail:
11717 if (primary)
11718 drm_plane_cleanup(primary);
11719 if (cursor)
11720 drm_plane_cleanup(cursor);
11721 kfree(intel_crtc);
11722 }
11723
11724 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11725 {
11726 struct drm_encoder *encoder = connector->base.encoder;
11727 struct drm_device *dev = connector->base.dev;
11728
11729 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11730
11731 if (!encoder)
11732 return INVALID_PIPE;
11733
11734 return to_intel_crtc(encoder->crtc)->pipe;
11735 }
11736
11737 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11738 struct drm_file *file)
11739 {
11740 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11741 struct drm_mode_object *drmmode_obj;
11742 struct intel_crtc *crtc;
11743
11744 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11745 return -ENODEV;
11746
11747 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11748 DRM_MODE_OBJECT_CRTC);
11749
11750 if (!drmmode_obj) {
11751 DRM_ERROR("no such CRTC id\n");
11752 return -ENOENT;
11753 }
11754
11755 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11756 pipe_from_crtc_id->pipe = crtc->pipe;
11757
11758 return 0;
11759 }
11760
11761 static int intel_encoder_clones(struct intel_encoder *encoder)
11762 {
11763 struct drm_device *dev = encoder->base.dev;
11764 struct intel_encoder *source_encoder;
11765 int index_mask = 0;
11766 int entry = 0;
11767
11768 list_for_each_entry(source_encoder,
11769 &dev->mode_config.encoder_list, base.head) {
11770 if (encoders_cloneable(encoder, source_encoder))
11771 index_mask |= (1 << entry);
11772
11773 entry++;
11774 }
11775
11776 return index_mask;
11777 }
11778
11779 static bool has_edp_a(struct drm_device *dev)
11780 {
11781 struct drm_i915_private *dev_priv = dev->dev_private;
11782
11783 if (!IS_MOBILE(dev))
11784 return false;
11785
11786 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11787 return false;
11788
11789 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11790 return false;
11791
11792 return true;
11793 }
11794
11795 const char *intel_output_name(int output)
11796 {
11797 static const char *names[] = {
11798 [INTEL_OUTPUT_UNUSED] = "Unused",
11799 [INTEL_OUTPUT_ANALOG] = "Analog",
11800 [INTEL_OUTPUT_DVO] = "DVO",
11801 [INTEL_OUTPUT_SDVO] = "SDVO",
11802 [INTEL_OUTPUT_LVDS] = "LVDS",
11803 [INTEL_OUTPUT_TVOUT] = "TV",
11804 [INTEL_OUTPUT_HDMI] = "HDMI",
11805 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11806 [INTEL_OUTPUT_EDP] = "eDP",
11807 [INTEL_OUTPUT_DSI] = "DSI",
11808 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11809 };
11810
11811 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11812 return "Invalid";
11813
11814 return names[output];
11815 }
11816
11817 static bool intel_crt_present(struct drm_device *dev)
11818 {
11819 struct drm_i915_private *dev_priv = dev->dev_private;
11820
11821 if (IS_ULT(dev))
11822 return false;
11823
11824 if (IS_CHERRYVIEW(dev))
11825 return false;
11826
11827 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11828 return false;
11829
11830 return true;
11831 }
11832
11833 static void intel_setup_outputs(struct drm_device *dev)
11834 {
11835 struct drm_i915_private *dev_priv = dev->dev_private;
11836 struct intel_encoder *encoder;
11837 bool dpd_is_edp = false;
11838
11839 intel_lvds_init(dev);
11840
11841 if (intel_crt_present(dev))
11842 intel_crt_init(dev);
11843
11844 if (HAS_DDI(dev)) {
11845 int found;
11846
11847 /* Haswell uses DDI functions to detect digital outputs */
11848 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11849 /* DDI A only supports eDP */
11850 if (found)
11851 intel_ddi_init(dev, PORT_A);
11852
11853 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11854 * register */
11855 found = I915_READ(SFUSE_STRAP);
11856
11857 if (found & SFUSE_STRAP_DDIB_DETECTED)
11858 intel_ddi_init(dev, PORT_B);
11859 if (found & SFUSE_STRAP_DDIC_DETECTED)
11860 intel_ddi_init(dev, PORT_C);
11861 if (found & SFUSE_STRAP_DDID_DETECTED)
11862 intel_ddi_init(dev, PORT_D);
11863 } else if (HAS_PCH_SPLIT(dev)) {
11864 int found;
11865 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11866
11867 if (has_edp_a(dev))
11868 intel_dp_init(dev, DP_A, PORT_A);
11869
11870 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11871 /* PCH SDVOB multiplex with HDMIB */
11872 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11873 if (!found)
11874 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11875 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11876 intel_dp_init(dev, PCH_DP_B, PORT_B);
11877 }
11878
11879 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11880 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11881
11882 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11883 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11884
11885 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11886 intel_dp_init(dev, PCH_DP_C, PORT_C);
11887
11888 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11889 intel_dp_init(dev, PCH_DP_D, PORT_D);
11890 } else if (IS_VALLEYVIEW(dev)) {
11891 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11892 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11893 PORT_B);
11894 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11895 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11896 }
11897
11898 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11899 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11900 PORT_C);
11901 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11902 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11903 }
11904
11905 if (IS_CHERRYVIEW(dev)) {
11906 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11907 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11908 PORT_D);
11909 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11910 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11911 }
11912 }
11913
11914 intel_dsi_init(dev);
11915 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11916 bool found = false;
11917
11918 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11919 DRM_DEBUG_KMS("probing SDVOB\n");
11920 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11921 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11922 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11923 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11924 }
11925
11926 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11927 intel_dp_init(dev, DP_B, PORT_B);
11928 }
11929
11930 /* Before G4X SDVOC doesn't have its own detect register */
11931
11932 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11933 DRM_DEBUG_KMS("probing SDVOC\n");
11934 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11935 }
11936
11937 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11938
11939 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11940 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11941 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11942 }
11943 if (SUPPORTS_INTEGRATED_DP(dev))
11944 intel_dp_init(dev, DP_C, PORT_C);
11945 }
11946
11947 if (SUPPORTS_INTEGRATED_DP(dev) &&
11948 (I915_READ(DP_D) & DP_DETECTED))
11949 intel_dp_init(dev, DP_D, PORT_D);
11950 } else if (IS_GEN2(dev))
11951 intel_dvo_init(dev);
11952
11953 if (SUPPORTS_TV(dev))
11954 intel_tv_init(dev);
11955
11956 intel_edp_psr_init(dev);
11957
11958 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11959 encoder->base.possible_crtcs = encoder->crtc_mask;
11960 encoder->base.possible_clones =
11961 intel_encoder_clones(encoder);
11962 }
11963
11964 intel_init_pch_refclk(dev);
11965
11966 drm_helper_move_panel_connectors_to_head(dev);
11967 }
11968
11969 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11970 {
11971 struct drm_device *dev = fb->dev;
11972 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11973
11974 drm_framebuffer_cleanup(fb);
11975 mutex_lock(&dev->struct_mutex);
11976 WARN_ON(!intel_fb->obj->framebuffer_references--);
11977 drm_gem_object_unreference(&intel_fb->obj->base);
11978 mutex_unlock(&dev->struct_mutex);
11979 kfree(intel_fb);
11980 }
11981
11982 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11983 struct drm_file *file,
11984 unsigned int *handle)
11985 {
11986 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11987 struct drm_i915_gem_object *obj = intel_fb->obj;
11988
11989 return drm_gem_handle_create(file, &obj->base, handle);
11990 }
11991
11992 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11993 .destroy = intel_user_framebuffer_destroy,
11994 .create_handle = intel_user_framebuffer_create_handle,
11995 };
11996
11997 static int intel_framebuffer_init(struct drm_device *dev,
11998 struct intel_framebuffer *intel_fb,
11999 struct drm_mode_fb_cmd2 *mode_cmd,
12000 struct drm_i915_gem_object *obj)
12001 {
12002 int aligned_height;
12003 int pitch_limit;
12004 int ret;
12005
12006 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12007
12008 if (obj->tiling_mode == I915_TILING_Y) {
12009 DRM_DEBUG("hardware does not support tiling Y\n");
12010 return -EINVAL;
12011 }
12012
12013 if (mode_cmd->pitches[0] & 63) {
12014 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12015 mode_cmd->pitches[0]);
12016 return -EINVAL;
12017 }
12018
12019 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12020 pitch_limit = 32*1024;
12021 } else if (INTEL_INFO(dev)->gen >= 4) {
12022 if (obj->tiling_mode)
12023 pitch_limit = 16*1024;
12024 else
12025 pitch_limit = 32*1024;
12026 } else if (INTEL_INFO(dev)->gen >= 3) {
12027 if (obj->tiling_mode)
12028 pitch_limit = 8*1024;
12029 else
12030 pitch_limit = 16*1024;
12031 } else
12032 /* XXX DSPC is limited to 4k tiled */
12033 pitch_limit = 8*1024;
12034
12035 if (mode_cmd->pitches[0] > pitch_limit) {
12036 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12037 obj->tiling_mode ? "tiled" : "linear",
12038 mode_cmd->pitches[0], pitch_limit);
12039 return -EINVAL;
12040 }
12041
12042 if (obj->tiling_mode != I915_TILING_NONE &&
12043 mode_cmd->pitches[0] != obj->stride) {
12044 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12045 mode_cmd->pitches[0], obj->stride);
12046 return -EINVAL;
12047 }
12048
12049 /* Reject formats not supported by any plane early. */
12050 switch (mode_cmd->pixel_format) {
12051 case DRM_FORMAT_C8:
12052 case DRM_FORMAT_RGB565:
12053 case DRM_FORMAT_XRGB8888:
12054 case DRM_FORMAT_ARGB8888:
12055 break;
12056 case DRM_FORMAT_XRGB1555:
12057 case DRM_FORMAT_ARGB1555:
12058 if (INTEL_INFO(dev)->gen > 3) {
12059 DRM_DEBUG("unsupported pixel format: %s\n",
12060 drm_get_format_name(mode_cmd->pixel_format));
12061 return -EINVAL;
12062 }
12063 break;
12064 case DRM_FORMAT_XBGR8888:
12065 case DRM_FORMAT_ABGR8888:
12066 case DRM_FORMAT_XRGB2101010:
12067 case DRM_FORMAT_ARGB2101010:
12068 case DRM_FORMAT_XBGR2101010:
12069 case DRM_FORMAT_ABGR2101010:
12070 if (INTEL_INFO(dev)->gen < 4) {
12071 DRM_DEBUG("unsupported pixel format: %s\n",
12072 drm_get_format_name(mode_cmd->pixel_format));
12073 return -EINVAL;
12074 }
12075 break;
12076 case DRM_FORMAT_YUYV:
12077 case DRM_FORMAT_UYVY:
12078 case DRM_FORMAT_YVYU:
12079 case DRM_FORMAT_VYUY:
12080 if (INTEL_INFO(dev)->gen < 5) {
12081 DRM_DEBUG("unsupported pixel format: %s\n",
12082 drm_get_format_name(mode_cmd->pixel_format));
12083 return -EINVAL;
12084 }
12085 break;
12086 default:
12087 DRM_DEBUG("unsupported pixel format: %s\n",
12088 drm_get_format_name(mode_cmd->pixel_format));
12089 return -EINVAL;
12090 }
12091
12092 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12093 if (mode_cmd->offsets[0] != 0)
12094 return -EINVAL;
12095
12096 aligned_height = intel_align_height(dev, mode_cmd->height,
12097 obj->tiling_mode);
12098 /* FIXME drm helper for size checks (especially planar formats)? */
12099 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12100 return -EINVAL;
12101
12102 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12103 intel_fb->obj = obj;
12104 intel_fb->obj->framebuffer_references++;
12105
12106 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12107 if (ret) {
12108 DRM_ERROR("framebuffer init failed %d\n", ret);
12109 return ret;
12110 }
12111
12112 return 0;
12113 }
12114
12115 static struct drm_framebuffer *
12116 intel_user_framebuffer_create(struct drm_device *dev,
12117 struct drm_file *filp,
12118 struct drm_mode_fb_cmd2 *mode_cmd)
12119 {
12120 struct drm_i915_gem_object *obj;
12121
12122 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12123 mode_cmd->handles[0]));
12124 if (&obj->base == NULL)
12125 return ERR_PTR(-ENOENT);
12126
12127 return intel_framebuffer_create(dev, mode_cmd, obj);
12128 }
12129
12130 #ifndef CONFIG_DRM_I915_FBDEV
12131 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12132 {
12133 }
12134 #endif
12135
12136 static const struct drm_mode_config_funcs intel_mode_funcs = {
12137 .fb_create = intel_user_framebuffer_create,
12138 .output_poll_changed = intel_fbdev_output_poll_changed,
12139 };
12140
12141 /* Set up chip specific display functions */
12142 static void intel_init_display(struct drm_device *dev)
12143 {
12144 struct drm_i915_private *dev_priv = dev->dev_private;
12145
12146 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12147 dev_priv->display.find_dpll = g4x_find_best_dpll;
12148 else if (IS_CHERRYVIEW(dev))
12149 dev_priv->display.find_dpll = chv_find_best_dpll;
12150 else if (IS_VALLEYVIEW(dev))
12151 dev_priv->display.find_dpll = vlv_find_best_dpll;
12152 else if (IS_PINEVIEW(dev))
12153 dev_priv->display.find_dpll = pnv_find_best_dpll;
12154 else
12155 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12156
12157 if (HAS_DDI(dev)) {
12158 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12159 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12160 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12161 dev_priv->display.crtc_enable = haswell_crtc_enable;
12162 dev_priv->display.crtc_disable = haswell_crtc_disable;
12163 dev_priv->display.off = haswell_crtc_off;
12164 dev_priv->display.update_primary_plane =
12165 ironlake_update_primary_plane;
12166 } else if (HAS_PCH_SPLIT(dev)) {
12167 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12168 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12169 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12170 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12171 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12172 dev_priv->display.off = ironlake_crtc_off;
12173 dev_priv->display.update_primary_plane =
12174 ironlake_update_primary_plane;
12175 } else if (IS_VALLEYVIEW(dev)) {
12176 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12177 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12178 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12179 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12180 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12181 dev_priv->display.off = i9xx_crtc_off;
12182 dev_priv->display.update_primary_plane =
12183 i9xx_update_primary_plane;
12184 } else {
12185 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12186 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12187 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12188 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12189 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12190 dev_priv->display.off = i9xx_crtc_off;
12191 dev_priv->display.update_primary_plane =
12192 i9xx_update_primary_plane;
12193 }
12194
12195 /* Returns the core display clock speed */
12196 if (IS_VALLEYVIEW(dev))
12197 dev_priv->display.get_display_clock_speed =
12198 valleyview_get_display_clock_speed;
12199 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12200 dev_priv->display.get_display_clock_speed =
12201 i945_get_display_clock_speed;
12202 else if (IS_I915G(dev))
12203 dev_priv->display.get_display_clock_speed =
12204 i915_get_display_clock_speed;
12205 else if (IS_I945GM(dev) || IS_845G(dev))
12206 dev_priv->display.get_display_clock_speed =
12207 i9xx_misc_get_display_clock_speed;
12208 else if (IS_PINEVIEW(dev))
12209 dev_priv->display.get_display_clock_speed =
12210 pnv_get_display_clock_speed;
12211 else if (IS_I915GM(dev))
12212 dev_priv->display.get_display_clock_speed =
12213 i915gm_get_display_clock_speed;
12214 else if (IS_I865G(dev))
12215 dev_priv->display.get_display_clock_speed =
12216 i865_get_display_clock_speed;
12217 else if (IS_I85X(dev))
12218 dev_priv->display.get_display_clock_speed =
12219 i855_get_display_clock_speed;
12220 else /* 852, 830 */
12221 dev_priv->display.get_display_clock_speed =
12222 i830_get_display_clock_speed;
12223
12224 if (HAS_PCH_SPLIT(dev)) {
12225 if (IS_GEN5(dev)) {
12226 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12227 dev_priv->display.write_eld = ironlake_write_eld;
12228 } else if (IS_GEN6(dev)) {
12229 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12230 dev_priv->display.write_eld = ironlake_write_eld;
12231 dev_priv->display.modeset_global_resources =
12232 snb_modeset_global_resources;
12233 } else if (IS_IVYBRIDGE(dev)) {
12234 /* FIXME: detect B0+ stepping and use auto training */
12235 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12236 dev_priv->display.write_eld = ironlake_write_eld;
12237 dev_priv->display.modeset_global_resources =
12238 ivb_modeset_global_resources;
12239 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12240 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12241 dev_priv->display.write_eld = haswell_write_eld;
12242 dev_priv->display.modeset_global_resources =
12243 haswell_modeset_global_resources;
12244 }
12245 } else if (IS_G4X(dev)) {
12246 dev_priv->display.write_eld = g4x_write_eld;
12247 } else if (IS_VALLEYVIEW(dev)) {
12248 dev_priv->display.modeset_global_resources =
12249 valleyview_modeset_global_resources;
12250 dev_priv->display.write_eld = ironlake_write_eld;
12251 }
12252
12253 /* Default just returns -ENODEV to indicate unsupported */
12254 dev_priv->display.queue_flip = intel_default_queue_flip;
12255
12256 switch (INTEL_INFO(dev)->gen) {
12257 case 2:
12258 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12259 break;
12260
12261 case 3:
12262 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12263 break;
12264
12265 case 4:
12266 case 5:
12267 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12268 break;
12269
12270 case 6:
12271 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12272 break;
12273 case 7:
12274 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12275 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12276 break;
12277 }
12278
12279 intel_panel_init_backlight_funcs(dev);
12280 }
12281
12282 /*
12283 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12284 * resume, or other times. This quirk makes sure that's the case for
12285 * affected systems.
12286 */
12287 static void quirk_pipea_force(struct drm_device *dev)
12288 {
12289 struct drm_i915_private *dev_priv = dev->dev_private;
12290
12291 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12292 DRM_INFO("applying pipe a force quirk\n");
12293 }
12294
12295 /*
12296 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12297 */
12298 static void quirk_ssc_force_disable(struct drm_device *dev)
12299 {
12300 struct drm_i915_private *dev_priv = dev->dev_private;
12301 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12302 DRM_INFO("applying lvds SSC disable quirk\n");
12303 }
12304
12305 /*
12306 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12307 * brightness value
12308 */
12309 static void quirk_invert_brightness(struct drm_device *dev)
12310 {
12311 struct drm_i915_private *dev_priv = dev->dev_private;
12312 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12313 DRM_INFO("applying inverted panel brightness quirk\n");
12314 }
12315
12316 struct intel_quirk {
12317 int device;
12318 int subsystem_vendor;
12319 int subsystem_device;
12320 void (*hook)(struct drm_device *dev);
12321 };
12322
12323 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12324 struct intel_dmi_quirk {
12325 void (*hook)(struct drm_device *dev);
12326 const struct dmi_system_id (*dmi_id_list)[];
12327 };
12328
12329 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12330 {
12331 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12332 return 1;
12333 }
12334
12335 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12336 {
12337 .dmi_id_list = &(const struct dmi_system_id[]) {
12338 {
12339 .callback = intel_dmi_reverse_brightness,
12340 .ident = "NCR Corporation",
12341 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12342 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12343 },
12344 },
12345 { } /* terminating entry */
12346 },
12347 .hook = quirk_invert_brightness,
12348 },
12349 };
12350
12351 static struct intel_quirk intel_quirks[] = {
12352 /* HP Mini needs pipe A force quirk (LP: #322104) */
12353 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12354
12355 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12356 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12357
12358 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12359 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12360
12361 /* Lenovo U160 cannot use SSC on LVDS */
12362 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12363
12364 /* Sony Vaio Y cannot use SSC on LVDS */
12365 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12366
12367 /* Acer Aspire 5734Z must invert backlight brightness */
12368 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12369
12370 /* Acer/eMachines G725 */
12371 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12372
12373 /* Acer/eMachines e725 */
12374 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12375
12376 /* Acer/Packard Bell NCL20 */
12377 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12378
12379 /* Acer Aspire 4736Z */
12380 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12381
12382 /* Acer Aspire 5336 */
12383 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12384 };
12385
12386 static void intel_init_quirks(struct drm_device *dev)
12387 {
12388 struct pci_dev *d = dev->pdev;
12389 int i;
12390
12391 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12392 struct intel_quirk *q = &intel_quirks[i];
12393
12394 if (d->device == q->device &&
12395 (d->subsystem_vendor == q->subsystem_vendor ||
12396 q->subsystem_vendor == PCI_ANY_ID) &&
12397 (d->subsystem_device == q->subsystem_device ||
12398 q->subsystem_device == PCI_ANY_ID))
12399 q->hook(dev);
12400 }
12401 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12402 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12403 intel_dmi_quirks[i].hook(dev);
12404 }
12405 }
12406
12407 /* Disable the VGA plane that we never use */
12408 static void i915_disable_vga(struct drm_device *dev)
12409 {
12410 struct drm_i915_private *dev_priv = dev->dev_private;
12411 u8 sr1;
12412 u32 vga_reg = i915_vgacntrl_reg(dev);
12413
12414 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12415 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12416 outb(SR01, VGA_SR_INDEX);
12417 sr1 = inb(VGA_SR_DATA);
12418 outb(sr1 | 1<<5, VGA_SR_DATA);
12419 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12420 udelay(300);
12421
12422 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12423 POSTING_READ(vga_reg);
12424 }
12425
12426 void intel_modeset_init_hw(struct drm_device *dev)
12427 {
12428 intel_prepare_ddi(dev);
12429
12430 intel_init_clock_gating(dev);
12431
12432 intel_reset_dpio(dev);
12433
12434 intel_enable_gt_powersave(dev);
12435 }
12436
12437 void intel_modeset_suspend_hw(struct drm_device *dev)
12438 {
12439 intel_suspend_hw(dev);
12440 }
12441
12442 void intel_modeset_init(struct drm_device *dev)
12443 {
12444 struct drm_i915_private *dev_priv = dev->dev_private;
12445 int sprite, ret;
12446 enum pipe pipe;
12447 struct intel_crtc *crtc;
12448
12449 drm_mode_config_init(dev);
12450
12451 dev->mode_config.min_width = 0;
12452 dev->mode_config.min_height = 0;
12453
12454 dev->mode_config.preferred_depth = 24;
12455 dev->mode_config.prefer_shadow = 1;
12456
12457 dev->mode_config.funcs = &intel_mode_funcs;
12458
12459 intel_init_quirks(dev);
12460
12461 intel_init_pm(dev);
12462
12463 if (INTEL_INFO(dev)->num_pipes == 0)
12464 return;
12465
12466 intel_init_display(dev);
12467
12468 if (IS_GEN2(dev)) {
12469 dev->mode_config.max_width = 2048;
12470 dev->mode_config.max_height = 2048;
12471 } else if (IS_GEN3(dev)) {
12472 dev->mode_config.max_width = 4096;
12473 dev->mode_config.max_height = 4096;
12474 } else {
12475 dev->mode_config.max_width = 8192;
12476 dev->mode_config.max_height = 8192;
12477 }
12478
12479 if (IS_GEN2(dev)) {
12480 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12481 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12482 } else {
12483 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12484 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12485 }
12486
12487 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12488
12489 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12490 INTEL_INFO(dev)->num_pipes,
12491 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12492
12493 for_each_pipe(pipe) {
12494 intel_crtc_init(dev, pipe);
12495 for_each_sprite(pipe, sprite) {
12496 ret = intel_plane_init(dev, pipe, sprite);
12497 if (ret)
12498 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12499 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12500 }
12501 }
12502
12503 intel_init_dpio(dev);
12504 intel_reset_dpio(dev);
12505
12506 intel_cpu_pll_init(dev);
12507 intel_shared_dpll_init(dev);
12508
12509 /* Just disable it once at startup */
12510 i915_disable_vga(dev);
12511 intel_setup_outputs(dev);
12512
12513 /* Just in case the BIOS is doing something questionable. */
12514 intel_disable_fbc(dev);
12515
12516 drm_modeset_lock_all(dev);
12517 intel_modeset_setup_hw_state(dev, false);
12518 drm_modeset_unlock_all(dev);
12519
12520 for_each_intel_crtc(dev, crtc) {
12521 if (!crtc->active)
12522 continue;
12523
12524 /*
12525 * Note that reserving the BIOS fb up front prevents us
12526 * from stuffing other stolen allocations like the ring
12527 * on top. This prevents some ugliness at boot time, and
12528 * can even allow for smooth boot transitions if the BIOS
12529 * fb is large enough for the active pipe configuration.
12530 */
12531 if (dev_priv->display.get_plane_config) {
12532 dev_priv->display.get_plane_config(crtc,
12533 &crtc->plane_config);
12534 /*
12535 * If the fb is shared between multiple heads, we'll
12536 * just get the first one.
12537 */
12538 intel_find_plane_obj(crtc, &crtc->plane_config);
12539 }
12540 }
12541 }
12542
12543 static void intel_enable_pipe_a(struct drm_device *dev)
12544 {
12545 struct intel_connector *connector;
12546 struct drm_connector *crt = NULL;
12547 struct intel_load_detect_pipe load_detect_temp;
12548 struct drm_modeset_acquire_ctx ctx;
12549
12550 /* We can't just switch on the pipe A, we need to set things up with a
12551 * proper mode and output configuration. As a gross hack, enable pipe A
12552 * by enabling the load detect pipe once. */
12553 list_for_each_entry(connector,
12554 &dev->mode_config.connector_list,
12555 base.head) {
12556 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12557 crt = &connector->base;
12558 break;
12559 }
12560 }
12561
12562 if (!crt)
12563 return;
12564
12565 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12566 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12567
12568
12569 }
12570
12571 static bool
12572 intel_check_plane_mapping(struct intel_crtc *crtc)
12573 {
12574 struct drm_device *dev = crtc->base.dev;
12575 struct drm_i915_private *dev_priv = dev->dev_private;
12576 u32 reg, val;
12577
12578 if (INTEL_INFO(dev)->num_pipes == 1)
12579 return true;
12580
12581 reg = DSPCNTR(!crtc->plane);
12582 val = I915_READ(reg);
12583
12584 if ((val & DISPLAY_PLANE_ENABLE) &&
12585 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12586 return false;
12587
12588 return true;
12589 }
12590
12591 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12592 {
12593 struct drm_device *dev = crtc->base.dev;
12594 struct drm_i915_private *dev_priv = dev->dev_private;
12595 u32 reg;
12596
12597 /* Clear any frame start delays used for debugging left by the BIOS */
12598 reg = PIPECONF(crtc->config.cpu_transcoder);
12599 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12600
12601 /* restore vblank interrupts to correct state */
12602 if (crtc->active)
12603 drm_vblank_on(dev, crtc->pipe);
12604 else
12605 drm_vblank_off(dev, crtc->pipe);
12606
12607 /* We need to sanitize the plane -> pipe mapping first because this will
12608 * disable the crtc (and hence change the state) if it is wrong. Note
12609 * that gen4+ has a fixed plane -> pipe mapping. */
12610 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12611 struct intel_connector *connector;
12612 bool plane;
12613
12614 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12615 crtc->base.base.id);
12616
12617 /* Pipe has the wrong plane attached and the plane is active.
12618 * Temporarily change the plane mapping and disable everything
12619 * ... */
12620 plane = crtc->plane;
12621 crtc->plane = !plane;
12622 dev_priv->display.crtc_disable(&crtc->base);
12623 crtc->plane = plane;
12624
12625 /* ... and break all links. */
12626 list_for_each_entry(connector, &dev->mode_config.connector_list,
12627 base.head) {
12628 if (connector->encoder->base.crtc != &crtc->base)
12629 continue;
12630
12631 connector->base.dpms = DRM_MODE_DPMS_OFF;
12632 connector->base.encoder = NULL;
12633 }
12634 /* multiple connectors may have the same encoder:
12635 * handle them and break crtc link separately */
12636 list_for_each_entry(connector, &dev->mode_config.connector_list,
12637 base.head)
12638 if (connector->encoder->base.crtc == &crtc->base) {
12639 connector->encoder->base.crtc = NULL;
12640 connector->encoder->connectors_active = false;
12641 }
12642
12643 WARN_ON(crtc->active);
12644 crtc->base.enabled = false;
12645 }
12646
12647 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12648 crtc->pipe == PIPE_A && !crtc->active) {
12649 /* BIOS forgot to enable pipe A, this mostly happens after
12650 * resume. Force-enable the pipe to fix this, the update_dpms
12651 * call below we restore the pipe to the right state, but leave
12652 * the required bits on. */
12653 intel_enable_pipe_a(dev);
12654 }
12655
12656 /* Adjust the state of the output pipe according to whether we
12657 * have active connectors/encoders. */
12658 intel_crtc_update_dpms(&crtc->base);
12659
12660 if (crtc->active != crtc->base.enabled) {
12661 struct intel_encoder *encoder;
12662
12663 /* This can happen either due to bugs in the get_hw_state
12664 * functions or because the pipe is force-enabled due to the
12665 * pipe A quirk. */
12666 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12667 crtc->base.base.id,
12668 crtc->base.enabled ? "enabled" : "disabled",
12669 crtc->active ? "enabled" : "disabled");
12670
12671 crtc->base.enabled = crtc->active;
12672
12673 /* Because we only establish the connector -> encoder ->
12674 * crtc links if something is active, this means the
12675 * crtc is now deactivated. Break the links. connector
12676 * -> encoder links are only establish when things are
12677 * actually up, hence no need to break them. */
12678 WARN_ON(crtc->active);
12679
12680 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12681 WARN_ON(encoder->connectors_active);
12682 encoder->base.crtc = NULL;
12683 }
12684 }
12685
12686 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12687 /*
12688 * We start out with underrun reporting disabled to avoid races.
12689 * For correct bookkeeping mark this on active crtcs.
12690 *
12691 * Also on gmch platforms we dont have any hardware bits to
12692 * disable the underrun reporting. Which means we need to start
12693 * out with underrun reporting disabled also on inactive pipes,
12694 * since otherwise we'll complain about the garbage we read when
12695 * e.g. coming up after runtime pm.
12696 *
12697 * No protection against concurrent access is required - at
12698 * worst a fifo underrun happens which also sets this to false.
12699 */
12700 crtc->cpu_fifo_underrun_disabled = true;
12701 crtc->pch_fifo_underrun_disabled = true;
12702
12703 update_scanline_offset(crtc);
12704 }
12705 }
12706
12707 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12708 {
12709 struct intel_connector *connector;
12710 struct drm_device *dev = encoder->base.dev;
12711
12712 /* We need to check both for a crtc link (meaning that the
12713 * encoder is active and trying to read from a pipe) and the
12714 * pipe itself being active. */
12715 bool has_active_crtc = encoder->base.crtc &&
12716 to_intel_crtc(encoder->base.crtc)->active;
12717
12718 if (encoder->connectors_active && !has_active_crtc) {
12719 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12720 encoder->base.base.id,
12721 encoder->base.name);
12722
12723 /* Connector is active, but has no active pipe. This is
12724 * fallout from our resume register restoring. Disable
12725 * the encoder manually again. */
12726 if (encoder->base.crtc) {
12727 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12728 encoder->base.base.id,
12729 encoder->base.name);
12730 encoder->disable(encoder);
12731 }
12732 encoder->base.crtc = NULL;
12733 encoder->connectors_active = false;
12734
12735 /* Inconsistent output/port/pipe state happens presumably due to
12736 * a bug in one of the get_hw_state functions. Or someplace else
12737 * in our code, like the register restore mess on resume. Clamp
12738 * things to off as a safer default. */
12739 list_for_each_entry(connector,
12740 &dev->mode_config.connector_list,
12741 base.head) {
12742 if (connector->encoder != encoder)
12743 continue;
12744 connector->base.dpms = DRM_MODE_DPMS_OFF;
12745 connector->base.encoder = NULL;
12746 }
12747 }
12748 /* Enabled encoders without active connectors will be fixed in
12749 * the crtc fixup. */
12750 }
12751
12752 void i915_redisable_vga_power_on(struct drm_device *dev)
12753 {
12754 struct drm_i915_private *dev_priv = dev->dev_private;
12755 u32 vga_reg = i915_vgacntrl_reg(dev);
12756
12757 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12758 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12759 i915_disable_vga(dev);
12760 }
12761 }
12762
12763 void i915_redisable_vga(struct drm_device *dev)
12764 {
12765 struct drm_i915_private *dev_priv = dev->dev_private;
12766
12767 /* This function can be called both from intel_modeset_setup_hw_state or
12768 * at a very early point in our resume sequence, where the power well
12769 * structures are not yet restored. Since this function is at a very
12770 * paranoid "someone might have enabled VGA while we were not looking"
12771 * level, just check if the power well is enabled instead of trying to
12772 * follow the "don't touch the power well if we don't need it" policy
12773 * the rest of the driver uses. */
12774 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12775 return;
12776
12777 i915_redisable_vga_power_on(dev);
12778 }
12779
12780 static bool primary_get_hw_state(struct intel_crtc *crtc)
12781 {
12782 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12783
12784 if (!crtc->active)
12785 return false;
12786
12787 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12788 }
12789
12790 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12791 {
12792 struct drm_i915_private *dev_priv = dev->dev_private;
12793 enum pipe pipe;
12794 struct intel_crtc *crtc;
12795 struct intel_encoder *encoder;
12796 struct intel_connector *connector;
12797 int i;
12798
12799 for_each_intel_crtc(dev, crtc) {
12800 memset(&crtc->config, 0, sizeof(crtc->config));
12801
12802 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12803
12804 crtc->active = dev_priv->display.get_pipe_config(crtc,
12805 &crtc->config);
12806
12807 crtc->base.enabled = crtc->active;
12808 crtc->primary_enabled = primary_get_hw_state(crtc);
12809
12810 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12811 crtc->base.base.id,
12812 crtc->active ? "enabled" : "disabled");
12813 }
12814
12815 /* FIXME: Smash this into the new shared dpll infrastructure. */
12816 if (HAS_DDI(dev))
12817 intel_ddi_setup_hw_pll_state(dev);
12818
12819 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12820 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12821
12822 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12823 pll->active = 0;
12824 for_each_intel_crtc(dev, crtc) {
12825 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12826 pll->active++;
12827 }
12828 pll->refcount = pll->active;
12829
12830 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12831 pll->name, pll->refcount, pll->on);
12832 }
12833
12834 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12835 base.head) {
12836 pipe = 0;
12837
12838 if (encoder->get_hw_state(encoder, &pipe)) {
12839 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12840 encoder->base.crtc = &crtc->base;
12841 encoder->get_config(encoder, &crtc->config);
12842 } else {
12843 encoder->base.crtc = NULL;
12844 }
12845
12846 encoder->connectors_active = false;
12847 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12848 encoder->base.base.id,
12849 encoder->base.name,
12850 encoder->base.crtc ? "enabled" : "disabled",
12851 pipe_name(pipe));
12852 }
12853
12854 list_for_each_entry(connector, &dev->mode_config.connector_list,
12855 base.head) {
12856 if (connector->get_hw_state(connector)) {
12857 connector->base.dpms = DRM_MODE_DPMS_ON;
12858 connector->encoder->connectors_active = true;
12859 connector->base.encoder = &connector->encoder->base;
12860 } else {
12861 connector->base.dpms = DRM_MODE_DPMS_OFF;
12862 connector->base.encoder = NULL;
12863 }
12864 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12865 connector->base.base.id,
12866 connector->base.name,
12867 connector->base.encoder ? "enabled" : "disabled");
12868 }
12869 }
12870
12871 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12872 * and i915 state tracking structures. */
12873 void intel_modeset_setup_hw_state(struct drm_device *dev,
12874 bool force_restore)
12875 {
12876 struct drm_i915_private *dev_priv = dev->dev_private;
12877 enum pipe pipe;
12878 struct intel_crtc *crtc;
12879 struct intel_encoder *encoder;
12880 int i;
12881
12882 intel_modeset_readout_hw_state(dev);
12883
12884 /*
12885 * Now that we have the config, copy it to each CRTC struct
12886 * Note that this could go away if we move to using crtc_config
12887 * checking everywhere.
12888 */
12889 for_each_intel_crtc(dev, crtc) {
12890 if (crtc->active && i915.fastboot) {
12891 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12892 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12893 crtc->base.base.id);
12894 drm_mode_debug_printmodeline(&crtc->base.mode);
12895 }
12896 }
12897
12898 /* HW state is read out, now we need to sanitize this mess. */
12899 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12900 base.head) {
12901 intel_sanitize_encoder(encoder);
12902 }
12903
12904 for_each_pipe(pipe) {
12905 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12906 intel_sanitize_crtc(crtc);
12907 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12908 }
12909
12910 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12911 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12912
12913 if (!pll->on || pll->active)
12914 continue;
12915
12916 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12917
12918 pll->disable(dev_priv, pll);
12919 pll->on = false;
12920 }
12921
12922 if (HAS_PCH_SPLIT(dev))
12923 ilk_wm_get_hw_state(dev);
12924
12925 if (force_restore) {
12926 i915_redisable_vga(dev);
12927
12928 /*
12929 * We need to use raw interfaces for restoring state to avoid
12930 * checking (bogus) intermediate states.
12931 */
12932 for_each_pipe(pipe) {
12933 struct drm_crtc *crtc =
12934 dev_priv->pipe_to_crtc_mapping[pipe];
12935
12936 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12937 crtc->primary->fb);
12938 }
12939 } else {
12940 intel_modeset_update_staged_output_state(dev);
12941 }
12942
12943 intel_modeset_check_state(dev);
12944 }
12945
12946 void intel_modeset_gem_init(struct drm_device *dev)
12947 {
12948 struct drm_crtc *c;
12949 struct intel_framebuffer *fb;
12950
12951 mutex_lock(&dev->struct_mutex);
12952 intel_init_gt_powersave(dev);
12953 mutex_unlock(&dev->struct_mutex);
12954
12955 intel_modeset_init_hw(dev);
12956
12957 intel_setup_overlay(dev);
12958
12959 /*
12960 * Make sure any fbs we allocated at startup are properly
12961 * pinned & fenced. When we do the allocation it's too early
12962 * for this.
12963 */
12964 mutex_lock(&dev->struct_mutex);
12965 for_each_crtc(dev, c) {
12966 if (!c->primary->fb)
12967 continue;
12968
12969 fb = to_intel_framebuffer(c->primary->fb);
12970 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12971 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12972 to_intel_crtc(c)->pipe);
12973 drm_framebuffer_unreference(c->primary->fb);
12974 c->primary->fb = NULL;
12975 }
12976 }
12977 mutex_unlock(&dev->struct_mutex);
12978 }
12979
12980 void intel_connector_unregister(struct intel_connector *intel_connector)
12981 {
12982 struct drm_connector *connector = &intel_connector->base;
12983
12984 intel_panel_destroy_backlight(connector);
12985 drm_connector_unregister(connector);
12986 }
12987
12988 void intel_modeset_cleanup(struct drm_device *dev)
12989 {
12990 struct drm_i915_private *dev_priv = dev->dev_private;
12991 struct drm_connector *connector;
12992
12993 /*
12994 * Interrupts and polling as the first thing to avoid creating havoc.
12995 * Too much stuff here (turning of rps, connectors, ...) would
12996 * experience fancy races otherwise.
12997 */
12998 drm_irq_uninstall(dev);
12999 cancel_work_sync(&dev_priv->hotplug_work);
13000 /*
13001 * Due to the hpd irq storm handling the hotplug work can re-arm the
13002 * poll handlers. Hence disable polling after hpd handling is shut down.
13003 */
13004 drm_kms_helper_poll_fini(dev);
13005
13006 mutex_lock(&dev->struct_mutex);
13007
13008 intel_unregister_dsm_handler();
13009
13010 intel_disable_fbc(dev);
13011
13012 intel_disable_gt_powersave(dev);
13013
13014 ironlake_teardown_rc6(dev);
13015
13016 mutex_unlock(&dev->struct_mutex);
13017
13018 /* flush any delayed tasks or pending work */
13019 flush_scheduled_work();
13020
13021 /* destroy the backlight and sysfs files before encoders/connectors */
13022 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13023 struct intel_connector *intel_connector;
13024
13025 intel_connector = to_intel_connector(connector);
13026 intel_connector->unregister(intel_connector);
13027 }
13028
13029 drm_mode_config_cleanup(dev);
13030
13031 intel_cleanup_overlay(dev);
13032
13033 mutex_lock(&dev->struct_mutex);
13034 intel_cleanup_gt_powersave(dev);
13035 mutex_unlock(&dev->struct_mutex);
13036 }
13037
13038 /*
13039 * Return which encoder is currently attached for connector.
13040 */
13041 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13042 {
13043 return &intel_attached_encoder(connector)->base;
13044 }
13045
13046 void intel_connector_attach_encoder(struct intel_connector *connector,
13047 struct intel_encoder *encoder)
13048 {
13049 connector->encoder = encoder;
13050 drm_mode_connector_attach_encoder(&connector->base,
13051 &encoder->base);
13052 }
13053
13054 /*
13055 * set vga decode state - true == enable VGA decode
13056 */
13057 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13058 {
13059 struct drm_i915_private *dev_priv = dev->dev_private;
13060 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13061 u16 gmch_ctrl;
13062
13063 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13064 DRM_ERROR("failed to read control word\n");
13065 return -EIO;
13066 }
13067
13068 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13069 return 0;
13070
13071 if (state)
13072 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13073 else
13074 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13075
13076 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13077 DRM_ERROR("failed to write control word\n");
13078 return -EIO;
13079 }
13080
13081 return 0;
13082 }
13083
13084 struct intel_display_error_state {
13085
13086 u32 power_well_driver;
13087
13088 int num_transcoders;
13089
13090 struct intel_cursor_error_state {
13091 u32 control;
13092 u32 position;
13093 u32 base;
13094 u32 size;
13095 } cursor[I915_MAX_PIPES];
13096
13097 struct intel_pipe_error_state {
13098 bool power_domain_on;
13099 u32 source;
13100 u32 stat;
13101 } pipe[I915_MAX_PIPES];
13102
13103 struct intel_plane_error_state {
13104 u32 control;
13105 u32 stride;
13106 u32 size;
13107 u32 pos;
13108 u32 addr;
13109 u32 surface;
13110 u32 tile_offset;
13111 } plane[I915_MAX_PIPES];
13112
13113 struct intel_transcoder_error_state {
13114 bool power_domain_on;
13115 enum transcoder cpu_transcoder;
13116
13117 u32 conf;
13118
13119 u32 htotal;
13120 u32 hblank;
13121 u32 hsync;
13122 u32 vtotal;
13123 u32 vblank;
13124 u32 vsync;
13125 } transcoder[4];
13126 };
13127
13128 struct intel_display_error_state *
13129 intel_display_capture_error_state(struct drm_device *dev)
13130 {
13131 struct drm_i915_private *dev_priv = dev->dev_private;
13132 struct intel_display_error_state *error;
13133 int transcoders[] = {
13134 TRANSCODER_A,
13135 TRANSCODER_B,
13136 TRANSCODER_C,
13137 TRANSCODER_EDP,
13138 };
13139 int i;
13140
13141 if (INTEL_INFO(dev)->num_pipes == 0)
13142 return NULL;
13143
13144 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13145 if (error == NULL)
13146 return NULL;
13147
13148 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13149 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13150
13151 for_each_pipe(i) {
13152 error->pipe[i].power_domain_on =
13153 intel_display_power_enabled_unlocked(dev_priv,
13154 POWER_DOMAIN_PIPE(i));
13155 if (!error->pipe[i].power_domain_on)
13156 continue;
13157
13158 error->cursor[i].control = I915_READ(CURCNTR(i));
13159 error->cursor[i].position = I915_READ(CURPOS(i));
13160 error->cursor[i].base = I915_READ(CURBASE(i));
13161
13162 error->plane[i].control = I915_READ(DSPCNTR(i));
13163 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13164 if (INTEL_INFO(dev)->gen <= 3) {
13165 error->plane[i].size = I915_READ(DSPSIZE(i));
13166 error->plane[i].pos = I915_READ(DSPPOS(i));
13167 }
13168 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13169 error->plane[i].addr = I915_READ(DSPADDR(i));
13170 if (INTEL_INFO(dev)->gen >= 4) {
13171 error->plane[i].surface = I915_READ(DSPSURF(i));
13172 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13173 }
13174
13175 error->pipe[i].source = I915_READ(PIPESRC(i));
13176
13177 if (!HAS_PCH_SPLIT(dev))
13178 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13179 }
13180
13181 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13182 if (HAS_DDI(dev_priv->dev))
13183 error->num_transcoders++; /* Account for eDP. */
13184
13185 for (i = 0; i < error->num_transcoders; i++) {
13186 enum transcoder cpu_transcoder = transcoders[i];
13187
13188 error->transcoder[i].power_domain_on =
13189 intel_display_power_enabled_unlocked(dev_priv,
13190 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13191 if (!error->transcoder[i].power_domain_on)
13192 continue;
13193
13194 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13195
13196 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13197 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13198 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13199 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13200 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13201 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13202 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13203 }
13204
13205 return error;
13206 }
13207
13208 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13209
13210 void
13211 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13212 struct drm_device *dev,
13213 struct intel_display_error_state *error)
13214 {
13215 int i;
13216
13217 if (!error)
13218 return;
13219
13220 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13221 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13222 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13223 error->power_well_driver);
13224 for_each_pipe(i) {
13225 err_printf(m, "Pipe [%d]:\n", i);
13226 err_printf(m, " Power: %s\n",
13227 error->pipe[i].power_domain_on ? "on" : "off");
13228 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13229 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13230
13231 err_printf(m, "Plane [%d]:\n", i);
13232 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13233 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13234 if (INTEL_INFO(dev)->gen <= 3) {
13235 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13236 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13237 }
13238 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13239 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13240 if (INTEL_INFO(dev)->gen >= 4) {
13241 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13242 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13243 }
13244
13245 err_printf(m, "Cursor [%d]:\n", i);
13246 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13247 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13248 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13249 }
13250
13251 for (i = 0; i < error->num_transcoders; i++) {
13252 err_printf(m, "CPU transcoder: %c\n",
13253 transcoder_name(error->transcoder[i].cpu_transcoder));
13254 err_printf(m, " Power: %s\n",
13255 error->transcoder[i].power_domain_on ? "on" : "off");
13256 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13257 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13258 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13259 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13260 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13261 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13262 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13263 }
13264 }
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