2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
51 static bool is_mmio_work(struct intel_flip_work
*work
)
53 return work
->mmio_work
.func
;
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats
[] = {
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats
[] = {
70 DRM_FORMAT_XRGB2101010
,
71 DRM_FORMAT_XBGR2101010
,
74 static const uint32_t skl_primary_formats
[] = {
81 DRM_FORMAT_XRGB2101010
,
82 DRM_FORMAT_XBGR2101010
,
90 static const uint32_t intel_cursor_formats
[] = {
94 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
95 struct intel_crtc_state
*pipe_config
);
96 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
97 struct intel_crtc_state
*pipe_config
);
99 static int intel_framebuffer_init(struct drm_device
*dev
,
100 struct intel_framebuffer
*ifb
,
101 struct drm_mode_fb_cmd2
*mode_cmd
,
102 struct drm_i915_gem_object
*obj
);
103 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
104 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
105 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
107 struct intel_link_m_n
*m_n
,
108 struct intel_link_m_n
*m2_n2
);
109 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
110 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
111 static void haswell_set_pipemisc(struct drm_crtc
*crtc
);
112 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
113 const struct intel_crtc_state
*pipe_config
);
114 static void chv_prepare_pll(struct intel_crtc
*crtc
,
115 const struct intel_crtc_state
*pipe_config
);
116 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
117 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
118 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
119 struct intel_crtc_state
*crtc_state
);
120 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
121 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
122 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
123 static void intel_modeset_setup_hw_state(struct drm_device
*dev
);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
125 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
);
126 static int glk_calc_cdclk(int max_pixclk
);
127 static int bxt_calc_cdclk(int max_pixclk
);
132 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
136 int p2_slow
, p2_fast
;
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
143 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv
->sb_lock
);
147 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
148 CCK_FUSE_HPLL_FREQ_MASK
;
149 mutex_unlock(&dev_priv
->sb_lock
);
151 return vco_freq
[hpll_freq
] * 1000;
154 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
155 const char *name
, u32 reg
, int ref_freq
)
160 mutex_lock(&dev_priv
->sb_lock
);
161 val
= vlv_cck_read(dev_priv
, reg
);
162 mutex_unlock(&dev_priv
->sb_lock
);
164 divider
= val
& CCK_FREQUENCY_VALUES
;
166 WARN((val
& CCK_FREQUENCY_STATUS
) !=
167 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
168 "%s change in progress\n", name
);
170 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
174 const char *name
, u32 reg
)
176 if (dev_priv
->hpll_freq
== 0)
177 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
179 return vlv_get_cck_clock(dev_priv
, name
, reg
,
180 dev_priv
->hpll_freq
);
184 intel_pch_rawclk(struct drm_i915_private
*dev_priv
)
186 return (I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
) * 1000;
190 intel_vlv_hrawclk(struct drm_i915_private
*dev_priv
)
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv
, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL
);
198 intel_g4x_hrawclk(struct drm_i915_private
*dev_priv
)
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg
= I915_READ(CLKCFG
);
204 switch (clkcfg
& CLKCFG_FSB_MASK
) {
213 case CLKCFG_FSB_1067
:
215 case CLKCFG_FSB_1333
:
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600
:
219 case CLKCFG_FSB_1600_ALT
:
226 void intel_update_rawclk(struct drm_i915_private
*dev_priv
)
228 if (HAS_PCH_SPLIT(dev_priv
))
229 dev_priv
->rawclk_freq
= intel_pch_rawclk(dev_priv
);
230 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
231 dev_priv
->rawclk_freq
= intel_vlv_hrawclk(dev_priv
);
232 else if (IS_G4X(dev_priv
) || IS_PINEVIEW(dev_priv
))
233 dev_priv
->rawclk_freq
= intel_g4x_hrawclk(dev_priv
);
235 return; /* no rawclk on other platforms, or no need to know it */
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv
->rawclk_freq
);
240 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
242 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
245 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
246 CCK_CZ_CLOCK_CONTROL
);
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
251 static inline u32
/* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
253 const struct intel_crtc_state
*pipe_config
)
255 if (HAS_DDI(dev_priv
))
256 return pipe_config
->port_clock
; /* SPLL */
257 else if (IS_GEN5(dev_priv
))
258 return ((I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2) * 10000;
263 static const struct intel_limit intel_limits_i8xx_dac
= {
264 .dot
= { .min
= 25000, .max
= 350000 },
265 .vco
= { .min
= 908000, .max
= 1512000 },
266 .n
= { .min
= 2, .max
= 16 },
267 .m
= { .min
= 96, .max
= 140 },
268 .m1
= { .min
= 18, .max
= 26 },
269 .m2
= { .min
= 6, .max
= 16 },
270 .p
= { .min
= 4, .max
= 128 },
271 .p1
= { .min
= 2, .max
= 33 },
272 .p2
= { .dot_limit
= 165000,
273 .p2_slow
= 4, .p2_fast
= 2 },
276 static const struct intel_limit intel_limits_i8xx_dvo
= {
277 .dot
= { .min
= 25000, .max
= 350000 },
278 .vco
= { .min
= 908000, .max
= 1512000 },
279 .n
= { .min
= 2, .max
= 16 },
280 .m
= { .min
= 96, .max
= 140 },
281 .m1
= { .min
= 18, .max
= 26 },
282 .m2
= { .min
= 6, .max
= 16 },
283 .p
= { .min
= 4, .max
= 128 },
284 .p1
= { .min
= 2, .max
= 33 },
285 .p2
= { .dot_limit
= 165000,
286 .p2_slow
= 4, .p2_fast
= 4 },
289 static const struct intel_limit intel_limits_i8xx_lvds
= {
290 .dot
= { .min
= 25000, .max
= 350000 },
291 .vco
= { .min
= 908000, .max
= 1512000 },
292 .n
= { .min
= 2, .max
= 16 },
293 .m
= { .min
= 96, .max
= 140 },
294 .m1
= { .min
= 18, .max
= 26 },
295 .m2
= { .min
= 6, .max
= 16 },
296 .p
= { .min
= 4, .max
= 128 },
297 .p1
= { .min
= 1, .max
= 6 },
298 .p2
= { .dot_limit
= 165000,
299 .p2_slow
= 14, .p2_fast
= 7 },
302 static const struct intel_limit intel_limits_i9xx_sdvo
= {
303 .dot
= { .min
= 20000, .max
= 400000 },
304 .vco
= { .min
= 1400000, .max
= 2800000 },
305 .n
= { .min
= 1, .max
= 6 },
306 .m
= { .min
= 70, .max
= 120 },
307 .m1
= { .min
= 8, .max
= 18 },
308 .m2
= { .min
= 3, .max
= 7 },
309 .p
= { .min
= 5, .max
= 80 },
310 .p1
= { .min
= 1, .max
= 8 },
311 .p2
= { .dot_limit
= 200000,
312 .p2_slow
= 10, .p2_fast
= 5 },
315 static const struct intel_limit intel_limits_i9xx_lvds
= {
316 .dot
= { .min
= 20000, .max
= 400000 },
317 .vco
= { .min
= 1400000, .max
= 2800000 },
318 .n
= { .min
= 1, .max
= 6 },
319 .m
= { .min
= 70, .max
= 120 },
320 .m1
= { .min
= 8, .max
= 18 },
321 .m2
= { .min
= 3, .max
= 7 },
322 .p
= { .min
= 7, .max
= 98 },
323 .p1
= { .min
= 1, .max
= 8 },
324 .p2
= { .dot_limit
= 112000,
325 .p2_slow
= 14, .p2_fast
= 7 },
329 static const struct intel_limit intel_limits_g4x_sdvo
= {
330 .dot
= { .min
= 25000, .max
= 270000 },
331 .vco
= { .min
= 1750000, .max
= 3500000},
332 .n
= { .min
= 1, .max
= 4 },
333 .m
= { .min
= 104, .max
= 138 },
334 .m1
= { .min
= 17, .max
= 23 },
335 .m2
= { .min
= 5, .max
= 11 },
336 .p
= { .min
= 10, .max
= 30 },
337 .p1
= { .min
= 1, .max
= 3},
338 .p2
= { .dot_limit
= 270000,
344 static const struct intel_limit intel_limits_g4x_hdmi
= {
345 .dot
= { .min
= 22000, .max
= 400000 },
346 .vco
= { .min
= 1750000, .max
= 3500000},
347 .n
= { .min
= 1, .max
= 4 },
348 .m
= { .min
= 104, .max
= 138 },
349 .m1
= { .min
= 16, .max
= 23 },
350 .m2
= { .min
= 5, .max
= 11 },
351 .p
= { .min
= 5, .max
= 80 },
352 .p1
= { .min
= 1, .max
= 8},
353 .p2
= { .dot_limit
= 165000,
354 .p2_slow
= 10, .p2_fast
= 5 },
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
358 .dot
= { .min
= 20000, .max
= 115000 },
359 .vco
= { .min
= 1750000, .max
= 3500000 },
360 .n
= { .min
= 1, .max
= 3 },
361 .m
= { .min
= 104, .max
= 138 },
362 .m1
= { .min
= 17, .max
= 23 },
363 .m2
= { .min
= 5, .max
= 11 },
364 .p
= { .min
= 28, .max
= 112 },
365 .p1
= { .min
= 2, .max
= 8 },
366 .p2
= { .dot_limit
= 0,
367 .p2_slow
= 14, .p2_fast
= 14
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
372 .dot
= { .min
= 80000, .max
= 224000 },
373 .vco
= { .min
= 1750000, .max
= 3500000 },
374 .n
= { .min
= 1, .max
= 3 },
375 .m
= { .min
= 104, .max
= 138 },
376 .m1
= { .min
= 17, .max
= 23 },
377 .m2
= { .min
= 5, .max
= 11 },
378 .p
= { .min
= 14, .max
= 42 },
379 .p1
= { .min
= 2, .max
= 6 },
380 .p2
= { .dot_limit
= 0,
381 .p2_slow
= 7, .p2_fast
= 7
385 static const struct intel_limit intel_limits_pineview_sdvo
= {
386 .dot
= { .min
= 20000, .max
= 400000},
387 .vco
= { .min
= 1700000, .max
= 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n
= { .min
= 3, .max
= 6 },
390 .m
= { .min
= 2, .max
= 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1
= { .min
= 0, .max
= 0 },
393 .m2
= { .min
= 0, .max
= 254 },
394 .p
= { .min
= 5, .max
= 80 },
395 .p1
= { .min
= 1, .max
= 8 },
396 .p2
= { .dot_limit
= 200000,
397 .p2_slow
= 10, .p2_fast
= 5 },
400 static const struct intel_limit intel_limits_pineview_lvds
= {
401 .dot
= { .min
= 20000, .max
= 400000 },
402 .vco
= { .min
= 1700000, .max
= 3500000 },
403 .n
= { .min
= 3, .max
= 6 },
404 .m
= { .min
= 2, .max
= 256 },
405 .m1
= { .min
= 0, .max
= 0 },
406 .m2
= { .min
= 0, .max
= 254 },
407 .p
= { .min
= 7, .max
= 112 },
408 .p1
= { .min
= 1, .max
= 8 },
409 .p2
= { .dot_limit
= 112000,
410 .p2_slow
= 14, .p2_fast
= 14 },
413 /* Ironlake / Sandybridge
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
418 static const struct intel_limit intel_limits_ironlake_dac
= {
419 .dot
= { .min
= 25000, .max
= 350000 },
420 .vco
= { .min
= 1760000, .max
= 3510000 },
421 .n
= { .min
= 1, .max
= 5 },
422 .m
= { .min
= 79, .max
= 127 },
423 .m1
= { .min
= 12, .max
= 22 },
424 .m2
= { .min
= 5, .max
= 9 },
425 .p
= { .min
= 5, .max
= 80 },
426 .p1
= { .min
= 1, .max
= 8 },
427 .p2
= { .dot_limit
= 225000,
428 .p2_slow
= 10, .p2_fast
= 5 },
431 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
432 .dot
= { .min
= 25000, .max
= 350000 },
433 .vco
= { .min
= 1760000, .max
= 3510000 },
434 .n
= { .min
= 1, .max
= 3 },
435 .m
= { .min
= 79, .max
= 118 },
436 .m1
= { .min
= 12, .max
= 22 },
437 .m2
= { .min
= 5, .max
= 9 },
438 .p
= { .min
= 28, .max
= 112 },
439 .p1
= { .min
= 2, .max
= 8 },
440 .p2
= { .dot_limit
= 225000,
441 .p2_slow
= 14, .p2_fast
= 14 },
444 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
445 .dot
= { .min
= 25000, .max
= 350000 },
446 .vco
= { .min
= 1760000, .max
= 3510000 },
447 .n
= { .min
= 1, .max
= 3 },
448 .m
= { .min
= 79, .max
= 127 },
449 .m1
= { .min
= 12, .max
= 22 },
450 .m2
= { .min
= 5, .max
= 9 },
451 .p
= { .min
= 14, .max
= 56 },
452 .p1
= { .min
= 2, .max
= 8 },
453 .p2
= { .dot_limit
= 225000,
454 .p2_slow
= 7, .p2_fast
= 7 },
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
459 .dot
= { .min
= 25000, .max
= 350000 },
460 .vco
= { .min
= 1760000, .max
= 3510000 },
461 .n
= { .min
= 1, .max
= 2 },
462 .m
= { .min
= 79, .max
= 126 },
463 .m1
= { .min
= 12, .max
= 22 },
464 .m2
= { .min
= 5, .max
= 9 },
465 .p
= { .min
= 28, .max
= 112 },
466 .p1
= { .min
= 2, .max
= 8 },
467 .p2
= { .dot_limit
= 225000,
468 .p2_slow
= 14, .p2_fast
= 14 },
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
472 .dot
= { .min
= 25000, .max
= 350000 },
473 .vco
= { .min
= 1760000, .max
= 3510000 },
474 .n
= { .min
= 1, .max
= 3 },
475 .m
= { .min
= 79, .max
= 126 },
476 .m1
= { .min
= 12, .max
= 22 },
477 .m2
= { .min
= 5, .max
= 9 },
478 .p
= { .min
= 14, .max
= 42 },
479 .p1
= { .min
= 2, .max
= 6 },
480 .p2
= { .dot_limit
= 225000,
481 .p2_slow
= 7, .p2_fast
= 7 },
484 static const struct intel_limit intel_limits_vlv
= {
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
491 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
492 .vco
= { .min
= 4000000, .max
= 6000000 },
493 .n
= { .min
= 1, .max
= 7 },
494 .m1
= { .min
= 2, .max
= 3 },
495 .m2
= { .min
= 11, .max
= 156 },
496 .p1
= { .min
= 2, .max
= 3 },
497 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
500 static const struct intel_limit intel_limits_chv
= {
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
507 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
508 .vco
= { .min
= 4800000, .max
= 6480000 },
509 .n
= { .min
= 1, .max
= 1 },
510 .m1
= { .min
= 2, .max
= 2 },
511 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
512 .p1
= { .min
= 2, .max
= 4 },
513 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
516 static const struct intel_limit intel_limits_bxt
= {
517 /* FIXME: find real dot limits */
518 .dot
= { .min
= 0, .max
= INT_MAX
},
519 .vco
= { .min
= 4800000, .max
= 6700000 },
520 .n
= { .min
= 1, .max
= 1 },
521 .m1
= { .min
= 2, .max
= 2 },
522 /* FIXME: find real m2 limits */
523 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
524 .p1
= { .min
= 2, .max
= 4 },
525 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
529 needs_modeset(struct drm_crtc_state
*state
)
531 return drm_atomic_crtc_needs_modeset(state
);
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
545 clock
->m
= clock
->m2
+ 2;
546 clock
->p
= clock
->p1
* clock
->p2
;
547 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
549 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
550 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
555 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
557 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
560 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
562 clock
->m
= i9xx_dpll_compute_m(clock
);
563 clock
->p
= clock
->p1
* clock
->p2
;
564 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
566 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
567 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
572 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
574 clock
->m
= clock
->m1
* clock
->m2
;
575 clock
->p
= clock
->p1
* clock
->p2
;
576 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
578 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
579 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
581 return clock
->dot
/ 5;
584 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
586 clock
->m
= clock
->m1
* clock
->m2
;
587 clock
->p
= clock
->p1
* clock
->p2
;
588 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
590 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
592 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
594 return clock
->dot
/ 5;
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
603 static bool intel_PLL_is_valid(struct drm_i915_private
*dev_priv
,
604 const struct intel_limit
*limit
,
605 const struct dpll
*clock
)
607 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
608 INTELPllInvalid("n out of range\n");
609 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
614 INTELPllInvalid("m1 out of range\n");
616 if (!IS_PINEVIEW(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
617 !IS_CHERRYVIEW(dev_priv
) && !IS_GEN9_LP(dev_priv
))
618 if (clock
->m1
<= clock
->m2
)
619 INTELPllInvalid("m1 <= m2\n");
621 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
622 !IS_GEN9_LP(dev_priv
)) {
623 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
624 INTELPllInvalid("p out of range\n");
625 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
626 INTELPllInvalid("m out of range\n");
629 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
630 INTELPllInvalid("vco out of range\n");
631 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
632 * connector, etc., rather than just a single range.
634 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
635 INTELPllInvalid("dot out of range\n");
641 i9xx_select_p2_div(const struct intel_limit
*limit
,
642 const struct intel_crtc_state
*crtc_state
,
645 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
647 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
649 * For LVDS just rely on its current settings for dual-channel.
650 * We haven't figured out how to reliably set up different
651 * single/dual channel state, if we even can.
653 if (intel_is_dual_link_lvds(dev
))
654 return limit
->p2
.p2_fast
;
656 return limit
->p2
.p2_slow
;
658 if (target
< limit
->p2
.dot_limit
)
659 return limit
->p2
.p2_slow
;
661 return limit
->p2
.p2_fast
;
666 * Returns a set of divisors for the desired target clock with the given
667 * refclk, or FALSE. The returned values represent the clock equation:
668 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
670 * Target and reference clocks are specified in kHz.
672 * If match_clock is provided, then best_clock P divider must match the P
673 * divider from @match_clock used for LVDS downclocking.
676 i9xx_find_best_dpll(const struct intel_limit
*limit
,
677 struct intel_crtc_state
*crtc_state
,
678 int target
, int refclk
, struct dpll
*match_clock
,
679 struct dpll
*best_clock
)
681 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
685 memset(best_clock
, 0, sizeof(*best_clock
));
687 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
689 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
691 for (clock
.m2
= limit
->m2
.min
;
692 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
693 if (clock
.m2
>= clock
.m1
)
695 for (clock
.n
= limit
->n
.min
;
696 clock
.n
<= limit
->n
.max
; clock
.n
++) {
697 for (clock
.p1
= limit
->p1
.min
;
698 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
701 i9xx_calc_dpll_params(refclk
, &clock
);
702 if (!intel_PLL_is_valid(to_i915(dev
),
707 clock
.p
!= match_clock
->p
)
710 this_err
= abs(clock
.dot
- target
);
711 if (this_err
< err
) {
720 return (err
!= target
);
724 * Returns a set of divisors for the desired target clock with the given
725 * refclk, or FALSE. The returned values represent the clock equation:
726 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
728 * Target and reference clocks are specified in kHz.
730 * If match_clock is provided, then best_clock P divider must match the P
731 * divider from @match_clock used for LVDS downclocking.
734 pnv_find_best_dpll(const struct intel_limit
*limit
,
735 struct intel_crtc_state
*crtc_state
,
736 int target
, int refclk
, struct dpll
*match_clock
,
737 struct dpll
*best_clock
)
739 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
743 memset(best_clock
, 0, sizeof(*best_clock
));
745 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
747 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
749 for (clock
.m2
= limit
->m2
.min
;
750 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
751 for (clock
.n
= limit
->n
.min
;
752 clock
.n
<= limit
->n
.max
; clock
.n
++) {
753 for (clock
.p1
= limit
->p1
.min
;
754 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
757 pnv_calc_dpll_params(refclk
, &clock
);
758 if (!intel_PLL_is_valid(to_i915(dev
),
763 clock
.p
!= match_clock
->p
)
766 this_err
= abs(clock
.dot
- target
);
767 if (this_err
< err
) {
776 return (err
!= target
);
780 * Returns a set of divisors for the desired target clock with the given
781 * refclk, or FALSE. The returned values represent the clock equation:
782 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
784 * Target and reference clocks are specified in kHz.
786 * If match_clock is provided, then best_clock P divider must match the P
787 * divider from @match_clock used for LVDS downclocking.
790 g4x_find_best_dpll(const struct intel_limit
*limit
,
791 struct intel_crtc_state
*crtc_state
,
792 int target
, int refclk
, struct dpll
*match_clock
,
793 struct dpll
*best_clock
)
795 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
799 /* approximately equals target * 0.00585 */
800 int err_most
= (target
>> 8) + (target
>> 9);
802 memset(best_clock
, 0, sizeof(*best_clock
));
804 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
806 max_n
= limit
->n
.max
;
807 /* based on hardware requirement, prefer smaller n to precision */
808 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
809 /* based on hardware requirement, prefere larger m1,m2 */
810 for (clock
.m1
= limit
->m1
.max
;
811 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
812 for (clock
.m2
= limit
->m2
.max
;
813 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
814 for (clock
.p1
= limit
->p1
.max
;
815 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
818 i9xx_calc_dpll_params(refclk
, &clock
);
819 if (!intel_PLL_is_valid(to_i915(dev
),
824 this_err
= abs(clock
.dot
- target
);
825 if (this_err
< err_most
) {
839 * Check if the calculated PLL configuration is more optimal compared to the
840 * best configuration and error found so far. Return the calculated error.
842 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
843 const struct dpll
*calculated_clock
,
844 const struct dpll
*best_clock
,
845 unsigned int best_error_ppm
,
846 unsigned int *error_ppm
)
849 * For CHV ignore the error and consider only the P value.
850 * Prefer a bigger P value based on HW requirements.
852 if (IS_CHERRYVIEW(to_i915(dev
))) {
855 return calculated_clock
->p
> best_clock
->p
;
858 if (WARN_ON_ONCE(!target_freq
))
861 *error_ppm
= div_u64(1000000ULL *
862 abs(target_freq
- calculated_clock
->dot
),
865 * Prefer a better P value over a better (smaller) error if the error
866 * is small. Ensure this preference for future configurations too by
867 * setting the error to 0.
869 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
875 return *error_ppm
+ 10 < best_error_ppm
;
879 * Returns a set of divisors for the desired target clock with the given
880 * refclk, or FALSE. The returned values represent the clock equation:
881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
884 vlv_find_best_dpll(const struct intel_limit
*limit
,
885 struct intel_crtc_state
*crtc_state
,
886 int target
, int refclk
, struct dpll
*match_clock
,
887 struct dpll
*best_clock
)
889 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
890 struct drm_device
*dev
= crtc
->base
.dev
;
892 unsigned int bestppm
= 1000000;
893 /* min update 19.2 MHz */
894 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
897 target
*= 5; /* fast clock */
899 memset(best_clock
, 0, sizeof(*best_clock
));
901 /* based on hardware requirement, prefer smaller n to precision */
902 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
903 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
904 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
905 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
906 clock
.p
= clock
.p1
* clock
.p2
;
907 /* based on hardware requirement, prefer bigger m1,m2 values */
908 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
911 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
914 vlv_calc_dpll_params(refclk
, &clock
);
916 if (!intel_PLL_is_valid(to_i915(dev
),
921 if (!vlv_PLL_is_optimal(dev
, target
,
939 * Returns a set of divisors for the desired target clock with the given
940 * refclk, or FALSE. The returned values represent the clock equation:
941 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
944 chv_find_best_dpll(const struct intel_limit
*limit
,
945 struct intel_crtc_state
*crtc_state
,
946 int target
, int refclk
, struct dpll
*match_clock
,
947 struct dpll
*best_clock
)
949 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
950 struct drm_device
*dev
= crtc
->base
.dev
;
951 unsigned int best_error_ppm
;
956 memset(best_clock
, 0, sizeof(*best_clock
));
957 best_error_ppm
= 1000000;
960 * Based on hardware doc, the n always set to 1, and m1 always
961 * set to 2. If requires to support 200Mhz refclk, we need to
962 * revisit this because n may not 1 anymore.
964 clock
.n
= 1, clock
.m1
= 2;
965 target
*= 5; /* fast clock */
967 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
968 for (clock
.p2
= limit
->p2
.p2_fast
;
969 clock
.p2
>= limit
->p2
.p2_slow
;
970 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
971 unsigned int error_ppm
;
973 clock
.p
= clock
.p1
* clock
.p2
;
975 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
976 clock
.n
) << 22, refclk
* clock
.m1
);
978 if (m2
> INT_MAX
/clock
.m1
)
983 chv_calc_dpll_params(refclk
, &clock
);
985 if (!intel_PLL_is_valid(to_i915(dev
), limit
, &clock
))
988 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
989 best_error_ppm
, &error_ppm
))
993 best_error_ppm
= error_ppm
;
1001 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1002 struct dpll
*best_clock
)
1004 int refclk
= 100000;
1005 const struct intel_limit
*limit
= &intel_limits_bxt
;
1007 return chv_find_best_dpll(limit
, crtc_state
,
1008 target_clock
, refclk
, NULL
, best_clock
);
1011 bool intel_crtc_active(struct intel_crtc
*crtc
)
1013 /* Be paranoid as we can arrive here with only partial
1014 * state retrieved from the hardware during setup.
1016 * We can ditch the adjusted_mode.crtc_clock check as soon
1017 * as Haswell has gained clock readout/fastboot support.
1019 * We can ditch the crtc->primary->fb check as soon as we can
1020 * properly reconstruct framebuffers.
1022 * FIXME: The intel_crtc->active here should be switched to
1023 * crtc->state->active once we have proper CRTC states wired up
1026 return crtc
->active
&& crtc
->base
.primary
->state
->fb
&&
1027 crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1030 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1033 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1035 return crtc
->config
->cpu_transcoder
;
1038 static bool pipe_dsl_stopped(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1040 i915_reg_t reg
= PIPEDSL(pipe
);
1044 if (IS_GEN2(dev_priv
))
1045 line_mask
= DSL_LINEMASK_GEN2
;
1047 line_mask
= DSL_LINEMASK_GEN3
;
1049 line1
= I915_READ(reg
) & line_mask
;
1051 line2
= I915_READ(reg
) & line_mask
;
1053 return line1
== line2
;
1057 * intel_wait_for_pipe_off - wait for pipe to turn off
1058 * @crtc: crtc whose pipe to wait for
1060 * After disabling a pipe, we can't wait for vblank in the usual way,
1061 * spinning on the vblank interrupt status bit, since we won't actually
1062 * see an interrupt when the pipe is disabled.
1064 * On Gen4 and above:
1065 * wait for the pipe register state bit to turn off
1068 * wait for the display line value to settle (it usually
1069 * ends up stopping at the start of the next frame).
1072 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1074 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1075 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1076 enum pipe pipe
= crtc
->pipe
;
1078 if (INTEL_GEN(dev_priv
) >= 4) {
1079 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1081 /* Wait for the Pipe State to go off */
1082 if (intel_wait_for_register(dev_priv
,
1083 reg
, I965_PIPECONF_ACTIVE
, 0,
1085 WARN(1, "pipe_off wait timed out\n");
1087 /* Wait for the display line to settle */
1088 if (wait_for(pipe_dsl_stopped(dev_priv
, pipe
), 100))
1089 WARN(1, "pipe_off wait timed out\n");
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private
*dev_priv
,
1095 enum pipe pipe
, bool state
)
1100 val
= I915_READ(DPLL(pipe
));
1101 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1102 I915_STATE_WARN(cur_state
!= state
,
1103 "PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state
), onoff(cur_state
));
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1113 mutex_lock(&dev_priv
->sb_lock
);
1114 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1115 mutex_unlock(&dev_priv
->sb_lock
);
1117 cur_state
= val
& DSI_PLL_VCO_EN
;
1118 I915_STATE_WARN(cur_state
!= state
,
1119 "DSI PLL state assertion failure (expected %s, current %s)\n",
1120 onoff(state
), onoff(cur_state
));
1123 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1124 enum pipe pipe
, bool state
)
1127 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1130 if (HAS_DDI(dev_priv
)) {
1131 /* DDI does not have a specific FDI_TX register */
1132 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1133 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1135 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1136 cur_state
= !!(val
& FDI_TX_ENABLE
);
1138 I915_STATE_WARN(cur_state
!= state
,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 onoff(state
), onoff(cur_state
));
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1145 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1146 enum pipe pipe
, bool state
)
1151 val
= I915_READ(FDI_RX_CTL(pipe
));
1152 cur_state
= !!(val
& FDI_RX_ENABLE
);
1153 I915_STATE_WARN(cur_state
!= state
,
1154 "FDI RX state assertion failure (expected %s, current %s)\n",
1155 onoff(state
), onoff(cur_state
));
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1165 /* ILK FDI PLL is always enabled */
1166 if (IS_GEN5(dev_priv
))
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv
))
1173 val
= I915_READ(FDI_TX_CTL(pipe
));
1174 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1178 enum pipe pipe
, bool state
)
1183 val
= I915_READ(FDI_RX_CTL(pipe
));
1184 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1185 I915_STATE_WARN(cur_state
!= state
,
1186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187 onoff(state
), onoff(cur_state
));
1190 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1194 enum pipe panel_pipe
= PIPE_A
;
1197 if (WARN_ON(HAS_DDI(dev_priv
)))
1200 if (HAS_PCH_SPLIT(dev_priv
)) {
1203 pp_reg
= PP_CONTROL(0);
1204 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1206 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1207 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1208 panel_pipe
= PIPE_B
;
1209 /* XXX: else fix for eDP */
1210 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1211 /* presumably write lock depends on pipe, not port select */
1212 pp_reg
= PP_CONTROL(pipe
);
1215 pp_reg
= PP_CONTROL(0);
1216 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1217 panel_pipe
= PIPE_B
;
1220 val
= I915_READ(pp_reg
);
1221 if (!(val
& PANEL_POWER_ON
) ||
1222 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1225 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1226 "panel assertion failure, pipe %c regs locked\n",
1230 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1231 enum pipe pipe
, bool state
)
1235 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
1236 cur_state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
1238 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1240 I915_STATE_WARN(cur_state
!= state
,
1241 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1242 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1244 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1245 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1247 void assert_pipe(struct drm_i915_private
*dev_priv
,
1248 enum pipe pipe
, bool state
)
1251 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1253 enum intel_display_power_domain power_domain
;
1255 /* if we need the pipe quirk it must be always on */
1256 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1257 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1260 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1261 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
1262 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1263 cur_state
= !!(val
& PIPECONF_ENABLE
);
1265 intel_display_power_put(dev_priv
, power_domain
);
1270 I915_STATE_WARN(cur_state
!= state
,
1271 "pipe %c assertion failure (expected %s, current %s)\n",
1272 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1275 static void assert_plane(struct drm_i915_private
*dev_priv
,
1276 enum plane plane
, bool state
)
1281 val
= I915_READ(DSPCNTR(plane
));
1282 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1283 I915_STATE_WARN(cur_state
!= state
,
1284 "plane %c assertion failure (expected %s, current %s)\n",
1285 plane_name(plane
), onoff(state
), onoff(cur_state
));
1288 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1289 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1291 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1296 /* Primary planes are fixed to pipes on gen4+ */
1297 if (INTEL_GEN(dev_priv
) >= 4) {
1298 u32 val
= I915_READ(DSPCNTR(pipe
));
1299 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1300 "plane %c assertion failure, should be disabled but not\n",
1305 /* Need to check both planes against the pipe */
1306 for_each_pipe(dev_priv
, i
) {
1307 u32 val
= I915_READ(DSPCNTR(i
));
1308 enum pipe cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1309 DISPPLANE_SEL_PIPE_SHIFT
;
1310 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1311 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1312 plane_name(i
), pipe_name(pipe
));
1316 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1321 if (INTEL_GEN(dev_priv
) >= 9) {
1322 for_each_sprite(dev_priv
, pipe
, sprite
) {
1323 u32 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1324 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1325 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1326 sprite
, pipe_name(pipe
));
1328 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1329 for_each_sprite(dev_priv
, pipe
, sprite
) {
1330 u32 val
= I915_READ(SPCNTR(pipe
, PLANE_SPRITE0
+ sprite
));
1331 I915_STATE_WARN(val
& SP_ENABLE
,
1332 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1335 } else if (INTEL_GEN(dev_priv
) >= 7) {
1336 u32 val
= I915_READ(SPRCTL(pipe
));
1337 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1338 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1339 plane_name(pipe
), pipe_name(pipe
));
1340 } else if (INTEL_GEN(dev_priv
) >= 5) {
1341 u32 val
= I915_READ(DVSCNTR(pipe
));
1342 I915_STATE_WARN(val
& DVS_ENABLE
,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 plane_name(pipe
), pipe_name(pipe
));
1348 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1350 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1351 drm_crtc_vblank_put(crtc
);
1354 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1360 val
= I915_READ(PCH_TRANSCONF(pipe
));
1361 enabled
= !!(val
& TRANS_ENABLE
);
1362 I915_STATE_WARN(enabled
,
1363 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1367 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1368 enum pipe pipe
, u32 port_sel
, u32 val
)
1370 if ((val
& DP_PORT_EN
) == 0)
1373 if (HAS_PCH_CPT(dev_priv
)) {
1374 u32 trans_dp_ctl
= I915_READ(TRANS_DP_CTL(pipe
));
1375 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1377 } else if (IS_CHERRYVIEW(dev_priv
)) {
1378 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1381 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1387 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1388 enum pipe pipe
, u32 val
)
1390 if ((val
& SDVO_ENABLE
) == 0)
1393 if (HAS_PCH_CPT(dev_priv
)) {
1394 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1396 } else if (IS_CHERRYVIEW(dev_priv
)) {
1397 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1400 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1406 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1407 enum pipe pipe
, u32 val
)
1409 if ((val
& LVDS_PORT_EN
) == 0)
1412 if (HAS_PCH_CPT(dev_priv
)) {
1413 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1416 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1422 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1423 enum pipe pipe
, u32 val
)
1425 if ((val
& ADPA_DAC_ENABLE
) == 0)
1427 if (HAS_PCH_CPT(dev_priv
)) {
1428 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1431 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1437 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1438 enum pipe pipe
, i915_reg_t reg
,
1441 u32 val
= I915_READ(reg
);
1442 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1443 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1444 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1446 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& DP_PORT_EN
) == 0
1447 && (val
& DP_PIPEB_SELECT
),
1448 "IBX PCH dp port still using transcoder B\n");
1451 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1452 enum pipe pipe
, i915_reg_t reg
)
1454 u32 val
= I915_READ(reg
);
1455 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1456 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1457 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1459 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& SDVO_ENABLE
) == 0
1460 && (val
& SDVO_PIPE_B_SELECT
),
1461 "IBX PCH hdmi port still using transcoder B\n");
1464 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1469 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1470 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1471 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1473 val
= I915_READ(PCH_ADPA
);
1474 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1475 "PCH VGA enabled on transcoder %c, should be disabled\n",
1478 val
= I915_READ(PCH_LVDS
);
1479 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1480 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1484 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1485 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1488 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1489 const struct intel_crtc_state
*pipe_config
)
1491 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1492 enum pipe pipe
= crtc
->pipe
;
1494 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1495 POSTING_READ(DPLL(pipe
));
1498 if (intel_wait_for_register(dev_priv
,
1503 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1506 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1507 const struct intel_crtc_state
*pipe_config
)
1509 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1510 enum pipe pipe
= crtc
->pipe
;
1512 assert_pipe_disabled(dev_priv
, pipe
);
1514 /* PLL is protected by panel, make sure we can write it */
1515 assert_panel_unlocked(dev_priv
, pipe
);
1517 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1518 _vlv_enable_pll(crtc
, pipe_config
);
1520 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1521 POSTING_READ(DPLL_MD(pipe
));
1525 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1526 const struct intel_crtc_state
*pipe_config
)
1528 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1529 enum pipe pipe
= crtc
->pipe
;
1530 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1533 mutex_lock(&dev_priv
->sb_lock
);
1535 /* Enable back the 10bit clock to display controller */
1536 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1537 tmp
|= DPIO_DCLKP_EN
;
1538 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1540 mutex_unlock(&dev_priv
->sb_lock
);
1543 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1548 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1550 /* Check PLL is locked */
1551 if (intel_wait_for_register(dev_priv
,
1552 DPLL(pipe
), DPLL_LOCK_VLV
, DPLL_LOCK_VLV
,
1554 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1557 static void chv_enable_pll(struct intel_crtc
*crtc
,
1558 const struct intel_crtc_state
*pipe_config
)
1560 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1561 enum pipe pipe
= crtc
->pipe
;
1563 assert_pipe_disabled(dev_priv
, pipe
);
1565 /* PLL is protected by panel, make sure we can write it */
1566 assert_panel_unlocked(dev_priv
, pipe
);
1568 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1569 _chv_enable_pll(crtc
, pipe_config
);
1571 if (pipe
!= PIPE_A
) {
1573 * WaPixelRepeatModeFixForC0:chv
1575 * DPLLCMD is AWOL. Use chicken bits to propagate
1576 * the value from DPLLBMD to either pipe B or C.
1578 I915_WRITE(CBR4_VLV
, pipe
== PIPE_B
? CBR_DPLLBMD_PIPE_B
: CBR_DPLLBMD_PIPE_C
);
1579 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1580 I915_WRITE(CBR4_VLV
, 0);
1581 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1584 * DPLLB VGA mode also seems to cause problems.
1585 * We should always have it disabled.
1587 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1589 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1590 POSTING_READ(DPLL_MD(pipe
));
1594 static int intel_num_dvo_pipes(struct drm_i915_private
*dev_priv
)
1596 struct intel_crtc
*crtc
;
1599 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1600 count
+= crtc
->base
.state
->active
&&
1601 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
);
1607 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1609 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1610 i915_reg_t reg
= DPLL(crtc
->pipe
);
1611 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1613 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1615 /* PLL is protected by panel, make sure we can write it */
1616 if (IS_MOBILE(dev_priv
) && !IS_I830(dev_priv
))
1617 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1619 /* Enable DVO 2x clock on both PLLs if necessary */
1620 if (IS_I830(dev_priv
) && intel_num_dvo_pipes(dev_priv
) > 0) {
1622 * It appears to be important that we don't enable this
1623 * for the current pipe before otherwise configuring the
1624 * PLL. No idea how this should be handled if multiple
1625 * DVO outputs are enabled simultaneosly.
1627 dpll
|= DPLL_DVO_2X_MODE
;
1628 I915_WRITE(DPLL(!crtc
->pipe
),
1629 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1633 * Apparently we need to have VGA mode enabled prior to changing
1634 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1635 * dividers, even though the register value does change.
1639 I915_WRITE(reg
, dpll
);
1641 /* Wait for the clocks to stabilize. */
1645 if (INTEL_GEN(dev_priv
) >= 4) {
1646 I915_WRITE(DPLL_MD(crtc
->pipe
),
1647 crtc
->config
->dpll_hw_state
.dpll_md
);
1649 /* The pixel multiplier can only be updated once the
1650 * DPLL is enabled and the clocks are stable.
1652 * So write it again.
1654 I915_WRITE(reg
, dpll
);
1657 /* We do this three times for luck */
1658 I915_WRITE(reg
, dpll
);
1660 udelay(150); /* wait for warmup */
1661 I915_WRITE(reg
, dpll
);
1663 udelay(150); /* wait for warmup */
1664 I915_WRITE(reg
, dpll
);
1666 udelay(150); /* wait for warmup */
1670 * i9xx_disable_pll - disable a PLL
1671 * @dev_priv: i915 private structure
1672 * @pipe: pipe PLL to disable
1674 * Disable the PLL for @pipe, making sure the pipe is off first.
1676 * Note! This is for pre-ILK only.
1678 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1680 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1681 enum pipe pipe
= crtc
->pipe
;
1683 /* Disable DVO 2x clock on both PLLs if necessary */
1684 if (IS_I830(dev_priv
) &&
1685 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
) &&
1686 !intel_num_dvo_pipes(dev_priv
)) {
1687 I915_WRITE(DPLL(PIPE_B
),
1688 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1689 I915_WRITE(DPLL(PIPE_A
),
1690 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1693 /* Don't disable pipe or pipe PLLs if needed */
1694 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1695 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv
, pipe
);
1701 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1702 POSTING_READ(DPLL(pipe
));
1705 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1709 /* Make sure the pipe isn't still relying on us */
1710 assert_pipe_disabled(dev_priv
, pipe
);
1712 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1713 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1715 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1717 I915_WRITE(DPLL(pipe
), val
);
1718 POSTING_READ(DPLL(pipe
));
1721 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1723 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1726 /* Make sure the pipe isn't still relying on us */
1727 assert_pipe_disabled(dev_priv
, pipe
);
1729 val
= DPLL_SSC_REF_CLK_CHV
|
1730 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1732 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1734 I915_WRITE(DPLL(pipe
), val
);
1735 POSTING_READ(DPLL(pipe
));
1737 mutex_lock(&dev_priv
->sb_lock
);
1739 /* Disable 10bit clock to display controller */
1740 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1741 val
&= ~DPIO_DCLKP_EN
;
1742 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1744 mutex_unlock(&dev_priv
->sb_lock
);
1747 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1748 struct intel_digital_port
*dport
,
1749 unsigned int expected_mask
)
1752 i915_reg_t dpll_reg
;
1754 switch (dport
->port
) {
1756 port_mask
= DPLL_PORTB_READY_MASK
;
1760 port_mask
= DPLL_PORTC_READY_MASK
;
1762 expected_mask
<<= 4;
1765 port_mask
= DPLL_PORTD_READY_MASK
;
1766 dpll_reg
= DPIO_PHY_STATUS
;
1772 if (intel_wait_for_register(dev_priv
,
1773 dpll_reg
, port_mask
, expected_mask
,
1775 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1776 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1779 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1782 struct intel_crtc
*intel_crtc
= intel_get_crtc_for_pipe(dev_priv
,
1785 uint32_t val
, pipeconf_val
;
1787 /* Make sure PCH DPLL is enabled */
1788 assert_shared_dpll_enabled(dev_priv
, intel_crtc
->config
->shared_dpll
);
1790 /* FDI must be feeding us bits for PCH ports */
1791 assert_fdi_tx_enabled(dev_priv
, pipe
);
1792 assert_fdi_rx_enabled(dev_priv
, pipe
);
1794 if (HAS_PCH_CPT(dev_priv
)) {
1795 /* Workaround: Set the timing override bit before enabling the
1796 * pch transcoder. */
1797 reg
= TRANS_CHICKEN2(pipe
);
1798 val
= I915_READ(reg
);
1799 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1800 I915_WRITE(reg
, val
);
1803 reg
= PCH_TRANSCONF(pipe
);
1804 val
= I915_READ(reg
);
1805 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1807 if (HAS_PCH_IBX(dev_priv
)) {
1809 * Make the BPC in transcoder be consistent with
1810 * that in pipeconf reg. For HDMI we must use 8bpc
1811 * here for both 8bpc and 12bpc.
1813 val
&= ~PIPECONF_BPC_MASK
;
1814 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_HDMI
))
1815 val
|= PIPECONF_8BPC
;
1817 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1820 val
&= ~TRANS_INTERLACE_MASK
;
1821 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1822 if (HAS_PCH_IBX(dev_priv
) &&
1823 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
1824 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1826 val
|= TRANS_INTERLACED
;
1828 val
|= TRANS_PROGRESSIVE
;
1830 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1831 if (intel_wait_for_register(dev_priv
,
1832 reg
, TRANS_STATE_ENABLE
, TRANS_STATE_ENABLE
,
1834 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1837 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1838 enum transcoder cpu_transcoder
)
1840 u32 val
, pipeconf_val
;
1842 /* FDI must be feeding us bits for PCH ports */
1843 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1844 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1846 /* Workaround: set timing override bit. */
1847 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1848 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1849 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1852 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1854 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1855 PIPECONF_INTERLACED_ILK
)
1856 val
|= TRANS_INTERLACED
;
1858 val
|= TRANS_PROGRESSIVE
;
1860 I915_WRITE(LPT_TRANSCONF
, val
);
1861 if (intel_wait_for_register(dev_priv
,
1866 DRM_ERROR("Failed to enable PCH transcoder\n");
1869 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1875 /* FDI relies on the transcoder */
1876 assert_fdi_tx_disabled(dev_priv
, pipe
);
1877 assert_fdi_rx_disabled(dev_priv
, pipe
);
1879 /* Ports must be off as well */
1880 assert_pch_ports_disabled(dev_priv
, pipe
);
1882 reg
= PCH_TRANSCONF(pipe
);
1883 val
= I915_READ(reg
);
1884 val
&= ~TRANS_ENABLE
;
1885 I915_WRITE(reg
, val
);
1886 /* wait for PCH transcoder off, transcoder state */
1887 if (intel_wait_for_register(dev_priv
,
1888 reg
, TRANS_STATE_ENABLE
, 0,
1890 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1892 if (HAS_PCH_CPT(dev_priv
)) {
1893 /* Workaround: Clear the timing override chicken bit again. */
1894 reg
= TRANS_CHICKEN2(pipe
);
1895 val
= I915_READ(reg
);
1896 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1897 I915_WRITE(reg
, val
);
1901 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1905 val
= I915_READ(LPT_TRANSCONF
);
1906 val
&= ~TRANS_ENABLE
;
1907 I915_WRITE(LPT_TRANSCONF
, val
);
1908 /* wait for PCH transcoder off, transcoder state */
1909 if (intel_wait_for_register(dev_priv
,
1910 LPT_TRANSCONF
, TRANS_STATE_ENABLE
, 0,
1912 DRM_ERROR("Failed to disable PCH transcoder\n");
1914 /* Workaround: clear timing override bit. */
1915 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1916 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1917 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1920 enum transcoder
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
)
1922 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1924 WARN_ON(!crtc
->config
->has_pch_encoder
);
1926 if (HAS_PCH_LPT(dev_priv
))
1927 return TRANSCODER_A
;
1929 return (enum transcoder
) crtc
->pipe
;
1933 * intel_enable_pipe - enable a pipe, asserting requirements
1934 * @crtc: crtc responsible for the pipe
1936 * Enable @crtc's pipe, making sure that various hardware specific requirements
1937 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1939 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1941 struct drm_device
*dev
= crtc
->base
.dev
;
1942 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1943 enum pipe pipe
= crtc
->pipe
;
1944 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1948 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1950 assert_planes_disabled(dev_priv
, pipe
);
1951 assert_cursor_disabled(dev_priv
, pipe
);
1952 assert_sprites_disabled(dev_priv
, pipe
);
1955 * A pipe without a PLL won't actually be able to drive bits from
1956 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1959 if (HAS_GMCH_DISPLAY(dev_priv
)) {
1960 if (intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DSI
))
1961 assert_dsi_pll_enabled(dev_priv
);
1963 assert_pll_enabled(dev_priv
, pipe
);
1965 if (crtc
->config
->has_pch_encoder
) {
1966 /* if driving the PCH, we need FDI enabled */
1967 assert_fdi_rx_pll_enabled(dev_priv
,
1968 (enum pipe
) intel_crtc_pch_transcoder(crtc
));
1969 assert_fdi_tx_pll_enabled(dev_priv
,
1970 (enum pipe
) cpu_transcoder
);
1972 /* FIXME: assert CPU port conditions for SNB+ */
1975 reg
= PIPECONF(cpu_transcoder
);
1976 val
= I915_READ(reg
);
1977 if (val
& PIPECONF_ENABLE
) {
1978 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1979 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
1983 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1987 * Until the pipe starts DSL will read as 0, which would cause
1988 * an apparent vblank timestamp jump, which messes up also the
1989 * frame count when it's derived from the timestamps. So let's
1990 * wait for the pipe to start properly before we call
1991 * drm_crtc_vblank_on()
1993 if (dev
->max_vblank_count
== 0 &&
1994 wait_for(intel_get_crtc_scanline(crtc
) != crtc
->scanline_offset
, 50))
1995 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe
));
1999 * intel_disable_pipe - disable a pipe, asserting requirements
2000 * @crtc: crtc whose pipes is to be disabled
2002 * Disable the pipe of @crtc, making sure that various hardware
2003 * specific requirements are met, if applicable, e.g. plane
2004 * disabled, panel fitter off, etc.
2006 * Will wait until the pipe has shut down before returning.
2008 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2010 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2011 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2012 enum pipe pipe
= crtc
->pipe
;
2016 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
2019 * Make sure planes won't keep trying to pump pixels to us,
2020 * or we might hang the display.
2022 assert_planes_disabled(dev_priv
, pipe
);
2023 assert_cursor_disabled(dev_priv
, pipe
);
2024 assert_sprites_disabled(dev_priv
, pipe
);
2026 reg
= PIPECONF(cpu_transcoder
);
2027 val
= I915_READ(reg
);
2028 if ((val
& PIPECONF_ENABLE
) == 0)
2032 * Double wide has implications for planes
2033 * so best keep it disabled when not needed.
2035 if (crtc
->config
->double_wide
)
2036 val
&= ~PIPECONF_DOUBLE_WIDE
;
2038 /* Don't disable pipe or pipe PLLs if needed */
2039 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2040 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2041 val
&= ~PIPECONF_ENABLE
;
2043 I915_WRITE(reg
, val
);
2044 if ((val
& PIPECONF_ENABLE
) == 0)
2045 intel_wait_for_pipe_off(crtc
);
2048 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
2050 return IS_GEN2(dev_priv
) ? 2048 : 4096;
2053 static unsigned int intel_tile_width_bytes(const struct drm_i915_private
*dev_priv
,
2054 uint64_t fb_modifier
, unsigned int cpp
)
2056 switch (fb_modifier
) {
2057 case DRM_FORMAT_MOD_NONE
:
2059 case I915_FORMAT_MOD_X_TILED
:
2060 if (IS_GEN2(dev_priv
))
2064 case I915_FORMAT_MOD_Y_TILED
:
2065 if (IS_GEN2(dev_priv
) || HAS_128_BYTE_Y_TILING(dev_priv
))
2069 case I915_FORMAT_MOD_Yf_TILED
:
2085 MISSING_CASE(fb_modifier
);
2090 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
2091 uint64_t fb_modifier
, unsigned int cpp
)
2093 if (fb_modifier
== DRM_FORMAT_MOD_NONE
)
2096 return intel_tile_size(dev_priv
) /
2097 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2100 /* Return the tile dimensions in pixel units */
2101 static void intel_tile_dims(const struct drm_i915_private
*dev_priv
,
2102 unsigned int *tile_width
,
2103 unsigned int *tile_height
,
2104 uint64_t fb_modifier
,
2107 unsigned int tile_width_bytes
=
2108 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2110 *tile_width
= tile_width_bytes
/ cpp
;
2111 *tile_height
= intel_tile_size(dev_priv
) / tile_width_bytes
;
2115 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2116 uint32_t pixel_format
, uint64_t fb_modifier
)
2118 unsigned int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2119 unsigned int tile_height
= intel_tile_height(to_i915(dev
), fb_modifier
, cpp
);
2121 return ALIGN(height
, tile_height
);
2124 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
2126 unsigned int size
= 0;
2129 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
2130 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2136 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2137 const struct drm_framebuffer
*fb
,
2138 unsigned int rotation
)
2140 view
->type
= I915_GGTT_VIEW_NORMAL
;
2141 if (drm_rotation_90_or_270(rotation
)) {
2142 view
->type
= I915_GGTT_VIEW_ROTATED
;
2143 view
->rotated
= to_intel_framebuffer(fb
)->rot_info
;
2147 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2149 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2151 else if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
) ||
2152 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2154 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2160 static unsigned int intel_surf_alignment(const struct drm_i915_private
*dev_priv
,
2161 uint64_t fb_modifier
)
2163 switch (fb_modifier
) {
2164 case DRM_FORMAT_MOD_NONE
:
2165 return intel_linear_alignment(dev_priv
);
2166 case I915_FORMAT_MOD_X_TILED
:
2167 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2170 case I915_FORMAT_MOD_Y_TILED
:
2171 case I915_FORMAT_MOD_Yf_TILED
:
2172 return 1 * 1024 * 1024;
2174 MISSING_CASE(fb_modifier
);
2180 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
)
2182 struct drm_device
*dev
= fb
->dev
;
2183 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2184 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2185 struct i915_ggtt_view view
;
2186 struct i915_vma
*vma
;
2189 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2191 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
);
2193 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2195 /* Note that the w/a also requires 64 PTE of padding following the
2196 * bo. We currently fill all unused PTE with the shadow page and so
2197 * we should always have valid PTE following the scanout preventing
2200 if (intel_scanout_needs_vtd_wa(dev_priv
) && alignment
< 256 * 1024)
2201 alignment
= 256 * 1024;
2204 * Global gtt pte registers are special registers which actually forward
2205 * writes to a chunk of system memory. Which means that there is no risk
2206 * that the register values disappear as soon as we call
2207 * intel_runtime_pm_put(), so it is correct to wrap only the
2208 * pin/unpin/fence and not more.
2210 intel_runtime_pm_get(dev_priv
);
2212 vma
= i915_gem_object_pin_to_display_plane(obj
, alignment
, &view
);
2216 if (i915_vma_is_map_and_fenceable(vma
)) {
2217 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2218 * fence, whereas 965+ only requires a fence if using
2219 * framebuffer compression. For simplicity, we always, when
2220 * possible, install a fence as the cost is not that onerous.
2222 * If we fail to fence the tiled scanout, then either the
2223 * modeset will reject the change (which is highly unlikely as
2224 * the affected systems, all but one, do not have unmappable
2225 * space) or we will not be able to enable full powersaving
2226 * techniques (also likely not to apply due to various limits
2227 * FBC and the like impose on the size of the buffer, which
2228 * presumably we violated anyway with this unmappable buffer).
2229 * Anyway, it is presumably better to stumble onwards with
2230 * something and try to run the system in a "less than optimal"
2231 * mode that matches the user configuration.
2233 if (i915_vma_get_fence(vma
) == 0)
2234 i915_vma_pin_fence(vma
);
2239 intel_runtime_pm_put(dev_priv
);
2243 void intel_unpin_fb_vma(struct i915_vma
*vma
)
2245 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
2247 i915_vma_unpin_fence(vma
);
2248 i915_gem_object_unpin_from_display_plane(vma
);
2252 static int intel_fb_pitch(const struct drm_framebuffer
*fb
, int plane
,
2253 unsigned int rotation
)
2255 if (drm_rotation_90_or_270(rotation
))
2256 return to_intel_framebuffer(fb
)->rotated
[plane
].pitch
;
2258 return fb
->pitches
[plane
];
2262 * Convert the x/y offsets into a linear offset.
2263 * Only valid with 0/180 degree rotation, which is fine since linear
2264 * offset is only used with linear buffers on pre-hsw and tiled buffers
2265 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2267 u32
intel_fb_xy_to_linear(int x
, int y
,
2268 const struct intel_plane_state
*state
,
2271 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2272 unsigned int cpp
= fb
->format
->cpp
[plane
];
2273 unsigned int pitch
= fb
->pitches
[plane
];
2275 return y
* pitch
+ x
* cpp
;
2279 * Add the x/y offsets derived from fb->offsets[] to the user
2280 * specified plane src x/y offsets. The resulting x/y offsets
2281 * specify the start of scanout from the beginning of the gtt mapping.
2283 void intel_add_fb_offsets(int *x
, int *y
,
2284 const struct intel_plane_state
*state
,
2288 const struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(state
->base
.fb
);
2289 unsigned int rotation
= state
->base
.rotation
;
2291 if (drm_rotation_90_or_270(rotation
)) {
2292 *x
+= intel_fb
->rotated
[plane
].x
;
2293 *y
+= intel_fb
->rotated
[plane
].y
;
2295 *x
+= intel_fb
->normal
[plane
].x
;
2296 *y
+= intel_fb
->normal
[plane
].y
;
2301 * Input tile dimensions and pitch must already be
2302 * rotated to match x and y, and in pixel units.
2304 static u32
_intel_adjust_tile_offset(int *x
, int *y
,
2305 unsigned int tile_width
,
2306 unsigned int tile_height
,
2307 unsigned int tile_size
,
2308 unsigned int pitch_tiles
,
2312 unsigned int pitch_pixels
= pitch_tiles
* tile_width
;
2315 WARN_ON(old_offset
& (tile_size
- 1));
2316 WARN_ON(new_offset
& (tile_size
- 1));
2317 WARN_ON(new_offset
> old_offset
);
2319 tiles
= (old_offset
- new_offset
) / tile_size
;
2321 *y
+= tiles
/ pitch_tiles
* tile_height
;
2322 *x
+= tiles
% pitch_tiles
* tile_width
;
2324 /* minimize x in case it got needlessly big */
2325 *y
+= *x
/ pitch_pixels
* tile_height
;
2332 * Adjust the tile offset by moving the difference into
2335 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2336 const struct intel_plane_state
*state
, int plane
,
2337 u32 old_offset
, u32 new_offset
)
2339 const struct drm_i915_private
*dev_priv
= to_i915(state
->base
.plane
->dev
);
2340 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2341 unsigned int cpp
= fb
->format
->cpp
[plane
];
2342 unsigned int rotation
= state
->base
.rotation
;
2343 unsigned int pitch
= intel_fb_pitch(fb
, plane
, rotation
);
2345 WARN_ON(new_offset
> old_offset
);
2347 if (fb
->modifier
!= DRM_FORMAT_MOD_NONE
) {
2348 unsigned int tile_size
, tile_width
, tile_height
;
2349 unsigned int pitch_tiles
;
2351 tile_size
= intel_tile_size(dev_priv
);
2352 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2355 if (drm_rotation_90_or_270(rotation
)) {
2356 pitch_tiles
= pitch
/ tile_height
;
2357 swap(tile_width
, tile_height
);
2359 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2362 _intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2363 tile_size
, pitch_tiles
,
2364 old_offset
, new_offset
);
2366 old_offset
+= *y
* pitch
+ *x
* cpp
;
2368 *y
= (old_offset
- new_offset
) / pitch
;
2369 *x
= ((old_offset
- new_offset
) - *y
* pitch
) / cpp
;
2376 * Computes the linear offset to the base tile and adjusts
2377 * x, y. bytes per pixel is assumed to be a power-of-two.
2379 * In the 90/270 rotated case, x and y are assumed
2380 * to be already rotated to match the rotated GTT view, and
2381 * pitch is the tile_height aligned framebuffer height.
2383 * This function is used when computing the derived information
2384 * under intel_framebuffer, so using any of that information
2385 * here is not allowed. Anything under drm_framebuffer can be
2386 * used. This is why the user has to pass in the pitch since it
2387 * is specified in the rotated orientation.
2389 static u32
_intel_compute_tile_offset(const struct drm_i915_private
*dev_priv
,
2391 const struct drm_framebuffer
*fb
, int plane
,
2393 unsigned int rotation
,
2396 uint64_t fb_modifier
= fb
->modifier
;
2397 unsigned int cpp
= fb
->format
->cpp
[plane
];
2398 u32 offset
, offset_aligned
;
2403 if (fb_modifier
!= DRM_FORMAT_MOD_NONE
) {
2404 unsigned int tile_size
, tile_width
, tile_height
;
2405 unsigned int tile_rows
, tiles
, pitch_tiles
;
2407 tile_size
= intel_tile_size(dev_priv
);
2408 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2411 if (drm_rotation_90_or_270(rotation
)) {
2412 pitch_tiles
= pitch
/ tile_height
;
2413 swap(tile_width
, tile_height
);
2415 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2418 tile_rows
= *y
/ tile_height
;
2421 tiles
= *x
/ tile_width
;
2424 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2425 offset_aligned
= offset
& ~alignment
;
2427 _intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2428 tile_size
, pitch_tiles
,
2429 offset
, offset_aligned
);
2431 offset
= *y
* pitch
+ *x
* cpp
;
2432 offset_aligned
= offset
& ~alignment
;
2434 *y
= (offset
& alignment
) / pitch
;
2435 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2438 return offset_aligned
;
2441 u32
intel_compute_tile_offset(int *x
, int *y
,
2442 const struct intel_plane_state
*state
,
2445 const struct drm_i915_private
*dev_priv
= to_i915(state
->base
.plane
->dev
);
2446 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2447 unsigned int rotation
= state
->base
.rotation
;
2448 int pitch
= intel_fb_pitch(fb
, plane
, rotation
);
2451 /* AUX_DIST needs only 4K alignment */
2452 if (fb
->format
->format
== DRM_FORMAT_NV12
&& plane
== 1)
2455 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
);
2457 return _intel_compute_tile_offset(dev_priv
, x
, y
, fb
, plane
, pitch
,
2458 rotation
, alignment
);
2461 /* Convert the fb->offset[] linear offset into x/y offsets */
2462 static void intel_fb_offset_to_xy(int *x
, int *y
,
2463 const struct drm_framebuffer
*fb
, int plane
)
2465 unsigned int cpp
= fb
->format
->cpp
[plane
];
2466 unsigned int pitch
= fb
->pitches
[plane
];
2467 u32 linear_offset
= fb
->offsets
[plane
];
2469 *y
= linear_offset
/ pitch
;
2470 *x
= linear_offset
% pitch
/ cpp
;
2473 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier
)
2475 switch (fb_modifier
) {
2476 case I915_FORMAT_MOD_X_TILED
:
2477 return I915_TILING_X
;
2478 case I915_FORMAT_MOD_Y_TILED
:
2479 return I915_TILING_Y
;
2481 return I915_TILING_NONE
;
2486 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2487 struct drm_framebuffer
*fb
)
2489 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
2490 struct intel_rotation_info
*rot_info
= &intel_fb
->rot_info
;
2491 u32 gtt_offset_rotated
= 0;
2492 unsigned int max_size
= 0;
2493 int i
, num_planes
= fb
->format
->num_planes
;
2494 unsigned int tile_size
= intel_tile_size(dev_priv
);
2496 for (i
= 0; i
< num_planes
; i
++) {
2497 unsigned int width
, height
;
2498 unsigned int cpp
, size
;
2502 cpp
= fb
->format
->cpp
[i
];
2503 width
= drm_framebuffer_plane_width(fb
->width
, fb
, i
);
2504 height
= drm_framebuffer_plane_height(fb
->height
, fb
, i
);
2506 intel_fb_offset_to_xy(&x
, &y
, fb
, i
);
2509 * The fence (if used) is aligned to the start of the object
2510 * so having the framebuffer wrap around across the edge of the
2511 * fenced region doesn't really work. We have no API to configure
2512 * the fence start offset within the object (nor could we probably
2513 * on gen2/3). So it's just easier if we just require that the
2514 * fb layout agrees with the fence layout. We already check that the
2515 * fb stride matches the fence stride elsewhere.
2517 if (i915_gem_object_is_tiled(intel_fb
->obj
) &&
2518 (x
+ width
) * cpp
> fb
->pitches
[i
]) {
2519 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2525 * First pixel of the framebuffer from
2526 * the start of the normal gtt mapping.
2528 intel_fb
->normal
[i
].x
= x
;
2529 intel_fb
->normal
[i
].y
= y
;
2531 offset
= _intel_compute_tile_offset(dev_priv
, &x
, &y
,
2532 fb
, 0, fb
->pitches
[i
],
2533 DRM_ROTATE_0
, tile_size
);
2534 offset
/= tile_size
;
2536 if (fb
->modifier
!= DRM_FORMAT_MOD_NONE
) {
2537 unsigned int tile_width
, tile_height
;
2538 unsigned int pitch_tiles
;
2541 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2544 rot_info
->plane
[i
].offset
= offset
;
2545 rot_info
->plane
[i
].stride
= DIV_ROUND_UP(fb
->pitches
[i
], tile_width
* cpp
);
2546 rot_info
->plane
[i
].width
= DIV_ROUND_UP(x
+ width
, tile_width
);
2547 rot_info
->plane
[i
].height
= DIV_ROUND_UP(y
+ height
, tile_height
);
2549 intel_fb
->rotated
[i
].pitch
=
2550 rot_info
->plane
[i
].height
* tile_height
;
2552 /* how many tiles does this plane need */
2553 size
= rot_info
->plane
[i
].stride
* rot_info
->plane
[i
].height
;
2555 * If the plane isn't horizontally tile aligned,
2556 * we need one more tile.
2561 /* rotate the x/y offsets to match the GTT view */
2567 rot_info
->plane
[i
].width
* tile_width
,
2568 rot_info
->plane
[i
].height
* tile_height
,
2573 /* rotate the tile dimensions to match the GTT view */
2574 pitch_tiles
= intel_fb
->rotated
[i
].pitch
/ tile_height
;
2575 swap(tile_width
, tile_height
);
2578 * We only keep the x/y offsets, so push all of the
2579 * gtt offset into the x/y offsets.
2581 _intel_adjust_tile_offset(&x
, &y
,
2582 tile_width
, tile_height
,
2583 tile_size
, pitch_tiles
,
2584 gtt_offset_rotated
* tile_size
, 0);
2586 gtt_offset_rotated
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2589 * First pixel of the framebuffer from
2590 * the start of the rotated gtt mapping.
2592 intel_fb
->rotated
[i
].x
= x
;
2593 intel_fb
->rotated
[i
].y
= y
;
2595 size
= DIV_ROUND_UP((y
+ height
) * fb
->pitches
[i
] +
2596 x
* cpp
, tile_size
);
2599 /* how many tiles in total needed in the bo */
2600 max_size
= max(max_size
, offset
+ size
);
2603 if (max_size
* tile_size
> to_intel_framebuffer(fb
)->obj
->base
.size
) {
2604 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2605 max_size
* tile_size
, to_intel_framebuffer(fb
)->obj
->base
.size
);
2612 static int i9xx_format_to_fourcc(int format
)
2615 case DISPPLANE_8BPP
:
2616 return DRM_FORMAT_C8
;
2617 case DISPPLANE_BGRX555
:
2618 return DRM_FORMAT_XRGB1555
;
2619 case DISPPLANE_BGRX565
:
2620 return DRM_FORMAT_RGB565
;
2622 case DISPPLANE_BGRX888
:
2623 return DRM_FORMAT_XRGB8888
;
2624 case DISPPLANE_RGBX888
:
2625 return DRM_FORMAT_XBGR8888
;
2626 case DISPPLANE_BGRX101010
:
2627 return DRM_FORMAT_XRGB2101010
;
2628 case DISPPLANE_RGBX101010
:
2629 return DRM_FORMAT_XBGR2101010
;
2633 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2636 case PLANE_CTL_FORMAT_RGB_565
:
2637 return DRM_FORMAT_RGB565
;
2639 case PLANE_CTL_FORMAT_XRGB_8888
:
2642 return DRM_FORMAT_ABGR8888
;
2644 return DRM_FORMAT_XBGR8888
;
2647 return DRM_FORMAT_ARGB8888
;
2649 return DRM_FORMAT_XRGB8888
;
2651 case PLANE_CTL_FORMAT_XRGB_2101010
:
2653 return DRM_FORMAT_XBGR2101010
;
2655 return DRM_FORMAT_XRGB2101010
;
2660 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2661 struct intel_initial_plane_config
*plane_config
)
2663 struct drm_device
*dev
= crtc
->base
.dev
;
2664 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2665 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2666 struct drm_i915_gem_object
*obj
= NULL
;
2667 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2668 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2669 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2670 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2673 size_aligned
-= base_aligned
;
2675 if (plane_config
->size
== 0)
2678 /* If the FB is too big, just don't use it since fbdev is not very
2679 * important and we should probably use that space with FBC or other
2681 if (size_aligned
* 2 > ggtt
->stolen_usable_size
)
2684 mutex_lock(&dev
->struct_mutex
);
2686 obj
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
2691 mutex_unlock(&dev
->struct_mutex
);
2695 if (plane_config
->tiling
== I915_TILING_X
)
2696 obj
->tiling_and_stride
= fb
->pitches
[0] | I915_TILING_X
;
2698 mode_cmd
.pixel_format
= fb
->format
->format
;
2699 mode_cmd
.width
= fb
->width
;
2700 mode_cmd
.height
= fb
->height
;
2701 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2702 mode_cmd
.modifier
[0] = fb
->modifier
;
2703 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2705 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2707 DRM_DEBUG_KMS("intel fb init failed\n");
2711 mutex_unlock(&dev
->struct_mutex
);
2713 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2717 i915_gem_object_put(obj
);
2718 mutex_unlock(&dev
->struct_mutex
);
2722 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2724 update_state_fb(struct drm_plane
*plane
)
2726 if (plane
->fb
== plane
->state
->fb
)
2729 if (plane
->state
->fb
)
2730 drm_framebuffer_unreference(plane
->state
->fb
);
2731 plane
->state
->fb
= plane
->fb
;
2732 if (plane
->state
->fb
)
2733 drm_framebuffer_reference(plane
->state
->fb
);
2737 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2738 struct intel_initial_plane_config
*plane_config
)
2740 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2741 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2743 struct drm_i915_gem_object
*obj
;
2744 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2745 struct drm_plane_state
*plane_state
= primary
->state
;
2746 struct drm_crtc_state
*crtc_state
= intel_crtc
->base
.state
;
2747 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2748 struct intel_plane_state
*intel_state
=
2749 to_intel_plane_state(plane_state
);
2750 struct drm_framebuffer
*fb
;
2752 if (!plane_config
->fb
)
2755 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2756 fb
= &plane_config
->fb
->base
;
2760 kfree(plane_config
->fb
);
2763 * Failed to alloc the obj, check to see if we should share
2764 * an fb with another CRTC instead
2766 for_each_crtc(dev
, c
) {
2767 struct intel_plane_state
*state
;
2769 if (c
== &intel_crtc
->base
)
2772 if (!to_intel_crtc(c
)->active
)
2775 state
= to_intel_plane_state(c
->primary
->state
);
2779 if (intel_plane_ggtt_offset(state
) == plane_config
->base
) {
2780 fb
= c
->primary
->fb
;
2781 drm_framebuffer_reference(fb
);
2787 * We've failed to reconstruct the BIOS FB. Current display state
2788 * indicates that the primary plane is visible, but has a NULL FB,
2789 * which will lead to problems later if we don't fix it up. The
2790 * simplest solution is to just disable the primary plane now and
2791 * pretend the BIOS never had it enabled.
2793 plane_state
->visible
= false;
2794 crtc_state
->plane_mask
&= ~(1 << drm_plane_index(primary
));
2795 intel_pre_disable_primary_noatomic(&intel_crtc
->base
);
2796 intel_plane
->disable_plane(primary
, &intel_crtc
->base
);
2801 mutex_lock(&dev
->struct_mutex
);
2803 intel_pin_and_fence_fb_obj(fb
, primary
->state
->rotation
);
2804 mutex_unlock(&dev
->struct_mutex
);
2805 if (IS_ERR(intel_state
->vma
)) {
2806 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2807 intel_crtc
->pipe
, PTR_ERR(intel_state
->vma
));
2809 intel_state
->vma
= NULL
;
2810 drm_framebuffer_unreference(fb
);
2814 plane_state
->src_x
= 0;
2815 plane_state
->src_y
= 0;
2816 plane_state
->src_w
= fb
->width
<< 16;
2817 plane_state
->src_h
= fb
->height
<< 16;
2819 plane_state
->crtc_x
= 0;
2820 plane_state
->crtc_y
= 0;
2821 plane_state
->crtc_w
= fb
->width
;
2822 plane_state
->crtc_h
= fb
->height
;
2824 intel_state
->base
.src
= drm_plane_state_src(plane_state
);
2825 intel_state
->base
.dst
= drm_plane_state_dest(plane_state
);
2827 obj
= intel_fb_obj(fb
);
2828 if (i915_gem_object_is_tiled(obj
))
2829 dev_priv
->preserve_bios_swizzle
= true;
2831 drm_framebuffer_reference(fb
);
2832 primary
->fb
= primary
->state
->fb
= fb
;
2833 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2834 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2835 atomic_or(to_intel_plane(primary
)->frontbuffer_bit
,
2836 &obj
->frontbuffer_bits
);
2839 static int skl_max_plane_width(const struct drm_framebuffer
*fb
, int plane
,
2840 unsigned int rotation
)
2842 int cpp
= fb
->format
->cpp
[plane
];
2844 switch (fb
->modifier
) {
2845 case DRM_FORMAT_MOD_NONE
:
2846 case I915_FORMAT_MOD_X_TILED
:
2859 case I915_FORMAT_MOD_Y_TILED
:
2860 case I915_FORMAT_MOD_Yf_TILED
:
2875 MISSING_CASE(fb
->modifier
);
2881 static int skl_check_main_surface(struct intel_plane_state
*plane_state
)
2883 const struct drm_i915_private
*dev_priv
= to_i915(plane_state
->base
.plane
->dev
);
2884 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2885 unsigned int rotation
= plane_state
->base
.rotation
;
2886 int x
= plane_state
->base
.src
.x1
>> 16;
2887 int y
= plane_state
->base
.src
.y1
>> 16;
2888 int w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
2889 int h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
2890 int max_width
= skl_max_plane_width(fb
, 0, rotation
);
2891 int max_height
= 4096;
2892 u32 alignment
, offset
, aux_offset
= plane_state
->aux
.offset
;
2894 if (w
> max_width
|| h
> max_height
) {
2895 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2896 w
, h
, max_width
, max_height
);
2900 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
2901 offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
2903 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
);
2906 * AUX surface offset is specified as the distance from the
2907 * main surface offset, and it must be non-negative. Make
2908 * sure that is what we will get.
2910 if (offset
> aux_offset
)
2911 offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 0,
2912 offset
, aux_offset
& ~(alignment
- 1));
2915 * When using an X-tiled surface, the plane blows up
2916 * if the x offset + width exceed the stride.
2918 * TODO: linear and Y-tiled seem fine, Yf untested,
2920 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
) {
2921 int cpp
= fb
->format
->cpp
[0];
2923 while ((x
+ w
) * cpp
> fb
->pitches
[0]) {
2925 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2929 offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 0,
2930 offset
, offset
- alignment
);
2934 plane_state
->main
.offset
= offset
;
2935 plane_state
->main
.x
= x
;
2936 plane_state
->main
.y
= y
;
2941 static int skl_check_nv12_aux_surface(struct intel_plane_state
*plane_state
)
2943 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2944 unsigned int rotation
= plane_state
->base
.rotation
;
2945 int max_width
= skl_max_plane_width(fb
, 1, rotation
);
2946 int max_height
= 4096;
2947 int x
= plane_state
->base
.src
.x1
>> 17;
2948 int y
= plane_state
->base
.src
.y1
>> 17;
2949 int w
= drm_rect_width(&plane_state
->base
.src
) >> 17;
2950 int h
= drm_rect_height(&plane_state
->base
.src
) >> 17;
2953 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
2954 offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 1);
2956 /* FIXME not quite sure how/if these apply to the chroma plane */
2957 if (w
> max_width
|| h
> max_height
) {
2958 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2959 w
, h
, max_width
, max_height
);
2963 plane_state
->aux
.offset
= offset
;
2964 plane_state
->aux
.x
= x
;
2965 plane_state
->aux
.y
= y
;
2970 int skl_check_plane_surface(struct intel_plane_state
*plane_state
)
2972 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2973 unsigned int rotation
= plane_state
->base
.rotation
;
2976 if (!plane_state
->base
.visible
)
2979 /* Rotate src coordinates to match rotated GTT view */
2980 if (drm_rotation_90_or_270(rotation
))
2981 drm_rect_rotate(&plane_state
->base
.src
,
2982 fb
->width
<< 16, fb
->height
<< 16,
2986 * Handle the AUX surface first since
2987 * the main surface setup depends on it.
2989 if (fb
->format
->format
== DRM_FORMAT_NV12
) {
2990 ret
= skl_check_nv12_aux_surface(plane_state
);
2994 plane_state
->aux
.offset
= ~0xfff;
2995 plane_state
->aux
.x
= 0;
2996 plane_state
->aux
.y
= 0;
2999 ret
= skl_check_main_surface(plane_state
);
3006 static void i9xx_update_primary_plane(struct drm_plane
*primary
,
3007 const struct intel_crtc_state
*crtc_state
,
3008 const struct intel_plane_state
*plane_state
)
3010 struct drm_i915_private
*dev_priv
= to_i915(primary
->dev
);
3011 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3012 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3013 int plane
= intel_crtc
->plane
;
3016 i915_reg_t reg
= DSPCNTR(plane
);
3017 unsigned int rotation
= plane_state
->base
.rotation
;
3018 int x
= plane_state
->base
.src
.x1
>> 16;
3019 int y
= plane_state
->base
.src
.y1
>> 16;
3021 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3023 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3025 if (INTEL_GEN(dev_priv
) < 4) {
3026 if (intel_crtc
->pipe
== PIPE_B
)
3027 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3029 /* pipesrc and dspsize control the size that is scaled from,
3030 * which should always be the user's requested size.
3032 I915_WRITE(DSPSIZE(plane
),
3033 ((crtc_state
->pipe_src_h
- 1) << 16) |
3034 (crtc_state
->pipe_src_w
- 1));
3035 I915_WRITE(DSPPOS(plane
), 0);
3036 } else if (IS_CHERRYVIEW(dev_priv
) && plane
== PLANE_B
) {
3037 I915_WRITE(PRIMSIZE(plane
),
3038 ((crtc_state
->pipe_src_h
- 1) << 16) |
3039 (crtc_state
->pipe_src_w
- 1));
3040 I915_WRITE(PRIMPOS(plane
), 0);
3041 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
3044 switch (fb
->format
->format
) {
3046 dspcntr
|= DISPPLANE_8BPP
;
3048 case DRM_FORMAT_XRGB1555
:
3049 dspcntr
|= DISPPLANE_BGRX555
;
3051 case DRM_FORMAT_RGB565
:
3052 dspcntr
|= DISPPLANE_BGRX565
;
3054 case DRM_FORMAT_XRGB8888
:
3055 dspcntr
|= DISPPLANE_BGRX888
;
3057 case DRM_FORMAT_XBGR8888
:
3058 dspcntr
|= DISPPLANE_RGBX888
;
3060 case DRM_FORMAT_XRGB2101010
:
3061 dspcntr
|= DISPPLANE_BGRX101010
;
3063 case DRM_FORMAT_XBGR2101010
:
3064 dspcntr
|= DISPPLANE_RGBX101010
;
3070 if (INTEL_GEN(dev_priv
) >= 4 &&
3071 fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3072 dspcntr
|= DISPPLANE_TILED
;
3074 if (rotation
& DRM_ROTATE_180
)
3075 dspcntr
|= DISPPLANE_ROTATE_180
;
3077 if (rotation
& DRM_REFLECT_X
)
3078 dspcntr
|= DISPPLANE_MIRROR
;
3080 if (IS_G4X(dev_priv
))
3081 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
3083 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
3085 if (INTEL_GEN(dev_priv
) >= 4)
3086 intel_crtc
->dspaddr_offset
=
3087 intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
3089 if (rotation
& DRM_ROTATE_180
) {
3090 x
+= crtc_state
->pipe_src_w
- 1;
3091 y
+= crtc_state
->pipe_src_h
- 1;
3092 } else if (rotation
& DRM_REFLECT_X
) {
3093 x
+= crtc_state
->pipe_src_w
- 1;
3096 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
3098 if (INTEL_GEN(dev_priv
) < 4)
3099 intel_crtc
->dspaddr_offset
= linear_offset
;
3101 intel_crtc
->adjusted_x
= x
;
3102 intel_crtc
->adjusted_y
= y
;
3104 I915_WRITE(reg
, dspcntr
);
3106 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
3107 if (INTEL_GEN(dev_priv
) >= 4) {
3108 I915_WRITE(DSPSURF(plane
),
3109 intel_plane_ggtt_offset(plane_state
) +
3110 intel_crtc
->dspaddr_offset
);
3111 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
3112 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
3114 I915_WRITE(DSPADDR(plane
),
3115 intel_plane_ggtt_offset(plane_state
) +
3116 intel_crtc
->dspaddr_offset
);
3121 static void i9xx_disable_primary_plane(struct drm_plane
*primary
,
3122 struct drm_crtc
*crtc
)
3124 struct drm_device
*dev
= crtc
->dev
;
3125 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3126 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3127 int plane
= intel_crtc
->plane
;
3129 I915_WRITE(DSPCNTR(plane
), 0);
3130 if (INTEL_INFO(dev_priv
)->gen
>= 4)
3131 I915_WRITE(DSPSURF(plane
), 0);
3133 I915_WRITE(DSPADDR(plane
), 0);
3134 POSTING_READ(DSPCNTR(plane
));
3137 static void ironlake_update_primary_plane(struct drm_plane
*primary
,
3138 const struct intel_crtc_state
*crtc_state
,
3139 const struct intel_plane_state
*plane_state
)
3141 struct drm_device
*dev
= primary
->dev
;
3142 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3143 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3144 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3145 int plane
= intel_crtc
->plane
;
3148 i915_reg_t reg
= DSPCNTR(plane
);
3149 unsigned int rotation
= plane_state
->base
.rotation
;
3150 int x
= plane_state
->base
.src
.x1
>> 16;
3151 int y
= plane_state
->base
.src
.y1
>> 16;
3153 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3154 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3156 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
3157 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
3159 switch (fb
->format
->format
) {
3161 dspcntr
|= DISPPLANE_8BPP
;
3163 case DRM_FORMAT_RGB565
:
3164 dspcntr
|= DISPPLANE_BGRX565
;
3166 case DRM_FORMAT_XRGB8888
:
3167 dspcntr
|= DISPPLANE_BGRX888
;
3169 case DRM_FORMAT_XBGR8888
:
3170 dspcntr
|= DISPPLANE_RGBX888
;
3172 case DRM_FORMAT_XRGB2101010
:
3173 dspcntr
|= DISPPLANE_BGRX101010
;
3175 case DRM_FORMAT_XBGR2101010
:
3176 dspcntr
|= DISPPLANE_RGBX101010
;
3182 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3183 dspcntr
|= DISPPLANE_TILED
;
3185 if (rotation
& DRM_ROTATE_180
)
3186 dspcntr
|= DISPPLANE_ROTATE_180
;
3188 if (!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
))
3189 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
3191 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
3193 intel_crtc
->dspaddr_offset
=
3194 intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
3196 /* HSW+ does this automagically in hardware */
3197 if (!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
) &&
3198 rotation
& DRM_ROTATE_180
) {
3199 x
+= crtc_state
->pipe_src_w
- 1;
3200 y
+= crtc_state
->pipe_src_h
- 1;
3203 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
3205 intel_crtc
->adjusted_x
= x
;
3206 intel_crtc
->adjusted_y
= y
;
3208 I915_WRITE(reg
, dspcntr
);
3210 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
3211 I915_WRITE(DSPSURF(plane
),
3212 intel_plane_ggtt_offset(plane_state
) +
3213 intel_crtc
->dspaddr_offset
);
3214 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3215 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
3217 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
3218 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
3223 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
3224 uint64_t fb_modifier
, uint32_t pixel_format
)
3226 if (fb_modifier
== DRM_FORMAT_MOD_NONE
) {
3229 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
3231 return intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
3235 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
3237 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3238 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3240 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
3241 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
3242 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
3246 * This function detaches (aka. unbinds) unused scalers in hardware
3248 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
3250 struct intel_crtc_scaler_state
*scaler_state
;
3253 scaler_state
= &intel_crtc
->config
->scaler_state
;
3255 /* loop through and disable scalers that aren't in use */
3256 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
3257 if (!scaler_state
->scalers
[i
].in_use
)
3258 skl_detach_scaler(intel_crtc
, i
);
3262 u32
skl_plane_stride(const struct drm_framebuffer
*fb
, int plane
,
3263 unsigned int rotation
)
3265 const struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
3266 u32 stride
= intel_fb_pitch(fb
, plane
, rotation
);
3269 * The stride is either expressed as a multiple of 64 bytes chunks for
3270 * linear buffers or in number of tiles for tiled buffers.
3272 if (drm_rotation_90_or_270(rotation
)) {
3273 int cpp
= fb
->format
->cpp
[plane
];
3275 stride
/= intel_tile_height(dev_priv
, fb
->modifier
, cpp
);
3277 stride
/= intel_fb_stride_alignment(dev_priv
, fb
->modifier
,
3278 fb
->format
->format
);
3284 u32
skl_plane_ctl_format(uint32_t pixel_format
)
3286 switch (pixel_format
) {
3288 return PLANE_CTL_FORMAT_INDEXED
;
3289 case DRM_FORMAT_RGB565
:
3290 return PLANE_CTL_FORMAT_RGB_565
;
3291 case DRM_FORMAT_XBGR8888
:
3292 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
3293 case DRM_FORMAT_XRGB8888
:
3294 return PLANE_CTL_FORMAT_XRGB_8888
;
3296 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3297 * to be already pre-multiplied. We need to add a knob (or a different
3298 * DRM_FORMAT) for user-space to configure that.
3300 case DRM_FORMAT_ABGR8888
:
3301 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
3302 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3303 case DRM_FORMAT_ARGB8888
:
3304 return PLANE_CTL_FORMAT_XRGB_8888
|
3305 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3306 case DRM_FORMAT_XRGB2101010
:
3307 return PLANE_CTL_FORMAT_XRGB_2101010
;
3308 case DRM_FORMAT_XBGR2101010
:
3309 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
3310 case DRM_FORMAT_YUYV
:
3311 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
3312 case DRM_FORMAT_YVYU
:
3313 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
3314 case DRM_FORMAT_UYVY
:
3315 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
3316 case DRM_FORMAT_VYUY
:
3317 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3319 MISSING_CASE(pixel_format
);
3325 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
3327 switch (fb_modifier
) {
3328 case DRM_FORMAT_MOD_NONE
:
3330 case I915_FORMAT_MOD_X_TILED
:
3331 return PLANE_CTL_TILED_X
;
3332 case I915_FORMAT_MOD_Y_TILED
:
3333 return PLANE_CTL_TILED_Y
;
3334 case I915_FORMAT_MOD_Yf_TILED
:
3335 return PLANE_CTL_TILED_YF
;
3337 MISSING_CASE(fb_modifier
);
3343 u32
skl_plane_ctl_rotation(unsigned int rotation
)
3349 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3350 * while i915 HW rotation is clockwise, thats why this swapping.
3353 return PLANE_CTL_ROTATE_270
;
3354 case DRM_ROTATE_180
:
3355 return PLANE_CTL_ROTATE_180
;
3356 case DRM_ROTATE_270
:
3357 return PLANE_CTL_ROTATE_90
;
3359 MISSING_CASE(rotation
);
3365 static void skylake_update_primary_plane(struct drm_plane
*plane
,
3366 const struct intel_crtc_state
*crtc_state
,
3367 const struct intel_plane_state
*plane_state
)
3369 struct drm_device
*dev
= plane
->dev
;
3370 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3371 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3372 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3373 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
3374 enum pipe pipe
= to_intel_plane(plane
)->pipe
;
3376 unsigned int rotation
= plane_state
->base
.rotation
;
3377 u32 stride
= skl_plane_stride(fb
, 0, rotation
);
3378 u32 surf_addr
= plane_state
->main
.offset
;
3379 int scaler_id
= plane_state
->scaler_id
;
3380 int src_x
= plane_state
->main
.x
;
3381 int src_y
= plane_state
->main
.y
;
3382 int src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3383 int src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3384 int dst_x
= plane_state
->base
.dst
.x1
;
3385 int dst_y
= plane_state
->base
.dst
.y1
;
3386 int dst_w
= drm_rect_width(&plane_state
->base
.dst
);
3387 int dst_h
= drm_rect_height(&plane_state
->base
.dst
);
3389 plane_ctl
= PLANE_CTL_ENABLE
|
3390 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3391 PLANE_CTL_PIPE_CSC_ENABLE
;
3393 plane_ctl
|= skl_plane_ctl_format(fb
->format
->format
);
3394 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
);
3395 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3396 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3398 /* Sizes are 0 based */
3404 intel_crtc
->dspaddr_offset
= surf_addr
;
3406 intel_crtc
->adjusted_x
= src_x
;
3407 intel_crtc
->adjusted_y
= src_y
;
3409 I915_WRITE(PLANE_CTL(pipe
, plane_id
), plane_ctl
);
3410 I915_WRITE(PLANE_OFFSET(pipe
, plane_id
), (src_y
<< 16) | src_x
);
3411 I915_WRITE(PLANE_STRIDE(pipe
, plane_id
), stride
);
3412 I915_WRITE(PLANE_SIZE(pipe
, plane_id
), (src_h
<< 16) | src_w
);
3414 if (scaler_id
>= 0) {
3415 uint32_t ps_ctrl
= 0;
3417 WARN_ON(!dst_w
|| !dst_h
);
3418 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(plane_id
) |
3419 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3420 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3421 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3422 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3423 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3424 I915_WRITE(PLANE_POS(pipe
, plane_id
), 0);
3426 I915_WRITE(PLANE_POS(pipe
, plane_id
), (dst_y
<< 16) | dst_x
);
3429 I915_WRITE(PLANE_SURF(pipe
, plane_id
),
3430 intel_plane_ggtt_offset(plane_state
) + surf_addr
);
3432 POSTING_READ(PLANE_SURF(pipe
, plane_id
));
3435 static void skylake_disable_primary_plane(struct drm_plane
*primary
,
3436 struct drm_crtc
*crtc
)
3438 struct drm_device
*dev
= crtc
->dev
;
3439 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3440 enum plane_id plane_id
= to_intel_plane(primary
)->id
;
3441 enum pipe pipe
= to_intel_plane(primary
)->pipe
;
3443 I915_WRITE(PLANE_CTL(pipe
, plane_id
), 0);
3444 I915_WRITE(PLANE_SURF(pipe
, plane_id
), 0);
3445 POSTING_READ(PLANE_SURF(pipe
, plane_id
));
3448 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3450 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3451 int x
, int y
, enum mode_set_atomic state
)
3453 /* Support for kgdboc is disabled, this needs a major rework. */
3454 DRM_ERROR("legacy panic handler not supported any more.\n");
3459 static void intel_complete_page_flips(struct drm_i915_private
*dev_priv
)
3461 struct intel_crtc
*crtc
;
3463 for_each_intel_crtc(&dev_priv
->drm
, crtc
)
3464 intel_finish_page_flip_cs(dev_priv
, crtc
->pipe
);
3467 static void intel_update_primary_planes(struct drm_device
*dev
)
3469 struct drm_crtc
*crtc
;
3471 for_each_crtc(dev
, crtc
) {
3472 struct intel_plane
*plane
= to_intel_plane(crtc
->primary
);
3473 struct intel_plane_state
*plane_state
=
3474 to_intel_plane_state(plane
->base
.state
);
3476 if (plane_state
->base
.visible
)
3477 plane
->update_plane(&plane
->base
,
3478 to_intel_crtc_state(crtc
->state
),
3484 __intel_display_resume(struct drm_device
*dev
,
3485 struct drm_atomic_state
*state
,
3486 struct drm_modeset_acquire_ctx
*ctx
)
3488 struct drm_crtc_state
*crtc_state
;
3489 struct drm_crtc
*crtc
;
3492 intel_modeset_setup_hw_state(dev
);
3493 i915_redisable_vga(to_i915(dev
));
3498 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
3500 * Force recalculation even if we restore
3501 * current state. With fast modeset this may not result
3502 * in a modeset when the state is compatible.
3504 crtc_state
->mode_changed
= true;
3507 /* ignore any reset values/BIOS leftovers in the WM registers */
3508 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
3510 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
3512 WARN_ON(ret
== -EDEADLK
);
3516 static bool gpu_reset_clobbers_display(struct drm_i915_private
*dev_priv
)
3518 return intel_has_gpu_reset(dev_priv
) &&
3519 INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
);
3522 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
3524 struct drm_device
*dev
= &dev_priv
->drm
;
3525 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3526 struct drm_atomic_state
*state
;
3530 * Need mode_config.mutex so that we don't
3531 * trample ongoing ->detect() and whatnot.
3533 mutex_lock(&dev
->mode_config
.mutex
);
3534 drm_modeset_acquire_init(ctx
, 0);
3536 ret
= drm_modeset_lock_all_ctx(dev
, ctx
);
3537 if (ret
!= -EDEADLK
)
3540 drm_modeset_backoff(ctx
);
3543 /* reset doesn't touch the display, but flips might get nuked anyway, */
3544 if (!i915
.force_reset_modeset_test
&&
3545 !gpu_reset_clobbers_display(dev_priv
))
3549 * Disabling the crtcs gracefully seems nicer. Also the
3550 * g33 docs say we should at least disable all the planes.
3552 state
= drm_atomic_helper_duplicate_state(dev
, ctx
);
3553 if (IS_ERR(state
)) {
3554 ret
= PTR_ERR(state
);
3555 DRM_ERROR("Duplicating state failed with %i\n", ret
);
3559 ret
= drm_atomic_helper_disable_all(dev
, ctx
);
3561 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
3562 drm_atomic_state_put(state
);
3566 dev_priv
->modeset_restore_state
= state
;
3567 state
->acquire_ctx
= ctx
;
3570 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
3572 struct drm_device
*dev
= &dev_priv
->drm
;
3573 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3574 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
3578 * Flips in the rings will be nuked by the reset,
3579 * so complete all pending flips so that user space
3580 * will get its events and not get stuck.
3582 intel_complete_page_flips(dev_priv
);
3584 dev_priv
->modeset_restore_state
= NULL
;
3586 /* reset doesn't touch the display */
3587 if (!gpu_reset_clobbers_display(dev_priv
)) {
3590 * Flips in the rings have been nuked by the reset,
3591 * so update the base address of all primary
3592 * planes to the the last fb to make sure we're
3593 * showing the correct fb after a reset.
3595 * FIXME: Atomic will make this obsolete since we won't schedule
3596 * CS-based flips (which might get lost in gpu resets) any more.
3598 intel_update_primary_planes(dev
);
3600 ret
= __intel_display_resume(dev
, state
, ctx
);
3602 DRM_ERROR("Restoring old state failed with %i\n", ret
);
3606 * The display has been reset as well,
3607 * so need a full re-initialization.
3609 intel_runtime_pm_disable_interrupts(dev_priv
);
3610 intel_runtime_pm_enable_interrupts(dev_priv
);
3612 intel_pps_unlock_regs_wa(dev_priv
);
3613 intel_modeset_init_hw(dev
);
3615 spin_lock_irq(&dev_priv
->irq_lock
);
3616 if (dev_priv
->display
.hpd_irq_setup
)
3617 dev_priv
->display
.hpd_irq_setup(dev_priv
);
3618 spin_unlock_irq(&dev_priv
->irq_lock
);
3620 ret
= __intel_display_resume(dev
, state
, ctx
);
3622 DRM_ERROR("Restoring old state failed with %i\n", ret
);
3624 intel_hpd_init(dev_priv
);
3628 drm_atomic_state_put(state
);
3629 drm_modeset_drop_locks(ctx
);
3630 drm_modeset_acquire_fini(ctx
);
3631 mutex_unlock(&dev
->mode_config
.mutex
);
3634 static bool abort_flip_on_reset(struct intel_crtc
*crtc
)
3636 struct i915_gpu_error
*error
= &to_i915(crtc
->base
.dev
)->gpu_error
;
3638 if (i915_reset_in_progress(error
))
3641 if (crtc
->reset_count
!= i915_reset_count(error
))
3647 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3649 struct drm_device
*dev
= crtc
->dev
;
3650 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3653 if (abort_flip_on_reset(intel_crtc
))
3656 spin_lock_irq(&dev
->event_lock
);
3657 pending
= to_intel_crtc(crtc
)->flip_work
!= NULL
;
3658 spin_unlock_irq(&dev
->event_lock
);
3663 static void intel_update_pipe_config(struct intel_crtc
*crtc
,
3664 struct intel_crtc_state
*old_crtc_state
)
3666 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3667 struct intel_crtc_state
*pipe_config
=
3668 to_intel_crtc_state(crtc
->base
.state
);
3670 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3671 crtc
->base
.mode
= crtc
->base
.state
->mode
;
3673 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3674 old_crtc_state
->pipe_src_w
, old_crtc_state
->pipe_src_h
,
3675 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
3678 * Update pipe size and adjust fitter if needed: the reason for this is
3679 * that in compute_mode_changes we check the native mode (not the pfit
3680 * mode) to see if we can flip rather than do a full mode set. In the
3681 * fastboot case, we'll flip, but if we don't update the pipesrc and
3682 * pfit state, we'll end up with a big fb scanned out into the wrong
3686 I915_WRITE(PIPESRC(crtc
->pipe
),
3687 ((pipe_config
->pipe_src_w
- 1) << 16) |
3688 (pipe_config
->pipe_src_h
- 1));
3690 /* on skylake this is done by detaching scalers */
3691 if (INTEL_GEN(dev_priv
) >= 9) {
3692 skl_detach_scalers(crtc
);
3694 if (pipe_config
->pch_pfit
.enabled
)
3695 skylake_pfit_enable(crtc
);
3696 } else if (HAS_PCH_SPLIT(dev_priv
)) {
3697 if (pipe_config
->pch_pfit
.enabled
)
3698 ironlake_pfit_enable(crtc
);
3699 else if (old_crtc_state
->pch_pfit
.enabled
)
3700 ironlake_pfit_disable(crtc
, true);
3704 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3706 struct drm_device
*dev
= crtc
->dev
;
3707 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3708 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3709 int pipe
= intel_crtc
->pipe
;
3713 /* enable normal train */
3714 reg
= FDI_TX_CTL(pipe
);
3715 temp
= I915_READ(reg
);
3716 if (IS_IVYBRIDGE(dev_priv
)) {
3717 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3718 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3720 temp
&= ~FDI_LINK_TRAIN_NONE
;
3721 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3723 I915_WRITE(reg
, temp
);
3725 reg
= FDI_RX_CTL(pipe
);
3726 temp
= I915_READ(reg
);
3727 if (HAS_PCH_CPT(dev_priv
)) {
3728 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3729 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3731 temp
&= ~FDI_LINK_TRAIN_NONE
;
3732 temp
|= FDI_LINK_TRAIN_NONE
;
3734 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3736 /* wait one idle pattern time */
3740 /* IVB wants error correction enabled */
3741 if (IS_IVYBRIDGE(dev_priv
))
3742 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3743 FDI_FE_ERRC_ENABLE
);
3746 /* The FDI link training functions for ILK/Ibexpeak. */
3747 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3749 struct drm_device
*dev
= crtc
->dev
;
3750 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3751 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3752 int pipe
= intel_crtc
->pipe
;
3756 /* FDI needs bits from pipe first */
3757 assert_pipe_enabled(dev_priv
, pipe
);
3759 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3761 reg
= FDI_RX_IMR(pipe
);
3762 temp
= I915_READ(reg
);
3763 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3764 temp
&= ~FDI_RX_BIT_LOCK
;
3765 I915_WRITE(reg
, temp
);
3769 /* enable CPU FDI TX and PCH FDI RX */
3770 reg
= FDI_TX_CTL(pipe
);
3771 temp
= I915_READ(reg
);
3772 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3773 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3774 temp
&= ~FDI_LINK_TRAIN_NONE
;
3775 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3776 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3778 reg
= FDI_RX_CTL(pipe
);
3779 temp
= I915_READ(reg
);
3780 temp
&= ~FDI_LINK_TRAIN_NONE
;
3781 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3782 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3787 /* Ironlake workaround, enable clock pointer after FDI enable*/
3788 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3789 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3790 FDI_RX_PHASE_SYNC_POINTER_EN
);
3792 reg
= FDI_RX_IIR(pipe
);
3793 for (tries
= 0; tries
< 5; tries
++) {
3794 temp
= I915_READ(reg
);
3795 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3797 if ((temp
& FDI_RX_BIT_LOCK
)) {
3798 DRM_DEBUG_KMS("FDI train 1 done.\n");
3799 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3804 DRM_ERROR("FDI train 1 fail!\n");
3807 reg
= FDI_TX_CTL(pipe
);
3808 temp
= I915_READ(reg
);
3809 temp
&= ~FDI_LINK_TRAIN_NONE
;
3810 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3811 I915_WRITE(reg
, temp
);
3813 reg
= FDI_RX_CTL(pipe
);
3814 temp
= I915_READ(reg
);
3815 temp
&= ~FDI_LINK_TRAIN_NONE
;
3816 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3817 I915_WRITE(reg
, temp
);
3822 reg
= FDI_RX_IIR(pipe
);
3823 for (tries
= 0; tries
< 5; tries
++) {
3824 temp
= I915_READ(reg
);
3825 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3827 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3828 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3829 DRM_DEBUG_KMS("FDI train 2 done.\n");
3834 DRM_ERROR("FDI train 2 fail!\n");
3836 DRM_DEBUG_KMS("FDI train done\n");
3840 static const int snb_b_fdi_train_param
[] = {
3841 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3842 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3843 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3844 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3847 /* The FDI link training functions for SNB/Cougarpoint. */
3848 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3850 struct drm_device
*dev
= crtc
->dev
;
3851 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3852 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3853 int pipe
= intel_crtc
->pipe
;
3857 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3859 reg
= FDI_RX_IMR(pipe
);
3860 temp
= I915_READ(reg
);
3861 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3862 temp
&= ~FDI_RX_BIT_LOCK
;
3863 I915_WRITE(reg
, temp
);
3868 /* enable CPU FDI TX and PCH FDI RX */
3869 reg
= FDI_TX_CTL(pipe
);
3870 temp
= I915_READ(reg
);
3871 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3872 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3873 temp
&= ~FDI_LINK_TRAIN_NONE
;
3874 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3875 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3877 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3878 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3880 I915_WRITE(FDI_RX_MISC(pipe
),
3881 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3883 reg
= FDI_RX_CTL(pipe
);
3884 temp
= I915_READ(reg
);
3885 if (HAS_PCH_CPT(dev_priv
)) {
3886 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3887 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3889 temp
&= ~FDI_LINK_TRAIN_NONE
;
3890 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3892 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3897 for (i
= 0; i
< 4; i
++) {
3898 reg
= FDI_TX_CTL(pipe
);
3899 temp
= I915_READ(reg
);
3900 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3901 temp
|= snb_b_fdi_train_param
[i
];
3902 I915_WRITE(reg
, temp
);
3907 for (retry
= 0; retry
< 5; retry
++) {
3908 reg
= FDI_RX_IIR(pipe
);
3909 temp
= I915_READ(reg
);
3910 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3911 if (temp
& FDI_RX_BIT_LOCK
) {
3912 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3913 DRM_DEBUG_KMS("FDI train 1 done.\n");
3922 DRM_ERROR("FDI train 1 fail!\n");
3925 reg
= FDI_TX_CTL(pipe
);
3926 temp
= I915_READ(reg
);
3927 temp
&= ~FDI_LINK_TRAIN_NONE
;
3928 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3929 if (IS_GEN6(dev_priv
)) {
3930 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3932 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3934 I915_WRITE(reg
, temp
);
3936 reg
= FDI_RX_CTL(pipe
);
3937 temp
= I915_READ(reg
);
3938 if (HAS_PCH_CPT(dev_priv
)) {
3939 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3940 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3942 temp
&= ~FDI_LINK_TRAIN_NONE
;
3943 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3945 I915_WRITE(reg
, temp
);
3950 for (i
= 0; i
< 4; i
++) {
3951 reg
= FDI_TX_CTL(pipe
);
3952 temp
= I915_READ(reg
);
3953 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3954 temp
|= snb_b_fdi_train_param
[i
];
3955 I915_WRITE(reg
, temp
);
3960 for (retry
= 0; retry
< 5; retry
++) {
3961 reg
= FDI_RX_IIR(pipe
);
3962 temp
= I915_READ(reg
);
3963 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3964 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3965 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3966 DRM_DEBUG_KMS("FDI train 2 done.\n");
3975 DRM_ERROR("FDI train 2 fail!\n");
3977 DRM_DEBUG_KMS("FDI train done.\n");
3980 /* Manual link training for Ivy Bridge A0 parts */
3981 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3983 struct drm_device
*dev
= crtc
->dev
;
3984 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3985 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3986 int pipe
= intel_crtc
->pipe
;
3990 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3992 reg
= FDI_RX_IMR(pipe
);
3993 temp
= I915_READ(reg
);
3994 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3995 temp
&= ~FDI_RX_BIT_LOCK
;
3996 I915_WRITE(reg
, temp
);
4001 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4002 I915_READ(FDI_RX_IIR(pipe
)));
4004 /* Try each vswing and preemphasis setting twice before moving on */
4005 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
4006 /* disable first in case we need to retry */
4007 reg
= FDI_TX_CTL(pipe
);
4008 temp
= I915_READ(reg
);
4009 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
4010 temp
&= ~FDI_TX_ENABLE
;
4011 I915_WRITE(reg
, temp
);
4013 reg
= FDI_RX_CTL(pipe
);
4014 temp
= I915_READ(reg
);
4015 temp
&= ~FDI_LINK_TRAIN_AUTO
;
4016 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4017 temp
&= ~FDI_RX_ENABLE
;
4018 I915_WRITE(reg
, temp
);
4020 /* enable CPU FDI TX and PCH FDI RX */
4021 reg
= FDI_TX_CTL(pipe
);
4022 temp
= I915_READ(reg
);
4023 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4024 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
4025 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
4026 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4027 temp
|= snb_b_fdi_train_param
[j
/2];
4028 temp
|= FDI_COMPOSITE_SYNC
;
4029 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4031 I915_WRITE(FDI_RX_MISC(pipe
),
4032 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4034 reg
= FDI_RX_CTL(pipe
);
4035 temp
= I915_READ(reg
);
4036 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4037 temp
|= FDI_COMPOSITE_SYNC
;
4038 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4041 udelay(1); /* should be 0.5us */
4043 for (i
= 0; i
< 4; i
++) {
4044 reg
= FDI_RX_IIR(pipe
);
4045 temp
= I915_READ(reg
);
4046 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4048 if (temp
& FDI_RX_BIT_LOCK
||
4049 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
4050 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4051 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4055 udelay(1); /* should be 0.5us */
4058 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
4063 reg
= FDI_TX_CTL(pipe
);
4064 temp
= I915_READ(reg
);
4065 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4066 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
4067 I915_WRITE(reg
, temp
);
4069 reg
= FDI_RX_CTL(pipe
);
4070 temp
= I915_READ(reg
);
4071 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4072 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4073 I915_WRITE(reg
, temp
);
4076 udelay(2); /* should be 1.5us */
4078 for (i
= 0; i
< 4; i
++) {
4079 reg
= FDI_RX_IIR(pipe
);
4080 temp
= I915_READ(reg
);
4081 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4083 if (temp
& FDI_RX_SYMBOL_LOCK
||
4084 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
4085 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4086 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4090 udelay(2); /* should be 1.5us */
4093 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
4097 DRM_DEBUG_KMS("FDI train done.\n");
4100 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
4102 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4103 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4104 int pipe
= intel_crtc
->pipe
;
4108 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4109 reg
= FDI_RX_CTL(pipe
);
4110 temp
= I915_READ(reg
);
4111 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
4112 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
4113 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4114 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
4119 /* Switch from Rawclk to PCDclk */
4120 temp
= I915_READ(reg
);
4121 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
4126 /* Enable CPU FDI TX PLL, always on for Ironlake */
4127 reg
= FDI_TX_CTL(pipe
);
4128 temp
= I915_READ(reg
);
4129 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
4130 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
4137 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
4139 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4140 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4141 int pipe
= intel_crtc
->pipe
;
4145 /* Switch from PCDclk to Rawclk */
4146 reg
= FDI_RX_CTL(pipe
);
4147 temp
= I915_READ(reg
);
4148 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
4150 /* Disable CPU FDI TX PLL */
4151 reg
= FDI_TX_CTL(pipe
);
4152 temp
= I915_READ(reg
);
4153 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
4158 reg
= FDI_RX_CTL(pipe
);
4159 temp
= I915_READ(reg
);
4160 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
4162 /* Wait for the clocks to turn off. */
4167 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
4169 struct drm_device
*dev
= crtc
->dev
;
4170 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4172 int pipe
= intel_crtc
->pipe
;
4176 /* disable CPU FDI tx and PCH FDI rx */
4177 reg
= FDI_TX_CTL(pipe
);
4178 temp
= I915_READ(reg
);
4179 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
4182 reg
= FDI_RX_CTL(pipe
);
4183 temp
= I915_READ(reg
);
4184 temp
&= ~(0x7 << 16);
4185 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4186 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
4191 /* Ironlake workaround, disable clock pointer after downing FDI */
4192 if (HAS_PCH_IBX(dev_priv
))
4193 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4195 /* still set train pattern 1 */
4196 reg
= FDI_TX_CTL(pipe
);
4197 temp
= I915_READ(reg
);
4198 temp
&= ~FDI_LINK_TRAIN_NONE
;
4199 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4200 I915_WRITE(reg
, temp
);
4202 reg
= FDI_RX_CTL(pipe
);
4203 temp
= I915_READ(reg
);
4204 if (HAS_PCH_CPT(dev_priv
)) {
4205 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4206 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4208 temp
&= ~FDI_LINK_TRAIN_NONE
;
4209 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4211 /* BPC in FDI rx is consistent with that in PIPECONF */
4212 temp
&= ~(0x07 << 16);
4213 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4214 I915_WRITE(reg
, temp
);
4220 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
)
4222 struct intel_crtc
*crtc
;
4224 /* Note that we don't need to be called with mode_config.lock here
4225 * as our list of CRTC objects is static for the lifetime of the
4226 * device and so cannot disappear as we iterate. Similarly, we can
4227 * happily treat the predicates as racy, atomic checks as userspace
4228 * cannot claim and pin a new fb without at least acquring the
4229 * struct_mutex and so serialising with us.
4231 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
4232 if (atomic_read(&crtc
->unpin_work_count
) == 0)
4235 if (crtc
->flip_work
)
4236 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4244 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
4246 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
4247 struct intel_flip_work
*work
= intel_crtc
->flip_work
;
4249 intel_crtc
->flip_work
= NULL
;
4252 drm_crtc_send_vblank_event(&intel_crtc
->base
, work
->event
);
4254 drm_crtc_vblank_put(&intel_crtc
->base
);
4256 wake_up_all(&dev_priv
->pending_flip_queue
);
4257 trace_i915_flip_complete(intel_crtc
->plane
,
4258 work
->pending_flip_obj
);
4260 queue_work(dev_priv
->wq
, &work
->unpin_work
);
4263 static int intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
4265 struct drm_device
*dev
= crtc
->dev
;
4266 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4269 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
4271 ret
= wait_event_interruptible_timeout(
4272 dev_priv
->pending_flip_queue
,
4273 !intel_crtc_has_pending_flip(crtc
),
4280 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4281 struct intel_flip_work
*work
;
4283 spin_lock_irq(&dev
->event_lock
);
4284 work
= intel_crtc
->flip_work
;
4285 if (work
&& !is_mmio_work(work
)) {
4286 WARN_ONCE(1, "Removing stuck page flip\n");
4287 page_flip_completed(intel_crtc
);
4289 spin_unlock_irq(&dev
->event_lock
);
4295 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
4299 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
4301 mutex_lock(&dev_priv
->sb_lock
);
4303 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4304 temp
|= SBI_SSCCTL_DISABLE
;
4305 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4307 mutex_unlock(&dev_priv
->sb_lock
);
4310 /* Program iCLKIP clock to the desired frequency */
4311 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
4313 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
4314 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
4315 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
4318 lpt_disable_iclkip(dev_priv
);
4320 /* The iCLK virtual clock root frequency is in MHz,
4321 * but the adjusted_mode->crtc_clock in in KHz. To get the
4322 * divisors, it is necessary to divide one by another, so we
4323 * convert the virtual clock precision to KHz here for higher
4326 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
4327 u32 iclk_virtual_root_freq
= 172800 * 1000;
4328 u32 iclk_pi_range
= 64;
4329 u32 desired_divisor
;
4331 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4333 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
4334 phaseinc
= desired_divisor
% iclk_pi_range
;
4337 * Near 20MHz is a corner case which is
4338 * out of range for the 7-bit divisor
4344 /* This should not happen with any sane values */
4345 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4346 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4347 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4348 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4350 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4357 mutex_lock(&dev_priv
->sb_lock
);
4359 /* Program SSCDIVINTPHASE6 */
4360 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4361 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4362 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4363 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4364 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4365 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4366 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4367 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4369 /* Program SSCAUXDIV */
4370 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4371 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4372 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4373 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4375 /* Enable modulator and associated divider */
4376 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4377 temp
&= ~SBI_SSCCTL_DISABLE
;
4378 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4380 mutex_unlock(&dev_priv
->sb_lock
);
4382 /* Wait for initialization time */
4385 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4388 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
4390 u32 divsel
, phaseinc
, auxdiv
;
4391 u32 iclk_virtual_root_freq
= 172800 * 1000;
4392 u32 iclk_pi_range
= 64;
4393 u32 desired_divisor
;
4396 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
4399 mutex_lock(&dev_priv
->sb_lock
);
4401 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4402 if (temp
& SBI_SSCCTL_DISABLE
) {
4403 mutex_unlock(&dev_priv
->sb_lock
);
4407 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4408 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
4409 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
4410 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
4411 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
4413 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4414 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
4415 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
4417 mutex_unlock(&dev_priv
->sb_lock
);
4419 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
4421 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4422 desired_divisor
<< auxdiv
);
4425 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4426 enum pipe pch_transcoder
)
4428 struct drm_device
*dev
= crtc
->base
.dev
;
4429 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4430 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4432 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4433 I915_READ(HTOTAL(cpu_transcoder
)));
4434 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4435 I915_READ(HBLANK(cpu_transcoder
)));
4436 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4437 I915_READ(HSYNC(cpu_transcoder
)));
4439 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4440 I915_READ(VTOTAL(cpu_transcoder
)));
4441 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4442 I915_READ(VBLANK(cpu_transcoder
)));
4443 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4444 I915_READ(VSYNC(cpu_transcoder
)));
4445 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4446 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4449 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4451 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4454 temp
= I915_READ(SOUTH_CHICKEN1
);
4455 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4458 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4459 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4461 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4463 temp
|= FDI_BC_BIFURCATION_SELECT
;
4465 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4466 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4467 POSTING_READ(SOUTH_CHICKEN1
);
4470 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4472 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4474 switch (intel_crtc
->pipe
) {
4478 if (intel_crtc
->config
->fdi_lanes
> 2)
4479 cpt_set_fdi_bc_bifurcation(dev
, false);
4481 cpt_set_fdi_bc_bifurcation(dev
, true);
4485 cpt_set_fdi_bc_bifurcation(dev
, true);
4493 /* Return which DP Port should be selected for Transcoder DP control */
4495 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4497 struct drm_device
*dev
= crtc
->dev
;
4498 struct intel_encoder
*encoder
;
4500 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4501 if (encoder
->type
== INTEL_OUTPUT_DP
||
4502 encoder
->type
== INTEL_OUTPUT_EDP
)
4503 return enc_to_dig_port(&encoder
->base
)->port
;
4510 * Enable PCH resources required for PCH ports:
4512 * - FDI training & RX/TX
4513 * - update transcoder timings
4514 * - DP transcoding bits
4517 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4519 struct drm_device
*dev
= crtc
->dev
;
4520 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4521 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4522 int pipe
= intel_crtc
->pipe
;
4525 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4527 if (IS_IVYBRIDGE(dev_priv
))
4528 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4530 /* Write the TU size bits before fdi link training, so that error
4531 * detection works. */
4532 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4533 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4535 /* For PCH output, training FDI link */
4536 dev_priv
->display
.fdi_link_train(crtc
);
4538 /* We need to program the right clock selection before writing the pixel
4539 * mutliplier into the DPLL. */
4540 if (HAS_PCH_CPT(dev_priv
)) {
4543 temp
= I915_READ(PCH_DPLL_SEL
);
4544 temp
|= TRANS_DPLL_ENABLE(pipe
);
4545 sel
= TRANS_DPLLB_SEL(pipe
);
4546 if (intel_crtc
->config
->shared_dpll
==
4547 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4551 I915_WRITE(PCH_DPLL_SEL
, temp
);
4554 /* XXX: pch pll's can be enabled any time before we enable the PCH
4555 * transcoder, and we actually should do this to not upset any PCH
4556 * transcoder that already use the clock when we share it.
4558 * Note that enable_shared_dpll tries to do the right thing, but
4559 * get_shared_dpll unconditionally resets the pll - we need that to have
4560 * the right LVDS enable sequence. */
4561 intel_enable_shared_dpll(intel_crtc
);
4563 /* set transcoder timing, panel must allow it */
4564 assert_panel_unlocked(dev_priv
, pipe
);
4565 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4567 intel_fdi_normal_train(crtc
);
4569 /* For PCH DP, enable TRANS_DP_CTL */
4570 if (HAS_PCH_CPT(dev_priv
) &&
4571 intel_crtc_has_dp_encoder(intel_crtc
->config
)) {
4572 const struct drm_display_mode
*adjusted_mode
=
4573 &intel_crtc
->config
->base
.adjusted_mode
;
4574 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4575 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4576 temp
= I915_READ(reg
);
4577 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4578 TRANS_DP_SYNC_MASK
|
4580 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4581 temp
|= bpc
<< 9; /* same format but at 11:9 */
4583 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4584 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4585 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4586 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4588 switch (intel_trans_dp_port_sel(crtc
)) {
4590 temp
|= TRANS_DP_PORT_SEL_B
;
4593 temp
|= TRANS_DP_PORT_SEL_C
;
4596 temp
|= TRANS_DP_PORT_SEL_D
;
4602 I915_WRITE(reg
, temp
);
4605 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4608 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4610 struct drm_device
*dev
= crtc
->dev
;
4611 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4612 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4613 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4615 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4617 lpt_program_iclkip(crtc
);
4619 /* Set transcoder timing. */
4620 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4622 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4625 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4627 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4628 i915_reg_t dslreg
= PIPEDSL(pipe
);
4631 temp
= I915_READ(dslreg
);
4633 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4634 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4635 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4640 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4641 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4642 int src_w
, int src_h
, int dst_w
, int dst_h
)
4644 struct intel_crtc_scaler_state
*scaler_state
=
4645 &crtc_state
->scaler_state
;
4646 struct intel_crtc
*intel_crtc
=
4647 to_intel_crtc(crtc_state
->base
.crtc
);
4650 need_scaling
= drm_rotation_90_or_270(rotation
) ?
4651 (src_h
!= dst_w
|| src_w
!= dst_h
):
4652 (src_w
!= dst_w
|| src_h
!= dst_h
);
4655 * if plane is being disabled or scaler is no more required or force detach
4656 * - free scaler binded to this plane/crtc
4657 * - in order to do this, update crtc->scaler_usage
4659 * Here scaler state in crtc_state is set free so that
4660 * scaler can be assigned to other user. Actual register
4661 * update to free the scaler is done in plane/panel-fit programming.
4662 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4664 if (force_detach
|| !need_scaling
) {
4665 if (*scaler_id
>= 0) {
4666 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4667 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4669 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4670 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4671 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4672 scaler_state
->scaler_users
);
4679 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4680 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4682 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4683 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4684 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4685 "size is out of scaler range\n",
4686 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4690 /* mark this plane as a scaler user in crtc_state */
4691 scaler_state
->scaler_users
|= (1 << scaler_user
);
4692 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4693 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4694 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4695 scaler_state
->scaler_users
);
4701 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4703 * @state: crtc's scaler state
4706 * 0 - scaler_usage updated successfully
4707 * error - requested scaling cannot be supported or other error condition
4709 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4711 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4713 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4714 &state
->scaler_state
.scaler_id
, DRM_ROTATE_0
,
4715 state
->pipe_src_w
, state
->pipe_src_h
,
4716 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4720 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4722 * @state: crtc's scaler state
4723 * @plane_state: atomic plane state to update
4726 * 0 - scaler_usage updated successfully
4727 * error - requested scaling cannot be supported or other error condition
4729 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4730 struct intel_plane_state
*plane_state
)
4733 struct intel_plane
*intel_plane
=
4734 to_intel_plane(plane_state
->base
.plane
);
4735 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4738 bool force_detach
= !fb
|| !plane_state
->base
.visible
;
4740 ret
= skl_update_scaler(crtc_state
, force_detach
,
4741 drm_plane_index(&intel_plane
->base
),
4742 &plane_state
->scaler_id
,
4743 plane_state
->base
.rotation
,
4744 drm_rect_width(&plane_state
->base
.src
) >> 16,
4745 drm_rect_height(&plane_state
->base
.src
) >> 16,
4746 drm_rect_width(&plane_state
->base
.dst
),
4747 drm_rect_height(&plane_state
->base
.dst
));
4749 if (ret
|| plane_state
->scaler_id
< 0)
4752 /* check colorkey */
4753 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4754 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4755 intel_plane
->base
.base
.id
,
4756 intel_plane
->base
.name
);
4760 /* Check src format */
4761 switch (fb
->format
->format
) {
4762 case DRM_FORMAT_RGB565
:
4763 case DRM_FORMAT_XBGR8888
:
4764 case DRM_FORMAT_XRGB8888
:
4765 case DRM_FORMAT_ABGR8888
:
4766 case DRM_FORMAT_ARGB8888
:
4767 case DRM_FORMAT_XRGB2101010
:
4768 case DRM_FORMAT_XBGR2101010
:
4769 case DRM_FORMAT_YUYV
:
4770 case DRM_FORMAT_YVYU
:
4771 case DRM_FORMAT_UYVY
:
4772 case DRM_FORMAT_VYUY
:
4775 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4776 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
4777 fb
->base
.id
, fb
->format
->format
);
4784 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4788 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4789 skl_detach_scaler(crtc
, i
);
4792 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4794 struct drm_device
*dev
= crtc
->base
.dev
;
4795 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4796 int pipe
= crtc
->pipe
;
4797 struct intel_crtc_scaler_state
*scaler_state
=
4798 &crtc
->config
->scaler_state
;
4800 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4802 if (crtc
->config
->pch_pfit
.enabled
) {
4805 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4806 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4810 id
= scaler_state
->scaler_id
;
4811 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4812 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4813 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4814 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4816 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4820 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4822 struct drm_device
*dev
= crtc
->base
.dev
;
4823 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4824 int pipe
= crtc
->pipe
;
4826 if (crtc
->config
->pch_pfit
.enabled
) {
4827 /* Force use of hard-coded filter coefficients
4828 * as some pre-programmed values are broken,
4831 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
4832 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4833 PF_PIPE_SEL_IVB(pipe
));
4835 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4836 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4837 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4841 void hsw_enable_ips(struct intel_crtc
*crtc
)
4843 struct drm_device
*dev
= crtc
->base
.dev
;
4844 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4846 if (!crtc
->config
->ips_enabled
)
4850 * We can only enable IPS after we enable a plane and wait for a vblank
4851 * This function is called from post_plane_update, which is run after
4855 assert_plane_enabled(dev_priv
, crtc
->plane
);
4856 if (IS_BROADWELL(dev_priv
)) {
4857 mutex_lock(&dev_priv
->rps
.hw_lock
);
4858 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4859 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4860 /* Quoting Art Runyan: "its not safe to expect any particular
4861 * value in IPS_CTL bit 31 after enabling IPS through the
4862 * mailbox." Moreover, the mailbox may return a bogus state,
4863 * so we need to just enable it and continue on.
4866 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4867 /* The bit only becomes 1 in the next vblank, so this wait here
4868 * is essentially intel_wait_for_vblank. If we don't have this
4869 * and don't wait for vblanks until the end of crtc_enable, then
4870 * the HW state readout code will complain that the expected
4871 * IPS_CTL value is not the one we read. */
4872 if (intel_wait_for_register(dev_priv
,
4873 IPS_CTL
, IPS_ENABLE
, IPS_ENABLE
,
4875 DRM_ERROR("Timed out waiting for IPS enable\n");
4879 void hsw_disable_ips(struct intel_crtc
*crtc
)
4881 struct drm_device
*dev
= crtc
->base
.dev
;
4882 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4884 if (!crtc
->config
->ips_enabled
)
4887 assert_plane_enabled(dev_priv
, crtc
->plane
);
4888 if (IS_BROADWELL(dev_priv
)) {
4889 mutex_lock(&dev_priv
->rps
.hw_lock
);
4890 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4891 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4892 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4893 if (intel_wait_for_register(dev_priv
,
4894 IPS_CTL
, IPS_ENABLE
, 0,
4896 DRM_ERROR("Timed out waiting for IPS disable\n");
4898 I915_WRITE(IPS_CTL
, 0);
4899 POSTING_READ(IPS_CTL
);
4902 /* We need to wait for a vblank before we can disable the plane. */
4903 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4906 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4908 if (intel_crtc
->overlay
) {
4909 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4910 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4912 mutex_lock(&dev
->struct_mutex
);
4913 dev_priv
->mm
.interruptible
= false;
4914 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4915 dev_priv
->mm
.interruptible
= true;
4916 mutex_unlock(&dev
->struct_mutex
);
4919 /* Let userspace switch the overlay on again. In most cases userspace
4920 * has to recompute where to put it anyway.
4925 * intel_post_enable_primary - Perform operations after enabling primary plane
4926 * @crtc: the CRTC whose primary plane was just enabled
4928 * Performs potentially sleeping operations that must be done after the primary
4929 * plane is enabled, such as updating FBC and IPS. Note that this may be
4930 * called due to an explicit primary plane update, or due to an implicit
4931 * re-enable that is caused when a sprite plane is updated to no longer
4932 * completely hide the primary plane.
4935 intel_post_enable_primary(struct drm_crtc
*crtc
)
4937 struct drm_device
*dev
= crtc
->dev
;
4938 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4939 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4940 int pipe
= intel_crtc
->pipe
;
4943 * FIXME IPS should be fine as long as one plane is
4944 * enabled, but in practice it seems to have problems
4945 * when going from primary only to sprite only and vice
4948 hsw_enable_ips(intel_crtc
);
4951 * Gen2 reports pipe underruns whenever all planes are disabled.
4952 * So don't enable underrun reporting before at least some planes
4954 * FIXME: Need to fix the logic to work when we turn off all planes
4955 * but leave the pipe running.
4957 if (IS_GEN2(dev_priv
))
4958 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4960 /* Underruns don't always raise interrupts, so check manually. */
4961 intel_check_cpu_fifo_underruns(dev_priv
);
4962 intel_check_pch_fifo_underruns(dev_priv
);
4965 /* FIXME move all this to pre_plane_update() with proper state tracking */
4967 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4969 struct drm_device
*dev
= crtc
->dev
;
4970 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4971 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4972 int pipe
= intel_crtc
->pipe
;
4975 * Gen2 reports pipe underruns whenever all planes are disabled.
4976 * So diasble underrun reporting before all the planes get disabled.
4977 * FIXME: Need to fix the logic to work when we turn off all planes
4978 * but leave the pipe running.
4980 if (IS_GEN2(dev_priv
))
4981 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4984 * FIXME IPS should be fine as long as one plane is
4985 * enabled, but in practice it seems to have problems
4986 * when going from primary only to sprite only and vice
4989 hsw_disable_ips(intel_crtc
);
4992 /* FIXME get rid of this and use pre_plane_update */
4994 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
4996 struct drm_device
*dev
= crtc
->dev
;
4997 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4998 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4999 int pipe
= intel_crtc
->pipe
;
5001 intel_pre_disable_primary(crtc
);
5004 * Vblank time updates from the shadow to live plane control register
5005 * are blocked if the memory self-refresh mode is active at that
5006 * moment. So to make sure the plane gets truly disabled, disable
5007 * first the self-refresh mode. The self-refresh enable bit in turn
5008 * will be checked/applied by the HW only at the next frame start
5009 * event which is after the vblank start event, so we need to have a
5010 * wait-for-vblank between disabling the plane and the pipe.
5012 if (HAS_GMCH_DISPLAY(dev_priv
) &&
5013 intel_set_memory_cxsr(dev_priv
, false))
5014 intel_wait_for_vblank(dev_priv
, pipe
);
5017 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
5019 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5020 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5021 struct intel_crtc_state
*pipe_config
=
5022 to_intel_crtc_state(crtc
->base
.state
);
5023 struct drm_plane
*primary
= crtc
->base
.primary
;
5024 struct drm_plane_state
*old_pri_state
=
5025 drm_atomic_get_existing_plane_state(old_state
, primary
);
5027 intel_frontbuffer_flip(to_i915(crtc
->base
.dev
), pipe_config
->fb_bits
);
5029 crtc
->wm
.cxsr_allowed
= true;
5031 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
5032 intel_update_watermarks(crtc
);
5034 if (old_pri_state
) {
5035 struct intel_plane_state
*primary_state
=
5036 to_intel_plane_state(primary
->state
);
5037 struct intel_plane_state
*old_primary_state
=
5038 to_intel_plane_state(old_pri_state
);
5040 intel_fbc_post_update(crtc
);
5042 if (primary_state
->base
.visible
&&
5043 (needs_modeset(&pipe_config
->base
) ||
5044 !old_primary_state
->base
.visible
))
5045 intel_post_enable_primary(&crtc
->base
);
5049 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
)
5051 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5052 struct drm_device
*dev
= crtc
->base
.dev
;
5053 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5054 struct intel_crtc_state
*pipe_config
=
5055 to_intel_crtc_state(crtc
->base
.state
);
5056 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5057 struct drm_plane
*primary
= crtc
->base
.primary
;
5058 struct drm_plane_state
*old_pri_state
=
5059 drm_atomic_get_existing_plane_state(old_state
, primary
);
5060 bool modeset
= needs_modeset(&pipe_config
->base
);
5061 struct intel_atomic_state
*old_intel_state
=
5062 to_intel_atomic_state(old_state
);
5064 if (old_pri_state
) {
5065 struct intel_plane_state
*primary_state
=
5066 to_intel_plane_state(primary
->state
);
5067 struct intel_plane_state
*old_primary_state
=
5068 to_intel_plane_state(old_pri_state
);
5070 intel_fbc_pre_update(crtc
, pipe_config
, primary_state
);
5072 if (old_primary_state
->base
.visible
&&
5073 (modeset
|| !primary_state
->base
.visible
))
5074 intel_pre_disable_primary(&crtc
->base
);
5077 if (pipe_config
->disable_cxsr
&& HAS_GMCH_DISPLAY(dev_priv
)) {
5078 crtc
->wm
.cxsr_allowed
= false;
5081 * Vblank time updates from the shadow to live plane control register
5082 * are blocked if the memory self-refresh mode is active at that
5083 * moment. So to make sure the plane gets truly disabled, disable
5084 * first the self-refresh mode. The self-refresh enable bit in turn
5085 * will be checked/applied by the HW only at the next frame start
5086 * event which is after the vblank start event, so we need to have a
5087 * wait-for-vblank between disabling the plane and the pipe.
5089 if (old_crtc_state
->base
.active
&&
5090 intel_set_memory_cxsr(dev_priv
, false))
5091 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5095 * IVB workaround: must disable low power watermarks for at least
5096 * one frame before enabling scaling. LP watermarks can be re-enabled
5097 * when scaling is disabled.
5099 * WaCxSRDisabledForSpriteScaling:ivb
5101 if (pipe_config
->disable_lp_wm
&& ilk_disable_lp_wm(dev
))
5102 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5105 * If we're doing a modeset, we're done. No need to do any pre-vblank
5106 * watermark programming here.
5108 if (needs_modeset(&pipe_config
->base
))
5112 * For platforms that support atomic watermarks, program the
5113 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5114 * will be the intermediate values that are safe for both pre- and
5115 * post- vblank; when vblank happens, the 'active' values will be set
5116 * to the final 'target' values and we'll do this again to get the
5117 * optimal watermarks. For gen9+ platforms, the values we program here
5118 * will be the final target values which will get automatically latched
5119 * at vblank time; no further programming will be necessary.
5121 * If a platform hasn't been transitioned to atomic watermarks yet,
5122 * we'll continue to update watermarks the old way, if flags tell
5125 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5126 dev_priv
->display
.initial_watermarks(old_intel_state
,
5128 else if (pipe_config
->update_wm_pre
)
5129 intel_update_watermarks(crtc
);
5132 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
5134 struct drm_device
*dev
= crtc
->dev
;
5135 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5136 struct drm_plane
*p
;
5137 int pipe
= intel_crtc
->pipe
;
5139 intel_crtc_dpms_overlay_disable(intel_crtc
);
5141 drm_for_each_plane_mask(p
, dev
, plane_mask
)
5142 to_intel_plane(p
)->disable_plane(p
, crtc
);
5145 * FIXME: Once we grow proper nuclear flip support out of this we need
5146 * to compute the mask of flip planes precisely. For the time being
5147 * consider this a flip to a NULL plane.
5149 intel_frontbuffer_flip(to_i915(dev
), INTEL_FRONTBUFFER_ALL_MASK(pipe
));
5152 static void intel_encoders_pre_pll_enable(struct drm_crtc
*crtc
,
5153 struct intel_crtc_state
*crtc_state
,
5154 struct drm_atomic_state
*old_state
)
5156 struct drm_connector_state
*old_conn_state
;
5157 struct drm_connector
*conn
;
5160 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5161 struct drm_connector_state
*conn_state
= conn
->state
;
5162 struct intel_encoder
*encoder
=
5163 to_intel_encoder(conn_state
->best_encoder
);
5165 if (conn_state
->crtc
!= crtc
)
5168 if (encoder
->pre_pll_enable
)
5169 encoder
->pre_pll_enable(encoder
, crtc_state
, conn_state
);
5173 static void intel_encoders_pre_enable(struct drm_crtc
*crtc
,
5174 struct intel_crtc_state
*crtc_state
,
5175 struct drm_atomic_state
*old_state
)
5177 struct drm_connector_state
*old_conn_state
;
5178 struct drm_connector
*conn
;
5181 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5182 struct drm_connector_state
*conn_state
= conn
->state
;
5183 struct intel_encoder
*encoder
=
5184 to_intel_encoder(conn_state
->best_encoder
);
5186 if (conn_state
->crtc
!= crtc
)
5189 if (encoder
->pre_enable
)
5190 encoder
->pre_enable(encoder
, crtc_state
, conn_state
);
5194 static void intel_encoders_enable(struct drm_crtc
*crtc
,
5195 struct intel_crtc_state
*crtc_state
,
5196 struct drm_atomic_state
*old_state
)
5198 struct drm_connector_state
*old_conn_state
;
5199 struct drm_connector
*conn
;
5202 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5203 struct drm_connector_state
*conn_state
= conn
->state
;
5204 struct intel_encoder
*encoder
=
5205 to_intel_encoder(conn_state
->best_encoder
);
5207 if (conn_state
->crtc
!= crtc
)
5210 encoder
->enable(encoder
, crtc_state
, conn_state
);
5211 intel_opregion_notify_encoder(encoder
, true);
5215 static void intel_encoders_disable(struct drm_crtc
*crtc
,
5216 struct intel_crtc_state
*old_crtc_state
,
5217 struct drm_atomic_state
*old_state
)
5219 struct drm_connector_state
*old_conn_state
;
5220 struct drm_connector
*conn
;
5223 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5224 struct intel_encoder
*encoder
=
5225 to_intel_encoder(old_conn_state
->best_encoder
);
5227 if (old_conn_state
->crtc
!= crtc
)
5230 intel_opregion_notify_encoder(encoder
, false);
5231 encoder
->disable(encoder
, old_crtc_state
, old_conn_state
);
5235 static void intel_encoders_post_disable(struct drm_crtc
*crtc
,
5236 struct intel_crtc_state
*old_crtc_state
,
5237 struct drm_atomic_state
*old_state
)
5239 struct drm_connector_state
*old_conn_state
;
5240 struct drm_connector
*conn
;
5243 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5244 struct intel_encoder
*encoder
=
5245 to_intel_encoder(old_conn_state
->best_encoder
);
5247 if (old_conn_state
->crtc
!= crtc
)
5250 if (encoder
->post_disable
)
5251 encoder
->post_disable(encoder
, old_crtc_state
, old_conn_state
);
5255 static void intel_encoders_post_pll_disable(struct drm_crtc
*crtc
,
5256 struct intel_crtc_state
*old_crtc_state
,
5257 struct drm_atomic_state
*old_state
)
5259 struct drm_connector_state
*old_conn_state
;
5260 struct drm_connector
*conn
;
5263 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5264 struct intel_encoder
*encoder
=
5265 to_intel_encoder(old_conn_state
->best_encoder
);
5267 if (old_conn_state
->crtc
!= crtc
)
5270 if (encoder
->post_pll_disable
)
5271 encoder
->post_pll_disable(encoder
, old_crtc_state
, old_conn_state
);
5275 static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config
,
5276 struct drm_atomic_state
*old_state
)
5278 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5279 struct drm_device
*dev
= crtc
->dev
;
5280 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5281 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5282 int pipe
= intel_crtc
->pipe
;
5283 struct intel_atomic_state
*old_intel_state
=
5284 to_intel_atomic_state(old_state
);
5286 if (WARN_ON(intel_crtc
->active
))
5290 * Sometimes spurious CPU pipe underruns happen during FDI
5291 * training, at least with VGA+HDMI cloning. Suppress them.
5293 * On ILK we get an occasional spurious CPU pipe underruns
5294 * between eDP port A enable and vdd enable. Also PCH port
5295 * enable seems to result in the occasional CPU pipe underrun.
5297 * Spurious PCH underruns also occur during PCH enabling.
5299 if (intel_crtc
->config
->has_pch_encoder
|| IS_GEN5(dev_priv
))
5300 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5301 if (intel_crtc
->config
->has_pch_encoder
)
5302 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5304 if (intel_crtc
->config
->has_pch_encoder
)
5305 intel_prepare_shared_dpll(intel_crtc
);
5307 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5308 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5310 intel_set_pipe_timings(intel_crtc
);
5311 intel_set_pipe_src_size(intel_crtc
);
5313 if (intel_crtc
->config
->has_pch_encoder
) {
5314 intel_cpu_transcoder_set_m_n(intel_crtc
,
5315 &intel_crtc
->config
->fdi_m_n
, NULL
);
5318 ironlake_set_pipeconf(crtc
);
5320 intel_crtc
->active
= true;
5322 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5324 if (intel_crtc
->config
->has_pch_encoder
) {
5325 /* Note: FDI PLL enabling _must_ be done before we enable the
5326 * cpu pipes, hence this is separate from all the other fdi/pch
5328 ironlake_fdi_pll_enable(intel_crtc
);
5330 assert_fdi_tx_disabled(dev_priv
, pipe
);
5331 assert_fdi_rx_disabled(dev_priv
, pipe
);
5334 ironlake_pfit_enable(intel_crtc
);
5337 * On ILK+ LUT must be loaded before the pipe is running but with
5340 intel_color_load_luts(&pipe_config
->base
);
5342 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5343 dev_priv
->display
.initial_watermarks(old_intel_state
, intel_crtc
->config
);
5344 intel_enable_pipe(intel_crtc
);
5346 if (intel_crtc
->config
->has_pch_encoder
)
5347 ironlake_pch_enable(crtc
);
5349 assert_vblank_disabled(crtc
);
5350 drm_crtc_vblank_on(crtc
);
5352 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5354 if (HAS_PCH_CPT(dev_priv
))
5355 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
5357 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5358 if (intel_crtc
->config
->has_pch_encoder
)
5359 intel_wait_for_vblank(dev_priv
, pipe
);
5360 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5361 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5364 /* IPS only exists on ULT machines and is tied to pipe A. */
5365 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
5367 return HAS_IPS(to_i915(crtc
->base
.dev
)) && crtc
->pipe
== PIPE_A
;
5370 static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config
,
5371 struct drm_atomic_state
*old_state
)
5373 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5374 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5375 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5376 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
5377 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5378 struct intel_atomic_state
*old_intel_state
=
5379 to_intel_atomic_state(old_state
);
5381 if (WARN_ON(intel_crtc
->active
))
5384 if (intel_crtc
->config
->has_pch_encoder
)
5385 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5388 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
5390 if (intel_crtc
->config
->shared_dpll
)
5391 intel_enable_shared_dpll(intel_crtc
);
5393 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5394 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5396 if (!transcoder_is_dsi(cpu_transcoder
))
5397 intel_set_pipe_timings(intel_crtc
);
5399 intel_set_pipe_src_size(intel_crtc
);
5401 if (cpu_transcoder
!= TRANSCODER_EDP
&&
5402 !transcoder_is_dsi(cpu_transcoder
)) {
5403 I915_WRITE(PIPE_MULT(cpu_transcoder
),
5404 intel_crtc
->config
->pixel_multiplier
- 1);
5407 if (intel_crtc
->config
->has_pch_encoder
) {
5408 intel_cpu_transcoder_set_m_n(intel_crtc
,
5409 &intel_crtc
->config
->fdi_m_n
, NULL
);
5412 if (!transcoder_is_dsi(cpu_transcoder
))
5413 haswell_set_pipeconf(crtc
);
5415 haswell_set_pipemisc(crtc
);
5417 intel_color_set_csc(&pipe_config
->base
);
5419 intel_crtc
->active
= true;
5421 if (intel_crtc
->config
->has_pch_encoder
)
5422 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5424 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5426 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5428 if (intel_crtc
->config
->has_pch_encoder
)
5429 dev_priv
->display
.fdi_link_train(crtc
);
5431 if (!transcoder_is_dsi(cpu_transcoder
))
5432 intel_ddi_enable_pipe_clock(intel_crtc
);
5434 if (INTEL_GEN(dev_priv
) >= 9)
5435 skylake_pfit_enable(intel_crtc
);
5437 ironlake_pfit_enable(intel_crtc
);
5440 * On ILK+ LUT must be loaded before the pipe is running but with
5443 intel_color_load_luts(&pipe_config
->base
);
5445 intel_ddi_set_pipe_settings(crtc
);
5446 if (!transcoder_is_dsi(cpu_transcoder
))
5447 intel_ddi_enable_transcoder_func(crtc
);
5449 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5450 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
5452 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5453 if (!transcoder_is_dsi(cpu_transcoder
))
5454 intel_enable_pipe(intel_crtc
);
5456 if (intel_crtc
->config
->has_pch_encoder
)
5457 lpt_pch_enable(crtc
);
5459 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DP_MST
))
5460 intel_ddi_set_vc_payload_alloc(crtc
, true);
5462 assert_vblank_disabled(crtc
);
5463 drm_crtc_vblank_on(crtc
);
5465 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5467 if (intel_crtc
->config
->has_pch_encoder
) {
5468 intel_wait_for_vblank(dev_priv
, pipe
);
5469 intel_wait_for_vblank(dev_priv
, pipe
);
5470 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5471 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5475 /* If we change the relative order between pipe/planes enabling, we need
5476 * to change the workaround. */
5477 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
5478 if (IS_HASWELL(dev_priv
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
5479 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
5480 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
5484 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
5486 struct drm_device
*dev
= crtc
->base
.dev
;
5487 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5488 int pipe
= crtc
->pipe
;
5490 /* To avoid upsetting the power well on haswell only disable the pfit if
5491 * it's in use. The hw state code will make sure we get this right. */
5492 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
5493 I915_WRITE(PF_CTL(pipe
), 0);
5494 I915_WRITE(PF_WIN_POS(pipe
), 0);
5495 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5499 static void ironlake_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
5500 struct drm_atomic_state
*old_state
)
5502 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
5503 struct drm_device
*dev
= crtc
->dev
;
5504 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5505 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5506 int pipe
= intel_crtc
->pipe
;
5509 * Sometimes spurious CPU pipe underruns happen when the
5510 * pipe is already disabled, but FDI RX/TX is still enabled.
5511 * Happens at least with VGA+HDMI cloning. Suppress them.
5513 if (intel_crtc
->config
->has_pch_encoder
) {
5514 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5515 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5518 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
5520 drm_crtc_vblank_off(crtc
);
5521 assert_vblank_disabled(crtc
);
5523 intel_disable_pipe(intel_crtc
);
5525 ironlake_pfit_disable(intel_crtc
, false);
5527 if (intel_crtc
->config
->has_pch_encoder
)
5528 ironlake_fdi_disable(crtc
);
5530 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
5532 if (intel_crtc
->config
->has_pch_encoder
) {
5533 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5535 if (HAS_PCH_CPT(dev_priv
)) {
5539 /* disable TRANS_DP_CTL */
5540 reg
= TRANS_DP_CTL(pipe
);
5541 temp
= I915_READ(reg
);
5542 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5543 TRANS_DP_PORT_SEL_MASK
);
5544 temp
|= TRANS_DP_PORT_SEL_NONE
;
5545 I915_WRITE(reg
, temp
);
5547 /* disable DPLL_SEL */
5548 temp
= I915_READ(PCH_DPLL_SEL
);
5549 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5550 I915_WRITE(PCH_DPLL_SEL
, temp
);
5553 ironlake_fdi_pll_disable(intel_crtc
);
5556 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5557 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5560 static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
5561 struct drm_atomic_state
*old_state
)
5563 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
5564 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5565 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5566 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5568 if (intel_crtc
->config
->has_pch_encoder
)
5569 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5572 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
5574 drm_crtc_vblank_off(crtc
);
5575 assert_vblank_disabled(crtc
);
5577 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5578 if (!transcoder_is_dsi(cpu_transcoder
))
5579 intel_disable_pipe(intel_crtc
);
5581 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DP_MST
))
5582 intel_ddi_set_vc_payload_alloc(crtc
, false);
5584 if (!transcoder_is_dsi(cpu_transcoder
))
5585 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5587 if (INTEL_GEN(dev_priv
) >= 9)
5588 skylake_scaler_disable(intel_crtc
);
5590 ironlake_pfit_disable(intel_crtc
, false);
5592 if (!transcoder_is_dsi(cpu_transcoder
))
5593 intel_ddi_disable_pipe_clock(intel_crtc
);
5595 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
5597 if (old_crtc_state
->has_pch_encoder
)
5598 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5602 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5604 struct drm_device
*dev
= crtc
->base
.dev
;
5605 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5606 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5608 if (!pipe_config
->gmch_pfit
.control
)
5612 * The panel fitter should only be adjusted whilst the pipe is disabled,
5613 * according to register description and PRM.
5615 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5616 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5618 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5619 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5621 /* Border color in case we don't scale up to the full screen. Black by
5622 * default, change to something else for debugging. */
5623 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5626 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5630 return POWER_DOMAIN_PORT_DDI_A_LANES
;
5632 return POWER_DOMAIN_PORT_DDI_B_LANES
;
5634 return POWER_DOMAIN_PORT_DDI_C_LANES
;
5636 return POWER_DOMAIN_PORT_DDI_D_LANES
;
5638 return POWER_DOMAIN_PORT_DDI_E_LANES
;
5641 return POWER_DOMAIN_PORT_OTHER
;
5645 static enum intel_display_power_domain
port_to_aux_power_domain(enum port port
)
5649 return POWER_DOMAIN_AUX_A
;
5651 return POWER_DOMAIN_AUX_B
;
5653 return POWER_DOMAIN_AUX_C
;
5655 return POWER_DOMAIN_AUX_D
;
5657 /* FIXME: Check VBT for actual wiring of PORT E */
5658 return POWER_DOMAIN_AUX_D
;
5661 return POWER_DOMAIN_AUX_A
;
5665 enum intel_display_power_domain
5666 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5668 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
5669 struct intel_digital_port
*intel_dig_port
;
5671 switch (intel_encoder
->type
) {
5672 case INTEL_OUTPUT_UNKNOWN
:
5673 /* Only DDI platforms should ever use this output type */
5674 WARN_ON_ONCE(!HAS_DDI(dev_priv
));
5675 case INTEL_OUTPUT_DP
:
5676 case INTEL_OUTPUT_HDMI
:
5677 case INTEL_OUTPUT_EDP
:
5678 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5679 return port_to_power_domain(intel_dig_port
->port
);
5680 case INTEL_OUTPUT_DP_MST
:
5681 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5682 return port_to_power_domain(intel_dig_port
->port
);
5683 case INTEL_OUTPUT_ANALOG
:
5684 return POWER_DOMAIN_PORT_CRT
;
5685 case INTEL_OUTPUT_DSI
:
5686 return POWER_DOMAIN_PORT_DSI
;
5688 return POWER_DOMAIN_PORT_OTHER
;
5692 enum intel_display_power_domain
5693 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
)
5695 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
5696 struct intel_digital_port
*intel_dig_port
;
5698 switch (intel_encoder
->type
) {
5699 case INTEL_OUTPUT_UNKNOWN
:
5700 case INTEL_OUTPUT_HDMI
:
5702 * Only DDI platforms should ever use these output types.
5703 * We can get here after the HDMI detect code has already set
5704 * the type of the shared encoder. Since we can't be sure
5705 * what's the status of the given connectors, play safe and
5706 * run the DP detection too.
5708 WARN_ON_ONCE(!HAS_DDI(dev_priv
));
5709 case INTEL_OUTPUT_DP
:
5710 case INTEL_OUTPUT_EDP
:
5711 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5712 return port_to_aux_power_domain(intel_dig_port
->port
);
5713 case INTEL_OUTPUT_DP_MST
:
5714 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5715 return port_to_aux_power_domain(intel_dig_port
->port
);
5717 MISSING_CASE(intel_encoder
->type
);
5718 return POWER_DOMAIN_AUX_A
;
5722 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
,
5723 struct intel_crtc_state
*crtc_state
)
5725 struct drm_device
*dev
= crtc
->dev
;
5726 struct drm_encoder
*encoder
;
5727 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5728 enum pipe pipe
= intel_crtc
->pipe
;
5730 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
5732 if (!crtc_state
->base
.active
)
5735 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5736 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5737 if (crtc_state
->pch_pfit
.enabled
||
5738 crtc_state
->pch_pfit
.force_thru
)
5739 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5741 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
5742 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5744 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5747 if (crtc_state
->shared_dpll
)
5748 mask
|= BIT(POWER_DOMAIN_PLLS
);
5753 static unsigned long
5754 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
5755 struct intel_crtc_state
*crtc_state
)
5757 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5758 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5759 enum intel_display_power_domain domain
;
5760 unsigned long domains
, new_domains
, old_domains
;
5762 old_domains
= intel_crtc
->enabled_power_domains
;
5763 intel_crtc
->enabled_power_domains
= new_domains
=
5764 get_crtc_power_domains(crtc
, crtc_state
);
5766 domains
= new_domains
& ~old_domains
;
5768 for_each_power_domain(domain
, domains
)
5769 intel_display_power_get(dev_priv
, domain
);
5771 return old_domains
& ~new_domains
;
5774 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5775 unsigned long domains
)
5777 enum intel_display_power_domain domain
;
5779 for_each_power_domain(domain
, domains
)
5780 intel_display_power_put(dev_priv
, domain
);
5783 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
5785 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
5787 if (IS_GEMINILAKE(dev_priv
))
5788 return 2 * max_cdclk_freq
;
5789 else if (INTEL_INFO(dev_priv
)->gen
>= 9 ||
5790 IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5791 return max_cdclk_freq
;
5792 else if (IS_CHERRYVIEW(dev_priv
))
5793 return max_cdclk_freq
*95/100;
5794 else if (INTEL_INFO(dev_priv
)->gen
< 4)
5795 return 2*max_cdclk_freq
*90/100;
5797 return max_cdclk_freq
*90/100;
5800 static int skl_calc_cdclk(int max_pixclk
, int vco
);
5802 static void intel_update_max_cdclk(struct drm_i915_private
*dev_priv
)
5804 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5805 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5808 vco
= dev_priv
->skl_preferred_vco_freq
;
5809 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
5812 * Use the lower (vco 8640) cdclk values as a
5813 * first guess. skl_calc_cdclk() will correct it
5814 * if the preferred vco is 8100 instead.
5816 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5818 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5820 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5825 dev_priv
->max_cdclk_freq
= skl_calc_cdclk(max_cdclk
, vco
);
5826 } else if (IS_GEMINILAKE(dev_priv
)) {
5827 dev_priv
->max_cdclk_freq
= 316800;
5828 } else if (IS_BROXTON(dev_priv
)) {
5829 dev_priv
->max_cdclk_freq
= 624000;
5830 } else if (IS_BROADWELL(dev_priv
)) {
5832 * FIXME with extra cooling we can allow
5833 * 540 MHz for ULX and 675 Mhz for ULT.
5834 * How can we know if extra cooling is
5835 * available? PCI ID, VTB, something else?
5837 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5838 dev_priv
->max_cdclk_freq
= 450000;
5839 else if (IS_BDW_ULX(dev_priv
))
5840 dev_priv
->max_cdclk_freq
= 450000;
5841 else if (IS_BDW_ULT(dev_priv
))
5842 dev_priv
->max_cdclk_freq
= 540000;
5844 dev_priv
->max_cdclk_freq
= 675000;
5845 } else if (IS_CHERRYVIEW(dev_priv
)) {
5846 dev_priv
->max_cdclk_freq
= 320000;
5847 } else if (IS_VALLEYVIEW(dev_priv
)) {
5848 dev_priv
->max_cdclk_freq
= 400000;
5850 /* otherwise assume cdclk is fixed */
5851 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5854 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
5856 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5857 dev_priv
->max_cdclk_freq
);
5859 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5860 dev_priv
->max_dotclk_freq
);
5863 static void intel_update_cdclk(struct drm_i915_private
*dev_priv
)
5865 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev_priv
);
5867 if (INTEL_GEN(dev_priv
) >= 9)
5868 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5869 dev_priv
->cdclk_freq
, dev_priv
->cdclk_pll
.vco
,
5870 dev_priv
->cdclk_pll
.ref
);
5872 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5873 dev_priv
->cdclk_freq
);
5876 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5877 * Programmng [sic] note: bit[9:2] should be programmed to the number
5878 * of cdclk that generates 4MHz reference clock freq which is used to
5879 * generate GMBus clock. This will vary with the cdclk freq.
5881 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5882 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5885 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5886 static int skl_cdclk_decimal(int cdclk
)
5888 return DIV_ROUND_CLOSEST(cdclk
- 1000, 500);
5891 static int bxt_de_pll_vco(struct drm_i915_private
*dev_priv
, int cdclk
)
5895 if (cdclk
== dev_priv
->cdclk_pll
.ref
)
5900 MISSING_CASE(cdclk
);
5912 return dev_priv
->cdclk_pll
.ref
* ratio
;
5915 static int glk_de_pll_vco(struct drm_i915_private
*dev_priv
, int cdclk
)
5919 if (cdclk
== dev_priv
->cdclk_pll
.ref
)
5924 MISSING_CASE(cdclk
);
5932 return dev_priv
->cdclk_pll
.ref
* ratio
;
5935 static void bxt_de_pll_disable(struct drm_i915_private
*dev_priv
)
5937 I915_WRITE(BXT_DE_PLL_ENABLE
, 0);
5940 if (intel_wait_for_register(dev_priv
,
5941 BXT_DE_PLL_ENABLE
, BXT_DE_PLL_LOCK
, 0,
5943 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5945 dev_priv
->cdclk_pll
.vco
= 0;
5948 static void bxt_de_pll_enable(struct drm_i915_private
*dev_priv
, int vco
)
5950 int ratio
= DIV_ROUND_CLOSEST(vco
, dev_priv
->cdclk_pll
.ref
);
5953 val
= I915_READ(BXT_DE_PLL_CTL
);
5954 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5955 val
|= BXT_DE_PLL_RATIO(ratio
);
5956 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5958 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5961 if (intel_wait_for_register(dev_priv
,
5966 DRM_ERROR("timeout waiting for DE PLL lock\n");
5968 dev_priv
->cdclk_pll
.vco
= vco
;
5971 static void bxt_set_cdclk(struct drm_i915_private
*dev_priv
, int cdclk
)
5976 if (IS_GEMINILAKE(dev_priv
))
5977 vco
= glk_de_pll_vco(dev_priv
, cdclk
);
5979 vco
= bxt_de_pll_vco(dev_priv
, cdclk
);
5981 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk
, vco
);
5983 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5984 switch (DIV_ROUND_CLOSEST(vco
, cdclk
)) {
5986 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5989 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5992 WARN(IS_GEMINILAKE(dev_priv
), "Unsupported divider\n");
5993 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5996 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5999 WARN_ON(cdclk
!= dev_priv
->cdclk_pll
.ref
);
6002 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
6006 /* Inform power controller of upcoming frequency change */
6007 mutex_lock(&dev_priv
->rps
.hw_lock
);
6008 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
6010 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6013 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6018 if (dev_priv
->cdclk_pll
.vco
!= 0 &&
6019 dev_priv
->cdclk_pll
.vco
!= vco
)
6020 bxt_de_pll_disable(dev_priv
);
6022 if (dev_priv
->cdclk_pll
.vco
!= vco
)
6023 bxt_de_pll_enable(dev_priv
, vco
);
6025 val
= divider
| skl_cdclk_decimal(cdclk
);
6027 * FIXME if only the cd2x divider needs changing, it could be done
6028 * without shutting off the pipe (if only one pipe is active).
6030 val
|= BXT_CDCLK_CD2X_PIPE_NONE
;
6032 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6035 if (cdclk
>= 500000)
6036 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
6037 I915_WRITE(CDCLK_CTL
, val
);
6039 mutex_lock(&dev_priv
->rps
.hw_lock
);
6040 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
6041 DIV_ROUND_UP(cdclk
, 25000));
6042 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6045 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6050 intel_update_cdclk(dev_priv
);
6053 static void bxt_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
6055 u32 cdctl
, expected
;
6057 intel_update_cdclk(dev_priv
);
6059 if (dev_priv
->cdclk_pll
.vco
== 0 ||
6060 dev_priv
->cdclk_freq
== dev_priv
->cdclk_pll
.ref
)
6063 /* DPLL okay; verify the cdclock
6065 * Some BIOS versions leave an incorrect decimal frequency value and
6066 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6067 * so sanitize this register.
6069 cdctl
= I915_READ(CDCLK_CTL
);
6071 * Let's ignore the pipe field, since BIOS could have configured the
6072 * dividers both synching to an active pipe, or asynchronously
6075 cdctl
&= ~BXT_CDCLK_CD2X_PIPE_NONE
;
6077 expected
= (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) |
6078 skl_cdclk_decimal(dev_priv
->cdclk_freq
);
6080 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6083 if (dev_priv
->cdclk_freq
>= 500000)
6084 expected
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
6086 if (cdctl
== expected
)
6087 /* All well; nothing to sanitize */
6091 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6093 /* force cdclk programming */
6094 dev_priv
->cdclk_freq
= 0;
6096 /* force full PLL disable + enable */
6097 dev_priv
->cdclk_pll
.vco
= -1;
6100 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
)
6104 bxt_sanitize_cdclk(dev_priv
);
6106 if (dev_priv
->cdclk_freq
!= 0 && dev_priv
->cdclk_pll
.vco
!= 0)
6111 * - The initial CDCLK needs to be read from VBT.
6112 * Need to make this change after VBT has changes for BXT.
6114 if (IS_GEMINILAKE(dev_priv
))
6115 cdclk
= glk_calc_cdclk(0);
6117 cdclk
= bxt_calc_cdclk(0);
6119 bxt_set_cdclk(dev_priv
, cdclk
);
6122 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
)
6124 bxt_set_cdclk(dev_priv
, dev_priv
->cdclk_pll
.ref
);
6127 static int skl_calc_cdclk(int max_pixclk
, int vco
)
6129 if (vco
== 8640000) {
6130 if (max_pixclk
> 540000)
6132 else if (max_pixclk
> 432000)
6134 else if (max_pixclk
> 308571)
6139 if (max_pixclk
> 540000)
6141 else if (max_pixclk
> 450000)
6143 else if (max_pixclk
> 337500)
6151 skl_dpll0_update(struct drm_i915_private
*dev_priv
)
6155 dev_priv
->cdclk_pll
.ref
= 24000;
6156 dev_priv
->cdclk_pll
.vco
= 0;
6158 val
= I915_READ(LCPLL1_CTL
);
6159 if ((val
& LCPLL_PLL_ENABLE
) == 0)
6162 if (WARN_ON((val
& LCPLL_PLL_LOCK
) == 0))
6165 val
= I915_READ(DPLL_CTRL1
);
6167 if (WARN_ON((val
& (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) |
6168 DPLL_CTRL1_SSC(SKL_DPLL0
) |
6169 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
))) !=
6170 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
)))
6173 switch (val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) {
6174 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, SKL_DPLL0
):
6175 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, SKL_DPLL0
):
6176 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
, SKL_DPLL0
):
6177 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, SKL_DPLL0
):
6178 dev_priv
->cdclk_pll
.vco
= 8100000;
6180 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
, SKL_DPLL0
):
6181 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
, SKL_DPLL0
):
6182 dev_priv
->cdclk_pll
.vco
= 8640000;
6185 MISSING_CASE(val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
6190 void skl_set_preferred_cdclk_vco(struct drm_i915_private
*dev_priv
, int vco
)
6192 bool changed
= dev_priv
->skl_preferred_vco_freq
!= vco
;
6194 dev_priv
->skl_preferred_vco_freq
= vco
;
6197 intel_update_max_cdclk(dev_priv
);
6201 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, int vco
)
6203 int min_cdclk
= skl_calc_cdclk(0, vco
);
6206 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
6208 /* select the minimum CDCLK before enabling DPLL 0 */
6209 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_cdclk
);
6210 I915_WRITE(CDCLK_CTL
, val
);
6211 POSTING_READ(CDCLK_CTL
);
6214 * We always enable DPLL0 with the lowest link rate possible, but still
6215 * taking into account the VCO required to operate the eDP panel at the
6216 * desired frequency. The usual DP link rates operate with a VCO of
6217 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6218 * The modeset code is responsible for the selection of the exact link
6219 * rate later on, with the constraint of choosing a frequency that
6222 val
= I915_READ(DPLL_CTRL1
);
6224 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
6225 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
6226 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
6228 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
6231 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
6234 I915_WRITE(DPLL_CTRL1
, val
);
6235 POSTING_READ(DPLL_CTRL1
);
6237 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
6239 if (intel_wait_for_register(dev_priv
,
6240 LCPLL1_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
6242 DRM_ERROR("DPLL0 not locked\n");
6244 dev_priv
->cdclk_pll
.vco
= vco
;
6246 /* We'll want to keep using the current vco from now on. */
6247 skl_set_preferred_cdclk_vco(dev_priv
, vco
);
6251 skl_dpll0_disable(struct drm_i915_private
*dev_priv
)
6253 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
6254 if (intel_wait_for_register(dev_priv
,
6255 LCPLL1_CTL
, LCPLL_PLL_LOCK
, 0,
6257 DRM_ERROR("Couldn't disable DPLL0\n");
6259 dev_priv
->cdclk_pll
.vco
= 0;
6262 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, int cdclk
, int vco
)
6264 u32 freq_select
, pcu_ack
;
6267 WARN_ON((cdclk
== 24000) != (vco
== 0));
6269 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk
, vco
);
6271 mutex_lock(&dev_priv
->rps
.hw_lock
);
6272 ret
= skl_pcode_request(dev_priv
, SKL_PCODE_CDCLK_CONTROL
,
6273 SKL_CDCLK_PREPARE_FOR_CHANGE
,
6274 SKL_CDCLK_READY_FOR_CHANGE
,
6275 SKL_CDCLK_READY_FOR_CHANGE
, 3);
6276 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6278 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6287 freq_select
= CDCLK_FREQ_450_432
;
6291 freq_select
= CDCLK_FREQ_540
;
6297 freq_select
= CDCLK_FREQ_337_308
;
6302 freq_select
= CDCLK_FREQ_675_617
;
6307 if (dev_priv
->cdclk_pll
.vco
!= 0 &&
6308 dev_priv
->cdclk_pll
.vco
!= vco
)
6309 skl_dpll0_disable(dev_priv
);
6311 if (dev_priv
->cdclk_pll
.vco
!= vco
)
6312 skl_dpll0_enable(dev_priv
, vco
);
6314 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(cdclk
));
6315 POSTING_READ(CDCLK_CTL
);
6317 /* inform PCU of the change */
6318 mutex_lock(&dev_priv
->rps
.hw_lock
);
6319 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
6320 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6322 intel_update_cdclk(dev_priv
);
6325 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
);
6327 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
6329 skl_set_cdclk(dev_priv
, dev_priv
->cdclk_pll
.ref
, 0);
6332 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
6336 skl_sanitize_cdclk(dev_priv
);
6338 if (dev_priv
->cdclk_freq
!= 0 && dev_priv
->cdclk_pll
.vco
!= 0) {
6340 * Use the current vco as our initial
6341 * guess as to what the preferred vco is.
6343 if (dev_priv
->skl_preferred_vco_freq
== 0)
6344 skl_set_preferred_cdclk_vco(dev_priv
,
6345 dev_priv
->cdclk_pll
.vco
);
6349 vco
= dev_priv
->skl_preferred_vco_freq
;
6352 cdclk
= skl_calc_cdclk(0, vco
);
6354 skl_set_cdclk(dev_priv
, cdclk
, vco
);
6357 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
6359 uint32_t cdctl
, expected
;
6362 * check if the pre-os intialized the display
6363 * There is SWF18 scratchpad register defined which is set by the
6364 * pre-os which can be used by the OS drivers to check the status
6366 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6369 intel_update_cdclk(dev_priv
);
6370 /* Is PLL enabled and locked ? */
6371 if (dev_priv
->cdclk_pll
.vco
== 0 ||
6372 dev_priv
->cdclk_freq
== dev_priv
->cdclk_pll
.ref
)
6375 /* DPLL okay; verify the cdclock
6377 * Noticed in some instances that the freq selection is correct but
6378 * decimal part is programmed wrong from BIOS where pre-os does not
6379 * enable display. Verify the same as well.
6381 cdctl
= I915_READ(CDCLK_CTL
);
6382 expected
= (cdctl
& CDCLK_FREQ_SEL_MASK
) |
6383 skl_cdclk_decimal(dev_priv
->cdclk_freq
);
6384 if (cdctl
== expected
)
6385 /* All well; nothing to sanitize */
6389 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6391 /* force cdclk programming */
6392 dev_priv
->cdclk_freq
= 0;
6393 /* force full PLL disable + enable */
6394 dev_priv
->cdclk_pll
.vco
= -1;
6397 /* Adjust CDclk dividers to allow high res or save power if possible */
6398 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
6400 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6403 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev_priv
)
6404 != dev_priv
->cdclk_freq
);
6406 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
6408 else if (cdclk
== 266667)
6413 mutex_lock(&dev_priv
->rps
.hw_lock
);
6414 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
6415 val
&= ~DSPFREQGUAR_MASK
;
6416 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
6417 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
6418 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
6419 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
6421 DRM_ERROR("timed out waiting for CDclk change\n");
6423 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6425 mutex_lock(&dev_priv
->sb_lock
);
6427 if (cdclk
== 400000) {
6430 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
6432 /* adjust cdclk divider */
6433 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6434 val
&= ~CCK_FREQUENCY_VALUES
;
6436 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
6438 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
6439 CCK_FREQUENCY_STATUS
) == (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
6441 DRM_ERROR("timed out waiting for CDclk change\n");
6444 /* adjust self-refresh exit latency value */
6445 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
6449 * For high bandwidth configs, we set a higher latency in the bunit
6450 * so that the core display fetch happens in time to avoid underruns.
6452 if (cdclk
== 400000)
6453 val
|= 4500 / 250; /* 4.5 usec */
6455 val
|= 3000 / 250; /* 3.0 usec */
6456 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
6458 mutex_unlock(&dev_priv
->sb_lock
);
6460 intel_update_cdclk(dev_priv
);
6463 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
6465 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6468 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev_priv
)
6469 != dev_priv
->cdclk_freq
);
6478 MISSING_CASE(cdclk
);
6483 * Specs are full of misinformation, but testing on actual
6484 * hardware has shown that we just need to write the desired
6485 * CCK divider into the Punit register.
6487 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
6489 mutex_lock(&dev_priv
->rps
.hw_lock
);
6490 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
6491 val
&= ~DSPFREQGUAR_MASK_CHV
;
6492 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
6493 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
6494 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
6495 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
6497 DRM_ERROR("timed out waiting for CDclk change\n");
6499 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6501 intel_update_cdclk(dev_priv
);
6504 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
6507 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
6508 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
6511 * Really only a few cases to deal with, as only 4 CDclks are supported:
6514 * 320/333MHz (depends on HPLL freq)
6516 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6517 * of the lower bin and adjust if needed.
6519 * We seem to get an unstable or solid color picture at 200MHz.
6520 * Not sure what's wrong. For now use 200MHz only when all pipes
6523 if (!IS_CHERRYVIEW(dev_priv
) &&
6524 max_pixclk
> freq_320
*limit
/100)
6526 else if (max_pixclk
> 266667*limit
/100)
6528 else if (max_pixclk
> 0)
6534 static int glk_calc_cdclk(int max_pixclk
)
6536 if (max_pixclk
> 2 * 158400)
6538 else if (max_pixclk
> 2 * 79200)
6544 static int bxt_calc_cdclk(int max_pixclk
)
6546 if (max_pixclk
> 576000)
6548 else if (max_pixclk
> 384000)
6550 else if (max_pixclk
> 288000)
6552 else if (max_pixclk
> 144000)
6558 /* Compute the max pixel clock for new configuration. */
6559 static int intel_mode_max_pixclk(struct drm_device
*dev
,
6560 struct drm_atomic_state
*state
)
6562 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
6563 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6564 struct drm_crtc
*crtc
;
6565 struct drm_crtc_state
*crtc_state
;
6566 unsigned max_pixclk
= 0, i
;
6569 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
6570 sizeof(intel_state
->min_pixclk
));
6572 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
6575 if (crtc_state
->enable
)
6576 pixclk
= crtc_state
->adjusted_mode
.crtc_clock
;
6578 intel_state
->min_pixclk
[i
] = pixclk
;
6581 for_each_pipe(dev_priv
, pipe
)
6582 max_pixclk
= max(intel_state
->min_pixclk
[pipe
], max_pixclk
);
6587 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6589 struct drm_device
*dev
= state
->dev
;
6590 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6591 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
6592 struct intel_atomic_state
*intel_state
=
6593 to_intel_atomic_state(state
);
6595 intel_state
->cdclk
= intel_state
->dev_cdclk
=
6596 valleyview_calc_cdclk(dev_priv
, max_pixclk
);
6598 if (!intel_state
->active_crtcs
)
6599 intel_state
->dev_cdclk
= valleyview_calc_cdclk(dev_priv
, 0);
6604 static int bxt_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6606 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
6607 int max_pixclk
= ilk_max_pixel_rate(state
);
6608 struct intel_atomic_state
*intel_state
=
6609 to_intel_atomic_state(state
);
6612 if (IS_GEMINILAKE(dev_priv
))
6613 cdclk
= glk_calc_cdclk(max_pixclk
);
6615 cdclk
= bxt_calc_cdclk(max_pixclk
);
6617 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
6619 if (!intel_state
->active_crtcs
) {
6620 if (IS_GEMINILAKE(dev_priv
))
6621 cdclk
= glk_calc_cdclk(0);
6623 cdclk
= bxt_calc_cdclk(0);
6625 intel_state
->dev_cdclk
= cdclk
;
6631 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
6633 unsigned int credits
, default_credits
;
6635 if (IS_CHERRYVIEW(dev_priv
))
6636 default_credits
= PFI_CREDIT(12);
6638 default_credits
= PFI_CREDIT(8);
6640 if (dev_priv
->cdclk_freq
>= dev_priv
->czclk_freq
) {
6641 /* CHV suggested value is 31 or 63 */
6642 if (IS_CHERRYVIEW(dev_priv
))
6643 credits
= PFI_CREDIT_63
;
6645 credits
= PFI_CREDIT(15);
6647 credits
= default_credits
;
6651 * WA - write default credits before re-programming
6652 * FIXME: should we also set the resend bit here?
6654 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6657 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6658 credits
| PFI_CREDIT_RESEND
);
6661 * FIXME is this guaranteed to clear
6662 * immediately or should we poll for it?
6664 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6667 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
6669 struct drm_device
*dev
= old_state
->dev
;
6670 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6671 struct intel_atomic_state
*old_intel_state
=
6672 to_intel_atomic_state(old_state
);
6673 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
6676 * FIXME: We can end up here with all power domains off, yet
6677 * with a CDCLK frequency other than the minimum. To account
6678 * for this take the PIPE-A power domain, which covers the HW
6679 * blocks needed for the following programming. This can be
6680 * removed once it's guaranteed that we get here either with
6681 * the minimum CDCLK set, or the required power domains
6684 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6686 if (IS_CHERRYVIEW(dev_priv
))
6687 cherryview_set_cdclk(dev
, req_cdclk
);
6689 valleyview_set_cdclk(dev
, req_cdclk
);
6691 vlv_program_pfi_credits(dev_priv
);
6693 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6696 static void valleyview_crtc_enable(struct intel_crtc_state
*pipe_config
,
6697 struct drm_atomic_state
*old_state
)
6699 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6700 struct drm_device
*dev
= crtc
->dev
;
6701 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6702 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6703 int pipe
= intel_crtc
->pipe
;
6705 if (WARN_ON(intel_crtc
->active
))
6708 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
6709 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6711 intel_set_pipe_timings(intel_crtc
);
6712 intel_set_pipe_src_size(intel_crtc
);
6714 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
6715 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6717 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6718 I915_WRITE(CHV_CANVAS(pipe
), 0);
6721 i9xx_set_pipeconf(intel_crtc
);
6723 intel_crtc
->active
= true;
6725 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6727 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
6729 if (IS_CHERRYVIEW(dev_priv
)) {
6730 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6731 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6733 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6734 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6737 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6739 i9xx_pfit_enable(intel_crtc
);
6741 intel_color_load_luts(&pipe_config
->base
);
6743 intel_update_watermarks(intel_crtc
);
6744 intel_enable_pipe(intel_crtc
);
6746 assert_vblank_disabled(crtc
);
6747 drm_crtc_vblank_on(crtc
);
6749 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6752 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6754 struct drm_device
*dev
= crtc
->base
.dev
;
6755 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6757 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6758 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6761 static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config
,
6762 struct drm_atomic_state
*old_state
)
6764 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6765 struct drm_device
*dev
= crtc
->dev
;
6766 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6767 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6768 enum pipe pipe
= intel_crtc
->pipe
;
6770 if (WARN_ON(intel_crtc
->active
))
6773 i9xx_set_pll_dividers(intel_crtc
);
6775 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
6776 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6778 intel_set_pipe_timings(intel_crtc
);
6779 intel_set_pipe_src_size(intel_crtc
);
6781 i9xx_set_pipeconf(intel_crtc
);
6783 intel_crtc
->active
= true;
6785 if (!IS_GEN2(dev_priv
))
6786 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6788 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6790 i9xx_enable_pll(intel_crtc
);
6792 i9xx_pfit_enable(intel_crtc
);
6794 intel_color_load_luts(&pipe_config
->base
);
6796 intel_update_watermarks(intel_crtc
);
6797 intel_enable_pipe(intel_crtc
);
6799 assert_vblank_disabled(crtc
);
6800 drm_crtc_vblank_on(crtc
);
6802 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6805 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6807 struct drm_device
*dev
= crtc
->base
.dev
;
6808 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6810 if (!crtc
->config
->gmch_pfit
.control
)
6813 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6815 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6816 I915_READ(PFIT_CONTROL
));
6817 I915_WRITE(PFIT_CONTROL
, 0);
6820 static void i9xx_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6821 struct drm_atomic_state
*old_state
)
6823 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6824 struct drm_device
*dev
= crtc
->dev
;
6825 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6827 int pipe
= intel_crtc
->pipe
;
6830 * On gen2 planes are double buffered but the pipe isn't, so we must
6831 * wait for planes to fully turn off before disabling the pipe.
6833 if (IS_GEN2(dev_priv
))
6834 intel_wait_for_vblank(dev_priv
, pipe
);
6836 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6838 drm_crtc_vblank_off(crtc
);
6839 assert_vblank_disabled(crtc
);
6841 intel_disable_pipe(intel_crtc
);
6843 i9xx_pfit_disable(intel_crtc
);
6845 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6847 if (!intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DSI
)) {
6848 if (IS_CHERRYVIEW(dev_priv
))
6849 chv_disable_pll(dev_priv
, pipe
);
6850 else if (IS_VALLEYVIEW(dev_priv
))
6851 vlv_disable_pll(dev_priv
, pipe
);
6853 i9xx_disable_pll(intel_crtc
);
6856 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
6858 if (!IS_GEN2(dev_priv
))
6859 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6862 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6864 struct intel_encoder
*encoder
;
6865 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6866 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6867 enum intel_display_power_domain domain
;
6868 unsigned long domains
;
6869 struct drm_atomic_state
*state
;
6870 struct intel_crtc_state
*crtc_state
;
6873 if (!intel_crtc
->active
)
6876 if (crtc
->primary
->state
->visible
) {
6877 WARN_ON(intel_crtc
->flip_work
);
6879 intel_pre_disable_primary_noatomic(crtc
);
6881 intel_crtc_disable_planes(crtc
, 1 << drm_plane_index(crtc
->primary
));
6882 crtc
->primary
->state
->visible
= false;
6885 state
= drm_atomic_state_alloc(crtc
->dev
);
6887 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6888 crtc
->base
.id
, crtc
->name
);
6892 state
->acquire_ctx
= crtc
->dev
->mode_config
.acquire_ctx
;
6894 /* Everything's already locked, -EDEADLK can't happen. */
6895 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
6896 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
6898 WARN_ON(IS_ERR(crtc_state
) || ret
);
6900 dev_priv
->display
.crtc_disable(crtc_state
, state
);
6902 drm_atomic_state_put(state
);
6904 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6905 crtc
->base
.id
, crtc
->name
);
6907 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6908 crtc
->state
->active
= false;
6909 intel_crtc
->active
= false;
6910 crtc
->enabled
= false;
6911 crtc
->state
->connector_mask
= 0;
6912 crtc
->state
->encoder_mask
= 0;
6914 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6915 encoder
->base
.crtc
= NULL
;
6917 intel_fbc_disable(intel_crtc
);
6918 intel_update_watermarks(intel_crtc
);
6919 intel_disable_shared_dpll(intel_crtc
);
6921 domains
= intel_crtc
->enabled_power_domains
;
6922 for_each_power_domain(domain
, domains
)
6923 intel_display_power_put(dev_priv
, domain
);
6924 intel_crtc
->enabled_power_domains
= 0;
6926 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6927 dev_priv
->min_pixclk
[intel_crtc
->pipe
] = 0;
6931 * turn all crtc's off, but do not adjust state
6932 * This has to be paired with a call to intel_modeset_setup_hw_state.
6934 int intel_display_suspend(struct drm_device
*dev
)
6936 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6937 struct drm_atomic_state
*state
;
6940 state
= drm_atomic_helper_suspend(dev
);
6941 ret
= PTR_ERR_OR_ZERO(state
);
6943 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6945 dev_priv
->modeset_restore_state
= state
;
6949 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6951 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6953 drm_encoder_cleanup(encoder
);
6954 kfree(intel_encoder
);
6957 /* Cross check the actual hw state with our own modeset state tracking (and it's
6958 * internal consistency). */
6959 static void intel_connector_verify_state(struct intel_connector
*connector
)
6961 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
6963 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6964 connector
->base
.base
.id
,
6965 connector
->base
.name
);
6967 if (connector
->get_hw_state(connector
)) {
6968 struct intel_encoder
*encoder
= connector
->encoder
;
6969 struct drm_connector_state
*conn_state
= connector
->base
.state
;
6971 I915_STATE_WARN(!crtc
,
6972 "connector enabled without attached crtc\n");
6977 I915_STATE_WARN(!crtc
->state
->active
,
6978 "connector is active, but attached crtc isn't\n");
6980 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6983 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6984 "atomic encoder doesn't match attached encoder\n");
6986 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6987 "attached encoder crtc differs from connector crtc\n");
6989 I915_STATE_WARN(crtc
&& crtc
->state
->active
,
6990 "attached crtc is active, but connector isn't\n");
6991 I915_STATE_WARN(!crtc
&& connector
->base
.state
->best_encoder
,
6992 "best encoder set without crtc!\n");
6996 int intel_connector_init(struct intel_connector
*connector
)
6998 drm_atomic_helper_connector_reset(&connector
->base
);
7000 if (!connector
->base
.state
)
7006 struct intel_connector
*intel_connector_alloc(void)
7008 struct intel_connector
*connector
;
7010 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
7014 if (intel_connector_init(connector
) < 0) {
7022 /* Simple connector->get_hw_state implementation for encoders that support only
7023 * one connector and no cloning and hence the encoder state determines the state
7024 * of the connector. */
7025 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
7028 struct intel_encoder
*encoder
= connector
->encoder
;
7030 return encoder
->get_hw_state(encoder
, &pipe
);
7033 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
7035 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
7036 return crtc_state
->fdi_lanes
;
7041 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
7042 struct intel_crtc_state
*pipe_config
)
7044 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7045 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
7046 struct intel_crtc
*other_crtc
;
7047 struct intel_crtc_state
*other_crtc_state
;
7049 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7050 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7051 if (pipe_config
->fdi_lanes
> 4) {
7052 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7053 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7057 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
7058 if (pipe_config
->fdi_lanes
> 2) {
7059 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7060 pipe_config
->fdi_lanes
);
7067 if (INTEL_INFO(dev_priv
)->num_pipes
== 2)
7070 /* Ivybridge 3 pipe is really complicated */
7075 if (pipe_config
->fdi_lanes
<= 2)
7078 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_C
);
7080 intel_atomic_get_crtc_state(state
, other_crtc
);
7081 if (IS_ERR(other_crtc_state
))
7082 return PTR_ERR(other_crtc_state
);
7084 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
7085 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7086 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7091 if (pipe_config
->fdi_lanes
> 2) {
7092 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7093 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7097 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_B
);
7099 intel_atomic_get_crtc_state(state
, other_crtc
);
7100 if (IS_ERR(other_crtc_state
))
7101 return PTR_ERR(other_crtc_state
);
7103 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
7104 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7114 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
7115 struct intel_crtc_state
*pipe_config
)
7117 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7118 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
7119 int lane
, link_bw
, fdi_dotclock
, ret
;
7120 bool needs_recompute
= false;
7123 /* FDI is a binary signal running at ~2.7GHz, encoding
7124 * each output octet as 10 bits. The actual frequency
7125 * is stored as a divider into a 100MHz clock, and the
7126 * mode pixel clock is stored in units of 1KHz.
7127 * Hence the bw of each lane in terms of the mode signal
7130 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
7132 fdi_dotclock
= adjusted_mode
->crtc_clock
;
7134 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
7135 pipe_config
->pipe_bpp
);
7137 pipe_config
->fdi_lanes
= lane
;
7139 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
7140 link_bw
, &pipe_config
->fdi_m_n
);
7142 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
7143 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
7144 pipe_config
->pipe_bpp
-= 2*3;
7145 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7146 pipe_config
->pipe_bpp
);
7147 needs_recompute
= true;
7148 pipe_config
->bw_constrained
= true;
7153 if (needs_recompute
)
7159 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
7160 struct intel_crtc_state
*pipe_config
)
7162 if (pipe_config
->pipe_bpp
> 24)
7165 /* HSW can handle pixel rate up to cdclk? */
7166 if (IS_HASWELL(dev_priv
))
7170 * We compare against max which means we must take
7171 * the increased cdclk requirement into account when
7172 * calculating the new cdclk.
7174 * Should measure whether using a lower cdclk w/o IPS
7176 return ilk_pipe_pixel_rate(pipe_config
) <=
7177 dev_priv
->max_cdclk_freq
* 95 / 100;
7180 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
7181 struct intel_crtc_state
*pipe_config
)
7183 struct drm_device
*dev
= crtc
->base
.dev
;
7184 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7186 pipe_config
->ips_enabled
= i915
.enable_ips
&&
7187 hsw_crtc_supports_ips(crtc
) &&
7188 pipe_config_supports_ips(dev_priv
, pipe_config
);
7191 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
7193 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7195 /* GDG double wide on either pipe, otherwise pipe A only */
7196 return INTEL_INFO(dev_priv
)->gen
< 4 &&
7197 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
7200 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
7201 struct intel_crtc_state
*pipe_config
)
7203 struct drm_device
*dev
= crtc
->base
.dev
;
7204 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7205 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
7206 int clock_limit
= dev_priv
->max_dotclk_freq
;
7208 if (INTEL_GEN(dev_priv
) < 4) {
7209 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
7212 * Enable double wide mode when the dot clock
7213 * is > 90% of the (display) core speed.
7215 if (intel_crtc_supports_double_wide(crtc
) &&
7216 adjusted_mode
->crtc_clock
> clock_limit
) {
7217 clock_limit
= dev_priv
->max_dotclk_freq
;
7218 pipe_config
->double_wide
= true;
7222 if (adjusted_mode
->crtc_clock
> clock_limit
) {
7223 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7224 adjusted_mode
->crtc_clock
, clock_limit
,
7225 yesno(pipe_config
->double_wide
));
7230 * Pipe horizontal size must be even in:
7232 * - LVDS dual channel mode
7233 * - Double wide pipe
7235 if ((intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
7236 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
7237 pipe_config
->pipe_src_w
&= ~1;
7239 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7240 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7242 if ((INTEL_GEN(dev_priv
) > 4 || IS_G4X(dev_priv
)) &&
7243 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
7246 if (HAS_IPS(dev_priv
))
7247 hsw_compute_ips_config(crtc
, pipe_config
);
7249 if (pipe_config
->has_pch_encoder
)
7250 return ironlake_fdi_compute_config(crtc
, pipe_config
);
7255 static int skylake_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7259 skl_dpll0_update(dev_priv
);
7261 if (dev_priv
->cdclk_pll
.vco
== 0)
7262 return dev_priv
->cdclk_pll
.ref
;
7264 cdctl
= I915_READ(CDCLK_CTL
);
7266 if (dev_priv
->cdclk_pll
.vco
== 8640000) {
7267 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
7268 case CDCLK_FREQ_450_432
:
7270 case CDCLK_FREQ_337_308
:
7272 case CDCLK_FREQ_540
:
7274 case CDCLK_FREQ_675_617
:
7277 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
7280 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
7281 case CDCLK_FREQ_450_432
:
7283 case CDCLK_FREQ_337_308
:
7285 case CDCLK_FREQ_540
:
7287 case CDCLK_FREQ_675_617
:
7290 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
7294 return dev_priv
->cdclk_pll
.ref
;
7297 static void bxt_de_pll_update(struct drm_i915_private
*dev_priv
)
7301 dev_priv
->cdclk_pll
.ref
= 19200;
7302 dev_priv
->cdclk_pll
.vco
= 0;
7304 val
= I915_READ(BXT_DE_PLL_ENABLE
);
7305 if ((val
& BXT_DE_PLL_PLL_ENABLE
) == 0)
7308 if (WARN_ON((val
& BXT_DE_PLL_LOCK
) == 0))
7311 val
= I915_READ(BXT_DE_PLL_CTL
);
7312 dev_priv
->cdclk_pll
.vco
= (val
& BXT_DE_PLL_RATIO_MASK
) *
7313 dev_priv
->cdclk_pll
.ref
;
7316 static int broxton_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7321 bxt_de_pll_update(dev_priv
);
7323 vco
= dev_priv
->cdclk_pll
.vco
;
7325 return dev_priv
->cdclk_pll
.ref
;
7327 divider
= I915_READ(CDCLK_CTL
) & BXT_CDCLK_CD2X_DIV_SEL_MASK
;
7330 case BXT_CDCLK_CD2X_DIV_SEL_1
:
7333 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
7334 WARN(IS_GEMINILAKE(dev_priv
), "Unsupported divider\n");
7337 case BXT_CDCLK_CD2X_DIV_SEL_2
:
7340 case BXT_CDCLK_CD2X_DIV_SEL_4
:
7344 MISSING_CASE(divider
);
7345 return dev_priv
->cdclk_pll
.ref
;
7348 return DIV_ROUND_CLOSEST(vco
, div
);
7351 static int broadwell_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7353 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
7354 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
7356 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
7358 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
7360 else if (freq
== LCPLL_CLK_FREQ_450
)
7362 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
7364 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
7370 static int haswell_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7372 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
7373 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
7375 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
7377 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
7379 else if (freq
== LCPLL_CLK_FREQ_450
)
7381 else if (IS_HSW_ULT(dev_priv
))
7387 static int valleyview_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7389 return vlv_get_cck_clock_hpll(dev_priv
, "cdclk",
7390 CCK_DISPLAY_CLOCK_CONTROL
);
7393 static int ilk_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7398 static int i945_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7403 static int i915_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7408 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7413 static int pnv_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7415 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7418 pci_read_config_word(pdev
, GCFGC
, &gcfgc
);
7420 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
7421 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
7423 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
7425 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
7427 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
7430 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
7431 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
7433 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
7438 static int i915gm_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7440 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7443 pci_read_config_word(pdev
, GCFGC
, &gcfgc
);
7445 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
7448 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
7449 case GC_DISPLAY_CLOCK_333_MHZ
:
7452 case GC_DISPLAY_CLOCK_190_200_MHZ
:
7458 static int i865_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7463 static int i85x_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7465 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7469 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7470 * encoding is different :(
7471 * FIXME is this the right way to detect 852GM/852GMV?
7473 if (pdev
->revision
== 0x1)
7476 pci_bus_read_config_word(pdev
->bus
,
7477 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
7479 /* Assume that the hardware is in the high speed state. This
7480 * should be the default.
7482 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
7483 case GC_CLOCK_133_200
:
7484 case GC_CLOCK_133_200_2
:
7485 case GC_CLOCK_100_200
:
7487 case GC_CLOCK_166_250
:
7489 case GC_CLOCK_100_133
:
7491 case GC_CLOCK_133_266
:
7492 case GC_CLOCK_133_266_2
:
7493 case GC_CLOCK_166_266
:
7497 /* Shouldn't happen */
7501 static int i830_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7506 static unsigned int intel_hpll_vco(struct drm_i915_private
*dev_priv
)
7508 static const unsigned int blb_vco
[8] = {
7515 static const unsigned int pnv_vco
[8] = {
7522 static const unsigned int cl_vco
[8] = {
7531 static const unsigned int elk_vco
[8] = {
7537 static const unsigned int ctg_vco
[8] = {
7545 const unsigned int *vco_table
;
7549 /* FIXME other chipsets? */
7550 if (IS_GM45(dev_priv
))
7551 vco_table
= ctg_vco
;
7552 else if (IS_G4X(dev_priv
))
7553 vco_table
= elk_vco
;
7554 else if (IS_I965GM(dev_priv
))
7556 else if (IS_PINEVIEW(dev_priv
))
7557 vco_table
= pnv_vco
;
7558 else if (IS_G33(dev_priv
))
7559 vco_table
= blb_vco
;
7563 tmp
= I915_READ(IS_MOBILE(dev_priv
) ? HPLLVCO_MOBILE
: HPLLVCO
);
7565 vco
= vco_table
[tmp
& 0x7];
7567 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
7569 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
7574 static int gm45_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7576 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7577 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev_priv
);
7580 pci_read_config_word(pdev
, GCFGC
, &tmp
);
7582 cdclk_sel
= (tmp
>> 12) & 0x1;
7588 return cdclk_sel
? 333333 : 222222;
7590 return cdclk_sel
? 320000 : 228571;
7592 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
7597 static int i965gm_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7599 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7600 static const uint8_t div_3200
[] = { 16, 10, 8 };
7601 static const uint8_t div_4000
[] = { 20, 12, 10 };
7602 static const uint8_t div_5333
[] = { 24, 16, 14 };
7603 const uint8_t *div_table
;
7604 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev_priv
);
7607 pci_read_config_word(pdev
, GCFGC
, &tmp
);
7609 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
7611 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7616 div_table
= div_3200
;
7619 div_table
= div_4000
;
7622 div_table
= div_5333
;
7628 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7631 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
7635 static int g33_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7637 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7638 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
7639 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
7640 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
7641 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
7642 const uint8_t *div_table
;
7643 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev_priv
);
7646 pci_read_config_word(pdev
, GCFGC
, &tmp
);
7648 cdclk_sel
= (tmp
>> 4) & 0x7;
7650 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7655 div_table
= div_3200
;
7658 div_table
= div_4000
;
7661 div_table
= div_4800
;
7664 div_table
= div_5333
;
7670 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7673 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
7678 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
7680 while (*num
> DATA_LINK_M_N_MASK
||
7681 *den
> DATA_LINK_M_N_MASK
) {
7687 static void compute_m_n(unsigned int m
, unsigned int n
,
7688 uint32_t *ret_m
, uint32_t *ret_n
)
7690 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7691 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7692 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7696 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7697 int pixel_clock
, int link_clock
,
7698 struct intel_link_m_n
*m_n
)
7702 compute_m_n(bits_per_pixel
* pixel_clock
,
7703 link_clock
* nlanes
* 8,
7704 &m_n
->gmch_m
, &m_n
->gmch_n
);
7706 compute_m_n(pixel_clock
, link_clock
,
7707 &m_n
->link_m
, &m_n
->link_n
);
7710 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7712 if (i915
.panel_use_ssc
>= 0)
7713 return i915
.panel_use_ssc
!= 0;
7714 return dev_priv
->vbt
.lvds_use_ssc
7715 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7718 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7720 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7723 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7725 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7728 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7729 struct intel_crtc_state
*crtc_state
,
7730 struct dpll
*reduced_clock
)
7732 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7735 if (IS_PINEVIEW(dev_priv
)) {
7736 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7738 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7740 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7742 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7745 crtc_state
->dpll_hw_state
.fp0
= fp
;
7747 crtc
->lowfreq_avail
= false;
7748 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7750 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7751 crtc
->lowfreq_avail
= true;
7753 crtc_state
->dpll_hw_state
.fp1
= fp
;
7757 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7763 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7764 * and set it to a reasonable value instead.
7766 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7767 reg_val
&= 0xffffff00;
7768 reg_val
|= 0x00000030;
7769 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7771 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7772 reg_val
&= 0x8cffffff;
7773 reg_val
= 0x8c000000;
7774 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7776 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7777 reg_val
&= 0xffffff00;
7778 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7780 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7781 reg_val
&= 0x00ffffff;
7782 reg_val
|= 0xb0000000;
7783 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7786 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7787 struct intel_link_m_n
*m_n
)
7789 struct drm_device
*dev
= crtc
->base
.dev
;
7790 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7791 int pipe
= crtc
->pipe
;
7793 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7794 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7795 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7796 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7799 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7800 struct intel_link_m_n
*m_n
,
7801 struct intel_link_m_n
*m2_n2
)
7803 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7804 int pipe
= crtc
->pipe
;
7805 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7807 if (INTEL_GEN(dev_priv
) >= 5) {
7808 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7809 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7810 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7811 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7812 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7813 * for gen < 8) and if DRRS is supported (to make sure the
7814 * registers are not unnecessarily accessed).
7816 if (m2_n2
&& (IS_CHERRYVIEW(dev_priv
) ||
7817 INTEL_GEN(dev_priv
) < 8) && crtc
->config
->has_drrs
) {
7818 I915_WRITE(PIPE_DATA_M2(transcoder
),
7819 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7820 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7821 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7822 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7825 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7826 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7827 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7828 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7832 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7834 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7837 dp_m_n
= &crtc
->config
->dp_m_n
;
7838 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7839 } else if (m_n
== M2_N2
) {
7842 * M2_N2 registers are not supported. Hence m2_n2 divider value
7843 * needs to be programmed into M1_N1.
7845 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7847 DRM_ERROR("Unsupported divider value\n");
7851 if (crtc
->config
->has_pch_encoder
)
7852 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7854 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7857 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7858 struct intel_crtc_state
*pipe_config
)
7860 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7861 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7862 if (crtc
->pipe
!= PIPE_A
)
7863 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7865 /* DPLL not used with DSI, but still need the rest set up */
7866 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7867 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
7868 DPLL_EXT_BUFFER_ENABLE_VLV
;
7870 pipe_config
->dpll_hw_state
.dpll_md
=
7871 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7874 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7875 struct intel_crtc_state
*pipe_config
)
7877 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7878 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7879 if (crtc
->pipe
!= PIPE_A
)
7880 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7882 /* DPLL not used with DSI, but still need the rest set up */
7883 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7884 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
7886 pipe_config
->dpll_hw_state
.dpll_md
=
7887 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7890 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7891 const struct intel_crtc_state
*pipe_config
)
7893 struct drm_device
*dev
= crtc
->base
.dev
;
7894 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7895 enum pipe pipe
= crtc
->pipe
;
7897 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7898 u32 coreclk
, reg_val
;
7901 I915_WRITE(DPLL(pipe
),
7902 pipe_config
->dpll_hw_state
.dpll
&
7903 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
7905 /* No need to actually set up the DPLL with DSI */
7906 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7909 mutex_lock(&dev_priv
->sb_lock
);
7911 bestn
= pipe_config
->dpll
.n
;
7912 bestm1
= pipe_config
->dpll
.m1
;
7913 bestm2
= pipe_config
->dpll
.m2
;
7914 bestp1
= pipe_config
->dpll
.p1
;
7915 bestp2
= pipe_config
->dpll
.p2
;
7917 /* See eDP HDMI DPIO driver vbios notes doc */
7919 /* PLL B needs special handling */
7921 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7923 /* Set up Tx target for periodic Rcomp update */
7924 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7926 /* Disable target IRef on PLL */
7927 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7928 reg_val
&= 0x00ffffff;
7929 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7931 /* Disable fast lock */
7932 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7934 /* Set idtafcrecal before PLL is enabled */
7935 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7936 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7937 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7938 mdiv
|= (1 << DPIO_K_SHIFT
);
7941 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7942 * but we don't support that).
7943 * Note: don't use the DAC post divider as it seems unstable.
7945 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7946 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7948 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7949 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7951 /* Set HBR and RBR LPF coefficients */
7952 if (pipe_config
->port_clock
== 162000 ||
7953 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_ANALOG
) ||
7954 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
))
7955 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7958 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7961 if (intel_crtc_has_dp_encoder(pipe_config
)) {
7962 /* Use SSC source */
7964 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7967 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7969 } else { /* HDMI or VGA */
7970 /* Use bend source */
7972 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7975 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7979 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7980 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7981 if (intel_crtc_has_dp_encoder(crtc
->config
))
7982 coreclk
|= 0x01000000;
7983 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7985 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7986 mutex_unlock(&dev_priv
->sb_lock
);
7989 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7990 const struct intel_crtc_state
*pipe_config
)
7992 struct drm_device
*dev
= crtc
->base
.dev
;
7993 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7994 enum pipe pipe
= crtc
->pipe
;
7995 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7996 u32 loopfilter
, tribuf_calcntr
;
7997 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
8001 /* Enable Refclk and SSC */
8002 I915_WRITE(DPLL(pipe
),
8003 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
8005 /* No need to actually set up the DPLL with DSI */
8006 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8009 bestn
= pipe_config
->dpll
.n
;
8010 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
8011 bestm1
= pipe_config
->dpll
.m1
;
8012 bestm2
= pipe_config
->dpll
.m2
>> 22;
8013 bestp1
= pipe_config
->dpll
.p1
;
8014 bestp2
= pipe_config
->dpll
.p2
;
8015 vco
= pipe_config
->dpll
.vco
;
8019 mutex_lock(&dev_priv
->sb_lock
);
8021 /* p1 and p2 divider */
8022 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
8023 5 << DPIO_CHV_S1_DIV_SHIFT
|
8024 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
8025 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
8026 1 << DPIO_CHV_K_DIV_SHIFT
);
8028 /* Feedback post-divider - m2 */
8029 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
8031 /* Feedback refclk divider - n and m1 */
8032 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
8033 DPIO_CHV_M1_DIV_BY_2
|
8034 1 << DPIO_CHV_N_DIV_SHIFT
);
8036 /* M2 fraction division */
8037 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
8039 /* M2 fraction division enable */
8040 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8041 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
8042 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
8044 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
8045 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
8047 /* Program digital lock detect threshold */
8048 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
8049 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
8050 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
8051 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
8053 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
8054 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
8057 if (vco
== 5400000) {
8058 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
8059 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
8060 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
8061 tribuf_calcntr
= 0x9;
8062 } else if (vco
<= 6200000) {
8063 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
8064 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
8065 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
8066 tribuf_calcntr
= 0x9;
8067 } else if (vco
<= 6480000) {
8068 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
8069 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
8070 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
8071 tribuf_calcntr
= 0x8;
8073 /* Not supported. Apply the same limits as in the max case */
8074 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
8075 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
8076 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
8079 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
8081 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
8082 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
8083 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
8084 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
8087 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
8088 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
8091 mutex_unlock(&dev_priv
->sb_lock
);
8095 * vlv_force_pll_on - forcibly enable just the PLL
8096 * @dev_priv: i915 private structure
8097 * @pipe: pipe PLL to enable
8098 * @dpll: PLL configuration
8100 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8101 * in cases where we need the PLL enabled even when @pipe is not going to
8104 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
8105 const struct dpll
*dpll
)
8107 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
8108 struct intel_crtc_state
*pipe_config
;
8110 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8114 pipe_config
->base
.crtc
= &crtc
->base
;
8115 pipe_config
->pixel_multiplier
= 1;
8116 pipe_config
->dpll
= *dpll
;
8118 if (IS_CHERRYVIEW(dev_priv
)) {
8119 chv_compute_dpll(crtc
, pipe_config
);
8120 chv_prepare_pll(crtc
, pipe_config
);
8121 chv_enable_pll(crtc
, pipe_config
);
8123 vlv_compute_dpll(crtc
, pipe_config
);
8124 vlv_prepare_pll(crtc
, pipe_config
);
8125 vlv_enable_pll(crtc
, pipe_config
);
8134 * vlv_force_pll_off - forcibly disable just the PLL
8135 * @dev_priv: i915 private structure
8136 * @pipe: pipe PLL to disable
8138 * Disable the PLL for @pipe. To be used in cases where we need
8139 * the PLL enabled even when @pipe is not going to be enabled.
8141 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
8143 if (IS_CHERRYVIEW(dev_priv
))
8144 chv_disable_pll(dev_priv
, pipe
);
8146 vlv_disable_pll(dev_priv
, pipe
);
8149 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
8150 struct intel_crtc_state
*crtc_state
,
8151 struct dpll
*reduced_clock
)
8153 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8155 struct dpll
*clock
= &crtc_state
->dpll
;
8157 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
8159 dpll
= DPLL_VGA_MODE_DIS
;
8161 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
8162 dpll
|= DPLLB_MODE_LVDS
;
8164 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8166 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
8167 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
8168 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8169 << SDVO_MULTIPLIER_SHIFT_HIRES
;
8172 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
8173 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
8174 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8176 if (intel_crtc_has_dp_encoder(crtc_state
))
8177 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8179 /* compute bitmask from p1 value */
8180 if (IS_PINEVIEW(dev_priv
))
8181 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
8183 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8184 if (IS_G4X(dev_priv
) && reduced_clock
)
8185 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8187 switch (clock
->p2
) {
8189 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8192 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8195 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8198 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8201 if (INTEL_GEN(dev_priv
) >= 4)
8202 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
8204 if (crtc_state
->sdvo_tv_clock
)
8205 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
8206 else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
8207 intel_panel_use_ssc(dev_priv
))
8208 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8210 dpll
|= PLL_REF_INPUT_DREFCLK
;
8212 dpll
|= DPLL_VCO_ENABLE
;
8213 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8215 if (INTEL_GEN(dev_priv
) >= 4) {
8216 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
8217 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
8218 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
8222 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
8223 struct intel_crtc_state
*crtc_state
,
8224 struct dpll
*reduced_clock
)
8226 struct drm_device
*dev
= crtc
->base
.dev
;
8227 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8229 struct dpll
*clock
= &crtc_state
->dpll
;
8231 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
8233 dpll
= DPLL_VGA_MODE_DIS
;
8235 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8236 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8239 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
8241 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8243 dpll
|= PLL_P2_DIVIDE_BY_4
;
8246 if (!IS_I830(dev_priv
) &&
8247 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
))
8248 dpll
|= DPLL_DVO_2X_MODE
;
8250 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
8251 intel_panel_use_ssc(dev_priv
))
8252 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8254 dpll
|= PLL_REF_INPUT_DREFCLK
;
8256 dpll
|= DPLL_VCO_ENABLE
;
8257 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8260 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
8262 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
8263 enum pipe pipe
= intel_crtc
->pipe
;
8264 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8265 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
8266 uint32_t crtc_vtotal
, crtc_vblank_end
;
8269 /* We need to be careful not to changed the adjusted mode, for otherwise
8270 * the hw state checker will get angry at the mismatch. */
8271 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
8272 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
8274 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
8275 /* the chip adds 2 halflines automatically */
8277 crtc_vblank_end
-= 1;
8279 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
8280 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
8282 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
8283 adjusted_mode
->crtc_htotal
/ 2;
8285 vsyncshift
+= adjusted_mode
->crtc_htotal
;
8288 if (INTEL_GEN(dev_priv
) > 3)
8289 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
8291 I915_WRITE(HTOTAL(cpu_transcoder
),
8292 (adjusted_mode
->crtc_hdisplay
- 1) |
8293 ((adjusted_mode
->crtc_htotal
- 1) << 16));
8294 I915_WRITE(HBLANK(cpu_transcoder
),
8295 (adjusted_mode
->crtc_hblank_start
- 1) |
8296 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
8297 I915_WRITE(HSYNC(cpu_transcoder
),
8298 (adjusted_mode
->crtc_hsync_start
- 1) |
8299 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
8301 I915_WRITE(VTOTAL(cpu_transcoder
),
8302 (adjusted_mode
->crtc_vdisplay
- 1) |
8303 ((crtc_vtotal
- 1) << 16));
8304 I915_WRITE(VBLANK(cpu_transcoder
),
8305 (adjusted_mode
->crtc_vblank_start
- 1) |
8306 ((crtc_vblank_end
- 1) << 16));
8307 I915_WRITE(VSYNC(cpu_transcoder
),
8308 (adjusted_mode
->crtc_vsync_start
- 1) |
8309 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
8311 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8312 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8313 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8315 if (IS_HASWELL(dev_priv
) && cpu_transcoder
== TRANSCODER_EDP
&&
8316 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
8317 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
8321 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
)
8323 struct drm_device
*dev
= intel_crtc
->base
.dev
;
8324 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8325 enum pipe pipe
= intel_crtc
->pipe
;
8327 /* pipesrc controls the size that is scaled from, which should
8328 * always be the user's requested size.
8330 I915_WRITE(PIPESRC(pipe
),
8331 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
8332 (intel_crtc
->config
->pipe_src_h
- 1));
8335 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
8336 struct intel_crtc_state
*pipe_config
)
8338 struct drm_device
*dev
= crtc
->base
.dev
;
8339 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8340 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
8343 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
8344 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
8345 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
8346 tmp
= I915_READ(HBLANK(cpu_transcoder
));
8347 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
8348 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
8349 tmp
= I915_READ(HSYNC(cpu_transcoder
));
8350 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
8351 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
8353 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
8354 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
8355 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
8356 tmp
= I915_READ(VBLANK(cpu_transcoder
));
8357 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
8358 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
8359 tmp
= I915_READ(VSYNC(cpu_transcoder
));
8360 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
8361 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
8363 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
8364 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
8365 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
8366 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
8370 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
8371 struct intel_crtc_state
*pipe_config
)
8373 struct drm_device
*dev
= crtc
->base
.dev
;
8374 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8377 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
8378 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
8379 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
8381 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
8382 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
8385 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
8386 struct intel_crtc_state
*pipe_config
)
8388 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
8389 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
8390 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
8391 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
8393 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
8394 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
8395 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
8396 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
8398 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
8399 mode
->type
= DRM_MODE_TYPE_DRIVER
;
8401 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
8403 mode
->hsync
= drm_mode_hsync(mode
);
8404 mode
->vrefresh
= drm_mode_vrefresh(mode
);
8405 drm_mode_set_name(mode
);
8408 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
8410 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
8415 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
8416 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
8417 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
8419 if (intel_crtc
->config
->double_wide
)
8420 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
8422 /* only g4x and later have fancy bpc/dither controls */
8423 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
8424 IS_CHERRYVIEW(dev_priv
)) {
8425 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8426 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
8427 pipeconf
|= PIPECONF_DITHER_EN
|
8428 PIPECONF_DITHER_TYPE_SP
;
8430 switch (intel_crtc
->config
->pipe_bpp
) {
8432 pipeconf
|= PIPECONF_6BPC
;
8435 pipeconf
|= PIPECONF_8BPC
;
8438 pipeconf
|= PIPECONF_10BPC
;
8441 /* Case prevented by intel_choose_pipe_bpp_dither. */
8446 if (HAS_PIPE_CXSR(dev_priv
)) {
8447 if (intel_crtc
->lowfreq_avail
) {
8448 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8449 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
8451 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8455 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
8456 if (INTEL_GEN(dev_priv
) < 4 ||
8457 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
8458 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
8460 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
8462 pipeconf
|= PIPECONF_PROGRESSIVE
;
8464 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
8465 intel_crtc
->config
->limited_color_range
)
8466 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
8468 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
8469 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
8472 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
8473 struct intel_crtc_state
*crtc_state
)
8475 struct drm_device
*dev
= crtc
->base
.dev
;
8476 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8477 const struct intel_limit
*limit
;
8480 memset(&crtc_state
->dpll_hw_state
, 0,
8481 sizeof(crtc_state
->dpll_hw_state
));
8483 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8484 if (intel_panel_use_ssc(dev_priv
)) {
8485 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8486 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8489 limit
= &intel_limits_i8xx_lvds
;
8490 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
8491 limit
= &intel_limits_i8xx_dvo
;
8493 limit
= &intel_limits_i8xx_dac
;
8496 if (!crtc_state
->clock_set
&&
8497 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8498 refclk
, NULL
, &crtc_state
->dpll
)) {
8499 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8503 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
8508 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
8509 struct intel_crtc_state
*crtc_state
)
8511 struct drm_device
*dev
= crtc
->base
.dev
;
8512 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8513 const struct intel_limit
*limit
;
8516 memset(&crtc_state
->dpll_hw_state
, 0,
8517 sizeof(crtc_state
->dpll_hw_state
));
8519 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8520 if (intel_panel_use_ssc(dev_priv
)) {
8521 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8522 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8525 if (intel_is_dual_link_lvds(dev
))
8526 limit
= &intel_limits_g4x_dual_channel_lvds
;
8528 limit
= &intel_limits_g4x_single_channel_lvds
;
8529 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
8530 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
8531 limit
= &intel_limits_g4x_hdmi
;
8532 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
8533 limit
= &intel_limits_g4x_sdvo
;
8535 /* The option is for other outputs */
8536 limit
= &intel_limits_i9xx_sdvo
;
8539 if (!crtc_state
->clock_set
&&
8540 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8541 refclk
, NULL
, &crtc_state
->dpll
)) {
8542 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8546 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8551 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
8552 struct intel_crtc_state
*crtc_state
)
8554 struct drm_device
*dev
= crtc
->base
.dev
;
8555 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8556 const struct intel_limit
*limit
;
8559 memset(&crtc_state
->dpll_hw_state
, 0,
8560 sizeof(crtc_state
->dpll_hw_state
));
8562 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8563 if (intel_panel_use_ssc(dev_priv
)) {
8564 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8565 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8568 limit
= &intel_limits_pineview_lvds
;
8570 limit
= &intel_limits_pineview_sdvo
;
8573 if (!crtc_state
->clock_set
&&
8574 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8575 refclk
, NULL
, &crtc_state
->dpll
)) {
8576 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8580 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8585 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
8586 struct intel_crtc_state
*crtc_state
)
8588 struct drm_device
*dev
= crtc
->base
.dev
;
8589 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8590 const struct intel_limit
*limit
;
8593 memset(&crtc_state
->dpll_hw_state
, 0,
8594 sizeof(crtc_state
->dpll_hw_state
));
8596 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8597 if (intel_panel_use_ssc(dev_priv
)) {
8598 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8599 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8602 limit
= &intel_limits_i9xx_lvds
;
8604 limit
= &intel_limits_i9xx_sdvo
;
8607 if (!crtc_state
->clock_set
&&
8608 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8609 refclk
, NULL
, &crtc_state
->dpll
)) {
8610 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8614 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8619 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
8620 struct intel_crtc_state
*crtc_state
)
8622 int refclk
= 100000;
8623 const struct intel_limit
*limit
= &intel_limits_chv
;
8625 memset(&crtc_state
->dpll_hw_state
, 0,
8626 sizeof(crtc_state
->dpll_hw_state
));
8628 if (!crtc_state
->clock_set
&&
8629 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8630 refclk
, NULL
, &crtc_state
->dpll
)) {
8631 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8635 chv_compute_dpll(crtc
, crtc_state
);
8640 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
8641 struct intel_crtc_state
*crtc_state
)
8643 int refclk
= 100000;
8644 const struct intel_limit
*limit
= &intel_limits_vlv
;
8646 memset(&crtc_state
->dpll_hw_state
, 0,
8647 sizeof(crtc_state
->dpll_hw_state
));
8649 if (!crtc_state
->clock_set
&&
8650 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8651 refclk
, NULL
, &crtc_state
->dpll
)) {
8652 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8656 vlv_compute_dpll(crtc
, crtc_state
);
8661 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
8662 struct intel_crtc_state
*pipe_config
)
8664 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8667 if (INTEL_GEN(dev_priv
) <= 3 &&
8668 (IS_I830(dev_priv
) || !IS_MOBILE(dev_priv
)))
8671 tmp
= I915_READ(PFIT_CONTROL
);
8672 if (!(tmp
& PFIT_ENABLE
))
8675 /* Check whether the pfit is attached to our pipe. */
8676 if (INTEL_GEN(dev_priv
) < 4) {
8677 if (crtc
->pipe
!= PIPE_B
)
8680 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8684 pipe_config
->gmch_pfit
.control
= tmp
;
8685 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8688 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8689 struct intel_crtc_state
*pipe_config
)
8691 struct drm_device
*dev
= crtc
->base
.dev
;
8692 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8693 int pipe
= pipe_config
->cpu_transcoder
;
8696 int refclk
= 100000;
8698 /* In case of DSI, DPLL will not be used */
8699 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8702 mutex_lock(&dev_priv
->sb_lock
);
8703 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8704 mutex_unlock(&dev_priv
->sb_lock
);
8706 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8707 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8708 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8709 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8710 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8712 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8716 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8717 struct intel_initial_plane_config
*plane_config
)
8719 struct drm_device
*dev
= crtc
->base
.dev
;
8720 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8721 u32 val
, base
, offset
;
8722 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
8723 int fourcc
, pixel_format
;
8724 unsigned int aligned_height
;
8725 struct drm_framebuffer
*fb
;
8726 struct intel_framebuffer
*intel_fb
;
8728 val
= I915_READ(DSPCNTR(plane
));
8729 if (!(val
& DISPLAY_PLANE_ENABLE
))
8732 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8734 DRM_DEBUG_KMS("failed to alloc fb\n");
8738 fb
= &intel_fb
->base
;
8742 if (INTEL_GEN(dev_priv
) >= 4) {
8743 if (val
& DISPPLANE_TILED
) {
8744 plane_config
->tiling
= I915_TILING_X
;
8745 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
8749 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8750 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8751 fb
->format
= drm_format_info(fourcc
);
8753 if (INTEL_GEN(dev_priv
) >= 4) {
8754 if (plane_config
->tiling
)
8755 offset
= I915_READ(DSPTILEOFF(plane
));
8757 offset
= I915_READ(DSPLINOFF(plane
));
8758 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
8760 base
= I915_READ(DSPADDR(plane
));
8762 plane_config
->base
= base
;
8764 val
= I915_READ(PIPESRC(pipe
));
8765 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8766 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8768 val
= I915_READ(DSPSTRIDE(pipe
));
8769 fb
->pitches
[0] = val
& 0xffffffc0;
8771 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8775 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8777 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8778 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8779 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
8780 plane_config
->size
);
8782 plane_config
->fb
= intel_fb
;
8785 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8786 struct intel_crtc_state
*pipe_config
)
8788 struct drm_device
*dev
= crtc
->base
.dev
;
8789 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8790 int pipe
= pipe_config
->cpu_transcoder
;
8791 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8793 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8794 int refclk
= 100000;
8796 /* In case of DSI, DPLL will not be used */
8797 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8800 mutex_lock(&dev_priv
->sb_lock
);
8801 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8802 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8803 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8804 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8805 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8806 mutex_unlock(&dev_priv
->sb_lock
);
8808 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8809 clock
.m2
= (pll_dw0
& 0xff) << 22;
8810 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8811 clock
.m2
|= pll_dw2
& 0x3fffff;
8812 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8813 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8814 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8816 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8819 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8820 struct intel_crtc_state
*pipe_config
)
8822 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8823 enum intel_display_power_domain power_domain
;
8827 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8828 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
8831 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8832 pipe_config
->shared_dpll
= NULL
;
8836 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8837 if (!(tmp
& PIPECONF_ENABLE
))
8840 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
8841 IS_CHERRYVIEW(dev_priv
)) {
8842 switch (tmp
& PIPECONF_BPC_MASK
) {
8844 pipe_config
->pipe_bpp
= 18;
8847 pipe_config
->pipe_bpp
= 24;
8849 case PIPECONF_10BPC
:
8850 pipe_config
->pipe_bpp
= 30;
8857 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
8858 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8859 pipe_config
->limited_color_range
= true;
8861 if (INTEL_GEN(dev_priv
) < 4)
8862 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8864 intel_get_pipe_timings(crtc
, pipe_config
);
8865 intel_get_pipe_src_size(crtc
, pipe_config
);
8867 i9xx_get_pfit_config(crtc
, pipe_config
);
8869 if (INTEL_GEN(dev_priv
) >= 4) {
8870 /* No way to read it out on pipes B and C */
8871 if (IS_CHERRYVIEW(dev_priv
) && crtc
->pipe
!= PIPE_A
)
8872 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8874 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8875 pipe_config
->pixel_multiplier
=
8876 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8877 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8878 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8879 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
8880 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
)) {
8881 tmp
= I915_READ(DPLL(crtc
->pipe
));
8882 pipe_config
->pixel_multiplier
=
8883 ((tmp
& SDVO_MULTIPLIER_MASK
)
8884 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8886 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8887 * port and will be fixed up in the encoder->get_config
8889 pipe_config
->pixel_multiplier
= 1;
8891 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8892 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
8894 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8895 * on 830. Filter it out here so that we don't
8896 * report errors due to that.
8898 if (IS_I830(dev_priv
))
8899 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8901 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8902 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8904 /* Mask out read-only status bits. */
8905 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8906 DPLL_PORTC_READY_MASK
|
8907 DPLL_PORTB_READY_MASK
);
8910 if (IS_CHERRYVIEW(dev_priv
))
8911 chv_crtc_clock_get(crtc
, pipe_config
);
8912 else if (IS_VALLEYVIEW(dev_priv
))
8913 vlv_crtc_clock_get(crtc
, pipe_config
);
8915 i9xx_crtc_clock_get(crtc
, pipe_config
);
8918 * Normally the dotclock is filled in by the encoder .get_config()
8919 * but in case the pipe is enabled w/o any ports we need a sane
8922 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8923 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8928 intel_display_power_put(dev_priv
, power_domain
);
8933 static void ironlake_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8935 struct intel_encoder
*encoder
;
8938 bool has_lvds
= false;
8939 bool has_cpu_edp
= false;
8940 bool has_panel
= false;
8941 bool has_ck505
= false;
8942 bool can_ssc
= false;
8943 bool using_ssc_source
= false;
8945 /* We need to take the global config into account */
8946 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
8947 switch (encoder
->type
) {
8948 case INTEL_OUTPUT_LVDS
:
8952 case INTEL_OUTPUT_EDP
:
8954 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8962 if (HAS_PCH_IBX(dev_priv
)) {
8963 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8964 can_ssc
= has_ck505
;
8970 /* Check if any DPLLs are using the SSC source */
8971 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8972 u32 temp
= I915_READ(PCH_DPLL(i
));
8974 if (!(temp
& DPLL_VCO_ENABLE
))
8977 if ((temp
& PLL_REF_INPUT_MASK
) ==
8978 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
8979 using_ssc_source
= true;
8984 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8985 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
8987 /* Ironlake: try to setup display ref clock before DPLL
8988 * enabling. This is only under driver's control after
8989 * PCH B stepping, previous chipset stepping should be
8990 * ignoring this setting.
8992 val
= I915_READ(PCH_DREF_CONTROL
);
8994 /* As we must carefully and slowly disable/enable each source in turn,
8995 * compute the final state we want first and check if we need to
8996 * make any changes at all.
8999 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
9001 final
|= DREF_NONSPREAD_CK505_ENABLE
;
9003 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
9005 final
&= ~DREF_SSC_SOURCE_MASK
;
9006 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
9007 final
&= ~DREF_SSC1_ENABLE
;
9010 final
|= DREF_SSC_SOURCE_ENABLE
;
9012 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
9013 final
|= DREF_SSC1_ENABLE
;
9016 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
9017 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
9019 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
9021 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
9022 } else if (using_ssc_source
) {
9023 final
|= DREF_SSC_SOURCE_ENABLE
;
9024 final
|= DREF_SSC1_ENABLE
;
9030 /* Always enable nonspread source */
9031 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
9034 val
|= DREF_NONSPREAD_CK505_ENABLE
;
9036 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
9039 val
&= ~DREF_SSC_SOURCE_MASK
;
9040 val
|= DREF_SSC_SOURCE_ENABLE
;
9042 /* SSC must be turned on before enabling the CPU output */
9043 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
9044 DRM_DEBUG_KMS("Using SSC on panel\n");
9045 val
|= DREF_SSC1_ENABLE
;
9047 val
&= ~DREF_SSC1_ENABLE
;
9049 /* Get SSC going before enabling the outputs */
9050 I915_WRITE(PCH_DREF_CONTROL
, val
);
9051 POSTING_READ(PCH_DREF_CONTROL
);
9054 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
9056 /* Enable CPU source on CPU attached eDP */
9058 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
9059 DRM_DEBUG_KMS("Using SSC on eDP\n");
9060 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
9062 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
9064 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
9066 I915_WRITE(PCH_DREF_CONTROL
, val
);
9067 POSTING_READ(PCH_DREF_CONTROL
);
9070 DRM_DEBUG_KMS("Disabling CPU source output\n");
9072 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
9074 /* Turn off CPU output */
9075 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
9077 I915_WRITE(PCH_DREF_CONTROL
, val
);
9078 POSTING_READ(PCH_DREF_CONTROL
);
9081 if (!using_ssc_source
) {
9082 DRM_DEBUG_KMS("Disabling SSC source\n");
9084 /* Turn off the SSC source */
9085 val
&= ~DREF_SSC_SOURCE_MASK
;
9086 val
|= DREF_SSC_SOURCE_DISABLE
;
9089 val
&= ~DREF_SSC1_ENABLE
;
9091 I915_WRITE(PCH_DREF_CONTROL
, val
);
9092 POSTING_READ(PCH_DREF_CONTROL
);
9097 BUG_ON(val
!= final
);
9100 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
9104 tmp
= I915_READ(SOUTH_CHICKEN2
);
9105 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
9106 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
9108 if (wait_for_us(I915_READ(SOUTH_CHICKEN2
) &
9109 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
9110 DRM_ERROR("FDI mPHY reset assert timeout\n");
9112 tmp
= I915_READ(SOUTH_CHICKEN2
);
9113 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
9114 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
9116 if (wait_for_us((I915_READ(SOUTH_CHICKEN2
) &
9117 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
9118 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9121 /* WaMPhyProgramming:hsw */
9122 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
9126 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
9127 tmp
&= ~(0xFF << 24);
9128 tmp
|= (0x12 << 24);
9129 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
9131 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
9133 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
9135 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
9137 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
9139 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
9140 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
9141 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
9143 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
9144 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
9145 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
9147 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
9150 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
9152 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
9155 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
9157 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
9160 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
9162 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
9165 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
9167 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
9168 tmp
&= ~(0xFF << 16);
9169 tmp
|= (0x1C << 16);
9170 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
9172 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
9173 tmp
&= ~(0xFF << 16);
9174 tmp
|= (0x1C << 16);
9175 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
9177 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
9179 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
9181 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
9183 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
9185 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
9186 tmp
&= ~(0xF << 28);
9188 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
9190 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
9191 tmp
&= ~(0xF << 28);
9193 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
9196 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9197 * Programming" based on the parameters passed:
9198 * - Sequence to enable CLKOUT_DP
9199 * - Sequence to enable CLKOUT_DP without spread
9200 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9202 static void lpt_enable_clkout_dp(struct drm_i915_private
*dev_priv
,
9203 bool with_spread
, bool with_fdi
)
9207 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
9209 if (WARN(HAS_PCH_LPT_LP(dev_priv
) &&
9210 with_fdi
, "LP PCH doesn't have FDI\n"))
9213 mutex_lock(&dev_priv
->sb_lock
);
9215 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
9216 tmp
&= ~SBI_SSCCTL_DISABLE
;
9217 tmp
|= SBI_SSCCTL_PATHALT
;
9218 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9223 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
9224 tmp
&= ~SBI_SSCCTL_PATHALT
;
9225 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9228 lpt_reset_fdi_mphy(dev_priv
);
9229 lpt_program_fdi_mphy(dev_priv
);
9233 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
9234 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
9235 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
9236 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
9238 mutex_unlock(&dev_priv
->sb_lock
);
9241 /* Sequence to disable CLKOUT_DP */
9242 static void lpt_disable_clkout_dp(struct drm_i915_private
*dev_priv
)
9246 mutex_lock(&dev_priv
->sb_lock
);
9248 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
9249 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
9250 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
9251 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
9253 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
9254 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
9255 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
9256 tmp
|= SBI_SSCCTL_PATHALT
;
9257 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9260 tmp
|= SBI_SSCCTL_DISABLE
;
9261 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9264 mutex_unlock(&dev_priv
->sb_lock
);
9267 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9269 static const uint16_t sscdivintphase
[] = {
9270 [BEND_IDX( 50)] = 0x3B23,
9271 [BEND_IDX( 45)] = 0x3B23,
9272 [BEND_IDX( 40)] = 0x3C23,
9273 [BEND_IDX( 35)] = 0x3C23,
9274 [BEND_IDX( 30)] = 0x3D23,
9275 [BEND_IDX( 25)] = 0x3D23,
9276 [BEND_IDX( 20)] = 0x3E23,
9277 [BEND_IDX( 15)] = 0x3E23,
9278 [BEND_IDX( 10)] = 0x3F23,
9279 [BEND_IDX( 5)] = 0x3F23,
9280 [BEND_IDX( 0)] = 0x0025,
9281 [BEND_IDX( -5)] = 0x0025,
9282 [BEND_IDX(-10)] = 0x0125,
9283 [BEND_IDX(-15)] = 0x0125,
9284 [BEND_IDX(-20)] = 0x0225,
9285 [BEND_IDX(-25)] = 0x0225,
9286 [BEND_IDX(-30)] = 0x0325,
9287 [BEND_IDX(-35)] = 0x0325,
9288 [BEND_IDX(-40)] = 0x0425,
9289 [BEND_IDX(-45)] = 0x0425,
9290 [BEND_IDX(-50)] = 0x0525,
9295 * steps -50 to 50 inclusive, in steps of 5
9296 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9297 * change in clock period = -(steps / 10) * 5.787 ps
9299 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
9302 int idx
= BEND_IDX(steps
);
9304 if (WARN_ON(steps
% 5 != 0))
9307 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
9310 mutex_lock(&dev_priv
->sb_lock
);
9312 if (steps
% 10 != 0)
9316 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
9318 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
9320 tmp
|= sscdivintphase
[idx
];
9321 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
9323 mutex_unlock(&dev_priv
->sb_lock
);
9328 static void lpt_init_pch_refclk(struct drm_i915_private
*dev_priv
)
9330 struct intel_encoder
*encoder
;
9331 bool has_vga
= false;
9333 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
9334 switch (encoder
->type
) {
9335 case INTEL_OUTPUT_ANALOG
:
9344 lpt_bend_clkout_dp(dev_priv
, 0);
9345 lpt_enable_clkout_dp(dev_priv
, true, true);
9347 lpt_disable_clkout_dp(dev_priv
);
9352 * Initialize reference clocks when the driver loads
9354 void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
)
9356 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
))
9357 ironlake_init_pch_refclk(dev_priv
);
9358 else if (HAS_PCH_LPT(dev_priv
))
9359 lpt_init_pch_refclk(dev_priv
);
9362 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
9364 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
9365 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9366 int pipe
= intel_crtc
->pipe
;
9371 switch (intel_crtc
->config
->pipe_bpp
) {
9373 val
|= PIPECONF_6BPC
;
9376 val
|= PIPECONF_8BPC
;
9379 val
|= PIPECONF_10BPC
;
9382 val
|= PIPECONF_12BPC
;
9385 /* Case prevented by intel_choose_pipe_bpp_dither. */
9389 if (intel_crtc
->config
->dither
)
9390 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
9392 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
9393 val
|= PIPECONF_INTERLACED_ILK
;
9395 val
|= PIPECONF_PROGRESSIVE
;
9397 if (intel_crtc
->config
->limited_color_range
)
9398 val
|= PIPECONF_COLOR_RANGE_SELECT
;
9400 I915_WRITE(PIPECONF(pipe
), val
);
9401 POSTING_READ(PIPECONF(pipe
));
9404 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
9406 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
9407 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9408 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
9411 if (IS_HASWELL(dev_priv
) && intel_crtc
->config
->dither
)
9412 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
9414 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
9415 val
|= PIPECONF_INTERLACED_ILK
;
9417 val
|= PIPECONF_PROGRESSIVE
;
9419 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
9420 POSTING_READ(PIPECONF(cpu_transcoder
));
9423 static void haswell_set_pipemisc(struct drm_crtc
*crtc
)
9425 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
9426 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9428 if (IS_BROADWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 9) {
9431 switch (intel_crtc
->config
->pipe_bpp
) {
9433 val
|= PIPEMISC_DITHER_6_BPC
;
9436 val
|= PIPEMISC_DITHER_8_BPC
;
9439 val
|= PIPEMISC_DITHER_10_BPC
;
9442 val
|= PIPEMISC_DITHER_12_BPC
;
9445 /* Case prevented by pipe_config_set_bpp. */
9449 if (intel_crtc
->config
->dither
)
9450 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
9452 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
9456 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
9459 * Account for spread spectrum to avoid
9460 * oversubscribing the link. Max center spread
9461 * is 2.5%; use 5% for safety's sake.
9463 u32 bps
= target_clock
* bpp
* 21 / 20;
9464 return DIV_ROUND_UP(bps
, link_bw
* 8);
9467 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
9469 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
9472 static void ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
9473 struct intel_crtc_state
*crtc_state
,
9474 struct dpll
*reduced_clock
)
9476 struct drm_crtc
*crtc
= &intel_crtc
->base
;
9477 struct drm_device
*dev
= crtc
->dev
;
9478 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9482 /* Enable autotuning of the PLL clock (if permissible) */
9484 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9485 if ((intel_panel_use_ssc(dev_priv
) &&
9486 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
9487 (HAS_PCH_IBX(dev_priv
) && intel_is_dual_link_lvds(dev
)))
9489 } else if (crtc_state
->sdvo_tv_clock
)
9492 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
9494 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
9497 if (reduced_clock
) {
9498 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
9500 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
9508 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
9509 dpll
|= DPLLB_MODE_LVDS
;
9511 dpll
|= DPLLB_MODE_DAC_SERIAL
;
9513 dpll
|= (crtc_state
->pixel_multiplier
- 1)
9514 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
9516 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
9517 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
9518 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9520 if (intel_crtc_has_dp_encoder(crtc_state
))
9521 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9524 * The high speed IO clock is only really required for
9525 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9526 * possible to share the DPLL between CRT and HDMI. Enabling
9527 * the clock needlessly does no real harm, except use up a
9528 * bit of power potentially.
9530 * We'll limit this to IVB with 3 pipes, since it has only two
9531 * DPLLs and so DPLL sharing is the only way to get three pipes
9532 * driving PCH ports at the same time. On SNB we could do this,
9533 * and potentially avoid enabling the second DPLL, but it's not
9534 * clear if it''s a win or loss power wise. No point in doing
9535 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9537 if (INTEL_INFO(dev_priv
)->num_pipes
== 3 &&
9538 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
))
9539 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9541 /* compute bitmask from p1 value */
9542 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
9544 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
9546 switch (crtc_state
->dpll
.p2
) {
9548 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
9551 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
9554 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
9557 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
9561 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9562 intel_panel_use_ssc(dev_priv
))
9563 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
9565 dpll
|= PLL_REF_INPUT_DREFCLK
;
9567 dpll
|= DPLL_VCO_ENABLE
;
9569 crtc_state
->dpll_hw_state
.dpll
= dpll
;
9570 crtc_state
->dpll_hw_state
.fp0
= fp
;
9571 crtc_state
->dpll_hw_state
.fp1
= fp2
;
9574 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
9575 struct intel_crtc_state
*crtc_state
)
9577 struct drm_device
*dev
= crtc
->base
.dev
;
9578 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9579 struct dpll reduced_clock
;
9580 bool has_reduced_clock
= false;
9581 struct intel_shared_dpll
*pll
;
9582 const struct intel_limit
*limit
;
9583 int refclk
= 120000;
9585 memset(&crtc_state
->dpll_hw_state
, 0,
9586 sizeof(crtc_state
->dpll_hw_state
));
9588 crtc
->lowfreq_avail
= false;
9590 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9591 if (!crtc_state
->has_pch_encoder
)
9594 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9595 if (intel_panel_use_ssc(dev_priv
)) {
9596 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9597 dev_priv
->vbt
.lvds_ssc_freq
);
9598 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
9601 if (intel_is_dual_link_lvds(dev
)) {
9602 if (refclk
== 100000)
9603 limit
= &intel_limits_ironlake_dual_lvds_100m
;
9605 limit
= &intel_limits_ironlake_dual_lvds
;
9607 if (refclk
== 100000)
9608 limit
= &intel_limits_ironlake_single_lvds_100m
;
9610 limit
= &intel_limits_ironlake_single_lvds
;
9613 limit
= &intel_limits_ironlake_dac
;
9616 if (!crtc_state
->clock_set
&&
9617 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
9618 refclk
, NULL
, &crtc_state
->dpll
)) {
9619 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9623 ironlake_compute_dpll(crtc
, crtc_state
,
9624 has_reduced_clock
? &reduced_clock
: NULL
);
9626 pll
= intel_get_shared_dpll(crtc
, crtc_state
, NULL
);
9628 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9629 pipe_name(crtc
->pipe
));
9633 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9635 crtc
->lowfreq_avail
= true;
9640 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9641 struct intel_link_m_n
*m_n
)
9643 struct drm_device
*dev
= crtc
->base
.dev
;
9644 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9645 enum pipe pipe
= crtc
->pipe
;
9647 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9648 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9649 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9651 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9652 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9653 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9656 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9657 enum transcoder transcoder
,
9658 struct intel_link_m_n
*m_n
,
9659 struct intel_link_m_n
*m2_n2
)
9661 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9662 enum pipe pipe
= crtc
->pipe
;
9664 if (INTEL_GEN(dev_priv
) >= 5) {
9665 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9666 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9667 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9669 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9670 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9671 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9672 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9673 * gen < 8) and if DRRS is supported (to make sure the
9674 * registers are not unnecessarily read).
9676 if (m2_n2
&& INTEL_GEN(dev_priv
) < 8 &&
9677 crtc
->config
->has_drrs
) {
9678 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9679 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9680 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9682 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9683 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9684 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9687 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9688 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9689 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9691 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9692 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9693 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9697 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9698 struct intel_crtc_state
*pipe_config
)
9700 if (pipe_config
->has_pch_encoder
)
9701 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9703 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9704 &pipe_config
->dp_m_n
,
9705 &pipe_config
->dp_m2_n2
);
9708 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9709 struct intel_crtc_state
*pipe_config
)
9711 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9712 &pipe_config
->fdi_m_n
, NULL
);
9715 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9716 struct intel_crtc_state
*pipe_config
)
9718 struct drm_device
*dev
= crtc
->base
.dev
;
9719 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9720 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9721 uint32_t ps_ctrl
= 0;
9725 /* find scaler attached to this pipe */
9726 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9727 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9728 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9730 pipe_config
->pch_pfit
.enabled
= true;
9731 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9732 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9737 scaler_state
->scaler_id
= id
;
9739 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9741 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9746 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9747 struct intel_initial_plane_config
*plane_config
)
9749 struct drm_device
*dev
= crtc
->base
.dev
;
9750 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9751 u32 val
, base
, offset
, stride_mult
, tiling
;
9752 int pipe
= crtc
->pipe
;
9753 int fourcc
, pixel_format
;
9754 unsigned int aligned_height
;
9755 struct drm_framebuffer
*fb
;
9756 struct intel_framebuffer
*intel_fb
;
9758 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9760 DRM_DEBUG_KMS("failed to alloc fb\n");
9764 fb
= &intel_fb
->base
;
9768 val
= I915_READ(PLANE_CTL(pipe
, 0));
9769 if (!(val
& PLANE_CTL_ENABLE
))
9772 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9773 fourcc
= skl_format_to_fourcc(pixel_format
,
9774 val
& PLANE_CTL_ORDER_RGBX
,
9775 val
& PLANE_CTL_ALPHA_MASK
);
9776 fb
->format
= drm_format_info(fourcc
);
9778 tiling
= val
& PLANE_CTL_TILED_MASK
;
9780 case PLANE_CTL_TILED_LINEAR
:
9781 fb
->modifier
= DRM_FORMAT_MOD_NONE
;
9783 case PLANE_CTL_TILED_X
:
9784 plane_config
->tiling
= I915_TILING_X
;
9785 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
9787 case PLANE_CTL_TILED_Y
:
9788 fb
->modifier
= I915_FORMAT_MOD_Y_TILED
;
9790 case PLANE_CTL_TILED_YF
:
9791 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED
;
9794 MISSING_CASE(tiling
);
9798 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9799 plane_config
->base
= base
;
9801 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9803 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9804 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9805 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9807 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9808 stride_mult
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
,
9809 fb
->format
->format
);
9810 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9812 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9816 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9818 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9819 pipe_name(pipe
), fb
->width
, fb
->height
,
9820 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
9821 plane_config
->size
);
9823 plane_config
->fb
= intel_fb
;
9830 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9831 struct intel_crtc_state
*pipe_config
)
9833 struct drm_device
*dev
= crtc
->base
.dev
;
9834 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9837 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9839 if (tmp
& PF_ENABLE
) {
9840 pipe_config
->pch_pfit
.enabled
= true;
9841 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9842 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9844 /* We currently do not free assignements of panel fitters on
9845 * ivb/hsw (since we don't use the higher upscaling modes which
9846 * differentiates them) so just WARN about this case for now. */
9847 if (IS_GEN7(dev_priv
)) {
9848 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9849 PF_PIPE_SEL_IVB(crtc
->pipe
));
9855 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9856 struct intel_initial_plane_config
*plane_config
)
9858 struct drm_device
*dev
= crtc
->base
.dev
;
9859 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9860 u32 val
, base
, offset
;
9861 int pipe
= crtc
->pipe
;
9862 int fourcc
, pixel_format
;
9863 unsigned int aligned_height
;
9864 struct drm_framebuffer
*fb
;
9865 struct intel_framebuffer
*intel_fb
;
9867 val
= I915_READ(DSPCNTR(pipe
));
9868 if (!(val
& DISPLAY_PLANE_ENABLE
))
9871 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9873 DRM_DEBUG_KMS("failed to alloc fb\n");
9877 fb
= &intel_fb
->base
;
9881 if (INTEL_GEN(dev_priv
) >= 4) {
9882 if (val
& DISPPLANE_TILED
) {
9883 plane_config
->tiling
= I915_TILING_X
;
9884 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
9888 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9889 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9890 fb
->format
= drm_format_info(fourcc
);
9892 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9893 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
9894 offset
= I915_READ(DSPOFFSET(pipe
));
9896 if (plane_config
->tiling
)
9897 offset
= I915_READ(DSPTILEOFF(pipe
));
9899 offset
= I915_READ(DSPLINOFF(pipe
));
9901 plane_config
->base
= base
;
9903 val
= I915_READ(PIPESRC(pipe
));
9904 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9905 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9907 val
= I915_READ(DSPSTRIDE(pipe
));
9908 fb
->pitches
[0] = val
& 0xffffffc0;
9910 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9914 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9916 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9917 pipe_name(pipe
), fb
->width
, fb
->height
,
9918 fb
->format
->cpp
[0] * 8, base
, fb
->pitches
[0],
9919 plane_config
->size
);
9921 plane_config
->fb
= intel_fb
;
9924 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9925 struct intel_crtc_state
*pipe_config
)
9927 struct drm_device
*dev
= crtc
->base
.dev
;
9928 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9929 enum intel_display_power_domain power_domain
;
9933 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9934 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9937 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9938 pipe_config
->shared_dpll
= NULL
;
9941 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9942 if (!(tmp
& PIPECONF_ENABLE
))
9945 switch (tmp
& PIPECONF_BPC_MASK
) {
9947 pipe_config
->pipe_bpp
= 18;
9950 pipe_config
->pipe_bpp
= 24;
9952 case PIPECONF_10BPC
:
9953 pipe_config
->pipe_bpp
= 30;
9955 case PIPECONF_12BPC
:
9956 pipe_config
->pipe_bpp
= 36;
9962 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9963 pipe_config
->limited_color_range
= true;
9965 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9966 struct intel_shared_dpll
*pll
;
9967 enum intel_dpll_id pll_id
;
9969 pipe_config
->has_pch_encoder
= true;
9971 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9972 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9973 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9975 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9977 if (HAS_PCH_IBX(dev_priv
)) {
9979 * The pipe->pch transcoder and pch transcoder->pll
9982 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9984 tmp
= I915_READ(PCH_DPLL_SEL
);
9985 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9986 pll_id
= DPLL_ID_PCH_PLL_B
;
9988 pll_id
= DPLL_ID_PCH_PLL_A
;
9991 pipe_config
->shared_dpll
=
9992 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
9993 pll
= pipe_config
->shared_dpll
;
9995 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
9996 &pipe_config
->dpll_hw_state
));
9998 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9999 pipe_config
->pixel_multiplier
=
10000 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
10001 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
10003 ironlake_pch_clock_get(crtc
, pipe_config
);
10005 pipe_config
->pixel_multiplier
= 1;
10008 intel_get_pipe_timings(crtc
, pipe_config
);
10009 intel_get_pipe_src_size(crtc
, pipe_config
);
10011 ironlake_get_pfit_config(crtc
, pipe_config
);
10016 intel_display_power_put(dev_priv
, power_domain
);
10021 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
10023 struct drm_device
*dev
= &dev_priv
->drm
;
10024 struct intel_crtc
*crtc
;
10026 for_each_intel_crtc(dev
, crtc
)
10027 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
10028 pipe_name(crtc
->pipe
));
10030 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
10031 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
10032 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
10033 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
10034 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON
, "Panel power on\n");
10035 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
10036 "CPU PWM1 enabled\n");
10037 if (IS_HASWELL(dev_priv
))
10038 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
10039 "CPU PWM2 enabled\n");
10040 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
10041 "PCH PWM1 enabled\n");
10042 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
10043 "Utility pin enabled\n");
10044 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
10047 * In theory we can still leave IRQs enabled, as long as only the HPD
10048 * interrupts remain enabled. We used to check for that, but since it's
10049 * gen-specific and since we only disable LCPLL after we fully disable
10050 * the interrupts, the check below should be enough.
10052 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
10055 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
10057 if (IS_HASWELL(dev_priv
))
10058 return I915_READ(D_COMP_HSW
);
10060 return I915_READ(D_COMP_BDW
);
10063 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
10065 if (IS_HASWELL(dev_priv
)) {
10066 mutex_lock(&dev_priv
->rps
.hw_lock
);
10067 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
10069 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10070 mutex_unlock(&dev_priv
->rps
.hw_lock
);
10072 I915_WRITE(D_COMP_BDW
, val
);
10073 POSTING_READ(D_COMP_BDW
);
10078 * This function implements pieces of two sequences from BSpec:
10079 * - Sequence for display software to disable LCPLL
10080 * - Sequence for display software to allow package C8+
10081 * The steps implemented here are just the steps that actually touch the LCPLL
10082 * register. Callers should take care of disabling all the display engine
10083 * functions, doing the mode unset, fixing interrupts, etc.
10085 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
10086 bool switch_to_fclk
, bool allow_power_down
)
10090 assert_can_disable_lcpll(dev_priv
);
10092 val
= I915_READ(LCPLL_CTL
);
10094 if (switch_to_fclk
) {
10095 val
|= LCPLL_CD_SOURCE_FCLK
;
10096 I915_WRITE(LCPLL_CTL
, val
);
10098 if (wait_for_us(I915_READ(LCPLL_CTL
) &
10099 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
10100 DRM_ERROR("Switching to FCLK failed\n");
10102 val
= I915_READ(LCPLL_CTL
);
10105 val
|= LCPLL_PLL_DISABLE
;
10106 I915_WRITE(LCPLL_CTL
, val
);
10107 POSTING_READ(LCPLL_CTL
);
10109 if (intel_wait_for_register(dev_priv
, LCPLL_CTL
, LCPLL_PLL_LOCK
, 0, 1))
10110 DRM_ERROR("LCPLL still locked\n");
10112 val
= hsw_read_dcomp(dev_priv
);
10113 val
|= D_COMP_COMP_DISABLE
;
10114 hsw_write_dcomp(dev_priv
, val
);
10117 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
10119 DRM_ERROR("D_COMP RCOMP still in progress\n");
10121 if (allow_power_down
) {
10122 val
= I915_READ(LCPLL_CTL
);
10123 val
|= LCPLL_POWER_DOWN_ALLOW
;
10124 I915_WRITE(LCPLL_CTL
, val
);
10125 POSTING_READ(LCPLL_CTL
);
10130 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10133 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
10137 val
= I915_READ(LCPLL_CTL
);
10139 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
10140 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
10144 * Make sure we're not on PC8 state before disabling PC8, otherwise
10145 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10147 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
10149 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
10150 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
10151 I915_WRITE(LCPLL_CTL
, val
);
10152 POSTING_READ(LCPLL_CTL
);
10155 val
= hsw_read_dcomp(dev_priv
);
10156 val
|= D_COMP_COMP_FORCE
;
10157 val
&= ~D_COMP_COMP_DISABLE
;
10158 hsw_write_dcomp(dev_priv
, val
);
10160 val
= I915_READ(LCPLL_CTL
);
10161 val
&= ~LCPLL_PLL_DISABLE
;
10162 I915_WRITE(LCPLL_CTL
, val
);
10164 if (intel_wait_for_register(dev_priv
,
10165 LCPLL_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
10167 DRM_ERROR("LCPLL not locked yet\n");
10169 if (val
& LCPLL_CD_SOURCE_FCLK
) {
10170 val
= I915_READ(LCPLL_CTL
);
10171 val
&= ~LCPLL_CD_SOURCE_FCLK
;
10172 I915_WRITE(LCPLL_CTL
, val
);
10174 if (wait_for_us((I915_READ(LCPLL_CTL
) &
10175 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
10176 DRM_ERROR("Switching back to LCPLL failed\n");
10179 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
10180 intel_update_cdclk(dev_priv
);
10184 * Package states C8 and deeper are really deep PC states that can only be
10185 * reached when all the devices on the system allow it, so even if the graphics
10186 * device allows PC8+, it doesn't mean the system will actually get to these
10187 * states. Our driver only allows PC8+ when going into runtime PM.
10189 * The requirements for PC8+ are that all the outputs are disabled, the power
10190 * well is disabled and most interrupts are disabled, and these are also
10191 * requirements for runtime PM. When these conditions are met, we manually do
10192 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10193 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10194 * hang the machine.
10196 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10197 * the state of some registers, so when we come back from PC8+ we need to
10198 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10199 * need to take care of the registers kept by RC6. Notice that this happens even
10200 * if we don't put the device in PCI D3 state (which is what currently happens
10201 * because of the runtime PM support).
10203 * For more, read "Display Sequences for Package C8" on the hardware
10206 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
10210 DRM_DEBUG_KMS("Enabling package C8+\n");
10212 if (HAS_PCH_LPT_LP(dev_priv
)) {
10213 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
10214 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
10215 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
10218 lpt_disable_clkout_dp(dev_priv
);
10219 hsw_disable_lcpll(dev_priv
, true, true);
10222 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
10226 DRM_DEBUG_KMS("Disabling package C8+\n");
10228 hsw_restore_lcpll(dev_priv
);
10229 lpt_init_pch_refclk(dev_priv
);
10231 if (HAS_PCH_LPT_LP(dev_priv
)) {
10232 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
10233 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
10234 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
10238 static void bxt_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
10240 struct drm_device
*dev
= old_state
->dev
;
10241 struct intel_atomic_state
*old_intel_state
=
10242 to_intel_atomic_state(old_state
);
10243 unsigned int req_cdclk
= old_intel_state
->dev_cdclk
;
10245 bxt_set_cdclk(to_i915(dev
), req_cdclk
);
10248 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state
*crtc_state
,
10251 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
10253 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10254 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
10255 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
10257 /* BSpec says "Do not use DisplayPort with CDCLK less than
10258 * 432 MHz, audio enabled, port width x4, and link rate
10259 * HBR2 (5.4 GHz), or else there may be audio corruption or
10260 * screen corruption."
10262 if (intel_crtc_has_dp_encoder(crtc_state
) &&
10263 crtc_state
->has_audio
&&
10264 crtc_state
->port_clock
>= 540000 &&
10265 crtc_state
->lane_count
== 4)
10266 pixel_rate
= max(432000, pixel_rate
);
10271 /* compute the max rate for new configuration */
10272 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
)
10274 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
10275 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
10276 struct drm_crtc
*crtc
;
10277 struct drm_crtc_state
*cstate
;
10278 struct intel_crtc_state
*crtc_state
;
10279 unsigned max_pixel_rate
= 0, i
;
10282 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
10283 sizeof(intel_state
->min_pixclk
));
10285 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
10288 crtc_state
= to_intel_crtc_state(cstate
);
10289 if (!crtc_state
->base
.enable
) {
10290 intel_state
->min_pixclk
[i
] = 0;
10294 pixel_rate
= ilk_pipe_pixel_rate(crtc_state
);
10296 if (IS_BROADWELL(dev_priv
) || IS_GEN9(dev_priv
))
10297 pixel_rate
= bdw_adjust_min_pipe_pixel_rate(crtc_state
,
10300 intel_state
->min_pixclk
[i
] = pixel_rate
;
10303 for_each_pipe(dev_priv
, pipe
)
10304 max_pixel_rate
= max(intel_state
->min_pixclk
[pipe
], max_pixel_rate
);
10306 return max_pixel_rate
;
10309 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
10311 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10312 uint32_t val
, data
;
10315 if (WARN((I915_READ(LCPLL_CTL
) &
10316 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
10317 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
10318 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
10319 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
10320 "trying to change cdclk frequency with cdclk not enabled\n"))
10323 mutex_lock(&dev_priv
->rps
.hw_lock
);
10324 ret
= sandybridge_pcode_write(dev_priv
,
10325 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
10326 mutex_unlock(&dev_priv
->rps
.hw_lock
);
10328 DRM_ERROR("failed to inform pcode about cdclk change\n");
10332 val
= I915_READ(LCPLL_CTL
);
10333 val
|= LCPLL_CD_SOURCE_FCLK
;
10334 I915_WRITE(LCPLL_CTL
, val
);
10336 if (wait_for_us(I915_READ(LCPLL_CTL
) &
10337 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
10338 DRM_ERROR("Switching to FCLK failed\n");
10340 val
= I915_READ(LCPLL_CTL
);
10341 val
&= ~LCPLL_CLK_FREQ_MASK
;
10345 val
|= LCPLL_CLK_FREQ_450
;
10349 val
|= LCPLL_CLK_FREQ_54O_BDW
;
10353 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
10357 val
|= LCPLL_CLK_FREQ_675_BDW
;
10361 WARN(1, "invalid cdclk frequency\n");
10365 I915_WRITE(LCPLL_CTL
, val
);
10367 val
= I915_READ(LCPLL_CTL
);
10368 val
&= ~LCPLL_CD_SOURCE_FCLK
;
10369 I915_WRITE(LCPLL_CTL
, val
);
10371 if (wait_for_us((I915_READ(LCPLL_CTL
) &
10372 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
10373 DRM_ERROR("Switching back to LCPLL failed\n");
10375 mutex_lock(&dev_priv
->rps
.hw_lock
);
10376 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
10377 mutex_unlock(&dev_priv
->rps
.hw_lock
);
10379 I915_WRITE(CDCLK_FREQ
, DIV_ROUND_CLOSEST(cdclk
, 1000) - 1);
10381 intel_update_cdclk(dev_priv
);
10383 WARN(cdclk
!= dev_priv
->cdclk_freq
,
10384 "cdclk requested %d kHz but got %d kHz\n",
10385 cdclk
, dev_priv
->cdclk_freq
);
10388 static int broadwell_calc_cdclk(int max_pixclk
)
10390 if (max_pixclk
> 540000)
10392 else if (max_pixclk
> 450000)
10394 else if (max_pixclk
> 337500)
10400 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state
*state
)
10402 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
10403 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
10404 int max_pixclk
= ilk_max_pixel_rate(state
);
10408 * FIXME should also account for plane ratio
10409 * once 64bpp pixel formats are supported.
10411 cdclk
= broadwell_calc_cdclk(max_pixclk
);
10413 if (cdclk
> dev_priv
->max_cdclk_freq
) {
10414 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10415 cdclk
, dev_priv
->max_cdclk_freq
);
10419 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
10420 if (!intel_state
->active_crtcs
)
10421 intel_state
->dev_cdclk
= broadwell_calc_cdclk(0);
10426 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
10428 struct drm_device
*dev
= old_state
->dev
;
10429 struct intel_atomic_state
*old_intel_state
=
10430 to_intel_atomic_state(old_state
);
10431 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
10433 broadwell_set_cdclk(dev
, req_cdclk
);
10436 static int skl_modeset_calc_cdclk(struct drm_atomic_state
*state
)
10438 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
10439 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
10440 const int max_pixclk
= ilk_max_pixel_rate(state
);
10441 int vco
= intel_state
->cdclk_pll_vco
;
10445 * FIXME should also account for plane ratio
10446 * once 64bpp pixel formats are supported.
10448 cdclk
= skl_calc_cdclk(max_pixclk
, vco
);
10451 * FIXME move the cdclk caclulation to
10452 * compute_config() so we can fail gracegully.
10454 if (cdclk
> dev_priv
->max_cdclk_freq
) {
10455 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10456 cdclk
, dev_priv
->max_cdclk_freq
);
10457 cdclk
= dev_priv
->max_cdclk_freq
;
10460 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
10461 if (!intel_state
->active_crtcs
)
10462 intel_state
->dev_cdclk
= skl_calc_cdclk(0, vco
);
10467 static void skl_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
10469 struct drm_i915_private
*dev_priv
= to_i915(old_state
->dev
);
10470 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(old_state
);
10471 unsigned int req_cdclk
= intel_state
->dev_cdclk
;
10472 unsigned int req_vco
= intel_state
->cdclk_pll_vco
;
10474 skl_set_cdclk(dev_priv
, req_cdclk
, req_vco
);
10477 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
10478 struct intel_crtc_state
*crtc_state
)
10480 if (!intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
)) {
10481 if (!intel_ddi_pll_select(crtc
, crtc_state
))
10485 crtc
->lowfreq_avail
= false;
10490 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
10492 struct intel_crtc_state
*pipe_config
)
10494 enum intel_dpll_id id
;
10498 id
= DPLL_ID_SKL_DPLL0
;
10501 id
= DPLL_ID_SKL_DPLL1
;
10504 id
= DPLL_ID_SKL_DPLL2
;
10507 DRM_ERROR("Incorrect port type\n");
10511 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
10514 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
10516 struct intel_crtc_state
*pipe_config
)
10518 enum intel_dpll_id id
;
10521 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
10522 id
= temp
>> (port
* 3 + 1);
10524 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL3
))
10527 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
10530 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
10532 struct intel_crtc_state
*pipe_config
)
10534 enum intel_dpll_id id
;
10535 uint32_t ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
10537 switch (ddi_pll_sel
) {
10538 case PORT_CLK_SEL_WRPLL1
:
10539 id
= DPLL_ID_WRPLL1
;
10541 case PORT_CLK_SEL_WRPLL2
:
10542 id
= DPLL_ID_WRPLL2
;
10544 case PORT_CLK_SEL_SPLL
:
10547 case PORT_CLK_SEL_LCPLL_810
:
10548 id
= DPLL_ID_LCPLL_810
;
10550 case PORT_CLK_SEL_LCPLL_1350
:
10551 id
= DPLL_ID_LCPLL_1350
;
10553 case PORT_CLK_SEL_LCPLL_2700
:
10554 id
= DPLL_ID_LCPLL_2700
;
10557 MISSING_CASE(ddi_pll_sel
);
10559 case PORT_CLK_SEL_NONE
:
10563 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
10566 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
10567 struct intel_crtc_state
*pipe_config
,
10568 unsigned long *power_domain_mask
)
10570 struct drm_device
*dev
= crtc
->base
.dev
;
10571 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10572 enum intel_display_power_domain power_domain
;
10576 * The pipe->transcoder mapping is fixed with the exception of the eDP
10577 * transcoder handled below.
10579 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
10582 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10583 * consistency and less surprising code; it's in always on power).
10585 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
10586 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
10587 enum pipe trans_edp_pipe
;
10588 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
10590 WARN(1, "unknown pipe linked to edp transcoder\n");
10591 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
10592 case TRANS_DDI_EDP_INPUT_A_ON
:
10593 trans_edp_pipe
= PIPE_A
;
10595 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
10596 trans_edp_pipe
= PIPE_B
;
10598 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
10599 trans_edp_pipe
= PIPE_C
;
10603 if (trans_edp_pipe
== crtc
->pipe
)
10604 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
10607 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
10608 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10610 *power_domain_mask
|= BIT(power_domain
);
10612 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
10614 return tmp
& PIPECONF_ENABLE
;
10617 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
10618 struct intel_crtc_state
*pipe_config
,
10619 unsigned long *power_domain_mask
)
10621 struct drm_device
*dev
= crtc
->base
.dev
;
10622 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10623 enum intel_display_power_domain power_domain
;
10625 enum transcoder cpu_transcoder
;
10628 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
10629 if (port
== PORT_A
)
10630 cpu_transcoder
= TRANSCODER_DSI_A
;
10632 cpu_transcoder
= TRANSCODER_DSI_C
;
10634 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
10635 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10637 *power_domain_mask
|= BIT(power_domain
);
10640 * The PLL needs to be enabled with a valid divider
10641 * configuration, otherwise accessing DSI registers will hang
10642 * the machine. See BSpec North Display Engine
10643 * registers/MIPI[BXT]. We can break out here early, since we
10644 * need the same DSI PLL to be enabled for both DSI ports.
10646 if (!intel_dsi_pll_is_enabled(dev_priv
))
10649 /* XXX: this works for video mode only */
10650 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
10651 if (!(tmp
& DPI_ENABLE
))
10654 tmp
= I915_READ(MIPI_CTRL(port
));
10655 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
10658 pipe_config
->cpu_transcoder
= cpu_transcoder
;
10662 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
10665 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
10666 struct intel_crtc_state
*pipe_config
)
10668 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10669 struct intel_shared_dpll
*pll
;
10673 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
10675 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
10677 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
10678 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10679 else if (IS_GEN9_LP(dev_priv
))
10680 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
10682 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
10684 pll
= pipe_config
->shared_dpll
;
10686 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
10687 &pipe_config
->dpll_hw_state
));
10691 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10692 * DDI E. So just check whether this pipe is wired to DDI E and whether
10693 * the PCH transcoder is on.
10695 if (INTEL_GEN(dev_priv
) < 9 &&
10696 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
10697 pipe_config
->has_pch_encoder
= true;
10699 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
10700 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
10701 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
10703 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
10707 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
10708 struct intel_crtc_state
*pipe_config
)
10710 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10711 enum intel_display_power_domain power_domain
;
10712 unsigned long power_domain_mask
;
10715 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
10716 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10718 power_domain_mask
= BIT(power_domain
);
10720 pipe_config
->shared_dpll
= NULL
;
10722 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &power_domain_mask
);
10724 if (IS_GEN9_LP(dev_priv
) &&
10725 bxt_get_dsi_transcoder_state(crtc
, pipe_config
, &power_domain_mask
)) {
10733 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10734 haswell_get_ddi_port_state(crtc
, pipe_config
);
10735 intel_get_pipe_timings(crtc
, pipe_config
);
10738 intel_get_pipe_src_size(crtc
, pipe_config
);
10740 pipe_config
->gamma_mode
=
10741 I915_READ(GAMMA_MODE(crtc
->pipe
)) & GAMMA_MODE_MODE_MASK
;
10743 if (INTEL_GEN(dev_priv
) >= 9) {
10744 intel_crtc_init_scalers(crtc
, pipe_config
);
10746 pipe_config
->scaler_state
.scaler_id
= -1;
10747 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
10750 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
10751 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
10752 power_domain_mask
|= BIT(power_domain
);
10753 if (INTEL_GEN(dev_priv
) >= 9)
10754 skylake_get_pfit_config(crtc
, pipe_config
);
10756 ironlake_get_pfit_config(crtc
, pipe_config
);
10759 if (IS_HASWELL(dev_priv
))
10760 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
10761 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
10763 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10764 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10765 pipe_config
->pixel_multiplier
=
10766 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10768 pipe_config
->pixel_multiplier
= 1;
10772 for_each_power_domain(power_domain
, power_domain_mask
)
10773 intel_display_power_put(dev_priv
, power_domain
);
10778 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10779 const struct intel_plane_state
*plane_state
)
10781 struct drm_device
*dev
= crtc
->dev
;
10782 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10783 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10784 uint32_t cntl
= 0, size
= 0;
10786 if (plane_state
&& plane_state
->base
.visible
) {
10787 unsigned int width
= plane_state
->base
.crtc_w
;
10788 unsigned int height
= plane_state
->base
.crtc_h
;
10789 unsigned int stride
= roundup_pow_of_two(width
) * 4;
10793 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10804 cntl
|= CURSOR_ENABLE
|
10805 CURSOR_GAMMA_ENABLE
|
10806 CURSOR_FORMAT_ARGB
|
10807 CURSOR_STRIDE(stride
);
10809 size
= (height
<< 12) | width
;
10812 if (intel_crtc
->cursor_cntl
!= 0 &&
10813 (intel_crtc
->cursor_base
!= base
||
10814 intel_crtc
->cursor_size
!= size
||
10815 intel_crtc
->cursor_cntl
!= cntl
)) {
10816 /* On these chipsets we can only modify the base/size/stride
10817 * whilst the cursor is disabled.
10819 I915_WRITE(CURCNTR(PIPE_A
), 0);
10820 POSTING_READ(CURCNTR(PIPE_A
));
10821 intel_crtc
->cursor_cntl
= 0;
10824 if (intel_crtc
->cursor_base
!= base
) {
10825 I915_WRITE(CURBASE(PIPE_A
), base
);
10826 intel_crtc
->cursor_base
= base
;
10829 if (intel_crtc
->cursor_size
!= size
) {
10830 I915_WRITE(CURSIZE
, size
);
10831 intel_crtc
->cursor_size
= size
;
10834 if (intel_crtc
->cursor_cntl
!= cntl
) {
10835 I915_WRITE(CURCNTR(PIPE_A
), cntl
);
10836 POSTING_READ(CURCNTR(PIPE_A
));
10837 intel_crtc
->cursor_cntl
= cntl
;
10841 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10842 const struct intel_plane_state
*plane_state
)
10844 struct drm_device
*dev
= crtc
->dev
;
10845 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10846 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10847 int pipe
= intel_crtc
->pipe
;
10850 if (plane_state
&& plane_state
->base
.visible
) {
10851 cntl
= MCURSOR_GAMMA_ENABLE
;
10852 switch (plane_state
->base
.crtc_w
) {
10854 cntl
|= CURSOR_MODE_64_ARGB_AX
;
10857 cntl
|= CURSOR_MODE_128_ARGB_AX
;
10860 cntl
|= CURSOR_MODE_256_ARGB_AX
;
10863 MISSING_CASE(plane_state
->base
.crtc_w
);
10866 cntl
|= pipe
<< 28; /* Connect to correct pipe */
10868 if (HAS_DDI(dev_priv
))
10869 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
10871 if (plane_state
->base
.rotation
& DRM_ROTATE_180
)
10872 cntl
|= CURSOR_ROTATE_180
;
10875 if (intel_crtc
->cursor_cntl
!= cntl
) {
10876 I915_WRITE(CURCNTR(pipe
), cntl
);
10877 POSTING_READ(CURCNTR(pipe
));
10878 intel_crtc
->cursor_cntl
= cntl
;
10881 /* and commit changes on next vblank */
10882 I915_WRITE(CURBASE(pipe
), base
);
10883 POSTING_READ(CURBASE(pipe
));
10885 intel_crtc
->cursor_base
= base
;
10888 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10889 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
10890 const struct intel_plane_state
*plane_state
)
10892 struct drm_device
*dev
= crtc
->dev
;
10893 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10894 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10895 int pipe
= intel_crtc
->pipe
;
10896 u32 base
= intel_crtc
->cursor_addr
;
10900 int x
= plane_state
->base
.crtc_x
;
10901 int y
= plane_state
->base
.crtc_y
;
10904 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10907 pos
|= x
<< CURSOR_X_SHIFT
;
10910 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10913 pos
|= y
<< CURSOR_Y_SHIFT
;
10915 /* ILK+ do this automagically */
10916 if (HAS_GMCH_DISPLAY(dev_priv
) &&
10917 plane_state
->base
.rotation
& DRM_ROTATE_180
) {
10918 base
+= (plane_state
->base
.crtc_h
*
10919 plane_state
->base
.crtc_w
- 1) * 4;
10923 I915_WRITE(CURPOS(pipe
), pos
);
10925 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
10926 i845_update_cursor(crtc
, base
, plane_state
);
10928 i9xx_update_cursor(crtc
, base
, plane_state
);
10931 static bool cursor_size_ok(struct drm_i915_private
*dev_priv
,
10932 uint32_t width
, uint32_t height
)
10934 if (width
== 0 || height
== 0)
10938 * 845g/865g are special in that they are only limited by
10939 * the width of their cursors, the height is arbitrary up to
10940 * the precision of the register. Everything else requires
10941 * square cursors, limited to a few power-of-two sizes.
10943 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
10944 if ((width
& 63) != 0)
10947 if (width
> (IS_I845G(dev_priv
) ? 64 : 512))
10953 switch (width
| height
) {
10956 if (IS_GEN2(dev_priv
))
10968 /* VESA 640x480x72Hz mode to set on the pipe */
10969 static struct drm_display_mode load_detect_mode
= {
10970 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10971 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10974 struct drm_framebuffer
*
10975 __intel_framebuffer_create(struct drm_device
*dev
,
10976 struct drm_mode_fb_cmd2
*mode_cmd
,
10977 struct drm_i915_gem_object
*obj
)
10979 struct intel_framebuffer
*intel_fb
;
10982 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10984 return ERR_PTR(-ENOMEM
);
10986 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10990 return &intel_fb
->base
;
10994 return ERR_PTR(ret
);
10997 static struct drm_framebuffer
*
10998 intel_framebuffer_create(struct drm_device
*dev
,
10999 struct drm_mode_fb_cmd2
*mode_cmd
,
11000 struct drm_i915_gem_object
*obj
)
11002 struct drm_framebuffer
*fb
;
11005 ret
= i915_mutex_lock_interruptible(dev
);
11007 return ERR_PTR(ret
);
11008 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
11009 mutex_unlock(&dev
->struct_mutex
);
11015 intel_framebuffer_pitch_for_width(int width
, int bpp
)
11017 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
11018 return ALIGN(pitch
, 64);
11022 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
11024 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
11025 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
11028 static struct drm_framebuffer
*
11029 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
11030 struct drm_display_mode
*mode
,
11031 int depth
, int bpp
)
11033 struct drm_framebuffer
*fb
;
11034 struct drm_i915_gem_object
*obj
;
11035 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
11037 obj
= i915_gem_object_create(to_i915(dev
),
11038 intel_framebuffer_size_for_mode(mode
, bpp
));
11040 return ERR_CAST(obj
);
11042 mode_cmd
.width
= mode
->hdisplay
;
11043 mode_cmd
.height
= mode
->vdisplay
;
11044 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
11046 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
11048 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
11050 i915_gem_object_put(obj
);
11055 static struct drm_framebuffer
*
11056 mode_fits_in_fbdev(struct drm_device
*dev
,
11057 struct drm_display_mode
*mode
)
11059 #ifdef CONFIG_DRM_FBDEV_EMULATION
11060 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11061 struct drm_i915_gem_object
*obj
;
11062 struct drm_framebuffer
*fb
;
11064 if (!dev_priv
->fbdev
)
11067 if (!dev_priv
->fbdev
->fb
)
11070 obj
= dev_priv
->fbdev
->fb
->obj
;
11073 fb
= &dev_priv
->fbdev
->fb
->base
;
11074 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
11075 fb
->format
->cpp
[0] * 8))
11078 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
11081 drm_framebuffer_reference(fb
);
11088 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
11089 struct drm_crtc
*crtc
,
11090 struct drm_display_mode
*mode
,
11091 struct drm_framebuffer
*fb
,
11094 struct drm_plane_state
*plane_state
;
11095 int hdisplay
, vdisplay
;
11098 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
11099 if (IS_ERR(plane_state
))
11100 return PTR_ERR(plane_state
);
11103 drm_mode_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
11105 hdisplay
= vdisplay
= 0;
11107 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
11110 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11111 plane_state
->crtc_x
= 0;
11112 plane_state
->crtc_y
= 0;
11113 plane_state
->crtc_w
= hdisplay
;
11114 plane_state
->crtc_h
= vdisplay
;
11115 plane_state
->src_x
= x
<< 16;
11116 plane_state
->src_y
= y
<< 16;
11117 plane_state
->src_w
= hdisplay
<< 16;
11118 plane_state
->src_h
= vdisplay
<< 16;
11123 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
11124 struct drm_display_mode
*mode
,
11125 struct intel_load_detect_pipe
*old
,
11126 struct drm_modeset_acquire_ctx
*ctx
)
11128 struct intel_crtc
*intel_crtc
;
11129 struct intel_encoder
*intel_encoder
=
11130 intel_attached_encoder(connector
);
11131 struct drm_crtc
*possible_crtc
;
11132 struct drm_encoder
*encoder
= &intel_encoder
->base
;
11133 struct drm_crtc
*crtc
= NULL
;
11134 struct drm_device
*dev
= encoder
->dev
;
11135 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11136 struct drm_framebuffer
*fb
;
11137 struct drm_mode_config
*config
= &dev
->mode_config
;
11138 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
11139 struct drm_connector_state
*connector_state
;
11140 struct intel_crtc_state
*crtc_state
;
11143 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11144 connector
->base
.id
, connector
->name
,
11145 encoder
->base
.id
, encoder
->name
);
11147 old
->restore_state
= NULL
;
11150 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
11155 * Algorithm gets a little messy:
11157 * - if the connector already has an assigned crtc, use it (but make
11158 * sure it's on first)
11160 * - try to find the first unused crtc that can drive this connector,
11161 * and use that if we find one
11164 /* See if we already have a CRTC for this connector */
11165 if (connector
->state
->crtc
) {
11166 crtc
= connector
->state
->crtc
;
11168 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
11172 /* Make sure the crtc and connector are running */
11176 /* Find an unused one (if possible) */
11177 for_each_crtc(dev
, possible_crtc
) {
11179 if (!(encoder
->possible_crtcs
& (1 << i
)))
11182 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
11186 if (possible_crtc
->state
->enable
) {
11187 drm_modeset_unlock(&possible_crtc
->mutex
);
11191 crtc
= possible_crtc
;
11196 * If we didn't find an unused CRTC, don't use any.
11199 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11204 intel_crtc
= to_intel_crtc(crtc
);
11206 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
11210 state
= drm_atomic_state_alloc(dev
);
11211 restore_state
= drm_atomic_state_alloc(dev
);
11212 if (!state
|| !restore_state
) {
11217 state
->acquire_ctx
= ctx
;
11218 restore_state
->acquire_ctx
= ctx
;
11220 connector_state
= drm_atomic_get_connector_state(state
, connector
);
11221 if (IS_ERR(connector_state
)) {
11222 ret
= PTR_ERR(connector_state
);
11226 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
11230 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
11231 if (IS_ERR(crtc_state
)) {
11232 ret
= PTR_ERR(crtc_state
);
11236 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
11239 mode
= &load_detect_mode
;
11241 /* We need a framebuffer large enough to accommodate all accesses
11242 * that the plane may generate whilst we perform load detection.
11243 * We can not rely on the fbcon either being present (we get called
11244 * during its initialisation to detect all boot displays, or it may
11245 * not even exist) or that it is large enough to satisfy the
11248 fb
= mode_fits_in_fbdev(dev
, mode
);
11250 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11251 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
11253 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11255 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11259 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
11263 drm_framebuffer_unreference(fb
);
11265 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
11269 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
11271 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
11273 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state
, crtc
->primary
));
11275 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
11279 ret
= drm_atomic_commit(state
);
11281 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11285 old
->restore_state
= restore_state
;
11286 drm_atomic_state_put(state
);
11288 /* let the connector get through one full cycle before testing */
11289 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
11294 drm_atomic_state_put(state
);
11297 if (restore_state
) {
11298 drm_atomic_state_put(restore_state
);
11299 restore_state
= NULL
;
11302 if (ret
== -EDEADLK
) {
11303 drm_modeset_backoff(ctx
);
11310 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
11311 struct intel_load_detect_pipe
*old
,
11312 struct drm_modeset_acquire_ctx
*ctx
)
11314 struct intel_encoder
*intel_encoder
=
11315 intel_attached_encoder(connector
);
11316 struct drm_encoder
*encoder
= &intel_encoder
->base
;
11317 struct drm_atomic_state
*state
= old
->restore_state
;
11320 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11321 connector
->base
.id
, connector
->name
,
11322 encoder
->base
.id
, encoder
->name
);
11327 ret
= drm_atomic_helper_commit_duplicated_state(state
, ctx
);
11329 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
11330 drm_atomic_state_put(state
);
11333 static int i9xx_pll_refclk(struct drm_device
*dev
,
11334 const struct intel_crtc_state
*pipe_config
)
11336 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11337 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
11339 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
11340 return dev_priv
->vbt
.lvds_ssc_freq
;
11341 else if (HAS_PCH_SPLIT(dev_priv
))
11343 else if (!IS_GEN2(dev_priv
))
11349 /* Returns the clock of the currently programmed mode of the given pipe. */
11350 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
11351 struct intel_crtc_state
*pipe_config
)
11353 struct drm_device
*dev
= crtc
->base
.dev
;
11354 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11355 int pipe
= pipe_config
->cpu_transcoder
;
11356 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
11360 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
11362 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
11363 fp
= pipe_config
->dpll_hw_state
.fp0
;
11365 fp
= pipe_config
->dpll_hw_state
.fp1
;
11367 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
11368 if (IS_PINEVIEW(dev_priv
)) {
11369 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
11370 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
11372 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
11373 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
11376 if (!IS_GEN2(dev_priv
)) {
11377 if (IS_PINEVIEW(dev_priv
))
11378 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
11379 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
11381 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
11382 DPLL_FPA01_P1_POST_DIV_SHIFT
);
11384 switch (dpll
& DPLL_MODE_MASK
) {
11385 case DPLLB_MODE_DAC_SERIAL
:
11386 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
11389 case DPLLB_MODE_LVDS
:
11390 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
11394 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11395 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
11399 if (IS_PINEVIEW(dev_priv
))
11400 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
11402 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
11404 u32 lvds
= IS_I830(dev_priv
) ? 0 : I915_READ(LVDS
);
11405 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
11408 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
11409 DPLL_FPA01_P1_POST_DIV_SHIFT
);
11411 if (lvds
& LVDS_CLKB_POWER_UP
)
11416 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
11419 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
11420 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
11422 if (dpll
& PLL_P2_DIVIDE_BY_4
)
11428 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
11432 * This value includes pixel_multiplier. We will use
11433 * port_clock to compute adjusted_mode.crtc_clock in the
11434 * encoder's get_config() function.
11436 pipe_config
->port_clock
= port_clock
;
11439 int intel_dotclock_calculate(int link_freq
,
11440 const struct intel_link_m_n
*m_n
)
11443 * The calculation for the data clock is:
11444 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11445 * But we want to avoid losing precison if possible, so:
11446 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11448 * and the link clock is simpler:
11449 * link_clock = (m * link_clock) / n
11455 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
11458 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
11459 struct intel_crtc_state
*pipe_config
)
11461 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11463 /* read out port_clock from the DPLL */
11464 i9xx_crtc_clock_get(crtc
, pipe_config
);
11467 * In case there is an active pipe without active ports,
11468 * we may need some idea for the dotclock anyway.
11469 * Calculate one based on the FDI configuration.
11471 pipe_config
->base
.adjusted_mode
.crtc_clock
=
11472 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
11473 &pipe_config
->fdi_m_n
);
11476 /** Returns the currently programmed mode of the given pipe. */
11477 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
11478 struct drm_crtc
*crtc
)
11480 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11481 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11482 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
11483 struct drm_display_mode
*mode
;
11484 struct intel_crtc_state
*pipe_config
;
11485 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
11486 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
11487 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
11488 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
11489 enum pipe pipe
= intel_crtc
->pipe
;
11491 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
11495 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
11496 if (!pipe_config
) {
11502 * Construct a pipe_config sufficient for getting the clock info
11503 * back out of crtc_clock_get.
11505 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11506 * to use a real value here instead.
11508 pipe_config
->cpu_transcoder
= (enum transcoder
) pipe
;
11509 pipe_config
->pixel_multiplier
= 1;
11510 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
11511 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
11512 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
11513 i9xx_crtc_clock_get(intel_crtc
, pipe_config
);
11515 mode
->clock
= pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
11516 mode
->hdisplay
= (htot
& 0xffff) + 1;
11517 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
11518 mode
->hsync_start
= (hsync
& 0xffff) + 1;
11519 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
11520 mode
->vdisplay
= (vtot
& 0xffff) + 1;
11521 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
11522 mode
->vsync_start
= (vsync
& 0xffff) + 1;
11523 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
11525 drm_mode_set_name(mode
);
11527 kfree(pipe_config
);
11532 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
11534 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11535 struct drm_device
*dev
= crtc
->dev
;
11536 struct intel_flip_work
*work
;
11538 spin_lock_irq(&dev
->event_lock
);
11539 work
= intel_crtc
->flip_work
;
11540 intel_crtc
->flip_work
= NULL
;
11541 spin_unlock_irq(&dev
->event_lock
);
11544 cancel_work_sync(&work
->mmio_work
);
11545 cancel_work_sync(&work
->unpin_work
);
11549 drm_crtc_cleanup(crtc
);
11554 static void intel_unpin_work_fn(struct work_struct
*__work
)
11556 struct intel_flip_work
*work
=
11557 container_of(__work
, struct intel_flip_work
, unpin_work
);
11558 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
11559 struct drm_device
*dev
= crtc
->base
.dev
;
11560 struct drm_plane
*primary
= crtc
->base
.primary
;
11562 if (is_mmio_work(work
))
11563 flush_work(&work
->mmio_work
);
11565 mutex_lock(&dev
->struct_mutex
);
11566 intel_unpin_fb_vma(work
->old_vma
);
11567 i915_gem_object_put(work
->pending_flip_obj
);
11568 mutex_unlock(&dev
->struct_mutex
);
11570 i915_gem_request_put(work
->flip_queued_req
);
11572 intel_frontbuffer_flip_complete(to_i915(dev
),
11573 to_intel_plane(primary
)->frontbuffer_bit
);
11574 intel_fbc_post_update(crtc
);
11575 drm_framebuffer_unreference(work
->old_fb
);
11577 BUG_ON(atomic_read(&crtc
->unpin_work_count
) == 0);
11578 atomic_dec(&crtc
->unpin_work_count
);
11583 /* Is 'a' after or equal to 'b'? */
11584 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
11586 return !((a
- b
) & 0x80000000);
11589 static bool __pageflip_finished_cs(struct intel_crtc
*crtc
,
11590 struct intel_flip_work
*work
)
11592 struct drm_device
*dev
= crtc
->base
.dev
;
11593 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11595 if (abort_flip_on_reset(crtc
))
11599 * The relevant registers doen't exist on pre-ctg.
11600 * As the flip done interrupt doesn't trigger for mmio
11601 * flips on gmch platforms, a flip count check isn't
11602 * really needed there. But since ctg has the registers,
11603 * include it in the check anyway.
11605 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
11609 * BDW signals flip done immediately if the plane
11610 * is disabled, even if the plane enable is already
11611 * armed to occur at the next vblank :(
11615 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11616 * used the same base address. In that case the mmio flip might
11617 * have completed, but the CS hasn't even executed the flip yet.
11619 * A flip count check isn't enough as the CS might have updated
11620 * the base address just after start of vblank, but before we
11621 * managed to process the interrupt. This means we'd complete the
11622 * CS flip too soon.
11624 * Combining both checks should get us a good enough result. It may
11625 * still happen that the CS flip has been executed, but has not
11626 * yet actually completed. But in case the base address is the same
11627 * anyway, we don't really care.
11629 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
11630 crtc
->flip_work
->gtt_offset
&&
11631 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc
->pipe
)),
11632 crtc
->flip_work
->flip_count
);
11636 __pageflip_finished_mmio(struct intel_crtc
*crtc
,
11637 struct intel_flip_work
*work
)
11640 * MMIO work completes when vblank is different from
11641 * flip_queued_vblank.
11643 * Reset counter value doesn't matter, this is handled by
11644 * i915_wait_request finishing early, so no need to handle
11647 return intel_crtc_get_vblank_counter(crtc
) != work
->flip_queued_vblank
;
11651 static bool pageflip_finished(struct intel_crtc
*crtc
,
11652 struct intel_flip_work
*work
)
11654 if (!atomic_read(&work
->pending
))
11659 if (is_mmio_work(work
))
11660 return __pageflip_finished_mmio(crtc
, work
);
11662 return __pageflip_finished_cs(crtc
, work
);
11665 void intel_finish_page_flip_cs(struct drm_i915_private
*dev_priv
, int pipe
)
11667 struct drm_device
*dev
= &dev_priv
->drm
;
11668 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
11669 struct intel_flip_work
*work
;
11670 unsigned long flags
;
11672 /* Ignore early vblank irqs */
11677 * This is called both by irq handlers and the reset code (to complete
11678 * lost pageflips) so needs the full irqsave spinlocks.
11680 spin_lock_irqsave(&dev
->event_lock
, flags
);
11681 work
= crtc
->flip_work
;
11683 if (work
!= NULL
&&
11684 !is_mmio_work(work
) &&
11685 pageflip_finished(crtc
, work
))
11686 page_flip_completed(crtc
);
11688 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11691 void intel_finish_page_flip_mmio(struct drm_i915_private
*dev_priv
, int pipe
)
11693 struct drm_device
*dev
= &dev_priv
->drm
;
11694 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
11695 struct intel_flip_work
*work
;
11696 unsigned long flags
;
11698 /* Ignore early vblank irqs */
11703 * This is called both by irq handlers and the reset code (to complete
11704 * lost pageflips) so needs the full irqsave spinlocks.
11706 spin_lock_irqsave(&dev
->event_lock
, flags
);
11707 work
= crtc
->flip_work
;
11709 if (work
!= NULL
&&
11710 is_mmio_work(work
) &&
11711 pageflip_finished(crtc
, work
))
11712 page_flip_completed(crtc
);
11714 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11717 static inline void intel_mark_page_flip_active(struct intel_crtc
*crtc
,
11718 struct intel_flip_work
*work
)
11720 work
->flip_queued_vblank
= intel_crtc_get_vblank_counter(crtc
);
11722 /* Ensure that the work item is consistent when activating it ... */
11723 smp_mb__before_atomic();
11724 atomic_set(&work
->pending
, 1);
11727 static int intel_gen2_queue_flip(struct drm_device
*dev
,
11728 struct drm_crtc
*crtc
,
11729 struct drm_framebuffer
*fb
,
11730 struct drm_i915_gem_object
*obj
,
11731 struct drm_i915_gem_request
*req
,
11734 struct intel_ring
*ring
= req
->ring
;
11735 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11739 ret
= intel_ring_begin(req
, 6);
11743 /* Can't queue multiple flips, so wait for the previous
11744 * one to finish before executing the next.
11746 if (intel_crtc
->plane
)
11747 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11749 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11750 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
11751 intel_ring_emit(ring
, MI_NOOP
);
11752 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11753 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11754 intel_ring_emit(ring
, fb
->pitches
[0]);
11755 intel_ring_emit(ring
, intel_crtc
->flip_work
->gtt_offset
);
11756 intel_ring_emit(ring
, 0); /* aux display base address, unused */
11761 static int intel_gen3_queue_flip(struct drm_device
*dev
,
11762 struct drm_crtc
*crtc
,
11763 struct drm_framebuffer
*fb
,
11764 struct drm_i915_gem_object
*obj
,
11765 struct drm_i915_gem_request
*req
,
11768 struct intel_ring
*ring
= req
->ring
;
11769 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11773 ret
= intel_ring_begin(req
, 6);
11777 if (intel_crtc
->plane
)
11778 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11780 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11781 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
11782 intel_ring_emit(ring
, MI_NOOP
);
11783 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
11784 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11785 intel_ring_emit(ring
, fb
->pitches
[0]);
11786 intel_ring_emit(ring
, intel_crtc
->flip_work
->gtt_offset
);
11787 intel_ring_emit(ring
, MI_NOOP
);
11792 static int intel_gen4_queue_flip(struct drm_device
*dev
,
11793 struct drm_crtc
*crtc
,
11794 struct drm_framebuffer
*fb
,
11795 struct drm_i915_gem_object
*obj
,
11796 struct drm_i915_gem_request
*req
,
11799 struct intel_ring
*ring
= req
->ring
;
11800 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11801 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11802 uint32_t pf
, pipesrc
;
11805 ret
= intel_ring_begin(req
, 4);
11809 /* i965+ uses the linear or tiled offsets from the
11810 * Display Registers (which do not change across a page-flip)
11811 * so we need only reprogram the base address.
11813 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11814 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11815 intel_ring_emit(ring
, fb
->pitches
[0]);
11816 intel_ring_emit(ring
, intel_crtc
->flip_work
->gtt_offset
|
11817 intel_fb_modifier_to_tiling(fb
->modifier
));
11819 /* XXX Enabling the panel-fitter across page-flip is so far
11820 * untested on non-native modes, so ignore it for now.
11821 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11824 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11825 intel_ring_emit(ring
, pf
| pipesrc
);
11830 static int intel_gen6_queue_flip(struct drm_device
*dev
,
11831 struct drm_crtc
*crtc
,
11832 struct drm_framebuffer
*fb
,
11833 struct drm_i915_gem_object
*obj
,
11834 struct drm_i915_gem_request
*req
,
11837 struct intel_ring
*ring
= req
->ring
;
11838 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11839 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11840 uint32_t pf
, pipesrc
;
11843 ret
= intel_ring_begin(req
, 4);
11847 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11848 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11849 intel_ring_emit(ring
, fb
->pitches
[0] |
11850 intel_fb_modifier_to_tiling(fb
->modifier
));
11851 intel_ring_emit(ring
, intel_crtc
->flip_work
->gtt_offset
);
11853 /* Contrary to the suggestions in the documentation,
11854 * "Enable Panel Fitter" does not seem to be required when page
11855 * flipping with a non-native mode, and worse causes a normal
11857 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11860 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11861 intel_ring_emit(ring
, pf
| pipesrc
);
11866 static int intel_gen7_queue_flip(struct drm_device
*dev
,
11867 struct drm_crtc
*crtc
,
11868 struct drm_framebuffer
*fb
,
11869 struct drm_i915_gem_object
*obj
,
11870 struct drm_i915_gem_request
*req
,
11873 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11874 struct intel_ring
*ring
= req
->ring
;
11875 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11876 uint32_t plane_bit
= 0;
11879 switch (intel_crtc
->plane
) {
11881 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11884 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11887 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11890 WARN_ONCE(1, "unknown plane in flip command\n");
11895 if (req
->engine
->id
== RCS
) {
11898 * On Gen 8, SRM is now taking an extra dword to accommodate
11899 * 48bits addresses, and we need a NOOP for the batch size to
11902 if (IS_GEN8(dev_priv
))
11907 * BSpec MI_DISPLAY_FLIP for IVB:
11908 * "The full packet must be contained within the same cache line."
11910 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11911 * cacheline, if we ever start emitting more commands before
11912 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11913 * then do the cacheline alignment, and finally emit the
11916 ret
= intel_ring_cacheline_align(req
);
11920 ret
= intel_ring_begin(req
, len
);
11924 /* Unmask the flip-done completion message. Note that the bspec says that
11925 * we should do this for both the BCS and RCS, and that we must not unmask
11926 * more than one flip event at any time (or ensure that one flip message
11927 * can be sent by waiting for flip-done prior to queueing new flips).
11928 * Experimentation says that BCS works despite DERRMR masking all
11929 * flip-done completion events and that unmasking all planes at once
11930 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11931 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11933 if (req
->engine
->id
== RCS
) {
11934 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
11935 intel_ring_emit_reg(ring
, DERRMR
);
11936 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11937 DERRMR_PIPEB_PRI_FLIP_DONE
|
11938 DERRMR_PIPEC_PRI_FLIP_DONE
));
11939 if (IS_GEN8(dev_priv
))
11940 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8
|
11941 MI_SRM_LRM_GLOBAL_GTT
);
11943 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM
|
11944 MI_SRM_LRM_GLOBAL_GTT
);
11945 intel_ring_emit_reg(ring
, DERRMR
);
11946 intel_ring_emit(ring
,
11947 i915_ggtt_offset(req
->engine
->scratch
) + 256);
11948 if (IS_GEN8(dev_priv
)) {
11949 intel_ring_emit(ring
, 0);
11950 intel_ring_emit(ring
, MI_NOOP
);
11954 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11955 intel_ring_emit(ring
, fb
->pitches
[0] |
11956 intel_fb_modifier_to_tiling(fb
->modifier
));
11957 intel_ring_emit(ring
, intel_crtc
->flip_work
->gtt_offset
);
11958 intel_ring_emit(ring
, (MI_NOOP
));
11963 static bool use_mmio_flip(struct intel_engine_cs
*engine
,
11964 struct drm_i915_gem_object
*obj
)
11967 * This is not being used for older platforms, because
11968 * non-availability of flip done interrupt forces us to use
11969 * CS flips. Older platforms derive flip done using some clever
11970 * tricks involving the flip_pending status bits and vblank irqs.
11971 * So using MMIO flips there would disrupt this mechanism.
11974 if (engine
== NULL
)
11977 if (INTEL_GEN(engine
->i915
) < 5)
11980 if (i915
.use_mmio_flip
< 0)
11982 else if (i915
.use_mmio_flip
> 0)
11984 else if (i915
.enable_execlists
)
11987 return engine
!= i915_gem_object_last_write_engine(obj
);
11990 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11991 unsigned int rotation
,
11992 struct intel_flip_work
*work
)
11994 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11995 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11996 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11997 const enum pipe pipe
= intel_crtc
->pipe
;
11998 u32 ctl
, stride
= skl_plane_stride(fb
, 0, rotation
);
12000 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
12001 ctl
&= ~PLANE_CTL_TILED_MASK
;
12002 switch (fb
->modifier
) {
12003 case DRM_FORMAT_MOD_NONE
:
12005 case I915_FORMAT_MOD_X_TILED
:
12006 ctl
|= PLANE_CTL_TILED_X
;
12008 case I915_FORMAT_MOD_Y_TILED
:
12009 ctl
|= PLANE_CTL_TILED_Y
;
12011 case I915_FORMAT_MOD_Yf_TILED
:
12012 ctl
|= PLANE_CTL_TILED_YF
;
12015 MISSING_CASE(fb
->modifier
);
12019 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12020 * PLANE_SURF updates, the update is then guaranteed to be atomic.
12022 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
12023 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
12025 I915_WRITE(PLANE_SURF(pipe
, 0), work
->gtt_offset
);
12026 POSTING_READ(PLANE_SURF(pipe
, 0));
12029 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
,
12030 struct intel_flip_work
*work
)
12032 struct drm_device
*dev
= intel_crtc
->base
.dev
;
12033 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12034 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
12035 i915_reg_t reg
= DSPCNTR(intel_crtc
->plane
);
12038 dspcntr
= I915_READ(reg
);
12040 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
12041 dspcntr
|= DISPPLANE_TILED
;
12043 dspcntr
&= ~DISPPLANE_TILED
;
12045 I915_WRITE(reg
, dspcntr
);
12047 I915_WRITE(DSPSURF(intel_crtc
->plane
), work
->gtt_offset
);
12048 POSTING_READ(DSPSURF(intel_crtc
->plane
));
12051 static void intel_mmio_flip_work_func(struct work_struct
*w
)
12053 struct intel_flip_work
*work
=
12054 container_of(w
, struct intel_flip_work
, mmio_work
);
12055 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
12056 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
12057 struct intel_framebuffer
*intel_fb
=
12058 to_intel_framebuffer(crtc
->base
.primary
->fb
);
12059 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12061 WARN_ON(i915_gem_object_wait(obj
, 0, MAX_SCHEDULE_TIMEOUT
, NULL
) < 0);
12063 intel_pipe_update_start(crtc
);
12065 if (INTEL_GEN(dev_priv
) >= 9)
12066 skl_do_mmio_flip(crtc
, work
->rotation
, work
);
12068 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12069 ilk_do_mmio_flip(crtc
, work
);
12071 intel_pipe_update_end(crtc
, work
);
12074 static int intel_default_queue_flip(struct drm_device
*dev
,
12075 struct drm_crtc
*crtc
,
12076 struct drm_framebuffer
*fb
,
12077 struct drm_i915_gem_object
*obj
,
12078 struct drm_i915_gem_request
*req
,
12084 static bool __pageflip_stall_check_cs(struct drm_i915_private
*dev_priv
,
12085 struct intel_crtc
*intel_crtc
,
12086 struct intel_flip_work
*work
)
12090 if (!atomic_read(&work
->pending
))
12095 vblank
= intel_crtc_get_vblank_counter(intel_crtc
);
12096 if (work
->flip_ready_vblank
== 0) {
12097 if (work
->flip_queued_req
&&
12098 !i915_gem_request_completed(work
->flip_queued_req
))
12101 work
->flip_ready_vblank
= vblank
;
12104 if (vblank
- work
->flip_ready_vblank
< 3)
12107 /* Potential stall - if we see that the flip has happened,
12108 * assume a missed interrupt. */
12109 if (INTEL_GEN(dev_priv
) >= 4)
12110 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
12112 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
12114 /* There is a potential issue here with a false positive after a flip
12115 * to the same address. We could address this by checking for a
12116 * non-incrementing frame counter.
12118 return addr
== work
->gtt_offset
;
12121 void intel_check_page_flip(struct drm_i915_private
*dev_priv
, int pipe
)
12123 struct drm_device
*dev
= &dev_priv
->drm
;
12124 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
12125 struct intel_flip_work
*work
;
12127 WARN_ON(!in_interrupt());
12132 spin_lock(&dev
->event_lock
);
12133 work
= crtc
->flip_work
;
12135 if (work
!= NULL
&& !is_mmio_work(work
) &&
12136 __pageflip_stall_check_cs(dev_priv
, crtc
, work
)) {
12138 "Kicking stuck page flip: queued at %d, now %d\n",
12139 work
->flip_queued_vblank
, intel_crtc_get_vblank_counter(crtc
));
12140 page_flip_completed(crtc
);
12144 if (work
!= NULL
&& !is_mmio_work(work
) &&
12145 intel_crtc_get_vblank_counter(crtc
) - work
->flip_queued_vblank
> 1)
12146 intel_queue_rps_boost_for_request(work
->flip_queued_req
);
12147 spin_unlock(&dev
->event_lock
);
12150 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
12151 struct drm_framebuffer
*fb
,
12152 struct drm_pending_vblank_event
*event
,
12153 uint32_t page_flip_flags
)
12155 struct drm_device
*dev
= crtc
->dev
;
12156 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12157 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
12158 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12159 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12160 struct drm_plane
*primary
= crtc
->primary
;
12161 enum pipe pipe
= intel_crtc
->pipe
;
12162 struct intel_flip_work
*work
;
12163 struct intel_engine_cs
*engine
;
12165 struct drm_i915_gem_request
*request
;
12166 struct i915_vma
*vma
;
12170 * drm_mode_page_flip_ioctl() should already catch this, but double
12171 * check to be safe. In the future we may enable pageflipping from
12172 * a disabled primary plane.
12174 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
12177 /* Can't change pixel format via MI display flips. */
12178 if (fb
->format
!= crtc
->primary
->fb
->format
)
12182 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12183 * Note that pitch changes could also affect these register.
12185 if (INTEL_GEN(dev_priv
) > 3 &&
12186 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
12187 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
12190 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
12193 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
12197 work
->event
= event
;
12199 work
->old_fb
= old_fb
;
12200 INIT_WORK(&work
->unpin_work
, intel_unpin_work_fn
);
12202 ret
= drm_crtc_vblank_get(crtc
);
12206 /* We borrow the event spin lock for protecting flip_work */
12207 spin_lock_irq(&dev
->event_lock
);
12208 if (intel_crtc
->flip_work
) {
12209 /* Before declaring the flip queue wedged, check if
12210 * the hardware completed the operation behind our backs.
12212 if (pageflip_finished(intel_crtc
, intel_crtc
->flip_work
)) {
12213 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12214 page_flip_completed(intel_crtc
);
12216 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12217 spin_unlock_irq(&dev
->event_lock
);
12219 drm_crtc_vblank_put(crtc
);
12224 intel_crtc
->flip_work
= work
;
12225 spin_unlock_irq(&dev
->event_lock
);
12227 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
12228 flush_workqueue(dev_priv
->wq
);
12230 /* Reference the objects for the scheduled work. */
12231 drm_framebuffer_reference(work
->old_fb
);
12233 crtc
->primary
->fb
= fb
;
12234 update_state_fb(crtc
->primary
);
12236 work
->pending_flip_obj
= i915_gem_object_get(obj
);
12238 ret
= i915_mutex_lock_interruptible(dev
);
12242 intel_crtc
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
12243 if (i915_reset_in_progress_or_wedged(&dev_priv
->gpu_error
)) {
12248 atomic_inc(&intel_crtc
->unpin_work_count
);
12250 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
12251 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_G4X(pipe
)) + 1;
12253 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
12254 engine
= dev_priv
->engine
[BCS
];
12255 if (fb
->modifier
!= old_fb
->modifier
)
12256 /* vlv: DISPLAY_FLIP fails to change tiling */
12258 } else if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
)) {
12259 engine
= dev_priv
->engine
[BCS
];
12260 } else if (INTEL_GEN(dev_priv
) >= 7) {
12261 engine
= i915_gem_object_last_write_engine(obj
);
12262 if (engine
== NULL
|| engine
->id
!= RCS
)
12263 engine
= dev_priv
->engine
[BCS
];
12265 engine
= dev_priv
->engine
[RCS
];
12268 mmio_flip
= use_mmio_flip(engine
, obj
);
12270 vma
= intel_pin_and_fence_fb_obj(fb
, primary
->state
->rotation
);
12272 ret
= PTR_ERR(vma
);
12273 goto cleanup_pending
;
12276 work
->old_vma
= to_intel_plane_state(primary
->state
)->vma
;
12277 to_intel_plane_state(primary
->state
)->vma
= vma
;
12279 work
->gtt_offset
= i915_ggtt_offset(vma
) + intel_crtc
->dspaddr_offset
;
12280 work
->rotation
= crtc
->primary
->state
->rotation
;
12283 * There's the potential that the next frame will not be compatible with
12284 * FBC, so we want to call pre_update() before the actual page flip.
12285 * The problem is that pre_update() caches some information about the fb
12286 * object, so we want to do this only after the object is pinned. Let's
12287 * be on the safe side and do this immediately before scheduling the
12290 intel_fbc_pre_update(intel_crtc
, intel_crtc
->config
,
12291 to_intel_plane_state(primary
->state
));
12294 INIT_WORK(&work
->mmio_work
, intel_mmio_flip_work_func
);
12295 queue_work(system_unbound_wq
, &work
->mmio_work
);
12297 request
= i915_gem_request_alloc(engine
,
12298 dev_priv
->kernel_context
);
12299 if (IS_ERR(request
)) {
12300 ret
= PTR_ERR(request
);
12301 goto cleanup_unpin
;
12304 ret
= i915_gem_request_await_object(request
, obj
, false);
12306 goto cleanup_request
;
12308 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, request
,
12311 goto cleanup_request
;
12313 intel_mark_page_flip_active(intel_crtc
, work
);
12315 work
->flip_queued_req
= i915_gem_request_get(request
);
12316 i915_add_request_no_flush(request
);
12319 i915_gem_object_wait_priority(obj
, 0, I915_PRIORITY_DISPLAY
);
12320 i915_gem_track_fb(intel_fb_obj(old_fb
), obj
,
12321 to_intel_plane(primary
)->frontbuffer_bit
);
12322 mutex_unlock(&dev
->struct_mutex
);
12324 intel_frontbuffer_flip_prepare(to_i915(dev
),
12325 to_intel_plane(primary
)->frontbuffer_bit
);
12327 trace_i915_flip_request(intel_crtc
->plane
, obj
);
12332 i915_add_request_no_flush(request
);
12334 to_intel_plane_state(primary
->state
)->vma
= work
->old_vma
;
12335 intel_unpin_fb_vma(vma
);
12337 atomic_dec(&intel_crtc
->unpin_work_count
);
12339 mutex_unlock(&dev
->struct_mutex
);
12341 crtc
->primary
->fb
= old_fb
;
12342 update_state_fb(crtc
->primary
);
12344 i915_gem_object_put(obj
);
12345 drm_framebuffer_unreference(work
->old_fb
);
12347 spin_lock_irq(&dev
->event_lock
);
12348 intel_crtc
->flip_work
= NULL
;
12349 spin_unlock_irq(&dev
->event_lock
);
12351 drm_crtc_vblank_put(crtc
);
12356 struct drm_atomic_state
*state
;
12357 struct drm_plane_state
*plane_state
;
12360 state
= drm_atomic_state_alloc(dev
);
12363 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
12366 plane_state
= drm_atomic_get_plane_state(state
, primary
);
12367 ret
= PTR_ERR_OR_ZERO(plane_state
);
12369 drm_atomic_set_fb_for_plane(plane_state
, fb
);
12371 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
12373 ret
= drm_atomic_commit(state
);
12376 if (ret
== -EDEADLK
) {
12377 drm_modeset_backoff(state
->acquire_ctx
);
12378 drm_atomic_state_clear(state
);
12382 drm_atomic_state_put(state
);
12384 if (ret
== 0 && event
) {
12385 spin_lock_irq(&dev
->event_lock
);
12386 drm_crtc_send_vblank_event(crtc
, event
);
12387 spin_unlock_irq(&dev
->event_lock
);
12395 * intel_wm_need_update - Check whether watermarks need updating
12396 * @plane: drm plane
12397 * @state: new plane state
12399 * Check current plane state versus the new one to determine whether
12400 * watermarks need to be recalculated.
12402 * Returns true or false.
12404 static bool intel_wm_need_update(struct drm_plane
*plane
,
12405 struct drm_plane_state
*state
)
12407 struct intel_plane_state
*new = to_intel_plane_state(state
);
12408 struct intel_plane_state
*cur
= to_intel_plane_state(plane
->state
);
12410 /* Update watermarks on tiling or size changes. */
12411 if (new->base
.visible
!= cur
->base
.visible
)
12414 if (!cur
->base
.fb
|| !new->base
.fb
)
12417 if (cur
->base
.fb
->modifier
!= new->base
.fb
->modifier
||
12418 cur
->base
.rotation
!= new->base
.rotation
||
12419 drm_rect_width(&new->base
.src
) != drm_rect_width(&cur
->base
.src
) ||
12420 drm_rect_height(&new->base
.src
) != drm_rect_height(&cur
->base
.src
) ||
12421 drm_rect_width(&new->base
.dst
) != drm_rect_width(&cur
->base
.dst
) ||
12422 drm_rect_height(&new->base
.dst
) != drm_rect_height(&cur
->base
.dst
))
12428 static bool needs_scaling(struct intel_plane_state
*state
)
12430 int src_w
= drm_rect_width(&state
->base
.src
) >> 16;
12431 int src_h
= drm_rect_height(&state
->base
.src
) >> 16;
12432 int dst_w
= drm_rect_width(&state
->base
.dst
);
12433 int dst_h
= drm_rect_height(&state
->base
.dst
);
12435 return (src_w
!= dst_w
|| src_h
!= dst_h
);
12438 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
12439 struct drm_plane_state
*plane_state
)
12441 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
12442 struct drm_crtc
*crtc
= crtc_state
->crtc
;
12443 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12444 struct drm_plane
*plane
= plane_state
->plane
;
12445 struct drm_device
*dev
= crtc
->dev
;
12446 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12447 struct intel_plane_state
*old_plane_state
=
12448 to_intel_plane_state(plane
->state
);
12449 bool mode_changed
= needs_modeset(crtc_state
);
12450 bool was_crtc_enabled
= crtc
->state
->active
;
12451 bool is_crtc_enabled
= crtc_state
->active
;
12452 bool turn_off
, turn_on
, visible
, was_visible
;
12453 struct drm_framebuffer
*fb
= plane_state
->fb
;
12456 if (INTEL_GEN(dev_priv
) >= 9 && plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
12457 ret
= skl_update_scaler_plane(
12458 to_intel_crtc_state(crtc_state
),
12459 to_intel_plane_state(plane_state
));
12464 was_visible
= old_plane_state
->base
.visible
;
12465 visible
= plane_state
->visible
;
12467 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
12468 was_visible
= false;
12471 * Visibility is calculated as if the crtc was on, but
12472 * after scaler setup everything depends on it being off
12473 * when the crtc isn't active.
12475 * FIXME this is wrong for watermarks. Watermarks should also
12476 * be computed as if the pipe would be active. Perhaps move
12477 * per-plane wm computation to the .check_plane() hook, and
12478 * only combine the results from all planes in the current place?
12480 if (!is_crtc_enabled
)
12481 plane_state
->visible
= visible
= false;
12483 if (!was_visible
&& !visible
)
12486 if (fb
!= old_plane_state
->base
.fb
)
12487 pipe_config
->fb_changed
= true;
12489 turn_off
= was_visible
&& (!visible
|| mode_changed
);
12490 turn_on
= visible
&& (!was_visible
|| mode_changed
);
12492 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12493 intel_crtc
->base
.base
.id
,
12494 intel_crtc
->base
.name
,
12495 plane
->base
.id
, plane
->name
,
12496 fb
? fb
->base
.id
: -1);
12498 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12499 plane
->base
.id
, plane
->name
,
12500 was_visible
, visible
,
12501 turn_off
, turn_on
, mode_changed
);
12504 pipe_config
->update_wm_pre
= true;
12506 /* must disable cxsr around plane enable/disable */
12507 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
12508 pipe_config
->disable_cxsr
= true;
12509 } else if (turn_off
) {
12510 pipe_config
->update_wm_post
= true;
12512 /* must disable cxsr around plane enable/disable */
12513 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
12514 pipe_config
->disable_cxsr
= true;
12515 } else if (intel_wm_need_update(plane
, plane_state
)) {
12516 /* FIXME bollocks */
12517 pipe_config
->update_wm_pre
= true;
12518 pipe_config
->update_wm_post
= true;
12521 /* Pre-gen9 platforms need two-step watermark updates */
12522 if ((pipe_config
->update_wm_pre
|| pipe_config
->update_wm_post
) &&
12523 INTEL_GEN(dev_priv
) < 9 && dev_priv
->display
.optimize_watermarks
)
12524 to_intel_crtc_state(crtc_state
)->wm
.need_postvbl_update
= true;
12526 if (visible
|| was_visible
)
12527 pipe_config
->fb_bits
|= to_intel_plane(plane
)->frontbuffer_bit
;
12530 * WaCxSRDisabledForSpriteScaling:ivb
12532 * cstate->update_wm was already set above, so this flag will
12533 * take effect when we commit and program watermarks.
12535 if (plane
->type
== DRM_PLANE_TYPE_OVERLAY
&& IS_IVYBRIDGE(dev_priv
) &&
12536 needs_scaling(to_intel_plane_state(plane_state
)) &&
12537 !needs_scaling(old_plane_state
))
12538 pipe_config
->disable_lp_wm
= true;
12543 static bool encoders_cloneable(const struct intel_encoder
*a
,
12544 const struct intel_encoder
*b
)
12546 /* masks could be asymmetric, so check both ways */
12547 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
12548 b
->cloneable
& (1 << a
->type
));
12551 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
12552 struct intel_crtc
*crtc
,
12553 struct intel_encoder
*encoder
)
12555 struct intel_encoder
*source_encoder
;
12556 struct drm_connector
*connector
;
12557 struct drm_connector_state
*connector_state
;
12560 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12561 if (connector_state
->crtc
!= &crtc
->base
)
12565 to_intel_encoder(connector_state
->best_encoder
);
12566 if (!encoders_cloneable(encoder
, source_encoder
))
12573 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
12574 struct drm_crtc_state
*crtc_state
)
12576 struct drm_device
*dev
= crtc
->dev
;
12577 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12578 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12579 struct intel_crtc_state
*pipe_config
=
12580 to_intel_crtc_state(crtc_state
);
12581 struct drm_atomic_state
*state
= crtc_state
->state
;
12583 bool mode_changed
= needs_modeset(crtc_state
);
12585 if (mode_changed
&& !crtc_state
->active
)
12586 pipe_config
->update_wm_post
= true;
12588 if (mode_changed
&& crtc_state
->enable
&&
12589 dev_priv
->display
.crtc_compute_clock
&&
12590 !WARN_ON(pipe_config
->shared_dpll
)) {
12591 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12597 if (crtc_state
->color_mgmt_changed
) {
12598 ret
= intel_color_check(crtc
, crtc_state
);
12603 * Changing color management on Intel hardware is
12604 * handled as part of planes update.
12606 crtc_state
->planes_changed
= true;
12610 if (dev_priv
->display
.compute_pipe_wm
) {
12611 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
12613 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12618 if (dev_priv
->display
.compute_intermediate_wm
&&
12619 !to_intel_atomic_state(state
)->skip_intermediate_wm
) {
12620 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
12624 * Calculate 'intermediate' watermarks that satisfy both the
12625 * old state and the new state. We can program these
12628 ret
= dev_priv
->display
.compute_intermediate_wm(dev
,
12632 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12635 } else if (dev_priv
->display
.compute_intermediate_wm
) {
12636 if (HAS_PCH_SPLIT(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
12637 pipe_config
->wm
.ilk
.intermediate
= pipe_config
->wm
.ilk
.optimal
;
12640 if (INTEL_GEN(dev_priv
) >= 9) {
12642 ret
= skl_update_scaler_crtc(pipe_config
);
12645 ret
= intel_atomic_setup_scalers(dev
, intel_crtc
,
12652 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
12653 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
12654 .atomic_begin
= intel_begin_crtc_commit
,
12655 .atomic_flush
= intel_finish_crtc_commit
,
12656 .atomic_check
= intel_crtc_atomic_check
,
12659 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
12661 struct intel_connector
*connector
;
12663 for_each_intel_connector(dev
, connector
) {
12664 if (connector
->base
.state
->crtc
)
12665 drm_connector_unreference(&connector
->base
);
12667 if (connector
->base
.encoder
) {
12668 connector
->base
.state
->best_encoder
=
12669 connector
->base
.encoder
;
12670 connector
->base
.state
->crtc
=
12671 connector
->base
.encoder
->crtc
;
12673 drm_connector_reference(&connector
->base
);
12675 connector
->base
.state
->best_encoder
= NULL
;
12676 connector
->base
.state
->crtc
= NULL
;
12682 connected_sink_compute_bpp(struct intel_connector
*connector
,
12683 struct intel_crtc_state
*pipe_config
)
12685 const struct drm_display_info
*info
= &connector
->base
.display_info
;
12686 int bpp
= pipe_config
->pipe_bpp
;
12688 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12689 connector
->base
.base
.id
,
12690 connector
->base
.name
);
12692 /* Don't use an invalid EDID bpc value */
12693 if (info
->bpc
!= 0 && info
->bpc
* 3 < bpp
) {
12694 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12695 bpp
, info
->bpc
* 3);
12696 pipe_config
->pipe_bpp
= info
->bpc
* 3;
12699 /* Clamp bpp to 8 on screens without EDID 1.4 */
12700 if (info
->bpc
== 0 && bpp
> 24) {
12701 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12703 pipe_config
->pipe_bpp
= 24;
12708 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
12709 struct intel_crtc_state
*pipe_config
)
12711 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
12712 struct drm_atomic_state
*state
;
12713 struct drm_connector
*connector
;
12714 struct drm_connector_state
*connector_state
;
12717 if ((IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
12718 IS_CHERRYVIEW(dev_priv
)))
12720 else if (INTEL_GEN(dev_priv
) >= 5)
12726 pipe_config
->pipe_bpp
= bpp
;
12728 state
= pipe_config
->base
.state
;
12730 /* Clamp display bpp to EDID value */
12731 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12732 if (connector_state
->crtc
!= &crtc
->base
)
12735 connected_sink_compute_bpp(to_intel_connector(connector
),
12742 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
12744 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12745 "type: 0x%x flags: 0x%x\n",
12747 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
12748 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
12749 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
12750 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
12754 intel_dump_m_n_config(struct intel_crtc_state
*pipe_config
, char *id
,
12755 unsigned int lane_count
, struct intel_link_m_n
*m_n
)
12757 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12759 m_n
->gmch_m
, m_n
->gmch_n
,
12760 m_n
->link_m
, m_n
->link_n
, m_n
->tu
);
12763 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
12764 struct intel_crtc_state
*pipe_config
,
12765 const char *context
)
12767 struct drm_device
*dev
= crtc
->base
.dev
;
12768 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12769 struct drm_plane
*plane
;
12770 struct intel_plane
*intel_plane
;
12771 struct intel_plane_state
*state
;
12772 struct drm_framebuffer
*fb
;
12774 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
12775 crtc
->base
.base
.id
, crtc
->base
.name
, context
);
12777 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12778 transcoder_name(pipe_config
->cpu_transcoder
),
12779 pipe_config
->pipe_bpp
, pipe_config
->dither
);
12781 if (pipe_config
->has_pch_encoder
)
12782 intel_dump_m_n_config(pipe_config
, "fdi",
12783 pipe_config
->fdi_lanes
,
12784 &pipe_config
->fdi_m_n
);
12786 if (intel_crtc_has_dp_encoder(pipe_config
)) {
12787 intel_dump_m_n_config(pipe_config
, "dp m_n",
12788 pipe_config
->lane_count
, &pipe_config
->dp_m_n
);
12789 if (pipe_config
->has_drrs
)
12790 intel_dump_m_n_config(pipe_config
, "dp m2_n2",
12791 pipe_config
->lane_count
,
12792 &pipe_config
->dp_m2_n2
);
12795 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12796 pipe_config
->has_audio
, pipe_config
->has_infoframe
);
12798 DRM_DEBUG_KMS("requested mode:\n");
12799 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
12800 DRM_DEBUG_KMS("adjusted mode:\n");
12801 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
12802 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
12803 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",
12804 pipe_config
->port_clock
,
12805 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
12807 if (INTEL_GEN(dev_priv
) >= 9)
12808 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12810 pipe_config
->scaler_state
.scaler_users
,
12811 pipe_config
->scaler_state
.scaler_id
);
12813 if (HAS_GMCH_DISPLAY(dev_priv
))
12814 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12815 pipe_config
->gmch_pfit
.control
,
12816 pipe_config
->gmch_pfit
.pgm_ratios
,
12817 pipe_config
->gmch_pfit
.lvds_border_bits
);
12819 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12820 pipe_config
->pch_pfit
.pos
,
12821 pipe_config
->pch_pfit
.size
,
12822 enableddisabled(pipe_config
->pch_pfit
.enabled
));
12824 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12825 pipe_config
->ips_enabled
, pipe_config
->double_wide
);
12827 intel_dpll_dump_hw_state(dev_priv
, &pipe_config
->dpll_hw_state
);
12829 DRM_DEBUG_KMS("planes on this crtc\n");
12830 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12831 struct drm_format_name_buf format_name
;
12832 intel_plane
= to_intel_plane(plane
);
12833 if (intel_plane
->pipe
!= crtc
->pipe
)
12836 state
= to_intel_plane_state(plane
->state
);
12837 fb
= state
->base
.fb
;
12839 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12840 plane
->base
.id
, plane
->name
, state
->scaler_id
);
12844 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
12845 plane
->base
.id
, plane
->name
,
12846 fb
->base
.id
, fb
->width
, fb
->height
,
12847 drm_get_format_name(fb
->format
->format
, &format_name
));
12848 if (INTEL_GEN(dev_priv
) >= 9)
12849 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12851 state
->base
.src
.x1
>> 16,
12852 state
->base
.src
.y1
>> 16,
12853 drm_rect_width(&state
->base
.src
) >> 16,
12854 drm_rect_height(&state
->base
.src
) >> 16,
12855 state
->base
.dst
.x1
, state
->base
.dst
.y1
,
12856 drm_rect_width(&state
->base
.dst
),
12857 drm_rect_height(&state
->base
.dst
));
12861 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12863 struct drm_device
*dev
= state
->dev
;
12864 struct drm_connector
*connector
;
12865 unsigned int used_ports
= 0;
12866 unsigned int used_mst_ports
= 0;
12869 * Walk the connector list instead of the encoder
12870 * list to detect the problem on ddi platforms
12871 * where there's just one encoder per digital port.
12873 drm_for_each_connector(connector
, dev
) {
12874 struct drm_connector_state
*connector_state
;
12875 struct intel_encoder
*encoder
;
12877 connector_state
= drm_atomic_get_existing_connector_state(state
, connector
);
12878 if (!connector_state
)
12879 connector_state
= connector
->state
;
12881 if (!connector_state
->best_encoder
)
12884 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12886 WARN_ON(!connector_state
->crtc
);
12888 switch (encoder
->type
) {
12889 unsigned int port_mask
;
12890 case INTEL_OUTPUT_UNKNOWN
:
12891 if (WARN_ON(!HAS_DDI(to_i915(dev
))))
12893 case INTEL_OUTPUT_DP
:
12894 case INTEL_OUTPUT_HDMI
:
12895 case INTEL_OUTPUT_EDP
:
12896 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12898 /* the same port mustn't appear more than once */
12899 if (used_ports
& port_mask
)
12902 used_ports
|= port_mask
;
12904 case INTEL_OUTPUT_DP_MST
:
12906 1 << enc_to_mst(&encoder
->base
)->primary
->port
;
12913 /* can't mix MST and SST/HDMI on the same port */
12914 if (used_ports
& used_mst_ports
)
12921 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12923 struct drm_crtc_state tmp_state
;
12924 struct intel_crtc_scaler_state scaler_state
;
12925 struct intel_dpll_hw_state dpll_hw_state
;
12926 struct intel_shared_dpll
*shared_dpll
;
12929 /* FIXME: before the switch to atomic started, a new pipe_config was
12930 * kzalloc'd. Code that depends on any field being zero should be
12931 * fixed, so that the crtc_state can be safely duplicated. For now,
12932 * only fields that are know to not cause problems are preserved. */
12934 tmp_state
= crtc_state
->base
;
12935 scaler_state
= crtc_state
->scaler_state
;
12936 shared_dpll
= crtc_state
->shared_dpll
;
12937 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12938 force_thru
= crtc_state
->pch_pfit
.force_thru
;
12940 memset(crtc_state
, 0, sizeof *crtc_state
);
12942 crtc_state
->base
= tmp_state
;
12943 crtc_state
->scaler_state
= scaler_state
;
12944 crtc_state
->shared_dpll
= shared_dpll
;
12945 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12946 crtc_state
->pch_pfit
.force_thru
= force_thru
;
12950 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12951 struct intel_crtc_state
*pipe_config
)
12953 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12954 struct intel_encoder
*encoder
;
12955 struct drm_connector
*connector
;
12956 struct drm_connector_state
*connector_state
;
12957 int base_bpp
, ret
= -EINVAL
;
12961 clear_intel_crtc_state(pipe_config
);
12963 pipe_config
->cpu_transcoder
=
12964 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12967 * Sanitize sync polarity flags based on requested ones. If neither
12968 * positive or negative polarity is requested, treat this as meaning
12969 * negative polarity.
12971 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12972 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12973 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12975 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12976 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12977 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12979 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12985 * Determine the real pipe dimensions. Note that stereo modes can
12986 * increase the actual pipe size due to the frame doubling and
12987 * insertion of additional space for blanks between the frame. This
12988 * is stored in the crtc timings. We use the requested mode to do this
12989 * computation to clearly distinguish it from the adjusted mode, which
12990 * can be changed by the connectors in the below retry loop.
12992 drm_mode_get_hv_timing(&pipe_config
->base
.mode
,
12993 &pipe_config
->pipe_src_w
,
12994 &pipe_config
->pipe_src_h
);
12996 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12997 if (connector_state
->crtc
!= crtc
)
13000 encoder
= to_intel_encoder(connector_state
->best_encoder
);
13002 if (!check_single_encoder_cloning(state
, to_intel_crtc(crtc
), encoder
)) {
13003 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13008 * Determine output_types before calling the .compute_config()
13009 * hooks so that the hooks can use this information safely.
13011 pipe_config
->output_types
|= 1 << encoder
->type
;
13015 /* Ensure the port clock defaults are reset when retrying. */
13016 pipe_config
->port_clock
= 0;
13017 pipe_config
->pixel_multiplier
= 1;
13019 /* Fill in default crtc timings, allow encoders to overwrite them. */
13020 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
13021 CRTC_STEREO_DOUBLE
);
13023 /* Pass our mode to the connectors and the CRTC to give them a chance to
13024 * adjust it according to limitations or connector properties, and also
13025 * a chance to reject the mode entirely.
13027 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
13028 if (connector_state
->crtc
!= crtc
)
13031 encoder
= to_intel_encoder(connector_state
->best_encoder
);
13033 if (!(encoder
->compute_config(encoder
, pipe_config
, connector_state
))) {
13034 DRM_DEBUG_KMS("Encoder config failure\n");
13039 /* Set default port clock if not overwritten by the encoder. Needs to be
13040 * done afterwards in case the encoder adjusts the mode. */
13041 if (!pipe_config
->port_clock
)
13042 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
13043 * pipe_config
->pixel_multiplier
;
13045 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
13047 DRM_DEBUG_KMS("CRTC fixup failed\n");
13051 if (ret
== RETRY
) {
13052 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
13057 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13059 goto encoder_retry
;
13062 /* Dithering seems to not pass-through bits correctly when it should, so
13063 * only enable it on 6bpc panels. */
13064 pipe_config
->dither
= pipe_config
->pipe_bpp
== 6*3;
13065 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13066 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
13073 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
13075 struct drm_crtc
*crtc
;
13076 struct drm_crtc_state
*crtc_state
;
13079 /* Double check state. */
13080 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13081 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
13083 /* Update hwmode for vblank functions */
13084 if (crtc
->state
->active
)
13085 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
13087 crtc
->hwmode
.crtc_clock
= 0;
13090 * Update legacy state to satisfy fbc code. This can
13091 * be removed when fbc uses the atomic state.
13093 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
13094 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
13096 crtc
->primary
->fb
= plane_state
->fb
;
13097 crtc
->x
= plane_state
->src_x
>> 16;
13098 crtc
->y
= plane_state
->src_y
>> 16;
13103 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
13107 if (clock1
== clock2
)
13110 if (!clock1
|| !clock2
)
13113 diff
= abs(clock1
- clock2
);
13115 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
13122 intel_compare_m_n(unsigned int m
, unsigned int n
,
13123 unsigned int m2
, unsigned int n2
,
13126 if (m
== m2
&& n
== n2
)
13129 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
13132 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
13139 } else if (n
< n2
) {
13149 return intel_fuzzy_clock_check(m
, m2
);
13153 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
13154 struct intel_link_m_n
*m2_n2
,
13157 if (m_n
->tu
== m2_n2
->tu
&&
13158 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
13159 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
13160 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
13161 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
13171 static void __printf(3, 4)
13172 pipe_config_err(bool adjust
, const char *name
, const char *format
, ...)
13175 unsigned int category
;
13176 struct va_format vaf
;
13180 level
= KERN_DEBUG
;
13181 category
= DRM_UT_KMS
;
13184 category
= DRM_UT_NONE
;
13187 va_start(args
, format
);
13191 drm_printk(level
, category
, "mismatch in %s %pV", name
, &vaf
);
13197 intel_pipe_config_compare(struct drm_i915_private
*dev_priv
,
13198 struct intel_crtc_state
*current_config
,
13199 struct intel_crtc_state
*pipe_config
,
13204 #define PIPE_CONF_CHECK_X(name) \
13205 if (current_config->name != pipe_config->name) { \
13206 pipe_config_err(adjust, __stringify(name), \
13207 "(expected 0x%08x, found 0x%08x)\n", \
13208 current_config->name, \
13209 pipe_config->name); \
13213 #define PIPE_CONF_CHECK_I(name) \
13214 if (current_config->name != pipe_config->name) { \
13215 pipe_config_err(adjust, __stringify(name), \
13216 "(expected %i, found %i)\n", \
13217 current_config->name, \
13218 pipe_config->name); \
13222 #define PIPE_CONF_CHECK_P(name) \
13223 if (current_config->name != pipe_config->name) { \
13224 pipe_config_err(adjust, __stringify(name), \
13225 "(expected %p, found %p)\n", \
13226 current_config->name, \
13227 pipe_config->name); \
13231 #define PIPE_CONF_CHECK_M_N(name) \
13232 if (!intel_compare_link_m_n(¤t_config->name, \
13233 &pipe_config->name,\
13235 pipe_config_err(adjust, __stringify(name), \
13236 "(expected tu %i gmch %i/%i link %i/%i, " \
13237 "found tu %i, gmch %i/%i link %i/%i)\n", \
13238 current_config->name.tu, \
13239 current_config->name.gmch_m, \
13240 current_config->name.gmch_n, \
13241 current_config->name.link_m, \
13242 current_config->name.link_n, \
13243 pipe_config->name.tu, \
13244 pipe_config->name.gmch_m, \
13245 pipe_config->name.gmch_n, \
13246 pipe_config->name.link_m, \
13247 pipe_config->name.link_n); \
13251 /* This is required for BDW+ where there is only one set of registers for
13252 * switching between high and low RR.
13253 * This macro can be used whenever a comparison has to be made between one
13254 * hw state and multiple sw state variables.
13256 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13257 if (!intel_compare_link_m_n(¤t_config->name, \
13258 &pipe_config->name, adjust) && \
13259 !intel_compare_link_m_n(¤t_config->alt_name, \
13260 &pipe_config->name, adjust)) { \
13261 pipe_config_err(adjust, __stringify(name), \
13262 "(expected tu %i gmch %i/%i link %i/%i, " \
13263 "or tu %i gmch %i/%i link %i/%i, " \
13264 "found tu %i, gmch %i/%i link %i/%i)\n", \
13265 current_config->name.tu, \
13266 current_config->name.gmch_m, \
13267 current_config->name.gmch_n, \
13268 current_config->name.link_m, \
13269 current_config->name.link_n, \
13270 current_config->alt_name.tu, \
13271 current_config->alt_name.gmch_m, \
13272 current_config->alt_name.gmch_n, \
13273 current_config->alt_name.link_m, \
13274 current_config->alt_name.link_n, \
13275 pipe_config->name.tu, \
13276 pipe_config->name.gmch_m, \
13277 pipe_config->name.gmch_n, \
13278 pipe_config->name.link_m, \
13279 pipe_config->name.link_n); \
13283 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13284 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13285 pipe_config_err(adjust, __stringify(name), \
13286 "(%x) (expected %i, found %i)\n", \
13288 current_config->name & (mask), \
13289 pipe_config->name & (mask)); \
13293 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13294 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13295 pipe_config_err(adjust, __stringify(name), \
13296 "(expected %i, found %i)\n", \
13297 current_config->name, \
13298 pipe_config->name); \
13302 #define PIPE_CONF_QUIRK(quirk) \
13303 ((current_config->quirks | pipe_config->quirks) & (quirk))
13305 PIPE_CONF_CHECK_I(cpu_transcoder
);
13307 PIPE_CONF_CHECK_I(has_pch_encoder
);
13308 PIPE_CONF_CHECK_I(fdi_lanes
);
13309 PIPE_CONF_CHECK_M_N(fdi_m_n
);
13311 PIPE_CONF_CHECK_I(lane_count
);
13312 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
13314 if (INTEL_GEN(dev_priv
) < 8) {
13315 PIPE_CONF_CHECK_M_N(dp_m_n
);
13317 if (current_config
->has_drrs
)
13318 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
13320 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
13322 PIPE_CONF_CHECK_X(output_types
);
13324 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
13325 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
13326 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
13327 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
13328 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
13329 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
13331 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
13332 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
13333 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
13334 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
13335 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
13336 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
13338 PIPE_CONF_CHECK_I(pixel_multiplier
);
13339 PIPE_CONF_CHECK_I(has_hdmi_sink
);
13340 if ((INTEL_GEN(dev_priv
) < 8 && !IS_HASWELL(dev_priv
)) ||
13341 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
13342 PIPE_CONF_CHECK_I(limited_color_range
);
13343 PIPE_CONF_CHECK_I(has_infoframe
);
13345 PIPE_CONF_CHECK_I(has_audio
);
13347 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
13348 DRM_MODE_FLAG_INTERLACE
);
13350 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
13351 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
13352 DRM_MODE_FLAG_PHSYNC
);
13353 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
13354 DRM_MODE_FLAG_NHSYNC
);
13355 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
13356 DRM_MODE_FLAG_PVSYNC
);
13357 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
13358 DRM_MODE_FLAG_NVSYNC
);
13361 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
13362 /* pfit ratios are autocomputed by the hw on gen4+ */
13363 if (INTEL_GEN(dev_priv
) < 4)
13364 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
13365 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
13368 PIPE_CONF_CHECK_I(pipe_src_w
);
13369 PIPE_CONF_CHECK_I(pipe_src_h
);
13371 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
13372 if (current_config
->pch_pfit
.enabled
) {
13373 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
13374 PIPE_CONF_CHECK_X(pch_pfit
.size
);
13377 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
13380 /* BDW+ don't expose a synchronous way to read the state */
13381 if (IS_HASWELL(dev_priv
))
13382 PIPE_CONF_CHECK_I(ips_enabled
);
13384 PIPE_CONF_CHECK_I(double_wide
);
13386 PIPE_CONF_CHECK_P(shared_dpll
);
13387 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
13388 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
13389 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
13390 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
13391 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
13392 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
13393 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
13394 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
13395 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
13397 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
13398 PIPE_CONF_CHECK_X(dsi_pll
.div
);
13400 if (IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5)
13401 PIPE_CONF_CHECK_I(pipe_bpp
);
13403 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
13404 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
13406 #undef PIPE_CONF_CHECK_X
13407 #undef PIPE_CONF_CHECK_I
13408 #undef PIPE_CONF_CHECK_P
13409 #undef PIPE_CONF_CHECK_FLAGS
13410 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13411 #undef PIPE_CONF_QUIRK
13416 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
13417 const struct intel_crtc_state
*pipe_config
)
13419 if (pipe_config
->has_pch_encoder
) {
13420 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
13421 &pipe_config
->fdi_m_n
);
13422 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
13425 * FDI already provided one idea for the dotclock.
13426 * Yell if the encoder disagrees.
13428 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
13429 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13430 fdi_dotclock
, dotclock
);
13434 static void verify_wm_state(struct drm_crtc
*crtc
,
13435 struct drm_crtc_state
*new_state
)
13437 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
13438 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
13439 struct skl_pipe_wm hw_wm
, *sw_wm
;
13440 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
13441 struct skl_ddb_entry
*hw_ddb_entry
, *sw_ddb_entry
;
13442 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13443 const enum pipe pipe
= intel_crtc
->pipe
;
13444 int plane
, level
, max_level
= ilk_wm_max_level(dev_priv
);
13446 if (INTEL_GEN(dev_priv
) < 9 || !new_state
->active
)
13449 skl_pipe_wm_get_hw_state(crtc
, &hw_wm
);
13450 sw_wm
= &to_intel_crtc_state(new_state
)->wm
.skl
.optimal
;
13452 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
13453 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
13456 for_each_universal_plane(dev_priv
, pipe
, plane
) {
13457 hw_plane_wm
= &hw_wm
.planes
[plane
];
13458 sw_plane_wm
= &sw_wm
->planes
[plane
];
13461 for (level
= 0; level
<= max_level
; level
++) {
13462 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
13463 &sw_plane_wm
->wm
[level
]))
13466 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13467 pipe_name(pipe
), plane
+ 1, level
,
13468 sw_plane_wm
->wm
[level
].plane_en
,
13469 sw_plane_wm
->wm
[level
].plane_res_b
,
13470 sw_plane_wm
->wm
[level
].plane_res_l
,
13471 hw_plane_wm
->wm
[level
].plane_en
,
13472 hw_plane_wm
->wm
[level
].plane_res_b
,
13473 hw_plane_wm
->wm
[level
].plane_res_l
);
13476 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
13477 &sw_plane_wm
->trans_wm
)) {
13478 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13479 pipe_name(pipe
), plane
+ 1,
13480 sw_plane_wm
->trans_wm
.plane_en
,
13481 sw_plane_wm
->trans_wm
.plane_res_b
,
13482 sw_plane_wm
->trans_wm
.plane_res_l
,
13483 hw_plane_wm
->trans_wm
.plane_en
,
13484 hw_plane_wm
->trans_wm
.plane_res_b
,
13485 hw_plane_wm
->trans_wm
.plane_res_l
);
13489 hw_ddb_entry
= &hw_ddb
.plane
[pipe
][plane
];
13490 sw_ddb_entry
= &sw_ddb
->plane
[pipe
][plane
];
13492 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
13493 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13494 pipe_name(pipe
), plane
+ 1,
13495 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
13496 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
13502 * If the cursor plane isn't active, we may not have updated it's ddb
13503 * allocation. In that case since the ddb allocation will be updated
13504 * once the plane becomes visible, we can skip this check
13506 if (intel_crtc
->cursor_addr
) {
13507 hw_plane_wm
= &hw_wm
.planes
[PLANE_CURSOR
];
13508 sw_plane_wm
= &sw_wm
->planes
[PLANE_CURSOR
];
13511 for (level
= 0; level
<= max_level
; level
++) {
13512 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
13513 &sw_plane_wm
->wm
[level
]))
13516 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13517 pipe_name(pipe
), level
,
13518 sw_plane_wm
->wm
[level
].plane_en
,
13519 sw_plane_wm
->wm
[level
].plane_res_b
,
13520 sw_plane_wm
->wm
[level
].plane_res_l
,
13521 hw_plane_wm
->wm
[level
].plane_en
,
13522 hw_plane_wm
->wm
[level
].plane_res_b
,
13523 hw_plane_wm
->wm
[level
].plane_res_l
);
13526 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
13527 &sw_plane_wm
->trans_wm
)) {
13528 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13530 sw_plane_wm
->trans_wm
.plane_en
,
13531 sw_plane_wm
->trans_wm
.plane_res_b
,
13532 sw_plane_wm
->trans_wm
.plane_res_l
,
13533 hw_plane_wm
->trans_wm
.plane_en
,
13534 hw_plane_wm
->trans_wm
.plane_res_b
,
13535 hw_plane_wm
->trans_wm
.plane_res_l
);
13539 hw_ddb_entry
= &hw_ddb
.plane
[pipe
][PLANE_CURSOR
];
13540 sw_ddb_entry
= &sw_ddb
->plane
[pipe
][PLANE_CURSOR
];
13542 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
13543 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13545 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
13546 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
13552 verify_connector_state(struct drm_device
*dev
,
13553 struct drm_atomic_state
*state
,
13554 struct drm_crtc
*crtc
)
13556 struct drm_connector
*connector
;
13557 struct drm_connector_state
*old_conn_state
;
13560 for_each_connector_in_state(state
, connector
, old_conn_state
, i
) {
13561 struct drm_encoder
*encoder
= connector
->encoder
;
13562 struct drm_connector_state
*state
= connector
->state
;
13564 if (state
->crtc
!= crtc
)
13567 intel_connector_verify_state(to_intel_connector(connector
));
13569 I915_STATE_WARN(state
->best_encoder
!= encoder
,
13570 "connector's atomic encoder doesn't match legacy encoder\n");
13575 verify_encoder_state(struct drm_device
*dev
)
13577 struct intel_encoder
*encoder
;
13578 struct intel_connector
*connector
;
13580 for_each_intel_encoder(dev
, encoder
) {
13581 bool enabled
= false;
13584 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13585 encoder
->base
.base
.id
,
13586 encoder
->base
.name
);
13588 for_each_intel_connector(dev
, connector
) {
13589 if (connector
->base
.state
->best_encoder
!= &encoder
->base
)
13593 I915_STATE_WARN(connector
->base
.state
->crtc
!=
13594 encoder
->base
.crtc
,
13595 "connector's crtc doesn't match encoder crtc\n");
13598 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
13599 "encoder's enabled state mismatch "
13600 "(expected %i, found %i)\n",
13601 !!encoder
->base
.crtc
, enabled
);
13603 if (!encoder
->base
.crtc
) {
13606 active
= encoder
->get_hw_state(encoder
, &pipe
);
13607 I915_STATE_WARN(active
,
13608 "encoder detached but still enabled on pipe %c.\n",
13615 verify_crtc_state(struct drm_crtc
*crtc
,
13616 struct drm_crtc_state
*old_crtc_state
,
13617 struct drm_crtc_state
*new_crtc_state
)
13619 struct drm_device
*dev
= crtc
->dev
;
13620 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13621 struct intel_encoder
*encoder
;
13622 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13623 struct intel_crtc_state
*pipe_config
, *sw_config
;
13624 struct drm_atomic_state
*old_state
;
13627 old_state
= old_crtc_state
->state
;
13628 __drm_atomic_helper_crtc_destroy_state(old_crtc_state
);
13629 pipe_config
= to_intel_crtc_state(old_crtc_state
);
13630 memset(pipe_config
, 0, sizeof(*pipe_config
));
13631 pipe_config
->base
.crtc
= crtc
;
13632 pipe_config
->base
.state
= old_state
;
13634 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
13636 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
13638 /* hw state is inconsistent with the pipe quirk */
13639 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
13640 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
13641 active
= new_crtc_state
->active
;
13643 I915_STATE_WARN(new_crtc_state
->active
!= active
,
13644 "crtc active state doesn't match with hw state "
13645 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
13647 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
13648 "transitional active state does not match atomic hw state "
13649 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
13651 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
13654 active
= encoder
->get_hw_state(encoder
, &pipe
);
13655 I915_STATE_WARN(active
!= new_crtc_state
->active
,
13656 "[ENCODER:%i] active %i with crtc active %i\n",
13657 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
13659 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
13660 "Encoder connected to wrong pipe %c\n",
13664 pipe_config
->output_types
|= 1 << encoder
->type
;
13665 encoder
->get_config(encoder
, pipe_config
);
13669 if (!new_crtc_state
->active
)
13672 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
13674 sw_config
= to_intel_crtc_state(crtc
->state
);
13675 if (!intel_pipe_config_compare(dev_priv
, sw_config
,
13676 pipe_config
, false)) {
13677 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13678 intel_dump_pipe_config(intel_crtc
, pipe_config
,
13680 intel_dump_pipe_config(intel_crtc
, sw_config
,
13686 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
13687 struct intel_shared_dpll
*pll
,
13688 struct drm_crtc
*crtc
,
13689 struct drm_crtc_state
*new_state
)
13691 struct intel_dpll_hw_state dpll_hw_state
;
13692 unsigned crtc_mask
;
13695 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
13697 DRM_DEBUG_KMS("%s\n", pll
->name
);
13699 active
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
13701 if (!(pll
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
13702 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
13703 "pll in active use but not on in sw tracking\n");
13704 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
13705 "pll is on but not used by any active crtc\n");
13706 I915_STATE_WARN(pll
->on
!= active
,
13707 "pll on state mismatch (expected %i, found %i)\n",
13712 I915_STATE_WARN(pll
->active_mask
& ~pll
->state
.crtc_mask
,
13713 "more active pll users than references: %x vs %x\n",
13714 pll
->active_mask
, pll
->state
.crtc_mask
);
13719 crtc_mask
= 1 << drm_crtc_index(crtc
);
13721 if (new_state
->active
)
13722 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
13723 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13724 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13726 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13727 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13728 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13730 I915_STATE_WARN(!(pll
->state
.crtc_mask
& crtc_mask
),
13731 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13732 crtc_mask
, pll
->state
.crtc_mask
);
13734 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->state
.hw_state
,
13736 sizeof(dpll_hw_state
)),
13737 "pll hw state mismatch\n");
13741 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
13742 struct drm_crtc_state
*old_crtc_state
,
13743 struct drm_crtc_state
*new_crtc_state
)
13745 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13746 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
13747 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
13749 if (new_state
->shared_dpll
)
13750 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
13752 if (old_state
->shared_dpll
&&
13753 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
13754 unsigned crtc_mask
= 1 << drm_crtc_index(crtc
);
13755 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
13757 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13758 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13759 pipe_name(drm_crtc_index(crtc
)));
13760 I915_STATE_WARN(pll
->state
.crtc_mask
& crtc_mask
,
13761 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13762 pipe_name(drm_crtc_index(crtc
)));
13767 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
13768 struct drm_atomic_state
*state
,
13769 struct drm_crtc_state
*old_state
,
13770 struct drm_crtc_state
*new_state
)
13772 if (!needs_modeset(new_state
) &&
13773 !to_intel_crtc_state(new_state
)->update_pipe
)
13776 verify_wm_state(crtc
, new_state
);
13777 verify_connector_state(crtc
->dev
, state
, crtc
);
13778 verify_crtc_state(crtc
, old_state
, new_state
);
13779 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
13783 verify_disabled_dpll_state(struct drm_device
*dev
)
13785 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13788 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
13789 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
13793 intel_modeset_verify_disabled(struct drm_device
*dev
,
13794 struct drm_atomic_state
*state
)
13796 verify_encoder_state(dev
);
13797 verify_connector_state(dev
, state
, NULL
);
13798 verify_disabled_dpll_state(dev
);
13801 static void update_scanline_offset(struct intel_crtc
*crtc
)
13803 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
13806 * The scanline counter increments at the leading edge of hsync.
13808 * On most platforms it starts counting from vtotal-1 on the
13809 * first active line. That means the scanline counter value is
13810 * always one less than what we would expect. Ie. just after
13811 * start of vblank, which also occurs at start of hsync (on the
13812 * last active line), the scanline counter will read vblank_start-1.
13814 * On gen2 the scanline counter starts counting from 1 instead
13815 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13816 * to keep the value positive), instead of adding one.
13818 * On HSW+ the behaviour of the scanline counter depends on the output
13819 * type. For DP ports it behaves like most other platforms, but on HDMI
13820 * there's an extra 1 line difference. So we need to add two instead of
13821 * one to the value.
13823 if (IS_GEN2(dev_priv
)) {
13824 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
13827 vtotal
= adjusted_mode
->crtc_vtotal
;
13828 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
13831 crtc
->scanline_offset
= vtotal
- 1;
13832 } else if (HAS_DDI(dev_priv
) &&
13833 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
)) {
13834 crtc
->scanline_offset
= 2;
13836 crtc
->scanline_offset
= 1;
13839 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
13841 struct drm_device
*dev
= state
->dev
;
13842 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13843 struct drm_crtc
*crtc
;
13844 struct drm_crtc_state
*crtc_state
;
13847 if (!dev_priv
->display
.crtc_compute_clock
)
13850 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13851 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13852 struct intel_shared_dpll
*old_dpll
=
13853 to_intel_crtc_state(crtc
->state
)->shared_dpll
;
13855 if (!needs_modeset(crtc_state
))
13858 to_intel_crtc_state(crtc_state
)->shared_dpll
= NULL
;
13863 intel_release_shared_dpll(old_dpll
, intel_crtc
, state
);
13868 * This implements the workaround described in the "notes" section of the mode
13869 * set sequence documentation. When going from no pipes or single pipe to
13870 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13871 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13873 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
13875 struct drm_crtc_state
*crtc_state
;
13876 struct intel_crtc
*intel_crtc
;
13877 struct drm_crtc
*crtc
;
13878 struct intel_crtc_state
*first_crtc_state
= NULL
;
13879 struct intel_crtc_state
*other_crtc_state
= NULL
;
13880 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
13883 /* look at all crtc's that are going to be enabled in during modeset */
13884 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13885 intel_crtc
= to_intel_crtc(crtc
);
13887 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
13890 if (first_crtc_state
) {
13891 other_crtc_state
= to_intel_crtc_state(crtc_state
);
13894 first_crtc_state
= to_intel_crtc_state(crtc_state
);
13895 first_pipe
= intel_crtc
->pipe
;
13899 /* No workaround needed? */
13900 if (!first_crtc_state
)
13903 /* w/a possibly needed, check how many crtc's are already enabled. */
13904 for_each_intel_crtc(state
->dev
, intel_crtc
) {
13905 struct intel_crtc_state
*pipe_config
;
13907 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13908 if (IS_ERR(pipe_config
))
13909 return PTR_ERR(pipe_config
);
13911 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
13913 if (!pipe_config
->base
.active
||
13914 needs_modeset(&pipe_config
->base
))
13917 /* 2 or more enabled crtcs means no need for w/a */
13918 if (enabled_pipe
!= INVALID_PIPE
)
13921 enabled_pipe
= intel_crtc
->pipe
;
13924 if (enabled_pipe
!= INVALID_PIPE
)
13925 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13926 else if (other_crtc_state
)
13927 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13932 static int intel_lock_all_pipes(struct drm_atomic_state
*state
)
13934 struct drm_crtc
*crtc
;
13936 /* Add all pipes to the state */
13937 for_each_crtc(state
->dev
, crtc
) {
13938 struct drm_crtc_state
*crtc_state
;
13940 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13941 if (IS_ERR(crtc_state
))
13942 return PTR_ERR(crtc_state
);
13948 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13950 struct drm_crtc
*crtc
;
13953 * Add all pipes to the state, and force
13954 * a modeset on all the active ones.
13956 for_each_crtc(state
->dev
, crtc
) {
13957 struct drm_crtc_state
*crtc_state
;
13960 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13961 if (IS_ERR(crtc_state
))
13962 return PTR_ERR(crtc_state
);
13964 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13967 crtc_state
->mode_changed
= true;
13969 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13973 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13981 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13983 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
13984 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
13985 struct drm_crtc
*crtc
;
13986 struct drm_crtc_state
*crtc_state
;
13989 if (!check_digital_port_conflicts(state
)) {
13990 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13994 intel_state
->modeset
= true;
13995 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
13997 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13998 if (crtc_state
->active
)
13999 intel_state
->active_crtcs
|= 1 << i
;
14001 intel_state
->active_crtcs
&= ~(1 << i
);
14003 if (crtc_state
->active
!= crtc
->state
->active
)
14004 intel_state
->active_pipe_changes
|= drm_crtc_mask(crtc
);
14008 * See if the config requires any additional preparation, e.g.
14009 * to adjust global state with pipes off. We need to do this
14010 * here so we can get the modeset_pipe updated config for the new
14011 * mode set on this crtc. For other crtcs we need to use the
14012 * adjusted_mode bits in the crtc directly.
14014 if (dev_priv
->display
.modeset_calc_cdclk
) {
14015 if (!intel_state
->cdclk_pll_vco
)
14016 intel_state
->cdclk_pll_vco
= dev_priv
->cdclk_pll
.vco
;
14017 if (!intel_state
->cdclk_pll_vco
)
14018 intel_state
->cdclk_pll_vco
= dev_priv
->skl_preferred_vco_freq
;
14020 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
14025 * Writes to dev_priv->atomic_cdclk_freq must protected by
14026 * holding all the crtc locks, even if we don't end up
14027 * touching the hardware
14029 if (intel_state
->cdclk
!= dev_priv
->atomic_cdclk_freq
) {
14030 ret
= intel_lock_all_pipes(state
);
14035 /* All pipes must be switched off while we change the cdclk. */
14036 if (intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
||
14037 intel_state
->cdclk_pll_vco
!= dev_priv
->cdclk_pll
.vco
) {
14038 ret
= intel_modeset_all_pipes(state
);
14043 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
14044 intel_state
->cdclk
, intel_state
->dev_cdclk
);
14046 to_intel_atomic_state(state
)->cdclk
= dev_priv
->atomic_cdclk_freq
;
14049 intel_modeset_clear_plls(state
);
14051 if (IS_HASWELL(dev_priv
))
14052 return haswell_mode_set_planes_workaround(state
);
14058 * Handle calculation of various watermark data at the end of the atomic check
14059 * phase. The code here should be run after the per-crtc and per-plane 'check'
14060 * handlers to ensure that all derived state has been updated.
14062 static int calc_watermark_data(struct drm_atomic_state
*state
)
14064 struct drm_device
*dev
= state
->dev
;
14065 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14067 /* Is there platform-specific watermark information to calculate? */
14068 if (dev_priv
->display
.compute_global_watermarks
)
14069 return dev_priv
->display
.compute_global_watermarks(state
);
14075 * intel_atomic_check - validate state object
14077 * @state: state to validate
14079 static int intel_atomic_check(struct drm_device
*dev
,
14080 struct drm_atomic_state
*state
)
14082 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14083 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14084 struct drm_crtc
*crtc
;
14085 struct drm_crtc_state
*crtc_state
;
14087 bool any_ms
= false;
14089 ret
= drm_atomic_helper_check_modeset(dev
, state
);
14093 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
14094 struct intel_crtc_state
*pipe_config
=
14095 to_intel_crtc_state(crtc_state
);
14097 /* Catch I915_MODE_FLAG_INHERITED */
14098 if (crtc_state
->mode
.private_flags
!= crtc
->state
->mode
.private_flags
)
14099 crtc_state
->mode_changed
= true;
14101 if (!needs_modeset(crtc_state
))
14104 if (!crtc_state
->enable
) {
14109 /* FIXME: For only active_changed we shouldn't need to do any
14110 * state recomputation at all. */
14112 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
14116 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
14118 intel_dump_pipe_config(to_intel_crtc(crtc
),
14119 pipe_config
, "[failed]");
14123 if (i915
.fastboot
&&
14124 intel_pipe_config_compare(dev_priv
,
14125 to_intel_crtc_state(crtc
->state
),
14126 pipe_config
, true)) {
14127 crtc_state
->mode_changed
= false;
14128 to_intel_crtc_state(crtc_state
)->update_pipe
= true;
14131 if (needs_modeset(crtc_state
))
14134 ret
= drm_atomic_add_affected_planes(state
, crtc
);
14138 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
14139 needs_modeset(crtc_state
) ?
14140 "[modeset]" : "[fastset]");
14144 ret
= intel_modeset_checks(state
);
14149 intel_state
->cdclk
= dev_priv
->atomic_cdclk_freq
;
14152 ret
= drm_atomic_helper_check_planes(dev
, state
);
14156 intel_fbc_choose_crtc(dev_priv
, state
);
14157 return calc_watermark_data(state
);
14160 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
14161 struct drm_atomic_state
*state
)
14163 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14164 struct drm_crtc_state
*crtc_state
;
14165 struct drm_crtc
*crtc
;
14168 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
14169 if (state
->legacy_cursor_update
)
14172 ret
= intel_crtc_wait_for_pending_flips(crtc
);
14176 if (atomic_read(&to_intel_crtc(crtc
)->unpin_work_count
) >= 2)
14177 flush_workqueue(dev_priv
->wq
);
14180 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
14184 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
14185 mutex_unlock(&dev
->struct_mutex
);
14190 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
14192 struct drm_device
*dev
= crtc
->base
.dev
;
14194 if (!dev
->max_vblank_count
)
14195 return drm_accurate_vblank_count(&crtc
->base
);
14197 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
14200 static void intel_atomic_wait_for_vblanks(struct drm_device
*dev
,
14201 struct drm_i915_private
*dev_priv
,
14202 unsigned crtc_mask
)
14204 unsigned last_vblank_count
[I915_MAX_PIPES
];
14211 for_each_pipe(dev_priv
, pipe
) {
14212 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
,
14215 if (!((1 << pipe
) & crtc_mask
))
14218 ret
= drm_crtc_vblank_get(&crtc
->base
);
14219 if (WARN_ON(ret
!= 0)) {
14220 crtc_mask
&= ~(1 << pipe
);
14224 last_vblank_count
[pipe
] = drm_crtc_vblank_count(&crtc
->base
);
14227 for_each_pipe(dev_priv
, pipe
) {
14228 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
,
14232 if (!((1 << pipe
) & crtc_mask
))
14235 lret
= wait_event_timeout(dev
->vblank
[pipe
].queue
,
14236 last_vblank_count
[pipe
] !=
14237 drm_crtc_vblank_count(&crtc
->base
),
14238 msecs_to_jiffies(50));
14240 WARN(!lret
, "pipe %c vblank wait timed out\n", pipe_name(pipe
));
14242 drm_crtc_vblank_put(&crtc
->base
);
14246 static bool needs_vblank_wait(struct intel_crtc_state
*crtc_state
)
14248 /* fb updated, need to unpin old fb */
14249 if (crtc_state
->fb_changed
)
14252 /* wm changes, need vblank before final wm's */
14253 if (crtc_state
->update_wm_post
)
14257 * cxsr is re-enabled after vblank.
14258 * This is already handled by crtc_state->update_wm_post,
14259 * but added for clarity.
14261 if (crtc_state
->disable_cxsr
)
14267 static void intel_update_crtc(struct drm_crtc
*crtc
,
14268 struct drm_atomic_state
*state
,
14269 struct drm_crtc_state
*old_crtc_state
,
14270 unsigned int *crtc_vblank_mask
)
14272 struct drm_device
*dev
= crtc
->dev
;
14273 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14274 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14275 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc
->state
);
14276 bool modeset
= needs_modeset(crtc
->state
);
14279 update_scanline_offset(intel_crtc
);
14280 dev_priv
->display
.crtc_enable(pipe_config
, state
);
14282 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
14285 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
14287 intel_crtc
, pipe_config
,
14288 to_intel_plane_state(crtc
->primary
->state
));
14291 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state
);
14293 if (needs_vblank_wait(pipe_config
))
14294 *crtc_vblank_mask
|= drm_crtc_mask(crtc
);
14297 static void intel_update_crtcs(struct drm_atomic_state
*state
,
14298 unsigned int *crtc_vblank_mask
)
14300 struct drm_crtc
*crtc
;
14301 struct drm_crtc_state
*old_crtc_state
;
14304 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14305 if (!crtc
->state
->active
)
14308 intel_update_crtc(crtc
, state
, old_crtc_state
,
14313 static void skl_update_crtcs(struct drm_atomic_state
*state
,
14314 unsigned int *crtc_vblank_mask
)
14316 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
14317 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14318 struct drm_crtc
*crtc
;
14319 struct intel_crtc
*intel_crtc
;
14320 struct drm_crtc_state
*old_crtc_state
;
14321 struct intel_crtc_state
*cstate
;
14322 unsigned int updated
= 0;
14327 const struct skl_ddb_entry
*entries
[I915_MAX_PIPES
] = {};
14329 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
)
14330 /* ignore allocations for crtc's that have been turned off. */
14331 if (crtc
->state
->active
)
14332 entries
[i
] = &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
;
14335 * Whenever the number of active pipes changes, we need to make sure we
14336 * update the pipes in the right order so that their ddb allocations
14337 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14338 * cause pipe underruns and other bad stuff.
14343 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14344 bool vbl_wait
= false;
14345 unsigned int cmask
= drm_crtc_mask(crtc
);
14347 intel_crtc
= to_intel_crtc(crtc
);
14348 cstate
= to_intel_crtc_state(crtc
->state
);
14349 pipe
= intel_crtc
->pipe
;
14351 if (updated
& cmask
|| !cstate
->base
.active
)
14354 if (skl_ddb_allocation_overlaps(entries
, &cstate
->wm
.skl
.ddb
, i
))
14358 entries
[i
] = &cstate
->wm
.skl
.ddb
;
14361 * If this is an already active pipe, it's DDB changed,
14362 * and this isn't the last pipe that needs updating
14363 * then we need to wait for a vblank to pass for the
14364 * new ddb allocation to take effect.
14366 if (!skl_ddb_entry_equal(&cstate
->wm
.skl
.ddb
,
14367 &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
) &&
14368 !crtc
->state
->active_changed
&&
14369 intel_state
->wm_results
.dirty_pipes
!= updated
)
14372 intel_update_crtc(crtc
, state
, old_crtc_state
,
14376 intel_wait_for_vblank(dev_priv
, pipe
);
14380 } while (progress
);
14383 static void intel_atomic_commit_tail(struct drm_atomic_state
*state
)
14385 struct drm_device
*dev
= state
->dev
;
14386 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14387 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14388 struct drm_crtc_state
*old_crtc_state
;
14389 struct drm_crtc
*crtc
;
14390 struct intel_crtc_state
*intel_cstate
;
14391 bool hw_check
= intel_state
->modeset
;
14392 unsigned long put_domains
[I915_MAX_PIPES
] = {};
14393 unsigned crtc_vblank_mask
= 0;
14396 drm_atomic_helper_wait_for_dependencies(state
);
14398 if (intel_state
->modeset
)
14399 intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
14401 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14402 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14404 if (needs_modeset(crtc
->state
) ||
14405 to_intel_crtc_state(crtc
->state
)->update_pipe
) {
14408 put_domains
[to_intel_crtc(crtc
)->pipe
] =
14409 modeset_get_crtc_power_domains(crtc
,
14410 to_intel_crtc_state(crtc
->state
));
14413 if (!needs_modeset(crtc
->state
))
14416 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
14418 if (old_crtc_state
->active
) {
14419 intel_crtc_disable_planes(crtc
, old_crtc_state
->plane_mask
);
14420 dev_priv
->display
.crtc_disable(to_intel_crtc_state(old_crtc_state
), state
);
14421 intel_crtc
->active
= false;
14422 intel_fbc_disable(intel_crtc
);
14423 intel_disable_shared_dpll(intel_crtc
);
14426 * Underruns don't always raise
14427 * interrupts, so check manually.
14429 intel_check_cpu_fifo_underruns(dev_priv
);
14430 intel_check_pch_fifo_underruns(dev_priv
);
14432 if (!crtc
->state
->active
) {
14434 * Make sure we don't call initial_watermarks
14435 * for ILK-style watermark updates.
14437 if (dev_priv
->display
.atomic_update_watermarks
)
14438 dev_priv
->display
.initial_watermarks(intel_state
,
14439 to_intel_crtc_state(crtc
->state
));
14441 intel_update_watermarks(intel_crtc
);
14446 /* Only after disabling all output pipelines that will be changed can we
14447 * update the the output configuration. */
14448 intel_modeset_update_crtc_state(state
);
14450 if (intel_state
->modeset
) {
14451 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
14453 if (dev_priv
->display
.modeset_commit_cdclk
&&
14454 (intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
||
14455 intel_state
->cdclk_pll_vco
!= dev_priv
->cdclk_pll
.vco
))
14456 dev_priv
->display
.modeset_commit_cdclk(state
);
14459 * SKL workaround: bspec recommends we disable the SAGV when we
14460 * have more then one pipe enabled
14462 if (!intel_can_enable_sagv(state
))
14463 intel_disable_sagv(dev_priv
);
14465 intel_modeset_verify_disabled(dev
, state
);
14468 /* Complete the events for pipes that have now been disabled */
14469 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14470 bool modeset
= needs_modeset(crtc
->state
);
14472 /* Complete events for now disable pipes here. */
14473 if (modeset
&& !crtc
->state
->active
&& crtc
->state
->event
) {
14474 spin_lock_irq(&dev
->event_lock
);
14475 drm_crtc_send_vblank_event(crtc
, crtc
->state
->event
);
14476 spin_unlock_irq(&dev
->event_lock
);
14478 crtc
->state
->event
= NULL
;
14482 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14483 dev_priv
->display
.update_crtcs(state
, &crtc_vblank_mask
);
14485 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14486 * already, but still need the state for the delayed optimization. To
14488 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14489 * - schedule that vblank worker _before_ calling hw_done
14490 * - at the start of commit_tail, cancel it _synchrously
14491 * - switch over to the vblank wait helper in the core after that since
14492 * we don't need out special handling any more.
14494 if (!state
->legacy_cursor_update
)
14495 intel_atomic_wait_for_vblanks(dev
, dev_priv
, crtc_vblank_mask
);
14498 * Now that the vblank has passed, we can go ahead and program the
14499 * optimal watermarks on platforms that need two-step watermark
14502 * TODO: Move this (and other cleanup) to an async worker eventually.
14504 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14505 intel_cstate
= to_intel_crtc_state(crtc
->state
);
14507 if (dev_priv
->display
.optimize_watermarks
)
14508 dev_priv
->display
.optimize_watermarks(intel_state
,
14512 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14513 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
14515 if (put_domains
[i
])
14516 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
14518 intel_modeset_verify_crtc(crtc
, state
, old_crtc_state
, crtc
->state
);
14521 if (intel_state
->modeset
&& intel_can_enable_sagv(state
))
14522 intel_enable_sagv(dev_priv
);
14524 drm_atomic_helper_commit_hw_done(state
);
14526 if (intel_state
->modeset
)
14527 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
);
14529 mutex_lock(&dev
->struct_mutex
);
14530 drm_atomic_helper_cleanup_planes(dev
, state
);
14531 mutex_unlock(&dev
->struct_mutex
);
14533 drm_atomic_helper_commit_cleanup_done(state
);
14535 drm_atomic_state_put(state
);
14537 /* As one of the primary mmio accessors, KMS has a high likelihood
14538 * of triggering bugs in unclaimed access. After we finish
14539 * modesetting, see if an error has been flagged, and if so
14540 * enable debugging for the next modeset - and hope we catch
14543 * XXX note that we assume display power is on at this point.
14544 * This might hold true now but we need to add pm helper to check
14545 * unclaimed only when the hardware is on, as atomic commits
14546 * can happen also when the device is completely off.
14548 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
14551 static void intel_atomic_commit_work(struct work_struct
*work
)
14553 struct drm_atomic_state
*state
=
14554 container_of(work
, struct drm_atomic_state
, commit_work
);
14556 intel_atomic_commit_tail(state
);
14559 static int __i915_sw_fence_call
14560 intel_atomic_commit_ready(struct i915_sw_fence
*fence
,
14561 enum i915_sw_fence_notify notify
)
14563 struct intel_atomic_state
*state
=
14564 container_of(fence
, struct intel_atomic_state
, commit_ready
);
14567 case FENCE_COMPLETE
:
14568 if (state
->base
.commit_work
.func
)
14569 queue_work(system_unbound_wq
, &state
->base
.commit_work
);
14574 struct intel_atomic_helper
*helper
=
14575 &to_i915(state
->base
.dev
)->atomic_helper
;
14577 if (llist_add(&state
->freed
, &helper
->free_list
))
14578 schedule_work(&helper
->free_work
);
14583 return NOTIFY_DONE
;
14586 static void intel_atomic_track_fbs(struct drm_atomic_state
*state
)
14588 struct drm_plane_state
*old_plane_state
;
14589 struct drm_plane
*plane
;
14592 for_each_plane_in_state(state
, plane
, old_plane_state
, i
)
14593 i915_gem_track_fb(intel_fb_obj(old_plane_state
->fb
),
14594 intel_fb_obj(plane
->state
->fb
),
14595 to_intel_plane(plane
)->frontbuffer_bit
);
14599 * intel_atomic_commit - commit validated state object
14601 * @state: the top-level driver state object
14602 * @nonblock: nonblocking commit
14604 * This function commits a top-level state object that has been validated
14605 * with drm_atomic_helper_check().
14608 * Zero for success or -errno.
14610 static int intel_atomic_commit(struct drm_device
*dev
,
14611 struct drm_atomic_state
*state
,
14614 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14615 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14618 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
14622 drm_atomic_state_get(state
);
14623 i915_sw_fence_init(&intel_state
->commit_ready
,
14624 intel_atomic_commit_ready
);
14626 ret
= intel_atomic_prepare_commit(dev
, state
);
14628 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
14629 i915_sw_fence_commit(&intel_state
->commit_ready
);
14633 drm_atomic_helper_swap_state(state
, true);
14634 dev_priv
->wm
.distrust_bios_wm
= false;
14635 intel_shared_dpll_swap_state(state
);
14636 intel_atomic_track_fbs(state
);
14638 if (intel_state
->modeset
) {
14639 memcpy(dev_priv
->min_pixclk
, intel_state
->min_pixclk
,
14640 sizeof(intel_state
->min_pixclk
));
14641 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
14642 dev_priv
->atomic_cdclk_freq
= intel_state
->cdclk
;
14645 drm_atomic_state_get(state
);
14646 INIT_WORK(&state
->commit_work
,
14647 nonblock
? intel_atomic_commit_work
: NULL
);
14649 i915_sw_fence_commit(&intel_state
->commit_ready
);
14651 i915_sw_fence_wait(&intel_state
->commit_ready
);
14652 intel_atomic_commit_tail(state
);
14658 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
14660 struct drm_device
*dev
= crtc
->dev
;
14661 struct drm_atomic_state
*state
;
14662 struct drm_crtc_state
*crtc_state
;
14665 state
= drm_atomic_state_alloc(dev
);
14667 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14668 crtc
->base
.id
, crtc
->name
);
14672 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
14675 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
14676 ret
= PTR_ERR_OR_ZERO(crtc_state
);
14678 if (!crtc_state
->active
)
14681 crtc_state
->mode_changed
= true;
14682 ret
= drm_atomic_commit(state
);
14685 if (ret
== -EDEADLK
) {
14686 drm_atomic_state_clear(state
);
14687 drm_modeset_backoff(state
->acquire_ctx
);
14692 drm_atomic_state_put(state
);
14696 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14697 * drm_atomic_helper_legacy_gamma_set() directly.
14699 static int intel_atomic_legacy_gamma_set(struct drm_crtc
*crtc
,
14700 u16
*red
, u16
*green
, u16
*blue
,
14703 struct drm_device
*dev
= crtc
->dev
;
14704 struct drm_mode_config
*config
= &dev
->mode_config
;
14705 struct drm_crtc_state
*state
;
14708 ret
= drm_atomic_helper_legacy_gamma_set(crtc
, red
, green
, blue
, size
);
14713 * Make sure we update the legacy properties so this works when
14714 * atomic is not enabled.
14717 state
= crtc
->state
;
14719 drm_object_property_set_value(&crtc
->base
,
14720 config
->degamma_lut_property
,
14721 (state
->degamma_lut
) ?
14722 state
->degamma_lut
->base
.id
: 0);
14724 drm_object_property_set_value(&crtc
->base
,
14725 config
->ctm_property
,
14727 state
->ctm
->base
.id
: 0);
14729 drm_object_property_set_value(&crtc
->base
,
14730 config
->gamma_lut_property
,
14731 (state
->gamma_lut
) ?
14732 state
->gamma_lut
->base
.id
: 0);
14737 static const struct drm_crtc_funcs intel_crtc_funcs
= {
14738 .gamma_set
= intel_atomic_legacy_gamma_set
,
14739 .set_config
= drm_atomic_helper_set_config
,
14740 .set_property
= drm_atomic_helper_crtc_set_property
,
14741 .destroy
= intel_crtc_destroy
,
14742 .page_flip
= intel_crtc_page_flip
,
14743 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
14744 .atomic_destroy_state
= intel_crtc_destroy_state
,
14745 .set_crc_source
= intel_crtc_set_crc_source
,
14749 * intel_prepare_plane_fb - Prepare fb for usage on plane
14750 * @plane: drm plane to prepare for
14751 * @fb: framebuffer to prepare for presentation
14753 * Prepares a framebuffer for usage on a display plane. Generally this
14754 * involves pinning the underlying object and updating the frontbuffer tracking
14755 * bits. Some older platforms need special physical address handling for
14758 * Must be called with struct_mutex held.
14760 * Returns 0 on success, negative error code on failure.
14763 intel_prepare_plane_fb(struct drm_plane
*plane
,
14764 struct drm_plane_state
*new_state
)
14766 struct intel_atomic_state
*intel_state
=
14767 to_intel_atomic_state(new_state
->state
);
14768 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14769 struct drm_framebuffer
*fb
= new_state
->fb
;
14770 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14771 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
14774 if (!obj
&& !old_obj
)
14778 struct drm_crtc_state
*crtc_state
=
14779 drm_atomic_get_existing_crtc_state(new_state
->state
,
14780 plane
->state
->crtc
);
14782 /* Big Hammer, we also need to ensure that any pending
14783 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14784 * current scanout is retired before unpinning the old
14785 * framebuffer. Note that we rely on userspace rendering
14786 * into the buffer attached to the pipe they are waiting
14787 * on. If not, userspace generates a GPU hang with IPEHR
14788 * point to the MI_WAIT_FOR_EVENT.
14790 * This should only fail upon a hung GPU, in which case we
14791 * can safely continue.
14793 if (needs_modeset(crtc_state
)) {
14794 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
14795 old_obj
->resv
, NULL
,
14803 if (new_state
->fence
) { /* explicit fencing */
14804 ret
= i915_sw_fence_await_dma_fence(&intel_state
->commit_ready
,
14806 I915_FENCE_TIMEOUT
,
14815 if (!new_state
->fence
) { /* implicit fencing */
14816 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
14818 false, I915_FENCE_TIMEOUT
,
14823 i915_gem_object_wait_priority(obj
, 0, I915_PRIORITY_DISPLAY
);
14826 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
14827 INTEL_INFO(dev_priv
)->cursor_needs_physical
) {
14828 int align
= IS_I830(dev_priv
) ? 16 * 1024 : 256;
14829 ret
= i915_gem_object_attach_phys(obj
, align
);
14831 DRM_DEBUG_KMS("failed to attach phys object\n");
14835 struct i915_vma
*vma
;
14837 vma
= intel_pin_and_fence_fb_obj(fb
, new_state
->rotation
);
14839 DRM_DEBUG_KMS("failed to pin object\n");
14840 return PTR_ERR(vma
);
14843 to_intel_plane_state(new_state
)->vma
= vma
;
14850 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14851 * @plane: drm plane to clean up for
14852 * @fb: old framebuffer that was on plane
14854 * Cleans up a framebuffer that has just been removed from a plane.
14856 * Must be called with struct_mutex held.
14859 intel_cleanup_plane_fb(struct drm_plane
*plane
,
14860 struct drm_plane_state
*old_state
)
14862 struct i915_vma
*vma
;
14864 /* Should only be called after a successful intel_prepare_plane_fb()! */
14865 vma
= fetch_and_zero(&to_intel_plane_state(old_state
)->vma
);
14867 intel_unpin_fb_vma(vma
);
14871 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
14874 int crtc_clock
, cdclk
;
14876 if (!intel_crtc
|| !crtc_state
->base
.enable
)
14877 return DRM_PLANE_HELPER_NO_SCALING
;
14879 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
14880 cdclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
;
14882 if (WARN_ON_ONCE(!crtc_clock
|| cdclk
< crtc_clock
))
14883 return DRM_PLANE_HELPER_NO_SCALING
;
14886 * skl max scale is lower of:
14887 * close to 3 but not 3, -1 is for that purpose
14891 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
14897 intel_check_primary_plane(struct drm_plane
*plane
,
14898 struct intel_crtc_state
*crtc_state
,
14899 struct intel_plane_state
*state
)
14901 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14902 struct drm_crtc
*crtc
= state
->base
.crtc
;
14903 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
14904 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
14905 bool can_position
= false;
14908 if (INTEL_GEN(dev_priv
) >= 9) {
14909 /* use scaler when colorkey is not required */
14910 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
14912 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
14914 can_position
= true;
14917 ret
= drm_plane_helper_check_state(&state
->base
,
14919 min_scale
, max_scale
,
14920 can_position
, true);
14924 if (!state
->base
.fb
)
14927 if (INTEL_GEN(dev_priv
) >= 9) {
14928 ret
= skl_check_plane_surface(state
);
14936 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
14937 struct drm_crtc_state
*old_crtc_state
)
14939 struct drm_device
*dev
= crtc
->dev
;
14940 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14941 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14942 struct intel_crtc_state
*intel_cstate
=
14943 to_intel_crtc_state(crtc
->state
);
14944 struct intel_crtc_state
*old_intel_cstate
=
14945 to_intel_crtc_state(old_crtc_state
);
14946 struct intel_atomic_state
*old_intel_state
=
14947 to_intel_atomic_state(old_crtc_state
->state
);
14948 bool modeset
= needs_modeset(crtc
->state
);
14950 /* Perform vblank evasion around commit operation */
14951 intel_pipe_update_start(intel_crtc
);
14956 if (crtc
->state
->color_mgmt_changed
|| to_intel_crtc_state(crtc
->state
)->update_pipe
) {
14957 intel_color_set_csc(crtc
->state
);
14958 intel_color_load_luts(crtc
->state
);
14961 if (intel_cstate
->update_pipe
)
14962 intel_update_pipe_config(intel_crtc
, old_intel_cstate
);
14963 else if (INTEL_GEN(dev_priv
) >= 9)
14964 skl_detach_scalers(intel_crtc
);
14967 if (dev_priv
->display
.atomic_update_watermarks
)
14968 dev_priv
->display
.atomic_update_watermarks(old_intel_state
,
14972 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
14973 struct drm_crtc_state
*old_crtc_state
)
14975 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14977 intel_pipe_update_end(intel_crtc
, NULL
);
14981 * intel_plane_destroy - destroy a plane
14982 * @plane: plane to destroy
14984 * Common destruction function for all types of planes (primary, cursor,
14987 void intel_plane_destroy(struct drm_plane
*plane
)
14989 drm_plane_cleanup(plane
);
14990 kfree(to_intel_plane(plane
));
14993 const struct drm_plane_funcs intel_plane_funcs
= {
14994 .update_plane
= drm_atomic_helper_update_plane
,
14995 .disable_plane
= drm_atomic_helper_disable_plane
,
14996 .destroy
= intel_plane_destroy
,
14997 .set_property
= drm_atomic_helper_plane_set_property
,
14998 .atomic_get_property
= intel_plane_atomic_get_property
,
14999 .atomic_set_property
= intel_plane_atomic_set_property
,
15000 .atomic_duplicate_state
= intel_plane_duplicate_state
,
15001 .atomic_destroy_state
= intel_plane_destroy_state
,
15005 intel_legacy_cursor_update(struct drm_plane
*plane
,
15006 struct drm_crtc
*crtc
,
15007 struct drm_framebuffer
*fb
,
15008 int crtc_x
, int crtc_y
,
15009 unsigned int crtc_w
, unsigned int crtc_h
,
15010 uint32_t src_x
, uint32_t src_y
,
15011 uint32_t src_w
, uint32_t src_h
)
15013 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
15015 struct drm_plane_state
*old_plane_state
, *new_plane_state
;
15016 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
15017 struct drm_framebuffer
*old_fb
;
15018 struct drm_crtc_state
*crtc_state
= crtc
->state
;
15019 struct i915_vma
*old_vma
;
15022 * When crtc is inactive or there is a modeset pending,
15023 * wait for it to complete in the slowpath
15025 if (!crtc_state
->active
|| needs_modeset(crtc_state
) ||
15026 to_intel_crtc_state(crtc_state
)->update_pipe
)
15029 old_plane_state
= plane
->state
;
15032 * If any parameters change that may affect watermarks,
15033 * take the slowpath. Only changing fb or position should be
15036 if (old_plane_state
->crtc
!= crtc
||
15037 old_plane_state
->src_w
!= src_w
||
15038 old_plane_state
->src_h
!= src_h
||
15039 old_plane_state
->crtc_w
!= crtc_w
||
15040 old_plane_state
->crtc_h
!= crtc_h
||
15041 !old_plane_state
->visible
||
15042 old_plane_state
->fb
->modifier
!= fb
->modifier
)
15045 new_plane_state
= intel_plane_duplicate_state(plane
);
15046 if (!new_plane_state
)
15049 drm_atomic_set_fb_for_plane(new_plane_state
, fb
);
15051 new_plane_state
->src_x
= src_x
;
15052 new_plane_state
->src_y
= src_y
;
15053 new_plane_state
->src_w
= src_w
;
15054 new_plane_state
->src_h
= src_h
;
15055 new_plane_state
->crtc_x
= crtc_x
;
15056 new_plane_state
->crtc_y
= crtc_y
;
15057 new_plane_state
->crtc_w
= crtc_w
;
15058 new_plane_state
->crtc_h
= crtc_h
;
15060 ret
= intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc
->state
),
15061 to_intel_plane_state(new_plane_state
));
15065 /* Visibility changed, must take slowpath. */
15066 if (!new_plane_state
->visible
)
15069 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
15073 if (INTEL_INFO(dev_priv
)->cursor_needs_physical
) {
15074 int align
= IS_I830(dev_priv
) ? 16 * 1024 : 256;
15076 ret
= i915_gem_object_attach_phys(intel_fb_obj(fb
), align
);
15078 DRM_DEBUG_KMS("failed to attach phys object\n");
15082 struct i915_vma
*vma
;
15084 vma
= intel_pin_and_fence_fb_obj(fb
, new_plane_state
->rotation
);
15086 DRM_DEBUG_KMS("failed to pin object\n");
15088 ret
= PTR_ERR(vma
);
15092 to_intel_plane_state(new_plane_state
)->vma
= vma
;
15095 old_fb
= old_plane_state
->fb
;
15096 old_vma
= to_intel_plane_state(old_plane_state
)->vma
;
15098 i915_gem_track_fb(intel_fb_obj(old_fb
), intel_fb_obj(fb
),
15099 intel_plane
->frontbuffer_bit
);
15101 /* Swap plane state */
15102 new_plane_state
->fence
= old_plane_state
->fence
;
15103 *to_intel_plane_state(old_plane_state
) = *to_intel_plane_state(new_plane_state
);
15104 new_plane_state
->fence
= NULL
;
15105 new_plane_state
->fb
= old_fb
;
15106 to_intel_plane_state(new_plane_state
)->vma
= old_vma
;
15108 intel_plane
->update_plane(plane
,
15109 to_intel_crtc_state(crtc
->state
),
15110 to_intel_plane_state(plane
->state
));
15112 intel_cleanup_plane_fb(plane
, new_plane_state
);
15115 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
15117 intel_plane_destroy_state(plane
, new_plane_state
);
15121 intel_plane_destroy_state(plane
, new_plane_state
);
15123 return drm_atomic_helper_update_plane(plane
, crtc
, fb
,
15124 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
15125 src_x
, src_y
, src_w
, src_h
);
15128 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
15129 .update_plane
= intel_legacy_cursor_update
,
15130 .disable_plane
= drm_atomic_helper_disable_plane
,
15131 .destroy
= intel_plane_destroy
,
15132 .set_property
= drm_atomic_helper_plane_set_property
,
15133 .atomic_get_property
= intel_plane_atomic_get_property
,
15134 .atomic_set_property
= intel_plane_atomic_set_property
,
15135 .atomic_duplicate_state
= intel_plane_duplicate_state
,
15136 .atomic_destroy_state
= intel_plane_destroy_state
,
15139 static struct intel_plane
*
15140 intel_primary_plane_create(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15142 struct intel_plane
*primary
= NULL
;
15143 struct intel_plane_state
*state
= NULL
;
15144 const uint32_t *intel_primary_formats
;
15145 unsigned int supported_rotations
;
15146 unsigned int num_formats
;
15149 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
15155 state
= intel_create_plane_state(&primary
->base
);
15161 primary
->base
.state
= &state
->base
;
15163 primary
->can_scale
= false;
15164 primary
->max_downscale
= 1;
15165 if (INTEL_GEN(dev_priv
) >= 9) {
15166 primary
->can_scale
= true;
15167 state
->scaler_id
= -1;
15169 primary
->pipe
= pipe
;
15171 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15172 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15174 if (HAS_FBC(dev_priv
) && INTEL_GEN(dev_priv
) < 4)
15175 primary
->plane
= (enum plane
) !pipe
;
15177 primary
->plane
= (enum plane
) pipe
;
15178 primary
->id
= PLANE_PRIMARY
;
15179 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
15180 primary
->check_plane
= intel_check_primary_plane
;
15182 if (INTEL_GEN(dev_priv
) >= 9) {
15183 intel_primary_formats
= skl_primary_formats
;
15184 num_formats
= ARRAY_SIZE(skl_primary_formats
);
15186 primary
->update_plane
= skylake_update_primary_plane
;
15187 primary
->disable_plane
= skylake_disable_primary_plane
;
15188 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15189 intel_primary_formats
= i965_primary_formats
;
15190 num_formats
= ARRAY_SIZE(i965_primary_formats
);
15192 primary
->update_plane
= ironlake_update_primary_plane
;
15193 primary
->disable_plane
= i9xx_disable_primary_plane
;
15194 } else if (INTEL_GEN(dev_priv
) >= 4) {
15195 intel_primary_formats
= i965_primary_formats
;
15196 num_formats
= ARRAY_SIZE(i965_primary_formats
);
15198 primary
->update_plane
= i9xx_update_primary_plane
;
15199 primary
->disable_plane
= i9xx_disable_primary_plane
;
15201 intel_primary_formats
= i8xx_primary_formats
;
15202 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
15204 primary
->update_plane
= i9xx_update_primary_plane
;
15205 primary
->disable_plane
= i9xx_disable_primary_plane
;
15208 if (INTEL_GEN(dev_priv
) >= 9)
15209 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
15210 0, &intel_plane_funcs
,
15211 intel_primary_formats
, num_formats
,
15212 DRM_PLANE_TYPE_PRIMARY
,
15213 "plane 1%c", pipe_name(pipe
));
15214 else if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
15215 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
15216 0, &intel_plane_funcs
,
15217 intel_primary_formats
, num_formats
,
15218 DRM_PLANE_TYPE_PRIMARY
,
15219 "primary %c", pipe_name(pipe
));
15221 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
15222 0, &intel_plane_funcs
,
15223 intel_primary_formats
, num_formats
,
15224 DRM_PLANE_TYPE_PRIMARY
,
15225 "plane %c", plane_name(primary
->plane
));
15229 if (INTEL_GEN(dev_priv
) >= 9) {
15230 supported_rotations
=
15231 DRM_ROTATE_0
| DRM_ROTATE_90
|
15232 DRM_ROTATE_180
| DRM_ROTATE_270
;
15233 } else if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
15234 supported_rotations
=
15235 DRM_ROTATE_0
| DRM_ROTATE_180
|
15237 } else if (INTEL_GEN(dev_priv
) >= 4) {
15238 supported_rotations
=
15239 DRM_ROTATE_0
| DRM_ROTATE_180
;
15241 supported_rotations
= DRM_ROTATE_0
;
15244 if (INTEL_GEN(dev_priv
) >= 4)
15245 drm_plane_create_rotation_property(&primary
->base
,
15247 supported_rotations
);
15249 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
15257 return ERR_PTR(ret
);
15261 intel_check_cursor_plane(struct drm_plane
*plane
,
15262 struct intel_crtc_state
*crtc_state
,
15263 struct intel_plane_state
*state
)
15265 struct drm_framebuffer
*fb
= state
->base
.fb
;
15266 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15267 enum pipe pipe
= to_intel_plane(plane
)->pipe
;
15271 ret
= drm_plane_helper_check_state(&state
->base
,
15273 DRM_PLANE_HELPER_NO_SCALING
,
15274 DRM_PLANE_HELPER_NO_SCALING
,
15279 /* if we want to turn off the cursor ignore width and height */
15283 /* Check for which cursor types we support */
15284 if (!cursor_size_ok(to_i915(plane
->dev
), state
->base
.crtc_w
,
15285 state
->base
.crtc_h
)) {
15286 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15287 state
->base
.crtc_w
, state
->base
.crtc_h
);
15291 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
15292 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
15293 DRM_DEBUG_KMS("buffer is too small\n");
15297 if (fb
->modifier
!= DRM_FORMAT_MOD_NONE
) {
15298 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15303 * There's something wrong with the cursor on CHV pipe C.
15304 * If it straddles the left edge of the screen then
15305 * moving it away from the edge or disabling it often
15306 * results in a pipe underrun, and often that can lead to
15307 * dead pipe (constant underrun reported, and it scans
15308 * out just a solid color). To recover from that, the
15309 * display power well must be turned off and on again.
15310 * Refuse the put the cursor into that compromised position.
15312 if (IS_CHERRYVIEW(to_i915(plane
->dev
)) && pipe
== PIPE_C
&&
15313 state
->base
.visible
&& state
->base
.crtc_x
< 0) {
15314 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15322 intel_disable_cursor_plane(struct drm_plane
*plane
,
15323 struct drm_crtc
*crtc
)
15325 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
15327 intel_crtc
->cursor_addr
= 0;
15328 intel_crtc_update_cursor(crtc
, NULL
);
15332 intel_update_cursor_plane(struct drm_plane
*plane
,
15333 const struct intel_crtc_state
*crtc_state
,
15334 const struct intel_plane_state
*state
)
15336 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
15337 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
15338 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
15339 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
15344 else if (!INTEL_INFO(dev_priv
)->cursor_needs_physical
)
15345 addr
= intel_plane_ggtt_offset(state
);
15347 addr
= obj
->phys_handle
->busaddr
;
15349 intel_crtc
->cursor_addr
= addr
;
15350 intel_crtc_update_cursor(crtc
, state
);
15353 static struct intel_plane
*
15354 intel_cursor_plane_create(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15356 struct intel_plane
*cursor
= NULL
;
15357 struct intel_plane_state
*state
= NULL
;
15360 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
15366 state
= intel_create_plane_state(&cursor
->base
);
15372 cursor
->base
.state
= &state
->base
;
15374 cursor
->can_scale
= false;
15375 cursor
->max_downscale
= 1;
15376 cursor
->pipe
= pipe
;
15377 cursor
->plane
= pipe
;
15378 cursor
->id
= PLANE_CURSOR
;
15379 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
15380 cursor
->check_plane
= intel_check_cursor_plane
;
15381 cursor
->update_plane
= intel_update_cursor_plane
;
15382 cursor
->disable_plane
= intel_disable_cursor_plane
;
15384 ret
= drm_universal_plane_init(&dev_priv
->drm
, &cursor
->base
,
15385 0, &intel_cursor_plane_funcs
,
15386 intel_cursor_formats
,
15387 ARRAY_SIZE(intel_cursor_formats
),
15388 DRM_PLANE_TYPE_CURSOR
,
15389 "cursor %c", pipe_name(pipe
));
15393 if (INTEL_GEN(dev_priv
) >= 4)
15394 drm_plane_create_rotation_property(&cursor
->base
,
15399 if (INTEL_GEN(dev_priv
) >= 9)
15400 state
->scaler_id
= -1;
15402 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
15410 return ERR_PTR(ret
);
15413 static void intel_crtc_init_scalers(struct intel_crtc
*crtc
,
15414 struct intel_crtc_state
*crtc_state
)
15416 struct intel_crtc_scaler_state
*scaler_state
=
15417 &crtc_state
->scaler_state
;
15418 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
15421 crtc
->num_scalers
= dev_priv
->info
.num_scalers
[crtc
->pipe
];
15422 if (!crtc
->num_scalers
)
15425 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
15426 struct intel_scaler
*scaler
= &scaler_state
->scalers
[i
];
15428 scaler
->in_use
= 0;
15429 scaler
->mode
= PS_SCALER_MODE_DYN
;
15432 scaler_state
->scaler_id
= -1;
15435 static int intel_crtc_init(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15437 struct intel_crtc
*intel_crtc
;
15438 struct intel_crtc_state
*crtc_state
= NULL
;
15439 struct intel_plane
*primary
= NULL
;
15440 struct intel_plane
*cursor
= NULL
;
15443 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
15447 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
15452 intel_crtc
->config
= crtc_state
;
15453 intel_crtc
->base
.state
= &crtc_state
->base
;
15454 crtc_state
->base
.crtc
= &intel_crtc
->base
;
15456 primary
= intel_primary_plane_create(dev_priv
, pipe
);
15457 if (IS_ERR(primary
)) {
15458 ret
= PTR_ERR(primary
);
15461 intel_crtc
->plane_ids_mask
|= BIT(primary
->id
);
15463 for_each_sprite(dev_priv
, pipe
, sprite
) {
15464 struct intel_plane
*plane
;
15466 plane
= intel_sprite_plane_create(dev_priv
, pipe
, sprite
);
15467 if (IS_ERR(plane
)) {
15468 ret
= PTR_ERR(plane
);
15471 intel_crtc
->plane_ids_mask
|= BIT(plane
->id
);
15474 cursor
= intel_cursor_plane_create(dev_priv
, pipe
);
15475 if (IS_ERR(cursor
)) {
15476 ret
= PTR_ERR(cursor
);
15479 intel_crtc
->plane_ids_mask
|= BIT(cursor
->id
);
15481 ret
= drm_crtc_init_with_planes(&dev_priv
->drm
, &intel_crtc
->base
,
15482 &primary
->base
, &cursor
->base
,
15484 "pipe %c", pipe_name(pipe
));
15488 intel_crtc
->pipe
= pipe
;
15489 intel_crtc
->plane
= primary
->plane
;
15491 intel_crtc
->cursor_base
= ~0;
15492 intel_crtc
->cursor_cntl
= ~0;
15493 intel_crtc
->cursor_size
= ~0;
15495 intel_crtc
->wm
.cxsr_allowed
= true;
15497 /* initialize shared scalers */
15498 intel_crtc_init_scalers(intel_crtc
, crtc_state
);
15500 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
15501 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
15502 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = intel_crtc
;
15503 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = intel_crtc
;
15505 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
15507 intel_color_init(&intel_crtc
->base
);
15509 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
15515 * drm_mode_config_cleanup() will free up any
15516 * crtcs/planes already initialized.
15524 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
15526 struct drm_encoder
*encoder
= connector
->base
.encoder
;
15527 struct drm_device
*dev
= connector
->base
.dev
;
15529 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
15531 if (!encoder
|| WARN_ON(!encoder
->crtc
))
15532 return INVALID_PIPE
;
15534 return to_intel_crtc(encoder
->crtc
)->pipe
;
15537 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
15538 struct drm_file
*file
)
15540 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
15541 struct drm_crtc
*drmmode_crtc
;
15542 struct intel_crtc
*crtc
;
15544 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
15548 crtc
= to_intel_crtc(drmmode_crtc
);
15549 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
15554 static int intel_encoder_clones(struct intel_encoder
*encoder
)
15556 struct drm_device
*dev
= encoder
->base
.dev
;
15557 struct intel_encoder
*source_encoder
;
15558 int index_mask
= 0;
15561 for_each_intel_encoder(dev
, source_encoder
) {
15562 if (encoders_cloneable(encoder
, source_encoder
))
15563 index_mask
|= (1 << entry
);
15571 static bool has_edp_a(struct drm_i915_private
*dev_priv
)
15573 if (!IS_MOBILE(dev_priv
))
15576 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
15579 if (IS_GEN5(dev_priv
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
15585 static bool intel_crt_present(struct drm_i915_private
*dev_priv
)
15587 if (INTEL_GEN(dev_priv
) >= 9)
15590 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
15593 if (IS_CHERRYVIEW(dev_priv
))
15596 if (HAS_PCH_LPT_H(dev_priv
) &&
15597 I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
15600 /* DDI E can't be used if DDI A requires 4 lanes */
15601 if (HAS_DDI(dev_priv
) && I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
15604 if (!dev_priv
->vbt
.int_crt_support
)
15610 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
)
15615 if (HAS_DDI(dev_priv
))
15618 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15619 * everywhere where registers can be write protected.
15621 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15626 for (pps_idx
= 0; pps_idx
< pps_num
; pps_idx
++) {
15627 u32 val
= I915_READ(PP_CONTROL(pps_idx
));
15629 val
= (val
& ~PANEL_UNLOCK_MASK
) | PANEL_UNLOCK_REGS
;
15630 I915_WRITE(PP_CONTROL(pps_idx
), val
);
15634 static void intel_pps_init(struct drm_i915_private
*dev_priv
)
15636 if (HAS_PCH_SPLIT(dev_priv
) || IS_GEN9_LP(dev_priv
))
15637 dev_priv
->pps_mmio_base
= PCH_PPS_BASE
;
15638 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15639 dev_priv
->pps_mmio_base
= VLV_PPS_BASE
;
15641 dev_priv
->pps_mmio_base
= PPS_BASE
;
15643 intel_pps_unlock_regs_wa(dev_priv
);
15646 static void intel_setup_outputs(struct drm_i915_private
*dev_priv
)
15648 struct intel_encoder
*encoder
;
15649 bool dpd_is_edp
= false;
15651 intel_pps_init(dev_priv
);
15654 * intel_edp_init_connector() depends on this completing first, to
15655 * prevent the registeration of both eDP and LVDS and the incorrect
15656 * sharing of the PPS.
15658 intel_lvds_init(dev_priv
);
15660 if (intel_crt_present(dev_priv
))
15661 intel_crt_init(dev_priv
);
15663 if (IS_GEN9_LP(dev_priv
)) {
15665 * FIXME: Broxton doesn't support port detection via the
15666 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15667 * detect the ports.
15669 intel_ddi_init(dev_priv
, PORT_A
);
15670 intel_ddi_init(dev_priv
, PORT_B
);
15671 intel_ddi_init(dev_priv
, PORT_C
);
15673 intel_dsi_init(dev_priv
);
15674 } else if (HAS_DDI(dev_priv
)) {
15678 * Haswell uses DDI functions to detect digital outputs.
15679 * On SKL pre-D0 the strap isn't connected, so we assume
15682 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
15683 /* WaIgnoreDDIAStrap: skl */
15684 if (found
|| IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
15685 intel_ddi_init(dev_priv
, PORT_A
);
15687 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15689 found
= I915_READ(SFUSE_STRAP
);
15691 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
15692 intel_ddi_init(dev_priv
, PORT_B
);
15693 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
15694 intel_ddi_init(dev_priv
, PORT_C
);
15695 if (found
& SFUSE_STRAP_DDID_DETECTED
)
15696 intel_ddi_init(dev_priv
, PORT_D
);
15698 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15700 if ((IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) &&
15701 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
15702 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
15703 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
15704 intel_ddi_init(dev_priv
, PORT_E
);
15706 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15708 dpd_is_edp
= intel_dp_is_edp(dev_priv
, PORT_D
);
15710 if (has_edp_a(dev_priv
))
15711 intel_dp_init(dev_priv
, DP_A
, PORT_A
);
15713 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
15714 /* PCH SDVOB multiplex with HDMIB */
15715 found
= intel_sdvo_init(dev_priv
, PCH_SDVOB
, PORT_B
);
15717 intel_hdmi_init(dev_priv
, PCH_HDMIB
, PORT_B
);
15718 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
15719 intel_dp_init(dev_priv
, PCH_DP_B
, PORT_B
);
15722 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
15723 intel_hdmi_init(dev_priv
, PCH_HDMIC
, PORT_C
);
15725 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
15726 intel_hdmi_init(dev_priv
, PCH_HDMID
, PORT_D
);
15728 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
15729 intel_dp_init(dev_priv
, PCH_DP_C
, PORT_C
);
15731 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
15732 intel_dp_init(dev_priv
, PCH_DP_D
, PORT_D
);
15733 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15734 bool has_edp
, has_port
;
15737 * The DP_DETECTED bit is the latched state of the DDC
15738 * SDA pin at boot. However since eDP doesn't require DDC
15739 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15740 * eDP ports may have been muxed to an alternate function.
15741 * Thus we can't rely on the DP_DETECTED bit alone to detect
15742 * eDP ports. Consult the VBT as well as DP_DETECTED to
15743 * detect eDP ports.
15745 * Sadly the straps seem to be missing sometimes even for HDMI
15746 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15747 * and VBT for the presence of the port. Additionally we can't
15748 * trust the port type the VBT declares as we've seen at least
15749 * HDMI ports that the VBT claim are DP or eDP.
15751 has_edp
= intel_dp_is_edp(dev_priv
, PORT_B
);
15752 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
15753 if (I915_READ(VLV_DP_B
) & DP_DETECTED
|| has_port
)
15754 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_B
, PORT_B
);
15755 if ((I915_READ(VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
15756 intel_hdmi_init(dev_priv
, VLV_HDMIB
, PORT_B
);
15758 has_edp
= intel_dp_is_edp(dev_priv
, PORT_C
);
15759 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
15760 if (I915_READ(VLV_DP_C
) & DP_DETECTED
|| has_port
)
15761 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_C
, PORT_C
);
15762 if ((I915_READ(VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
15763 intel_hdmi_init(dev_priv
, VLV_HDMIC
, PORT_C
);
15765 if (IS_CHERRYVIEW(dev_priv
)) {
15767 * eDP not supported on port D,
15768 * so no need to worry about it
15770 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
15771 if (I915_READ(CHV_DP_D
) & DP_DETECTED
|| has_port
)
15772 intel_dp_init(dev_priv
, CHV_DP_D
, PORT_D
);
15773 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
15774 intel_hdmi_init(dev_priv
, CHV_HDMID
, PORT_D
);
15777 intel_dsi_init(dev_priv
);
15778 } else if (!IS_GEN2(dev_priv
) && !IS_PINEVIEW(dev_priv
)) {
15779 bool found
= false;
15781 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
15782 DRM_DEBUG_KMS("probing SDVOB\n");
15783 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOB
, PORT_B
);
15784 if (!found
&& IS_G4X(dev_priv
)) {
15785 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15786 intel_hdmi_init(dev_priv
, GEN4_HDMIB
, PORT_B
);
15789 if (!found
&& IS_G4X(dev_priv
))
15790 intel_dp_init(dev_priv
, DP_B
, PORT_B
);
15793 /* Before G4X SDVOC doesn't have its own detect register */
15795 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
15796 DRM_DEBUG_KMS("probing SDVOC\n");
15797 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOC
, PORT_C
);
15800 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
15802 if (IS_G4X(dev_priv
)) {
15803 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15804 intel_hdmi_init(dev_priv
, GEN4_HDMIC
, PORT_C
);
15806 if (IS_G4X(dev_priv
))
15807 intel_dp_init(dev_priv
, DP_C
, PORT_C
);
15810 if (IS_G4X(dev_priv
) && (I915_READ(DP_D
) & DP_DETECTED
))
15811 intel_dp_init(dev_priv
, DP_D
, PORT_D
);
15812 } else if (IS_GEN2(dev_priv
))
15813 intel_dvo_init(dev_priv
);
15815 if (SUPPORTS_TV(dev_priv
))
15816 intel_tv_init(dev_priv
);
15818 intel_psr_init(dev_priv
);
15820 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
15821 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
15822 encoder
->base
.possible_clones
=
15823 intel_encoder_clones(encoder
);
15826 intel_init_pch_refclk(dev_priv
);
15828 drm_helper_move_panel_connectors_to_head(&dev_priv
->drm
);
15831 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
15833 struct drm_device
*dev
= fb
->dev
;
15834 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
15836 drm_framebuffer_cleanup(fb
);
15837 mutex_lock(&dev
->struct_mutex
);
15838 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
15839 i915_gem_object_put(intel_fb
->obj
);
15840 mutex_unlock(&dev
->struct_mutex
);
15844 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
15845 struct drm_file
*file
,
15846 unsigned int *handle
)
15848 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
15849 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
15851 if (obj
->userptr
.mm
) {
15852 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15856 return drm_gem_handle_create(file
, &obj
->base
, handle
);
15859 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
15860 struct drm_file
*file
,
15861 unsigned flags
, unsigned color
,
15862 struct drm_clip_rect
*clips
,
15863 unsigned num_clips
)
15865 struct drm_device
*dev
= fb
->dev
;
15866 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
15867 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
15869 mutex_lock(&dev
->struct_mutex
);
15870 if (obj
->pin_display
&& obj
->cache_dirty
)
15871 i915_gem_clflush_object(obj
, true);
15872 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
15873 mutex_unlock(&dev
->struct_mutex
);
15878 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
15879 .destroy
= intel_user_framebuffer_destroy
,
15880 .create_handle
= intel_user_framebuffer_create_handle
,
15881 .dirty
= intel_user_framebuffer_dirty
,
15885 u32
intel_fb_pitch_limit(struct drm_i915_private
*dev_priv
,
15886 uint64_t fb_modifier
, uint32_t pixel_format
)
15888 u32 gen
= INTEL_INFO(dev_priv
)->gen
;
15891 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
15893 /* "The stride in bytes must not exceed the of the size of 8K
15894 * pixels and 32K bytes."
15896 return min(8192 * cpp
, 32768);
15897 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev_priv
) &&
15898 !IS_CHERRYVIEW(dev_priv
)) {
15900 } else if (gen
>= 4) {
15901 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
15905 } else if (gen
>= 3) {
15906 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
15911 /* XXX DSPC is limited to 4k tiled */
15916 static int intel_framebuffer_init(struct drm_device
*dev
,
15917 struct intel_framebuffer
*intel_fb
,
15918 struct drm_mode_fb_cmd2
*mode_cmd
,
15919 struct drm_i915_gem_object
*obj
)
15921 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15922 unsigned int tiling
= i915_gem_object_get_tiling(obj
);
15924 u32 pitch_limit
, stride_alignment
;
15925 struct drm_format_name_buf format_name
;
15927 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
15929 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
15931 * If there's a fence, enforce that
15932 * the fb modifier and tiling mode match.
15934 if (tiling
!= I915_TILING_NONE
&&
15935 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15936 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15940 if (tiling
== I915_TILING_X
) {
15941 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
15942 } else if (tiling
== I915_TILING_Y
) {
15943 DRM_DEBUG("No Y tiling for legacy addfb\n");
15948 /* Passed in modifier sanity checking. */
15949 switch (mode_cmd
->modifier
[0]) {
15950 case I915_FORMAT_MOD_Y_TILED
:
15951 case I915_FORMAT_MOD_Yf_TILED
:
15952 if (INTEL_GEN(dev_priv
) < 9) {
15953 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15954 mode_cmd
->modifier
[0]);
15957 case DRM_FORMAT_MOD_NONE
:
15958 case I915_FORMAT_MOD_X_TILED
:
15961 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15962 mode_cmd
->modifier
[0]);
15967 * gen2/3 display engine uses the fence if present,
15968 * so the tiling mode must match the fb modifier exactly.
15970 if (INTEL_INFO(dev_priv
)->gen
< 4 &&
15971 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15972 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15976 stride_alignment
= intel_fb_stride_alignment(dev_priv
,
15977 mode_cmd
->modifier
[0],
15978 mode_cmd
->pixel_format
);
15979 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
15980 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15981 mode_cmd
->pitches
[0], stride_alignment
);
15985 pitch_limit
= intel_fb_pitch_limit(dev_priv
, mode_cmd
->modifier
[0],
15986 mode_cmd
->pixel_format
);
15987 if (mode_cmd
->pitches
[0] > pitch_limit
) {
15988 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15989 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
15990 "tiled" : "linear",
15991 mode_cmd
->pitches
[0], pitch_limit
);
15996 * If there's a fence, enforce that
15997 * the fb pitch and fence stride match.
15999 if (tiling
!= I915_TILING_NONE
&&
16000 mode_cmd
->pitches
[0] != i915_gem_object_get_stride(obj
)) {
16001 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
16002 mode_cmd
->pitches
[0],
16003 i915_gem_object_get_stride(obj
));
16007 /* Reject formats not supported by any plane early. */
16008 switch (mode_cmd
->pixel_format
) {
16009 case DRM_FORMAT_C8
:
16010 case DRM_FORMAT_RGB565
:
16011 case DRM_FORMAT_XRGB8888
:
16012 case DRM_FORMAT_ARGB8888
:
16014 case DRM_FORMAT_XRGB1555
:
16015 if (INTEL_GEN(dev_priv
) > 3) {
16016 DRM_DEBUG("unsupported pixel format: %s\n",
16017 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
16021 case DRM_FORMAT_ABGR8888
:
16022 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
16023 INTEL_GEN(dev_priv
) < 9) {
16024 DRM_DEBUG("unsupported pixel format: %s\n",
16025 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
16029 case DRM_FORMAT_XBGR8888
:
16030 case DRM_FORMAT_XRGB2101010
:
16031 case DRM_FORMAT_XBGR2101010
:
16032 if (INTEL_GEN(dev_priv
) < 4) {
16033 DRM_DEBUG("unsupported pixel format: %s\n",
16034 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
16038 case DRM_FORMAT_ABGR2101010
:
16039 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
16040 DRM_DEBUG("unsupported pixel format: %s\n",
16041 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
16045 case DRM_FORMAT_YUYV
:
16046 case DRM_FORMAT_UYVY
:
16047 case DRM_FORMAT_YVYU
:
16048 case DRM_FORMAT_VYUY
:
16049 if (INTEL_GEN(dev_priv
) < 5) {
16050 DRM_DEBUG("unsupported pixel format: %s\n",
16051 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
16056 DRM_DEBUG("unsupported pixel format: %s\n",
16057 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
16061 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
16062 if (mode_cmd
->offsets
[0] != 0)
16065 drm_helper_mode_fill_fb_struct(dev
, &intel_fb
->base
, mode_cmd
);
16066 intel_fb
->obj
= obj
;
16068 ret
= intel_fill_fb_info(dev_priv
, &intel_fb
->base
);
16072 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
16074 DRM_ERROR("framebuffer init failed %d\n", ret
);
16078 intel_fb
->obj
->framebuffer_references
++;
16083 static struct drm_framebuffer
*
16084 intel_user_framebuffer_create(struct drm_device
*dev
,
16085 struct drm_file
*filp
,
16086 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
16088 struct drm_framebuffer
*fb
;
16089 struct drm_i915_gem_object
*obj
;
16090 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
16092 obj
= i915_gem_object_lookup(filp
, mode_cmd
.handles
[0]);
16094 return ERR_PTR(-ENOENT
);
16096 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
16098 i915_gem_object_put(obj
);
16103 static void intel_atomic_state_free(struct drm_atomic_state
*state
)
16105 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
16107 drm_atomic_state_default_release(state
);
16109 i915_sw_fence_fini(&intel_state
->commit_ready
);
16114 static const struct drm_mode_config_funcs intel_mode_funcs
= {
16115 .fb_create
= intel_user_framebuffer_create
,
16116 .output_poll_changed
= intel_fbdev_output_poll_changed
,
16117 .atomic_check
= intel_atomic_check
,
16118 .atomic_commit
= intel_atomic_commit
,
16119 .atomic_state_alloc
= intel_atomic_state_alloc
,
16120 .atomic_state_clear
= intel_atomic_state_clear
,
16121 .atomic_state_free
= intel_atomic_state_free
,
16125 * intel_init_display_hooks - initialize the display modesetting hooks
16126 * @dev_priv: device private
16128 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
16130 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
16131 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
16132 dev_priv
->display
.get_initial_plane_config
=
16133 skylake_get_initial_plane_config
;
16134 dev_priv
->display
.crtc_compute_clock
=
16135 haswell_crtc_compute_clock
;
16136 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
16137 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
16138 } else if (HAS_DDI(dev_priv
)) {
16139 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
16140 dev_priv
->display
.get_initial_plane_config
=
16141 ironlake_get_initial_plane_config
;
16142 dev_priv
->display
.crtc_compute_clock
=
16143 haswell_crtc_compute_clock
;
16144 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
16145 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
16146 } else if (HAS_PCH_SPLIT(dev_priv
)) {
16147 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
16148 dev_priv
->display
.get_initial_plane_config
=
16149 ironlake_get_initial_plane_config
;
16150 dev_priv
->display
.crtc_compute_clock
=
16151 ironlake_crtc_compute_clock
;
16152 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
16153 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
16154 } else if (IS_CHERRYVIEW(dev_priv
)) {
16155 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16156 dev_priv
->display
.get_initial_plane_config
=
16157 i9xx_get_initial_plane_config
;
16158 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
16159 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
16160 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16161 } else if (IS_VALLEYVIEW(dev_priv
)) {
16162 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16163 dev_priv
->display
.get_initial_plane_config
=
16164 i9xx_get_initial_plane_config
;
16165 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
16166 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
16167 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16168 } else if (IS_G4X(dev_priv
)) {
16169 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16170 dev_priv
->display
.get_initial_plane_config
=
16171 i9xx_get_initial_plane_config
;
16172 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
16173 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
16174 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16175 } else if (IS_PINEVIEW(dev_priv
)) {
16176 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16177 dev_priv
->display
.get_initial_plane_config
=
16178 i9xx_get_initial_plane_config
;
16179 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
16180 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
16181 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16182 } else if (!IS_GEN2(dev_priv
)) {
16183 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16184 dev_priv
->display
.get_initial_plane_config
=
16185 i9xx_get_initial_plane_config
;
16186 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
16187 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
16188 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16190 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16191 dev_priv
->display
.get_initial_plane_config
=
16192 i9xx_get_initial_plane_config
;
16193 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
16194 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
16195 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16198 /* Returns the core display clock speed */
16199 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
16200 dev_priv
->display
.get_display_clock_speed
=
16201 skylake_get_display_clock_speed
;
16202 else if (IS_GEN9_LP(dev_priv
))
16203 dev_priv
->display
.get_display_clock_speed
=
16204 broxton_get_display_clock_speed
;
16205 else if (IS_BROADWELL(dev_priv
))
16206 dev_priv
->display
.get_display_clock_speed
=
16207 broadwell_get_display_clock_speed
;
16208 else if (IS_HASWELL(dev_priv
))
16209 dev_priv
->display
.get_display_clock_speed
=
16210 haswell_get_display_clock_speed
;
16211 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
16212 dev_priv
->display
.get_display_clock_speed
=
16213 valleyview_get_display_clock_speed
;
16214 else if (IS_GEN5(dev_priv
))
16215 dev_priv
->display
.get_display_clock_speed
=
16216 ilk_get_display_clock_speed
;
16217 else if (IS_I945G(dev_priv
) || IS_I965G(dev_priv
) ||
16218 IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
))
16219 dev_priv
->display
.get_display_clock_speed
=
16220 i945_get_display_clock_speed
;
16221 else if (IS_GM45(dev_priv
))
16222 dev_priv
->display
.get_display_clock_speed
=
16223 gm45_get_display_clock_speed
;
16224 else if (IS_I965GM(dev_priv
))
16225 dev_priv
->display
.get_display_clock_speed
=
16226 i965gm_get_display_clock_speed
;
16227 else if (IS_PINEVIEW(dev_priv
))
16228 dev_priv
->display
.get_display_clock_speed
=
16229 pnv_get_display_clock_speed
;
16230 else if (IS_G33(dev_priv
) || IS_G4X(dev_priv
))
16231 dev_priv
->display
.get_display_clock_speed
=
16232 g33_get_display_clock_speed
;
16233 else if (IS_I915G(dev_priv
))
16234 dev_priv
->display
.get_display_clock_speed
=
16235 i915_get_display_clock_speed
;
16236 else if (IS_I945GM(dev_priv
) || IS_I845G(dev_priv
))
16237 dev_priv
->display
.get_display_clock_speed
=
16238 i9xx_misc_get_display_clock_speed
;
16239 else if (IS_I915GM(dev_priv
))
16240 dev_priv
->display
.get_display_clock_speed
=
16241 i915gm_get_display_clock_speed
;
16242 else if (IS_I865G(dev_priv
))
16243 dev_priv
->display
.get_display_clock_speed
=
16244 i865_get_display_clock_speed
;
16245 else if (IS_I85X(dev_priv
))
16246 dev_priv
->display
.get_display_clock_speed
=
16247 i85x_get_display_clock_speed
;
16249 WARN(!IS_I830(dev_priv
), "Unknown platform. Assuming 133 MHz CDCLK\n");
16250 dev_priv
->display
.get_display_clock_speed
=
16251 i830_get_display_clock_speed
;
16254 if (IS_GEN5(dev_priv
)) {
16255 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
16256 } else if (IS_GEN6(dev_priv
)) {
16257 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
16258 } else if (IS_IVYBRIDGE(dev_priv
)) {
16259 /* FIXME: detect B0+ stepping and use auto training */
16260 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
16261 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
16262 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
16265 if (IS_BROADWELL(dev_priv
)) {
16266 dev_priv
->display
.modeset_commit_cdclk
=
16267 broadwell_modeset_commit_cdclk
;
16268 dev_priv
->display
.modeset_calc_cdclk
=
16269 broadwell_modeset_calc_cdclk
;
16270 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
16271 dev_priv
->display
.modeset_commit_cdclk
=
16272 valleyview_modeset_commit_cdclk
;
16273 dev_priv
->display
.modeset_calc_cdclk
=
16274 valleyview_modeset_calc_cdclk
;
16275 } else if (IS_GEN9_LP(dev_priv
)) {
16276 dev_priv
->display
.modeset_commit_cdclk
=
16277 bxt_modeset_commit_cdclk
;
16278 dev_priv
->display
.modeset_calc_cdclk
=
16279 bxt_modeset_calc_cdclk
;
16280 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
16281 dev_priv
->display
.modeset_commit_cdclk
=
16282 skl_modeset_commit_cdclk
;
16283 dev_priv
->display
.modeset_calc_cdclk
=
16284 skl_modeset_calc_cdclk
;
16287 if (dev_priv
->info
.gen
>= 9)
16288 dev_priv
->display
.update_crtcs
= skl_update_crtcs
;
16290 dev_priv
->display
.update_crtcs
= intel_update_crtcs
;
16292 switch (INTEL_INFO(dev_priv
)->gen
) {
16294 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
16298 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
16303 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
16307 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
16310 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16311 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
16314 /* Drop through - unsupported since execlist only. */
16316 /* Default just returns -ENODEV to indicate unsupported */
16317 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
16322 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16323 * resume, or other times. This quirk makes sure that's the case for
16324 * affected systems.
16326 static void quirk_pipea_force(struct drm_device
*dev
)
16328 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16330 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
16331 DRM_INFO("applying pipe a force quirk\n");
16334 static void quirk_pipeb_force(struct drm_device
*dev
)
16336 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16338 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
16339 DRM_INFO("applying pipe b force quirk\n");
16343 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16345 static void quirk_ssc_force_disable(struct drm_device
*dev
)
16347 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16348 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
16349 DRM_INFO("applying lvds SSC disable quirk\n");
16353 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16356 static void quirk_invert_brightness(struct drm_device
*dev
)
16358 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16359 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
16360 DRM_INFO("applying inverted panel brightness quirk\n");
16363 /* Some VBT's incorrectly indicate no backlight is present */
16364 static void quirk_backlight_present(struct drm_device
*dev
)
16366 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16367 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
16368 DRM_INFO("applying backlight present quirk\n");
16371 struct intel_quirk
{
16373 int subsystem_vendor
;
16374 int subsystem_device
;
16375 void (*hook
)(struct drm_device
*dev
);
16378 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16379 struct intel_dmi_quirk
{
16380 void (*hook
)(struct drm_device
*dev
);
16381 const struct dmi_system_id (*dmi_id_list
)[];
16384 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
16386 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
16390 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
16392 .dmi_id_list
= &(const struct dmi_system_id
[]) {
16394 .callback
= intel_dmi_reverse_brightness
,
16395 .ident
= "NCR Corporation",
16396 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
16397 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
16400 { } /* terminating entry */
16402 .hook
= quirk_invert_brightness
,
16406 static struct intel_quirk intel_quirks
[] = {
16407 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16408 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
16410 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16411 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
16413 /* 830 needs to leave pipe A & dpll A up */
16414 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
16416 /* 830 needs to leave pipe B & dpll B up */
16417 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
16419 /* Lenovo U160 cannot use SSC on LVDS */
16420 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
16422 /* Sony Vaio Y cannot use SSC on LVDS */
16423 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
16425 /* Acer Aspire 5734Z must invert backlight brightness */
16426 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
16428 /* Acer/eMachines G725 */
16429 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
16431 /* Acer/eMachines e725 */
16432 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
16434 /* Acer/Packard Bell NCL20 */
16435 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
16437 /* Acer Aspire 4736Z */
16438 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
16440 /* Acer Aspire 5336 */
16441 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
16443 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16444 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
16446 /* Acer C720 Chromebook (Core i3 4005U) */
16447 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
16449 /* Apple Macbook 2,1 (Core 2 T7400) */
16450 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
16452 /* Apple Macbook 4,1 */
16453 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present
},
16455 /* Toshiba CB35 Chromebook (Celeron 2955U) */
16456 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
16458 /* HP Chromebook 14 (Celeron 2955U) */
16459 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
16461 /* Dell Chromebook 11 */
16462 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
16464 /* Dell Chromebook 11 (2015 version) */
16465 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present
},
16468 static void intel_init_quirks(struct drm_device
*dev
)
16470 struct pci_dev
*d
= dev
->pdev
;
16473 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
16474 struct intel_quirk
*q
= &intel_quirks
[i
];
16476 if (d
->device
== q
->device
&&
16477 (d
->subsystem_vendor
== q
->subsystem_vendor
||
16478 q
->subsystem_vendor
== PCI_ANY_ID
) &&
16479 (d
->subsystem_device
== q
->subsystem_device
||
16480 q
->subsystem_device
== PCI_ANY_ID
))
16483 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
16484 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
16485 intel_dmi_quirks
[i
].hook(dev
);
16489 /* Disable the VGA plane that we never use */
16490 static void i915_disable_vga(struct drm_i915_private
*dev_priv
)
16492 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
16494 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
16496 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16497 vga_get_uninterruptible(pdev
, VGA_RSRC_LEGACY_IO
);
16498 outb(SR01
, VGA_SR_INDEX
);
16499 sr1
= inb(VGA_SR_DATA
);
16500 outb(sr1
| 1<<5, VGA_SR_DATA
);
16501 vga_put(pdev
, VGA_RSRC_LEGACY_IO
);
16504 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
16505 POSTING_READ(vga_reg
);
16508 void intel_modeset_init_hw(struct drm_device
*dev
)
16510 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16512 intel_update_cdclk(dev_priv
);
16514 dev_priv
->atomic_cdclk_freq
= dev_priv
->cdclk_freq
;
16516 intel_init_clock_gating(dev_priv
);
16520 * Calculate what we think the watermarks should be for the state we've read
16521 * out of the hardware and then immediately program those watermarks so that
16522 * we ensure the hardware settings match our internal state.
16524 * We can calculate what we think WM's should be by creating a duplicate of the
16525 * current state (which was constructed during hardware readout) and running it
16526 * through the atomic check code to calculate new watermark values in the
16529 static void sanitize_watermarks(struct drm_device
*dev
)
16531 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16532 struct drm_atomic_state
*state
;
16533 struct intel_atomic_state
*intel_state
;
16534 struct drm_crtc
*crtc
;
16535 struct drm_crtc_state
*cstate
;
16536 struct drm_modeset_acquire_ctx ctx
;
16540 /* Only supported on platforms that use atomic watermark design */
16541 if (!dev_priv
->display
.optimize_watermarks
)
16545 * We need to hold connection_mutex before calling duplicate_state so
16546 * that the connector loop is protected.
16548 drm_modeset_acquire_init(&ctx
, 0);
16550 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
16551 if (ret
== -EDEADLK
) {
16552 drm_modeset_backoff(&ctx
);
16554 } else if (WARN_ON(ret
)) {
16558 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
16559 if (WARN_ON(IS_ERR(state
)))
16562 intel_state
= to_intel_atomic_state(state
);
16565 * Hardware readout is the only time we don't want to calculate
16566 * intermediate watermarks (since we don't trust the current
16569 intel_state
->skip_intermediate_wm
= true;
16571 ret
= intel_atomic_check(dev
, state
);
16574 * If we fail here, it means that the hardware appears to be
16575 * programmed in a way that shouldn't be possible, given our
16576 * understanding of watermark requirements. This might mean a
16577 * mistake in the hardware readout code or a mistake in the
16578 * watermark calculations for a given platform. Raise a WARN
16579 * so that this is noticeable.
16581 * If this actually happens, we'll have to just leave the
16582 * BIOS-programmed watermarks untouched and hope for the best.
16584 WARN(true, "Could not determine valid watermarks for inherited state\n");
16588 /* Write calculated watermark values back */
16589 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
16590 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
16592 cs
->wm
.need_postvbl_update
= true;
16593 dev_priv
->display
.optimize_watermarks(intel_state
, cs
);
16597 drm_atomic_state_put(state
);
16599 drm_modeset_drop_locks(&ctx
);
16600 drm_modeset_acquire_fini(&ctx
);
16603 static void intel_atomic_helper_free_state(struct work_struct
*work
)
16605 struct drm_i915_private
*dev_priv
=
16606 container_of(work
, typeof(*dev_priv
), atomic_helper
.free_work
);
16607 struct intel_atomic_state
*state
, *next
;
16608 struct llist_node
*freed
;
16610 freed
= llist_del_all(&dev_priv
->atomic_helper
.free_list
);
16611 llist_for_each_entry_safe(state
, next
, freed
, freed
)
16612 drm_atomic_state_put(&state
->base
);
16615 int intel_modeset_init(struct drm_device
*dev
)
16617 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16618 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
16620 struct intel_crtc
*crtc
;
16622 drm_mode_config_init(dev
);
16624 dev
->mode_config
.min_width
= 0;
16625 dev
->mode_config
.min_height
= 0;
16627 dev
->mode_config
.preferred_depth
= 24;
16628 dev
->mode_config
.prefer_shadow
= 1;
16630 dev
->mode_config
.allow_fb_modifiers
= true;
16632 dev
->mode_config
.funcs
= &intel_mode_funcs
;
16634 INIT_WORK(&dev_priv
->atomic_helper
.free_work
,
16635 intel_atomic_helper_free_state
);
16637 intel_init_quirks(dev
);
16639 intel_init_pm(dev_priv
);
16641 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
16645 * There may be no VBT; and if the BIOS enabled SSC we can
16646 * just keep using it to avoid unnecessary flicker. Whereas if the
16647 * BIOS isn't using it, don't assume it will work even if the VBT
16648 * indicates as much.
16650 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
16651 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
16654 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
16655 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16656 bios_lvds_use_ssc
? "en" : "dis",
16657 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
16658 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
16662 if (IS_GEN2(dev_priv
)) {
16663 dev
->mode_config
.max_width
= 2048;
16664 dev
->mode_config
.max_height
= 2048;
16665 } else if (IS_GEN3(dev_priv
)) {
16666 dev
->mode_config
.max_width
= 4096;
16667 dev
->mode_config
.max_height
= 4096;
16669 dev
->mode_config
.max_width
= 8192;
16670 dev
->mode_config
.max_height
= 8192;
16673 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
16674 dev
->mode_config
.cursor_width
= IS_I845G(dev_priv
) ? 64 : 512;
16675 dev
->mode_config
.cursor_height
= 1023;
16676 } else if (IS_GEN2(dev_priv
)) {
16677 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
16678 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
16680 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
16681 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
16684 dev
->mode_config
.fb_base
= ggtt
->mappable_base
;
16686 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16687 INTEL_INFO(dev_priv
)->num_pipes
,
16688 INTEL_INFO(dev_priv
)->num_pipes
> 1 ? "s" : "");
16690 for_each_pipe(dev_priv
, pipe
) {
16693 ret
= intel_crtc_init(dev_priv
, pipe
);
16695 drm_mode_config_cleanup(dev
);
16700 intel_update_czclk(dev_priv
);
16701 intel_update_cdclk(dev_priv
);
16702 dev_priv
->atomic_cdclk_freq
= dev_priv
->cdclk_freq
;
16704 intel_shared_dpll_init(dev
);
16706 if (dev_priv
->max_cdclk_freq
== 0)
16707 intel_update_max_cdclk(dev_priv
);
16709 /* Just disable it once at startup */
16710 i915_disable_vga(dev_priv
);
16711 intel_setup_outputs(dev_priv
);
16713 drm_modeset_lock_all(dev
);
16714 intel_modeset_setup_hw_state(dev
);
16715 drm_modeset_unlock_all(dev
);
16717 for_each_intel_crtc(dev
, crtc
) {
16718 struct intel_initial_plane_config plane_config
= {};
16724 * Note that reserving the BIOS fb up front prevents us
16725 * from stuffing other stolen allocations like the ring
16726 * on top. This prevents some ugliness at boot time, and
16727 * can even allow for smooth boot transitions if the BIOS
16728 * fb is large enough for the active pipe configuration.
16730 dev_priv
->display
.get_initial_plane_config(crtc
,
16734 * If the fb is shared between multiple heads, we'll
16735 * just get the first one.
16737 intel_find_initial_plane_obj(crtc
, &plane_config
);
16741 * Make sure hardware watermarks really match the state we read out.
16742 * Note that we need to do this after reconstructing the BIOS fb's
16743 * since the watermark calculation done here will use pstate->fb.
16745 sanitize_watermarks(dev
);
16750 static void intel_enable_pipe_a(struct drm_device
*dev
)
16752 struct intel_connector
*connector
;
16753 struct drm_connector
*crt
= NULL
;
16754 struct intel_load_detect_pipe load_detect_temp
;
16755 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
16757 /* We can't just switch on the pipe A, we need to set things up with a
16758 * proper mode and output configuration. As a gross hack, enable pipe A
16759 * by enabling the load detect pipe once. */
16760 for_each_intel_connector(dev
, connector
) {
16761 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
16762 crt
= &connector
->base
;
16770 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
16771 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
16775 intel_check_plane_mapping(struct intel_crtc
*crtc
)
16777 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
16780 if (INTEL_INFO(dev_priv
)->num_pipes
== 1)
16783 val
= I915_READ(DSPCNTR(!crtc
->plane
));
16785 if ((val
& DISPLAY_PLANE_ENABLE
) &&
16786 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
16792 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
16794 struct drm_device
*dev
= crtc
->base
.dev
;
16795 struct intel_encoder
*encoder
;
16797 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
16803 static struct intel_connector
*intel_encoder_find_connector(struct intel_encoder
*encoder
)
16805 struct drm_device
*dev
= encoder
->base
.dev
;
16806 struct intel_connector
*connector
;
16808 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
16814 static bool has_pch_trancoder(struct drm_i915_private
*dev_priv
,
16815 enum transcoder pch_transcoder
)
16817 return HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
) ||
16818 (HAS_PCH_LPT_H(dev_priv
) && pch_transcoder
== TRANSCODER_A
);
16821 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
16823 struct drm_device
*dev
= crtc
->base
.dev
;
16824 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16825 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
16827 /* Clear any frame start delays used for debugging left by the BIOS */
16828 if (!transcoder_is_dsi(cpu_transcoder
)) {
16829 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
16832 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
16835 /* restore vblank interrupts to correct state */
16836 drm_crtc_vblank_reset(&crtc
->base
);
16837 if (crtc
->active
) {
16838 struct intel_plane
*plane
;
16840 drm_crtc_vblank_on(&crtc
->base
);
16842 /* Disable everything but the primary plane */
16843 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
16844 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
16847 plane
->disable_plane(&plane
->base
, &crtc
->base
);
16851 /* We need to sanitize the plane -> pipe mapping first because this will
16852 * disable the crtc (and hence change the state) if it is wrong. Note
16853 * that gen4+ has a fixed plane -> pipe mapping. */
16854 if (INTEL_GEN(dev_priv
) < 4 && !intel_check_plane_mapping(crtc
)) {
16857 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16858 crtc
->base
.base
.id
, crtc
->base
.name
);
16860 /* Pipe has the wrong plane attached and the plane is active.
16861 * Temporarily change the plane mapping and disable everything
16863 plane
= crtc
->plane
;
16864 crtc
->base
.primary
->state
->visible
= true;
16865 crtc
->plane
= !plane
;
16866 intel_crtc_disable_noatomic(&crtc
->base
);
16867 crtc
->plane
= plane
;
16870 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
16871 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
16872 /* BIOS forgot to enable pipe A, this mostly happens after
16873 * resume. Force-enable the pipe to fix this, the update_dpms
16874 * call below we restore the pipe to the right state, but leave
16875 * the required bits on. */
16876 intel_enable_pipe_a(dev
);
16879 /* Adjust the state of the output pipe according to whether we
16880 * have active connectors/encoders. */
16881 if (crtc
->active
&& !intel_crtc_has_encoders(crtc
))
16882 intel_crtc_disable_noatomic(&crtc
->base
);
16884 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev_priv
)) {
16886 * We start out with underrun reporting disabled to avoid races.
16887 * For correct bookkeeping mark this on active crtcs.
16889 * Also on gmch platforms we dont have any hardware bits to
16890 * disable the underrun reporting. Which means we need to start
16891 * out with underrun reporting disabled also on inactive pipes,
16892 * since otherwise we'll complain about the garbage we read when
16893 * e.g. coming up after runtime pm.
16895 * No protection against concurrent access is required - at
16896 * worst a fifo underrun happens which also sets this to false.
16898 crtc
->cpu_fifo_underrun_disabled
= true;
16900 * We track the PCH trancoder underrun reporting state
16901 * within the crtc. With crtc for pipe A housing the underrun
16902 * reporting state for PCH transcoder A, crtc for pipe B housing
16903 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16904 * and marking underrun reporting as disabled for the non-existing
16905 * PCH transcoders B and C would prevent enabling the south
16906 * error interrupt (see cpt_can_enable_serr_int()).
16908 if (has_pch_trancoder(dev_priv
, (enum transcoder
)crtc
->pipe
))
16909 crtc
->pch_fifo_underrun_disabled
= true;
16913 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
16915 struct intel_connector
*connector
;
16917 /* We need to check both for a crtc link (meaning that the
16918 * encoder is active and trying to read from a pipe) and the
16919 * pipe itself being active. */
16920 bool has_active_crtc
= encoder
->base
.crtc
&&
16921 to_intel_crtc(encoder
->base
.crtc
)->active
;
16923 connector
= intel_encoder_find_connector(encoder
);
16924 if (connector
&& !has_active_crtc
) {
16925 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16926 encoder
->base
.base
.id
,
16927 encoder
->base
.name
);
16929 /* Connector is active, but has no active pipe. This is
16930 * fallout from our resume register restoring. Disable
16931 * the encoder manually again. */
16932 if (encoder
->base
.crtc
) {
16933 struct drm_crtc_state
*crtc_state
= encoder
->base
.crtc
->state
;
16935 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16936 encoder
->base
.base
.id
,
16937 encoder
->base
.name
);
16938 encoder
->disable(encoder
, to_intel_crtc_state(crtc_state
), connector
->base
.state
);
16939 if (encoder
->post_disable
)
16940 encoder
->post_disable(encoder
, to_intel_crtc_state(crtc_state
), connector
->base
.state
);
16942 encoder
->base
.crtc
= NULL
;
16944 /* Inconsistent output/port/pipe state happens presumably due to
16945 * a bug in one of the get_hw_state functions. Or someplace else
16946 * in our code, like the register restore mess on resume. Clamp
16947 * things to off as a safer default. */
16949 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16950 connector
->base
.encoder
= NULL
;
16952 /* Enabled encoders without active connectors will be fixed in
16953 * the crtc fixup. */
16956 void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
)
16958 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
16960 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
16961 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16962 i915_disable_vga(dev_priv
);
16966 void i915_redisable_vga(struct drm_i915_private
*dev_priv
)
16968 /* This function can be called both from intel_modeset_setup_hw_state or
16969 * at a very early point in our resume sequence, where the power well
16970 * structures are not yet restored. Since this function is at a very
16971 * paranoid "someone might have enabled VGA while we were not looking"
16972 * level, just check if the power well is enabled instead of trying to
16973 * follow the "don't touch the power well if we don't need it" policy
16974 * the rest of the driver uses. */
16975 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_VGA
))
16978 i915_redisable_vga_power_on(dev_priv
);
16980 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
16983 static bool primary_get_hw_state(struct intel_plane
*plane
)
16985 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
16987 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
16990 /* FIXME read out full plane state for all planes */
16991 static void readout_plane_state(struct intel_crtc
*crtc
)
16993 struct drm_plane
*primary
= crtc
->base
.primary
;
16994 struct intel_plane_state
*plane_state
=
16995 to_intel_plane_state(primary
->state
);
16997 plane_state
->base
.visible
= crtc
->active
&&
16998 primary_get_hw_state(to_intel_plane(primary
));
17000 if (plane_state
->base
.visible
)
17001 crtc
->base
.state
->plane_mask
|= 1 << drm_plane_index(primary
);
17004 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
17006 struct drm_i915_private
*dev_priv
= to_i915(dev
);
17008 struct intel_crtc
*crtc
;
17009 struct intel_encoder
*encoder
;
17010 struct intel_connector
*connector
;
17013 dev_priv
->active_crtcs
= 0;
17015 for_each_intel_crtc(dev
, crtc
) {
17016 struct intel_crtc_state
*crtc_state
=
17017 to_intel_crtc_state(crtc
->base
.state
);
17019 __drm_atomic_helper_crtc_destroy_state(&crtc_state
->base
);
17020 memset(crtc_state
, 0, sizeof(*crtc_state
));
17021 crtc_state
->base
.crtc
= &crtc
->base
;
17023 crtc_state
->base
.active
= crtc_state
->base
.enable
=
17024 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
17026 crtc
->base
.enabled
= crtc_state
->base
.enable
;
17027 crtc
->active
= crtc_state
->base
.active
;
17029 if (crtc_state
->base
.active
)
17030 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
17032 readout_plane_state(crtc
);
17034 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
17035 crtc
->base
.base
.id
, crtc
->base
.name
,
17036 enableddisabled(crtc_state
->base
.active
));
17039 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
17040 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
17042 pll
->on
= pll
->funcs
.get_hw_state(dev_priv
, pll
,
17043 &pll
->state
.hw_state
);
17044 pll
->state
.crtc_mask
= 0;
17045 for_each_intel_crtc(dev
, crtc
) {
17046 struct intel_crtc_state
*crtc_state
=
17047 to_intel_crtc_state(crtc
->base
.state
);
17049 if (crtc_state
->base
.active
&&
17050 crtc_state
->shared_dpll
== pll
)
17051 pll
->state
.crtc_mask
|= 1 << crtc
->pipe
;
17053 pll
->active_mask
= pll
->state
.crtc_mask
;
17055 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
17056 pll
->name
, pll
->state
.crtc_mask
, pll
->on
);
17059 for_each_intel_encoder(dev
, encoder
) {
17062 if (encoder
->get_hw_state(encoder
, &pipe
)) {
17063 struct intel_crtc_state
*crtc_state
;
17065 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
17066 crtc_state
= to_intel_crtc_state(crtc
->base
.state
);
17068 encoder
->base
.crtc
= &crtc
->base
;
17069 crtc_state
->output_types
|= 1 << encoder
->type
;
17070 encoder
->get_config(encoder
, crtc_state
);
17072 encoder
->base
.crtc
= NULL
;
17075 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
17076 encoder
->base
.base
.id
, encoder
->base
.name
,
17077 enableddisabled(encoder
->base
.crtc
),
17081 for_each_intel_connector(dev
, connector
) {
17082 if (connector
->get_hw_state(connector
)) {
17083 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
17085 encoder
= connector
->encoder
;
17086 connector
->base
.encoder
= &encoder
->base
;
17088 if (encoder
->base
.crtc
&&
17089 encoder
->base
.crtc
->state
->active
) {
17091 * This has to be done during hardware readout
17092 * because anything calling .crtc_disable may
17093 * rely on the connector_mask being accurate.
17095 encoder
->base
.crtc
->state
->connector_mask
|=
17096 1 << drm_connector_index(&connector
->base
);
17097 encoder
->base
.crtc
->state
->encoder_mask
|=
17098 1 << drm_encoder_index(&encoder
->base
);
17102 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
17103 connector
->base
.encoder
= NULL
;
17105 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
17106 connector
->base
.base
.id
, connector
->base
.name
,
17107 enableddisabled(connector
->base
.encoder
));
17110 for_each_intel_crtc(dev
, crtc
) {
17111 struct intel_crtc_state
*crtc_state
=
17112 to_intel_crtc_state(crtc
->base
.state
);
17115 crtc
->base
.hwmode
= crtc_state
->base
.adjusted_mode
;
17117 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
17118 if (crtc_state
->base
.active
) {
17119 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc_state
);
17120 intel_mode_from_pipe_config(&crtc_state
->base
.adjusted_mode
, crtc_state
);
17121 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
17124 * The initial mode needs to be set in order to keep
17125 * the atomic core happy. It wants a valid mode if the
17126 * crtc's enabled, so we do the above call.
17128 * But we don't set all the derived state fully, hence
17129 * set a flag to indicate that a full recalculation is
17130 * needed on the next commit.
17132 crtc_state
->base
.mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
17134 if (INTEL_GEN(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
17135 pixclk
= ilk_pipe_pixel_rate(crtc_state
);
17136 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
17137 pixclk
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
17139 WARN_ON(dev_priv
->display
.modeset_calc_cdclk
);
17141 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
17142 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
17143 pixclk
= DIV_ROUND_UP(pixclk
* 100, 95);
17145 drm_calc_timestamping_constants(&crtc
->base
, &crtc
->base
.hwmode
);
17146 update_scanline_offset(crtc
);
17149 dev_priv
->min_pixclk
[crtc
->pipe
] = pixclk
;
17151 intel_pipe_config_sanity_check(dev_priv
, crtc_state
);
17155 /* Scan out the current hw modeset state,
17156 * and sanitizes it to the current state
17159 intel_modeset_setup_hw_state(struct drm_device
*dev
)
17161 struct drm_i915_private
*dev_priv
= to_i915(dev
);
17163 struct intel_crtc
*crtc
;
17164 struct intel_encoder
*encoder
;
17167 intel_modeset_readout_hw_state(dev
);
17169 /* HW state is read out, now we need to sanitize this mess. */
17170 for_each_intel_encoder(dev
, encoder
) {
17171 intel_sanitize_encoder(encoder
);
17174 for_each_pipe(dev_priv
, pipe
) {
17175 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
17177 intel_sanitize_crtc(crtc
);
17178 intel_dump_pipe_config(crtc
, crtc
->config
,
17179 "[setup_hw_state]");
17182 intel_modeset_update_connector_atomic_state(dev
);
17184 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
17185 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
17187 if (!pll
->on
|| pll
->active_mask
)
17190 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
17192 pll
->funcs
.disable(dev_priv
, pll
);
17196 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
17197 vlv_wm_get_hw_state(dev
);
17198 else if (IS_GEN9(dev_priv
))
17199 skl_wm_get_hw_state(dev
);
17200 else if (HAS_PCH_SPLIT(dev_priv
))
17201 ilk_wm_get_hw_state(dev
);
17203 for_each_intel_crtc(dev
, crtc
) {
17204 unsigned long put_domains
;
17206 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc
->config
);
17207 if (WARN_ON(put_domains
))
17208 modeset_put_power_domains(dev_priv
, put_domains
);
17210 intel_display_set_init_power(dev_priv
, false);
17212 intel_fbc_init_pipe_state(dev_priv
);
17215 void intel_display_resume(struct drm_device
*dev
)
17217 struct drm_i915_private
*dev_priv
= to_i915(dev
);
17218 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
17219 struct drm_modeset_acquire_ctx ctx
;
17222 dev_priv
->modeset_restore_state
= NULL
;
17224 state
->acquire_ctx
= &ctx
;
17227 * This is a cludge because with real atomic modeset mode_config.mutex
17228 * won't be taken. Unfortunately some probed state like
17229 * audio_codec_enable is still protected by mode_config.mutex, so lock
17232 mutex_lock(&dev
->mode_config
.mutex
);
17233 drm_modeset_acquire_init(&ctx
, 0);
17236 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
17237 if (ret
!= -EDEADLK
)
17240 drm_modeset_backoff(&ctx
);
17244 ret
= __intel_display_resume(dev
, state
, &ctx
);
17246 drm_modeset_drop_locks(&ctx
);
17247 drm_modeset_acquire_fini(&ctx
);
17248 mutex_unlock(&dev
->mode_config
.mutex
);
17251 DRM_ERROR("Restoring old state failed with %i\n", ret
);
17253 drm_atomic_state_put(state
);
17256 void intel_modeset_gem_init(struct drm_device
*dev
)
17258 struct drm_i915_private
*dev_priv
= to_i915(dev
);
17260 intel_init_gt_powersave(dev_priv
);
17262 intel_modeset_init_hw(dev
);
17264 intel_setup_overlay(dev_priv
);
17267 int intel_connector_register(struct drm_connector
*connector
)
17269 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
17272 ret
= intel_backlight_device_register(intel_connector
);
17282 void intel_connector_unregister(struct drm_connector
*connector
)
17284 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
17286 intel_backlight_device_unregister(intel_connector
);
17287 intel_panel_destroy_backlight(connector
);
17290 void intel_modeset_cleanup(struct drm_device
*dev
)
17292 struct drm_i915_private
*dev_priv
= to_i915(dev
);
17294 flush_work(&dev_priv
->atomic_helper
.free_work
);
17295 WARN_ON(!llist_empty(&dev_priv
->atomic_helper
.free_list
));
17297 intel_disable_gt_powersave(dev_priv
);
17300 * Interrupts and polling as the first thing to avoid creating havoc.
17301 * Too much stuff here (turning of connectors, ...) would
17302 * experience fancy races otherwise.
17304 intel_irq_uninstall(dev_priv
);
17307 * Due to the hpd irq storm handling the hotplug work can re-arm the
17308 * poll handlers. Hence disable polling after hpd handling is shut down.
17310 drm_kms_helper_poll_fini(dev
);
17312 intel_unregister_dsm_handler();
17314 intel_fbc_global_disable(dev_priv
);
17316 /* flush any delayed tasks or pending work */
17317 flush_scheduled_work();
17319 drm_mode_config_cleanup(dev
);
17321 intel_cleanup_overlay(dev_priv
);
17323 intel_cleanup_gt_powersave(dev_priv
);
17325 intel_teardown_gmbus(dev_priv
);
17328 void intel_connector_attach_encoder(struct intel_connector
*connector
,
17329 struct intel_encoder
*encoder
)
17331 connector
->encoder
= encoder
;
17332 drm_mode_connector_attach_encoder(&connector
->base
,
17337 * set vga decode state - true == enable VGA decode
17339 int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
, bool state
)
17341 unsigned reg
= INTEL_GEN(dev_priv
) >= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
17344 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
17345 DRM_ERROR("failed to read control word\n");
17349 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
17353 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
17355 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
17357 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
17358 DRM_ERROR("failed to write control word\n");
17365 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17367 struct intel_display_error_state
{
17369 u32 power_well_driver
;
17371 int num_transcoders
;
17373 struct intel_cursor_error_state
{
17378 } cursor
[I915_MAX_PIPES
];
17380 struct intel_pipe_error_state
{
17381 bool power_domain_on
;
17384 } pipe
[I915_MAX_PIPES
];
17386 struct intel_plane_error_state
{
17394 } plane
[I915_MAX_PIPES
];
17396 struct intel_transcoder_error_state
{
17397 bool power_domain_on
;
17398 enum transcoder cpu_transcoder
;
17411 struct intel_display_error_state
*
17412 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
17414 struct intel_display_error_state
*error
;
17415 int transcoders
[] = {
17423 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
17426 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
17430 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
17431 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
17433 for_each_pipe(dev_priv
, i
) {
17434 error
->pipe
[i
].power_domain_on
=
17435 __intel_display_power_is_enabled(dev_priv
,
17436 POWER_DOMAIN_PIPE(i
));
17437 if (!error
->pipe
[i
].power_domain_on
)
17440 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
17441 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
17442 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
17444 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
17445 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
17446 if (INTEL_GEN(dev_priv
) <= 3) {
17447 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
17448 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
17450 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
17451 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
17452 if (INTEL_GEN(dev_priv
) >= 4) {
17453 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
17454 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
17457 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
17459 if (HAS_GMCH_DISPLAY(dev_priv
))
17460 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
17463 /* Note: this does not include DSI transcoders. */
17464 error
->num_transcoders
= INTEL_INFO(dev_priv
)->num_pipes
;
17465 if (HAS_DDI(dev_priv
))
17466 error
->num_transcoders
++; /* Account for eDP. */
17468 for (i
= 0; i
< error
->num_transcoders
; i
++) {
17469 enum transcoder cpu_transcoder
= transcoders
[i
];
17471 error
->transcoder
[i
].power_domain_on
=
17472 __intel_display_power_is_enabled(dev_priv
,
17473 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
17474 if (!error
->transcoder
[i
].power_domain_on
)
17477 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
17479 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
17480 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
17481 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
17482 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
17483 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
17484 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
17485 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
17491 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17494 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
17495 struct drm_i915_private
*dev_priv
,
17496 struct intel_display_error_state
*error
)
17503 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev_priv
)->num_pipes
);
17504 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
17505 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
17506 error
->power_well_driver
);
17507 for_each_pipe(dev_priv
, i
) {
17508 err_printf(m
, "Pipe [%d]:\n", i
);
17509 err_printf(m
, " Power: %s\n",
17510 onoff(error
->pipe
[i
].power_domain_on
));
17511 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
17512 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
17514 err_printf(m
, "Plane [%d]:\n", i
);
17515 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
17516 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
17517 if (INTEL_GEN(dev_priv
) <= 3) {
17518 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
17519 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
17521 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
17522 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
17523 if (INTEL_GEN(dev_priv
) >= 4) {
17524 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
17525 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
17528 err_printf(m
, "Cursor [%d]:\n", i
);
17529 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
17530 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
17531 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
17534 for (i
= 0; i
< error
->num_transcoders
; i
++) {
17535 err_printf(m
, "CPU transcoder: %s\n",
17536 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
17537 err_printf(m
, " Power: %s\n",
17538 onoff(error
->transcoder
[i
].power_domain_on
));
17539 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
17540 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
17541 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
17542 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
17543 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
17544 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
17545 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);