2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
51 static bool is_mmio_work(struct intel_flip_work
*work
)
53 return work
->mmio_work
.func
;
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats
[] = {
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats
[] = {
70 DRM_FORMAT_XRGB2101010
,
71 DRM_FORMAT_XBGR2101010
,
74 static const uint32_t skl_primary_formats
[] = {
81 DRM_FORMAT_XRGB2101010
,
82 DRM_FORMAT_XBGR2101010
,
90 static const uint32_t intel_cursor_formats
[] = {
94 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
95 struct intel_crtc_state
*pipe_config
);
96 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
97 struct intel_crtc_state
*pipe_config
);
99 static int intel_framebuffer_init(struct drm_device
*dev
,
100 struct intel_framebuffer
*ifb
,
101 struct drm_mode_fb_cmd2
*mode_cmd
,
102 struct drm_i915_gem_object
*obj
);
103 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
104 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
105 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
107 struct intel_link_m_n
*m_n
,
108 struct intel_link_m_n
*m2_n2
);
109 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
110 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
111 static void haswell_set_pipemisc(struct drm_crtc
*crtc
);
112 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
113 const struct intel_crtc_state
*pipe_config
);
114 static void chv_prepare_pll(struct intel_crtc
*crtc
,
115 const struct intel_crtc_state
*pipe_config
);
116 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
117 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
118 static void skl_init_scalers(struct drm_i915_private
*dev_priv
,
119 struct intel_crtc
*crtc
,
120 struct intel_crtc_state
*crtc_state
);
121 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
122 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
123 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
124 static void intel_modeset_setup_hw_state(struct drm_device
*dev
);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
);
126 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
);
127 static int glk_calc_cdclk(int max_pixclk
);
128 static int bxt_calc_cdclk(int max_pixclk
);
133 } dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
137 int p2_slow
, p2_fast
;
141 /* returns HPLL frequency in kHz */
142 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
144 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
146 /* Obtain SKU information */
147 mutex_lock(&dev_priv
->sb_lock
);
148 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
149 CCK_FUSE_HPLL_FREQ_MASK
;
150 mutex_unlock(&dev_priv
->sb_lock
);
152 return vco_freq
[hpll_freq
] * 1000;
155 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
156 const char *name
, u32 reg
, int ref_freq
)
161 mutex_lock(&dev_priv
->sb_lock
);
162 val
= vlv_cck_read(dev_priv
, reg
);
163 mutex_unlock(&dev_priv
->sb_lock
);
165 divider
= val
& CCK_FREQUENCY_VALUES
;
167 WARN((val
& CCK_FREQUENCY_STATUS
) !=
168 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
169 "%s change in progress\n", name
);
171 return DIV_ROUND_CLOSEST(ref_freq
<< 1, divider
+ 1);
174 static int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
175 const char *name
, u32 reg
)
177 if (dev_priv
->hpll_freq
== 0)
178 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
180 return vlv_get_cck_clock(dev_priv
, name
, reg
,
181 dev_priv
->hpll_freq
);
185 intel_pch_rawclk(struct drm_i915_private
*dev_priv
)
187 return (I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
) * 1000;
191 intel_vlv_hrawclk(struct drm_i915_private
*dev_priv
)
193 /* RAWCLK_FREQ_VLV register updated from power well code */
194 return vlv_get_cck_clock_hpll(dev_priv
, "hrawclk",
195 CCK_DISPLAY_REF_CLOCK_CONTROL
);
199 intel_g4x_hrawclk(struct drm_i915_private
*dev_priv
)
203 /* hrawclock is 1/4 the FSB frequency */
204 clkcfg
= I915_READ(CLKCFG
);
205 switch (clkcfg
& CLKCFG_FSB_MASK
) {
214 case CLKCFG_FSB_1067
:
216 case CLKCFG_FSB_1333
:
218 /* these two are just a guess; one of them might be right */
219 case CLKCFG_FSB_1600
:
220 case CLKCFG_FSB_1600_ALT
:
227 void intel_update_rawclk(struct drm_i915_private
*dev_priv
)
229 if (HAS_PCH_SPLIT(dev_priv
))
230 dev_priv
->rawclk_freq
= intel_pch_rawclk(dev_priv
);
231 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
232 dev_priv
->rawclk_freq
= intel_vlv_hrawclk(dev_priv
);
233 else if (IS_G4X(dev_priv
) || IS_PINEVIEW(dev_priv
))
234 dev_priv
->rawclk_freq
= intel_g4x_hrawclk(dev_priv
);
236 return; /* no rawclk on other platforms, or no need to know it */
238 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv
->rawclk_freq
);
241 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
243 if (!(IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)))
246 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
247 CCK_CZ_CLOCK_CONTROL
);
249 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
252 static inline u32
/* units of 100MHz */
253 intel_fdi_link_freq(struct drm_i915_private
*dev_priv
,
254 const struct intel_crtc_state
*pipe_config
)
256 if (HAS_DDI(dev_priv
))
257 return pipe_config
->port_clock
; /* SPLL */
258 else if (IS_GEN5(dev_priv
))
259 return ((I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2) * 10000;
264 static const struct intel_limit intel_limits_i8xx_dac
= {
265 .dot
= { .min
= 25000, .max
= 350000 },
266 .vco
= { .min
= 908000, .max
= 1512000 },
267 .n
= { .min
= 2, .max
= 16 },
268 .m
= { .min
= 96, .max
= 140 },
269 .m1
= { .min
= 18, .max
= 26 },
270 .m2
= { .min
= 6, .max
= 16 },
271 .p
= { .min
= 4, .max
= 128 },
272 .p1
= { .min
= 2, .max
= 33 },
273 .p2
= { .dot_limit
= 165000,
274 .p2_slow
= 4, .p2_fast
= 2 },
277 static const struct intel_limit intel_limits_i8xx_dvo
= {
278 .dot
= { .min
= 25000, .max
= 350000 },
279 .vco
= { .min
= 908000, .max
= 1512000 },
280 .n
= { .min
= 2, .max
= 16 },
281 .m
= { .min
= 96, .max
= 140 },
282 .m1
= { .min
= 18, .max
= 26 },
283 .m2
= { .min
= 6, .max
= 16 },
284 .p
= { .min
= 4, .max
= 128 },
285 .p1
= { .min
= 2, .max
= 33 },
286 .p2
= { .dot_limit
= 165000,
287 .p2_slow
= 4, .p2_fast
= 4 },
290 static const struct intel_limit intel_limits_i8xx_lvds
= {
291 .dot
= { .min
= 25000, .max
= 350000 },
292 .vco
= { .min
= 908000, .max
= 1512000 },
293 .n
= { .min
= 2, .max
= 16 },
294 .m
= { .min
= 96, .max
= 140 },
295 .m1
= { .min
= 18, .max
= 26 },
296 .m2
= { .min
= 6, .max
= 16 },
297 .p
= { .min
= 4, .max
= 128 },
298 .p1
= { .min
= 1, .max
= 6 },
299 .p2
= { .dot_limit
= 165000,
300 .p2_slow
= 14, .p2_fast
= 7 },
303 static const struct intel_limit intel_limits_i9xx_sdvo
= {
304 .dot
= { .min
= 20000, .max
= 400000 },
305 .vco
= { .min
= 1400000, .max
= 2800000 },
306 .n
= { .min
= 1, .max
= 6 },
307 .m
= { .min
= 70, .max
= 120 },
308 .m1
= { .min
= 8, .max
= 18 },
309 .m2
= { .min
= 3, .max
= 7 },
310 .p
= { .min
= 5, .max
= 80 },
311 .p1
= { .min
= 1, .max
= 8 },
312 .p2
= { .dot_limit
= 200000,
313 .p2_slow
= 10, .p2_fast
= 5 },
316 static const struct intel_limit intel_limits_i9xx_lvds
= {
317 .dot
= { .min
= 20000, .max
= 400000 },
318 .vco
= { .min
= 1400000, .max
= 2800000 },
319 .n
= { .min
= 1, .max
= 6 },
320 .m
= { .min
= 70, .max
= 120 },
321 .m1
= { .min
= 8, .max
= 18 },
322 .m2
= { .min
= 3, .max
= 7 },
323 .p
= { .min
= 7, .max
= 98 },
324 .p1
= { .min
= 1, .max
= 8 },
325 .p2
= { .dot_limit
= 112000,
326 .p2_slow
= 14, .p2_fast
= 7 },
330 static const struct intel_limit intel_limits_g4x_sdvo
= {
331 .dot
= { .min
= 25000, .max
= 270000 },
332 .vco
= { .min
= 1750000, .max
= 3500000},
333 .n
= { .min
= 1, .max
= 4 },
334 .m
= { .min
= 104, .max
= 138 },
335 .m1
= { .min
= 17, .max
= 23 },
336 .m2
= { .min
= 5, .max
= 11 },
337 .p
= { .min
= 10, .max
= 30 },
338 .p1
= { .min
= 1, .max
= 3},
339 .p2
= { .dot_limit
= 270000,
345 static const struct intel_limit intel_limits_g4x_hdmi
= {
346 .dot
= { .min
= 22000, .max
= 400000 },
347 .vco
= { .min
= 1750000, .max
= 3500000},
348 .n
= { .min
= 1, .max
= 4 },
349 .m
= { .min
= 104, .max
= 138 },
350 .m1
= { .min
= 16, .max
= 23 },
351 .m2
= { .min
= 5, .max
= 11 },
352 .p
= { .min
= 5, .max
= 80 },
353 .p1
= { .min
= 1, .max
= 8},
354 .p2
= { .dot_limit
= 165000,
355 .p2_slow
= 10, .p2_fast
= 5 },
358 static const struct intel_limit intel_limits_g4x_single_channel_lvds
= {
359 .dot
= { .min
= 20000, .max
= 115000 },
360 .vco
= { .min
= 1750000, .max
= 3500000 },
361 .n
= { .min
= 1, .max
= 3 },
362 .m
= { .min
= 104, .max
= 138 },
363 .m1
= { .min
= 17, .max
= 23 },
364 .m2
= { .min
= 5, .max
= 11 },
365 .p
= { .min
= 28, .max
= 112 },
366 .p1
= { .min
= 2, .max
= 8 },
367 .p2
= { .dot_limit
= 0,
368 .p2_slow
= 14, .p2_fast
= 14
372 static const struct intel_limit intel_limits_g4x_dual_channel_lvds
= {
373 .dot
= { .min
= 80000, .max
= 224000 },
374 .vco
= { .min
= 1750000, .max
= 3500000 },
375 .n
= { .min
= 1, .max
= 3 },
376 .m
= { .min
= 104, .max
= 138 },
377 .m1
= { .min
= 17, .max
= 23 },
378 .m2
= { .min
= 5, .max
= 11 },
379 .p
= { .min
= 14, .max
= 42 },
380 .p1
= { .min
= 2, .max
= 6 },
381 .p2
= { .dot_limit
= 0,
382 .p2_slow
= 7, .p2_fast
= 7
386 static const struct intel_limit intel_limits_pineview_sdvo
= {
387 .dot
= { .min
= 20000, .max
= 400000},
388 .vco
= { .min
= 1700000, .max
= 3500000 },
389 /* Pineview's Ncounter is a ring counter */
390 .n
= { .min
= 3, .max
= 6 },
391 .m
= { .min
= 2, .max
= 256 },
392 /* Pineview only has one combined m divider, which we treat as m2. */
393 .m1
= { .min
= 0, .max
= 0 },
394 .m2
= { .min
= 0, .max
= 254 },
395 .p
= { .min
= 5, .max
= 80 },
396 .p1
= { .min
= 1, .max
= 8 },
397 .p2
= { .dot_limit
= 200000,
398 .p2_slow
= 10, .p2_fast
= 5 },
401 static const struct intel_limit intel_limits_pineview_lvds
= {
402 .dot
= { .min
= 20000, .max
= 400000 },
403 .vco
= { .min
= 1700000, .max
= 3500000 },
404 .n
= { .min
= 3, .max
= 6 },
405 .m
= { .min
= 2, .max
= 256 },
406 .m1
= { .min
= 0, .max
= 0 },
407 .m2
= { .min
= 0, .max
= 254 },
408 .p
= { .min
= 7, .max
= 112 },
409 .p1
= { .min
= 1, .max
= 8 },
410 .p2
= { .dot_limit
= 112000,
411 .p2_slow
= 14, .p2_fast
= 14 },
414 /* Ironlake / Sandybridge
416 * We calculate clock using (register_value + 2) for N/M1/M2, so here
417 * the range value for them is (actual_value - 2).
419 static const struct intel_limit intel_limits_ironlake_dac
= {
420 .dot
= { .min
= 25000, .max
= 350000 },
421 .vco
= { .min
= 1760000, .max
= 3510000 },
422 .n
= { .min
= 1, .max
= 5 },
423 .m
= { .min
= 79, .max
= 127 },
424 .m1
= { .min
= 12, .max
= 22 },
425 .m2
= { .min
= 5, .max
= 9 },
426 .p
= { .min
= 5, .max
= 80 },
427 .p1
= { .min
= 1, .max
= 8 },
428 .p2
= { .dot_limit
= 225000,
429 .p2_slow
= 10, .p2_fast
= 5 },
432 static const struct intel_limit intel_limits_ironlake_single_lvds
= {
433 .dot
= { .min
= 25000, .max
= 350000 },
434 .vco
= { .min
= 1760000, .max
= 3510000 },
435 .n
= { .min
= 1, .max
= 3 },
436 .m
= { .min
= 79, .max
= 118 },
437 .m1
= { .min
= 12, .max
= 22 },
438 .m2
= { .min
= 5, .max
= 9 },
439 .p
= { .min
= 28, .max
= 112 },
440 .p1
= { .min
= 2, .max
= 8 },
441 .p2
= { .dot_limit
= 225000,
442 .p2_slow
= 14, .p2_fast
= 14 },
445 static const struct intel_limit intel_limits_ironlake_dual_lvds
= {
446 .dot
= { .min
= 25000, .max
= 350000 },
447 .vco
= { .min
= 1760000, .max
= 3510000 },
448 .n
= { .min
= 1, .max
= 3 },
449 .m
= { .min
= 79, .max
= 127 },
450 .m1
= { .min
= 12, .max
= 22 },
451 .m2
= { .min
= 5, .max
= 9 },
452 .p
= { .min
= 14, .max
= 56 },
453 .p1
= { .min
= 2, .max
= 8 },
454 .p2
= { .dot_limit
= 225000,
455 .p2_slow
= 7, .p2_fast
= 7 },
458 /* LVDS 100mhz refclk limits. */
459 static const struct intel_limit intel_limits_ironlake_single_lvds_100m
= {
460 .dot
= { .min
= 25000, .max
= 350000 },
461 .vco
= { .min
= 1760000, .max
= 3510000 },
462 .n
= { .min
= 1, .max
= 2 },
463 .m
= { .min
= 79, .max
= 126 },
464 .m1
= { .min
= 12, .max
= 22 },
465 .m2
= { .min
= 5, .max
= 9 },
466 .p
= { .min
= 28, .max
= 112 },
467 .p1
= { .min
= 2, .max
= 8 },
468 .p2
= { .dot_limit
= 225000,
469 .p2_slow
= 14, .p2_fast
= 14 },
472 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m
= {
473 .dot
= { .min
= 25000, .max
= 350000 },
474 .vco
= { .min
= 1760000, .max
= 3510000 },
475 .n
= { .min
= 1, .max
= 3 },
476 .m
= { .min
= 79, .max
= 126 },
477 .m1
= { .min
= 12, .max
= 22 },
478 .m2
= { .min
= 5, .max
= 9 },
479 .p
= { .min
= 14, .max
= 42 },
480 .p1
= { .min
= 2, .max
= 6 },
481 .p2
= { .dot_limit
= 225000,
482 .p2_slow
= 7, .p2_fast
= 7 },
485 static const struct intel_limit intel_limits_vlv
= {
487 * These are the data rate limits (measured in fast clocks)
488 * since those are the strictest limits we have. The fast
489 * clock and actual rate limits are more relaxed, so checking
490 * them would make no difference.
492 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
493 .vco
= { .min
= 4000000, .max
= 6000000 },
494 .n
= { .min
= 1, .max
= 7 },
495 .m1
= { .min
= 2, .max
= 3 },
496 .m2
= { .min
= 11, .max
= 156 },
497 .p1
= { .min
= 2, .max
= 3 },
498 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
501 static const struct intel_limit intel_limits_chv
= {
503 * These are the data rate limits (measured in fast clocks)
504 * since those are the strictest limits we have. The fast
505 * clock and actual rate limits are more relaxed, so checking
506 * them would make no difference.
508 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
509 .vco
= { .min
= 4800000, .max
= 6480000 },
510 .n
= { .min
= 1, .max
= 1 },
511 .m1
= { .min
= 2, .max
= 2 },
512 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
513 .p1
= { .min
= 2, .max
= 4 },
514 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
517 static const struct intel_limit intel_limits_bxt
= {
518 /* FIXME: find real dot limits */
519 .dot
= { .min
= 0, .max
= INT_MAX
},
520 .vco
= { .min
= 4800000, .max
= 6700000 },
521 .n
= { .min
= 1, .max
= 1 },
522 .m1
= { .min
= 2, .max
= 2 },
523 /* FIXME: find real m2 limits */
524 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
525 .p1
= { .min
= 2, .max
= 4 },
526 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
530 needs_modeset(struct drm_crtc_state
*state
)
532 return drm_atomic_crtc_needs_modeset(state
);
536 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
537 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
538 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
539 * The helpers' return value is the rate of the clock that is fed to the
540 * display engine's pipe which can be the above fast dot clock rate or a
541 * divided-down version of it.
543 /* m1 is reserved as 0 in Pineview, n is a ring counter */
544 static int pnv_calc_dpll_params(int refclk
, struct dpll
*clock
)
546 clock
->m
= clock
->m2
+ 2;
547 clock
->p
= clock
->p1
* clock
->p2
;
548 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
550 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
551 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
556 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
558 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
561 static int i9xx_calc_dpll_params(int refclk
, struct dpll
*clock
)
563 clock
->m
= i9xx_dpll_compute_m(clock
);
564 clock
->p
= clock
->p1
* clock
->p2
;
565 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
567 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
568 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
573 static int vlv_calc_dpll_params(int refclk
, struct dpll
*clock
)
575 clock
->m
= clock
->m1
* clock
->m2
;
576 clock
->p
= clock
->p1
* clock
->p2
;
577 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
579 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
580 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
582 return clock
->dot
/ 5;
585 int chv_calc_dpll_params(int refclk
, struct dpll
*clock
)
587 clock
->m
= clock
->m1
* clock
->m2
;
588 clock
->p
= clock
->p1
* clock
->p2
;
589 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
591 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
593 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
595 return clock
->dot
/ 5;
598 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
600 * Returns whether the given set of divisors are valid for a given refclk with
601 * the given connectors.
604 static bool intel_PLL_is_valid(struct drm_i915_private
*dev_priv
,
605 const struct intel_limit
*limit
,
606 const struct dpll
*clock
)
608 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
609 INTELPllInvalid("n out of range\n");
610 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
611 INTELPllInvalid("p1 out of range\n");
612 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
613 INTELPllInvalid("m2 out of range\n");
614 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
615 INTELPllInvalid("m1 out of range\n");
617 if (!IS_PINEVIEW(dev_priv
) && !IS_VALLEYVIEW(dev_priv
) &&
618 !IS_CHERRYVIEW(dev_priv
) && !IS_GEN9_LP(dev_priv
))
619 if (clock
->m1
<= clock
->m2
)
620 INTELPllInvalid("m1 <= m2\n");
622 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
623 !IS_GEN9_LP(dev_priv
)) {
624 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
625 INTELPllInvalid("p out of range\n");
626 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
627 INTELPllInvalid("m out of range\n");
630 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
631 INTELPllInvalid("vco out of range\n");
632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
635 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
636 INTELPllInvalid("dot out of range\n");
642 i9xx_select_p2_div(const struct intel_limit
*limit
,
643 const struct intel_crtc_state
*crtc_state
,
646 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
648 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
654 if (intel_is_dual_link_lvds(dev
))
655 return limit
->p2
.p2_fast
;
657 return limit
->p2
.p2_slow
;
659 if (target
< limit
->p2
.dot_limit
)
660 return limit
->p2
.p2_slow
;
662 return limit
->p2
.p2_fast
;
667 * Returns a set of divisors for the desired target clock with the given
668 * refclk, or FALSE. The returned values represent the clock equation:
669 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
671 * Target and reference clocks are specified in kHz.
673 * If match_clock is provided, then best_clock P divider must match the P
674 * divider from @match_clock used for LVDS downclocking.
677 i9xx_find_best_dpll(const struct intel_limit
*limit
,
678 struct intel_crtc_state
*crtc_state
,
679 int target
, int refclk
, struct dpll
*match_clock
,
680 struct dpll
*best_clock
)
682 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
686 memset(best_clock
, 0, sizeof(*best_clock
));
688 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
690 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
692 for (clock
.m2
= limit
->m2
.min
;
693 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
694 if (clock
.m2
>= clock
.m1
)
696 for (clock
.n
= limit
->n
.min
;
697 clock
.n
<= limit
->n
.max
; clock
.n
++) {
698 for (clock
.p1
= limit
->p1
.min
;
699 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
702 i9xx_calc_dpll_params(refclk
, &clock
);
703 if (!intel_PLL_is_valid(to_i915(dev
),
708 clock
.p
!= match_clock
->p
)
711 this_err
= abs(clock
.dot
- target
);
712 if (this_err
< err
) {
721 return (err
!= target
);
725 * Returns a set of divisors for the desired target clock with the given
726 * refclk, or FALSE. The returned values represent the clock equation:
727 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
729 * Target and reference clocks are specified in kHz.
731 * If match_clock is provided, then best_clock P divider must match the P
732 * divider from @match_clock used for LVDS downclocking.
735 pnv_find_best_dpll(const struct intel_limit
*limit
,
736 struct intel_crtc_state
*crtc_state
,
737 int target
, int refclk
, struct dpll
*match_clock
,
738 struct dpll
*best_clock
)
740 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
744 memset(best_clock
, 0, sizeof(*best_clock
));
746 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
748 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
750 for (clock
.m2
= limit
->m2
.min
;
751 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
752 for (clock
.n
= limit
->n
.min
;
753 clock
.n
<= limit
->n
.max
; clock
.n
++) {
754 for (clock
.p1
= limit
->p1
.min
;
755 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
758 pnv_calc_dpll_params(refclk
, &clock
);
759 if (!intel_PLL_is_valid(to_i915(dev
),
764 clock
.p
!= match_clock
->p
)
767 this_err
= abs(clock
.dot
- target
);
768 if (this_err
< err
) {
777 return (err
!= target
);
781 * Returns a set of divisors for the desired target clock with the given
782 * refclk, or FALSE. The returned values represent the clock equation:
783 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
785 * Target and reference clocks are specified in kHz.
787 * If match_clock is provided, then best_clock P divider must match the P
788 * divider from @match_clock used for LVDS downclocking.
791 g4x_find_best_dpll(const struct intel_limit
*limit
,
792 struct intel_crtc_state
*crtc_state
,
793 int target
, int refclk
, struct dpll
*match_clock
,
794 struct dpll
*best_clock
)
796 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
800 /* approximately equals target * 0.00585 */
801 int err_most
= (target
>> 8) + (target
>> 9);
803 memset(best_clock
, 0, sizeof(*best_clock
));
805 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
807 max_n
= limit
->n
.max
;
808 /* based on hardware requirement, prefer smaller n to precision */
809 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
810 /* based on hardware requirement, prefere larger m1,m2 */
811 for (clock
.m1
= limit
->m1
.max
;
812 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
813 for (clock
.m2
= limit
->m2
.max
;
814 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
815 for (clock
.p1
= limit
->p1
.max
;
816 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
819 i9xx_calc_dpll_params(refclk
, &clock
);
820 if (!intel_PLL_is_valid(to_i915(dev
),
825 this_err
= abs(clock
.dot
- target
);
826 if (this_err
< err_most
) {
840 * Check if the calculated PLL configuration is more optimal compared to the
841 * best configuration and error found so far. Return the calculated error.
843 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
844 const struct dpll
*calculated_clock
,
845 const struct dpll
*best_clock
,
846 unsigned int best_error_ppm
,
847 unsigned int *error_ppm
)
850 * For CHV ignore the error and consider only the P value.
851 * Prefer a bigger P value based on HW requirements.
853 if (IS_CHERRYVIEW(to_i915(dev
))) {
856 return calculated_clock
->p
> best_clock
->p
;
859 if (WARN_ON_ONCE(!target_freq
))
862 *error_ppm
= div_u64(1000000ULL *
863 abs(target_freq
- calculated_clock
->dot
),
866 * Prefer a better P value over a better (smaller) error if the error
867 * is small. Ensure this preference for future configurations too by
868 * setting the error to 0.
870 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
876 return *error_ppm
+ 10 < best_error_ppm
;
880 * Returns a set of divisors for the desired target clock with the given
881 * refclk, or FALSE. The returned values represent the clock equation:
882 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
885 vlv_find_best_dpll(const struct intel_limit
*limit
,
886 struct intel_crtc_state
*crtc_state
,
887 int target
, int refclk
, struct dpll
*match_clock
,
888 struct dpll
*best_clock
)
890 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
891 struct drm_device
*dev
= crtc
->base
.dev
;
893 unsigned int bestppm
= 1000000;
894 /* min update 19.2 MHz */
895 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
898 target
*= 5; /* fast clock */
900 memset(best_clock
, 0, sizeof(*best_clock
));
902 /* based on hardware requirement, prefer smaller n to precision */
903 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
904 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
905 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
906 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
907 clock
.p
= clock
.p1
* clock
.p2
;
908 /* based on hardware requirement, prefer bigger m1,m2 values */
909 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
912 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
915 vlv_calc_dpll_params(refclk
, &clock
);
917 if (!intel_PLL_is_valid(to_i915(dev
),
922 if (!vlv_PLL_is_optimal(dev
, target
,
940 * Returns a set of divisors for the desired target clock with the given
941 * refclk, or FALSE. The returned values represent the clock equation:
942 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
945 chv_find_best_dpll(const struct intel_limit
*limit
,
946 struct intel_crtc_state
*crtc_state
,
947 int target
, int refclk
, struct dpll
*match_clock
,
948 struct dpll
*best_clock
)
950 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
951 struct drm_device
*dev
= crtc
->base
.dev
;
952 unsigned int best_error_ppm
;
957 memset(best_clock
, 0, sizeof(*best_clock
));
958 best_error_ppm
= 1000000;
961 * Based on hardware doc, the n always set to 1, and m1 always
962 * set to 2. If requires to support 200Mhz refclk, we need to
963 * revisit this because n may not 1 anymore.
965 clock
.n
= 1, clock
.m1
= 2;
966 target
*= 5; /* fast clock */
968 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
969 for (clock
.p2
= limit
->p2
.p2_fast
;
970 clock
.p2
>= limit
->p2
.p2_slow
;
971 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
972 unsigned int error_ppm
;
974 clock
.p
= clock
.p1
* clock
.p2
;
976 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
977 clock
.n
) << 22, refclk
* clock
.m1
);
979 if (m2
> INT_MAX
/clock
.m1
)
984 chv_calc_dpll_params(refclk
, &clock
);
986 if (!intel_PLL_is_valid(to_i915(dev
), limit
, &clock
))
989 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
990 best_error_ppm
, &error_ppm
))
994 best_error_ppm
= error_ppm
;
1002 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1003 struct dpll
*best_clock
)
1005 int refclk
= 100000;
1006 const struct intel_limit
*limit
= &intel_limits_bxt
;
1008 return chv_find_best_dpll(limit
, crtc_state
,
1009 target_clock
, refclk
, NULL
, best_clock
);
1012 bool intel_crtc_active(struct intel_crtc
*crtc
)
1014 /* Be paranoid as we can arrive here with only partial
1015 * state retrieved from the hardware during setup.
1017 * We can ditch the adjusted_mode.crtc_clock check as soon
1018 * as Haswell has gained clock readout/fastboot support.
1020 * We can ditch the crtc->primary->fb check as soon as we can
1021 * properly reconstruct framebuffers.
1023 * FIXME: The intel_crtc->active here should be switched to
1024 * crtc->state->active once we have proper CRTC states wired up
1027 return crtc
->active
&& crtc
->base
.primary
->state
->fb
&&
1028 crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1031 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1034 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1036 return crtc
->config
->cpu_transcoder
;
1039 static bool pipe_dsl_stopped(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1041 i915_reg_t reg
= PIPEDSL(pipe
);
1045 if (IS_GEN2(dev_priv
))
1046 line_mask
= DSL_LINEMASK_GEN2
;
1048 line_mask
= DSL_LINEMASK_GEN3
;
1050 line1
= I915_READ(reg
) & line_mask
;
1052 line2
= I915_READ(reg
) & line_mask
;
1054 return line1
== line2
;
1058 * intel_wait_for_pipe_off - wait for pipe to turn off
1059 * @crtc: crtc whose pipe to wait for
1061 * After disabling a pipe, we can't wait for vblank in the usual way,
1062 * spinning on the vblank interrupt status bit, since we won't actually
1063 * see an interrupt when the pipe is disabled.
1065 * On Gen4 and above:
1066 * wait for the pipe register state bit to turn off
1069 * wait for the display line value to settle (it usually
1070 * ends up stopping at the start of the next frame).
1073 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1075 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1076 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1077 enum pipe pipe
= crtc
->pipe
;
1079 if (INTEL_GEN(dev_priv
) >= 4) {
1080 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
1082 /* Wait for the Pipe State to go off */
1083 if (intel_wait_for_register(dev_priv
,
1084 reg
, I965_PIPECONF_ACTIVE
, 0,
1086 WARN(1, "pipe_off wait timed out\n");
1088 /* Wait for the display line to settle */
1089 if (wait_for(pipe_dsl_stopped(dev_priv
, pipe
), 100))
1090 WARN(1, "pipe_off wait timed out\n");
1094 /* Only for pre-ILK configs */
1095 void assert_pll(struct drm_i915_private
*dev_priv
,
1096 enum pipe pipe
, bool state
)
1101 val
= I915_READ(DPLL(pipe
));
1102 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1103 I915_STATE_WARN(cur_state
!= state
,
1104 "PLL state assertion failure (expected %s, current %s)\n",
1105 onoff(state
), onoff(cur_state
));
1108 /* XXX: the dsi pll is shared between MIPI DSI ports */
1109 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1114 mutex_lock(&dev_priv
->sb_lock
);
1115 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1116 mutex_unlock(&dev_priv
->sb_lock
);
1118 cur_state
= val
& DSI_PLL_VCO_EN
;
1119 I915_STATE_WARN(cur_state
!= state
,
1120 "DSI PLL state assertion failure (expected %s, current %s)\n",
1121 onoff(state
), onoff(cur_state
));
1124 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1125 enum pipe pipe
, bool state
)
1128 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1131 if (HAS_DDI(dev_priv
)) {
1132 /* DDI does not have a specific FDI_TX register */
1133 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1134 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1136 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1137 cur_state
= !!(val
& FDI_TX_ENABLE
);
1139 I915_STATE_WARN(cur_state
!= state
,
1140 "FDI TX state assertion failure (expected %s, current %s)\n",
1141 onoff(state
), onoff(cur_state
));
1143 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1144 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1147 enum pipe pipe
, bool state
)
1152 val
= I915_READ(FDI_RX_CTL(pipe
));
1153 cur_state
= !!(val
& FDI_RX_ENABLE
);
1154 I915_STATE_WARN(cur_state
!= state
,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 onoff(state
), onoff(cur_state
));
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1166 /* ILK FDI PLL is always enabled */
1167 if (IS_GEN5(dev_priv
))
1170 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1171 if (HAS_DDI(dev_priv
))
1174 val
= I915_READ(FDI_TX_CTL(pipe
));
1175 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1179 enum pipe pipe
, bool state
)
1184 val
= I915_READ(FDI_RX_CTL(pipe
));
1185 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1186 I915_STATE_WARN(cur_state
!= state
,
1187 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1188 onoff(state
), onoff(cur_state
));
1191 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1195 enum pipe panel_pipe
= PIPE_A
;
1198 if (WARN_ON(HAS_DDI(dev_priv
)))
1201 if (HAS_PCH_SPLIT(dev_priv
)) {
1204 pp_reg
= PP_CONTROL(0);
1205 port_sel
= I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK
;
1207 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1208 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1209 panel_pipe
= PIPE_B
;
1210 /* XXX: else fix for eDP */
1211 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1212 /* presumably write lock depends on pipe, not port select */
1213 pp_reg
= PP_CONTROL(pipe
);
1216 pp_reg
= PP_CONTROL(0);
1217 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1218 panel_pipe
= PIPE_B
;
1221 val
= I915_READ(pp_reg
);
1222 if (!(val
& PANEL_POWER_ON
) ||
1223 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1226 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1227 "panel assertion failure, pipe %c regs locked\n",
1231 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1232 enum pipe pipe
, bool state
)
1236 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
1237 cur_state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
1239 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1241 I915_STATE_WARN(cur_state
!= state
,
1242 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1243 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1245 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1246 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1248 void assert_pipe(struct drm_i915_private
*dev_priv
,
1249 enum pipe pipe
, bool state
)
1252 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1254 enum intel_display_power_domain power_domain
;
1256 /* if we need the pipe quirk it must be always on */
1257 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1258 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1261 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
1262 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
1263 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1264 cur_state
= !!(val
& PIPECONF_ENABLE
);
1266 intel_display_power_put(dev_priv
, power_domain
);
1271 I915_STATE_WARN(cur_state
!= state
,
1272 "pipe %c assertion failure (expected %s, current %s)\n",
1273 pipe_name(pipe
), onoff(state
), onoff(cur_state
));
1276 static void assert_plane(struct drm_i915_private
*dev_priv
,
1277 enum plane plane
, bool state
)
1282 val
= I915_READ(DSPCNTR(plane
));
1283 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1284 I915_STATE_WARN(cur_state
!= state
,
1285 "plane %c assertion failure (expected %s, current %s)\n",
1286 plane_name(plane
), onoff(state
), onoff(cur_state
));
1289 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1290 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1292 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1297 /* Primary planes are fixed to pipes on gen4+ */
1298 if (INTEL_GEN(dev_priv
) >= 4) {
1299 u32 val
= I915_READ(DSPCNTR(pipe
));
1300 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1301 "plane %c assertion failure, should be disabled but not\n",
1306 /* Need to check both planes against the pipe */
1307 for_each_pipe(dev_priv
, i
) {
1308 u32 val
= I915_READ(DSPCNTR(i
));
1309 enum pipe cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1310 DISPPLANE_SEL_PIPE_SHIFT
;
1311 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1312 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1313 plane_name(i
), pipe_name(pipe
));
1317 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1322 if (INTEL_GEN(dev_priv
) >= 9) {
1323 for_each_sprite(dev_priv
, pipe
, sprite
) {
1324 u32 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1325 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1326 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1327 sprite
, pipe_name(pipe
));
1329 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1330 for_each_sprite(dev_priv
, pipe
, sprite
) {
1331 u32 val
= I915_READ(SPCNTR(pipe
, PLANE_SPRITE0
+ sprite
));
1332 I915_STATE_WARN(val
& SP_ENABLE
,
1333 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1334 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1336 } else if (INTEL_GEN(dev_priv
) >= 7) {
1337 u32 val
= I915_READ(SPRCTL(pipe
));
1338 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1339 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1340 plane_name(pipe
), pipe_name(pipe
));
1341 } else if (INTEL_GEN(dev_priv
) >= 5) {
1342 u32 val
= I915_READ(DVSCNTR(pipe
));
1343 I915_STATE_WARN(val
& DVS_ENABLE
,
1344 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1345 plane_name(pipe
), pipe_name(pipe
));
1349 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1351 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1352 drm_crtc_vblank_put(crtc
);
1355 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1361 val
= I915_READ(PCH_TRANSCONF(pipe
));
1362 enabled
= !!(val
& TRANS_ENABLE
);
1363 I915_STATE_WARN(enabled
,
1364 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1368 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1369 enum pipe pipe
, u32 port_sel
, u32 val
)
1371 if ((val
& DP_PORT_EN
) == 0)
1374 if (HAS_PCH_CPT(dev_priv
)) {
1375 u32 trans_dp_ctl
= I915_READ(TRANS_DP_CTL(pipe
));
1376 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1378 } else if (IS_CHERRYVIEW(dev_priv
)) {
1379 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1382 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1388 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1389 enum pipe pipe
, u32 val
)
1391 if ((val
& SDVO_ENABLE
) == 0)
1394 if (HAS_PCH_CPT(dev_priv
)) {
1395 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1397 } else if (IS_CHERRYVIEW(dev_priv
)) {
1398 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1401 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1407 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1408 enum pipe pipe
, u32 val
)
1410 if ((val
& LVDS_PORT_EN
) == 0)
1413 if (HAS_PCH_CPT(dev_priv
)) {
1414 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1417 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1423 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1424 enum pipe pipe
, u32 val
)
1426 if ((val
& ADPA_DAC_ENABLE
) == 0)
1428 if (HAS_PCH_CPT(dev_priv
)) {
1429 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1432 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1438 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1439 enum pipe pipe
, i915_reg_t reg
,
1442 u32 val
= I915_READ(reg
);
1443 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1444 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1445 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1447 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& DP_PORT_EN
) == 0
1448 && (val
& DP_PIPEB_SELECT
),
1449 "IBX PCH dp port still using transcoder B\n");
1452 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1453 enum pipe pipe
, i915_reg_t reg
)
1455 u32 val
= I915_READ(reg
);
1456 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1457 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1458 i915_mmio_reg_offset(reg
), pipe_name(pipe
));
1460 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
) && (val
& SDVO_ENABLE
) == 0
1461 && (val
& SDVO_PIPE_B_SELECT
),
1462 "IBX PCH hdmi port still using transcoder B\n");
1465 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1470 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1471 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1472 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1474 val
= I915_READ(PCH_ADPA
);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1479 val
= I915_READ(PCH_LVDS
);
1480 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1481 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1484 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1485 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1486 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1489 static void _vlv_enable_pll(struct intel_crtc
*crtc
,
1490 const struct intel_crtc_state
*pipe_config
)
1492 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1493 enum pipe pipe
= crtc
->pipe
;
1495 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1496 POSTING_READ(DPLL(pipe
));
1499 if (intel_wait_for_register(dev_priv
,
1504 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
1507 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1508 const struct intel_crtc_state
*pipe_config
)
1510 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1511 enum pipe pipe
= crtc
->pipe
;
1513 assert_pipe_disabled(dev_priv
, pipe
);
1515 /* PLL is protected by panel, make sure we can write it */
1516 assert_panel_unlocked(dev_priv
, pipe
);
1518 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1519 _vlv_enable_pll(crtc
, pipe_config
);
1521 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1522 POSTING_READ(DPLL_MD(pipe
));
1526 static void _chv_enable_pll(struct intel_crtc
*crtc
,
1527 const struct intel_crtc_state
*pipe_config
)
1529 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1530 enum pipe pipe
= crtc
->pipe
;
1531 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1534 mutex_lock(&dev_priv
->sb_lock
);
1536 /* Enable back the 10bit clock to display controller */
1537 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1538 tmp
|= DPIO_DCLKP_EN
;
1539 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1541 mutex_unlock(&dev_priv
->sb_lock
);
1544 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1551 /* Check PLL is locked */
1552 if (intel_wait_for_register(dev_priv
,
1553 DPLL(pipe
), DPLL_LOCK_VLV
, DPLL_LOCK_VLV
,
1555 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1558 static void chv_enable_pll(struct intel_crtc
*crtc
,
1559 const struct intel_crtc_state
*pipe_config
)
1561 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1562 enum pipe pipe
= crtc
->pipe
;
1564 assert_pipe_disabled(dev_priv
, pipe
);
1566 /* PLL is protected by panel, make sure we can write it */
1567 assert_panel_unlocked(dev_priv
, pipe
);
1569 if (pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
)
1570 _chv_enable_pll(crtc
, pipe_config
);
1572 if (pipe
!= PIPE_A
) {
1574 * WaPixelRepeatModeFixForC0:chv
1576 * DPLLCMD is AWOL. Use chicken bits to propagate
1577 * the value from DPLLBMD to either pipe B or C.
1579 I915_WRITE(CBR4_VLV
, pipe
== PIPE_B
? CBR_DPLLBMD_PIPE_B
: CBR_DPLLBMD_PIPE_C
);
1580 I915_WRITE(DPLL_MD(PIPE_B
), pipe_config
->dpll_hw_state
.dpll_md
);
1581 I915_WRITE(CBR4_VLV
, 0);
1582 dev_priv
->chv_dpll_md
[pipe
] = pipe_config
->dpll_hw_state
.dpll_md
;
1585 * DPLLB VGA mode also seems to cause problems.
1586 * We should always have it disabled.
1588 WARN_ON((I915_READ(DPLL(PIPE_B
)) & DPLL_VGA_MODE_DIS
) == 0);
1590 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1591 POSTING_READ(DPLL_MD(pipe
));
1595 static int intel_num_dvo_pipes(struct drm_i915_private
*dev_priv
)
1597 struct intel_crtc
*crtc
;
1600 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
1601 count
+= crtc
->base
.state
->active
&&
1602 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
);
1608 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1610 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1611 i915_reg_t reg
= DPLL(crtc
->pipe
);
1612 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1614 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1616 /* PLL is protected by panel, make sure we can write it */
1617 if (IS_MOBILE(dev_priv
) && !IS_I830(dev_priv
))
1618 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1620 /* Enable DVO 2x clock on both PLLs if necessary */
1621 if (IS_I830(dev_priv
) && intel_num_dvo_pipes(dev_priv
) > 0) {
1623 * It appears to be important that we don't enable this
1624 * for the current pipe before otherwise configuring the
1625 * PLL. No idea how this should be handled if multiple
1626 * DVO outputs are enabled simultaneosly.
1628 dpll
|= DPLL_DVO_2X_MODE
;
1629 I915_WRITE(DPLL(!crtc
->pipe
),
1630 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1634 * Apparently we need to have VGA mode enabled prior to changing
1635 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1636 * dividers, even though the register value does change.
1640 I915_WRITE(reg
, dpll
);
1642 /* Wait for the clocks to stabilize. */
1646 if (INTEL_GEN(dev_priv
) >= 4) {
1647 I915_WRITE(DPLL_MD(crtc
->pipe
),
1648 crtc
->config
->dpll_hw_state
.dpll_md
);
1650 /* The pixel multiplier can only be updated once the
1651 * DPLL is enabled and the clocks are stable.
1653 * So write it again.
1655 I915_WRITE(reg
, dpll
);
1658 /* We do this three times for luck */
1659 I915_WRITE(reg
, dpll
);
1661 udelay(150); /* wait for warmup */
1662 I915_WRITE(reg
, dpll
);
1664 udelay(150); /* wait for warmup */
1665 I915_WRITE(reg
, dpll
);
1667 udelay(150); /* wait for warmup */
1671 * i9xx_disable_pll - disable a PLL
1672 * @dev_priv: i915 private structure
1673 * @pipe: pipe PLL to disable
1675 * Disable the PLL for @pipe, making sure the pipe is off first.
1677 * Note! This is for pre-ILK only.
1679 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1681 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1682 enum pipe pipe
= crtc
->pipe
;
1684 /* Disable DVO 2x clock on both PLLs if necessary */
1685 if (IS_I830(dev_priv
) &&
1686 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DVO
) &&
1687 !intel_num_dvo_pipes(dev_priv
)) {
1688 I915_WRITE(DPLL(PIPE_B
),
1689 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1690 I915_WRITE(DPLL(PIPE_A
),
1691 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1694 /* Don't disable pipe or pipe PLLs if needed */
1695 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1696 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1699 /* Make sure the pipe isn't still relying on us */
1700 assert_pipe_disabled(dev_priv
, pipe
);
1702 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1703 POSTING_READ(DPLL(pipe
));
1706 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1710 /* Make sure the pipe isn't still relying on us */
1711 assert_pipe_disabled(dev_priv
, pipe
);
1713 val
= DPLL_INTEGRATED_REF_CLK_VLV
|
1714 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1716 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1718 I915_WRITE(DPLL(pipe
), val
);
1719 POSTING_READ(DPLL(pipe
));
1722 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1724 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1727 /* Make sure the pipe isn't still relying on us */
1728 assert_pipe_disabled(dev_priv
, pipe
);
1730 val
= DPLL_SSC_REF_CLK_CHV
|
1731 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1733 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1735 I915_WRITE(DPLL(pipe
), val
);
1736 POSTING_READ(DPLL(pipe
));
1738 mutex_lock(&dev_priv
->sb_lock
);
1740 /* Disable 10bit clock to display controller */
1741 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1742 val
&= ~DPIO_DCLKP_EN
;
1743 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1745 mutex_unlock(&dev_priv
->sb_lock
);
1748 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1749 struct intel_digital_port
*dport
,
1750 unsigned int expected_mask
)
1753 i915_reg_t dpll_reg
;
1755 switch (dport
->port
) {
1757 port_mask
= DPLL_PORTB_READY_MASK
;
1761 port_mask
= DPLL_PORTC_READY_MASK
;
1763 expected_mask
<<= 4;
1766 port_mask
= DPLL_PORTD_READY_MASK
;
1767 dpll_reg
= DPIO_PHY_STATUS
;
1773 if (intel_wait_for_register(dev_priv
,
1774 dpll_reg
, port_mask
, expected_mask
,
1776 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1777 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1780 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1783 struct intel_crtc
*intel_crtc
= intel_get_crtc_for_pipe(dev_priv
,
1786 uint32_t val
, pipeconf_val
;
1788 /* Make sure PCH DPLL is enabled */
1789 assert_shared_dpll_enabled(dev_priv
, intel_crtc
->config
->shared_dpll
);
1791 /* FDI must be feeding us bits for PCH ports */
1792 assert_fdi_tx_enabled(dev_priv
, pipe
);
1793 assert_fdi_rx_enabled(dev_priv
, pipe
);
1795 if (HAS_PCH_CPT(dev_priv
)) {
1796 /* Workaround: Set the timing override bit before enabling the
1797 * pch transcoder. */
1798 reg
= TRANS_CHICKEN2(pipe
);
1799 val
= I915_READ(reg
);
1800 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1801 I915_WRITE(reg
, val
);
1804 reg
= PCH_TRANSCONF(pipe
);
1805 val
= I915_READ(reg
);
1806 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1808 if (HAS_PCH_IBX(dev_priv
)) {
1810 * Make the BPC in transcoder be consistent with
1811 * that in pipeconf reg. For HDMI we must use 8bpc
1812 * here for both 8bpc and 12bpc.
1814 val
&= ~PIPECONF_BPC_MASK
;
1815 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_HDMI
))
1816 val
|= PIPECONF_8BPC
;
1818 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1821 val
&= ~TRANS_INTERLACE_MASK
;
1822 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1823 if (HAS_PCH_IBX(dev_priv
) &&
1824 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
1825 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1827 val
|= TRANS_INTERLACED
;
1829 val
|= TRANS_PROGRESSIVE
;
1831 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1832 if (intel_wait_for_register(dev_priv
,
1833 reg
, TRANS_STATE_ENABLE
, TRANS_STATE_ENABLE
,
1835 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1838 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1839 enum transcoder cpu_transcoder
)
1841 u32 val
, pipeconf_val
;
1843 /* FDI must be feeding us bits for PCH ports */
1844 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1845 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1847 /* Workaround: set timing override bit. */
1848 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1849 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1850 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1853 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1855 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1856 PIPECONF_INTERLACED_ILK
)
1857 val
|= TRANS_INTERLACED
;
1859 val
|= TRANS_PROGRESSIVE
;
1861 I915_WRITE(LPT_TRANSCONF
, val
);
1862 if (intel_wait_for_register(dev_priv
,
1867 DRM_ERROR("Failed to enable PCH transcoder\n");
1870 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1876 /* FDI relies on the transcoder */
1877 assert_fdi_tx_disabled(dev_priv
, pipe
);
1878 assert_fdi_rx_disabled(dev_priv
, pipe
);
1880 /* Ports must be off as well */
1881 assert_pch_ports_disabled(dev_priv
, pipe
);
1883 reg
= PCH_TRANSCONF(pipe
);
1884 val
= I915_READ(reg
);
1885 val
&= ~TRANS_ENABLE
;
1886 I915_WRITE(reg
, val
);
1887 /* wait for PCH transcoder off, transcoder state */
1888 if (intel_wait_for_register(dev_priv
,
1889 reg
, TRANS_STATE_ENABLE
, 0,
1891 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1893 if (HAS_PCH_CPT(dev_priv
)) {
1894 /* Workaround: Clear the timing override chicken bit again. */
1895 reg
= TRANS_CHICKEN2(pipe
);
1896 val
= I915_READ(reg
);
1897 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1898 I915_WRITE(reg
, val
);
1902 void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1906 val
= I915_READ(LPT_TRANSCONF
);
1907 val
&= ~TRANS_ENABLE
;
1908 I915_WRITE(LPT_TRANSCONF
, val
);
1909 /* wait for PCH transcoder off, transcoder state */
1910 if (intel_wait_for_register(dev_priv
,
1911 LPT_TRANSCONF
, TRANS_STATE_ENABLE
, 0,
1913 DRM_ERROR("Failed to disable PCH transcoder\n");
1915 /* Workaround: clear timing override bit. */
1916 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
1917 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1918 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
1921 enum transcoder
intel_crtc_pch_transcoder(struct intel_crtc
*crtc
)
1923 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1925 WARN_ON(!crtc
->config
->has_pch_encoder
);
1927 if (HAS_PCH_LPT(dev_priv
))
1928 return TRANSCODER_A
;
1930 return (enum transcoder
) crtc
->pipe
;
1934 * intel_enable_pipe - enable a pipe, asserting requirements
1935 * @crtc: crtc responsible for the pipe
1937 * Enable @crtc's pipe, making sure that various hardware specific requirements
1938 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1940 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1942 struct drm_device
*dev
= crtc
->base
.dev
;
1943 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1944 enum pipe pipe
= crtc
->pipe
;
1945 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1949 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
1951 assert_planes_disabled(dev_priv
, pipe
);
1952 assert_cursor_disabled(dev_priv
, pipe
);
1953 assert_sprites_disabled(dev_priv
, pipe
);
1956 * A pipe without a PLL won't actually be able to drive bits from
1957 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1960 if (HAS_GMCH_DISPLAY(dev_priv
)) {
1961 if (intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_DSI
))
1962 assert_dsi_pll_enabled(dev_priv
);
1964 assert_pll_enabled(dev_priv
, pipe
);
1966 if (crtc
->config
->has_pch_encoder
) {
1967 /* if driving the PCH, we need FDI enabled */
1968 assert_fdi_rx_pll_enabled(dev_priv
,
1969 (enum pipe
) intel_crtc_pch_transcoder(crtc
));
1970 assert_fdi_tx_pll_enabled(dev_priv
,
1971 (enum pipe
) cpu_transcoder
);
1973 /* FIXME: assert CPU port conditions for SNB+ */
1976 reg
= PIPECONF(cpu_transcoder
);
1977 val
= I915_READ(reg
);
1978 if (val
& PIPECONF_ENABLE
) {
1979 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1980 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
1984 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1988 * Until the pipe starts DSL will read as 0, which would cause
1989 * an apparent vblank timestamp jump, which messes up also the
1990 * frame count when it's derived from the timestamps. So let's
1991 * wait for the pipe to start properly before we call
1992 * drm_crtc_vblank_on()
1994 if (dev
->max_vblank_count
== 0 &&
1995 wait_for(intel_get_crtc_scanline(crtc
) != crtc
->scanline_offset
, 50))
1996 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe
));
2000 * intel_disable_pipe - disable a pipe, asserting requirements
2001 * @crtc: crtc whose pipes is to be disabled
2003 * Disable the pipe of @crtc, making sure that various hardware
2004 * specific requirements are met, if applicable, e.g. plane
2005 * disabled, panel fitter off, etc.
2007 * Will wait until the pipe has shut down before returning.
2009 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2011 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2012 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2013 enum pipe pipe
= crtc
->pipe
;
2017 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
2020 * Make sure planes won't keep trying to pump pixels to us,
2021 * or we might hang the display.
2023 assert_planes_disabled(dev_priv
, pipe
);
2024 assert_cursor_disabled(dev_priv
, pipe
);
2025 assert_sprites_disabled(dev_priv
, pipe
);
2027 reg
= PIPECONF(cpu_transcoder
);
2028 val
= I915_READ(reg
);
2029 if ((val
& PIPECONF_ENABLE
) == 0)
2033 * Double wide has implications for planes
2034 * so best keep it disabled when not needed.
2036 if (crtc
->config
->double_wide
)
2037 val
&= ~PIPECONF_DOUBLE_WIDE
;
2039 /* Don't disable pipe or pipe PLLs if needed */
2040 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2041 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2042 val
&= ~PIPECONF_ENABLE
;
2044 I915_WRITE(reg
, val
);
2045 if ((val
& PIPECONF_ENABLE
) == 0)
2046 intel_wait_for_pipe_off(crtc
);
2049 static unsigned int intel_tile_size(const struct drm_i915_private
*dev_priv
)
2051 return IS_GEN2(dev_priv
) ? 2048 : 4096;
2054 static unsigned int intel_tile_width_bytes(const struct drm_i915_private
*dev_priv
,
2055 uint64_t fb_modifier
, unsigned int cpp
)
2057 switch (fb_modifier
) {
2058 case DRM_FORMAT_MOD_NONE
:
2060 case I915_FORMAT_MOD_X_TILED
:
2061 if (IS_GEN2(dev_priv
))
2065 case I915_FORMAT_MOD_Y_TILED
:
2066 if (IS_GEN2(dev_priv
) || HAS_128_BYTE_Y_TILING(dev_priv
))
2070 case I915_FORMAT_MOD_Yf_TILED
:
2086 MISSING_CASE(fb_modifier
);
2091 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
2092 uint64_t fb_modifier
, unsigned int cpp
)
2094 if (fb_modifier
== DRM_FORMAT_MOD_NONE
)
2097 return intel_tile_size(dev_priv
) /
2098 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2101 /* Return the tile dimensions in pixel units */
2102 static void intel_tile_dims(const struct drm_i915_private
*dev_priv
,
2103 unsigned int *tile_width
,
2104 unsigned int *tile_height
,
2105 uint64_t fb_modifier
,
2108 unsigned int tile_width_bytes
=
2109 intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
2111 *tile_width
= tile_width_bytes
/ cpp
;
2112 *tile_height
= intel_tile_size(dev_priv
) / tile_width_bytes
;
2116 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2117 uint32_t pixel_format
, uint64_t fb_modifier
)
2119 unsigned int cpp
= drm_format_plane_cpp(pixel_format
, 0);
2120 unsigned int tile_height
= intel_tile_height(to_i915(dev
), fb_modifier
, cpp
);
2122 return ALIGN(height
, tile_height
);
2125 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
)
2127 unsigned int size
= 0;
2130 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++)
2131 size
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2137 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
,
2138 const struct drm_framebuffer
*fb
,
2139 unsigned int rotation
)
2141 if (drm_rotation_90_or_270(rotation
)) {
2142 *view
= i915_ggtt_view_rotated
;
2143 view
->params
.rotated
= to_intel_framebuffer(fb
)->rot_info
;
2145 *view
= i915_ggtt_view_normal
;
2149 static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv
)
2151 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2153 else if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
) ||
2154 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2156 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2162 static unsigned int intel_surf_alignment(const struct drm_i915_private
*dev_priv
,
2163 uint64_t fb_modifier
)
2165 switch (fb_modifier
) {
2166 case DRM_FORMAT_MOD_NONE
:
2167 return intel_linear_alignment(dev_priv
);
2168 case I915_FORMAT_MOD_X_TILED
:
2169 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2172 case I915_FORMAT_MOD_Y_TILED
:
2173 case I915_FORMAT_MOD_Yf_TILED
:
2174 return 1 * 1024 * 1024;
2176 MISSING_CASE(fb_modifier
);
2182 intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
)
2184 struct drm_device
*dev
= fb
->dev
;
2185 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2186 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2187 struct i915_ggtt_view view
;
2188 struct i915_vma
*vma
;
2191 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2193 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
);
2195 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2197 /* Note that the w/a also requires 64 PTE of padding following the
2198 * bo. We currently fill all unused PTE with the shadow page and so
2199 * we should always have valid PTE following the scanout preventing
2202 if (intel_scanout_needs_vtd_wa(dev_priv
) && alignment
< 256 * 1024)
2203 alignment
= 256 * 1024;
2206 * Global gtt pte registers are special registers which actually forward
2207 * writes to a chunk of system memory. Which means that there is no risk
2208 * that the register values disappear as soon as we call
2209 * intel_runtime_pm_put(), so it is correct to wrap only the
2210 * pin/unpin/fence and not more.
2212 intel_runtime_pm_get(dev_priv
);
2214 vma
= i915_gem_object_pin_to_display_plane(obj
, alignment
, &view
);
2218 if (i915_vma_is_map_and_fenceable(vma
)) {
2219 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2220 * fence, whereas 965+ only requires a fence if using
2221 * framebuffer compression. For simplicity, we always, when
2222 * possible, install a fence as the cost is not that onerous.
2224 * If we fail to fence the tiled scanout, then either the
2225 * modeset will reject the change (which is highly unlikely as
2226 * the affected systems, all but one, do not have unmappable
2227 * space) or we will not be able to enable full powersaving
2228 * techniques (also likely not to apply due to various limits
2229 * FBC and the like impose on the size of the buffer, which
2230 * presumably we violated anyway with this unmappable buffer).
2231 * Anyway, it is presumably better to stumble onwards with
2232 * something and try to run the system in a "less than optimal"
2233 * mode that matches the user configuration.
2235 if (i915_vma_get_fence(vma
) == 0)
2236 i915_vma_pin_fence(vma
);
2240 intel_runtime_pm_put(dev_priv
);
2244 void intel_unpin_fb_obj(struct drm_framebuffer
*fb
, unsigned int rotation
)
2246 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2247 struct i915_ggtt_view view
;
2248 struct i915_vma
*vma
;
2250 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2252 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
2253 vma
= i915_gem_object_to_ggtt(obj
, &view
);
2255 i915_vma_unpin_fence(vma
);
2256 i915_gem_object_unpin_from_display_plane(vma
);
2259 static int intel_fb_pitch(const struct drm_framebuffer
*fb
, int plane
,
2260 unsigned int rotation
)
2262 if (drm_rotation_90_or_270(rotation
))
2263 return to_intel_framebuffer(fb
)->rotated
[plane
].pitch
;
2265 return fb
->pitches
[plane
];
2269 * Convert the x/y offsets into a linear offset.
2270 * Only valid with 0/180 degree rotation, which is fine since linear
2271 * offset is only used with linear buffers on pre-hsw and tiled buffers
2272 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2274 u32
intel_fb_xy_to_linear(int x
, int y
,
2275 const struct intel_plane_state
*state
,
2278 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2279 unsigned int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
2280 unsigned int pitch
= fb
->pitches
[plane
];
2282 return y
* pitch
+ x
* cpp
;
2286 * Add the x/y offsets derived from fb->offsets[] to the user
2287 * specified plane src x/y offsets. The resulting x/y offsets
2288 * specify the start of scanout from the beginning of the gtt mapping.
2290 void intel_add_fb_offsets(int *x
, int *y
,
2291 const struct intel_plane_state
*state
,
2295 const struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(state
->base
.fb
);
2296 unsigned int rotation
= state
->base
.rotation
;
2298 if (drm_rotation_90_or_270(rotation
)) {
2299 *x
+= intel_fb
->rotated
[plane
].x
;
2300 *y
+= intel_fb
->rotated
[plane
].y
;
2302 *x
+= intel_fb
->normal
[plane
].x
;
2303 *y
+= intel_fb
->normal
[plane
].y
;
2308 * Input tile dimensions and pitch must already be
2309 * rotated to match x and y, and in pixel units.
2311 static u32
_intel_adjust_tile_offset(int *x
, int *y
,
2312 unsigned int tile_width
,
2313 unsigned int tile_height
,
2314 unsigned int tile_size
,
2315 unsigned int pitch_tiles
,
2319 unsigned int pitch_pixels
= pitch_tiles
* tile_width
;
2322 WARN_ON(old_offset
& (tile_size
- 1));
2323 WARN_ON(new_offset
& (tile_size
- 1));
2324 WARN_ON(new_offset
> old_offset
);
2326 tiles
= (old_offset
- new_offset
) / tile_size
;
2328 *y
+= tiles
/ pitch_tiles
* tile_height
;
2329 *x
+= tiles
% pitch_tiles
* tile_width
;
2331 /* minimize x in case it got needlessly big */
2332 *y
+= *x
/ pitch_pixels
* tile_height
;
2339 * Adjust the tile offset by moving the difference into
2342 static u32
intel_adjust_tile_offset(int *x
, int *y
,
2343 const struct intel_plane_state
*state
, int plane
,
2344 u32 old_offset
, u32 new_offset
)
2346 const struct drm_i915_private
*dev_priv
= to_i915(state
->base
.plane
->dev
);
2347 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2348 unsigned int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
2349 unsigned int rotation
= state
->base
.rotation
;
2350 unsigned int pitch
= intel_fb_pitch(fb
, plane
, rotation
);
2352 WARN_ON(new_offset
> old_offset
);
2354 if (fb
->modifier
!= DRM_FORMAT_MOD_NONE
) {
2355 unsigned int tile_size
, tile_width
, tile_height
;
2356 unsigned int pitch_tiles
;
2358 tile_size
= intel_tile_size(dev_priv
);
2359 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2362 if (drm_rotation_90_or_270(rotation
)) {
2363 pitch_tiles
= pitch
/ tile_height
;
2364 swap(tile_width
, tile_height
);
2366 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2369 _intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2370 tile_size
, pitch_tiles
,
2371 old_offset
, new_offset
);
2373 old_offset
+= *y
* pitch
+ *x
* cpp
;
2375 *y
= (old_offset
- new_offset
) / pitch
;
2376 *x
= ((old_offset
- new_offset
) - *y
* pitch
) / cpp
;
2383 * Computes the linear offset to the base tile and adjusts
2384 * x, y. bytes per pixel is assumed to be a power-of-two.
2386 * In the 90/270 rotated case, x and y are assumed
2387 * to be already rotated to match the rotated GTT view, and
2388 * pitch is the tile_height aligned framebuffer height.
2390 * This function is used when computing the derived information
2391 * under intel_framebuffer, so using any of that information
2392 * here is not allowed. Anything under drm_framebuffer can be
2393 * used. This is why the user has to pass in the pitch since it
2394 * is specified in the rotated orientation.
2396 static u32
_intel_compute_tile_offset(const struct drm_i915_private
*dev_priv
,
2398 const struct drm_framebuffer
*fb
, int plane
,
2400 unsigned int rotation
,
2403 uint64_t fb_modifier
= fb
->modifier
;
2404 unsigned int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
2405 u32 offset
, offset_aligned
;
2410 if (fb_modifier
!= DRM_FORMAT_MOD_NONE
) {
2411 unsigned int tile_size
, tile_width
, tile_height
;
2412 unsigned int tile_rows
, tiles
, pitch_tiles
;
2414 tile_size
= intel_tile_size(dev_priv
);
2415 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2418 if (drm_rotation_90_or_270(rotation
)) {
2419 pitch_tiles
= pitch
/ tile_height
;
2420 swap(tile_width
, tile_height
);
2422 pitch_tiles
= pitch
/ (tile_width
* cpp
);
2425 tile_rows
= *y
/ tile_height
;
2428 tiles
= *x
/ tile_width
;
2431 offset
= (tile_rows
* pitch_tiles
+ tiles
) * tile_size
;
2432 offset_aligned
= offset
& ~alignment
;
2434 _intel_adjust_tile_offset(x
, y
, tile_width
, tile_height
,
2435 tile_size
, pitch_tiles
,
2436 offset
, offset_aligned
);
2438 offset
= *y
* pitch
+ *x
* cpp
;
2439 offset_aligned
= offset
& ~alignment
;
2441 *y
= (offset
& alignment
) / pitch
;
2442 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2445 return offset_aligned
;
2448 u32
intel_compute_tile_offset(int *x
, int *y
,
2449 const struct intel_plane_state
*state
,
2452 const struct drm_i915_private
*dev_priv
= to_i915(state
->base
.plane
->dev
);
2453 const struct drm_framebuffer
*fb
= state
->base
.fb
;
2454 unsigned int rotation
= state
->base
.rotation
;
2455 int pitch
= intel_fb_pitch(fb
, plane
, rotation
);
2458 /* AUX_DIST needs only 4K alignment */
2459 if (fb
->pixel_format
== DRM_FORMAT_NV12
&& plane
== 1)
2462 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
);
2464 return _intel_compute_tile_offset(dev_priv
, x
, y
, fb
, plane
, pitch
,
2465 rotation
, alignment
);
2468 /* Convert the fb->offset[] linear offset into x/y offsets */
2469 static void intel_fb_offset_to_xy(int *x
, int *y
,
2470 const struct drm_framebuffer
*fb
, int plane
)
2472 unsigned int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
2473 unsigned int pitch
= fb
->pitches
[plane
];
2474 u32 linear_offset
= fb
->offsets
[plane
];
2476 *y
= linear_offset
/ pitch
;
2477 *x
= linear_offset
% pitch
/ cpp
;
2480 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier
)
2482 switch (fb_modifier
) {
2483 case I915_FORMAT_MOD_X_TILED
:
2484 return I915_TILING_X
;
2485 case I915_FORMAT_MOD_Y_TILED
:
2486 return I915_TILING_Y
;
2488 return I915_TILING_NONE
;
2493 intel_fill_fb_info(struct drm_i915_private
*dev_priv
,
2494 struct drm_framebuffer
*fb
)
2496 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
2497 struct intel_rotation_info
*rot_info
= &intel_fb
->rot_info
;
2498 u32 gtt_offset_rotated
= 0;
2499 unsigned int max_size
= 0;
2500 uint32_t format
= fb
->pixel_format
;
2501 int i
, num_planes
= drm_format_num_planes(format
);
2502 unsigned int tile_size
= intel_tile_size(dev_priv
);
2504 for (i
= 0; i
< num_planes
; i
++) {
2505 unsigned int width
, height
;
2506 unsigned int cpp
, size
;
2510 cpp
= drm_format_plane_cpp(format
, i
);
2511 width
= drm_format_plane_width(fb
->width
, format
, i
);
2512 height
= drm_format_plane_height(fb
->height
, format
, i
);
2514 intel_fb_offset_to_xy(&x
, &y
, fb
, i
);
2517 * The fence (if used) is aligned to the start of the object
2518 * so having the framebuffer wrap around across the edge of the
2519 * fenced region doesn't really work. We have no API to configure
2520 * the fence start offset within the object (nor could we probably
2521 * on gen2/3). So it's just easier if we just require that the
2522 * fb layout agrees with the fence layout. We already check that the
2523 * fb stride matches the fence stride elsewhere.
2525 if (i915_gem_object_is_tiled(intel_fb
->obj
) &&
2526 (x
+ width
) * cpp
> fb
->pitches
[i
]) {
2527 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2533 * First pixel of the framebuffer from
2534 * the start of the normal gtt mapping.
2536 intel_fb
->normal
[i
].x
= x
;
2537 intel_fb
->normal
[i
].y
= y
;
2539 offset
= _intel_compute_tile_offset(dev_priv
, &x
, &y
,
2540 fb
, 0, fb
->pitches
[i
],
2541 DRM_ROTATE_0
, tile_size
);
2542 offset
/= tile_size
;
2544 if (fb
->modifier
!= DRM_FORMAT_MOD_NONE
) {
2545 unsigned int tile_width
, tile_height
;
2546 unsigned int pitch_tiles
;
2549 intel_tile_dims(dev_priv
, &tile_width
, &tile_height
,
2552 rot_info
->plane
[i
].offset
= offset
;
2553 rot_info
->plane
[i
].stride
= DIV_ROUND_UP(fb
->pitches
[i
], tile_width
* cpp
);
2554 rot_info
->plane
[i
].width
= DIV_ROUND_UP(x
+ width
, tile_width
);
2555 rot_info
->plane
[i
].height
= DIV_ROUND_UP(y
+ height
, tile_height
);
2557 intel_fb
->rotated
[i
].pitch
=
2558 rot_info
->plane
[i
].height
* tile_height
;
2560 /* how many tiles does this plane need */
2561 size
= rot_info
->plane
[i
].stride
* rot_info
->plane
[i
].height
;
2563 * If the plane isn't horizontally tile aligned,
2564 * we need one more tile.
2569 /* rotate the x/y offsets to match the GTT view */
2575 rot_info
->plane
[i
].width
* tile_width
,
2576 rot_info
->plane
[i
].height
* tile_height
,
2581 /* rotate the tile dimensions to match the GTT view */
2582 pitch_tiles
= intel_fb
->rotated
[i
].pitch
/ tile_height
;
2583 swap(tile_width
, tile_height
);
2586 * We only keep the x/y offsets, so push all of the
2587 * gtt offset into the x/y offsets.
2589 _intel_adjust_tile_offset(&x
, &y
, tile_size
,
2590 tile_width
, tile_height
, pitch_tiles
,
2591 gtt_offset_rotated
* tile_size
, 0);
2593 gtt_offset_rotated
+= rot_info
->plane
[i
].width
* rot_info
->plane
[i
].height
;
2596 * First pixel of the framebuffer from
2597 * the start of the rotated gtt mapping.
2599 intel_fb
->rotated
[i
].x
= x
;
2600 intel_fb
->rotated
[i
].y
= y
;
2602 size
= DIV_ROUND_UP((y
+ height
) * fb
->pitches
[i
] +
2603 x
* cpp
, tile_size
);
2606 /* how many tiles in total needed in the bo */
2607 max_size
= max(max_size
, offset
+ size
);
2610 if (max_size
* tile_size
> to_intel_framebuffer(fb
)->obj
->base
.size
) {
2611 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2612 max_size
* tile_size
, to_intel_framebuffer(fb
)->obj
->base
.size
);
2619 static int i9xx_format_to_fourcc(int format
)
2622 case DISPPLANE_8BPP
:
2623 return DRM_FORMAT_C8
;
2624 case DISPPLANE_BGRX555
:
2625 return DRM_FORMAT_XRGB1555
;
2626 case DISPPLANE_BGRX565
:
2627 return DRM_FORMAT_RGB565
;
2629 case DISPPLANE_BGRX888
:
2630 return DRM_FORMAT_XRGB8888
;
2631 case DISPPLANE_RGBX888
:
2632 return DRM_FORMAT_XBGR8888
;
2633 case DISPPLANE_BGRX101010
:
2634 return DRM_FORMAT_XRGB2101010
;
2635 case DISPPLANE_RGBX101010
:
2636 return DRM_FORMAT_XBGR2101010
;
2640 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2643 case PLANE_CTL_FORMAT_RGB_565
:
2644 return DRM_FORMAT_RGB565
;
2646 case PLANE_CTL_FORMAT_XRGB_8888
:
2649 return DRM_FORMAT_ABGR8888
;
2651 return DRM_FORMAT_XBGR8888
;
2654 return DRM_FORMAT_ARGB8888
;
2656 return DRM_FORMAT_XRGB8888
;
2658 case PLANE_CTL_FORMAT_XRGB_2101010
:
2660 return DRM_FORMAT_XBGR2101010
;
2662 return DRM_FORMAT_XRGB2101010
;
2667 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2668 struct intel_initial_plane_config
*plane_config
)
2670 struct drm_device
*dev
= crtc
->base
.dev
;
2671 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2672 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2673 struct drm_i915_gem_object
*obj
= NULL
;
2674 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2675 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2676 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2677 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2680 size_aligned
-= base_aligned
;
2682 if (plane_config
->size
== 0)
2685 /* If the FB is too big, just don't use it since fbdev is not very
2686 * important and we should probably use that space with FBC or other
2688 if (size_aligned
* 2 > ggtt
->stolen_usable_size
)
2691 mutex_lock(&dev
->struct_mutex
);
2693 obj
= i915_gem_object_create_stolen_for_preallocated(dev_priv
,
2698 mutex_unlock(&dev
->struct_mutex
);
2702 if (plane_config
->tiling
== I915_TILING_X
)
2703 obj
->tiling_and_stride
= fb
->pitches
[0] | I915_TILING_X
;
2705 mode_cmd
.pixel_format
= fb
->pixel_format
;
2706 mode_cmd
.width
= fb
->width
;
2707 mode_cmd
.height
= fb
->height
;
2708 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2709 mode_cmd
.modifier
[0] = fb
->modifier
;
2710 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2712 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2714 DRM_DEBUG_KMS("intel fb init failed\n");
2718 mutex_unlock(&dev
->struct_mutex
);
2720 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2724 i915_gem_object_put(obj
);
2725 mutex_unlock(&dev
->struct_mutex
);
2729 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2731 update_state_fb(struct drm_plane
*plane
)
2733 if (plane
->fb
== plane
->state
->fb
)
2736 if (plane
->state
->fb
)
2737 drm_framebuffer_unreference(plane
->state
->fb
);
2738 plane
->state
->fb
= plane
->fb
;
2739 if (plane
->state
->fb
)
2740 drm_framebuffer_reference(plane
->state
->fb
);
2744 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2745 struct intel_initial_plane_config
*plane_config
)
2747 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2748 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2750 struct intel_crtc
*i
;
2751 struct drm_i915_gem_object
*obj
;
2752 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2753 struct drm_plane_state
*plane_state
= primary
->state
;
2754 struct drm_crtc_state
*crtc_state
= intel_crtc
->base
.state
;
2755 struct intel_plane
*intel_plane
= to_intel_plane(primary
);
2756 struct intel_plane_state
*intel_state
=
2757 to_intel_plane_state(plane_state
);
2758 struct drm_framebuffer
*fb
;
2760 if (!plane_config
->fb
)
2763 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2764 fb
= &plane_config
->fb
->base
;
2768 kfree(plane_config
->fb
);
2771 * Failed to alloc the obj, check to see if we should share
2772 * an fb with another CRTC instead
2774 for_each_crtc(dev
, c
) {
2775 i
= to_intel_crtc(c
);
2777 if (c
== &intel_crtc
->base
)
2783 fb
= c
->primary
->fb
;
2787 obj
= intel_fb_obj(fb
);
2788 if (i915_gem_object_ggtt_offset(obj
, NULL
) == plane_config
->base
) {
2789 drm_framebuffer_reference(fb
);
2795 * We've failed to reconstruct the BIOS FB. Current display state
2796 * indicates that the primary plane is visible, but has a NULL FB,
2797 * which will lead to problems later if we don't fix it up. The
2798 * simplest solution is to just disable the primary plane now and
2799 * pretend the BIOS never had it enabled.
2801 to_intel_plane_state(plane_state
)->base
.visible
= false;
2802 crtc_state
->plane_mask
&= ~(1 << drm_plane_index(primary
));
2803 intel_pre_disable_primary_noatomic(&intel_crtc
->base
);
2804 intel_plane
->disable_plane(primary
, &intel_crtc
->base
);
2809 plane_state
->src_x
= 0;
2810 plane_state
->src_y
= 0;
2811 plane_state
->src_w
= fb
->width
<< 16;
2812 plane_state
->src_h
= fb
->height
<< 16;
2814 plane_state
->crtc_x
= 0;
2815 plane_state
->crtc_y
= 0;
2816 plane_state
->crtc_w
= fb
->width
;
2817 plane_state
->crtc_h
= fb
->height
;
2819 intel_state
->base
.src
= drm_plane_state_src(plane_state
);
2820 intel_state
->base
.dst
= drm_plane_state_dest(plane_state
);
2822 obj
= intel_fb_obj(fb
);
2823 if (i915_gem_object_is_tiled(obj
))
2824 dev_priv
->preserve_bios_swizzle
= true;
2826 drm_framebuffer_reference(fb
);
2827 primary
->fb
= primary
->state
->fb
= fb
;
2828 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2829 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2830 atomic_or(to_intel_plane(primary
)->frontbuffer_bit
,
2831 &obj
->frontbuffer_bits
);
2834 static int skl_max_plane_width(const struct drm_framebuffer
*fb
, int plane
,
2835 unsigned int rotation
)
2837 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
2839 switch (fb
->modifier
) {
2840 case DRM_FORMAT_MOD_NONE
:
2841 case I915_FORMAT_MOD_X_TILED
:
2854 case I915_FORMAT_MOD_Y_TILED
:
2855 case I915_FORMAT_MOD_Yf_TILED
:
2870 MISSING_CASE(fb
->modifier
);
2876 static int skl_check_main_surface(struct intel_plane_state
*plane_state
)
2878 const struct drm_i915_private
*dev_priv
= to_i915(plane_state
->base
.plane
->dev
);
2879 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2880 unsigned int rotation
= plane_state
->base
.rotation
;
2881 int x
= plane_state
->base
.src
.x1
>> 16;
2882 int y
= plane_state
->base
.src
.y1
>> 16;
2883 int w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
2884 int h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
2885 int max_width
= skl_max_plane_width(fb
, 0, rotation
);
2886 int max_height
= 4096;
2887 u32 alignment
, offset
, aux_offset
= plane_state
->aux
.offset
;
2889 if (w
> max_width
|| h
> max_height
) {
2890 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2891 w
, h
, max_width
, max_height
);
2895 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
2896 offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
2898 alignment
= intel_surf_alignment(dev_priv
, fb
->modifier
);
2901 * AUX surface offset is specified as the distance from the
2902 * main surface offset, and it must be non-negative. Make
2903 * sure that is what we will get.
2905 if (offset
> aux_offset
)
2906 offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 0,
2907 offset
, aux_offset
& ~(alignment
- 1));
2910 * When using an X-tiled surface, the plane blows up
2911 * if the x offset + width exceed the stride.
2913 * TODO: linear and Y-tiled seem fine, Yf untested,
2915 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
) {
2916 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2918 while ((x
+ w
) * cpp
> fb
->pitches
[0]) {
2920 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2924 offset
= intel_adjust_tile_offset(&x
, &y
, plane_state
, 0,
2925 offset
, offset
- alignment
);
2929 plane_state
->main
.offset
= offset
;
2930 plane_state
->main
.x
= x
;
2931 plane_state
->main
.y
= y
;
2936 static int skl_check_nv12_aux_surface(struct intel_plane_state
*plane_state
)
2938 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2939 unsigned int rotation
= plane_state
->base
.rotation
;
2940 int max_width
= skl_max_plane_width(fb
, 1, rotation
);
2941 int max_height
= 4096;
2942 int x
= plane_state
->base
.src
.x1
>> 17;
2943 int y
= plane_state
->base
.src
.y1
>> 17;
2944 int w
= drm_rect_width(&plane_state
->base
.src
) >> 17;
2945 int h
= drm_rect_height(&plane_state
->base
.src
) >> 17;
2948 intel_add_fb_offsets(&x
, &y
, plane_state
, 1);
2949 offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 1);
2951 /* FIXME not quite sure how/if these apply to the chroma plane */
2952 if (w
> max_width
|| h
> max_height
) {
2953 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2954 w
, h
, max_width
, max_height
);
2958 plane_state
->aux
.offset
= offset
;
2959 plane_state
->aux
.x
= x
;
2960 plane_state
->aux
.y
= y
;
2965 int skl_check_plane_surface(struct intel_plane_state
*plane_state
)
2967 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
2968 unsigned int rotation
= plane_state
->base
.rotation
;
2971 /* Rotate src coordinates to match rotated GTT view */
2972 if (drm_rotation_90_or_270(rotation
))
2973 drm_rect_rotate(&plane_state
->base
.src
,
2974 fb
->width
<< 16, fb
->height
<< 16,
2978 * Handle the AUX surface first since
2979 * the main surface setup depends on it.
2981 if (fb
->pixel_format
== DRM_FORMAT_NV12
) {
2982 ret
= skl_check_nv12_aux_surface(plane_state
);
2986 plane_state
->aux
.offset
= ~0xfff;
2987 plane_state
->aux
.x
= 0;
2988 plane_state
->aux
.y
= 0;
2991 ret
= skl_check_main_surface(plane_state
);
2998 static void i9xx_update_primary_plane(struct drm_plane
*primary
,
2999 const struct intel_crtc_state
*crtc_state
,
3000 const struct intel_plane_state
*plane_state
)
3002 struct drm_i915_private
*dev_priv
= to_i915(primary
->dev
);
3003 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3004 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3005 int plane
= intel_crtc
->plane
;
3008 i915_reg_t reg
= DSPCNTR(plane
);
3009 unsigned int rotation
= plane_state
->base
.rotation
;
3010 int x
= plane_state
->base
.src
.x1
>> 16;
3011 int y
= plane_state
->base
.src
.y1
>> 16;
3013 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3015 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3017 if (INTEL_GEN(dev_priv
) < 4) {
3018 if (intel_crtc
->pipe
== PIPE_B
)
3019 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3021 /* pipesrc and dspsize control the size that is scaled from,
3022 * which should always be the user's requested size.
3024 I915_WRITE(DSPSIZE(plane
),
3025 ((crtc_state
->pipe_src_h
- 1) << 16) |
3026 (crtc_state
->pipe_src_w
- 1));
3027 I915_WRITE(DSPPOS(plane
), 0);
3028 } else if (IS_CHERRYVIEW(dev_priv
) && plane
== PLANE_B
) {
3029 I915_WRITE(PRIMSIZE(plane
),
3030 ((crtc_state
->pipe_src_h
- 1) << 16) |
3031 (crtc_state
->pipe_src_w
- 1));
3032 I915_WRITE(PRIMPOS(plane
), 0);
3033 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
3036 switch (fb
->pixel_format
) {
3038 dspcntr
|= DISPPLANE_8BPP
;
3040 case DRM_FORMAT_XRGB1555
:
3041 dspcntr
|= DISPPLANE_BGRX555
;
3043 case DRM_FORMAT_RGB565
:
3044 dspcntr
|= DISPPLANE_BGRX565
;
3046 case DRM_FORMAT_XRGB8888
:
3047 dspcntr
|= DISPPLANE_BGRX888
;
3049 case DRM_FORMAT_XBGR8888
:
3050 dspcntr
|= DISPPLANE_RGBX888
;
3052 case DRM_FORMAT_XRGB2101010
:
3053 dspcntr
|= DISPPLANE_BGRX101010
;
3055 case DRM_FORMAT_XBGR2101010
:
3056 dspcntr
|= DISPPLANE_RGBX101010
;
3062 if (INTEL_GEN(dev_priv
) >= 4 &&
3063 fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3064 dspcntr
|= DISPPLANE_TILED
;
3066 if (rotation
& DRM_ROTATE_180
)
3067 dspcntr
|= DISPPLANE_ROTATE_180
;
3069 if (rotation
& DRM_REFLECT_X
)
3070 dspcntr
|= DISPPLANE_MIRROR
;
3072 if (IS_G4X(dev_priv
))
3073 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
3075 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
3077 if (INTEL_GEN(dev_priv
) >= 4)
3078 intel_crtc
->dspaddr_offset
=
3079 intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
3081 if (rotation
& DRM_ROTATE_180
) {
3082 x
+= crtc_state
->pipe_src_w
- 1;
3083 y
+= crtc_state
->pipe_src_h
- 1;
3084 } else if (rotation
& DRM_REFLECT_X
) {
3085 x
+= crtc_state
->pipe_src_w
- 1;
3088 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
3090 if (INTEL_GEN(dev_priv
) < 4)
3091 intel_crtc
->dspaddr_offset
= linear_offset
;
3093 intel_crtc
->adjusted_x
= x
;
3094 intel_crtc
->adjusted_y
= y
;
3096 I915_WRITE(reg
, dspcntr
);
3098 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
3099 if (INTEL_GEN(dev_priv
) >= 4) {
3100 I915_WRITE(DSPSURF(plane
),
3101 intel_fb_gtt_offset(fb
, rotation
) +
3102 intel_crtc
->dspaddr_offset
);
3103 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
3104 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
3106 I915_WRITE(DSPADDR(plane
),
3107 intel_fb_gtt_offset(fb
, rotation
) +
3108 intel_crtc
->dspaddr_offset
);
3113 static void i9xx_disable_primary_plane(struct drm_plane
*primary
,
3114 struct drm_crtc
*crtc
)
3116 struct drm_device
*dev
= crtc
->dev
;
3117 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3118 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3119 int plane
= intel_crtc
->plane
;
3121 I915_WRITE(DSPCNTR(plane
), 0);
3122 if (INTEL_INFO(dev_priv
)->gen
>= 4)
3123 I915_WRITE(DSPSURF(plane
), 0);
3125 I915_WRITE(DSPADDR(plane
), 0);
3126 POSTING_READ(DSPCNTR(plane
));
3129 static void ironlake_update_primary_plane(struct drm_plane
*primary
,
3130 const struct intel_crtc_state
*crtc_state
,
3131 const struct intel_plane_state
*plane_state
)
3133 struct drm_device
*dev
= primary
->dev
;
3134 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3135 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3136 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3137 int plane
= intel_crtc
->plane
;
3140 i915_reg_t reg
= DSPCNTR(plane
);
3141 unsigned int rotation
= plane_state
->base
.rotation
;
3142 int x
= plane_state
->base
.src
.x1
>> 16;
3143 int y
= plane_state
->base
.src
.y1
>> 16;
3145 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3146 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3148 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
3149 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
3151 switch (fb
->pixel_format
) {
3153 dspcntr
|= DISPPLANE_8BPP
;
3155 case DRM_FORMAT_RGB565
:
3156 dspcntr
|= DISPPLANE_BGRX565
;
3158 case DRM_FORMAT_XRGB8888
:
3159 dspcntr
|= DISPPLANE_BGRX888
;
3161 case DRM_FORMAT_XBGR8888
:
3162 dspcntr
|= DISPPLANE_RGBX888
;
3164 case DRM_FORMAT_XRGB2101010
:
3165 dspcntr
|= DISPPLANE_BGRX101010
;
3167 case DRM_FORMAT_XBGR2101010
:
3168 dspcntr
|= DISPPLANE_RGBX101010
;
3174 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3175 dspcntr
|= DISPPLANE_TILED
;
3177 if (rotation
& DRM_ROTATE_180
)
3178 dspcntr
|= DISPPLANE_ROTATE_180
;
3180 if (!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
))
3181 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
3183 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
3185 intel_crtc
->dspaddr_offset
=
3186 intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
3188 /* HSW+ does this automagically in hardware */
3189 if (!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
) &&
3190 rotation
& DRM_ROTATE_180
) {
3191 x
+= crtc_state
->pipe_src_w
- 1;
3192 y
+= crtc_state
->pipe_src_h
- 1;
3195 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
3197 intel_crtc
->adjusted_x
= x
;
3198 intel_crtc
->adjusted_y
= y
;
3200 I915_WRITE(reg
, dspcntr
);
3202 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
3203 I915_WRITE(DSPSURF(plane
),
3204 intel_fb_gtt_offset(fb
, rotation
) +
3205 intel_crtc
->dspaddr_offset
);
3206 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3207 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
3209 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
3210 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
3215 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
3216 uint64_t fb_modifier
, uint32_t pixel_format
)
3218 if (fb_modifier
== DRM_FORMAT_MOD_NONE
) {
3221 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
3223 return intel_tile_width_bytes(dev_priv
, fb_modifier
, cpp
);
3227 u32
intel_fb_gtt_offset(struct drm_framebuffer
*fb
,
3228 unsigned int rotation
)
3230 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
3231 struct i915_ggtt_view view
;
3232 struct i915_vma
*vma
;
3234 intel_fill_fb_ggtt_view(&view
, fb
, rotation
);
3236 vma
= i915_gem_object_to_ggtt(obj
, &view
);
3237 if (WARN(!vma
, "ggtt vma for display object not found! (view=%u)\n",
3241 return i915_ggtt_offset(vma
);
3244 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
3246 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3247 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3249 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
3250 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
3251 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
3255 * This function detaches (aka. unbinds) unused scalers in hardware
3257 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
3259 struct intel_crtc_scaler_state
*scaler_state
;
3262 scaler_state
= &intel_crtc
->config
->scaler_state
;
3264 /* loop through and disable scalers that aren't in use */
3265 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
3266 if (!scaler_state
->scalers
[i
].in_use
)
3267 skl_detach_scaler(intel_crtc
, i
);
3271 u32
skl_plane_stride(const struct drm_framebuffer
*fb
, int plane
,
3272 unsigned int rotation
)
3274 const struct drm_i915_private
*dev_priv
= to_i915(fb
->dev
);
3275 u32 stride
= intel_fb_pitch(fb
, plane
, rotation
);
3278 * The stride is either expressed as a multiple of 64 bytes chunks for
3279 * linear buffers or in number of tiles for tiled buffers.
3281 if (drm_rotation_90_or_270(rotation
)) {
3282 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, plane
);
3284 stride
/= intel_tile_height(dev_priv
, fb
->modifier
, cpp
);
3286 stride
/= intel_fb_stride_alignment(dev_priv
, fb
->modifier
,
3293 u32
skl_plane_ctl_format(uint32_t pixel_format
)
3295 switch (pixel_format
) {
3297 return PLANE_CTL_FORMAT_INDEXED
;
3298 case DRM_FORMAT_RGB565
:
3299 return PLANE_CTL_FORMAT_RGB_565
;
3300 case DRM_FORMAT_XBGR8888
:
3301 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
3302 case DRM_FORMAT_XRGB8888
:
3303 return PLANE_CTL_FORMAT_XRGB_8888
;
3305 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3306 * to be already pre-multiplied. We need to add a knob (or a different
3307 * DRM_FORMAT) for user-space to configure that.
3309 case DRM_FORMAT_ABGR8888
:
3310 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
3311 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3312 case DRM_FORMAT_ARGB8888
:
3313 return PLANE_CTL_FORMAT_XRGB_8888
|
3314 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3315 case DRM_FORMAT_XRGB2101010
:
3316 return PLANE_CTL_FORMAT_XRGB_2101010
;
3317 case DRM_FORMAT_XBGR2101010
:
3318 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
3319 case DRM_FORMAT_YUYV
:
3320 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
3321 case DRM_FORMAT_YVYU
:
3322 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
3323 case DRM_FORMAT_UYVY
:
3324 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
3325 case DRM_FORMAT_VYUY
:
3326 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3328 MISSING_CASE(pixel_format
);
3334 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
3336 switch (fb_modifier
) {
3337 case DRM_FORMAT_MOD_NONE
:
3339 case I915_FORMAT_MOD_X_TILED
:
3340 return PLANE_CTL_TILED_X
;
3341 case I915_FORMAT_MOD_Y_TILED
:
3342 return PLANE_CTL_TILED_Y
;
3343 case I915_FORMAT_MOD_Yf_TILED
:
3344 return PLANE_CTL_TILED_YF
;
3346 MISSING_CASE(fb_modifier
);
3352 u32
skl_plane_ctl_rotation(unsigned int rotation
)
3358 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3359 * while i915 HW rotation is clockwise, thats why this swapping.
3362 return PLANE_CTL_ROTATE_270
;
3363 case DRM_ROTATE_180
:
3364 return PLANE_CTL_ROTATE_180
;
3365 case DRM_ROTATE_270
:
3366 return PLANE_CTL_ROTATE_90
;
3368 MISSING_CASE(rotation
);
3374 static void skylake_update_primary_plane(struct drm_plane
*plane
,
3375 const struct intel_crtc_state
*crtc_state
,
3376 const struct intel_plane_state
*plane_state
)
3378 struct drm_device
*dev
= plane
->dev
;
3379 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3380 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
3381 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
3382 enum plane_id plane_id
= to_intel_plane(plane
)->id
;
3383 enum pipe pipe
= to_intel_plane(plane
)->pipe
;
3385 unsigned int rotation
= plane_state
->base
.rotation
;
3386 u32 stride
= skl_plane_stride(fb
, 0, rotation
);
3387 u32 surf_addr
= plane_state
->main
.offset
;
3388 int scaler_id
= plane_state
->scaler_id
;
3389 int src_x
= plane_state
->main
.x
;
3390 int src_y
= plane_state
->main
.y
;
3391 int src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
3392 int src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
3393 int dst_x
= plane_state
->base
.dst
.x1
;
3394 int dst_y
= plane_state
->base
.dst
.y1
;
3395 int dst_w
= drm_rect_width(&plane_state
->base
.dst
);
3396 int dst_h
= drm_rect_height(&plane_state
->base
.dst
);
3398 plane_ctl
= PLANE_CTL_ENABLE
|
3399 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3400 PLANE_CTL_PIPE_CSC_ENABLE
;
3402 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3403 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
);
3404 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3405 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3407 /* Sizes are 0 based */
3413 intel_crtc
->dspaddr_offset
= surf_addr
;
3415 intel_crtc
->adjusted_x
= src_x
;
3416 intel_crtc
->adjusted_y
= src_y
;
3418 I915_WRITE(PLANE_CTL(pipe
, plane_id
), plane_ctl
);
3419 I915_WRITE(PLANE_OFFSET(pipe
, plane_id
), (src_y
<< 16) | src_x
);
3420 I915_WRITE(PLANE_STRIDE(pipe
, plane_id
), stride
);
3421 I915_WRITE(PLANE_SIZE(pipe
, plane_id
), (src_h
<< 16) | src_w
);
3423 if (scaler_id
>= 0) {
3424 uint32_t ps_ctrl
= 0;
3426 WARN_ON(!dst_w
|| !dst_h
);
3427 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(plane_id
) |
3428 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3429 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3430 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3431 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3432 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3433 I915_WRITE(PLANE_POS(pipe
, plane_id
), 0);
3435 I915_WRITE(PLANE_POS(pipe
, plane_id
), (dst_y
<< 16) | dst_x
);
3438 I915_WRITE(PLANE_SURF(pipe
, plane_id
),
3439 intel_fb_gtt_offset(fb
, rotation
) + surf_addr
);
3441 POSTING_READ(PLANE_SURF(pipe
, plane_id
));
3444 static void skylake_disable_primary_plane(struct drm_plane
*primary
,
3445 struct drm_crtc
*crtc
)
3447 struct drm_device
*dev
= crtc
->dev
;
3448 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3449 enum plane_id plane_id
= to_intel_plane(primary
)->id
;
3450 enum pipe pipe
= to_intel_plane(primary
)->pipe
;
3452 I915_WRITE(PLANE_CTL(pipe
, plane_id
), 0);
3453 I915_WRITE(PLANE_SURF(pipe
, plane_id
), 0);
3454 POSTING_READ(PLANE_SURF(pipe
, plane_id
));
3457 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3459 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3460 int x
, int y
, enum mode_set_atomic state
)
3462 /* Support for kgdboc is disabled, this needs a major rework. */
3463 DRM_ERROR("legacy panic handler not supported any more.\n");
3468 static void intel_complete_page_flips(struct drm_i915_private
*dev_priv
)
3470 struct intel_crtc
*crtc
;
3472 for_each_intel_crtc(&dev_priv
->drm
, crtc
)
3473 intel_finish_page_flip_cs(dev_priv
, crtc
->pipe
);
3476 static void intel_update_primary_planes(struct drm_device
*dev
)
3478 struct drm_crtc
*crtc
;
3480 for_each_crtc(dev
, crtc
) {
3481 struct intel_plane
*plane
= to_intel_plane(crtc
->primary
);
3482 struct intel_plane_state
*plane_state
=
3483 to_intel_plane_state(plane
->base
.state
);
3485 if (plane_state
->base
.visible
)
3486 plane
->update_plane(&plane
->base
,
3487 to_intel_crtc_state(crtc
->state
),
3493 __intel_display_resume(struct drm_device
*dev
,
3494 struct drm_atomic_state
*state
)
3496 struct drm_crtc_state
*crtc_state
;
3497 struct drm_crtc
*crtc
;
3500 intel_modeset_setup_hw_state(dev
);
3501 i915_redisable_vga(to_i915(dev
));
3506 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
3508 * Force recalculation even if we restore
3509 * current state. With fast modeset this may not result
3510 * in a modeset when the state is compatible.
3512 crtc_state
->mode_changed
= true;
3515 /* ignore any reset values/BIOS leftovers in the WM registers */
3516 to_intel_atomic_state(state
)->skip_intermediate_wm
= true;
3518 ret
= drm_atomic_commit(state
);
3520 WARN_ON(ret
== -EDEADLK
);
3524 static bool gpu_reset_clobbers_display(struct drm_i915_private
*dev_priv
)
3526 return intel_has_gpu_reset(dev_priv
) &&
3527 INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
);
3530 void intel_prepare_reset(struct drm_i915_private
*dev_priv
)
3532 struct drm_device
*dev
= &dev_priv
->drm
;
3533 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3534 struct drm_atomic_state
*state
;
3538 * Need mode_config.mutex so that we don't
3539 * trample ongoing ->detect() and whatnot.
3541 mutex_lock(&dev
->mode_config
.mutex
);
3542 drm_modeset_acquire_init(ctx
, 0);
3544 ret
= drm_modeset_lock_all_ctx(dev
, ctx
);
3545 if (ret
!= -EDEADLK
)
3548 drm_modeset_backoff(ctx
);
3551 /* reset doesn't touch the display, but flips might get nuked anyway, */
3552 if (!i915
.force_reset_modeset_test
&&
3553 !gpu_reset_clobbers_display(dev_priv
))
3557 * Disabling the crtcs gracefully seems nicer. Also the
3558 * g33 docs say we should at least disable all the planes.
3560 state
= drm_atomic_helper_duplicate_state(dev
, ctx
);
3561 if (IS_ERR(state
)) {
3562 ret
= PTR_ERR(state
);
3564 DRM_ERROR("Duplicating state failed with %i\n", ret
);
3568 ret
= drm_atomic_helper_disable_all(dev
, ctx
);
3570 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
3574 dev_priv
->modeset_restore_state
= state
;
3575 state
->acquire_ctx
= ctx
;
3579 drm_atomic_state_put(state
);
3582 void intel_finish_reset(struct drm_i915_private
*dev_priv
)
3584 struct drm_device
*dev
= &dev_priv
->drm
;
3585 struct drm_modeset_acquire_ctx
*ctx
= &dev_priv
->reset_ctx
;
3586 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
3590 * Flips in the rings will be nuked by the reset,
3591 * so complete all pending flips so that user space
3592 * will get its events and not get stuck.
3594 intel_complete_page_flips(dev_priv
);
3596 dev_priv
->modeset_restore_state
= NULL
;
3598 /* reset doesn't touch the display */
3599 if (!gpu_reset_clobbers_display(dev_priv
)) {
3602 * Flips in the rings have been nuked by the reset,
3603 * so update the base address of all primary
3604 * planes to the the last fb to make sure we're
3605 * showing the correct fb after a reset.
3607 * FIXME: Atomic will make this obsolete since we won't schedule
3608 * CS-based flips (which might get lost in gpu resets) any more.
3610 intel_update_primary_planes(dev
);
3612 ret
= __intel_display_resume(dev
, state
);
3614 DRM_ERROR("Restoring old state failed with %i\n", ret
);
3618 * The display has been reset as well,
3619 * so need a full re-initialization.
3621 intel_runtime_pm_disable_interrupts(dev_priv
);
3622 intel_runtime_pm_enable_interrupts(dev_priv
);
3624 intel_pps_unlock_regs_wa(dev_priv
);
3625 intel_modeset_init_hw(dev
);
3627 spin_lock_irq(&dev_priv
->irq_lock
);
3628 if (dev_priv
->display
.hpd_irq_setup
)
3629 dev_priv
->display
.hpd_irq_setup(dev_priv
);
3630 spin_unlock_irq(&dev_priv
->irq_lock
);
3632 ret
= __intel_display_resume(dev
, state
);
3634 DRM_ERROR("Restoring old state failed with %i\n", ret
);
3636 intel_hpd_init(dev_priv
);
3640 drm_atomic_state_put(state
);
3641 drm_modeset_drop_locks(ctx
);
3642 drm_modeset_acquire_fini(ctx
);
3643 mutex_unlock(&dev
->mode_config
.mutex
);
3646 static bool abort_flip_on_reset(struct intel_crtc
*crtc
)
3648 struct i915_gpu_error
*error
= &to_i915(crtc
->base
.dev
)->gpu_error
;
3650 if (i915_reset_in_progress(error
))
3653 if (crtc
->reset_count
!= i915_reset_count(error
))
3659 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3661 struct drm_device
*dev
= crtc
->dev
;
3662 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3665 if (abort_flip_on_reset(intel_crtc
))
3668 spin_lock_irq(&dev
->event_lock
);
3669 pending
= to_intel_crtc(crtc
)->flip_work
!= NULL
;
3670 spin_unlock_irq(&dev
->event_lock
);
3675 static void intel_update_pipe_config(struct intel_crtc
*crtc
,
3676 struct intel_crtc_state
*old_crtc_state
)
3678 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3679 struct intel_crtc_state
*pipe_config
=
3680 to_intel_crtc_state(crtc
->base
.state
);
3682 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3683 crtc
->base
.mode
= crtc
->base
.state
->mode
;
3685 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3686 old_crtc_state
->pipe_src_w
, old_crtc_state
->pipe_src_h
,
3687 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
3690 * Update pipe size and adjust fitter if needed: the reason for this is
3691 * that in compute_mode_changes we check the native mode (not the pfit
3692 * mode) to see if we can flip rather than do a full mode set. In the
3693 * fastboot case, we'll flip, but if we don't update the pipesrc and
3694 * pfit state, we'll end up with a big fb scanned out into the wrong
3698 I915_WRITE(PIPESRC(crtc
->pipe
),
3699 ((pipe_config
->pipe_src_w
- 1) << 16) |
3700 (pipe_config
->pipe_src_h
- 1));
3702 /* on skylake this is done by detaching scalers */
3703 if (INTEL_GEN(dev_priv
) >= 9) {
3704 skl_detach_scalers(crtc
);
3706 if (pipe_config
->pch_pfit
.enabled
)
3707 skylake_pfit_enable(crtc
);
3708 } else if (HAS_PCH_SPLIT(dev_priv
)) {
3709 if (pipe_config
->pch_pfit
.enabled
)
3710 ironlake_pfit_enable(crtc
);
3711 else if (old_crtc_state
->pch_pfit
.enabled
)
3712 ironlake_pfit_disable(crtc
, true);
3716 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3718 struct drm_device
*dev
= crtc
->dev
;
3719 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3720 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3721 int pipe
= intel_crtc
->pipe
;
3725 /* enable normal train */
3726 reg
= FDI_TX_CTL(pipe
);
3727 temp
= I915_READ(reg
);
3728 if (IS_IVYBRIDGE(dev_priv
)) {
3729 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3730 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3732 temp
&= ~FDI_LINK_TRAIN_NONE
;
3733 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3735 I915_WRITE(reg
, temp
);
3737 reg
= FDI_RX_CTL(pipe
);
3738 temp
= I915_READ(reg
);
3739 if (HAS_PCH_CPT(dev_priv
)) {
3740 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3741 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3743 temp
&= ~FDI_LINK_TRAIN_NONE
;
3744 temp
|= FDI_LINK_TRAIN_NONE
;
3746 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3748 /* wait one idle pattern time */
3752 /* IVB wants error correction enabled */
3753 if (IS_IVYBRIDGE(dev_priv
))
3754 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3755 FDI_FE_ERRC_ENABLE
);
3758 /* The FDI link training functions for ILK/Ibexpeak. */
3759 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3761 struct drm_device
*dev
= crtc
->dev
;
3762 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3763 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3764 int pipe
= intel_crtc
->pipe
;
3768 /* FDI needs bits from pipe first */
3769 assert_pipe_enabled(dev_priv
, pipe
);
3771 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3773 reg
= FDI_RX_IMR(pipe
);
3774 temp
= I915_READ(reg
);
3775 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3776 temp
&= ~FDI_RX_BIT_LOCK
;
3777 I915_WRITE(reg
, temp
);
3781 /* enable CPU FDI TX and PCH FDI RX */
3782 reg
= FDI_TX_CTL(pipe
);
3783 temp
= I915_READ(reg
);
3784 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3785 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3786 temp
&= ~FDI_LINK_TRAIN_NONE
;
3787 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3788 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3790 reg
= FDI_RX_CTL(pipe
);
3791 temp
= I915_READ(reg
);
3792 temp
&= ~FDI_LINK_TRAIN_NONE
;
3793 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3794 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3799 /* Ironlake workaround, enable clock pointer after FDI enable*/
3800 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3801 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3802 FDI_RX_PHASE_SYNC_POINTER_EN
);
3804 reg
= FDI_RX_IIR(pipe
);
3805 for (tries
= 0; tries
< 5; tries
++) {
3806 temp
= I915_READ(reg
);
3807 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3809 if ((temp
& FDI_RX_BIT_LOCK
)) {
3810 DRM_DEBUG_KMS("FDI train 1 done.\n");
3811 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3816 DRM_ERROR("FDI train 1 fail!\n");
3819 reg
= FDI_TX_CTL(pipe
);
3820 temp
= I915_READ(reg
);
3821 temp
&= ~FDI_LINK_TRAIN_NONE
;
3822 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3823 I915_WRITE(reg
, temp
);
3825 reg
= FDI_RX_CTL(pipe
);
3826 temp
= I915_READ(reg
);
3827 temp
&= ~FDI_LINK_TRAIN_NONE
;
3828 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3829 I915_WRITE(reg
, temp
);
3834 reg
= FDI_RX_IIR(pipe
);
3835 for (tries
= 0; tries
< 5; tries
++) {
3836 temp
= I915_READ(reg
);
3837 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3839 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3840 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3841 DRM_DEBUG_KMS("FDI train 2 done.\n");
3846 DRM_ERROR("FDI train 2 fail!\n");
3848 DRM_DEBUG_KMS("FDI train done\n");
3852 static const int snb_b_fdi_train_param
[] = {
3853 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3854 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3855 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3856 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3859 /* The FDI link training functions for SNB/Cougarpoint. */
3860 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3862 struct drm_device
*dev
= crtc
->dev
;
3863 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3864 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3865 int pipe
= intel_crtc
->pipe
;
3869 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3871 reg
= FDI_RX_IMR(pipe
);
3872 temp
= I915_READ(reg
);
3873 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3874 temp
&= ~FDI_RX_BIT_LOCK
;
3875 I915_WRITE(reg
, temp
);
3880 /* enable CPU FDI TX and PCH FDI RX */
3881 reg
= FDI_TX_CTL(pipe
);
3882 temp
= I915_READ(reg
);
3883 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3884 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3885 temp
&= ~FDI_LINK_TRAIN_NONE
;
3886 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3887 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3889 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3890 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3892 I915_WRITE(FDI_RX_MISC(pipe
),
3893 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3895 reg
= FDI_RX_CTL(pipe
);
3896 temp
= I915_READ(reg
);
3897 if (HAS_PCH_CPT(dev_priv
)) {
3898 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3899 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3901 temp
&= ~FDI_LINK_TRAIN_NONE
;
3902 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3904 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3909 for (i
= 0; i
< 4; i
++) {
3910 reg
= FDI_TX_CTL(pipe
);
3911 temp
= I915_READ(reg
);
3912 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3913 temp
|= snb_b_fdi_train_param
[i
];
3914 I915_WRITE(reg
, temp
);
3919 for (retry
= 0; retry
< 5; retry
++) {
3920 reg
= FDI_RX_IIR(pipe
);
3921 temp
= I915_READ(reg
);
3922 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3923 if (temp
& FDI_RX_BIT_LOCK
) {
3924 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3925 DRM_DEBUG_KMS("FDI train 1 done.\n");
3934 DRM_ERROR("FDI train 1 fail!\n");
3937 reg
= FDI_TX_CTL(pipe
);
3938 temp
= I915_READ(reg
);
3939 temp
&= ~FDI_LINK_TRAIN_NONE
;
3940 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3941 if (IS_GEN6(dev_priv
)) {
3942 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3944 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3946 I915_WRITE(reg
, temp
);
3948 reg
= FDI_RX_CTL(pipe
);
3949 temp
= I915_READ(reg
);
3950 if (HAS_PCH_CPT(dev_priv
)) {
3951 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3952 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3954 temp
&= ~FDI_LINK_TRAIN_NONE
;
3955 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3957 I915_WRITE(reg
, temp
);
3962 for (i
= 0; i
< 4; i
++) {
3963 reg
= FDI_TX_CTL(pipe
);
3964 temp
= I915_READ(reg
);
3965 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3966 temp
|= snb_b_fdi_train_param
[i
];
3967 I915_WRITE(reg
, temp
);
3972 for (retry
= 0; retry
< 5; retry
++) {
3973 reg
= FDI_RX_IIR(pipe
);
3974 temp
= I915_READ(reg
);
3975 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3976 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3977 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3978 DRM_DEBUG_KMS("FDI train 2 done.\n");
3987 DRM_ERROR("FDI train 2 fail!\n");
3989 DRM_DEBUG_KMS("FDI train done.\n");
3992 /* Manual link training for Ivy Bridge A0 parts */
3993 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3995 struct drm_device
*dev
= crtc
->dev
;
3996 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3997 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3998 int pipe
= intel_crtc
->pipe
;
4002 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4004 reg
= FDI_RX_IMR(pipe
);
4005 temp
= I915_READ(reg
);
4006 temp
&= ~FDI_RX_SYMBOL_LOCK
;
4007 temp
&= ~FDI_RX_BIT_LOCK
;
4008 I915_WRITE(reg
, temp
);
4013 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4014 I915_READ(FDI_RX_IIR(pipe
)));
4016 /* Try each vswing and preemphasis setting twice before moving on */
4017 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
4018 /* disable first in case we need to retry */
4019 reg
= FDI_TX_CTL(pipe
);
4020 temp
= I915_READ(reg
);
4021 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
4022 temp
&= ~FDI_TX_ENABLE
;
4023 I915_WRITE(reg
, temp
);
4025 reg
= FDI_RX_CTL(pipe
);
4026 temp
= I915_READ(reg
);
4027 temp
&= ~FDI_LINK_TRAIN_AUTO
;
4028 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4029 temp
&= ~FDI_RX_ENABLE
;
4030 I915_WRITE(reg
, temp
);
4032 /* enable CPU FDI TX and PCH FDI RX */
4033 reg
= FDI_TX_CTL(pipe
);
4034 temp
= I915_READ(reg
);
4035 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
4036 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
4037 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
4038 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
4039 temp
|= snb_b_fdi_train_param
[j
/2];
4040 temp
|= FDI_COMPOSITE_SYNC
;
4041 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
4043 I915_WRITE(FDI_RX_MISC(pipe
),
4044 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
4046 reg
= FDI_RX_CTL(pipe
);
4047 temp
= I915_READ(reg
);
4048 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4049 temp
|= FDI_COMPOSITE_SYNC
;
4050 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
4053 udelay(1); /* should be 0.5us */
4055 for (i
= 0; i
< 4; i
++) {
4056 reg
= FDI_RX_IIR(pipe
);
4057 temp
= I915_READ(reg
);
4058 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4060 if (temp
& FDI_RX_BIT_LOCK
||
4061 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
4062 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
4063 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4067 udelay(1); /* should be 0.5us */
4070 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
4075 reg
= FDI_TX_CTL(pipe
);
4076 temp
= I915_READ(reg
);
4077 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
4078 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
4079 I915_WRITE(reg
, temp
);
4081 reg
= FDI_RX_CTL(pipe
);
4082 temp
= I915_READ(reg
);
4083 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4084 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
4085 I915_WRITE(reg
, temp
);
4088 udelay(2); /* should be 1.5us */
4090 for (i
= 0; i
< 4; i
++) {
4091 reg
= FDI_RX_IIR(pipe
);
4092 temp
= I915_READ(reg
);
4093 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
4095 if (temp
& FDI_RX_SYMBOL_LOCK
||
4096 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
4097 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
4098 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4102 udelay(2); /* should be 1.5us */
4105 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
4109 DRM_DEBUG_KMS("FDI train done.\n");
4112 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
4114 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4115 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4116 int pipe
= intel_crtc
->pipe
;
4120 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4121 reg
= FDI_RX_CTL(pipe
);
4122 temp
= I915_READ(reg
);
4123 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
4124 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
4125 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4126 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
4131 /* Switch from Rawclk to PCDclk */
4132 temp
= I915_READ(reg
);
4133 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
4138 /* Enable CPU FDI TX PLL, always on for Ironlake */
4139 reg
= FDI_TX_CTL(pipe
);
4140 temp
= I915_READ(reg
);
4141 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
4142 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
4149 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
4151 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4152 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4153 int pipe
= intel_crtc
->pipe
;
4157 /* Switch from PCDclk to Rawclk */
4158 reg
= FDI_RX_CTL(pipe
);
4159 temp
= I915_READ(reg
);
4160 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
4162 /* Disable CPU FDI TX PLL */
4163 reg
= FDI_TX_CTL(pipe
);
4164 temp
= I915_READ(reg
);
4165 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
4170 reg
= FDI_RX_CTL(pipe
);
4171 temp
= I915_READ(reg
);
4172 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
4174 /* Wait for the clocks to turn off. */
4179 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
4181 struct drm_device
*dev
= crtc
->dev
;
4182 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4183 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4184 int pipe
= intel_crtc
->pipe
;
4188 /* disable CPU FDI tx and PCH FDI rx */
4189 reg
= FDI_TX_CTL(pipe
);
4190 temp
= I915_READ(reg
);
4191 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
4194 reg
= FDI_RX_CTL(pipe
);
4195 temp
= I915_READ(reg
);
4196 temp
&= ~(0x7 << 16);
4197 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4198 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
4203 /* Ironlake workaround, disable clock pointer after downing FDI */
4204 if (HAS_PCH_IBX(dev_priv
))
4205 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
4207 /* still set train pattern 1 */
4208 reg
= FDI_TX_CTL(pipe
);
4209 temp
= I915_READ(reg
);
4210 temp
&= ~FDI_LINK_TRAIN_NONE
;
4211 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4212 I915_WRITE(reg
, temp
);
4214 reg
= FDI_RX_CTL(pipe
);
4215 temp
= I915_READ(reg
);
4216 if (HAS_PCH_CPT(dev_priv
)) {
4217 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
4218 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
4220 temp
&= ~FDI_LINK_TRAIN_NONE
;
4221 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
4223 /* BPC in FDI rx is consistent with that in PIPECONF */
4224 temp
&= ~(0x07 << 16);
4225 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
4226 I915_WRITE(reg
, temp
);
4232 bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv
)
4234 struct intel_crtc
*crtc
;
4236 /* Note that we don't need to be called with mode_config.lock here
4237 * as our list of CRTC objects is static for the lifetime of the
4238 * device and so cannot disappear as we iterate. Similarly, we can
4239 * happily treat the predicates as racy, atomic checks as userspace
4240 * cannot claim and pin a new fb without at least acquring the
4241 * struct_mutex and so serialising with us.
4243 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
4244 if (atomic_read(&crtc
->unpin_work_count
) == 0)
4247 if (crtc
->flip_work
)
4248 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4256 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
4258 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
4259 struct intel_flip_work
*work
= intel_crtc
->flip_work
;
4261 intel_crtc
->flip_work
= NULL
;
4264 drm_crtc_send_vblank_event(&intel_crtc
->base
, work
->event
);
4266 drm_crtc_vblank_put(&intel_crtc
->base
);
4268 wake_up_all(&dev_priv
->pending_flip_queue
);
4269 queue_work(dev_priv
->wq
, &work
->unpin_work
);
4271 trace_i915_flip_complete(intel_crtc
->plane
,
4272 work
->pending_flip_obj
);
4275 static int intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
4277 struct drm_device
*dev
= crtc
->dev
;
4278 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4281 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
4283 ret
= wait_event_interruptible_timeout(
4284 dev_priv
->pending_flip_queue
,
4285 !intel_crtc_has_pending_flip(crtc
),
4292 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4293 struct intel_flip_work
*work
;
4295 spin_lock_irq(&dev
->event_lock
);
4296 work
= intel_crtc
->flip_work
;
4297 if (work
&& !is_mmio_work(work
)) {
4298 WARN_ONCE(1, "Removing stuck page flip\n");
4299 page_flip_completed(intel_crtc
);
4301 spin_unlock_irq(&dev
->event_lock
);
4307 void lpt_disable_iclkip(struct drm_i915_private
*dev_priv
)
4311 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
4313 mutex_lock(&dev_priv
->sb_lock
);
4315 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4316 temp
|= SBI_SSCCTL_DISABLE
;
4317 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4319 mutex_unlock(&dev_priv
->sb_lock
);
4322 /* Program iCLKIP clock to the desired frequency */
4323 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
4325 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
4326 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
4327 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
4330 lpt_disable_iclkip(dev_priv
);
4332 /* The iCLK virtual clock root frequency is in MHz,
4333 * but the adjusted_mode->crtc_clock in in KHz. To get the
4334 * divisors, it is necessary to divide one by another, so we
4335 * convert the virtual clock precision to KHz here for higher
4338 for (auxdiv
= 0; auxdiv
< 2; auxdiv
++) {
4339 u32 iclk_virtual_root_freq
= 172800 * 1000;
4340 u32 iclk_pi_range
= 64;
4341 u32 desired_divisor
;
4343 desired_divisor
= DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4345 divsel
= (desired_divisor
/ iclk_pi_range
) - 2;
4346 phaseinc
= desired_divisor
% iclk_pi_range
;
4349 * Near 20MHz is a corner case which is
4350 * out of range for the 7-bit divisor
4356 /* This should not happen with any sane values */
4357 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4358 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4359 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4360 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4362 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4369 mutex_lock(&dev_priv
->sb_lock
);
4371 /* Program SSCDIVINTPHASE6 */
4372 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4373 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4374 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4375 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4376 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4377 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4378 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4379 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4381 /* Program SSCAUXDIV */
4382 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4383 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4384 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4385 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4387 /* Enable modulator and associated divider */
4388 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4389 temp
&= ~SBI_SSCCTL_DISABLE
;
4390 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4392 mutex_unlock(&dev_priv
->sb_lock
);
4394 /* Wait for initialization time */
4397 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4400 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
)
4402 u32 divsel
, phaseinc
, auxdiv
;
4403 u32 iclk_virtual_root_freq
= 172800 * 1000;
4404 u32 iclk_pi_range
= 64;
4405 u32 desired_divisor
;
4408 if ((I915_READ(PIXCLK_GATE
) & PIXCLK_GATE_UNGATE
) == 0)
4411 mutex_lock(&dev_priv
->sb_lock
);
4413 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4414 if (temp
& SBI_SSCCTL_DISABLE
) {
4415 mutex_unlock(&dev_priv
->sb_lock
);
4419 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4420 divsel
= (temp
& SBI_SSCDIVINTPHASE_DIVSEL_MASK
) >>
4421 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT
;
4422 phaseinc
= (temp
& SBI_SSCDIVINTPHASE_INCVAL_MASK
) >>
4423 SBI_SSCDIVINTPHASE_INCVAL_SHIFT
;
4425 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4426 auxdiv
= (temp
& SBI_SSCAUXDIV_FINALDIV2SEL_MASK
) >>
4427 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT
;
4429 mutex_unlock(&dev_priv
->sb_lock
);
4431 desired_divisor
= (divsel
+ 2) * iclk_pi_range
+ phaseinc
;
4433 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq
,
4434 desired_divisor
<< auxdiv
);
4437 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4438 enum pipe pch_transcoder
)
4440 struct drm_device
*dev
= crtc
->base
.dev
;
4441 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4442 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4444 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4445 I915_READ(HTOTAL(cpu_transcoder
)));
4446 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4447 I915_READ(HBLANK(cpu_transcoder
)));
4448 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4449 I915_READ(HSYNC(cpu_transcoder
)));
4451 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4452 I915_READ(VTOTAL(cpu_transcoder
)));
4453 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4454 I915_READ(VBLANK(cpu_transcoder
)));
4455 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4456 I915_READ(VSYNC(cpu_transcoder
)));
4457 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4458 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4461 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4463 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4466 temp
= I915_READ(SOUTH_CHICKEN1
);
4467 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4470 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4471 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4473 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4475 temp
|= FDI_BC_BIFURCATION_SELECT
;
4477 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4478 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4479 POSTING_READ(SOUTH_CHICKEN1
);
4482 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4484 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4486 switch (intel_crtc
->pipe
) {
4490 if (intel_crtc
->config
->fdi_lanes
> 2)
4491 cpt_set_fdi_bc_bifurcation(dev
, false);
4493 cpt_set_fdi_bc_bifurcation(dev
, true);
4497 cpt_set_fdi_bc_bifurcation(dev
, true);
4505 /* Return which DP Port should be selected for Transcoder DP control */
4507 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4509 struct drm_device
*dev
= crtc
->dev
;
4510 struct intel_encoder
*encoder
;
4512 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4513 if (encoder
->type
== INTEL_OUTPUT_DP
||
4514 encoder
->type
== INTEL_OUTPUT_EDP
)
4515 return enc_to_dig_port(&encoder
->base
)->port
;
4522 * Enable PCH resources required for PCH ports:
4524 * - FDI training & RX/TX
4525 * - update transcoder timings
4526 * - DP transcoding bits
4529 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4531 struct drm_device
*dev
= crtc
->dev
;
4532 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4533 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4534 int pipe
= intel_crtc
->pipe
;
4537 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4539 if (IS_IVYBRIDGE(dev_priv
))
4540 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4542 /* Write the TU size bits before fdi link training, so that error
4543 * detection works. */
4544 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4545 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4547 /* For PCH output, training FDI link */
4548 dev_priv
->display
.fdi_link_train(crtc
);
4550 /* We need to program the right clock selection before writing the pixel
4551 * mutliplier into the DPLL. */
4552 if (HAS_PCH_CPT(dev_priv
)) {
4555 temp
= I915_READ(PCH_DPLL_SEL
);
4556 temp
|= TRANS_DPLL_ENABLE(pipe
);
4557 sel
= TRANS_DPLLB_SEL(pipe
);
4558 if (intel_crtc
->config
->shared_dpll
==
4559 intel_get_shared_dpll_by_id(dev_priv
, DPLL_ID_PCH_PLL_B
))
4563 I915_WRITE(PCH_DPLL_SEL
, temp
);
4566 /* XXX: pch pll's can be enabled any time before we enable the PCH
4567 * transcoder, and we actually should do this to not upset any PCH
4568 * transcoder that already use the clock when we share it.
4570 * Note that enable_shared_dpll tries to do the right thing, but
4571 * get_shared_dpll unconditionally resets the pll - we need that to have
4572 * the right LVDS enable sequence. */
4573 intel_enable_shared_dpll(intel_crtc
);
4575 /* set transcoder timing, panel must allow it */
4576 assert_panel_unlocked(dev_priv
, pipe
);
4577 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4579 intel_fdi_normal_train(crtc
);
4581 /* For PCH DP, enable TRANS_DP_CTL */
4582 if (HAS_PCH_CPT(dev_priv
) &&
4583 intel_crtc_has_dp_encoder(intel_crtc
->config
)) {
4584 const struct drm_display_mode
*adjusted_mode
=
4585 &intel_crtc
->config
->base
.adjusted_mode
;
4586 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4587 i915_reg_t reg
= TRANS_DP_CTL(pipe
);
4588 temp
= I915_READ(reg
);
4589 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4590 TRANS_DP_SYNC_MASK
|
4592 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4593 temp
|= bpc
<< 9; /* same format but at 11:9 */
4595 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
4596 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4597 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
4598 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4600 switch (intel_trans_dp_port_sel(crtc
)) {
4602 temp
|= TRANS_DP_PORT_SEL_B
;
4605 temp
|= TRANS_DP_PORT_SEL_C
;
4608 temp
|= TRANS_DP_PORT_SEL_D
;
4614 I915_WRITE(reg
, temp
);
4617 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4620 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4622 struct drm_device
*dev
= crtc
->dev
;
4623 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4624 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4625 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4627 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4629 lpt_program_iclkip(crtc
);
4631 /* Set transcoder timing. */
4632 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4634 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4637 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4639 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4640 i915_reg_t dslreg
= PIPEDSL(pipe
);
4643 temp
= I915_READ(dslreg
);
4645 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4646 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4647 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4652 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4653 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4654 int src_w
, int src_h
, int dst_w
, int dst_h
)
4656 struct intel_crtc_scaler_state
*scaler_state
=
4657 &crtc_state
->scaler_state
;
4658 struct intel_crtc
*intel_crtc
=
4659 to_intel_crtc(crtc_state
->base
.crtc
);
4662 need_scaling
= drm_rotation_90_or_270(rotation
) ?
4663 (src_h
!= dst_w
|| src_w
!= dst_h
):
4664 (src_w
!= dst_w
|| src_h
!= dst_h
);
4667 * if plane is being disabled or scaler is no more required or force detach
4668 * - free scaler binded to this plane/crtc
4669 * - in order to do this, update crtc->scaler_usage
4671 * Here scaler state in crtc_state is set free so that
4672 * scaler can be assigned to other user. Actual register
4673 * update to free the scaler is done in plane/panel-fit programming.
4674 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4676 if (force_detach
|| !need_scaling
) {
4677 if (*scaler_id
>= 0) {
4678 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4679 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4681 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4682 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4683 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4684 scaler_state
->scaler_users
);
4691 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4692 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4694 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4695 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4696 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4697 "size is out of scaler range\n",
4698 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4702 /* mark this plane as a scaler user in crtc_state */
4703 scaler_state
->scaler_users
|= (1 << scaler_user
);
4704 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4705 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4706 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4707 scaler_state
->scaler_users
);
4713 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4715 * @state: crtc's scaler state
4718 * 0 - scaler_usage updated successfully
4719 * error - requested scaling cannot be supported or other error condition
4721 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4723 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4725 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4726 &state
->scaler_state
.scaler_id
, DRM_ROTATE_0
,
4727 state
->pipe_src_w
, state
->pipe_src_h
,
4728 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4732 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4734 * @state: crtc's scaler state
4735 * @plane_state: atomic plane state to update
4738 * 0 - scaler_usage updated successfully
4739 * error - requested scaling cannot be supported or other error condition
4741 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4742 struct intel_plane_state
*plane_state
)
4745 struct intel_plane
*intel_plane
=
4746 to_intel_plane(plane_state
->base
.plane
);
4747 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4750 bool force_detach
= !fb
|| !plane_state
->base
.visible
;
4752 ret
= skl_update_scaler(crtc_state
, force_detach
,
4753 drm_plane_index(&intel_plane
->base
),
4754 &plane_state
->scaler_id
,
4755 plane_state
->base
.rotation
,
4756 drm_rect_width(&plane_state
->base
.src
) >> 16,
4757 drm_rect_height(&plane_state
->base
.src
) >> 16,
4758 drm_rect_width(&plane_state
->base
.dst
),
4759 drm_rect_height(&plane_state
->base
.dst
));
4761 if (ret
|| plane_state
->scaler_id
< 0)
4764 /* check colorkey */
4765 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4766 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4767 intel_plane
->base
.base
.id
,
4768 intel_plane
->base
.name
);
4772 /* Check src format */
4773 switch (fb
->pixel_format
) {
4774 case DRM_FORMAT_RGB565
:
4775 case DRM_FORMAT_XBGR8888
:
4776 case DRM_FORMAT_XRGB8888
:
4777 case DRM_FORMAT_ABGR8888
:
4778 case DRM_FORMAT_ARGB8888
:
4779 case DRM_FORMAT_XRGB2101010
:
4780 case DRM_FORMAT_XBGR2101010
:
4781 case DRM_FORMAT_YUYV
:
4782 case DRM_FORMAT_YVYU
:
4783 case DRM_FORMAT_UYVY
:
4784 case DRM_FORMAT_VYUY
:
4787 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4788 intel_plane
->base
.base
.id
, intel_plane
->base
.name
,
4789 fb
->base
.id
, fb
->pixel_format
);
4796 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4800 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4801 skl_detach_scaler(crtc
, i
);
4804 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4806 struct drm_device
*dev
= crtc
->base
.dev
;
4807 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4808 int pipe
= crtc
->pipe
;
4809 struct intel_crtc_scaler_state
*scaler_state
=
4810 &crtc
->config
->scaler_state
;
4812 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4814 if (crtc
->config
->pch_pfit
.enabled
) {
4817 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4818 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4822 id
= scaler_state
->scaler_id
;
4823 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4824 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4825 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4826 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4828 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4832 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4834 struct drm_device
*dev
= crtc
->base
.dev
;
4835 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4836 int pipe
= crtc
->pipe
;
4838 if (crtc
->config
->pch_pfit
.enabled
) {
4839 /* Force use of hard-coded filter coefficients
4840 * as some pre-programmed values are broken,
4843 if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
))
4844 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4845 PF_PIPE_SEL_IVB(pipe
));
4847 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4848 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4849 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4853 void hsw_enable_ips(struct intel_crtc
*crtc
)
4855 struct drm_device
*dev
= crtc
->base
.dev
;
4856 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4858 if (!crtc
->config
->ips_enabled
)
4862 * We can only enable IPS after we enable a plane and wait for a vblank
4863 * This function is called from post_plane_update, which is run after
4867 assert_plane_enabled(dev_priv
, crtc
->plane
);
4868 if (IS_BROADWELL(dev_priv
)) {
4869 mutex_lock(&dev_priv
->rps
.hw_lock
);
4870 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4871 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4872 /* Quoting Art Runyan: "its not safe to expect any particular
4873 * value in IPS_CTL bit 31 after enabling IPS through the
4874 * mailbox." Moreover, the mailbox may return a bogus state,
4875 * so we need to just enable it and continue on.
4878 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4879 /* The bit only becomes 1 in the next vblank, so this wait here
4880 * is essentially intel_wait_for_vblank. If we don't have this
4881 * and don't wait for vblanks until the end of crtc_enable, then
4882 * the HW state readout code will complain that the expected
4883 * IPS_CTL value is not the one we read. */
4884 if (intel_wait_for_register(dev_priv
,
4885 IPS_CTL
, IPS_ENABLE
, IPS_ENABLE
,
4887 DRM_ERROR("Timed out waiting for IPS enable\n");
4891 void hsw_disable_ips(struct intel_crtc
*crtc
)
4893 struct drm_device
*dev
= crtc
->base
.dev
;
4894 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4896 if (!crtc
->config
->ips_enabled
)
4899 assert_plane_enabled(dev_priv
, crtc
->plane
);
4900 if (IS_BROADWELL(dev_priv
)) {
4901 mutex_lock(&dev_priv
->rps
.hw_lock
);
4902 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4903 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4904 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4905 if (intel_wait_for_register(dev_priv
,
4906 IPS_CTL
, IPS_ENABLE
, 0,
4908 DRM_ERROR("Timed out waiting for IPS disable\n");
4910 I915_WRITE(IPS_CTL
, 0);
4911 POSTING_READ(IPS_CTL
);
4914 /* We need to wait for a vblank before we can disable the plane. */
4915 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
4918 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4920 if (intel_crtc
->overlay
) {
4921 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4922 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4924 mutex_lock(&dev
->struct_mutex
);
4925 dev_priv
->mm
.interruptible
= false;
4926 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4927 dev_priv
->mm
.interruptible
= true;
4928 mutex_unlock(&dev
->struct_mutex
);
4931 /* Let userspace switch the overlay on again. In most cases userspace
4932 * has to recompute where to put it anyway.
4937 * intel_post_enable_primary - Perform operations after enabling primary plane
4938 * @crtc: the CRTC whose primary plane was just enabled
4940 * Performs potentially sleeping operations that must be done after the primary
4941 * plane is enabled, such as updating FBC and IPS. Note that this may be
4942 * called due to an explicit primary plane update, or due to an implicit
4943 * re-enable that is caused when a sprite plane is updated to no longer
4944 * completely hide the primary plane.
4947 intel_post_enable_primary(struct drm_crtc
*crtc
)
4949 struct drm_device
*dev
= crtc
->dev
;
4950 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4951 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4952 int pipe
= intel_crtc
->pipe
;
4955 * FIXME IPS should be fine as long as one plane is
4956 * enabled, but in practice it seems to have problems
4957 * when going from primary only to sprite only and vice
4960 hsw_enable_ips(intel_crtc
);
4963 * Gen2 reports pipe underruns whenever all planes are disabled.
4964 * So don't enable underrun reporting before at least some planes
4966 * FIXME: Need to fix the logic to work when we turn off all planes
4967 * but leave the pipe running.
4969 if (IS_GEN2(dev_priv
))
4970 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4972 /* Underruns don't always raise interrupts, so check manually. */
4973 intel_check_cpu_fifo_underruns(dev_priv
);
4974 intel_check_pch_fifo_underruns(dev_priv
);
4977 /* FIXME move all this to pre_plane_update() with proper state tracking */
4979 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4981 struct drm_device
*dev
= crtc
->dev
;
4982 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4983 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4984 int pipe
= intel_crtc
->pipe
;
4987 * Gen2 reports pipe underruns whenever all planes are disabled.
4988 * So diasble underrun reporting before all the planes get disabled.
4989 * FIXME: Need to fix the logic to work when we turn off all planes
4990 * but leave the pipe running.
4992 if (IS_GEN2(dev_priv
))
4993 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4996 * FIXME IPS should be fine as long as one plane is
4997 * enabled, but in practice it seems to have problems
4998 * when going from primary only to sprite only and vice
5001 hsw_disable_ips(intel_crtc
);
5004 /* FIXME get rid of this and use pre_plane_update */
5006 intel_pre_disable_primary_noatomic(struct drm_crtc
*crtc
)
5008 struct drm_device
*dev
= crtc
->dev
;
5009 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5011 int pipe
= intel_crtc
->pipe
;
5013 intel_pre_disable_primary(crtc
);
5016 * Vblank time updates from the shadow to live plane control register
5017 * are blocked if the memory self-refresh mode is active at that
5018 * moment. So to make sure the plane gets truly disabled, disable
5019 * first the self-refresh mode. The self-refresh enable bit in turn
5020 * will be checked/applied by the HW only at the next frame start
5021 * event which is after the vblank start event, so we need to have a
5022 * wait-for-vblank between disabling the plane and the pipe.
5024 if (HAS_GMCH_DISPLAY(dev_priv
) &&
5025 intel_set_memory_cxsr(dev_priv
, false))
5026 intel_wait_for_vblank(dev_priv
, pipe
);
5029 static void intel_post_plane_update(struct intel_crtc_state
*old_crtc_state
)
5031 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5032 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5033 struct intel_crtc_state
*pipe_config
=
5034 to_intel_crtc_state(crtc
->base
.state
);
5035 struct drm_plane
*primary
= crtc
->base
.primary
;
5036 struct drm_plane_state
*old_pri_state
=
5037 drm_atomic_get_existing_plane_state(old_state
, primary
);
5039 intel_frontbuffer_flip(to_i915(crtc
->base
.dev
), pipe_config
->fb_bits
);
5041 crtc
->wm
.cxsr_allowed
= true;
5043 if (pipe_config
->update_wm_post
&& pipe_config
->base
.active
)
5044 intel_update_watermarks(crtc
);
5046 if (old_pri_state
) {
5047 struct intel_plane_state
*primary_state
=
5048 to_intel_plane_state(primary
->state
);
5049 struct intel_plane_state
*old_primary_state
=
5050 to_intel_plane_state(old_pri_state
);
5052 intel_fbc_post_update(crtc
);
5054 if (primary_state
->base
.visible
&&
5055 (needs_modeset(&pipe_config
->base
) ||
5056 !old_primary_state
->base
.visible
))
5057 intel_post_enable_primary(&crtc
->base
);
5061 static void intel_pre_plane_update(struct intel_crtc_state
*old_crtc_state
)
5063 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->base
.crtc
);
5064 struct drm_device
*dev
= crtc
->base
.dev
;
5065 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5066 struct intel_crtc_state
*pipe_config
=
5067 to_intel_crtc_state(crtc
->base
.state
);
5068 struct drm_atomic_state
*old_state
= old_crtc_state
->base
.state
;
5069 struct drm_plane
*primary
= crtc
->base
.primary
;
5070 struct drm_plane_state
*old_pri_state
=
5071 drm_atomic_get_existing_plane_state(old_state
, primary
);
5072 bool modeset
= needs_modeset(&pipe_config
->base
);
5073 struct intel_atomic_state
*old_intel_state
=
5074 to_intel_atomic_state(old_state
);
5076 if (old_pri_state
) {
5077 struct intel_plane_state
*primary_state
=
5078 to_intel_plane_state(primary
->state
);
5079 struct intel_plane_state
*old_primary_state
=
5080 to_intel_plane_state(old_pri_state
);
5082 intel_fbc_pre_update(crtc
, pipe_config
, primary_state
);
5084 if (old_primary_state
->base
.visible
&&
5085 (modeset
|| !primary_state
->base
.visible
))
5086 intel_pre_disable_primary(&crtc
->base
);
5089 if (pipe_config
->disable_cxsr
&& HAS_GMCH_DISPLAY(dev_priv
)) {
5090 crtc
->wm
.cxsr_allowed
= false;
5093 * Vblank time updates from the shadow to live plane control register
5094 * are blocked if the memory self-refresh mode is active at that
5095 * moment. So to make sure the plane gets truly disabled, disable
5096 * first the self-refresh mode. The self-refresh enable bit in turn
5097 * will be checked/applied by the HW only at the next frame start
5098 * event which is after the vblank start event, so we need to have a
5099 * wait-for-vblank between disabling the plane and the pipe.
5101 if (old_crtc_state
->base
.active
&&
5102 intel_set_memory_cxsr(dev_priv
, false))
5103 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5107 * IVB workaround: must disable low power watermarks for at least
5108 * one frame before enabling scaling. LP watermarks can be re-enabled
5109 * when scaling is disabled.
5111 * WaCxSRDisabledForSpriteScaling:ivb
5113 if (pipe_config
->disable_lp_wm
&& ilk_disable_lp_wm(dev
))
5114 intel_wait_for_vblank(dev_priv
, crtc
->pipe
);
5117 * If we're doing a modeset, we're done. No need to do any pre-vblank
5118 * watermark programming here.
5120 if (needs_modeset(&pipe_config
->base
))
5124 * For platforms that support atomic watermarks, program the
5125 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5126 * will be the intermediate values that are safe for both pre- and
5127 * post- vblank; when vblank happens, the 'active' values will be set
5128 * to the final 'target' values and we'll do this again to get the
5129 * optimal watermarks. For gen9+ platforms, the values we program here
5130 * will be the final target values which will get automatically latched
5131 * at vblank time; no further programming will be necessary.
5133 * If a platform hasn't been transitioned to atomic watermarks yet,
5134 * we'll continue to update watermarks the old way, if flags tell
5137 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5138 dev_priv
->display
.initial_watermarks(old_intel_state
,
5140 else if (pipe_config
->update_wm_pre
)
5141 intel_update_watermarks(crtc
);
5144 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
5146 struct drm_device
*dev
= crtc
->dev
;
5147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5148 struct drm_plane
*p
;
5149 int pipe
= intel_crtc
->pipe
;
5151 intel_crtc_dpms_overlay_disable(intel_crtc
);
5153 drm_for_each_plane_mask(p
, dev
, plane_mask
)
5154 to_intel_plane(p
)->disable_plane(p
, crtc
);
5157 * FIXME: Once we grow proper nuclear flip support out of this we need
5158 * to compute the mask of flip planes precisely. For the time being
5159 * consider this a flip to a NULL plane.
5161 intel_frontbuffer_flip(to_i915(dev
), INTEL_FRONTBUFFER_ALL_MASK(pipe
));
5164 static void intel_encoders_pre_pll_enable(struct drm_crtc
*crtc
,
5165 struct intel_crtc_state
*crtc_state
,
5166 struct drm_atomic_state
*old_state
)
5168 struct drm_connector_state
*old_conn_state
;
5169 struct drm_connector
*conn
;
5172 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5173 struct drm_connector_state
*conn_state
= conn
->state
;
5174 struct intel_encoder
*encoder
=
5175 to_intel_encoder(conn_state
->best_encoder
);
5177 if (conn_state
->crtc
!= crtc
)
5180 if (encoder
->pre_pll_enable
)
5181 encoder
->pre_pll_enable(encoder
, crtc_state
, conn_state
);
5185 static void intel_encoders_pre_enable(struct drm_crtc
*crtc
,
5186 struct intel_crtc_state
*crtc_state
,
5187 struct drm_atomic_state
*old_state
)
5189 struct drm_connector_state
*old_conn_state
;
5190 struct drm_connector
*conn
;
5193 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5194 struct drm_connector_state
*conn_state
= conn
->state
;
5195 struct intel_encoder
*encoder
=
5196 to_intel_encoder(conn_state
->best_encoder
);
5198 if (conn_state
->crtc
!= crtc
)
5201 if (encoder
->pre_enable
)
5202 encoder
->pre_enable(encoder
, crtc_state
, conn_state
);
5206 static void intel_encoders_enable(struct drm_crtc
*crtc
,
5207 struct intel_crtc_state
*crtc_state
,
5208 struct drm_atomic_state
*old_state
)
5210 struct drm_connector_state
*old_conn_state
;
5211 struct drm_connector
*conn
;
5214 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5215 struct drm_connector_state
*conn_state
= conn
->state
;
5216 struct intel_encoder
*encoder
=
5217 to_intel_encoder(conn_state
->best_encoder
);
5219 if (conn_state
->crtc
!= crtc
)
5222 encoder
->enable(encoder
, crtc_state
, conn_state
);
5223 intel_opregion_notify_encoder(encoder
, true);
5227 static void intel_encoders_disable(struct drm_crtc
*crtc
,
5228 struct intel_crtc_state
*old_crtc_state
,
5229 struct drm_atomic_state
*old_state
)
5231 struct drm_connector_state
*old_conn_state
;
5232 struct drm_connector
*conn
;
5235 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5236 struct intel_encoder
*encoder
=
5237 to_intel_encoder(old_conn_state
->best_encoder
);
5239 if (old_conn_state
->crtc
!= crtc
)
5242 intel_opregion_notify_encoder(encoder
, false);
5243 encoder
->disable(encoder
, old_crtc_state
, old_conn_state
);
5247 static void intel_encoders_post_disable(struct drm_crtc
*crtc
,
5248 struct intel_crtc_state
*old_crtc_state
,
5249 struct drm_atomic_state
*old_state
)
5251 struct drm_connector_state
*old_conn_state
;
5252 struct drm_connector
*conn
;
5255 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5256 struct intel_encoder
*encoder
=
5257 to_intel_encoder(old_conn_state
->best_encoder
);
5259 if (old_conn_state
->crtc
!= crtc
)
5262 if (encoder
->post_disable
)
5263 encoder
->post_disable(encoder
, old_crtc_state
, old_conn_state
);
5267 static void intel_encoders_post_pll_disable(struct drm_crtc
*crtc
,
5268 struct intel_crtc_state
*old_crtc_state
,
5269 struct drm_atomic_state
*old_state
)
5271 struct drm_connector_state
*old_conn_state
;
5272 struct drm_connector
*conn
;
5275 for_each_connector_in_state(old_state
, conn
, old_conn_state
, i
) {
5276 struct intel_encoder
*encoder
=
5277 to_intel_encoder(old_conn_state
->best_encoder
);
5279 if (old_conn_state
->crtc
!= crtc
)
5282 if (encoder
->post_pll_disable
)
5283 encoder
->post_pll_disable(encoder
, old_crtc_state
, old_conn_state
);
5287 static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config
,
5288 struct drm_atomic_state
*old_state
)
5290 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5291 struct drm_device
*dev
= crtc
->dev
;
5292 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5293 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5294 int pipe
= intel_crtc
->pipe
;
5295 struct intel_atomic_state
*old_intel_state
=
5296 to_intel_atomic_state(old_state
);
5298 if (WARN_ON(intel_crtc
->active
))
5302 * Sometimes spurious CPU pipe underruns happen during FDI
5303 * training, at least with VGA+HDMI cloning. Suppress them.
5305 * On ILK we get an occasional spurious CPU pipe underruns
5306 * between eDP port A enable and vdd enable. Also PCH port
5307 * enable seems to result in the occasional CPU pipe underrun.
5309 * Spurious PCH underruns also occur during PCH enabling.
5311 if (intel_crtc
->config
->has_pch_encoder
|| IS_GEN5(dev_priv
))
5312 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5313 if (intel_crtc
->config
->has_pch_encoder
)
5314 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5316 if (intel_crtc
->config
->has_pch_encoder
)
5317 intel_prepare_shared_dpll(intel_crtc
);
5319 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5320 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5322 intel_set_pipe_timings(intel_crtc
);
5323 intel_set_pipe_src_size(intel_crtc
);
5325 if (intel_crtc
->config
->has_pch_encoder
) {
5326 intel_cpu_transcoder_set_m_n(intel_crtc
,
5327 &intel_crtc
->config
->fdi_m_n
, NULL
);
5330 ironlake_set_pipeconf(crtc
);
5332 intel_crtc
->active
= true;
5334 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5336 if (intel_crtc
->config
->has_pch_encoder
) {
5337 /* Note: FDI PLL enabling _must_ be done before we enable the
5338 * cpu pipes, hence this is separate from all the other fdi/pch
5340 ironlake_fdi_pll_enable(intel_crtc
);
5342 assert_fdi_tx_disabled(dev_priv
, pipe
);
5343 assert_fdi_rx_disabled(dev_priv
, pipe
);
5346 ironlake_pfit_enable(intel_crtc
);
5349 * On ILK+ LUT must be loaded before the pipe is running but with
5352 intel_color_load_luts(&pipe_config
->base
);
5354 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5355 dev_priv
->display
.initial_watermarks(old_intel_state
, intel_crtc
->config
);
5356 intel_enable_pipe(intel_crtc
);
5358 if (intel_crtc
->config
->has_pch_encoder
)
5359 ironlake_pch_enable(crtc
);
5361 assert_vblank_disabled(crtc
);
5362 drm_crtc_vblank_on(crtc
);
5364 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5366 if (HAS_PCH_CPT(dev_priv
))
5367 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
5369 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5370 if (intel_crtc
->config
->has_pch_encoder
)
5371 intel_wait_for_vblank(dev_priv
, pipe
);
5372 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5373 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5376 /* IPS only exists on ULT machines and is tied to pipe A. */
5377 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
5379 return HAS_IPS(to_i915(crtc
->base
.dev
)) && crtc
->pipe
== PIPE_A
;
5382 static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config
,
5383 struct drm_atomic_state
*old_state
)
5385 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
5386 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5387 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5388 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
5389 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5390 struct intel_atomic_state
*old_intel_state
=
5391 to_intel_atomic_state(old_state
);
5393 if (WARN_ON(intel_crtc
->active
))
5396 if (intel_crtc
->config
->has_pch_encoder
)
5397 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5400 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
5402 if (intel_crtc
->config
->shared_dpll
)
5403 intel_enable_shared_dpll(intel_crtc
);
5405 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
5406 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5408 if (!transcoder_is_dsi(cpu_transcoder
))
5409 intel_set_pipe_timings(intel_crtc
);
5411 intel_set_pipe_src_size(intel_crtc
);
5413 if (cpu_transcoder
!= TRANSCODER_EDP
&&
5414 !transcoder_is_dsi(cpu_transcoder
)) {
5415 I915_WRITE(PIPE_MULT(cpu_transcoder
),
5416 intel_crtc
->config
->pixel_multiplier
- 1);
5419 if (intel_crtc
->config
->has_pch_encoder
) {
5420 intel_cpu_transcoder_set_m_n(intel_crtc
,
5421 &intel_crtc
->config
->fdi_m_n
, NULL
);
5424 if (!transcoder_is_dsi(cpu_transcoder
))
5425 haswell_set_pipeconf(crtc
);
5427 haswell_set_pipemisc(crtc
);
5429 intel_color_set_csc(&pipe_config
->base
);
5431 intel_crtc
->active
= true;
5433 if (intel_crtc
->config
->has_pch_encoder
)
5434 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5436 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5438 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
5440 if (intel_crtc
->config
->has_pch_encoder
)
5441 dev_priv
->display
.fdi_link_train(crtc
);
5443 if (!transcoder_is_dsi(cpu_transcoder
))
5444 intel_ddi_enable_pipe_clock(intel_crtc
);
5446 if (INTEL_GEN(dev_priv
) >= 9)
5447 skylake_pfit_enable(intel_crtc
);
5449 ironlake_pfit_enable(intel_crtc
);
5452 * On ILK+ LUT must be loaded before the pipe is running but with
5455 intel_color_load_luts(&pipe_config
->base
);
5457 intel_ddi_set_pipe_settings(crtc
);
5458 if (!transcoder_is_dsi(cpu_transcoder
))
5459 intel_ddi_enable_transcoder_func(crtc
);
5461 if (dev_priv
->display
.initial_watermarks
!= NULL
)
5462 dev_priv
->display
.initial_watermarks(old_intel_state
, pipe_config
);
5464 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5465 if (!transcoder_is_dsi(cpu_transcoder
))
5466 intel_enable_pipe(intel_crtc
);
5468 if (intel_crtc
->config
->has_pch_encoder
)
5469 lpt_pch_enable(crtc
);
5471 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DP_MST
))
5472 intel_ddi_set_vc_payload_alloc(crtc
, true);
5474 assert_vblank_disabled(crtc
);
5475 drm_crtc_vblank_on(crtc
);
5477 intel_encoders_enable(crtc
, pipe_config
, old_state
);
5479 if (intel_crtc
->config
->has_pch_encoder
) {
5480 intel_wait_for_vblank(dev_priv
, pipe
);
5481 intel_wait_for_vblank(dev_priv
, pipe
);
5482 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5483 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5487 /* If we change the relative order between pipe/planes enabling, we need
5488 * to change the workaround. */
5489 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
5490 if (IS_HASWELL(dev_priv
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
5491 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
5492 intel_wait_for_vblank(dev_priv
, hsw_workaround_pipe
);
5496 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
5498 struct drm_device
*dev
= crtc
->base
.dev
;
5499 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5500 int pipe
= crtc
->pipe
;
5502 /* To avoid upsetting the power well on haswell only disable the pfit if
5503 * it's in use. The hw state code will make sure we get this right. */
5504 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
5505 I915_WRITE(PF_CTL(pipe
), 0);
5506 I915_WRITE(PF_WIN_POS(pipe
), 0);
5507 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5511 static void ironlake_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
5512 struct drm_atomic_state
*old_state
)
5514 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
5515 struct drm_device
*dev
= crtc
->dev
;
5516 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5517 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5518 int pipe
= intel_crtc
->pipe
;
5521 * Sometimes spurious CPU pipe underruns happen when the
5522 * pipe is already disabled, but FDI RX/TX is still enabled.
5523 * Happens at least with VGA+HDMI cloning. Suppress them.
5525 if (intel_crtc
->config
->has_pch_encoder
) {
5526 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5527 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5530 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
5532 drm_crtc_vblank_off(crtc
);
5533 assert_vblank_disabled(crtc
);
5535 intel_disable_pipe(intel_crtc
);
5537 ironlake_pfit_disable(intel_crtc
, false);
5539 if (intel_crtc
->config
->has_pch_encoder
)
5540 ironlake_fdi_disable(crtc
);
5542 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
5544 if (intel_crtc
->config
->has_pch_encoder
) {
5545 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5547 if (HAS_PCH_CPT(dev_priv
)) {
5551 /* disable TRANS_DP_CTL */
5552 reg
= TRANS_DP_CTL(pipe
);
5553 temp
= I915_READ(reg
);
5554 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5555 TRANS_DP_PORT_SEL_MASK
);
5556 temp
|= TRANS_DP_PORT_SEL_NONE
;
5557 I915_WRITE(reg
, temp
);
5559 /* disable DPLL_SEL */
5560 temp
= I915_READ(PCH_DPLL_SEL
);
5561 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5562 I915_WRITE(PCH_DPLL_SEL
, temp
);
5565 ironlake_fdi_pll_disable(intel_crtc
);
5568 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5569 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
5572 static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
5573 struct drm_atomic_state
*old_state
)
5575 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
5576 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5577 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5578 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5580 if (intel_crtc
->config
->has_pch_encoder
)
5581 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5584 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
5586 drm_crtc_vblank_off(crtc
);
5587 assert_vblank_disabled(crtc
);
5589 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5590 if (!transcoder_is_dsi(cpu_transcoder
))
5591 intel_disable_pipe(intel_crtc
);
5593 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DP_MST
))
5594 intel_ddi_set_vc_payload_alloc(crtc
, false);
5596 if (!transcoder_is_dsi(cpu_transcoder
))
5597 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5599 if (INTEL_GEN(dev_priv
) >= 9)
5600 skylake_scaler_disable(intel_crtc
);
5602 ironlake_pfit_disable(intel_crtc
, false);
5604 if (!transcoder_is_dsi(cpu_transcoder
))
5605 intel_ddi_disable_pipe_clock(intel_crtc
);
5607 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
5609 if (old_crtc_state
->has_pch_encoder
)
5610 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5614 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5616 struct drm_device
*dev
= crtc
->base
.dev
;
5617 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5618 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5620 if (!pipe_config
->gmch_pfit
.control
)
5624 * The panel fitter should only be adjusted whilst the pipe is disabled,
5625 * according to register description and PRM.
5627 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5628 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5630 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5631 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5633 /* Border color in case we don't scale up to the full screen. Black by
5634 * default, change to something else for debugging. */
5635 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5638 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5642 return POWER_DOMAIN_PORT_DDI_A_LANES
;
5644 return POWER_DOMAIN_PORT_DDI_B_LANES
;
5646 return POWER_DOMAIN_PORT_DDI_C_LANES
;
5648 return POWER_DOMAIN_PORT_DDI_D_LANES
;
5650 return POWER_DOMAIN_PORT_DDI_E_LANES
;
5653 return POWER_DOMAIN_PORT_OTHER
;
5657 static enum intel_display_power_domain
port_to_aux_power_domain(enum port port
)
5661 return POWER_DOMAIN_AUX_A
;
5663 return POWER_DOMAIN_AUX_B
;
5665 return POWER_DOMAIN_AUX_C
;
5667 return POWER_DOMAIN_AUX_D
;
5669 /* FIXME: Check VBT for actual wiring of PORT E */
5670 return POWER_DOMAIN_AUX_D
;
5673 return POWER_DOMAIN_AUX_A
;
5677 enum intel_display_power_domain
5678 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5680 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
5681 struct intel_digital_port
*intel_dig_port
;
5683 switch (intel_encoder
->type
) {
5684 case INTEL_OUTPUT_UNKNOWN
:
5685 /* Only DDI platforms should ever use this output type */
5686 WARN_ON_ONCE(!HAS_DDI(dev_priv
));
5687 case INTEL_OUTPUT_DP
:
5688 case INTEL_OUTPUT_HDMI
:
5689 case INTEL_OUTPUT_EDP
:
5690 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5691 return port_to_power_domain(intel_dig_port
->port
);
5692 case INTEL_OUTPUT_DP_MST
:
5693 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5694 return port_to_power_domain(intel_dig_port
->port
);
5695 case INTEL_OUTPUT_ANALOG
:
5696 return POWER_DOMAIN_PORT_CRT
;
5697 case INTEL_OUTPUT_DSI
:
5698 return POWER_DOMAIN_PORT_DSI
;
5700 return POWER_DOMAIN_PORT_OTHER
;
5704 enum intel_display_power_domain
5705 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
)
5707 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
5708 struct intel_digital_port
*intel_dig_port
;
5710 switch (intel_encoder
->type
) {
5711 case INTEL_OUTPUT_UNKNOWN
:
5712 case INTEL_OUTPUT_HDMI
:
5714 * Only DDI platforms should ever use these output types.
5715 * We can get here after the HDMI detect code has already set
5716 * the type of the shared encoder. Since we can't be sure
5717 * what's the status of the given connectors, play safe and
5718 * run the DP detection too.
5720 WARN_ON_ONCE(!HAS_DDI(dev_priv
));
5721 case INTEL_OUTPUT_DP
:
5722 case INTEL_OUTPUT_EDP
:
5723 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5724 return port_to_aux_power_domain(intel_dig_port
->port
);
5725 case INTEL_OUTPUT_DP_MST
:
5726 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5727 return port_to_aux_power_domain(intel_dig_port
->port
);
5729 MISSING_CASE(intel_encoder
->type
);
5730 return POWER_DOMAIN_AUX_A
;
5734 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
,
5735 struct intel_crtc_state
*crtc_state
)
5737 struct drm_device
*dev
= crtc
->dev
;
5738 struct drm_encoder
*encoder
;
5739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5740 enum pipe pipe
= intel_crtc
->pipe
;
5742 enum transcoder transcoder
= crtc_state
->cpu_transcoder
;
5744 if (!crtc_state
->base
.active
)
5747 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5748 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5749 if (crtc_state
->pch_pfit
.enabled
||
5750 crtc_state
->pch_pfit
.force_thru
)
5751 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5753 drm_for_each_encoder_mask(encoder
, dev
, crtc_state
->base
.encoder_mask
) {
5754 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5756 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5759 if (crtc_state
->shared_dpll
)
5760 mask
|= BIT(POWER_DOMAIN_PLLS
);
5765 static unsigned long
5766 modeset_get_crtc_power_domains(struct drm_crtc
*crtc
,
5767 struct intel_crtc_state
*crtc_state
)
5769 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
5770 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5771 enum intel_display_power_domain domain
;
5772 unsigned long domains
, new_domains
, old_domains
;
5774 old_domains
= intel_crtc
->enabled_power_domains
;
5775 intel_crtc
->enabled_power_domains
= new_domains
=
5776 get_crtc_power_domains(crtc
, crtc_state
);
5778 domains
= new_domains
& ~old_domains
;
5780 for_each_power_domain(domain
, domains
)
5781 intel_display_power_get(dev_priv
, domain
);
5783 return old_domains
& ~new_domains
;
5786 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5787 unsigned long domains
)
5789 enum intel_display_power_domain domain
;
5791 for_each_power_domain(domain
, domains
)
5792 intel_display_power_put(dev_priv
, domain
);
5795 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
5797 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
5799 if (IS_GEMINILAKE(dev_priv
))
5800 return 2 * max_cdclk_freq
;
5801 else if (INTEL_INFO(dev_priv
)->gen
>= 9 ||
5802 IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5803 return max_cdclk_freq
;
5804 else if (IS_CHERRYVIEW(dev_priv
))
5805 return max_cdclk_freq
*95/100;
5806 else if (INTEL_INFO(dev_priv
)->gen
< 4)
5807 return 2*max_cdclk_freq
*90/100;
5809 return max_cdclk_freq
*90/100;
5812 static int skl_calc_cdclk(int max_pixclk
, int vco
);
5814 static void intel_update_max_cdclk(struct drm_i915_private
*dev_priv
)
5816 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5817 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5820 vco
= dev_priv
->skl_preferred_vco_freq
;
5821 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
5824 * Use the lower (vco 8640) cdclk values as a
5825 * first guess. skl_calc_cdclk() will correct it
5826 * if the preferred vco is 8100 instead.
5828 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5830 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5832 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5837 dev_priv
->max_cdclk_freq
= skl_calc_cdclk(max_cdclk
, vco
);
5838 } else if (IS_GEMINILAKE(dev_priv
)) {
5839 dev_priv
->max_cdclk_freq
= 316800;
5840 } else if (IS_BROXTON(dev_priv
)) {
5841 dev_priv
->max_cdclk_freq
= 624000;
5842 } else if (IS_BROADWELL(dev_priv
)) {
5844 * FIXME with extra cooling we can allow
5845 * 540 MHz for ULX and 675 Mhz for ULT.
5846 * How can we know if extra cooling is
5847 * available? PCI ID, VTB, something else?
5849 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5850 dev_priv
->max_cdclk_freq
= 450000;
5851 else if (IS_BDW_ULX(dev_priv
))
5852 dev_priv
->max_cdclk_freq
= 450000;
5853 else if (IS_BDW_ULT(dev_priv
))
5854 dev_priv
->max_cdclk_freq
= 540000;
5856 dev_priv
->max_cdclk_freq
= 675000;
5857 } else if (IS_CHERRYVIEW(dev_priv
)) {
5858 dev_priv
->max_cdclk_freq
= 320000;
5859 } else if (IS_VALLEYVIEW(dev_priv
)) {
5860 dev_priv
->max_cdclk_freq
= 400000;
5862 /* otherwise assume cdclk is fixed */
5863 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5866 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
5868 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5869 dev_priv
->max_cdclk_freq
);
5871 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5872 dev_priv
->max_dotclk_freq
);
5875 static void intel_update_cdclk(struct drm_i915_private
*dev_priv
)
5877 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev_priv
);
5879 if (INTEL_GEN(dev_priv
) >= 9)
5880 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5881 dev_priv
->cdclk_freq
, dev_priv
->cdclk_pll
.vco
,
5882 dev_priv
->cdclk_pll
.ref
);
5884 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5885 dev_priv
->cdclk_freq
);
5888 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5889 * Programmng [sic] note: bit[9:2] should be programmed to the number
5890 * of cdclk that generates 4MHz reference clock freq which is used to
5891 * generate GMBus clock. This will vary with the cdclk freq.
5893 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5894 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5897 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5898 static int skl_cdclk_decimal(int cdclk
)
5900 return DIV_ROUND_CLOSEST(cdclk
- 1000, 500);
5903 static int bxt_de_pll_vco(struct drm_i915_private
*dev_priv
, int cdclk
)
5907 if (cdclk
== dev_priv
->cdclk_pll
.ref
)
5912 MISSING_CASE(cdclk
);
5924 return dev_priv
->cdclk_pll
.ref
* ratio
;
5927 static int glk_de_pll_vco(struct drm_i915_private
*dev_priv
, int cdclk
)
5931 if (cdclk
== dev_priv
->cdclk_pll
.ref
)
5936 MISSING_CASE(cdclk
);
5944 return dev_priv
->cdclk_pll
.ref
* ratio
;
5947 static void bxt_de_pll_disable(struct drm_i915_private
*dev_priv
)
5949 I915_WRITE(BXT_DE_PLL_ENABLE
, 0);
5952 if (intel_wait_for_register(dev_priv
,
5953 BXT_DE_PLL_ENABLE
, BXT_DE_PLL_LOCK
, 0,
5955 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5957 dev_priv
->cdclk_pll
.vco
= 0;
5960 static void bxt_de_pll_enable(struct drm_i915_private
*dev_priv
, int vco
)
5962 int ratio
= DIV_ROUND_CLOSEST(vco
, dev_priv
->cdclk_pll
.ref
);
5965 val
= I915_READ(BXT_DE_PLL_CTL
);
5966 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5967 val
|= BXT_DE_PLL_RATIO(ratio
);
5968 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5970 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5973 if (intel_wait_for_register(dev_priv
,
5978 DRM_ERROR("timeout waiting for DE PLL lock\n");
5980 dev_priv
->cdclk_pll
.vco
= vco
;
5983 static void bxt_set_cdclk(struct drm_i915_private
*dev_priv
, int cdclk
)
5988 if (IS_GEMINILAKE(dev_priv
))
5989 vco
= glk_de_pll_vco(dev_priv
, cdclk
);
5991 vco
= bxt_de_pll_vco(dev_priv
, cdclk
);
5993 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk
, vco
);
5995 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5996 switch (DIV_ROUND_CLOSEST(vco
, cdclk
)) {
5998 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
6001 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
6004 WARN(IS_GEMINILAKE(dev_priv
), "Unsupported divider\n");
6005 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
6008 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
6011 WARN_ON(cdclk
!= dev_priv
->cdclk_pll
.ref
);
6014 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
6018 /* Inform power controller of upcoming frequency change */
6019 mutex_lock(&dev_priv
->rps
.hw_lock
);
6020 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
6022 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6025 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6030 if (dev_priv
->cdclk_pll
.vco
!= 0 &&
6031 dev_priv
->cdclk_pll
.vco
!= vco
)
6032 bxt_de_pll_disable(dev_priv
);
6034 if (dev_priv
->cdclk_pll
.vco
!= vco
)
6035 bxt_de_pll_enable(dev_priv
, vco
);
6037 val
= divider
| skl_cdclk_decimal(cdclk
);
6039 * FIXME if only the cd2x divider needs changing, it could be done
6040 * without shutting off the pipe (if only one pipe is active).
6042 val
|= BXT_CDCLK_CD2X_PIPE_NONE
;
6044 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6047 if (cdclk
>= 500000)
6048 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
6049 I915_WRITE(CDCLK_CTL
, val
);
6051 mutex_lock(&dev_priv
->rps
.hw_lock
);
6052 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
6053 DIV_ROUND_UP(cdclk
, 25000));
6054 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6057 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6062 intel_update_cdclk(dev_priv
);
6065 static void bxt_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
6067 u32 cdctl
, expected
;
6069 intel_update_cdclk(dev_priv
);
6071 if (dev_priv
->cdclk_pll
.vco
== 0 ||
6072 dev_priv
->cdclk_freq
== dev_priv
->cdclk_pll
.ref
)
6075 /* DPLL okay; verify the cdclock
6077 * Some BIOS versions leave an incorrect decimal frequency value and
6078 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6079 * so sanitize this register.
6081 cdctl
= I915_READ(CDCLK_CTL
);
6083 * Let's ignore the pipe field, since BIOS could have configured the
6084 * dividers both synching to an active pipe, or asynchronously
6087 cdctl
&= ~BXT_CDCLK_CD2X_PIPE_NONE
;
6089 expected
= (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) |
6090 skl_cdclk_decimal(dev_priv
->cdclk_freq
);
6092 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6095 if (dev_priv
->cdclk_freq
>= 500000)
6096 expected
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
6098 if (cdctl
== expected
)
6099 /* All well; nothing to sanitize */
6103 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6105 /* force cdclk programming */
6106 dev_priv
->cdclk_freq
= 0;
6108 /* force full PLL disable + enable */
6109 dev_priv
->cdclk_pll
.vco
= -1;
6112 void bxt_init_cdclk(struct drm_i915_private
*dev_priv
)
6116 bxt_sanitize_cdclk(dev_priv
);
6118 if (dev_priv
->cdclk_freq
!= 0 && dev_priv
->cdclk_pll
.vco
!= 0)
6123 * - The initial CDCLK needs to be read from VBT.
6124 * Need to make this change after VBT has changes for BXT.
6126 if (IS_GEMINILAKE(dev_priv
))
6127 cdclk
= glk_calc_cdclk(0);
6129 cdclk
= bxt_calc_cdclk(0);
6131 bxt_set_cdclk(dev_priv
, cdclk
);
6134 void bxt_uninit_cdclk(struct drm_i915_private
*dev_priv
)
6136 bxt_set_cdclk(dev_priv
, dev_priv
->cdclk_pll
.ref
);
6139 static int skl_calc_cdclk(int max_pixclk
, int vco
)
6141 if (vco
== 8640000) {
6142 if (max_pixclk
> 540000)
6144 else if (max_pixclk
> 432000)
6146 else if (max_pixclk
> 308571)
6151 if (max_pixclk
> 540000)
6153 else if (max_pixclk
> 450000)
6155 else if (max_pixclk
> 337500)
6163 skl_dpll0_update(struct drm_i915_private
*dev_priv
)
6167 dev_priv
->cdclk_pll
.ref
= 24000;
6168 dev_priv
->cdclk_pll
.vco
= 0;
6170 val
= I915_READ(LCPLL1_CTL
);
6171 if ((val
& LCPLL_PLL_ENABLE
) == 0)
6174 if (WARN_ON((val
& LCPLL_PLL_LOCK
) == 0))
6177 val
= I915_READ(DPLL_CTRL1
);
6179 if (WARN_ON((val
& (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) |
6180 DPLL_CTRL1_SSC(SKL_DPLL0
) |
6181 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
))) !=
6182 DPLL_CTRL1_OVERRIDE(SKL_DPLL0
)))
6185 switch (val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) {
6186 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
, SKL_DPLL0
):
6187 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
, SKL_DPLL0
):
6188 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
, SKL_DPLL0
):
6189 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
, SKL_DPLL0
):
6190 dev_priv
->cdclk_pll
.vco
= 8100000;
6192 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
, SKL_DPLL0
):
6193 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
, SKL_DPLL0
):
6194 dev_priv
->cdclk_pll
.vco
= 8640000;
6197 MISSING_CASE(val
& DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
6202 void skl_set_preferred_cdclk_vco(struct drm_i915_private
*dev_priv
, int vco
)
6204 bool changed
= dev_priv
->skl_preferred_vco_freq
!= vco
;
6206 dev_priv
->skl_preferred_vco_freq
= vco
;
6209 intel_update_max_cdclk(dev_priv
);
6213 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, int vco
)
6215 int min_cdclk
= skl_calc_cdclk(0, vco
);
6218 WARN_ON(vco
!= 8100000 && vco
!= 8640000);
6220 /* select the minimum CDCLK before enabling DPLL 0 */
6221 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_cdclk
);
6222 I915_WRITE(CDCLK_CTL
, val
);
6223 POSTING_READ(CDCLK_CTL
);
6226 * We always enable DPLL0 with the lowest link rate possible, but still
6227 * taking into account the VCO required to operate the eDP panel at the
6228 * desired frequency. The usual DP link rates operate with a VCO of
6229 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6230 * The modeset code is responsible for the selection of the exact link
6231 * rate later on, with the constraint of choosing a frequency that
6234 val
= I915_READ(DPLL_CTRL1
);
6236 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
6237 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
6238 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
6240 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
6243 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
6246 I915_WRITE(DPLL_CTRL1
, val
);
6247 POSTING_READ(DPLL_CTRL1
);
6249 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
6251 if (intel_wait_for_register(dev_priv
,
6252 LCPLL1_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
6254 DRM_ERROR("DPLL0 not locked\n");
6256 dev_priv
->cdclk_pll
.vco
= vco
;
6258 /* We'll want to keep using the current vco from now on. */
6259 skl_set_preferred_cdclk_vco(dev_priv
, vco
);
6263 skl_dpll0_disable(struct drm_i915_private
*dev_priv
)
6265 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
6266 if (intel_wait_for_register(dev_priv
,
6267 LCPLL1_CTL
, LCPLL_PLL_LOCK
, 0,
6269 DRM_ERROR("Couldn't disable DPLL0\n");
6271 dev_priv
->cdclk_pll
.vco
= 0;
6274 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
6279 /* inform PCU we want to change CDCLK */
6280 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
6281 mutex_lock(&dev_priv
->rps
.hw_lock
);
6282 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
6283 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6285 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
6288 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
6290 return _wait_for(skl_cdclk_pcu_ready(dev_priv
), 3000, 10) == 0;
6293 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, int cdclk
, int vco
)
6295 u32 freq_select
, pcu_ack
;
6297 WARN_ON((cdclk
== 24000) != (vco
== 0));
6299 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk
, vco
);
6301 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
6302 DRM_ERROR("failed to inform PCU about cdclk change\n");
6310 freq_select
= CDCLK_FREQ_450_432
;
6314 freq_select
= CDCLK_FREQ_540
;
6320 freq_select
= CDCLK_FREQ_337_308
;
6325 freq_select
= CDCLK_FREQ_675_617
;
6330 if (dev_priv
->cdclk_pll
.vco
!= 0 &&
6331 dev_priv
->cdclk_pll
.vco
!= vco
)
6332 skl_dpll0_disable(dev_priv
);
6334 if (dev_priv
->cdclk_pll
.vco
!= vco
)
6335 skl_dpll0_enable(dev_priv
, vco
);
6337 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(cdclk
));
6338 POSTING_READ(CDCLK_CTL
);
6340 /* inform PCU of the change */
6341 mutex_lock(&dev_priv
->rps
.hw_lock
);
6342 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
6343 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6345 intel_update_cdclk(dev_priv
);
6348 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
);
6350 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
6352 skl_set_cdclk(dev_priv
, dev_priv
->cdclk_pll
.ref
, 0);
6355 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
6359 skl_sanitize_cdclk(dev_priv
);
6361 if (dev_priv
->cdclk_freq
!= 0 && dev_priv
->cdclk_pll
.vco
!= 0) {
6363 * Use the current vco as our initial
6364 * guess as to what the preferred vco is.
6366 if (dev_priv
->skl_preferred_vco_freq
== 0)
6367 skl_set_preferred_cdclk_vco(dev_priv
,
6368 dev_priv
->cdclk_pll
.vco
);
6372 vco
= dev_priv
->skl_preferred_vco_freq
;
6375 cdclk
= skl_calc_cdclk(0, vco
);
6377 skl_set_cdclk(dev_priv
, cdclk
, vco
);
6380 static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
)
6382 uint32_t cdctl
, expected
;
6385 * check if the pre-os intialized the display
6386 * There is SWF18 scratchpad register defined which is set by the
6387 * pre-os which can be used by the OS drivers to check the status
6389 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6392 intel_update_cdclk(dev_priv
);
6393 /* Is PLL enabled and locked ? */
6394 if (dev_priv
->cdclk_pll
.vco
== 0 ||
6395 dev_priv
->cdclk_freq
== dev_priv
->cdclk_pll
.ref
)
6398 /* DPLL okay; verify the cdclock
6400 * Noticed in some instances that the freq selection is correct but
6401 * decimal part is programmed wrong from BIOS where pre-os does not
6402 * enable display. Verify the same as well.
6404 cdctl
= I915_READ(CDCLK_CTL
);
6405 expected
= (cdctl
& CDCLK_FREQ_SEL_MASK
) |
6406 skl_cdclk_decimal(dev_priv
->cdclk_freq
);
6407 if (cdctl
== expected
)
6408 /* All well; nothing to sanitize */
6412 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6414 /* force cdclk programming */
6415 dev_priv
->cdclk_freq
= 0;
6416 /* force full PLL disable + enable */
6417 dev_priv
->cdclk_pll
.vco
= -1;
6420 /* Adjust CDclk dividers to allow high res or save power if possible */
6421 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
6423 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6426 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev_priv
)
6427 != dev_priv
->cdclk_freq
);
6429 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
6431 else if (cdclk
== 266667)
6436 mutex_lock(&dev_priv
->rps
.hw_lock
);
6437 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
6438 val
&= ~DSPFREQGUAR_MASK
;
6439 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
6440 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
6441 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
6442 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
6444 DRM_ERROR("timed out waiting for CDclk change\n");
6446 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6448 mutex_lock(&dev_priv
->sb_lock
);
6450 if (cdclk
== 400000) {
6453 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
6455 /* adjust cdclk divider */
6456 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6457 val
&= ~CCK_FREQUENCY_VALUES
;
6459 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
6461 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
6462 CCK_FREQUENCY_STATUS
) == (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
6464 DRM_ERROR("timed out waiting for CDclk change\n");
6467 /* adjust self-refresh exit latency value */
6468 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
6472 * For high bandwidth configs, we set a higher latency in the bunit
6473 * so that the core display fetch happens in time to avoid underruns.
6475 if (cdclk
== 400000)
6476 val
|= 4500 / 250; /* 4.5 usec */
6478 val
|= 3000 / 250; /* 3.0 usec */
6479 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
6481 mutex_unlock(&dev_priv
->sb_lock
);
6483 intel_update_cdclk(dev_priv
);
6486 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
6488 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6491 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev_priv
)
6492 != dev_priv
->cdclk_freq
);
6501 MISSING_CASE(cdclk
);
6506 * Specs are full of misinformation, but testing on actual
6507 * hardware has shown that we just need to write the desired
6508 * CCK divider into the Punit register.
6510 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
6512 mutex_lock(&dev_priv
->rps
.hw_lock
);
6513 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
6514 val
&= ~DSPFREQGUAR_MASK_CHV
;
6515 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
6516 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
6517 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
6518 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
6520 DRM_ERROR("timed out waiting for CDclk change\n");
6522 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6524 intel_update_cdclk(dev_priv
);
6527 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
6530 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
6531 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
6534 * Really only a few cases to deal with, as only 4 CDclks are supported:
6537 * 320/333MHz (depends on HPLL freq)
6539 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6540 * of the lower bin and adjust if needed.
6542 * We seem to get an unstable or solid color picture at 200MHz.
6543 * Not sure what's wrong. For now use 200MHz only when all pipes
6546 if (!IS_CHERRYVIEW(dev_priv
) &&
6547 max_pixclk
> freq_320
*limit
/100)
6549 else if (max_pixclk
> 266667*limit
/100)
6551 else if (max_pixclk
> 0)
6557 static int glk_calc_cdclk(int max_pixclk
)
6559 if (max_pixclk
> 2 * 158400)
6561 else if (max_pixclk
> 2 * 79200)
6567 static int bxt_calc_cdclk(int max_pixclk
)
6569 if (max_pixclk
> 576000)
6571 else if (max_pixclk
> 384000)
6573 else if (max_pixclk
> 288000)
6575 else if (max_pixclk
> 144000)
6581 /* Compute the max pixel clock for new configuration. */
6582 static int intel_mode_max_pixclk(struct drm_device
*dev
,
6583 struct drm_atomic_state
*state
)
6585 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
6586 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6587 struct drm_crtc
*crtc
;
6588 struct drm_crtc_state
*crtc_state
;
6589 unsigned max_pixclk
= 0, i
;
6592 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
6593 sizeof(intel_state
->min_pixclk
));
6595 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
6598 if (crtc_state
->enable
)
6599 pixclk
= crtc_state
->adjusted_mode
.crtc_clock
;
6601 intel_state
->min_pixclk
[i
] = pixclk
;
6604 for_each_pipe(dev_priv
, pipe
)
6605 max_pixclk
= max(intel_state
->min_pixclk
[pipe
], max_pixclk
);
6610 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6612 struct drm_device
*dev
= state
->dev
;
6613 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6614 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
6615 struct intel_atomic_state
*intel_state
=
6616 to_intel_atomic_state(state
);
6618 intel_state
->cdclk
= intel_state
->dev_cdclk
=
6619 valleyview_calc_cdclk(dev_priv
, max_pixclk
);
6621 if (!intel_state
->active_crtcs
)
6622 intel_state
->dev_cdclk
= valleyview_calc_cdclk(dev_priv
, 0);
6627 static int bxt_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6629 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
6630 int max_pixclk
= ilk_max_pixel_rate(state
);
6631 struct intel_atomic_state
*intel_state
=
6632 to_intel_atomic_state(state
);
6635 if (IS_GEMINILAKE(dev_priv
))
6636 cdclk
= glk_calc_cdclk(max_pixclk
);
6638 cdclk
= bxt_calc_cdclk(max_pixclk
);
6640 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
6642 if (!intel_state
->active_crtcs
) {
6643 if (IS_GEMINILAKE(dev_priv
))
6644 cdclk
= glk_calc_cdclk(0);
6646 cdclk
= bxt_calc_cdclk(0);
6648 intel_state
->dev_cdclk
= cdclk
;
6654 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
6656 unsigned int credits
, default_credits
;
6658 if (IS_CHERRYVIEW(dev_priv
))
6659 default_credits
= PFI_CREDIT(12);
6661 default_credits
= PFI_CREDIT(8);
6663 if (dev_priv
->cdclk_freq
>= dev_priv
->czclk_freq
) {
6664 /* CHV suggested value is 31 or 63 */
6665 if (IS_CHERRYVIEW(dev_priv
))
6666 credits
= PFI_CREDIT_63
;
6668 credits
= PFI_CREDIT(15);
6670 credits
= default_credits
;
6674 * WA - write default credits before re-programming
6675 * FIXME: should we also set the resend bit here?
6677 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6680 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6681 credits
| PFI_CREDIT_RESEND
);
6684 * FIXME is this guaranteed to clear
6685 * immediately or should we poll for it?
6687 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6690 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
6692 struct drm_device
*dev
= old_state
->dev
;
6693 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6694 struct intel_atomic_state
*old_intel_state
=
6695 to_intel_atomic_state(old_state
);
6696 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
6699 * FIXME: We can end up here with all power domains off, yet
6700 * with a CDCLK frequency other than the minimum. To account
6701 * for this take the PIPE-A power domain, which covers the HW
6702 * blocks needed for the following programming. This can be
6703 * removed once it's guaranteed that we get here either with
6704 * the minimum CDCLK set, or the required power domains
6707 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6709 if (IS_CHERRYVIEW(dev_priv
))
6710 cherryview_set_cdclk(dev
, req_cdclk
);
6712 valleyview_set_cdclk(dev
, req_cdclk
);
6714 vlv_program_pfi_credits(dev_priv
);
6716 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6719 static void valleyview_crtc_enable(struct intel_crtc_state
*pipe_config
,
6720 struct drm_atomic_state
*old_state
)
6722 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6723 struct drm_device
*dev
= crtc
->dev
;
6724 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6725 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6726 int pipe
= intel_crtc
->pipe
;
6728 if (WARN_ON(intel_crtc
->active
))
6731 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
6732 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6734 intel_set_pipe_timings(intel_crtc
);
6735 intel_set_pipe_src_size(intel_crtc
);
6737 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
6738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6740 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6741 I915_WRITE(CHV_CANVAS(pipe
), 0);
6744 i9xx_set_pipeconf(intel_crtc
);
6746 intel_crtc
->active
= true;
6748 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6750 intel_encoders_pre_pll_enable(crtc
, pipe_config
, old_state
);
6752 if (IS_CHERRYVIEW(dev_priv
)) {
6753 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6754 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6756 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6757 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6760 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6762 i9xx_pfit_enable(intel_crtc
);
6764 intel_color_load_luts(&pipe_config
->base
);
6766 intel_update_watermarks(intel_crtc
);
6767 intel_enable_pipe(intel_crtc
);
6769 assert_vblank_disabled(crtc
);
6770 drm_crtc_vblank_on(crtc
);
6772 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6775 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6777 struct drm_device
*dev
= crtc
->base
.dev
;
6778 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6780 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6781 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6784 static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config
,
6785 struct drm_atomic_state
*old_state
)
6787 struct drm_crtc
*crtc
= pipe_config
->base
.crtc
;
6788 struct drm_device
*dev
= crtc
->dev
;
6789 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6790 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6791 enum pipe pipe
= intel_crtc
->pipe
;
6793 if (WARN_ON(intel_crtc
->active
))
6796 i9xx_set_pll_dividers(intel_crtc
);
6798 if (intel_crtc_has_dp_encoder(intel_crtc
->config
))
6799 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6801 intel_set_pipe_timings(intel_crtc
);
6802 intel_set_pipe_src_size(intel_crtc
);
6804 i9xx_set_pipeconf(intel_crtc
);
6806 intel_crtc
->active
= true;
6808 if (!IS_GEN2(dev_priv
))
6809 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6811 intel_encoders_pre_enable(crtc
, pipe_config
, old_state
);
6813 i9xx_enable_pll(intel_crtc
);
6815 i9xx_pfit_enable(intel_crtc
);
6817 intel_color_load_luts(&pipe_config
->base
);
6819 intel_update_watermarks(intel_crtc
);
6820 intel_enable_pipe(intel_crtc
);
6822 assert_vblank_disabled(crtc
);
6823 drm_crtc_vblank_on(crtc
);
6825 intel_encoders_enable(crtc
, pipe_config
, old_state
);
6828 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6830 struct drm_device
*dev
= crtc
->base
.dev
;
6831 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6833 if (!crtc
->config
->gmch_pfit
.control
)
6836 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6838 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6839 I915_READ(PFIT_CONTROL
));
6840 I915_WRITE(PFIT_CONTROL
, 0);
6843 static void i9xx_crtc_disable(struct intel_crtc_state
*old_crtc_state
,
6844 struct drm_atomic_state
*old_state
)
6846 struct drm_crtc
*crtc
= old_crtc_state
->base
.crtc
;
6847 struct drm_device
*dev
= crtc
->dev
;
6848 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6849 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6850 int pipe
= intel_crtc
->pipe
;
6853 * On gen2 planes are double buffered but the pipe isn't, so we must
6854 * wait for planes to fully turn off before disabling the pipe.
6856 if (IS_GEN2(dev_priv
))
6857 intel_wait_for_vblank(dev_priv
, pipe
);
6859 intel_encoders_disable(crtc
, old_crtc_state
, old_state
);
6861 drm_crtc_vblank_off(crtc
);
6862 assert_vblank_disabled(crtc
);
6864 intel_disable_pipe(intel_crtc
);
6866 i9xx_pfit_disable(intel_crtc
);
6868 intel_encoders_post_disable(crtc
, old_crtc_state
, old_state
);
6870 if (!intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_DSI
)) {
6871 if (IS_CHERRYVIEW(dev_priv
))
6872 chv_disable_pll(dev_priv
, pipe
);
6873 else if (IS_VALLEYVIEW(dev_priv
))
6874 vlv_disable_pll(dev_priv
, pipe
);
6876 i9xx_disable_pll(intel_crtc
);
6879 intel_encoders_post_pll_disable(crtc
, old_crtc_state
, old_state
);
6881 if (!IS_GEN2(dev_priv
))
6882 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6885 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6887 struct intel_encoder
*encoder
;
6888 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6889 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6890 enum intel_display_power_domain domain
;
6891 unsigned long domains
;
6892 struct drm_atomic_state
*state
;
6893 struct intel_crtc_state
*crtc_state
;
6896 if (!intel_crtc
->active
)
6899 if (to_intel_plane_state(crtc
->primary
->state
)->base
.visible
) {
6900 WARN_ON(intel_crtc
->flip_work
);
6902 intel_pre_disable_primary_noatomic(crtc
);
6904 intel_crtc_disable_planes(crtc
, 1 << drm_plane_index(crtc
->primary
));
6905 to_intel_plane_state(crtc
->primary
->state
)->base
.visible
= false;
6908 state
= drm_atomic_state_alloc(crtc
->dev
);
6909 state
->acquire_ctx
= crtc
->dev
->mode_config
.acquire_ctx
;
6911 /* Everything's already locked, -EDEADLK can't happen. */
6912 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
6913 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
6915 WARN_ON(IS_ERR(crtc_state
) || ret
);
6917 dev_priv
->display
.crtc_disable(crtc_state
, state
);
6919 drm_atomic_state_put(state
);
6921 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6922 crtc
->base
.id
, crtc
->name
);
6924 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->state
, NULL
) < 0);
6925 crtc
->state
->active
= false;
6926 intel_crtc
->active
= false;
6927 crtc
->enabled
= false;
6928 crtc
->state
->connector_mask
= 0;
6929 crtc
->state
->encoder_mask
= 0;
6931 for_each_encoder_on_crtc(crtc
->dev
, crtc
, encoder
)
6932 encoder
->base
.crtc
= NULL
;
6934 intel_fbc_disable(intel_crtc
);
6935 intel_update_watermarks(intel_crtc
);
6936 intel_disable_shared_dpll(intel_crtc
);
6938 domains
= intel_crtc
->enabled_power_domains
;
6939 for_each_power_domain(domain
, domains
)
6940 intel_display_power_put(dev_priv
, domain
);
6941 intel_crtc
->enabled_power_domains
= 0;
6943 dev_priv
->active_crtcs
&= ~(1 << intel_crtc
->pipe
);
6944 dev_priv
->min_pixclk
[intel_crtc
->pipe
] = 0;
6948 * turn all crtc's off, but do not adjust state
6949 * This has to be paired with a call to intel_modeset_setup_hw_state.
6951 int intel_display_suspend(struct drm_device
*dev
)
6953 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6954 struct drm_atomic_state
*state
;
6957 state
= drm_atomic_helper_suspend(dev
);
6958 ret
= PTR_ERR_OR_ZERO(state
);
6960 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6962 dev_priv
->modeset_restore_state
= state
;
6966 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6968 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6970 drm_encoder_cleanup(encoder
);
6971 kfree(intel_encoder
);
6974 /* Cross check the actual hw state with our own modeset state tracking (and it's
6975 * internal consistency). */
6976 static void intel_connector_verify_state(struct intel_connector
*connector
)
6978 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
6980 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6981 connector
->base
.base
.id
,
6982 connector
->base
.name
);
6984 if (connector
->get_hw_state(connector
)) {
6985 struct intel_encoder
*encoder
= connector
->encoder
;
6986 struct drm_connector_state
*conn_state
= connector
->base
.state
;
6988 I915_STATE_WARN(!crtc
,
6989 "connector enabled without attached crtc\n");
6994 I915_STATE_WARN(!crtc
->state
->active
,
6995 "connector is active, but attached crtc isn't\n");
6997 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
7000 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
7001 "atomic encoder doesn't match attached encoder\n");
7003 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
7004 "attached encoder crtc differs from connector crtc\n");
7006 I915_STATE_WARN(crtc
&& crtc
->state
->active
,
7007 "attached crtc is active, but connector isn't\n");
7008 I915_STATE_WARN(!crtc
&& connector
->base
.state
->best_encoder
,
7009 "best encoder set without crtc!\n");
7013 int intel_connector_init(struct intel_connector
*connector
)
7015 drm_atomic_helper_connector_reset(&connector
->base
);
7017 if (!connector
->base
.state
)
7023 struct intel_connector
*intel_connector_alloc(void)
7025 struct intel_connector
*connector
;
7027 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
7031 if (intel_connector_init(connector
) < 0) {
7039 /* Simple connector->get_hw_state implementation for encoders that support only
7040 * one connector and no cloning and hence the encoder state determines the state
7041 * of the connector. */
7042 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
7045 struct intel_encoder
*encoder
= connector
->encoder
;
7047 return encoder
->get_hw_state(encoder
, &pipe
);
7050 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
7052 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
7053 return crtc_state
->fdi_lanes
;
7058 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
7059 struct intel_crtc_state
*pipe_config
)
7061 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7062 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
7063 struct intel_crtc
*other_crtc
;
7064 struct intel_crtc_state
*other_crtc_state
;
7066 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7067 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7068 if (pipe_config
->fdi_lanes
> 4) {
7069 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7070 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7074 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
7075 if (pipe_config
->fdi_lanes
> 2) {
7076 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7077 pipe_config
->fdi_lanes
);
7084 if (INTEL_INFO(dev_priv
)->num_pipes
== 2)
7087 /* Ivybridge 3 pipe is really complicated */
7092 if (pipe_config
->fdi_lanes
<= 2)
7095 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_C
);
7097 intel_atomic_get_crtc_state(state
, other_crtc
);
7098 if (IS_ERR(other_crtc_state
))
7099 return PTR_ERR(other_crtc_state
);
7101 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
7102 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7103 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7108 if (pipe_config
->fdi_lanes
> 2) {
7109 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7110 pipe_name(pipe
), pipe_config
->fdi_lanes
);
7114 other_crtc
= intel_get_crtc_for_pipe(dev_priv
, PIPE_B
);
7116 intel_atomic_get_crtc_state(state
, other_crtc
);
7117 if (IS_ERR(other_crtc_state
))
7118 return PTR_ERR(other_crtc_state
);
7120 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
7121 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7131 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
7132 struct intel_crtc_state
*pipe_config
)
7134 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7135 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
7136 int lane
, link_bw
, fdi_dotclock
, ret
;
7137 bool needs_recompute
= false;
7140 /* FDI is a binary signal running at ~2.7GHz, encoding
7141 * each output octet as 10 bits. The actual frequency
7142 * is stored as a divider into a 100MHz clock, and the
7143 * mode pixel clock is stored in units of 1KHz.
7144 * Hence the bw of each lane in terms of the mode signal
7147 link_bw
= intel_fdi_link_freq(to_i915(dev
), pipe_config
);
7149 fdi_dotclock
= adjusted_mode
->crtc_clock
;
7151 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
7152 pipe_config
->pipe_bpp
);
7154 pipe_config
->fdi_lanes
= lane
;
7156 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
7157 link_bw
, &pipe_config
->fdi_m_n
);
7159 ret
= ironlake_check_fdi_lanes(dev
, intel_crtc
->pipe
, pipe_config
);
7160 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
7161 pipe_config
->pipe_bpp
-= 2*3;
7162 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7163 pipe_config
->pipe_bpp
);
7164 needs_recompute
= true;
7165 pipe_config
->bw_constrained
= true;
7170 if (needs_recompute
)
7176 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
7177 struct intel_crtc_state
*pipe_config
)
7179 if (pipe_config
->pipe_bpp
> 24)
7182 /* HSW can handle pixel rate up to cdclk? */
7183 if (IS_HASWELL(dev_priv
))
7187 * We compare against max which means we must take
7188 * the increased cdclk requirement into account when
7189 * calculating the new cdclk.
7191 * Should measure whether using a lower cdclk w/o IPS
7193 return ilk_pipe_pixel_rate(pipe_config
) <=
7194 dev_priv
->max_cdclk_freq
* 95 / 100;
7197 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
7198 struct intel_crtc_state
*pipe_config
)
7200 struct drm_device
*dev
= crtc
->base
.dev
;
7201 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7203 pipe_config
->ips_enabled
= i915
.enable_ips
&&
7204 hsw_crtc_supports_ips(crtc
) &&
7205 pipe_config_supports_ips(dev_priv
, pipe_config
);
7208 static bool intel_crtc_supports_double_wide(const struct intel_crtc
*crtc
)
7210 const struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7212 /* GDG double wide on either pipe, otherwise pipe A only */
7213 return INTEL_INFO(dev_priv
)->gen
< 4 &&
7214 (crtc
->pipe
== PIPE_A
|| IS_I915G(dev_priv
));
7217 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
7218 struct intel_crtc_state
*pipe_config
)
7220 struct drm_device
*dev
= crtc
->base
.dev
;
7221 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7222 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
7223 int clock_limit
= dev_priv
->max_dotclk_freq
;
7225 if (INTEL_GEN(dev_priv
) < 4) {
7226 clock_limit
= dev_priv
->max_cdclk_freq
* 9 / 10;
7229 * Enable double wide mode when the dot clock
7230 * is > 90% of the (display) core speed.
7232 if (intel_crtc_supports_double_wide(crtc
) &&
7233 adjusted_mode
->crtc_clock
> clock_limit
) {
7234 clock_limit
= dev_priv
->max_dotclk_freq
;
7235 pipe_config
->double_wide
= true;
7239 if (adjusted_mode
->crtc_clock
> clock_limit
) {
7240 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7241 adjusted_mode
->crtc_clock
, clock_limit
,
7242 yesno(pipe_config
->double_wide
));
7247 * Pipe horizontal size must be even in:
7249 * - LVDS dual channel mode
7250 * - Double wide pipe
7252 if ((intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
7253 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
7254 pipe_config
->pipe_src_w
&= ~1;
7256 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7257 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7259 if ((INTEL_GEN(dev_priv
) > 4 || IS_G4X(dev_priv
)) &&
7260 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
7263 if (HAS_IPS(dev_priv
))
7264 hsw_compute_ips_config(crtc
, pipe_config
);
7266 if (pipe_config
->has_pch_encoder
)
7267 return ironlake_fdi_compute_config(crtc
, pipe_config
);
7272 static int skylake_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7276 skl_dpll0_update(dev_priv
);
7278 if (dev_priv
->cdclk_pll
.vco
== 0)
7279 return dev_priv
->cdclk_pll
.ref
;
7281 cdctl
= I915_READ(CDCLK_CTL
);
7283 if (dev_priv
->cdclk_pll
.vco
== 8640000) {
7284 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
7285 case CDCLK_FREQ_450_432
:
7287 case CDCLK_FREQ_337_308
:
7289 case CDCLK_FREQ_540
:
7291 case CDCLK_FREQ_675_617
:
7294 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
7297 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
7298 case CDCLK_FREQ_450_432
:
7300 case CDCLK_FREQ_337_308
:
7302 case CDCLK_FREQ_540
:
7304 case CDCLK_FREQ_675_617
:
7307 MISSING_CASE(cdctl
& CDCLK_FREQ_SEL_MASK
);
7311 return dev_priv
->cdclk_pll
.ref
;
7314 static void bxt_de_pll_update(struct drm_i915_private
*dev_priv
)
7318 dev_priv
->cdclk_pll
.ref
= 19200;
7319 dev_priv
->cdclk_pll
.vco
= 0;
7321 val
= I915_READ(BXT_DE_PLL_ENABLE
);
7322 if ((val
& BXT_DE_PLL_PLL_ENABLE
) == 0)
7325 if (WARN_ON((val
& BXT_DE_PLL_LOCK
) == 0))
7328 val
= I915_READ(BXT_DE_PLL_CTL
);
7329 dev_priv
->cdclk_pll
.vco
= (val
& BXT_DE_PLL_RATIO_MASK
) *
7330 dev_priv
->cdclk_pll
.ref
;
7333 static int broxton_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7338 bxt_de_pll_update(dev_priv
);
7340 vco
= dev_priv
->cdclk_pll
.vco
;
7342 return dev_priv
->cdclk_pll
.ref
;
7344 divider
= I915_READ(CDCLK_CTL
) & BXT_CDCLK_CD2X_DIV_SEL_MASK
;
7347 case BXT_CDCLK_CD2X_DIV_SEL_1
:
7350 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
7351 WARN(IS_GEMINILAKE(dev_priv
), "Unsupported divider\n");
7354 case BXT_CDCLK_CD2X_DIV_SEL_2
:
7357 case BXT_CDCLK_CD2X_DIV_SEL_4
:
7361 MISSING_CASE(divider
);
7362 return dev_priv
->cdclk_pll
.ref
;
7365 return DIV_ROUND_CLOSEST(vco
, div
);
7368 static int broadwell_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7370 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
7371 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
7373 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
7375 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
7377 else if (freq
== LCPLL_CLK_FREQ_450
)
7379 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
7381 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
7387 static int haswell_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7389 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
7390 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
7392 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
7394 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
7396 else if (freq
== LCPLL_CLK_FREQ_450
)
7398 else if (IS_HSW_ULT(dev_priv
))
7404 static int valleyview_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7406 return vlv_get_cck_clock_hpll(dev_priv
, "cdclk",
7407 CCK_DISPLAY_CLOCK_CONTROL
);
7410 static int ilk_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7415 static int i945_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7420 static int i915_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7425 static int i9xx_misc_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7430 static int pnv_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7432 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7435 pci_read_config_word(pdev
, GCFGC
, &gcfgc
);
7437 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
7438 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
7440 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
7442 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
7444 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
7447 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
7448 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
7450 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
7455 static int i915gm_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7457 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7460 pci_read_config_word(pdev
, GCFGC
, &gcfgc
);
7462 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
7465 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
7466 case GC_DISPLAY_CLOCK_333_MHZ
:
7469 case GC_DISPLAY_CLOCK_190_200_MHZ
:
7475 static int i865_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7480 static int i85x_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7482 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7486 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7487 * encoding is different :(
7488 * FIXME is this the right way to detect 852GM/852GMV?
7490 if (pdev
->revision
== 0x1)
7493 pci_bus_read_config_word(pdev
->bus
,
7494 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
7496 /* Assume that the hardware is in the high speed state. This
7497 * should be the default.
7499 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
7500 case GC_CLOCK_133_200
:
7501 case GC_CLOCK_133_200_2
:
7502 case GC_CLOCK_100_200
:
7504 case GC_CLOCK_166_250
:
7506 case GC_CLOCK_100_133
:
7508 case GC_CLOCK_133_266
:
7509 case GC_CLOCK_133_266_2
:
7510 case GC_CLOCK_166_266
:
7514 /* Shouldn't happen */
7518 static int i830_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7523 static unsigned int intel_hpll_vco(struct drm_i915_private
*dev_priv
)
7525 static const unsigned int blb_vco
[8] = {
7532 static const unsigned int pnv_vco
[8] = {
7539 static const unsigned int cl_vco
[8] = {
7548 static const unsigned int elk_vco
[8] = {
7554 static const unsigned int ctg_vco
[8] = {
7562 const unsigned int *vco_table
;
7566 /* FIXME other chipsets? */
7567 if (IS_GM45(dev_priv
))
7568 vco_table
= ctg_vco
;
7569 else if (IS_G4X(dev_priv
))
7570 vco_table
= elk_vco
;
7571 else if (IS_I965GM(dev_priv
))
7573 else if (IS_PINEVIEW(dev_priv
))
7574 vco_table
= pnv_vco
;
7575 else if (IS_G33(dev_priv
))
7576 vco_table
= blb_vco
;
7580 tmp
= I915_READ(IS_MOBILE(dev_priv
) ? HPLLVCO_MOBILE
: HPLLVCO
);
7582 vco
= vco_table
[tmp
& 0x7];
7584 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
7586 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
7591 static int gm45_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7593 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7594 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev_priv
);
7597 pci_read_config_word(pdev
, GCFGC
, &tmp
);
7599 cdclk_sel
= (tmp
>> 12) & 0x1;
7605 return cdclk_sel
? 333333 : 222222;
7607 return cdclk_sel
? 320000 : 228571;
7609 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
7614 static int i965gm_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7616 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7617 static const uint8_t div_3200
[] = { 16, 10, 8 };
7618 static const uint8_t div_4000
[] = { 20, 12, 10 };
7619 static const uint8_t div_5333
[] = { 24, 16, 14 };
7620 const uint8_t *div_table
;
7621 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev_priv
);
7624 pci_read_config_word(pdev
, GCFGC
, &tmp
);
7626 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
7628 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7633 div_table
= div_3200
;
7636 div_table
= div_4000
;
7639 div_table
= div_5333
;
7645 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7648 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
7652 static int g33_get_display_clock_speed(struct drm_i915_private
*dev_priv
)
7654 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
7655 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
7656 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
7657 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
7658 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
7659 const uint8_t *div_table
;
7660 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev_priv
);
7663 pci_read_config_word(pdev
, GCFGC
, &tmp
);
7665 cdclk_sel
= (tmp
>> 4) & 0x7;
7667 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7672 div_table
= div_3200
;
7675 div_table
= div_4000
;
7678 div_table
= div_4800
;
7681 div_table
= div_5333
;
7687 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7690 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
7695 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
7697 while (*num
> DATA_LINK_M_N_MASK
||
7698 *den
> DATA_LINK_M_N_MASK
) {
7704 static void compute_m_n(unsigned int m
, unsigned int n
,
7705 uint32_t *ret_m
, uint32_t *ret_n
)
7707 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7708 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7709 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7713 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7714 int pixel_clock
, int link_clock
,
7715 struct intel_link_m_n
*m_n
)
7719 compute_m_n(bits_per_pixel
* pixel_clock
,
7720 link_clock
* nlanes
* 8,
7721 &m_n
->gmch_m
, &m_n
->gmch_n
);
7723 compute_m_n(pixel_clock
, link_clock
,
7724 &m_n
->link_m
, &m_n
->link_n
);
7727 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7729 if (i915
.panel_use_ssc
>= 0)
7730 return i915
.panel_use_ssc
!= 0;
7731 return dev_priv
->vbt
.lvds_use_ssc
7732 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7735 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7737 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7740 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7742 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7745 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7746 struct intel_crtc_state
*crtc_state
,
7747 struct dpll
*reduced_clock
)
7749 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7752 if (IS_PINEVIEW(dev_priv
)) {
7753 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7755 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7757 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7759 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7762 crtc_state
->dpll_hw_state
.fp0
= fp
;
7764 crtc
->lowfreq_avail
= false;
7765 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7767 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7768 crtc
->lowfreq_avail
= true;
7770 crtc_state
->dpll_hw_state
.fp1
= fp
;
7774 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7780 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7781 * and set it to a reasonable value instead.
7783 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7784 reg_val
&= 0xffffff00;
7785 reg_val
|= 0x00000030;
7786 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7788 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7789 reg_val
&= 0x8cffffff;
7790 reg_val
= 0x8c000000;
7791 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7793 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7794 reg_val
&= 0xffffff00;
7795 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7797 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7798 reg_val
&= 0x00ffffff;
7799 reg_val
|= 0xb0000000;
7800 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7803 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7804 struct intel_link_m_n
*m_n
)
7806 struct drm_device
*dev
= crtc
->base
.dev
;
7807 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7808 int pipe
= crtc
->pipe
;
7810 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7811 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7812 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7813 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7816 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7817 struct intel_link_m_n
*m_n
,
7818 struct intel_link_m_n
*m2_n2
)
7820 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
7821 int pipe
= crtc
->pipe
;
7822 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7824 if (INTEL_GEN(dev_priv
) >= 5) {
7825 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7826 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7827 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7828 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7829 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7830 * for gen < 8) and if DRRS is supported (to make sure the
7831 * registers are not unnecessarily accessed).
7833 if (m2_n2
&& (IS_CHERRYVIEW(dev_priv
) ||
7834 INTEL_GEN(dev_priv
) < 8) && crtc
->config
->has_drrs
) {
7835 I915_WRITE(PIPE_DATA_M2(transcoder
),
7836 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7837 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7838 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7839 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7842 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7843 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7844 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7845 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7849 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7851 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7854 dp_m_n
= &crtc
->config
->dp_m_n
;
7855 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7856 } else if (m_n
== M2_N2
) {
7859 * M2_N2 registers are not supported. Hence m2_n2 divider value
7860 * needs to be programmed into M1_N1.
7862 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7864 DRM_ERROR("Unsupported divider value\n");
7868 if (crtc
->config
->has_pch_encoder
)
7869 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7871 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7874 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7875 struct intel_crtc_state
*pipe_config
)
7877 pipe_config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
7878 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7879 if (crtc
->pipe
!= PIPE_A
)
7880 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7882 /* DPLL not used with DSI, but still need the rest set up */
7883 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7884 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
|
7885 DPLL_EXT_BUFFER_ENABLE_VLV
;
7887 pipe_config
->dpll_hw_state
.dpll_md
=
7888 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7891 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7892 struct intel_crtc_state
*pipe_config
)
7894 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7895 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
7896 if (crtc
->pipe
!= PIPE_A
)
7897 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7899 /* DPLL not used with DSI, but still need the rest set up */
7900 if (!intel_crtc_has_type(pipe_config
, INTEL_OUTPUT_DSI
))
7901 pipe_config
->dpll_hw_state
.dpll
|= DPLL_VCO_ENABLE
;
7903 pipe_config
->dpll_hw_state
.dpll_md
=
7904 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7907 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7908 const struct intel_crtc_state
*pipe_config
)
7910 struct drm_device
*dev
= crtc
->base
.dev
;
7911 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7912 enum pipe pipe
= crtc
->pipe
;
7914 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7915 u32 coreclk
, reg_val
;
7918 I915_WRITE(DPLL(pipe
),
7919 pipe_config
->dpll_hw_state
.dpll
&
7920 ~(DPLL_VCO_ENABLE
| DPLL_EXT_BUFFER_ENABLE_VLV
));
7922 /* No need to actually set up the DPLL with DSI */
7923 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
7926 mutex_lock(&dev_priv
->sb_lock
);
7928 bestn
= pipe_config
->dpll
.n
;
7929 bestm1
= pipe_config
->dpll
.m1
;
7930 bestm2
= pipe_config
->dpll
.m2
;
7931 bestp1
= pipe_config
->dpll
.p1
;
7932 bestp2
= pipe_config
->dpll
.p2
;
7934 /* See eDP HDMI DPIO driver vbios notes doc */
7936 /* PLL B needs special handling */
7938 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7940 /* Set up Tx target for periodic Rcomp update */
7941 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7943 /* Disable target IRef on PLL */
7944 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7945 reg_val
&= 0x00ffffff;
7946 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7948 /* Disable fast lock */
7949 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7951 /* Set idtafcrecal before PLL is enabled */
7952 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7953 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7954 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7955 mdiv
|= (1 << DPIO_K_SHIFT
);
7958 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7959 * but we don't support that).
7960 * Note: don't use the DAC post divider as it seems unstable.
7962 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7963 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7965 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7966 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7968 /* Set HBR and RBR LPF coefficients */
7969 if (pipe_config
->port_clock
== 162000 ||
7970 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_ANALOG
) ||
7971 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
))
7972 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7975 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7978 if (intel_crtc_has_dp_encoder(pipe_config
)) {
7979 /* Use SSC source */
7981 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7984 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7986 } else { /* HDMI or VGA */
7987 /* Use bend source */
7989 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7992 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7996 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7997 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7998 if (intel_crtc_has_dp_encoder(crtc
->config
))
7999 coreclk
|= 0x01000000;
8000 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
8002 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
8003 mutex_unlock(&dev_priv
->sb_lock
);
8006 static void chv_prepare_pll(struct intel_crtc
*crtc
,
8007 const struct intel_crtc_state
*pipe_config
)
8009 struct drm_device
*dev
= crtc
->base
.dev
;
8010 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8011 enum pipe pipe
= crtc
->pipe
;
8012 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8013 u32 loopfilter
, tribuf_calcntr
;
8014 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
8018 /* Enable Refclk and SSC */
8019 I915_WRITE(DPLL(pipe
),
8020 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
8022 /* No need to actually set up the DPLL with DSI */
8023 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8026 bestn
= pipe_config
->dpll
.n
;
8027 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
8028 bestm1
= pipe_config
->dpll
.m1
;
8029 bestm2
= pipe_config
->dpll
.m2
>> 22;
8030 bestp1
= pipe_config
->dpll
.p1
;
8031 bestp2
= pipe_config
->dpll
.p2
;
8032 vco
= pipe_config
->dpll
.vco
;
8036 mutex_lock(&dev_priv
->sb_lock
);
8038 /* p1 and p2 divider */
8039 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
8040 5 << DPIO_CHV_S1_DIV_SHIFT
|
8041 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
8042 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
8043 1 << DPIO_CHV_K_DIV_SHIFT
);
8045 /* Feedback post-divider - m2 */
8046 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
8048 /* Feedback refclk divider - n and m1 */
8049 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
8050 DPIO_CHV_M1_DIV_BY_2
|
8051 1 << DPIO_CHV_N_DIV_SHIFT
);
8053 /* M2 fraction division */
8054 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
8056 /* M2 fraction division enable */
8057 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8058 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
8059 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
8061 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
8062 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
8064 /* Program digital lock detect threshold */
8065 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
8066 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
8067 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
8068 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
8070 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
8071 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
8074 if (vco
== 5400000) {
8075 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
8076 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
8077 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
8078 tribuf_calcntr
= 0x9;
8079 } else if (vco
<= 6200000) {
8080 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
8081 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
8082 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
8083 tribuf_calcntr
= 0x9;
8084 } else if (vco
<= 6480000) {
8085 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
8086 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
8087 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
8088 tribuf_calcntr
= 0x8;
8090 /* Not supported. Apply the same limits as in the max case */
8091 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
8092 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
8093 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
8096 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
8098 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
8099 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
8100 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
8101 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
8104 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
8105 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
8108 mutex_unlock(&dev_priv
->sb_lock
);
8112 * vlv_force_pll_on - forcibly enable just the PLL
8113 * @dev_priv: i915 private structure
8114 * @pipe: pipe PLL to enable
8115 * @dpll: PLL configuration
8117 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8118 * in cases where we need the PLL enabled even when @pipe is not going to
8121 int vlv_force_pll_on(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
8122 const struct dpll
*dpll
)
8124 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
8125 struct intel_crtc_state
*pipe_config
;
8127 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8131 pipe_config
->base
.crtc
= &crtc
->base
;
8132 pipe_config
->pixel_multiplier
= 1;
8133 pipe_config
->dpll
= *dpll
;
8135 if (IS_CHERRYVIEW(dev_priv
)) {
8136 chv_compute_dpll(crtc
, pipe_config
);
8137 chv_prepare_pll(crtc
, pipe_config
);
8138 chv_enable_pll(crtc
, pipe_config
);
8140 vlv_compute_dpll(crtc
, pipe_config
);
8141 vlv_prepare_pll(crtc
, pipe_config
);
8142 vlv_enable_pll(crtc
, pipe_config
);
8151 * vlv_force_pll_off - forcibly disable just the PLL
8152 * @dev_priv: i915 private structure
8153 * @pipe: pipe PLL to disable
8155 * Disable the PLL for @pipe. To be used in cases where we need
8156 * the PLL enabled even when @pipe is not going to be enabled.
8158 void vlv_force_pll_off(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
8160 if (IS_CHERRYVIEW(dev_priv
))
8161 chv_disable_pll(dev_priv
, pipe
);
8163 vlv_disable_pll(dev_priv
, pipe
);
8166 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
8167 struct intel_crtc_state
*crtc_state
,
8168 struct dpll
*reduced_clock
)
8170 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8172 struct dpll
*clock
= &crtc_state
->dpll
;
8174 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
8176 dpll
= DPLL_VGA_MODE_DIS
;
8178 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
8179 dpll
|= DPLLB_MODE_LVDS
;
8181 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8183 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) || IS_G33(dev_priv
)) {
8184 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8185 << SDVO_MULTIPLIER_SHIFT_HIRES
;
8188 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
8189 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
8190 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8192 if (intel_crtc_has_dp_encoder(crtc_state
))
8193 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8195 /* compute bitmask from p1 value */
8196 if (IS_PINEVIEW(dev_priv
))
8197 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
8199 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8200 if (IS_G4X(dev_priv
) && reduced_clock
)
8201 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8203 switch (clock
->p2
) {
8205 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8208 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8211 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8214 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8217 if (INTEL_GEN(dev_priv
) >= 4)
8218 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
8220 if (crtc_state
->sdvo_tv_clock
)
8221 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
8222 else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
8223 intel_panel_use_ssc(dev_priv
))
8224 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8226 dpll
|= PLL_REF_INPUT_DREFCLK
;
8228 dpll
|= DPLL_VCO_ENABLE
;
8229 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8231 if (INTEL_GEN(dev_priv
) >= 4) {
8232 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
8233 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
8234 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
8238 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
8239 struct intel_crtc_state
*crtc_state
,
8240 struct dpll
*reduced_clock
)
8242 struct drm_device
*dev
= crtc
->base
.dev
;
8243 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8245 struct dpll
*clock
= &crtc_state
->dpll
;
8247 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
8249 dpll
= DPLL_VGA_MODE_DIS
;
8251 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8252 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8255 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
8257 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8259 dpll
|= PLL_P2_DIVIDE_BY_4
;
8262 if (!IS_I830(dev_priv
) &&
8263 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
))
8264 dpll
|= DPLL_DVO_2X_MODE
;
8266 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
8267 intel_panel_use_ssc(dev_priv
))
8268 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8270 dpll
|= PLL_REF_INPUT_DREFCLK
;
8272 dpll
|= DPLL_VCO_ENABLE
;
8273 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8276 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
8278 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
8279 enum pipe pipe
= intel_crtc
->pipe
;
8280 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8281 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
8282 uint32_t crtc_vtotal
, crtc_vblank_end
;
8285 /* We need to be careful not to changed the adjusted mode, for otherwise
8286 * the hw state checker will get angry at the mismatch. */
8287 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
8288 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
8290 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
8291 /* the chip adds 2 halflines automatically */
8293 crtc_vblank_end
-= 1;
8295 if (intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
8296 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
8298 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
8299 adjusted_mode
->crtc_htotal
/ 2;
8301 vsyncshift
+= adjusted_mode
->crtc_htotal
;
8304 if (INTEL_GEN(dev_priv
) > 3)
8305 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
8307 I915_WRITE(HTOTAL(cpu_transcoder
),
8308 (adjusted_mode
->crtc_hdisplay
- 1) |
8309 ((adjusted_mode
->crtc_htotal
- 1) << 16));
8310 I915_WRITE(HBLANK(cpu_transcoder
),
8311 (adjusted_mode
->crtc_hblank_start
- 1) |
8312 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
8313 I915_WRITE(HSYNC(cpu_transcoder
),
8314 (adjusted_mode
->crtc_hsync_start
- 1) |
8315 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
8317 I915_WRITE(VTOTAL(cpu_transcoder
),
8318 (adjusted_mode
->crtc_vdisplay
- 1) |
8319 ((crtc_vtotal
- 1) << 16));
8320 I915_WRITE(VBLANK(cpu_transcoder
),
8321 (adjusted_mode
->crtc_vblank_start
- 1) |
8322 ((crtc_vblank_end
- 1) << 16));
8323 I915_WRITE(VSYNC(cpu_transcoder
),
8324 (adjusted_mode
->crtc_vsync_start
- 1) |
8325 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
8327 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8328 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8329 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8331 if (IS_HASWELL(dev_priv
) && cpu_transcoder
== TRANSCODER_EDP
&&
8332 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
8333 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
8337 static void intel_set_pipe_src_size(struct intel_crtc
*intel_crtc
)
8339 struct drm_device
*dev
= intel_crtc
->base
.dev
;
8340 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8341 enum pipe pipe
= intel_crtc
->pipe
;
8343 /* pipesrc controls the size that is scaled from, which should
8344 * always be the user's requested size.
8346 I915_WRITE(PIPESRC(pipe
),
8347 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
8348 (intel_crtc
->config
->pipe_src_h
- 1));
8351 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
8352 struct intel_crtc_state
*pipe_config
)
8354 struct drm_device
*dev
= crtc
->base
.dev
;
8355 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8356 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
8359 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
8360 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
8361 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
8362 tmp
= I915_READ(HBLANK(cpu_transcoder
));
8363 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
8364 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
8365 tmp
= I915_READ(HSYNC(cpu_transcoder
));
8366 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
8367 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
8369 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
8370 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
8371 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
8372 tmp
= I915_READ(VBLANK(cpu_transcoder
));
8373 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
8374 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
8375 tmp
= I915_READ(VSYNC(cpu_transcoder
));
8376 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
8377 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
8379 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
8380 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
8381 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
8382 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
8386 static void intel_get_pipe_src_size(struct intel_crtc
*crtc
,
8387 struct intel_crtc_state
*pipe_config
)
8389 struct drm_device
*dev
= crtc
->base
.dev
;
8390 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8393 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
8394 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
8395 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
8397 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
8398 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
8401 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
8402 struct intel_crtc_state
*pipe_config
)
8404 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
8405 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
8406 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
8407 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
8409 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
8410 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
8411 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
8412 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
8414 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
8415 mode
->type
= DRM_MODE_TYPE_DRIVER
;
8417 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
8418 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
8420 mode
->hsync
= drm_mode_hsync(mode
);
8421 mode
->vrefresh
= drm_mode_vrefresh(mode
);
8422 drm_mode_set_name(mode
);
8425 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
8427 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
8432 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
8433 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
8434 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
8436 if (intel_crtc
->config
->double_wide
)
8437 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
8439 /* only g4x and later have fancy bpc/dither controls */
8440 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
8441 IS_CHERRYVIEW(dev_priv
)) {
8442 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8443 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
8444 pipeconf
|= PIPECONF_DITHER_EN
|
8445 PIPECONF_DITHER_TYPE_SP
;
8447 switch (intel_crtc
->config
->pipe_bpp
) {
8449 pipeconf
|= PIPECONF_6BPC
;
8452 pipeconf
|= PIPECONF_8BPC
;
8455 pipeconf
|= PIPECONF_10BPC
;
8458 /* Case prevented by intel_choose_pipe_bpp_dither. */
8463 if (HAS_PIPE_CXSR(dev_priv
)) {
8464 if (intel_crtc
->lowfreq_avail
) {
8465 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8466 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
8468 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8472 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
8473 if (INTEL_GEN(dev_priv
) < 4 ||
8474 intel_crtc_has_type(intel_crtc
->config
, INTEL_OUTPUT_SDVO
))
8475 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
8477 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
8479 pipeconf
|= PIPECONF_PROGRESSIVE
;
8481 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
8482 intel_crtc
->config
->limited_color_range
)
8483 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
8485 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
8486 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
8489 static int i8xx_crtc_compute_clock(struct intel_crtc
*crtc
,
8490 struct intel_crtc_state
*crtc_state
)
8492 struct drm_device
*dev
= crtc
->base
.dev
;
8493 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8494 const struct intel_limit
*limit
;
8497 memset(&crtc_state
->dpll_hw_state
, 0,
8498 sizeof(crtc_state
->dpll_hw_state
));
8500 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8501 if (intel_panel_use_ssc(dev_priv
)) {
8502 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8503 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8506 limit
= &intel_limits_i8xx_lvds
;
8507 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DVO
)) {
8508 limit
= &intel_limits_i8xx_dvo
;
8510 limit
= &intel_limits_i8xx_dac
;
8513 if (!crtc_state
->clock_set
&&
8514 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8515 refclk
, NULL
, &crtc_state
->dpll
)) {
8516 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8520 i8xx_compute_dpll(crtc
, crtc_state
, NULL
);
8525 static int g4x_crtc_compute_clock(struct intel_crtc
*crtc
,
8526 struct intel_crtc_state
*crtc_state
)
8528 struct drm_device
*dev
= crtc
->base
.dev
;
8529 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8530 const struct intel_limit
*limit
;
8533 memset(&crtc_state
->dpll_hw_state
, 0,
8534 sizeof(crtc_state
->dpll_hw_state
));
8536 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8537 if (intel_panel_use_ssc(dev_priv
)) {
8538 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8539 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8542 if (intel_is_dual_link_lvds(dev
))
8543 limit
= &intel_limits_g4x_dual_channel_lvds
;
8545 limit
= &intel_limits_g4x_single_channel_lvds
;
8546 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
8547 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
8548 limit
= &intel_limits_g4x_hdmi
;
8549 } else if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
8550 limit
= &intel_limits_g4x_sdvo
;
8552 /* The option is for other outputs */
8553 limit
= &intel_limits_i9xx_sdvo
;
8556 if (!crtc_state
->clock_set
&&
8557 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8558 refclk
, NULL
, &crtc_state
->dpll
)) {
8559 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8563 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8568 static int pnv_crtc_compute_clock(struct intel_crtc
*crtc
,
8569 struct intel_crtc_state
*crtc_state
)
8571 struct drm_device
*dev
= crtc
->base
.dev
;
8572 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8573 const struct intel_limit
*limit
;
8576 memset(&crtc_state
->dpll_hw_state
, 0,
8577 sizeof(crtc_state
->dpll_hw_state
));
8579 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8580 if (intel_panel_use_ssc(dev_priv
)) {
8581 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8582 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8585 limit
= &intel_limits_pineview_lvds
;
8587 limit
= &intel_limits_pineview_sdvo
;
8590 if (!crtc_state
->clock_set
&&
8591 !pnv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8592 refclk
, NULL
, &crtc_state
->dpll
)) {
8593 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8597 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8602 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
8603 struct intel_crtc_state
*crtc_state
)
8605 struct drm_device
*dev
= crtc
->base
.dev
;
8606 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8607 const struct intel_limit
*limit
;
8610 memset(&crtc_state
->dpll_hw_state
, 0,
8611 sizeof(crtc_state
->dpll_hw_state
));
8613 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
8614 if (intel_panel_use_ssc(dev_priv
)) {
8615 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
8616 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
8619 limit
= &intel_limits_i9xx_lvds
;
8621 limit
= &intel_limits_i9xx_sdvo
;
8624 if (!crtc_state
->clock_set
&&
8625 !i9xx_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8626 refclk
, NULL
, &crtc_state
->dpll
)) {
8627 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8631 i9xx_compute_dpll(crtc
, crtc_state
, NULL
);
8636 static int chv_crtc_compute_clock(struct intel_crtc
*crtc
,
8637 struct intel_crtc_state
*crtc_state
)
8639 int refclk
= 100000;
8640 const struct intel_limit
*limit
= &intel_limits_chv
;
8642 memset(&crtc_state
->dpll_hw_state
, 0,
8643 sizeof(crtc_state
->dpll_hw_state
));
8645 if (!crtc_state
->clock_set
&&
8646 !chv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8647 refclk
, NULL
, &crtc_state
->dpll
)) {
8648 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8652 chv_compute_dpll(crtc
, crtc_state
);
8657 static int vlv_crtc_compute_clock(struct intel_crtc
*crtc
,
8658 struct intel_crtc_state
*crtc_state
)
8660 int refclk
= 100000;
8661 const struct intel_limit
*limit
= &intel_limits_vlv
;
8663 memset(&crtc_state
->dpll_hw_state
, 0,
8664 sizeof(crtc_state
->dpll_hw_state
));
8666 if (!crtc_state
->clock_set
&&
8667 !vlv_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
8668 refclk
, NULL
, &crtc_state
->dpll
)) {
8669 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8673 vlv_compute_dpll(crtc
, crtc_state
);
8678 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
8679 struct intel_crtc_state
*pipe_config
)
8681 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8684 if (INTEL_GEN(dev_priv
) <= 3 &&
8685 (IS_I830(dev_priv
) || !IS_MOBILE(dev_priv
)))
8688 tmp
= I915_READ(PFIT_CONTROL
);
8689 if (!(tmp
& PFIT_ENABLE
))
8692 /* Check whether the pfit is attached to our pipe. */
8693 if (INTEL_GEN(dev_priv
) < 4) {
8694 if (crtc
->pipe
!= PIPE_B
)
8697 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8701 pipe_config
->gmch_pfit
.control
= tmp
;
8702 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8705 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8706 struct intel_crtc_state
*pipe_config
)
8708 struct drm_device
*dev
= crtc
->base
.dev
;
8709 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8710 int pipe
= pipe_config
->cpu_transcoder
;
8713 int refclk
= 100000;
8715 /* In case of DSI, DPLL will not be used */
8716 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8719 mutex_lock(&dev_priv
->sb_lock
);
8720 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8721 mutex_unlock(&dev_priv
->sb_lock
);
8723 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8724 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8725 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8726 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8727 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8729 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8733 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8734 struct intel_initial_plane_config
*plane_config
)
8736 struct drm_device
*dev
= crtc
->base
.dev
;
8737 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8738 u32 val
, base
, offset
;
8739 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
8740 int fourcc
, pixel_format
;
8741 unsigned int aligned_height
;
8742 struct drm_framebuffer
*fb
;
8743 struct intel_framebuffer
*intel_fb
;
8745 val
= I915_READ(DSPCNTR(plane
));
8746 if (!(val
& DISPLAY_PLANE_ENABLE
))
8749 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8751 DRM_DEBUG_KMS("failed to alloc fb\n");
8755 fb
= &intel_fb
->base
;
8757 if (INTEL_GEN(dev_priv
) >= 4) {
8758 if (val
& DISPPLANE_TILED
) {
8759 plane_config
->tiling
= I915_TILING_X
;
8760 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
8764 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8765 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8766 fb
->pixel_format
= fourcc
;
8767 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8769 if (INTEL_GEN(dev_priv
) >= 4) {
8770 if (plane_config
->tiling
)
8771 offset
= I915_READ(DSPTILEOFF(plane
));
8773 offset
= I915_READ(DSPLINOFF(plane
));
8774 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
8776 base
= I915_READ(DSPADDR(plane
));
8778 plane_config
->base
= base
;
8780 val
= I915_READ(PIPESRC(pipe
));
8781 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8782 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8784 val
= I915_READ(DSPSTRIDE(pipe
));
8785 fb
->pitches
[0] = val
& 0xffffffc0;
8787 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8791 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8793 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8794 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8795 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8796 plane_config
->size
);
8798 plane_config
->fb
= intel_fb
;
8801 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8802 struct intel_crtc_state
*pipe_config
)
8804 struct drm_device
*dev
= crtc
->base
.dev
;
8805 struct drm_i915_private
*dev_priv
= to_i915(dev
);
8806 int pipe
= pipe_config
->cpu_transcoder
;
8807 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8809 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8810 int refclk
= 100000;
8812 /* In case of DSI, DPLL will not be used */
8813 if ((pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
) == 0)
8816 mutex_lock(&dev_priv
->sb_lock
);
8817 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8818 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8819 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8820 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8821 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8822 mutex_unlock(&dev_priv
->sb_lock
);
8824 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8825 clock
.m2
= (pll_dw0
& 0xff) << 22;
8826 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8827 clock
.m2
|= pll_dw2
& 0x3fffff;
8828 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8829 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8830 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8832 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8835 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8836 struct intel_crtc_state
*pipe_config
)
8838 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
8839 enum intel_display_power_domain power_domain
;
8843 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
8844 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
8847 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8848 pipe_config
->shared_dpll
= NULL
;
8852 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8853 if (!(tmp
& PIPECONF_ENABLE
))
8856 if (IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
8857 IS_CHERRYVIEW(dev_priv
)) {
8858 switch (tmp
& PIPECONF_BPC_MASK
) {
8860 pipe_config
->pipe_bpp
= 18;
8863 pipe_config
->pipe_bpp
= 24;
8865 case PIPECONF_10BPC
:
8866 pipe_config
->pipe_bpp
= 30;
8873 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
8874 (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8875 pipe_config
->limited_color_range
= true;
8877 if (INTEL_GEN(dev_priv
) < 4)
8878 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8880 intel_get_pipe_timings(crtc
, pipe_config
);
8881 intel_get_pipe_src_size(crtc
, pipe_config
);
8883 i9xx_get_pfit_config(crtc
, pipe_config
);
8885 if (INTEL_GEN(dev_priv
) >= 4) {
8886 /* No way to read it out on pipes B and C */
8887 if (IS_CHERRYVIEW(dev_priv
) && crtc
->pipe
!= PIPE_A
)
8888 tmp
= dev_priv
->chv_dpll_md
[crtc
->pipe
];
8890 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8891 pipe_config
->pixel_multiplier
=
8892 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8893 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8894 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8895 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
8897 tmp
= I915_READ(DPLL(crtc
->pipe
));
8898 pipe_config
->pixel_multiplier
=
8899 ((tmp
& SDVO_MULTIPLIER_MASK
)
8900 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8902 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8903 * port and will be fixed up in the encoder->get_config
8905 pipe_config
->pixel_multiplier
= 1;
8907 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8908 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
8910 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8911 * on 830. Filter it out here so that we don't
8912 * report errors due to that.
8914 if (IS_I830(dev_priv
))
8915 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8917 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8918 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8920 /* Mask out read-only status bits. */
8921 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8922 DPLL_PORTC_READY_MASK
|
8923 DPLL_PORTB_READY_MASK
);
8926 if (IS_CHERRYVIEW(dev_priv
))
8927 chv_crtc_clock_get(crtc
, pipe_config
);
8928 else if (IS_VALLEYVIEW(dev_priv
))
8929 vlv_crtc_clock_get(crtc
, pipe_config
);
8931 i9xx_crtc_clock_get(crtc
, pipe_config
);
8934 * Normally the dotclock is filled in by the encoder .get_config()
8935 * but in case the pipe is enabled w/o any ports we need a sane
8938 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8939 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8944 intel_display_power_put(dev_priv
, power_domain
);
8949 static void ironlake_init_pch_refclk(struct drm_i915_private
*dev_priv
)
8951 struct intel_encoder
*encoder
;
8954 bool has_lvds
= false;
8955 bool has_cpu_edp
= false;
8956 bool has_panel
= false;
8957 bool has_ck505
= false;
8958 bool can_ssc
= false;
8959 bool using_ssc_source
= false;
8961 /* We need to take the global config into account */
8962 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
8963 switch (encoder
->type
) {
8964 case INTEL_OUTPUT_LVDS
:
8968 case INTEL_OUTPUT_EDP
:
8970 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8978 if (HAS_PCH_IBX(dev_priv
)) {
8979 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8980 can_ssc
= has_ck505
;
8986 /* Check if any DPLLs are using the SSC source */
8987 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8988 u32 temp
= I915_READ(PCH_DPLL(i
));
8990 if (!(temp
& DPLL_VCO_ENABLE
))
8993 if ((temp
& PLL_REF_INPUT_MASK
) ==
8994 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
8995 using_ssc_source
= true;
9000 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9001 has_panel
, has_lvds
, has_ck505
, using_ssc_source
);
9003 /* Ironlake: try to setup display ref clock before DPLL
9004 * enabling. This is only under driver's control after
9005 * PCH B stepping, previous chipset stepping should be
9006 * ignoring this setting.
9008 val
= I915_READ(PCH_DREF_CONTROL
);
9010 /* As we must carefully and slowly disable/enable each source in turn,
9011 * compute the final state we want first and check if we need to
9012 * make any changes at all.
9015 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
9017 final
|= DREF_NONSPREAD_CK505_ENABLE
;
9019 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
9021 final
&= ~DREF_SSC_SOURCE_MASK
;
9022 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
9023 final
&= ~DREF_SSC1_ENABLE
;
9026 final
|= DREF_SSC_SOURCE_ENABLE
;
9028 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
9029 final
|= DREF_SSC1_ENABLE
;
9032 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
9033 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
9035 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
9037 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
9038 } else if (using_ssc_source
) {
9039 final
|= DREF_SSC_SOURCE_ENABLE
;
9040 final
|= DREF_SSC1_ENABLE
;
9046 /* Always enable nonspread source */
9047 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
9050 val
|= DREF_NONSPREAD_CK505_ENABLE
;
9052 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
9055 val
&= ~DREF_SSC_SOURCE_MASK
;
9056 val
|= DREF_SSC_SOURCE_ENABLE
;
9058 /* SSC must be turned on before enabling the CPU output */
9059 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
9060 DRM_DEBUG_KMS("Using SSC on panel\n");
9061 val
|= DREF_SSC1_ENABLE
;
9063 val
&= ~DREF_SSC1_ENABLE
;
9065 /* Get SSC going before enabling the outputs */
9066 I915_WRITE(PCH_DREF_CONTROL
, val
);
9067 POSTING_READ(PCH_DREF_CONTROL
);
9070 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
9072 /* Enable CPU source on CPU attached eDP */
9074 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
9075 DRM_DEBUG_KMS("Using SSC on eDP\n");
9076 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
9078 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
9080 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
9082 I915_WRITE(PCH_DREF_CONTROL
, val
);
9083 POSTING_READ(PCH_DREF_CONTROL
);
9086 DRM_DEBUG_KMS("Disabling CPU source output\n");
9088 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
9090 /* Turn off CPU output */
9091 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
9093 I915_WRITE(PCH_DREF_CONTROL
, val
);
9094 POSTING_READ(PCH_DREF_CONTROL
);
9097 if (!using_ssc_source
) {
9098 DRM_DEBUG_KMS("Disabling SSC source\n");
9100 /* Turn off the SSC source */
9101 val
&= ~DREF_SSC_SOURCE_MASK
;
9102 val
|= DREF_SSC_SOURCE_DISABLE
;
9105 val
&= ~DREF_SSC1_ENABLE
;
9107 I915_WRITE(PCH_DREF_CONTROL
, val
);
9108 POSTING_READ(PCH_DREF_CONTROL
);
9113 BUG_ON(val
!= final
);
9116 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
9120 tmp
= I915_READ(SOUTH_CHICKEN2
);
9121 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
9122 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
9124 if (wait_for_us(I915_READ(SOUTH_CHICKEN2
) &
9125 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
9126 DRM_ERROR("FDI mPHY reset assert timeout\n");
9128 tmp
= I915_READ(SOUTH_CHICKEN2
);
9129 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
9130 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
9132 if (wait_for_us((I915_READ(SOUTH_CHICKEN2
) &
9133 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
9134 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9137 /* WaMPhyProgramming:hsw */
9138 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
9142 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
9143 tmp
&= ~(0xFF << 24);
9144 tmp
|= (0x12 << 24);
9145 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
9147 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
9149 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
9151 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
9153 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
9155 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
9156 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
9157 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
9159 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
9160 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
9161 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
9163 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
9166 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
9168 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
9171 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
9173 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
9176 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
9178 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
9181 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
9183 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
9184 tmp
&= ~(0xFF << 16);
9185 tmp
|= (0x1C << 16);
9186 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
9188 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
9189 tmp
&= ~(0xFF << 16);
9190 tmp
|= (0x1C << 16);
9191 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
9193 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
9195 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
9197 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
9199 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
9201 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
9202 tmp
&= ~(0xF << 28);
9204 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
9206 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
9207 tmp
&= ~(0xF << 28);
9209 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
9212 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9213 * Programming" based on the parameters passed:
9214 * - Sequence to enable CLKOUT_DP
9215 * - Sequence to enable CLKOUT_DP without spread
9216 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9218 static void lpt_enable_clkout_dp(struct drm_i915_private
*dev_priv
,
9219 bool with_spread
, bool with_fdi
)
9223 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
9225 if (WARN(HAS_PCH_LPT_LP(dev_priv
) &&
9226 with_fdi
, "LP PCH doesn't have FDI\n"))
9229 mutex_lock(&dev_priv
->sb_lock
);
9231 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
9232 tmp
&= ~SBI_SSCCTL_DISABLE
;
9233 tmp
|= SBI_SSCCTL_PATHALT
;
9234 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9239 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
9240 tmp
&= ~SBI_SSCCTL_PATHALT
;
9241 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9244 lpt_reset_fdi_mphy(dev_priv
);
9245 lpt_program_fdi_mphy(dev_priv
);
9249 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
9250 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
9251 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
9252 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
9254 mutex_unlock(&dev_priv
->sb_lock
);
9257 /* Sequence to disable CLKOUT_DP */
9258 static void lpt_disable_clkout_dp(struct drm_i915_private
*dev_priv
)
9262 mutex_lock(&dev_priv
->sb_lock
);
9264 reg
= HAS_PCH_LPT_LP(dev_priv
) ? SBI_GEN0
: SBI_DBUFF0
;
9265 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
9266 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
9267 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
9269 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
9270 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
9271 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
9272 tmp
|= SBI_SSCCTL_PATHALT
;
9273 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9276 tmp
|= SBI_SSCCTL_DISABLE
;
9277 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
9280 mutex_unlock(&dev_priv
->sb_lock
);
9283 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9285 static const uint16_t sscdivintphase
[] = {
9286 [BEND_IDX( 50)] = 0x3B23,
9287 [BEND_IDX( 45)] = 0x3B23,
9288 [BEND_IDX( 40)] = 0x3C23,
9289 [BEND_IDX( 35)] = 0x3C23,
9290 [BEND_IDX( 30)] = 0x3D23,
9291 [BEND_IDX( 25)] = 0x3D23,
9292 [BEND_IDX( 20)] = 0x3E23,
9293 [BEND_IDX( 15)] = 0x3E23,
9294 [BEND_IDX( 10)] = 0x3F23,
9295 [BEND_IDX( 5)] = 0x3F23,
9296 [BEND_IDX( 0)] = 0x0025,
9297 [BEND_IDX( -5)] = 0x0025,
9298 [BEND_IDX(-10)] = 0x0125,
9299 [BEND_IDX(-15)] = 0x0125,
9300 [BEND_IDX(-20)] = 0x0225,
9301 [BEND_IDX(-25)] = 0x0225,
9302 [BEND_IDX(-30)] = 0x0325,
9303 [BEND_IDX(-35)] = 0x0325,
9304 [BEND_IDX(-40)] = 0x0425,
9305 [BEND_IDX(-45)] = 0x0425,
9306 [BEND_IDX(-50)] = 0x0525,
9311 * steps -50 to 50 inclusive, in steps of 5
9312 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9313 * change in clock period = -(steps / 10) * 5.787 ps
9315 static void lpt_bend_clkout_dp(struct drm_i915_private
*dev_priv
, int steps
)
9318 int idx
= BEND_IDX(steps
);
9320 if (WARN_ON(steps
% 5 != 0))
9323 if (WARN_ON(idx
>= ARRAY_SIZE(sscdivintphase
)))
9326 mutex_lock(&dev_priv
->sb_lock
);
9328 if (steps
% 10 != 0)
9332 intel_sbi_write(dev_priv
, SBI_SSCDITHPHASE
, tmp
, SBI_ICLK
);
9334 tmp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE
, SBI_ICLK
);
9336 tmp
|= sscdivintphase
[idx
];
9337 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE
, tmp
, SBI_ICLK
);
9339 mutex_unlock(&dev_priv
->sb_lock
);
9344 static void lpt_init_pch_refclk(struct drm_i915_private
*dev_priv
)
9346 struct intel_encoder
*encoder
;
9347 bool has_vga
= false;
9349 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
9350 switch (encoder
->type
) {
9351 case INTEL_OUTPUT_ANALOG
:
9360 lpt_bend_clkout_dp(dev_priv
, 0);
9361 lpt_enable_clkout_dp(dev_priv
, true, true);
9363 lpt_disable_clkout_dp(dev_priv
);
9368 * Initialize reference clocks when the driver loads
9370 void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
)
9372 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
))
9373 ironlake_init_pch_refclk(dev_priv
);
9374 else if (HAS_PCH_LPT(dev_priv
))
9375 lpt_init_pch_refclk(dev_priv
);
9378 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
9380 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
9381 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9382 int pipe
= intel_crtc
->pipe
;
9387 switch (intel_crtc
->config
->pipe_bpp
) {
9389 val
|= PIPECONF_6BPC
;
9392 val
|= PIPECONF_8BPC
;
9395 val
|= PIPECONF_10BPC
;
9398 val
|= PIPECONF_12BPC
;
9401 /* Case prevented by intel_choose_pipe_bpp_dither. */
9405 if (intel_crtc
->config
->dither
)
9406 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
9408 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
9409 val
|= PIPECONF_INTERLACED_ILK
;
9411 val
|= PIPECONF_PROGRESSIVE
;
9413 if (intel_crtc
->config
->limited_color_range
)
9414 val
|= PIPECONF_COLOR_RANGE_SELECT
;
9416 I915_WRITE(PIPECONF(pipe
), val
);
9417 POSTING_READ(PIPECONF(pipe
));
9420 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
9422 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
9423 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9424 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
9427 if (IS_HASWELL(dev_priv
) && intel_crtc
->config
->dither
)
9428 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
9430 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
9431 val
|= PIPECONF_INTERLACED_ILK
;
9433 val
|= PIPECONF_PROGRESSIVE
;
9435 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
9436 POSTING_READ(PIPECONF(cpu_transcoder
));
9439 static void haswell_set_pipemisc(struct drm_crtc
*crtc
)
9441 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
9442 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9444 if (IS_BROADWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 9) {
9447 switch (intel_crtc
->config
->pipe_bpp
) {
9449 val
|= PIPEMISC_DITHER_6_BPC
;
9452 val
|= PIPEMISC_DITHER_8_BPC
;
9455 val
|= PIPEMISC_DITHER_10_BPC
;
9458 val
|= PIPEMISC_DITHER_12_BPC
;
9461 /* Case prevented by pipe_config_set_bpp. */
9465 if (intel_crtc
->config
->dither
)
9466 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
9468 I915_WRITE(PIPEMISC(intel_crtc
->pipe
), val
);
9472 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
9475 * Account for spread spectrum to avoid
9476 * oversubscribing the link. Max center spread
9477 * is 2.5%; use 5% for safety's sake.
9479 u32 bps
= target_clock
* bpp
* 21 / 20;
9480 return DIV_ROUND_UP(bps
, link_bw
* 8);
9483 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
9485 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
9488 static void ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
9489 struct intel_crtc_state
*crtc_state
,
9490 struct dpll
*reduced_clock
)
9492 struct drm_crtc
*crtc
= &intel_crtc
->base
;
9493 struct drm_device
*dev
= crtc
->dev
;
9494 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9498 /* Enable autotuning of the PLL clock (if permissible) */
9500 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9501 if ((intel_panel_use_ssc(dev_priv
) &&
9502 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
9503 (HAS_PCH_IBX(dev_priv
) && intel_is_dual_link_lvds(dev
)))
9505 } else if (crtc_state
->sdvo_tv_clock
)
9508 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
9510 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
9513 if (reduced_clock
) {
9514 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
9516 if (reduced_clock
->m
< factor
* reduced_clock
->n
)
9524 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
))
9525 dpll
|= DPLLB_MODE_LVDS
;
9527 dpll
|= DPLLB_MODE_DAC_SERIAL
;
9529 dpll
|= (crtc_state
->pixel_multiplier
- 1)
9530 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
9532 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
9533 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_HDMI
))
9534 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9536 if (intel_crtc_has_dp_encoder(crtc_state
))
9537 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9540 * The high speed IO clock is only really required for
9541 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9542 * possible to share the DPLL between CRT and HDMI. Enabling
9543 * the clock needlessly does no real harm, except use up a
9544 * bit of power potentially.
9546 * We'll limit this to IVB with 3 pipes, since it has only two
9547 * DPLLs and so DPLL sharing is the only way to get three pipes
9548 * driving PCH ports at the same time. On SNB we could do this,
9549 * and potentially avoid enabling the second DPLL, but it's not
9550 * clear if it''s a win or loss power wise. No point in doing
9551 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9553 if (INTEL_INFO(dev_priv
)->num_pipes
== 3 &&
9554 intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_ANALOG
))
9555 dpll
|= DPLL_SDVO_HIGH_SPEED
;
9557 /* compute bitmask from p1 value */
9558 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
9560 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
9562 switch (crtc_state
->dpll
.p2
) {
9564 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
9567 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
9570 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
9573 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
9577 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9578 intel_panel_use_ssc(dev_priv
))
9579 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
9581 dpll
|= PLL_REF_INPUT_DREFCLK
;
9583 dpll
|= DPLL_VCO_ENABLE
;
9585 crtc_state
->dpll_hw_state
.dpll
= dpll
;
9586 crtc_state
->dpll_hw_state
.fp0
= fp
;
9587 crtc_state
->dpll_hw_state
.fp1
= fp2
;
9590 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
9591 struct intel_crtc_state
*crtc_state
)
9593 struct drm_device
*dev
= crtc
->base
.dev
;
9594 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9595 struct dpll reduced_clock
;
9596 bool has_reduced_clock
= false;
9597 struct intel_shared_dpll
*pll
;
9598 const struct intel_limit
*limit
;
9599 int refclk
= 120000;
9601 memset(&crtc_state
->dpll_hw_state
, 0,
9602 sizeof(crtc_state
->dpll_hw_state
));
9604 crtc
->lowfreq_avail
= false;
9606 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9607 if (!crtc_state
->has_pch_encoder
)
9610 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
9611 if (intel_panel_use_ssc(dev_priv
)) {
9612 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9613 dev_priv
->vbt
.lvds_ssc_freq
);
9614 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
9617 if (intel_is_dual_link_lvds(dev
)) {
9618 if (refclk
== 100000)
9619 limit
= &intel_limits_ironlake_dual_lvds_100m
;
9621 limit
= &intel_limits_ironlake_dual_lvds
;
9623 if (refclk
== 100000)
9624 limit
= &intel_limits_ironlake_single_lvds_100m
;
9626 limit
= &intel_limits_ironlake_single_lvds
;
9629 limit
= &intel_limits_ironlake_dac
;
9632 if (!crtc_state
->clock_set
&&
9633 !g4x_find_best_dpll(limit
, crtc_state
, crtc_state
->port_clock
,
9634 refclk
, NULL
, &crtc_state
->dpll
)) {
9635 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9639 ironlake_compute_dpll(crtc
, crtc_state
,
9640 has_reduced_clock
? &reduced_clock
: NULL
);
9642 pll
= intel_get_shared_dpll(crtc
, crtc_state
, NULL
);
9644 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9645 pipe_name(crtc
->pipe
));
9649 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
9651 crtc
->lowfreq_avail
= true;
9656 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9657 struct intel_link_m_n
*m_n
)
9659 struct drm_device
*dev
= crtc
->base
.dev
;
9660 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9661 enum pipe pipe
= crtc
->pipe
;
9663 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9664 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9665 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9667 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9668 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9669 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9672 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9673 enum transcoder transcoder
,
9674 struct intel_link_m_n
*m_n
,
9675 struct intel_link_m_n
*m2_n2
)
9677 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
9678 enum pipe pipe
= crtc
->pipe
;
9680 if (INTEL_GEN(dev_priv
) >= 5) {
9681 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9682 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9683 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9685 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9686 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9687 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9688 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9689 * gen < 8) and if DRRS is supported (to make sure the
9690 * registers are not unnecessarily read).
9692 if (m2_n2
&& INTEL_GEN(dev_priv
) < 8 &&
9693 crtc
->config
->has_drrs
) {
9694 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9695 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9696 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9698 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9699 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9700 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9703 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9704 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9705 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9707 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9708 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9709 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9713 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9714 struct intel_crtc_state
*pipe_config
)
9716 if (pipe_config
->has_pch_encoder
)
9717 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9719 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9720 &pipe_config
->dp_m_n
,
9721 &pipe_config
->dp_m2_n2
);
9724 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9725 struct intel_crtc_state
*pipe_config
)
9727 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9728 &pipe_config
->fdi_m_n
, NULL
);
9731 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9732 struct intel_crtc_state
*pipe_config
)
9734 struct drm_device
*dev
= crtc
->base
.dev
;
9735 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9736 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9737 uint32_t ps_ctrl
= 0;
9741 /* find scaler attached to this pipe */
9742 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9743 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9744 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9746 pipe_config
->pch_pfit
.enabled
= true;
9747 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9748 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9753 scaler_state
->scaler_id
= id
;
9755 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9757 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9762 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9763 struct intel_initial_plane_config
*plane_config
)
9765 struct drm_device
*dev
= crtc
->base
.dev
;
9766 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9767 u32 val
, base
, offset
, stride_mult
, tiling
;
9768 int pipe
= crtc
->pipe
;
9769 int fourcc
, pixel_format
;
9770 unsigned int aligned_height
;
9771 struct drm_framebuffer
*fb
;
9772 struct intel_framebuffer
*intel_fb
;
9774 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9776 DRM_DEBUG_KMS("failed to alloc fb\n");
9780 fb
= &intel_fb
->base
;
9782 val
= I915_READ(PLANE_CTL(pipe
, 0));
9783 if (!(val
& PLANE_CTL_ENABLE
))
9786 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9787 fourcc
= skl_format_to_fourcc(pixel_format
,
9788 val
& PLANE_CTL_ORDER_RGBX
,
9789 val
& PLANE_CTL_ALPHA_MASK
);
9790 fb
->pixel_format
= fourcc
;
9791 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9793 tiling
= val
& PLANE_CTL_TILED_MASK
;
9795 case PLANE_CTL_TILED_LINEAR
:
9796 fb
->modifier
= DRM_FORMAT_MOD_NONE
;
9798 case PLANE_CTL_TILED_X
:
9799 plane_config
->tiling
= I915_TILING_X
;
9800 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
9802 case PLANE_CTL_TILED_Y
:
9803 fb
->modifier
= I915_FORMAT_MOD_Y_TILED
;
9805 case PLANE_CTL_TILED_YF
:
9806 fb
->modifier
= I915_FORMAT_MOD_Yf_TILED
;
9809 MISSING_CASE(tiling
);
9813 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9814 plane_config
->base
= base
;
9816 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9818 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9819 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9820 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9822 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9823 stride_mult
= intel_fb_stride_alignment(dev_priv
, fb
->modifier
,
9825 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9827 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9831 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9833 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9834 pipe_name(pipe
), fb
->width
, fb
->height
,
9835 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9836 plane_config
->size
);
9838 plane_config
->fb
= intel_fb
;
9845 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9846 struct intel_crtc_state
*pipe_config
)
9848 struct drm_device
*dev
= crtc
->base
.dev
;
9849 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9852 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9854 if (tmp
& PF_ENABLE
) {
9855 pipe_config
->pch_pfit
.enabled
= true;
9856 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9857 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9859 /* We currently do not free assignements of panel fitters on
9860 * ivb/hsw (since we don't use the higher upscaling modes which
9861 * differentiates them) so just WARN about this case for now. */
9862 if (IS_GEN7(dev_priv
)) {
9863 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9864 PF_PIPE_SEL_IVB(crtc
->pipe
));
9870 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9871 struct intel_initial_plane_config
*plane_config
)
9873 struct drm_device
*dev
= crtc
->base
.dev
;
9874 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9875 u32 val
, base
, offset
;
9876 int pipe
= crtc
->pipe
;
9877 int fourcc
, pixel_format
;
9878 unsigned int aligned_height
;
9879 struct drm_framebuffer
*fb
;
9880 struct intel_framebuffer
*intel_fb
;
9882 val
= I915_READ(DSPCNTR(pipe
));
9883 if (!(val
& DISPLAY_PLANE_ENABLE
))
9886 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9888 DRM_DEBUG_KMS("failed to alloc fb\n");
9892 fb
= &intel_fb
->base
;
9894 if (INTEL_GEN(dev_priv
) >= 4) {
9895 if (val
& DISPPLANE_TILED
) {
9896 plane_config
->tiling
= I915_TILING_X
;
9897 fb
->modifier
= I915_FORMAT_MOD_X_TILED
;
9901 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9902 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9903 fb
->pixel_format
= fourcc
;
9904 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9906 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9907 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
9908 offset
= I915_READ(DSPOFFSET(pipe
));
9910 if (plane_config
->tiling
)
9911 offset
= I915_READ(DSPTILEOFF(pipe
));
9913 offset
= I915_READ(DSPLINOFF(pipe
));
9915 plane_config
->base
= base
;
9917 val
= I915_READ(PIPESRC(pipe
));
9918 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9919 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9921 val
= I915_READ(DSPSTRIDE(pipe
));
9922 fb
->pitches
[0] = val
& 0xffffffc0;
9924 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9928 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9930 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9931 pipe_name(pipe
), fb
->width
, fb
->height
,
9932 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9933 plane_config
->size
);
9935 plane_config
->fb
= intel_fb
;
9938 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9939 struct intel_crtc_state
*pipe_config
)
9941 struct drm_device
*dev
= crtc
->base
.dev
;
9942 struct drm_i915_private
*dev_priv
= to_i915(dev
);
9943 enum intel_display_power_domain power_domain
;
9947 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
9948 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
9951 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9952 pipe_config
->shared_dpll
= NULL
;
9955 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9956 if (!(tmp
& PIPECONF_ENABLE
))
9959 switch (tmp
& PIPECONF_BPC_MASK
) {
9961 pipe_config
->pipe_bpp
= 18;
9964 pipe_config
->pipe_bpp
= 24;
9966 case PIPECONF_10BPC
:
9967 pipe_config
->pipe_bpp
= 30;
9969 case PIPECONF_12BPC
:
9970 pipe_config
->pipe_bpp
= 36;
9976 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9977 pipe_config
->limited_color_range
= true;
9979 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9980 struct intel_shared_dpll
*pll
;
9981 enum intel_dpll_id pll_id
;
9983 pipe_config
->has_pch_encoder
= true;
9985 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9986 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9987 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9989 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9991 if (HAS_PCH_IBX(dev_priv
)) {
9993 * The pipe->pch transcoder and pch transcoder->pll
9996 pll_id
= (enum intel_dpll_id
) crtc
->pipe
;
9998 tmp
= I915_READ(PCH_DPLL_SEL
);
9999 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
10000 pll_id
= DPLL_ID_PCH_PLL_B
;
10002 pll_id
= DPLL_ID_PCH_PLL_A
;
10005 pipe_config
->shared_dpll
=
10006 intel_get_shared_dpll_by_id(dev_priv
, pll_id
);
10007 pll
= pipe_config
->shared_dpll
;
10009 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
10010 &pipe_config
->dpll_hw_state
));
10012 tmp
= pipe_config
->dpll_hw_state
.dpll
;
10013 pipe_config
->pixel_multiplier
=
10014 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
10015 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
10017 ironlake_pch_clock_get(crtc
, pipe_config
);
10019 pipe_config
->pixel_multiplier
= 1;
10022 intel_get_pipe_timings(crtc
, pipe_config
);
10023 intel_get_pipe_src_size(crtc
, pipe_config
);
10025 ironlake_get_pfit_config(crtc
, pipe_config
);
10030 intel_display_power_put(dev_priv
, power_domain
);
10035 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
10037 struct drm_device
*dev
= &dev_priv
->drm
;
10038 struct intel_crtc
*crtc
;
10040 for_each_intel_crtc(dev
, crtc
)
10041 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
10042 pipe_name(crtc
->pipe
));
10044 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
10045 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
10046 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
10047 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
10048 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON
, "Panel power on\n");
10049 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
10050 "CPU PWM1 enabled\n");
10051 if (IS_HASWELL(dev_priv
))
10052 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
10053 "CPU PWM2 enabled\n");
10054 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
10055 "PCH PWM1 enabled\n");
10056 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
10057 "Utility pin enabled\n");
10058 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
10061 * In theory we can still leave IRQs enabled, as long as only the HPD
10062 * interrupts remain enabled. We used to check for that, but since it's
10063 * gen-specific and since we only disable LCPLL after we fully disable
10064 * the interrupts, the check below should be enough.
10066 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
10069 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
10071 if (IS_HASWELL(dev_priv
))
10072 return I915_READ(D_COMP_HSW
);
10074 return I915_READ(D_COMP_BDW
);
10077 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
10079 if (IS_HASWELL(dev_priv
)) {
10080 mutex_lock(&dev_priv
->rps
.hw_lock
);
10081 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
10083 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10084 mutex_unlock(&dev_priv
->rps
.hw_lock
);
10086 I915_WRITE(D_COMP_BDW
, val
);
10087 POSTING_READ(D_COMP_BDW
);
10092 * This function implements pieces of two sequences from BSpec:
10093 * - Sequence for display software to disable LCPLL
10094 * - Sequence for display software to allow package C8+
10095 * The steps implemented here are just the steps that actually touch the LCPLL
10096 * register. Callers should take care of disabling all the display engine
10097 * functions, doing the mode unset, fixing interrupts, etc.
10099 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
10100 bool switch_to_fclk
, bool allow_power_down
)
10104 assert_can_disable_lcpll(dev_priv
);
10106 val
= I915_READ(LCPLL_CTL
);
10108 if (switch_to_fclk
) {
10109 val
|= LCPLL_CD_SOURCE_FCLK
;
10110 I915_WRITE(LCPLL_CTL
, val
);
10112 if (wait_for_us(I915_READ(LCPLL_CTL
) &
10113 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
10114 DRM_ERROR("Switching to FCLK failed\n");
10116 val
= I915_READ(LCPLL_CTL
);
10119 val
|= LCPLL_PLL_DISABLE
;
10120 I915_WRITE(LCPLL_CTL
, val
);
10121 POSTING_READ(LCPLL_CTL
);
10123 if (intel_wait_for_register(dev_priv
, LCPLL_CTL
, LCPLL_PLL_LOCK
, 0, 1))
10124 DRM_ERROR("LCPLL still locked\n");
10126 val
= hsw_read_dcomp(dev_priv
);
10127 val
|= D_COMP_COMP_DISABLE
;
10128 hsw_write_dcomp(dev_priv
, val
);
10131 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
10133 DRM_ERROR("D_COMP RCOMP still in progress\n");
10135 if (allow_power_down
) {
10136 val
= I915_READ(LCPLL_CTL
);
10137 val
|= LCPLL_POWER_DOWN_ALLOW
;
10138 I915_WRITE(LCPLL_CTL
, val
);
10139 POSTING_READ(LCPLL_CTL
);
10144 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10147 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
10151 val
= I915_READ(LCPLL_CTL
);
10153 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
10154 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
10158 * Make sure we're not on PC8 state before disabling PC8, otherwise
10159 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10161 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
10163 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
10164 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
10165 I915_WRITE(LCPLL_CTL
, val
);
10166 POSTING_READ(LCPLL_CTL
);
10169 val
= hsw_read_dcomp(dev_priv
);
10170 val
|= D_COMP_COMP_FORCE
;
10171 val
&= ~D_COMP_COMP_DISABLE
;
10172 hsw_write_dcomp(dev_priv
, val
);
10174 val
= I915_READ(LCPLL_CTL
);
10175 val
&= ~LCPLL_PLL_DISABLE
;
10176 I915_WRITE(LCPLL_CTL
, val
);
10178 if (intel_wait_for_register(dev_priv
,
10179 LCPLL_CTL
, LCPLL_PLL_LOCK
, LCPLL_PLL_LOCK
,
10181 DRM_ERROR("LCPLL not locked yet\n");
10183 if (val
& LCPLL_CD_SOURCE_FCLK
) {
10184 val
= I915_READ(LCPLL_CTL
);
10185 val
&= ~LCPLL_CD_SOURCE_FCLK
;
10186 I915_WRITE(LCPLL_CTL
, val
);
10188 if (wait_for_us((I915_READ(LCPLL_CTL
) &
10189 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
10190 DRM_ERROR("Switching back to LCPLL failed\n");
10193 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
10194 intel_update_cdclk(dev_priv
);
10198 * Package states C8 and deeper are really deep PC states that can only be
10199 * reached when all the devices on the system allow it, so even if the graphics
10200 * device allows PC8+, it doesn't mean the system will actually get to these
10201 * states. Our driver only allows PC8+ when going into runtime PM.
10203 * The requirements for PC8+ are that all the outputs are disabled, the power
10204 * well is disabled and most interrupts are disabled, and these are also
10205 * requirements for runtime PM. When these conditions are met, we manually do
10206 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10207 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10208 * hang the machine.
10210 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10211 * the state of some registers, so when we come back from PC8+ we need to
10212 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10213 * need to take care of the registers kept by RC6. Notice that this happens even
10214 * if we don't put the device in PCI D3 state (which is what currently happens
10215 * because of the runtime PM support).
10217 * For more, read "Display Sequences for Package C8" on the hardware
10220 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
10224 DRM_DEBUG_KMS("Enabling package C8+\n");
10226 if (HAS_PCH_LPT_LP(dev_priv
)) {
10227 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
10228 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
10229 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
10232 lpt_disable_clkout_dp(dev_priv
);
10233 hsw_disable_lcpll(dev_priv
, true, true);
10236 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
10240 DRM_DEBUG_KMS("Disabling package C8+\n");
10242 hsw_restore_lcpll(dev_priv
);
10243 lpt_init_pch_refclk(dev_priv
);
10245 if (HAS_PCH_LPT_LP(dev_priv
)) {
10246 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
10247 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
10248 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
10252 static void bxt_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
10254 struct drm_device
*dev
= old_state
->dev
;
10255 struct intel_atomic_state
*old_intel_state
=
10256 to_intel_atomic_state(old_state
);
10257 unsigned int req_cdclk
= old_intel_state
->dev_cdclk
;
10259 bxt_set_cdclk(to_i915(dev
), req_cdclk
);
10262 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state
*crtc_state
,
10265 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->base
.crtc
->dev
);
10267 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10268 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
10269 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
10271 /* BSpec says "Do not use DisplayPort with CDCLK less than
10272 * 432 MHz, audio enabled, port width x4, and link rate
10273 * HBR2 (5.4 GHz), or else there may be audio corruption or
10274 * screen corruption."
10276 if (intel_crtc_has_dp_encoder(crtc_state
) &&
10277 crtc_state
->has_audio
&&
10278 crtc_state
->port_clock
>= 540000 &&
10279 crtc_state
->lane_count
== 4)
10280 pixel_rate
= max(432000, pixel_rate
);
10285 /* compute the max rate for new configuration */
10286 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
)
10288 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
10289 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
10290 struct drm_crtc
*crtc
;
10291 struct drm_crtc_state
*cstate
;
10292 struct intel_crtc_state
*crtc_state
;
10293 unsigned max_pixel_rate
= 0, i
;
10296 memcpy(intel_state
->min_pixclk
, dev_priv
->min_pixclk
,
10297 sizeof(intel_state
->min_pixclk
));
10299 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
10302 crtc_state
= to_intel_crtc_state(cstate
);
10303 if (!crtc_state
->base
.enable
) {
10304 intel_state
->min_pixclk
[i
] = 0;
10308 pixel_rate
= ilk_pipe_pixel_rate(crtc_state
);
10310 if (IS_BROADWELL(dev_priv
) || IS_GEN9(dev_priv
))
10311 pixel_rate
= bdw_adjust_min_pipe_pixel_rate(crtc_state
,
10314 intel_state
->min_pixclk
[i
] = pixel_rate
;
10317 for_each_pipe(dev_priv
, pipe
)
10318 max_pixel_rate
= max(intel_state
->min_pixclk
[pipe
], max_pixel_rate
);
10320 return max_pixel_rate
;
10323 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
10325 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10326 uint32_t val
, data
;
10329 if (WARN((I915_READ(LCPLL_CTL
) &
10330 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
10331 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
10332 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
10333 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
10334 "trying to change cdclk frequency with cdclk not enabled\n"))
10337 mutex_lock(&dev_priv
->rps
.hw_lock
);
10338 ret
= sandybridge_pcode_write(dev_priv
,
10339 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
10340 mutex_unlock(&dev_priv
->rps
.hw_lock
);
10342 DRM_ERROR("failed to inform pcode about cdclk change\n");
10346 val
= I915_READ(LCPLL_CTL
);
10347 val
|= LCPLL_CD_SOURCE_FCLK
;
10348 I915_WRITE(LCPLL_CTL
, val
);
10350 if (wait_for_us(I915_READ(LCPLL_CTL
) &
10351 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
10352 DRM_ERROR("Switching to FCLK failed\n");
10354 val
= I915_READ(LCPLL_CTL
);
10355 val
&= ~LCPLL_CLK_FREQ_MASK
;
10359 val
|= LCPLL_CLK_FREQ_450
;
10363 val
|= LCPLL_CLK_FREQ_54O_BDW
;
10367 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
10371 val
|= LCPLL_CLK_FREQ_675_BDW
;
10375 WARN(1, "invalid cdclk frequency\n");
10379 I915_WRITE(LCPLL_CTL
, val
);
10381 val
= I915_READ(LCPLL_CTL
);
10382 val
&= ~LCPLL_CD_SOURCE_FCLK
;
10383 I915_WRITE(LCPLL_CTL
, val
);
10385 if (wait_for_us((I915_READ(LCPLL_CTL
) &
10386 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
10387 DRM_ERROR("Switching back to LCPLL failed\n");
10389 mutex_lock(&dev_priv
->rps
.hw_lock
);
10390 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
10391 mutex_unlock(&dev_priv
->rps
.hw_lock
);
10393 I915_WRITE(CDCLK_FREQ
, DIV_ROUND_CLOSEST(cdclk
, 1000) - 1);
10395 intel_update_cdclk(dev_priv
);
10397 WARN(cdclk
!= dev_priv
->cdclk_freq
,
10398 "cdclk requested %d kHz but got %d kHz\n",
10399 cdclk
, dev_priv
->cdclk_freq
);
10402 static int broadwell_calc_cdclk(int max_pixclk
)
10404 if (max_pixclk
> 540000)
10406 else if (max_pixclk
> 450000)
10408 else if (max_pixclk
> 337500)
10414 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state
*state
)
10416 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
10417 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
10418 int max_pixclk
= ilk_max_pixel_rate(state
);
10422 * FIXME should also account for plane ratio
10423 * once 64bpp pixel formats are supported.
10425 cdclk
= broadwell_calc_cdclk(max_pixclk
);
10427 if (cdclk
> dev_priv
->max_cdclk_freq
) {
10428 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10429 cdclk
, dev_priv
->max_cdclk_freq
);
10433 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
10434 if (!intel_state
->active_crtcs
)
10435 intel_state
->dev_cdclk
= broadwell_calc_cdclk(0);
10440 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
10442 struct drm_device
*dev
= old_state
->dev
;
10443 struct intel_atomic_state
*old_intel_state
=
10444 to_intel_atomic_state(old_state
);
10445 unsigned req_cdclk
= old_intel_state
->dev_cdclk
;
10447 broadwell_set_cdclk(dev
, req_cdclk
);
10450 static int skl_modeset_calc_cdclk(struct drm_atomic_state
*state
)
10452 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
10453 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
10454 const int max_pixclk
= ilk_max_pixel_rate(state
);
10455 int vco
= intel_state
->cdclk_pll_vco
;
10459 * FIXME should also account for plane ratio
10460 * once 64bpp pixel formats are supported.
10462 cdclk
= skl_calc_cdclk(max_pixclk
, vco
);
10465 * FIXME move the cdclk caclulation to
10466 * compute_config() so we can fail gracegully.
10468 if (cdclk
> dev_priv
->max_cdclk_freq
) {
10469 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10470 cdclk
, dev_priv
->max_cdclk_freq
);
10471 cdclk
= dev_priv
->max_cdclk_freq
;
10474 intel_state
->cdclk
= intel_state
->dev_cdclk
= cdclk
;
10475 if (!intel_state
->active_crtcs
)
10476 intel_state
->dev_cdclk
= skl_calc_cdclk(0, vco
);
10481 static void skl_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
10483 struct drm_i915_private
*dev_priv
= to_i915(old_state
->dev
);
10484 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(old_state
);
10485 unsigned int req_cdclk
= intel_state
->dev_cdclk
;
10486 unsigned int req_vco
= intel_state
->cdclk_pll_vco
;
10488 skl_set_cdclk(dev_priv
, req_cdclk
, req_vco
);
10491 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
10492 struct intel_crtc_state
*crtc_state
)
10494 if (!intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
)) {
10495 if (!intel_ddi_pll_select(crtc
, crtc_state
))
10499 crtc
->lowfreq_avail
= false;
10504 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
10506 struct intel_crtc_state
*pipe_config
)
10508 enum intel_dpll_id id
;
10512 id
= DPLL_ID_SKL_DPLL0
;
10515 id
= DPLL_ID_SKL_DPLL1
;
10518 id
= DPLL_ID_SKL_DPLL2
;
10521 DRM_ERROR("Incorrect port type\n");
10525 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
10528 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
10530 struct intel_crtc_state
*pipe_config
)
10532 enum intel_dpll_id id
;
10535 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
10536 id
= temp
>> (port
* 3 + 1);
10538 if (WARN_ON(id
< SKL_DPLL0
|| id
> SKL_DPLL3
))
10541 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
10544 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
10546 struct intel_crtc_state
*pipe_config
)
10548 enum intel_dpll_id id
;
10549 uint32_t ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
10551 switch (ddi_pll_sel
) {
10552 case PORT_CLK_SEL_WRPLL1
:
10553 id
= DPLL_ID_WRPLL1
;
10555 case PORT_CLK_SEL_WRPLL2
:
10556 id
= DPLL_ID_WRPLL2
;
10558 case PORT_CLK_SEL_SPLL
:
10561 case PORT_CLK_SEL_LCPLL_810
:
10562 id
= DPLL_ID_LCPLL_810
;
10564 case PORT_CLK_SEL_LCPLL_1350
:
10565 id
= DPLL_ID_LCPLL_1350
;
10567 case PORT_CLK_SEL_LCPLL_2700
:
10568 id
= DPLL_ID_LCPLL_2700
;
10571 MISSING_CASE(ddi_pll_sel
);
10573 case PORT_CLK_SEL_NONE
:
10577 pipe_config
->shared_dpll
= intel_get_shared_dpll_by_id(dev_priv
, id
);
10580 static bool hsw_get_transcoder_state(struct intel_crtc
*crtc
,
10581 struct intel_crtc_state
*pipe_config
,
10582 unsigned long *power_domain_mask
)
10584 struct drm_device
*dev
= crtc
->base
.dev
;
10585 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10586 enum intel_display_power_domain power_domain
;
10590 * The pipe->transcoder mapping is fixed with the exception of the eDP
10591 * transcoder handled below.
10593 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
10596 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10597 * consistency and less surprising code; it's in always on power).
10599 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
10600 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
10601 enum pipe trans_edp_pipe
;
10602 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
10604 WARN(1, "unknown pipe linked to edp transcoder\n");
10605 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
10606 case TRANS_DDI_EDP_INPUT_A_ON
:
10607 trans_edp_pipe
= PIPE_A
;
10609 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
10610 trans_edp_pipe
= PIPE_B
;
10612 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
10613 trans_edp_pipe
= PIPE_C
;
10617 if (trans_edp_pipe
== crtc
->pipe
)
10618 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
10621 power_domain
= POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
);
10622 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10624 *power_domain_mask
|= BIT(power_domain
);
10626 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
10628 return tmp
& PIPECONF_ENABLE
;
10631 static bool bxt_get_dsi_transcoder_state(struct intel_crtc
*crtc
,
10632 struct intel_crtc_state
*pipe_config
,
10633 unsigned long *power_domain_mask
)
10635 struct drm_device
*dev
= crtc
->base
.dev
;
10636 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10637 enum intel_display_power_domain power_domain
;
10639 enum transcoder cpu_transcoder
;
10642 for_each_port_masked(port
, BIT(PORT_A
) | BIT(PORT_C
)) {
10643 if (port
== PORT_A
)
10644 cpu_transcoder
= TRANSCODER_DSI_A
;
10646 cpu_transcoder
= TRANSCODER_DSI_C
;
10648 power_domain
= POWER_DOMAIN_TRANSCODER(cpu_transcoder
);
10649 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10651 *power_domain_mask
|= BIT(power_domain
);
10654 * The PLL needs to be enabled with a valid divider
10655 * configuration, otherwise accessing DSI registers will hang
10656 * the machine. See BSpec North Display Engine
10657 * registers/MIPI[BXT]. We can break out here early, since we
10658 * need the same DSI PLL to be enabled for both DSI ports.
10660 if (!intel_dsi_pll_is_enabled(dev_priv
))
10663 /* XXX: this works for video mode only */
10664 tmp
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
10665 if (!(tmp
& DPI_ENABLE
))
10668 tmp
= I915_READ(MIPI_CTRL(port
));
10669 if ((tmp
& BXT_PIPE_SELECT_MASK
) != BXT_PIPE_SELECT(crtc
->pipe
))
10672 pipe_config
->cpu_transcoder
= cpu_transcoder
;
10676 return transcoder_is_dsi(pipe_config
->cpu_transcoder
);
10679 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
10680 struct intel_crtc_state
*pipe_config
)
10682 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10683 struct intel_shared_dpll
*pll
;
10687 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
10689 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
10691 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
10692 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
10693 else if (IS_GEN9_LP(dev_priv
))
10694 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
10696 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
10698 pll
= pipe_config
->shared_dpll
;
10700 WARN_ON(!pll
->funcs
.get_hw_state(dev_priv
, pll
,
10701 &pipe_config
->dpll_hw_state
));
10705 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10706 * DDI E. So just check whether this pipe is wired to DDI E and whether
10707 * the PCH transcoder is on.
10709 if (INTEL_GEN(dev_priv
) < 9 &&
10710 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
10711 pipe_config
->has_pch_encoder
= true;
10713 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
10714 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
10715 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
10717 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
10721 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
10722 struct intel_crtc_state
*pipe_config
)
10724 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
10725 enum intel_display_power_domain power_domain
;
10726 unsigned long power_domain_mask
;
10729 power_domain
= POWER_DOMAIN_PIPE(crtc
->pipe
);
10730 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
10732 power_domain_mask
= BIT(power_domain
);
10734 pipe_config
->shared_dpll
= NULL
;
10736 active
= hsw_get_transcoder_state(crtc
, pipe_config
, &power_domain_mask
);
10738 if (IS_GEN9_LP(dev_priv
) &&
10739 bxt_get_dsi_transcoder_state(crtc
, pipe_config
, &power_domain_mask
)) {
10747 if (!transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10748 haswell_get_ddi_port_state(crtc
, pipe_config
);
10749 intel_get_pipe_timings(crtc
, pipe_config
);
10752 intel_get_pipe_src_size(crtc
, pipe_config
);
10754 pipe_config
->gamma_mode
=
10755 I915_READ(GAMMA_MODE(crtc
->pipe
)) & GAMMA_MODE_MODE_MASK
;
10757 if (INTEL_GEN(dev_priv
) >= 9) {
10758 skl_init_scalers(dev_priv
, crtc
, pipe_config
);
10760 pipe_config
->scaler_state
.scaler_id
= -1;
10761 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
10764 power_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
10765 if (intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
10766 power_domain_mask
|= BIT(power_domain
);
10767 if (INTEL_GEN(dev_priv
) >= 9)
10768 skylake_get_pfit_config(crtc
, pipe_config
);
10770 ironlake_get_pfit_config(crtc
, pipe_config
);
10773 if (IS_HASWELL(dev_priv
))
10774 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
10775 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
10777 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
&&
10778 !transcoder_is_dsi(pipe_config
->cpu_transcoder
)) {
10779 pipe_config
->pixel_multiplier
=
10780 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
10782 pipe_config
->pixel_multiplier
= 1;
10786 for_each_power_domain(power_domain
, power_domain_mask
)
10787 intel_display_power_put(dev_priv
, power_domain
);
10792 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10793 const struct intel_plane_state
*plane_state
)
10795 struct drm_device
*dev
= crtc
->dev
;
10796 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10797 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10798 uint32_t cntl
= 0, size
= 0;
10800 if (plane_state
&& plane_state
->base
.visible
) {
10801 unsigned int width
= plane_state
->base
.crtc_w
;
10802 unsigned int height
= plane_state
->base
.crtc_h
;
10803 unsigned int stride
= roundup_pow_of_two(width
) * 4;
10807 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10818 cntl
|= CURSOR_ENABLE
|
10819 CURSOR_GAMMA_ENABLE
|
10820 CURSOR_FORMAT_ARGB
|
10821 CURSOR_STRIDE(stride
);
10823 size
= (height
<< 12) | width
;
10826 if (intel_crtc
->cursor_cntl
!= 0 &&
10827 (intel_crtc
->cursor_base
!= base
||
10828 intel_crtc
->cursor_size
!= size
||
10829 intel_crtc
->cursor_cntl
!= cntl
)) {
10830 /* On these chipsets we can only modify the base/size/stride
10831 * whilst the cursor is disabled.
10833 I915_WRITE(CURCNTR(PIPE_A
), 0);
10834 POSTING_READ(CURCNTR(PIPE_A
));
10835 intel_crtc
->cursor_cntl
= 0;
10838 if (intel_crtc
->cursor_base
!= base
) {
10839 I915_WRITE(CURBASE(PIPE_A
), base
);
10840 intel_crtc
->cursor_base
= base
;
10843 if (intel_crtc
->cursor_size
!= size
) {
10844 I915_WRITE(CURSIZE
, size
);
10845 intel_crtc
->cursor_size
= size
;
10848 if (intel_crtc
->cursor_cntl
!= cntl
) {
10849 I915_WRITE(CURCNTR(PIPE_A
), cntl
);
10850 POSTING_READ(CURCNTR(PIPE_A
));
10851 intel_crtc
->cursor_cntl
= cntl
;
10855 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
,
10856 const struct intel_plane_state
*plane_state
)
10858 struct drm_device
*dev
= crtc
->dev
;
10859 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10860 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10861 int pipe
= intel_crtc
->pipe
;
10864 if (plane_state
&& plane_state
->base
.visible
) {
10865 cntl
= MCURSOR_GAMMA_ENABLE
;
10866 switch (plane_state
->base
.crtc_w
) {
10868 cntl
|= CURSOR_MODE_64_ARGB_AX
;
10871 cntl
|= CURSOR_MODE_128_ARGB_AX
;
10874 cntl
|= CURSOR_MODE_256_ARGB_AX
;
10877 MISSING_CASE(plane_state
->base
.crtc_w
);
10880 cntl
|= pipe
<< 28; /* Connect to correct pipe */
10882 if (HAS_DDI(dev_priv
))
10883 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
10885 if (plane_state
->base
.rotation
& DRM_ROTATE_180
)
10886 cntl
|= CURSOR_ROTATE_180
;
10889 if (intel_crtc
->cursor_cntl
!= cntl
) {
10890 I915_WRITE(CURCNTR(pipe
), cntl
);
10891 POSTING_READ(CURCNTR(pipe
));
10892 intel_crtc
->cursor_cntl
= cntl
;
10895 /* and commit changes on next vblank */
10896 I915_WRITE(CURBASE(pipe
), base
);
10897 POSTING_READ(CURBASE(pipe
));
10899 intel_crtc
->cursor_base
= base
;
10902 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10903 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
10904 const struct intel_plane_state
*plane_state
)
10906 struct drm_device
*dev
= crtc
->dev
;
10907 struct drm_i915_private
*dev_priv
= to_i915(dev
);
10908 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10909 int pipe
= intel_crtc
->pipe
;
10910 u32 base
= intel_crtc
->cursor_addr
;
10914 int x
= plane_state
->base
.crtc_x
;
10915 int y
= plane_state
->base
.crtc_y
;
10918 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10921 pos
|= x
<< CURSOR_X_SHIFT
;
10924 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10927 pos
|= y
<< CURSOR_Y_SHIFT
;
10929 /* ILK+ do this automagically */
10930 if (HAS_GMCH_DISPLAY(dev_priv
) &&
10931 plane_state
->base
.rotation
& DRM_ROTATE_180
) {
10932 base
+= (plane_state
->base
.crtc_h
*
10933 plane_state
->base
.crtc_w
- 1) * 4;
10937 I915_WRITE(CURPOS(pipe
), pos
);
10939 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
))
10940 i845_update_cursor(crtc
, base
, plane_state
);
10942 i9xx_update_cursor(crtc
, base
, plane_state
);
10945 static bool cursor_size_ok(struct drm_i915_private
*dev_priv
,
10946 uint32_t width
, uint32_t height
)
10948 if (width
== 0 || height
== 0)
10952 * 845g/865g are special in that they are only limited by
10953 * the width of their cursors, the height is arbitrary up to
10954 * the precision of the register. Everything else requires
10955 * square cursors, limited to a few power-of-two sizes.
10957 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
10958 if ((width
& 63) != 0)
10961 if (width
> (IS_I845G(dev_priv
) ? 64 : 512))
10967 switch (width
| height
) {
10970 if (IS_GEN2(dev_priv
))
10982 /* VESA 640x480x72Hz mode to set on the pipe */
10983 static struct drm_display_mode load_detect_mode
= {
10984 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10985 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10988 struct drm_framebuffer
*
10989 __intel_framebuffer_create(struct drm_device
*dev
,
10990 struct drm_mode_fb_cmd2
*mode_cmd
,
10991 struct drm_i915_gem_object
*obj
)
10993 struct intel_framebuffer
*intel_fb
;
10996 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10998 return ERR_PTR(-ENOMEM
);
11000 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
11004 return &intel_fb
->base
;
11008 return ERR_PTR(ret
);
11011 static struct drm_framebuffer
*
11012 intel_framebuffer_create(struct drm_device
*dev
,
11013 struct drm_mode_fb_cmd2
*mode_cmd
,
11014 struct drm_i915_gem_object
*obj
)
11016 struct drm_framebuffer
*fb
;
11019 ret
= i915_mutex_lock_interruptible(dev
);
11021 return ERR_PTR(ret
);
11022 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
11023 mutex_unlock(&dev
->struct_mutex
);
11029 intel_framebuffer_pitch_for_width(int width
, int bpp
)
11031 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
11032 return ALIGN(pitch
, 64);
11036 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
11038 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
11039 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
11042 static struct drm_framebuffer
*
11043 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
11044 struct drm_display_mode
*mode
,
11045 int depth
, int bpp
)
11047 struct drm_framebuffer
*fb
;
11048 struct drm_i915_gem_object
*obj
;
11049 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
11051 obj
= i915_gem_object_create(to_i915(dev
),
11052 intel_framebuffer_size_for_mode(mode
, bpp
));
11054 return ERR_CAST(obj
);
11056 mode_cmd
.width
= mode
->hdisplay
;
11057 mode_cmd
.height
= mode
->vdisplay
;
11058 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
11060 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
11062 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
11064 i915_gem_object_put(obj
);
11069 static struct drm_framebuffer
*
11070 mode_fits_in_fbdev(struct drm_device
*dev
,
11071 struct drm_display_mode
*mode
)
11073 #ifdef CONFIG_DRM_FBDEV_EMULATION
11074 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11075 struct drm_i915_gem_object
*obj
;
11076 struct drm_framebuffer
*fb
;
11078 if (!dev_priv
->fbdev
)
11081 if (!dev_priv
->fbdev
->fb
)
11084 obj
= dev_priv
->fbdev
->fb
->obj
;
11087 fb
= &dev_priv
->fbdev
->fb
->base
;
11088 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
11089 fb
->bits_per_pixel
))
11092 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
11095 drm_framebuffer_reference(fb
);
11102 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
11103 struct drm_crtc
*crtc
,
11104 struct drm_display_mode
*mode
,
11105 struct drm_framebuffer
*fb
,
11108 struct drm_plane_state
*plane_state
;
11109 int hdisplay
, vdisplay
;
11112 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
11113 if (IS_ERR(plane_state
))
11114 return PTR_ERR(plane_state
);
11117 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
11119 hdisplay
= vdisplay
= 0;
11121 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
11124 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11125 plane_state
->crtc_x
= 0;
11126 plane_state
->crtc_y
= 0;
11127 plane_state
->crtc_w
= hdisplay
;
11128 plane_state
->crtc_h
= vdisplay
;
11129 plane_state
->src_x
= x
<< 16;
11130 plane_state
->src_y
= y
<< 16;
11131 plane_state
->src_w
= hdisplay
<< 16;
11132 plane_state
->src_h
= vdisplay
<< 16;
11137 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
11138 struct drm_display_mode
*mode
,
11139 struct intel_load_detect_pipe
*old
,
11140 struct drm_modeset_acquire_ctx
*ctx
)
11142 struct intel_crtc
*intel_crtc
;
11143 struct intel_encoder
*intel_encoder
=
11144 intel_attached_encoder(connector
);
11145 struct drm_crtc
*possible_crtc
;
11146 struct drm_encoder
*encoder
= &intel_encoder
->base
;
11147 struct drm_crtc
*crtc
= NULL
;
11148 struct drm_device
*dev
= encoder
->dev
;
11149 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11150 struct drm_framebuffer
*fb
;
11151 struct drm_mode_config
*config
= &dev
->mode_config
;
11152 struct drm_atomic_state
*state
= NULL
, *restore_state
= NULL
;
11153 struct drm_connector_state
*connector_state
;
11154 struct intel_crtc_state
*crtc_state
;
11157 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11158 connector
->base
.id
, connector
->name
,
11159 encoder
->base
.id
, encoder
->name
);
11161 old
->restore_state
= NULL
;
11164 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
11169 * Algorithm gets a little messy:
11171 * - if the connector already has an assigned crtc, use it (but make
11172 * sure it's on first)
11174 * - try to find the first unused crtc that can drive this connector,
11175 * and use that if we find one
11178 /* See if we already have a CRTC for this connector */
11179 if (connector
->state
->crtc
) {
11180 crtc
= connector
->state
->crtc
;
11182 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
11186 /* Make sure the crtc and connector are running */
11190 /* Find an unused one (if possible) */
11191 for_each_crtc(dev
, possible_crtc
) {
11193 if (!(encoder
->possible_crtcs
& (1 << i
)))
11196 ret
= drm_modeset_lock(&possible_crtc
->mutex
, ctx
);
11200 if (possible_crtc
->state
->enable
) {
11201 drm_modeset_unlock(&possible_crtc
->mutex
);
11205 crtc
= possible_crtc
;
11210 * If we didn't find an unused CRTC, don't use any.
11213 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11218 intel_crtc
= to_intel_crtc(crtc
);
11220 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
11224 state
= drm_atomic_state_alloc(dev
);
11225 restore_state
= drm_atomic_state_alloc(dev
);
11226 if (!state
|| !restore_state
) {
11231 state
->acquire_ctx
= ctx
;
11232 restore_state
->acquire_ctx
= ctx
;
11234 connector_state
= drm_atomic_get_connector_state(state
, connector
);
11235 if (IS_ERR(connector_state
)) {
11236 ret
= PTR_ERR(connector_state
);
11240 ret
= drm_atomic_set_crtc_for_connector(connector_state
, crtc
);
11244 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
11245 if (IS_ERR(crtc_state
)) {
11246 ret
= PTR_ERR(crtc_state
);
11250 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
11253 mode
= &load_detect_mode
;
11255 /* We need a framebuffer large enough to accommodate all accesses
11256 * that the plane may generate whilst we perform load detection.
11257 * We can not rely on the fbcon either being present (we get called
11258 * during its initialisation to detect all boot displays, or it may
11259 * not even exist) or that it is large enough to satisfy the
11262 fb
= mode_fits_in_fbdev(dev
, mode
);
11264 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11265 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
11267 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11269 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11273 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
11277 drm_framebuffer_unreference(fb
);
11279 ret
= drm_atomic_set_mode_for_crtc(&crtc_state
->base
, mode
);
11283 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state
, connector
));
11285 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state
, crtc
));
11287 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state
, crtc
->primary
));
11289 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret
);
11293 ret
= drm_atomic_commit(state
);
11295 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11299 old
->restore_state
= restore_state
;
11301 /* let the connector get through one full cycle before testing */
11302 intel_wait_for_vblank(dev_priv
, intel_crtc
->pipe
);
11307 drm_atomic_state_put(state
);
11310 if (restore_state
) {
11311 drm_atomic_state_put(restore_state
);
11312 restore_state
= NULL
;
11315 if (ret
== -EDEADLK
) {
11316 drm_modeset_backoff(ctx
);
11323 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
11324 struct intel_load_detect_pipe
*old
,
11325 struct drm_modeset_acquire_ctx
*ctx
)
11327 struct intel_encoder
*intel_encoder
=
11328 intel_attached_encoder(connector
);
11329 struct drm_encoder
*encoder
= &intel_encoder
->base
;
11330 struct drm_atomic_state
*state
= old
->restore_state
;
11333 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11334 connector
->base
.id
, connector
->name
,
11335 encoder
->base
.id
, encoder
->name
);
11340 ret
= drm_atomic_commit(state
);
11342 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret
);
11343 drm_atomic_state_put(state
);
11346 static int i9xx_pll_refclk(struct drm_device
*dev
,
11347 const struct intel_crtc_state
*pipe_config
)
11349 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11350 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
11352 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
11353 return dev_priv
->vbt
.lvds_ssc_freq
;
11354 else if (HAS_PCH_SPLIT(dev_priv
))
11356 else if (!IS_GEN2(dev_priv
))
11362 /* Returns the clock of the currently programmed mode of the given pipe. */
11363 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
11364 struct intel_crtc_state
*pipe_config
)
11366 struct drm_device
*dev
= crtc
->base
.dev
;
11367 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11368 int pipe
= pipe_config
->cpu_transcoder
;
11369 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
11373 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
11375 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
11376 fp
= pipe_config
->dpll_hw_state
.fp0
;
11378 fp
= pipe_config
->dpll_hw_state
.fp1
;
11380 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
11381 if (IS_PINEVIEW(dev_priv
)) {
11382 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
11383 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
11385 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
11386 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
11389 if (!IS_GEN2(dev_priv
)) {
11390 if (IS_PINEVIEW(dev_priv
))
11391 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
11392 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
11394 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
11395 DPLL_FPA01_P1_POST_DIV_SHIFT
);
11397 switch (dpll
& DPLL_MODE_MASK
) {
11398 case DPLLB_MODE_DAC_SERIAL
:
11399 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
11402 case DPLLB_MODE_LVDS
:
11403 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
11407 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11408 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
11412 if (IS_PINEVIEW(dev_priv
))
11413 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
11415 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
11417 u32 lvds
= IS_I830(dev_priv
) ? 0 : I915_READ(LVDS
);
11418 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
11421 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
11422 DPLL_FPA01_P1_POST_DIV_SHIFT
);
11424 if (lvds
& LVDS_CLKB_POWER_UP
)
11429 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
11432 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
11433 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
11435 if (dpll
& PLL_P2_DIVIDE_BY_4
)
11441 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
11445 * This value includes pixel_multiplier. We will use
11446 * port_clock to compute adjusted_mode.crtc_clock in the
11447 * encoder's get_config() function.
11449 pipe_config
->port_clock
= port_clock
;
11452 int intel_dotclock_calculate(int link_freq
,
11453 const struct intel_link_m_n
*m_n
)
11456 * The calculation for the data clock is:
11457 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11458 * But we want to avoid losing precison if possible, so:
11459 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11461 * and the link clock is simpler:
11462 * link_clock = (m * link_clock) / n
11468 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
11471 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
11472 struct intel_crtc_state
*pipe_config
)
11474 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
11476 /* read out port_clock from the DPLL */
11477 i9xx_crtc_clock_get(crtc
, pipe_config
);
11480 * In case there is an active pipe without active ports,
11481 * we may need some idea for the dotclock anyway.
11482 * Calculate one based on the FDI configuration.
11484 pipe_config
->base
.adjusted_mode
.crtc_clock
=
11485 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
11486 &pipe_config
->fdi_m_n
);
11489 /** Returns the currently programmed mode of the given pipe. */
11490 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
11491 struct drm_crtc
*crtc
)
11493 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11494 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11495 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
11496 struct drm_display_mode
*mode
;
11497 struct intel_crtc_state
*pipe_config
;
11498 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
11499 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
11500 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
11501 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
11502 enum pipe pipe
= intel_crtc
->pipe
;
11504 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
11508 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
11509 if (!pipe_config
) {
11515 * Construct a pipe_config sufficient for getting the clock info
11516 * back out of crtc_clock_get.
11518 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11519 * to use a real value here instead.
11521 pipe_config
->cpu_transcoder
= (enum transcoder
) pipe
;
11522 pipe_config
->pixel_multiplier
= 1;
11523 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
11524 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
11525 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
11526 i9xx_crtc_clock_get(intel_crtc
, pipe_config
);
11528 mode
->clock
= pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
11529 mode
->hdisplay
= (htot
& 0xffff) + 1;
11530 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
11531 mode
->hsync_start
= (hsync
& 0xffff) + 1;
11532 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
11533 mode
->vdisplay
= (vtot
& 0xffff) + 1;
11534 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
11535 mode
->vsync_start
= (vsync
& 0xffff) + 1;
11536 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
11538 drm_mode_set_name(mode
);
11540 kfree(pipe_config
);
11545 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
11547 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11548 struct drm_device
*dev
= crtc
->dev
;
11549 struct intel_flip_work
*work
;
11551 spin_lock_irq(&dev
->event_lock
);
11552 work
= intel_crtc
->flip_work
;
11553 intel_crtc
->flip_work
= NULL
;
11554 spin_unlock_irq(&dev
->event_lock
);
11557 cancel_work_sync(&work
->mmio_work
);
11558 cancel_work_sync(&work
->unpin_work
);
11562 drm_crtc_cleanup(crtc
);
11567 static void intel_unpin_work_fn(struct work_struct
*__work
)
11569 struct intel_flip_work
*work
=
11570 container_of(__work
, struct intel_flip_work
, unpin_work
);
11571 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
11572 struct drm_device
*dev
= crtc
->base
.dev
;
11573 struct drm_plane
*primary
= crtc
->base
.primary
;
11575 if (is_mmio_work(work
))
11576 flush_work(&work
->mmio_work
);
11578 mutex_lock(&dev
->struct_mutex
);
11579 intel_unpin_fb_obj(work
->old_fb
, primary
->state
->rotation
);
11580 i915_gem_object_put(work
->pending_flip_obj
);
11581 mutex_unlock(&dev
->struct_mutex
);
11583 i915_gem_request_put(work
->flip_queued_req
);
11585 intel_frontbuffer_flip_complete(to_i915(dev
),
11586 to_intel_plane(primary
)->frontbuffer_bit
);
11587 intel_fbc_post_update(crtc
);
11588 drm_framebuffer_unreference(work
->old_fb
);
11590 BUG_ON(atomic_read(&crtc
->unpin_work_count
) == 0);
11591 atomic_dec(&crtc
->unpin_work_count
);
11596 /* Is 'a' after or equal to 'b'? */
11597 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
11599 return !((a
- b
) & 0x80000000);
11602 static bool __pageflip_finished_cs(struct intel_crtc
*crtc
,
11603 struct intel_flip_work
*work
)
11605 struct drm_device
*dev
= crtc
->base
.dev
;
11606 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11608 if (abort_flip_on_reset(crtc
))
11612 * The relevant registers doen't exist on pre-ctg.
11613 * As the flip done interrupt doesn't trigger for mmio
11614 * flips on gmch platforms, a flip count check isn't
11615 * really needed there. But since ctg has the registers,
11616 * include it in the check anyway.
11618 if (INTEL_GEN(dev_priv
) < 5 && !IS_G4X(dev_priv
))
11622 * BDW signals flip done immediately if the plane
11623 * is disabled, even if the plane enable is already
11624 * armed to occur at the next vblank :(
11628 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11629 * used the same base address. In that case the mmio flip might
11630 * have completed, but the CS hasn't even executed the flip yet.
11632 * A flip count check isn't enough as the CS might have updated
11633 * the base address just after start of vblank, but before we
11634 * managed to process the interrupt. This means we'd complete the
11635 * CS flip too soon.
11637 * Combining both checks should get us a good enough result. It may
11638 * still happen that the CS flip has been executed, but has not
11639 * yet actually completed. But in case the base address is the same
11640 * anyway, we don't really care.
11642 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
11643 crtc
->flip_work
->gtt_offset
&&
11644 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc
->pipe
)),
11645 crtc
->flip_work
->flip_count
);
11649 __pageflip_finished_mmio(struct intel_crtc
*crtc
,
11650 struct intel_flip_work
*work
)
11653 * MMIO work completes when vblank is different from
11654 * flip_queued_vblank.
11656 * Reset counter value doesn't matter, this is handled by
11657 * i915_wait_request finishing early, so no need to handle
11660 return intel_crtc_get_vblank_counter(crtc
) != work
->flip_queued_vblank
;
11664 static bool pageflip_finished(struct intel_crtc
*crtc
,
11665 struct intel_flip_work
*work
)
11667 if (!atomic_read(&work
->pending
))
11672 if (is_mmio_work(work
))
11673 return __pageflip_finished_mmio(crtc
, work
);
11675 return __pageflip_finished_cs(crtc
, work
);
11678 void intel_finish_page_flip_cs(struct drm_i915_private
*dev_priv
, int pipe
)
11680 struct drm_device
*dev
= &dev_priv
->drm
;
11681 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
11682 struct intel_flip_work
*work
;
11683 unsigned long flags
;
11685 /* Ignore early vblank irqs */
11690 * This is called both by irq handlers and the reset code (to complete
11691 * lost pageflips) so needs the full irqsave spinlocks.
11693 spin_lock_irqsave(&dev
->event_lock
, flags
);
11694 work
= crtc
->flip_work
;
11696 if (work
!= NULL
&&
11697 !is_mmio_work(work
) &&
11698 pageflip_finished(crtc
, work
))
11699 page_flip_completed(crtc
);
11701 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11704 void intel_finish_page_flip_mmio(struct drm_i915_private
*dev_priv
, int pipe
)
11706 struct drm_device
*dev
= &dev_priv
->drm
;
11707 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
11708 struct intel_flip_work
*work
;
11709 unsigned long flags
;
11711 /* Ignore early vblank irqs */
11716 * This is called both by irq handlers and the reset code (to complete
11717 * lost pageflips) so needs the full irqsave spinlocks.
11719 spin_lock_irqsave(&dev
->event_lock
, flags
);
11720 work
= crtc
->flip_work
;
11722 if (work
!= NULL
&&
11723 is_mmio_work(work
) &&
11724 pageflip_finished(crtc
, work
))
11725 page_flip_completed(crtc
);
11727 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11730 static inline void intel_mark_page_flip_active(struct intel_crtc
*crtc
,
11731 struct intel_flip_work
*work
)
11733 work
->flip_queued_vblank
= intel_crtc_get_vblank_counter(crtc
);
11735 /* Ensure that the work item is consistent when activating it ... */
11736 smp_mb__before_atomic();
11737 atomic_set(&work
->pending
, 1);
11740 static int intel_gen2_queue_flip(struct drm_device
*dev
,
11741 struct drm_crtc
*crtc
,
11742 struct drm_framebuffer
*fb
,
11743 struct drm_i915_gem_object
*obj
,
11744 struct drm_i915_gem_request
*req
,
11747 struct intel_ring
*ring
= req
->ring
;
11748 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11752 ret
= intel_ring_begin(req
, 6);
11756 /* Can't queue multiple flips, so wait for the previous
11757 * one to finish before executing the next.
11759 if (intel_crtc
->plane
)
11760 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11762 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11763 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
11764 intel_ring_emit(ring
, MI_NOOP
);
11765 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11766 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11767 intel_ring_emit(ring
, fb
->pitches
[0]);
11768 intel_ring_emit(ring
, intel_crtc
->flip_work
->gtt_offset
);
11769 intel_ring_emit(ring
, 0); /* aux display base address, unused */
11774 static int intel_gen3_queue_flip(struct drm_device
*dev
,
11775 struct drm_crtc
*crtc
,
11776 struct drm_framebuffer
*fb
,
11777 struct drm_i915_gem_object
*obj
,
11778 struct drm_i915_gem_request
*req
,
11781 struct intel_ring
*ring
= req
->ring
;
11782 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11786 ret
= intel_ring_begin(req
, 6);
11790 if (intel_crtc
->plane
)
11791 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11793 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11794 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
11795 intel_ring_emit(ring
, MI_NOOP
);
11796 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
11797 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11798 intel_ring_emit(ring
, fb
->pitches
[0]);
11799 intel_ring_emit(ring
, intel_crtc
->flip_work
->gtt_offset
);
11800 intel_ring_emit(ring
, MI_NOOP
);
11805 static int intel_gen4_queue_flip(struct drm_device
*dev
,
11806 struct drm_crtc
*crtc
,
11807 struct drm_framebuffer
*fb
,
11808 struct drm_i915_gem_object
*obj
,
11809 struct drm_i915_gem_request
*req
,
11812 struct intel_ring
*ring
= req
->ring
;
11813 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11814 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11815 uint32_t pf
, pipesrc
;
11818 ret
= intel_ring_begin(req
, 4);
11822 /* i965+ uses the linear or tiled offsets from the
11823 * Display Registers (which do not change across a page-flip)
11824 * so we need only reprogram the base address.
11826 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11827 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11828 intel_ring_emit(ring
, fb
->pitches
[0]);
11829 intel_ring_emit(ring
, intel_crtc
->flip_work
->gtt_offset
|
11830 intel_fb_modifier_to_tiling(fb
->modifier
));
11832 /* XXX Enabling the panel-fitter across page-flip is so far
11833 * untested on non-native modes, so ignore it for now.
11834 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11837 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11838 intel_ring_emit(ring
, pf
| pipesrc
);
11843 static int intel_gen6_queue_flip(struct drm_device
*dev
,
11844 struct drm_crtc
*crtc
,
11845 struct drm_framebuffer
*fb
,
11846 struct drm_i915_gem_object
*obj
,
11847 struct drm_i915_gem_request
*req
,
11850 struct intel_ring
*ring
= req
->ring
;
11851 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11852 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11853 uint32_t pf
, pipesrc
;
11856 ret
= intel_ring_begin(req
, 4);
11860 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11861 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11862 intel_ring_emit(ring
, fb
->pitches
[0] |
11863 intel_fb_modifier_to_tiling(fb
->modifier
));
11864 intel_ring_emit(ring
, intel_crtc
->flip_work
->gtt_offset
);
11866 /* Contrary to the suggestions in the documentation,
11867 * "Enable Panel Fitter" does not seem to be required when page
11868 * flipping with a non-native mode, and worse causes a normal
11870 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11873 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11874 intel_ring_emit(ring
, pf
| pipesrc
);
11879 static int intel_gen7_queue_flip(struct drm_device
*dev
,
11880 struct drm_crtc
*crtc
,
11881 struct drm_framebuffer
*fb
,
11882 struct drm_i915_gem_object
*obj
,
11883 struct drm_i915_gem_request
*req
,
11886 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11887 struct intel_ring
*ring
= req
->ring
;
11888 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11889 uint32_t plane_bit
= 0;
11892 switch (intel_crtc
->plane
) {
11894 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11897 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11900 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11903 WARN_ONCE(1, "unknown plane in flip command\n");
11908 if (req
->engine
->id
== RCS
) {
11911 * On Gen 8, SRM is now taking an extra dword to accommodate
11912 * 48bits addresses, and we need a NOOP for the batch size to
11915 if (IS_GEN8(dev_priv
))
11920 * BSpec MI_DISPLAY_FLIP for IVB:
11921 * "The full packet must be contained within the same cache line."
11923 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11924 * cacheline, if we ever start emitting more commands before
11925 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11926 * then do the cacheline alignment, and finally emit the
11929 ret
= intel_ring_cacheline_align(req
);
11933 ret
= intel_ring_begin(req
, len
);
11937 /* Unmask the flip-done completion message. Note that the bspec says that
11938 * we should do this for both the BCS and RCS, and that we must not unmask
11939 * more than one flip event at any time (or ensure that one flip message
11940 * can be sent by waiting for flip-done prior to queueing new flips).
11941 * Experimentation says that BCS works despite DERRMR masking all
11942 * flip-done completion events and that unmasking all planes at once
11943 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11944 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11946 if (req
->engine
->id
== RCS
) {
11947 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
11948 intel_ring_emit_reg(ring
, DERRMR
);
11949 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11950 DERRMR_PIPEB_PRI_FLIP_DONE
|
11951 DERRMR_PIPEC_PRI_FLIP_DONE
));
11952 if (IS_GEN8(dev_priv
))
11953 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8
|
11954 MI_SRM_LRM_GLOBAL_GTT
);
11956 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM
|
11957 MI_SRM_LRM_GLOBAL_GTT
);
11958 intel_ring_emit_reg(ring
, DERRMR
);
11959 intel_ring_emit(ring
,
11960 i915_ggtt_offset(req
->engine
->scratch
) + 256);
11961 if (IS_GEN8(dev_priv
)) {
11962 intel_ring_emit(ring
, 0);
11963 intel_ring_emit(ring
, MI_NOOP
);
11967 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11968 intel_ring_emit(ring
, fb
->pitches
[0] |
11969 intel_fb_modifier_to_tiling(fb
->modifier
));
11970 intel_ring_emit(ring
, intel_crtc
->flip_work
->gtt_offset
);
11971 intel_ring_emit(ring
, (MI_NOOP
));
11976 static bool use_mmio_flip(struct intel_engine_cs
*engine
,
11977 struct drm_i915_gem_object
*obj
)
11980 * This is not being used for older platforms, because
11981 * non-availability of flip done interrupt forces us to use
11982 * CS flips. Older platforms derive flip done using some clever
11983 * tricks involving the flip_pending status bits and vblank irqs.
11984 * So using MMIO flips there would disrupt this mechanism.
11987 if (engine
== NULL
)
11990 if (INTEL_GEN(engine
->i915
) < 5)
11993 if (i915
.use_mmio_flip
< 0)
11995 else if (i915
.use_mmio_flip
> 0)
11997 else if (i915
.enable_execlists
)
12000 return engine
!= i915_gem_object_last_write_engine(obj
);
12003 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
,
12004 unsigned int rotation
,
12005 struct intel_flip_work
*work
)
12007 struct drm_device
*dev
= intel_crtc
->base
.dev
;
12008 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12009 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
12010 const enum pipe pipe
= intel_crtc
->pipe
;
12011 u32 ctl
, stride
= skl_plane_stride(fb
, 0, rotation
);
12013 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
12014 ctl
&= ~PLANE_CTL_TILED_MASK
;
12015 switch (fb
->modifier
) {
12016 case DRM_FORMAT_MOD_NONE
:
12018 case I915_FORMAT_MOD_X_TILED
:
12019 ctl
|= PLANE_CTL_TILED_X
;
12021 case I915_FORMAT_MOD_Y_TILED
:
12022 ctl
|= PLANE_CTL_TILED_Y
;
12024 case I915_FORMAT_MOD_Yf_TILED
:
12025 ctl
|= PLANE_CTL_TILED_YF
;
12028 MISSING_CASE(fb
->modifier
);
12032 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12033 * PLANE_SURF updates, the update is then guaranteed to be atomic.
12035 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
12036 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
12038 I915_WRITE(PLANE_SURF(pipe
, 0), work
->gtt_offset
);
12039 POSTING_READ(PLANE_SURF(pipe
, 0));
12042 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
,
12043 struct intel_flip_work
*work
)
12045 struct drm_device
*dev
= intel_crtc
->base
.dev
;
12046 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12047 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
12048 i915_reg_t reg
= DSPCNTR(intel_crtc
->plane
);
12051 dspcntr
= I915_READ(reg
);
12053 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
12054 dspcntr
|= DISPPLANE_TILED
;
12056 dspcntr
&= ~DISPPLANE_TILED
;
12058 I915_WRITE(reg
, dspcntr
);
12060 I915_WRITE(DSPSURF(intel_crtc
->plane
), work
->gtt_offset
);
12061 POSTING_READ(DSPSURF(intel_crtc
->plane
));
12064 static void intel_mmio_flip_work_func(struct work_struct
*w
)
12066 struct intel_flip_work
*work
=
12067 container_of(w
, struct intel_flip_work
, mmio_work
);
12068 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
12069 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
12070 struct intel_framebuffer
*intel_fb
=
12071 to_intel_framebuffer(crtc
->base
.primary
->fb
);
12072 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12074 WARN_ON(i915_gem_object_wait(obj
, 0, MAX_SCHEDULE_TIMEOUT
, NULL
) < 0);
12076 intel_pipe_update_start(crtc
);
12078 if (INTEL_GEN(dev_priv
) >= 9)
12079 skl_do_mmio_flip(crtc
, work
->rotation
, work
);
12081 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12082 ilk_do_mmio_flip(crtc
, work
);
12084 intel_pipe_update_end(crtc
, work
);
12087 static int intel_default_queue_flip(struct drm_device
*dev
,
12088 struct drm_crtc
*crtc
,
12089 struct drm_framebuffer
*fb
,
12090 struct drm_i915_gem_object
*obj
,
12091 struct drm_i915_gem_request
*req
,
12097 static bool __pageflip_stall_check_cs(struct drm_i915_private
*dev_priv
,
12098 struct intel_crtc
*intel_crtc
,
12099 struct intel_flip_work
*work
)
12103 if (!atomic_read(&work
->pending
))
12108 vblank
= intel_crtc_get_vblank_counter(intel_crtc
);
12109 if (work
->flip_ready_vblank
== 0) {
12110 if (work
->flip_queued_req
&&
12111 !i915_gem_request_completed(work
->flip_queued_req
))
12114 work
->flip_ready_vblank
= vblank
;
12117 if (vblank
- work
->flip_ready_vblank
< 3)
12120 /* Potential stall - if we see that the flip has happened,
12121 * assume a missed interrupt. */
12122 if (INTEL_GEN(dev_priv
) >= 4)
12123 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
12125 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
12127 /* There is a potential issue here with a false positive after a flip
12128 * to the same address. We could address this by checking for a
12129 * non-incrementing frame counter.
12131 return addr
== work
->gtt_offset
;
12134 void intel_check_page_flip(struct drm_i915_private
*dev_priv
, int pipe
)
12136 struct drm_device
*dev
= &dev_priv
->drm
;
12137 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
12138 struct intel_flip_work
*work
;
12140 WARN_ON(!in_interrupt());
12145 spin_lock(&dev
->event_lock
);
12146 work
= crtc
->flip_work
;
12148 if (work
!= NULL
&& !is_mmio_work(work
) &&
12149 __pageflip_stall_check_cs(dev_priv
, crtc
, work
)) {
12151 "Kicking stuck page flip: queued at %d, now %d\n",
12152 work
->flip_queued_vblank
, intel_crtc_get_vblank_counter(crtc
));
12153 page_flip_completed(crtc
);
12157 if (work
!= NULL
&& !is_mmio_work(work
) &&
12158 intel_crtc_get_vblank_counter(crtc
) - work
->flip_queued_vblank
> 1)
12159 intel_queue_rps_boost_for_request(work
->flip_queued_req
);
12160 spin_unlock(&dev
->event_lock
);
12163 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
12164 struct drm_framebuffer
*fb
,
12165 struct drm_pending_vblank_event
*event
,
12166 uint32_t page_flip_flags
)
12168 struct drm_device
*dev
= crtc
->dev
;
12169 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12170 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
12171 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12172 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12173 struct drm_plane
*primary
= crtc
->primary
;
12174 enum pipe pipe
= intel_crtc
->pipe
;
12175 struct intel_flip_work
*work
;
12176 struct intel_engine_cs
*engine
;
12178 struct drm_i915_gem_request
*request
;
12179 struct i915_vma
*vma
;
12183 * drm_mode_page_flip_ioctl() should already catch this, but double
12184 * check to be safe. In the future we may enable pageflipping from
12185 * a disabled primary plane.
12187 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
12190 /* Can't change pixel format via MI display flips. */
12191 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
12195 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12196 * Note that pitch changes could also affect these register.
12198 if (INTEL_GEN(dev_priv
) > 3 &&
12199 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
12200 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
12203 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
12206 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
12210 work
->event
= event
;
12212 work
->old_fb
= old_fb
;
12213 INIT_WORK(&work
->unpin_work
, intel_unpin_work_fn
);
12215 ret
= drm_crtc_vblank_get(crtc
);
12219 /* We borrow the event spin lock for protecting flip_work */
12220 spin_lock_irq(&dev
->event_lock
);
12221 if (intel_crtc
->flip_work
) {
12222 /* Before declaring the flip queue wedged, check if
12223 * the hardware completed the operation behind our backs.
12225 if (pageflip_finished(intel_crtc
, intel_crtc
->flip_work
)) {
12226 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12227 page_flip_completed(intel_crtc
);
12229 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12230 spin_unlock_irq(&dev
->event_lock
);
12232 drm_crtc_vblank_put(crtc
);
12237 intel_crtc
->flip_work
= work
;
12238 spin_unlock_irq(&dev
->event_lock
);
12240 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
12241 flush_workqueue(dev_priv
->wq
);
12243 /* Reference the objects for the scheduled work. */
12244 drm_framebuffer_reference(work
->old_fb
);
12246 crtc
->primary
->fb
= fb
;
12247 update_state_fb(crtc
->primary
);
12249 work
->pending_flip_obj
= i915_gem_object_get(obj
);
12251 ret
= i915_mutex_lock_interruptible(dev
);
12255 intel_crtc
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
12256 if (i915_reset_in_progress_or_wedged(&dev_priv
->gpu_error
)) {
12261 atomic_inc(&intel_crtc
->unpin_work_count
);
12263 if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
12264 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_G4X(pipe
)) + 1;
12266 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
12267 engine
= dev_priv
->engine
[BCS
];
12268 if (fb
->modifier
!= old_fb
->modifier
)
12269 /* vlv: DISPLAY_FLIP fails to change tiling */
12271 } else if (IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
)) {
12272 engine
= dev_priv
->engine
[BCS
];
12273 } else if (INTEL_GEN(dev_priv
) >= 7) {
12274 engine
= i915_gem_object_last_write_engine(obj
);
12275 if (engine
== NULL
|| engine
->id
!= RCS
)
12276 engine
= dev_priv
->engine
[BCS
];
12278 engine
= dev_priv
->engine
[RCS
];
12281 mmio_flip
= use_mmio_flip(engine
, obj
);
12283 vma
= intel_pin_and_fence_fb_obj(fb
, primary
->state
->rotation
);
12285 ret
= PTR_ERR(vma
);
12286 goto cleanup_pending
;
12289 work
->gtt_offset
= intel_fb_gtt_offset(fb
, primary
->state
->rotation
);
12290 work
->gtt_offset
+= intel_crtc
->dspaddr_offset
;
12291 work
->rotation
= crtc
->primary
->state
->rotation
;
12294 * There's the potential that the next frame will not be compatible with
12295 * FBC, so we want to call pre_update() before the actual page flip.
12296 * The problem is that pre_update() caches some information about the fb
12297 * object, so we want to do this only after the object is pinned. Let's
12298 * be on the safe side and do this immediately before scheduling the
12301 intel_fbc_pre_update(intel_crtc
, intel_crtc
->config
,
12302 to_intel_plane_state(primary
->state
));
12305 INIT_WORK(&work
->mmio_work
, intel_mmio_flip_work_func
);
12306 queue_work(system_unbound_wq
, &work
->mmio_work
);
12308 request
= i915_gem_request_alloc(engine
, engine
->last_context
);
12309 if (IS_ERR(request
)) {
12310 ret
= PTR_ERR(request
);
12311 goto cleanup_unpin
;
12314 ret
= i915_gem_request_await_object(request
, obj
, false);
12316 goto cleanup_request
;
12318 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, request
,
12321 goto cleanup_request
;
12323 intel_mark_page_flip_active(intel_crtc
, work
);
12325 work
->flip_queued_req
= i915_gem_request_get(request
);
12326 i915_add_request_no_flush(request
);
12329 i915_gem_object_wait_priority(obj
, 0, I915_PRIORITY_DISPLAY
);
12330 i915_gem_track_fb(intel_fb_obj(old_fb
), obj
,
12331 to_intel_plane(primary
)->frontbuffer_bit
);
12332 mutex_unlock(&dev
->struct_mutex
);
12334 intel_frontbuffer_flip_prepare(to_i915(dev
),
12335 to_intel_plane(primary
)->frontbuffer_bit
);
12337 trace_i915_flip_request(intel_crtc
->plane
, obj
);
12342 i915_add_request_no_flush(request
);
12344 intel_unpin_fb_obj(fb
, crtc
->primary
->state
->rotation
);
12346 atomic_dec(&intel_crtc
->unpin_work_count
);
12348 mutex_unlock(&dev
->struct_mutex
);
12350 crtc
->primary
->fb
= old_fb
;
12351 update_state_fb(crtc
->primary
);
12353 i915_gem_object_put(obj
);
12354 drm_framebuffer_unreference(work
->old_fb
);
12356 spin_lock_irq(&dev
->event_lock
);
12357 intel_crtc
->flip_work
= NULL
;
12358 spin_unlock_irq(&dev
->event_lock
);
12360 drm_crtc_vblank_put(crtc
);
12365 struct drm_atomic_state
*state
;
12366 struct drm_plane_state
*plane_state
;
12369 state
= drm_atomic_state_alloc(dev
);
12372 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
12375 plane_state
= drm_atomic_get_plane_state(state
, primary
);
12376 ret
= PTR_ERR_OR_ZERO(plane_state
);
12378 drm_atomic_set_fb_for_plane(plane_state
, fb
);
12380 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
12382 ret
= drm_atomic_commit(state
);
12385 if (ret
== -EDEADLK
) {
12386 drm_modeset_backoff(state
->acquire_ctx
);
12387 drm_atomic_state_clear(state
);
12391 drm_atomic_state_put(state
);
12393 if (ret
== 0 && event
) {
12394 spin_lock_irq(&dev
->event_lock
);
12395 drm_crtc_send_vblank_event(crtc
, event
);
12396 spin_unlock_irq(&dev
->event_lock
);
12404 * intel_wm_need_update - Check whether watermarks need updating
12405 * @plane: drm plane
12406 * @state: new plane state
12408 * Check current plane state versus the new one to determine whether
12409 * watermarks need to be recalculated.
12411 * Returns true or false.
12413 static bool intel_wm_need_update(struct drm_plane
*plane
,
12414 struct drm_plane_state
*state
)
12416 struct intel_plane_state
*new = to_intel_plane_state(state
);
12417 struct intel_plane_state
*cur
= to_intel_plane_state(plane
->state
);
12419 /* Update watermarks on tiling or size changes. */
12420 if (new->base
.visible
!= cur
->base
.visible
)
12423 if (!cur
->base
.fb
|| !new->base
.fb
)
12426 if (cur
->base
.fb
->modifier
!= new->base
.fb
->modifier
||
12427 cur
->base
.rotation
!= new->base
.rotation
||
12428 drm_rect_width(&new->base
.src
) != drm_rect_width(&cur
->base
.src
) ||
12429 drm_rect_height(&new->base
.src
) != drm_rect_height(&cur
->base
.src
) ||
12430 drm_rect_width(&new->base
.dst
) != drm_rect_width(&cur
->base
.dst
) ||
12431 drm_rect_height(&new->base
.dst
) != drm_rect_height(&cur
->base
.dst
))
12437 static bool needs_scaling(struct intel_plane_state
*state
)
12439 int src_w
= drm_rect_width(&state
->base
.src
) >> 16;
12440 int src_h
= drm_rect_height(&state
->base
.src
) >> 16;
12441 int dst_w
= drm_rect_width(&state
->base
.dst
);
12442 int dst_h
= drm_rect_height(&state
->base
.dst
);
12444 return (src_w
!= dst_w
|| src_h
!= dst_h
);
12447 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
12448 struct drm_plane_state
*plane_state
)
12450 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc_state
);
12451 struct drm_crtc
*crtc
= crtc_state
->crtc
;
12452 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12453 struct drm_plane
*plane
= plane_state
->plane
;
12454 struct drm_device
*dev
= crtc
->dev
;
12455 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12456 struct intel_plane_state
*old_plane_state
=
12457 to_intel_plane_state(plane
->state
);
12458 bool mode_changed
= needs_modeset(crtc_state
);
12459 bool was_crtc_enabled
= crtc
->state
->active
;
12460 bool is_crtc_enabled
= crtc_state
->active
;
12461 bool turn_off
, turn_on
, visible
, was_visible
;
12462 struct drm_framebuffer
*fb
= plane_state
->fb
;
12465 if (INTEL_GEN(dev_priv
) >= 9 && plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
12466 ret
= skl_update_scaler_plane(
12467 to_intel_crtc_state(crtc_state
),
12468 to_intel_plane_state(plane_state
));
12473 was_visible
= old_plane_state
->base
.visible
;
12474 visible
= to_intel_plane_state(plane_state
)->base
.visible
;
12476 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
12477 was_visible
= false;
12480 * Visibility is calculated as if the crtc was on, but
12481 * after scaler setup everything depends on it being off
12482 * when the crtc isn't active.
12484 * FIXME this is wrong for watermarks. Watermarks should also
12485 * be computed as if the pipe would be active. Perhaps move
12486 * per-plane wm computation to the .check_plane() hook, and
12487 * only combine the results from all planes in the current place?
12489 if (!is_crtc_enabled
)
12490 to_intel_plane_state(plane_state
)->base
.visible
= visible
= false;
12492 if (!was_visible
&& !visible
)
12495 if (fb
!= old_plane_state
->base
.fb
)
12496 pipe_config
->fb_changed
= true;
12498 turn_off
= was_visible
&& (!visible
|| mode_changed
);
12499 turn_on
= visible
&& (!was_visible
|| mode_changed
);
12501 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12502 intel_crtc
->base
.base
.id
,
12503 intel_crtc
->base
.name
,
12504 plane
->base
.id
, plane
->name
,
12505 fb
? fb
->base
.id
: -1);
12507 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12508 plane
->base
.id
, plane
->name
,
12509 was_visible
, visible
,
12510 turn_off
, turn_on
, mode_changed
);
12513 pipe_config
->update_wm_pre
= true;
12515 /* must disable cxsr around plane enable/disable */
12516 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
12517 pipe_config
->disable_cxsr
= true;
12518 } else if (turn_off
) {
12519 pipe_config
->update_wm_post
= true;
12521 /* must disable cxsr around plane enable/disable */
12522 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
)
12523 pipe_config
->disable_cxsr
= true;
12524 } else if (intel_wm_need_update(plane
, plane_state
)) {
12525 /* FIXME bollocks */
12526 pipe_config
->update_wm_pre
= true;
12527 pipe_config
->update_wm_post
= true;
12530 /* Pre-gen9 platforms need two-step watermark updates */
12531 if ((pipe_config
->update_wm_pre
|| pipe_config
->update_wm_post
) &&
12532 INTEL_GEN(dev_priv
) < 9 && dev_priv
->display
.optimize_watermarks
)
12533 to_intel_crtc_state(crtc_state
)->wm
.need_postvbl_update
= true;
12535 if (visible
|| was_visible
)
12536 pipe_config
->fb_bits
|= to_intel_plane(plane
)->frontbuffer_bit
;
12539 * WaCxSRDisabledForSpriteScaling:ivb
12541 * cstate->update_wm was already set above, so this flag will
12542 * take effect when we commit and program watermarks.
12544 if (plane
->type
== DRM_PLANE_TYPE_OVERLAY
&& IS_IVYBRIDGE(dev_priv
) &&
12545 needs_scaling(to_intel_plane_state(plane_state
)) &&
12546 !needs_scaling(old_plane_state
))
12547 pipe_config
->disable_lp_wm
= true;
12552 static bool encoders_cloneable(const struct intel_encoder
*a
,
12553 const struct intel_encoder
*b
)
12555 /* masks could be asymmetric, so check both ways */
12556 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
12557 b
->cloneable
& (1 << a
->type
));
12560 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
12561 struct intel_crtc
*crtc
,
12562 struct intel_encoder
*encoder
)
12564 struct intel_encoder
*source_encoder
;
12565 struct drm_connector
*connector
;
12566 struct drm_connector_state
*connector_state
;
12569 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12570 if (connector_state
->crtc
!= &crtc
->base
)
12574 to_intel_encoder(connector_state
->best_encoder
);
12575 if (!encoders_cloneable(encoder
, source_encoder
))
12582 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
12583 struct drm_crtc_state
*crtc_state
)
12585 struct drm_device
*dev
= crtc
->dev
;
12586 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12587 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12588 struct intel_crtc_state
*pipe_config
=
12589 to_intel_crtc_state(crtc_state
);
12590 struct drm_atomic_state
*state
= crtc_state
->state
;
12592 bool mode_changed
= needs_modeset(crtc_state
);
12594 if (mode_changed
&& !crtc_state
->active
)
12595 pipe_config
->update_wm_post
= true;
12597 if (mode_changed
&& crtc_state
->enable
&&
12598 dev_priv
->display
.crtc_compute_clock
&&
12599 !WARN_ON(pipe_config
->shared_dpll
)) {
12600 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12606 if (crtc_state
->color_mgmt_changed
) {
12607 ret
= intel_color_check(crtc
, crtc_state
);
12612 * Changing color management on Intel hardware is
12613 * handled as part of planes update.
12615 crtc_state
->planes_changed
= true;
12619 if (dev_priv
->display
.compute_pipe_wm
) {
12620 ret
= dev_priv
->display
.compute_pipe_wm(pipe_config
);
12622 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12627 if (dev_priv
->display
.compute_intermediate_wm
&&
12628 !to_intel_atomic_state(state
)->skip_intermediate_wm
) {
12629 if (WARN_ON(!dev_priv
->display
.compute_pipe_wm
))
12633 * Calculate 'intermediate' watermarks that satisfy both the
12634 * old state and the new state. We can program these
12637 ret
= dev_priv
->display
.compute_intermediate_wm(dev
,
12641 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12644 } else if (dev_priv
->display
.compute_intermediate_wm
) {
12645 if (HAS_PCH_SPLIT(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
12646 pipe_config
->wm
.ilk
.intermediate
= pipe_config
->wm
.ilk
.optimal
;
12649 if (INTEL_GEN(dev_priv
) >= 9) {
12651 ret
= skl_update_scaler_crtc(pipe_config
);
12654 ret
= intel_atomic_setup_scalers(dev
, intel_crtc
,
12661 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
12662 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
12663 .atomic_begin
= intel_begin_crtc_commit
,
12664 .atomic_flush
= intel_finish_crtc_commit
,
12665 .atomic_check
= intel_crtc_atomic_check
,
12668 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
12670 struct intel_connector
*connector
;
12672 for_each_intel_connector(dev
, connector
) {
12673 if (connector
->base
.state
->crtc
)
12674 drm_connector_unreference(&connector
->base
);
12676 if (connector
->base
.encoder
) {
12677 connector
->base
.state
->best_encoder
=
12678 connector
->base
.encoder
;
12679 connector
->base
.state
->crtc
=
12680 connector
->base
.encoder
->crtc
;
12682 drm_connector_reference(&connector
->base
);
12684 connector
->base
.state
->best_encoder
= NULL
;
12685 connector
->base
.state
->crtc
= NULL
;
12691 connected_sink_compute_bpp(struct intel_connector
*connector
,
12692 struct intel_crtc_state
*pipe_config
)
12694 const struct drm_display_info
*info
= &connector
->base
.display_info
;
12695 int bpp
= pipe_config
->pipe_bpp
;
12697 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12698 connector
->base
.base
.id
,
12699 connector
->base
.name
);
12701 /* Don't use an invalid EDID bpc value */
12702 if (info
->bpc
!= 0 && info
->bpc
* 3 < bpp
) {
12703 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12704 bpp
, info
->bpc
* 3);
12705 pipe_config
->pipe_bpp
= info
->bpc
* 3;
12708 /* Clamp bpp to 8 on screens without EDID 1.4 */
12709 if (info
->bpc
== 0 && bpp
> 24) {
12710 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12712 pipe_config
->pipe_bpp
= 24;
12717 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
12718 struct intel_crtc_state
*pipe_config
)
12720 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
12721 struct drm_atomic_state
*state
;
12722 struct drm_connector
*connector
;
12723 struct drm_connector_state
*connector_state
;
12726 if ((IS_G4X(dev_priv
) || IS_VALLEYVIEW(dev_priv
) ||
12727 IS_CHERRYVIEW(dev_priv
)))
12729 else if (INTEL_GEN(dev_priv
) >= 5)
12735 pipe_config
->pipe_bpp
= bpp
;
12737 state
= pipe_config
->base
.state
;
12739 /* Clamp display bpp to EDID value */
12740 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12741 if (connector_state
->crtc
!= &crtc
->base
)
12744 connected_sink_compute_bpp(to_intel_connector(connector
),
12751 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
12753 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12754 "type: 0x%x flags: 0x%x\n",
12756 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
12757 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
12758 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
12759 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
12763 intel_dump_m_n_config(struct intel_crtc_state
*pipe_config
, char *id
,
12764 unsigned int lane_count
, struct intel_link_m_n
*m_n
)
12766 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12768 m_n
->gmch_m
, m_n
->gmch_n
,
12769 m_n
->link_m
, m_n
->link_n
, m_n
->tu
);
12772 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
12773 struct intel_crtc_state
*pipe_config
,
12774 const char *context
)
12776 struct drm_device
*dev
= crtc
->base
.dev
;
12777 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12778 struct drm_plane
*plane
;
12779 struct intel_plane
*intel_plane
;
12780 struct intel_plane_state
*state
;
12781 struct drm_framebuffer
*fb
;
12783 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
12784 crtc
->base
.base
.id
, crtc
->base
.name
, context
);
12786 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12787 transcoder_name(pipe_config
->cpu_transcoder
),
12788 pipe_config
->pipe_bpp
, pipe_config
->dither
);
12790 if (pipe_config
->has_pch_encoder
)
12791 intel_dump_m_n_config(pipe_config
, "fdi",
12792 pipe_config
->fdi_lanes
,
12793 &pipe_config
->fdi_m_n
);
12795 if (intel_crtc_has_dp_encoder(pipe_config
)) {
12796 intel_dump_m_n_config(pipe_config
, "dp m_n",
12797 pipe_config
->lane_count
, &pipe_config
->dp_m_n
);
12798 if (pipe_config
->has_drrs
)
12799 intel_dump_m_n_config(pipe_config
, "dp m2_n2",
12800 pipe_config
->lane_count
,
12801 &pipe_config
->dp_m2_n2
);
12804 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12805 pipe_config
->has_audio
, pipe_config
->has_infoframe
);
12807 DRM_DEBUG_KMS("requested mode:\n");
12808 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
12809 DRM_DEBUG_KMS("adjusted mode:\n");
12810 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
12811 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
12812 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",
12813 pipe_config
->port_clock
,
12814 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
12816 if (INTEL_GEN(dev_priv
) >= 9)
12817 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12819 pipe_config
->scaler_state
.scaler_users
,
12820 pipe_config
->scaler_state
.scaler_id
);
12822 if (HAS_GMCH_DISPLAY(dev_priv
))
12823 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12824 pipe_config
->gmch_pfit
.control
,
12825 pipe_config
->gmch_pfit
.pgm_ratios
,
12826 pipe_config
->gmch_pfit
.lvds_border_bits
);
12828 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12829 pipe_config
->pch_pfit
.pos
,
12830 pipe_config
->pch_pfit
.size
,
12831 enableddisabled(pipe_config
->pch_pfit
.enabled
));
12833 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12834 pipe_config
->ips_enabled
, pipe_config
->double_wide
);
12836 if (IS_GEN9_LP(dev_priv
)) {
12837 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12838 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12839 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12840 pipe_config
->dpll_hw_state
.ebb0
,
12841 pipe_config
->dpll_hw_state
.ebb4
,
12842 pipe_config
->dpll_hw_state
.pll0
,
12843 pipe_config
->dpll_hw_state
.pll1
,
12844 pipe_config
->dpll_hw_state
.pll2
,
12845 pipe_config
->dpll_hw_state
.pll3
,
12846 pipe_config
->dpll_hw_state
.pll6
,
12847 pipe_config
->dpll_hw_state
.pll8
,
12848 pipe_config
->dpll_hw_state
.pll9
,
12849 pipe_config
->dpll_hw_state
.pll10
,
12850 pipe_config
->dpll_hw_state
.pcsdw12
);
12851 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
12852 DRM_DEBUG_KMS("dpll_hw_state: "
12853 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12854 pipe_config
->dpll_hw_state
.ctrl1
,
12855 pipe_config
->dpll_hw_state
.cfgcr1
,
12856 pipe_config
->dpll_hw_state
.cfgcr2
);
12857 } else if (HAS_DDI(dev_priv
)) {
12858 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12859 pipe_config
->dpll_hw_state
.wrpll
,
12860 pipe_config
->dpll_hw_state
.spll
);
12862 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12863 "fp0: 0x%x, fp1: 0x%x\n",
12864 pipe_config
->dpll_hw_state
.dpll
,
12865 pipe_config
->dpll_hw_state
.dpll_md
,
12866 pipe_config
->dpll_hw_state
.fp0
,
12867 pipe_config
->dpll_hw_state
.fp1
);
12870 DRM_DEBUG_KMS("planes on this crtc\n");
12871 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12872 struct drm_format_name_buf format_name
;
12873 intel_plane
= to_intel_plane(plane
);
12874 if (intel_plane
->pipe
!= crtc
->pipe
)
12877 state
= to_intel_plane_state(plane
->state
);
12878 fb
= state
->base
.fb
;
12880 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12881 plane
->base
.id
, plane
->name
, state
->scaler_id
);
12885 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
12886 plane
->base
.id
, plane
->name
,
12887 fb
->base
.id
, fb
->width
, fb
->height
,
12888 drm_get_format_name(fb
->pixel_format
, &format_name
));
12889 if (INTEL_GEN(dev_priv
) >= 9)
12890 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12892 state
->base
.src
.x1
>> 16,
12893 state
->base
.src
.y1
>> 16,
12894 drm_rect_width(&state
->base
.src
) >> 16,
12895 drm_rect_height(&state
->base
.src
) >> 16,
12896 state
->base
.dst
.x1
, state
->base
.dst
.y1
,
12897 drm_rect_width(&state
->base
.dst
),
12898 drm_rect_height(&state
->base
.dst
));
12902 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12904 struct drm_device
*dev
= state
->dev
;
12905 struct drm_connector
*connector
;
12906 unsigned int used_ports
= 0;
12907 unsigned int used_mst_ports
= 0;
12910 * Walk the connector list instead of the encoder
12911 * list to detect the problem on ddi platforms
12912 * where there's just one encoder per digital port.
12914 drm_for_each_connector(connector
, dev
) {
12915 struct drm_connector_state
*connector_state
;
12916 struct intel_encoder
*encoder
;
12918 connector_state
= drm_atomic_get_existing_connector_state(state
, connector
);
12919 if (!connector_state
)
12920 connector_state
= connector
->state
;
12922 if (!connector_state
->best_encoder
)
12925 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12927 WARN_ON(!connector_state
->crtc
);
12929 switch (encoder
->type
) {
12930 unsigned int port_mask
;
12931 case INTEL_OUTPUT_UNKNOWN
:
12932 if (WARN_ON(!HAS_DDI(to_i915(dev
))))
12934 case INTEL_OUTPUT_DP
:
12935 case INTEL_OUTPUT_HDMI
:
12936 case INTEL_OUTPUT_EDP
:
12937 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12939 /* the same port mustn't appear more than once */
12940 if (used_ports
& port_mask
)
12943 used_ports
|= port_mask
;
12945 case INTEL_OUTPUT_DP_MST
:
12947 1 << enc_to_mst(&encoder
->base
)->primary
->port
;
12954 /* can't mix MST and SST/HDMI on the same port */
12955 if (used_ports
& used_mst_ports
)
12962 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12964 struct drm_crtc_state tmp_state
;
12965 struct intel_crtc_scaler_state scaler_state
;
12966 struct intel_dpll_hw_state dpll_hw_state
;
12967 struct intel_shared_dpll
*shared_dpll
;
12970 /* FIXME: before the switch to atomic started, a new pipe_config was
12971 * kzalloc'd. Code that depends on any field being zero should be
12972 * fixed, so that the crtc_state can be safely duplicated. For now,
12973 * only fields that are know to not cause problems are preserved. */
12975 tmp_state
= crtc_state
->base
;
12976 scaler_state
= crtc_state
->scaler_state
;
12977 shared_dpll
= crtc_state
->shared_dpll
;
12978 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12979 force_thru
= crtc_state
->pch_pfit
.force_thru
;
12981 memset(crtc_state
, 0, sizeof *crtc_state
);
12983 crtc_state
->base
= tmp_state
;
12984 crtc_state
->scaler_state
= scaler_state
;
12985 crtc_state
->shared_dpll
= shared_dpll
;
12986 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12987 crtc_state
->pch_pfit
.force_thru
= force_thru
;
12991 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12992 struct intel_crtc_state
*pipe_config
)
12994 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12995 struct intel_encoder
*encoder
;
12996 struct drm_connector
*connector
;
12997 struct drm_connector_state
*connector_state
;
12998 int base_bpp
, ret
= -EINVAL
;
13002 clear_intel_crtc_state(pipe_config
);
13004 pipe_config
->cpu_transcoder
=
13005 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
13008 * Sanitize sync polarity flags based on requested ones. If neither
13009 * positive or negative polarity is requested, treat this as meaning
13010 * negative polarity.
13012 if (!(pipe_config
->base
.adjusted_mode
.flags
&
13013 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
13014 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
13016 if (!(pipe_config
->base
.adjusted_mode
.flags
&
13017 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
13018 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
13020 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
13026 * Determine the real pipe dimensions. Note that stereo modes can
13027 * increase the actual pipe size due to the frame doubling and
13028 * insertion of additional space for blanks between the frame. This
13029 * is stored in the crtc timings. We use the requested mode to do this
13030 * computation to clearly distinguish it from the adjusted mode, which
13031 * can be changed by the connectors in the below retry loop.
13033 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
13034 &pipe_config
->pipe_src_w
,
13035 &pipe_config
->pipe_src_h
);
13037 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
13038 if (connector_state
->crtc
!= crtc
)
13041 encoder
= to_intel_encoder(connector_state
->best_encoder
);
13043 if (!check_single_encoder_cloning(state
, to_intel_crtc(crtc
), encoder
)) {
13044 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13049 * Determine output_types before calling the .compute_config()
13050 * hooks so that the hooks can use this information safely.
13052 pipe_config
->output_types
|= 1 << encoder
->type
;
13056 /* Ensure the port clock defaults are reset when retrying. */
13057 pipe_config
->port_clock
= 0;
13058 pipe_config
->pixel_multiplier
= 1;
13060 /* Fill in default crtc timings, allow encoders to overwrite them. */
13061 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
13062 CRTC_STEREO_DOUBLE
);
13064 /* Pass our mode to the connectors and the CRTC to give them a chance to
13065 * adjust it according to limitations or connector properties, and also
13066 * a chance to reject the mode entirely.
13068 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
13069 if (connector_state
->crtc
!= crtc
)
13072 encoder
= to_intel_encoder(connector_state
->best_encoder
);
13074 if (!(encoder
->compute_config(encoder
, pipe_config
, connector_state
))) {
13075 DRM_DEBUG_KMS("Encoder config failure\n");
13080 /* Set default port clock if not overwritten by the encoder. Needs to be
13081 * done afterwards in case the encoder adjusts the mode. */
13082 if (!pipe_config
->port_clock
)
13083 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
13084 * pipe_config
->pixel_multiplier
;
13086 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
13088 DRM_DEBUG_KMS("CRTC fixup failed\n");
13092 if (ret
== RETRY
) {
13093 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
13098 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13100 goto encoder_retry
;
13103 /* Dithering seems to not pass-through bits correctly when it should, so
13104 * only enable it on 6bpc panels. */
13105 pipe_config
->dither
= pipe_config
->pipe_bpp
== 6*3;
13106 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13107 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
13114 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
13116 struct drm_crtc
*crtc
;
13117 struct drm_crtc_state
*crtc_state
;
13120 /* Double check state. */
13121 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13122 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
13124 /* Update hwmode for vblank functions */
13125 if (crtc
->state
->active
)
13126 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
13128 crtc
->hwmode
.crtc_clock
= 0;
13131 * Update legacy state to satisfy fbc code. This can
13132 * be removed when fbc uses the atomic state.
13134 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
13135 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
13137 crtc
->primary
->fb
= plane_state
->fb
;
13138 crtc
->x
= plane_state
->src_x
>> 16;
13139 crtc
->y
= plane_state
->src_y
>> 16;
13144 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
13148 if (clock1
== clock2
)
13151 if (!clock1
|| !clock2
)
13154 diff
= abs(clock1
- clock2
);
13156 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
13163 intel_compare_m_n(unsigned int m
, unsigned int n
,
13164 unsigned int m2
, unsigned int n2
,
13167 if (m
== m2
&& n
== n2
)
13170 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
13173 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
13180 } else if (n
< n2
) {
13190 return intel_fuzzy_clock_check(m
, m2
);
13194 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
13195 struct intel_link_m_n
*m2_n2
,
13198 if (m_n
->tu
== m2_n2
->tu
&&
13199 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
13200 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
13201 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
13202 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
13213 intel_pipe_config_compare(struct drm_i915_private
*dev_priv
,
13214 struct intel_crtc_state
*current_config
,
13215 struct intel_crtc_state
*pipe_config
,
13220 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13223 DRM_ERROR(fmt, ##__VA_ARGS__); \
13225 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13228 #define PIPE_CONF_CHECK_X(name) \
13229 if (current_config->name != pipe_config->name) { \
13230 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13231 "(expected 0x%08x, found 0x%08x)\n", \
13232 current_config->name, \
13233 pipe_config->name); \
13237 #define PIPE_CONF_CHECK_I(name) \
13238 if (current_config->name != pipe_config->name) { \
13239 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13240 "(expected %i, found %i)\n", \
13241 current_config->name, \
13242 pipe_config->name); \
13246 #define PIPE_CONF_CHECK_P(name) \
13247 if (current_config->name != pipe_config->name) { \
13248 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13249 "(expected %p, found %p)\n", \
13250 current_config->name, \
13251 pipe_config->name); \
13255 #define PIPE_CONF_CHECK_M_N(name) \
13256 if (!intel_compare_link_m_n(¤t_config->name, \
13257 &pipe_config->name,\
13259 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13260 "(expected tu %i gmch %i/%i link %i/%i, " \
13261 "found tu %i, gmch %i/%i link %i/%i)\n", \
13262 current_config->name.tu, \
13263 current_config->name.gmch_m, \
13264 current_config->name.gmch_n, \
13265 current_config->name.link_m, \
13266 current_config->name.link_n, \
13267 pipe_config->name.tu, \
13268 pipe_config->name.gmch_m, \
13269 pipe_config->name.gmch_n, \
13270 pipe_config->name.link_m, \
13271 pipe_config->name.link_n); \
13275 /* This is required for BDW+ where there is only one set of registers for
13276 * switching between high and low RR.
13277 * This macro can be used whenever a comparison has to be made between one
13278 * hw state and multiple sw state variables.
13280 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13281 if (!intel_compare_link_m_n(¤t_config->name, \
13282 &pipe_config->name, adjust) && \
13283 !intel_compare_link_m_n(¤t_config->alt_name, \
13284 &pipe_config->name, adjust)) { \
13285 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13286 "(expected tu %i gmch %i/%i link %i/%i, " \
13287 "or tu %i gmch %i/%i link %i/%i, " \
13288 "found tu %i, gmch %i/%i link %i/%i)\n", \
13289 current_config->name.tu, \
13290 current_config->name.gmch_m, \
13291 current_config->name.gmch_n, \
13292 current_config->name.link_m, \
13293 current_config->name.link_n, \
13294 current_config->alt_name.tu, \
13295 current_config->alt_name.gmch_m, \
13296 current_config->alt_name.gmch_n, \
13297 current_config->alt_name.link_m, \
13298 current_config->alt_name.link_n, \
13299 pipe_config->name.tu, \
13300 pipe_config->name.gmch_m, \
13301 pipe_config->name.gmch_n, \
13302 pipe_config->name.link_m, \
13303 pipe_config->name.link_n); \
13307 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13308 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13309 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13310 "(expected %i, found %i)\n", \
13311 current_config->name & (mask), \
13312 pipe_config->name & (mask)); \
13316 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13317 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13318 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13319 "(expected %i, found %i)\n", \
13320 current_config->name, \
13321 pipe_config->name); \
13325 #define PIPE_CONF_QUIRK(quirk) \
13326 ((current_config->quirks | pipe_config->quirks) & (quirk))
13328 PIPE_CONF_CHECK_I(cpu_transcoder
);
13330 PIPE_CONF_CHECK_I(has_pch_encoder
);
13331 PIPE_CONF_CHECK_I(fdi_lanes
);
13332 PIPE_CONF_CHECK_M_N(fdi_m_n
);
13334 PIPE_CONF_CHECK_I(lane_count
);
13335 PIPE_CONF_CHECK_X(lane_lat_optim_mask
);
13337 if (INTEL_GEN(dev_priv
) < 8) {
13338 PIPE_CONF_CHECK_M_N(dp_m_n
);
13340 if (current_config
->has_drrs
)
13341 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
13343 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
13345 PIPE_CONF_CHECK_X(output_types
);
13347 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
13348 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
13349 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
13350 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
13351 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
13352 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
13354 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
13355 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
13356 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
13357 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
13358 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
13359 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
13361 PIPE_CONF_CHECK_I(pixel_multiplier
);
13362 PIPE_CONF_CHECK_I(has_hdmi_sink
);
13363 if ((INTEL_GEN(dev_priv
) < 8 && !IS_HASWELL(dev_priv
)) ||
13364 IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
13365 PIPE_CONF_CHECK_I(limited_color_range
);
13366 PIPE_CONF_CHECK_I(has_infoframe
);
13368 PIPE_CONF_CHECK_I(has_audio
);
13370 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
13371 DRM_MODE_FLAG_INTERLACE
);
13373 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
13374 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
13375 DRM_MODE_FLAG_PHSYNC
);
13376 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
13377 DRM_MODE_FLAG_NHSYNC
);
13378 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
13379 DRM_MODE_FLAG_PVSYNC
);
13380 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
13381 DRM_MODE_FLAG_NVSYNC
);
13384 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
13385 /* pfit ratios are autocomputed by the hw on gen4+ */
13386 if (INTEL_GEN(dev_priv
) < 4)
13387 PIPE_CONF_CHECK_X(gmch_pfit
.pgm_ratios
);
13388 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
13391 PIPE_CONF_CHECK_I(pipe_src_w
);
13392 PIPE_CONF_CHECK_I(pipe_src_h
);
13394 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
13395 if (current_config
->pch_pfit
.enabled
) {
13396 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
13397 PIPE_CONF_CHECK_X(pch_pfit
.size
);
13400 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
13403 /* BDW+ don't expose a synchronous way to read the state */
13404 if (IS_HASWELL(dev_priv
))
13405 PIPE_CONF_CHECK_I(ips_enabled
);
13407 PIPE_CONF_CHECK_I(double_wide
);
13409 PIPE_CONF_CHECK_P(shared_dpll
);
13410 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
13411 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
13412 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
13413 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
13414 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
13415 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
13416 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
13417 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
13418 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
13420 PIPE_CONF_CHECK_X(dsi_pll
.ctrl
);
13421 PIPE_CONF_CHECK_X(dsi_pll
.div
);
13423 if (IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5)
13424 PIPE_CONF_CHECK_I(pipe_bpp
);
13426 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
13427 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
13429 #undef PIPE_CONF_CHECK_X
13430 #undef PIPE_CONF_CHECK_I
13431 #undef PIPE_CONF_CHECK_P
13432 #undef PIPE_CONF_CHECK_FLAGS
13433 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13434 #undef PIPE_CONF_QUIRK
13435 #undef INTEL_ERR_OR_DBG_KMS
13440 static void intel_pipe_config_sanity_check(struct drm_i915_private
*dev_priv
,
13441 const struct intel_crtc_state
*pipe_config
)
13443 if (pipe_config
->has_pch_encoder
) {
13444 int fdi_dotclock
= intel_dotclock_calculate(intel_fdi_link_freq(dev_priv
, pipe_config
),
13445 &pipe_config
->fdi_m_n
);
13446 int dotclock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
13449 * FDI already provided one idea for the dotclock.
13450 * Yell if the encoder disagrees.
13452 WARN(!intel_fuzzy_clock_check(fdi_dotclock
, dotclock
),
13453 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13454 fdi_dotclock
, dotclock
);
13458 static void verify_wm_state(struct drm_crtc
*crtc
,
13459 struct drm_crtc_state
*new_state
)
13461 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
13462 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
13463 struct skl_pipe_wm hw_wm
, *sw_wm
;
13464 struct skl_plane_wm
*hw_plane_wm
, *sw_plane_wm
;
13465 struct skl_ddb_entry
*hw_ddb_entry
, *sw_ddb_entry
;
13466 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13467 const enum pipe pipe
= intel_crtc
->pipe
;
13468 int plane
, level
, max_level
= ilk_wm_max_level(dev_priv
);
13470 if (INTEL_GEN(dev_priv
) < 9 || !new_state
->active
)
13473 skl_pipe_wm_get_hw_state(crtc
, &hw_wm
);
13474 sw_wm
= &to_intel_crtc_state(new_state
)->wm
.skl
.optimal
;
13476 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
13477 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
13480 for_each_universal_plane(dev_priv
, pipe
, plane
) {
13481 hw_plane_wm
= &hw_wm
.planes
[plane
];
13482 sw_plane_wm
= &sw_wm
->planes
[plane
];
13485 for (level
= 0; level
<= max_level
; level
++) {
13486 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
13487 &sw_plane_wm
->wm
[level
]))
13490 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13491 pipe_name(pipe
), plane
+ 1, level
,
13492 sw_plane_wm
->wm
[level
].plane_en
,
13493 sw_plane_wm
->wm
[level
].plane_res_b
,
13494 sw_plane_wm
->wm
[level
].plane_res_l
,
13495 hw_plane_wm
->wm
[level
].plane_en
,
13496 hw_plane_wm
->wm
[level
].plane_res_b
,
13497 hw_plane_wm
->wm
[level
].plane_res_l
);
13500 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
13501 &sw_plane_wm
->trans_wm
)) {
13502 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13503 pipe_name(pipe
), plane
+ 1,
13504 sw_plane_wm
->trans_wm
.plane_en
,
13505 sw_plane_wm
->trans_wm
.plane_res_b
,
13506 sw_plane_wm
->trans_wm
.plane_res_l
,
13507 hw_plane_wm
->trans_wm
.plane_en
,
13508 hw_plane_wm
->trans_wm
.plane_res_b
,
13509 hw_plane_wm
->trans_wm
.plane_res_l
);
13513 hw_ddb_entry
= &hw_ddb
.plane
[pipe
][plane
];
13514 sw_ddb_entry
= &sw_ddb
->plane
[pipe
][plane
];
13516 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
13517 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
13518 pipe_name(pipe
), plane
+ 1,
13519 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
13520 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
13526 * If the cursor plane isn't active, we may not have updated it's ddb
13527 * allocation. In that case since the ddb allocation will be updated
13528 * once the plane becomes visible, we can skip this check
13530 if (intel_crtc
->cursor_addr
) {
13531 hw_plane_wm
= &hw_wm
.planes
[PLANE_CURSOR
];
13532 sw_plane_wm
= &sw_wm
->planes
[PLANE_CURSOR
];
13535 for (level
= 0; level
<= max_level
; level
++) {
13536 if (skl_wm_level_equals(&hw_plane_wm
->wm
[level
],
13537 &sw_plane_wm
->wm
[level
]))
13540 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13541 pipe_name(pipe
), level
,
13542 sw_plane_wm
->wm
[level
].plane_en
,
13543 sw_plane_wm
->wm
[level
].plane_res_b
,
13544 sw_plane_wm
->wm
[level
].plane_res_l
,
13545 hw_plane_wm
->wm
[level
].plane_en
,
13546 hw_plane_wm
->wm
[level
].plane_res_b
,
13547 hw_plane_wm
->wm
[level
].plane_res_l
);
13550 if (!skl_wm_level_equals(&hw_plane_wm
->trans_wm
,
13551 &sw_plane_wm
->trans_wm
)) {
13552 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13554 sw_plane_wm
->trans_wm
.plane_en
,
13555 sw_plane_wm
->trans_wm
.plane_res_b
,
13556 sw_plane_wm
->trans_wm
.plane_res_l
,
13557 hw_plane_wm
->trans_wm
.plane_en
,
13558 hw_plane_wm
->trans_wm
.plane_res_b
,
13559 hw_plane_wm
->trans_wm
.plane_res_l
);
13563 hw_ddb_entry
= &hw_ddb
.plane
[pipe
][PLANE_CURSOR
];
13564 sw_ddb_entry
= &sw_ddb
->plane
[pipe
][PLANE_CURSOR
];
13566 if (!skl_ddb_entry_equal(hw_ddb_entry
, sw_ddb_entry
)) {
13567 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13569 sw_ddb_entry
->start
, sw_ddb_entry
->end
,
13570 hw_ddb_entry
->start
, hw_ddb_entry
->end
);
13576 verify_connector_state(struct drm_device
*dev
,
13577 struct drm_atomic_state
*state
,
13578 struct drm_crtc
*crtc
)
13580 struct drm_connector
*connector
;
13581 struct drm_connector_state
*old_conn_state
;
13584 for_each_connector_in_state(state
, connector
, old_conn_state
, i
) {
13585 struct drm_encoder
*encoder
= connector
->encoder
;
13586 struct drm_connector_state
*state
= connector
->state
;
13588 if (state
->crtc
!= crtc
)
13591 intel_connector_verify_state(to_intel_connector(connector
));
13593 I915_STATE_WARN(state
->best_encoder
!= encoder
,
13594 "connector's atomic encoder doesn't match legacy encoder\n");
13599 verify_encoder_state(struct drm_device
*dev
)
13601 struct intel_encoder
*encoder
;
13602 struct intel_connector
*connector
;
13604 for_each_intel_encoder(dev
, encoder
) {
13605 bool enabled
= false;
13608 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13609 encoder
->base
.base
.id
,
13610 encoder
->base
.name
);
13612 for_each_intel_connector(dev
, connector
) {
13613 if (connector
->base
.state
->best_encoder
!= &encoder
->base
)
13617 I915_STATE_WARN(connector
->base
.state
->crtc
!=
13618 encoder
->base
.crtc
,
13619 "connector's crtc doesn't match encoder crtc\n");
13622 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
13623 "encoder's enabled state mismatch "
13624 "(expected %i, found %i)\n",
13625 !!encoder
->base
.crtc
, enabled
);
13627 if (!encoder
->base
.crtc
) {
13630 active
= encoder
->get_hw_state(encoder
, &pipe
);
13631 I915_STATE_WARN(active
,
13632 "encoder detached but still enabled on pipe %c.\n",
13639 verify_crtc_state(struct drm_crtc
*crtc
,
13640 struct drm_crtc_state
*old_crtc_state
,
13641 struct drm_crtc_state
*new_crtc_state
)
13643 struct drm_device
*dev
= crtc
->dev
;
13644 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13645 struct intel_encoder
*encoder
;
13646 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13647 struct intel_crtc_state
*pipe_config
, *sw_config
;
13648 struct drm_atomic_state
*old_state
;
13651 old_state
= old_crtc_state
->state
;
13652 __drm_atomic_helper_crtc_destroy_state(old_crtc_state
);
13653 pipe_config
= to_intel_crtc_state(old_crtc_state
);
13654 memset(pipe_config
, 0, sizeof(*pipe_config
));
13655 pipe_config
->base
.crtc
= crtc
;
13656 pipe_config
->base
.state
= old_state
;
13658 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc
->base
.id
, crtc
->name
);
13660 active
= dev_priv
->display
.get_pipe_config(intel_crtc
, pipe_config
);
13662 /* hw state is inconsistent with the pipe quirk */
13663 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
13664 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
13665 active
= new_crtc_state
->active
;
13667 I915_STATE_WARN(new_crtc_state
->active
!= active
,
13668 "crtc active state doesn't match with hw state "
13669 "(expected %i, found %i)\n", new_crtc_state
->active
, active
);
13671 I915_STATE_WARN(intel_crtc
->active
!= new_crtc_state
->active
,
13672 "transitional active state does not match atomic hw state "
13673 "(expected %i, found %i)\n", new_crtc_state
->active
, intel_crtc
->active
);
13675 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
13678 active
= encoder
->get_hw_state(encoder
, &pipe
);
13679 I915_STATE_WARN(active
!= new_crtc_state
->active
,
13680 "[ENCODER:%i] active %i with crtc active %i\n",
13681 encoder
->base
.base
.id
, active
, new_crtc_state
->active
);
13683 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
13684 "Encoder connected to wrong pipe %c\n",
13688 pipe_config
->output_types
|= 1 << encoder
->type
;
13689 encoder
->get_config(encoder
, pipe_config
);
13693 if (!new_crtc_state
->active
)
13696 intel_pipe_config_sanity_check(dev_priv
, pipe_config
);
13698 sw_config
= to_intel_crtc_state(crtc
->state
);
13699 if (!intel_pipe_config_compare(dev_priv
, sw_config
,
13700 pipe_config
, false)) {
13701 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13702 intel_dump_pipe_config(intel_crtc
, pipe_config
,
13704 intel_dump_pipe_config(intel_crtc
, sw_config
,
13710 verify_single_dpll_state(struct drm_i915_private
*dev_priv
,
13711 struct intel_shared_dpll
*pll
,
13712 struct drm_crtc
*crtc
,
13713 struct drm_crtc_state
*new_state
)
13715 struct intel_dpll_hw_state dpll_hw_state
;
13716 unsigned crtc_mask
;
13719 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
13721 DRM_DEBUG_KMS("%s\n", pll
->name
);
13723 active
= pll
->funcs
.get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
13725 if (!(pll
->flags
& INTEL_DPLL_ALWAYS_ON
)) {
13726 I915_STATE_WARN(!pll
->on
&& pll
->active_mask
,
13727 "pll in active use but not on in sw tracking\n");
13728 I915_STATE_WARN(pll
->on
&& !pll
->active_mask
,
13729 "pll is on but not used by any active crtc\n");
13730 I915_STATE_WARN(pll
->on
!= active
,
13731 "pll on state mismatch (expected %i, found %i)\n",
13736 I915_STATE_WARN(pll
->active_mask
& ~pll
->config
.crtc_mask
,
13737 "more active pll users than references: %x vs %x\n",
13738 pll
->active_mask
, pll
->config
.crtc_mask
);
13743 crtc_mask
= 1 << drm_crtc_index(crtc
);
13745 if (new_state
->active
)
13746 I915_STATE_WARN(!(pll
->active_mask
& crtc_mask
),
13747 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13748 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13750 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13751 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13752 pipe_name(drm_crtc_index(crtc
)), pll
->active_mask
);
13754 I915_STATE_WARN(!(pll
->config
.crtc_mask
& crtc_mask
),
13755 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13756 crtc_mask
, pll
->config
.crtc_mask
);
13758 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
,
13760 sizeof(dpll_hw_state
)),
13761 "pll hw state mismatch\n");
13765 verify_shared_dpll_state(struct drm_device
*dev
, struct drm_crtc
*crtc
,
13766 struct drm_crtc_state
*old_crtc_state
,
13767 struct drm_crtc_state
*new_crtc_state
)
13769 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13770 struct intel_crtc_state
*old_state
= to_intel_crtc_state(old_crtc_state
);
13771 struct intel_crtc_state
*new_state
= to_intel_crtc_state(new_crtc_state
);
13773 if (new_state
->shared_dpll
)
13774 verify_single_dpll_state(dev_priv
, new_state
->shared_dpll
, crtc
, new_crtc_state
);
13776 if (old_state
->shared_dpll
&&
13777 old_state
->shared_dpll
!= new_state
->shared_dpll
) {
13778 unsigned crtc_mask
= 1 << drm_crtc_index(crtc
);
13779 struct intel_shared_dpll
*pll
= old_state
->shared_dpll
;
13781 I915_STATE_WARN(pll
->active_mask
& crtc_mask
,
13782 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13783 pipe_name(drm_crtc_index(crtc
)));
13784 I915_STATE_WARN(pll
->config
.crtc_mask
& crtc_mask
,
13785 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13786 pipe_name(drm_crtc_index(crtc
)));
13791 intel_modeset_verify_crtc(struct drm_crtc
*crtc
,
13792 struct drm_atomic_state
*state
,
13793 struct drm_crtc_state
*old_state
,
13794 struct drm_crtc_state
*new_state
)
13796 if (!needs_modeset(new_state
) &&
13797 !to_intel_crtc_state(new_state
)->update_pipe
)
13800 verify_wm_state(crtc
, new_state
);
13801 verify_connector_state(crtc
->dev
, state
, crtc
);
13802 verify_crtc_state(crtc
, old_state
, new_state
);
13803 verify_shared_dpll_state(crtc
->dev
, crtc
, old_state
, new_state
);
13807 verify_disabled_dpll_state(struct drm_device
*dev
)
13809 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13812 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++)
13813 verify_single_dpll_state(dev_priv
, &dev_priv
->shared_dplls
[i
], NULL
, NULL
);
13817 intel_modeset_verify_disabled(struct drm_device
*dev
,
13818 struct drm_atomic_state
*state
)
13820 verify_encoder_state(dev
);
13821 verify_connector_state(dev
, state
, NULL
);
13822 verify_disabled_dpll_state(dev
);
13825 static void update_scanline_offset(struct intel_crtc
*crtc
)
13827 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
13830 * The scanline counter increments at the leading edge of hsync.
13832 * On most platforms it starts counting from vtotal-1 on the
13833 * first active line. That means the scanline counter value is
13834 * always one less than what we would expect. Ie. just after
13835 * start of vblank, which also occurs at start of hsync (on the
13836 * last active line), the scanline counter will read vblank_start-1.
13838 * On gen2 the scanline counter starts counting from 1 instead
13839 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13840 * to keep the value positive), instead of adding one.
13842 * On HSW+ the behaviour of the scanline counter depends on the output
13843 * type. For DP ports it behaves like most other platforms, but on HDMI
13844 * there's an extra 1 line difference. So we need to add two instead of
13845 * one to the value.
13847 if (IS_GEN2(dev_priv
)) {
13848 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
13851 vtotal
= adjusted_mode
->crtc_vtotal
;
13852 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
13855 crtc
->scanline_offset
= vtotal
- 1;
13856 } else if (HAS_DDI(dev_priv
) &&
13857 intel_crtc_has_type(crtc
->config
, INTEL_OUTPUT_HDMI
)) {
13858 crtc
->scanline_offset
= 2;
13860 crtc
->scanline_offset
= 1;
13863 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
13865 struct drm_device
*dev
= state
->dev
;
13866 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13867 struct intel_shared_dpll_config
*shared_dpll
= NULL
;
13868 struct drm_crtc
*crtc
;
13869 struct drm_crtc_state
*crtc_state
;
13872 if (!dev_priv
->display
.crtc_compute_clock
)
13875 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13876 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13877 struct intel_shared_dpll
*old_dpll
=
13878 to_intel_crtc_state(crtc
->state
)->shared_dpll
;
13880 if (!needs_modeset(crtc_state
))
13883 to_intel_crtc_state(crtc_state
)->shared_dpll
= NULL
;
13889 shared_dpll
= intel_atomic_get_shared_dpll_state(state
);
13891 intel_shared_dpll_config_put(shared_dpll
, old_dpll
, intel_crtc
);
13896 * This implements the workaround described in the "notes" section of the mode
13897 * set sequence documentation. When going from no pipes or single pipe to
13898 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13899 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13901 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
13903 struct drm_crtc_state
*crtc_state
;
13904 struct intel_crtc
*intel_crtc
;
13905 struct drm_crtc
*crtc
;
13906 struct intel_crtc_state
*first_crtc_state
= NULL
;
13907 struct intel_crtc_state
*other_crtc_state
= NULL
;
13908 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
13911 /* look at all crtc's that are going to be enabled in during modeset */
13912 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13913 intel_crtc
= to_intel_crtc(crtc
);
13915 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
13918 if (first_crtc_state
) {
13919 other_crtc_state
= to_intel_crtc_state(crtc_state
);
13922 first_crtc_state
= to_intel_crtc_state(crtc_state
);
13923 first_pipe
= intel_crtc
->pipe
;
13927 /* No workaround needed? */
13928 if (!first_crtc_state
)
13931 /* w/a possibly needed, check how many crtc's are already enabled. */
13932 for_each_intel_crtc(state
->dev
, intel_crtc
) {
13933 struct intel_crtc_state
*pipe_config
;
13935 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13936 if (IS_ERR(pipe_config
))
13937 return PTR_ERR(pipe_config
);
13939 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
13941 if (!pipe_config
->base
.active
||
13942 needs_modeset(&pipe_config
->base
))
13945 /* 2 or more enabled crtcs means no need for w/a */
13946 if (enabled_pipe
!= INVALID_PIPE
)
13949 enabled_pipe
= intel_crtc
->pipe
;
13952 if (enabled_pipe
!= INVALID_PIPE
)
13953 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13954 else if (other_crtc_state
)
13955 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13960 static int intel_lock_all_pipes(struct drm_atomic_state
*state
)
13962 struct drm_crtc
*crtc
;
13964 /* Add all pipes to the state */
13965 for_each_crtc(state
->dev
, crtc
) {
13966 struct drm_crtc_state
*crtc_state
;
13968 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13969 if (IS_ERR(crtc_state
))
13970 return PTR_ERR(crtc_state
);
13976 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13978 struct drm_crtc
*crtc
;
13981 * Add all pipes to the state, and force
13982 * a modeset on all the active ones.
13984 for_each_crtc(state
->dev
, crtc
) {
13985 struct drm_crtc_state
*crtc_state
;
13988 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13989 if (IS_ERR(crtc_state
))
13990 return PTR_ERR(crtc_state
);
13992 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13995 crtc_state
->mode_changed
= true;
13997 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
14001 ret
= drm_atomic_add_affected_planes(state
, crtc
);
14009 static int intel_modeset_checks(struct drm_atomic_state
*state
)
14011 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14012 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
14013 struct drm_crtc
*crtc
;
14014 struct drm_crtc_state
*crtc_state
;
14017 if (!check_digital_port_conflicts(state
)) {
14018 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
14022 intel_state
->modeset
= true;
14023 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
14025 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
14026 if (crtc_state
->active
)
14027 intel_state
->active_crtcs
|= 1 << i
;
14029 intel_state
->active_crtcs
&= ~(1 << i
);
14031 if (crtc_state
->active
!= crtc
->state
->active
)
14032 intel_state
->active_pipe_changes
|= drm_crtc_mask(crtc
);
14036 * See if the config requires any additional preparation, e.g.
14037 * to adjust global state with pipes off. We need to do this
14038 * here so we can get the modeset_pipe updated config for the new
14039 * mode set on this crtc. For other crtcs we need to use the
14040 * adjusted_mode bits in the crtc directly.
14042 if (dev_priv
->display
.modeset_calc_cdclk
) {
14043 if (!intel_state
->cdclk_pll_vco
)
14044 intel_state
->cdclk_pll_vco
= dev_priv
->cdclk_pll
.vco
;
14045 if (!intel_state
->cdclk_pll_vco
)
14046 intel_state
->cdclk_pll_vco
= dev_priv
->skl_preferred_vco_freq
;
14048 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
14053 * Writes to dev_priv->atomic_cdclk_freq must protected by
14054 * holding all the crtc locks, even if we don't end up
14055 * touching the hardware
14057 if (intel_state
->cdclk
!= dev_priv
->atomic_cdclk_freq
) {
14058 ret
= intel_lock_all_pipes(state
);
14063 /* All pipes must be switched off while we change the cdclk. */
14064 if (intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
||
14065 intel_state
->cdclk_pll_vco
!= dev_priv
->cdclk_pll
.vco
) {
14066 ret
= intel_modeset_all_pipes(state
);
14071 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
14072 intel_state
->cdclk
, intel_state
->dev_cdclk
);
14074 to_intel_atomic_state(state
)->cdclk
= dev_priv
->atomic_cdclk_freq
;
14077 intel_modeset_clear_plls(state
);
14079 if (IS_HASWELL(dev_priv
))
14080 return haswell_mode_set_planes_workaround(state
);
14086 * Handle calculation of various watermark data at the end of the atomic check
14087 * phase. The code here should be run after the per-crtc and per-plane 'check'
14088 * handlers to ensure that all derived state has been updated.
14090 static int calc_watermark_data(struct drm_atomic_state
*state
)
14092 struct drm_device
*dev
= state
->dev
;
14093 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14095 /* Is there platform-specific watermark information to calculate? */
14096 if (dev_priv
->display
.compute_global_watermarks
)
14097 return dev_priv
->display
.compute_global_watermarks(state
);
14103 * intel_atomic_check - validate state object
14105 * @state: state to validate
14107 static int intel_atomic_check(struct drm_device
*dev
,
14108 struct drm_atomic_state
*state
)
14110 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14111 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14112 struct drm_crtc
*crtc
;
14113 struct drm_crtc_state
*crtc_state
;
14115 bool any_ms
= false;
14117 ret
= drm_atomic_helper_check_modeset(dev
, state
);
14121 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
14122 struct intel_crtc_state
*pipe_config
=
14123 to_intel_crtc_state(crtc_state
);
14125 /* Catch I915_MODE_FLAG_INHERITED */
14126 if (crtc_state
->mode
.private_flags
!= crtc
->state
->mode
.private_flags
)
14127 crtc_state
->mode_changed
= true;
14129 if (!needs_modeset(crtc_state
))
14132 if (!crtc_state
->enable
) {
14137 /* FIXME: For only active_changed we shouldn't need to do any
14138 * state recomputation at all. */
14140 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
14144 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
14146 intel_dump_pipe_config(to_intel_crtc(crtc
),
14147 pipe_config
, "[failed]");
14151 if (i915
.fastboot
&&
14152 intel_pipe_config_compare(dev_priv
,
14153 to_intel_crtc_state(crtc
->state
),
14154 pipe_config
, true)) {
14155 crtc_state
->mode_changed
= false;
14156 to_intel_crtc_state(crtc_state
)->update_pipe
= true;
14159 if (needs_modeset(crtc_state
))
14162 ret
= drm_atomic_add_affected_planes(state
, crtc
);
14166 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
14167 needs_modeset(crtc_state
) ?
14168 "[modeset]" : "[fastset]");
14172 ret
= intel_modeset_checks(state
);
14177 intel_state
->cdclk
= dev_priv
->atomic_cdclk_freq
;
14180 ret
= drm_atomic_helper_check_planes(dev
, state
);
14184 intel_fbc_choose_crtc(dev_priv
, state
);
14185 return calc_watermark_data(state
);
14188 static int intel_atomic_prepare_commit(struct drm_device
*dev
,
14189 struct drm_atomic_state
*state
)
14191 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14192 struct drm_crtc_state
*crtc_state
;
14193 struct drm_crtc
*crtc
;
14196 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
14197 if (state
->legacy_cursor_update
)
14200 ret
= intel_crtc_wait_for_pending_flips(crtc
);
14204 if (atomic_read(&to_intel_crtc(crtc
)->unpin_work_count
) >= 2)
14205 flush_workqueue(dev_priv
->wq
);
14208 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
14212 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
14213 mutex_unlock(&dev
->struct_mutex
);
14218 u32
intel_crtc_get_vblank_counter(struct intel_crtc
*crtc
)
14220 struct drm_device
*dev
= crtc
->base
.dev
;
14222 if (!dev
->max_vblank_count
)
14223 return drm_accurate_vblank_count(&crtc
->base
);
14225 return dev
->driver
->get_vblank_counter(dev
, crtc
->pipe
);
14228 static void intel_atomic_wait_for_vblanks(struct drm_device
*dev
,
14229 struct drm_i915_private
*dev_priv
,
14230 unsigned crtc_mask
)
14232 unsigned last_vblank_count
[I915_MAX_PIPES
];
14239 for_each_pipe(dev_priv
, pipe
) {
14240 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
,
14243 if (!((1 << pipe
) & crtc_mask
))
14246 ret
= drm_crtc_vblank_get(&crtc
->base
);
14247 if (WARN_ON(ret
!= 0)) {
14248 crtc_mask
&= ~(1 << pipe
);
14252 last_vblank_count
[pipe
] = drm_crtc_vblank_count(&crtc
->base
);
14255 for_each_pipe(dev_priv
, pipe
) {
14256 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
,
14260 if (!((1 << pipe
) & crtc_mask
))
14263 lret
= wait_event_timeout(dev
->vblank
[pipe
].queue
,
14264 last_vblank_count
[pipe
] !=
14265 drm_crtc_vblank_count(&crtc
->base
),
14266 msecs_to_jiffies(50));
14268 WARN(!lret
, "pipe %c vblank wait timed out\n", pipe_name(pipe
));
14270 drm_crtc_vblank_put(&crtc
->base
);
14274 static bool needs_vblank_wait(struct intel_crtc_state
*crtc_state
)
14276 /* fb updated, need to unpin old fb */
14277 if (crtc_state
->fb_changed
)
14280 /* wm changes, need vblank before final wm's */
14281 if (crtc_state
->update_wm_post
)
14285 * cxsr is re-enabled after vblank.
14286 * This is already handled by crtc_state->update_wm_post,
14287 * but added for clarity.
14289 if (crtc_state
->disable_cxsr
)
14295 static void intel_update_crtc(struct drm_crtc
*crtc
,
14296 struct drm_atomic_state
*state
,
14297 struct drm_crtc_state
*old_crtc_state
,
14298 unsigned int *crtc_vblank_mask
)
14300 struct drm_device
*dev
= crtc
->dev
;
14301 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14302 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14303 struct intel_crtc_state
*pipe_config
= to_intel_crtc_state(crtc
->state
);
14304 bool modeset
= needs_modeset(crtc
->state
);
14307 update_scanline_offset(intel_crtc
);
14308 dev_priv
->display
.crtc_enable(pipe_config
, state
);
14310 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
14313 if (drm_atomic_get_existing_plane_state(state
, crtc
->primary
)) {
14315 intel_crtc
, pipe_config
,
14316 to_intel_plane_state(crtc
->primary
->state
));
14319 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state
);
14321 if (needs_vblank_wait(pipe_config
))
14322 *crtc_vblank_mask
|= drm_crtc_mask(crtc
);
14325 static void intel_update_crtcs(struct drm_atomic_state
*state
,
14326 unsigned int *crtc_vblank_mask
)
14328 struct drm_crtc
*crtc
;
14329 struct drm_crtc_state
*old_crtc_state
;
14332 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14333 if (!crtc
->state
->active
)
14336 intel_update_crtc(crtc
, state
, old_crtc_state
,
14341 static void skl_update_crtcs(struct drm_atomic_state
*state
,
14342 unsigned int *crtc_vblank_mask
)
14344 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
14345 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14346 struct drm_crtc
*crtc
;
14347 struct intel_crtc
*intel_crtc
;
14348 struct drm_crtc_state
*old_crtc_state
;
14349 struct intel_crtc_state
*cstate
;
14350 unsigned int updated
= 0;
14355 const struct skl_ddb_entry
*entries
[I915_MAX_PIPES
] = {};
14357 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
)
14358 /* ignore allocations for crtc's that have been turned off. */
14359 if (crtc
->state
->active
)
14360 entries
[i
] = &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
;
14363 * Whenever the number of active pipes changes, we need to make sure we
14364 * update the pipes in the right order so that their ddb allocations
14365 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14366 * cause pipe underruns and other bad stuff.
14371 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14372 bool vbl_wait
= false;
14373 unsigned int cmask
= drm_crtc_mask(crtc
);
14375 intel_crtc
= to_intel_crtc(crtc
);
14376 cstate
= to_intel_crtc_state(crtc
->state
);
14377 pipe
= intel_crtc
->pipe
;
14379 if (updated
& cmask
|| !cstate
->base
.active
)
14382 if (skl_ddb_allocation_overlaps(entries
, &cstate
->wm
.skl
.ddb
, i
))
14386 entries
[i
] = &cstate
->wm
.skl
.ddb
;
14389 * If this is an already active pipe, it's DDB changed,
14390 * and this isn't the last pipe that needs updating
14391 * then we need to wait for a vblank to pass for the
14392 * new ddb allocation to take effect.
14394 if (!skl_ddb_entry_equal(&cstate
->wm
.skl
.ddb
,
14395 &to_intel_crtc_state(old_crtc_state
)->wm
.skl
.ddb
) &&
14396 !crtc
->state
->active_changed
&&
14397 intel_state
->wm_results
.dirty_pipes
!= updated
)
14400 intel_update_crtc(crtc
, state
, old_crtc_state
,
14404 intel_wait_for_vblank(dev_priv
, pipe
);
14408 } while (progress
);
14411 static void intel_atomic_commit_tail(struct drm_atomic_state
*state
)
14413 struct drm_device
*dev
= state
->dev
;
14414 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14415 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14416 struct drm_crtc_state
*old_crtc_state
;
14417 struct drm_crtc
*crtc
;
14418 struct intel_crtc_state
*intel_cstate
;
14419 bool hw_check
= intel_state
->modeset
;
14420 unsigned long put_domains
[I915_MAX_PIPES
] = {};
14421 unsigned crtc_vblank_mask
= 0;
14424 drm_atomic_helper_wait_for_dependencies(state
);
14426 if (intel_state
->modeset
)
14427 intel_display_power_get(dev_priv
, POWER_DOMAIN_MODESET
);
14429 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14430 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14432 if (needs_modeset(crtc
->state
) ||
14433 to_intel_crtc_state(crtc
->state
)->update_pipe
) {
14436 put_domains
[to_intel_crtc(crtc
)->pipe
] =
14437 modeset_get_crtc_power_domains(crtc
,
14438 to_intel_crtc_state(crtc
->state
));
14441 if (!needs_modeset(crtc
->state
))
14444 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state
));
14446 if (old_crtc_state
->active
) {
14447 intel_crtc_disable_planes(crtc
, old_crtc_state
->plane_mask
);
14448 dev_priv
->display
.crtc_disable(to_intel_crtc_state(old_crtc_state
), state
);
14449 intel_crtc
->active
= false;
14450 intel_fbc_disable(intel_crtc
);
14451 intel_disable_shared_dpll(intel_crtc
);
14454 * Underruns don't always raise
14455 * interrupts, so check manually.
14457 intel_check_cpu_fifo_underruns(dev_priv
);
14458 intel_check_pch_fifo_underruns(dev_priv
);
14460 if (!crtc
->state
->active
) {
14462 * Make sure we don't call initial_watermarks
14463 * for ILK-style watermark updates.
14465 if (dev_priv
->display
.atomic_update_watermarks
)
14466 dev_priv
->display
.initial_watermarks(intel_state
,
14467 to_intel_crtc_state(crtc
->state
));
14469 intel_update_watermarks(intel_crtc
);
14474 /* Only after disabling all output pipelines that will be changed can we
14475 * update the the output configuration. */
14476 intel_modeset_update_crtc_state(state
);
14478 if (intel_state
->modeset
) {
14479 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
14481 if (dev_priv
->display
.modeset_commit_cdclk
&&
14482 (intel_state
->dev_cdclk
!= dev_priv
->cdclk_freq
||
14483 intel_state
->cdclk_pll_vco
!= dev_priv
->cdclk_pll
.vco
))
14484 dev_priv
->display
.modeset_commit_cdclk(state
);
14487 * SKL workaround: bspec recommends we disable the SAGV when we
14488 * have more then one pipe enabled
14490 if (!intel_can_enable_sagv(state
))
14491 intel_disable_sagv(dev_priv
);
14493 intel_modeset_verify_disabled(dev
, state
);
14496 /* Complete the events for pipes that have now been disabled */
14497 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14498 bool modeset
= needs_modeset(crtc
->state
);
14500 /* Complete events for now disable pipes here. */
14501 if (modeset
&& !crtc
->state
->active
&& crtc
->state
->event
) {
14502 spin_lock_irq(&dev
->event_lock
);
14503 drm_crtc_send_vblank_event(crtc
, crtc
->state
->event
);
14504 spin_unlock_irq(&dev
->event_lock
);
14506 crtc
->state
->event
= NULL
;
14510 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14511 dev_priv
->display
.update_crtcs(state
, &crtc_vblank_mask
);
14513 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14514 * already, but still need the state for the delayed optimization. To
14516 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14517 * - schedule that vblank worker _before_ calling hw_done
14518 * - at the start of commit_tail, cancel it _synchrously
14519 * - switch over to the vblank wait helper in the core after that since
14520 * we don't need out special handling any more.
14522 if (!state
->legacy_cursor_update
)
14523 intel_atomic_wait_for_vblanks(dev
, dev_priv
, crtc_vblank_mask
);
14526 * Now that the vblank has passed, we can go ahead and program the
14527 * optimal watermarks on platforms that need two-step watermark
14530 * TODO: Move this (and other cleanup) to an async worker eventually.
14532 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14533 intel_cstate
= to_intel_crtc_state(crtc
->state
);
14535 if (dev_priv
->display
.optimize_watermarks
)
14536 dev_priv
->display
.optimize_watermarks(intel_state
,
14540 for_each_crtc_in_state(state
, crtc
, old_crtc_state
, i
) {
14541 intel_post_plane_update(to_intel_crtc_state(old_crtc_state
));
14543 if (put_domains
[i
])
14544 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
14546 intel_modeset_verify_crtc(crtc
, state
, old_crtc_state
, crtc
->state
);
14549 if (intel_state
->modeset
&& intel_can_enable_sagv(state
))
14550 intel_enable_sagv(dev_priv
);
14552 drm_atomic_helper_commit_hw_done(state
);
14554 if (intel_state
->modeset
)
14555 intel_display_power_put(dev_priv
, POWER_DOMAIN_MODESET
);
14557 mutex_lock(&dev
->struct_mutex
);
14558 drm_atomic_helper_cleanup_planes(dev
, state
);
14559 mutex_unlock(&dev
->struct_mutex
);
14561 drm_atomic_helper_commit_cleanup_done(state
);
14563 drm_atomic_state_put(state
);
14565 /* As one of the primary mmio accessors, KMS has a high likelihood
14566 * of triggering bugs in unclaimed access. After we finish
14567 * modesetting, see if an error has been flagged, and if so
14568 * enable debugging for the next modeset - and hope we catch
14571 * XXX note that we assume display power is on at this point.
14572 * This might hold true now but we need to add pm helper to check
14573 * unclaimed only when the hardware is on, as atomic commits
14574 * can happen also when the device is completely off.
14576 intel_uncore_arm_unclaimed_mmio_detection(dev_priv
);
14579 static void intel_atomic_commit_work(struct work_struct
*work
)
14581 struct drm_atomic_state
*state
=
14582 container_of(work
, struct drm_atomic_state
, commit_work
);
14584 intel_atomic_commit_tail(state
);
14587 static int __i915_sw_fence_call
14588 intel_atomic_commit_ready(struct i915_sw_fence
*fence
,
14589 enum i915_sw_fence_notify notify
)
14591 struct intel_atomic_state
*state
=
14592 container_of(fence
, struct intel_atomic_state
, commit_ready
);
14595 case FENCE_COMPLETE
:
14596 if (state
->base
.commit_work
.func
)
14597 queue_work(system_unbound_wq
, &state
->base
.commit_work
);
14601 drm_atomic_state_put(&state
->base
);
14605 return NOTIFY_DONE
;
14608 static void intel_atomic_track_fbs(struct drm_atomic_state
*state
)
14610 struct drm_plane_state
*old_plane_state
;
14611 struct drm_plane
*plane
;
14614 for_each_plane_in_state(state
, plane
, old_plane_state
, i
)
14615 i915_gem_track_fb(intel_fb_obj(old_plane_state
->fb
),
14616 intel_fb_obj(plane
->state
->fb
),
14617 to_intel_plane(plane
)->frontbuffer_bit
);
14621 * intel_atomic_commit - commit validated state object
14623 * @state: the top-level driver state object
14624 * @nonblock: nonblocking commit
14626 * This function commits a top-level state object that has been validated
14627 * with drm_atomic_helper_check().
14630 * Zero for success or -errno.
14632 static int intel_atomic_commit(struct drm_device
*dev
,
14633 struct drm_atomic_state
*state
,
14636 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
14637 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14640 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
14644 drm_atomic_state_get(state
);
14645 i915_sw_fence_init(&intel_state
->commit_ready
,
14646 intel_atomic_commit_ready
);
14648 ret
= intel_atomic_prepare_commit(dev
, state
);
14650 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret
);
14651 i915_sw_fence_commit(&intel_state
->commit_ready
);
14655 drm_atomic_helper_swap_state(state
, true);
14656 dev_priv
->wm
.distrust_bios_wm
= false;
14657 intel_shared_dpll_commit(state
);
14658 intel_atomic_track_fbs(state
);
14660 if (intel_state
->modeset
) {
14661 memcpy(dev_priv
->min_pixclk
, intel_state
->min_pixclk
,
14662 sizeof(intel_state
->min_pixclk
));
14663 dev_priv
->active_crtcs
= intel_state
->active_crtcs
;
14664 dev_priv
->atomic_cdclk_freq
= intel_state
->cdclk
;
14667 drm_atomic_state_get(state
);
14668 INIT_WORK(&state
->commit_work
,
14669 nonblock
? intel_atomic_commit_work
: NULL
);
14671 i915_sw_fence_commit(&intel_state
->commit_ready
);
14673 i915_sw_fence_wait(&intel_state
->commit_ready
);
14674 intel_atomic_commit_tail(state
);
14680 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
14682 struct drm_device
*dev
= crtc
->dev
;
14683 struct drm_atomic_state
*state
;
14684 struct drm_crtc_state
*crtc_state
;
14687 state
= drm_atomic_state_alloc(dev
);
14689 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14690 crtc
->base
.id
, crtc
->name
);
14694 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
14697 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
14698 ret
= PTR_ERR_OR_ZERO(crtc_state
);
14700 if (!crtc_state
->active
)
14703 crtc_state
->mode_changed
= true;
14704 ret
= drm_atomic_commit(state
);
14707 if (ret
== -EDEADLK
) {
14708 drm_atomic_state_clear(state
);
14709 drm_modeset_backoff(state
->acquire_ctx
);
14714 drm_atomic_state_put(state
);
14718 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14719 * drm_atomic_helper_legacy_gamma_set() directly.
14721 static int intel_atomic_legacy_gamma_set(struct drm_crtc
*crtc
,
14722 u16
*red
, u16
*green
, u16
*blue
,
14725 struct drm_device
*dev
= crtc
->dev
;
14726 struct drm_mode_config
*config
= &dev
->mode_config
;
14727 struct drm_crtc_state
*state
;
14730 ret
= drm_atomic_helper_legacy_gamma_set(crtc
, red
, green
, blue
, size
);
14735 * Make sure we update the legacy properties so this works when
14736 * atomic is not enabled.
14739 state
= crtc
->state
;
14741 drm_object_property_set_value(&crtc
->base
,
14742 config
->degamma_lut_property
,
14743 (state
->degamma_lut
) ?
14744 state
->degamma_lut
->base
.id
: 0);
14746 drm_object_property_set_value(&crtc
->base
,
14747 config
->ctm_property
,
14749 state
->ctm
->base
.id
: 0);
14751 drm_object_property_set_value(&crtc
->base
,
14752 config
->gamma_lut_property
,
14753 (state
->gamma_lut
) ?
14754 state
->gamma_lut
->base
.id
: 0);
14759 static const struct drm_crtc_funcs intel_crtc_funcs
= {
14760 .gamma_set
= intel_atomic_legacy_gamma_set
,
14761 .set_config
= drm_atomic_helper_set_config
,
14762 .set_property
= drm_atomic_helper_crtc_set_property
,
14763 .destroy
= intel_crtc_destroy
,
14764 .page_flip
= intel_crtc_page_flip
,
14765 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
14766 .atomic_destroy_state
= intel_crtc_destroy_state
,
14770 * intel_prepare_plane_fb - Prepare fb for usage on plane
14771 * @plane: drm plane to prepare for
14772 * @fb: framebuffer to prepare for presentation
14774 * Prepares a framebuffer for usage on a display plane. Generally this
14775 * involves pinning the underlying object and updating the frontbuffer tracking
14776 * bits. Some older platforms need special physical address handling for
14779 * Must be called with struct_mutex held.
14781 * Returns 0 on success, negative error code on failure.
14784 intel_prepare_plane_fb(struct drm_plane
*plane
,
14785 struct drm_plane_state
*new_state
)
14787 struct intel_atomic_state
*intel_state
=
14788 to_intel_atomic_state(new_state
->state
);
14789 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14790 struct drm_framebuffer
*fb
= new_state
->fb
;
14791 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
14792 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->state
->fb
);
14795 if (!obj
&& !old_obj
)
14799 struct drm_crtc_state
*crtc_state
=
14800 drm_atomic_get_existing_crtc_state(new_state
->state
,
14801 plane
->state
->crtc
);
14803 /* Big Hammer, we also need to ensure that any pending
14804 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14805 * current scanout is retired before unpinning the old
14806 * framebuffer. Note that we rely on userspace rendering
14807 * into the buffer attached to the pipe they are waiting
14808 * on. If not, userspace generates a GPU hang with IPEHR
14809 * point to the MI_WAIT_FOR_EVENT.
14811 * This should only fail upon a hung GPU, in which case we
14812 * can safely continue.
14814 if (needs_modeset(crtc_state
)) {
14815 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
14816 old_obj
->resv
, NULL
,
14824 if (new_state
->fence
) { /* explicit fencing */
14825 ret
= i915_sw_fence_await_dma_fence(&intel_state
->commit_ready
,
14827 I915_FENCE_TIMEOUT
,
14836 if (!new_state
->fence
) { /* implicit fencing */
14837 ret
= i915_sw_fence_await_reservation(&intel_state
->commit_ready
,
14839 false, I915_FENCE_TIMEOUT
,
14844 i915_gem_object_wait_priority(obj
, 0, I915_PRIORITY_DISPLAY
);
14847 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
14848 INTEL_INFO(dev_priv
)->cursor_needs_physical
) {
14849 int align
= IS_I830(dev_priv
) ? 16 * 1024 : 256;
14850 ret
= i915_gem_object_attach_phys(obj
, align
);
14852 DRM_DEBUG_KMS("failed to attach phys object\n");
14856 struct i915_vma
*vma
;
14858 vma
= intel_pin_and_fence_fb_obj(fb
, new_state
->rotation
);
14860 DRM_DEBUG_KMS("failed to pin object\n");
14861 return PTR_ERR(vma
);
14869 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14870 * @plane: drm plane to clean up for
14871 * @fb: old framebuffer that was on plane
14873 * Cleans up a framebuffer that has just been removed from a plane.
14875 * Must be called with struct_mutex held.
14878 intel_cleanup_plane_fb(struct drm_plane
*plane
,
14879 struct drm_plane_state
*old_state
)
14881 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14882 struct intel_plane_state
*old_intel_state
;
14883 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_state
->fb
);
14884 struct drm_i915_gem_object
*obj
= intel_fb_obj(plane
->state
->fb
);
14886 old_intel_state
= to_intel_plane_state(old_state
);
14888 if (!obj
&& !old_obj
)
14891 if (old_obj
&& (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
14892 !INTEL_INFO(dev_priv
)->cursor_needs_physical
))
14893 intel_unpin_fb_obj(old_state
->fb
, old_state
->rotation
);
14897 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
14900 int crtc_clock
, cdclk
;
14902 if (!intel_crtc
|| !crtc_state
->base
.enable
)
14903 return DRM_PLANE_HELPER_NO_SCALING
;
14905 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
14906 cdclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
;
14908 if (WARN_ON_ONCE(!crtc_clock
|| cdclk
< crtc_clock
))
14909 return DRM_PLANE_HELPER_NO_SCALING
;
14912 * skl max scale is lower of:
14913 * close to 3 but not 3, -1 is for that purpose
14917 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
14923 intel_check_primary_plane(struct drm_plane
*plane
,
14924 struct intel_crtc_state
*crtc_state
,
14925 struct intel_plane_state
*state
)
14927 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
14928 struct drm_crtc
*crtc
= state
->base
.crtc
;
14929 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
14930 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
14931 bool can_position
= false;
14934 if (INTEL_GEN(dev_priv
) >= 9) {
14935 /* use scaler when colorkey is not required */
14936 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
14938 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
14940 can_position
= true;
14943 ret
= drm_plane_helper_check_state(&state
->base
,
14945 min_scale
, max_scale
,
14946 can_position
, true);
14950 if (!state
->base
.fb
)
14953 if (INTEL_GEN(dev_priv
) >= 9) {
14954 ret
= skl_check_plane_surface(state
);
14962 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
14963 struct drm_crtc_state
*old_crtc_state
)
14965 struct drm_device
*dev
= crtc
->dev
;
14966 struct drm_i915_private
*dev_priv
= to_i915(dev
);
14967 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
14968 struct intel_crtc_state
*intel_cstate
=
14969 to_intel_crtc_state(crtc
->state
);
14970 struct intel_crtc_state
*old_intel_cstate
=
14971 to_intel_crtc_state(old_crtc_state
);
14972 struct intel_atomic_state
*old_intel_state
=
14973 to_intel_atomic_state(old_crtc_state
->state
);
14974 bool modeset
= needs_modeset(crtc
->state
);
14976 /* Perform vblank evasion around commit operation */
14977 intel_pipe_update_start(intel_crtc
);
14982 if (crtc
->state
->color_mgmt_changed
|| to_intel_crtc_state(crtc
->state
)->update_pipe
) {
14983 intel_color_set_csc(crtc
->state
);
14984 intel_color_load_luts(crtc
->state
);
14987 if (intel_cstate
->update_pipe
)
14988 intel_update_pipe_config(intel_crtc
, old_intel_cstate
);
14989 else if (INTEL_GEN(dev_priv
) >= 9)
14990 skl_detach_scalers(intel_crtc
);
14993 if (dev_priv
->display
.atomic_update_watermarks
)
14994 dev_priv
->display
.atomic_update_watermarks(old_intel_state
,
14998 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
14999 struct drm_crtc_state
*old_crtc_state
)
15001 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
15003 intel_pipe_update_end(intel_crtc
, NULL
);
15007 * intel_plane_destroy - destroy a plane
15008 * @plane: plane to destroy
15010 * Common destruction function for all types of planes (primary, cursor,
15013 void intel_plane_destroy(struct drm_plane
*plane
)
15015 drm_plane_cleanup(plane
);
15016 kfree(to_intel_plane(plane
));
15019 const struct drm_plane_funcs intel_plane_funcs
= {
15020 .update_plane
= drm_atomic_helper_update_plane
,
15021 .disable_plane
= drm_atomic_helper_disable_plane
,
15022 .destroy
= intel_plane_destroy
,
15023 .set_property
= drm_atomic_helper_plane_set_property
,
15024 .atomic_get_property
= intel_plane_atomic_get_property
,
15025 .atomic_set_property
= intel_plane_atomic_set_property
,
15026 .atomic_duplicate_state
= intel_plane_duplicate_state
,
15027 .atomic_destroy_state
= intel_plane_destroy_state
,
15030 static struct intel_plane
*
15031 intel_primary_plane_create(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15033 struct intel_plane
*primary
= NULL
;
15034 struct intel_plane_state
*state
= NULL
;
15035 const uint32_t *intel_primary_formats
;
15036 unsigned int supported_rotations
;
15037 unsigned int num_formats
;
15040 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
15046 state
= intel_create_plane_state(&primary
->base
);
15052 primary
->base
.state
= &state
->base
;
15054 primary
->can_scale
= false;
15055 primary
->max_downscale
= 1;
15056 if (INTEL_GEN(dev_priv
) >= 9) {
15057 primary
->can_scale
= true;
15058 state
->scaler_id
= -1;
15060 primary
->pipe
= pipe
;
15062 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
15063 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
15065 if (HAS_FBC(dev_priv
) && INTEL_GEN(dev_priv
) < 4)
15066 primary
->plane
= (enum plane
) !pipe
;
15068 primary
->plane
= (enum plane
) pipe
;
15069 primary
->id
= PLANE_PRIMARY
;
15070 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
15071 primary
->check_plane
= intel_check_primary_plane
;
15073 if (INTEL_GEN(dev_priv
) >= 9) {
15074 intel_primary_formats
= skl_primary_formats
;
15075 num_formats
= ARRAY_SIZE(skl_primary_formats
);
15077 primary
->update_plane
= skylake_update_primary_plane
;
15078 primary
->disable_plane
= skylake_disable_primary_plane
;
15079 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15080 intel_primary_formats
= i965_primary_formats
;
15081 num_formats
= ARRAY_SIZE(i965_primary_formats
);
15083 primary
->update_plane
= ironlake_update_primary_plane
;
15084 primary
->disable_plane
= i9xx_disable_primary_plane
;
15085 } else if (INTEL_GEN(dev_priv
) >= 4) {
15086 intel_primary_formats
= i965_primary_formats
;
15087 num_formats
= ARRAY_SIZE(i965_primary_formats
);
15089 primary
->update_plane
= i9xx_update_primary_plane
;
15090 primary
->disable_plane
= i9xx_disable_primary_plane
;
15092 intel_primary_formats
= i8xx_primary_formats
;
15093 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
15095 primary
->update_plane
= i9xx_update_primary_plane
;
15096 primary
->disable_plane
= i9xx_disable_primary_plane
;
15099 if (INTEL_GEN(dev_priv
) >= 9)
15100 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
15101 0, &intel_plane_funcs
,
15102 intel_primary_formats
, num_formats
,
15103 DRM_PLANE_TYPE_PRIMARY
,
15104 "plane 1%c", pipe_name(pipe
));
15105 else if (INTEL_GEN(dev_priv
) >= 5 || IS_G4X(dev_priv
))
15106 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
15107 0, &intel_plane_funcs
,
15108 intel_primary_formats
, num_formats
,
15109 DRM_PLANE_TYPE_PRIMARY
,
15110 "primary %c", pipe_name(pipe
));
15112 ret
= drm_universal_plane_init(&dev_priv
->drm
, &primary
->base
,
15113 0, &intel_plane_funcs
,
15114 intel_primary_formats
, num_formats
,
15115 DRM_PLANE_TYPE_PRIMARY
,
15116 "plane %c", plane_name(primary
->plane
));
15120 if (INTEL_GEN(dev_priv
) >= 9) {
15121 supported_rotations
=
15122 DRM_ROTATE_0
| DRM_ROTATE_90
|
15123 DRM_ROTATE_180
| DRM_ROTATE_270
;
15124 } else if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
15125 supported_rotations
=
15126 DRM_ROTATE_0
| DRM_ROTATE_180
|
15128 } else if (INTEL_GEN(dev_priv
) >= 4) {
15129 supported_rotations
=
15130 DRM_ROTATE_0
| DRM_ROTATE_180
;
15132 supported_rotations
= DRM_ROTATE_0
;
15135 if (INTEL_GEN(dev_priv
) >= 4)
15136 drm_plane_create_rotation_property(&primary
->base
,
15138 supported_rotations
);
15140 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
15148 return ERR_PTR(ret
);
15152 intel_check_cursor_plane(struct drm_plane
*plane
,
15153 struct intel_crtc_state
*crtc_state
,
15154 struct intel_plane_state
*state
)
15156 struct drm_framebuffer
*fb
= state
->base
.fb
;
15157 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
15158 enum pipe pipe
= to_intel_plane(plane
)->pipe
;
15162 ret
= drm_plane_helper_check_state(&state
->base
,
15164 DRM_PLANE_HELPER_NO_SCALING
,
15165 DRM_PLANE_HELPER_NO_SCALING
,
15170 /* if we want to turn off the cursor ignore width and height */
15174 /* Check for which cursor types we support */
15175 if (!cursor_size_ok(to_i915(plane
->dev
), state
->base
.crtc_w
,
15176 state
->base
.crtc_h
)) {
15177 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15178 state
->base
.crtc_w
, state
->base
.crtc_h
);
15182 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
15183 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
15184 DRM_DEBUG_KMS("buffer is too small\n");
15188 if (fb
->modifier
!= DRM_FORMAT_MOD_NONE
) {
15189 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15194 * There's something wrong with the cursor on CHV pipe C.
15195 * If it straddles the left edge of the screen then
15196 * moving it away from the edge or disabling it often
15197 * results in a pipe underrun, and often that can lead to
15198 * dead pipe (constant underrun reported, and it scans
15199 * out just a solid color). To recover from that, the
15200 * display power well must be turned off and on again.
15201 * Refuse the put the cursor into that compromised position.
15203 if (IS_CHERRYVIEW(to_i915(plane
->dev
)) && pipe
== PIPE_C
&&
15204 state
->base
.visible
&& state
->base
.crtc_x
< 0) {
15205 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15213 intel_disable_cursor_plane(struct drm_plane
*plane
,
15214 struct drm_crtc
*crtc
)
15216 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
15218 intel_crtc
->cursor_addr
= 0;
15219 intel_crtc_update_cursor(crtc
, NULL
);
15223 intel_update_cursor_plane(struct drm_plane
*plane
,
15224 const struct intel_crtc_state
*crtc_state
,
15225 const struct intel_plane_state
*state
)
15227 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
15228 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
15229 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
15230 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
15235 else if (!INTEL_INFO(dev_priv
)->cursor_needs_physical
)
15236 addr
= i915_gem_object_ggtt_offset(obj
, NULL
);
15238 addr
= obj
->phys_handle
->busaddr
;
15240 intel_crtc
->cursor_addr
= addr
;
15241 intel_crtc_update_cursor(crtc
, state
);
15244 static struct intel_plane
*
15245 intel_cursor_plane_create(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15247 struct intel_plane
*cursor
= NULL
;
15248 struct intel_plane_state
*state
= NULL
;
15251 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
15257 state
= intel_create_plane_state(&cursor
->base
);
15263 cursor
->base
.state
= &state
->base
;
15265 cursor
->can_scale
= false;
15266 cursor
->max_downscale
= 1;
15267 cursor
->pipe
= pipe
;
15268 cursor
->plane
= pipe
;
15269 cursor
->id
= PLANE_CURSOR
;
15270 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
15271 cursor
->check_plane
= intel_check_cursor_plane
;
15272 cursor
->update_plane
= intel_update_cursor_plane
;
15273 cursor
->disable_plane
= intel_disable_cursor_plane
;
15275 ret
= drm_universal_plane_init(&dev_priv
->drm
, &cursor
->base
,
15276 0, &intel_plane_funcs
,
15277 intel_cursor_formats
,
15278 ARRAY_SIZE(intel_cursor_formats
),
15279 DRM_PLANE_TYPE_CURSOR
,
15280 "cursor %c", pipe_name(pipe
));
15284 if (INTEL_GEN(dev_priv
) >= 4)
15285 drm_plane_create_rotation_property(&cursor
->base
,
15290 if (INTEL_GEN(dev_priv
) >= 9)
15291 state
->scaler_id
= -1;
15293 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
15301 return ERR_PTR(ret
);
15304 static void skl_init_scalers(struct drm_i915_private
*dev_priv
,
15305 struct intel_crtc
*crtc
,
15306 struct intel_crtc_state
*crtc_state
)
15308 struct intel_crtc_scaler_state
*scaler_state
=
15309 &crtc_state
->scaler_state
;
15312 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
15313 struct intel_scaler
*scaler
= &scaler_state
->scalers
[i
];
15315 scaler
->in_use
= 0;
15316 scaler
->mode
= PS_SCALER_MODE_DYN
;
15319 scaler_state
->scaler_id
= -1;
15322 static int intel_crtc_init(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
15324 struct intel_crtc
*intel_crtc
;
15325 struct intel_crtc_state
*crtc_state
= NULL
;
15326 struct intel_plane
*primary
= NULL
;
15327 struct intel_plane
*cursor
= NULL
;
15330 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
15334 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
15339 intel_crtc
->config
= crtc_state
;
15340 intel_crtc
->base
.state
= &crtc_state
->base
;
15341 crtc_state
->base
.crtc
= &intel_crtc
->base
;
15343 /* initialize shared scalers */
15344 if (INTEL_GEN(dev_priv
) >= 9) {
15345 if (pipe
== PIPE_C
)
15346 intel_crtc
->num_scalers
= 1;
15348 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
15350 skl_init_scalers(dev_priv
, intel_crtc
, crtc_state
);
15353 primary
= intel_primary_plane_create(dev_priv
, pipe
);
15354 if (IS_ERR(primary
)) {
15355 ret
= PTR_ERR(primary
);
15358 intel_crtc
->plane_ids_mask
|= BIT(primary
->id
);
15360 for_each_sprite(dev_priv
, pipe
, sprite
) {
15361 struct intel_plane
*plane
;
15363 plane
= intel_sprite_plane_create(dev_priv
, pipe
, sprite
);
15364 if (IS_ERR(plane
)) {
15365 ret
= PTR_ERR(plane
);
15368 intel_crtc
->plane_ids_mask
|= BIT(plane
->id
);
15371 cursor
= intel_cursor_plane_create(dev_priv
, pipe
);
15372 if (IS_ERR(cursor
)) {
15373 ret
= PTR_ERR(cursor
);
15376 intel_crtc
->plane_ids_mask
|= BIT(cursor
->id
);
15378 ret
= drm_crtc_init_with_planes(&dev_priv
->drm
, &intel_crtc
->base
,
15379 &primary
->base
, &cursor
->base
,
15381 "pipe %c", pipe_name(pipe
));
15385 intel_crtc
->pipe
= pipe
;
15386 intel_crtc
->plane
= primary
->plane
;
15388 intel_crtc
->cursor_base
= ~0;
15389 intel_crtc
->cursor_cntl
= ~0;
15390 intel_crtc
->cursor_size
= ~0;
15392 intel_crtc
->wm
.cxsr_allowed
= true;
15394 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
15395 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
15396 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = intel_crtc
;
15397 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = intel_crtc
;
15399 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
15401 intel_color_init(&intel_crtc
->base
);
15403 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
15409 * drm_mode_config_cleanup() will free up any
15410 * crtcs/planes already initialized.
15418 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
15420 struct drm_encoder
*encoder
= connector
->base
.encoder
;
15421 struct drm_device
*dev
= connector
->base
.dev
;
15423 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
15425 if (!encoder
|| WARN_ON(!encoder
->crtc
))
15426 return INVALID_PIPE
;
15428 return to_intel_crtc(encoder
->crtc
)->pipe
;
15431 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
15432 struct drm_file
*file
)
15434 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
15435 struct drm_crtc
*drmmode_crtc
;
15436 struct intel_crtc
*crtc
;
15438 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
15442 crtc
= to_intel_crtc(drmmode_crtc
);
15443 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
15448 static int intel_encoder_clones(struct intel_encoder
*encoder
)
15450 struct drm_device
*dev
= encoder
->base
.dev
;
15451 struct intel_encoder
*source_encoder
;
15452 int index_mask
= 0;
15455 for_each_intel_encoder(dev
, source_encoder
) {
15456 if (encoders_cloneable(encoder
, source_encoder
))
15457 index_mask
|= (1 << entry
);
15465 static bool has_edp_a(struct drm_i915_private
*dev_priv
)
15467 if (!IS_MOBILE(dev_priv
))
15470 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
15473 if (IS_GEN5(dev_priv
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
15479 static bool intel_crt_present(struct drm_i915_private
*dev_priv
)
15481 if (INTEL_GEN(dev_priv
) >= 9)
15484 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
15487 if (IS_CHERRYVIEW(dev_priv
))
15490 if (HAS_PCH_LPT_H(dev_priv
) &&
15491 I915_READ(SFUSE_STRAP
) & SFUSE_STRAP_CRT_DISABLED
)
15494 /* DDI E can't be used if DDI A requires 4 lanes */
15495 if (HAS_DDI(dev_priv
) && I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_A_4_LANES
)
15498 if (!dev_priv
->vbt
.int_crt_support
)
15504 void intel_pps_unlock_regs_wa(struct drm_i915_private
*dev_priv
)
15509 if (HAS_DDI(dev_priv
))
15512 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15513 * everywhere where registers can be write protected.
15515 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15520 for (pps_idx
= 0; pps_idx
< pps_num
; pps_idx
++) {
15521 u32 val
= I915_READ(PP_CONTROL(pps_idx
));
15523 val
= (val
& ~PANEL_UNLOCK_MASK
) | PANEL_UNLOCK_REGS
;
15524 I915_WRITE(PP_CONTROL(pps_idx
), val
);
15528 static void intel_pps_init(struct drm_i915_private
*dev_priv
)
15530 if (HAS_PCH_SPLIT(dev_priv
) || IS_GEN9_LP(dev_priv
))
15531 dev_priv
->pps_mmio_base
= PCH_PPS_BASE
;
15532 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
15533 dev_priv
->pps_mmio_base
= VLV_PPS_BASE
;
15535 dev_priv
->pps_mmio_base
= PPS_BASE
;
15537 intel_pps_unlock_regs_wa(dev_priv
);
15540 static void intel_setup_outputs(struct drm_i915_private
*dev_priv
)
15542 struct intel_encoder
*encoder
;
15543 bool dpd_is_edp
= false;
15545 intel_pps_init(dev_priv
);
15548 * intel_edp_init_connector() depends on this completing first, to
15549 * prevent the registeration of both eDP and LVDS and the incorrect
15550 * sharing of the PPS.
15552 intel_lvds_init(dev_priv
);
15554 if (intel_crt_present(dev_priv
))
15555 intel_crt_init(dev_priv
);
15557 if (IS_GEN9_LP(dev_priv
)) {
15559 * FIXME: Broxton doesn't support port detection via the
15560 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15561 * detect the ports.
15563 intel_ddi_init(dev_priv
, PORT_A
);
15564 intel_ddi_init(dev_priv
, PORT_B
);
15565 intel_ddi_init(dev_priv
, PORT_C
);
15567 intel_dsi_init(dev_priv
);
15568 } else if (HAS_DDI(dev_priv
)) {
15572 * Haswell uses DDI functions to detect digital outputs.
15573 * On SKL pre-D0 the strap isn't connected, so we assume
15576 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
15577 /* WaIgnoreDDIAStrap: skl */
15578 if (found
|| IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
15579 intel_ddi_init(dev_priv
, PORT_A
);
15581 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15583 found
= I915_READ(SFUSE_STRAP
);
15585 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
15586 intel_ddi_init(dev_priv
, PORT_B
);
15587 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
15588 intel_ddi_init(dev_priv
, PORT_C
);
15589 if (found
& SFUSE_STRAP_DDID_DETECTED
)
15590 intel_ddi_init(dev_priv
, PORT_D
);
15592 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15594 if ((IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) &&
15595 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
15596 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
15597 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
15598 intel_ddi_init(dev_priv
, PORT_E
);
15600 } else if (HAS_PCH_SPLIT(dev_priv
)) {
15602 dpd_is_edp
= intel_dp_is_edp(dev_priv
, PORT_D
);
15604 if (has_edp_a(dev_priv
))
15605 intel_dp_init(dev_priv
, DP_A
, PORT_A
);
15607 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
15608 /* PCH SDVOB multiplex with HDMIB */
15609 found
= intel_sdvo_init(dev_priv
, PCH_SDVOB
, PORT_B
);
15611 intel_hdmi_init(dev_priv
, PCH_HDMIB
, PORT_B
);
15612 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
15613 intel_dp_init(dev_priv
, PCH_DP_B
, PORT_B
);
15616 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
15617 intel_hdmi_init(dev_priv
, PCH_HDMIC
, PORT_C
);
15619 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
15620 intel_hdmi_init(dev_priv
, PCH_HDMID
, PORT_D
);
15622 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
15623 intel_dp_init(dev_priv
, PCH_DP_C
, PORT_C
);
15625 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
15626 intel_dp_init(dev_priv
, PCH_DP_D
, PORT_D
);
15627 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
15628 bool has_edp
, has_port
;
15631 * The DP_DETECTED bit is the latched state of the DDC
15632 * SDA pin at boot. However since eDP doesn't require DDC
15633 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15634 * eDP ports may have been muxed to an alternate function.
15635 * Thus we can't rely on the DP_DETECTED bit alone to detect
15636 * eDP ports. Consult the VBT as well as DP_DETECTED to
15637 * detect eDP ports.
15639 * Sadly the straps seem to be missing sometimes even for HDMI
15640 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15641 * and VBT for the presence of the port. Additionally we can't
15642 * trust the port type the VBT declares as we've seen at least
15643 * HDMI ports that the VBT claim are DP or eDP.
15645 has_edp
= intel_dp_is_edp(dev_priv
, PORT_B
);
15646 has_port
= intel_bios_is_port_present(dev_priv
, PORT_B
);
15647 if (I915_READ(VLV_DP_B
) & DP_DETECTED
|| has_port
)
15648 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_B
, PORT_B
);
15649 if ((I915_READ(VLV_HDMIB
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
15650 intel_hdmi_init(dev_priv
, VLV_HDMIB
, PORT_B
);
15652 has_edp
= intel_dp_is_edp(dev_priv
, PORT_C
);
15653 has_port
= intel_bios_is_port_present(dev_priv
, PORT_C
);
15654 if (I915_READ(VLV_DP_C
) & DP_DETECTED
|| has_port
)
15655 has_edp
&= intel_dp_init(dev_priv
, VLV_DP_C
, PORT_C
);
15656 if ((I915_READ(VLV_HDMIC
) & SDVO_DETECTED
|| has_port
) && !has_edp
)
15657 intel_hdmi_init(dev_priv
, VLV_HDMIC
, PORT_C
);
15659 if (IS_CHERRYVIEW(dev_priv
)) {
15661 * eDP not supported on port D,
15662 * so no need to worry about it
15664 has_port
= intel_bios_is_port_present(dev_priv
, PORT_D
);
15665 if (I915_READ(CHV_DP_D
) & DP_DETECTED
|| has_port
)
15666 intel_dp_init(dev_priv
, CHV_DP_D
, PORT_D
);
15667 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
|| has_port
)
15668 intel_hdmi_init(dev_priv
, CHV_HDMID
, PORT_D
);
15671 intel_dsi_init(dev_priv
);
15672 } else if (!IS_GEN2(dev_priv
) && !IS_PINEVIEW(dev_priv
)) {
15673 bool found
= false;
15675 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
15676 DRM_DEBUG_KMS("probing SDVOB\n");
15677 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOB
, PORT_B
);
15678 if (!found
&& IS_G4X(dev_priv
)) {
15679 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15680 intel_hdmi_init(dev_priv
, GEN4_HDMIB
, PORT_B
);
15683 if (!found
&& IS_G4X(dev_priv
))
15684 intel_dp_init(dev_priv
, DP_B
, PORT_B
);
15687 /* Before G4X SDVOC doesn't have its own detect register */
15689 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
15690 DRM_DEBUG_KMS("probing SDVOC\n");
15691 found
= intel_sdvo_init(dev_priv
, GEN3_SDVOC
, PORT_C
);
15694 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
15696 if (IS_G4X(dev_priv
)) {
15697 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15698 intel_hdmi_init(dev_priv
, GEN4_HDMIC
, PORT_C
);
15700 if (IS_G4X(dev_priv
))
15701 intel_dp_init(dev_priv
, DP_C
, PORT_C
);
15704 if (IS_G4X(dev_priv
) && (I915_READ(DP_D
) & DP_DETECTED
))
15705 intel_dp_init(dev_priv
, DP_D
, PORT_D
);
15706 } else if (IS_GEN2(dev_priv
))
15707 intel_dvo_init(dev_priv
);
15709 if (SUPPORTS_TV(dev_priv
))
15710 intel_tv_init(dev_priv
);
15712 intel_psr_init(dev_priv
);
15714 for_each_intel_encoder(&dev_priv
->drm
, encoder
) {
15715 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
15716 encoder
->base
.possible_clones
=
15717 intel_encoder_clones(encoder
);
15720 intel_init_pch_refclk(dev_priv
);
15722 drm_helper_move_panel_connectors_to_head(&dev_priv
->drm
);
15725 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
15727 struct drm_device
*dev
= fb
->dev
;
15728 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
15730 drm_framebuffer_cleanup(fb
);
15731 mutex_lock(&dev
->struct_mutex
);
15732 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
15733 i915_gem_object_put(intel_fb
->obj
);
15734 mutex_unlock(&dev
->struct_mutex
);
15738 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
15739 struct drm_file
*file
,
15740 unsigned int *handle
)
15742 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
15743 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
15745 if (obj
->userptr
.mm
) {
15746 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15750 return drm_gem_handle_create(file
, &obj
->base
, handle
);
15753 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
15754 struct drm_file
*file
,
15755 unsigned flags
, unsigned color
,
15756 struct drm_clip_rect
*clips
,
15757 unsigned num_clips
)
15759 struct drm_device
*dev
= fb
->dev
;
15760 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
15761 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
15763 mutex_lock(&dev
->struct_mutex
);
15764 if (obj
->pin_display
&& obj
->cache_dirty
)
15765 i915_gem_clflush_object(obj
, true);
15766 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
15767 mutex_unlock(&dev
->struct_mutex
);
15772 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
15773 .destroy
= intel_user_framebuffer_destroy
,
15774 .create_handle
= intel_user_framebuffer_create_handle
,
15775 .dirty
= intel_user_framebuffer_dirty
,
15779 u32
intel_fb_pitch_limit(struct drm_i915_private
*dev_priv
,
15780 uint64_t fb_modifier
, uint32_t pixel_format
)
15782 u32 gen
= INTEL_INFO(dev_priv
)->gen
;
15785 int cpp
= drm_format_plane_cpp(pixel_format
, 0);
15787 /* "The stride in bytes must not exceed the of the size of 8K
15788 * pixels and 32K bytes."
15790 return min(8192 * cpp
, 32768);
15791 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev_priv
) &&
15792 !IS_CHERRYVIEW(dev_priv
)) {
15794 } else if (gen
>= 4) {
15795 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
15799 } else if (gen
>= 3) {
15800 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
15805 /* XXX DSPC is limited to 4k tiled */
15810 static int intel_framebuffer_init(struct drm_device
*dev
,
15811 struct intel_framebuffer
*intel_fb
,
15812 struct drm_mode_fb_cmd2
*mode_cmd
,
15813 struct drm_i915_gem_object
*obj
)
15815 struct drm_i915_private
*dev_priv
= to_i915(dev
);
15816 unsigned int tiling
= i915_gem_object_get_tiling(obj
);
15818 u32 pitch_limit
, stride_alignment
;
15819 struct drm_format_name_buf format_name
;
15821 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
15823 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
15825 * If there's a fence, enforce that
15826 * the fb modifier and tiling mode match.
15828 if (tiling
!= I915_TILING_NONE
&&
15829 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15830 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15834 if (tiling
== I915_TILING_X
) {
15835 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
15836 } else if (tiling
== I915_TILING_Y
) {
15837 DRM_DEBUG("No Y tiling for legacy addfb\n");
15842 /* Passed in modifier sanity checking. */
15843 switch (mode_cmd
->modifier
[0]) {
15844 case I915_FORMAT_MOD_Y_TILED
:
15845 case I915_FORMAT_MOD_Yf_TILED
:
15846 if (INTEL_GEN(dev_priv
) < 9) {
15847 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15848 mode_cmd
->modifier
[0]);
15851 case DRM_FORMAT_MOD_NONE
:
15852 case I915_FORMAT_MOD_X_TILED
:
15855 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15856 mode_cmd
->modifier
[0]);
15861 * gen2/3 display engine uses the fence if present,
15862 * so the tiling mode must match the fb modifier exactly.
15864 if (INTEL_INFO(dev_priv
)->gen
< 4 &&
15865 tiling
!= intel_fb_modifier_to_tiling(mode_cmd
->modifier
[0])) {
15866 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15870 stride_alignment
= intel_fb_stride_alignment(dev_priv
,
15871 mode_cmd
->modifier
[0],
15872 mode_cmd
->pixel_format
);
15873 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
15874 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15875 mode_cmd
->pitches
[0], stride_alignment
);
15879 pitch_limit
= intel_fb_pitch_limit(dev_priv
, mode_cmd
->modifier
[0],
15880 mode_cmd
->pixel_format
);
15881 if (mode_cmd
->pitches
[0] > pitch_limit
) {
15882 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15883 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
15884 "tiled" : "linear",
15885 mode_cmd
->pitches
[0], pitch_limit
);
15890 * If there's a fence, enforce that
15891 * the fb pitch and fence stride match.
15893 if (tiling
!= I915_TILING_NONE
&&
15894 mode_cmd
->pitches
[0] != i915_gem_object_get_stride(obj
)) {
15895 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15896 mode_cmd
->pitches
[0],
15897 i915_gem_object_get_stride(obj
));
15901 /* Reject formats not supported by any plane early. */
15902 switch (mode_cmd
->pixel_format
) {
15903 case DRM_FORMAT_C8
:
15904 case DRM_FORMAT_RGB565
:
15905 case DRM_FORMAT_XRGB8888
:
15906 case DRM_FORMAT_ARGB8888
:
15908 case DRM_FORMAT_XRGB1555
:
15909 if (INTEL_GEN(dev_priv
) > 3) {
15910 DRM_DEBUG("unsupported pixel format: %s\n",
15911 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
15915 case DRM_FORMAT_ABGR8888
:
15916 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
) &&
15917 INTEL_GEN(dev_priv
) < 9) {
15918 DRM_DEBUG("unsupported pixel format: %s\n",
15919 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
15923 case DRM_FORMAT_XBGR8888
:
15924 case DRM_FORMAT_XRGB2101010
:
15925 case DRM_FORMAT_XBGR2101010
:
15926 if (INTEL_GEN(dev_priv
) < 4) {
15927 DRM_DEBUG("unsupported pixel format: %s\n",
15928 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
15932 case DRM_FORMAT_ABGR2101010
:
15933 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
)) {
15934 DRM_DEBUG("unsupported pixel format: %s\n",
15935 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
15939 case DRM_FORMAT_YUYV
:
15940 case DRM_FORMAT_UYVY
:
15941 case DRM_FORMAT_YVYU
:
15942 case DRM_FORMAT_VYUY
:
15943 if (INTEL_GEN(dev_priv
) < 5) {
15944 DRM_DEBUG("unsupported pixel format: %s\n",
15945 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
15950 DRM_DEBUG("unsupported pixel format: %s\n",
15951 drm_get_format_name(mode_cmd
->pixel_format
, &format_name
));
15955 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15956 if (mode_cmd
->offsets
[0] != 0)
15959 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
15960 intel_fb
->obj
= obj
;
15962 ret
= intel_fill_fb_info(dev_priv
, &intel_fb
->base
);
15966 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
15968 DRM_ERROR("framebuffer init failed %d\n", ret
);
15972 intel_fb
->obj
->framebuffer_references
++;
15977 static struct drm_framebuffer
*
15978 intel_user_framebuffer_create(struct drm_device
*dev
,
15979 struct drm_file
*filp
,
15980 const struct drm_mode_fb_cmd2
*user_mode_cmd
)
15982 struct drm_framebuffer
*fb
;
15983 struct drm_i915_gem_object
*obj
;
15984 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
15986 obj
= i915_gem_object_lookup(filp
, mode_cmd
.handles
[0]);
15988 return ERR_PTR(-ENOENT
);
15990 fb
= intel_framebuffer_create(dev
, &mode_cmd
, obj
);
15992 i915_gem_object_put(obj
);
15997 static void intel_atomic_state_free(struct drm_atomic_state
*state
)
15999 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
16001 drm_atomic_state_default_release(state
);
16003 i915_sw_fence_fini(&intel_state
->commit_ready
);
16008 static const struct drm_mode_config_funcs intel_mode_funcs
= {
16009 .fb_create
= intel_user_framebuffer_create
,
16010 .output_poll_changed
= intel_fbdev_output_poll_changed
,
16011 .atomic_check
= intel_atomic_check
,
16012 .atomic_commit
= intel_atomic_commit
,
16013 .atomic_state_alloc
= intel_atomic_state_alloc
,
16014 .atomic_state_clear
= intel_atomic_state_clear
,
16015 .atomic_state_free
= intel_atomic_state_free
,
16019 * intel_init_display_hooks - initialize the display modesetting hooks
16020 * @dev_priv: device private
16022 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
)
16024 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
16025 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
16026 dev_priv
->display
.get_initial_plane_config
=
16027 skylake_get_initial_plane_config
;
16028 dev_priv
->display
.crtc_compute_clock
=
16029 haswell_crtc_compute_clock
;
16030 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
16031 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
16032 } else if (HAS_DDI(dev_priv
)) {
16033 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
16034 dev_priv
->display
.get_initial_plane_config
=
16035 ironlake_get_initial_plane_config
;
16036 dev_priv
->display
.crtc_compute_clock
=
16037 haswell_crtc_compute_clock
;
16038 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
16039 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
16040 } else if (HAS_PCH_SPLIT(dev_priv
)) {
16041 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
16042 dev_priv
->display
.get_initial_plane_config
=
16043 ironlake_get_initial_plane_config
;
16044 dev_priv
->display
.crtc_compute_clock
=
16045 ironlake_crtc_compute_clock
;
16046 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
16047 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
16048 } else if (IS_CHERRYVIEW(dev_priv
)) {
16049 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16050 dev_priv
->display
.get_initial_plane_config
=
16051 i9xx_get_initial_plane_config
;
16052 dev_priv
->display
.crtc_compute_clock
= chv_crtc_compute_clock
;
16053 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
16054 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16055 } else if (IS_VALLEYVIEW(dev_priv
)) {
16056 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16057 dev_priv
->display
.get_initial_plane_config
=
16058 i9xx_get_initial_plane_config
;
16059 dev_priv
->display
.crtc_compute_clock
= vlv_crtc_compute_clock
;
16060 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
16061 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16062 } else if (IS_G4X(dev_priv
)) {
16063 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16064 dev_priv
->display
.get_initial_plane_config
=
16065 i9xx_get_initial_plane_config
;
16066 dev_priv
->display
.crtc_compute_clock
= g4x_crtc_compute_clock
;
16067 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
16068 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16069 } else if (IS_PINEVIEW(dev_priv
)) {
16070 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16071 dev_priv
->display
.get_initial_plane_config
=
16072 i9xx_get_initial_plane_config
;
16073 dev_priv
->display
.crtc_compute_clock
= pnv_crtc_compute_clock
;
16074 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
16075 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16076 } else if (!IS_GEN2(dev_priv
)) {
16077 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16078 dev_priv
->display
.get_initial_plane_config
=
16079 i9xx_get_initial_plane_config
;
16080 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
16081 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
16082 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16084 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
16085 dev_priv
->display
.get_initial_plane_config
=
16086 i9xx_get_initial_plane_config
;
16087 dev_priv
->display
.crtc_compute_clock
= i8xx_crtc_compute_clock
;
16088 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
16089 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
16092 /* Returns the core display clock speed */
16093 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
16094 dev_priv
->display
.get_display_clock_speed
=
16095 skylake_get_display_clock_speed
;
16096 else if (IS_GEN9_LP(dev_priv
))
16097 dev_priv
->display
.get_display_clock_speed
=
16098 broxton_get_display_clock_speed
;
16099 else if (IS_BROADWELL(dev_priv
))
16100 dev_priv
->display
.get_display_clock_speed
=
16101 broadwell_get_display_clock_speed
;
16102 else if (IS_HASWELL(dev_priv
))
16103 dev_priv
->display
.get_display_clock_speed
=
16104 haswell_get_display_clock_speed
;
16105 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
16106 dev_priv
->display
.get_display_clock_speed
=
16107 valleyview_get_display_clock_speed
;
16108 else if (IS_GEN5(dev_priv
))
16109 dev_priv
->display
.get_display_clock_speed
=
16110 ilk_get_display_clock_speed
;
16111 else if (IS_I945G(dev_priv
) || IS_I965G(dev_priv
) ||
16112 IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
))
16113 dev_priv
->display
.get_display_clock_speed
=
16114 i945_get_display_clock_speed
;
16115 else if (IS_GM45(dev_priv
))
16116 dev_priv
->display
.get_display_clock_speed
=
16117 gm45_get_display_clock_speed
;
16118 else if (IS_I965GM(dev_priv
))
16119 dev_priv
->display
.get_display_clock_speed
=
16120 i965gm_get_display_clock_speed
;
16121 else if (IS_PINEVIEW(dev_priv
))
16122 dev_priv
->display
.get_display_clock_speed
=
16123 pnv_get_display_clock_speed
;
16124 else if (IS_G33(dev_priv
) || IS_G4X(dev_priv
))
16125 dev_priv
->display
.get_display_clock_speed
=
16126 g33_get_display_clock_speed
;
16127 else if (IS_I915G(dev_priv
))
16128 dev_priv
->display
.get_display_clock_speed
=
16129 i915_get_display_clock_speed
;
16130 else if (IS_I945GM(dev_priv
) || IS_I845G(dev_priv
))
16131 dev_priv
->display
.get_display_clock_speed
=
16132 i9xx_misc_get_display_clock_speed
;
16133 else if (IS_I915GM(dev_priv
))
16134 dev_priv
->display
.get_display_clock_speed
=
16135 i915gm_get_display_clock_speed
;
16136 else if (IS_I865G(dev_priv
))
16137 dev_priv
->display
.get_display_clock_speed
=
16138 i865_get_display_clock_speed
;
16139 else if (IS_I85X(dev_priv
))
16140 dev_priv
->display
.get_display_clock_speed
=
16141 i85x_get_display_clock_speed
;
16143 WARN(!IS_I830(dev_priv
), "Unknown platform. Assuming 133 MHz CDCLK\n");
16144 dev_priv
->display
.get_display_clock_speed
=
16145 i830_get_display_clock_speed
;
16148 if (IS_GEN5(dev_priv
)) {
16149 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
16150 } else if (IS_GEN6(dev_priv
)) {
16151 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
16152 } else if (IS_IVYBRIDGE(dev_priv
)) {
16153 /* FIXME: detect B0+ stepping and use auto training */
16154 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
16155 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
16156 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
16159 if (IS_BROADWELL(dev_priv
)) {
16160 dev_priv
->display
.modeset_commit_cdclk
=
16161 broadwell_modeset_commit_cdclk
;
16162 dev_priv
->display
.modeset_calc_cdclk
=
16163 broadwell_modeset_calc_cdclk
;
16164 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
16165 dev_priv
->display
.modeset_commit_cdclk
=
16166 valleyview_modeset_commit_cdclk
;
16167 dev_priv
->display
.modeset_calc_cdclk
=
16168 valleyview_modeset_calc_cdclk
;
16169 } else if (IS_GEN9_LP(dev_priv
)) {
16170 dev_priv
->display
.modeset_commit_cdclk
=
16171 bxt_modeset_commit_cdclk
;
16172 dev_priv
->display
.modeset_calc_cdclk
=
16173 bxt_modeset_calc_cdclk
;
16174 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
16175 dev_priv
->display
.modeset_commit_cdclk
=
16176 skl_modeset_commit_cdclk
;
16177 dev_priv
->display
.modeset_calc_cdclk
=
16178 skl_modeset_calc_cdclk
;
16181 if (dev_priv
->info
.gen
>= 9)
16182 dev_priv
->display
.update_crtcs
= skl_update_crtcs
;
16184 dev_priv
->display
.update_crtcs
= intel_update_crtcs
;
16186 switch (INTEL_INFO(dev_priv
)->gen
) {
16188 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
16192 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
16197 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
16201 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
16204 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16205 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
16208 /* Drop through - unsupported since execlist only. */
16210 /* Default just returns -ENODEV to indicate unsupported */
16211 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
16216 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16217 * resume, or other times. This quirk makes sure that's the case for
16218 * affected systems.
16220 static void quirk_pipea_force(struct drm_device
*dev
)
16222 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16224 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
16225 DRM_INFO("applying pipe a force quirk\n");
16228 static void quirk_pipeb_force(struct drm_device
*dev
)
16230 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16232 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
16233 DRM_INFO("applying pipe b force quirk\n");
16237 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16239 static void quirk_ssc_force_disable(struct drm_device
*dev
)
16241 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16242 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
16243 DRM_INFO("applying lvds SSC disable quirk\n");
16247 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16250 static void quirk_invert_brightness(struct drm_device
*dev
)
16252 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16253 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
16254 DRM_INFO("applying inverted panel brightness quirk\n");
16257 /* Some VBT's incorrectly indicate no backlight is present */
16258 static void quirk_backlight_present(struct drm_device
*dev
)
16260 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16261 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
16262 DRM_INFO("applying backlight present quirk\n");
16265 struct intel_quirk
{
16267 int subsystem_vendor
;
16268 int subsystem_device
;
16269 void (*hook
)(struct drm_device
*dev
);
16272 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16273 struct intel_dmi_quirk
{
16274 void (*hook
)(struct drm_device
*dev
);
16275 const struct dmi_system_id (*dmi_id_list
)[];
16278 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
16280 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
16284 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
16286 .dmi_id_list
= &(const struct dmi_system_id
[]) {
16288 .callback
= intel_dmi_reverse_brightness
,
16289 .ident
= "NCR Corporation",
16290 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
16291 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
16294 { } /* terminating entry */
16296 .hook
= quirk_invert_brightness
,
16300 static struct intel_quirk intel_quirks
[] = {
16301 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16302 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
16304 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16305 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
16307 /* 830 needs to leave pipe A & dpll A up */
16308 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
16310 /* 830 needs to leave pipe B & dpll B up */
16311 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
16313 /* Lenovo U160 cannot use SSC on LVDS */
16314 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
16316 /* Sony Vaio Y cannot use SSC on LVDS */
16317 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
16319 /* Acer Aspire 5734Z must invert backlight brightness */
16320 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
16322 /* Acer/eMachines G725 */
16323 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
16325 /* Acer/eMachines e725 */
16326 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
16328 /* Acer/Packard Bell NCL20 */
16329 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
16331 /* Acer Aspire 4736Z */
16332 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
16334 /* Acer Aspire 5336 */
16335 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
16337 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16338 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
16340 /* Acer C720 Chromebook (Core i3 4005U) */
16341 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
16343 /* Apple Macbook 2,1 (Core 2 T7400) */
16344 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
16346 /* Apple Macbook 4,1 */
16347 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present
},
16349 /* Toshiba CB35 Chromebook (Celeron 2955U) */
16350 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
16352 /* HP Chromebook 14 (Celeron 2955U) */
16353 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
16355 /* Dell Chromebook 11 */
16356 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
16358 /* Dell Chromebook 11 (2015 version) */
16359 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present
},
16362 static void intel_init_quirks(struct drm_device
*dev
)
16364 struct pci_dev
*d
= dev
->pdev
;
16367 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
16368 struct intel_quirk
*q
= &intel_quirks
[i
];
16370 if (d
->device
== q
->device
&&
16371 (d
->subsystem_vendor
== q
->subsystem_vendor
||
16372 q
->subsystem_vendor
== PCI_ANY_ID
) &&
16373 (d
->subsystem_device
== q
->subsystem_device
||
16374 q
->subsystem_device
== PCI_ANY_ID
))
16377 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
16378 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
16379 intel_dmi_quirks
[i
].hook(dev
);
16383 /* Disable the VGA plane that we never use */
16384 static void i915_disable_vga(struct drm_i915_private
*dev_priv
)
16386 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
16388 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
16390 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16391 vga_get_uninterruptible(pdev
, VGA_RSRC_LEGACY_IO
);
16392 outb(SR01
, VGA_SR_INDEX
);
16393 sr1
= inb(VGA_SR_DATA
);
16394 outb(sr1
| 1<<5, VGA_SR_DATA
);
16395 vga_put(pdev
, VGA_RSRC_LEGACY_IO
);
16398 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
16399 POSTING_READ(vga_reg
);
16402 void intel_modeset_init_hw(struct drm_device
*dev
)
16404 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16406 intel_update_cdclk(dev_priv
);
16408 dev_priv
->atomic_cdclk_freq
= dev_priv
->cdclk_freq
;
16410 intel_init_clock_gating(dev_priv
);
16414 * Calculate what we think the watermarks should be for the state we've read
16415 * out of the hardware and then immediately program those watermarks so that
16416 * we ensure the hardware settings match our internal state.
16418 * We can calculate what we think WM's should be by creating a duplicate of the
16419 * current state (which was constructed during hardware readout) and running it
16420 * through the atomic check code to calculate new watermark values in the
16423 static void sanitize_watermarks(struct drm_device
*dev
)
16425 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16426 struct drm_atomic_state
*state
;
16427 struct intel_atomic_state
*intel_state
;
16428 struct drm_crtc
*crtc
;
16429 struct drm_crtc_state
*cstate
;
16430 struct drm_modeset_acquire_ctx ctx
;
16434 /* Only supported on platforms that use atomic watermark design */
16435 if (!dev_priv
->display
.optimize_watermarks
)
16439 * We need to hold connection_mutex before calling duplicate_state so
16440 * that the connector loop is protected.
16442 drm_modeset_acquire_init(&ctx
, 0);
16444 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
16445 if (ret
== -EDEADLK
) {
16446 drm_modeset_backoff(&ctx
);
16448 } else if (WARN_ON(ret
)) {
16452 state
= drm_atomic_helper_duplicate_state(dev
, &ctx
);
16453 if (WARN_ON(IS_ERR(state
)))
16456 intel_state
= to_intel_atomic_state(state
);
16459 * Hardware readout is the only time we don't want to calculate
16460 * intermediate watermarks (since we don't trust the current
16463 intel_state
->skip_intermediate_wm
= true;
16465 ret
= intel_atomic_check(dev
, state
);
16468 * If we fail here, it means that the hardware appears to be
16469 * programmed in a way that shouldn't be possible, given our
16470 * understanding of watermark requirements. This might mean a
16471 * mistake in the hardware readout code or a mistake in the
16472 * watermark calculations for a given platform. Raise a WARN
16473 * so that this is noticeable.
16475 * If this actually happens, we'll have to just leave the
16476 * BIOS-programmed watermarks untouched and hope for the best.
16478 WARN(true, "Could not determine valid watermarks for inherited state\n");
16482 /* Write calculated watermark values back */
16483 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
16484 struct intel_crtc_state
*cs
= to_intel_crtc_state(cstate
);
16486 cs
->wm
.need_postvbl_update
= true;
16487 dev_priv
->display
.optimize_watermarks(intel_state
, cs
);
16491 drm_atomic_state_put(state
);
16493 drm_modeset_drop_locks(&ctx
);
16494 drm_modeset_acquire_fini(&ctx
);
16497 int intel_modeset_init(struct drm_device
*dev
)
16499 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16500 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
16502 struct intel_crtc
*crtc
;
16504 drm_mode_config_init(dev
);
16506 dev
->mode_config
.min_width
= 0;
16507 dev
->mode_config
.min_height
= 0;
16509 dev
->mode_config
.preferred_depth
= 24;
16510 dev
->mode_config
.prefer_shadow
= 1;
16512 dev
->mode_config
.allow_fb_modifiers
= true;
16514 dev
->mode_config
.funcs
= &intel_mode_funcs
;
16516 intel_init_quirks(dev
);
16518 intel_init_pm(dev_priv
);
16520 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
16524 * There may be no VBT; and if the BIOS enabled SSC we can
16525 * just keep using it to avoid unnecessary flicker. Whereas if the
16526 * BIOS isn't using it, don't assume it will work even if the VBT
16527 * indicates as much.
16529 if (HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)) {
16530 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
16533 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
16534 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16535 bios_lvds_use_ssc
? "en" : "dis",
16536 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
16537 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
16541 if (IS_GEN2(dev_priv
)) {
16542 dev
->mode_config
.max_width
= 2048;
16543 dev
->mode_config
.max_height
= 2048;
16544 } else if (IS_GEN3(dev_priv
)) {
16545 dev
->mode_config
.max_width
= 4096;
16546 dev
->mode_config
.max_height
= 4096;
16548 dev
->mode_config
.max_width
= 8192;
16549 dev
->mode_config
.max_height
= 8192;
16552 if (IS_I845G(dev_priv
) || IS_I865G(dev_priv
)) {
16553 dev
->mode_config
.cursor_width
= IS_I845G(dev_priv
) ? 64 : 512;
16554 dev
->mode_config
.cursor_height
= 1023;
16555 } else if (IS_GEN2(dev_priv
)) {
16556 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
16557 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
16559 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
16560 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
16563 dev
->mode_config
.fb_base
= ggtt
->mappable_base
;
16565 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16566 INTEL_INFO(dev_priv
)->num_pipes
,
16567 INTEL_INFO(dev_priv
)->num_pipes
> 1 ? "s" : "");
16569 for_each_pipe(dev_priv
, pipe
) {
16572 ret
= intel_crtc_init(dev_priv
, pipe
);
16574 drm_mode_config_cleanup(dev
);
16579 intel_update_czclk(dev_priv
);
16580 intel_update_cdclk(dev_priv
);
16581 dev_priv
->atomic_cdclk_freq
= dev_priv
->cdclk_freq
;
16583 intel_shared_dpll_init(dev
);
16585 if (dev_priv
->max_cdclk_freq
== 0)
16586 intel_update_max_cdclk(dev_priv
);
16588 /* Just disable it once at startup */
16589 i915_disable_vga(dev_priv
);
16590 intel_setup_outputs(dev_priv
);
16592 drm_modeset_lock_all(dev
);
16593 intel_modeset_setup_hw_state(dev
);
16594 drm_modeset_unlock_all(dev
);
16596 for_each_intel_crtc(dev
, crtc
) {
16597 struct intel_initial_plane_config plane_config
= {};
16603 * Note that reserving the BIOS fb up front prevents us
16604 * from stuffing other stolen allocations like the ring
16605 * on top. This prevents some ugliness at boot time, and
16606 * can even allow for smooth boot transitions if the BIOS
16607 * fb is large enough for the active pipe configuration.
16609 dev_priv
->display
.get_initial_plane_config(crtc
,
16613 * If the fb is shared between multiple heads, we'll
16614 * just get the first one.
16616 intel_find_initial_plane_obj(crtc
, &plane_config
);
16620 * Make sure hardware watermarks really match the state we read out.
16621 * Note that we need to do this after reconstructing the BIOS fb's
16622 * since the watermark calculation done here will use pstate->fb.
16624 sanitize_watermarks(dev
);
16629 static void intel_enable_pipe_a(struct drm_device
*dev
)
16631 struct intel_connector
*connector
;
16632 struct drm_connector
*crt
= NULL
;
16633 struct intel_load_detect_pipe load_detect_temp
;
16634 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
16636 /* We can't just switch on the pipe A, we need to set things up with a
16637 * proper mode and output configuration. As a gross hack, enable pipe A
16638 * by enabling the load detect pipe once. */
16639 for_each_intel_connector(dev
, connector
) {
16640 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
16641 crt
= &connector
->base
;
16649 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
16650 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
16654 intel_check_plane_mapping(struct intel_crtc
*crtc
)
16656 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
16659 if (INTEL_INFO(dev_priv
)->num_pipes
== 1)
16662 val
= I915_READ(DSPCNTR(!crtc
->plane
));
16664 if ((val
& DISPLAY_PLANE_ENABLE
) &&
16665 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
16671 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
16673 struct drm_device
*dev
= crtc
->base
.dev
;
16674 struct intel_encoder
*encoder
;
16676 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
16682 static struct intel_connector
*intel_encoder_find_connector(struct intel_encoder
*encoder
)
16684 struct drm_device
*dev
= encoder
->base
.dev
;
16685 struct intel_connector
*connector
;
16687 for_each_connector_on_encoder(dev
, &encoder
->base
, connector
)
16693 static bool has_pch_trancoder(struct drm_i915_private
*dev_priv
,
16694 enum transcoder pch_transcoder
)
16696 return HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
) ||
16697 (HAS_PCH_LPT_H(dev_priv
) && pch_transcoder
== TRANSCODER_A
);
16700 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
16702 struct drm_device
*dev
= crtc
->base
.dev
;
16703 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16704 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
16706 /* Clear any frame start delays used for debugging left by the BIOS */
16707 if (!transcoder_is_dsi(cpu_transcoder
)) {
16708 i915_reg_t reg
= PIPECONF(cpu_transcoder
);
16711 I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
16714 /* restore vblank interrupts to correct state */
16715 drm_crtc_vblank_reset(&crtc
->base
);
16716 if (crtc
->active
) {
16717 struct intel_plane
*plane
;
16719 drm_crtc_vblank_on(&crtc
->base
);
16721 /* Disable everything but the primary plane */
16722 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
16723 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
16726 plane
->disable_plane(&plane
->base
, &crtc
->base
);
16730 /* We need to sanitize the plane -> pipe mapping first because this will
16731 * disable the crtc (and hence change the state) if it is wrong. Note
16732 * that gen4+ has a fixed plane -> pipe mapping. */
16733 if (INTEL_GEN(dev_priv
) < 4 && !intel_check_plane_mapping(crtc
)) {
16736 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16737 crtc
->base
.base
.id
, crtc
->base
.name
);
16739 /* Pipe has the wrong plane attached and the plane is active.
16740 * Temporarily change the plane mapping and disable everything
16742 plane
= crtc
->plane
;
16743 to_intel_plane_state(crtc
->base
.primary
->state
)->base
.visible
= true;
16744 crtc
->plane
= !plane
;
16745 intel_crtc_disable_noatomic(&crtc
->base
);
16746 crtc
->plane
= plane
;
16749 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
16750 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
16751 /* BIOS forgot to enable pipe A, this mostly happens after
16752 * resume. Force-enable the pipe to fix this, the update_dpms
16753 * call below we restore the pipe to the right state, but leave
16754 * the required bits on. */
16755 intel_enable_pipe_a(dev
);
16758 /* Adjust the state of the output pipe according to whether we
16759 * have active connectors/encoders. */
16760 if (crtc
->active
&& !intel_crtc_has_encoders(crtc
))
16761 intel_crtc_disable_noatomic(&crtc
->base
);
16763 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev_priv
)) {
16765 * We start out with underrun reporting disabled to avoid races.
16766 * For correct bookkeeping mark this on active crtcs.
16768 * Also on gmch platforms we dont have any hardware bits to
16769 * disable the underrun reporting. Which means we need to start
16770 * out with underrun reporting disabled also on inactive pipes,
16771 * since otherwise we'll complain about the garbage we read when
16772 * e.g. coming up after runtime pm.
16774 * No protection against concurrent access is required - at
16775 * worst a fifo underrun happens which also sets this to false.
16777 crtc
->cpu_fifo_underrun_disabled
= true;
16779 * We track the PCH trancoder underrun reporting state
16780 * within the crtc. With crtc for pipe A housing the underrun
16781 * reporting state for PCH transcoder A, crtc for pipe B housing
16782 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16783 * and marking underrun reporting as disabled for the non-existing
16784 * PCH transcoders B and C would prevent enabling the south
16785 * error interrupt (see cpt_can_enable_serr_int()).
16787 if (has_pch_trancoder(dev_priv
, (enum transcoder
)crtc
->pipe
))
16788 crtc
->pch_fifo_underrun_disabled
= true;
16792 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
16794 struct intel_connector
*connector
;
16796 /* We need to check both for a crtc link (meaning that the
16797 * encoder is active and trying to read from a pipe) and the
16798 * pipe itself being active. */
16799 bool has_active_crtc
= encoder
->base
.crtc
&&
16800 to_intel_crtc(encoder
->base
.crtc
)->active
;
16802 connector
= intel_encoder_find_connector(encoder
);
16803 if (connector
&& !has_active_crtc
) {
16804 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16805 encoder
->base
.base
.id
,
16806 encoder
->base
.name
);
16808 /* Connector is active, but has no active pipe. This is
16809 * fallout from our resume register restoring. Disable
16810 * the encoder manually again. */
16811 if (encoder
->base
.crtc
) {
16812 struct drm_crtc_state
*crtc_state
= encoder
->base
.crtc
->state
;
16814 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16815 encoder
->base
.base
.id
,
16816 encoder
->base
.name
);
16817 encoder
->disable(encoder
, to_intel_crtc_state(crtc_state
), connector
->base
.state
);
16818 if (encoder
->post_disable
)
16819 encoder
->post_disable(encoder
, to_intel_crtc_state(crtc_state
), connector
->base
.state
);
16821 encoder
->base
.crtc
= NULL
;
16823 /* Inconsistent output/port/pipe state happens presumably due to
16824 * a bug in one of the get_hw_state functions. Or someplace else
16825 * in our code, like the register restore mess on resume. Clamp
16826 * things to off as a safer default. */
16828 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16829 connector
->base
.encoder
= NULL
;
16831 /* Enabled encoders without active connectors will be fixed in
16832 * the crtc fixup. */
16835 void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
)
16837 i915_reg_t vga_reg
= i915_vgacntrl_reg(dev_priv
);
16839 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
16840 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16841 i915_disable_vga(dev_priv
);
16845 void i915_redisable_vga(struct drm_i915_private
*dev_priv
)
16847 /* This function can be called both from intel_modeset_setup_hw_state or
16848 * at a very early point in our resume sequence, where the power well
16849 * structures are not yet restored. Since this function is at a very
16850 * paranoid "someone might have enabled VGA while we were not looking"
16851 * level, just check if the power well is enabled instead of trying to
16852 * follow the "don't touch the power well if we don't need it" policy
16853 * the rest of the driver uses. */
16854 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_VGA
))
16857 i915_redisable_vga_power_on(dev_priv
);
16859 intel_display_power_put(dev_priv
, POWER_DOMAIN_VGA
);
16862 static bool primary_get_hw_state(struct intel_plane
*plane
)
16864 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
16866 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
16869 /* FIXME read out full plane state for all planes */
16870 static void readout_plane_state(struct intel_crtc
*crtc
)
16872 struct drm_plane
*primary
= crtc
->base
.primary
;
16873 struct intel_plane_state
*plane_state
=
16874 to_intel_plane_state(primary
->state
);
16876 plane_state
->base
.visible
= crtc
->active
&&
16877 primary_get_hw_state(to_intel_plane(primary
));
16879 if (plane_state
->base
.visible
)
16880 crtc
->base
.state
->plane_mask
|= 1 << drm_plane_index(primary
);
16883 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
16885 struct drm_i915_private
*dev_priv
= to_i915(dev
);
16887 struct intel_crtc
*crtc
;
16888 struct intel_encoder
*encoder
;
16889 struct intel_connector
*connector
;
16892 dev_priv
->active_crtcs
= 0;
16894 for_each_intel_crtc(dev
, crtc
) {
16895 struct intel_crtc_state
*crtc_state
= crtc
->config
;
16898 __drm_atomic_helper_crtc_destroy_state(&crtc_state
->base
);
16899 memset(crtc_state
, 0, sizeof(*crtc_state
));
16900 crtc_state
->base
.crtc
= &crtc
->base
;
16902 crtc_state
->base
.active
= crtc_state
->base
.enable
=
16903 dev_priv
->display
.get_pipe_config(crtc
, crtc_state
);
16905 crtc
->base
.enabled
= crtc_state
->base
.enable
;
16906 crtc
->active
= crtc_state
->base
.active
;
16908 if (crtc_state
->base
.active
) {
16909 dev_priv
->active_crtcs
|= 1 << crtc
->pipe
;
16911 if (INTEL_GEN(dev_priv
) >= 9 || IS_BROADWELL(dev_priv
))
16912 pixclk
= ilk_pipe_pixel_rate(crtc_state
);
16913 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
16914 pixclk
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
16916 WARN_ON(dev_priv
->display
.modeset_calc_cdclk
);
16918 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16919 if (IS_BROADWELL(dev_priv
) && crtc_state
->ips_enabled
)
16920 pixclk
= DIV_ROUND_UP(pixclk
* 100, 95);
16923 dev_priv
->min_pixclk
[crtc
->pipe
] = pixclk
;
16925 readout_plane_state(crtc
);
16927 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16928 crtc
->base
.base
.id
, crtc
->base
.name
,
16929 enableddisabled(crtc
->active
));
16932 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
16933 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
16935 pll
->on
= pll
->funcs
.get_hw_state(dev_priv
, pll
,
16936 &pll
->config
.hw_state
);
16937 pll
->config
.crtc_mask
= 0;
16938 for_each_intel_crtc(dev
, crtc
) {
16939 if (crtc
->active
&& crtc
->config
->shared_dpll
== pll
)
16940 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
16942 pll
->active_mask
= pll
->config
.crtc_mask
;
16944 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16945 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
16948 for_each_intel_encoder(dev
, encoder
) {
16951 if (encoder
->get_hw_state(encoder
, &pipe
)) {
16952 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
16954 encoder
->base
.crtc
= &crtc
->base
;
16955 crtc
->config
->output_types
|= 1 << encoder
->type
;
16956 encoder
->get_config(encoder
, crtc
->config
);
16958 encoder
->base
.crtc
= NULL
;
16961 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16962 encoder
->base
.base
.id
, encoder
->base
.name
,
16963 enableddisabled(encoder
->base
.crtc
),
16967 for_each_intel_connector(dev
, connector
) {
16968 if (connector
->get_hw_state(connector
)) {
16969 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
16971 encoder
= connector
->encoder
;
16972 connector
->base
.encoder
= &encoder
->base
;
16974 if (encoder
->base
.crtc
&&
16975 encoder
->base
.crtc
->state
->active
) {
16977 * This has to be done during hardware readout
16978 * because anything calling .crtc_disable may
16979 * rely on the connector_mask being accurate.
16981 encoder
->base
.crtc
->state
->connector_mask
|=
16982 1 << drm_connector_index(&connector
->base
);
16983 encoder
->base
.crtc
->state
->encoder_mask
|=
16984 1 << drm_encoder_index(&encoder
->base
);
16988 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
16989 connector
->base
.encoder
= NULL
;
16991 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16992 connector
->base
.base
.id
, connector
->base
.name
,
16993 enableddisabled(connector
->base
.encoder
));
16996 for_each_intel_crtc(dev
, crtc
) {
16997 crtc
->base
.hwmode
= crtc
->config
->base
.adjusted_mode
;
16999 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
17000 if (crtc
->base
.state
->active
) {
17001 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc
->config
);
17002 intel_mode_from_pipe_config(&crtc
->base
.state
->adjusted_mode
, crtc
->config
);
17003 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
17006 * The initial mode needs to be set in order to keep
17007 * the atomic core happy. It wants a valid mode if the
17008 * crtc's enabled, so we do the above call.
17010 * At this point some state updated by the connectors
17011 * in their ->detect() callback has not run yet, so
17012 * no recalculation can be done yet.
17014 * Even if we could do a recalculation and modeset
17015 * right now it would cause a double modeset if
17016 * fbdev or userspace chooses a different initial mode.
17018 * If that happens, someone indicated they wanted a
17019 * mode change, which means it's safe to do a full
17022 crtc
->base
.state
->mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
17024 drm_calc_timestamping_constants(&crtc
->base
, &crtc
->base
.hwmode
);
17025 update_scanline_offset(crtc
);
17028 intel_pipe_config_sanity_check(dev_priv
, crtc
->config
);
17032 /* Scan out the current hw modeset state,
17033 * and sanitizes it to the current state
17036 intel_modeset_setup_hw_state(struct drm_device
*dev
)
17038 struct drm_i915_private
*dev_priv
= to_i915(dev
);
17040 struct intel_crtc
*crtc
;
17041 struct intel_encoder
*encoder
;
17044 intel_modeset_readout_hw_state(dev
);
17046 /* HW state is read out, now we need to sanitize this mess. */
17047 for_each_intel_encoder(dev
, encoder
) {
17048 intel_sanitize_encoder(encoder
);
17051 for_each_pipe(dev_priv
, pipe
) {
17052 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
17054 intel_sanitize_crtc(crtc
);
17055 intel_dump_pipe_config(crtc
, crtc
->config
,
17056 "[setup_hw_state]");
17059 intel_modeset_update_connector_atomic_state(dev
);
17061 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
17062 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
17064 if (!pll
->on
|| pll
->active_mask
)
17067 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
17069 pll
->funcs
.disable(dev_priv
, pll
);
17073 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
17074 vlv_wm_get_hw_state(dev
);
17075 else if (IS_GEN9(dev_priv
))
17076 skl_wm_get_hw_state(dev
);
17077 else if (HAS_PCH_SPLIT(dev_priv
))
17078 ilk_wm_get_hw_state(dev
);
17080 for_each_intel_crtc(dev
, crtc
) {
17081 unsigned long put_domains
;
17083 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
, crtc
->config
);
17084 if (WARN_ON(put_domains
))
17085 modeset_put_power_domains(dev_priv
, put_domains
);
17087 intel_display_set_init_power(dev_priv
, false);
17089 intel_fbc_init_pipe_state(dev_priv
);
17092 void intel_display_resume(struct drm_device
*dev
)
17094 struct drm_i915_private
*dev_priv
= to_i915(dev
);
17095 struct drm_atomic_state
*state
= dev_priv
->modeset_restore_state
;
17096 struct drm_modeset_acquire_ctx ctx
;
17099 dev_priv
->modeset_restore_state
= NULL
;
17101 state
->acquire_ctx
= &ctx
;
17104 * This is a cludge because with real atomic modeset mode_config.mutex
17105 * won't be taken. Unfortunately some probed state like
17106 * audio_codec_enable is still protected by mode_config.mutex, so lock
17109 mutex_lock(&dev
->mode_config
.mutex
);
17110 drm_modeset_acquire_init(&ctx
, 0);
17113 ret
= drm_modeset_lock_all_ctx(dev
, &ctx
);
17114 if (ret
!= -EDEADLK
)
17117 drm_modeset_backoff(&ctx
);
17121 ret
= __intel_display_resume(dev
, state
);
17123 drm_modeset_drop_locks(&ctx
);
17124 drm_modeset_acquire_fini(&ctx
);
17125 mutex_unlock(&dev
->mode_config
.mutex
);
17128 DRM_ERROR("Restoring old state failed with %i\n", ret
);
17129 drm_atomic_state_put(state
);
17132 void intel_modeset_gem_init(struct drm_device
*dev
)
17134 struct drm_i915_private
*dev_priv
= to_i915(dev
);
17135 struct drm_crtc
*c
;
17136 struct drm_i915_gem_object
*obj
;
17138 intel_init_gt_powersave(dev_priv
);
17140 intel_modeset_init_hw(dev
);
17142 intel_setup_overlay(dev_priv
);
17145 * Make sure any fbs we allocated at startup are properly
17146 * pinned & fenced. When we do the allocation it's too early
17149 for_each_crtc(dev
, c
) {
17150 struct i915_vma
*vma
;
17152 obj
= intel_fb_obj(c
->primary
->fb
);
17156 mutex_lock(&dev
->struct_mutex
);
17157 vma
= intel_pin_and_fence_fb_obj(c
->primary
->fb
,
17158 c
->primary
->state
->rotation
);
17159 mutex_unlock(&dev
->struct_mutex
);
17161 DRM_ERROR("failed to pin boot fb on pipe %d\n",
17162 to_intel_crtc(c
)->pipe
);
17163 drm_framebuffer_unreference(c
->primary
->fb
);
17164 c
->primary
->fb
= NULL
;
17165 c
->primary
->crtc
= c
->primary
->state
->crtc
= NULL
;
17166 update_state_fb(c
->primary
);
17167 c
->state
->plane_mask
&= ~(1 << drm_plane_index(c
->primary
));
17172 int intel_connector_register(struct drm_connector
*connector
)
17174 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
17177 ret
= intel_backlight_device_register(intel_connector
);
17187 void intel_connector_unregister(struct drm_connector
*connector
)
17189 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
17191 intel_backlight_device_unregister(intel_connector
);
17192 intel_panel_destroy_backlight(connector
);
17195 void intel_modeset_cleanup(struct drm_device
*dev
)
17197 struct drm_i915_private
*dev_priv
= to_i915(dev
);
17199 intel_disable_gt_powersave(dev_priv
);
17202 * Interrupts and polling as the first thing to avoid creating havoc.
17203 * Too much stuff here (turning of connectors, ...) would
17204 * experience fancy races otherwise.
17206 intel_irq_uninstall(dev_priv
);
17209 * Due to the hpd irq storm handling the hotplug work can re-arm the
17210 * poll handlers. Hence disable polling after hpd handling is shut down.
17212 drm_kms_helper_poll_fini(dev
);
17214 intel_unregister_dsm_handler();
17216 intel_fbc_global_disable(dev_priv
);
17218 /* flush any delayed tasks or pending work */
17219 flush_scheduled_work();
17221 drm_mode_config_cleanup(dev
);
17223 intel_cleanup_overlay(dev_priv
);
17225 intel_cleanup_gt_powersave(dev_priv
);
17227 intel_teardown_gmbus(dev_priv
);
17230 void intel_connector_attach_encoder(struct intel_connector
*connector
,
17231 struct intel_encoder
*encoder
)
17233 connector
->encoder
= encoder
;
17234 drm_mode_connector_attach_encoder(&connector
->base
,
17239 * set vga decode state - true == enable VGA decode
17241 int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
, bool state
)
17243 unsigned reg
= INTEL_GEN(dev_priv
) >= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
17246 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
17247 DRM_ERROR("failed to read control word\n");
17251 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
17255 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
17257 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
17259 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
17260 DRM_ERROR("failed to write control word\n");
17267 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17269 struct intel_display_error_state
{
17271 u32 power_well_driver
;
17273 int num_transcoders
;
17275 struct intel_cursor_error_state
{
17280 } cursor
[I915_MAX_PIPES
];
17282 struct intel_pipe_error_state
{
17283 bool power_domain_on
;
17286 } pipe
[I915_MAX_PIPES
];
17288 struct intel_plane_error_state
{
17296 } plane
[I915_MAX_PIPES
];
17298 struct intel_transcoder_error_state
{
17299 bool power_domain_on
;
17300 enum transcoder cpu_transcoder
;
17313 struct intel_display_error_state
*
17314 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
)
17316 struct intel_display_error_state
*error
;
17317 int transcoders
[] = {
17325 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
17328 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
17332 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
17333 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
17335 for_each_pipe(dev_priv
, i
) {
17336 error
->pipe
[i
].power_domain_on
=
17337 __intel_display_power_is_enabled(dev_priv
,
17338 POWER_DOMAIN_PIPE(i
));
17339 if (!error
->pipe
[i
].power_domain_on
)
17342 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
17343 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
17344 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
17346 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
17347 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
17348 if (INTEL_GEN(dev_priv
) <= 3) {
17349 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
17350 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
17352 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
17353 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
17354 if (INTEL_GEN(dev_priv
) >= 4) {
17355 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
17356 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
17359 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
17361 if (HAS_GMCH_DISPLAY(dev_priv
))
17362 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
17365 /* Note: this does not include DSI transcoders. */
17366 error
->num_transcoders
= INTEL_INFO(dev_priv
)->num_pipes
;
17367 if (HAS_DDI(dev_priv
))
17368 error
->num_transcoders
++; /* Account for eDP. */
17370 for (i
= 0; i
< error
->num_transcoders
; i
++) {
17371 enum transcoder cpu_transcoder
= transcoders
[i
];
17373 error
->transcoder
[i
].power_domain_on
=
17374 __intel_display_power_is_enabled(dev_priv
,
17375 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
17376 if (!error
->transcoder
[i
].power_domain_on
)
17379 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
17381 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
17382 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
17383 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
17384 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
17385 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
17386 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
17387 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
17393 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17396 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
17397 struct drm_i915_private
*dev_priv
,
17398 struct intel_display_error_state
*error
)
17405 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev_priv
)->num_pipes
);
17406 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
17407 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
17408 error
->power_well_driver
);
17409 for_each_pipe(dev_priv
, i
) {
17410 err_printf(m
, "Pipe [%d]:\n", i
);
17411 err_printf(m
, " Power: %s\n",
17412 onoff(error
->pipe
[i
].power_domain_on
));
17413 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
17414 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
17416 err_printf(m
, "Plane [%d]:\n", i
);
17417 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
17418 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
17419 if (INTEL_GEN(dev_priv
) <= 3) {
17420 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
17421 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
17423 if (INTEL_GEN(dev_priv
) <= 7 && !IS_HASWELL(dev_priv
))
17424 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
17425 if (INTEL_GEN(dev_priv
) >= 4) {
17426 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
17427 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
17430 err_printf(m
, "Cursor [%d]:\n", i
);
17431 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
17432 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
17433 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
17436 for (i
= 0; i
< error
->num_transcoders
; i
++) {
17437 err_printf(m
, "CPU transcoder: %s\n",
17438 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
17439 err_printf(m
, " Power: %s\n",
17440 onoff(error
->transcoder
[i
].power_domain_on
));
17441 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
17442 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
17443 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
17444 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
17445 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
17446 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
17447 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);