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drm/i915: Make power domain masks 64 bit long
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125
126 struct intel_limit {
127 struct {
128 int min, max;
129 } dot, vco, n, m, m1, m2, p, p1;
130
131 struct {
132 int dot_limit;
133 int p2_slow, p2_fast;
134 } p2;
135 };
136
137 /* returns HPLL frequency in kHz */
138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
139 {
140 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
141
142 /* Obtain SKU information */
143 mutex_lock(&dev_priv->sb_lock);
144 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145 CCK_FUSE_HPLL_FREQ_MASK;
146 mutex_unlock(&dev_priv->sb_lock);
147
148 return vco_freq[hpll_freq] * 1000;
149 }
150
151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
152 const char *name, u32 reg, int ref_freq)
153 {
154 u32 val;
155 int divider;
156
157 mutex_lock(&dev_priv->sb_lock);
158 val = vlv_cck_read(dev_priv, reg);
159 mutex_unlock(&dev_priv->sb_lock);
160
161 divider = val & CCK_FREQUENCY_VALUES;
162
163 WARN((val & CCK_FREQUENCY_STATUS) !=
164 (divider << CCK_FREQUENCY_STATUS_SHIFT),
165 "%s change in progress\n", name);
166
167 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
168 }
169
170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
171 const char *name, u32 reg)
172 {
173 if (dev_priv->hpll_freq == 0)
174 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
175
176 return vlv_get_cck_clock(dev_priv, name, reg,
177 dev_priv->hpll_freq);
178 }
179
180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
181 {
182 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
183 return;
184
185 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
186 CCK_CZ_CLOCK_CONTROL);
187
188 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
189 }
190
191 static inline u32 /* units of 100MHz */
192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
193 const struct intel_crtc_state *pipe_config)
194 {
195 if (HAS_DDI(dev_priv))
196 return pipe_config->port_clock; /* SPLL */
197 else if (IS_GEN5(dev_priv))
198 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
199 else
200 return 270000;
201 }
202
203 static const struct intel_limit intel_limits_i8xx_dac = {
204 .dot = { .min = 25000, .max = 350000 },
205 .vco = { .min = 908000, .max = 1512000 },
206 .n = { .min = 2, .max = 16 },
207 .m = { .min = 96, .max = 140 },
208 .m1 = { .min = 18, .max = 26 },
209 .m2 = { .min = 6, .max = 16 },
210 .p = { .min = 4, .max = 128 },
211 .p1 = { .min = 2, .max = 33 },
212 .p2 = { .dot_limit = 165000,
213 .p2_slow = 4, .p2_fast = 2 },
214 };
215
216 static const struct intel_limit intel_limits_i8xx_dvo = {
217 .dot = { .min = 25000, .max = 350000 },
218 .vco = { .min = 908000, .max = 1512000 },
219 .n = { .min = 2, .max = 16 },
220 .m = { .min = 96, .max = 140 },
221 .m1 = { .min = 18, .max = 26 },
222 .m2 = { .min = 6, .max = 16 },
223 .p = { .min = 4, .max = 128 },
224 .p1 = { .min = 2, .max = 33 },
225 .p2 = { .dot_limit = 165000,
226 .p2_slow = 4, .p2_fast = 4 },
227 };
228
229 static const struct intel_limit intel_limits_i8xx_lvds = {
230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 908000, .max = 1512000 },
232 .n = { .min = 2, .max = 16 },
233 .m = { .min = 96, .max = 140 },
234 .m1 = { .min = 18, .max = 26 },
235 .m2 = { .min = 6, .max = 16 },
236 .p = { .min = 4, .max = 128 },
237 .p1 = { .min = 1, .max = 6 },
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 14, .p2_fast = 7 },
240 };
241
242 static const struct intel_limit intel_limits_i9xx_sdvo = {
243 .dot = { .min = 20000, .max = 400000 },
244 .vco = { .min = 1400000, .max = 2800000 },
245 .n = { .min = 1, .max = 6 },
246 .m = { .min = 70, .max = 120 },
247 .m1 = { .min = 8, .max = 18 },
248 .m2 = { .min = 3, .max = 7 },
249 .p = { .min = 5, .max = 80 },
250 .p1 = { .min = 1, .max = 8 },
251 .p2 = { .dot_limit = 200000,
252 .p2_slow = 10, .p2_fast = 5 },
253 };
254
255 static const struct intel_limit intel_limits_i9xx_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1400000, .max = 2800000 },
258 .n = { .min = 1, .max = 6 },
259 .m = { .min = 70, .max = 120 },
260 .m1 = { .min = 8, .max = 18 },
261 .m2 = { .min = 3, .max = 7 },
262 .p = { .min = 7, .max = 98 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 7 },
266 };
267
268
269 static const struct intel_limit intel_limits_g4x_sdvo = {
270 .dot = { .min = 25000, .max = 270000 },
271 .vco = { .min = 1750000, .max = 3500000},
272 .n = { .min = 1, .max = 4 },
273 .m = { .min = 104, .max = 138 },
274 .m1 = { .min = 17, .max = 23 },
275 .m2 = { .min = 5, .max = 11 },
276 .p = { .min = 10, .max = 30 },
277 .p1 = { .min = 1, .max = 3},
278 .p2 = { .dot_limit = 270000,
279 .p2_slow = 10,
280 .p2_fast = 10
281 },
282 };
283
284 static const struct intel_limit intel_limits_g4x_hdmi = {
285 .dot = { .min = 22000, .max = 400000 },
286 .vco = { .min = 1750000, .max = 3500000},
287 .n = { .min = 1, .max = 4 },
288 .m = { .min = 104, .max = 138 },
289 .m1 = { .min = 16, .max = 23 },
290 .m2 = { .min = 5, .max = 11 },
291 .p = { .min = 5, .max = 80 },
292 .p1 = { .min = 1, .max = 8},
293 .p2 = { .dot_limit = 165000,
294 .p2_slow = 10, .p2_fast = 5 },
295 };
296
297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
298 .dot = { .min = 20000, .max = 115000 },
299 .vco = { .min = 1750000, .max = 3500000 },
300 .n = { .min = 1, .max = 3 },
301 .m = { .min = 104, .max = 138 },
302 .m1 = { .min = 17, .max = 23 },
303 .m2 = { .min = 5, .max = 11 },
304 .p = { .min = 28, .max = 112 },
305 .p1 = { .min = 2, .max = 8 },
306 .p2 = { .dot_limit = 0,
307 .p2_slow = 14, .p2_fast = 14
308 },
309 };
310
311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
312 .dot = { .min = 80000, .max = 224000 },
313 .vco = { .min = 1750000, .max = 3500000 },
314 .n = { .min = 1, .max = 3 },
315 .m = { .min = 104, .max = 138 },
316 .m1 = { .min = 17, .max = 23 },
317 .m2 = { .min = 5, .max = 11 },
318 .p = { .min = 14, .max = 42 },
319 .p1 = { .min = 2, .max = 6 },
320 .p2 = { .dot_limit = 0,
321 .p2_slow = 7, .p2_fast = 7
322 },
323 };
324
325 static const struct intel_limit intel_limits_pineview_sdvo = {
326 .dot = { .min = 20000, .max = 400000},
327 .vco = { .min = 1700000, .max = 3500000 },
328 /* Pineview's Ncounter is a ring counter */
329 .n = { .min = 3, .max = 6 },
330 .m = { .min = 2, .max = 256 },
331 /* Pineview only has one combined m divider, which we treat as m2. */
332 .m1 = { .min = 0, .max = 0 },
333 .m2 = { .min = 0, .max = 254 },
334 .p = { .min = 5, .max = 80 },
335 .p1 = { .min = 1, .max = 8 },
336 .p2 = { .dot_limit = 200000,
337 .p2_slow = 10, .p2_fast = 5 },
338 };
339
340 static const struct intel_limit intel_limits_pineview_lvds = {
341 .dot = { .min = 20000, .max = 400000 },
342 .vco = { .min = 1700000, .max = 3500000 },
343 .n = { .min = 3, .max = 6 },
344 .m = { .min = 2, .max = 256 },
345 .m1 = { .min = 0, .max = 0 },
346 .m2 = { .min = 0, .max = 254 },
347 .p = { .min = 7, .max = 112 },
348 .p1 = { .min = 1, .max = 8 },
349 .p2 = { .dot_limit = 112000,
350 .p2_slow = 14, .p2_fast = 14 },
351 };
352
353 /* Ironlake / Sandybridge
354 *
355 * We calculate clock using (register_value + 2) for N/M1/M2, so here
356 * the range value for them is (actual_value - 2).
357 */
358 static const struct intel_limit intel_limits_ironlake_dac = {
359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 5 },
362 .m = { .min = 79, .max = 127 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 5, .max = 80 },
366 .p1 = { .min = 1, .max = 8 },
367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 10, .p2_fast = 5 },
369 };
370
371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
372 .dot = { .min = 25000, .max = 350000 },
373 .vco = { .min = 1760000, .max = 3510000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 79, .max = 118 },
376 .m1 = { .min = 12, .max = 22 },
377 .m2 = { .min = 5, .max = 9 },
378 .p = { .min = 28, .max = 112 },
379 .p1 = { .min = 2, .max = 8 },
380 .p2 = { .dot_limit = 225000,
381 .p2_slow = 14, .p2_fast = 14 },
382 };
383
384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
385 .dot = { .min = 25000, .max = 350000 },
386 .vco = { .min = 1760000, .max = 3510000 },
387 .n = { .min = 1, .max = 3 },
388 .m = { .min = 79, .max = 127 },
389 .m1 = { .min = 12, .max = 22 },
390 .m2 = { .min = 5, .max = 9 },
391 .p = { .min = 14, .max = 56 },
392 .p1 = { .min = 2, .max = 8 },
393 .p2 = { .dot_limit = 225000,
394 .p2_slow = 7, .p2_fast = 7 },
395 };
396
397 /* LVDS 100mhz refclk limits. */
398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
399 .dot = { .min = 25000, .max = 350000 },
400 .vco = { .min = 1760000, .max = 3510000 },
401 .n = { .min = 1, .max = 2 },
402 .m = { .min = 79, .max = 126 },
403 .m1 = { .min = 12, .max = 22 },
404 .m2 = { .min = 5, .max = 9 },
405 .p = { .min = 28, .max = 112 },
406 .p1 = { .min = 2, .max = 8 },
407 .p2 = { .dot_limit = 225000,
408 .p2_slow = 14, .p2_fast = 14 },
409 };
410
411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
412 .dot = { .min = 25000, .max = 350000 },
413 .vco = { .min = 1760000, .max = 3510000 },
414 .n = { .min = 1, .max = 3 },
415 .m = { .min = 79, .max = 126 },
416 .m1 = { .min = 12, .max = 22 },
417 .m2 = { .min = 5, .max = 9 },
418 .p = { .min = 14, .max = 42 },
419 .p1 = { .min = 2, .max = 6 },
420 .p2 = { .dot_limit = 225000,
421 .p2_slow = 7, .p2_fast = 7 },
422 };
423
424 static const struct intel_limit intel_limits_vlv = {
425 /*
426 * These are the data rate limits (measured in fast clocks)
427 * since those are the strictest limits we have. The fast
428 * clock and actual rate limits are more relaxed, so checking
429 * them would make no difference.
430 */
431 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
432 .vco = { .min = 4000000, .max = 6000000 },
433 .n = { .min = 1, .max = 7 },
434 .m1 = { .min = 2, .max = 3 },
435 .m2 = { .min = 11, .max = 156 },
436 .p1 = { .min = 2, .max = 3 },
437 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
438 };
439
440 static const struct intel_limit intel_limits_chv = {
441 /*
442 * These are the data rate limits (measured in fast clocks)
443 * since those are the strictest limits we have. The fast
444 * clock and actual rate limits are more relaxed, so checking
445 * them would make no difference.
446 */
447 .dot = { .min = 25000 * 5, .max = 540000 * 5},
448 .vco = { .min = 4800000, .max = 6480000 },
449 .n = { .min = 1, .max = 1 },
450 .m1 = { .min = 2, .max = 2 },
451 .m2 = { .min = 24 << 22, .max = 175 << 22 },
452 .p1 = { .min = 2, .max = 4 },
453 .p2 = { .p2_slow = 1, .p2_fast = 14 },
454 };
455
456 static const struct intel_limit intel_limits_bxt = {
457 /* FIXME: find real dot limits */
458 .dot = { .min = 0, .max = INT_MAX },
459 .vco = { .min = 4800000, .max = 6700000 },
460 .n = { .min = 1, .max = 1 },
461 .m1 = { .min = 2, .max = 2 },
462 /* FIXME: find real m2 limits */
463 .m2 = { .min = 2 << 22, .max = 255 << 22 },
464 .p1 = { .min = 2, .max = 4 },
465 .p2 = { .p2_slow = 1, .p2_fast = 20 },
466 };
467
468 static bool
469 needs_modeset(struct drm_crtc_state *state)
470 {
471 return drm_atomic_crtc_needs_modeset(state);
472 }
473
474 /*
475 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
476 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
477 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
478 * The helpers' return value is the rate of the clock that is fed to the
479 * display engine's pipe which can be the above fast dot clock rate or a
480 * divided-down version of it.
481 */
482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
484 {
485 clock->m = clock->m2 + 2;
486 clock->p = clock->p1 * clock->p2;
487 if (WARN_ON(clock->n == 0 || clock->p == 0))
488 return 0;
489 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
490 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
491
492 return clock->dot;
493 }
494
495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
496 {
497 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
498 }
499
500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
501 {
502 clock->m = i9xx_dpll_compute_m(clock);
503 clock->p = clock->p1 * clock->p2;
504 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
505 return 0;
506 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
507 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
508
509 return clock->dot;
510 }
511
512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
513 {
514 clock->m = clock->m1 * clock->m2;
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n == 0 || clock->p == 0))
517 return 0;
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520
521 return clock->dot / 5;
522 }
523
524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
525 {
526 clock->m = clock->m1 * clock->m2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return 0;
530 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
531 clock->n << 22);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533
534 return clock->dot / 5;
535 }
536
537 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
538 /**
539 * Returns whether the given set of divisors are valid for a given refclk with
540 * the given connectors.
541 */
542
543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
544 const struct intel_limit *limit,
545 const struct dpll *clock)
546 {
547 if (clock->n < limit->n.min || limit->n.max < clock->n)
548 INTELPllInvalid("n out of range\n");
549 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
550 INTELPllInvalid("p1 out of range\n");
551 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
552 INTELPllInvalid("m2 out of range\n");
553 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
554 INTELPllInvalid("m1 out of range\n");
555
556 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
557 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
558 if (clock->m1 <= clock->m2)
559 INTELPllInvalid("m1 <= m2\n");
560
561 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
562 !IS_GEN9_LP(dev_priv)) {
563 if (clock->p < limit->p.min || limit->p.max < clock->p)
564 INTELPllInvalid("p out of range\n");
565 if (clock->m < limit->m.min || limit->m.max < clock->m)
566 INTELPllInvalid("m out of range\n");
567 }
568
569 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
570 INTELPllInvalid("vco out of range\n");
571 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
572 * connector, etc., rather than just a single range.
573 */
574 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
575 INTELPllInvalid("dot out of range\n");
576
577 return true;
578 }
579
580 static int
581 i9xx_select_p2_div(const struct intel_limit *limit,
582 const struct intel_crtc_state *crtc_state,
583 int target)
584 {
585 struct drm_device *dev = crtc_state->base.crtc->dev;
586
587 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
588 /*
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
592 */
593 if (intel_is_dual_link_lvds(dev))
594 return limit->p2.p2_fast;
595 else
596 return limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 return limit->p2.p2_slow;
600 else
601 return limit->p2.p2_fast;
602 }
603 }
604
605 /*
606 * Returns a set of divisors for the desired target clock with the given
607 * refclk, or FALSE. The returned values represent the clock equation:
608 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
609 *
610 * Target and reference clocks are specified in kHz.
611 *
612 * If match_clock is provided, then best_clock P divider must match the P
613 * divider from @match_clock used for LVDS downclocking.
614 */
615 static bool
616 i9xx_find_best_dpll(const struct intel_limit *limit,
617 struct intel_crtc_state *crtc_state,
618 int target, int refclk, struct dpll *match_clock,
619 struct dpll *best_clock)
620 {
621 struct drm_device *dev = crtc_state->base.crtc->dev;
622 struct dpll clock;
623 int err = target;
624
625 memset(best_clock, 0, sizeof(*best_clock));
626
627 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_calc_dpll_params(refclk, &clock);
642 if (!intel_PLL_is_valid(to_i915(dev),
643 limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661 }
662
663 /*
664 * Returns a set of divisors for the desired target clock with the given
665 * refclk, or FALSE. The returned values represent the clock equation:
666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
667 *
668 * Target and reference clocks are specified in kHz.
669 *
670 * If match_clock is provided, then best_clock P divider must match the P
671 * divider from @match_clock used for LVDS downclocking.
672 */
673 static bool
674 pnv_find_best_dpll(const struct intel_limit *limit,
675 struct intel_crtc_state *crtc_state,
676 int target, int refclk, struct dpll *match_clock,
677 struct dpll *best_clock)
678 {
679 struct drm_device *dev = crtc_state->base.crtc->dev;
680 struct dpll clock;
681 int err = target;
682
683 memset(best_clock, 0, sizeof(*best_clock));
684
685 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
686
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
695 int this_err;
696
697 pnv_calc_dpll_params(refclk, &clock);
698 if (!intel_PLL_is_valid(to_i915(dev),
699 limit,
700 &clock))
701 continue;
702 if (match_clock &&
703 clock.p != match_clock->p)
704 continue;
705
706 this_err = abs(clock.dot - target);
707 if (this_err < err) {
708 *best_clock = clock;
709 err = this_err;
710 }
711 }
712 }
713 }
714 }
715
716 return (err != target);
717 }
718
719 /*
720 * Returns a set of divisors for the desired target clock with the given
721 * refclk, or FALSE. The returned values represent the clock equation:
722 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
723 *
724 * Target and reference clocks are specified in kHz.
725 *
726 * If match_clock is provided, then best_clock P divider must match the P
727 * divider from @match_clock used for LVDS downclocking.
728 */
729 static bool
730 g4x_find_best_dpll(const struct intel_limit *limit,
731 struct intel_crtc_state *crtc_state,
732 int target, int refclk, struct dpll *match_clock,
733 struct dpll *best_clock)
734 {
735 struct drm_device *dev = crtc_state->base.crtc->dev;
736 struct dpll clock;
737 int max_n;
738 bool found = false;
739 /* approximately equals target * 0.00585 */
740 int err_most = (target >> 8) + (target >> 9);
741
742 memset(best_clock, 0, sizeof(*best_clock));
743
744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
746 max_n = limit->n.max;
747 /* based on hardware requirement, prefer smaller n to precision */
748 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
749 /* based on hardware requirement, prefere larger m1,m2 */
750 for (clock.m1 = limit->m1.max;
751 clock.m1 >= limit->m1.min; clock.m1--) {
752 for (clock.m2 = limit->m2.max;
753 clock.m2 >= limit->m2.min; clock.m2--) {
754 for (clock.p1 = limit->p1.max;
755 clock.p1 >= limit->p1.min; clock.p1--) {
756 int this_err;
757
758 i9xx_calc_dpll_params(refclk, &clock);
759 if (!intel_PLL_is_valid(to_i915(dev),
760 limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 /*
779 * Check if the calculated PLL configuration is more optimal compared to the
780 * best configuration and error found so far. Return the calculated error.
781 */
782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
783 const struct dpll *calculated_clock,
784 const struct dpll *best_clock,
785 unsigned int best_error_ppm,
786 unsigned int *error_ppm)
787 {
788 /*
789 * For CHV ignore the error and consider only the P value.
790 * Prefer a bigger P value based on HW requirements.
791 */
792 if (IS_CHERRYVIEW(to_i915(dev))) {
793 *error_ppm = 0;
794
795 return calculated_clock->p > best_clock->p;
796 }
797
798 if (WARN_ON_ONCE(!target_freq))
799 return false;
800
801 *error_ppm = div_u64(1000000ULL *
802 abs(target_freq - calculated_clock->dot),
803 target_freq);
804 /*
805 * Prefer a better P value over a better (smaller) error if the error
806 * is small. Ensure this preference for future configurations too by
807 * setting the error to 0.
808 */
809 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
810 *error_ppm = 0;
811
812 return true;
813 }
814
815 return *error_ppm + 10 < best_error_ppm;
816 }
817
818 /*
819 * Returns a set of divisors for the desired target clock with the given
820 * refclk, or FALSE. The returned values represent the clock equation:
821 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
822 */
823 static bool
824 vlv_find_best_dpll(const struct intel_limit *limit,
825 struct intel_crtc_state *crtc_state,
826 int target, int refclk, struct dpll *match_clock,
827 struct dpll *best_clock)
828 {
829 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
830 struct drm_device *dev = crtc->base.dev;
831 struct dpll clock;
832 unsigned int bestppm = 1000000;
833 /* min update 19.2 MHz */
834 int max_n = min(limit->n.max, refclk / 19200);
835 bool found = false;
836
837 target *= 5; /* fast clock */
838
839 memset(best_clock, 0, sizeof(*best_clock));
840
841 /* based on hardware requirement, prefer smaller n to precision */
842 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
843 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
844 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
845 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
846 clock.p = clock.p1 * clock.p2;
847 /* based on hardware requirement, prefer bigger m1,m2 values */
848 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
849 unsigned int ppm;
850
851 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
852 refclk * clock.m1);
853
854 vlv_calc_dpll_params(refclk, &clock);
855
856 if (!intel_PLL_is_valid(to_i915(dev),
857 limit,
858 &clock))
859 continue;
860
861 if (!vlv_PLL_is_optimal(dev, target,
862 &clock,
863 best_clock,
864 bestppm, &ppm))
865 continue;
866
867 *best_clock = clock;
868 bestppm = ppm;
869 found = true;
870 }
871 }
872 }
873 }
874
875 return found;
876 }
877
878 /*
879 * Returns a set of divisors for the desired target clock with the given
880 * refclk, or FALSE. The returned values represent the clock equation:
881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882 */
883 static bool
884 chv_find_best_dpll(const struct intel_limit *limit,
885 struct intel_crtc_state *crtc_state,
886 int target, int refclk, struct dpll *match_clock,
887 struct dpll *best_clock)
888 {
889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
890 struct drm_device *dev = crtc->base.dev;
891 unsigned int best_error_ppm;
892 struct dpll clock;
893 uint64_t m2;
894 int found = false;
895
896 memset(best_clock, 0, sizeof(*best_clock));
897 best_error_ppm = 1000000;
898
899 /*
900 * Based on hardware doc, the n always set to 1, and m1 always
901 * set to 2. If requires to support 200Mhz refclk, we need to
902 * revisit this because n may not 1 anymore.
903 */
904 clock.n = 1, clock.m1 = 2;
905 target *= 5; /* fast clock */
906
907 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
908 for (clock.p2 = limit->p2.p2_fast;
909 clock.p2 >= limit->p2.p2_slow;
910 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
911 unsigned int error_ppm;
912
913 clock.p = clock.p1 * clock.p2;
914
915 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
916 clock.n) << 22, refclk * clock.m1);
917
918 if (m2 > INT_MAX/clock.m1)
919 continue;
920
921 clock.m2 = m2;
922
923 chv_calc_dpll_params(refclk, &clock);
924
925 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
926 continue;
927
928 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
929 best_error_ppm, &error_ppm))
930 continue;
931
932 *best_clock = clock;
933 best_error_ppm = error_ppm;
934 found = true;
935 }
936 }
937
938 return found;
939 }
940
941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
942 struct dpll *best_clock)
943 {
944 int refclk = 100000;
945 const struct intel_limit *limit = &intel_limits_bxt;
946
947 return chv_find_best_dpll(limit, crtc_state,
948 target_clock, refclk, NULL, best_clock);
949 }
950
951 bool intel_crtc_active(struct intel_crtc *crtc)
952 {
953 /* Be paranoid as we can arrive here with only partial
954 * state retrieved from the hardware during setup.
955 *
956 * We can ditch the adjusted_mode.crtc_clock check as soon
957 * as Haswell has gained clock readout/fastboot support.
958 *
959 * We can ditch the crtc->primary->fb check as soon as we can
960 * properly reconstruct framebuffers.
961 *
962 * FIXME: The intel_crtc->active here should be switched to
963 * crtc->state->active once we have proper CRTC states wired up
964 * for atomic.
965 */
966 return crtc->active && crtc->base.primary->state->fb &&
967 crtc->config->base.adjusted_mode.crtc_clock;
968 }
969
970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
971 enum pipe pipe)
972 {
973 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
974
975 return crtc->config->cpu_transcoder;
976 }
977
978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
979 {
980 i915_reg_t reg = PIPEDSL(pipe);
981 u32 line1, line2;
982 u32 line_mask;
983
984 if (IS_GEN2(dev_priv))
985 line_mask = DSL_LINEMASK_GEN2;
986 else
987 line_mask = DSL_LINEMASK_GEN3;
988
989 line1 = I915_READ(reg) & line_mask;
990 msleep(5);
991 line2 = I915_READ(reg) & line_mask;
992
993 return line1 == line2;
994 }
995
996 /*
997 * intel_wait_for_pipe_off - wait for pipe to turn off
998 * @crtc: crtc whose pipe to wait for
999 *
1000 * After disabling a pipe, we can't wait for vblank in the usual way,
1001 * spinning on the vblank interrupt status bit, since we won't actually
1002 * see an interrupt when the pipe is disabled.
1003 *
1004 * On Gen4 and above:
1005 * wait for the pipe register state bit to turn off
1006 *
1007 * Otherwise:
1008 * wait for the display line value to settle (it usually
1009 * ends up stopping at the start of the next frame).
1010 *
1011 */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016 enum pipe pipe = crtc->pipe;
1017
1018 if (INTEL_GEN(dev_priv) >= 4) {
1019 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021 /* Wait for the Pipe State to go off */
1022 if (intel_wait_for_register(dev_priv,
1023 reg, I965_PIPECONF_ACTIVE, 0,
1024 100))
1025 WARN(1, "pipe_off wait timed out\n");
1026 } else {
1027 /* Wait for the display line to settle */
1028 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029 WARN(1, "pipe_off wait timed out\n");
1030 }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, bool state)
1036 {
1037 u32 val;
1038 bool cur_state;
1039
1040 val = I915_READ(DPLL(pipe));
1041 cur_state = !!(val & DPLL_VCO_ENABLE);
1042 I915_STATE_WARN(cur_state != state,
1043 "PLL state assertion failure (expected %s, current %s)\n",
1044 onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050 u32 val;
1051 bool cur_state;
1052
1053 mutex_lock(&dev_priv->sb_lock);
1054 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055 mutex_unlock(&dev_priv->sb_lock);
1056
1057 cur_state = val & DSI_PLL_VCO_EN;
1058 I915_STATE_WARN(cur_state != state,
1059 "DSI PLL state assertion failure (expected %s, current %s)\n",
1060 onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064 enum pipe pipe, bool state)
1065 {
1066 bool cur_state;
1067 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068 pipe);
1069
1070 if (HAS_DDI(dev_priv)) {
1071 /* DDI does not have a specific FDI_TX register */
1072 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074 } else {
1075 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076 cur_state = !!(val & FDI_TX_ENABLE);
1077 }
1078 I915_STATE_WARN(cur_state != state,
1079 "FDI TX state assertion failure (expected %s, current %s)\n",
1080 onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1087 {
1088 u32 val;
1089 bool cur_state;
1090
1091 val = I915_READ(FDI_RX_CTL(pipe));
1092 cur_state = !!(val & FDI_RX_ENABLE);
1093 I915_STATE_WARN(cur_state != state,
1094 "FDI RX state assertion failure (expected %s, current %s)\n",
1095 onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101 enum pipe pipe)
1102 {
1103 u32 val;
1104
1105 /* ILK FDI PLL is always enabled */
1106 if (IS_GEN5(dev_priv))
1107 return;
1108
1109 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110 if (HAS_DDI(dev_priv))
1111 return;
1112
1113 val = I915_READ(FDI_TX_CTL(pipe));
1114 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118 enum pipe pipe, bool state)
1119 {
1120 u32 val;
1121 bool cur_state;
1122
1123 val = I915_READ(FDI_RX_CTL(pipe));
1124 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125 I915_STATE_WARN(cur_state != state,
1126 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127 onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132 i915_reg_t pp_reg;
1133 u32 val;
1134 enum pipe panel_pipe = PIPE_A;
1135 bool locked = true;
1136
1137 if (WARN_ON(HAS_DDI(dev_priv)))
1138 return;
1139
1140 if (HAS_PCH_SPLIT(dev_priv)) {
1141 u32 port_sel;
1142
1143 pp_reg = PP_CONTROL(0);
1144 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148 panel_pipe = PIPE_B;
1149 /* XXX: else fix for eDP */
1150 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151 /* presumably write lock depends on pipe, not port select */
1152 pp_reg = PP_CONTROL(pipe);
1153 panel_pipe = pipe;
1154 } else {
1155 pp_reg = PP_CONTROL(0);
1156 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157 panel_pipe = PIPE_B;
1158 }
1159
1160 val = I915_READ(pp_reg);
1161 if (!(val & PANEL_POWER_ON) ||
1162 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163 locked = false;
1164
1165 I915_STATE_WARN(panel_pipe == pipe && locked,
1166 "panel assertion failure, pipe %c regs locked\n",
1167 pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171 enum pipe pipe, bool state)
1172 {
1173 bool cur_state;
1174
1175 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177 else
1178 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180 I915_STATE_WARN(cur_state != state,
1181 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182 pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188 enum pipe pipe, bool state)
1189 {
1190 bool cur_state;
1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
1193 enum intel_display_power_domain power_domain;
1194
1195 /* if we need the pipe quirk it must be always on */
1196 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198 state = true;
1199
1200 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205 intel_display_power_put(dev_priv, power_domain);
1206 } else {
1207 cur_state = false;
1208 }
1209
1210 I915_STATE_WARN(cur_state != state,
1211 "pipe %c assertion failure (expected %s, current %s)\n",
1212 pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216 enum plane plane, bool state)
1217 {
1218 u32 val;
1219 bool cur_state;
1220
1221 val = I915_READ(DSPCNTR(plane));
1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "plane %c assertion failure (expected %s, current %s)\n",
1225 plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233 {
1234 int i;
1235
1236 /* Primary planes are fixed to pipes on gen4+ */
1237 if (INTEL_GEN(dev_priv) >= 4) {
1238 u32 val = I915_READ(DSPCNTR(pipe));
1239 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240 "plane %c assertion failure, should be disabled but not\n",
1241 plane_name(pipe));
1242 return;
1243 }
1244
1245 /* Need to check both planes against the pipe */
1246 for_each_pipe(dev_priv, i) {
1247 u32 val = I915_READ(DSPCNTR(i));
1248 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249 DISPPLANE_SEL_PIPE_SHIFT;
1250 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252 plane_name(i), pipe_name(pipe));
1253 }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
1258 {
1259 int sprite;
1260
1261 if (INTEL_GEN(dev_priv) >= 9) {
1262 for_each_sprite(dev_priv, pipe, sprite) {
1263 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266 sprite, pipe_name(pipe));
1267 }
1268 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269 for_each_sprite(dev_priv, pipe, sprite) {
1270 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271 I915_STATE_WARN(val & SP_ENABLE,
1272 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273 sprite_name(pipe, sprite), pipe_name(pipe));
1274 }
1275 } else if (INTEL_GEN(dev_priv) >= 7) {
1276 u32 val = I915_READ(SPRCTL(pipe));
1277 I915_STATE_WARN(val & SPRITE_ENABLE,
1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279 plane_name(pipe), pipe_name(pipe));
1280 } else if (INTEL_GEN(dev_priv) >= 5) {
1281 u32 val = I915_READ(DVSCNTR(pipe));
1282 I915_STATE_WARN(val & DVS_ENABLE,
1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284 plane_name(pipe), pipe_name(pipe));
1285 }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 u32 val;
1298 bool enabled;
1299
1300 val = I915_READ(PCH_TRANSCONF(pipe));
1301 enabled = !!(val & TRANS_ENABLE);
1302 I915_STATE_WARN(enabled,
1303 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304 pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310 if ((val & DP_PORT_EN) == 0)
1311 return false;
1312
1313 if (HAS_PCH_CPT(dev_priv)) {
1314 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else if (IS_CHERRYVIEW(dev_priv)) {
1318 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329 {
1330 if ((val & SDVO_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv)) {
1334 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335 return false;
1336 } else if (IS_CHERRYVIEW(dev_priv)) {
1337 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338 return false;
1339 } else {
1340 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341 return false;
1342 }
1343 return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1348 {
1349 if ((val & LVDS_PORT_EN) == 0)
1350 return false;
1351
1352 if (HAS_PCH_CPT(dev_priv)) {
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354 return false;
1355 } else {
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357 return false;
1358 }
1359 return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1366 return false;
1367 if (HAS_PCH_CPT(dev_priv)) {
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 return false;
1370 } else {
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372 return false;
1373 }
1374 return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe, i915_reg_t reg,
1379 u32 port_sel)
1380 {
1381 u32 val = I915_READ(reg);
1382 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384 i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387 && (val & DP_PIPEB_SELECT),
1388 "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, i915_reg_t reg)
1393 {
1394 u32 val = I915_READ(reg);
1395 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397 i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400 && (val & SDVO_PIPE_B_SELECT),
1401 "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
1406 {
1407 u32 val;
1408
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413 val = I915_READ(PCH_ADPA);
1414 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415 "PCH VGA enabled on transcoder %c, should be disabled\n",
1416 pipe_name(pipe));
1417
1418 val = I915_READ(PCH_LVDS);
1419 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421 pipe_name(pipe));
1422
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429 const struct intel_crtc_state *pipe_config)
1430 {
1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432 enum pipe pipe = crtc->pipe;
1433
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435 POSTING_READ(DPLL(pipe));
1436 udelay(150);
1437
1438 if (intel_wait_for_register(dev_priv,
1439 DPLL(pipe),
1440 DPLL_LOCK_VLV,
1441 DPLL_LOCK_VLV,
1442 1))
1443 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447 const struct intel_crtc_state *pipe_config)
1448 {
1449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450 enum pipe pipe = crtc->pipe;
1451
1452 assert_pipe_disabled(dev_priv, pipe);
1453
1454 /* PLL is protected by panel, make sure we can write it */
1455 assert_panel_unlocked(dev_priv, pipe);
1456
1457 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458 _vlv_enable_pll(crtc, pipe_config);
1459
1460 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461 POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466 const struct intel_crtc_state *pipe_config)
1467 {
1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469 enum pipe pipe = crtc->pipe;
1470 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471 u32 tmp;
1472
1473 mutex_lock(&dev_priv->sb_lock);
1474
1475 /* Enable back the 10bit clock to display controller */
1476 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477 tmp |= DPIO_DCLKP_EN;
1478 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480 mutex_unlock(&dev_priv->sb_lock);
1481
1482 /*
1483 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484 */
1485 udelay(1);
1486
1487 /* Enable PLL */
1488 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490 /* Check PLL is locked */
1491 if (intel_wait_for_register(dev_priv,
1492 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493 1))
1494 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498 const struct intel_crtc_state *pipe_config)
1499 {
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501 enum pipe pipe = crtc->pipe;
1502
1503 assert_pipe_disabled(dev_priv, pipe);
1504
1505 /* PLL is protected by panel, make sure we can write it */
1506 assert_panel_unlocked(dev_priv, pipe);
1507
1508 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509 _chv_enable_pll(crtc, pipe_config);
1510
1511 if (pipe != PIPE_A) {
1512 /*
1513 * WaPixelRepeatModeFixForC0:chv
1514 *
1515 * DPLLCMD is AWOL. Use chicken bits to propagate
1516 * the value from DPLLBMD to either pipe B or C.
1517 */
1518 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520 I915_WRITE(CBR4_VLV, 0);
1521 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523 /*
1524 * DPLLB VGA mode also seems to cause problems.
1525 * We should always have it disabled.
1526 */
1527 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528 } else {
1529 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530 POSTING_READ(DPLL_MD(pipe));
1531 }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536 struct intel_crtc *crtc;
1537 int count = 0;
1538
1539 for_each_intel_crtc(&dev_priv->drm, crtc) {
1540 count += crtc->base.state->active &&
1541 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542 }
1543
1544 return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550 i915_reg_t reg = DPLL(crtc->pipe);
1551 u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553 assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555 /* PLL is protected by panel, make sure we can write it */
1556 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559 /* Enable DVO 2x clock on both PLLs if necessary */
1560 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561 /*
1562 * It appears to be important that we don't enable this
1563 * for the current pipe before otherwise configuring the
1564 * PLL. No idea how this should be handled if multiple
1565 * DVO outputs are enabled simultaneosly.
1566 */
1567 dpll |= DPLL_DVO_2X_MODE;
1568 I915_WRITE(DPLL(!crtc->pipe),
1569 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570 }
1571
1572 /*
1573 * Apparently we need to have VGA mode enabled prior to changing
1574 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575 * dividers, even though the register value does change.
1576 */
1577 I915_WRITE(reg, 0);
1578
1579 I915_WRITE(reg, dpll);
1580
1581 /* Wait for the clocks to stabilize. */
1582 POSTING_READ(reg);
1583 udelay(150);
1584
1585 if (INTEL_GEN(dev_priv) >= 4) {
1586 I915_WRITE(DPLL_MD(crtc->pipe),
1587 crtc->config->dpll_hw_state.dpll_md);
1588 } else {
1589 /* The pixel multiplier can only be updated once the
1590 * DPLL is enabled and the clocks are stable.
1591 *
1592 * So write it again.
1593 */
1594 I915_WRITE(reg, dpll);
1595 }
1596
1597 /* We do this three times for luck */
1598 I915_WRITE(reg, dpll);
1599 POSTING_READ(reg);
1600 udelay(150); /* wait for warmup */
1601 I915_WRITE(reg, dpll);
1602 POSTING_READ(reg);
1603 udelay(150); /* wait for warmup */
1604 I915_WRITE(reg, dpll);
1605 POSTING_READ(reg);
1606 udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610 * i9xx_disable_pll - disable a PLL
1611 * @dev_priv: i915 private structure
1612 * @pipe: pipe PLL to disable
1613 *
1614 * Disable the PLL for @pipe, making sure the pipe is off first.
1615 *
1616 * Note! This is for pre-ILK only.
1617 */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621 enum pipe pipe = crtc->pipe;
1622
1623 /* Disable DVO 2x clock on both PLLs if necessary */
1624 if (IS_I830(dev_priv) &&
1625 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626 !intel_num_dvo_pipes(dev_priv)) {
1627 I915_WRITE(DPLL(PIPE_B),
1628 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629 I915_WRITE(DPLL(PIPE_A),
1630 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631 }
1632
1633 /* Don't disable pipe or pipe PLLs if needed */
1634 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636 return;
1637
1638 /* Make sure the pipe isn't still relying on us */
1639 assert_pipe_disabled(dev_priv, pipe);
1640
1641 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642 POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647 u32 val;
1648
1649 /* Make sure the pipe isn't still relying on us */
1650 assert_pipe_disabled(dev_priv, pipe);
1651
1652 val = DPLL_INTEGRATED_REF_CLK_VLV |
1653 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654 if (pipe != PIPE_A)
1655 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657 I915_WRITE(DPLL(pipe), val);
1658 POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664 u32 val;
1665
1666 /* Make sure the pipe isn't still relying on us */
1667 assert_pipe_disabled(dev_priv, pipe);
1668
1669 val = DPLL_SSC_REF_CLK_CHV |
1670 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671 if (pipe != PIPE_A)
1672 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674 I915_WRITE(DPLL(pipe), val);
1675 POSTING_READ(DPLL(pipe));
1676
1677 mutex_lock(&dev_priv->sb_lock);
1678
1679 /* Disable 10bit clock to display controller */
1680 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681 val &= ~DPIO_DCLKP_EN;
1682 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684 mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688 struct intel_digital_port *dport,
1689 unsigned int expected_mask)
1690 {
1691 u32 port_mask;
1692 i915_reg_t dpll_reg;
1693
1694 switch (dport->port) {
1695 case PORT_B:
1696 port_mask = DPLL_PORTB_READY_MASK;
1697 dpll_reg = DPLL(0);
1698 break;
1699 case PORT_C:
1700 port_mask = DPLL_PORTC_READY_MASK;
1701 dpll_reg = DPLL(0);
1702 expected_mask <<= 4;
1703 break;
1704 case PORT_D:
1705 port_mask = DPLL_PORTD_READY_MASK;
1706 dpll_reg = DPIO_PHY_STATUS;
1707 break;
1708 default:
1709 BUG();
1710 }
1711
1712 if (intel_wait_for_register(dev_priv,
1713 dpll_reg, port_mask, expected_mask,
1714 1000))
1715 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720 enum pipe pipe)
1721 {
1722 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723 pipe);
1724 i915_reg_t reg;
1725 uint32_t val, pipeconf_val;
1726
1727 /* Make sure PCH DPLL is enabled */
1728 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730 /* FDI must be feeding us bits for PCH ports */
1731 assert_fdi_tx_enabled(dev_priv, pipe);
1732 assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734 if (HAS_PCH_CPT(dev_priv)) {
1735 /* Workaround: Set the timing override bit before enabling the
1736 * pch transcoder. */
1737 reg = TRANS_CHICKEN2(pipe);
1738 val = I915_READ(reg);
1739 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740 I915_WRITE(reg, val);
1741 }
1742
1743 reg = PCH_TRANSCONF(pipe);
1744 val = I915_READ(reg);
1745 pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747 if (HAS_PCH_IBX(dev_priv)) {
1748 /*
1749 * Make the BPC in transcoder be consistent with
1750 * that in pipeconf reg. For HDMI we must use 8bpc
1751 * here for both 8bpc and 12bpc.
1752 */
1753 val &= ~PIPECONF_BPC_MASK;
1754 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755 val |= PIPECONF_8BPC;
1756 else
1757 val |= pipeconf_val & PIPECONF_BPC_MASK;
1758 }
1759
1760 val &= ~TRANS_INTERLACE_MASK;
1761 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762 if (HAS_PCH_IBX(dev_priv) &&
1763 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764 val |= TRANS_LEGACY_INTERLACED_ILK;
1765 else
1766 val |= TRANS_INTERLACED;
1767 else
1768 val |= TRANS_PROGRESSIVE;
1769
1770 I915_WRITE(reg, val | TRANS_ENABLE);
1771 if (intel_wait_for_register(dev_priv,
1772 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773 100))
1774 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778 enum transcoder cpu_transcoder)
1779 {
1780 u32 val, pipeconf_val;
1781
1782 /* FDI must be feeding us bits for PCH ports */
1783 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786 /* Workaround: set timing override bit. */
1787 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791 val = TRANS_ENABLE;
1792 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795 PIPECONF_INTERLACED_ILK)
1796 val |= TRANS_INTERLACED;
1797 else
1798 val |= TRANS_PROGRESSIVE;
1799
1800 I915_WRITE(LPT_TRANSCONF, val);
1801 if (intel_wait_for_register(dev_priv,
1802 LPT_TRANSCONF,
1803 TRANS_STATE_ENABLE,
1804 TRANS_STATE_ENABLE,
1805 100))
1806 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810 enum pipe pipe)
1811 {
1812 i915_reg_t reg;
1813 uint32_t val;
1814
1815 /* FDI relies on the transcoder */
1816 assert_fdi_tx_disabled(dev_priv, pipe);
1817 assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819 /* Ports must be off as well */
1820 assert_pch_ports_disabled(dev_priv, pipe);
1821
1822 reg = PCH_TRANSCONF(pipe);
1823 val = I915_READ(reg);
1824 val &= ~TRANS_ENABLE;
1825 I915_WRITE(reg, val);
1826 /* wait for PCH transcoder off, transcoder state */
1827 if (intel_wait_for_register(dev_priv,
1828 reg, TRANS_STATE_ENABLE, 0,
1829 50))
1830 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832 if (HAS_PCH_CPT(dev_priv)) {
1833 /* Workaround: Clear the timing override chicken bit again. */
1834 reg = TRANS_CHICKEN2(pipe);
1835 val = I915_READ(reg);
1836 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837 I915_WRITE(reg, val);
1838 }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843 u32 val;
1844
1845 val = I915_READ(LPT_TRANSCONF);
1846 val &= ~TRANS_ENABLE;
1847 I915_WRITE(LPT_TRANSCONF, val);
1848 /* wait for PCH transcoder off, transcoder state */
1849 if (intel_wait_for_register(dev_priv,
1850 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851 50))
1852 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854 /* Workaround: clear timing override bit. */
1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864 WARN_ON(!crtc->config->has_pch_encoder);
1865
1866 if (HAS_PCH_LPT(dev_priv))
1867 return TRANSCODER_A;
1868 else
1869 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873 * intel_enable_pipe - enable a pipe, asserting requirements
1874 * @crtc: crtc responsible for the pipe
1875 *
1876 * Enable @crtc's pipe, making sure that various hardware specific requirements
1877 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878 */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881 struct drm_device *dev = crtc->base.dev;
1882 struct drm_i915_private *dev_priv = to_i915(dev);
1883 enum pipe pipe = crtc->pipe;
1884 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885 i915_reg_t reg;
1886 u32 val;
1887
1888 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890 assert_planes_disabled(dev_priv, pipe);
1891 assert_cursor_disabled(dev_priv, pipe);
1892 assert_sprites_disabled(dev_priv, pipe);
1893
1894 /*
1895 * A pipe without a PLL won't actually be able to drive bits from
1896 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1897 * need the check.
1898 */
1899 if (HAS_GMCH_DISPLAY(dev_priv)) {
1900 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901 assert_dsi_pll_enabled(dev_priv);
1902 else
1903 assert_pll_enabled(dev_priv, pipe);
1904 } else {
1905 if (crtc->config->has_pch_encoder) {
1906 /* if driving the PCH, we need FDI enabled */
1907 assert_fdi_rx_pll_enabled(dev_priv,
1908 (enum pipe) intel_crtc_pch_transcoder(crtc));
1909 assert_fdi_tx_pll_enabled(dev_priv,
1910 (enum pipe) cpu_transcoder);
1911 }
1912 /* FIXME: assert CPU port conditions for SNB+ */
1913 }
1914
1915 reg = PIPECONF(cpu_transcoder);
1916 val = I915_READ(reg);
1917 if (val & PIPECONF_ENABLE) {
1918 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920 return;
1921 }
1922
1923 I915_WRITE(reg, val | PIPECONF_ENABLE);
1924 POSTING_READ(reg);
1925
1926 /*
1927 * Until the pipe starts DSL will read as 0, which would cause
1928 * an apparent vblank timestamp jump, which messes up also the
1929 * frame count when it's derived from the timestamps. So let's
1930 * wait for the pipe to start properly before we call
1931 * drm_crtc_vblank_on()
1932 */
1933 if (dev->max_vblank_count == 0 &&
1934 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939 * intel_disable_pipe - disable a pipe, asserting requirements
1940 * @crtc: crtc whose pipes is to be disabled
1941 *
1942 * Disable the pipe of @crtc, making sure that various hardware
1943 * specific requirements are met, if applicable, e.g. plane
1944 * disabled, panel fitter off, etc.
1945 *
1946 * Will wait until the pipe has shut down before returning.
1947 */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952 enum pipe pipe = crtc->pipe;
1953 i915_reg_t reg;
1954 u32 val;
1955
1956 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958 /*
1959 * Make sure planes won't keep trying to pump pixels to us,
1960 * or we might hang the display.
1961 */
1962 assert_planes_disabled(dev_priv, pipe);
1963 assert_cursor_disabled(dev_priv, pipe);
1964 assert_sprites_disabled(dev_priv, pipe);
1965
1966 reg = PIPECONF(cpu_transcoder);
1967 val = I915_READ(reg);
1968 if ((val & PIPECONF_ENABLE) == 0)
1969 return;
1970
1971 /*
1972 * Double wide has implications for planes
1973 * so best keep it disabled when not needed.
1974 */
1975 if (crtc->config->double_wide)
1976 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978 /* Don't disable pipe or pipe PLLs if needed */
1979 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981 val &= ~PIPECONF_ENABLE;
1982
1983 I915_WRITE(reg, val);
1984 if ((val & PIPECONF_ENABLE) == 0)
1985 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990 return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
1994 uint64_t fb_modifier, unsigned int cpp)
1995 {
1996 switch (fb_modifier) {
1997 case DRM_FORMAT_MOD_NONE:
1998 return cpp;
1999 case I915_FORMAT_MOD_X_TILED:
2000 if (IS_GEN2(dev_priv))
2001 return 128;
2002 else
2003 return 512;
2004 case I915_FORMAT_MOD_Y_TILED:
2005 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2006 return 128;
2007 else
2008 return 512;
2009 case I915_FORMAT_MOD_Yf_TILED:
2010 switch (cpp) {
2011 case 1:
2012 return 64;
2013 case 2:
2014 case 4:
2015 return 128;
2016 case 8:
2017 case 16:
2018 return 256;
2019 default:
2020 MISSING_CASE(cpp);
2021 return cpp;
2022 }
2023 break;
2024 default:
2025 MISSING_CASE(fb_modifier);
2026 return cpp;
2027 }
2028 }
2029
2030 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2031 uint64_t fb_modifier, unsigned int cpp)
2032 {
2033 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2034 return 1;
2035 else
2036 return intel_tile_size(dev_priv) /
2037 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2038 }
2039
2040 /* Return the tile dimensions in pixel units */
2041 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2042 unsigned int *tile_width,
2043 unsigned int *tile_height,
2044 uint64_t fb_modifier,
2045 unsigned int cpp)
2046 {
2047 unsigned int tile_width_bytes =
2048 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2049
2050 *tile_width = tile_width_bytes / cpp;
2051 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2052 }
2053
2054 unsigned int
2055 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2056 uint32_t pixel_format, uint64_t fb_modifier)
2057 {
2058 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2059 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2060
2061 return ALIGN(height, tile_height);
2062 }
2063
2064 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2065 {
2066 unsigned int size = 0;
2067 int i;
2068
2069 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070 size += rot_info->plane[i].width * rot_info->plane[i].height;
2071
2072 return size;
2073 }
2074
2075 static void
2076 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077 const struct drm_framebuffer *fb,
2078 unsigned int rotation)
2079 {
2080 view->type = I915_GGTT_VIEW_NORMAL;
2081 if (drm_rotation_90_or_270(rotation)) {
2082 view->type = I915_GGTT_VIEW_ROTATED;
2083 view->rotated = to_intel_framebuffer(fb)->rot_info;
2084 }
2085 }
2086
2087 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2088 {
2089 if (INTEL_INFO(dev_priv)->gen >= 9)
2090 return 256 * 1024;
2091 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2092 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2093 return 128 * 1024;
2094 else if (INTEL_INFO(dev_priv)->gen >= 4)
2095 return 4 * 1024;
2096 else
2097 return 0;
2098 }
2099
2100 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2101 uint64_t fb_modifier)
2102 {
2103 switch (fb_modifier) {
2104 case DRM_FORMAT_MOD_NONE:
2105 return intel_linear_alignment(dev_priv);
2106 case I915_FORMAT_MOD_X_TILED:
2107 if (INTEL_INFO(dev_priv)->gen >= 9)
2108 return 256 * 1024;
2109 return 0;
2110 case I915_FORMAT_MOD_Y_TILED:
2111 case I915_FORMAT_MOD_Yf_TILED:
2112 return 1 * 1024 * 1024;
2113 default:
2114 MISSING_CASE(fb_modifier);
2115 return 0;
2116 }
2117 }
2118
2119 struct i915_vma *
2120 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2121 {
2122 struct drm_device *dev = fb->dev;
2123 struct drm_i915_private *dev_priv = to_i915(dev);
2124 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2125 struct i915_ggtt_view view;
2126 struct i915_vma *vma;
2127 u32 alignment;
2128
2129 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2130
2131 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2132
2133 intel_fill_fb_ggtt_view(&view, fb, rotation);
2134
2135 /* Note that the w/a also requires 64 PTE of padding following the
2136 * bo. We currently fill all unused PTE with the shadow page and so
2137 * we should always have valid PTE following the scanout preventing
2138 * the VT-d warning.
2139 */
2140 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2141 alignment = 256 * 1024;
2142
2143 /*
2144 * Global gtt pte registers are special registers which actually forward
2145 * writes to a chunk of system memory. Which means that there is no risk
2146 * that the register values disappear as soon as we call
2147 * intel_runtime_pm_put(), so it is correct to wrap only the
2148 * pin/unpin/fence and not more.
2149 */
2150 intel_runtime_pm_get(dev_priv);
2151
2152 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2153 if (IS_ERR(vma))
2154 goto err;
2155
2156 if (i915_vma_is_map_and_fenceable(vma)) {
2157 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2158 * fence, whereas 965+ only requires a fence if using
2159 * framebuffer compression. For simplicity, we always, when
2160 * possible, install a fence as the cost is not that onerous.
2161 *
2162 * If we fail to fence the tiled scanout, then either the
2163 * modeset will reject the change (which is highly unlikely as
2164 * the affected systems, all but one, do not have unmappable
2165 * space) or we will not be able to enable full powersaving
2166 * techniques (also likely not to apply due to various limits
2167 * FBC and the like impose on the size of the buffer, which
2168 * presumably we violated anyway with this unmappable buffer).
2169 * Anyway, it is presumably better to stumble onwards with
2170 * something and try to run the system in a "less than optimal"
2171 * mode that matches the user configuration.
2172 */
2173 if (i915_vma_get_fence(vma) == 0)
2174 i915_vma_pin_fence(vma);
2175 }
2176
2177 i915_vma_get(vma);
2178 err:
2179 intel_runtime_pm_put(dev_priv);
2180 return vma;
2181 }
2182
2183 void intel_unpin_fb_vma(struct i915_vma *vma)
2184 {
2185 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2186
2187 i915_vma_unpin_fence(vma);
2188 i915_gem_object_unpin_from_display_plane(vma);
2189 i915_vma_put(vma);
2190 }
2191
2192 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2193 unsigned int rotation)
2194 {
2195 if (drm_rotation_90_or_270(rotation))
2196 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2197 else
2198 return fb->pitches[plane];
2199 }
2200
2201 /*
2202 * Convert the x/y offsets into a linear offset.
2203 * Only valid with 0/180 degree rotation, which is fine since linear
2204 * offset is only used with linear buffers on pre-hsw and tiled buffers
2205 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2206 */
2207 u32 intel_fb_xy_to_linear(int x, int y,
2208 const struct intel_plane_state *state,
2209 int plane)
2210 {
2211 const struct drm_framebuffer *fb = state->base.fb;
2212 unsigned int cpp = fb->format->cpp[plane];
2213 unsigned int pitch = fb->pitches[plane];
2214
2215 return y * pitch + x * cpp;
2216 }
2217
2218 /*
2219 * Add the x/y offsets derived from fb->offsets[] to the user
2220 * specified plane src x/y offsets. The resulting x/y offsets
2221 * specify the start of scanout from the beginning of the gtt mapping.
2222 */
2223 void intel_add_fb_offsets(int *x, int *y,
2224 const struct intel_plane_state *state,
2225 int plane)
2226
2227 {
2228 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2229 unsigned int rotation = state->base.rotation;
2230
2231 if (drm_rotation_90_or_270(rotation)) {
2232 *x += intel_fb->rotated[plane].x;
2233 *y += intel_fb->rotated[plane].y;
2234 } else {
2235 *x += intel_fb->normal[plane].x;
2236 *y += intel_fb->normal[plane].y;
2237 }
2238 }
2239
2240 /*
2241 * Input tile dimensions and pitch must already be
2242 * rotated to match x and y, and in pixel units.
2243 */
2244 static u32 _intel_adjust_tile_offset(int *x, int *y,
2245 unsigned int tile_width,
2246 unsigned int tile_height,
2247 unsigned int tile_size,
2248 unsigned int pitch_tiles,
2249 u32 old_offset,
2250 u32 new_offset)
2251 {
2252 unsigned int pitch_pixels = pitch_tiles * tile_width;
2253 unsigned int tiles;
2254
2255 WARN_ON(old_offset & (tile_size - 1));
2256 WARN_ON(new_offset & (tile_size - 1));
2257 WARN_ON(new_offset > old_offset);
2258
2259 tiles = (old_offset - new_offset) / tile_size;
2260
2261 *y += tiles / pitch_tiles * tile_height;
2262 *x += tiles % pitch_tiles * tile_width;
2263
2264 /* minimize x in case it got needlessly big */
2265 *y += *x / pitch_pixels * tile_height;
2266 *x %= pitch_pixels;
2267
2268 return new_offset;
2269 }
2270
2271 /*
2272 * Adjust the tile offset by moving the difference into
2273 * the x/y offsets.
2274 */
2275 static u32 intel_adjust_tile_offset(int *x, int *y,
2276 const struct intel_plane_state *state, int plane,
2277 u32 old_offset, u32 new_offset)
2278 {
2279 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2280 const struct drm_framebuffer *fb = state->base.fb;
2281 unsigned int cpp = fb->format->cpp[plane];
2282 unsigned int rotation = state->base.rotation;
2283 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2284
2285 WARN_ON(new_offset > old_offset);
2286
2287 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2288 unsigned int tile_size, tile_width, tile_height;
2289 unsigned int pitch_tiles;
2290
2291 tile_size = intel_tile_size(dev_priv);
2292 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2293 fb->modifier, cpp);
2294
2295 if (drm_rotation_90_or_270(rotation)) {
2296 pitch_tiles = pitch / tile_height;
2297 swap(tile_width, tile_height);
2298 } else {
2299 pitch_tiles = pitch / (tile_width * cpp);
2300 }
2301
2302 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2303 tile_size, pitch_tiles,
2304 old_offset, new_offset);
2305 } else {
2306 old_offset += *y * pitch + *x * cpp;
2307
2308 *y = (old_offset - new_offset) / pitch;
2309 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2310 }
2311
2312 return new_offset;
2313 }
2314
2315 /*
2316 * Computes the linear offset to the base tile and adjusts
2317 * x, y. bytes per pixel is assumed to be a power-of-two.
2318 *
2319 * In the 90/270 rotated case, x and y are assumed
2320 * to be already rotated to match the rotated GTT view, and
2321 * pitch is the tile_height aligned framebuffer height.
2322 *
2323 * This function is used when computing the derived information
2324 * under intel_framebuffer, so using any of that information
2325 * here is not allowed. Anything under drm_framebuffer can be
2326 * used. This is why the user has to pass in the pitch since it
2327 * is specified in the rotated orientation.
2328 */
2329 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2330 int *x, int *y,
2331 const struct drm_framebuffer *fb, int plane,
2332 unsigned int pitch,
2333 unsigned int rotation,
2334 u32 alignment)
2335 {
2336 uint64_t fb_modifier = fb->modifier;
2337 unsigned int cpp = fb->format->cpp[plane];
2338 u32 offset, offset_aligned;
2339
2340 if (alignment)
2341 alignment--;
2342
2343 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2344 unsigned int tile_size, tile_width, tile_height;
2345 unsigned int tile_rows, tiles, pitch_tiles;
2346
2347 tile_size = intel_tile_size(dev_priv);
2348 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2349 fb_modifier, cpp);
2350
2351 if (drm_rotation_90_or_270(rotation)) {
2352 pitch_tiles = pitch / tile_height;
2353 swap(tile_width, tile_height);
2354 } else {
2355 pitch_tiles = pitch / (tile_width * cpp);
2356 }
2357
2358 tile_rows = *y / tile_height;
2359 *y %= tile_height;
2360
2361 tiles = *x / tile_width;
2362 *x %= tile_width;
2363
2364 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2365 offset_aligned = offset & ~alignment;
2366
2367 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2368 tile_size, pitch_tiles,
2369 offset, offset_aligned);
2370 } else {
2371 offset = *y * pitch + *x * cpp;
2372 offset_aligned = offset & ~alignment;
2373
2374 *y = (offset & alignment) / pitch;
2375 *x = ((offset & alignment) - *y * pitch) / cpp;
2376 }
2377
2378 return offset_aligned;
2379 }
2380
2381 u32 intel_compute_tile_offset(int *x, int *y,
2382 const struct intel_plane_state *state,
2383 int plane)
2384 {
2385 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2386 const struct drm_framebuffer *fb = state->base.fb;
2387 unsigned int rotation = state->base.rotation;
2388 int pitch = intel_fb_pitch(fb, plane, rotation);
2389 u32 alignment;
2390
2391 /* AUX_DIST needs only 4K alignment */
2392 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2393 alignment = 4096;
2394 else
2395 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2396
2397 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2398 rotation, alignment);
2399 }
2400
2401 /* Convert the fb->offset[] linear offset into x/y offsets */
2402 static void intel_fb_offset_to_xy(int *x, int *y,
2403 const struct drm_framebuffer *fb, int plane)
2404 {
2405 unsigned int cpp = fb->format->cpp[plane];
2406 unsigned int pitch = fb->pitches[plane];
2407 u32 linear_offset = fb->offsets[plane];
2408
2409 *y = linear_offset / pitch;
2410 *x = linear_offset % pitch / cpp;
2411 }
2412
2413 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2414 {
2415 switch (fb_modifier) {
2416 case I915_FORMAT_MOD_X_TILED:
2417 return I915_TILING_X;
2418 case I915_FORMAT_MOD_Y_TILED:
2419 return I915_TILING_Y;
2420 default:
2421 return I915_TILING_NONE;
2422 }
2423 }
2424
2425 static int
2426 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2427 struct drm_framebuffer *fb)
2428 {
2429 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2430 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2431 u32 gtt_offset_rotated = 0;
2432 unsigned int max_size = 0;
2433 int i, num_planes = fb->format->num_planes;
2434 unsigned int tile_size = intel_tile_size(dev_priv);
2435
2436 for (i = 0; i < num_planes; i++) {
2437 unsigned int width, height;
2438 unsigned int cpp, size;
2439 u32 offset;
2440 int x, y;
2441
2442 cpp = fb->format->cpp[i];
2443 width = drm_framebuffer_plane_width(fb->width, fb, i);
2444 height = drm_framebuffer_plane_height(fb->height, fb, i);
2445
2446 intel_fb_offset_to_xy(&x, &y, fb, i);
2447
2448 /*
2449 * The fence (if used) is aligned to the start of the object
2450 * so having the framebuffer wrap around across the edge of the
2451 * fenced region doesn't really work. We have no API to configure
2452 * the fence start offset within the object (nor could we probably
2453 * on gen2/3). So it's just easier if we just require that the
2454 * fb layout agrees with the fence layout. We already check that the
2455 * fb stride matches the fence stride elsewhere.
2456 */
2457 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2458 (x + width) * cpp > fb->pitches[i]) {
2459 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2460 i, fb->offsets[i]);
2461 return -EINVAL;
2462 }
2463
2464 /*
2465 * First pixel of the framebuffer from
2466 * the start of the normal gtt mapping.
2467 */
2468 intel_fb->normal[i].x = x;
2469 intel_fb->normal[i].y = y;
2470
2471 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2472 fb, 0, fb->pitches[i],
2473 DRM_ROTATE_0, tile_size);
2474 offset /= tile_size;
2475
2476 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2477 unsigned int tile_width, tile_height;
2478 unsigned int pitch_tiles;
2479 struct drm_rect r;
2480
2481 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2482 fb->modifier, cpp);
2483
2484 rot_info->plane[i].offset = offset;
2485 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2486 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2487 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2488
2489 intel_fb->rotated[i].pitch =
2490 rot_info->plane[i].height * tile_height;
2491
2492 /* how many tiles does this plane need */
2493 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2494 /*
2495 * If the plane isn't horizontally tile aligned,
2496 * we need one more tile.
2497 */
2498 if (x != 0)
2499 size++;
2500
2501 /* rotate the x/y offsets to match the GTT view */
2502 r.x1 = x;
2503 r.y1 = y;
2504 r.x2 = x + width;
2505 r.y2 = y + height;
2506 drm_rect_rotate(&r,
2507 rot_info->plane[i].width * tile_width,
2508 rot_info->plane[i].height * tile_height,
2509 DRM_ROTATE_270);
2510 x = r.x1;
2511 y = r.y1;
2512
2513 /* rotate the tile dimensions to match the GTT view */
2514 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2515 swap(tile_width, tile_height);
2516
2517 /*
2518 * We only keep the x/y offsets, so push all of the
2519 * gtt offset into the x/y offsets.
2520 */
2521 _intel_adjust_tile_offset(&x, &y,
2522 tile_width, tile_height,
2523 tile_size, pitch_tiles,
2524 gtt_offset_rotated * tile_size, 0);
2525
2526 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2527
2528 /*
2529 * First pixel of the framebuffer from
2530 * the start of the rotated gtt mapping.
2531 */
2532 intel_fb->rotated[i].x = x;
2533 intel_fb->rotated[i].y = y;
2534 } else {
2535 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2536 x * cpp, tile_size);
2537 }
2538
2539 /* how many tiles in total needed in the bo */
2540 max_size = max(max_size, offset + size);
2541 }
2542
2543 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2544 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2545 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2546 return -EINVAL;
2547 }
2548
2549 return 0;
2550 }
2551
2552 static int i9xx_format_to_fourcc(int format)
2553 {
2554 switch (format) {
2555 case DISPPLANE_8BPP:
2556 return DRM_FORMAT_C8;
2557 case DISPPLANE_BGRX555:
2558 return DRM_FORMAT_XRGB1555;
2559 case DISPPLANE_BGRX565:
2560 return DRM_FORMAT_RGB565;
2561 default:
2562 case DISPPLANE_BGRX888:
2563 return DRM_FORMAT_XRGB8888;
2564 case DISPPLANE_RGBX888:
2565 return DRM_FORMAT_XBGR8888;
2566 case DISPPLANE_BGRX101010:
2567 return DRM_FORMAT_XRGB2101010;
2568 case DISPPLANE_RGBX101010:
2569 return DRM_FORMAT_XBGR2101010;
2570 }
2571 }
2572
2573 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2574 {
2575 switch (format) {
2576 case PLANE_CTL_FORMAT_RGB_565:
2577 return DRM_FORMAT_RGB565;
2578 default:
2579 case PLANE_CTL_FORMAT_XRGB_8888:
2580 if (rgb_order) {
2581 if (alpha)
2582 return DRM_FORMAT_ABGR8888;
2583 else
2584 return DRM_FORMAT_XBGR8888;
2585 } else {
2586 if (alpha)
2587 return DRM_FORMAT_ARGB8888;
2588 else
2589 return DRM_FORMAT_XRGB8888;
2590 }
2591 case PLANE_CTL_FORMAT_XRGB_2101010:
2592 if (rgb_order)
2593 return DRM_FORMAT_XBGR2101010;
2594 else
2595 return DRM_FORMAT_XRGB2101010;
2596 }
2597 }
2598
2599 static bool
2600 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2601 struct intel_initial_plane_config *plane_config)
2602 {
2603 struct drm_device *dev = crtc->base.dev;
2604 struct drm_i915_private *dev_priv = to_i915(dev);
2605 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2606 struct drm_i915_gem_object *obj = NULL;
2607 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2608 struct drm_framebuffer *fb = &plane_config->fb->base;
2609 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2610 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2611 PAGE_SIZE);
2612
2613 size_aligned -= base_aligned;
2614
2615 if (plane_config->size == 0)
2616 return false;
2617
2618 /* If the FB is too big, just don't use it since fbdev is not very
2619 * important and we should probably use that space with FBC or other
2620 * features. */
2621 if (size_aligned * 2 > ggtt->stolen_usable_size)
2622 return false;
2623
2624 mutex_lock(&dev->struct_mutex);
2625
2626 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2627 base_aligned,
2628 base_aligned,
2629 size_aligned);
2630 if (!obj) {
2631 mutex_unlock(&dev->struct_mutex);
2632 return false;
2633 }
2634
2635 if (plane_config->tiling == I915_TILING_X)
2636 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2637
2638 mode_cmd.pixel_format = fb->format->format;
2639 mode_cmd.width = fb->width;
2640 mode_cmd.height = fb->height;
2641 mode_cmd.pitches[0] = fb->pitches[0];
2642 mode_cmd.modifier[0] = fb->modifier;
2643 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2644
2645 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2646 &mode_cmd, obj)) {
2647 DRM_DEBUG_KMS("intel fb init failed\n");
2648 goto out_unref_obj;
2649 }
2650
2651 mutex_unlock(&dev->struct_mutex);
2652
2653 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2654 return true;
2655
2656 out_unref_obj:
2657 i915_gem_object_put(obj);
2658 mutex_unlock(&dev->struct_mutex);
2659 return false;
2660 }
2661
2662 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2663 static void
2664 update_state_fb(struct drm_plane *plane)
2665 {
2666 if (plane->fb == plane->state->fb)
2667 return;
2668
2669 if (plane->state->fb)
2670 drm_framebuffer_unreference(plane->state->fb);
2671 plane->state->fb = plane->fb;
2672 if (plane->state->fb)
2673 drm_framebuffer_reference(plane->state->fb);
2674 }
2675
2676 static void
2677 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2678 struct intel_initial_plane_config *plane_config)
2679 {
2680 struct drm_device *dev = intel_crtc->base.dev;
2681 struct drm_i915_private *dev_priv = to_i915(dev);
2682 struct drm_crtc *c;
2683 struct drm_i915_gem_object *obj;
2684 struct drm_plane *primary = intel_crtc->base.primary;
2685 struct drm_plane_state *plane_state = primary->state;
2686 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2687 struct intel_plane *intel_plane = to_intel_plane(primary);
2688 struct intel_plane_state *intel_state =
2689 to_intel_plane_state(plane_state);
2690 struct drm_framebuffer *fb;
2691
2692 if (!plane_config->fb)
2693 return;
2694
2695 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2696 fb = &plane_config->fb->base;
2697 goto valid_fb;
2698 }
2699
2700 kfree(plane_config->fb);
2701
2702 /*
2703 * Failed to alloc the obj, check to see if we should share
2704 * an fb with another CRTC instead
2705 */
2706 for_each_crtc(dev, c) {
2707 struct intel_plane_state *state;
2708
2709 if (c == &intel_crtc->base)
2710 continue;
2711
2712 if (!to_intel_crtc(c)->active)
2713 continue;
2714
2715 state = to_intel_plane_state(c->primary->state);
2716 if (!state->vma)
2717 continue;
2718
2719 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2720 fb = c->primary->fb;
2721 drm_framebuffer_reference(fb);
2722 goto valid_fb;
2723 }
2724 }
2725
2726 /*
2727 * We've failed to reconstruct the BIOS FB. Current display state
2728 * indicates that the primary plane is visible, but has a NULL FB,
2729 * which will lead to problems later if we don't fix it up. The
2730 * simplest solution is to just disable the primary plane now and
2731 * pretend the BIOS never had it enabled.
2732 */
2733 plane_state->visible = false;
2734 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2735 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2736 intel_plane->disable_plane(primary, &intel_crtc->base);
2737
2738 return;
2739
2740 valid_fb:
2741 mutex_lock(&dev->struct_mutex);
2742 intel_state->vma =
2743 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2744 mutex_unlock(&dev->struct_mutex);
2745 if (IS_ERR(intel_state->vma)) {
2746 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2747 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2748
2749 intel_state->vma = NULL;
2750 drm_framebuffer_unreference(fb);
2751 return;
2752 }
2753
2754 plane_state->src_x = 0;
2755 plane_state->src_y = 0;
2756 plane_state->src_w = fb->width << 16;
2757 plane_state->src_h = fb->height << 16;
2758
2759 plane_state->crtc_x = 0;
2760 plane_state->crtc_y = 0;
2761 plane_state->crtc_w = fb->width;
2762 plane_state->crtc_h = fb->height;
2763
2764 intel_state->base.src = drm_plane_state_src(plane_state);
2765 intel_state->base.dst = drm_plane_state_dest(plane_state);
2766
2767 obj = intel_fb_obj(fb);
2768 if (i915_gem_object_is_tiled(obj))
2769 dev_priv->preserve_bios_swizzle = true;
2770
2771 drm_framebuffer_reference(fb);
2772 primary->fb = primary->state->fb = fb;
2773 primary->crtc = primary->state->crtc = &intel_crtc->base;
2774 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2775 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2776 &obj->frontbuffer_bits);
2777 }
2778
2779 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2780 unsigned int rotation)
2781 {
2782 int cpp = fb->format->cpp[plane];
2783
2784 switch (fb->modifier) {
2785 case DRM_FORMAT_MOD_NONE:
2786 case I915_FORMAT_MOD_X_TILED:
2787 switch (cpp) {
2788 case 8:
2789 return 4096;
2790 case 4:
2791 case 2:
2792 case 1:
2793 return 8192;
2794 default:
2795 MISSING_CASE(cpp);
2796 break;
2797 }
2798 break;
2799 case I915_FORMAT_MOD_Y_TILED:
2800 case I915_FORMAT_MOD_Yf_TILED:
2801 switch (cpp) {
2802 case 8:
2803 return 2048;
2804 case 4:
2805 return 4096;
2806 case 2:
2807 case 1:
2808 return 8192;
2809 default:
2810 MISSING_CASE(cpp);
2811 break;
2812 }
2813 break;
2814 default:
2815 MISSING_CASE(fb->modifier);
2816 }
2817
2818 return 2048;
2819 }
2820
2821 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2822 {
2823 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2824 const struct drm_framebuffer *fb = plane_state->base.fb;
2825 unsigned int rotation = plane_state->base.rotation;
2826 int x = plane_state->base.src.x1 >> 16;
2827 int y = plane_state->base.src.y1 >> 16;
2828 int w = drm_rect_width(&plane_state->base.src) >> 16;
2829 int h = drm_rect_height(&plane_state->base.src) >> 16;
2830 int max_width = skl_max_plane_width(fb, 0, rotation);
2831 int max_height = 4096;
2832 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2833
2834 if (w > max_width || h > max_height) {
2835 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2836 w, h, max_width, max_height);
2837 return -EINVAL;
2838 }
2839
2840 intel_add_fb_offsets(&x, &y, plane_state, 0);
2841 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2842
2843 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2844
2845 /*
2846 * AUX surface offset is specified as the distance from the
2847 * main surface offset, and it must be non-negative. Make
2848 * sure that is what we will get.
2849 */
2850 if (offset > aux_offset)
2851 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2852 offset, aux_offset & ~(alignment - 1));
2853
2854 /*
2855 * When using an X-tiled surface, the plane blows up
2856 * if the x offset + width exceed the stride.
2857 *
2858 * TODO: linear and Y-tiled seem fine, Yf untested,
2859 */
2860 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2861 int cpp = fb->format->cpp[0];
2862
2863 while ((x + w) * cpp > fb->pitches[0]) {
2864 if (offset == 0) {
2865 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2866 return -EINVAL;
2867 }
2868
2869 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2870 offset, offset - alignment);
2871 }
2872 }
2873
2874 plane_state->main.offset = offset;
2875 plane_state->main.x = x;
2876 plane_state->main.y = y;
2877
2878 return 0;
2879 }
2880
2881 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2882 {
2883 const struct drm_framebuffer *fb = plane_state->base.fb;
2884 unsigned int rotation = plane_state->base.rotation;
2885 int max_width = skl_max_plane_width(fb, 1, rotation);
2886 int max_height = 4096;
2887 int x = plane_state->base.src.x1 >> 17;
2888 int y = plane_state->base.src.y1 >> 17;
2889 int w = drm_rect_width(&plane_state->base.src) >> 17;
2890 int h = drm_rect_height(&plane_state->base.src) >> 17;
2891 u32 offset;
2892
2893 intel_add_fb_offsets(&x, &y, plane_state, 1);
2894 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2895
2896 /* FIXME not quite sure how/if these apply to the chroma plane */
2897 if (w > max_width || h > max_height) {
2898 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2899 w, h, max_width, max_height);
2900 return -EINVAL;
2901 }
2902
2903 plane_state->aux.offset = offset;
2904 plane_state->aux.x = x;
2905 plane_state->aux.y = y;
2906
2907 return 0;
2908 }
2909
2910 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2911 {
2912 const struct drm_framebuffer *fb = plane_state->base.fb;
2913 unsigned int rotation = plane_state->base.rotation;
2914 int ret;
2915
2916 if (!plane_state->base.visible)
2917 return 0;
2918
2919 /* Rotate src coordinates to match rotated GTT view */
2920 if (drm_rotation_90_or_270(rotation))
2921 drm_rect_rotate(&plane_state->base.src,
2922 fb->width << 16, fb->height << 16,
2923 DRM_ROTATE_270);
2924
2925 /*
2926 * Handle the AUX surface first since
2927 * the main surface setup depends on it.
2928 */
2929 if (fb->format->format == DRM_FORMAT_NV12) {
2930 ret = skl_check_nv12_aux_surface(plane_state);
2931 if (ret)
2932 return ret;
2933 } else {
2934 plane_state->aux.offset = ~0xfff;
2935 plane_state->aux.x = 0;
2936 plane_state->aux.y = 0;
2937 }
2938
2939 ret = skl_check_main_surface(plane_state);
2940 if (ret)
2941 return ret;
2942
2943 return 0;
2944 }
2945
2946 static void i9xx_update_primary_plane(struct drm_plane *primary,
2947 const struct intel_crtc_state *crtc_state,
2948 const struct intel_plane_state *plane_state)
2949 {
2950 struct drm_i915_private *dev_priv = to_i915(primary->dev);
2951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2952 struct drm_framebuffer *fb = plane_state->base.fb;
2953 int plane = intel_crtc->plane;
2954 u32 linear_offset;
2955 u32 dspcntr;
2956 i915_reg_t reg = DSPCNTR(plane);
2957 unsigned int rotation = plane_state->base.rotation;
2958 int x = plane_state->base.src.x1 >> 16;
2959 int y = plane_state->base.src.y1 >> 16;
2960
2961 dspcntr = DISPPLANE_GAMMA_ENABLE;
2962
2963 dspcntr |= DISPLAY_PLANE_ENABLE;
2964
2965 if (INTEL_GEN(dev_priv) < 4) {
2966 if (intel_crtc->pipe == PIPE_B)
2967 dspcntr |= DISPPLANE_SEL_PIPE_B;
2968
2969 /* pipesrc and dspsize control the size that is scaled from,
2970 * which should always be the user's requested size.
2971 */
2972 I915_WRITE(DSPSIZE(plane),
2973 ((crtc_state->pipe_src_h - 1) << 16) |
2974 (crtc_state->pipe_src_w - 1));
2975 I915_WRITE(DSPPOS(plane), 0);
2976 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
2977 I915_WRITE(PRIMSIZE(plane),
2978 ((crtc_state->pipe_src_h - 1) << 16) |
2979 (crtc_state->pipe_src_w - 1));
2980 I915_WRITE(PRIMPOS(plane), 0);
2981 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2982 }
2983
2984 switch (fb->format->format) {
2985 case DRM_FORMAT_C8:
2986 dspcntr |= DISPPLANE_8BPP;
2987 break;
2988 case DRM_FORMAT_XRGB1555:
2989 dspcntr |= DISPPLANE_BGRX555;
2990 break;
2991 case DRM_FORMAT_RGB565:
2992 dspcntr |= DISPPLANE_BGRX565;
2993 break;
2994 case DRM_FORMAT_XRGB8888:
2995 dspcntr |= DISPPLANE_BGRX888;
2996 break;
2997 case DRM_FORMAT_XBGR8888:
2998 dspcntr |= DISPPLANE_RGBX888;
2999 break;
3000 case DRM_FORMAT_XRGB2101010:
3001 dspcntr |= DISPPLANE_BGRX101010;
3002 break;
3003 case DRM_FORMAT_XBGR2101010:
3004 dspcntr |= DISPPLANE_RGBX101010;
3005 break;
3006 default:
3007 BUG();
3008 }
3009
3010 if (INTEL_GEN(dev_priv) >= 4 &&
3011 fb->modifier == I915_FORMAT_MOD_X_TILED)
3012 dspcntr |= DISPPLANE_TILED;
3013
3014 if (rotation & DRM_ROTATE_180)
3015 dspcntr |= DISPPLANE_ROTATE_180;
3016
3017 if (rotation & DRM_REFLECT_X)
3018 dspcntr |= DISPPLANE_MIRROR;
3019
3020 if (IS_G4X(dev_priv))
3021 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3022
3023 intel_add_fb_offsets(&x, &y, plane_state, 0);
3024
3025 if (INTEL_GEN(dev_priv) >= 4)
3026 intel_crtc->dspaddr_offset =
3027 intel_compute_tile_offset(&x, &y, plane_state, 0);
3028
3029 if (rotation & DRM_ROTATE_180) {
3030 x += crtc_state->pipe_src_w - 1;
3031 y += crtc_state->pipe_src_h - 1;
3032 } else if (rotation & DRM_REFLECT_X) {
3033 x += crtc_state->pipe_src_w - 1;
3034 }
3035
3036 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3037
3038 if (INTEL_GEN(dev_priv) < 4)
3039 intel_crtc->dspaddr_offset = linear_offset;
3040
3041 intel_crtc->adjusted_x = x;
3042 intel_crtc->adjusted_y = y;
3043
3044 I915_WRITE(reg, dspcntr);
3045
3046 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3047 if (INTEL_GEN(dev_priv) >= 4) {
3048 I915_WRITE(DSPSURF(plane),
3049 intel_plane_ggtt_offset(plane_state) +
3050 intel_crtc->dspaddr_offset);
3051 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3052 I915_WRITE(DSPLINOFF(plane), linear_offset);
3053 } else {
3054 I915_WRITE(DSPADDR(plane),
3055 intel_plane_ggtt_offset(plane_state) +
3056 intel_crtc->dspaddr_offset);
3057 }
3058 POSTING_READ(reg);
3059 }
3060
3061 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3062 struct drm_crtc *crtc)
3063 {
3064 struct drm_device *dev = crtc->dev;
3065 struct drm_i915_private *dev_priv = to_i915(dev);
3066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067 int plane = intel_crtc->plane;
3068
3069 I915_WRITE(DSPCNTR(plane), 0);
3070 if (INTEL_INFO(dev_priv)->gen >= 4)
3071 I915_WRITE(DSPSURF(plane), 0);
3072 else
3073 I915_WRITE(DSPADDR(plane), 0);
3074 POSTING_READ(DSPCNTR(plane));
3075 }
3076
3077 static void ironlake_update_primary_plane(struct drm_plane *primary,
3078 const struct intel_crtc_state *crtc_state,
3079 const struct intel_plane_state *plane_state)
3080 {
3081 struct drm_device *dev = primary->dev;
3082 struct drm_i915_private *dev_priv = to_i915(dev);
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3084 struct drm_framebuffer *fb = plane_state->base.fb;
3085 int plane = intel_crtc->plane;
3086 u32 linear_offset;
3087 u32 dspcntr;
3088 i915_reg_t reg = DSPCNTR(plane);
3089 unsigned int rotation = plane_state->base.rotation;
3090 int x = plane_state->base.src.x1 >> 16;
3091 int y = plane_state->base.src.y1 >> 16;
3092
3093 dspcntr = DISPPLANE_GAMMA_ENABLE;
3094 dspcntr |= DISPLAY_PLANE_ENABLE;
3095
3096 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3097 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3098
3099 switch (fb->format->format) {
3100 case DRM_FORMAT_C8:
3101 dspcntr |= DISPPLANE_8BPP;
3102 break;
3103 case DRM_FORMAT_RGB565:
3104 dspcntr |= DISPPLANE_BGRX565;
3105 break;
3106 case DRM_FORMAT_XRGB8888:
3107 dspcntr |= DISPPLANE_BGRX888;
3108 break;
3109 case DRM_FORMAT_XBGR8888:
3110 dspcntr |= DISPPLANE_RGBX888;
3111 break;
3112 case DRM_FORMAT_XRGB2101010:
3113 dspcntr |= DISPPLANE_BGRX101010;
3114 break;
3115 case DRM_FORMAT_XBGR2101010:
3116 dspcntr |= DISPPLANE_RGBX101010;
3117 break;
3118 default:
3119 BUG();
3120 }
3121
3122 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3123 dspcntr |= DISPPLANE_TILED;
3124
3125 if (rotation & DRM_ROTATE_180)
3126 dspcntr |= DISPPLANE_ROTATE_180;
3127
3128 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3129 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3130
3131 intel_add_fb_offsets(&x, &y, plane_state, 0);
3132
3133 intel_crtc->dspaddr_offset =
3134 intel_compute_tile_offset(&x, &y, plane_state, 0);
3135
3136 /* HSW+ does this automagically in hardware */
3137 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3138 rotation & DRM_ROTATE_180) {
3139 x += crtc_state->pipe_src_w - 1;
3140 y += crtc_state->pipe_src_h - 1;
3141 }
3142
3143 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3144
3145 intel_crtc->adjusted_x = x;
3146 intel_crtc->adjusted_y = y;
3147
3148 I915_WRITE(reg, dspcntr);
3149
3150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3151 I915_WRITE(DSPSURF(plane),
3152 intel_plane_ggtt_offset(plane_state) +
3153 intel_crtc->dspaddr_offset);
3154 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3155 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3156 } else {
3157 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3158 I915_WRITE(DSPLINOFF(plane), linear_offset);
3159 }
3160 POSTING_READ(reg);
3161 }
3162
3163 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3164 uint64_t fb_modifier, uint32_t pixel_format)
3165 {
3166 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3167 return 64;
3168 } else {
3169 int cpp = drm_format_plane_cpp(pixel_format, 0);
3170
3171 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3172 }
3173 }
3174
3175 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3176 {
3177 struct drm_device *dev = intel_crtc->base.dev;
3178 struct drm_i915_private *dev_priv = to_i915(dev);
3179
3180 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3181 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3182 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3183 }
3184
3185 /*
3186 * This function detaches (aka. unbinds) unused scalers in hardware
3187 */
3188 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3189 {
3190 struct intel_crtc_scaler_state *scaler_state;
3191 int i;
3192
3193 scaler_state = &intel_crtc->config->scaler_state;
3194
3195 /* loop through and disable scalers that aren't in use */
3196 for (i = 0; i < intel_crtc->num_scalers; i++) {
3197 if (!scaler_state->scalers[i].in_use)
3198 skl_detach_scaler(intel_crtc, i);
3199 }
3200 }
3201
3202 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3203 unsigned int rotation)
3204 {
3205 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3206 u32 stride = intel_fb_pitch(fb, plane, rotation);
3207
3208 /*
3209 * The stride is either expressed as a multiple of 64 bytes chunks for
3210 * linear buffers or in number of tiles for tiled buffers.
3211 */
3212 if (drm_rotation_90_or_270(rotation)) {
3213 int cpp = fb->format->cpp[plane];
3214
3215 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3216 } else {
3217 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3218 fb->format->format);
3219 }
3220
3221 return stride;
3222 }
3223
3224 u32 skl_plane_ctl_format(uint32_t pixel_format)
3225 {
3226 switch (pixel_format) {
3227 case DRM_FORMAT_C8:
3228 return PLANE_CTL_FORMAT_INDEXED;
3229 case DRM_FORMAT_RGB565:
3230 return PLANE_CTL_FORMAT_RGB_565;
3231 case DRM_FORMAT_XBGR8888:
3232 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3233 case DRM_FORMAT_XRGB8888:
3234 return PLANE_CTL_FORMAT_XRGB_8888;
3235 /*
3236 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3237 * to be already pre-multiplied. We need to add a knob (or a different
3238 * DRM_FORMAT) for user-space to configure that.
3239 */
3240 case DRM_FORMAT_ABGR8888:
3241 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3242 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3243 case DRM_FORMAT_ARGB8888:
3244 return PLANE_CTL_FORMAT_XRGB_8888 |
3245 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3246 case DRM_FORMAT_XRGB2101010:
3247 return PLANE_CTL_FORMAT_XRGB_2101010;
3248 case DRM_FORMAT_XBGR2101010:
3249 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3250 case DRM_FORMAT_YUYV:
3251 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3252 case DRM_FORMAT_YVYU:
3253 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3254 case DRM_FORMAT_UYVY:
3255 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3256 case DRM_FORMAT_VYUY:
3257 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3258 default:
3259 MISSING_CASE(pixel_format);
3260 }
3261
3262 return 0;
3263 }
3264
3265 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3266 {
3267 switch (fb_modifier) {
3268 case DRM_FORMAT_MOD_NONE:
3269 break;
3270 case I915_FORMAT_MOD_X_TILED:
3271 return PLANE_CTL_TILED_X;
3272 case I915_FORMAT_MOD_Y_TILED:
3273 return PLANE_CTL_TILED_Y;
3274 case I915_FORMAT_MOD_Yf_TILED:
3275 return PLANE_CTL_TILED_YF;
3276 default:
3277 MISSING_CASE(fb_modifier);
3278 }
3279
3280 return 0;
3281 }
3282
3283 u32 skl_plane_ctl_rotation(unsigned int rotation)
3284 {
3285 switch (rotation) {
3286 case DRM_ROTATE_0:
3287 break;
3288 /*
3289 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3290 * while i915 HW rotation is clockwise, thats why this swapping.
3291 */
3292 case DRM_ROTATE_90:
3293 return PLANE_CTL_ROTATE_270;
3294 case DRM_ROTATE_180:
3295 return PLANE_CTL_ROTATE_180;
3296 case DRM_ROTATE_270:
3297 return PLANE_CTL_ROTATE_90;
3298 default:
3299 MISSING_CASE(rotation);
3300 }
3301
3302 return 0;
3303 }
3304
3305 static void skylake_update_primary_plane(struct drm_plane *plane,
3306 const struct intel_crtc_state *crtc_state,
3307 const struct intel_plane_state *plane_state)
3308 {
3309 struct drm_device *dev = plane->dev;
3310 struct drm_i915_private *dev_priv = to_i915(dev);
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3312 struct drm_framebuffer *fb = plane_state->base.fb;
3313 enum plane_id plane_id = to_intel_plane(plane)->id;
3314 enum pipe pipe = to_intel_plane(plane)->pipe;
3315 u32 plane_ctl;
3316 unsigned int rotation = plane_state->base.rotation;
3317 u32 stride = skl_plane_stride(fb, 0, rotation);
3318 u32 surf_addr = plane_state->main.offset;
3319 int scaler_id = plane_state->scaler_id;
3320 int src_x = plane_state->main.x;
3321 int src_y = plane_state->main.y;
3322 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3323 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3324 int dst_x = plane_state->base.dst.x1;
3325 int dst_y = plane_state->base.dst.y1;
3326 int dst_w = drm_rect_width(&plane_state->base.dst);
3327 int dst_h = drm_rect_height(&plane_state->base.dst);
3328
3329 plane_ctl = PLANE_CTL_ENABLE;
3330
3331 if (IS_GEMINILAKE(dev_priv)) {
3332 I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
3333 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3334 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3335 } else {
3336 plane_ctl |=
3337 PLANE_CTL_PIPE_GAMMA_ENABLE |
3338 PLANE_CTL_PIPE_CSC_ENABLE |
3339 PLANE_CTL_PLANE_GAMMA_DISABLE;
3340 }
3341
3342 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3343 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3344 plane_ctl |= skl_plane_ctl_rotation(rotation);
3345
3346 /* Sizes are 0 based */
3347 src_w--;
3348 src_h--;
3349 dst_w--;
3350 dst_h--;
3351
3352 intel_crtc->dspaddr_offset = surf_addr;
3353
3354 intel_crtc->adjusted_x = src_x;
3355 intel_crtc->adjusted_y = src_y;
3356
3357 I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
3358 I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3359 I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
3360 I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3361
3362 if (scaler_id >= 0) {
3363 uint32_t ps_ctrl = 0;
3364
3365 WARN_ON(!dst_w || !dst_h);
3366 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3367 crtc_state->scaler_state.scalers[scaler_id].mode;
3368 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3369 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3370 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3371 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3372 I915_WRITE(PLANE_POS(pipe, plane_id), 0);
3373 } else {
3374 I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3375 }
3376
3377 I915_WRITE(PLANE_SURF(pipe, plane_id),
3378 intel_plane_ggtt_offset(plane_state) + surf_addr);
3379
3380 POSTING_READ(PLANE_SURF(pipe, plane_id));
3381 }
3382
3383 static void skylake_disable_primary_plane(struct drm_plane *primary,
3384 struct drm_crtc *crtc)
3385 {
3386 struct drm_device *dev = crtc->dev;
3387 struct drm_i915_private *dev_priv = to_i915(dev);
3388 enum plane_id plane_id = to_intel_plane(primary)->id;
3389 enum pipe pipe = to_intel_plane(primary)->pipe;
3390
3391 I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
3392 I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
3393 POSTING_READ(PLANE_SURF(pipe, plane_id));
3394 }
3395
3396 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3397 static int
3398 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3399 int x, int y, enum mode_set_atomic state)
3400 {
3401 /* Support for kgdboc is disabled, this needs a major rework. */
3402 DRM_ERROR("legacy panic handler not supported any more.\n");
3403
3404 return -ENODEV;
3405 }
3406
3407 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3408 {
3409 struct intel_crtc *crtc;
3410
3411 for_each_intel_crtc(&dev_priv->drm, crtc)
3412 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3413 }
3414
3415 static void intel_update_primary_planes(struct drm_device *dev)
3416 {
3417 struct drm_crtc *crtc;
3418
3419 for_each_crtc(dev, crtc) {
3420 struct intel_plane *plane = to_intel_plane(crtc->primary);
3421 struct intel_plane_state *plane_state =
3422 to_intel_plane_state(plane->base.state);
3423
3424 if (plane_state->base.visible)
3425 plane->update_plane(&plane->base,
3426 to_intel_crtc_state(crtc->state),
3427 plane_state);
3428 }
3429 }
3430
3431 static int
3432 __intel_display_resume(struct drm_device *dev,
3433 struct drm_atomic_state *state)
3434 {
3435 struct drm_crtc_state *crtc_state;
3436 struct drm_crtc *crtc;
3437 int i, ret;
3438
3439 intel_modeset_setup_hw_state(dev);
3440 i915_redisable_vga(to_i915(dev));
3441
3442 if (!state)
3443 return 0;
3444
3445 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3446 /*
3447 * Force recalculation even if we restore
3448 * current state. With fast modeset this may not result
3449 * in a modeset when the state is compatible.
3450 */
3451 crtc_state->mode_changed = true;
3452 }
3453
3454 /* ignore any reset values/BIOS leftovers in the WM registers */
3455 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3456
3457 ret = drm_atomic_commit(state);
3458
3459 WARN_ON(ret == -EDEADLK);
3460 return ret;
3461 }
3462
3463 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3464 {
3465 return intel_has_gpu_reset(dev_priv) &&
3466 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3467 }
3468
3469 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3470 {
3471 struct drm_device *dev = &dev_priv->drm;
3472 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3473 struct drm_atomic_state *state;
3474 int ret;
3475
3476 /*
3477 * Need mode_config.mutex so that we don't
3478 * trample ongoing ->detect() and whatnot.
3479 */
3480 mutex_lock(&dev->mode_config.mutex);
3481 drm_modeset_acquire_init(ctx, 0);
3482 while (1) {
3483 ret = drm_modeset_lock_all_ctx(dev, ctx);
3484 if (ret != -EDEADLK)
3485 break;
3486
3487 drm_modeset_backoff(ctx);
3488 }
3489
3490 /* reset doesn't touch the display, but flips might get nuked anyway, */
3491 if (!i915.force_reset_modeset_test &&
3492 !gpu_reset_clobbers_display(dev_priv))
3493 return;
3494
3495 /*
3496 * Disabling the crtcs gracefully seems nicer. Also the
3497 * g33 docs say we should at least disable all the planes.
3498 */
3499 state = drm_atomic_helper_duplicate_state(dev, ctx);
3500 if (IS_ERR(state)) {
3501 ret = PTR_ERR(state);
3502 DRM_ERROR("Duplicating state failed with %i\n", ret);
3503 return;
3504 }
3505
3506 ret = drm_atomic_helper_disable_all(dev, ctx);
3507 if (ret) {
3508 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3509 drm_atomic_state_put(state);
3510 return;
3511 }
3512
3513 dev_priv->modeset_restore_state = state;
3514 state->acquire_ctx = ctx;
3515 }
3516
3517 void intel_finish_reset(struct drm_i915_private *dev_priv)
3518 {
3519 struct drm_device *dev = &dev_priv->drm;
3520 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3521 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3522 int ret;
3523
3524 /*
3525 * Flips in the rings will be nuked by the reset,
3526 * so complete all pending flips so that user space
3527 * will get its events and not get stuck.
3528 */
3529 intel_complete_page_flips(dev_priv);
3530
3531 dev_priv->modeset_restore_state = NULL;
3532
3533 /* reset doesn't touch the display */
3534 if (!gpu_reset_clobbers_display(dev_priv)) {
3535 if (!state) {
3536 /*
3537 * Flips in the rings have been nuked by the reset,
3538 * so update the base address of all primary
3539 * planes to the the last fb to make sure we're
3540 * showing the correct fb after a reset.
3541 *
3542 * FIXME: Atomic will make this obsolete since we won't schedule
3543 * CS-based flips (which might get lost in gpu resets) any more.
3544 */
3545 intel_update_primary_planes(dev);
3546 } else {
3547 ret = __intel_display_resume(dev, state);
3548 if (ret)
3549 DRM_ERROR("Restoring old state failed with %i\n", ret);
3550 }
3551 } else {
3552 /*
3553 * The display has been reset as well,
3554 * so need a full re-initialization.
3555 */
3556 intel_runtime_pm_disable_interrupts(dev_priv);
3557 intel_runtime_pm_enable_interrupts(dev_priv);
3558
3559 intel_pps_unlock_regs_wa(dev_priv);
3560 intel_modeset_init_hw(dev);
3561
3562 spin_lock_irq(&dev_priv->irq_lock);
3563 if (dev_priv->display.hpd_irq_setup)
3564 dev_priv->display.hpd_irq_setup(dev_priv);
3565 spin_unlock_irq(&dev_priv->irq_lock);
3566
3567 ret = __intel_display_resume(dev, state);
3568 if (ret)
3569 DRM_ERROR("Restoring old state failed with %i\n", ret);
3570
3571 intel_hpd_init(dev_priv);
3572 }
3573
3574 if (state)
3575 drm_atomic_state_put(state);
3576 drm_modeset_drop_locks(ctx);
3577 drm_modeset_acquire_fini(ctx);
3578 mutex_unlock(&dev->mode_config.mutex);
3579 }
3580
3581 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3582 {
3583 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3584
3585 if (i915_reset_in_progress(error))
3586 return true;
3587
3588 if (crtc->reset_count != i915_reset_count(error))
3589 return true;
3590
3591 return false;
3592 }
3593
3594 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3595 {
3596 struct drm_device *dev = crtc->dev;
3597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3598 bool pending;
3599
3600 if (abort_flip_on_reset(intel_crtc))
3601 return false;
3602
3603 spin_lock_irq(&dev->event_lock);
3604 pending = to_intel_crtc(crtc)->flip_work != NULL;
3605 spin_unlock_irq(&dev->event_lock);
3606
3607 return pending;
3608 }
3609
3610 static void intel_update_pipe_config(struct intel_crtc *crtc,
3611 struct intel_crtc_state *old_crtc_state)
3612 {
3613 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3614 struct intel_crtc_state *pipe_config =
3615 to_intel_crtc_state(crtc->base.state);
3616
3617 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3618 crtc->base.mode = crtc->base.state->mode;
3619
3620 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3621 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3622 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3623
3624 /*
3625 * Update pipe size and adjust fitter if needed: the reason for this is
3626 * that in compute_mode_changes we check the native mode (not the pfit
3627 * mode) to see if we can flip rather than do a full mode set. In the
3628 * fastboot case, we'll flip, but if we don't update the pipesrc and
3629 * pfit state, we'll end up with a big fb scanned out into the wrong
3630 * sized surface.
3631 */
3632
3633 I915_WRITE(PIPESRC(crtc->pipe),
3634 ((pipe_config->pipe_src_w - 1) << 16) |
3635 (pipe_config->pipe_src_h - 1));
3636
3637 /* on skylake this is done by detaching scalers */
3638 if (INTEL_GEN(dev_priv) >= 9) {
3639 skl_detach_scalers(crtc);
3640
3641 if (pipe_config->pch_pfit.enabled)
3642 skylake_pfit_enable(crtc);
3643 } else if (HAS_PCH_SPLIT(dev_priv)) {
3644 if (pipe_config->pch_pfit.enabled)
3645 ironlake_pfit_enable(crtc);
3646 else if (old_crtc_state->pch_pfit.enabled)
3647 ironlake_pfit_disable(crtc, true);
3648 }
3649 }
3650
3651 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3652 {
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_private *dev_priv = to_i915(dev);
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 int pipe = intel_crtc->pipe;
3657 i915_reg_t reg;
3658 u32 temp;
3659
3660 /* enable normal train */
3661 reg = FDI_TX_CTL(pipe);
3662 temp = I915_READ(reg);
3663 if (IS_IVYBRIDGE(dev_priv)) {
3664 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3665 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3666 } else {
3667 temp &= ~FDI_LINK_TRAIN_NONE;
3668 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3669 }
3670 I915_WRITE(reg, temp);
3671
3672 reg = FDI_RX_CTL(pipe);
3673 temp = I915_READ(reg);
3674 if (HAS_PCH_CPT(dev_priv)) {
3675 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3676 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3677 } else {
3678 temp &= ~FDI_LINK_TRAIN_NONE;
3679 temp |= FDI_LINK_TRAIN_NONE;
3680 }
3681 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3682
3683 /* wait one idle pattern time */
3684 POSTING_READ(reg);
3685 udelay(1000);
3686
3687 /* IVB wants error correction enabled */
3688 if (IS_IVYBRIDGE(dev_priv))
3689 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3690 FDI_FE_ERRC_ENABLE);
3691 }
3692
3693 /* The FDI link training functions for ILK/Ibexpeak. */
3694 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3695 {
3696 struct drm_device *dev = crtc->dev;
3697 struct drm_i915_private *dev_priv = to_i915(dev);
3698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3699 int pipe = intel_crtc->pipe;
3700 i915_reg_t reg;
3701 u32 temp, tries;
3702
3703 /* FDI needs bits from pipe first */
3704 assert_pipe_enabled(dev_priv, pipe);
3705
3706 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3707 for train result */
3708 reg = FDI_RX_IMR(pipe);
3709 temp = I915_READ(reg);
3710 temp &= ~FDI_RX_SYMBOL_LOCK;
3711 temp &= ~FDI_RX_BIT_LOCK;
3712 I915_WRITE(reg, temp);
3713 I915_READ(reg);
3714 udelay(150);
3715
3716 /* enable CPU FDI TX and PCH FDI RX */
3717 reg = FDI_TX_CTL(pipe);
3718 temp = I915_READ(reg);
3719 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3720 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3721 temp &= ~FDI_LINK_TRAIN_NONE;
3722 temp |= FDI_LINK_TRAIN_PATTERN_1;
3723 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3724
3725 reg = FDI_RX_CTL(pipe);
3726 temp = I915_READ(reg);
3727 temp &= ~FDI_LINK_TRAIN_NONE;
3728 temp |= FDI_LINK_TRAIN_PATTERN_1;
3729 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3730
3731 POSTING_READ(reg);
3732 udelay(150);
3733
3734 /* Ironlake workaround, enable clock pointer after FDI enable*/
3735 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3736 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3737 FDI_RX_PHASE_SYNC_POINTER_EN);
3738
3739 reg = FDI_RX_IIR(pipe);
3740 for (tries = 0; tries < 5; tries++) {
3741 temp = I915_READ(reg);
3742 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3743
3744 if ((temp & FDI_RX_BIT_LOCK)) {
3745 DRM_DEBUG_KMS("FDI train 1 done.\n");
3746 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3747 break;
3748 }
3749 }
3750 if (tries == 5)
3751 DRM_ERROR("FDI train 1 fail!\n");
3752
3753 /* Train 2 */
3754 reg = FDI_TX_CTL(pipe);
3755 temp = I915_READ(reg);
3756 temp &= ~FDI_LINK_TRAIN_NONE;
3757 temp |= FDI_LINK_TRAIN_PATTERN_2;
3758 I915_WRITE(reg, temp);
3759
3760 reg = FDI_RX_CTL(pipe);
3761 temp = I915_READ(reg);
3762 temp &= ~FDI_LINK_TRAIN_NONE;
3763 temp |= FDI_LINK_TRAIN_PATTERN_2;
3764 I915_WRITE(reg, temp);
3765
3766 POSTING_READ(reg);
3767 udelay(150);
3768
3769 reg = FDI_RX_IIR(pipe);
3770 for (tries = 0; tries < 5; tries++) {
3771 temp = I915_READ(reg);
3772 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3773
3774 if (temp & FDI_RX_SYMBOL_LOCK) {
3775 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3776 DRM_DEBUG_KMS("FDI train 2 done.\n");
3777 break;
3778 }
3779 }
3780 if (tries == 5)
3781 DRM_ERROR("FDI train 2 fail!\n");
3782
3783 DRM_DEBUG_KMS("FDI train done\n");
3784
3785 }
3786
3787 static const int snb_b_fdi_train_param[] = {
3788 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3789 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3790 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3791 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3792 };
3793
3794 /* The FDI link training functions for SNB/Cougarpoint. */
3795 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3796 {
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = to_i915(dev);
3799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3800 int pipe = intel_crtc->pipe;
3801 i915_reg_t reg;
3802 u32 temp, i, retry;
3803
3804 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3805 for train result */
3806 reg = FDI_RX_IMR(pipe);
3807 temp = I915_READ(reg);
3808 temp &= ~FDI_RX_SYMBOL_LOCK;
3809 temp &= ~FDI_RX_BIT_LOCK;
3810 I915_WRITE(reg, temp);
3811
3812 POSTING_READ(reg);
3813 udelay(150);
3814
3815 /* enable CPU FDI TX and PCH FDI RX */
3816 reg = FDI_TX_CTL(pipe);
3817 temp = I915_READ(reg);
3818 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3819 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3820 temp &= ~FDI_LINK_TRAIN_NONE;
3821 temp |= FDI_LINK_TRAIN_PATTERN_1;
3822 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3823 /* SNB-B */
3824 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3825 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3826
3827 I915_WRITE(FDI_RX_MISC(pipe),
3828 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3829
3830 reg = FDI_RX_CTL(pipe);
3831 temp = I915_READ(reg);
3832 if (HAS_PCH_CPT(dev_priv)) {
3833 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3834 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3835 } else {
3836 temp &= ~FDI_LINK_TRAIN_NONE;
3837 temp |= FDI_LINK_TRAIN_PATTERN_1;
3838 }
3839 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3840
3841 POSTING_READ(reg);
3842 udelay(150);
3843
3844 for (i = 0; i < 4; i++) {
3845 reg = FDI_TX_CTL(pipe);
3846 temp = I915_READ(reg);
3847 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3848 temp |= snb_b_fdi_train_param[i];
3849 I915_WRITE(reg, temp);
3850
3851 POSTING_READ(reg);
3852 udelay(500);
3853
3854 for (retry = 0; retry < 5; retry++) {
3855 reg = FDI_RX_IIR(pipe);
3856 temp = I915_READ(reg);
3857 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3858 if (temp & FDI_RX_BIT_LOCK) {
3859 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3860 DRM_DEBUG_KMS("FDI train 1 done.\n");
3861 break;
3862 }
3863 udelay(50);
3864 }
3865 if (retry < 5)
3866 break;
3867 }
3868 if (i == 4)
3869 DRM_ERROR("FDI train 1 fail!\n");
3870
3871 /* Train 2 */
3872 reg = FDI_TX_CTL(pipe);
3873 temp = I915_READ(reg);
3874 temp &= ~FDI_LINK_TRAIN_NONE;
3875 temp |= FDI_LINK_TRAIN_PATTERN_2;
3876 if (IS_GEN6(dev_priv)) {
3877 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3878 /* SNB-B */
3879 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3880 }
3881 I915_WRITE(reg, temp);
3882
3883 reg = FDI_RX_CTL(pipe);
3884 temp = I915_READ(reg);
3885 if (HAS_PCH_CPT(dev_priv)) {
3886 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3887 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3888 } else {
3889 temp &= ~FDI_LINK_TRAIN_NONE;
3890 temp |= FDI_LINK_TRAIN_PATTERN_2;
3891 }
3892 I915_WRITE(reg, temp);
3893
3894 POSTING_READ(reg);
3895 udelay(150);
3896
3897 for (i = 0; i < 4; i++) {
3898 reg = FDI_TX_CTL(pipe);
3899 temp = I915_READ(reg);
3900 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3901 temp |= snb_b_fdi_train_param[i];
3902 I915_WRITE(reg, temp);
3903
3904 POSTING_READ(reg);
3905 udelay(500);
3906
3907 for (retry = 0; retry < 5; retry++) {
3908 reg = FDI_RX_IIR(pipe);
3909 temp = I915_READ(reg);
3910 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3911 if (temp & FDI_RX_SYMBOL_LOCK) {
3912 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3913 DRM_DEBUG_KMS("FDI train 2 done.\n");
3914 break;
3915 }
3916 udelay(50);
3917 }
3918 if (retry < 5)
3919 break;
3920 }
3921 if (i == 4)
3922 DRM_ERROR("FDI train 2 fail!\n");
3923
3924 DRM_DEBUG_KMS("FDI train done.\n");
3925 }
3926
3927 /* Manual link training for Ivy Bridge A0 parts */
3928 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3929 {
3930 struct drm_device *dev = crtc->dev;
3931 struct drm_i915_private *dev_priv = to_i915(dev);
3932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3933 int pipe = intel_crtc->pipe;
3934 i915_reg_t reg;
3935 u32 temp, i, j;
3936
3937 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3938 for train result */
3939 reg = FDI_RX_IMR(pipe);
3940 temp = I915_READ(reg);
3941 temp &= ~FDI_RX_SYMBOL_LOCK;
3942 temp &= ~FDI_RX_BIT_LOCK;
3943 I915_WRITE(reg, temp);
3944
3945 POSTING_READ(reg);
3946 udelay(150);
3947
3948 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3949 I915_READ(FDI_RX_IIR(pipe)));
3950
3951 /* Try each vswing and preemphasis setting twice before moving on */
3952 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3953 /* disable first in case we need to retry */
3954 reg = FDI_TX_CTL(pipe);
3955 temp = I915_READ(reg);
3956 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3957 temp &= ~FDI_TX_ENABLE;
3958 I915_WRITE(reg, temp);
3959
3960 reg = FDI_RX_CTL(pipe);
3961 temp = I915_READ(reg);
3962 temp &= ~FDI_LINK_TRAIN_AUTO;
3963 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3964 temp &= ~FDI_RX_ENABLE;
3965 I915_WRITE(reg, temp);
3966
3967 /* enable CPU FDI TX and PCH FDI RX */
3968 reg = FDI_TX_CTL(pipe);
3969 temp = I915_READ(reg);
3970 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3971 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3972 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3973 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3974 temp |= snb_b_fdi_train_param[j/2];
3975 temp |= FDI_COMPOSITE_SYNC;
3976 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3977
3978 I915_WRITE(FDI_RX_MISC(pipe),
3979 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3980
3981 reg = FDI_RX_CTL(pipe);
3982 temp = I915_READ(reg);
3983 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3984 temp |= FDI_COMPOSITE_SYNC;
3985 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3986
3987 POSTING_READ(reg);
3988 udelay(1); /* should be 0.5us */
3989
3990 for (i = 0; i < 4; i++) {
3991 reg = FDI_RX_IIR(pipe);
3992 temp = I915_READ(reg);
3993 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3994
3995 if (temp & FDI_RX_BIT_LOCK ||
3996 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3997 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3998 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3999 i);
4000 break;
4001 }
4002 udelay(1); /* should be 0.5us */
4003 }
4004 if (i == 4) {
4005 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4006 continue;
4007 }
4008
4009 /* Train 2 */
4010 reg = FDI_TX_CTL(pipe);
4011 temp = I915_READ(reg);
4012 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4013 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4014 I915_WRITE(reg, temp);
4015
4016 reg = FDI_RX_CTL(pipe);
4017 temp = I915_READ(reg);
4018 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4019 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4020 I915_WRITE(reg, temp);
4021
4022 POSTING_READ(reg);
4023 udelay(2); /* should be 1.5us */
4024
4025 for (i = 0; i < 4; i++) {
4026 reg = FDI_RX_IIR(pipe);
4027 temp = I915_READ(reg);
4028 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4029
4030 if (temp & FDI_RX_SYMBOL_LOCK ||
4031 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4032 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4033 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4034 i);
4035 goto train_done;
4036 }
4037 udelay(2); /* should be 1.5us */
4038 }
4039 if (i == 4)
4040 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4041 }
4042
4043 train_done:
4044 DRM_DEBUG_KMS("FDI train done.\n");
4045 }
4046
4047 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4048 {
4049 struct drm_device *dev = intel_crtc->base.dev;
4050 struct drm_i915_private *dev_priv = to_i915(dev);
4051 int pipe = intel_crtc->pipe;
4052 i915_reg_t reg;
4053 u32 temp;
4054
4055 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4056 reg = FDI_RX_CTL(pipe);
4057 temp = I915_READ(reg);
4058 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4059 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4060 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4061 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4062
4063 POSTING_READ(reg);
4064 udelay(200);
4065
4066 /* Switch from Rawclk to PCDclk */
4067 temp = I915_READ(reg);
4068 I915_WRITE(reg, temp | FDI_PCDCLK);
4069
4070 POSTING_READ(reg);
4071 udelay(200);
4072
4073 /* Enable CPU FDI TX PLL, always on for Ironlake */
4074 reg = FDI_TX_CTL(pipe);
4075 temp = I915_READ(reg);
4076 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4077 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4078
4079 POSTING_READ(reg);
4080 udelay(100);
4081 }
4082 }
4083
4084 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4085 {
4086 struct drm_device *dev = intel_crtc->base.dev;
4087 struct drm_i915_private *dev_priv = to_i915(dev);
4088 int pipe = intel_crtc->pipe;
4089 i915_reg_t reg;
4090 u32 temp;
4091
4092 /* Switch from PCDclk to Rawclk */
4093 reg = FDI_RX_CTL(pipe);
4094 temp = I915_READ(reg);
4095 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4096
4097 /* Disable CPU FDI TX PLL */
4098 reg = FDI_TX_CTL(pipe);
4099 temp = I915_READ(reg);
4100 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4101
4102 POSTING_READ(reg);
4103 udelay(100);
4104
4105 reg = FDI_RX_CTL(pipe);
4106 temp = I915_READ(reg);
4107 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4108
4109 /* Wait for the clocks to turn off. */
4110 POSTING_READ(reg);
4111 udelay(100);
4112 }
4113
4114 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4115 {
4116 struct drm_device *dev = crtc->dev;
4117 struct drm_i915_private *dev_priv = to_i915(dev);
4118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119 int pipe = intel_crtc->pipe;
4120 i915_reg_t reg;
4121 u32 temp;
4122
4123 /* disable CPU FDI tx and PCH FDI rx */
4124 reg = FDI_TX_CTL(pipe);
4125 temp = I915_READ(reg);
4126 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4127 POSTING_READ(reg);
4128
4129 reg = FDI_RX_CTL(pipe);
4130 temp = I915_READ(reg);
4131 temp &= ~(0x7 << 16);
4132 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4133 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4134
4135 POSTING_READ(reg);
4136 udelay(100);
4137
4138 /* Ironlake workaround, disable clock pointer after downing FDI */
4139 if (HAS_PCH_IBX(dev_priv))
4140 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4141
4142 /* still set train pattern 1 */
4143 reg = FDI_TX_CTL(pipe);
4144 temp = I915_READ(reg);
4145 temp &= ~FDI_LINK_TRAIN_NONE;
4146 temp |= FDI_LINK_TRAIN_PATTERN_1;
4147 I915_WRITE(reg, temp);
4148
4149 reg = FDI_RX_CTL(pipe);
4150 temp = I915_READ(reg);
4151 if (HAS_PCH_CPT(dev_priv)) {
4152 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4153 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4154 } else {
4155 temp &= ~FDI_LINK_TRAIN_NONE;
4156 temp |= FDI_LINK_TRAIN_PATTERN_1;
4157 }
4158 /* BPC in FDI rx is consistent with that in PIPECONF */
4159 temp &= ~(0x07 << 16);
4160 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4161 I915_WRITE(reg, temp);
4162
4163 POSTING_READ(reg);
4164 udelay(100);
4165 }
4166
4167 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4168 {
4169 struct intel_crtc *crtc;
4170
4171 /* Note that we don't need to be called with mode_config.lock here
4172 * as our list of CRTC objects is static for the lifetime of the
4173 * device and so cannot disappear as we iterate. Similarly, we can
4174 * happily treat the predicates as racy, atomic checks as userspace
4175 * cannot claim and pin a new fb without at least acquring the
4176 * struct_mutex and so serialising with us.
4177 */
4178 for_each_intel_crtc(&dev_priv->drm, crtc) {
4179 if (atomic_read(&crtc->unpin_work_count) == 0)
4180 continue;
4181
4182 if (crtc->flip_work)
4183 intel_wait_for_vblank(dev_priv, crtc->pipe);
4184
4185 return true;
4186 }
4187
4188 return false;
4189 }
4190
4191 static void page_flip_completed(struct intel_crtc *intel_crtc)
4192 {
4193 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4194 struct intel_flip_work *work = intel_crtc->flip_work;
4195
4196 intel_crtc->flip_work = NULL;
4197
4198 if (work->event)
4199 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4200
4201 drm_crtc_vblank_put(&intel_crtc->base);
4202
4203 wake_up_all(&dev_priv->pending_flip_queue);
4204 trace_i915_flip_complete(intel_crtc->plane,
4205 work->pending_flip_obj);
4206
4207 queue_work(dev_priv->wq, &work->unpin_work);
4208 }
4209
4210 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4211 {
4212 struct drm_device *dev = crtc->dev;
4213 struct drm_i915_private *dev_priv = to_i915(dev);
4214 long ret;
4215
4216 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4217
4218 ret = wait_event_interruptible_timeout(
4219 dev_priv->pending_flip_queue,
4220 !intel_crtc_has_pending_flip(crtc),
4221 60*HZ);
4222
4223 if (ret < 0)
4224 return ret;
4225
4226 if (ret == 0) {
4227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4228 struct intel_flip_work *work;
4229
4230 spin_lock_irq(&dev->event_lock);
4231 work = intel_crtc->flip_work;
4232 if (work && !is_mmio_work(work)) {
4233 WARN_ONCE(1, "Removing stuck page flip\n");
4234 page_flip_completed(intel_crtc);
4235 }
4236 spin_unlock_irq(&dev->event_lock);
4237 }
4238
4239 return 0;
4240 }
4241
4242 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4243 {
4244 u32 temp;
4245
4246 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4247
4248 mutex_lock(&dev_priv->sb_lock);
4249
4250 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4251 temp |= SBI_SSCCTL_DISABLE;
4252 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4253
4254 mutex_unlock(&dev_priv->sb_lock);
4255 }
4256
4257 /* Program iCLKIP clock to the desired frequency */
4258 static void lpt_program_iclkip(struct drm_crtc *crtc)
4259 {
4260 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4261 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4262 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4263 u32 temp;
4264
4265 lpt_disable_iclkip(dev_priv);
4266
4267 /* The iCLK virtual clock root frequency is in MHz,
4268 * but the adjusted_mode->crtc_clock in in KHz. To get the
4269 * divisors, it is necessary to divide one by another, so we
4270 * convert the virtual clock precision to KHz here for higher
4271 * precision.
4272 */
4273 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4274 u32 iclk_virtual_root_freq = 172800 * 1000;
4275 u32 iclk_pi_range = 64;
4276 u32 desired_divisor;
4277
4278 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4279 clock << auxdiv);
4280 divsel = (desired_divisor / iclk_pi_range) - 2;
4281 phaseinc = desired_divisor % iclk_pi_range;
4282
4283 /*
4284 * Near 20MHz is a corner case which is
4285 * out of range for the 7-bit divisor
4286 */
4287 if (divsel <= 0x7f)
4288 break;
4289 }
4290
4291 /* This should not happen with any sane values */
4292 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4293 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4294 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4295 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4296
4297 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4298 clock,
4299 auxdiv,
4300 divsel,
4301 phasedir,
4302 phaseinc);
4303
4304 mutex_lock(&dev_priv->sb_lock);
4305
4306 /* Program SSCDIVINTPHASE6 */
4307 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4308 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4309 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4310 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4311 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4312 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4313 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4314 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4315
4316 /* Program SSCAUXDIV */
4317 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4318 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4319 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4320 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4321
4322 /* Enable modulator and associated divider */
4323 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4324 temp &= ~SBI_SSCCTL_DISABLE;
4325 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4326
4327 mutex_unlock(&dev_priv->sb_lock);
4328
4329 /* Wait for initialization time */
4330 udelay(24);
4331
4332 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4333 }
4334
4335 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4336 {
4337 u32 divsel, phaseinc, auxdiv;
4338 u32 iclk_virtual_root_freq = 172800 * 1000;
4339 u32 iclk_pi_range = 64;
4340 u32 desired_divisor;
4341 u32 temp;
4342
4343 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4344 return 0;
4345
4346 mutex_lock(&dev_priv->sb_lock);
4347
4348 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4349 if (temp & SBI_SSCCTL_DISABLE) {
4350 mutex_unlock(&dev_priv->sb_lock);
4351 return 0;
4352 }
4353
4354 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4355 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4356 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4357 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4358 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4359
4360 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4361 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4362 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4363
4364 mutex_unlock(&dev_priv->sb_lock);
4365
4366 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4367
4368 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4369 desired_divisor << auxdiv);
4370 }
4371
4372 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4373 enum pipe pch_transcoder)
4374 {
4375 struct drm_device *dev = crtc->base.dev;
4376 struct drm_i915_private *dev_priv = to_i915(dev);
4377 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4378
4379 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4380 I915_READ(HTOTAL(cpu_transcoder)));
4381 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4382 I915_READ(HBLANK(cpu_transcoder)));
4383 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4384 I915_READ(HSYNC(cpu_transcoder)));
4385
4386 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4387 I915_READ(VTOTAL(cpu_transcoder)));
4388 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4389 I915_READ(VBLANK(cpu_transcoder)));
4390 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4391 I915_READ(VSYNC(cpu_transcoder)));
4392 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4393 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4394 }
4395
4396 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4397 {
4398 struct drm_i915_private *dev_priv = to_i915(dev);
4399 uint32_t temp;
4400
4401 temp = I915_READ(SOUTH_CHICKEN1);
4402 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4403 return;
4404
4405 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4406 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4407
4408 temp &= ~FDI_BC_BIFURCATION_SELECT;
4409 if (enable)
4410 temp |= FDI_BC_BIFURCATION_SELECT;
4411
4412 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4413 I915_WRITE(SOUTH_CHICKEN1, temp);
4414 POSTING_READ(SOUTH_CHICKEN1);
4415 }
4416
4417 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4418 {
4419 struct drm_device *dev = intel_crtc->base.dev;
4420
4421 switch (intel_crtc->pipe) {
4422 case PIPE_A:
4423 break;
4424 case PIPE_B:
4425 if (intel_crtc->config->fdi_lanes > 2)
4426 cpt_set_fdi_bc_bifurcation(dev, false);
4427 else
4428 cpt_set_fdi_bc_bifurcation(dev, true);
4429
4430 break;
4431 case PIPE_C:
4432 cpt_set_fdi_bc_bifurcation(dev, true);
4433
4434 break;
4435 default:
4436 BUG();
4437 }
4438 }
4439
4440 /* Return which DP Port should be selected for Transcoder DP control */
4441 static enum port
4442 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4443 {
4444 struct drm_device *dev = crtc->dev;
4445 struct intel_encoder *encoder;
4446
4447 for_each_encoder_on_crtc(dev, crtc, encoder) {
4448 if (encoder->type == INTEL_OUTPUT_DP ||
4449 encoder->type == INTEL_OUTPUT_EDP)
4450 return enc_to_dig_port(&encoder->base)->port;
4451 }
4452
4453 return -1;
4454 }
4455
4456 /*
4457 * Enable PCH resources required for PCH ports:
4458 * - PCH PLLs
4459 * - FDI training & RX/TX
4460 * - update transcoder timings
4461 * - DP transcoding bits
4462 * - transcoder
4463 */
4464 static void ironlake_pch_enable(struct drm_crtc *crtc)
4465 {
4466 struct drm_device *dev = crtc->dev;
4467 struct drm_i915_private *dev_priv = to_i915(dev);
4468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4469 int pipe = intel_crtc->pipe;
4470 u32 temp;
4471
4472 assert_pch_transcoder_disabled(dev_priv, pipe);
4473
4474 if (IS_IVYBRIDGE(dev_priv))
4475 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4476
4477 /* Write the TU size bits before fdi link training, so that error
4478 * detection works. */
4479 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4480 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4481
4482 /* For PCH output, training FDI link */
4483 dev_priv->display.fdi_link_train(crtc);
4484
4485 /* We need to program the right clock selection before writing the pixel
4486 * mutliplier into the DPLL. */
4487 if (HAS_PCH_CPT(dev_priv)) {
4488 u32 sel;
4489
4490 temp = I915_READ(PCH_DPLL_SEL);
4491 temp |= TRANS_DPLL_ENABLE(pipe);
4492 sel = TRANS_DPLLB_SEL(pipe);
4493 if (intel_crtc->config->shared_dpll ==
4494 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4495 temp |= sel;
4496 else
4497 temp &= ~sel;
4498 I915_WRITE(PCH_DPLL_SEL, temp);
4499 }
4500
4501 /* XXX: pch pll's can be enabled any time before we enable the PCH
4502 * transcoder, and we actually should do this to not upset any PCH
4503 * transcoder that already use the clock when we share it.
4504 *
4505 * Note that enable_shared_dpll tries to do the right thing, but
4506 * get_shared_dpll unconditionally resets the pll - we need that to have
4507 * the right LVDS enable sequence. */
4508 intel_enable_shared_dpll(intel_crtc);
4509
4510 /* set transcoder timing, panel must allow it */
4511 assert_panel_unlocked(dev_priv, pipe);
4512 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4513
4514 intel_fdi_normal_train(crtc);
4515
4516 /* For PCH DP, enable TRANS_DP_CTL */
4517 if (HAS_PCH_CPT(dev_priv) &&
4518 intel_crtc_has_dp_encoder(intel_crtc->config)) {
4519 const struct drm_display_mode *adjusted_mode =
4520 &intel_crtc->config->base.adjusted_mode;
4521 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4522 i915_reg_t reg = TRANS_DP_CTL(pipe);
4523 temp = I915_READ(reg);
4524 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4525 TRANS_DP_SYNC_MASK |
4526 TRANS_DP_BPC_MASK);
4527 temp |= TRANS_DP_OUTPUT_ENABLE;
4528 temp |= bpc << 9; /* same format but at 11:9 */
4529
4530 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4531 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4532 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4533 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4534
4535 switch (intel_trans_dp_port_sel(crtc)) {
4536 case PORT_B:
4537 temp |= TRANS_DP_PORT_SEL_B;
4538 break;
4539 case PORT_C:
4540 temp |= TRANS_DP_PORT_SEL_C;
4541 break;
4542 case PORT_D:
4543 temp |= TRANS_DP_PORT_SEL_D;
4544 break;
4545 default:
4546 BUG();
4547 }
4548
4549 I915_WRITE(reg, temp);
4550 }
4551
4552 ironlake_enable_pch_transcoder(dev_priv, pipe);
4553 }
4554
4555 static void lpt_pch_enable(struct drm_crtc *crtc)
4556 {
4557 struct drm_device *dev = crtc->dev;
4558 struct drm_i915_private *dev_priv = to_i915(dev);
4559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4560 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4561
4562 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4563
4564 lpt_program_iclkip(crtc);
4565
4566 /* Set transcoder timing. */
4567 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4568
4569 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4570 }
4571
4572 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4573 {
4574 struct drm_i915_private *dev_priv = to_i915(dev);
4575 i915_reg_t dslreg = PIPEDSL(pipe);
4576 u32 temp;
4577
4578 temp = I915_READ(dslreg);
4579 udelay(500);
4580 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4581 if (wait_for(I915_READ(dslreg) != temp, 5))
4582 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4583 }
4584 }
4585
4586 static int
4587 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4588 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4589 int src_w, int src_h, int dst_w, int dst_h)
4590 {
4591 struct intel_crtc_scaler_state *scaler_state =
4592 &crtc_state->scaler_state;
4593 struct intel_crtc *intel_crtc =
4594 to_intel_crtc(crtc_state->base.crtc);
4595 int need_scaling;
4596
4597 need_scaling = drm_rotation_90_or_270(rotation) ?
4598 (src_h != dst_w || src_w != dst_h):
4599 (src_w != dst_w || src_h != dst_h);
4600
4601 /*
4602 * if plane is being disabled or scaler is no more required or force detach
4603 * - free scaler binded to this plane/crtc
4604 * - in order to do this, update crtc->scaler_usage
4605 *
4606 * Here scaler state in crtc_state is set free so that
4607 * scaler can be assigned to other user. Actual register
4608 * update to free the scaler is done in plane/panel-fit programming.
4609 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4610 */
4611 if (force_detach || !need_scaling) {
4612 if (*scaler_id >= 0) {
4613 scaler_state->scaler_users &= ~(1 << scaler_user);
4614 scaler_state->scalers[*scaler_id].in_use = 0;
4615
4616 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4617 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4618 intel_crtc->pipe, scaler_user, *scaler_id,
4619 scaler_state->scaler_users);
4620 *scaler_id = -1;
4621 }
4622 return 0;
4623 }
4624
4625 /* range checks */
4626 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4627 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4628
4629 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4630 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4631 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4632 "size is out of scaler range\n",
4633 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4634 return -EINVAL;
4635 }
4636
4637 /* mark this plane as a scaler user in crtc_state */
4638 scaler_state->scaler_users |= (1 << scaler_user);
4639 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4640 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4641 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4642 scaler_state->scaler_users);
4643
4644 return 0;
4645 }
4646
4647 /**
4648 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4649 *
4650 * @state: crtc's scaler state
4651 *
4652 * Return
4653 * 0 - scaler_usage updated successfully
4654 * error - requested scaling cannot be supported or other error condition
4655 */
4656 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4657 {
4658 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4659
4660 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4661 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4662 state->pipe_src_w, state->pipe_src_h,
4663 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4664 }
4665
4666 /**
4667 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4668 *
4669 * @state: crtc's scaler state
4670 * @plane_state: atomic plane state to update
4671 *
4672 * Return
4673 * 0 - scaler_usage updated successfully
4674 * error - requested scaling cannot be supported or other error condition
4675 */
4676 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4677 struct intel_plane_state *plane_state)
4678 {
4679
4680 struct intel_plane *intel_plane =
4681 to_intel_plane(plane_state->base.plane);
4682 struct drm_framebuffer *fb = plane_state->base.fb;
4683 int ret;
4684
4685 bool force_detach = !fb || !plane_state->base.visible;
4686
4687 ret = skl_update_scaler(crtc_state, force_detach,
4688 drm_plane_index(&intel_plane->base),
4689 &plane_state->scaler_id,
4690 plane_state->base.rotation,
4691 drm_rect_width(&plane_state->base.src) >> 16,
4692 drm_rect_height(&plane_state->base.src) >> 16,
4693 drm_rect_width(&plane_state->base.dst),
4694 drm_rect_height(&plane_state->base.dst));
4695
4696 if (ret || plane_state->scaler_id < 0)
4697 return ret;
4698
4699 /* check colorkey */
4700 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4701 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4702 intel_plane->base.base.id,
4703 intel_plane->base.name);
4704 return -EINVAL;
4705 }
4706
4707 /* Check src format */
4708 switch (fb->format->format) {
4709 case DRM_FORMAT_RGB565:
4710 case DRM_FORMAT_XBGR8888:
4711 case DRM_FORMAT_XRGB8888:
4712 case DRM_FORMAT_ABGR8888:
4713 case DRM_FORMAT_ARGB8888:
4714 case DRM_FORMAT_XRGB2101010:
4715 case DRM_FORMAT_XBGR2101010:
4716 case DRM_FORMAT_YUYV:
4717 case DRM_FORMAT_YVYU:
4718 case DRM_FORMAT_UYVY:
4719 case DRM_FORMAT_VYUY:
4720 break;
4721 default:
4722 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4723 intel_plane->base.base.id, intel_plane->base.name,
4724 fb->base.id, fb->format->format);
4725 return -EINVAL;
4726 }
4727
4728 return 0;
4729 }
4730
4731 static void skylake_scaler_disable(struct intel_crtc *crtc)
4732 {
4733 int i;
4734
4735 for (i = 0; i < crtc->num_scalers; i++)
4736 skl_detach_scaler(crtc, i);
4737 }
4738
4739 static void skylake_pfit_enable(struct intel_crtc *crtc)
4740 {
4741 struct drm_device *dev = crtc->base.dev;
4742 struct drm_i915_private *dev_priv = to_i915(dev);
4743 int pipe = crtc->pipe;
4744 struct intel_crtc_scaler_state *scaler_state =
4745 &crtc->config->scaler_state;
4746
4747 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4748
4749 if (crtc->config->pch_pfit.enabled) {
4750 int id;
4751
4752 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4753 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4754 return;
4755 }
4756
4757 id = scaler_state->scaler_id;
4758 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4759 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4760 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4761 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4762
4763 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4764 }
4765 }
4766
4767 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4768 {
4769 struct drm_device *dev = crtc->base.dev;
4770 struct drm_i915_private *dev_priv = to_i915(dev);
4771 int pipe = crtc->pipe;
4772
4773 if (crtc->config->pch_pfit.enabled) {
4774 /* Force use of hard-coded filter coefficients
4775 * as some pre-programmed values are broken,
4776 * e.g. x201.
4777 */
4778 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4779 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4780 PF_PIPE_SEL_IVB(pipe));
4781 else
4782 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4783 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4784 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4785 }
4786 }
4787
4788 void hsw_enable_ips(struct intel_crtc *crtc)
4789 {
4790 struct drm_device *dev = crtc->base.dev;
4791 struct drm_i915_private *dev_priv = to_i915(dev);
4792
4793 if (!crtc->config->ips_enabled)
4794 return;
4795
4796 /*
4797 * We can only enable IPS after we enable a plane and wait for a vblank
4798 * This function is called from post_plane_update, which is run after
4799 * a vblank wait.
4800 */
4801
4802 assert_plane_enabled(dev_priv, crtc->plane);
4803 if (IS_BROADWELL(dev_priv)) {
4804 mutex_lock(&dev_priv->rps.hw_lock);
4805 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4806 mutex_unlock(&dev_priv->rps.hw_lock);
4807 /* Quoting Art Runyan: "its not safe to expect any particular
4808 * value in IPS_CTL bit 31 after enabling IPS through the
4809 * mailbox." Moreover, the mailbox may return a bogus state,
4810 * so we need to just enable it and continue on.
4811 */
4812 } else {
4813 I915_WRITE(IPS_CTL, IPS_ENABLE);
4814 /* The bit only becomes 1 in the next vblank, so this wait here
4815 * is essentially intel_wait_for_vblank. If we don't have this
4816 * and don't wait for vblanks until the end of crtc_enable, then
4817 * the HW state readout code will complain that the expected
4818 * IPS_CTL value is not the one we read. */
4819 if (intel_wait_for_register(dev_priv,
4820 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4821 50))
4822 DRM_ERROR("Timed out waiting for IPS enable\n");
4823 }
4824 }
4825
4826 void hsw_disable_ips(struct intel_crtc *crtc)
4827 {
4828 struct drm_device *dev = crtc->base.dev;
4829 struct drm_i915_private *dev_priv = to_i915(dev);
4830
4831 if (!crtc->config->ips_enabled)
4832 return;
4833
4834 assert_plane_enabled(dev_priv, crtc->plane);
4835 if (IS_BROADWELL(dev_priv)) {
4836 mutex_lock(&dev_priv->rps.hw_lock);
4837 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4838 mutex_unlock(&dev_priv->rps.hw_lock);
4839 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4840 if (intel_wait_for_register(dev_priv,
4841 IPS_CTL, IPS_ENABLE, 0,
4842 42))
4843 DRM_ERROR("Timed out waiting for IPS disable\n");
4844 } else {
4845 I915_WRITE(IPS_CTL, 0);
4846 POSTING_READ(IPS_CTL);
4847 }
4848
4849 /* We need to wait for a vblank before we can disable the plane. */
4850 intel_wait_for_vblank(dev_priv, crtc->pipe);
4851 }
4852
4853 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4854 {
4855 if (intel_crtc->overlay) {
4856 struct drm_device *dev = intel_crtc->base.dev;
4857 struct drm_i915_private *dev_priv = to_i915(dev);
4858
4859 mutex_lock(&dev->struct_mutex);
4860 dev_priv->mm.interruptible = false;
4861 (void) intel_overlay_switch_off(intel_crtc->overlay);
4862 dev_priv->mm.interruptible = true;
4863 mutex_unlock(&dev->struct_mutex);
4864 }
4865
4866 /* Let userspace switch the overlay on again. In most cases userspace
4867 * has to recompute where to put it anyway.
4868 */
4869 }
4870
4871 /**
4872 * intel_post_enable_primary - Perform operations after enabling primary plane
4873 * @crtc: the CRTC whose primary plane was just enabled
4874 *
4875 * Performs potentially sleeping operations that must be done after the primary
4876 * plane is enabled, such as updating FBC and IPS. Note that this may be
4877 * called due to an explicit primary plane update, or due to an implicit
4878 * re-enable that is caused when a sprite plane is updated to no longer
4879 * completely hide the primary plane.
4880 */
4881 static void
4882 intel_post_enable_primary(struct drm_crtc *crtc)
4883 {
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = to_i915(dev);
4886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887 int pipe = intel_crtc->pipe;
4888
4889 /*
4890 * FIXME IPS should be fine as long as one plane is
4891 * enabled, but in practice it seems to have problems
4892 * when going from primary only to sprite only and vice
4893 * versa.
4894 */
4895 hsw_enable_ips(intel_crtc);
4896
4897 /*
4898 * Gen2 reports pipe underruns whenever all planes are disabled.
4899 * So don't enable underrun reporting before at least some planes
4900 * are enabled.
4901 * FIXME: Need to fix the logic to work when we turn off all planes
4902 * but leave the pipe running.
4903 */
4904 if (IS_GEN2(dev_priv))
4905 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4906
4907 /* Underruns don't always raise interrupts, so check manually. */
4908 intel_check_cpu_fifo_underruns(dev_priv);
4909 intel_check_pch_fifo_underruns(dev_priv);
4910 }
4911
4912 /* FIXME move all this to pre_plane_update() with proper state tracking */
4913 static void
4914 intel_pre_disable_primary(struct drm_crtc *crtc)
4915 {
4916 struct drm_device *dev = crtc->dev;
4917 struct drm_i915_private *dev_priv = to_i915(dev);
4918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4919 int pipe = intel_crtc->pipe;
4920
4921 /*
4922 * Gen2 reports pipe underruns whenever all planes are disabled.
4923 * So diasble underrun reporting before all the planes get disabled.
4924 * FIXME: Need to fix the logic to work when we turn off all planes
4925 * but leave the pipe running.
4926 */
4927 if (IS_GEN2(dev_priv))
4928 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4929
4930 /*
4931 * FIXME IPS should be fine as long as one plane is
4932 * enabled, but in practice it seems to have problems
4933 * when going from primary only to sprite only and vice
4934 * versa.
4935 */
4936 hsw_disable_ips(intel_crtc);
4937 }
4938
4939 /* FIXME get rid of this and use pre_plane_update */
4940 static void
4941 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4942 {
4943 struct drm_device *dev = crtc->dev;
4944 struct drm_i915_private *dev_priv = to_i915(dev);
4945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4946 int pipe = intel_crtc->pipe;
4947
4948 intel_pre_disable_primary(crtc);
4949
4950 /*
4951 * Vblank time updates from the shadow to live plane control register
4952 * are blocked if the memory self-refresh mode is active at that
4953 * moment. So to make sure the plane gets truly disabled, disable
4954 * first the self-refresh mode. The self-refresh enable bit in turn
4955 * will be checked/applied by the HW only at the next frame start
4956 * event which is after the vblank start event, so we need to have a
4957 * wait-for-vblank between disabling the plane and the pipe.
4958 */
4959 if (HAS_GMCH_DISPLAY(dev_priv) &&
4960 intel_set_memory_cxsr(dev_priv, false))
4961 intel_wait_for_vblank(dev_priv, pipe);
4962 }
4963
4964 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4965 {
4966 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4967 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4968 struct intel_crtc_state *pipe_config =
4969 to_intel_crtc_state(crtc->base.state);
4970 struct drm_plane *primary = crtc->base.primary;
4971 struct drm_plane_state *old_pri_state =
4972 drm_atomic_get_existing_plane_state(old_state, primary);
4973
4974 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4975
4976 crtc->wm.cxsr_allowed = true;
4977
4978 if (pipe_config->update_wm_post && pipe_config->base.active)
4979 intel_update_watermarks(crtc);
4980
4981 if (old_pri_state) {
4982 struct intel_plane_state *primary_state =
4983 to_intel_plane_state(primary->state);
4984 struct intel_plane_state *old_primary_state =
4985 to_intel_plane_state(old_pri_state);
4986
4987 intel_fbc_post_update(crtc);
4988
4989 if (primary_state->base.visible &&
4990 (needs_modeset(&pipe_config->base) ||
4991 !old_primary_state->base.visible))
4992 intel_post_enable_primary(&crtc->base);
4993 }
4994 }
4995
4996 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4997 {
4998 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4999 struct drm_device *dev = crtc->base.dev;
5000 struct drm_i915_private *dev_priv = to_i915(dev);
5001 struct intel_crtc_state *pipe_config =
5002 to_intel_crtc_state(crtc->base.state);
5003 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5004 struct drm_plane *primary = crtc->base.primary;
5005 struct drm_plane_state *old_pri_state =
5006 drm_atomic_get_existing_plane_state(old_state, primary);
5007 bool modeset = needs_modeset(&pipe_config->base);
5008 struct intel_atomic_state *old_intel_state =
5009 to_intel_atomic_state(old_state);
5010
5011 if (old_pri_state) {
5012 struct intel_plane_state *primary_state =
5013 to_intel_plane_state(primary->state);
5014 struct intel_plane_state *old_primary_state =
5015 to_intel_plane_state(old_pri_state);
5016
5017 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5018
5019 if (old_primary_state->base.visible &&
5020 (modeset || !primary_state->base.visible))
5021 intel_pre_disable_primary(&crtc->base);
5022 }
5023
5024 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5025 crtc->wm.cxsr_allowed = false;
5026
5027 /*
5028 * Vblank time updates from the shadow to live plane control register
5029 * are blocked if the memory self-refresh mode is active at that
5030 * moment. So to make sure the plane gets truly disabled, disable
5031 * first the self-refresh mode. The self-refresh enable bit in turn
5032 * will be checked/applied by the HW only at the next frame start
5033 * event which is after the vblank start event, so we need to have a
5034 * wait-for-vblank between disabling the plane and the pipe.
5035 */
5036 if (old_crtc_state->base.active &&
5037 intel_set_memory_cxsr(dev_priv, false))
5038 intel_wait_for_vblank(dev_priv, crtc->pipe);
5039 }
5040
5041 /*
5042 * IVB workaround: must disable low power watermarks for at least
5043 * one frame before enabling scaling. LP watermarks can be re-enabled
5044 * when scaling is disabled.
5045 *
5046 * WaCxSRDisabledForSpriteScaling:ivb
5047 */
5048 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5049 intel_wait_for_vblank(dev_priv, crtc->pipe);
5050
5051 /*
5052 * If we're doing a modeset, we're done. No need to do any pre-vblank
5053 * watermark programming here.
5054 */
5055 if (needs_modeset(&pipe_config->base))
5056 return;
5057
5058 /*
5059 * For platforms that support atomic watermarks, program the
5060 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5061 * will be the intermediate values that are safe for both pre- and
5062 * post- vblank; when vblank happens, the 'active' values will be set
5063 * to the final 'target' values and we'll do this again to get the
5064 * optimal watermarks. For gen9+ platforms, the values we program here
5065 * will be the final target values which will get automatically latched
5066 * at vblank time; no further programming will be necessary.
5067 *
5068 * If a platform hasn't been transitioned to atomic watermarks yet,
5069 * we'll continue to update watermarks the old way, if flags tell
5070 * us to.
5071 */
5072 if (dev_priv->display.initial_watermarks != NULL)
5073 dev_priv->display.initial_watermarks(old_intel_state,
5074 pipe_config);
5075 else if (pipe_config->update_wm_pre)
5076 intel_update_watermarks(crtc);
5077 }
5078
5079 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5080 {
5081 struct drm_device *dev = crtc->dev;
5082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5083 struct drm_plane *p;
5084 int pipe = intel_crtc->pipe;
5085
5086 intel_crtc_dpms_overlay_disable(intel_crtc);
5087
5088 drm_for_each_plane_mask(p, dev, plane_mask)
5089 to_intel_plane(p)->disable_plane(p, crtc);
5090
5091 /*
5092 * FIXME: Once we grow proper nuclear flip support out of this we need
5093 * to compute the mask of flip planes precisely. For the time being
5094 * consider this a flip to a NULL plane.
5095 */
5096 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5097 }
5098
5099 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5100 struct intel_crtc_state *crtc_state,
5101 struct drm_atomic_state *old_state)
5102 {
5103 struct drm_connector_state *old_conn_state;
5104 struct drm_connector *conn;
5105 int i;
5106
5107 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5108 struct drm_connector_state *conn_state = conn->state;
5109 struct intel_encoder *encoder =
5110 to_intel_encoder(conn_state->best_encoder);
5111
5112 if (conn_state->crtc != crtc)
5113 continue;
5114
5115 if (encoder->pre_pll_enable)
5116 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5117 }
5118 }
5119
5120 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5121 struct intel_crtc_state *crtc_state,
5122 struct drm_atomic_state *old_state)
5123 {
5124 struct drm_connector_state *old_conn_state;
5125 struct drm_connector *conn;
5126 int i;
5127
5128 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5129 struct drm_connector_state *conn_state = conn->state;
5130 struct intel_encoder *encoder =
5131 to_intel_encoder(conn_state->best_encoder);
5132
5133 if (conn_state->crtc != crtc)
5134 continue;
5135
5136 if (encoder->pre_enable)
5137 encoder->pre_enable(encoder, crtc_state, conn_state);
5138 }
5139 }
5140
5141 static void intel_encoders_enable(struct drm_crtc *crtc,
5142 struct intel_crtc_state *crtc_state,
5143 struct drm_atomic_state *old_state)
5144 {
5145 struct drm_connector_state *old_conn_state;
5146 struct drm_connector *conn;
5147 int i;
5148
5149 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5150 struct drm_connector_state *conn_state = conn->state;
5151 struct intel_encoder *encoder =
5152 to_intel_encoder(conn_state->best_encoder);
5153
5154 if (conn_state->crtc != crtc)
5155 continue;
5156
5157 encoder->enable(encoder, crtc_state, conn_state);
5158 intel_opregion_notify_encoder(encoder, true);
5159 }
5160 }
5161
5162 static void intel_encoders_disable(struct drm_crtc *crtc,
5163 struct intel_crtc_state *old_crtc_state,
5164 struct drm_atomic_state *old_state)
5165 {
5166 struct drm_connector_state *old_conn_state;
5167 struct drm_connector *conn;
5168 int i;
5169
5170 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5171 struct intel_encoder *encoder =
5172 to_intel_encoder(old_conn_state->best_encoder);
5173
5174 if (old_conn_state->crtc != crtc)
5175 continue;
5176
5177 intel_opregion_notify_encoder(encoder, false);
5178 encoder->disable(encoder, old_crtc_state, old_conn_state);
5179 }
5180 }
5181
5182 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5183 struct intel_crtc_state *old_crtc_state,
5184 struct drm_atomic_state *old_state)
5185 {
5186 struct drm_connector_state *old_conn_state;
5187 struct drm_connector *conn;
5188 int i;
5189
5190 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5191 struct intel_encoder *encoder =
5192 to_intel_encoder(old_conn_state->best_encoder);
5193
5194 if (old_conn_state->crtc != crtc)
5195 continue;
5196
5197 if (encoder->post_disable)
5198 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5199 }
5200 }
5201
5202 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5203 struct intel_crtc_state *old_crtc_state,
5204 struct drm_atomic_state *old_state)
5205 {
5206 struct drm_connector_state *old_conn_state;
5207 struct drm_connector *conn;
5208 int i;
5209
5210 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5211 struct intel_encoder *encoder =
5212 to_intel_encoder(old_conn_state->best_encoder);
5213
5214 if (old_conn_state->crtc != crtc)
5215 continue;
5216
5217 if (encoder->post_pll_disable)
5218 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5219 }
5220 }
5221
5222 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5223 struct drm_atomic_state *old_state)
5224 {
5225 struct drm_crtc *crtc = pipe_config->base.crtc;
5226 struct drm_device *dev = crtc->dev;
5227 struct drm_i915_private *dev_priv = to_i915(dev);
5228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229 int pipe = intel_crtc->pipe;
5230 struct intel_atomic_state *old_intel_state =
5231 to_intel_atomic_state(old_state);
5232
5233 if (WARN_ON(intel_crtc->active))
5234 return;
5235
5236 /*
5237 * Sometimes spurious CPU pipe underruns happen during FDI
5238 * training, at least with VGA+HDMI cloning. Suppress them.
5239 *
5240 * On ILK we get an occasional spurious CPU pipe underruns
5241 * between eDP port A enable and vdd enable. Also PCH port
5242 * enable seems to result in the occasional CPU pipe underrun.
5243 *
5244 * Spurious PCH underruns also occur during PCH enabling.
5245 */
5246 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5247 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5248 if (intel_crtc->config->has_pch_encoder)
5249 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5250
5251 if (intel_crtc->config->has_pch_encoder)
5252 intel_prepare_shared_dpll(intel_crtc);
5253
5254 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5255 intel_dp_set_m_n(intel_crtc, M1_N1);
5256
5257 intel_set_pipe_timings(intel_crtc);
5258 intel_set_pipe_src_size(intel_crtc);
5259
5260 if (intel_crtc->config->has_pch_encoder) {
5261 intel_cpu_transcoder_set_m_n(intel_crtc,
5262 &intel_crtc->config->fdi_m_n, NULL);
5263 }
5264
5265 ironlake_set_pipeconf(crtc);
5266
5267 intel_crtc->active = true;
5268
5269 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5270
5271 if (intel_crtc->config->has_pch_encoder) {
5272 /* Note: FDI PLL enabling _must_ be done before we enable the
5273 * cpu pipes, hence this is separate from all the other fdi/pch
5274 * enabling. */
5275 ironlake_fdi_pll_enable(intel_crtc);
5276 } else {
5277 assert_fdi_tx_disabled(dev_priv, pipe);
5278 assert_fdi_rx_disabled(dev_priv, pipe);
5279 }
5280
5281 ironlake_pfit_enable(intel_crtc);
5282
5283 /*
5284 * On ILK+ LUT must be loaded before the pipe is running but with
5285 * clocks enabled
5286 */
5287 intel_color_load_luts(&pipe_config->base);
5288
5289 if (dev_priv->display.initial_watermarks != NULL)
5290 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5291 intel_enable_pipe(intel_crtc);
5292
5293 if (intel_crtc->config->has_pch_encoder)
5294 ironlake_pch_enable(crtc);
5295
5296 assert_vblank_disabled(crtc);
5297 drm_crtc_vblank_on(crtc);
5298
5299 intel_encoders_enable(crtc, pipe_config, old_state);
5300
5301 if (HAS_PCH_CPT(dev_priv))
5302 cpt_verify_modeset(dev, intel_crtc->pipe);
5303
5304 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5305 if (intel_crtc->config->has_pch_encoder)
5306 intel_wait_for_vblank(dev_priv, pipe);
5307 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5308 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5309 }
5310
5311 /* IPS only exists on ULT machines and is tied to pipe A. */
5312 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5313 {
5314 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5315 }
5316
5317 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5318 struct drm_atomic_state *old_state)
5319 {
5320 struct drm_crtc *crtc = pipe_config->base.crtc;
5321 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5323 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5324 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5325 struct intel_atomic_state *old_intel_state =
5326 to_intel_atomic_state(old_state);
5327
5328 if (WARN_ON(intel_crtc->active))
5329 return;
5330
5331 if (intel_crtc->config->has_pch_encoder)
5332 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5333 false);
5334
5335 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5336
5337 if (intel_crtc->config->shared_dpll)
5338 intel_enable_shared_dpll(intel_crtc);
5339
5340 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5341 intel_dp_set_m_n(intel_crtc, M1_N1);
5342
5343 if (!transcoder_is_dsi(cpu_transcoder))
5344 intel_set_pipe_timings(intel_crtc);
5345
5346 intel_set_pipe_src_size(intel_crtc);
5347
5348 if (cpu_transcoder != TRANSCODER_EDP &&
5349 !transcoder_is_dsi(cpu_transcoder)) {
5350 I915_WRITE(PIPE_MULT(cpu_transcoder),
5351 intel_crtc->config->pixel_multiplier - 1);
5352 }
5353
5354 if (intel_crtc->config->has_pch_encoder) {
5355 intel_cpu_transcoder_set_m_n(intel_crtc,
5356 &intel_crtc->config->fdi_m_n, NULL);
5357 }
5358
5359 if (!transcoder_is_dsi(cpu_transcoder))
5360 haswell_set_pipeconf(crtc);
5361
5362 haswell_set_pipemisc(crtc);
5363
5364 intel_color_set_csc(&pipe_config->base);
5365
5366 intel_crtc->active = true;
5367
5368 if (intel_crtc->config->has_pch_encoder)
5369 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5370 else
5371 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5372
5373 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5374
5375 if (intel_crtc->config->has_pch_encoder)
5376 dev_priv->display.fdi_link_train(crtc);
5377
5378 if (!transcoder_is_dsi(cpu_transcoder))
5379 intel_ddi_enable_pipe_clock(intel_crtc);
5380
5381 if (INTEL_GEN(dev_priv) >= 9)
5382 skylake_pfit_enable(intel_crtc);
5383 else
5384 ironlake_pfit_enable(intel_crtc);
5385
5386 /*
5387 * On ILK+ LUT must be loaded before the pipe is running but with
5388 * clocks enabled
5389 */
5390 intel_color_load_luts(&pipe_config->base);
5391
5392 intel_ddi_set_pipe_settings(crtc);
5393 if (!transcoder_is_dsi(cpu_transcoder))
5394 intel_ddi_enable_transcoder_func(crtc);
5395
5396 if (dev_priv->display.initial_watermarks != NULL)
5397 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5398
5399 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5400 if (!transcoder_is_dsi(cpu_transcoder))
5401 intel_enable_pipe(intel_crtc);
5402
5403 if (intel_crtc->config->has_pch_encoder)
5404 lpt_pch_enable(crtc);
5405
5406 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5407 intel_ddi_set_vc_payload_alloc(crtc, true);
5408
5409 assert_vblank_disabled(crtc);
5410 drm_crtc_vblank_on(crtc);
5411
5412 intel_encoders_enable(crtc, pipe_config, old_state);
5413
5414 if (intel_crtc->config->has_pch_encoder) {
5415 intel_wait_for_vblank(dev_priv, pipe);
5416 intel_wait_for_vblank(dev_priv, pipe);
5417 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5418 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5419 true);
5420 }
5421
5422 /* If we change the relative order between pipe/planes enabling, we need
5423 * to change the workaround. */
5424 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5425 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5426 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5427 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5428 }
5429 }
5430
5431 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5432 {
5433 struct drm_device *dev = crtc->base.dev;
5434 struct drm_i915_private *dev_priv = to_i915(dev);
5435 int pipe = crtc->pipe;
5436
5437 /* To avoid upsetting the power well on haswell only disable the pfit if
5438 * it's in use. The hw state code will make sure we get this right. */
5439 if (force || crtc->config->pch_pfit.enabled) {
5440 I915_WRITE(PF_CTL(pipe), 0);
5441 I915_WRITE(PF_WIN_POS(pipe), 0);
5442 I915_WRITE(PF_WIN_SZ(pipe), 0);
5443 }
5444 }
5445
5446 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5447 struct drm_atomic_state *old_state)
5448 {
5449 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5450 struct drm_device *dev = crtc->dev;
5451 struct drm_i915_private *dev_priv = to_i915(dev);
5452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5453 int pipe = intel_crtc->pipe;
5454
5455 /*
5456 * Sometimes spurious CPU pipe underruns happen when the
5457 * pipe is already disabled, but FDI RX/TX is still enabled.
5458 * Happens at least with VGA+HDMI cloning. Suppress them.
5459 */
5460 if (intel_crtc->config->has_pch_encoder) {
5461 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5462 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5463 }
5464
5465 intel_encoders_disable(crtc, old_crtc_state, old_state);
5466
5467 drm_crtc_vblank_off(crtc);
5468 assert_vblank_disabled(crtc);
5469
5470 intel_disable_pipe(intel_crtc);
5471
5472 ironlake_pfit_disable(intel_crtc, false);
5473
5474 if (intel_crtc->config->has_pch_encoder)
5475 ironlake_fdi_disable(crtc);
5476
5477 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5478
5479 if (intel_crtc->config->has_pch_encoder) {
5480 ironlake_disable_pch_transcoder(dev_priv, pipe);
5481
5482 if (HAS_PCH_CPT(dev_priv)) {
5483 i915_reg_t reg;
5484 u32 temp;
5485
5486 /* disable TRANS_DP_CTL */
5487 reg = TRANS_DP_CTL(pipe);
5488 temp = I915_READ(reg);
5489 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5490 TRANS_DP_PORT_SEL_MASK);
5491 temp |= TRANS_DP_PORT_SEL_NONE;
5492 I915_WRITE(reg, temp);
5493
5494 /* disable DPLL_SEL */
5495 temp = I915_READ(PCH_DPLL_SEL);
5496 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5497 I915_WRITE(PCH_DPLL_SEL, temp);
5498 }
5499
5500 ironlake_fdi_pll_disable(intel_crtc);
5501 }
5502
5503 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5504 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5505 }
5506
5507 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5508 struct drm_atomic_state *old_state)
5509 {
5510 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5511 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5513 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5514
5515 if (intel_crtc->config->has_pch_encoder)
5516 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5517 false);
5518
5519 intel_encoders_disable(crtc, old_crtc_state, old_state);
5520
5521 drm_crtc_vblank_off(crtc);
5522 assert_vblank_disabled(crtc);
5523
5524 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5525 if (!transcoder_is_dsi(cpu_transcoder))
5526 intel_disable_pipe(intel_crtc);
5527
5528 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5529 intel_ddi_set_vc_payload_alloc(crtc, false);
5530
5531 if (!transcoder_is_dsi(cpu_transcoder))
5532 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5533
5534 if (INTEL_GEN(dev_priv) >= 9)
5535 skylake_scaler_disable(intel_crtc);
5536 else
5537 ironlake_pfit_disable(intel_crtc, false);
5538
5539 if (!transcoder_is_dsi(cpu_transcoder))
5540 intel_ddi_disable_pipe_clock(intel_crtc);
5541
5542 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5543
5544 if (old_crtc_state->has_pch_encoder)
5545 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5546 true);
5547 }
5548
5549 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5550 {
5551 struct drm_device *dev = crtc->base.dev;
5552 struct drm_i915_private *dev_priv = to_i915(dev);
5553 struct intel_crtc_state *pipe_config = crtc->config;
5554
5555 if (!pipe_config->gmch_pfit.control)
5556 return;
5557
5558 /*
5559 * The panel fitter should only be adjusted whilst the pipe is disabled,
5560 * according to register description and PRM.
5561 */
5562 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5563 assert_pipe_disabled(dev_priv, crtc->pipe);
5564
5565 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5566 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5567
5568 /* Border color in case we don't scale up to the full screen. Black by
5569 * default, change to something else for debugging. */
5570 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5571 }
5572
5573 static enum intel_display_power_domain port_to_power_domain(enum port port)
5574 {
5575 switch (port) {
5576 case PORT_A:
5577 return POWER_DOMAIN_PORT_DDI_A_LANES;
5578 case PORT_B:
5579 return POWER_DOMAIN_PORT_DDI_B_LANES;
5580 case PORT_C:
5581 return POWER_DOMAIN_PORT_DDI_C_LANES;
5582 case PORT_D:
5583 return POWER_DOMAIN_PORT_DDI_D_LANES;
5584 case PORT_E:
5585 return POWER_DOMAIN_PORT_DDI_E_LANES;
5586 default:
5587 MISSING_CASE(port);
5588 return POWER_DOMAIN_PORT_OTHER;
5589 }
5590 }
5591
5592 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5593 {
5594 switch (port) {
5595 case PORT_A:
5596 return POWER_DOMAIN_AUX_A;
5597 case PORT_B:
5598 return POWER_DOMAIN_AUX_B;
5599 case PORT_C:
5600 return POWER_DOMAIN_AUX_C;
5601 case PORT_D:
5602 return POWER_DOMAIN_AUX_D;
5603 case PORT_E:
5604 /* FIXME: Check VBT for actual wiring of PORT E */
5605 return POWER_DOMAIN_AUX_D;
5606 default:
5607 MISSING_CASE(port);
5608 return POWER_DOMAIN_AUX_A;
5609 }
5610 }
5611
5612 enum intel_display_power_domain
5613 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5614 {
5615 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5616 struct intel_digital_port *intel_dig_port;
5617
5618 switch (intel_encoder->type) {
5619 case INTEL_OUTPUT_UNKNOWN:
5620 /* Only DDI platforms should ever use this output type */
5621 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5622 case INTEL_OUTPUT_DP:
5623 case INTEL_OUTPUT_HDMI:
5624 case INTEL_OUTPUT_EDP:
5625 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5626 return port_to_power_domain(intel_dig_port->port);
5627 case INTEL_OUTPUT_DP_MST:
5628 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5629 return port_to_power_domain(intel_dig_port->port);
5630 case INTEL_OUTPUT_ANALOG:
5631 return POWER_DOMAIN_PORT_CRT;
5632 case INTEL_OUTPUT_DSI:
5633 return POWER_DOMAIN_PORT_DSI;
5634 default:
5635 return POWER_DOMAIN_PORT_OTHER;
5636 }
5637 }
5638
5639 enum intel_display_power_domain
5640 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5641 {
5642 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5643 struct intel_digital_port *intel_dig_port;
5644
5645 switch (intel_encoder->type) {
5646 case INTEL_OUTPUT_UNKNOWN:
5647 case INTEL_OUTPUT_HDMI:
5648 /*
5649 * Only DDI platforms should ever use these output types.
5650 * We can get here after the HDMI detect code has already set
5651 * the type of the shared encoder. Since we can't be sure
5652 * what's the status of the given connectors, play safe and
5653 * run the DP detection too.
5654 */
5655 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5656 case INTEL_OUTPUT_DP:
5657 case INTEL_OUTPUT_EDP:
5658 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5659 return port_to_aux_power_domain(intel_dig_port->port);
5660 case INTEL_OUTPUT_DP_MST:
5661 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5662 return port_to_aux_power_domain(intel_dig_port->port);
5663 default:
5664 MISSING_CASE(intel_encoder->type);
5665 return POWER_DOMAIN_AUX_A;
5666 }
5667 }
5668
5669 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5670 struct intel_crtc_state *crtc_state)
5671 {
5672 struct drm_device *dev = crtc->dev;
5673 struct drm_i915_private *dev_priv = to_i915(dev);
5674 struct drm_encoder *encoder;
5675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5676 enum pipe pipe = intel_crtc->pipe;
5677 u64 mask;
5678 enum transcoder transcoder = crtc_state->cpu_transcoder;
5679
5680 if (!crtc_state->base.active)
5681 return 0;
5682
5683 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5684 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5685 if (crtc_state->pch_pfit.enabled ||
5686 crtc_state->pch_pfit.force_thru)
5687 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5688
5689 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5690 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5691
5692 mask |= BIT_ULL(intel_display_port_power_domain(intel_encoder));
5693 }
5694
5695 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5696 mask |= BIT(POWER_DOMAIN_AUDIO);
5697
5698 if (crtc_state->shared_dpll)
5699 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5700
5701 return mask;
5702 }
5703
5704 static unsigned long
5705 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5706 struct intel_crtc_state *crtc_state)
5707 {
5708 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5710 enum intel_display_power_domain domain;
5711 u64 domains, new_domains, old_domains;
5712
5713 old_domains = intel_crtc->enabled_power_domains;
5714 intel_crtc->enabled_power_domains = new_domains =
5715 get_crtc_power_domains(crtc, crtc_state);
5716
5717 domains = new_domains & ~old_domains;
5718
5719 for_each_power_domain(domain, domains)
5720 intel_display_power_get(dev_priv, domain);
5721
5722 return old_domains & ~new_domains;
5723 }
5724
5725 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5726 u64 domains)
5727 {
5728 enum intel_display_power_domain domain;
5729
5730 for_each_power_domain(domain, domains)
5731 intel_display_power_put(dev_priv, domain);
5732 }
5733
5734 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5735 struct drm_atomic_state *old_state)
5736 {
5737 struct drm_crtc *crtc = pipe_config->base.crtc;
5738 struct drm_device *dev = crtc->dev;
5739 struct drm_i915_private *dev_priv = to_i915(dev);
5740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5741 int pipe = intel_crtc->pipe;
5742
5743 if (WARN_ON(intel_crtc->active))
5744 return;
5745
5746 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5747 intel_dp_set_m_n(intel_crtc, M1_N1);
5748
5749 intel_set_pipe_timings(intel_crtc);
5750 intel_set_pipe_src_size(intel_crtc);
5751
5752 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5753 struct drm_i915_private *dev_priv = to_i915(dev);
5754
5755 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5756 I915_WRITE(CHV_CANVAS(pipe), 0);
5757 }
5758
5759 i9xx_set_pipeconf(intel_crtc);
5760
5761 intel_crtc->active = true;
5762
5763 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5764
5765 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5766
5767 if (IS_CHERRYVIEW(dev_priv)) {
5768 chv_prepare_pll(intel_crtc, intel_crtc->config);
5769 chv_enable_pll(intel_crtc, intel_crtc->config);
5770 } else {
5771 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5772 vlv_enable_pll(intel_crtc, intel_crtc->config);
5773 }
5774
5775 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5776
5777 i9xx_pfit_enable(intel_crtc);
5778
5779 intel_color_load_luts(&pipe_config->base);
5780
5781 intel_update_watermarks(intel_crtc);
5782 intel_enable_pipe(intel_crtc);
5783
5784 assert_vblank_disabled(crtc);
5785 drm_crtc_vblank_on(crtc);
5786
5787 intel_encoders_enable(crtc, pipe_config, old_state);
5788 }
5789
5790 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5791 {
5792 struct drm_device *dev = crtc->base.dev;
5793 struct drm_i915_private *dev_priv = to_i915(dev);
5794
5795 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5796 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5797 }
5798
5799 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5800 struct drm_atomic_state *old_state)
5801 {
5802 struct drm_crtc *crtc = pipe_config->base.crtc;
5803 struct drm_device *dev = crtc->dev;
5804 struct drm_i915_private *dev_priv = to_i915(dev);
5805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5806 enum pipe pipe = intel_crtc->pipe;
5807
5808 if (WARN_ON(intel_crtc->active))
5809 return;
5810
5811 i9xx_set_pll_dividers(intel_crtc);
5812
5813 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5814 intel_dp_set_m_n(intel_crtc, M1_N1);
5815
5816 intel_set_pipe_timings(intel_crtc);
5817 intel_set_pipe_src_size(intel_crtc);
5818
5819 i9xx_set_pipeconf(intel_crtc);
5820
5821 intel_crtc->active = true;
5822
5823 if (!IS_GEN2(dev_priv))
5824 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5825
5826 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5827
5828 i9xx_enable_pll(intel_crtc);
5829
5830 i9xx_pfit_enable(intel_crtc);
5831
5832 intel_color_load_luts(&pipe_config->base);
5833
5834 intel_update_watermarks(intel_crtc);
5835 intel_enable_pipe(intel_crtc);
5836
5837 assert_vblank_disabled(crtc);
5838 drm_crtc_vblank_on(crtc);
5839
5840 intel_encoders_enable(crtc, pipe_config, old_state);
5841 }
5842
5843 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5844 {
5845 struct drm_device *dev = crtc->base.dev;
5846 struct drm_i915_private *dev_priv = to_i915(dev);
5847
5848 if (!crtc->config->gmch_pfit.control)
5849 return;
5850
5851 assert_pipe_disabled(dev_priv, crtc->pipe);
5852
5853 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5854 I915_READ(PFIT_CONTROL));
5855 I915_WRITE(PFIT_CONTROL, 0);
5856 }
5857
5858 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5859 struct drm_atomic_state *old_state)
5860 {
5861 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5862 struct drm_device *dev = crtc->dev;
5863 struct drm_i915_private *dev_priv = to_i915(dev);
5864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5865 int pipe = intel_crtc->pipe;
5866
5867 /*
5868 * On gen2 planes are double buffered but the pipe isn't, so we must
5869 * wait for planes to fully turn off before disabling the pipe.
5870 */
5871 if (IS_GEN2(dev_priv))
5872 intel_wait_for_vblank(dev_priv, pipe);
5873
5874 intel_encoders_disable(crtc, old_crtc_state, old_state);
5875
5876 drm_crtc_vblank_off(crtc);
5877 assert_vblank_disabled(crtc);
5878
5879 intel_disable_pipe(intel_crtc);
5880
5881 i9xx_pfit_disable(intel_crtc);
5882
5883 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5884
5885 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5886 if (IS_CHERRYVIEW(dev_priv))
5887 chv_disable_pll(dev_priv, pipe);
5888 else if (IS_VALLEYVIEW(dev_priv))
5889 vlv_disable_pll(dev_priv, pipe);
5890 else
5891 i9xx_disable_pll(intel_crtc);
5892 }
5893
5894 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5895
5896 if (!IS_GEN2(dev_priv))
5897 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5898 }
5899
5900 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5901 {
5902 struct intel_encoder *encoder;
5903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5904 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5905 enum intel_display_power_domain domain;
5906 unsigned long domains;
5907 struct drm_atomic_state *state;
5908 struct intel_crtc_state *crtc_state;
5909 int ret;
5910
5911 if (!intel_crtc->active)
5912 return;
5913
5914 if (crtc->primary->state->visible) {
5915 WARN_ON(intel_crtc->flip_work);
5916
5917 intel_pre_disable_primary_noatomic(crtc);
5918
5919 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5920 crtc->primary->state->visible = false;
5921 }
5922
5923 state = drm_atomic_state_alloc(crtc->dev);
5924 if (!state) {
5925 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5926 crtc->base.id, crtc->name);
5927 return;
5928 }
5929
5930 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5931
5932 /* Everything's already locked, -EDEADLK can't happen. */
5933 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5934 ret = drm_atomic_add_affected_connectors(state, crtc);
5935
5936 WARN_ON(IS_ERR(crtc_state) || ret);
5937
5938 dev_priv->display.crtc_disable(crtc_state, state);
5939
5940 drm_atomic_state_put(state);
5941
5942 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5943 crtc->base.id, crtc->name);
5944
5945 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5946 crtc->state->active = false;
5947 intel_crtc->active = false;
5948 crtc->enabled = false;
5949 crtc->state->connector_mask = 0;
5950 crtc->state->encoder_mask = 0;
5951
5952 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5953 encoder->base.crtc = NULL;
5954
5955 intel_fbc_disable(intel_crtc);
5956 intel_update_watermarks(intel_crtc);
5957 intel_disable_shared_dpll(intel_crtc);
5958
5959 domains = intel_crtc->enabled_power_domains;
5960 for_each_power_domain(domain, domains)
5961 intel_display_power_put(dev_priv, domain);
5962 intel_crtc->enabled_power_domains = 0;
5963
5964 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5965 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5966 }
5967
5968 /*
5969 * turn all crtc's off, but do not adjust state
5970 * This has to be paired with a call to intel_modeset_setup_hw_state.
5971 */
5972 int intel_display_suspend(struct drm_device *dev)
5973 {
5974 struct drm_i915_private *dev_priv = to_i915(dev);
5975 struct drm_atomic_state *state;
5976 int ret;
5977
5978 state = drm_atomic_helper_suspend(dev);
5979 ret = PTR_ERR_OR_ZERO(state);
5980 if (ret)
5981 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5982 else
5983 dev_priv->modeset_restore_state = state;
5984 return ret;
5985 }
5986
5987 void intel_encoder_destroy(struct drm_encoder *encoder)
5988 {
5989 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5990
5991 drm_encoder_cleanup(encoder);
5992 kfree(intel_encoder);
5993 }
5994
5995 /* Cross check the actual hw state with our own modeset state tracking (and it's
5996 * internal consistency). */
5997 static void intel_connector_verify_state(struct intel_connector *connector)
5998 {
5999 struct drm_crtc *crtc = connector->base.state->crtc;
6000
6001 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6002 connector->base.base.id,
6003 connector->base.name);
6004
6005 if (connector->get_hw_state(connector)) {
6006 struct intel_encoder *encoder = connector->encoder;
6007 struct drm_connector_state *conn_state = connector->base.state;
6008
6009 I915_STATE_WARN(!crtc,
6010 "connector enabled without attached crtc\n");
6011
6012 if (!crtc)
6013 return;
6014
6015 I915_STATE_WARN(!crtc->state->active,
6016 "connector is active, but attached crtc isn't\n");
6017
6018 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6019 return;
6020
6021 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6022 "atomic encoder doesn't match attached encoder\n");
6023
6024 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6025 "attached encoder crtc differs from connector crtc\n");
6026 } else {
6027 I915_STATE_WARN(crtc && crtc->state->active,
6028 "attached crtc is active, but connector isn't\n");
6029 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6030 "best encoder set without crtc!\n");
6031 }
6032 }
6033
6034 int intel_connector_init(struct intel_connector *connector)
6035 {
6036 drm_atomic_helper_connector_reset(&connector->base);
6037
6038 if (!connector->base.state)
6039 return -ENOMEM;
6040
6041 return 0;
6042 }
6043
6044 struct intel_connector *intel_connector_alloc(void)
6045 {
6046 struct intel_connector *connector;
6047
6048 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6049 if (!connector)
6050 return NULL;
6051
6052 if (intel_connector_init(connector) < 0) {
6053 kfree(connector);
6054 return NULL;
6055 }
6056
6057 return connector;
6058 }
6059
6060 /* Simple connector->get_hw_state implementation for encoders that support only
6061 * one connector and no cloning and hence the encoder state determines the state
6062 * of the connector. */
6063 bool intel_connector_get_hw_state(struct intel_connector *connector)
6064 {
6065 enum pipe pipe = 0;
6066 struct intel_encoder *encoder = connector->encoder;
6067
6068 return encoder->get_hw_state(encoder, &pipe);
6069 }
6070
6071 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6072 {
6073 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6074 return crtc_state->fdi_lanes;
6075
6076 return 0;
6077 }
6078
6079 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6080 struct intel_crtc_state *pipe_config)
6081 {
6082 struct drm_i915_private *dev_priv = to_i915(dev);
6083 struct drm_atomic_state *state = pipe_config->base.state;
6084 struct intel_crtc *other_crtc;
6085 struct intel_crtc_state *other_crtc_state;
6086
6087 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6088 pipe_name(pipe), pipe_config->fdi_lanes);
6089 if (pipe_config->fdi_lanes > 4) {
6090 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6091 pipe_name(pipe), pipe_config->fdi_lanes);
6092 return -EINVAL;
6093 }
6094
6095 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6096 if (pipe_config->fdi_lanes > 2) {
6097 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6098 pipe_config->fdi_lanes);
6099 return -EINVAL;
6100 } else {
6101 return 0;
6102 }
6103 }
6104
6105 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6106 return 0;
6107
6108 /* Ivybridge 3 pipe is really complicated */
6109 switch (pipe) {
6110 case PIPE_A:
6111 return 0;
6112 case PIPE_B:
6113 if (pipe_config->fdi_lanes <= 2)
6114 return 0;
6115
6116 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6117 other_crtc_state =
6118 intel_atomic_get_crtc_state(state, other_crtc);
6119 if (IS_ERR(other_crtc_state))
6120 return PTR_ERR(other_crtc_state);
6121
6122 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6123 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6124 pipe_name(pipe), pipe_config->fdi_lanes);
6125 return -EINVAL;
6126 }
6127 return 0;
6128 case PIPE_C:
6129 if (pipe_config->fdi_lanes > 2) {
6130 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6131 pipe_name(pipe), pipe_config->fdi_lanes);
6132 return -EINVAL;
6133 }
6134
6135 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6136 other_crtc_state =
6137 intel_atomic_get_crtc_state(state, other_crtc);
6138 if (IS_ERR(other_crtc_state))
6139 return PTR_ERR(other_crtc_state);
6140
6141 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6142 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6143 return -EINVAL;
6144 }
6145 return 0;
6146 default:
6147 BUG();
6148 }
6149 }
6150
6151 #define RETRY 1
6152 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6153 struct intel_crtc_state *pipe_config)
6154 {
6155 struct drm_device *dev = intel_crtc->base.dev;
6156 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6157 int lane, link_bw, fdi_dotclock, ret;
6158 bool needs_recompute = false;
6159
6160 retry:
6161 /* FDI is a binary signal running at ~2.7GHz, encoding
6162 * each output octet as 10 bits. The actual frequency
6163 * is stored as a divider into a 100MHz clock, and the
6164 * mode pixel clock is stored in units of 1KHz.
6165 * Hence the bw of each lane in terms of the mode signal
6166 * is:
6167 */
6168 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6169
6170 fdi_dotclock = adjusted_mode->crtc_clock;
6171
6172 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6173 pipe_config->pipe_bpp);
6174
6175 pipe_config->fdi_lanes = lane;
6176
6177 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6178 link_bw, &pipe_config->fdi_m_n);
6179
6180 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6181 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6182 pipe_config->pipe_bpp -= 2*3;
6183 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6184 pipe_config->pipe_bpp);
6185 needs_recompute = true;
6186 pipe_config->bw_constrained = true;
6187
6188 goto retry;
6189 }
6190
6191 if (needs_recompute)
6192 return RETRY;
6193
6194 return ret;
6195 }
6196
6197 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6198 struct intel_crtc_state *pipe_config)
6199 {
6200 if (pipe_config->pipe_bpp > 24)
6201 return false;
6202
6203 /* HSW can handle pixel rate up to cdclk? */
6204 if (IS_HASWELL(dev_priv))
6205 return true;
6206
6207 /*
6208 * We compare against max which means we must take
6209 * the increased cdclk requirement into account when
6210 * calculating the new cdclk.
6211 *
6212 * Should measure whether using a lower cdclk w/o IPS
6213 */
6214 return pipe_config->pixel_rate <=
6215 dev_priv->max_cdclk_freq * 95 / 100;
6216 }
6217
6218 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6219 struct intel_crtc_state *pipe_config)
6220 {
6221 struct drm_device *dev = crtc->base.dev;
6222 struct drm_i915_private *dev_priv = to_i915(dev);
6223
6224 pipe_config->ips_enabled = i915.enable_ips &&
6225 hsw_crtc_supports_ips(crtc) &&
6226 pipe_config_supports_ips(dev_priv, pipe_config);
6227 }
6228
6229 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6230 {
6231 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6232
6233 /* GDG double wide on either pipe, otherwise pipe A only */
6234 return INTEL_INFO(dev_priv)->gen < 4 &&
6235 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6236 }
6237
6238 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6239 {
6240 uint32_t pixel_rate;
6241
6242 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6243
6244 /*
6245 * We only use IF-ID interlacing. If we ever use
6246 * PF-ID we'll need to adjust the pixel_rate here.
6247 */
6248
6249 if (pipe_config->pch_pfit.enabled) {
6250 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6251 uint32_t pfit_size = pipe_config->pch_pfit.size;
6252
6253 pipe_w = pipe_config->pipe_src_w;
6254 pipe_h = pipe_config->pipe_src_h;
6255
6256 pfit_w = (pfit_size >> 16) & 0xFFFF;
6257 pfit_h = pfit_size & 0xFFFF;
6258 if (pipe_w < pfit_w)
6259 pipe_w = pfit_w;
6260 if (pipe_h < pfit_h)
6261 pipe_h = pfit_h;
6262
6263 if (WARN_ON(!pfit_w || !pfit_h))
6264 return pixel_rate;
6265
6266 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6267 pfit_w * pfit_h);
6268 }
6269
6270 return pixel_rate;
6271 }
6272
6273 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6274 {
6275 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6276
6277 if (HAS_GMCH_DISPLAY(dev_priv))
6278 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6279 crtc_state->pixel_rate =
6280 crtc_state->base.adjusted_mode.crtc_clock;
6281 else
6282 crtc_state->pixel_rate =
6283 ilk_pipe_pixel_rate(crtc_state);
6284 }
6285
6286 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6287 struct intel_crtc_state *pipe_config)
6288 {
6289 struct drm_device *dev = crtc->base.dev;
6290 struct drm_i915_private *dev_priv = to_i915(dev);
6291 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6292 int clock_limit = dev_priv->max_dotclk_freq;
6293
6294 if (INTEL_GEN(dev_priv) < 4) {
6295 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6296
6297 /*
6298 * Enable double wide mode when the dot clock
6299 * is > 90% of the (display) core speed.
6300 */
6301 if (intel_crtc_supports_double_wide(crtc) &&
6302 adjusted_mode->crtc_clock > clock_limit) {
6303 clock_limit = dev_priv->max_dotclk_freq;
6304 pipe_config->double_wide = true;
6305 }
6306 }
6307
6308 if (adjusted_mode->crtc_clock > clock_limit) {
6309 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6310 adjusted_mode->crtc_clock, clock_limit,
6311 yesno(pipe_config->double_wide));
6312 return -EINVAL;
6313 }
6314
6315 /*
6316 * Pipe horizontal size must be even in:
6317 * - DVO ganged mode
6318 * - LVDS dual channel mode
6319 * - Double wide pipe
6320 */
6321 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6322 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6323 pipe_config->pipe_src_w &= ~1;
6324
6325 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6326 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6327 */
6328 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6329 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6330 return -EINVAL;
6331
6332 intel_crtc_compute_pixel_rate(pipe_config);
6333
6334 if (HAS_IPS(dev_priv))
6335 hsw_compute_ips_config(crtc, pipe_config);
6336
6337 if (pipe_config->has_pch_encoder)
6338 return ironlake_fdi_compute_config(crtc, pipe_config);
6339
6340 return 0;
6341 }
6342
6343 static void
6344 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6345 {
6346 while (*num > DATA_LINK_M_N_MASK ||
6347 *den > DATA_LINK_M_N_MASK) {
6348 *num >>= 1;
6349 *den >>= 1;
6350 }
6351 }
6352
6353 static void compute_m_n(unsigned int m, unsigned int n,
6354 uint32_t *ret_m, uint32_t *ret_n)
6355 {
6356 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6357 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6358 intel_reduce_m_n_ratio(ret_m, ret_n);
6359 }
6360
6361 void
6362 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6363 int pixel_clock, int link_clock,
6364 struct intel_link_m_n *m_n)
6365 {
6366 m_n->tu = 64;
6367
6368 compute_m_n(bits_per_pixel * pixel_clock,
6369 link_clock * nlanes * 8,
6370 &m_n->gmch_m, &m_n->gmch_n);
6371
6372 compute_m_n(pixel_clock, link_clock,
6373 &m_n->link_m, &m_n->link_n);
6374 }
6375
6376 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6377 {
6378 if (i915.panel_use_ssc >= 0)
6379 return i915.panel_use_ssc != 0;
6380 return dev_priv->vbt.lvds_use_ssc
6381 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6382 }
6383
6384 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6385 {
6386 return (1 << dpll->n) << 16 | dpll->m2;
6387 }
6388
6389 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6390 {
6391 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6392 }
6393
6394 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6395 struct intel_crtc_state *crtc_state,
6396 struct dpll *reduced_clock)
6397 {
6398 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6399 u32 fp, fp2 = 0;
6400
6401 if (IS_PINEVIEW(dev_priv)) {
6402 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6403 if (reduced_clock)
6404 fp2 = pnv_dpll_compute_fp(reduced_clock);
6405 } else {
6406 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6407 if (reduced_clock)
6408 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6409 }
6410
6411 crtc_state->dpll_hw_state.fp0 = fp;
6412
6413 crtc->lowfreq_avail = false;
6414 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6415 reduced_clock) {
6416 crtc_state->dpll_hw_state.fp1 = fp2;
6417 crtc->lowfreq_avail = true;
6418 } else {
6419 crtc_state->dpll_hw_state.fp1 = fp;
6420 }
6421 }
6422
6423 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6424 pipe)
6425 {
6426 u32 reg_val;
6427
6428 /*
6429 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6430 * and set it to a reasonable value instead.
6431 */
6432 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6433 reg_val &= 0xffffff00;
6434 reg_val |= 0x00000030;
6435 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6436
6437 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6438 reg_val &= 0x8cffffff;
6439 reg_val = 0x8c000000;
6440 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6441
6442 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6443 reg_val &= 0xffffff00;
6444 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6445
6446 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6447 reg_val &= 0x00ffffff;
6448 reg_val |= 0xb0000000;
6449 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6450 }
6451
6452 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6453 struct intel_link_m_n *m_n)
6454 {
6455 struct drm_device *dev = crtc->base.dev;
6456 struct drm_i915_private *dev_priv = to_i915(dev);
6457 int pipe = crtc->pipe;
6458
6459 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6460 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6461 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6462 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6463 }
6464
6465 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6466 struct intel_link_m_n *m_n,
6467 struct intel_link_m_n *m2_n2)
6468 {
6469 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6470 int pipe = crtc->pipe;
6471 enum transcoder transcoder = crtc->config->cpu_transcoder;
6472
6473 if (INTEL_GEN(dev_priv) >= 5) {
6474 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6475 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6476 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6477 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6478 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6479 * for gen < 8) and if DRRS is supported (to make sure the
6480 * registers are not unnecessarily accessed).
6481 */
6482 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6483 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6484 I915_WRITE(PIPE_DATA_M2(transcoder),
6485 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6486 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6487 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6488 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6489 }
6490 } else {
6491 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6492 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6493 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6494 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6495 }
6496 }
6497
6498 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6499 {
6500 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6501
6502 if (m_n == M1_N1) {
6503 dp_m_n = &crtc->config->dp_m_n;
6504 dp_m2_n2 = &crtc->config->dp_m2_n2;
6505 } else if (m_n == M2_N2) {
6506
6507 /*
6508 * M2_N2 registers are not supported. Hence m2_n2 divider value
6509 * needs to be programmed into M1_N1.
6510 */
6511 dp_m_n = &crtc->config->dp_m2_n2;
6512 } else {
6513 DRM_ERROR("Unsupported divider value\n");
6514 return;
6515 }
6516
6517 if (crtc->config->has_pch_encoder)
6518 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6519 else
6520 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6521 }
6522
6523 static void vlv_compute_dpll(struct intel_crtc *crtc,
6524 struct intel_crtc_state *pipe_config)
6525 {
6526 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6527 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6528 if (crtc->pipe != PIPE_A)
6529 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6530
6531 /* DPLL not used with DSI, but still need the rest set up */
6532 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6533 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6534 DPLL_EXT_BUFFER_ENABLE_VLV;
6535
6536 pipe_config->dpll_hw_state.dpll_md =
6537 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6538 }
6539
6540 static void chv_compute_dpll(struct intel_crtc *crtc,
6541 struct intel_crtc_state *pipe_config)
6542 {
6543 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6544 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6545 if (crtc->pipe != PIPE_A)
6546 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6547
6548 /* DPLL not used with DSI, but still need the rest set up */
6549 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6550 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6551
6552 pipe_config->dpll_hw_state.dpll_md =
6553 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6554 }
6555
6556 static void vlv_prepare_pll(struct intel_crtc *crtc,
6557 const struct intel_crtc_state *pipe_config)
6558 {
6559 struct drm_device *dev = crtc->base.dev;
6560 struct drm_i915_private *dev_priv = to_i915(dev);
6561 enum pipe pipe = crtc->pipe;
6562 u32 mdiv;
6563 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6564 u32 coreclk, reg_val;
6565
6566 /* Enable Refclk */
6567 I915_WRITE(DPLL(pipe),
6568 pipe_config->dpll_hw_state.dpll &
6569 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6570
6571 /* No need to actually set up the DPLL with DSI */
6572 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6573 return;
6574
6575 mutex_lock(&dev_priv->sb_lock);
6576
6577 bestn = pipe_config->dpll.n;
6578 bestm1 = pipe_config->dpll.m1;
6579 bestm2 = pipe_config->dpll.m2;
6580 bestp1 = pipe_config->dpll.p1;
6581 bestp2 = pipe_config->dpll.p2;
6582
6583 /* See eDP HDMI DPIO driver vbios notes doc */
6584
6585 /* PLL B needs special handling */
6586 if (pipe == PIPE_B)
6587 vlv_pllb_recal_opamp(dev_priv, pipe);
6588
6589 /* Set up Tx target for periodic Rcomp update */
6590 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6591
6592 /* Disable target IRef on PLL */
6593 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6594 reg_val &= 0x00ffffff;
6595 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6596
6597 /* Disable fast lock */
6598 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6599
6600 /* Set idtafcrecal before PLL is enabled */
6601 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6602 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6603 mdiv |= ((bestn << DPIO_N_SHIFT));
6604 mdiv |= (1 << DPIO_K_SHIFT);
6605
6606 /*
6607 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6608 * but we don't support that).
6609 * Note: don't use the DAC post divider as it seems unstable.
6610 */
6611 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6612 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6613
6614 mdiv |= DPIO_ENABLE_CALIBRATION;
6615 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6616
6617 /* Set HBR and RBR LPF coefficients */
6618 if (pipe_config->port_clock == 162000 ||
6619 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6620 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6621 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6622 0x009f0003);
6623 else
6624 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6625 0x00d0000f);
6626
6627 if (intel_crtc_has_dp_encoder(pipe_config)) {
6628 /* Use SSC source */
6629 if (pipe == PIPE_A)
6630 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6631 0x0df40000);
6632 else
6633 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6634 0x0df70000);
6635 } else { /* HDMI or VGA */
6636 /* Use bend source */
6637 if (pipe == PIPE_A)
6638 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6639 0x0df70000);
6640 else
6641 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6642 0x0df40000);
6643 }
6644
6645 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6646 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6647 if (intel_crtc_has_dp_encoder(crtc->config))
6648 coreclk |= 0x01000000;
6649 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6650
6651 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6652 mutex_unlock(&dev_priv->sb_lock);
6653 }
6654
6655 static void chv_prepare_pll(struct intel_crtc *crtc,
6656 const struct intel_crtc_state *pipe_config)
6657 {
6658 struct drm_device *dev = crtc->base.dev;
6659 struct drm_i915_private *dev_priv = to_i915(dev);
6660 enum pipe pipe = crtc->pipe;
6661 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6662 u32 loopfilter, tribuf_calcntr;
6663 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6664 u32 dpio_val;
6665 int vco;
6666
6667 /* Enable Refclk and SSC */
6668 I915_WRITE(DPLL(pipe),
6669 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6670
6671 /* No need to actually set up the DPLL with DSI */
6672 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6673 return;
6674
6675 bestn = pipe_config->dpll.n;
6676 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6677 bestm1 = pipe_config->dpll.m1;
6678 bestm2 = pipe_config->dpll.m2 >> 22;
6679 bestp1 = pipe_config->dpll.p1;
6680 bestp2 = pipe_config->dpll.p2;
6681 vco = pipe_config->dpll.vco;
6682 dpio_val = 0;
6683 loopfilter = 0;
6684
6685 mutex_lock(&dev_priv->sb_lock);
6686
6687 /* p1 and p2 divider */
6688 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6689 5 << DPIO_CHV_S1_DIV_SHIFT |
6690 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6691 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6692 1 << DPIO_CHV_K_DIV_SHIFT);
6693
6694 /* Feedback post-divider - m2 */
6695 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6696
6697 /* Feedback refclk divider - n and m1 */
6698 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6699 DPIO_CHV_M1_DIV_BY_2 |
6700 1 << DPIO_CHV_N_DIV_SHIFT);
6701
6702 /* M2 fraction division */
6703 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6704
6705 /* M2 fraction division enable */
6706 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6707 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6708 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6709 if (bestm2_frac)
6710 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6711 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6712
6713 /* Program digital lock detect threshold */
6714 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6715 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6716 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6717 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6718 if (!bestm2_frac)
6719 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6720 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6721
6722 /* Loop filter */
6723 if (vco == 5400000) {
6724 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6725 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6726 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6727 tribuf_calcntr = 0x9;
6728 } else if (vco <= 6200000) {
6729 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6730 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6731 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6732 tribuf_calcntr = 0x9;
6733 } else if (vco <= 6480000) {
6734 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6735 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6736 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6737 tribuf_calcntr = 0x8;
6738 } else {
6739 /* Not supported. Apply the same limits as in the max case */
6740 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6741 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6742 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6743 tribuf_calcntr = 0;
6744 }
6745 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6746
6747 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6748 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6749 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6750 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6751
6752 /* AFC Recal */
6753 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6754 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6755 DPIO_AFC_RECAL);
6756
6757 mutex_unlock(&dev_priv->sb_lock);
6758 }
6759
6760 /**
6761 * vlv_force_pll_on - forcibly enable just the PLL
6762 * @dev_priv: i915 private structure
6763 * @pipe: pipe PLL to enable
6764 * @dpll: PLL configuration
6765 *
6766 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6767 * in cases where we need the PLL enabled even when @pipe is not going to
6768 * be enabled.
6769 */
6770 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6771 const struct dpll *dpll)
6772 {
6773 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6774 struct intel_crtc_state *pipe_config;
6775
6776 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6777 if (!pipe_config)
6778 return -ENOMEM;
6779
6780 pipe_config->base.crtc = &crtc->base;
6781 pipe_config->pixel_multiplier = 1;
6782 pipe_config->dpll = *dpll;
6783
6784 if (IS_CHERRYVIEW(dev_priv)) {
6785 chv_compute_dpll(crtc, pipe_config);
6786 chv_prepare_pll(crtc, pipe_config);
6787 chv_enable_pll(crtc, pipe_config);
6788 } else {
6789 vlv_compute_dpll(crtc, pipe_config);
6790 vlv_prepare_pll(crtc, pipe_config);
6791 vlv_enable_pll(crtc, pipe_config);
6792 }
6793
6794 kfree(pipe_config);
6795
6796 return 0;
6797 }
6798
6799 /**
6800 * vlv_force_pll_off - forcibly disable just the PLL
6801 * @dev_priv: i915 private structure
6802 * @pipe: pipe PLL to disable
6803 *
6804 * Disable the PLL for @pipe. To be used in cases where we need
6805 * the PLL enabled even when @pipe is not going to be enabled.
6806 */
6807 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6808 {
6809 if (IS_CHERRYVIEW(dev_priv))
6810 chv_disable_pll(dev_priv, pipe);
6811 else
6812 vlv_disable_pll(dev_priv, pipe);
6813 }
6814
6815 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6816 struct intel_crtc_state *crtc_state,
6817 struct dpll *reduced_clock)
6818 {
6819 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6820 u32 dpll;
6821 struct dpll *clock = &crtc_state->dpll;
6822
6823 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6824
6825 dpll = DPLL_VGA_MODE_DIS;
6826
6827 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6828 dpll |= DPLLB_MODE_LVDS;
6829 else
6830 dpll |= DPLLB_MODE_DAC_SERIAL;
6831
6832 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6833 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6834 dpll |= (crtc_state->pixel_multiplier - 1)
6835 << SDVO_MULTIPLIER_SHIFT_HIRES;
6836 }
6837
6838 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6839 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6840 dpll |= DPLL_SDVO_HIGH_SPEED;
6841
6842 if (intel_crtc_has_dp_encoder(crtc_state))
6843 dpll |= DPLL_SDVO_HIGH_SPEED;
6844
6845 /* compute bitmask from p1 value */
6846 if (IS_PINEVIEW(dev_priv))
6847 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6848 else {
6849 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6850 if (IS_G4X(dev_priv) && reduced_clock)
6851 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6852 }
6853 switch (clock->p2) {
6854 case 5:
6855 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6856 break;
6857 case 7:
6858 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6859 break;
6860 case 10:
6861 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6862 break;
6863 case 14:
6864 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6865 break;
6866 }
6867 if (INTEL_GEN(dev_priv) >= 4)
6868 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6869
6870 if (crtc_state->sdvo_tv_clock)
6871 dpll |= PLL_REF_INPUT_TVCLKINBC;
6872 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6873 intel_panel_use_ssc(dev_priv))
6874 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6875 else
6876 dpll |= PLL_REF_INPUT_DREFCLK;
6877
6878 dpll |= DPLL_VCO_ENABLE;
6879 crtc_state->dpll_hw_state.dpll = dpll;
6880
6881 if (INTEL_GEN(dev_priv) >= 4) {
6882 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6883 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6884 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6885 }
6886 }
6887
6888 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6889 struct intel_crtc_state *crtc_state,
6890 struct dpll *reduced_clock)
6891 {
6892 struct drm_device *dev = crtc->base.dev;
6893 struct drm_i915_private *dev_priv = to_i915(dev);
6894 u32 dpll;
6895 struct dpll *clock = &crtc_state->dpll;
6896
6897 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6898
6899 dpll = DPLL_VGA_MODE_DIS;
6900
6901 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6902 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6903 } else {
6904 if (clock->p1 == 2)
6905 dpll |= PLL_P1_DIVIDE_BY_TWO;
6906 else
6907 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6908 if (clock->p2 == 4)
6909 dpll |= PLL_P2_DIVIDE_BY_4;
6910 }
6911
6912 if (!IS_I830(dev_priv) &&
6913 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6914 dpll |= DPLL_DVO_2X_MODE;
6915
6916 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6917 intel_panel_use_ssc(dev_priv))
6918 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6919 else
6920 dpll |= PLL_REF_INPUT_DREFCLK;
6921
6922 dpll |= DPLL_VCO_ENABLE;
6923 crtc_state->dpll_hw_state.dpll = dpll;
6924 }
6925
6926 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6927 {
6928 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6929 enum pipe pipe = intel_crtc->pipe;
6930 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6931 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6932 uint32_t crtc_vtotal, crtc_vblank_end;
6933 int vsyncshift = 0;
6934
6935 /* We need to be careful not to changed the adjusted mode, for otherwise
6936 * the hw state checker will get angry at the mismatch. */
6937 crtc_vtotal = adjusted_mode->crtc_vtotal;
6938 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6939
6940 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6941 /* the chip adds 2 halflines automatically */
6942 crtc_vtotal -= 1;
6943 crtc_vblank_end -= 1;
6944
6945 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6946 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6947 else
6948 vsyncshift = adjusted_mode->crtc_hsync_start -
6949 adjusted_mode->crtc_htotal / 2;
6950 if (vsyncshift < 0)
6951 vsyncshift += adjusted_mode->crtc_htotal;
6952 }
6953
6954 if (INTEL_GEN(dev_priv) > 3)
6955 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6956
6957 I915_WRITE(HTOTAL(cpu_transcoder),
6958 (adjusted_mode->crtc_hdisplay - 1) |
6959 ((adjusted_mode->crtc_htotal - 1) << 16));
6960 I915_WRITE(HBLANK(cpu_transcoder),
6961 (adjusted_mode->crtc_hblank_start - 1) |
6962 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6963 I915_WRITE(HSYNC(cpu_transcoder),
6964 (adjusted_mode->crtc_hsync_start - 1) |
6965 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6966
6967 I915_WRITE(VTOTAL(cpu_transcoder),
6968 (adjusted_mode->crtc_vdisplay - 1) |
6969 ((crtc_vtotal - 1) << 16));
6970 I915_WRITE(VBLANK(cpu_transcoder),
6971 (adjusted_mode->crtc_vblank_start - 1) |
6972 ((crtc_vblank_end - 1) << 16));
6973 I915_WRITE(VSYNC(cpu_transcoder),
6974 (adjusted_mode->crtc_vsync_start - 1) |
6975 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6976
6977 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6978 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6979 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6980 * bits. */
6981 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6982 (pipe == PIPE_B || pipe == PIPE_C))
6983 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6984
6985 }
6986
6987 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6988 {
6989 struct drm_device *dev = intel_crtc->base.dev;
6990 struct drm_i915_private *dev_priv = to_i915(dev);
6991 enum pipe pipe = intel_crtc->pipe;
6992
6993 /* pipesrc controls the size that is scaled from, which should
6994 * always be the user's requested size.
6995 */
6996 I915_WRITE(PIPESRC(pipe),
6997 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6998 (intel_crtc->config->pipe_src_h - 1));
6999 }
7000
7001 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7002 struct intel_crtc_state *pipe_config)
7003 {
7004 struct drm_device *dev = crtc->base.dev;
7005 struct drm_i915_private *dev_priv = to_i915(dev);
7006 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7007 uint32_t tmp;
7008
7009 tmp = I915_READ(HTOTAL(cpu_transcoder));
7010 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7011 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7012 tmp = I915_READ(HBLANK(cpu_transcoder));
7013 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7014 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7015 tmp = I915_READ(HSYNC(cpu_transcoder));
7016 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7017 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7018
7019 tmp = I915_READ(VTOTAL(cpu_transcoder));
7020 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7021 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7022 tmp = I915_READ(VBLANK(cpu_transcoder));
7023 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7024 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7025 tmp = I915_READ(VSYNC(cpu_transcoder));
7026 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7027 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7028
7029 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7030 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7031 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7032 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7033 }
7034 }
7035
7036 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7037 struct intel_crtc_state *pipe_config)
7038 {
7039 struct drm_device *dev = crtc->base.dev;
7040 struct drm_i915_private *dev_priv = to_i915(dev);
7041 u32 tmp;
7042
7043 tmp = I915_READ(PIPESRC(crtc->pipe));
7044 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7045 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7046
7047 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7048 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7049 }
7050
7051 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7052 struct intel_crtc_state *pipe_config)
7053 {
7054 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7055 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7056 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7057 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7058
7059 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7060 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7061 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7062 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7063
7064 mode->flags = pipe_config->base.adjusted_mode.flags;
7065 mode->type = DRM_MODE_TYPE_DRIVER;
7066
7067 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7068
7069 mode->hsync = drm_mode_hsync(mode);
7070 mode->vrefresh = drm_mode_vrefresh(mode);
7071 drm_mode_set_name(mode);
7072 }
7073
7074 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7075 {
7076 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7077 uint32_t pipeconf;
7078
7079 pipeconf = 0;
7080
7081 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7082 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7083 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7084
7085 if (intel_crtc->config->double_wide)
7086 pipeconf |= PIPECONF_DOUBLE_WIDE;
7087
7088 /* only g4x and later have fancy bpc/dither controls */
7089 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7090 IS_CHERRYVIEW(dev_priv)) {
7091 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7092 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7093 pipeconf |= PIPECONF_DITHER_EN |
7094 PIPECONF_DITHER_TYPE_SP;
7095
7096 switch (intel_crtc->config->pipe_bpp) {
7097 case 18:
7098 pipeconf |= PIPECONF_6BPC;
7099 break;
7100 case 24:
7101 pipeconf |= PIPECONF_8BPC;
7102 break;
7103 case 30:
7104 pipeconf |= PIPECONF_10BPC;
7105 break;
7106 default:
7107 /* Case prevented by intel_choose_pipe_bpp_dither. */
7108 BUG();
7109 }
7110 }
7111
7112 if (HAS_PIPE_CXSR(dev_priv)) {
7113 if (intel_crtc->lowfreq_avail) {
7114 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7115 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7116 } else {
7117 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7118 }
7119 }
7120
7121 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7122 if (INTEL_GEN(dev_priv) < 4 ||
7123 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7124 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7125 else
7126 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7127 } else
7128 pipeconf |= PIPECONF_PROGRESSIVE;
7129
7130 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7131 intel_crtc->config->limited_color_range)
7132 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7133
7134 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7135 POSTING_READ(PIPECONF(intel_crtc->pipe));
7136 }
7137
7138 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7139 struct intel_crtc_state *crtc_state)
7140 {
7141 struct drm_device *dev = crtc->base.dev;
7142 struct drm_i915_private *dev_priv = to_i915(dev);
7143 const struct intel_limit *limit;
7144 int refclk = 48000;
7145
7146 memset(&crtc_state->dpll_hw_state, 0,
7147 sizeof(crtc_state->dpll_hw_state));
7148
7149 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7150 if (intel_panel_use_ssc(dev_priv)) {
7151 refclk = dev_priv->vbt.lvds_ssc_freq;
7152 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7153 }
7154
7155 limit = &intel_limits_i8xx_lvds;
7156 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7157 limit = &intel_limits_i8xx_dvo;
7158 } else {
7159 limit = &intel_limits_i8xx_dac;
7160 }
7161
7162 if (!crtc_state->clock_set &&
7163 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7164 refclk, NULL, &crtc_state->dpll)) {
7165 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7166 return -EINVAL;
7167 }
7168
7169 i8xx_compute_dpll(crtc, crtc_state, NULL);
7170
7171 return 0;
7172 }
7173
7174 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7175 struct intel_crtc_state *crtc_state)
7176 {
7177 struct drm_device *dev = crtc->base.dev;
7178 struct drm_i915_private *dev_priv = to_i915(dev);
7179 const struct intel_limit *limit;
7180 int refclk = 96000;
7181
7182 memset(&crtc_state->dpll_hw_state, 0,
7183 sizeof(crtc_state->dpll_hw_state));
7184
7185 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7186 if (intel_panel_use_ssc(dev_priv)) {
7187 refclk = dev_priv->vbt.lvds_ssc_freq;
7188 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7189 }
7190
7191 if (intel_is_dual_link_lvds(dev))
7192 limit = &intel_limits_g4x_dual_channel_lvds;
7193 else
7194 limit = &intel_limits_g4x_single_channel_lvds;
7195 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7196 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7197 limit = &intel_limits_g4x_hdmi;
7198 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7199 limit = &intel_limits_g4x_sdvo;
7200 } else {
7201 /* The option is for other outputs */
7202 limit = &intel_limits_i9xx_sdvo;
7203 }
7204
7205 if (!crtc_state->clock_set &&
7206 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7207 refclk, NULL, &crtc_state->dpll)) {
7208 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7209 return -EINVAL;
7210 }
7211
7212 i9xx_compute_dpll(crtc, crtc_state, NULL);
7213
7214 return 0;
7215 }
7216
7217 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7218 struct intel_crtc_state *crtc_state)
7219 {
7220 struct drm_device *dev = crtc->base.dev;
7221 struct drm_i915_private *dev_priv = to_i915(dev);
7222 const struct intel_limit *limit;
7223 int refclk = 96000;
7224
7225 memset(&crtc_state->dpll_hw_state, 0,
7226 sizeof(crtc_state->dpll_hw_state));
7227
7228 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7229 if (intel_panel_use_ssc(dev_priv)) {
7230 refclk = dev_priv->vbt.lvds_ssc_freq;
7231 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7232 }
7233
7234 limit = &intel_limits_pineview_lvds;
7235 } else {
7236 limit = &intel_limits_pineview_sdvo;
7237 }
7238
7239 if (!crtc_state->clock_set &&
7240 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7241 refclk, NULL, &crtc_state->dpll)) {
7242 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7243 return -EINVAL;
7244 }
7245
7246 i9xx_compute_dpll(crtc, crtc_state, NULL);
7247
7248 return 0;
7249 }
7250
7251 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7252 struct intel_crtc_state *crtc_state)
7253 {
7254 struct drm_device *dev = crtc->base.dev;
7255 struct drm_i915_private *dev_priv = to_i915(dev);
7256 const struct intel_limit *limit;
7257 int refclk = 96000;
7258
7259 memset(&crtc_state->dpll_hw_state, 0,
7260 sizeof(crtc_state->dpll_hw_state));
7261
7262 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7263 if (intel_panel_use_ssc(dev_priv)) {
7264 refclk = dev_priv->vbt.lvds_ssc_freq;
7265 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7266 }
7267
7268 limit = &intel_limits_i9xx_lvds;
7269 } else {
7270 limit = &intel_limits_i9xx_sdvo;
7271 }
7272
7273 if (!crtc_state->clock_set &&
7274 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7275 refclk, NULL, &crtc_state->dpll)) {
7276 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7277 return -EINVAL;
7278 }
7279
7280 i9xx_compute_dpll(crtc, crtc_state, NULL);
7281
7282 return 0;
7283 }
7284
7285 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7286 struct intel_crtc_state *crtc_state)
7287 {
7288 int refclk = 100000;
7289 const struct intel_limit *limit = &intel_limits_chv;
7290
7291 memset(&crtc_state->dpll_hw_state, 0,
7292 sizeof(crtc_state->dpll_hw_state));
7293
7294 if (!crtc_state->clock_set &&
7295 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7296 refclk, NULL, &crtc_state->dpll)) {
7297 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7298 return -EINVAL;
7299 }
7300
7301 chv_compute_dpll(crtc, crtc_state);
7302
7303 return 0;
7304 }
7305
7306 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7307 struct intel_crtc_state *crtc_state)
7308 {
7309 int refclk = 100000;
7310 const struct intel_limit *limit = &intel_limits_vlv;
7311
7312 memset(&crtc_state->dpll_hw_state, 0,
7313 sizeof(crtc_state->dpll_hw_state));
7314
7315 if (!crtc_state->clock_set &&
7316 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7317 refclk, NULL, &crtc_state->dpll)) {
7318 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7319 return -EINVAL;
7320 }
7321
7322 vlv_compute_dpll(crtc, crtc_state);
7323
7324 return 0;
7325 }
7326
7327 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7328 struct intel_crtc_state *pipe_config)
7329 {
7330 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7331 uint32_t tmp;
7332
7333 if (INTEL_GEN(dev_priv) <= 3 &&
7334 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7335 return;
7336
7337 tmp = I915_READ(PFIT_CONTROL);
7338 if (!(tmp & PFIT_ENABLE))
7339 return;
7340
7341 /* Check whether the pfit is attached to our pipe. */
7342 if (INTEL_GEN(dev_priv) < 4) {
7343 if (crtc->pipe != PIPE_B)
7344 return;
7345 } else {
7346 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7347 return;
7348 }
7349
7350 pipe_config->gmch_pfit.control = tmp;
7351 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7352 }
7353
7354 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7355 struct intel_crtc_state *pipe_config)
7356 {
7357 struct drm_device *dev = crtc->base.dev;
7358 struct drm_i915_private *dev_priv = to_i915(dev);
7359 int pipe = pipe_config->cpu_transcoder;
7360 struct dpll clock;
7361 u32 mdiv;
7362 int refclk = 100000;
7363
7364 /* In case of DSI, DPLL will not be used */
7365 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7366 return;
7367
7368 mutex_lock(&dev_priv->sb_lock);
7369 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7370 mutex_unlock(&dev_priv->sb_lock);
7371
7372 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7373 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7374 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7375 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7376 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7377
7378 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7379 }
7380
7381 static void
7382 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7383 struct intel_initial_plane_config *plane_config)
7384 {
7385 struct drm_device *dev = crtc->base.dev;
7386 struct drm_i915_private *dev_priv = to_i915(dev);
7387 u32 val, base, offset;
7388 int pipe = crtc->pipe, plane = crtc->plane;
7389 int fourcc, pixel_format;
7390 unsigned int aligned_height;
7391 struct drm_framebuffer *fb;
7392 struct intel_framebuffer *intel_fb;
7393
7394 val = I915_READ(DSPCNTR(plane));
7395 if (!(val & DISPLAY_PLANE_ENABLE))
7396 return;
7397
7398 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7399 if (!intel_fb) {
7400 DRM_DEBUG_KMS("failed to alloc fb\n");
7401 return;
7402 }
7403
7404 fb = &intel_fb->base;
7405
7406 fb->dev = dev;
7407
7408 if (INTEL_GEN(dev_priv) >= 4) {
7409 if (val & DISPPLANE_TILED) {
7410 plane_config->tiling = I915_TILING_X;
7411 fb->modifier = I915_FORMAT_MOD_X_TILED;
7412 }
7413 }
7414
7415 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7416 fourcc = i9xx_format_to_fourcc(pixel_format);
7417 fb->format = drm_format_info(fourcc);
7418
7419 if (INTEL_GEN(dev_priv) >= 4) {
7420 if (plane_config->tiling)
7421 offset = I915_READ(DSPTILEOFF(plane));
7422 else
7423 offset = I915_READ(DSPLINOFF(plane));
7424 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7425 } else {
7426 base = I915_READ(DSPADDR(plane));
7427 }
7428 plane_config->base = base;
7429
7430 val = I915_READ(PIPESRC(pipe));
7431 fb->width = ((val >> 16) & 0xfff) + 1;
7432 fb->height = ((val >> 0) & 0xfff) + 1;
7433
7434 val = I915_READ(DSPSTRIDE(pipe));
7435 fb->pitches[0] = val & 0xffffffc0;
7436
7437 aligned_height = intel_fb_align_height(dev, fb->height,
7438 fb->format->format,
7439 fb->modifier);
7440
7441 plane_config->size = fb->pitches[0] * aligned_height;
7442
7443 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7444 pipe_name(pipe), plane, fb->width, fb->height,
7445 fb->format->cpp[0] * 8, base, fb->pitches[0],
7446 plane_config->size);
7447
7448 plane_config->fb = intel_fb;
7449 }
7450
7451 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7452 struct intel_crtc_state *pipe_config)
7453 {
7454 struct drm_device *dev = crtc->base.dev;
7455 struct drm_i915_private *dev_priv = to_i915(dev);
7456 int pipe = pipe_config->cpu_transcoder;
7457 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7458 struct dpll clock;
7459 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7460 int refclk = 100000;
7461
7462 /* In case of DSI, DPLL will not be used */
7463 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7464 return;
7465
7466 mutex_lock(&dev_priv->sb_lock);
7467 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7468 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7469 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7470 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7471 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7472 mutex_unlock(&dev_priv->sb_lock);
7473
7474 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7475 clock.m2 = (pll_dw0 & 0xff) << 22;
7476 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7477 clock.m2 |= pll_dw2 & 0x3fffff;
7478 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7479 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7480 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7481
7482 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7483 }
7484
7485 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7486 struct intel_crtc_state *pipe_config)
7487 {
7488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7489 enum intel_display_power_domain power_domain;
7490 uint32_t tmp;
7491 bool ret;
7492
7493 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7494 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7495 return false;
7496
7497 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7498 pipe_config->shared_dpll = NULL;
7499
7500 ret = false;
7501
7502 tmp = I915_READ(PIPECONF(crtc->pipe));
7503 if (!(tmp & PIPECONF_ENABLE))
7504 goto out;
7505
7506 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7507 IS_CHERRYVIEW(dev_priv)) {
7508 switch (tmp & PIPECONF_BPC_MASK) {
7509 case PIPECONF_6BPC:
7510 pipe_config->pipe_bpp = 18;
7511 break;
7512 case PIPECONF_8BPC:
7513 pipe_config->pipe_bpp = 24;
7514 break;
7515 case PIPECONF_10BPC:
7516 pipe_config->pipe_bpp = 30;
7517 break;
7518 default:
7519 break;
7520 }
7521 }
7522
7523 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7524 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7525 pipe_config->limited_color_range = true;
7526
7527 if (INTEL_GEN(dev_priv) < 4)
7528 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7529
7530 intel_get_pipe_timings(crtc, pipe_config);
7531 intel_get_pipe_src_size(crtc, pipe_config);
7532
7533 i9xx_get_pfit_config(crtc, pipe_config);
7534
7535 if (INTEL_GEN(dev_priv) >= 4) {
7536 /* No way to read it out on pipes B and C */
7537 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7538 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7539 else
7540 tmp = I915_READ(DPLL_MD(crtc->pipe));
7541 pipe_config->pixel_multiplier =
7542 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7543 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7544 pipe_config->dpll_hw_state.dpll_md = tmp;
7545 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7546 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7547 tmp = I915_READ(DPLL(crtc->pipe));
7548 pipe_config->pixel_multiplier =
7549 ((tmp & SDVO_MULTIPLIER_MASK)
7550 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7551 } else {
7552 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7553 * port and will be fixed up in the encoder->get_config
7554 * function. */
7555 pipe_config->pixel_multiplier = 1;
7556 }
7557 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7558 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7559 /*
7560 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7561 * on 830. Filter it out here so that we don't
7562 * report errors due to that.
7563 */
7564 if (IS_I830(dev_priv))
7565 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7566
7567 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7568 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7569 } else {
7570 /* Mask out read-only status bits. */
7571 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7572 DPLL_PORTC_READY_MASK |
7573 DPLL_PORTB_READY_MASK);
7574 }
7575
7576 if (IS_CHERRYVIEW(dev_priv))
7577 chv_crtc_clock_get(crtc, pipe_config);
7578 else if (IS_VALLEYVIEW(dev_priv))
7579 vlv_crtc_clock_get(crtc, pipe_config);
7580 else
7581 i9xx_crtc_clock_get(crtc, pipe_config);
7582
7583 /*
7584 * Normally the dotclock is filled in by the encoder .get_config()
7585 * but in case the pipe is enabled w/o any ports we need a sane
7586 * default.
7587 */
7588 pipe_config->base.adjusted_mode.crtc_clock =
7589 pipe_config->port_clock / pipe_config->pixel_multiplier;
7590
7591 ret = true;
7592
7593 out:
7594 intel_display_power_put(dev_priv, power_domain);
7595
7596 return ret;
7597 }
7598
7599 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7600 {
7601 struct intel_encoder *encoder;
7602 int i;
7603 u32 val, final;
7604 bool has_lvds = false;
7605 bool has_cpu_edp = false;
7606 bool has_panel = false;
7607 bool has_ck505 = false;
7608 bool can_ssc = false;
7609 bool using_ssc_source = false;
7610
7611 /* We need to take the global config into account */
7612 for_each_intel_encoder(&dev_priv->drm, encoder) {
7613 switch (encoder->type) {
7614 case INTEL_OUTPUT_LVDS:
7615 has_panel = true;
7616 has_lvds = true;
7617 break;
7618 case INTEL_OUTPUT_EDP:
7619 has_panel = true;
7620 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7621 has_cpu_edp = true;
7622 break;
7623 default:
7624 break;
7625 }
7626 }
7627
7628 if (HAS_PCH_IBX(dev_priv)) {
7629 has_ck505 = dev_priv->vbt.display_clock_mode;
7630 can_ssc = has_ck505;
7631 } else {
7632 has_ck505 = false;
7633 can_ssc = true;
7634 }
7635
7636 /* Check if any DPLLs are using the SSC source */
7637 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7638 u32 temp = I915_READ(PCH_DPLL(i));
7639
7640 if (!(temp & DPLL_VCO_ENABLE))
7641 continue;
7642
7643 if ((temp & PLL_REF_INPUT_MASK) ==
7644 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7645 using_ssc_source = true;
7646 break;
7647 }
7648 }
7649
7650 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7651 has_panel, has_lvds, has_ck505, using_ssc_source);
7652
7653 /* Ironlake: try to setup display ref clock before DPLL
7654 * enabling. This is only under driver's control after
7655 * PCH B stepping, previous chipset stepping should be
7656 * ignoring this setting.
7657 */
7658 val = I915_READ(PCH_DREF_CONTROL);
7659
7660 /* As we must carefully and slowly disable/enable each source in turn,
7661 * compute the final state we want first and check if we need to
7662 * make any changes at all.
7663 */
7664 final = val;
7665 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7666 if (has_ck505)
7667 final |= DREF_NONSPREAD_CK505_ENABLE;
7668 else
7669 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7670
7671 final &= ~DREF_SSC_SOURCE_MASK;
7672 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7673 final &= ~DREF_SSC1_ENABLE;
7674
7675 if (has_panel) {
7676 final |= DREF_SSC_SOURCE_ENABLE;
7677
7678 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7679 final |= DREF_SSC1_ENABLE;
7680
7681 if (has_cpu_edp) {
7682 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7683 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7684 else
7685 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7686 } else
7687 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7688 } else if (using_ssc_source) {
7689 final |= DREF_SSC_SOURCE_ENABLE;
7690 final |= DREF_SSC1_ENABLE;
7691 }
7692
7693 if (final == val)
7694 return;
7695
7696 /* Always enable nonspread source */
7697 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7698
7699 if (has_ck505)
7700 val |= DREF_NONSPREAD_CK505_ENABLE;
7701 else
7702 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7703
7704 if (has_panel) {
7705 val &= ~DREF_SSC_SOURCE_MASK;
7706 val |= DREF_SSC_SOURCE_ENABLE;
7707
7708 /* SSC must be turned on before enabling the CPU output */
7709 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7710 DRM_DEBUG_KMS("Using SSC on panel\n");
7711 val |= DREF_SSC1_ENABLE;
7712 } else
7713 val &= ~DREF_SSC1_ENABLE;
7714
7715 /* Get SSC going before enabling the outputs */
7716 I915_WRITE(PCH_DREF_CONTROL, val);
7717 POSTING_READ(PCH_DREF_CONTROL);
7718 udelay(200);
7719
7720 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7721
7722 /* Enable CPU source on CPU attached eDP */
7723 if (has_cpu_edp) {
7724 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7725 DRM_DEBUG_KMS("Using SSC on eDP\n");
7726 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7727 } else
7728 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7729 } else
7730 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7731
7732 I915_WRITE(PCH_DREF_CONTROL, val);
7733 POSTING_READ(PCH_DREF_CONTROL);
7734 udelay(200);
7735 } else {
7736 DRM_DEBUG_KMS("Disabling CPU source output\n");
7737
7738 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7739
7740 /* Turn off CPU output */
7741 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7742
7743 I915_WRITE(PCH_DREF_CONTROL, val);
7744 POSTING_READ(PCH_DREF_CONTROL);
7745 udelay(200);
7746
7747 if (!using_ssc_source) {
7748 DRM_DEBUG_KMS("Disabling SSC source\n");
7749
7750 /* Turn off the SSC source */
7751 val &= ~DREF_SSC_SOURCE_MASK;
7752 val |= DREF_SSC_SOURCE_DISABLE;
7753
7754 /* Turn off SSC1 */
7755 val &= ~DREF_SSC1_ENABLE;
7756
7757 I915_WRITE(PCH_DREF_CONTROL, val);
7758 POSTING_READ(PCH_DREF_CONTROL);
7759 udelay(200);
7760 }
7761 }
7762
7763 BUG_ON(val != final);
7764 }
7765
7766 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7767 {
7768 uint32_t tmp;
7769
7770 tmp = I915_READ(SOUTH_CHICKEN2);
7771 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7772 I915_WRITE(SOUTH_CHICKEN2, tmp);
7773
7774 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7775 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7776 DRM_ERROR("FDI mPHY reset assert timeout\n");
7777
7778 tmp = I915_READ(SOUTH_CHICKEN2);
7779 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7780 I915_WRITE(SOUTH_CHICKEN2, tmp);
7781
7782 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7783 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7784 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7785 }
7786
7787 /* WaMPhyProgramming:hsw */
7788 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7789 {
7790 uint32_t tmp;
7791
7792 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7793 tmp &= ~(0xFF << 24);
7794 tmp |= (0x12 << 24);
7795 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7796
7797 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7798 tmp |= (1 << 11);
7799 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7800
7801 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7802 tmp |= (1 << 11);
7803 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7804
7805 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7806 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7807 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7808
7809 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7810 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7811 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7812
7813 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7814 tmp &= ~(7 << 13);
7815 tmp |= (5 << 13);
7816 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7817
7818 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7819 tmp &= ~(7 << 13);
7820 tmp |= (5 << 13);
7821 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7822
7823 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7824 tmp &= ~0xFF;
7825 tmp |= 0x1C;
7826 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7827
7828 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7829 tmp &= ~0xFF;
7830 tmp |= 0x1C;
7831 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7832
7833 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7834 tmp &= ~(0xFF << 16);
7835 tmp |= (0x1C << 16);
7836 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7837
7838 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7839 tmp &= ~(0xFF << 16);
7840 tmp |= (0x1C << 16);
7841 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7842
7843 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7844 tmp |= (1 << 27);
7845 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7846
7847 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7848 tmp |= (1 << 27);
7849 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7850
7851 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7852 tmp &= ~(0xF << 28);
7853 tmp |= (4 << 28);
7854 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7855
7856 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7857 tmp &= ~(0xF << 28);
7858 tmp |= (4 << 28);
7859 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7860 }
7861
7862 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7863 * Programming" based on the parameters passed:
7864 * - Sequence to enable CLKOUT_DP
7865 * - Sequence to enable CLKOUT_DP without spread
7866 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7867 */
7868 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7869 bool with_spread, bool with_fdi)
7870 {
7871 uint32_t reg, tmp;
7872
7873 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7874 with_spread = true;
7875 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7876 with_fdi, "LP PCH doesn't have FDI\n"))
7877 with_fdi = false;
7878
7879 mutex_lock(&dev_priv->sb_lock);
7880
7881 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7882 tmp &= ~SBI_SSCCTL_DISABLE;
7883 tmp |= SBI_SSCCTL_PATHALT;
7884 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7885
7886 udelay(24);
7887
7888 if (with_spread) {
7889 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7890 tmp &= ~SBI_SSCCTL_PATHALT;
7891 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7892
7893 if (with_fdi) {
7894 lpt_reset_fdi_mphy(dev_priv);
7895 lpt_program_fdi_mphy(dev_priv);
7896 }
7897 }
7898
7899 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7900 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7901 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7902 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7903
7904 mutex_unlock(&dev_priv->sb_lock);
7905 }
7906
7907 /* Sequence to disable CLKOUT_DP */
7908 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7909 {
7910 uint32_t reg, tmp;
7911
7912 mutex_lock(&dev_priv->sb_lock);
7913
7914 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7915 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7916 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7917 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7918
7919 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7920 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7921 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7922 tmp |= SBI_SSCCTL_PATHALT;
7923 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7924 udelay(32);
7925 }
7926 tmp |= SBI_SSCCTL_DISABLE;
7927 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7928 }
7929
7930 mutex_unlock(&dev_priv->sb_lock);
7931 }
7932
7933 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7934
7935 static const uint16_t sscdivintphase[] = {
7936 [BEND_IDX( 50)] = 0x3B23,
7937 [BEND_IDX( 45)] = 0x3B23,
7938 [BEND_IDX( 40)] = 0x3C23,
7939 [BEND_IDX( 35)] = 0x3C23,
7940 [BEND_IDX( 30)] = 0x3D23,
7941 [BEND_IDX( 25)] = 0x3D23,
7942 [BEND_IDX( 20)] = 0x3E23,
7943 [BEND_IDX( 15)] = 0x3E23,
7944 [BEND_IDX( 10)] = 0x3F23,
7945 [BEND_IDX( 5)] = 0x3F23,
7946 [BEND_IDX( 0)] = 0x0025,
7947 [BEND_IDX( -5)] = 0x0025,
7948 [BEND_IDX(-10)] = 0x0125,
7949 [BEND_IDX(-15)] = 0x0125,
7950 [BEND_IDX(-20)] = 0x0225,
7951 [BEND_IDX(-25)] = 0x0225,
7952 [BEND_IDX(-30)] = 0x0325,
7953 [BEND_IDX(-35)] = 0x0325,
7954 [BEND_IDX(-40)] = 0x0425,
7955 [BEND_IDX(-45)] = 0x0425,
7956 [BEND_IDX(-50)] = 0x0525,
7957 };
7958
7959 /*
7960 * Bend CLKOUT_DP
7961 * steps -50 to 50 inclusive, in steps of 5
7962 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7963 * change in clock period = -(steps / 10) * 5.787 ps
7964 */
7965 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7966 {
7967 uint32_t tmp;
7968 int idx = BEND_IDX(steps);
7969
7970 if (WARN_ON(steps % 5 != 0))
7971 return;
7972
7973 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7974 return;
7975
7976 mutex_lock(&dev_priv->sb_lock);
7977
7978 if (steps % 10 != 0)
7979 tmp = 0xAAAAAAAB;
7980 else
7981 tmp = 0x00000000;
7982 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7983
7984 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7985 tmp &= 0xffff0000;
7986 tmp |= sscdivintphase[idx];
7987 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7988
7989 mutex_unlock(&dev_priv->sb_lock);
7990 }
7991
7992 #undef BEND_IDX
7993
7994 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7995 {
7996 struct intel_encoder *encoder;
7997 bool has_vga = false;
7998
7999 for_each_intel_encoder(&dev_priv->drm, encoder) {
8000 switch (encoder->type) {
8001 case INTEL_OUTPUT_ANALOG:
8002 has_vga = true;
8003 break;
8004 default:
8005 break;
8006 }
8007 }
8008
8009 if (has_vga) {
8010 lpt_bend_clkout_dp(dev_priv, 0);
8011 lpt_enable_clkout_dp(dev_priv, true, true);
8012 } else {
8013 lpt_disable_clkout_dp(dev_priv);
8014 }
8015 }
8016
8017 /*
8018 * Initialize reference clocks when the driver loads
8019 */
8020 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8021 {
8022 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8023 ironlake_init_pch_refclk(dev_priv);
8024 else if (HAS_PCH_LPT(dev_priv))
8025 lpt_init_pch_refclk(dev_priv);
8026 }
8027
8028 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8029 {
8030 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8032 int pipe = intel_crtc->pipe;
8033 uint32_t val;
8034
8035 val = 0;
8036
8037 switch (intel_crtc->config->pipe_bpp) {
8038 case 18:
8039 val |= PIPECONF_6BPC;
8040 break;
8041 case 24:
8042 val |= PIPECONF_8BPC;
8043 break;
8044 case 30:
8045 val |= PIPECONF_10BPC;
8046 break;
8047 case 36:
8048 val |= PIPECONF_12BPC;
8049 break;
8050 default:
8051 /* Case prevented by intel_choose_pipe_bpp_dither. */
8052 BUG();
8053 }
8054
8055 if (intel_crtc->config->dither)
8056 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8057
8058 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8059 val |= PIPECONF_INTERLACED_ILK;
8060 else
8061 val |= PIPECONF_PROGRESSIVE;
8062
8063 if (intel_crtc->config->limited_color_range)
8064 val |= PIPECONF_COLOR_RANGE_SELECT;
8065
8066 I915_WRITE(PIPECONF(pipe), val);
8067 POSTING_READ(PIPECONF(pipe));
8068 }
8069
8070 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8071 {
8072 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8074 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8075 u32 val = 0;
8076
8077 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8078 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8079
8080 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8081 val |= PIPECONF_INTERLACED_ILK;
8082 else
8083 val |= PIPECONF_PROGRESSIVE;
8084
8085 I915_WRITE(PIPECONF(cpu_transcoder), val);
8086 POSTING_READ(PIPECONF(cpu_transcoder));
8087 }
8088
8089 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8090 {
8091 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8093
8094 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8095 u32 val = 0;
8096
8097 switch (intel_crtc->config->pipe_bpp) {
8098 case 18:
8099 val |= PIPEMISC_DITHER_6_BPC;
8100 break;
8101 case 24:
8102 val |= PIPEMISC_DITHER_8_BPC;
8103 break;
8104 case 30:
8105 val |= PIPEMISC_DITHER_10_BPC;
8106 break;
8107 case 36:
8108 val |= PIPEMISC_DITHER_12_BPC;
8109 break;
8110 default:
8111 /* Case prevented by pipe_config_set_bpp. */
8112 BUG();
8113 }
8114
8115 if (intel_crtc->config->dither)
8116 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8117
8118 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8119 }
8120 }
8121
8122 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8123 {
8124 /*
8125 * Account for spread spectrum to avoid
8126 * oversubscribing the link. Max center spread
8127 * is 2.5%; use 5% for safety's sake.
8128 */
8129 u32 bps = target_clock * bpp * 21 / 20;
8130 return DIV_ROUND_UP(bps, link_bw * 8);
8131 }
8132
8133 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8134 {
8135 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8136 }
8137
8138 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8139 struct intel_crtc_state *crtc_state,
8140 struct dpll *reduced_clock)
8141 {
8142 struct drm_crtc *crtc = &intel_crtc->base;
8143 struct drm_device *dev = crtc->dev;
8144 struct drm_i915_private *dev_priv = to_i915(dev);
8145 u32 dpll, fp, fp2;
8146 int factor;
8147
8148 /* Enable autotuning of the PLL clock (if permissible) */
8149 factor = 21;
8150 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8151 if ((intel_panel_use_ssc(dev_priv) &&
8152 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8153 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8154 factor = 25;
8155 } else if (crtc_state->sdvo_tv_clock)
8156 factor = 20;
8157
8158 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8159
8160 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8161 fp |= FP_CB_TUNE;
8162
8163 if (reduced_clock) {
8164 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8165
8166 if (reduced_clock->m < factor * reduced_clock->n)
8167 fp2 |= FP_CB_TUNE;
8168 } else {
8169 fp2 = fp;
8170 }
8171
8172 dpll = 0;
8173
8174 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8175 dpll |= DPLLB_MODE_LVDS;
8176 else
8177 dpll |= DPLLB_MODE_DAC_SERIAL;
8178
8179 dpll |= (crtc_state->pixel_multiplier - 1)
8180 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8181
8182 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8183 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8184 dpll |= DPLL_SDVO_HIGH_SPEED;
8185
8186 if (intel_crtc_has_dp_encoder(crtc_state))
8187 dpll |= DPLL_SDVO_HIGH_SPEED;
8188
8189 /*
8190 * The high speed IO clock is only really required for
8191 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8192 * possible to share the DPLL between CRT and HDMI. Enabling
8193 * the clock needlessly does no real harm, except use up a
8194 * bit of power potentially.
8195 *
8196 * We'll limit this to IVB with 3 pipes, since it has only two
8197 * DPLLs and so DPLL sharing is the only way to get three pipes
8198 * driving PCH ports at the same time. On SNB we could do this,
8199 * and potentially avoid enabling the second DPLL, but it's not
8200 * clear if it''s a win or loss power wise. No point in doing
8201 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8202 */
8203 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8204 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8205 dpll |= DPLL_SDVO_HIGH_SPEED;
8206
8207 /* compute bitmask from p1 value */
8208 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8209 /* also FPA1 */
8210 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8211
8212 switch (crtc_state->dpll.p2) {
8213 case 5:
8214 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8215 break;
8216 case 7:
8217 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8218 break;
8219 case 10:
8220 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8221 break;
8222 case 14:
8223 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8224 break;
8225 }
8226
8227 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8228 intel_panel_use_ssc(dev_priv))
8229 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8230 else
8231 dpll |= PLL_REF_INPUT_DREFCLK;
8232
8233 dpll |= DPLL_VCO_ENABLE;
8234
8235 crtc_state->dpll_hw_state.dpll = dpll;
8236 crtc_state->dpll_hw_state.fp0 = fp;
8237 crtc_state->dpll_hw_state.fp1 = fp2;
8238 }
8239
8240 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8241 struct intel_crtc_state *crtc_state)
8242 {
8243 struct drm_device *dev = crtc->base.dev;
8244 struct drm_i915_private *dev_priv = to_i915(dev);
8245 struct dpll reduced_clock;
8246 bool has_reduced_clock = false;
8247 struct intel_shared_dpll *pll;
8248 const struct intel_limit *limit;
8249 int refclk = 120000;
8250
8251 memset(&crtc_state->dpll_hw_state, 0,
8252 sizeof(crtc_state->dpll_hw_state));
8253
8254 crtc->lowfreq_avail = false;
8255
8256 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8257 if (!crtc_state->has_pch_encoder)
8258 return 0;
8259
8260 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8261 if (intel_panel_use_ssc(dev_priv)) {
8262 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8263 dev_priv->vbt.lvds_ssc_freq);
8264 refclk = dev_priv->vbt.lvds_ssc_freq;
8265 }
8266
8267 if (intel_is_dual_link_lvds(dev)) {
8268 if (refclk == 100000)
8269 limit = &intel_limits_ironlake_dual_lvds_100m;
8270 else
8271 limit = &intel_limits_ironlake_dual_lvds;
8272 } else {
8273 if (refclk == 100000)
8274 limit = &intel_limits_ironlake_single_lvds_100m;
8275 else
8276 limit = &intel_limits_ironlake_single_lvds;
8277 }
8278 } else {
8279 limit = &intel_limits_ironlake_dac;
8280 }
8281
8282 if (!crtc_state->clock_set &&
8283 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8284 refclk, NULL, &crtc_state->dpll)) {
8285 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8286 return -EINVAL;
8287 }
8288
8289 ironlake_compute_dpll(crtc, crtc_state,
8290 has_reduced_clock ? &reduced_clock : NULL);
8291
8292 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8293 if (pll == NULL) {
8294 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8295 pipe_name(crtc->pipe));
8296 return -EINVAL;
8297 }
8298
8299 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8300 has_reduced_clock)
8301 crtc->lowfreq_avail = true;
8302
8303 return 0;
8304 }
8305
8306 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8307 struct intel_link_m_n *m_n)
8308 {
8309 struct drm_device *dev = crtc->base.dev;
8310 struct drm_i915_private *dev_priv = to_i915(dev);
8311 enum pipe pipe = crtc->pipe;
8312
8313 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8314 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8315 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8316 & ~TU_SIZE_MASK;
8317 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8318 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8319 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8320 }
8321
8322 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8323 enum transcoder transcoder,
8324 struct intel_link_m_n *m_n,
8325 struct intel_link_m_n *m2_n2)
8326 {
8327 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8328 enum pipe pipe = crtc->pipe;
8329
8330 if (INTEL_GEN(dev_priv) >= 5) {
8331 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8332 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8333 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8334 & ~TU_SIZE_MASK;
8335 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8336 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8337 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8338 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8339 * gen < 8) and if DRRS is supported (to make sure the
8340 * registers are not unnecessarily read).
8341 */
8342 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8343 crtc->config->has_drrs) {
8344 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8345 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8346 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8347 & ~TU_SIZE_MASK;
8348 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8349 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8350 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8351 }
8352 } else {
8353 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8354 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8355 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8356 & ~TU_SIZE_MASK;
8357 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8358 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8359 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8360 }
8361 }
8362
8363 void intel_dp_get_m_n(struct intel_crtc *crtc,
8364 struct intel_crtc_state *pipe_config)
8365 {
8366 if (pipe_config->has_pch_encoder)
8367 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8368 else
8369 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8370 &pipe_config->dp_m_n,
8371 &pipe_config->dp_m2_n2);
8372 }
8373
8374 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8375 struct intel_crtc_state *pipe_config)
8376 {
8377 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8378 &pipe_config->fdi_m_n, NULL);
8379 }
8380
8381 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8382 struct intel_crtc_state *pipe_config)
8383 {
8384 struct drm_device *dev = crtc->base.dev;
8385 struct drm_i915_private *dev_priv = to_i915(dev);
8386 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8387 uint32_t ps_ctrl = 0;
8388 int id = -1;
8389 int i;
8390
8391 /* find scaler attached to this pipe */
8392 for (i = 0; i < crtc->num_scalers; i++) {
8393 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8394 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8395 id = i;
8396 pipe_config->pch_pfit.enabled = true;
8397 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8398 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8399 break;
8400 }
8401 }
8402
8403 scaler_state->scaler_id = id;
8404 if (id >= 0) {
8405 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8406 } else {
8407 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8408 }
8409 }
8410
8411 static void
8412 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8413 struct intel_initial_plane_config *plane_config)
8414 {
8415 struct drm_device *dev = crtc->base.dev;
8416 struct drm_i915_private *dev_priv = to_i915(dev);
8417 u32 val, base, offset, stride_mult, tiling;
8418 int pipe = crtc->pipe;
8419 int fourcc, pixel_format;
8420 unsigned int aligned_height;
8421 struct drm_framebuffer *fb;
8422 struct intel_framebuffer *intel_fb;
8423
8424 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8425 if (!intel_fb) {
8426 DRM_DEBUG_KMS("failed to alloc fb\n");
8427 return;
8428 }
8429
8430 fb = &intel_fb->base;
8431
8432 fb->dev = dev;
8433
8434 val = I915_READ(PLANE_CTL(pipe, 0));
8435 if (!(val & PLANE_CTL_ENABLE))
8436 goto error;
8437
8438 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8439 fourcc = skl_format_to_fourcc(pixel_format,
8440 val & PLANE_CTL_ORDER_RGBX,
8441 val & PLANE_CTL_ALPHA_MASK);
8442 fb->format = drm_format_info(fourcc);
8443
8444 tiling = val & PLANE_CTL_TILED_MASK;
8445 switch (tiling) {
8446 case PLANE_CTL_TILED_LINEAR:
8447 fb->modifier = DRM_FORMAT_MOD_NONE;
8448 break;
8449 case PLANE_CTL_TILED_X:
8450 plane_config->tiling = I915_TILING_X;
8451 fb->modifier = I915_FORMAT_MOD_X_TILED;
8452 break;
8453 case PLANE_CTL_TILED_Y:
8454 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8455 break;
8456 case PLANE_CTL_TILED_YF:
8457 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8458 break;
8459 default:
8460 MISSING_CASE(tiling);
8461 goto error;
8462 }
8463
8464 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8465 plane_config->base = base;
8466
8467 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8468
8469 val = I915_READ(PLANE_SIZE(pipe, 0));
8470 fb->height = ((val >> 16) & 0xfff) + 1;
8471 fb->width = ((val >> 0) & 0x1fff) + 1;
8472
8473 val = I915_READ(PLANE_STRIDE(pipe, 0));
8474 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
8475 fb->format->format);
8476 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8477
8478 aligned_height = intel_fb_align_height(dev, fb->height,
8479 fb->format->format,
8480 fb->modifier);
8481
8482 plane_config->size = fb->pitches[0] * aligned_height;
8483
8484 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8485 pipe_name(pipe), fb->width, fb->height,
8486 fb->format->cpp[0] * 8, base, fb->pitches[0],
8487 plane_config->size);
8488
8489 plane_config->fb = intel_fb;
8490 return;
8491
8492 error:
8493 kfree(intel_fb);
8494 }
8495
8496 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8497 struct intel_crtc_state *pipe_config)
8498 {
8499 struct drm_device *dev = crtc->base.dev;
8500 struct drm_i915_private *dev_priv = to_i915(dev);
8501 uint32_t tmp;
8502
8503 tmp = I915_READ(PF_CTL(crtc->pipe));
8504
8505 if (tmp & PF_ENABLE) {
8506 pipe_config->pch_pfit.enabled = true;
8507 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8508 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8509
8510 /* We currently do not free assignements of panel fitters on
8511 * ivb/hsw (since we don't use the higher upscaling modes which
8512 * differentiates them) so just WARN about this case for now. */
8513 if (IS_GEN7(dev_priv)) {
8514 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8515 PF_PIPE_SEL_IVB(crtc->pipe));
8516 }
8517 }
8518 }
8519
8520 static void
8521 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8522 struct intel_initial_plane_config *plane_config)
8523 {
8524 struct drm_device *dev = crtc->base.dev;
8525 struct drm_i915_private *dev_priv = to_i915(dev);
8526 u32 val, base, offset;
8527 int pipe = crtc->pipe;
8528 int fourcc, pixel_format;
8529 unsigned int aligned_height;
8530 struct drm_framebuffer *fb;
8531 struct intel_framebuffer *intel_fb;
8532
8533 val = I915_READ(DSPCNTR(pipe));
8534 if (!(val & DISPLAY_PLANE_ENABLE))
8535 return;
8536
8537 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8538 if (!intel_fb) {
8539 DRM_DEBUG_KMS("failed to alloc fb\n");
8540 return;
8541 }
8542
8543 fb = &intel_fb->base;
8544
8545 fb->dev = dev;
8546
8547 if (INTEL_GEN(dev_priv) >= 4) {
8548 if (val & DISPPLANE_TILED) {
8549 plane_config->tiling = I915_TILING_X;
8550 fb->modifier = I915_FORMAT_MOD_X_TILED;
8551 }
8552 }
8553
8554 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8555 fourcc = i9xx_format_to_fourcc(pixel_format);
8556 fb->format = drm_format_info(fourcc);
8557
8558 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8559 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8560 offset = I915_READ(DSPOFFSET(pipe));
8561 } else {
8562 if (plane_config->tiling)
8563 offset = I915_READ(DSPTILEOFF(pipe));
8564 else
8565 offset = I915_READ(DSPLINOFF(pipe));
8566 }
8567 plane_config->base = base;
8568
8569 val = I915_READ(PIPESRC(pipe));
8570 fb->width = ((val >> 16) & 0xfff) + 1;
8571 fb->height = ((val >> 0) & 0xfff) + 1;
8572
8573 val = I915_READ(DSPSTRIDE(pipe));
8574 fb->pitches[0] = val & 0xffffffc0;
8575
8576 aligned_height = intel_fb_align_height(dev, fb->height,
8577 fb->format->format,
8578 fb->modifier);
8579
8580 plane_config->size = fb->pitches[0] * aligned_height;
8581
8582 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8583 pipe_name(pipe), fb->width, fb->height,
8584 fb->format->cpp[0] * 8, base, fb->pitches[0],
8585 plane_config->size);
8586
8587 plane_config->fb = intel_fb;
8588 }
8589
8590 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8591 struct intel_crtc_state *pipe_config)
8592 {
8593 struct drm_device *dev = crtc->base.dev;
8594 struct drm_i915_private *dev_priv = to_i915(dev);
8595 enum intel_display_power_domain power_domain;
8596 uint32_t tmp;
8597 bool ret;
8598
8599 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8600 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8601 return false;
8602
8603 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8604 pipe_config->shared_dpll = NULL;
8605
8606 ret = false;
8607 tmp = I915_READ(PIPECONF(crtc->pipe));
8608 if (!(tmp & PIPECONF_ENABLE))
8609 goto out;
8610
8611 switch (tmp & PIPECONF_BPC_MASK) {
8612 case PIPECONF_6BPC:
8613 pipe_config->pipe_bpp = 18;
8614 break;
8615 case PIPECONF_8BPC:
8616 pipe_config->pipe_bpp = 24;
8617 break;
8618 case PIPECONF_10BPC:
8619 pipe_config->pipe_bpp = 30;
8620 break;
8621 case PIPECONF_12BPC:
8622 pipe_config->pipe_bpp = 36;
8623 break;
8624 default:
8625 break;
8626 }
8627
8628 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8629 pipe_config->limited_color_range = true;
8630
8631 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8632 struct intel_shared_dpll *pll;
8633 enum intel_dpll_id pll_id;
8634
8635 pipe_config->has_pch_encoder = true;
8636
8637 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8638 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8639 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8640
8641 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8642
8643 if (HAS_PCH_IBX(dev_priv)) {
8644 /*
8645 * The pipe->pch transcoder and pch transcoder->pll
8646 * mapping is fixed.
8647 */
8648 pll_id = (enum intel_dpll_id) crtc->pipe;
8649 } else {
8650 tmp = I915_READ(PCH_DPLL_SEL);
8651 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8652 pll_id = DPLL_ID_PCH_PLL_B;
8653 else
8654 pll_id= DPLL_ID_PCH_PLL_A;
8655 }
8656
8657 pipe_config->shared_dpll =
8658 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8659 pll = pipe_config->shared_dpll;
8660
8661 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8662 &pipe_config->dpll_hw_state));
8663
8664 tmp = pipe_config->dpll_hw_state.dpll;
8665 pipe_config->pixel_multiplier =
8666 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8667 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8668
8669 ironlake_pch_clock_get(crtc, pipe_config);
8670 } else {
8671 pipe_config->pixel_multiplier = 1;
8672 }
8673
8674 intel_get_pipe_timings(crtc, pipe_config);
8675 intel_get_pipe_src_size(crtc, pipe_config);
8676
8677 ironlake_get_pfit_config(crtc, pipe_config);
8678
8679 ret = true;
8680
8681 out:
8682 intel_display_power_put(dev_priv, power_domain);
8683
8684 return ret;
8685 }
8686
8687 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8688 {
8689 struct drm_device *dev = &dev_priv->drm;
8690 struct intel_crtc *crtc;
8691
8692 for_each_intel_crtc(dev, crtc)
8693 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8694 pipe_name(crtc->pipe));
8695
8696 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8697 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8698 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8699 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8700 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8701 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8702 "CPU PWM1 enabled\n");
8703 if (IS_HASWELL(dev_priv))
8704 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8705 "CPU PWM2 enabled\n");
8706 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8707 "PCH PWM1 enabled\n");
8708 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8709 "Utility pin enabled\n");
8710 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8711
8712 /*
8713 * In theory we can still leave IRQs enabled, as long as only the HPD
8714 * interrupts remain enabled. We used to check for that, but since it's
8715 * gen-specific and since we only disable LCPLL after we fully disable
8716 * the interrupts, the check below should be enough.
8717 */
8718 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8719 }
8720
8721 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8722 {
8723 if (IS_HASWELL(dev_priv))
8724 return I915_READ(D_COMP_HSW);
8725 else
8726 return I915_READ(D_COMP_BDW);
8727 }
8728
8729 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8730 {
8731 if (IS_HASWELL(dev_priv)) {
8732 mutex_lock(&dev_priv->rps.hw_lock);
8733 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8734 val))
8735 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8736 mutex_unlock(&dev_priv->rps.hw_lock);
8737 } else {
8738 I915_WRITE(D_COMP_BDW, val);
8739 POSTING_READ(D_COMP_BDW);
8740 }
8741 }
8742
8743 /*
8744 * This function implements pieces of two sequences from BSpec:
8745 * - Sequence for display software to disable LCPLL
8746 * - Sequence for display software to allow package C8+
8747 * The steps implemented here are just the steps that actually touch the LCPLL
8748 * register. Callers should take care of disabling all the display engine
8749 * functions, doing the mode unset, fixing interrupts, etc.
8750 */
8751 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8752 bool switch_to_fclk, bool allow_power_down)
8753 {
8754 uint32_t val;
8755
8756 assert_can_disable_lcpll(dev_priv);
8757
8758 val = I915_READ(LCPLL_CTL);
8759
8760 if (switch_to_fclk) {
8761 val |= LCPLL_CD_SOURCE_FCLK;
8762 I915_WRITE(LCPLL_CTL, val);
8763
8764 if (wait_for_us(I915_READ(LCPLL_CTL) &
8765 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8766 DRM_ERROR("Switching to FCLK failed\n");
8767
8768 val = I915_READ(LCPLL_CTL);
8769 }
8770
8771 val |= LCPLL_PLL_DISABLE;
8772 I915_WRITE(LCPLL_CTL, val);
8773 POSTING_READ(LCPLL_CTL);
8774
8775 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8776 DRM_ERROR("LCPLL still locked\n");
8777
8778 val = hsw_read_dcomp(dev_priv);
8779 val |= D_COMP_COMP_DISABLE;
8780 hsw_write_dcomp(dev_priv, val);
8781 ndelay(100);
8782
8783 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8784 1))
8785 DRM_ERROR("D_COMP RCOMP still in progress\n");
8786
8787 if (allow_power_down) {
8788 val = I915_READ(LCPLL_CTL);
8789 val |= LCPLL_POWER_DOWN_ALLOW;
8790 I915_WRITE(LCPLL_CTL, val);
8791 POSTING_READ(LCPLL_CTL);
8792 }
8793 }
8794
8795 /*
8796 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8797 * source.
8798 */
8799 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8800 {
8801 uint32_t val;
8802
8803 val = I915_READ(LCPLL_CTL);
8804
8805 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8806 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8807 return;
8808
8809 /*
8810 * Make sure we're not on PC8 state before disabling PC8, otherwise
8811 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8812 */
8813 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8814
8815 if (val & LCPLL_POWER_DOWN_ALLOW) {
8816 val &= ~LCPLL_POWER_DOWN_ALLOW;
8817 I915_WRITE(LCPLL_CTL, val);
8818 POSTING_READ(LCPLL_CTL);
8819 }
8820
8821 val = hsw_read_dcomp(dev_priv);
8822 val |= D_COMP_COMP_FORCE;
8823 val &= ~D_COMP_COMP_DISABLE;
8824 hsw_write_dcomp(dev_priv, val);
8825
8826 val = I915_READ(LCPLL_CTL);
8827 val &= ~LCPLL_PLL_DISABLE;
8828 I915_WRITE(LCPLL_CTL, val);
8829
8830 if (intel_wait_for_register(dev_priv,
8831 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8832 5))
8833 DRM_ERROR("LCPLL not locked yet\n");
8834
8835 if (val & LCPLL_CD_SOURCE_FCLK) {
8836 val = I915_READ(LCPLL_CTL);
8837 val &= ~LCPLL_CD_SOURCE_FCLK;
8838 I915_WRITE(LCPLL_CTL, val);
8839
8840 if (wait_for_us((I915_READ(LCPLL_CTL) &
8841 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8842 DRM_ERROR("Switching back to LCPLL failed\n");
8843 }
8844
8845 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8846 intel_update_cdclk(dev_priv);
8847 }
8848
8849 /*
8850 * Package states C8 and deeper are really deep PC states that can only be
8851 * reached when all the devices on the system allow it, so even if the graphics
8852 * device allows PC8+, it doesn't mean the system will actually get to these
8853 * states. Our driver only allows PC8+ when going into runtime PM.
8854 *
8855 * The requirements for PC8+ are that all the outputs are disabled, the power
8856 * well is disabled and most interrupts are disabled, and these are also
8857 * requirements for runtime PM. When these conditions are met, we manually do
8858 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8859 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8860 * hang the machine.
8861 *
8862 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8863 * the state of some registers, so when we come back from PC8+ we need to
8864 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8865 * need to take care of the registers kept by RC6. Notice that this happens even
8866 * if we don't put the device in PCI D3 state (which is what currently happens
8867 * because of the runtime PM support).
8868 *
8869 * For more, read "Display Sequences for Package C8" on the hardware
8870 * documentation.
8871 */
8872 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8873 {
8874 uint32_t val;
8875
8876 DRM_DEBUG_KMS("Enabling package C8+\n");
8877
8878 if (HAS_PCH_LPT_LP(dev_priv)) {
8879 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8880 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8881 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8882 }
8883
8884 lpt_disable_clkout_dp(dev_priv);
8885 hsw_disable_lcpll(dev_priv, true, true);
8886 }
8887
8888 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8889 {
8890 uint32_t val;
8891
8892 DRM_DEBUG_KMS("Disabling package C8+\n");
8893
8894 hsw_restore_lcpll(dev_priv);
8895 lpt_init_pch_refclk(dev_priv);
8896
8897 if (HAS_PCH_LPT_LP(dev_priv)) {
8898 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8899 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8900 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8901 }
8902 }
8903
8904 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8905 struct intel_crtc_state *crtc_state)
8906 {
8907 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8908 if (!intel_ddi_pll_select(crtc, crtc_state))
8909 return -EINVAL;
8910 }
8911
8912 crtc->lowfreq_avail = false;
8913
8914 return 0;
8915 }
8916
8917 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8918 enum port port,
8919 struct intel_crtc_state *pipe_config)
8920 {
8921 enum intel_dpll_id id;
8922
8923 switch (port) {
8924 case PORT_A:
8925 id = DPLL_ID_SKL_DPLL0;
8926 break;
8927 case PORT_B:
8928 id = DPLL_ID_SKL_DPLL1;
8929 break;
8930 case PORT_C:
8931 id = DPLL_ID_SKL_DPLL2;
8932 break;
8933 default:
8934 DRM_ERROR("Incorrect port type\n");
8935 return;
8936 }
8937
8938 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8939 }
8940
8941 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8942 enum port port,
8943 struct intel_crtc_state *pipe_config)
8944 {
8945 enum intel_dpll_id id;
8946 u32 temp;
8947
8948 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8949 id = temp >> (port * 3 + 1);
8950
8951 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8952 return;
8953
8954 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8955 }
8956
8957 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8958 enum port port,
8959 struct intel_crtc_state *pipe_config)
8960 {
8961 enum intel_dpll_id id;
8962 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8963
8964 switch (ddi_pll_sel) {
8965 case PORT_CLK_SEL_WRPLL1:
8966 id = DPLL_ID_WRPLL1;
8967 break;
8968 case PORT_CLK_SEL_WRPLL2:
8969 id = DPLL_ID_WRPLL2;
8970 break;
8971 case PORT_CLK_SEL_SPLL:
8972 id = DPLL_ID_SPLL;
8973 break;
8974 case PORT_CLK_SEL_LCPLL_810:
8975 id = DPLL_ID_LCPLL_810;
8976 break;
8977 case PORT_CLK_SEL_LCPLL_1350:
8978 id = DPLL_ID_LCPLL_1350;
8979 break;
8980 case PORT_CLK_SEL_LCPLL_2700:
8981 id = DPLL_ID_LCPLL_2700;
8982 break;
8983 default:
8984 MISSING_CASE(ddi_pll_sel);
8985 /* fall through */
8986 case PORT_CLK_SEL_NONE:
8987 return;
8988 }
8989
8990 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8991 }
8992
8993 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8994 struct intel_crtc_state *pipe_config,
8995 u64 *power_domain_mask)
8996 {
8997 struct drm_device *dev = crtc->base.dev;
8998 struct drm_i915_private *dev_priv = to_i915(dev);
8999 enum intel_display_power_domain power_domain;
9000 u32 tmp;
9001
9002 /*
9003 * The pipe->transcoder mapping is fixed with the exception of the eDP
9004 * transcoder handled below.
9005 */
9006 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9007
9008 /*
9009 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9010 * consistency and less surprising code; it's in always on power).
9011 */
9012 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9013 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9014 enum pipe trans_edp_pipe;
9015 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9016 default:
9017 WARN(1, "unknown pipe linked to edp transcoder\n");
9018 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9019 case TRANS_DDI_EDP_INPUT_A_ON:
9020 trans_edp_pipe = PIPE_A;
9021 break;
9022 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9023 trans_edp_pipe = PIPE_B;
9024 break;
9025 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9026 trans_edp_pipe = PIPE_C;
9027 break;
9028 }
9029
9030 if (trans_edp_pipe == crtc->pipe)
9031 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9032 }
9033
9034 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9035 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9036 return false;
9037 *power_domain_mask |= BIT_ULL(power_domain);
9038
9039 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9040
9041 return tmp & PIPECONF_ENABLE;
9042 }
9043
9044 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9045 struct intel_crtc_state *pipe_config,
9046 u64 *power_domain_mask)
9047 {
9048 struct drm_device *dev = crtc->base.dev;
9049 struct drm_i915_private *dev_priv = to_i915(dev);
9050 enum intel_display_power_domain power_domain;
9051 enum port port;
9052 enum transcoder cpu_transcoder;
9053 u32 tmp;
9054
9055 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9056 if (port == PORT_A)
9057 cpu_transcoder = TRANSCODER_DSI_A;
9058 else
9059 cpu_transcoder = TRANSCODER_DSI_C;
9060
9061 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9062 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9063 continue;
9064 *power_domain_mask |= BIT_ULL(power_domain);
9065
9066 /*
9067 * The PLL needs to be enabled with a valid divider
9068 * configuration, otherwise accessing DSI registers will hang
9069 * the machine. See BSpec North Display Engine
9070 * registers/MIPI[BXT]. We can break out here early, since we
9071 * need the same DSI PLL to be enabled for both DSI ports.
9072 */
9073 if (!intel_dsi_pll_is_enabled(dev_priv))
9074 break;
9075
9076 /* XXX: this works for video mode only */
9077 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9078 if (!(tmp & DPI_ENABLE))
9079 continue;
9080
9081 tmp = I915_READ(MIPI_CTRL(port));
9082 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9083 continue;
9084
9085 pipe_config->cpu_transcoder = cpu_transcoder;
9086 break;
9087 }
9088
9089 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9090 }
9091
9092 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9093 struct intel_crtc_state *pipe_config)
9094 {
9095 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9096 struct intel_shared_dpll *pll;
9097 enum port port;
9098 uint32_t tmp;
9099
9100 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9101
9102 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9103
9104 if (IS_GEN9_BC(dev_priv))
9105 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9106 else if (IS_GEN9_LP(dev_priv))
9107 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9108 else
9109 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9110
9111 pll = pipe_config->shared_dpll;
9112 if (pll) {
9113 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9114 &pipe_config->dpll_hw_state));
9115 }
9116
9117 /*
9118 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9119 * DDI E. So just check whether this pipe is wired to DDI E and whether
9120 * the PCH transcoder is on.
9121 */
9122 if (INTEL_GEN(dev_priv) < 9 &&
9123 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9124 pipe_config->has_pch_encoder = true;
9125
9126 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9127 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9128 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9129
9130 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9131 }
9132 }
9133
9134 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9135 struct intel_crtc_state *pipe_config)
9136 {
9137 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9138 enum intel_display_power_domain power_domain;
9139 u64 power_domain_mask;
9140 bool active;
9141
9142 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9143 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9144 return false;
9145 power_domain_mask = BIT_ULL(power_domain);
9146
9147 pipe_config->shared_dpll = NULL;
9148
9149 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9150
9151 if (IS_GEN9_LP(dev_priv) &&
9152 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9153 WARN_ON(active);
9154 active = true;
9155 }
9156
9157 if (!active)
9158 goto out;
9159
9160 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9161 haswell_get_ddi_port_state(crtc, pipe_config);
9162 intel_get_pipe_timings(crtc, pipe_config);
9163 }
9164
9165 intel_get_pipe_src_size(crtc, pipe_config);
9166
9167 pipe_config->gamma_mode =
9168 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9169
9170 if (INTEL_GEN(dev_priv) >= 9) {
9171 intel_crtc_init_scalers(crtc, pipe_config);
9172
9173 pipe_config->scaler_state.scaler_id = -1;
9174 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9175 }
9176
9177 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9178 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9179 power_domain_mask |= BIT_ULL(power_domain);
9180 if (INTEL_GEN(dev_priv) >= 9)
9181 skylake_get_pfit_config(crtc, pipe_config);
9182 else
9183 ironlake_get_pfit_config(crtc, pipe_config);
9184 }
9185
9186 if (IS_HASWELL(dev_priv))
9187 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9188 (I915_READ(IPS_CTL) & IPS_ENABLE);
9189
9190 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9191 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9192 pipe_config->pixel_multiplier =
9193 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9194 } else {
9195 pipe_config->pixel_multiplier = 1;
9196 }
9197
9198 out:
9199 for_each_power_domain(power_domain, power_domain_mask)
9200 intel_display_power_put(dev_priv, power_domain);
9201
9202 return active;
9203 }
9204
9205 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9206 const struct intel_plane_state *plane_state)
9207 {
9208 struct drm_device *dev = crtc->dev;
9209 struct drm_i915_private *dev_priv = to_i915(dev);
9210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9211 uint32_t cntl = 0, size = 0;
9212
9213 if (plane_state && plane_state->base.visible) {
9214 unsigned int width = plane_state->base.crtc_w;
9215 unsigned int height = plane_state->base.crtc_h;
9216 unsigned int stride = roundup_pow_of_two(width) * 4;
9217
9218 switch (stride) {
9219 default:
9220 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9221 width, stride);
9222 stride = 256;
9223 /* fallthrough */
9224 case 256:
9225 case 512:
9226 case 1024:
9227 case 2048:
9228 break;
9229 }
9230
9231 cntl |= CURSOR_ENABLE |
9232 CURSOR_GAMMA_ENABLE |
9233 CURSOR_FORMAT_ARGB |
9234 CURSOR_STRIDE(stride);
9235
9236 size = (height << 12) | width;
9237 }
9238
9239 if (intel_crtc->cursor_cntl != 0 &&
9240 (intel_crtc->cursor_base != base ||
9241 intel_crtc->cursor_size != size ||
9242 intel_crtc->cursor_cntl != cntl)) {
9243 /* On these chipsets we can only modify the base/size/stride
9244 * whilst the cursor is disabled.
9245 */
9246 I915_WRITE(CURCNTR(PIPE_A), 0);
9247 POSTING_READ(CURCNTR(PIPE_A));
9248 intel_crtc->cursor_cntl = 0;
9249 }
9250
9251 if (intel_crtc->cursor_base != base) {
9252 I915_WRITE(CURBASE(PIPE_A), base);
9253 intel_crtc->cursor_base = base;
9254 }
9255
9256 if (intel_crtc->cursor_size != size) {
9257 I915_WRITE(CURSIZE, size);
9258 intel_crtc->cursor_size = size;
9259 }
9260
9261 if (intel_crtc->cursor_cntl != cntl) {
9262 I915_WRITE(CURCNTR(PIPE_A), cntl);
9263 POSTING_READ(CURCNTR(PIPE_A));
9264 intel_crtc->cursor_cntl = cntl;
9265 }
9266 }
9267
9268 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9269 const struct intel_plane_state *plane_state)
9270 {
9271 struct drm_device *dev = crtc->dev;
9272 struct drm_i915_private *dev_priv = to_i915(dev);
9273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9274 int pipe = intel_crtc->pipe;
9275 uint32_t cntl = 0;
9276
9277 if (plane_state && plane_state->base.visible) {
9278 cntl = MCURSOR_GAMMA_ENABLE;
9279 switch (plane_state->base.crtc_w) {
9280 case 64:
9281 cntl |= CURSOR_MODE_64_ARGB_AX;
9282 break;
9283 case 128:
9284 cntl |= CURSOR_MODE_128_ARGB_AX;
9285 break;
9286 case 256:
9287 cntl |= CURSOR_MODE_256_ARGB_AX;
9288 break;
9289 default:
9290 MISSING_CASE(plane_state->base.crtc_w);
9291 return;
9292 }
9293 cntl |= pipe << 28; /* Connect to correct pipe */
9294
9295 if (HAS_DDI(dev_priv))
9296 cntl |= CURSOR_PIPE_CSC_ENABLE;
9297
9298 if (plane_state->base.rotation & DRM_ROTATE_180)
9299 cntl |= CURSOR_ROTATE_180;
9300 }
9301
9302 if (intel_crtc->cursor_cntl != cntl) {
9303 I915_WRITE(CURCNTR(pipe), cntl);
9304 POSTING_READ(CURCNTR(pipe));
9305 intel_crtc->cursor_cntl = cntl;
9306 }
9307
9308 /* and commit changes on next vblank */
9309 I915_WRITE(CURBASE(pipe), base);
9310 POSTING_READ(CURBASE(pipe));
9311
9312 intel_crtc->cursor_base = base;
9313 }
9314
9315 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9316 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9317 const struct intel_plane_state *plane_state)
9318 {
9319 struct drm_device *dev = crtc->dev;
9320 struct drm_i915_private *dev_priv = to_i915(dev);
9321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9322 int pipe = intel_crtc->pipe;
9323 u32 base = intel_crtc->cursor_addr;
9324 u32 pos = 0;
9325
9326 if (plane_state) {
9327 int x = plane_state->base.crtc_x;
9328 int y = plane_state->base.crtc_y;
9329
9330 if (x < 0) {
9331 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9332 x = -x;
9333 }
9334 pos |= x << CURSOR_X_SHIFT;
9335
9336 if (y < 0) {
9337 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9338 y = -y;
9339 }
9340 pos |= y << CURSOR_Y_SHIFT;
9341
9342 /* ILK+ do this automagically */
9343 if (HAS_GMCH_DISPLAY(dev_priv) &&
9344 plane_state->base.rotation & DRM_ROTATE_180) {
9345 base += (plane_state->base.crtc_h *
9346 plane_state->base.crtc_w - 1) * 4;
9347 }
9348 }
9349
9350 I915_WRITE(CURPOS(pipe), pos);
9351
9352 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9353 i845_update_cursor(crtc, base, plane_state);
9354 else
9355 i9xx_update_cursor(crtc, base, plane_state);
9356 }
9357
9358 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9359 uint32_t width, uint32_t height)
9360 {
9361 if (width == 0 || height == 0)
9362 return false;
9363
9364 /*
9365 * 845g/865g are special in that they are only limited by
9366 * the width of their cursors, the height is arbitrary up to
9367 * the precision of the register. Everything else requires
9368 * square cursors, limited to a few power-of-two sizes.
9369 */
9370 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9371 if ((width & 63) != 0)
9372 return false;
9373
9374 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9375 return false;
9376
9377 if (height > 1023)
9378 return false;
9379 } else {
9380 switch (width | height) {
9381 case 256:
9382 case 128:
9383 if (IS_GEN2(dev_priv))
9384 return false;
9385 case 64:
9386 break;
9387 default:
9388 return false;
9389 }
9390 }
9391
9392 return true;
9393 }
9394
9395 /* VESA 640x480x72Hz mode to set on the pipe */
9396 static struct drm_display_mode load_detect_mode = {
9397 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9398 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9399 };
9400
9401 struct drm_framebuffer *
9402 __intel_framebuffer_create(struct drm_device *dev,
9403 struct drm_mode_fb_cmd2 *mode_cmd,
9404 struct drm_i915_gem_object *obj)
9405 {
9406 struct intel_framebuffer *intel_fb;
9407 int ret;
9408
9409 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9410 if (!intel_fb)
9411 return ERR_PTR(-ENOMEM);
9412
9413 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9414 if (ret)
9415 goto err;
9416
9417 return &intel_fb->base;
9418
9419 err:
9420 kfree(intel_fb);
9421 return ERR_PTR(ret);
9422 }
9423
9424 static struct drm_framebuffer *
9425 intel_framebuffer_create(struct drm_device *dev,
9426 struct drm_mode_fb_cmd2 *mode_cmd,
9427 struct drm_i915_gem_object *obj)
9428 {
9429 struct drm_framebuffer *fb;
9430 int ret;
9431
9432 ret = i915_mutex_lock_interruptible(dev);
9433 if (ret)
9434 return ERR_PTR(ret);
9435 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9436 mutex_unlock(&dev->struct_mutex);
9437
9438 return fb;
9439 }
9440
9441 static u32
9442 intel_framebuffer_pitch_for_width(int width, int bpp)
9443 {
9444 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9445 return ALIGN(pitch, 64);
9446 }
9447
9448 static u32
9449 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9450 {
9451 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9452 return PAGE_ALIGN(pitch * mode->vdisplay);
9453 }
9454
9455 static struct drm_framebuffer *
9456 intel_framebuffer_create_for_mode(struct drm_device *dev,
9457 struct drm_display_mode *mode,
9458 int depth, int bpp)
9459 {
9460 struct drm_framebuffer *fb;
9461 struct drm_i915_gem_object *obj;
9462 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9463
9464 obj = i915_gem_object_create(to_i915(dev),
9465 intel_framebuffer_size_for_mode(mode, bpp));
9466 if (IS_ERR(obj))
9467 return ERR_CAST(obj);
9468
9469 mode_cmd.width = mode->hdisplay;
9470 mode_cmd.height = mode->vdisplay;
9471 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9472 bpp);
9473 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9474
9475 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
9476 if (IS_ERR(fb))
9477 i915_gem_object_put(obj);
9478
9479 return fb;
9480 }
9481
9482 static struct drm_framebuffer *
9483 mode_fits_in_fbdev(struct drm_device *dev,
9484 struct drm_display_mode *mode)
9485 {
9486 #ifdef CONFIG_DRM_FBDEV_EMULATION
9487 struct drm_i915_private *dev_priv = to_i915(dev);
9488 struct drm_i915_gem_object *obj;
9489 struct drm_framebuffer *fb;
9490
9491 if (!dev_priv->fbdev)
9492 return NULL;
9493
9494 if (!dev_priv->fbdev->fb)
9495 return NULL;
9496
9497 obj = dev_priv->fbdev->fb->obj;
9498 BUG_ON(!obj);
9499
9500 fb = &dev_priv->fbdev->fb->base;
9501 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9502 fb->format->cpp[0] * 8))
9503 return NULL;
9504
9505 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9506 return NULL;
9507
9508 drm_framebuffer_reference(fb);
9509 return fb;
9510 #else
9511 return NULL;
9512 #endif
9513 }
9514
9515 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9516 struct drm_crtc *crtc,
9517 struct drm_display_mode *mode,
9518 struct drm_framebuffer *fb,
9519 int x, int y)
9520 {
9521 struct drm_plane_state *plane_state;
9522 int hdisplay, vdisplay;
9523 int ret;
9524
9525 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9526 if (IS_ERR(plane_state))
9527 return PTR_ERR(plane_state);
9528
9529 if (mode)
9530 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9531 else
9532 hdisplay = vdisplay = 0;
9533
9534 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9535 if (ret)
9536 return ret;
9537 drm_atomic_set_fb_for_plane(plane_state, fb);
9538 plane_state->crtc_x = 0;
9539 plane_state->crtc_y = 0;
9540 plane_state->crtc_w = hdisplay;
9541 plane_state->crtc_h = vdisplay;
9542 plane_state->src_x = x << 16;
9543 plane_state->src_y = y << 16;
9544 plane_state->src_w = hdisplay << 16;
9545 plane_state->src_h = vdisplay << 16;
9546
9547 return 0;
9548 }
9549
9550 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9551 struct drm_display_mode *mode,
9552 struct intel_load_detect_pipe *old,
9553 struct drm_modeset_acquire_ctx *ctx)
9554 {
9555 struct intel_crtc *intel_crtc;
9556 struct intel_encoder *intel_encoder =
9557 intel_attached_encoder(connector);
9558 struct drm_crtc *possible_crtc;
9559 struct drm_encoder *encoder = &intel_encoder->base;
9560 struct drm_crtc *crtc = NULL;
9561 struct drm_device *dev = encoder->dev;
9562 struct drm_i915_private *dev_priv = to_i915(dev);
9563 struct drm_framebuffer *fb;
9564 struct drm_mode_config *config = &dev->mode_config;
9565 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9566 struct drm_connector_state *connector_state;
9567 struct intel_crtc_state *crtc_state;
9568 int ret, i = -1;
9569
9570 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9571 connector->base.id, connector->name,
9572 encoder->base.id, encoder->name);
9573
9574 old->restore_state = NULL;
9575
9576 retry:
9577 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9578 if (ret)
9579 goto fail;
9580
9581 /*
9582 * Algorithm gets a little messy:
9583 *
9584 * - if the connector already has an assigned crtc, use it (but make
9585 * sure it's on first)
9586 *
9587 * - try to find the first unused crtc that can drive this connector,
9588 * and use that if we find one
9589 */
9590
9591 /* See if we already have a CRTC for this connector */
9592 if (connector->state->crtc) {
9593 crtc = connector->state->crtc;
9594
9595 ret = drm_modeset_lock(&crtc->mutex, ctx);
9596 if (ret)
9597 goto fail;
9598
9599 /* Make sure the crtc and connector are running */
9600 goto found;
9601 }
9602
9603 /* Find an unused one (if possible) */
9604 for_each_crtc(dev, possible_crtc) {
9605 i++;
9606 if (!(encoder->possible_crtcs & (1 << i)))
9607 continue;
9608
9609 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9610 if (ret)
9611 goto fail;
9612
9613 if (possible_crtc->state->enable) {
9614 drm_modeset_unlock(&possible_crtc->mutex);
9615 continue;
9616 }
9617
9618 crtc = possible_crtc;
9619 break;
9620 }
9621
9622 /*
9623 * If we didn't find an unused CRTC, don't use any.
9624 */
9625 if (!crtc) {
9626 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9627 goto fail;
9628 }
9629
9630 found:
9631 intel_crtc = to_intel_crtc(crtc);
9632
9633 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9634 if (ret)
9635 goto fail;
9636
9637 state = drm_atomic_state_alloc(dev);
9638 restore_state = drm_atomic_state_alloc(dev);
9639 if (!state || !restore_state) {
9640 ret = -ENOMEM;
9641 goto fail;
9642 }
9643
9644 state->acquire_ctx = ctx;
9645 restore_state->acquire_ctx = ctx;
9646
9647 connector_state = drm_atomic_get_connector_state(state, connector);
9648 if (IS_ERR(connector_state)) {
9649 ret = PTR_ERR(connector_state);
9650 goto fail;
9651 }
9652
9653 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9654 if (ret)
9655 goto fail;
9656
9657 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9658 if (IS_ERR(crtc_state)) {
9659 ret = PTR_ERR(crtc_state);
9660 goto fail;
9661 }
9662
9663 crtc_state->base.active = crtc_state->base.enable = true;
9664
9665 if (!mode)
9666 mode = &load_detect_mode;
9667
9668 /* We need a framebuffer large enough to accommodate all accesses
9669 * that the plane may generate whilst we perform load detection.
9670 * We can not rely on the fbcon either being present (we get called
9671 * during its initialisation to detect all boot displays, or it may
9672 * not even exist) or that it is large enough to satisfy the
9673 * requested mode.
9674 */
9675 fb = mode_fits_in_fbdev(dev, mode);
9676 if (fb == NULL) {
9677 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9678 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9679 } else
9680 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9681 if (IS_ERR(fb)) {
9682 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9683 goto fail;
9684 }
9685
9686 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9687 if (ret)
9688 goto fail;
9689
9690 drm_framebuffer_unreference(fb);
9691
9692 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9693 if (ret)
9694 goto fail;
9695
9696 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9697 if (!ret)
9698 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9699 if (!ret)
9700 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9701 if (ret) {
9702 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9703 goto fail;
9704 }
9705
9706 ret = drm_atomic_commit(state);
9707 if (ret) {
9708 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9709 goto fail;
9710 }
9711
9712 old->restore_state = restore_state;
9713 drm_atomic_state_put(state);
9714
9715 /* let the connector get through one full cycle before testing */
9716 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9717 return true;
9718
9719 fail:
9720 if (state) {
9721 drm_atomic_state_put(state);
9722 state = NULL;
9723 }
9724 if (restore_state) {
9725 drm_atomic_state_put(restore_state);
9726 restore_state = NULL;
9727 }
9728
9729 if (ret == -EDEADLK) {
9730 drm_modeset_backoff(ctx);
9731 goto retry;
9732 }
9733
9734 return false;
9735 }
9736
9737 void intel_release_load_detect_pipe(struct drm_connector *connector,
9738 struct intel_load_detect_pipe *old,
9739 struct drm_modeset_acquire_ctx *ctx)
9740 {
9741 struct intel_encoder *intel_encoder =
9742 intel_attached_encoder(connector);
9743 struct drm_encoder *encoder = &intel_encoder->base;
9744 struct drm_atomic_state *state = old->restore_state;
9745 int ret;
9746
9747 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9748 connector->base.id, connector->name,
9749 encoder->base.id, encoder->name);
9750
9751 if (!state)
9752 return;
9753
9754 ret = drm_atomic_commit(state);
9755 if (ret)
9756 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9757 drm_atomic_state_put(state);
9758 }
9759
9760 static int i9xx_pll_refclk(struct drm_device *dev,
9761 const struct intel_crtc_state *pipe_config)
9762 {
9763 struct drm_i915_private *dev_priv = to_i915(dev);
9764 u32 dpll = pipe_config->dpll_hw_state.dpll;
9765
9766 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9767 return dev_priv->vbt.lvds_ssc_freq;
9768 else if (HAS_PCH_SPLIT(dev_priv))
9769 return 120000;
9770 else if (!IS_GEN2(dev_priv))
9771 return 96000;
9772 else
9773 return 48000;
9774 }
9775
9776 /* Returns the clock of the currently programmed mode of the given pipe. */
9777 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9778 struct intel_crtc_state *pipe_config)
9779 {
9780 struct drm_device *dev = crtc->base.dev;
9781 struct drm_i915_private *dev_priv = to_i915(dev);
9782 int pipe = pipe_config->cpu_transcoder;
9783 u32 dpll = pipe_config->dpll_hw_state.dpll;
9784 u32 fp;
9785 struct dpll clock;
9786 int port_clock;
9787 int refclk = i9xx_pll_refclk(dev, pipe_config);
9788
9789 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9790 fp = pipe_config->dpll_hw_state.fp0;
9791 else
9792 fp = pipe_config->dpll_hw_state.fp1;
9793
9794 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9795 if (IS_PINEVIEW(dev_priv)) {
9796 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9797 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9798 } else {
9799 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9800 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9801 }
9802
9803 if (!IS_GEN2(dev_priv)) {
9804 if (IS_PINEVIEW(dev_priv))
9805 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9806 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9807 else
9808 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9809 DPLL_FPA01_P1_POST_DIV_SHIFT);
9810
9811 switch (dpll & DPLL_MODE_MASK) {
9812 case DPLLB_MODE_DAC_SERIAL:
9813 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9814 5 : 10;
9815 break;
9816 case DPLLB_MODE_LVDS:
9817 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9818 7 : 14;
9819 break;
9820 default:
9821 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9822 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9823 return;
9824 }
9825
9826 if (IS_PINEVIEW(dev_priv))
9827 port_clock = pnv_calc_dpll_params(refclk, &clock);
9828 else
9829 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9830 } else {
9831 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9832 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9833
9834 if (is_lvds) {
9835 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9836 DPLL_FPA01_P1_POST_DIV_SHIFT);
9837
9838 if (lvds & LVDS_CLKB_POWER_UP)
9839 clock.p2 = 7;
9840 else
9841 clock.p2 = 14;
9842 } else {
9843 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9844 clock.p1 = 2;
9845 else {
9846 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9847 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9848 }
9849 if (dpll & PLL_P2_DIVIDE_BY_4)
9850 clock.p2 = 4;
9851 else
9852 clock.p2 = 2;
9853 }
9854
9855 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9856 }
9857
9858 /*
9859 * This value includes pixel_multiplier. We will use
9860 * port_clock to compute adjusted_mode.crtc_clock in the
9861 * encoder's get_config() function.
9862 */
9863 pipe_config->port_clock = port_clock;
9864 }
9865
9866 int intel_dotclock_calculate(int link_freq,
9867 const struct intel_link_m_n *m_n)
9868 {
9869 /*
9870 * The calculation for the data clock is:
9871 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9872 * But we want to avoid losing precison if possible, so:
9873 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9874 *
9875 * and the link clock is simpler:
9876 * link_clock = (m * link_clock) / n
9877 */
9878
9879 if (!m_n->link_n)
9880 return 0;
9881
9882 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9883 }
9884
9885 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9886 struct intel_crtc_state *pipe_config)
9887 {
9888 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9889
9890 /* read out port_clock from the DPLL */
9891 i9xx_crtc_clock_get(crtc, pipe_config);
9892
9893 /*
9894 * In case there is an active pipe without active ports,
9895 * we may need some idea for the dotclock anyway.
9896 * Calculate one based on the FDI configuration.
9897 */
9898 pipe_config->base.adjusted_mode.crtc_clock =
9899 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9900 &pipe_config->fdi_m_n);
9901 }
9902
9903 /** Returns the currently programmed mode of the given pipe. */
9904 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9905 struct drm_crtc *crtc)
9906 {
9907 struct drm_i915_private *dev_priv = to_i915(dev);
9908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9909 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9910 struct drm_display_mode *mode;
9911 struct intel_crtc_state *pipe_config;
9912 int htot = I915_READ(HTOTAL(cpu_transcoder));
9913 int hsync = I915_READ(HSYNC(cpu_transcoder));
9914 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9915 int vsync = I915_READ(VSYNC(cpu_transcoder));
9916 enum pipe pipe = intel_crtc->pipe;
9917
9918 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9919 if (!mode)
9920 return NULL;
9921
9922 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9923 if (!pipe_config) {
9924 kfree(mode);
9925 return NULL;
9926 }
9927
9928 /*
9929 * Construct a pipe_config sufficient for getting the clock info
9930 * back out of crtc_clock_get.
9931 *
9932 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9933 * to use a real value here instead.
9934 */
9935 pipe_config->cpu_transcoder = (enum transcoder) pipe;
9936 pipe_config->pixel_multiplier = 1;
9937 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9938 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9939 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9940 i9xx_crtc_clock_get(intel_crtc, pipe_config);
9941
9942 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9943 mode->hdisplay = (htot & 0xffff) + 1;
9944 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9945 mode->hsync_start = (hsync & 0xffff) + 1;
9946 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9947 mode->vdisplay = (vtot & 0xffff) + 1;
9948 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9949 mode->vsync_start = (vsync & 0xffff) + 1;
9950 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9951
9952 drm_mode_set_name(mode);
9953
9954 kfree(pipe_config);
9955
9956 return mode;
9957 }
9958
9959 static void intel_crtc_destroy(struct drm_crtc *crtc)
9960 {
9961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9962 struct drm_device *dev = crtc->dev;
9963 struct intel_flip_work *work;
9964
9965 spin_lock_irq(&dev->event_lock);
9966 work = intel_crtc->flip_work;
9967 intel_crtc->flip_work = NULL;
9968 spin_unlock_irq(&dev->event_lock);
9969
9970 if (work) {
9971 cancel_work_sync(&work->mmio_work);
9972 cancel_work_sync(&work->unpin_work);
9973 kfree(work);
9974 }
9975
9976 drm_crtc_cleanup(crtc);
9977
9978 kfree(intel_crtc);
9979 }
9980
9981 static void intel_unpin_work_fn(struct work_struct *__work)
9982 {
9983 struct intel_flip_work *work =
9984 container_of(__work, struct intel_flip_work, unpin_work);
9985 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9986 struct drm_device *dev = crtc->base.dev;
9987 struct drm_plane *primary = crtc->base.primary;
9988
9989 if (is_mmio_work(work))
9990 flush_work(&work->mmio_work);
9991
9992 mutex_lock(&dev->struct_mutex);
9993 intel_unpin_fb_vma(work->old_vma);
9994 i915_gem_object_put(work->pending_flip_obj);
9995 mutex_unlock(&dev->struct_mutex);
9996
9997 i915_gem_request_put(work->flip_queued_req);
9998
9999 intel_frontbuffer_flip_complete(to_i915(dev),
10000 to_intel_plane(primary)->frontbuffer_bit);
10001 intel_fbc_post_update(crtc);
10002 drm_framebuffer_unreference(work->old_fb);
10003
10004 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10005 atomic_dec(&crtc->unpin_work_count);
10006
10007 kfree(work);
10008 }
10009
10010 /* Is 'a' after or equal to 'b'? */
10011 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10012 {
10013 return !((a - b) & 0x80000000);
10014 }
10015
10016 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
10017 struct intel_flip_work *work)
10018 {
10019 struct drm_device *dev = crtc->base.dev;
10020 struct drm_i915_private *dev_priv = to_i915(dev);
10021
10022 if (abort_flip_on_reset(crtc))
10023 return true;
10024
10025 /*
10026 * The relevant registers doen't exist on pre-ctg.
10027 * As the flip done interrupt doesn't trigger for mmio
10028 * flips on gmch platforms, a flip count check isn't
10029 * really needed there. But since ctg has the registers,
10030 * include it in the check anyway.
10031 */
10032 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10033 return true;
10034
10035 /*
10036 * BDW signals flip done immediately if the plane
10037 * is disabled, even if the plane enable is already
10038 * armed to occur at the next vblank :(
10039 */
10040
10041 /*
10042 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10043 * used the same base address. In that case the mmio flip might
10044 * have completed, but the CS hasn't even executed the flip yet.
10045 *
10046 * A flip count check isn't enough as the CS might have updated
10047 * the base address just after start of vblank, but before we
10048 * managed to process the interrupt. This means we'd complete the
10049 * CS flip too soon.
10050 *
10051 * Combining both checks should get us a good enough result. It may
10052 * still happen that the CS flip has been executed, but has not
10053 * yet actually completed. But in case the base address is the same
10054 * anyway, we don't really care.
10055 */
10056 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10057 crtc->flip_work->gtt_offset &&
10058 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10059 crtc->flip_work->flip_count);
10060 }
10061
10062 static bool
10063 __pageflip_finished_mmio(struct intel_crtc *crtc,
10064 struct intel_flip_work *work)
10065 {
10066 /*
10067 * MMIO work completes when vblank is different from
10068 * flip_queued_vblank.
10069 *
10070 * Reset counter value doesn't matter, this is handled by
10071 * i915_wait_request finishing early, so no need to handle
10072 * reset here.
10073 */
10074 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10075 }
10076
10077
10078 static bool pageflip_finished(struct intel_crtc *crtc,
10079 struct intel_flip_work *work)
10080 {
10081 if (!atomic_read(&work->pending))
10082 return false;
10083
10084 smp_rmb();
10085
10086 if (is_mmio_work(work))
10087 return __pageflip_finished_mmio(crtc, work);
10088 else
10089 return __pageflip_finished_cs(crtc, work);
10090 }
10091
10092 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10093 {
10094 struct drm_device *dev = &dev_priv->drm;
10095 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10096 struct intel_flip_work *work;
10097 unsigned long flags;
10098
10099 /* Ignore early vblank irqs */
10100 if (!crtc)
10101 return;
10102
10103 /*
10104 * This is called both by irq handlers and the reset code (to complete
10105 * lost pageflips) so needs the full irqsave spinlocks.
10106 */
10107 spin_lock_irqsave(&dev->event_lock, flags);
10108 work = crtc->flip_work;
10109
10110 if (work != NULL &&
10111 !is_mmio_work(work) &&
10112 pageflip_finished(crtc, work))
10113 page_flip_completed(crtc);
10114
10115 spin_unlock_irqrestore(&dev->event_lock, flags);
10116 }
10117
10118 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10119 {
10120 struct drm_device *dev = &dev_priv->drm;
10121 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10122 struct intel_flip_work *work;
10123 unsigned long flags;
10124
10125 /* Ignore early vblank irqs */
10126 if (!crtc)
10127 return;
10128
10129 /*
10130 * This is called both by irq handlers and the reset code (to complete
10131 * lost pageflips) so needs the full irqsave spinlocks.
10132 */
10133 spin_lock_irqsave(&dev->event_lock, flags);
10134 work = crtc->flip_work;
10135
10136 if (work != NULL &&
10137 is_mmio_work(work) &&
10138 pageflip_finished(crtc, work))
10139 page_flip_completed(crtc);
10140
10141 spin_unlock_irqrestore(&dev->event_lock, flags);
10142 }
10143
10144 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10145 struct intel_flip_work *work)
10146 {
10147 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10148
10149 /* Ensure that the work item is consistent when activating it ... */
10150 smp_mb__before_atomic();
10151 atomic_set(&work->pending, 1);
10152 }
10153
10154 static int intel_gen2_queue_flip(struct drm_device *dev,
10155 struct drm_crtc *crtc,
10156 struct drm_framebuffer *fb,
10157 struct drm_i915_gem_object *obj,
10158 struct drm_i915_gem_request *req,
10159 uint32_t flags)
10160 {
10161 struct intel_ring *ring = req->ring;
10162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10163 u32 flip_mask;
10164 int ret;
10165
10166 ret = intel_ring_begin(req, 6);
10167 if (ret)
10168 return ret;
10169
10170 /* Can't queue multiple flips, so wait for the previous
10171 * one to finish before executing the next.
10172 */
10173 if (intel_crtc->plane)
10174 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10175 else
10176 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10177 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10178 intel_ring_emit(ring, MI_NOOP);
10179 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10180 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10181 intel_ring_emit(ring, fb->pitches[0]);
10182 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
10183 intel_ring_emit(ring, 0); /* aux display base address, unused */
10184
10185 return 0;
10186 }
10187
10188 static int intel_gen3_queue_flip(struct drm_device *dev,
10189 struct drm_crtc *crtc,
10190 struct drm_framebuffer *fb,
10191 struct drm_i915_gem_object *obj,
10192 struct drm_i915_gem_request *req,
10193 uint32_t flags)
10194 {
10195 struct intel_ring *ring = req->ring;
10196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10197 u32 flip_mask;
10198 int ret;
10199
10200 ret = intel_ring_begin(req, 6);
10201 if (ret)
10202 return ret;
10203
10204 if (intel_crtc->plane)
10205 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10206 else
10207 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10208 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10209 intel_ring_emit(ring, MI_NOOP);
10210 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10211 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10212 intel_ring_emit(ring, fb->pitches[0]);
10213 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
10214 intel_ring_emit(ring, MI_NOOP);
10215
10216 return 0;
10217 }
10218
10219 static int intel_gen4_queue_flip(struct drm_device *dev,
10220 struct drm_crtc *crtc,
10221 struct drm_framebuffer *fb,
10222 struct drm_i915_gem_object *obj,
10223 struct drm_i915_gem_request *req,
10224 uint32_t flags)
10225 {
10226 struct intel_ring *ring = req->ring;
10227 struct drm_i915_private *dev_priv = to_i915(dev);
10228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10229 uint32_t pf, pipesrc;
10230 int ret;
10231
10232 ret = intel_ring_begin(req, 4);
10233 if (ret)
10234 return ret;
10235
10236 /* i965+ uses the linear or tiled offsets from the
10237 * Display Registers (which do not change across a page-flip)
10238 * so we need only reprogram the base address.
10239 */
10240 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10241 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10242 intel_ring_emit(ring, fb->pitches[0]);
10243 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
10244 intel_fb_modifier_to_tiling(fb->modifier));
10245
10246 /* XXX Enabling the panel-fitter across page-flip is so far
10247 * untested on non-native modes, so ignore it for now.
10248 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10249 */
10250 pf = 0;
10251 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10252 intel_ring_emit(ring, pf | pipesrc);
10253
10254 return 0;
10255 }
10256
10257 static int intel_gen6_queue_flip(struct drm_device *dev,
10258 struct drm_crtc *crtc,
10259 struct drm_framebuffer *fb,
10260 struct drm_i915_gem_object *obj,
10261 struct drm_i915_gem_request *req,
10262 uint32_t flags)
10263 {
10264 struct intel_ring *ring = req->ring;
10265 struct drm_i915_private *dev_priv = to_i915(dev);
10266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10267 uint32_t pf, pipesrc;
10268 int ret;
10269
10270 ret = intel_ring_begin(req, 4);
10271 if (ret)
10272 return ret;
10273
10274 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10275 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10276 intel_ring_emit(ring, fb->pitches[0] |
10277 intel_fb_modifier_to_tiling(fb->modifier));
10278 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
10279
10280 /* Contrary to the suggestions in the documentation,
10281 * "Enable Panel Fitter" does not seem to be required when page
10282 * flipping with a non-native mode, and worse causes a normal
10283 * modeset to fail.
10284 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10285 */
10286 pf = 0;
10287 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10288 intel_ring_emit(ring, pf | pipesrc);
10289
10290 return 0;
10291 }
10292
10293 static int intel_gen7_queue_flip(struct drm_device *dev,
10294 struct drm_crtc *crtc,
10295 struct drm_framebuffer *fb,
10296 struct drm_i915_gem_object *obj,
10297 struct drm_i915_gem_request *req,
10298 uint32_t flags)
10299 {
10300 struct drm_i915_private *dev_priv = to_i915(dev);
10301 struct intel_ring *ring = req->ring;
10302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10303 uint32_t plane_bit = 0;
10304 int len, ret;
10305
10306 switch (intel_crtc->plane) {
10307 case PLANE_A:
10308 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10309 break;
10310 case PLANE_B:
10311 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10312 break;
10313 case PLANE_C:
10314 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10315 break;
10316 default:
10317 WARN_ONCE(1, "unknown plane in flip command\n");
10318 return -ENODEV;
10319 }
10320
10321 len = 4;
10322 if (req->engine->id == RCS) {
10323 len += 6;
10324 /*
10325 * On Gen 8, SRM is now taking an extra dword to accommodate
10326 * 48bits addresses, and we need a NOOP for the batch size to
10327 * stay even.
10328 */
10329 if (IS_GEN8(dev_priv))
10330 len += 2;
10331 }
10332
10333 /*
10334 * BSpec MI_DISPLAY_FLIP for IVB:
10335 * "The full packet must be contained within the same cache line."
10336 *
10337 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10338 * cacheline, if we ever start emitting more commands before
10339 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10340 * then do the cacheline alignment, and finally emit the
10341 * MI_DISPLAY_FLIP.
10342 */
10343 ret = intel_ring_cacheline_align(req);
10344 if (ret)
10345 return ret;
10346
10347 ret = intel_ring_begin(req, len);
10348 if (ret)
10349 return ret;
10350
10351 /* Unmask the flip-done completion message. Note that the bspec says that
10352 * we should do this for both the BCS and RCS, and that we must not unmask
10353 * more than one flip event at any time (or ensure that one flip message
10354 * can be sent by waiting for flip-done prior to queueing new flips).
10355 * Experimentation says that BCS works despite DERRMR masking all
10356 * flip-done completion events and that unmasking all planes at once
10357 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10358 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10359 */
10360 if (req->engine->id == RCS) {
10361 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10362 intel_ring_emit_reg(ring, DERRMR);
10363 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10364 DERRMR_PIPEB_PRI_FLIP_DONE |
10365 DERRMR_PIPEC_PRI_FLIP_DONE));
10366 if (IS_GEN8(dev_priv))
10367 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
10368 MI_SRM_LRM_GLOBAL_GTT);
10369 else
10370 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
10371 MI_SRM_LRM_GLOBAL_GTT);
10372 intel_ring_emit_reg(ring, DERRMR);
10373 intel_ring_emit(ring,
10374 i915_ggtt_offset(req->engine->scratch) + 256);
10375 if (IS_GEN8(dev_priv)) {
10376 intel_ring_emit(ring, 0);
10377 intel_ring_emit(ring, MI_NOOP);
10378 }
10379 }
10380
10381 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10382 intel_ring_emit(ring, fb->pitches[0] |
10383 intel_fb_modifier_to_tiling(fb->modifier));
10384 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
10385 intel_ring_emit(ring, (MI_NOOP));
10386
10387 return 0;
10388 }
10389
10390 static bool use_mmio_flip(struct intel_engine_cs *engine,
10391 struct drm_i915_gem_object *obj)
10392 {
10393 /*
10394 * This is not being used for older platforms, because
10395 * non-availability of flip done interrupt forces us to use
10396 * CS flips. Older platforms derive flip done using some clever
10397 * tricks involving the flip_pending status bits and vblank irqs.
10398 * So using MMIO flips there would disrupt this mechanism.
10399 */
10400
10401 if (engine == NULL)
10402 return true;
10403
10404 if (INTEL_GEN(engine->i915) < 5)
10405 return false;
10406
10407 if (i915.use_mmio_flip < 0)
10408 return false;
10409 else if (i915.use_mmio_flip > 0)
10410 return true;
10411 else if (i915.enable_execlists)
10412 return true;
10413
10414 return engine != i915_gem_object_last_write_engine(obj);
10415 }
10416
10417 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10418 unsigned int rotation,
10419 struct intel_flip_work *work)
10420 {
10421 struct drm_device *dev = intel_crtc->base.dev;
10422 struct drm_i915_private *dev_priv = to_i915(dev);
10423 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10424 const enum pipe pipe = intel_crtc->pipe;
10425 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10426
10427 ctl = I915_READ(PLANE_CTL(pipe, 0));
10428 ctl &= ~PLANE_CTL_TILED_MASK;
10429 switch (fb->modifier) {
10430 case DRM_FORMAT_MOD_NONE:
10431 break;
10432 case I915_FORMAT_MOD_X_TILED:
10433 ctl |= PLANE_CTL_TILED_X;
10434 break;
10435 case I915_FORMAT_MOD_Y_TILED:
10436 ctl |= PLANE_CTL_TILED_Y;
10437 break;
10438 case I915_FORMAT_MOD_Yf_TILED:
10439 ctl |= PLANE_CTL_TILED_YF;
10440 break;
10441 default:
10442 MISSING_CASE(fb->modifier);
10443 }
10444
10445 /*
10446 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10447 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10448 */
10449 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10450 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10451
10452 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10453 POSTING_READ(PLANE_SURF(pipe, 0));
10454 }
10455
10456 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10457 struct intel_flip_work *work)
10458 {
10459 struct drm_device *dev = intel_crtc->base.dev;
10460 struct drm_i915_private *dev_priv = to_i915(dev);
10461 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10462 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10463 u32 dspcntr;
10464
10465 dspcntr = I915_READ(reg);
10466
10467 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10468 dspcntr |= DISPPLANE_TILED;
10469 else
10470 dspcntr &= ~DISPPLANE_TILED;
10471
10472 I915_WRITE(reg, dspcntr);
10473
10474 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10475 POSTING_READ(DSPSURF(intel_crtc->plane));
10476 }
10477
10478 static void intel_mmio_flip_work_func(struct work_struct *w)
10479 {
10480 struct intel_flip_work *work =
10481 container_of(w, struct intel_flip_work, mmio_work);
10482 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10483 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10484 struct intel_framebuffer *intel_fb =
10485 to_intel_framebuffer(crtc->base.primary->fb);
10486 struct drm_i915_gem_object *obj = intel_fb->obj;
10487
10488 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10489
10490 intel_pipe_update_start(crtc);
10491
10492 if (INTEL_GEN(dev_priv) >= 9)
10493 skl_do_mmio_flip(crtc, work->rotation, work);
10494 else
10495 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10496 ilk_do_mmio_flip(crtc, work);
10497
10498 intel_pipe_update_end(crtc, work);
10499 }
10500
10501 static int intel_default_queue_flip(struct drm_device *dev,
10502 struct drm_crtc *crtc,
10503 struct drm_framebuffer *fb,
10504 struct drm_i915_gem_object *obj,
10505 struct drm_i915_gem_request *req,
10506 uint32_t flags)
10507 {
10508 return -ENODEV;
10509 }
10510
10511 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10512 struct intel_crtc *intel_crtc,
10513 struct intel_flip_work *work)
10514 {
10515 u32 addr, vblank;
10516
10517 if (!atomic_read(&work->pending))
10518 return false;
10519
10520 smp_rmb();
10521
10522 vblank = intel_crtc_get_vblank_counter(intel_crtc);
10523 if (work->flip_ready_vblank == 0) {
10524 if (work->flip_queued_req &&
10525 !i915_gem_request_completed(work->flip_queued_req))
10526 return false;
10527
10528 work->flip_ready_vblank = vblank;
10529 }
10530
10531 if (vblank - work->flip_ready_vblank < 3)
10532 return false;
10533
10534 /* Potential stall - if we see that the flip has happened,
10535 * assume a missed interrupt. */
10536 if (INTEL_GEN(dev_priv) >= 4)
10537 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10538 else
10539 addr = I915_READ(DSPADDR(intel_crtc->plane));
10540
10541 /* There is a potential issue here with a false positive after a flip
10542 * to the same address. We could address this by checking for a
10543 * non-incrementing frame counter.
10544 */
10545 return addr == work->gtt_offset;
10546 }
10547
10548 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10549 {
10550 struct drm_device *dev = &dev_priv->drm;
10551 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10552 struct intel_flip_work *work;
10553
10554 WARN_ON(!in_interrupt());
10555
10556 if (crtc == NULL)
10557 return;
10558
10559 spin_lock(&dev->event_lock);
10560 work = crtc->flip_work;
10561
10562 if (work != NULL && !is_mmio_work(work) &&
10563 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10564 WARN_ONCE(1,
10565 "Kicking stuck page flip: queued at %d, now %d\n",
10566 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10567 page_flip_completed(crtc);
10568 work = NULL;
10569 }
10570
10571 if (work != NULL && !is_mmio_work(work) &&
10572 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10573 intel_queue_rps_boost_for_request(work->flip_queued_req);
10574 spin_unlock(&dev->event_lock);
10575 }
10576
10577 __maybe_unused
10578 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10579 struct drm_framebuffer *fb,
10580 struct drm_pending_vblank_event *event,
10581 uint32_t page_flip_flags)
10582 {
10583 struct drm_device *dev = crtc->dev;
10584 struct drm_i915_private *dev_priv = to_i915(dev);
10585 struct drm_framebuffer *old_fb = crtc->primary->fb;
10586 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10588 struct drm_plane *primary = crtc->primary;
10589 enum pipe pipe = intel_crtc->pipe;
10590 struct intel_flip_work *work;
10591 struct intel_engine_cs *engine;
10592 bool mmio_flip;
10593 struct drm_i915_gem_request *request;
10594 struct i915_vma *vma;
10595 int ret;
10596
10597 /*
10598 * drm_mode_page_flip_ioctl() should already catch this, but double
10599 * check to be safe. In the future we may enable pageflipping from
10600 * a disabled primary plane.
10601 */
10602 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10603 return -EBUSY;
10604
10605 /* Can't change pixel format via MI display flips. */
10606 if (fb->format != crtc->primary->fb->format)
10607 return -EINVAL;
10608
10609 /*
10610 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10611 * Note that pitch changes could also affect these register.
10612 */
10613 if (INTEL_GEN(dev_priv) > 3 &&
10614 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10615 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10616 return -EINVAL;
10617
10618 if (i915_terminally_wedged(&dev_priv->gpu_error))
10619 goto out_hang;
10620
10621 work = kzalloc(sizeof(*work), GFP_KERNEL);
10622 if (work == NULL)
10623 return -ENOMEM;
10624
10625 work->event = event;
10626 work->crtc = crtc;
10627 work->old_fb = old_fb;
10628 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10629
10630 ret = drm_crtc_vblank_get(crtc);
10631 if (ret)
10632 goto free_work;
10633
10634 /* We borrow the event spin lock for protecting flip_work */
10635 spin_lock_irq(&dev->event_lock);
10636 if (intel_crtc->flip_work) {
10637 /* Before declaring the flip queue wedged, check if
10638 * the hardware completed the operation behind our backs.
10639 */
10640 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10641 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10642 page_flip_completed(intel_crtc);
10643 } else {
10644 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10645 spin_unlock_irq(&dev->event_lock);
10646
10647 drm_crtc_vblank_put(crtc);
10648 kfree(work);
10649 return -EBUSY;
10650 }
10651 }
10652 intel_crtc->flip_work = work;
10653 spin_unlock_irq(&dev->event_lock);
10654
10655 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10656 flush_workqueue(dev_priv->wq);
10657
10658 /* Reference the objects for the scheduled work. */
10659 drm_framebuffer_reference(work->old_fb);
10660
10661 crtc->primary->fb = fb;
10662 update_state_fb(crtc->primary);
10663
10664 work->pending_flip_obj = i915_gem_object_get(obj);
10665
10666 ret = i915_mutex_lock_interruptible(dev);
10667 if (ret)
10668 goto cleanup;
10669
10670 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10671 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
10672 ret = -EIO;
10673 goto unlock;
10674 }
10675
10676 atomic_inc(&intel_crtc->unpin_work_count);
10677
10678 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10679 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10680
10681 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10682 engine = dev_priv->engine[BCS];
10683 if (fb->modifier != old_fb->modifier)
10684 /* vlv: DISPLAY_FLIP fails to change tiling */
10685 engine = NULL;
10686 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10687 engine = dev_priv->engine[BCS];
10688 } else if (INTEL_GEN(dev_priv) >= 7) {
10689 engine = i915_gem_object_last_write_engine(obj);
10690 if (engine == NULL || engine->id != RCS)
10691 engine = dev_priv->engine[BCS];
10692 } else {
10693 engine = dev_priv->engine[RCS];
10694 }
10695
10696 mmio_flip = use_mmio_flip(engine, obj);
10697
10698 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10699 if (IS_ERR(vma)) {
10700 ret = PTR_ERR(vma);
10701 goto cleanup_pending;
10702 }
10703
10704 work->old_vma = to_intel_plane_state(primary->state)->vma;
10705 to_intel_plane_state(primary->state)->vma = vma;
10706
10707 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10708 work->rotation = crtc->primary->state->rotation;
10709
10710 /*
10711 * There's the potential that the next frame will not be compatible with
10712 * FBC, so we want to call pre_update() before the actual page flip.
10713 * The problem is that pre_update() caches some information about the fb
10714 * object, so we want to do this only after the object is pinned. Let's
10715 * be on the safe side and do this immediately before scheduling the
10716 * flip.
10717 */
10718 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10719 to_intel_plane_state(primary->state));
10720
10721 if (mmio_flip) {
10722 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10723 queue_work(system_unbound_wq, &work->mmio_work);
10724 } else {
10725 request = i915_gem_request_alloc(engine,
10726 dev_priv->kernel_context);
10727 if (IS_ERR(request)) {
10728 ret = PTR_ERR(request);
10729 goto cleanup_unpin;
10730 }
10731
10732 ret = i915_gem_request_await_object(request, obj, false);
10733 if (ret)
10734 goto cleanup_request;
10735
10736 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10737 page_flip_flags);
10738 if (ret)
10739 goto cleanup_request;
10740
10741 intel_mark_page_flip_active(intel_crtc, work);
10742
10743 work->flip_queued_req = i915_gem_request_get(request);
10744 i915_add_request_no_flush(request);
10745 }
10746
10747 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10748 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10749 to_intel_plane(primary)->frontbuffer_bit);
10750 mutex_unlock(&dev->struct_mutex);
10751
10752 intel_frontbuffer_flip_prepare(to_i915(dev),
10753 to_intel_plane(primary)->frontbuffer_bit);
10754
10755 trace_i915_flip_request(intel_crtc->plane, obj);
10756
10757 return 0;
10758
10759 cleanup_request:
10760 i915_add_request_no_flush(request);
10761 cleanup_unpin:
10762 to_intel_plane_state(primary->state)->vma = work->old_vma;
10763 intel_unpin_fb_vma(vma);
10764 cleanup_pending:
10765 atomic_dec(&intel_crtc->unpin_work_count);
10766 unlock:
10767 mutex_unlock(&dev->struct_mutex);
10768 cleanup:
10769 crtc->primary->fb = old_fb;
10770 update_state_fb(crtc->primary);
10771
10772 i915_gem_object_put(obj);
10773 drm_framebuffer_unreference(work->old_fb);
10774
10775 spin_lock_irq(&dev->event_lock);
10776 intel_crtc->flip_work = NULL;
10777 spin_unlock_irq(&dev->event_lock);
10778
10779 drm_crtc_vblank_put(crtc);
10780 free_work:
10781 kfree(work);
10782
10783 if (ret == -EIO) {
10784 struct drm_atomic_state *state;
10785 struct drm_plane_state *plane_state;
10786
10787 out_hang:
10788 state = drm_atomic_state_alloc(dev);
10789 if (!state)
10790 return -ENOMEM;
10791 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
10792
10793 retry:
10794 plane_state = drm_atomic_get_plane_state(state, primary);
10795 ret = PTR_ERR_OR_ZERO(plane_state);
10796 if (!ret) {
10797 drm_atomic_set_fb_for_plane(plane_state, fb);
10798
10799 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10800 if (!ret)
10801 ret = drm_atomic_commit(state);
10802 }
10803
10804 if (ret == -EDEADLK) {
10805 drm_modeset_backoff(state->acquire_ctx);
10806 drm_atomic_state_clear(state);
10807 goto retry;
10808 }
10809
10810 drm_atomic_state_put(state);
10811
10812 if (ret == 0 && event) {
10813 spin_lock_irq(&dev->event_lock);
10814 drm_crtc_send_vblank_event(crtc, event);
10815 spin_unlock_irq(&dev->event_lock);
10816 }
10817 }
10818 return ret;
10819 }
10820
10821
10822 /**
10823 * intel_wm_need_update - Check whether watermarks need updating
10824 * @plane: drm plane
10825 * @state: new plane state
10826 *
10827 * Check current plane state versus the new one to determine whether
10828 * watermarks need to be recalculated.
10829 *
10830 * Returns true or false.
10831 */
10832 static bool intel_wm_need_update(struct drm_plane *plane,
10833 struct drm_plane_state *state)
10834 {
10835 struct intel_plane_state *new = to_intel_plane_state(state);
10836 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10837
10838 /* Update watermarks on tiling or size changes. */
10839 if (new->base.visible != cur->base.visible)
10840 return true;
10841
10842 if (!cur->base.fb || !new->base.fb)
10843 return false;
10844
10845 if (cur->base.fb->modifier != new->base.fb->modifier ||
10846 cur->base.rotation != new->base.rotation ||
10847 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10848 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10849 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10850 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10851 return true;
10852
10853 return false;
10854 }
10855
10856 static bool needs_scaling(struct intel_plane_state *state)
10857 {
10858 int src_w = drm_rect_width(&state->base.src) >> 16;
10859 int src_h = drm_rect_height(&state->base.src) >> 16;
10860 int dst_w = drm_rect_width(&state->base.dst);
10861 int dst_h = drm_rect_height(&state->base.dst);
10862
10863 return (src_w != dst_w || src_h != dst_h);
10864 }
10865
10866 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10867 struct drm_plane_state *plane_state)
10868 {
10869 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10870 struct drm_crtc *crtc = crtc_state->crtc;
10871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10872 struct drm_plane *plane = plane_state->plane;
10873 struct drm_device *dev = crtc->dev;
10874 struct drm_i915_private *dev_priv = to_i915(dev);
10875 struct intel_plane_state *old_plane_state =
10876 to_intel_plane_state(plane->state);
10877 bool mode_changed = needs_modeset(crtc_state);
10878 bool was_crtc_enabled = crtc->state->active;
10879 bool is_crtc_enabled = crtc_state->active;
10880 bool turn_off, turn_on, visible, was_visible;
10881 struct drm_framebuffer *fb = plane_state->fb;
10882 int ret;
10883
10884 if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
10885 ret = skl_update_scaler_plane(
10886 to_intel_crtc_state(crtc_state),
10887 to_intel_plane_state(plane_state));
10888 if (ret)
10889 return ret;
10890 }
10891
10892 was_visible = old_plane_state->base.visible;
10893 visible = plane_state->visible;
10894
10895 if (!was_crtc_enabled && WARN_ON(was_visible))
10896 was_visible = false;
10897
10898 /*
10899 * Visibility is calculated as if the crtc was on, but
10900 * after scaler setup everything depends on it being off
10901 * when the crtc isn't active.
10902 *
10903 * FIXME this is wrong for watermarks. Watermarks should also
10904 * be computed as if the pipe would be active. Perhaps move
10905 * per-plane wm computation to the .check_plane() hook, and
10906 * only combine the results from all planes in the current place?
10907 */
10908 if (!is_crtc_enabled)
10909 plane_state->visible = visible = false;
10910
10911 if (!was_visible && !visible)
10912 return 0;
10913
10914 if (fb != old_plane_state->base.fb)
10915 pipe_config->fb_changed = true;
10916
10917 turn_off = was_visible && (!visible || mode_changed);
10918 turn_on = visible && (!was_visible || mode_changed);
10919
10920 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10921 intel_crtc->base.base.id,
10922 intel_crtc->base.name,
10923 plane->base.id, plane->name,
10924 fb ? fb->base.id : -1);
10925
10926 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10927 plane->base.id, plane->name,
10928 was_visible, visible,
10929 turn_off, turn_on, mode_changed);
10930
10931 if (turn_on) {
10932 pipe_config->update_wm_pre = true;
10933
10934 /* must disable cxsr around plane enable/disable */
10935 if (plane->type != DRM_PLANE_TYPE_CURSOR)
10936 pipe_config->disable_cxsr = true;
10937 } else if (turn_off) {
10938 pipe_config->update_wm_post = true;
10939
10940 /* must disable cxsr around plane enable/disable */
10941 if (plane->type != DRM_PLANE_TYPE_CURSOR)
10942 pipe_config->disable_cxsr = true;
10943 } else if (intel_wm_need_update(plane, plane_state)) {
10944 /* FIXME bollocks */
10945 pipe_config->update_wm_pre = true;
10946 pipe_config->update_wm_post = true;
10947 }
10948
10949 /* Pre-gen9 platforms need two-step watermark updates */
10950 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
10951 INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
10952 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
10953
10954 if (visible || was_visible)
10955 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
10956
10957 /*
10958 * WaCxSRDisabledForSpriteScaling:ivb
10959 *
10960 * cstate->update_wm was already set above, so this flag will
10961 * take effect when we commit and program watermarks.
10962 */
10963 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
10964 needs_scaling(to_intel_plane_state(plane_state)) &&
10965 !needs_scaling(old_plane_state))
10966 pipe_config->disable_lp_wm = true;
10967
10968 return 0;
10969 }
10970
10971 static bool encoders_cloneable(const struct intel_encoder *a,
10972 const struct intel_encoder *b)
10973 {
10974 /* masks could be asymmetric, so check both ways */
10975 return a == b || (a->cloneable & (1 << b->type) &&
10976 b->cloneable & (1 << a->type));
10977 }
10978
10979 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10980 struct intel_crtc *crtc,
10981 struct intel_encoder *encoder)
10982 {
10983 struct intel_encoder *source_encoder;
10984 struct drm_connector *connector;
10985 struct drm_connector_state *connector_state;
10986 int i;
10987
10988 for_each_connector_in_state(state, connector, connector_state, i) {
10989 if (connector_state->crtc != &crtc->base)
10990 continue;
10991
10992 source_encoder =
10993 to_intel_encoder(connector_state->best_encoder);
10994 if (!encoders_cloneable(encoder, source_encoder))
10995 return false;
10996 }
10997
10998 return true;
10999 }
11000
11001 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11002 struct drm_crtc_state *crtc_state)
11003 {
11004 struct drm_device *dev = crtc->dev;
11005 struct drm_i915_private *dev_priv = to_i915(dev);
11006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11007 struct intel_crtc_state *pipe_config =
11008 to_intel_crtc_state(crtc_state);
11009 struct drm_atomic_state *state = crtc_state->state;
11010 int ret;
11011 bool mode_changed = needs_modeset(crtc_state);
11012
11013 if (mode_changed && !crtc_state->active)
11014 pipe_config->update_wm_post = true;
11015
11016 if (mode_changed && crtc_state->enable &&
11017 dev_priv->display.crtc_compute_clock &&
11018 !WARN_ON(pipe_config->shared_dpll)) {
11019 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11020 pipe_config);
11021 if (ret)
11022 return ret;
11023 }
11024
11025 if (crtc_state->color_mgmt_changed) {
11026 ret = intel_color_check(crtc, crtc_state);
11027 if (ret)
11028 return ret;
11029
11030 /*
11031 * Changing color management on Intel hardware is
11032 * handled as part of planes update.
11033 */
11034 crtc_state->planes_changed = true;
11035 }
11036
11037 ret = 0;
11038 if (dev_priv->display.compute_pipe_wm) {
11039 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11040 if (ret) {
11041 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11042 return ret;
11043 }
11044 }
11045
11046 if (dev_priv->display.compute_intermediate_wm &&
11047 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11048 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11049 return 0;
11050
11051 /*
11052 * Calculate 'intermediate' watermarks that satisfy both the
11053 * old state and the new state. We can program these
11054 * immediately.
11055 */
11056 ret = dev_priv->display.compute_intermediate_wm(dev,
11057 intel_crtc,
11058 pipe_config);
11059 if (ret) {
11060 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11061 return ret;
11062 }
11063 } else if (dev_priv->display.compute_intermediate_wm) {
11064 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11065 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11066 }
11067
11068 if (INTEL_GEN(dev_priv) >= 9) {
11069 if (mode_changed)
11070 ret = skl_update_scaler_crtc(pipe_config);
11071
11072 if (!ret)
11073 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11074 pipe_config);
11075 }
11076
11077 return ret;
11078 }
11079
11080 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11081 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11082 .atomic_begin = intel_begin_crtc_commit,
11083 .atomic_flush = intel_finish_crtc_commit,
11084 .atomic_check = intel_crtc_atomic_check,
11085 };
11086
11087 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11088 {
11089 struct intel_connector *connector;
11090
11091 for_each_intel_connector(dev, connector) {
11092 if (connector->base.state->crtc)
11093 drm_connector_unreference(&connector->base);
11094
11095 if (connector->base.encoder) {
11096 connector->base.state->best_encoder =
11097 connector->base.encoder;
11098 connector->base.state->crtc =
11099 connector->base.encoder->crtc;
11100
11101 drm_connector_reference(&connector->base);
11102 } else {
11103 connector->base.state->best_encoder = NULL;
11104 connector->base.state->crtc = NULL;
11105 }
11106 }
11107 }
11108
11109 static void
11110 connected_sink_compute_bpp(struct intel_connector *connector,
11111 struct intel_crtc_state *pipe_config)
11112 {
11113 const struct drm_display_info *info = &connector->base.display_info;
11114 int bpp = pipe_config->pipe_bpp;
11115
11116 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11117 connector->base.base.id,
11118 connector->base.name);
11119
11120 /* Don't use an invalid EDID bpc value */
11121 if (info->bpc != 0 && info->bpc * 3 < bpp) {
11122 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11123 bpp, info->bpc * 3);
11124 pipe_config->pipe_bpp = info->bpc * 3;
11125 }
11126
11127 /* Clamp bpp to 8 on screens without EDID 1.4 */
11128 if (info->bpc == 0 && bpp > 24) {
11129 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11130 bpp);
11131 pipe_config->pipe_bpp = 24;
11132 }
11133 }
11134
11135 static int
11136 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11137 struct intel_crtc_state *pipe_config)
11138 {
11139 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11140 struct drm_atomic_state *state;
11141 struct drm_connector *connector;
11142 struct drm_connector_state *connector_state;
11143 int bpp, i;
11144
11145 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11146 IS_CHERRYVIEW(dev_priv)))
11147 bpp = 10*3;
11148 else if (INTEL_GEN(dev_priv) >= 5)
11149 bpp = 12*3;
11150 else
11151 bpp = 8*3;
11152
11153
11154 pipe_config->pipe_bpp = bpp;
11155
11156 state = pipe_config->base.state;
11157
11158 /* Clamp display bpp to EDID value */
11159 for_each_connector_in_state(state, connector, connector_state, i) {
11160 if (connector_state->crtc != &crtc->base)
11161 continue;
11162
11163 connected_sink_compute_bpp(to_intel_connector(connector),
11164 pipe_config);
11165 }
11166
11167 return bpp;
11168 }
11169
11170 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11171 {
11172 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11173 "type: 0x%x flags: 0x%x\n",
11174 mode->crtc_clock,
11175 mode->crtc_hdisplay, mode->crtc_hsync_start,
11176 mode->crtc_hsync_end, mode->crtc_htotal,
11177 mode->crtc_vdisplay, mode->crtc_vsync_start,
11178 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11179 }
11180
11181 static inline void
11182 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11183 unsigned int lane_count, struct intel_link_m_n *m_n)
11184 {
11185 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11186 id, lane_count,
11187 m_n->gmch_m, m_n->gmch_n,
11188 m_n->link_m, m_n->link_n, m_n->tu);
11189 }
11190
11191 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11192 struct intel_crtc_state *pipe_config,
11193 const char *context)
11194 {
11195 struct drm_device *dev = crtc->base.dev;
11196 struct drm_i915_private *dev_priv = to_i915(dev);
11197 struct drm_plane *plane;
11198 struct intel_plane *intel_plane;
11199 struct intel_plane_state *state;
11200 struct drm_framebuffer *fb;
11201
11202 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11203 crtc->base.base.id, crtc->base.name, context);
11204
11205 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11206 transcoder_name(pipe_config->cpu_transcoder),
11207 pipe_config->pipe_bpp, pipe_config->dither);
11208
11209 if (pipe_config->has_pch_encoder)
11210 intel_dump_m_n_config(pipe_config, "fdi",
11211 pipe_config->fdi_lanes,
11212 &pipe_config->fdi_m_n);
11213
11214 if (intel_crtc_has_dp_encoder(pipe_config)) {
11215 intel_dump_m_n_config(pipe_config, "dp m_n",
11216 pipe_config->lane_count, &pipe_config->dp_m_n);
11217 if (pipe_config->has_drrs)
11218 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11219 pipe_config->lane_count,
11220 &pipe_config->dp_m2_n2);
11221 }
11222
11223 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11224 pipe_config->has_audio, pipe_config->has_infoframe);
11225
11226 DRM_DEBUG_KMS("requested mode:\n");
11227 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11228 DRM_DEBUG_KMS("adjusted mode:\n");
11229 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11230 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11231 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11232 pipe_config->port_clock,
11233 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11234 pipe_config->pixel_rate);
11235
11236 if (INTEL_GEN(dev_priv) >= 9)
11237 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11238 crtc->num_scalers,
11239 pipe_config->scaler_state.scaler_users,
11240 pipe_config->scaler_state.scaler_id);
11241
11242 if (HAS_GMCH_DISPLAY(dev_priv))
11243 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11244 pipe_config->gmch_pfit.control,
11245 pipe_config->gmch_pfit.pgm_ratios,
11246 pipe_config->gmch_pfit.lvds_border_bits);
11247 else
11248 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11249 pipe_config->pch_pfit.pos,
11250 pipe_config->pch_pfit.size,
11251 enableddisabled(pipe_config->pch_pfit.enabled));
11252
11253 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11254 pipe_config->ips_enabled, pipe_config->double_wide);
11255
11256 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11257
11258 DRM_DEBUG_KMS("planes on this crtc\n");
11259 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11260 struct drm_format_name_buf format_name;
11261 intel_plane = to_intel_plane(plane);
11262 if (intel_plane->pipe != crtc->pipe)
11263 continue;
11264
11265 state = to_intel_plane_state(plane->state);
11266 fb = state->base.fb;
11267 if (!fb) {
11268 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11269 plane->base.id, plane->name, state->scaler_id);
11270 continue;
11271 }
11272
11273 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11274 plane->base.id, plane->name,
11275 fb->base.id, fb->width, fb->height,
11276 drm_get_format_name(fb->format->format, &format_name));
11277 if (INTEL_GEN(dev_priv) >= 9)
11278 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11279 state->scaler_id,
11280 state->base.src.x1 >> 16,
11281 state->base.src.y1 >> 16,
11282 drm_rect_width(&state->base.src) >> 16,
11283 drm_rect_height(&state->base.src) >> 16,
11284 state->base.dst.x1, state->base.dst.y1,
11285 drm_rect_width(&state->base.dst),
11286 drm_rect_height(&state->base.dst));
11287 }
11288 }
11289
11290 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11291 {
11292 struct drm_device *dev = state->dev;
11293 struct drm_connector *connector;
11294 unsigned int used_ports = 0;
11295 unsigned int used_mst_ports = 0;
11296
11297 /*
11298 * Walk the connector list instead of the encoder
11299 * list to detect the problem on ddi platforms
11300 * where there's just one encoder per digital port.
11301 */
11302 drm_for_each_connector(connector, dev) {
11303 struct drm_connector_state *connector_state;
11304 struct intel_encoder *encoder;
11305
11306 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11307 if (!connector_state)
11308 connector_state = connector->state;
11309
11310 if (!connector_state->best_encoder)
11311 continue;
11312
11313 encoder = to_intel_encoder(connector_state->best_encoder);
11314
11315 WARN_ON(!connector_state->crtc);
11316
11317 switch (encoder->type) {
11318 unsigned int port_mask;
11319 case INTEL_OUTPUT_UNKNOWN:
11320 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11321 break;
11322 case INTEL_OUTPUT_DP:
11323 case INTEL_OUTPUT_HDMI:
11324 case INTEL_OUTPUT_EDP:
11325 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11326
11327 /* the same port mustn't appear more than once */
11328 if (used_ports & port_mask)
11329 return false;
11330
11331 used_ports |= port_mask;
11332 break;
11333 case INTEL_OUTPUT_DP_MST:
11334 used_mst_ports |=
11335 1 << enc_to_mst(&encoder->base)->primary->port;
11336 break;
11337 default:
11338 break;
11339 }
11340 }
11341
11342 /* can't mix MST and SST/HDMI on the same port */
11343 if (used_ports & used_mst_ports)
11344 return false;
11345
11346 return true;
11347 }
11348
11349 static void
11350 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11351 {
11352 struct drm_crtc_state tmp_state;
11353 struct intel_crtc_scaler_state scaler_state;
11354 struct intel_dpll_hw_state dpll_hw_state;
11355 struct intel_shared_dpll *shared_dpll;
11356 bool force_thru;
11357
11358 /* FIXME: before the switch to atomic started, a new pipe_config was
11359 * kzalloc'd. Code that depends on any field being zero should be
11360 * fixed, so that the crtc_state can be safely duplicated. For now,
11361 * only fields that are know to not cause problems are preserved. */
11362
11363 tmp_state = crtc_state->base;
11364 scaler_state = crtc_state->scaler_state;
11365 shared_dpll = crtc_state->shared_dpll;
11366 dpll_hw_state = crtc_state->dpll_hw_state;
11367 force_thru = crtc_state->pch_pfit.force_thru;
11368
11369 memset(crtc_state, 0, sizeof *crtc_state);
11370
11371 crtc_state->base = tmp_state;
11372 crtc_state->scaler_state = scaler_state;
11373 crtc_state->shared_dpll = shared_dpll;
11374 crtc_state->dpll_hw_state = dpll_hw_state;
11375 crtc_state->pch_pfit.force_thru = force_thru;
11376 }
11377
11378 static int
11379 intel_modeset_pipe_config(struct drm_crtc *crtc,
11380 struct intel_crtc_state *pipe_config)
11381 {
11382 struct drm_atomic_state *state = pipe_config->base.state;
11383 struct intel_encoder *encoder;
11384 struct drm_connector *connector;
11385 struct drm_connector_state *connector_state;
11386 int base_bpp, ret = -EINVAL;
11387 int i;
11388 bool retry = true;
11389
11390 clear_intel_crtc_state(pipe_config);
11391
11392 pipe_config->cpu_transcoder =
11393 (enum transcoder) to_intel_crtc(crtc)->pipe;
11394
11395 /*
11396 * Sanitize sync polarity flags based on requested ones. If neither
11397 * positive or negative polarity is requested, treat this as meaning
11398 * negative polarity.
11399 */
11400 if (!(pipe_config->base.adjusted_mode.flags &
11401 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11402 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11403
11404 if (!(pipe_config->base.adjusted_mode.flags &
11405 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11406 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11407
11408 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11409 pipe_config);
11410 if (base_bpp < 0)
11411 goto fail;
11412
11413 /*
11414 * Determine the real pipe dimensions. Note that stereo modes can
11415 * increase the actual pipe size due to the frame doubling and
11416 * insertion of additional space for blanks between the frame. This
11417 * is stored in the crtc timings. We use the requested mode to do this
11418 * computation to clearly distinguish it from the adjusted mode, which
11419 * can be changed by the connectors in the below retry loop.
11420 */
11421 drm_mode_get_hv_timing(&pipe_config->base.mode,
11422 &pipe_config->pipe_src_w,
11423 &pipe_config->pipe_src_h);
11424
11425 for_each_connector_in_state(state, connector, connector_state, i) {
11426 if (connector_state->crtc != crtc)
11427 continue;
11428
11429 encoder = to_intel_encoder(connector_state->best_encoder);
11430
11431 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11432 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11433 goto fail;
11434 }
11435
11436 /*
11437 * Determine output_types before calling the .compute_config()
11438 * hooks so that the hooks can use this information safely.
11439 */
11440 pipe_config->output_types |= 1 << encoder->type;
11441 }
11442
11443 encoder_retry:
11444 /* Ensure the port clock defaults are reset when retrying. */
11445 pipe_config->port_clock = 0;
11446 pipe_config->pixel_multiplier = 1;
11447
11448 /* Fill in default crtc timings, allow encoders to overwrite them. */
11449 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11450 CRTC_STEREO_DOUBLE);
11451
11452 /* Pass our mode to the connectors and the CRTC to give them a chance to
11453 * adjust it according to limitations or connector properties, and also
11454 * a chance to reject the mode entirely.
11455 */
11456 for_each_connector_in_state(state, connector, connector_state, i) {
11457 if (connector_state->crtc != crtc)
11458 continue;
11459
11460 encoder = to_intel_encoder(connector_state->best_encoder);
11461
11462 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11463 DRM_DEBUG_KMS("Encoder config failure\n");
11464 goto fail;
11465 }
11466 }
11467
11468 /* Set default port clock if not overwritten by the encoder. Needs to be
11469 * done afterwards in case the encoder adjusts the mode. */
11470 if (!pipe_config->port_clock)
11471 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11472 * pipe_config->pixel_multiplier;
11473
11474 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11475 if (ret < 0) {
11476 DRM_DEBUG_KMS("CRTC fixup failed\n");
11477 goto fail;
11478 }
11479
11480 if (ret == RETRY) {
11481 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11482 ret = -EINVAL;
11483 goto fail;
11484 }
11485
11486 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11487 retry = false;
11488 goto encoder_retry;
11489 }
11490
11491 /* Dithering seems to not pass-through bits correctly when it should, so
11492 * only enable it on 6bpc panels and when its not a compliance
11493 * test requesting 6bpc video pattern.
11494 */
11495 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11496 !pipe_config->dither_force_disable;
11497 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11498 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11499
11500 fail:
11501 return ret;
11502 }
11503
11504 static void
11505 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11506 {
11507 struct drm_crtc *crtc;
11508 struct drm_crtc_state *crtc_state;
11509 int i;
11510
11511 /* Double check state. */
11512 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11513 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
11514
11515 /* Update hwmode for vblank functions */
11516 if (crtc->state->active)
11517 crtc->hwmode = crtc->state->adjusted_mode;
11518 else
11519 crtc->hwmode.crtc_clock = 0;
11520
11521 /*
11522 * Update legacy state to satisfy fbc code. This can
11523 * be removed when fbc uses the atomic state.
11524 */
11525 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11526 struct drm_plane_state *plane_state = crtc->primary->state;
11527
11528 crtc->primary->fb = plane_state->fb;
11529 crtc->x = plane_state->src_x >> 16;
11530 crtc->y = plane_state->src_y >> 16;
11531 }
11532 }
11533 }
11534
11535 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11536 {
11537 int diff;
11538
11539 if (clock1 == clock2)
11540 return true;
11541
11542 if (!clock1 || !clock2)
11543 return false;
11544
11545 diff = abs(clock1 - clock2);
11546
11547 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11548 return true;
11549
11550 return false;
11551 }
11552
11553 static bool
11554 intel_compare_m_n(unsigned int m, unsigned int n,
11555 unsigned int m2, unsigned int n2,
11556 bool exact)
11557 {
11558 if (m == m2 && n == n2)
11559 return true;
11560
11561 if (exact || !m || !n || !m2 || !n2)
11562 return false;
11563
11564 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11565
11566 if (n > n2) {
11567 while (n > n2) {
11568 m2 <<= 1;
11569 n2 <<= 1;
11570 }
11571 } else if (n < n2) {
11572 while (n < n2) {
11573 m <<= 1;
11574 n <<= 1;
11575 }
11576 }
11577
11578 if (n != n2)
11579 return false;
11580
11581 return intel_fuzzy_clock_check(m, m2);
11582 }
11583
11584 static bool
11585 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11586 struct intel_link_m_n *m2_n2,
11587 bool adjust)
11588 {
11589 if (m_n->tu == m2_n2->tu &&
11590 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11591 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11592 intel_compare_m_n(m_n->link_m, m_n->link_n,
11593 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11594 if (adjust)
11595 *m2_n2 = *m_n;
11596
11597 return true;
11598 }
11599
11600 return false;
11601 }
11602
11603 static void __printf(3, 4)
11604 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11605 {
11606 char *level;
11607 unsigned int category;
11608 struct va_format vaf;
11609 va_list args;
11610
11611 if (adjust) {
11612 level = KERN_DEBUG;
11613 category = DRM_UT_KMS;
11614 } else {
11615 level = KERN_ERR;
11616 category = DRM_UT_NONE;
11617 }
11618
11619 va_start(args, format);
11620 vaf.fmt = format;
11621 vaf.va = &args;
11622
11623 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11624
11625 va_end(args);
11626 }
11627
11628 static bool
11629 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11630 struct intel_crtc_state *current_config,
11631 struct intel_crtc_state *pipe_config,
11632 bool adjust)
11633 {
11634 bool ret = true;
11635
11636 #define PIPE_CONF_CHECK_X(name) \
11637 if (current_config->name != pipe_config->name) { \
11638 pipe_config_err(adjust, __stringify(name), \
11639 "(expected 0x%08x, found 0x%08x)\n", \
11640 current_config->name, \
11641 pipe_config->name); \
11642 ret = false; \
11643 }
11644
11645 #define PIPE_CONF_CHECK_I(name) \
11646 if (current_config->name != pipe_config->name) { \
11647 pipe_config_err(adjust, __stringify(name), \
11648 "(expected %i, found %i)\n", \
11649 current_config->name, \
11650 pipe_config->name); \
11651 ret = false; \
11652 }
11653
11654 #define PIPE_CONF_CHECK_P(name) \
11655 if (current_config->name != pipe_config->name) { \
11656 pipe_config_err(adjust, __stringify(name), \
11657 "(expected %p, found %p)\n", \
11658 current_config->name, \
11659 pipe_config->name); \
11660 ret = false; \
11661 }
11662
11663 #define PIPE_CONF_CHECK_M_N(name) \
11664 if (!intel_compare_link_m_n(&current_config->name, \
11665 &pipe_config->name,\
11666 adjust)) { \
11667 pipe_config_err(adjust, __stringify(name), \
11668 "(expected tu %i gmch %i/%i link %i/%i, " \
11669 "found tu %i, gmch %i/%i link %i/%i)\n", \
11670 current_config->name.tu, \
11671 current_config->name.gmch_m, \
11672 current_config->name.gmch_n, \
11673 current_config->name.link_m, \
11674 current_config->name.link_n, \
11675 pipe_config->name.tu, \
11676 pipe_config->name.gmch_m, \
11677 pipe_config->name.gmch_n, \
11678 pipe_config->name.link_m, \
11679 pipe_config->name.link_n); \
11680 ret = false; \
11681 }
11682
11683 /* This is required for BDW+ where there is only one set of registers for
11684 * switching between high and low RR.
11685 * This macro can be used whenever a comparison has to be made between one
11686 * hw state and multiple sw state variables.
11687 */
11688 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11689 if (!intel_compare_link_m_n(&current_config->name, \
11690 &pipe_config->name, adjust) && \
11691 !intel_compare_link_m_n(&current_config->alt_name, \
11692 &pipe_config->name, adjust)) { \
11693 pipe_config_err(adjust, __stringify(name), \
11694 "(expected tu %i gmch %i/%i link %i/%i, " \
11695 "or tu %i gmch %i/%i link %i/%i, " \
11696 "found tu %i, gmch %i/%i link %i/%i)\n", \
11697 current_config->name.tu, \
11698 current_config->name.gmch_m, \
11699 current_config->name.gmch_n, \
11700 current_config->name.link_m, \
11701 current_config->name.link_n, \
11702 current_config->alt_name.tu, \
11703 current_config->alt_name.gmch_m, \
11704 current_config->alt_name.gmch_n, \
11705 current_config->alt_name.link_m, \
11706 current_config->alt_name.link_n, \
11707 pipe_config->name.tu, \
11708 pipe_config->name.gmch_m, \
11709 pipe_config->name.gmch_n, \
11710 pipe_config->name.link_m, \
11711 pipe_config->name.link_n); \
11712 ret = false; \
11713 }
11714
11715 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11716 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11717 pipe_config_err(adjust, __stringify(name), \
11718 "(%x) (expected %i, found %i)\n", \
11719 (mask), \
11720 current_config->name & (mask), \
11721 pipe_config->name & (mask)); \
11722 ret = false; \
11723 }
11724
11725 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11726 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11727 pipe_config_err(adjust, __stringify(name), \
11728 "(expected %i, found %i)\n", \
11729 current_config->name, \
11730 pipe_config->name); \
11731 ret = false; \
11732 }
11733
11734 #define PIPE_CONF_QUIRK(quirk) \
11735 ((current_config->quirks | pipe_config->quirks) & (quirk))
11736
11737 PIPE_CONF_CHECK_I(cpu_transcoder);
11738
11739 PIPE_CONF_CHECK_I(has_pch_encoder);
11740 PIPE_CONF_CHECK_I(fdi_lanes);
11741 PIPE_CONF_CHECK_M_N(fdi_m_n);
11742
11743 PIPE_CONF_CHECK_I(lane_count);
11744 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11745
11746 if (INTEL_GEN(dev_priv) < 8) {
11747 PIPE_CONF_CHECK_M_N(dp_m_n);
11748
11749 if (current_config->has_drrs)
11750 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11751 } else
11752 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11753
11754 PIPE_CONF_CHECK_X(output_types);
11755
11756 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11757 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11758 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11759 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11760 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11761 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11762
11763 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11764 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11765 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11766 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11767 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11768 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11769
11770 PIPE_CONF_CHECK_I(pixel_multiplier);
11771 PIPE_CONF_CHECK_I(has_hdmi_sink);
11772 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11773 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11774 PIPE_CONF_CHECK_I(limited_color_range);
11775 PIPE_CONF_CHECK_I(has_infoframe);
11776
11777 PIPE_CONF_CHECK_I(has_audio);
11778
11779 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11780 DRM_MODE_FLAG_INTERLACE);
11781
11782 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11783 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11784 DRM_MODE_FLAG_PHSYNC);
11785 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11786 DRM_MODE_FLAG_NHSYNC);
11787 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11788 DRM_MODE_FLAG_PVSYNC);
11789 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11790 DRM_MODE_FLAG_NVSYNC);
11791 }
11792
11793 PIPE_CONF_CHECK_X(gmch_pfit.control);
11794 /* pfit ratios are autocomputed by the hw on gen4+ */
11795 if (INTEL_GEN(dev_priv) < 4)
11796 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11797 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11798
11799 if (!adjust) {
11800 PIPE_CONF_CHECK_I(pipe_src_w);
11801 PIPE_CONF_CHECK_I(pipe_src_h);
11802
11803 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11804 if (current_config->pch_pfit.enabled) {
11805 PIPE_CONF_CHECK_X(pch_pfit.pos);
11806 PIPE_CONF_CHECK_X(pch_pfit.size);
11807 }
11808
11809 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11810 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11811 }
11812
11813 /* BDW+ don't expose a synchronous way to read the state */
11814 if (IS_HASWELL(dev_priv))
11815 PIPE_CONF_CHECK_I(ips_enabled);
11816
11817 PIPE_CONF_CHECK_I(double_wide);
11818
11819 PIPE_CONF_CHECK_P(shared_dpll);
11820 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11821 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11822 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11823 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11824 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11825 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11826 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11827 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11828 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11829
11830 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11831 PIPE_CONF_CHECK_X(dsi_pll.div);
11832
11833 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11834 PIPE_CONF_CHECK_I(pipe_bpp);
11835
11836 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11837 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11838
11839 #undef PIPE_CONF_CHECK_X
11840 #undef PIPE_CONF_CHECK_I
11841 #undef PIPE_CONF_CHECK_P
11842 #undef PIPE_CONF_CHECK_FLAGS
11843 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11844 #undef PIPE_CONF_QUIRK
11845
11846 return ret;
11847 }
11848
11849 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11850 const struct intel_crtc_state *pipe_config)
11851 {
11852 if (pipe_config->has_pch_encoder) {
11853 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11854 &pipe_config->fdi_m_n);
11855 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11856
11857 /*
11858 * FDI already provided one idea for the dotclock.
11859 * Yell if the encoder disagrees.
11860 */
11861 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11862 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11863 fdi_dotclock, dotclock);
11864 }
11865 }
11866
11867 static void verify_wm_state(struct drm_crtc *crtc,
11868 struct drm_crtc_state *new_state)
11869 {
11870 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11871 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11872 struct skl_pipe_wm hw_wm, *sw_wm;
11873 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11874 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11876 const enum pipe pipe = intel_crtc->pipe;
11877 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11878
11879 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11880 return;
11881
11882 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11883 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11884
11885 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11886 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11887
11888 /* planes */
11889 for_each_universal_plane(dev_priv, pipe, plane) {
11890 hw_plane_wm = &hw_wm.planes[plane];
11891 sw_plane_wm = &sw_wm->planes[plane];
11892
11893 /* Watermarks */
11894 for (level = 0; level <= max_level; level++) {
11895 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11896 &sw_plane_wm->wm[level]))
11897 continue;
11898
11899 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11900 pipe_name(pipe), plane + 1, level,
11901 sw_plane_wm->wm[level].plane_en,
11902 sw_plane_wm->wm[level].plane_res_b,
11903 sw_plane_wm->wm[level].plane_res_l,
11904 hw_plane_wm->wm[level].plane_en,
11905 hw_plane_wm->wm[level].plane_res_b,
11906 hw_plane_wm->wm[level].plane_res_l);
11907 }
11908
11909 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11910 &sw_plane_wm->trans_wm)) {
11911 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11912 pipe_name(pipe), plane + 1,
11913 sw_plane_wm->trans_wm.plane_en,
11914 sw_plane_wm->trans_wm.plane_res_b,
11915 sw_plane_wm->trans_wm.plane_res_l,
11916 hw_plane_wm->trans_wm.plane_en,
11917 hw_plane_wm->trans_wm.plane_res_b,
11918 hw_plane_wm->trans_wm.plane_res_l);
11919 }
11920
11921 /* DDB */
11922 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11923 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11924
11925 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11926 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11927 pipe_name(pipe), plane + 1,
11928 sw_ddb_entry->start, sw_ddb_entry->end,
11929 hw_ddb_entry->start, hw_ddb_entry->end);
11930 }
11931 }
11932
11933 /*
11934 * cursor
11935 * If the cursor plane isn't active, we may not have updated it's ddb
11936 * allocation. In that case since the ddb allocation will be updated
11937 * once the plane becomes visible, we can skip this check
11938 */
11939 if (intel_crtc->cursor_addr) {
11940 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11941 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11942
11943 /* Watermarks */
11944 for (level = 0; level <= max_level; level++) {
11945 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11946 &sw_plane_wm->wm[level]))
11947 continue;
11948
11949 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11950 pipe_name(pipe), level,
11951 sw_plane_wm->wm[level].plane_en,
11952 sw_plane_wm->wm[level].plane_res_b,
11953 sw_plane_wm->wm[level].plane_res_l,
11954 hw_plane_wm->wm[level].plane_en,
11955 hw_plane_wm->wm[level].plane_res_b,
11956 hw_plane_wm->wm[level].plane_res_l);
11957 }
11958
11959 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11960 &sw_plane_wm->trans_wm)) {
11961 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11962 pipe_name(pipe),
11963 sw_plane_wm->trans_wm.plane_en,
11964 sw_plane_wm->trans_wm.plane_res_b,
11965 sw_plane_wm->trans_wm.plane_res_l,
11966 hw_plane_wm->trans_wm.plane_en,
11967 hw_plane_wm->trans_wm.plane_res_b,
11968 hw_plane_wm->trans_wm.plane_res_l);
11969 }
11970
11971 /* DDB */
11972 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11973 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11974
11975 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11976 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11977 pipe_name(pipe),
11978 sw_ddb_entry->start, sw_ddb_entry->end,
11979 hw_ddb_entry->start, hw_ddb_entry->end);
11980 }
11981 }
11982 }
11983
11984 static void
11985 verify_connector_state(struct drm_device *dev,
11986 struct drm_atomic_state *state,
11987 struct drm_crtc *crtc)
11988 {
11989 struct drm_connector *connector;
11990 struct drm_connector_state *old_conn_state;
11991 int i;
11992
11993 for_each_connector_in_state(state, connector, old_conn_state, i) {
11994 struct drm_encoder *encoder = connector->encoder;
11995 struct drm_connector_state *state = connector->state;
11996
11997 if (state->crtc != crtc)
11998 continue;
11999
12000 intel_connector_verify_state(to_intel_connector(connector));
12001
12002 I915_STATE_WARN(state->best_encoder != encoder,
12003 "connector's atomic encoder doesn't match legacy encoder\n");
12004 }
12005 }
12006
12007 static void
12008 verify_encoder_state(struct drm_device *dev)
12009 {
12010 struct intel_encoder *encoder;
12011 struct intel_connector *connector;
12012
12013 for_each_intel_encoder(dev, encoder) {
12014 bool enabled = false;
12015 enum pipe pipe;
12016
12017 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12018 encoder->base.base.id,
12019 encoder->base.name);
12020
12021 for_each_intel_connector(dev, connector) {
12022 if (connector->base.state->best_encoder != &encoder->base)
12023 continue;
12024 enabled = true;
12025
12026 I915_STATE_WARN(connector->base.state->crtc !=
12027 encoder->base.crtc,
12028 "connector's crtc doesn't match encoder crtc\n");
12029 }
12030
12031 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12032 "encoder's enabled state mismatch "
12033 "(expected %i, found %i)\n",
12034 !!encoder->base.crtc, enabled);
12035
12036 if (!encoder->base.crtc) {
12037 bool active;
12038
12039 active = encoder->get_hw_state(encoder, &pipe);
12040 I915_STATE_WARN(active,
12041 "encoder detached but still enabled on pipe %c.\n",
12042 pipe_name(pipe));
12043 }
12044 }
12045 }
12046
12047 static void
12048 verify_crtc_state(struct drm_crtc *crtc,
12049 struct drm_crtc_state *old_crtc_state,
12050 struct drm_crtc_state *new_crtc_state)
12051 {
12052 struct drm_device *dev = crtc->dev;
12053 struct drm_i915_private *dev_priv = to_i915(dev);
12054 struct intel_encoder *encoder;
12055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12056 struct intel_crtc_state *pipe_config, *sw_config;
12057 struct drm_atomic_state *old_state;
12058 bool active;
12059
12060 old_state = old_crtc_state->state;
12061 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12062 pipe_config = to_intel_crtc_state(old_crtc_state);
12063 memset(pipe_config, 0, sizeof(*pipe_config));
12064 pipe_config->base.crtc = crtc;
12065 pipe_config->base.state = old_state;
12066
12067 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12068
12069 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12070
12071 /* hw state is inconsistent with the pipe quirk */
12072 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12073 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12074 active = new_crtc_state->active;
12075
12076 I915_STATE_WARN(new_crtc_state->active != active,
12077 "crtc active state doesn't match with hw state "
12078 "(expected %i, found %i)\n", new_crtc_state->active, active);
12079
12080 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12081 "transitional active state does not match atomic hw state "
12082 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12083
12084 for_each_encoder_on_crtc(dev, crtc, encoder) {
12085 enum pipe pipe;
12086
12087 active = encoder->get_hw_state(encoder, &pipe);
12088 I915_STATE_WARN(active != new_crtc_state->active,
12089 "[ENCODER:%i] active %i with crtc active %i\n",
12090 encoder->base.base.id, active, new_crtc_state->active);
12091
12092 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12093 "Encoder connected to wrong pipe %c\n",
12094 pipe_name(pipe));
12095
12096 if (active) {
12097 pipe_config->output_types |= 1 << encoder->type;
12098 encoder->get_config(encoder, pipe_config);
12099 }
12100 }
12101
12102 intel_crtc_compute_pixel_rate(pipe_config);
12103
12104 if (!new_crtc_state->active)
12105 return;
12106
12107 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12108
12109 sw_config = to_intel_crtc_state(crtc->state);
12110 if (!intel_pipe_config_compare(dev_priv, sw_config,
12111 pipe_config, false)) {
12112 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12113 intel_dump_pipe_config(intel_crtc, pipe_config,
12114 "[hw state]");
12115 intel_dump_pipe_config(intel_crtc, sw_config,
12116 "[sw state]");
12117 }
12118 }
12119
12120 static void
12121 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12122 struct intel_shared_dpll *pll,
12123 struct drm_crtc *crtc,
12124 struct drm_crtc_state *new_state)
12125 {
12126 struct intel_dpll_hw_state dpll_hw_state;
12127 unsigned crtc_mask;
12128 bool active;
12129
12130 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12131
12132 DRM_DEBUG_KMS("%s\n", pll->name);
12133
12134 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12135
12136 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12137 I915_STATE_WARN(!pll->on && pll->active_mask,
12138 "pll in active use but not on in sw tracking\n");
12139 I915_STATE_WARN(pll->on && !pll->active_mask,
12140 "pll is on but not used by any active crtc\n");
12141 I915_STATE_WARN(pll->on != active,
12142 "pll on state mismatch (expected %i, found %i)\n",
12143 pll->on, active);
12144 }
12145
12146 if (!crtc) {
12147 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12148 "more active pll users than references: %x vs %x\n",
12149 pll->active_mask, pll->state.crtc_mask);
12150
12151 return;
12152 }
12153
12154 crtc_mask = 1 << drm_crtc_index(crtc);
12155
12156 if (new_state->active)
12157 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12158 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12159 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12160 else
12161 I915_STATE_WARN(pll->active_mask & crtc_mask,
12162 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12163 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12164
12165 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12166 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12167 crtc_mask, pll->state.crtc_mask);
12168
12169 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12170 &dpll_hw_state,
12171 sizeof(dpll_hw_state)),
12172 "pll hw state mismatch\n");
12173 }
12174
12175 static void
12176 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12177 struct drm_crtc_state *old_crtc_state,
12178 struct drm_crtc_state *new_crtc_state)
12179 {
12180 struct drm_i915_private *dev_priv = to_i915(dev);
12181 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12182 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12183
12184 if (new_state->shared_dpll)
12185 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12186
12187 if (old_state->shared_dpll &&
12188 old_state->shared_dpll != new_state->shared_dpll) {
12189 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12190 struct intel_shared_dpll *pll = old_state->shared_dpll;
12191
12192 I915_STATE_WARN(pll->active_mask & crtc_mask,
12193 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12194 pipe_name(drm_crtc_index(crtc)));
12195 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12196 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12197 pipe_name(drm_crtc_index(crtc)));
12198 }
12199 }
12200
12201 static void
12202 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12203 struct drm_atomic_state *state,
12204 struct drm_crtc_state *old_state,
12205 struct drm_crtc_state *new_state)
12206 {
12207 if (!needs_modeset(new_state) &&
12208 !to_intel_crtc_state(new_state)->update_pipe)
12209 return;
12210
12211 verify_wm_state(crtc, new_state);
12212 verify_connector_state(crtc->dev, state, crtc);
12213 verify_crtc_state(crtc, old_state, new_state);
12214 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12215 }
12216
12217 static void
12218 verify_disabled_dpll_state(struct drm_device *dev)
12219 {
12220 struct drm_i915_private *dev_priv = to_i915(dev);
12221 int i;
12222
12223 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12224 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12225 }
12226
12227 static void
12228 intel_modeset_verify_disabled(struct drm_device *dev,
12229 struct drm_atomic_state *state)
12230 {
12231 verify_encoder_state(dev);
12232 verify_connector_state(dev, state, NULL);
12233 verify_disabled_dpll_state(dev);
12234 }
12235
12236 static void update_scanline_offset(struct intel_crtc *crtc)
12237 {
12238 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12239
12240 /*
12241 * The scanline counter increments at the leading edge of hsync.
12242 *
12243 * On most platforms it starts counting from vtotal-1 on the
12244 * first active line. That means the scanline counter value is
12245 * always one less than what we would expect. Ie. just after
12246 * start of vblank, which also occurs at start of hsync (on the
12247 * last active line), the scanline counter will read vblank_start-1.
12248 *
12249 * On gen2 the scanline counter starts counting from 1 instead
12250 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12251 * to keep the value positive), instead of adding one.
12252 *
12253 * On HSW+ the behaviour of the scanline counter depends on the output
12254 * type. For DP ports it behaves like most other platforms, but on HDMI
12255 * there's an extra 1 line difference. So we need to add two instead of
12256 * one to the value.
12257 */
12258 if (IS_GEN2(dev_priv)) {
12259 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12260 int vtotal;
12261
12262 vtotal = adjusted_mode->crtc_vtotal;
12263 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12264 vtotal /= 2;
12265
12266 crtc->scanline_offset = vtotal - 1;
12267 } else if (HAS_DDI(dev_priv) &&
12268 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12269 crtc->scanline_offset = 2;
12270 } else
12271 crtc->scanline_offset = 1;
12272 }
12273
12274 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12275 {
12276 struct drm_device *dev = state->dev;
12277 struct drm_i915_private *dev_priv = to_i915(dev);
12278 struct drm_crtc *crtc;
12279 struct drm_crtc_state *crtc_state;
12280 int i;
12281
12282 if (!dev_priv->display.crtc_compute_clock)
12283 return;
12284
12285 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12287 struct intel_shared_dpll *old_dpll =
12288 to_intel_crtc_state(crtc->state)->shared_dpll;
12289
12290 if (!needs_modeset(crtc_state))
12291 continue;
12292
12293 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
12294
12295 if (!old_dpll)
12296 continue;
12297
12298 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12299 }
12300 }
12301
12302 /*
12303 * This implements the workaround described in the "notes" section of the mode
12304 * set sequence documentation. When going from no pipes or single pipe to
12305 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12306 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12307 */
12308 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12309 {
12310 struct drm_crtc_state *crtc_state;
12311 struct intel_crtc *intel_crtc;
12312 struct drm_crtc *crtc;
12313 struct intel_crtc_state *first_crtc_state = NULL;
12314 struct intel_crtc_state *other_crtc_state = NULL;
12315 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12316 int i;
12317
12318 /* look at all crtc's that are going to be enabled in during modeset */
12319 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12320 intel_crtc = to_intel_crtc(crtc);
12321
12322 if (!crtc_state->active || !needs_modeset(crtc_state))
12323 continue;
12324
12325 if (first_crtc_state) {
12326 other_crtc_state = to_intel_crtc_state(crtc_state);
12327 break;
12328 } else {
12329 first_crtc_state = to_intel_crtc_state(crtc_state);
12330 first_pipe = intel_crtc->pipe;
12331 }
12332 }
12333
12334 /* No workaround needed? */
12335 if (!first_crtc_state)
12336 return 0;
12337
12338 /* w/a possibly needed, check how many crtc's are already enabled. */
12339 for_each_intel_crtc(state->dev, intel_crtc) {
12340 struct intel_crtc_state *pipe_config;
12341
12342 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12343 if (IS_ERR(pipe_config))
12344 return PTR_ERR(pipe_config);
12345
12346 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12347
12348 if (!pipe_config->base.active ||
12349 needs_modeset(&pipe_config->base))
12350 continue;
12351
12352 /* 2 or more enabled crtcs means no need for w/a */
12353 if (enabled_pipe != INVALID_PIPE)
12354 return 0;
12355
12356 enabled_pipe = intel_crtc->pipe;
12357 }
12358
12359 if (enabled_pipe != INVALID_PIPE)
12360 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12361 else if (other_crtc_state)
12362 other_crtc_state->hsw_workaround_pipe = first_pipe;
12363
12364 return 0;
12365 }
12366
12367 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12368 {
12369 struct drm_crtc *crtc;
12370
12371 /* Add all pipes to the state */
12372 for_each_crtc(state->dev, crtc) {
12373 struct drm_crtc_state *crtc_state;
12374
12375 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12376 if (IS_ERR(crtc_state))
12377 return PTR_ERR(crtc_state);
12378 }
12379
12380 return 0;
12381 }
12382
12383 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12384 {
12385 struct drm_crtc *crtc;
12386
12387 /*
12388 * Add all pipes to the state, and force
12389 * a modeset on all the active ones.
12390 */
12391 for_each_crtc(state->dev, crtc) {
12392 struct drm_crtc_state *crtc_state;
12393 int ret;
12394
12395 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12396 if (IS_ERR(crtc_state))
12397 return PTR_ERR(crtc_state);
12398
12399 if (!crtc_state->active || needs_modeset(crtc_state))
12400 continue;
12401
12402 crtc_state->mode_changed = true;
12403
12404 ret = drm_atomic_add_affected_connectors(state, crtc);
12405 if (ret)
12406 return ret;
12407
12408 ret = drm_atomic_add_affected_planes(state, crtc);
12409 if (ret)
12410 return ret;
12411 }
12412
12413 return 0;
12414 }
12415
12416 static int intel_modeset_checks(struct drm_atomic_state *state)
12417 {
12418 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12419 struct drm_i915_private *dev_priv = to_i915(state->dev);
12420 struct drm_crtc *crtc;
12421 struct drm_crtc_state *crtc_state;
12422 int ret = 0, i;
12423
12424 if (!check_digital_port_conflicts(state)) {
12425 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12426 return -EINVAL;
12427 }
12428
12429 intel_state->modeset = true;
12430 intel_state->active_crtcs = dev_priv->active_crtcs;
12431 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12432 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12433
12434 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12435 if (crtc_state->active)
12436 intel_state->active_crtcs |= 1 << i;
12437 else
12438 intel_state->active_crtcs &= ~(1 << i);
12439
12440 if (crtc_state->active != crtc->state->active)
12441 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12442 }
12443
12444 /*
12445 * See if the config requires any additional preparation, e.g.
12446 * to adjust global state with pipes off. We need to do this
12447 * here so we can get the modeset_pipe updated config for the new
12448 * mode set on this crtc. For other crtcs we need to use the
12449 * adjusted_mode bits in the crtc directly.
12450 */
12451 if (dev_priv->display.modeset_calc_cdclk) {
12452 ret = dev_priv->display.modeset_calc_cdclk(state);
12453 if (ret < 0)
12454 return ret;
12455
12456 /*
12457 * Writes to dev_priv->cdclk.logical must protected by
12458 * holding all the crtc locks, even if we don't end up
12459 * touching the hardware
12460 */
12461 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12462 &intel_state->cdclk.logical)) {
12463 ret = intel_lock_all_pipes(state);
12464 if (ret < 0)
12465 return ret;
12466 }
12467
12468 /* All pipes must be switched off while we change the cdclk. */
12469 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12470 &intel_state->cdclk.actual)) {
12471 ret = intel_modeset_all_pipes(state);
12472 if (ret < 0)
12473 return ret;
12474 }
12475
12476 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12477 intel_state->cdclk.logical.cdclk,
12478 intel_state->cdclk.actual.cdclk);
12479 } else {
12480 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12481 }
12482
12483 intel_modeset_clear_plls(state);
12484
12485 if (IS_HASWELL(dev_priv))
12486 return haswell_mode_set_planes_workaround(state);
12487
12488 return 0;
12489 }
12490
12491 /*
12492 * Handle calculation of various watermark data at the end of the atomic check
12493 * phase. The code here should be run after the per-crtc and per-plane 'check'
12494 * handlers to ensure that all derived state has been updated.
12495 */
12496 static int calc_watermark_data(struct drm_atomic_state *state)
12497 {
12498 struct drm_device *dev = state->dev;
12499 struct drm_i915_private *dev_priv = to_i915(dev);
12500
12501 /* Is there platform-specific watermark information to calculate? */
12502 if (dev_priv->display.compute_global_watermarks)
12503 return dev_priv->display.compute_global_watermarks(state);
12504
12505 return 0;
12506 }
12507
12508 /**
12509 * intel_atomic_check - validate state object
12510 * @dev: drm device
12511 * @state: state to validate
12512 */
12513 static int intel_atomic_check(struct drm_device *dev,
12514 struct drm_atomic_state *state)
12515 {
12516 struct drm_i915_private *dev_priv = to_i915(dev);
12517 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12518 struct drm_crtc *crtc;
12519 struct drm_crtc_state *crtc_state;
12520 int ret, i;
12521 bool any_ms = false;
12522
12523 ret = drm_atomic_helper_check_modeset(dev, state);
12524 if (ret)
12525 return ret;
12526
12527 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12528 struct intel_crtc_state *pipe_config =
12529 to_intel_crtc_state(crtc_state);
12530
12531 /* Catch I915_MODE_FLAG_INHERITED */
12532 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12533 crtc_state->mode_changed = true;
12534
12535 if (!needs_modeset(crtc_state))
12536 continue;
12537
12538 if (!crtc_state->enable) {
12539 any_ms = true;
12540 continue;
12541 }
12542
12543 /* FIXME: For only active_changed we shouldn't need to do any
12544 * state recomputation at all. */
12545
12546 ret = drm_atomic_add_affected_connectors(state, crtc);
12547 if (ret)
12548 return ret;
12549
12550 ret = intel_modeset_pipe_config(crtc, pipe_config);
12551 if (ret) {
12552 intel_dump_pipe_config(to_intel_crtc(crtc),
12553 pipe_config, "[failed]");
12554 return ret;
12555 }
12556
12557 if (i915.fastboot &&
12558 intel_pipe_config_compare(dev_priv,
12559 to_intel_crtc_state(crtc->state),
12560 pipe_config, true)) {
12561 crtc_state->mode_changed = false;
12562 to_intel_crtc_state(crtc_state)->update_pipe = true;
12563 }
12564
12565 if (needs_modeset(crtc_state))
12566 any_ms = true;
12567
12568 ret = drm_atomic_add_affected_planes(state, crtc);
12569 if (ret)
12570 return ret;
12571
12572 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12573 needs_modeset(crtc_state) ?
12574 "[modeset]" : "[fastset]");
12575 }
12576
12577 if (any_ms) {
12578 ret = intel_modeset_checks(state);
12579
12580 if (ret)
12581 return ret;
12582 } else {
12583 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12584 }
12585
12586 ret = drm_atomic_helper_check_planes(dev, state);
12587 if (ret)
12588 return ret;
12589
12590 intel_fbc_choose_crtc(dev_priv, state);
12591 return calc_watermark_data(state);
12592 }
12593
12594 static int intel_atomic_prepare_commit(struct drm_device *dev,
12595 struct drm_atomic_state *state)
12596 {
12597 struct drm_i915_private *dev_priv = to_i915(dev);
12598 struct drm_crtc_state *crtc_state;
12599 struct drm_crtc *crtc;
12600 int i, ret;
12601
12602 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12603 if (state->legacy_cursor_update)
12604 continue;
12605
12606 ret = intel_crtc_wait_for_pending_flips(crtc);
12607 if (ret)
12608 return ret;
12609
12610 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12611 flush_workqueue(dev_priv->wq);
12612 }
12613
12614 ret = mutex_lock_interruptible(&dev->struct_mutex);
12615 if (ret)
12616 return ret;
12617
12618 ret = drm_atomic_helper_prepare_planes(dev, state);
12619 mutex_unlock(&dev->struct_mutex);
12620
12621 return ret;
12622 }
12623
12624 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12625 {
12626 struct drm_device *dev = crtc->base.dev;
12627
12628 if (!dev->max_vblank_count)
12629 return drm_accurate_vblank_count(&crtc->base);
12630
12631 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12632 }
12633
12634 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12635 struct drm_i915_private *dev_priv,
12636 unsigned crtc_mask)
12637 {
12638 unsigned last_vblank_count[I915_MAX_PIPES];
12639 enum pipe pipe;
12640 int ret;
12641
12642 if (!crtc_mask)
12643 return;
12644
12645 for_each_pipe(dev_priv, pipe) {
12646 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12647 pipe);
12648
12649 if (!((1 << pipe) & crtc_mask))
12650 continue;
12651
12652 ret = drm_crtc_vblank_get(&crtc->base);
12653 if (WARN_ON(ret != 0)) {
12654 crtc_mask &= ~(1 << pipe);
12655 continue;
12656 }
12657
12658 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12659 }
12660
12661 for_each_pipe(dev_priv, pipe) {
12662 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12663 pipe);
12664 long lret;
12665
12666 if (!((1 << pipe) & crtc_mask))
12667 continue;
12668
12669 lret = wait_event_timeout(dev->vblank[pipe].queue,
12670 last_vblank_count[pipe] !=
12671 drm_crtc_vblank_count(&crtc->base),
12672 msecs_to_jiffies(50));
12673
12674 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12675
12676 drm_crtc_vblank_put(&crtc->base);
12677 }
12678 }
12679
12680 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12681 {
12682 /* fb updated, need to unpin old fb */
12683 if (crtc_state->fb_changed)
12684 return true;
12685
12686 /* wm changes, need vblank before final wm's */
12687 if (crtc_state->update_wm_post)
12688 return true;
12689
12690 /*
12691 * cxsr is re-enabled after vblank.
12692 * This is already handled by crtc_state->update_wm_post,
12693 * but added for clarity.
12694 */
12695 if (crtc_state->disable_cxsr)
12696 return true;
12697
12698 return false;
12699 }
12700
12701 static void intel_update_crtc(struct drm_crtc *crtc,
12702 struct drm_atomic_state *state,
12703 struct drm_crtc_state *old_crtc_state,
12704 unsigned int *crtc_vblank_mask)
12705 {
12706 struct drm_device *dev = crtc->dev;
12707 struct drm_i915_private *dev_priv = to_i915(dev);
12708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12709 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
12710 bool modeset = needs_modeset(crtc->state);
12711
12712 if (modeset) {
12713 update_scanline_offset(intel_crtc);
12714 dev_priv->display.crtc_enable(pipe_config, state);
12715 } else {
12716 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
12717 }
12718
12719 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12720 intel_fbc_enable(
12721 intel_crtc, pipe_config,
12722 to_intel_plane_state(crtc->primary->state));
12723 }
12724
12725 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12726
12727 if (needs_vblank_wait(pipe_config))
12728 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12729 }
12730
12731 static void intel_update_crtcs(struct drm_atomic_state *state,
12732 unsigned int *crtc_vblank_mask)
12733 {
12734 struct drm_crtc *crtc;
12735 struct drm_crtc_state *old_crtc_state;
12736 int i;
12737
12738 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12739 if (!crtc->state->active)
12740 continue;
12741
12742 intel_update_crtc(crtc, state, old_crtc_state,
12743 crtc_vblank_mask);
12744 }
12745 }
12746
12747 static void skl_update_crtcs(struct drm_atomic_state *state,
12748 unsigned int *crtc_vblank_mask)
12749 {
12750 struct drm_i915_private *dev_priv = to_i915(state->dev);
12751 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12752 struct drm_crtc *crtc;
12753 struct intel_crtc *intel_crtc;
12754 struct drm_crtc_state *old_crtc_state;
12755 struct intel_crtc_state *cstate;
12756 unsigned int updated = 0;
12757 bool progress;
12758 enum pipe pipe;
12759 int i;
12760
12761 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12762
12763 for_each_crtc_in_state(state, crtc, old_crtc_state, i)
12764 /* ignore allocations for crtc's that have been turned off. */
12765 if (crtc->state->active)
12766 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12767
12768 /*
12769 * Whenever the number of active pipes changes, we need to make sure we
12770 * update the pipes in the right order so that their ddb allocations
12771 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12772 * cause pipe underruns and other bad stuff.
12773 */
12774 do {
12775 progress = false;
12776
12777 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12778 bool vbl_wait = false;
12779 unsigned int cmask = drm_crtc_mask(crtc);
12780
12781 intel_crtc = to_intel_crtc(crtc);
12782 cstate = to_intel_crtc_state(crtc->state);
12783 pipe = intel_crtc->pipe;
12784
12785 if (updated & cmask || !cstate->base.active)
12786 continue;
12787
12788 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12789 continue;
12790
12791 updated |= cmask;
12792 entries[i] = &cstate->wm.skl.ddb;
12793
12794 /*
12795 * If this is an already active pipe, it's DDB changed,
12796 * and this isn't the last pipe that needs updating
12797 * then we need to wait for a vblank to pass for the
12798 * new ddb allocation to take effect.
12799 */
12800 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12801 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12802 !crtc->state->active_changed &&
12803 intel_state->wm_results.dirty_pipes != updated)
12804 vbl_wait = true;
12805
12806 intel_update_crtc(crtc, state, old_crtc_state,
12807 crtc_vblank_mask);
12808
12809 if (vbl_wait)
12810 intel_wait_for_vblank(dev_priv, pipe);
12811
12812 progress = true;
12813 }
12814 } while (progress);
12815 }
12816
12817 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12818 {
12819 struct intel_atomic_state *state, *next;
12820 struct llist_node *freed;
12821
12822 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12823 llist_for_each_entry_safe(state, next, freed, freed)
12824 drm_atomic_state_put(&state->base);
12825 }
12826
12827 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12828 {
12829 struct drm_i915_private *dev_priv =
12830 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12831
12832 intel_atomic_helper_free_state(dev_priv);
12833 }
12834
12835 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12836 {
12837 struct drm_device *dev = state->dev;
12838 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12839 struct drm_i915_private *dev_priv = to_i915(dev);
12840 struct drm_crtc_state *old_crtc_state;
12841 struct drm_crtc *crtc;
12842 struct intel_crtc_state *intel_cstate;
12843 bool hw_check = intel_state->modeset;
12844 u64 put_domains[I915_MAX_PIPES] = {};
12845 unsigned crtc_vblank_mask = 0;
12846 int i;
12847
12848 drm_atomic_helper_wait_for_dependencies(state);
12849
12850 if (intel_state->modeset)
12851 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12852
12853 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12855
12856 if (needs_modeset(crtc->state) ||
12857 to_intel_crtc_state(crtc->state)->update_pipe) {
12858 hw_check = true;
12859
12860 put_domains[to_intel_crtc(crtc)->pipe] =
12861 modeset_get_crtc_power_domains(crtc,
12862 to_intel_crtc_state(crtc->state));
12863 }
12864
12865 if (!needs_modeset(crtc->state))
12866 continue;
12867
12868 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
12869
12870 if (old_crtc_state->active) {
12871 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12872 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12873 intel_crtc->active = false;
12874 intel_fbc_disable(intel_crtc);
12875 intel_disable_shared_dpll(intel_crtc);
12876
12877 /*
12878 * Underruns don't always raise
12879 * interrupts, so check manually.
12880 */
12881 intel_check_cpu_fifo_underruns(dev_priv);
12882 intel_check_pch_fifo_underruns(dev_priv);
12883
12884 if (!crtc->state->active) {
12885 /*
12886 * Make sure we don't call initial_watermarks
12887 * for ILK-style watermark updates.
12888 */
12889 if (dev_priv->display.atomic_update_watermarks)
12890 dev_priv->display.initial_watermarks(intel_state,
12891 to_intel_crtc_state(crtc->state));
12892 else
12893 intel_update_watermarks(intel_crtc);
12894 }
12895 }
12896 }
12897
12898 /* Only after disabling all output pipelines that will be changed can we
12899 * update the the output configuration. */
12900 intel_modeset_update_crtc_state(state);
12901
12902 if (intel_state->modeset) {
12903 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12904
12905 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12906
12907 /*
12908 * SKL workaround: bspec recommends we disable the SAGV when we
12909 * have more then one pipe enabled
12910 */
12911 if (!intel_can_enable_sagv(state))
12912 intel_disable_sagv(dev_priv);
12913
12914 intel_modeset_verify_disabled(dev, state);
12915 }
12916
12917 /* Complete the events for pipes that have now been disabled */
12918 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12919 bool modeset = needs_modeset(crtc->state);
12920
12921 /* Complete events for now disable pipes here. */
12922 if (modeset && !crtc->state->active && crtc->state->event) {
12923 spin_lock_irq(&dev->event_lock);
12924 drm_crtc_send_vblank_event(crtc, crtc->state->event);
12925 spin_unlock_irq(&dev->event_lock);
12926
12927 crtc->state->event = NULL;
12928 }
12929 }
12930
12931 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12932 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12933
12934 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12935 * already, but still need the state for the delayed optimization. To
12936 * fix this:
12937 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12938 * - schedule that vblank worker _before_ calling hw_done
12939 * - at the start of commit_tail, cancel it _synchrously
12940 * - switch over to the vblank wait helper in the core after that since
12941 * we don't need out special handling any more.
12942 */
12943 if (!state->legacy_cursor_update)
12944 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12945
12946 /*
12947 * Now that the vblank has passed, we can go ahead and program the
12948 * optimal watermarks on platforms that need two-step watermark
12949 * programming.
12950 *
12951 * TODO: Move this (and other cleanup) to an async worker eventually.
12952 */
12953 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12954 intel_cstate = to_intel_crtc_state(crtc->state);
12955
12956 if (dev_priv->display.optimize_watermarks)
12957 dev_priv->display.optimize_watermarks(intel_state,
12958 intel_cstate);
12959 }
12960
12961 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12962 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12963
12964 if (put_domains[i])
12965 modeset_put_power_domains(dev_priv, put_domains[i]);
12966
12967 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
12968 }
12969
12970 if (intel_state->modeset && intel_can_enable_sagv(state))
12971 intel_enable_sagv(dev_priv);
12972
12973 drm_atomic_helper_commit_hw_done(state);
12974
12975 if (intel_state->modeset)
12976 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12977
12978 mutex_lock(&dev->struct_mutex);
12979 drm_atomic_helper_cleanup_planes(dev, state);
12980 mutex_unlock(&dev->struct_mutex);
12981
12982 drm_atomic_helper_commit_cleanup_done(state);
12983
12984 drm_atomic_state_put(state);
12985
12986 /* As one of the primary mmio accessors, KMS has a high likelihood
12987 * of triggering bugs in unclaimed access. After we finish
12988 * modesetting, see if an error has been flagged, and if so
12989 * enable debugging for the next modeset - and hope we catch
12990 * the culprit.
12991 *
12992 * XXX note that we assume display power is on at this point.
12993 * This might hold true now but we need to add pm helper to check
12994 * unclaimed only when the hardware is on, as atomic commits
12995 * can happen also when the device is completely off.
12996 */
12997 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12998
12999 intel_atomic_helper_free_state(dev_priv);
13000 }
13001
13002 static void intel_atomic_commit_work(struct work_struct *work)
13003 {
13004 struct drm_atomic_state *state =
13005 container_of(work, struct drm_atomic_state, commit_work);
13006
13007 intel_atomic_commit_tail(state);
13008 }
13009
13010 static int __i915_sw_fence_call
13011 intel_atomic_commit_ready(struct i915_sw_fence *fence,
13012 enum i915_sw_fence_notify notify)
13013 {
13014 struct intel_atomic_state *state =
13015 container_of(fence, struct intel_atomic_state, commit_ready);
13016
13017 switch (notify) {
13018 case FENCE_COMPLETE:
13019 if (state->base.commit_work.func)
13020 queue_work(system_unbound_wq, &state->base.commit_work);
13021 break;
13022
13023 case FENCE_FREE:
13024 {
13025 struct intel_atomic_helper *helper =
13026 &to_i915(state->base.dev)->atomic_helper;
13027
13028 if (llist_add(&state->freed, &helper->free_list))
13029 schedule_work(&helper->free_work);
13030 break;
13031 }
13032 }
13033
13034 return NOTIFY_DONE;
13035 }
13036
13037 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13038 {
13039 struct drm_plane_state *old_plane_state;
13040 struct drm_plane *plane;
13041 int i;
13042
13043 for_each_plane_in_state(state, plane, old_plane_state, i)
13044 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13045 intel_fb_obj(plane->state->fb),
13046 to_intel_plane(plane)->frontbuffer_bit);
13047 }
13048
13049 /**
13050 * intel_atomic_commit - commit validated state object
13051 * @dev: DRM device
13052 * @state: the top-level driver state object
13053 * @nonblock: nonblocking commit
13054 *
13055 * This function commits a top-level state object that has been validated
13056 * with drm_atomic_helper_check().
13057 *
13058 * RETURNS
13059 * Zero for success or -errno.
13060 */
13061 static int intel_atomic_commit(struct drm_device *dev,
13062 struct drm_atomic_state *state,
13063 bool nonblock)
13064 {
13065 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13066 struct drm_i915_private *dev_priv = to_i915(dev);
13067 int ret = 0;
13068
13069 ret = drm_atomic_helper_setup_commit(state, nonblock);
13070 if (ret)
13071 return ret;
13072
13073 drm_atomic_state_get(state);
13074 i915_sw_fence_init(&intel_state->commit_ready,
13075 intel_atomic_commit_ready);
13076
13077 ret = intel_atomic_prepare_commit(dev, state);
13078 if (ret) {
13079 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13080 i915_sw_fence_commit(&intel_state->commit_ready);
13081 return ret;
13082 }
13083
13084 drm_atomic_helper_swap_state(state, true);
13085 dev_priv->wm.distrust_bios_wm = false;
13086 intel_shared_dpll_swap_state(state);
13087 intel_atomic_track_fbs(state);
13088
13089 if (intel_state->modeset) {
13090 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13091 sizeof(intel_state->min_pixclk));
13092 dev_priv->active_crtcs = intel_state->active_crtcs;
13093 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13094 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13095 }
13096
13097 drm_atomic_state_get(state);
13098 INIT_WORK(&state->commit_work,
13099 nonblock ? intel_atomic_commit_work : NULL);
13100
13101 i915_sw_fence_commit(&intel_state->commit_ready);
13102 if (!nonblock) {
13103 i915_sw_fence_wait(&intel_state->commit_ready);
13104 intel_atomic_commit_tail(state);
13105 }
13106
13107 return 0;
13108 }
13109
13110 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13111 {
13112 struct drm_device *dev = crtc->dev;
13113 struct drm_atomic_state *state;
13114 struct drm_crtc_state *crtc_state;
13115 int ret;
13116
13117 state = drm_atomic_state_alloc(dev);
13118 if (!state) {
13119 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13120 crtc->base.id, crtc->name);
13121 return;
13122 }
13123
13124 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13125
13126 retry:
13127 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13128 ret = PTR_ERR_OR_ZERO(crtc_state);
13129 if (!ret) {
13130 if (!crtc_state->active)
13131 goto out;
13132
13133 crtc_state->mode_changed = true;
13134 ret = drm_atomic_commit(state);
13135 }
13136
13137 if (ret == -EDEADLK) {
13138 drm_atomic_state_clear(state);
13139 drm_modeset_backoff(state->acquire_ctx);
13140 goto retry;
13141 }
13142
13143 out:
13144 drm_atomic_state_put(state);
13145 }
13146
13147 /*
13148 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13149 * drm_atomic_helper_legacy_gamma_set() directly.
13150 */
13151 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13152 u16 *red, u16 *green, u16 *blue,
13153 uint32_t size)
13154 {
13155 struct drm_device *dev = crtc->dev;
13156 struct drm_mode_config *config = &dev->mode_config;
13157 struct drm_crtc_state *state;
13158 int ret;
13159
13160 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13161 if (ret)
13162 return ret;
13163
13164 /*
13165 * Make sure we update the legacy properties so this works when
13166 * atomic is not enabled.
13167 */
13168
13169 state = crtc->state;
13170
13171 drm_object_property_set_value(&crtc->base,
13172 config->degamma_lut_property,
13173 (state->degamma_lut) ?
13174 state->degamma_lut->base.id : 0);
13175
13176 drm_object_property_set_value(&crtc->base,
13177 config->ctm_property,
13178 (state->ctm) ?
13179 state->ctm->base.id : 0);
13180
13181 drm_object_property_set_value(&crtc->base,
13182 config->gamma_lut_property,
13183 (state->gamma_lut) ?
13184 state->gamma_lut->base.id : 0);
13185
13186 return 0;
13187 }
13188
13189 static const struct drm_crtc_funcs intel_crtc_funcs = {
13190 .gamma_set = intel_atomic_legacy_gamma_set,
13191 .set_config = drm_atomic_helper_set_config,
13192 .set_property = drm_atomic_helper_crtc_set_property,
13193 .destroy = intel_crtc_destroy,
13194 .page_flip = drm_atomic_helper_page_flip,
13195 .atomic_duplicate_state = intel_crtc_duplicate_state,
13196 .atomic_destroy_state = intel_crtc_destroy_state,
13197 .set_crc_source = intel_crtc_set_crc_source,
13198 };
13199
13200 /**
13201 * intel_prepare_plane_fb - Prepare fb for usage on plane
13202 * @plane: drm plane to prepare for
13203 * @fb: framebuffer to prepare for presentation
13204 *
13205 * Prepares a framebuffer for usage on a display plane. Generally this
13206 * involves pinning the underlying object and updating the frontbuffer tracking
13207 * bits. Some older platforms need special physical address handling for
13208 * cursor planes.
13209 *
13210 * Must be called with struct_mutex held.
13211 *
13212 * Returns 0 on success, negative error code on failure.
13213 */
13214 int
13215 intel_prepare_plane_fb(struct drm_plane *plane,
13216 struct drm_plane_state *new_state)
13217 {
13218 struct intel_atomic_state *intel_state =
13219 to_intel_atomic_state(new_state->state);
13220 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13221 struct drm_framebuffer *fb = new_state->fb;
13222 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13223 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13224 int ret;
13225
13226 if (!obj && !old_obj)
13227 return 0;
13228
13229 if (old_obj) {
13230 struct drm_crtc_state *crtc_state =
13231 drm_atomic_get_existing_crtc_state(new_state->state,
13232 plane->state->crtc);
13233
13234 /* Big Hammer, we also need to ensure that any pending
13235 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13236 * current scanout is retired before unpinning the old
13237 * framebuffer. Note that we rely on userspace rendering
13238 * into the buffer attached to the pipe they are waiting
13239 * on. If not, userspace generates a GPU hang with IPEHR
13240 * point to the MI_WAIT_FOR_EVENT.
13241 *
13242 * This should only fail upon a hung GPU, in which case we
13243 * can safely continue.
13244 */
13245 if (needs_modeset(crtc_state)) {
13246 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13247 old_obj->resv, NULL,
13248 false, 0,
13249 GFP_KERNEL);
13250 if (ret < 0)
13251 return ret;
13252 }
13253 }
13254
13255 if (new_state->fence) { /* explicit fencing */
13256 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13257 new_state->fence,
13258 I915_FENCE_TIMEOUT,
13259 GFP_KERNEL);
13260 if (ret < 0)
13261 return ret;
13262 }
13263
13264 if (!obj)
13265 return 0;
13266
13267 if (!new_state->fence) { /* implicit fencing */
13268 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13269 obj->resv, NULL,
13270 false, I915_FENCE_TIMEOUT,
13271 GFP_KERNEL);
13272 if (ret < 0)
13273 return ret;
13274
13275 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13276 }
13277
13278 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13279 INTEL_INFO(dev_priv)->cursor_needs_physical) {
13280 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13281 ret = i915_gem_object_attach_phys(obj, align);
13282 if (ret) {
13283 DRM_DEBUG_KMS("failed to attach phys object\n");
13284 return ret;
13285 }
13286 } else {
13287 struct i915_vma *vma;
13288
13289 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13290 if (IS_ERR(vma)) {
13291 DRM_DEBUG_KMS("failed to pin object\n");
13292 return PTR_ERR(vma);
13293 }
13294
13295 to_intel_plane_state(new_state)->vma = vma;
13296 }
13297
13298 return 0;
13299 }
13300
13301 /**
13302 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13303 * @plane: drm plane to clean up for
13304 * @fb: old framebuffer that was on plane
13305 *
13306 * Cleans up a framebuffer that has just been removed from a plane.
13307 *
13308 * Must be called with struct_mutex held.
13309 */
13310 void
13311 intel_cleanup_plane_fb(struct drm_plane *plane,
13312 struct drm_plane_state *old_state)
13313 {
13314 struct i915_vma *vma;
13315
13316 /* Should only be called after a successful intel_prepare_plane_fb()! */
13317 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13318 if (vma)
13319 intel_unpin_fb_vma(vma);
13320 }
13321
13322 int
13323 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13324 {
13325 int max_scale;
13326 int crtc_clock, cdclk;
13327
13328 if (!intel_crtc || !crtc_state->base.enable)
13329 return DRM_PLANE_HELPER_NO_SCALING;
13330
13331 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13332 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13333
13334 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13335 return DRM_PLANE_HELPER_NO_SCALING;
13336
13337 /*
13338 * skl max scale is lower of:
13339 * close to 3 but not 3, -1 is for that purpose
13340 * or
13341 * cdclk/crtc_clock
13342 */
13343 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13344
13345 return max_scale;
13346 }
13347
13348 static int
13349 intel_check_primary_plane(struct drm_plane *plane,
13350 struct intel_crtc_state *crtc_state,
13351 struct intel_plane_state *state)
13352 {
13353 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13354 struct drm_crtc *crtc = state->base.crtc;
13355 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13356 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13357 bool can_position = false;
13358 int ret;
13359
13360 if (INTEL_GEN(dev_priv) >= 9) {
13361 /* use scaler when colorkey is not required */
13362 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13363 min_scale = 1;
13364 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13365 }
13366 can_position = true;
13367 }
13368
13369 ret = drm_plane_helper_check_state(&state->base,
13370 &state->clip,
13371 min_scale, max_scale,
13372 can_position, true);
13373 if (ret)
13374 return ret;
13375
13376 if (!state->base.fb)
13377 return 0;
13378
13379 if (INTEL_GEN(dev_priv) >= 9) {
13380 ret = skl_check_plane_surface(state);
13381 if (ret)
13382 return ret;
13383 }
13384
13385 return 0;
13386 }
13387
13388 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13389 struct drm_crtc_state *old_crtc_state)
13390 {
13391 struct drm_device *dev = crtc->dev;
13392 struct drm_i915_private *dev_priv = to_i915(dev);
13393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13394 struct intel_crtc_state *intel_cstate =
13395 to_intel_crtc_state(crtc->state);
13396 struct intel_crtc_state *old_intel_cstate =
13397 to_intel_crtc_state(old_crtc_state);
13398 struct intel_atomic_state *old_intel_state =
13399 to_intel_atomic_state(old_crtc_state->state);
13400 bool modeset = needs_modeset(crtc->state);
13401
13402 /* Perform vblank evasion around commit operation */
13403 intel_pipe_update_start(intel_crtc);
13404
13405 if (modeset)
13406 goto out;
13407
13408 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13409 intel_color_set_csc(crtc->state);
13410 intel_color_load_luts(crtc->state);
13411 }
13412
13413 if (intel_cstate->update_pipe)
13414 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13415 else if (INTEL_GEN(dev_priv) >= 9)
13416 skl_detach_scalers(intel_crtc);
13417
13418 out:
13419 if (dev_priv->display.atomic_update_watermarks)
13420 dev_priv->display.atomic_update_watermarks(old_intel_state,
13421 intel_cstate);
13422 }
13423
13424 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13425 struct drm_crtc_state *old_crtc_state)
13426 {
13427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13428
13429 intel_pipe_update_end(intel_crtc, NULL);
13430 }
13431
13432 /**
13433 * intel_plane_destroy - destroy a plane
13434 * @plane: plane to destroy
13435 *
13436 * Common destruction function for all types of planes (primary, cursor,
13437 * sprite).
13438 */
13439 void intel_plane_destroy(struct drm_plane *plane)
13440 {
13441 drm_plane_cleanup(plane);
13442 kfree(to_intel_plane(plane));
13443 }
13444
13445 const struct drm_plane_funcs intel_plane_funcs = {
13446 .update_plane = drm_atomic_helper_update_plane,
13447 .disable_plane = drm_atomic_helper_disable_plane,
13448 .destroy = intel_plane_destroy,
13449 .set_property = drm_atomic_helper_plane_set_property,
13450 .atomic_get_property = intel_plane_atomic_get_property,
13451 .atomic_set_property = intel_plane_atomic_set_property,
13452 .atomic_duplicate_state = intel_plane_duplicate_state,
13453 .atomic_destroy_state = intel_plane_destroy_state,
13454 };
13455
13456 static int
13457 intel_legacy_cursor_update(struct drm_plane *plane,
13458 struct drm_crtc *crtc,
13459 struct drm_framebuffer *fb,
13460 int crtc_x, int crtc_y,
13461 unsigned int crtc_w, unsigned int crtc_h,
13462 uint32_t src_x, uint32_t src_y,
13463 uint32_t src_w, uint32_t src_h)
13464 {
13465 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13466 int ret;
13467 struct drm_plane_state *old_plane_state, *new_plane_state;
13468 struct intel_plane *intel_plane = to_intel_plane(plane);
13469 struct drm_framebuffer *old_fb;
13470 struct drm_crtc_state *crtc_state = crtc->state;
13471 struct i915_vma *old_vma;
13472
13473 /*
13474 * When crtc is inactive or there is a modeset pending,
13475 * wait for it to complete in the slowpath
13476 */
13477 if (!crtc_state->active || needs_modeset(crtc_state) ||
13478 to_intel_crtc_state(crtc_state)->update_pipe)
13479 goto slow;
13480
13481 old_plane_state = plane->state;
13482
13483 /*
13484 * If any parameters change that may affect watermarks,
13485 * take the slowpath. Only changing fb or position should be
13486 * in the fastpath.
13487 */
13488 if (old_plane_state->crtc != crtc ||
13489 old_plane_state->src_w != src_w ||
13490 old_plane_state->src_h != src_h ||
13491 old_plane_state->crtc_w != crtc_w ||
13492 old_plane_state->crtc_h != crtc_h ||
13493 !old_plane_state->visible ||
13494 old_plane_state->fb->modifier != fb->modifier)
13495 goto slow;
13496
13497 new_plane_state = intel_plane_duplicate_state(plane);
13498 if (!new_plane_state)
13499 return -ENOMEM;
13500
13501 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13502
13503 new_plane_state->src_x = src_x;
13504 new_plane_state->src_y = src_y;
13505 new_plane_state->src_w = src_w;
13506 new_plane_state->src_h = src_h;
13507 new_plane_state->crtc_x = crtc_x;
13508 new_plane_state->crtc_y = crtc_y;
13509 new_plane_state->crtc_w = crtc_w;
13510 new_plane_state->crtc_h = crtc_h;
13511
13512 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13513 to_intel_plane_state(new_plane_state));
13514 if (ret)
13515 goto out_free;
13516
13517 /* Visibility changed, must take slowpath. */
13518 if (!new_plane_state->visible)
13519 goto slow_free;
13520
13521 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13522 if (ret)
13523 goto out_free;
13524
13525 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13526 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13527
13528 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13529 if (ret) {
13530 DRM_DEBUG_KMS("failed to attach phys object\n");
13531 goto out_unlock;
13532 }
13533 } else {
13534 struct i915_vma *vma;
13535
13536 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13537 if (IS_ERR(vma)) {
13538 DRM_DEBUG_KMS("failed to pin object\n");
13539
13540 ret = PTR_ERR(vma);
13541 goto out_unlock;
13542 }
13543
13544 to_intel_plane_state(new_plane_state)->vma = vma;
13545 }
13546
13547 old_fb = old_plane_state->fb;
13548 old_vma = to_intel_plane_state(old_plane_state)->vma;
13549
13550 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13551 intel_plane->frontbuffer_bit);
13552
13553 /* Swap plane state */
13554 new_plane_state->fence = old_plane_state->fence;
13555 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13556 new_plane_state->fence = NULL;
13557 new_plane_state->fb = old_fb;
13558 to_intel_plane_state(new_plane_state)->vma = old_vma;
13559
13560 intel_plane->update_plane(plane,
13561 to_intel_crtc_state(crtc->state),
13562 to_intel_plane_state(plane->state));
13563
13564 intel_cleanup_plane_fb(plane, new_plane_state);
13565
13566 out_unlock:
13567 mutex_unlock(&dev_priv->drm.struct_mutex);
13568 out_free:
13569 intel_plane_destroy_state(plane, new_plane_state);
13570 return ret;
13571
13572 slow_free:
13573 intel_plane_destroy_state(plane, new_plane_state);
13574 slow:
13575 return drm_atomic_helper_update_plane(plane, crtc, fb,
13576 crtc_x, crtc_y, crtc_w, crtc_h,
13577 src_x, src_y, src_w, src_h);
13578 }
13579
13580 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13581 .update_plane = intel_legacy_cursor_update,
13582 .disable_plane = drm_atomic_helper_disable_plane,
13583 .destroy = intel_plane_destroy,
13584 .set_property = drm_atomic_helper_plane_set_property,
13585 .atomic_get_property = intel_plane_atomic_get_property,
13586 .atomic_set_property = intel_plane_atomic_set_property,
13587 .atomic_duplicate_state = intel_plane_duplicate_state,
13588 .atomic_destroy_state = intel_plane_destroy_state,
13589 };
13590
13591 static struct intel_plane *
13592 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13593 {
13594 struct intel_plane *primary = NULL;
13595 struct intel_plane_state *state = NULL;
13596 const uint32_t *intel_primary_formats;
13597 unsigned int supported_rotations;
13598 unsigned int num_formats;
13599 int ret;
13600
13601 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13602 if (!primary) {
13603 ret = -ENOMEM;
13604 goto fail;
13605 }
13606
13607 state = intel_create_plane_state(&primary->base);
13608 if (!state) {
13609 ret = -ENOMEM;
13610 goto fail;
13611 }
13612
13613 primary->base.state = &state->base;
13614
13615 primary->can_scale = false;
13616 primary->max_downscale = 1;
13617 if (INTEL_GEN(dev_priv) >= 9) {
13618 primary->can_scale = true;
13619 state->scaler_id = -1;
13620 }
13621 primary->pipe = pipe;
13622 /*
13623 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13624 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13625 */
13626 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13627 primary->plane = (enum plane) !pipe;
13628 else
13629 primary->plane = (enum plane) pipe;
13630 primary->id = PLANE_PRIMARY;
13631 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13632 primary->check_plane = intel_check_primary_plane;
13633
13634 if (INTEL_GEN(dev_priv) >= 9) {
13635 intel_primary_formats = skl_primary_formats;
13636 num_formats = ARRAY_SIZE(skl_primary_formats);
13637
13638 primary->update_plane = skylake_update_primary_plane;
13639 primary->disable_plane = skylake_disable_primary_plane;
13640 } else if (HAS_PCH_SPLIT(dev_priv)) {
13641 intel_primary_formats = i965_primary_formats;
13642 num_formats = ARRAY_SIZE(i965_primary_formats);
13643
13644 primary->update_plane = ironlake_update_primary_plane;
13645 primary->disable_plane = i9xx_disable_primary_plane;
13646 } else if (INTEL_GEN(dev_priv) >= 4) {
13647 intel_primary_formats = i965_primary_formats;
13648 num_formats = ARRAY_SIZE(i965_primary_formats);
13649
13650 primary->update_plane = i9xx_update_primary_plane;
13651 primary->disable_plane = i9xx_disable_primary_plane;
13652 } else {
13653 intel_primary_formats = i8xx_primary_formats;
13654 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13655
13656 primary->update_plane = i9xx_update_primary_plane;
13657 primary->disable_plane = i9xx_disable_primary_plane;
13658 }
13659
13660 if (INTEL_GEN(dev_priv) >= 9)
13661 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13662 0, &intel_plane_funcs,
13663 intel_primary_formats, num_formats,
13664 DRM_PLANE_TYPE_PRIMARY,
13665 "plane 1%c", pipe_name(pipe));
13666 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13667 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13668 0, &intel_plane_funcs,
13669 intel_primary_formats, num_formats,
13670 DRM_PLANE_TYPE_PRIMARY,
13671 "primary %c", pipe_name(pipe));
13672 else
13673 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13674 0, &intel_plane_funcs,
13675 intel_primary_formats, num_formats,
13676 DRM_PLANE_TYPE_PRIMARY,
13677 "plane %c", plane_name(primary->plane));
13678 if (ret)
13679 goto fail;
13680
13681 if (INTEL_GEN(dev_priv) >= 9) {
13682 supported_rotations =
13683 DRM_ROTATE_0 | DRM_ROTATE_90 |
13684 DRM_ROTATE_180 | DRM_ROTATE_270;
13685 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13686 supported_rotations =
13687 DRM_ROTATE_0 | DRM_ROTATE_180 |
13688 DRM_REFLECT_X;
13689 } else if (INTEL_GEN(dev_priv) >= 4) {
13690 supported_rotations =
13691 DRM_ROTATE_0 | DRM_ROTATE_180;
13692 } else {
13693 supported_rotations = DRM_ROTATE_0;
13694 }
13695
13696 if (INTEL_GEN(dev_priv) >= 4)
13697 drm_plane_create_rotation_property(&primary->base,
13698 DRM_ROTATE_0,
13699 supported_rotations);
13700
13701 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13702
13703 return primary;
13704
13705 fail:
13706 kfree(state);
13707 kfree(primary);
13708
13709 return ERR_PTR(ret);
13710 }
13711
13712 static int
13713 intel_check_cursor_plane(struct drm_plane *plane,
13714 struct intel_crtc_state *crtc_state,
13715 struct intel_plane_state *state)
13716 {
13717 struct drm_framebuffer *fb = state->base.fb;
13718 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13719 enum pipe pipe = to_intel_plane(plane)->pipe;
13720 unsigned stride;
13721 int ret;
13722
13723 ret = drm_plane_helper_check_state(&state->base,
13724 &state->clip,
13725 DRM_PLANE_HELPER_NO_SCALING,
13726 DRM_PLANE_HELPER_NO_SCALING,
13727 true, true);
13728 if (ret)
13729 return ret;
13730
13731 /* if we want to turn off the cursor ignore width and height */
13732 if (!obj)
13733 return 0;
13734
13735 /* Check for which cursor types we support */
13736 if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
13737 state->base.crtc_h)) {
13738 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13739 state->base.crtc_w, state->base.crtc_h);
13740 return -EINVAL;
13741 }
13742
13743 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13744 if (obj->base.size < stride * state->base.crtc_h) {
13745 DRM_DEBUG_KMS("buffer is too small\n");
13746 return -ENOMEM;
13747 }
13748
13749 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
13750 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13751 return -EINVAL;
13752 }
13753
13754 /*
13755 * There's something wrong with the cursor on CHV pipe C.
13756 * If it straddles the left edge of the screen then
13757 * moving it away from the edge or disabling it often
13758 * results in a pipe underrun, and often that can lead to
13759 * dead pipe (constant underrun reported, and it scans
13760 * out just a solid color). To recover from that, the
13761 * display power well must be turned off and on again.
13762 * Refuse the put the cursor into that compromised position.
13763 */
13764 if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
13765 state->base.visible && state->base.crtc_x < 0) {
13766 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13767 return -EINVAL;
13768 }
13769
13770 return 0;
13771 }
13772
13773 static void
13774 intel_disable_cursor_plane(struct drm_plane *plane,
13775 struct drm_crtc *crtc)
13776 {
13777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13778
13779 intel_crtc->cursor_addr = 0;
13780 intel_crtc_update_cursor(crtc, NULL);
13781 }
13782
13783 static void
13784 intel_update_cursor_plane(struct drm_plane *plane,
13785 const struct intel_crtc_state *crtc_state,
13786 const struct intel_plane_state *state)
13787 {
13788 struct drm_crtc *crtc = crtc_state->base.crtc;
13789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13790 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13791 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13792 uint32_t addr;
13793
13794 if (!obj)
13795 addr = 0;
13796 else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13797 addr = intel_plane_ggtt_offset(state);
13798 else
13799 addr = obj->phys_handle->busaddr;
13800
13801 intel_crtc->cursor_addr = addr;
13802 intel_crtc_update_cursor(crtc, state);
13803 }
13804
13805 static struct intel_plane *
13806 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13807 {
13808 struct intel_plane *cursor = NULL;
13809 struct intel_plane_state *state = NULL;
13810 int ret;
13811
13812 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13813 if (!cursor) {
13814 ret = -ENOMEM;
13815 goto fail;
13816 }
13817
13818 state = intel_create_plane_state(&cursor->base);
13819 if (!state) {
13820 ret = -ENOMEM;
13821 goto fail;
13822 }
13823
13824 cursor->base.state = &state->base;
13825
13826 cursor->can_scale = false;
13827 cursor->max_downscale = 1;
13828 cursor->pipe = pipe;
13829 cursor->plane = pipe;
13830 cursor->id = PLANE_CURSOR;
13831 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13832 cursor->check_plane = intel_check_cursor_plane;
13833 cursor->update_plane = intel_update_cursor_plane;
13834 cursor->disable_plane = intel_disable_cursor_plane;
13835
13836 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13837 0, &intel_cursor_plane_funcs,
13838 intel_cursor_formats,
13839 ARRAY_SIZE(intel_cursor_formats),
13840 DRM_PLANE_TYPE_CURSOR,
13841 "cursor %c", pipe_name(pipe));
13842 if (ret)
13843 goto fail;
13844
13845 if (INTEL_GEN(dev_priv) >= 4)
13846 drm_plane_create_rotation_property(&cursor->base,
13847 DRM_ROTATE_0,
13848 DRM_ROTATE_0 |
13849 DRM_ROTATE_180);
13850
13851 if (INTEL_GEN(dev_priv) >= 9)
13852 state->scaler_id = -1;
13853
13854 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13855
13856 return cursor;
13857
13858 fail:
13859 kfree(state);
13860 kfree(cursor);
13861
13862 return ERR_PTR(ret);
13863 }
13864
13865 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13866 struct intel_crtc_state *crtc_state)
13867 {
13868 struct intel_crtc_scaler_state *scaler_state =
13869 &crtc_state->scaler_state;
13870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13871 int i;
13872
13873 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13874 if (!crtc->num_scalers)
13875 return;
13876
13877 for (i = 0; i < crtc->num_scalers; i++) {
13878 struct intel_scaler *scaler = &scaler_state->scalers[i];
13879
13880 scaler->in_use = 0;
13881 scaler->mode = PS_SCALER_MODE_DYN;
13882 }
13883
13884 scaler_state->scaler_id = -1;
13885 }
13886
13887 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13888 {
13889 struct intel_crtc *intel_crtc;
13890 struct intel_crtc_state *crtc_state = NULL;
13891 struct intel_plane *primary = NULL;
13892 struct intel_plane *cursor = NULL;
13893 int sprite, ret;
13894
13895 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13896 if (!intel_crtc)
13897 return -ENOMEM;
13898
13899 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13900 if (!crtc_state) {
13901 ret = -ENOMEM;
13902 goto fail;
13903 }
13904 intel_crtc->config = crtc_state;
13905 intel_crtc->base.state = &crtc_state->base;
13906 crtc_state->base.crtc = &intel_crtc->base;
13907
13908 primary = intel_primary_plane_create(dev_priv, pipe);
13909 if (IS_ERR(primary)) {
13910 ret = PTR_ERR(primary);
13911 goto fail;
13912 }
13913 intel_crtc->plane_ids_mask |= BIT(primary->id);
13914
13915 for_each_sprite(dev_priv, pipe, sprite) {
13916 struct intel_plane *plane;
13917
13918 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13919 if (IS_ERR(plane)) {
13920 ret = PTR_ERR(plane);
13921 goto fail;
13922 }
13923 intel_crtc->plane_ids_mask |= BIT(plane->id);
13924 }
13925
13926 cursor = intel_cursor_plane_create(dev_priv, pipe);
13927 if (IS_ERR(cursor)) {
13928 ret = PTR_ERR(cursor);
13929 goto fail;
13930 }
13931 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13932
13933 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13934 &primary->base, &cursor->base,
13935 &intel_crtc_funcs,
13936 "pipe %c", pipe_name(pipe));
13937 if (ret)
13938 goto fail;
13939
13940 intel_crtc->pipe = pipe;
13941 intel_crtc->plane = primary->plane;
13942
13943 intel_crtc->cursor_base = ~0;
13944 intel_crtc->cursor_cntl = ~0;
13945 intel_crtc->cursor_size = ~0;
13946
13947 intel_crtc->wm.cxsr_allowed = true;
13948
13949 /* initialize shared scalers */
13950 intel_crtc_init_scalers(intel_crtc, crtc_state);
13951
13952 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13953 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13954 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13955 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13956
13957 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13958
13959 intel_color_init(&intel_crtc->base);
13960
13961 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13962
13963 return 0;
13964
13965 fail:
13966 /*
13967 * drm_mode_config_cleanup() will free up any
13968 * crtcs/planes already initialized.
13969 */
13970 kfree(crtc_state);
13971 kfree(intel_crtc);
13972
13973 return ret;
13974 }
13975
13976 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13977 {
13978 struct drm_encoder *encoder = connector->base.encoder;
13979 struct drm_device *dev = connector->base.dev;
13980
13981 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13982
13983 if (!encoder || WARN_ON(!encoder->crtc))
13984 return INVALID_PIPE;
13985
13986 return to_intel_crtc(encoder->crtc)->pipe;
13987 }
13988
13989 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13990 struct drm_file *file)
13991 {
13992 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13993 struct drm_crtc *drmmode_crtc;
13994 struct intel_crtc *crtc;
13995
13996 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13997 if (!drmmode_crtc)
13998 return -ENOENT;
13999
14000 crtc = to_intel_crtc(drmmode_crtc);
14001 pipe_from_crtc_id->pipe = crtc->pipe;
14002
14003 return 0;
14004 }
14005
14006 static int intel_encoder_clones(struct intel_encoder *encoder)
14007 {
14008 struct drm_device *dev = encoder->base.dev;
14009 struct intel_encoder *source_encoder;
14010 int index_mask = 0;
14011 int entry = 0;
14012
14013 for_each_intel_encoder(dev, source_encoder) {
14014 if (encoders_cloneable(encoder, source_encoder))
14015 index_mask |= (1 << entry);
14016
14017 entry++;
14018 }
14019
14020 return index_mask;
14021 }
14022
14023 static bool has_edp_a(struct drm_i915_private *dev_priv)
14024 {
14025 if (!IS_MOBILE(dev_priv))
14026 return false;
14027
14028 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14029 return false;
14030
14031 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14032 return false;
14033
14034 return true;
14035 }
14036
14037 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14038 {
14039 if (INTEL_GEN(dev_priv) >= 9)
14040 return false;
14041
14042 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14043 return false;
14044
14045 if (IS_CHERRYVIEW(dev_priv))
14046 return false;
14047
14048 if (HAS_PCH_LPT_H(dev_priv) &&
14049 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14050 return false;
14051
14052 /* DDI E can't be used if DDI A requires 4 lanes */
14053 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14054 return false;
14055
14056 if (!dev_priv->vbt.int_crt_support)
14057 return false;
14058
14059 return true;
14060 }
14061
14062 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14063 {
14064 int pps_num;
14065 int pps_idx;
14066
14067 if (HAS_DDI(dev_priv))
14068 return;
14069 /*
14070 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14071 * everywhere where registers can be write protected.
14072 */
14073 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14074 pps_num = 2;
14075 else
14076 pps_num = 1;
14077
14078 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14079 u32 val = I915_READ(PP_CONTROL(pps_idx));
14080
14081 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14082 I915_WRITE(PP_CONTROL(pps_idx), val);
14083 }
14084 }
14085
14086 static void intel_pps_init(struct drm_i915_private *dev_priv)
14087 {
14088 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14089 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14090 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14091 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14092 else
14093 dev_priv->pps_mmio_base = PPS_BASE;
14094
14095 intel_pps_unlock_regs_wa(dev_priv);
14096 }
14097
14098 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14099 {
14100 struct intel_encoder *encoder;
14101 bool dpd_is_edp = false;
14102
14103 intel_pps_init(dev_priv);
14104
14105 /*
14106 * intel_edp_init_connector() depends on this completing first, to
14107 * prevent the registeration of both eDP and LVDS and the incorrect
14108 * sharing of the PPS.
14109 */
14110 intel_lvds_init(dev_priv);
14111
14112 if (intel_crt_present(dev_priv))
14113 intel_crt_init(dev_priv);
14114
14115 if (IS_GEN9_LP(dev_priv)) {
14116 /*
14117 * FIXME: Broxton doesn't support port detection via the
14118 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14119 * detect the ports.
14120 */
14121 intel_ddi_init(dev_priv, PORT_A);
14122 intel_ddi_init(dev_priv, PORT_B);
14123 intel_ddi_init(dev_priv, PORT_C);
14124
14125 intel_dsi_init(dev_priv);
14126 } else if (HAS_DDI(dev_priv)) {
14127 int found;
14128
14129 /*
14130 * Haswell uses DDI functions to detect digital outputs.
14131 * On SKL pre-D0 the strap isn't connected, so we assume
14132 * it's there.
14133 */
14134 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14135 /* WaIgnoreDDIAStrap: skl */
14136 if (found || IS_GEN9_BC(dev_priv))
14137 intel_ddi_init(dev_priv, PORT_A);
14138
14139 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14140 * register */
14141 found = I915_READ(SFUSE_STRAP);
14142
14143 if (found & SFUSE_STRAP_DDIB_DETECTED)
14144 intel_ddi_init(dev_priv, PORT_B);
14145 if (found & SFUSE_STRAP_DDIC_DETECTED)
14146 intel_ddi_init(dev_priv, PORT_C);
14147 if (found & SFUSE_STRAP_DDID_DETECTED)
14148 intel_ddi_init(dev_priv, PORT_D);
14149 /*
14150 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14151 */
14152 if (IS_GEN9_BC(dev_priv) &&
14153 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14154 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14155 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14156 intel_ddi_init(dev_priv, PORT_E);
14157
14158 } else if (HAS_PCH_SPLIT(dev_priv)) {
14159 int found;
14160 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14161
14162 if (has_edp_a(dev_priv))
14163 intel_dp_init(dev_priv, DP_A, PORT_A);
14164
14165 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14166 /* PCH SDVOB multiplex with HDMIB */
14167 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14168 if (!found)
14169 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14170 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14171 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14172 }
14173
14174 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14175 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14176
14177 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14178 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14179
14180 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14181 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14182
14183 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14184 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14185 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14186 bool has_edp, has_port;
14187
14188 /*
14189 * The DP_DETECTED bit is the latched state of the DDC
14190 * SDA pin at boot. However since eDP doesn't require DDC
14191 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14192 * eDP ports may have been muxed to an alternate function.
14193 * Thus we can't rely on the DP_DETECTED bit alone to detect
14194 * eDP ports. Consult the VBT as well as DP_DETECTED to
14195 * detect eDP ports.
14196 *
14197 * Sadly the straps seem to be missing sometimes even for HDMI
14198 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14199 * and VBT for the presence of the port. Additionally we can't
14200 * trust the port type the VBT declares as we've seen at least
14201 * HDMI ports that the VBT claim are DP or eDP.
14202 */
14203 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14204 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14205 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14206 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14207 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14208 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14209
14210 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14211 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14212 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14213 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14214 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14215 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14216
14217 if (IS_CHERRYVIEW(dev_priv)) {
14218 /*
14219 * eDP not supported on port D,
14220 * so no need to worry about it
14221 */
14222 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14223 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14224 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14225 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14226 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14227 }
14228
14229 intel_dsi_init(dev_priv);
14230 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14231 bool found = false;
14232
14233 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14234 DRM_DEBUG_KMS("probing SDVOB\n");
14235 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14236 if (!found && IS_G4X(dev_priv)) {
14237 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14238 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14239 }
14240
14241 if (!found && IS_G4X(dev_priv))
14242 intel_dp_init(dev_priv, DP_B, PORT_B);
14243 }
14244
14245 /* Before G4X SDVOC doesn't have its own detect register */
14246
14247 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14248 DRM_DEBUG_KMS("probing SDVOC\n");
14249 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14250 }
14251
14252 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14253
14254 if (IS_G4X(dev_priv)) {
14255 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14256 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14257 }
14258 if (IS_G4X(dev_priv))
14259 intel_dp_init(dev_priv, DP_C, PORT_C);
14260 }
14261
14262 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14263 intel_dp_init(dev_priv, DP_D, PORT_D);
14264 } else if (IS_GEN2(dev_priv))
14265 intel_dvo_init(dev_priv);
14266
14267 if (SUPPORTS_TV(dev_priv))
14268 intel_tv_init(dev_priv);
14269
14270 intel_psr_init(dev_priv);
14271
14272 for_each_intel_encoder(&dev_priv->drm, encoder) {
14273 encoder->base.possible_crtcs = encoder->crtc_mask;
14274 encoder->base.possible_clones =
14275 intel_encoder_clones(encoder);
14276 }
14277
14278 intel_init_pch_refclk(dev_priv);
14279
14280 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14281 }
14282
14283 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14284 {
14285 struct drm_device *dev = fb->dev;
14286 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14287
14288 drm_framebuffer_cleanup(fb);
14289 mutex_lock(&dev->struct_mutex);
14290 WARN_ON(!intel_fb->obj->framebuffer_references--);
14291 i915_gem_object_put(intel_fb->obj);
14292 mutex_unlock(&dev->struct_mutex);
14293 kfree(intel_fb);
14294 }
14295
14296 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14297 struct drm_file *file,
14298 unsigned int *handle)
14299 {
14300 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14301 struct drm_i915_gem_object *obj = intel_fb->obj;
14302
14303 if (obj->userptr.mm) {
14304 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14305 return -EINVAL;
14306 }
14307
14308 return drm_gem_handle_create(file, &obj->base, handle);
14309 }
14310
14311 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14312 struct drm_file *file,
14313 unsigned flags, unsigned color,
14314 struct drm_clip_rect *clips,
14315 unsigned num_clips)
14316 {
14317 struct drm_device *dev = fb->dev;
14318 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14319 struct drm_i915_gem_object *obj = intel_fb->obj;
14320
14321 mutex_lock(&dev->struct_mutex);
14322 if (obj->pin_display && obj->cache_dirty)
14323 i915_gem_clflush_object(obj, true);
14324 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14325 mutex_unlock(&dev->struct_mutex);
14326
14327 return 0;
14328 }
14329
14330 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14331 .destroy = intel_user_framebuffer_destroy,
14332 .create_handle = intel_user_framebuffer_create_handle,
14333 .dirty = intel_user_framebuffer_dirty,
14334 };
14335
14336 static
14337 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14338 uint64_t fb_modifier, uint32_t pixel_format)
14339 {
14340 u32 gen = INTEL_INFO(dev_priv)->gen;
14341
14342 if (gen >= 9) {
14343 int cpp = drm_format_plane_cpp(pixel_format, 0);
14344
14345 /* "The stride in bytes must not exceed the of the size of 8K
14346 * pixels and 32K bytes."
14347 */
14348 return min(8192 * cpp, 32768);
14349 } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
14350 !IS_CHERRYVIEW(dev_priv)) {
14351 return 32*1024;
14352 } else if (gen >= 4) {
14353 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14354 return 16*1024;
14355 else
14356 return 32*1024;
14357 } else if (gen >= 3) {
14358 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14359 return 8*1024;
14360 else
14361 return 16*1024;
14362 } else {
14363 /* XXX DSPC is limited to 4k tiled */
14364 return 8*1024;
14365 }
14366 }
14367
14368 static int intel_framebuffer_init(struct drm_device *dev,
14369 struct intel_framebuffer *intel_fb,
14370 struct drm_mode_fb_cmd2 *mode_cmd,
14371 struct drm_i915_gem_object *obj)
14372 {
14373 struct drm_i915_private *dev_priv = to_i915(dev);
14374 unsigned int tiling = i915_gem_object_get_tiling(obj);
14375 int ret;
14376 u32 pitch_limit, stride_alignment;
14377 struct drm_format_name_buf format_name;
14378
14379 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14380
14381 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14382 /*
14383 * If there's a fence, enforce that
14384 * the fb modifier and tiling mode match.
14385 */
14386 if (tiling != I915_TILING_NONE &&
14387 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14388 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14389 return -EINVAL;
14390 }
14391 } else {
14392 if (tiling == I915_TILING_X) {
14393 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14394 } else if (tiling == I915_TILING_Y) {
14395 DRM_DEBUG("No Y tiling for legacy addfb\n");
14396 return -EINVAL;
14397 }
14398 }
14399
14400 /* Passed in modifier sanity checking. */
14401 switch (mode_cmd->modifier[0]) {
14402 case I915_FORMAT_MOD_Y_TILED:
14403 case I915_FORMAT_MOD_Yf_TILED:
14404 if (INTEL_GEN(dev_priv) < 9) {
14405 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14406 mode_cmd->modifier[0]);
14407 return -EINVAL;
14408 }
14409 case DRM_FORMAT_MOD_NONE:
14410 case I915_FORMAT_MOD_X_TILED:
14411 break;
14412 default:
14413 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14414 mode_cmd->modifier[0]);
14415 return -EINVAL;
14416 }
14417
14418 /*
14419 * gen2/3 display engine uses the fence if present,
14420 * so the tiling mode must match the fb modifier exactly.
14421 */
14422 if (INTEL_INFO(dev_priv)->gen < 4 &&
14423 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14424 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
14425 return -EINVAL;
14426 }
14427
14428 stride_alignment = intel_fb_stride_alignment(dev_priv,
14429 mode_cmd->modifier[0],
14430 mode_cmd->pixel_format);
14431 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14432 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14433 mode_cmd->pitches[0], stride_alignment);
14434 return -EINVAL;
14435 }
14436
14437 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14438 mode_cmd->pixel_format);
14439 if (mode_cmd->pitches[0] > pitch_limit) {
14440 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14441 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14442 "tiled" : "linear",
14443 mode_cmd->pitches[0], pitch_limit);
14444 return -EINVAL;
14445 }
14446
14447 /*
14448 * If there's a fence, enforce that
14449 * the fb pitch and fence stride match.
14450 */
14451 if (tiling != I915_TILING_NONE &&
14452 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
14453 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14454 mode_cmd->pitches[0],
14455 i915_gem_object_get_stride(obj));
14456 return -EINVAL;
14457 }
14458
14459 /* Reject formats not supported by any plane early. */
14460 switch (mode_cmd->pixel_format) {
14461 case DRM_FORMAT_C8:
14462 case DRM_FORMAT_RGB565:
14463 case DRM_FORMAT_XRGB8888:
14464 case DRM_FORMAT_ARGB8888:
14465 break;
14466 case DRM_FORMAT_XRGB1555:
14467 if (INTEL_GEN(dev_priv) > 3) {
14468 DRM_DEBUG("unsupported pixel format: %s\n",
14469 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14470 return -EINVAL;
14471 }
14472 break;
14473 case DRM_FORMAT_ABGR8888:
14474 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14475 INTEL_GEN(dev_priv) < 9) {
14476 DRM_DEBUG("unsupported pixel format: %s\n",
14477 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14478 return -EINVAL;
14479 }
14480 break;
14481 case DRM_FORMAT_XBGR8888:
14482 case DRM_FORMAT_XRGB2101010:
14483 case DRM_FORMAT_XBGR2101010:
14484 if (INTEL_GEN(dev_priv) < 4) {
14485 DRM_DEBUG("unsupported pixel format: %s\n",
14486 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14487 return -EINVAL;
14488 }
14489 break;
14490 case DRM_FORMAT_ABGR2101010:
14491 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14492 DRM_DEBUG("unsupported pixel format: %s\n",
14493 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14494 return -EINVAL;
14495 }
14496 break;
14497 case DRM_FORMAT_YUYV:
14498 case DRM_FORMAT_UYVY:
14499 case DRM_FORMAT_YVYU:
14500 case DRM_FORMAT_VYUY:
14501 if (INTEL_GEN(dev_priv) < 5) {
14502 DRM_DEBUG("unsupported pixel format: %s\n",
14503 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14504 return -EINVAL;
14505 }
14506 break;
14507 default:
14508 DRM_DEBUG("unsupported pixel format: %s\n",
14509 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14510 return -EINVAL;
14511 }
14512
14513 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14514 if (mode_cmd->offsets[0] != 0)
14515 return -EINVAL;
14516
14517 drm_helper_mode_fill_fb_struct(dev, &intel_fb->base, mode_cmd);
14518 intel_fb->obj = obj;
14519
14520 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14521 if (ret)
14522 return ret;
14523
14524 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14525 if (ret) {
14526 DRM_ERROR("framebuffer init failed %d\n", ret);
14527 return ret;
14528 }
14529
14530 intel_fb->obj->framebuffer_references++;
14531
14532 return 0;
14533 }
14534
14535 static struct drm_framebuffer *
14536 intel_user_framebuffer_create(struct drm_device *dev,
14537 struct drm_file *filp,
14538 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14539 {
14540 struct drm_framebuffer *fb;
14541 struct drm_i915_gem_object *obj;
14542 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14543
14544 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14545 if (!obj)
14546 return ERR_PTR(-ENOENT);
14547
14548 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14549 if (IS_ERR(fb))
14550 i915_gem_object_put(obj);
14551
14552 return fb;
14553 }
14554
14555 static void intel_atomic_state_free(struct drm_atomic_state *state)
14556 {
14557 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14558
14559 drm_atomic_state_default_release(state);
14560
14561 i915_sw_fence_fini(&intel_state->commit_ready);
14562
14563 kfree(state);
14564 }
14565
14566 static const struct drm_mode_config_funcs intel_mode_funcs = {
14567 .fb_create = intel_user_framebuffer_create,
14568 .output_poll_changed = intel_fbdev_output_poll_changed,
14569 .atomic_check = intel_atomic_check,
14570 .atomic_commit = intel_atomic_commit,
14571 .atomic_state_alloc = intel_atomic_state_alloc,
14572 .atomic_state_clear = intel_atomic_state_clear,
14573 .atomic_state_free = intel_atomic_state_free,
14574 };
14575
14576 /**
14577 * intel_init_display_hooks - initialize the display modesetting hooks
14578 * @dev_priv: device private
14579 */
14580 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14581 {
14582 intel_init_cdclk_hooks(dev_priv);
14583
14584 if (INTEL_INFO(dev_priv)->gen >= 9) {
14585 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14586 dev_priv->display.get_initial_plane_config =
14587 skylake_get_initial_plane_config;
14588 dev_priv->display.crtc_compute_clock =
14589 haswell_crtc_compute_clock;
14590 dev_priv->display.crtc_enable = haswell_crtc_enable;
14591 dev_priv->display.crtc_disable = haswell_crtc_disable;
14592 } else if (HAS_DDI(dev_priv)) {
14593 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14594 dev_priv->display.get_initial_plane_config =
14595 ironlake_get_initial_plane_config;
14596 dev_priv->display.crtc_compute_clock =
14597 haswell_crtc_compute_clock;
14598 dev_priv->display.crtc_enable = haswell_crtc_enable;
14599 dev_priv->display.crtc_disable = haswell_crtc_disable;
14600 } else if (HAS_PCH_SPLIT(dev_priv)) {
14601 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14602 dev_priv->display.get_initial_plane_config =
14603 ironlake_get_initial_plane_config;
14604 dev_priv->display.crtc_compute_clock =
14605 ironlake_crtc_compute_clock;
14606 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14607 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14608 } else if (IS_CHERRYVIEW(dev_priv)) {
14609 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14610 dev_priv->display.get_initial_plane_config =
14611 i9xx_get_initial_plane_config;
14612 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14613 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14614 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14615 } else if (IS_VALLEYVIEW(dev_priv)) {
14616 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14617 dev_priv->display.get_initial_plane_config =
14618 i9xx_get_initial_plane_config;
14619 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14620 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14621 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14622 } else if (IS_G4X(dev_priv)) {
14623 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14624 dev_priv->display.get_initial_plane_config =
14625 i9xx_get_initial_plane_config;
14626 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14627 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14628 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14629 } else if (IS_PINEVIEW(dev_priv)) {
14630 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14631 dev_priv->display.get_initial_plane_config =
14632 i9xx_get_initial_plane_config;
14633 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14634 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14635 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14636 } else if (!IS_GEN2(dev_priv)) {
14637 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14638 dev_priv->display.get_initial_plane_config =
14639 i9xx_get_initial_plane_config;
14640 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14641 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14642 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14643 } else {
14644 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14645 dev_priv->display.get_initial_plane_config =
14646 i9xx_get_initial_plane_config;
14647 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14648 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14649 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14650 }
14651
14652 if (IS_GEN5(dev_priv)) {
14653 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14654 } else if (IS_GEN6(dev_priv)) {
14655 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14656 } else if (IS_IVYBRIDGE(dev_priv)) {
14657 /* FIXME: detect B0+ stepping and use auto training */
14658 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14659 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14660 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14661 }
14662
14663 if (dev_priv->info.gen >= 9)
14664 dev_priv->display.update_crtcs = skl_update_crtcs;
14665 else
14666 dev_priv->display.update_crtcs = intel_update_crtcs;
14667
14668 switch (INTEL_INFO(dev_priv)->gen) {
14669 case 2:
14670 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14671 break;
14672
14673 case 3:
14674 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14675 break;
14676
14677 case 4:
14678 case 5:
14679 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14680 break;
14681
14682 case 6:
14683 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14684 break;
14685 case 7:
14686 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14687 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14688 break;
14689 case 9:
14690 /* Drop through - unsupported since execlist only. */
14691 default:
14692 /* Default just returns -ENODEV to indicate unsupported */
14693 dev_priv->display.queue_flip = intel_default_queue_flip;
14694 }
14695 }
14696
14697 /*
14698 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14699 * resume, or other times. This quirk makes sure that's the case for
14700 * affected systems.
14701 */
14702 static void quirk_pipea_force(struct drm_device *dev)
14703 {
14704 struct drm_i915_private *dev_priv = to_i915(dev);
14705
14706 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14707 DRM_INFO("applying pipe a force quirk\n");
14708 }
14709
14710 static void quirk_pipeb_force(struct drm_device *dev)
14711 {
14712 struct drm_i915_private *dev_priv = to_i915(dev);
14713
14714 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14715 DRM_INFO("applying pipe b force quirk\n");
14716 }
14717
14718 /*
14719 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14720 */
14721 static void quirk_ssc_force_disable(struct drm_device *dev)
14722 {
14723 struct drm_i915_private *dev_priv = to_i915(dev);
14724 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14725 DRM_INFO("applying lvds SSC disable quirk\n");
14726 }
14727
14728 /*
14729 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14730 * brightness value
14731 */
14732 static void quirk_invert_brightness(struct drm_device *dev)
14733 {
14734 struct drm_i915_private *dev_priv = to_i915(dev);
14735 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14736 DRM_INFO("applying inverted panel brightness quirk\n");
14737 }
14738
14739 /* Some VBT's incorrectly indicate no backlight is present */
14740 static void quirk_backlight_present(struct drm_device *dev)
14741 {
14742 struct drm_i915_private *dev_priv = to_i915(dev);
14743 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14744 DRM_INFO("applying backlight present quirk\n");
14745 }
14746
14747 struct intel_quirk {
14748 int device;
14749 int subsystem_vendor;
14750 int subsystem_device;
14751 void (*hook)(struct drm_device *dev);
14752 };
14753
14754 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14755 struct intel_dmi_quirk {
14756 void (*hook)(struct drm_device *dev);
14757 const struct dmi_system_id (*dmi_id_list)[];
14758 };
14759
14760 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14761 {
14762 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14763 return 1;
14764 }
14765
14766 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14767 {
14768 .dmi_id_list = &(const struct dmi_system_id[]) {
14769 {
14770 .callback = intel_dmi_reverse_brightness,
14771 .ident = "NCR Corporation",
14772 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14773 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14774 },
14775 },
14776 { } /* terminating entry */
14777 },
14778 .hook = quirk_invert_brightness,
14779 },
14780 };
14781
14782 static struct intel_quirk intel_quirks[] = {
14783 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14784 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14785
14786 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14787 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14788
14789 /* 830 needs to leave pipe A & dpll A up */
14790 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14791
14792 /* 830 needs to leave pipe B & dpll B up */
14793 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14794
14795 /* Lenovo U160 cannot use SSC on LVDS */
14796 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14797
14798 /* Sony Vaio Y cannot use SSC on LVDS */
14799 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14800
14801 /* Acer Aspire 5734Z must invert backlight brightness */
14802 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14803
14804 /* Acer/eMachines G725 */
14805 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14806
14807 /* Acer/eMachines e725 */
14808 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14809
14810 /* Acer/Packard Bell NCL20 */
14811 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14812
14813 /* Acer Aspire 4736Z */
14814 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14815
14816 /* Acer Aspire 5336 */
14817 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14818
14819 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14820 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14821
14822 /* Acer C720 Chromebook (Core i3 4005U) */
14823 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14824
14825 /* Apple Macbook 2,1 (Core 2 T7400) */
14826 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14827
14828 /* Apple Macbook 4,1 */
14829 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14830
14831 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14832 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14833
14834 /* HP Chromebook 14 (Celeron 2955U) */
14835 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14836
14837 /* Dell Chromebook 11 */
14838 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14839
14840 /* Dell Chromebook 11 (2015 version) */
14841 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14842 };
14843
14844 static void intel_init_quirks(struct drm_device *dev)
14845 {
14846 struct pci_dev *d = dev->pdev;
14847 int i;
14848
14849 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14850 struct intel_quirk *q = &intel_quirks[i];
14851
14852 if (d->device == q->device &&
14853 (d->subsystem_vendor == q->subsystem_vendor ||
14854 q->subsystem_vendor == PCI_ANY_ID) &&
14855 (d->subsystem_device == q->subsystem_device ||
14856 q->subsystem_device == PCI_ANY_ID))
14857 q->hook(dev);
14858 }
14859 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14860 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14861 intel_dmi_quirks[i].hook(dev);
14862 }
14863 }
14864
14865 /* Disable the VGA plane that we never use */
14866 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14867 {
14868 struct pci_dev *pdev = dev_priv->drm.pdev;
14869 u8 sr1;
14870 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14871
14872 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14873 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14874 outb(SR01, VGA_SR_INDEX);
14875 sr1 = inb(VGA_SR_DATA);
14876 outb(sr1 | 1<<5, VGA_SR_DATA);
14877 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14878 udelay(300);
14879
14880 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14881 POSTING_READ(vga_reg);
14882 }
14883
14884 void intel_modeset_init_hw(struct drm_device *dev)
14885 {
14886 struct drm_i915_private *dev_priv = to_i915(dev);
14887
14888 intel_update_cdclk(dev_priv);
14889 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14890
14891 intel_init_clock_gating(dev_priv);
14892 }
14893
14894 /*
14895 * Calculate what we think the watermarks should be for the state we've read
14896 * out of the hardware and then immediately program those watermarks so that
14897 * we ensure the hardware settings match our internal state.
14898 *
14899 * We can calculate what we think WM's should be by creating a duplicate of the
14900 * current state (which was constructed during hardware readout) and running it
14901 * through the atomic check code to calculate new watermark values in the
14902 * state object.
14903 */
14904 static void sanitize_watermarks(struct drm_device *dev)
14905 {
14906 struct drm_i915_private *dev_priv = to_i915(dev);
14907 struct drm_atomic_state *state;
14908 struct intel_atomic_state *intel_state;
14909 struct drm_crtc *crtc;
14910 struct drm_crtc_state *cstate;
14911 struct drm_modeset_acquire_ctx ctx;
14912 int ret;
14913 int i;
14914
14915 /* Only supported on platforms that use atomic watermark design */
14916 if (!dev_priv->display.optimize_watermarks)
14917 return;
14918
14919 /*
14920 * We need to hold connection_mutex before calling duplicate_state so
14921 * that the connector loop is protected.
14922 */
14923 drm_modeset_acquire_init(&ctx, 0);
14924 retry:
14925 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14926 if (ret == -EDEADLK) {
14927 drm_modeset_backoff(&ctx);
14928 goto retry;
14929 } else if (WARN_ON(ret)) {
14930 goto fail;
14931 }
14932
14933 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14934 if (WARN_ON(IS_ERR(state)))
14935 goto fail;
14936
14937 intel_state = to_intel_atomic_state(state);
14938
14939 /*
14940 * Hardware readout is the only time we don't want to calculate
14941 * intermediate watermarks (since we don't trust the current
14942 * watermarks).
14943 */
14944 intel_state->skip_intermediate_wm = true;
14945
14946 ret = intel_atomic_check(dev, state);
14947 if (ret) {
14948 /*
14949 * If we fail here, it means that the hardware appears to be
14950 * programmed in a way that shouldn't be possible, given our
14951 * understanding of watermark requirements. This might mean a
14952 * mistake in the hardware readout code or a mistake in the
14953 * watermark calculations for a given platform. Raise a WARN
14954 * so that this is noticeable.
14955 *
14956 * If this actually happens, we'll have to just leave the
14957 * BIOS-programmed watermarks untouched and hope for the best.
14958 */
14959 WARN(true, "Could not determine valid watermarks for inherited state\n");
14960 goto put_state;
14961 }
14962
14963 /* Write calculated watermark values back */
14964 for_each_crtc_in_state(state, crtc, cstate, i) {
14965 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14966
14967 cs->wm.need_postvbl_update = true;
14968 dev_priv->display.optimize_watermarks(intel_state, cs);
14969 }
14970
14971 put_state:
14972 drm_atomic_state_put(state);
14973 fail:
14974 drm_modeset_drop_locks(&ctx);
14975 drm_modeset_acquire_fini(&ctx);
14976 }
14977
14978 int intel_modeset_init(struct drm_device *dev)
14979 {
14980 struct drm_i915_private *dev_priv = to_i915(dev);
14981 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14982 enum pipe pipe;
14983 struct intel_crtc *crtc;
14984
14985 drm_mode_config_init(dev);
14986
14987 dev->mode_config.min_width = 0;
14988 dev->mode_config.min_height = 0;
14989
14990 dev->mode_config.preferred_depth = 24;
14991 dev->mode_config.prefer_shadow = 1;
14992
14993 dev->mode_config.allow_fb_modifiers = true;
14994
14995 dev->mode_config.funcs = &intel_mode_funcs;
14996
14997 INIT_WORK(&dev_priv->atomic_helper.free_work,
14998 intel_atomic_helper_free_state_worker);
14999
15000 intel_init_quirks(dev);
15001
15002 intel_init_pm(dev_priv);
15003
15004 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15005 return 0;
15006
15007 /*
15008 * There may be no VBT; and if the BIOS enabled SSC we can
15009 * just keep using it to avoid unnecessary flicker. Whereas if the
15010 * BIOS isn't using it, don't assume it will work even if the VBT
15011 * indicates as much.
15012 */
15013 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15014 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15015 DREF_SSC1_ENABLE);
15016
15017 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15018 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15019 bios_lvds_use_ssc ? "en" : "dis",
15020 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15021 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15022 }
15023 }
15024
15025 if (IS_GEN2(dev_priv)) {
15026 dev->mode_config.max_width = 2048;
15027 dev->mode_config.max_height = 2048;
15028 } else if (IS_GEN3(dev_priv)) {
15029 dev->mode_config.max_width = 4096;
15030 dev->mode_config.max_height = 4096;
15031 } else {
15032 dev->mode_config.max_width = 8192;
15033 dev->mode_config.max_height = 8192;
15034 }
15035
15036 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15037 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15038 dev->mode_config.cursor_height = 1023;
15039 } else if (IS_GEN2(dev_priv)) {
15040 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15041 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15042 } else {
15043 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15044 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15045 }
15046
15047 dev->mode_config.fb_base = ggtt->mappable_base;
15048
15049 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15050 INTEL_INFO(dev_priv)->num_pipes,
15051 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15052
15053 for_each_pipe(dev_priv, pipe) {
15054 int ret;
15055
15056 ret = intel_crtc_init(dev_priv, pipe);
15057 if (ret) {
15058 drm_mode_config_cleanup(dev);
15059 return ret;
15060 }
15061 }
15062
15063 intel_update_czclk(dev_priv);
15064 intel_update_cdclk(dev_priv);
15065 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
15066
15067 intel_shared_dpll_init(dev);
15068
15069 if (dev_priv->max_cdclk_freq == 0)
15070 intel_update_max_cdclk(dev_priv);
15071
15072 /* Just disable it once at startup */
15073 i915_disable_vga(dev_priv);
15074 intel_setup_outputs(dev_priv);
15075
15076 drm_modeset_lock_all(dev);
15077 intel_modeset_setup_hw_state(dev);
15078 drm_modeset_unlock_all(dev);
15079
15080 for_each_intel_crtc(dev, crtc) {
15081 struct intel_initial_plane_config plane_config = {};
15082
15083 if (!crtc->active)
15084 continue;
15085
15086 /*
15087 * Note that reserving the BIOS fb up front prevents us
15088 * from stuffing other stolen allocations like the ring
15089 * on top. This prevents some ugliness at boot time, and
15090 * can even allow for smooth boot transitions if the BIOS
15091 * fb is large enough for the active pipe configuration.
15092 */
15093 dev_priv->display.get_initial_plane_config(crtc,
15094 &plane_config);
15095
15096 /*
15097 * If the fb is shared between multiple heads, we'll
15098 * just get the first one.
15099 */
15100 intel_find_initial_plane_obj(crtc, &plane_config);
15101 }
15102
15103 /*
15104 * Make sure hardware watermarks really match the state we read out.
15105 * Note that we need to do this after reconstructing the BIOS fb's
15106 * since the watermark calculation done here will use pstate->fb.
15107 */
15108 sanitize_watermarks(dev);
15109
15110 return 0;
15111 }
15112
15113 static void intel_enable_pipe_a(struct drm_device *dev)
15114 {
15115 struct intel_connector *connector;
15116 struct drm_connector *crt = NULL;
15117 struct intel_load_detect_pipe load_detect_temp;
15118 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15119
15120 /* We can't just switch on the pipe A, we need to set things up with a
15121 * proper mode and output configuration. As a gross hack, enable pipe A
15122 * by enabling the load detect pipe once. */
15123 for_each_intel_connector(dev, connector) {
15124 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15125 crt = &connector->base;
15126 break;
15127 }
15128 }
15129
15130 if (!crt)
15131 return;
15132
15133 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15134 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15135 }
15136
15137 static bool
15138 intel_check_plane_mapping(struct intel_crtc *crtc)
15139 {
15140 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15141 u32 val;
15142
15143 if (INTEL_INFO(dev_priv)->num_pipes == 1)
15144 return true;
15145
15146 val = I915_READ(DSPCNTR(!crtc->plane));
15147
15148 if ((val & DISPLAY_PLANE_ENABLE) &&
15149 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15150 return false;
15151
15152 return true;
15153 }
15154
15155 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15156 {
15157 struct drm_device *dev = crtc->base.dev;
15158 struct intel_encoder *encoder;
15159
15160 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15161 return true;
15162
15163 return false;
15164 }
15165
15166 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15167 {
15168 struct drm_device *dev = encoder->base.dev;
15169 struct intel_connector *connector;
15170
15171 for_each_connector_on_encoder(dev, &encoder->base, connector)
15172 return connector;
15173
15174 return NULL;
15175 }
15176
15177 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15178 enum transcoder pch_transcoder)
15179 {
15180 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15181 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15182 }
15183
15184 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15185 {
15186 struct drm_device *dev = crtc->base.dev;
15187 struct drm_i915_private *dev_priv = to_i915(dev);
15188 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15189
15190 /* Clear any frame start delays used for debugging left by the BIOS */
15191 if (!transcoder_is_dsi(cpu_transcoder)) {
15192 i915_reg_t reg = PIPECONF(cpu_transcoder);
15193
15194 I915_WRITE(reg,
15195 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15196 }
15197
15198 /* restore vblank interrupts to correct state */
15199 drm_crtc_vblank_reset(&crtc->base);
15200 if (crtc->active) {
15201 struct intel_plane *plane;
15202
15203 drm_crtc_vblank_on(&crtc->base);
15204
15205 /* Disable everything but the primary plane */
15206 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15207 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15208 continue;
15209
15210 plane->disable_plane(&plane->base, &crtc->base);
15211 }
15212 }
15213
15214 /* We need to sanitize the plane -> pipe mapping first because this will
15215 * disable the crtc (and hence change the state) if it is wrong. Note
15216 * that gen4+ has a fixed plane -> pipe mapping. */
15217 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15218 bool plane;
15219
15220 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15221 crtc->base.base.id, crtc->base.name);
15222
15223 /* Pipe has the wrong plane attached and the plane is active.
15224 * Temporarily change the plane mapping and disable everything
15225 * ... */
15226 plane = crtc->plane;
15227 crtc->base.primary->state->visible = true;
15228 crtc->plane = !plane;
15229 intel_crtc_disable_noatomic(&crtc->base);
15230 crtc->plane = plane;
15231 }
15232
15233 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15234 crtc->pipe == PIPE_A && !crtc->active) {
15235 /* BIOS forgot to enable pipe A, this mostly happens after
15236 * resume. Force-enable the pipe to fix this, the update_dpms
15237 * call below we restore the pipe to the right state, but leave
15238 * the required bits on. */
15239 intel_enable_pipe_a(dev);
15240 }
15241
15242 /* Adjust the state of the output pipe according to whether we
15243 * have active connectors/encoders. */
15244 if (crtc->active && !intel_crtc_has_encoders(crtc))
15245 intel_crtc_disable_noatomic(&crtc->base);
15246
15247 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15248 /*
15249 * We start out with underrun reporting disabled to avoid races.
15250 * For correct bookkeeping mark this on active crtcs.
15251 *
15252 * Also on gmch platforms we dont have any hardware bits to
15253 * disable the underrun reporting. Which means we need to start
15254 * out with underrun reporting disabled also on inactive pipes,
15255 * since otherwise we'll complain about the garbage we read when
15256 * e.g. coming up after runtime pm.
15257 *
15258 * No protection against concurrent access is required - at
15259 * worst a fifo underrun happens which also sets this to false.
15260 */
15261 crtc->cpu_fifo_underrun_disabled = true;
15262 /*
15263 * We track the PCH trancoder underrun reporting state
15264 * within the crtc. With crtc for pipe A housing the underrun
15265 * reporting state for PCH transcoder A, crtc for pipe B housing
15266 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15267 * and marking underrun reporting as disabled for the non-existing
15268 * PCH transcoders B and C would prevent enabling the south
15269 * error interrupt (see cpt_can_enable_serr_int()).
15270 */
15271 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15272 crtc->pch_fifo_underrun_disabled = true;
15273 }
15274 }
15275
15276 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15277 {
15278 struct intel_connector *connector;
15279
15280 /* We need to check both for a crtc link (meaning that the
15281 * encoder is active and trying to read from a pipe) and the
15282 * pipe itself being active. */
15283 bool has_active_crtc = encoder->base.crtc &&
15284 to_intel_crtc(encoder->base.crtc)->active;
15285
15286 connector = intel_encoder_find_connector(encoder);
15287 if (connector && !has_active_crtc) {
15288 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15289 encoder->base.base.id,
15290 encoder->base.name);
15291
15292 /* Connector is active, but has no active pipe. This is
15293 * fallout from our resume register restoring. Disable
15294 * the encoder manually again. */
15295 if (encoder->base.crtc) {
15296 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15297
15298 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15299 encoder->base.base.id,
15300 encoder->base.name);
15301 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15302 if (encoder->post_disable)
15303 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15304 }
15305 encoder->base.crtc = NULL;
15306
15307 /* Inconsistent output/port/pipe state happens presumably due to
15308 * a bug in one of the get_hw_state functions. Or someplace else
15309 * in our code, like the register restore mess on resume. Clamp
15310 * things to off as a safer default. */
15311
15312 connector->base.dpms = DRM_MODE_DPMS_OFF;
15313 connector->base.encoder = NULL;
15314 }
15315 /* Enabled encoders without active connectors will be fixed in
15316 * the crtc fixup. */
15317 }
15318
15319 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15320 {
15321 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15322
15323 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15324 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15325 i915_disable_vga(dev_priv);
15326 }
15327 }
15328
15329 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15330 {
15331 /* This function can be called both from intel_modeset_setup_hw_state or
15332 * at a very early point in our resume sequence, where the power well
15333 * structures are not yet restored. Since this function is at a very
15334 * paranoid "someone might have enabled VGA while we were not looking"
15335 * level, just check if the power well is enabled instead of trying to
15336 * follow the "don't touch the power well if we don't need it" policy
15337 * the rest of the driver uses. */
15338 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15339 return;
15340
15341 i915_redisable_vga_power_on(dev_priv);
15342
15343 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15344 }
15345
15346 static bool primary_get_hw_state(struct intel_plane *plane)
15347 {
15348 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15349
15350 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15351 }
15352
15353 /* FIXME read out full plane state for all planes */
15354 static void readout_plane_state(struct intel_crtc *crtc)
15355 {
15356 struct drm_plane *primary = crtc->base.primary;
15357 struct intel_plane_state *plane_state =
15358 to_intel_plane_state(primary->state);
15359
15360 plane_state->base.visible = crtc->active &&
15361 primary_get_hw_state(to_intel_plane(primary));
15362
15363 if (plane_state->base.visible)
15364 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15365 }
15366
15367 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15368 {
15369 struct drm_i915_private *dev_priv = to_i915(dev);
15370 enum pipe pipe;
15371 struct intel_crtc *crtc;
15372 struct intel_encoder *encoder;
15373 struct intel_connector *connector;
15374 int i;
15375
15376 dev_priv->active_crtcs = 0;
15377
15378 for_each_intel_crtc(dev, crtc) {
15379 struct intel_crtc_state *crtc_state =
15380 to_intel_crtc_state(crtc->base.state);
15381
15382 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15383 memset(crtc_state, 0, sizeof(*crtc_state));
15384 crtc_state->base.crtc = &crtc->base;
15385
15386 crtc_state->base.active = crtc_state->base.enable =
15387 dev_priv->display.get_pipe_config(crtc, crtc_state);
15388
15389 crtc->base.enabled = crtc_state->base.enable;
15390 crtc->active = crtc_state->base.active;
15391
15392 if (crtc_state->base.active)
15393 dev_priv->active_crtcs |= 1 << crtc->pipe;
15394
15395 readout_plane_state(crtc);
15396
15397 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15398 crtc->base.base.id, crtc->base.name,
15399 enableddisabled(crtc_state->base.active));
15400 }
15401
15402 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15403 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15404
15405 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15406 &pll->state.hw_state);
15407 pll->state.crtc_mask = 0;
15408 for_each_intel_crtc(dev, crtc) {
15409 struct intel_crtc_state *crtc_state =
15410 to_intel_crtc_state(crtc->base.state);
15411
15412 if (crtc_state->base.active &&
15413 crtc_state->shared_dpll == pll)
15414 pll->state.crtc_mask |= 1 << crtc->pipe;
15415 }
15416 pll->active_mask = pll->state.crtc_mask;
15417
15418 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15419 pll->name, pll->state.crtc_mask, pll->on);
15420 }
15421
15422 for_each_intel_encoder(dev, encoder) {
15423 pipe = 0;
15424
15425 if (encoder->get_hw_state(encoder, &pipe)) {
15426 struct intel_crtc_state *crtc_state;
15427
15428 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15429 crtc_state = to_intel_crtc_state(crtc->base.state);
15430
15431 encoder->base.crtc = &crtc->base;
15432 crtc_state->output_types |= 1 << encoder->type;
15433 encoder->get_config(encoder, crtc_state);
15434 } else {
15435 encoder->base.crtc = NULL;
15436 }
15437
15438 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15439 encoder->base.base.id, encoder->base.name,
15440 enableddisabled(encoder->base.crtc),
15441 pipe_name(pipe));
15442 }
15443
15444 for_each_intel_connector(dev, connector) {
15445 if (connector->get_hw_state(connector)) {
15446 connector->base.dpms = DRM_MODE_DPMS_ON;
15447
15448 encoder = connector->encoder;
15449 connector->base.encoder = &encoder->base;
15450
15451 if (encoder->base.crtc &&
15452 encoder->base.crtc->state->active) {
15453 /*
15454 * This has to be done during hardware readout
15455 * because anything calling .crtc_disable may
15456 * rely on the connector_mask being accurate.
15457 */
15458 encoder->base.crtc->state->connector_mask |=
15459 1 << drm_connector_index(&connector->base);
15460 encoder->base.crtc->state->encoder_mask |=
15461 1 << drm_encoder_index(&encoder->base);
15462 }
15463
15464 } else {
15465 connector->base.dpms = DRM_MODE_DPMS_OFF;
15466 connector->base.encoder = NULL;
15467 }
15468 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15469 connector->base.base.id, connector->base.name,
15470 enableddisabled(connector->base.encoder));
15471 }
15472
15473 for_each_intel_crtc(dev, crtc) {
15474 struct intel_crtc_state *crtc_state =
15475 to_intel_crtc_state(crtc->base.state);
15476 int pixclk = 0;
15477
15478 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15479
15480 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15481 if (crtc_state->base.active) {
15482 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15483 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15484 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15485
15486 /*
15487 * The initial mode needs to be set in order to keep
15488 * the atomic core happy. It wants a valid mode if the
15489 * crtc's enabled, so we do the above call.
15490 *
15491 * But we don't set all the derived state fully, hence
15492 * set a flag to indicate that a full recalculation is
15493 * needed on the next commit.
15494 */
15495 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15496
15497 intel_crtc_compute_pixel_rate(crtc_state);
15498
15499 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15500 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15501 pixclk = crtc_state->pixel_rate;
15502 else
15503 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15504
15505 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15506 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15507 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15508
15509 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15510 update_scanline_offset(crtc);
15511 }
15512
15513 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15514
15515 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15516 }
15517 }
15518
15519 /* Scan out the current hw modeset state,
15520 * and sanitizes it to the current state
15521 */
15522 static void
15523 intel_modeset_setup_hw_state(struct drm_device *dev)
15524 {
15525 struct drm_i915_private *dev_priv = to_i915(dev);
15526 enum pipe pipe;
15527 struct intel_crtc *crtc;
15528 struct intel_encoder *encoder;
15529 int i;
15530
15531 intel_modeset_readout_hw_state(dev);
15532
15533 /* HW state is read out, now we need to sanitize this mess. */
15534 for_each_intel_encoder(dev, encoder) {
15535 intel_sanitize_encoder(encoder);
15536 }
15537
15538 for_each_pipe(dev_priv, pipe) {
15539 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15540
15541 intel_sanitize_crtc(crtc);
15542 intel_dump_pipe_config(crtc, crtc->config,
15543 "[setup_hw_state]");
15544 }
15545
15546 intel_modeset_update_connector_atomic_state(dev);
15547
15548 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15549 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15550
15551 if (!pll->on || pll->active_mask)
15552 continue;
15553
15554 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15555
15556 pll->funcs.disable(dev_priv, pll);
15557 pll->on = false;
15558 }
15559
15560 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15561 vlv_wm_get_hw_state(dev);
15562 else if (IS_GEN9(dev_priv))
15563 skl_wm_get_hw_state(dev);
15564 else if (HAS_PCH_SPLIT(dev_priv))
15565 ilk_wm_get_hw_state(dev);
15566
15567 for_each_intel_crtc(dev, crtc) {
15568 u64 put_domains;
15569
15570 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15571 if (WARN_ON(put_domains))
15572 modeset_put_power_domains(dev_priv, put_domains);
15573 }
15574 intel_display_set_init_power(dev_priv, false);
15575
15576 intel_fbc_init_pipe_state(dev_priv);
15577 }
15578
15579 void intel_display_resume(struct drm_device *dev)
15580 {
15581 struct drm_i915_private *dev_priv = to_i915(dev);
15582 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15583 struct drm_modeset_acquire_ctx ctx;
15584 int ret;
15585
15586 dev_priv->modeset_restore_state = NULL;
15587 if (state)
15588 state->acquire_ctx = &ctx;
15589
15590 /*
15591 * This is a cludge because with real atomic modeset mode_config.mutex
15592 * won't be taken. Unfortunately some probed state like
15593 * audio_codec_enable is still protected by mode_config.mutex, so lock
15594 * it here for now.
15595 */
15596 mutex_lock(&dev->mode_config.mutex);
15597 drm_modeset_acquire_init(&ctx, 0);
15598
15599 while (1) {
15600 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15601 if (ret != -EDEADLK)
15602 break;
15603
15604 drm_modeset_backoff(&ctx);
15605 }
15606
15607 if (!ret)
15608 ret = __intel_display_resume(dev, state);
15609
15610 drm_modeset_drop_locks(&ctx);
15611 drm_modeset_acquire_fini(&ctx);
15612 mutex_unlock(&dev->mode_config.mutex);
15613
15614 if (ret)
15615 DRM_ERROR("Restoring old state failed with %i\n", ret);
15616 if (state)
15617 drm_atomic_state_put(state);
15618 }
15619
15620 void intel_modeset_gem_init(struct drm_device *dev)
15621 {
15622 struct drm_i915_private *dev_priv = to_i915(dev);
15623
15624 intel_init_gt_powersave(dev_priv);
15625
15626 intel_modeset_init_hw(dev);
15627
15628 intel_setup_overlay(dev_priv);
15629 }
15630
15631 int intel_connector_register(struct drm_connector *connector)
15632 {
15633 struct intel_connector *intel_connector = to_intel_connector(connector);
15634 int ret;
15635
15636 ret = intel_backlight_device_register(intel_connector);
15637 if (ret)
15638 goto err;
15639
15640 return 0;
15641
15642 err:
15643 return ret;
15644 }
15645
15646 void intel_connector_unregister(struct drm_connector *connector)
15647 {
15648 struct intel_connector *intel_connector = to_intel_connector(connector);
15649
15650 intel_backlight_device_unregister(intel_connector);
15651 intel_panel_destroy_backlight(connector);
15652 }
15653
15654 void intel_modeset_cleanup(struct drm_device *dev)
15655 {
15656 struct drm_i915_private *dev_priv = to_i915(dev);
15657
15658 flush_work(&dev_priv->atomic_helper.free_work);
15659 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15660
15661 intel_disable_gt_powersave(dev_priv);
15662
15663 /*
15664 * Interrupts and polling as the first thing to avoid creating havoc.
15665 * Too much stuff here (turning of connectors, ...) would
15666 * experience fancy races otherwise.
15667 */
15668 intel_irq_uninstall(dev_priv);
15669
15670 /*
15671 * Due to the hpd irq storm handling the hotplug work can re-arm the
15672 * poll handlers. Hence disable polling after hpd handling is shut down.
15673 */
15674 drm_kms_helper_poll_fini(dev);
15675
15676 intel_unregister_dsm_handler();
15677
15678 intel_fbc_global_disable(dev_priv);
15679
15680 /* flush any delayed tasks or pending work */
15681 flush_scheduled_work();
15682
15683 drm_mode_config_cleanup(dev);
15684
15685 intel_cleanup_overlay(dev_priv);
15686
15687 intel_cleanup_gt_powersave(dev_priv);
15688
15689 intel_teardown_gmbus(dev_priv);
15690 }
15691
15692 void intel_connector_attach_encoder(struct intel_connector *connector,
15693 struct intel_encoder *encoder)
15694 {
15695 connector->encoder = encoder;
15696 drm_mode_connector_attach_encoder(&connector->base,
15697 &encoder->base);
15698 }
15699
15700 /*
15701 * set vga decode state - true == enable VGA decode
15702 */
15703 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15704 {
15705 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15706 u16 gmch_ctrl;
15707
15708 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15709 DRM_ERROR("failed to read control word\n");
15710 return -EIO;
15711 }
15712
15713 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15714 return 0;
15715
15716 if (state)
15717 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15718 else
15719 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15720
15721 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15722 DRM_ERROR("failed to write control word\n");
15723 return -EIO;
15724 }
15725
15726 return 0;
15727 }
15728
15729 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15730
15731 struct intel_display_error_state {
15732
15733 u32 power_well_driver;
15734
15735 int num_transcoders;
15736
15737 struct intel_cursor_error_state {
15738 u32 control;
15739 u32 position;
15740 u32 base;
15741 u32 size;
15742 } cursor[I915_MAX_PIPES];
15743
15744 struct intel_pipe_error_state {
15745 bool power_domain_on;
15746 u32 source;
15747 u32 stat;
15748 } pipe[I915_MAX_PIPES];
15749
15750 struct intel_plane_error_state {
15751 u32 control;
15752 u32 stride;
15753 u32 size;
15754 u32 pos;
15755 u32 addr;
15756 u32 surface;
15757 u32 tile_offset;
15758 } plane[I915_MAX_PIPES];
15759
15760 struct intel_transcoder_error_state {
15761 bool power_domain_on;
15762 enum transcoder cpu_transcoder;
15763
15764 u32 conf;
15765
15766 u32 htotal;
15767 u32 hblank;
15768 u32 hsync;
15769 u32 vtotal;
15770 u32 vblank;
15771 u32 vsync;
15772 } transcoder[4];
15773 };
15774
15775 struct intel_display_error_state *
15776 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15777 {
15778 struct intel_display_error_state *error;
15779 int transcoders[] = {
15780 TRANSCODER_A,
15781 TRANSCODER_B,
15782 TRANSCODER_C,
15783 TRANSCODER_EDP,
15784 };
15785 int i;
15786
15787 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15788 return NULL;
15789
15790 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15791 if (error == NULL)
15792 return NULL;
15793
15794 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15795 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15796
15797 for_each_pipe(dev_priv, i) {
15798 error->pipe[i].power_domain_on =
15799 __intel_display_power_is_enabled(dev_priv,
15800 POWER_DOMAIN_PIPE(i));
15801 if (!error->pipe[i].power_domain_on)
15802 continue;
15803
15804 error->cursor[i].control = I915_READ(CURCNTR(i));
15805 error->cursor[i].position = I915_READ(CURPOS(i));
15806 error->cursor[i].base = I915_READ(CURBASE(i));
15807
15808 error->plane[i].control = I915_READ(DSPCNTR(i));
15809 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15810 if (INTEL_GEN(dev_priv) <= 3) {
15811 error->plane[i].size = I915_READ(DSPSIZE(i));
15812 error->plane[i].pos = I915_READ(DSPPOS(i));
15813 }
15814 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15815 error->plane[i].addr = I915_READ(DSPADDR(i));
15816 if (INTEL_GEN(dev_priv) >= 4) {
15817 error->plane[i].surface = I915_READ(DSPSURF(i));
15818 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15819 }
15820
15821 error->pipe[i].source = I915_READ(PIPESRC(i));
15822
15823 if (HAS_GMCH_DISPLAY(dev_priv))
15824 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15825 }
15826
15827 /* Note: this does not include DSI transcoders. */
15828 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15829 if (HAS_DDI(dev_priv))
15830 error->num_transcoders++; /* Account for eDP. */
15831
15832 for (i = 0; i < error->num_transcoders; i++) {
15833 enum transcoder cpu_transcoder = transcoders[i];
15834
15835 error->transcoder[i].power_domain_on =
15836 __intel_display_power_is_enabled(dev_priv,
15837 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15838 if (!error->transcoder[i].power_domain_on)
15839 continue;
15840
15841 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15842
15843 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15844 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15845 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15846 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15847 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15848 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15849 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15850 }
15851
15852 return error;
15853 }
15854
15855 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15856
15857 void
15858 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15859 struct drm_i915_private *dev_priv,
15860 struct intel_display_error_state *error)
15861 {
15862 int i;
15863
15864 if (!error)
15865 return;
15866
15867 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15868 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15869 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15870 error->power_well_driver);
15871 for_each_pipe(dev_priv, i) {
15872 err_printf(m, "Pipe [%d]:\n", i);
15873 err_printf(m, " Power: %s\n",
15874 onoff(error->pipe[i].power_domain_on));
15875 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15876 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15877
15878 err_printf(m, "Plane [%d]:\n", i);
15879 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15880 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15881 if (INTEL_GEN(dev_priv) <= 3) {
15882 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15883 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15884 }
15885 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15886 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15887 if (INTEL_GEN(dev_priv) >= 4) {
15888 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15889 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15890 }
15891
15892 err_printf(m, "Cursor [%d]:\n", i);
15893 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15894 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15895 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15896 }
15897
15898 for (i = 0; i < error->num_transcoders; i++) {
15899 err_printf(m, "CPU transcoder: %s\n",
15900 transcoder_name(error->transcoder[i].cpu_transcoder));
15901 err_printf(m, " Power: %s\n",
15902 onoff(error->transcoder[i].power_domain_on));
15903 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15904 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15905 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15906 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15907 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15908 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15909 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15910 }
15911 }
15912
15913 #endif
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