]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'drm-intel-next-2014-04-16' of git://anongit.freedesktop.org/drm-intel...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
46
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
51
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54 static int intel_framebuffer_init(struct drm_device *dev,
55 struct intel_framebuffer *ifb,
56 struct drm_mode_fb_cmd2 *mode_cmd,
57 struct drm_i915_gem_object *obj);
58
59 typedef struct {
60 int min, max;
61 } intel_range_t;
62
63 typedef struct {
64 int dot_limit;
65 int p2_slow, p2_fast;
66 } intel_p2_t;
67
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70 intel_range_t dot, vco, n, m, m1, m2, p, p1;
71 intel_p2_t p2;
72 };
73
74 int
75 intel_pch_rawclk(struct drm_device *dev)
76 {
77 struct drm_i915_private *dev_priv = dev->dev_private;
78
79 WARN_ON(!HAS_PCH_SPLIT(dev));
80
81 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
82 }
83
84 static inline u32 /* units of 100MHz */
85 intel_fdi_link_freq(struct drm_device *dev)
86 {
87 if (IS_GEN5(dev)) {
88 struct drm_i915_private *dev_priv = dev->dev_private;
89 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
90 } else
91 return 27;
92 }
93
94 static const intel_limit_t intel_limits_i8xx_dac = {
95 .dot = { .min = 25000, .max = 350000 },
96 .vco = { .min = 908000, .max = 1512000 },
97 .n = { .min = 2, .max = 16 },
98 .m = { .min = 96, .max = 140 },
99 .m1 = { .min = 18, .max = 26 },
100 .m2 = { .min = 6, .max = 16 },
101 .p = { .min = 4, .max = 128 },
102 .p1 = { .min = 2, .max = 33 },
103 .p2 = { .dot_limit = 165000,
104 .p2_slow = 4, .p2_fast = 2 },
105 };
106
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 908000, .max = 1512000 },
110 .n = { .min = 2, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 4 },
118 };
119
120 static const intel_limit_t intel_limits_i8xx_lvds = {
121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 908000, .max = 1512000 },
123 .n = { .min = 2, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
131 };
132
133 static const intel_limit_t intel_limits_i9xx_sdvo = {
134 .dot = { .min = 20000, .max = 400000 },
135 .vco = { .min = 1400000, .max = 2800000 },
136 .n = { .min = 1, .max = 6 },
137 .m = { .min = 70, .max = 120 },
138 .m1 = { .min = 8, .max = 18 },
139 .m2 = { .min = 3, .max = 7 },
140 .p = { .min = 5, .max = 80 },
141 .p1 = { .min = 1, .max = 8 },
142 .p2 = { .dot_limit = 200000,
143 .p2_slow = 10, .p2_fast = 5 },
144 };
145
146 static const intel_limit_t intel_limits_i9xx_lvds = {
147 .dot = { .min = 20000, .max = 400000 },
148 .vco = { .min = 1400000, .max = 2800000 },
149 .n = { .min = 1, .max = 6 },
150 .m = { .min = 70, .max = 120 },
151 .m1 = { .min = 8, .max = 18 },
152 .m2 = { .min = 3, .max = 7 },
153 .p = { .min = 7, .max = 98 },
154 .p1 = { .min = 1, .max = 8 },
155 .p2 = { .dot_limit = 112000,
156 .p2_slow = 14, .p2_fast = 7 },
157 };
158
159
160 static const intel_limit_t intel_limits_g4x_sdvo = {
161 .dot = { .min = 25000, .max = 270000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 17, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 10, .max = 30 },
168 .p1 = { .min = 1, .max = 3},
169 .p2 = { .dot_limit = 270000,
170 .p2_slow = 10,
171 .p2_fast = 10
172 },
173 };
174
175 static const intel_limit_t intel_limits_g4x_hdmi = {
176 .dot = { .min = 22000, .max = 400000 },
177 .vco = { .min = 1750000, .max = 3500000},
178 .n = { .min = 1, .max = 4 },
179 .m = { .min = 104, .max = 138 },
180 .m1 = { .min = 16, .max = 23 },
181 .m2 = { .min = 5, .max = 11 },
182 .p = { .min = 5, .max = 80 },
183 .p1 = { .min = 1, .max = 8},
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 10, .p2_fast = 5 },
186 };
187
188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
189 .dot = { .min = 20000, .max = 115000 },
190 .vco = { .min = 1750000, .max = 3500000 },
191 .n = { .min = 1, .max = 3 },
192 .m = { .min = 104, .max = 138 },
193 .m1 = { .min = 17, .max = 23 },
194 .m2 = { .min = 5, .max = 11 },
195 .p = { .min = 28, .max = 112 },
196 .p1 = { .min = 2, .max = 8 },
197 .p2 = { .dot_limit = 0,
198 .p2_slow = 14, .p2_fast = 14
199 },
200 };
201
202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
203 .dot = { .min = 80000, .max = 224000 },
204 .vco = { .min = 1750000, .max = 3500000 },
205 .n = { .min = 1, .max = 3 },
206 .m = { .min = 104, .max = 138 },
207 .m1 = { .min = 17, .max = 23 },
208 .m2 = { .min = 5, .max = 11 },
209 .p = { .min = 14, .max = 42 },
210 .p1 = { .min = 2, .max = 6 },
211 .p2 = { .dot_limit = 0,
212 .p2_slow = 7, .p2_fast = 7
213 },
214 };
215
216 static const intel_limit_t intel_limits_pineview_sdvo = {
217 .dot = { .min = 20000, .max = 400000},
218 .vco = { .min = 1700000, .max = 3500000 },
219 /* Pineview's Ncounter is a ring counter */
220 .n = { .min = 3, .max = 6 },
221 .m = { .min = 2, .max = 256 },
222 /* Pineview only has one combined m divider, which we treat as m2. */
223 .m1 = { .min = 0, .max = 0 },
224 .m2 = { .min = 0, .max = 254 },
225 .p = { .min = 5, .max = 80 },
226 .p1 = { .min = 1, .max = 8 },
227 .p2 = { .dot_limit = 200000,
228 .p2_slow = 10, .p2_fast = 5 },
229 };
230
231 static const intel_limit_t intel_limits_pineview_lvds = {
232 .dot = { .min = 20000, .max = 400000 },
233 .vco = { .min = 1700000, .max = 3500000 },
234 .n = { .min = 3, .max = 6 },
235 .m = { .min = 2, .max = 256 },
236 .m1 = { .min = 0, .max = 0 },
237 .m2 = { .min = 0, .max = 254 },
238 .p = { .min = 7, .max = 112 },
239 .p1 = { .min = 1, .max = 8 },
240 .p2 = { .dot_limit = 112000,
241 .p2_slow = 14, .p2_fast = 14 },
242 };
243
244 /* Ironlake / Sandybridge
245 *
246 * We calculate clock using (register_value + 2) for N/M1/M2, so here
247 * the range value for them is (actual_value - 2).
248 */
249 static const intel_limit_t intel_limits_ironlake_dac = {
250 .dot = { .min = 25000, .max = 350000 },
251 .vco = { .min = 1760000, .max = 3510000 },
252 .n = { .min = 1, .max = 5 },
253 .m = { .min = 79, .max = 127 },
254 .m1 = { .min = 12, .max = 22 },
255 .m2 = { .min = 5, .max = 9 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 225000,
259 .p2_slow = 10, .p2_fast = 5 },
260 };
261
262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 1760000, .max = 3510000 },
265 .n = { .min = 1, .max = 3 },
266 .m = { .min = 79, .max = 118 },
267 .m1 = { .min = 12, .max = 22 },
268 .m2 = { .min = 5, .max = 9 },
269 .p = { .min = 28, .max = 112 },
270 .p1 = { .min = 2, .max = 8 },
271 .p2 = { .dot_limit = 225000,
272 .p2_slow = 14, .p2_fast = 14 },
273 };
274
275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 1760000, .max = 3510000 },
278 .n = { .min = 1, .max = 3 },
279 .m = { .min = 79, .max = 127 },
280 .m1 = { .min = 12, .max = 22 },
281 .m2 = { .min = 5, .max = 9 },
282 .p = { .min = 14, .max = 56 },
283 .p1 = { .min = 2, .max = 8 },
284 .p2 = { .dot_limit = 225000,
285 .p2_slow = 7, .p2_fast = 7 },
286 };
287
288 /* LVDS 100mhz refclk limits. */
289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 1760000, .max = 3510000 },
292 .n = { .min = 1, .max = 2 },
293 .m = { .min = 79, .max = 126 },
294 .m1 = { .min = 12, .max = 22 },
295 .m2 = { .min = 5, .max = 9 },
296 .p = { .min = 28, .max = 112 },
297 .p1 = { .min = 2, .max = 8 },
298 .p2 = { .dot_limit = 225000,
299 .p2_slow = 14, .p2_fast = 14 },
300 };
301
302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 126 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 42 },
310 .p1 = { .min = 2, .max = 6 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
313 };
314
315 static const intel_limit_t intel_limits_vlv = {
316 /*
317 * These are the data rate limits (measured in fast clocks)
318 * since those are the strictest limits we have. The fast
319 * clock and actual rate limits are more relaxed, so checking
320 * them would make no difference.
321 */
322 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
323 .vco = { .min = 4000000, .max = 6000000 },
324 .n = { .min = 1, .max = 7 },
325 .m1 = { .min = 2, .max = 3 },
326 .m2 = { .min = 11, .max = 156 },
327 .p1 = { .min = 2, .max = 3 },
328 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
329 };
330
331 static void vlv_clock(int refclk, intel_clock_t *clock)
332 {
333 clock->m = clock->m1 * clock->m2;
334 clock->p = clock->p1 * clock->p2;
335 if (WARN_ON(clock->n == 0 || clock->p == 0))
336 return;
337 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
338 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
339 }
340
341 /**
342 * Returns whether any output on the specified pipe is of the specified type
343 */
344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
345 {
346 struct drm_device *dev = crtc->dev;
347 struct intel_encoder *encoder;
348
349 for_each_encoder_on_crtc(dev, crtc, encoder)
350 if (encoder->type == type)
351 return true;
352
353 return false;
354 }
355
356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
357 int refclk)
358 {
359 struct drm_device *dev = crtc->dev;
360 const intel_limit_t *limit;
361
362 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
363 if (intel_is_dual_link_lvds(dev)) {
364 if (refclk == 100000)
365 limit = &intel_limits_ironlake_dual_lvds_100m;
366 else
367 limit = &intel_limits_ironlake_dual_lvds;
368 } else {
369 if (refclk == 100000)
370 limit = &intel_limits_ironlake_single_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_single_lvds;
373 }
374 } else
375 limit = &intel_limits_ironlake_dac;
376
377 return limit;
378 }
379
380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
381 {
382 struct drm_device *dev = crtc->dev;
383 const intel_limit_t *limit;
384
385 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
386 if (intel_is_dual_link_lvds(dev))
387 limit = &intel_limits_g4x_dual_channel_lvds;
388 else
389 limit = &intel_limits_g4x_single_channel_lvds;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
391 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
392 limit = &intel_limits_g4x_hdmi;
393 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
394 limit = &intel_limits_g4x_sdvo;
395 } else /* The option is for other outputs */
396 limit = &intel_limits_i9xx_sdvo;
397
398 return limit;
399 }
400
401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
402 {
403 struct drm_device *dev = crtc->dev;
404 const intel_limit_t *limit;
405
406 if (HAS_PCH_SPLIT(dev))
407 limit = intel_ironlake_limit(crtc, refclk);
408 else if (IS_G4X(dev)) {
409 limit = intel_g4x_limit(crtc);
410 } else if (IS_PINEVIEW(dev)) {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
412 limit = &intel_limits_pineview_lvds;
413 else
414 limit = &intel_limits_pineview_sdvo;
415 } else if (IS_VALLEYVIEW(dev)) {
416 limit = &intel_limits_vlv;
417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
420 else
421 limit = &intel_limits_i9xx_sdvo;
422 } else {
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
424 limit = &intel_limits_i8xx_lvds;
425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
426 limit = &intel_limits_i8xx_dvo;
427 else
428 limit = &intel_limits_i8xx_dac;
429 }
430 return limit;
431 }
432
433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
434 static void pineview_clock(int refclk, intel_clock_t *clock)
435 {
436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 if (WARN_ON(clock->n == 0 || clock->p == 0))
439 return;
440 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
441 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
442 }
443
444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
445 {
446 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
447 }
448
449 static void i9xx_clock(int refclk, intel_clock_t *clock)
450 {
451 clock->m = i9xx_dpll_compute_m(clock);
452 clock->p = clock->p1 * clock->p2;
453 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
454 return;
455 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
456 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
457 }
458
459 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
460 /**
461 * Returns whether the given set of divisors are valid for a given refclk with
462 * the given connectors.
463 */
464
465 static bool intel_PLL_is_valid(struct drm_device *dev,
466 const intel_limit_t *limit,
467 const intel_clock_t *clock)
468 {
469 if (clock->n < limit->n.min || limit->n.max < clock->n)
470 INTELPllInvalid("n out of range\n");
471 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
472 INTELPllInvalid("p1 out of range\n");
473 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
474 INTELPllInvalid("m2 out of range\n");
475 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
476 INTELPllInvalid("m1 out of range\n");
477
478 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
479 if (clock->m1 <= clock->m2)
480 INTELPllInvalid("m1 <= m2\n");
481
482 if (!IS_VALLEYVIEW(dev)) {
483 if (clock->p < limit->p.min || limit->p.max < clock->p)
484 INTELPllInvalid("p out of range\n");
485 if (clock->m < limit->m.min || limit->m.max < clock->m)
486 INTELPllInvalid("m out of range\n");
487 }
488
489 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
490 INTELPllInvalid("vco out of range\n");
491 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
492 * connector, etc., rather than just a single range.
493 */
494 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
495 INTELPllInvalid("dot out of range\n");
496
497 return true;
498 }
499
500 static bool
501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
502 int target, int refclk, intel_clock_t *match_clock,
503 intel_clock_t *best_clock)
504 {
505 struct drm_device *dev = crtc->dev;
506 intel_clock_t clock;
507 int err = target;
508
509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
510 /*
511 * For LVDS just rely on its current settings for dual-channel.
512 * We haven't figured out how to reliably set up different
513 * single/dual channel state, if we even can.
514 */
515 if (intel_is_dual_link_lvds(dev))
516 clock.p2 = limit->p2.p2_fast;
517 else
518 clock.p2 = limit->p2.p2_slow;
519 } else {
520 if (target < limit->p2.dot_limit)
521 clock.p2 = limit->p2.p2_slow;
522 else
523 clock.p2 = limit->p2.p2_fast;
524 }
525
526 memset(best_clock, 0, sizeof(*best_clock));
527
528 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
529 clock.m1++) {
530 for (clock.m2 = limit->m2.min;
531 clock.m2 <= limit->m2.max; clock.m2++) {
532 if (clock.m2 >= clock.m1)
533 break;
534 for (clock.n = limit->n.min;
535 clock.n <= limit->n.max; clock.n++) {
536 for (clock.p1 = limit->p1.min;
537 clock.p1 <= limit->p1.max; clock.p1++) {
538 int this_err;
539
540 i9xx_clock(refclk, &clock);
541 if (!intel_PLL_is_valid(dev, limit,
542 &clock))
543 continue;
544 if (match_clock &&
545 clock.p != match_clock->p)
546 continue;
547
548 this_err = abs(clock.dot - target);
549 if (this_err < err) {
550 *best_clock = clock;
551 err = this_err;
552 }
553 }
554 }
555 }
556 }
557
558 return (err != target);
559 }
560
561 static bool
562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
563 int target, int refclk, intel_clock_t *match_clock,
564 intel_clock_t *best_clock)
565 {
566 struct drm_device *dev = crtc->dev;
567 intel_clock_t clock;
568 int err = target;
569
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
571 /*
572 * For LVDS just rely on its current settings for dual-channel.
573 * We haven't figured out how to reliably set up different
574 * single/dual channel state, if we even can.
575 */
576 if (intel_is_dual_link_lvds(dev))
577 clock.p2 = limit->p2.p2_fast;
578 else
579 clock.p2 = limit->p2.p2_slow;
580 } else {
581 if (target < limit->p2.dot_limit)
582 clock.p2 = limit->p2.p2_slow;
583 else
584 clock.p2 = limit->p2.p2_fast;
585 }
586
587 memset(best_clock, 0, sizeof(*best_clock));
588
589 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
590 clock.m1++) {
591 for (clock.m2 = limit->m2.min;
592 clock.m2 <= limit->m2.max; clock.m2++) {
593 for (clock.n = limit->n.min;
594 clock.n <= limit->n.max; clock.n++) {
595 for (clock.p1 = limit->p1.min;
596 clock.p1 <= limit->p1.max; clock.p1++) {
597 int this_err;
598
599 pineview_clock(refclk, &clock);
600 if (!intel_PLL_is_valid(dev, limit,
601 &clock))
602 continue;
603 if (match_clock &&
604 clock.p != match_clock->p)
605 continue;
606
607 this_err = abs(clock.dot - target);
608 if (this_err < err) {
609 *best_clock = clock;
610 err = this_err;
611 }
612 }
613 }
614 }
615 }
616
617 return (err != target);
618 }
619
620 static bool
621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
622 int target, int refclk, intel_clock_t *match_clock,
623 intel_clock_t *best_clock)
624 {
625 struct drm_device *dev = crtc->dev;
626 intel_clock_t clock;
627 int max_n;
628 bool found;
629 /* approximately equals target * 0.00585 */
630 int err_most = (target >> 8) + (target >> 9);
631 found = false;
632
633 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
634 if (intel_is_dual_link_lvds(dev))
635 clock.p2 = limit->p2.p2_fast;
636 else
637 clock.p2 = limit->p2.p2_slow;
638 } else {
639 if (target < limit->p2.dot_limit)
640 clock.p2 = limit->p2.p2_slow;
641 else
642 clock.p2 = limit->p2.p2_fast;
643 }
644
645 memset(best_clock, 0, sizeof(*best_clock));
646 max_n = limit->n.max;
647 /* based on hardware requirement, prefer smaller n to precision */
648 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
649 /* based on hardware requirement, prefere larger m1,m2 */
650 for (clock.m1 = limit->m1.max;
651 clock.m1 >= limit->m1.min; clock.m1--) {
652 for (clock.m2 = limit->m2.max;
653 clock.m2 >= limit->m2.min; clock.m2--) {
654 for (clock.p1 = limit->p1.max;
655 clock.p1 >= limit->p1.min; clock.p1--) {
656 int this_err;
657
658 i9xx_clock(refclk, &clock);
659 if (!intel_PLL_is_valid(dev, limit,
660 &clock))
661 continue;
662
663 this_err = abs(clock.dot - target);
664 if (this_err < err_most) {
665 *best_clock = clock;
666 err_most = this_err;
667 max_n = clock.n;
668 found = true;
669 }
670 }
671 }
672 }
673 }
674 return found;
675 }
676
677 static bool
678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *match_clock,
680 intel_clock_t *best_clock)
681 {
682 struct drm_device *dev = crtc->dev;
683 intel_clock_t clock;
684 unsigned int bestppm = 1000000;
685 /* min update 19.2 MHz */
686 int max_n = min(limit->n.max, refclk / 19200);
687 bool found = false;
688
689 target *= 5; /* fast clock */
690
691 memset(best_clock, 0, sizeof(*best_clock));
692
693 /* based on hardware requirement, prefer smaller n to precision */
694 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
695 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
696 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
697 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
698 clock.p = clock.p1 * clock.p2;
699 /* based on hardware requirement, prefer bigger m1,m2 values */
700 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
701 unsigned int ppm, diff;
702
703 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
704 refclk * clock.m1);
705
706 vlv_clock(refclk, &clock);
707
708 if (!intel_PLL_is_valid(dev, limit,
709 &clock))
710 continue;
711
712 diff = abs(clock.dot - target);
713 ppm = div_u64(1000000ULL * diff, target);
714
715 if (ppm < 100 && clock.p > best_clock->p) {
716 bestppm = 0;
717 *best_clock = clock;
718 found = true;
719 }
720
721 if (bestppm >= 10 && ppm < bestppm - 10) {
722 bestppm = ppm;
723 *best_clock = clock;
724 found = true;
725 }
726 }
727 }
728 }
729 }
730
731 return found;
732 }
733
734 bool intel_crtc_active(struct drm_crtc *crtc)
735 {
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
738 /* Be paranoid as we can arrive here with only partial
739 * state retrieved from the hardware during setup.
740 *
741 * We can ditch the adjusted_mode.crtc_clock check as soon
742 * as Haswell has gained clock readout/fastboot support.
743 *
744 * We can ditch the crtc->primary->fb check as soon as we can
745 * properly reconstruct framebuffers.
746 */
747 return intel_crtc->active && crtc->primary->fb &&
748 intel_crtc->config.adjusted_mode.crtc_clock;
749 }
750
751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
752 enum pipe pipe)
753 {
754 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756
757 return intel_crtc->config.cpu_transcoder;
758 }
759
760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
761 {
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
764
765 frame = I915_READ(frame_reg);
766
767 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
768 WARN(1, "vblank wait timed out\n");
769 }
770
771 /**
772 * intel_wait_for_vblank - wait for vblank on a given pipe
773 * @dev: drm device
774 * @pipe: pipe to wait for
775 *
776 * Wait for vblank to occur on a given pipe. Needed for various bits of
777 * mode setting code.
778 */
779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
780 {
781 struct drm_i915_private *dev_priv = dev->dev_private;
782 int pipestat_reg = PIPESTAT(pipe);
783
784 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
785 g4x_wait_for_vblank(dev, pipe);
786 return;
787 }
788
789 /* Clear existing vblank status. Note this will clear any other
790 * sticky status fields as well.
791 *
792 * This races with i915_driver_irq_handler() with the result
793 * that either function could miss a vblank event. Here it is not
794 * fatal, as we will either wait upon the next vblank interrupt or
795 * timeout. Generally speaking intel_wait_for_vblank() is only
796 * called during modeset at which time the GPU should be idle and
797 * should *not* be performing page flips and thus not waiting on
798 * vblanks...
799 * Currently, the result of us stealing a vblank from the irq
800 * handler is that a single frame will be skipped during swapbuffers.
801 */
802 I915_WRITE(pipestat_reg,
803 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
804
805 /* Wait for vblank interrupt bit to set */
806 if (wait_for(I915_READ(pipestat_reg) &
807 PIPE_VBLANK_INTERRUPT_STATUS,
808 50))
809 DRM_DEBUG_KMS("vblank wait timed out\n");
810 }
811
812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
813 {
814 struct drm_i915_private *dev_priv = dev->dev_private;
815 u32 reg = PIPEDSL(pipe);
816 u32 line1, line2;
817 u32 line_mask;
818
819 if (IS_GEN2(dev))
820 line_mask = DSL_LINEMASK_GEN2;
821 else
822 line_mask = DSL_LINEMASK_GEN3;
823
824 line1 = I915_READ(reg) & line_mask;
825 mdelay(5);
826 line2 = I915_READ(reg) & line_mask;
827
828 return line1 == line2;
829 }
830
831 /*
832 * intel_wait_for_pipe_off - wait for pipe to turn off
833 * @dev: drm device
834 * @pipe: pipe to wait for
835 *
836 * After disabling a pipe, we can't wait for vblank in the usual way,
837 * spinning on the vblank interrupt status bit, since we won't actually
838 * see an interrupt when the pipe is disabled.
839 *
840 * On Gen4 and above:
841 * wait for the pipe register state bit to turn off
842 *
843 * Otherwise:
844 * wait for the display line value to settle (it usually
845 * ends up stopping at the start of the next frame).
846 *
847 */
848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
849 {
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
852 pipe);
853
854 if (INTEL_INFO(dev)->gen >= 4) {
855 int reg = PIPECONF(cpu_transcoder);
856
857 /* Wait for the Pipe State to go off */
858 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
859 100))
860 WARN(1, "pipe_off wait timed out\n");
861 } else {
862 /* Wait for the display line to settle */
863 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
864 WARN(1, "pipe_off wait timed out\n");
865 }
866 }
867
868 /*
869 * ibx_digital_port_connected - is the specified port connected?
870 * @dev_priv: i915 private structure
871 * @port: the port to test
872 *
873 * Returns true if @port is connected, false otherwise.
874 */
875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
876 struct intel_digital_port *port)
877 {
878 u32 bit;
879
880 if (HAS_PCH_IBX(dev_priv->dev)) {
881 switch(port->port) {
882 case PORT_B:
883 bit = SDE_PORTB_HOTPLUG;
884 break;
885 case PORT_C:
886 bit = SDE_PORTC_HOTPLUG;
887 break;
888 case PORT_D:
889 bit = SDE_PORTD_HOTPLUG;
890 break;
891 default:
892 return true;
893 }
894 } else {
895 switch(port->port) {
896 case PORT_B:
897 bit = SDE_PORTB_HOTPLUG_CPT;
898 break;
899 case PORT_C:
900 bit = SDE_PORTC_HOTPLUG_CPT;
901 break;
902 case PORT_D:
903 bit = SDE_PORTD_HOTPLUG_CPT;
904 break;
905 default:
906 return true;
907 }
908 }
909
910 return I915_READ(SDEISR) & bit;
911 }
912
913 static const char *state_string(bool enabled)
914 {
915 return enabled ? "on" : "off";
916 }
917
918 /* Only for pre-ILK configs */
919 void assert_pll(struct drm_i915_private *dev_priv,
920 enum pipe pipe, bool state)
921 {
922 int reg;
923 u32 val;
924 bool cur_state;
925
926 reg = DPLL(pipe);
927 val = I915_READ(reg);
928 cur_state = !!(val & DPLL_VCO_ENABLE);
929 WARN(cur_state != state,
930 "PLL state assertion failure (expected %s, current %s)\n",
931 state_string(state), state_string(cur_state));
932 }
933
934 /* XXX: the dsi pll is shared between MIPI DSI ports */
935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
936 {
937 u32 val;
938 bool cur_state;
939
940 mutex_lock(&dev_priv->dpio_lock);
941 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
942 mutex_unlock(&dev_priv->dpio_lock);
943
944 cur_state = val & DSI_PLL_VCO_EN;
945 WARN(cur_state != state,
946 "DSI PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948 }
949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
951
952 struct intel_shared_dpll *
953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
954 {
955 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
956
957 if (crtc->config.shared_dpll < 0)
958 return NULL;
959
960 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
961 }
962
963 /* For ILK+ */
964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
965 struct intel_shared_dpll *pll,
966 bool state)
967 {
968 bool cur_state;
969 struct intel_dpll_hw_state hw_state;
970
971 if (HAS_PCH_LPT(dev_priv->dev)) {
972 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
973 return;
974 }
975
976 if (WARN (!pll,
977 "asserting DPLL %s with no DPLL\n", state_string(state)))
978 return;
979
980 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
981 WARN(cur_state != state,
982 "%s assertion failure (expected %s, current %s)\n",
983 pll->name, state_string(state), state_string(cur_state));
984 }
985
986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
987 enum pipe pipe, bool state)
988 {
989 int reg;
990 u32 val;
991 bool cur_state;
992 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
993 pipe);
994
995 if (HAS_DDI(dev_priv->dev)) {
996 /* DDI does not have a specific FDI_TX register */
997 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
998 val = I915_READ(reg);
999 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1000 } else {
1001 reg = FDI_TX_CTL(pipe);
1002 val = I915_READ(reg);
1003 cur_state = !!(val & FDI_TX_ENABLE);
1004 }
1005 WARN(cur_state != state,
1006 "FDI TX state assertion failure (expected %s, current %s)\n",
1007 state_string(state), state_string(cur_state));
1008 }
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1011
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
1014 {
1015 int reg;
1016 u32 val;
1017 bool cur_state;
1018
1019 reg = FDI_RX_CTL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & FDI_RX_ENABLE);
1022 WARN(cur_state != state,
1023 "FDI RX state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1025 }
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1028
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030 enum pipe pipe)
1031 {
1032 int reg;
1033 u32 val;
1034
1035 /* ILK FDI PLL is always enabled */
1036 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1037 return;
1038
1039 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040 if (HAS_DDI(dev_priv->dev))
1041 return;
1042
1043 reg = FDI_TX_CTL(pipe);
1044 val = I915_READ(reg);
1045 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 }
1047
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049 enum pipe pipe, bool state)
1050 {
1051 int reg;
1052 u32 val;
1053 bool cur_state;
1054
1055 reg = FDI_RX_CTL(pipe);
1056 val = I915_READ(reg);
1057 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058 WARN(cur_state != state,
1059 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060 state_string(state), state_string(cur_state));
1061 }
1062
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1064 enum pipe pipe)
1065 {
1066 int pp_reg, lvds_reg;
1067 u32 val;
1068 enum pipe panel_pipe = PIPE_A;
1069 bool locked = true;
1070
1071 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072 pp_reg = PCH_PP_CONTROL;
1073 lvds_reg = PCH_LVDS;
1074 } else {
1075 pp_reg = PP_CONTROL;
1076 lvds_reg = LVDS;
1077 }
1078
1079 val = I915_READ(pp_reg);
1080 if (!(val & PANEL_POWER_ON) ||
1081 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1082 locked = false;
1083
1084 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085 panel_pipe = PIPE_B;
1086
1087 WARN(panel_pipe == pipe && locked,
1088 "panel assertion failure, pipe %c regs locked\n",
1089 pipe_name(pipe));
1090 }
1091
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093 enum pipe pipe, bool state)
1094 {
1095 struct drm_device *dev = dev_priv->dev;
1096 bool cur_state;
1097
1098 if (IS_845G(dev) || IS_I865G(dev))
1099 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100 else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1102 else
1103 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1104
1105 WARN(cur_state != state,
1106 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107 pipe_name(pipe), state_string(state), state_string(cur_state));
1108 }
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1111
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119 pipe);
1120
1121 /* if we need the pipe A quirk it must be always on */
1122 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1123 state = true;
1124
1125 if (!intel_display_power_enabled(dev_priv,
1126 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1127 cur_state = false;
1128 } else {
1129 reg = PIPECONF(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & PIPECONF_ENABLE);
1132 }
1133
1134 WARN(cur_state != state,
1135 "pipe %c assertion failure (expected %s, current %s)\n",
1136 pipe_name(pipe), state_string(state), state_string(cur_state));
1137 }
1138
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140 enum plane plane, bool state)
1141 {
1142 int reg;
1143 u32 val;
1144 bool cur_state;
1145
1146 reg = DSPCNTR(plane);
1147 val = I915_READ(reg);
1148 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149 WARN(cur_state != state,
1150 "plane %c assertion failure (expected %s, current %s)\n",
1151 plane_name(plane), state_string(state), state_string(cur_state));
1152 }
1153
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1156
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1158 enum pipe pipe)
1159 {
1160 struct drm_device *dev = dev_priv->dev;
1161 int reg, i;
1162 u32 val;
1163 int cur_pipe;
1164
1165 /* Primary planes are fixed to pipes on gen4+ */
1166 if (INTEL_INFO(dev)->gen >= 4) {
1167 reg = DSPCNTR(pipe);
1168 val = I915_READ(reg);
1169 WARN(val & DISPLAY_PLANE_ENABLE,
1170 "plane %c assertion failure, should be disabled but not\n",
1171 plane_name(pipe));
1172 return;
1173 }
1174
1175 /* Need to check both planes against the pipe */
1176 for_each_pipe(i) {
1177 reg = DSPCNTR(i);
1178 val = I915_READ(reg);
1179 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180 DISPPLANE_SEL_PIPE_SHIFT;
1181 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183 plane_name(i), pipe_name(pipe));
1184 }
1185 }
1186
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1188 enum pipe pipe)
1189 {
1190 struct drm_device *dev = dev_priv->dev;
1191 int reg, sprite;
1192 u32 val;
1193
1194 if (IS_VALLEYVIEW(dev)) {
1195 for_each_sprite(pipe, sprite) {
1196 reg = SPCNTR(pipe, sprite);
1197 val = I915_READ(reg);
1198 WARN(val & SP_ENABLE,
1199 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200 sprite_name(pipe, sprite), pipe_name(pipe));
1201 }
1202 } else if (INTEL_INFO(dev)->gen >= 7) {
1203 reg = SPRCTL(pipe);
1204 val = I915_READ(reg);
1205 WARN(val & SPRITE_ENABLE,
1206 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207 plane_name(pipe), pipe_name(pipe));
1208 } else if (INTEL_INFO(dev)->gen >= 5) {
1209 reg = DVSCNTR(pipe);
1210 val = I915_READ(reg);
1211 WARN(val & DVS_ENABLE,
1212 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213 plane_name(pipe), pipe_name(pipe));
1214 }
1215 }
1216
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1218 {
1219 u32 val;
1220 bool enabled;
1221
1222 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1223
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265 {
1266 if ((val & SDVO_ENABLE) == 0)
1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271 return false;
1272 } else {
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274 return false;
1275 }
1276 return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281 {
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297 {
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1312 {
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1317
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325 {
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1330
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338 {
1339 int reg;
1340 u32 val;
1341
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1350 pipe_name(pipe));
1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356 pipe_name(pipe));
1357
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367 if (!IS_VALLEYVIEW(dev))
1368 return;
1369
1370 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1371 }
1372
1373 static void intel_reset_dpio(struct drm_device *dev)
1374 {
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376
1377 if (!IS_VALLEYVIEW(dev))
1378 return;
1379
1380 /*
1381 * Enable the CRI clock source so we can get at the display and the
1382 * reference clock for VGA hotplug / manual detection.
1383 */
1384 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385 DPLL_REFA_CLK_ENABLE_VLV |
1386 DPLL_INTEGRATED_CRI_CLK_VLV);
1387
1388 /*
1389 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1391 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392 * b. The other bits such as sfr settings / modesel may all be set
1393 * to 0.
1394 *
1395 * This should only be done on init and resume from S3 with both
1396 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1397 */
1398 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1399 }
1400
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1402 {
1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408 assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410 /* No really, not for ILK+ */
1411 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1412
1413 /* PLL is protected by panel, make sure we can write it */
1414 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417 I915_WRITE(reg, dpll);
1418 POSTING_READ(reg);
1419 udelay(150);
1420
1421 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1423
1424 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425 POSTING_READ(DPLL_MD(crtc->pipe));
1426
1427 /* We do this three times for luck */
1428 I915_WRITE(reg, dpll);
1429 POSTING_READ(reg);
1430 udelay(150); /* wait for warmup */
1431 I915_WRITE(reg, dpll);
1432 POSTING_READ(reg);
1433 udelay(150); /* wait for warmup */
1434 I915_WRITE(reg, dpll);
1435 POSTING_READ(reg);
1436 udelay(150); /* wait for warmup */
1437 }
1438
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1440 {
1441 struct drm_device *dev = crtc->base.dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 int reg = DPLL(crtc->pipe);
1444 u32 dpll = crtc->config.dpll_hw_state.dpll;
1445
1446 assert_pipe_disabled(dev_priv, crtc->pipe);
1447
1448 /* No really, not for ILK+ */
1449 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1450
1451 /* PLL is protected by panel, make sure we can write it */
1452 if (IS_MOBILE(dev) && !IS_I830(dev))
1453 assert_panel_unlocked(dev_priv, crtc->pipe);
1454
1455 I915_WRITE(reg, dpll);
1456
1457 /* Wait for the clocks to stabilize. */
1458 POSTING_READ(reg);
1459 udelay(150);
1460
1461 if (INTEL_INFO(dev)->gen >= 4) {
1462 I915_WRITE(DPLL_MD(crtc->pipe),
1463 crtc->config.dpll_hw_state.dpll_md);
1464 } else {
1465 /* The pixel multiplier can only be updated once the
1466 * DPLL is enabled and the clocks are stable.
1467 *
1468 * So write it again.
1469 */
1470 I915_WRITE(reg, dpll);
1471 }
1472
1473 /* We do this three times for luck */
1474 I915_WRITE(reg, dpll);
1475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
1477 I915_WRITE(reg, dpll);
1478 POSTING_READ(reg);
1479 udelay(150); /* wait for warmup */
1480 I915_WRITE(reg, dpll);
1481 POSTING_READ(reg);
1482 udelay(150); /* wait for warmup */
1483 }
1484
1485 /**
1486 * i9xx_disable_pll - disable a PLL
1487 * @dev_priv: i915 private structure
1488 * @pipe: pipe PLL to disable
1489 *
1490 * Disable the PLL for @pipe, making sure the pipe is off first.
1491 *
1492 * Note! This is for pre-ILK only.
1493 */
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1495 {
1496 /* Don't disable pipe A or pipe A PLLs if needed */
1497 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1498 return;
1499
1500 /* Make sure the pipe isn't still relying on us */
1501 assert_pipe_disabled(dev_priv, pipe);
1502
1503 I915_WRITE(DPLL(pipe), 0);
1504 POSTING_READ(DPLL(pipe));
1505 }
1506
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1508 {
1509 u32 val = 0;
1510
1511 /* Make sure the pipe isn't still relying on us */
1512 assert_pipe_disabled(dev_priv, pipe);
1513
1514 /*
1515 * Leave integrated clock source and reference clock enabled for pipe B.
1516 * The latter is needed for VGA hotplug / manual detection.
1517 */
1518 if (pipe == PIPE_B)
1519 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520 I915_WRITE(DPLL(pipe), val);
1521 POSTING_READ(DPLL(pipe));
1522 }
1523
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525 struct intel_digital_port *dport)
1526 {
1527 u32 port_mask;
1528
1529 switch (dport->port) {
1530 case PORT_B:
1531 port_mask = DPLL_PORTB_READY_MASK;
1532 break;
1533 case PORT_C:
1534 port_mask = DPLL_PORTC_READY_MASK;
1535 break;
1536 default:
1537 BUG();
1538 }
1539
1540 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542 port_name(dport->port), I915_READ(DPLL(0)));
1543 }
1544
1545 /**
1546 * ironlake_enable_shared_dpll - enable PCH PLL
1547 * @dev_priv: i915 private structure
1548 * @pipe: pipe PLL to enable
1549 *
1550 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551 * drives the transcoder clock.
1552 */
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1554 {
1555 struct drm_device *dev = crtc->base.dev;
1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1558
1559 /* PCH PLLs only available on ILK, SNB and IVB */
1560 BUG_ON(INTEL_INFO(dev)->gen < 5);
1561 if (WARN_ON(pll == NULL))
1562 return;
1563
1564 if (WARN_ON(pll->refcount == 0))
1565 return;
1566
1567 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568 pll->name, pll->active, pll->on,
1569 crtc->base.base.id);
1570
1571 if (pll->active++) {
1572 WARN_ON(!pll->on);
1573 assert_shared_dpll_enabled(dev_priv, pll);
1574 return;
1575 }
1576 WARN_ON(pll->on);
1577
1578 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579 pll->enable(dev_priv, pll);
1580 pll->on = true;
1581 }
1582
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1584 {
1585 struct drm_device *dev = crtc->base.dev;
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1588
1589 /* PCH only available on ILK+ */
1590 BUG_ON(INTEL_INFO(dev)->gen < 5);
1591 if (WARN_ON(pll == NULL))
1592 return;
1593
1594 if (WARN_ON(pll->refcount == 0))
1595 return;
1596
1597 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598 pll->name, pll->active, pll->on,
1599 crtc->base.base.id);
1600
1601 if (WARN_ON(pll->active == 0)) {
1602 assert_shared_dpll_disabled(dev_priv, pll);
1603 return;
1604 }
1605
1606 assert_shared_dpll_enabled(dev_priv, pll);
1607 WARN_ON(!pll->on);
1608 if (--pll->active)
1609 return;
1610
1611 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612 pll->disable(dev_priv, pll);
1613 pll->on = false;
1614 }
1615
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617 enum pipe pipe)
1618 {
1619 struct drm_device *dev = dev_priv->dev;
1620 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622 uint32_t reg, val, pipeconf_val;
1623
1624 /* PCH only available on ILK+ */
1625 BUG_ON(INTEL_INFO(dev)->gen < 5);
1626
1627 /* Make sure PCH DPLL is enabled */
1628 assert_shared_dpll_enabled(dev_priv,
1629 intel_crtc_to_shared_dpll(intel_crtc));
1630
1631 /* FDI must be feeding us bits for PCH ports */
1632 assert_fdi_tx_enabled(dev_priv, pipe);
1633 assert_fdi_rx_enabled(dev_priv, pipe);
1634
1635 if (HAS_PCH_CPT(dev)) {
1636 /* Workaround: Set the timing override bit before enabling the
1637 * pch transcoder. */
1638 reg = TRANS_CHICKEN2(pipe);
1639 val = I915_READ(reg);
1640 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641 I915_WRITE(reg, val);
1642 }
1643
1644 reg = PCH_TRANSCONF(pipe);
1645 val = I915_READ(reg);
1646 pipeconf_val = I915_READ(PIPECONF(pipe));
1647
1648 if (HAS_PCH_IBX(dev_priv->dev)) {
1649 /*
1650 * make the BPC in transcoder be consistent with
1651 * that in pipeconf reg.
1652 */
1653 val &= ~PIPECONF_BPC_MASK;
1654 val |= pipeconf_val & PIPECONF_BPC_MASK;
1655 }
1656
1657 val &= ~TRANS_INTERLACE_MASK;
1658 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659 if (HAS_PCH_IBX(dev_priv->dev) &&
1660 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661 val |= TRANS_LEGACY_INTERLACED_ILK;
1662 else
1663 val |= TRANS_INTERLACED;
1664 else
1665 val |= TRANS_PROGRESSIVE;
1666
1667 I915_WRITE(reg, val | TRANS_ENABLE);
1668 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1670 }
1671
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673 enum transcoder cpu_transcoder)
1674 {
1675 u32 val, pipeconf_val;
1676
1677 /* PCH only available on ILK+ */
1678 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1679
1680 /* FDI must be feeding us bits for PCH ports */
1681 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1683
1684 /* Workaround: set timing override bit. */
1685 val = I915_READ(_TRANSA_CHICKEN2);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(_TRANSA_CHICKEN2, val);
1688
1689 val = TRANS_ENABLE;
1690 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1691
1692 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693 PIPECONF_INTERLACED_ILK)
1694 val |= TRANS_INTERLACED;
1695 else
1696 val |= TRANS_PROGRESSIVE;
1697
1698 I915_WRITE(LPT_TRANSCONF, val);
1699 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700 DRM_ERROR("Failed to enable PCH transcoder\n");
1701 }
1702
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1704 enum pipe pipe)
1705 {
1706 struct drm_device *dev = dev_priv->dev;
1707 uint32_t reg, val;
1708
1709 /* FDI relies on the transcoder */
1710 assert_fdi_tx_disabled(dev_priv, pipe);
1711 assert_fdi_rx_disabled(dev_priv, pipe);
1712
1713 /* Ports must be off as well */
1714 assert_pch_ports_disabled(dev_priv, pipe);
1715
1716 reg = PCH_TRANSCONF(pipe);
1717 val = I915_READ(reg);
1718 val &= ~TRANS_ENABLE;
1719 I915_WRITE(reg, val);
1720 /* wait for PCH transcoder off, transcoder state */
1721 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1723
1724 if (!HAS_PCH_IBX(dev)) {
1725 /* Workaround: Clear the timing override chicken bit again. */
1726 reg = TRANS_CHICKEN2(pipe);
1727 val = I915_READ(reg);
1728 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 I915_WRITE(reg, val);
1730 }
1731 }
1732
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1734 {
1735 u32 val;
1736
1737 val = I915_READ(LPT_TRANSCONF);
1738 val &= ~TRANS_ENABLE;
1739 I915_WRITE(LPT_TRANSCONF, val);
1740 /* wait for PCH transcoder off, transcoder state */
1741 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742 DRM_ERROR("Failed to disable PCH transcoder\n");
1743
1744 /* Workaround: clear timing override bit. */
1745 val = I915_READ(_TRANSA_CHICKEN2);
1746 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747 I915_WRITE(_TRANSA_CHICKEN2, val);
1748 }
1749
1750 /**
1751 * intel_enable_pipe - enable a pipe, asserting requirements
1752 * @crtc: crtc responsible for the pipe
1753 *
1754 * Enable @crtc's pipe, making sure that various hardware specific requirements
1755 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1756 */
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1758 {
1759 struct drm_device *dev = crtc->base.dev;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 enum pipe pipe = crtc->pipe;
1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
1764 enum pipe pch_transcoder;
1765 int reg;
1766 u32 val;
1767
1768 assert_planes_disabled(dev_priv, pipe);
1769 assert_cursor_disabled(dev_priv, pipe);
1770 assert_sprites_disabled(dev_priv, pipe);
1771
1772 if (HAS_PCH_LPT(dev_priv->dev))
1773 pch_transcoder = TRANSCODER_A;
1774 else
1775 pch_transcoder = pipe;
1776
1777 /*
1778 * A pipe without a PLL won't actually be able to drive bits from
1779 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1780 * need the check.
1781 */
1782 if (!HAS_PCH_SPLIT(dev_priv->dev))
1783 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784 assert_dsi_pll_enabled(dev_priv);
1785 else
1786 assert_pll_enabled(dev_priv, pipe);
1787 else {
1788 if (crtc->config.has_pch_encoder) {
1789 /* if driving the PCH, we need FDI enabled */
1790 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791 assert_fdi_tx_pll_enabled(dev_priv,
1792 (enum pipe) cpu_transcoder);
1793 }
1794 /* FIXME: assert CPU port conditions for SNB+ */
1795 }
1796
1797 reg = PIPECONF(cpu_transcoder);
1798 val = I915_READ(reg);
1799 if (val & PIPECONF_ENABLE) {
1800 WARN_ON(!(pipe == PIPE_A &&
1801 dev_priv->quirks & QUIRK_PIPEA_FORCE));
1802 return;
1803 }
1804
1805 I915_WRITE(reg, val | PIPECONF_ENABLE);
1806 POSTING_READ(reg);
1807 }
1808
1809 /**
1810 * intel_disable_pipe - disable a pipe, asserting requirements
1811 * @dev_priv: i915 private structure
1812 * @pipe: pipe to disable
1813 *
1814 * Disable @pipe, making sure that various hardware specific requirements
1815 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1816 *
1817 * @pipe should be %PIPE_A or %PIPE_B.
1818 *
1819 * Will wait until the pipe has shut down before returning.
1820 */
1821 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1822 enum pipe pipe)
1823 {
1824 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1825 pipe);
1826 int reg;
1827 u32 val;
1828
1829 /*
1830 * Make sure planes won't keep trying to pump pixels to us,
1831 * or we might hang the display.
1832 */
1833 assert_planes_disabled(dev_priv, pipe);
1834 assert_cursor_disabled(dev_priv, pipe);
1835 assert_sprites_disabled(dev_priv, pipe);
1836
1837 /* Don't disable pipe A or pipe A PLLs if needed */
1838 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1839 return;
1840
1841 reg = PIPECONF(cpu_transcoder);
1842 val = I915_READ(reg);
1843 if ((val & PIPECONF_ENABLE) == 0)
1844 return;
1845
1846 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1847 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1848 }
1849
1850 /*
1851 * Plane regs are double buffered, going from enabled->disabled needs a
1852 * trigger in order to latch. The display address reg provides this.
1853 */
1854 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1855 enum plane plane)
1856 {
1857 struct drm_device *dev = dev_priv->dev;
1858 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1859
1860 I915_WRITE(reg, I915_READ(reg));
1861 POSTING_READ(reg);
1862 }
1863
1864 /**
1865 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1866 * @dev_priv: i915 private structure
1867 * @plane: plane to enable
1868 * @pipe: pipe being fed
1869 *
1870 * Enable @plane on @pipe, making sure that @pipe is running first.
1871 */
1872 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1873 enum plane plane, enum pipe pipe)
1874 {
1875 struct intel_crtc *intel_crtc =
1876 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1877 int reg;
1878 u32 val;
1879
1880 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1881 assert_pipe_enabled(dev_priv, pipe);
1882
1883 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1884
1885 intel_crtc->primary_enabled = true;
1886
1887 reg = DSPCNTR(plane);
1888 val = I915_READ(reg);
1889 if (val & DISPLAY_PLANE_ENABLE)
1890 return;
1891
1892 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1893 intel_flush_primary_plane(dev_priv, plane);
1894 intel_wait_for_vblank(dev_priv->dev, pipe);
1895 }
1896
1897 /**
1898 * intel_disable_primary_hw_plane - disable the primary hardware plane
1899 * @dev_priv: i915 private structure
1900 * @plane: plane to disable
1901 * @pipe: pipe consuming the data
1902 *
1903 * Disable @plane; should be an independent operation.
1904 */
1905 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1906 enum plane plane, enum pipe pipe)
1907 {
1908 struct intel_crtc *intel_crtc =
1909 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1910 int reg;
1911 u32 val;
1912
1913 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1914
1915 intel_crtc->primary_enabled = false;
1916
1917 reg = DSPCNTR(plane);
1918 val = I915_READ(reg);
1919 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1920 return;
1921
1922 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1923 intel_flush_primary_plane(dev_priv, plane);
1924 intel_wait_for_vblank(dev_priv->dev, pipe);
1925 }
1926
1927 static bool need_vtd_wa(struct drm_device *dev)
1928 {
1929 #ifdef CONFIG_INTEL_IOMMU
1930 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1931 return true;
1932 #endif
1933 return false;
1934 }
1935
1936 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1937 {
1938 int tile_height;
1939
1940 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1941 return ALIGN(height, tile_height);
1942 }
1943
1944 int
1945 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1946 struct drm_i915_gem_object *obj,
1947 struct intel_ring_buffer *pipelined)
1948 {
1949 struct drm_i915_private *dev_priv = dev->dev_private;
1950 u32 alignment;
1951 int ret;
1952
1953 switch (obj->tiling_mode) {
1954 case I915_TILING_NONE:
1955 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1956 alignment = 128 * 1024;
1957 else if (INTEL_INFO(dev)->gen >= 4)
1958 alignment = 4 * 1024;
1959 else
1960 alignment = 64 * 1024;
1961 break;
1962 case I915_TILING_X:
1963 /* pin() will align the object as required by fence */
1964 alignment = 0;
1965 break;
1966 case I915_TILING_Y:
1967 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1968 return -EINVAL;
1969 default:
1970 BUG();
1971 }
1972
1973 /* Note that the w/a also requires 64 PTE of padding following the
1974 * bo. We currently fill all unused PTE with the shadow page and so
1975 * we should always have valid PTE following the scanout preventing
1976 * the VT-d warning.
1977 */
1978 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1979 alignment = 256 * 1024;
1980
1981 dev_priv->mm.interruptible = false;
1982 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1983 if (ret)
1984 goto err_interruptible;
1985
1986 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1987 * fence, whereas 965+ only requires a fence if using
1988 * framebuffer compression. For simplicity, we always install
1989 * a fence as the cost is not that onerous.
1990 */
1991 ret = i915_gem_object_get_fence(obj);
1992 if (ret)
1993 goto err_unpin;
1994
1995 i915_gem_object_pin_fence(obj);
1996
1997 dev_priv->mm.interruptible = true;
1998 return 0;
1999
2000 err_unpin:
2001 i915_gem_object_unpin_from_display_plane(obj);
2002 err_interruptible:
2003 dev_priv->mm.interruptible = true;
2004 return ret;
2005 }
2006
2007 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2008 {
2009 i915_gem_object_unpin_fence(obj);
2010 i915_gem_object_unpin_from_display_plane(obj);
2011 }
2012
2013 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2014 * is assumed to be a power-of-two. */
2015 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2016 unsigned int tiling_mode,
2017 unsigned int cpp,
2018 unsigned int pitch)
2019 {
2020 if (tiling_mode != I915_TILING_NONE) {
2021 unsigned int tile_rows, tiles;
2022
2023 tile_rows = *y / 8;
2024 *y %= 8;
2025
2026 tiles = *x / (512/cpp);
2027 *x %= 512/cpp;
2028
2029 return tile_rows * pitch * 8 + tiles * 4096;
2030 } else {
2031 unsigned int offset;
2032
2033 offset = *y * pitch + *x * cpp;
2034 *y = 0;
2035 *x = (offset & 4095) / cpp;
2036 return offset & -4096;
2037 }
2038 }
2039
2040 int intel_format_to_fourcc(int format)
2041 {
2042 switch (format) {
2043 case DISPPLANE_8BPP:
2044 return DRM_FORMAT_C8;
2045 case DISPPLANE_BGRX555:
2046 return DRM_FORMAT_XRGB1555;
2047 case DISPPLANE_BGRX565:
2048 return DRM_FORMAT_RGB565;
2049 default:
2050 case DISPPLANE_BGRX888:
2051 return DRM_FORMAT_XRGB8888;
2052 case DISPPLANE_RGBX888:
2053 return DRM_FORMAT_XBGR8888;
2054 case DISPPLANE_BGRX101010:
2055 return DRM_FORMAT_XRGB2101010;
2056 case DISPPLANE_RGBX101010:
2057 return DRM_FORMAT_XBGR2101010;
2058 }
2059 }
2060
2061 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2062 struct intel_plane_config *plane_config)
2063 {
2064 struct drm_device *dev = crtc->base.dev;
2065 struct drm_i915_gem_object *obj = NULL;
2066 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2067 u32 base = plane_config->base;
2068
2069 if (plane_config->size == 0)
2070 return false;
2071
2072 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2073 plane_config->size);
2074 if (!obj)
2075 return false;
2076
2077 if (plane_config->tiled) {
2078 obj->tiling_mode = I915_TILING_X;
2079 obj->stride = crtc->base.primary->fb->pitches[0];
2080 }
2081
2082 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2083 mode_cmd.width = crtc->base.primary->fb->width;
2084 mode_cmd.height = crtc->base.primary->fb->height;
2085 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2086
2087 mutex_lock(&dev->struct_mutex);
2088
2089 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2090 &mode_cmd, obj)) {
2091 DRM_DEBUG_KMS("intel fb init failed\n");
2092 goto out_unref_obj;
2093 }
2094
2095 mutex_unlock(&dev->struct_mutex);
2096
2097 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2098 return true;
2099
2100 out_unref_obj:
2101 drm_gem_object_unreference(&obj->base);
2102 mutex_unlock(&dev->struct_mutex);
2103 return false;
2104 }
2105
2106 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2107 struct intel_plane_config *plane_config)
2108 {
2109 struct drm_device *dev = intel_crtc->base.dev;
2110 struct drm_crtc *c;
2111 struct intel_crtc *i;
2112 struct intel_framebuffer *fb;
2113
2114 if (!intel_crtc->base.primary->fb)
2115 return;
2116
2117 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2118 return;
2119
2120 kfree(intel_crtc->base.primary->fb);
2121 intel_crtc->base.primary->fb = NULL;
2122
2123 /*
2124 * Failed to alloc the obj, check to see if we should share
2125 * an fb with another CRTC instead
2126 */
2127 list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2128 i = to_intel_crtc(c);
2129
2130 if (c == &intel_crtc->base)
2131 continue;
2132
2133 if (!i->active || !c->primary->fb)
2134 continue;
2135
2136 fb = to_intel_framebuffer(c->primary->fb);
2137 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2138 drm_framebuffer_reference(c->primary->fb);
2139 intel_crtc->base.primary->fb = c->primary->fb;
2140 break;
2141 }
2142 }
2143 }
2144
2145 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2146 struct drm_framebuffer *fb,
2147 int x, int y)
2148 {
2149 struct drm_device *dev = crtc->dev;
2150 struct drm_i915_private *dev_priv = dev->dev_private;
2151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2152 struct intel_framebuffer *intel_fb;
2153 struct drm_i915_gem_object *obj;
2154 int plane = intel_crtc->plane;
2155 unsigned long linear_offset;
2156 u32 dspcntr;
2157 u32 reg;
2158
2159 intel_fb = to_intel_framebuffer(fb);
2160 obj = intel_fb->obj;
2161
2162 reg = DSPCNTR(plane);
2163 dspcntr = I915_READ(reg);
2164 /* Mask out pixel format bits in case we change it */
2165 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2166 switch (fb->pixel_format) {
2167 case DRM_FORMAT_C8:
2168 dspcntr |= DISPPLANE_8BPP;
2169 break;
2170 case DRM_FORMAT_XRGB1555:
2171 case DRM_FORMAT_ARGB1555:
2172 dspcntr |= DISPPLANE_BGRX555;
2173 break;
2174 case DRM_FORMAT_RGB565:
2175 dspcntr |= DISPPLANE_BGRX565;
2176 break;
2177 case DRM_FORMAT_XRGB8888:
2178 case DRM_FORMAT_ARGB8888:
2179 dspcntr |= DISPPLANE_BGRX888;
2180 break;
2181 case DRM_FORMAT_XBGR8888:
2182 case DRM_FORMAT_ABGR8888:
2183 dspcntr |= DISPPLANE_RGBX888;
2184 break;
2185 case DRM_FORMAT_XRGB2101010:
2186 case DRM_FORMAT_ARGB2101010:
2187 dspcntr |= DISPPLANE_BGRX101010;
2188 break;
2189 case DRM_FORMAT_XBGR2101010:
2190 case DRM_FORMAT_ABGR2101010:
2191 dspcntr |= DISPPLANE_RGBX101010;
2192 break;
2193 default:
2194 BUG();
2195 }
2196
2197 if (INTEL_INFO(dev)->gen >= 4) {
2198 if (obj->tiling_mode != I915_TILING_NONE)
2199 dspcntr |= DISPPLANE_TILED;
2200 else
2201 dspcntr &= ~DISPPLANE_TILED;
2202 }
2203
2204 if (IS_G4X(dev))
2205 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2206
2207 I915_WRITE(reg, dspcntr);
2208
2209 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2210
2211 if (INTEL_INFO(dev)->gen >= 4) {
2212 intel_crtc->dspaddr_offset =
2213 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2214 fb->bits_per_pixel / 8,
2215 fb->pitches[0]);
2216 linear_offset -= intel_crtc->dspaddr_offset;
2217 } else {
2218 intel_crtc->dspaddr_offset = linear_offset;
2219 }
2220
2221 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2222 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2223 fb->pitches[0]);
2224 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2225 if (INTEL_INFO(dev)->gen >= 4) {
2226 I915_WRITE(DSPSURF(plane),
2227 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2228 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2229 I915_WRITE(DSPLINOFF(plane), linear_offset);
2230 } else
2231 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2232 POSTING_READ(reg);
2233
2234 return 0;
2235 }
2236
2237 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2238 struct drm_framebuffer *fb,
2239 int x, int y)
2240 {
2241 struct drm_device *dev = crtc->dev;
2242 struct drm_i915_private *dev_priv = dev->dev_private;
2243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244 struct intel_framebuffer *intel_fb;
2245 struct drm_i915_gem_object *obj;
2246 int plane = intel_crtc->plane;
2247 unsigned long linear_offset;
2248 u32 dspcntr;
2249 u32 reg;
2250
2251 intel_fb = to_intel_framebuffer(fb);
2252 obj = intel_fb->obj;
2253
2254 reg = DSPCNTR(plane);
2255 dspcntr = I915_READ(reg);
2256 /* Mask out pixel format bits in case we change it */
2257 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2258 switch (fb->pixel_format) {
2259 case DRM_FORMAT_C8:
2260 dspcntr |= DISPPLANE_8BPP;
2261 break;
2262 case DRM_FORMAT_RGB565:
2263 dspcntr |= DISPPLANE_BGRX565;
2264 break;
2265 case DRM_FORMAT_XRGB8888:
2266 case DRM_FORMAT_ARGB8888:
2267 dspcntr |= DISPPLANE_BGRX888;
2268 break;
2269 case DRM_FORMAT_XBGR8888:
2270 case DRM_FORMAT_ABGR8888:
2271 dspcntr |= DISPPLANE_RGBX888;
2272 break;
2273 case DRM_FORMAT_XRGB2101010:
2274 case DRM_FORMAT_ARGB2101010:
2275 dspcntr |= DISPPLANE_BGRX101010;
2276 break;
2277 case DRM_FORMAT_XBGR2101010:
2278 case DRM_FORMAT_ABGR2101010:
2279 dspcntr |= DISPPLANE_RGBX101010;
2280 break;
2281 default:
2282 BUG();
2283 }
2284
2285 if (obj->tiling_mode != I915_TILING_NONE)
2286 dspcntr |= DISPPLANE_TILED;
2287 else
2288 dspcntr &= ~DISPPLANE_TILED;
2289
2290 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2291 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2292 else
2293 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2294
2295 I915_WRITE(reg, dspcntr);
2296
2297 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2298 intel_crtc->dspaddr_offset =
2299 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2300 fb->bits_per_pixel / 8,
2301 fb->pitches[0]);
2302 linear_offset -= intel_crtc->dspaddr_offset;
2303
2304 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2305 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2306 fb->pitches[0]);
2307 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2308 I915_WRITE(DSPSURF(plane),
2309 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2310 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2311 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2312 } else {
2313 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2314 I915_WRITE(DSPLINOFF(plane), linear_offset);
2315 }
2316 POSTING_READ(reg);
2317
2318 return 0;
2319 }
2320
2321 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2322 static int
2323 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2324 int x, int y, enum mode_set_atomic state)
2325 {
2326 struct drm_device *dev = crtc->dev;
2327 struct drm_i915_private *dev_priv = dev->dev_private;
2328
2329 if (dev_priv->display.disable_fbc)
2330 dev_priv->display.disable_fbc(dev);
2331 intel_increase_pllclock(crtc);
2332
2333 return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2334 }
2335
2336 void intel_display_handle_reset(struct drm_device *dev)
2337 {
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct drm_crtc *crtc;
2340
2341 /*
2342 * Flips in the rings have been nuked by the reset,
2343 * so complete all pending flips so that user space
2344 * will get its events and not get stuck.
2345 *
2346 * Also update the base address of all primary
2347 * planes to the the last fb to make sure we're
2348 * showing the correct fb after a reset.
2349 *
2350 * Need to make two loops over the crtcs so that we
2351 * don't try to grab a crtc mutex before the
2352 * pending_flip_queue really got woken up.
2353 */
2354
2355 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2357 enum plane plane = intel_crtc->plane;
2358
2359 intel_prepare_page_flip(dev, plane);
2360 intel_finish_page_flip_plane(dev, plane);
2361 }
2362
2363 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365
2366 mutex_lock(&crtc->mutex);
2367 /*
2368 * FIXME: Once we have proper support for primary planes (and
2369 * disabling them without disabling the entire crtc) allow again
2370 * a NULL crtc->primary->fb.
2371 */
2372 if (intel_crtc->active && crtc->primary->fb)
2373 dev_priv->display.update_primary_plane(crtc,
2374 crtc->primary->fb,
2375 crtc->x,
2376 crtc->y);
2377 mutex_unlock(&crtc->mutex);
2378 }
2379 }
2380
2381 static int
2382 intel_finish_fb(struct drm_framebuffer *old_fb)
2383 {
2384 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2385 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2386 bool was_interruptible = dev_priv->mm.interruptible;
2387 int ret;
2388
2389 /* Big Hammer, we also need to ensure that any pending
2390 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2391 * current scanout is retired before unpinning the old
2392 * framebuffer.
2393 *
2394 * This should only fail upon a hung GPU, in which case we
2395 * can safely continue.
2396 */
2397 dev_priv->mm.interruptible = false;
2398 ret = i915_gem_object_finish_gpu(obj);
2399 dev_priv->mm.interruptible = was_interruptible;
2400
2401 return ret;
2402 }
2403
2404 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2405 {
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 unsigned long flags;
2410 bool pending;
2411
2412 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2413 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2414 return false;
2415
2416 spin_lock_irqsave(&dev->event_lock, flags);
2417 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2418 spin_unlock_irqrestore(&dev->event_lock, flags);
2419
2420 return pending;
2421 }
2422
2423 static int
2424 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2425 struct drm_framebuffer *fb)
2426 {
2427 struct drm_device *dev = crtc->dev;
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430 struct drm_framebuffer *old_fb;
2431 int ret;
2432
2433 if (intel_crtc_has_pending_flip(crtc)) {
2434 DRM_ERROR("pipe is still busy with an old pageflip\n");
2435 return -EBUSY;
2436 }
2437
2438 /* no fb bound */
2439 if (!fb) {
2440 DRM_ERROR("No FB bound\n");
2441 return 0;
2442 }
2443
2444 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2445 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2446 plane_name(intel_crtc->plane),
2447 INTEL_INFO(dev)->num_pipes);
2448 return -EINVAL;
2449 }
2450
2451 mutex_lock(&dev->struct_mutex);
2452 ret = intel_pin_and_fence_fb_obj(dev,
2453 to_intel_framebuffer(fb)->obj,
2454 NULL);
2455 mutex_unlock(&dev->struct_mutex);
2456 if (ret != 0) {
2457 DRM_ERROR("pin & fence failed\n");
2458 return ret;
2459 }
2460
2461 /*
2462 * Update pipe size and adjust fitter if needed: the reason for this is
2463 * that in compute_mode_changes we check the native mode (not the pfit
2464 * mode) to see if we can flip rather than do a full mode set. In the
2465 * fastboot case, we'll flip, but if we don't update the pipesrc and
2466 * pfit state, we'll end up with a big fb scanned out into the wrong
2467 * sized surface.
2468 *
2469 * To fix this properly, we need to hoist the checks up into
2470 * compute_mode_changes (or above), check the actual pfit state and
2471 * whether the platform allows pfit disable with pipe active, and only
2472 * then update the pipesrc and pfit state, even on the flip path.
2473 */
2474 if (i915.fastboot) {
2475 const struct drm_display_mode *adjusted_mode =
2476 &intel_crtc->config.adjusted_mode;
2477
2478 I915_WRITE(PIPESRC(intel_crtc->pipe),
2479 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2480 (adjusted_mode->crtc_vdisplay - 1));
2481 if (!intel_crtc->config.pch_pfit.enabled &&
2482 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2483 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2484 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2485 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2486 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2487 }
2488 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2489 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2490 }
2491
2492 ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2493 if (ret) {
2494 mutex_lock(&dev->struct_mutex);
2495 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2496 mutex_unlock(&dev->struct_mutex);
2497 DRM_ERROR("failed to update base address\n");
2498 return ret;
2499 }
2500
2501 old_fb = crtc->primary->fb;
2502 crtc->primary->fb = fb;
2503 crtc->x = x;
2504 crtc->y = y;
2505
2506 if (old_fb) {
2507 if (intel_crtc->active && old_fb != fb)
2508 intel_wait_for_vblank(dev, intel_crtc->pipe);
2509 mutex_lock(&dev->struct_mutex);
2510 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2511 mutex_unlock(&dev->struct_mutex);
2512 }
2513
2514 mutex_lock(&dev->struct_mutex);
2515 intel_update_fbc(dev);
2516 intel_edp_psr_update(dev);
2517 mutex_unlock(&dev->struct_mutex);
2518
2519 return 0;
2520 }
2521
2522 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2523 {
2524 struct drm_device *dev = crtc->dev;
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2527 int pipe = intel_crtc->pipe;
2528 u32 reg, temp;
2529
2530 /* enable normal train */
2531 reg = FDI_TX_CTL(pipe);
2532 temp = I915_READ(reg);
2533 if (IS_IVYBRIDGE(dev)) {
2534 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2535 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2536 } else {
2537 temp &= ~FDI_LINK_TRAIN_NONE;
2538 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2539 }
2540 I915_WRITE(reg, temp);
2541
2542 reg = FDI_RX_CTL(pipe);
2543 temp = I915_READ(reg);
2544 if (HAS_PCH_CPT(dev)) {
2545 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2546 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2547 } else {
2548 temp &= ~FDI_LINK_TRAIN_NONE;
2549 temp |= FDI_LINK_TRAIN_NONE;
2550 }
2551 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2552
2553 /* wait one idle pattern time */
2554 POSTING_READ(reg);
2555 udelay(1000);
2556
2557 /* IVB wants error correction enabled */
2558 if (IS_IVYBRIDGE(dev))
2559 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2560 FDI_FE_ERRC_ENABLE);
2561 }
2562
2563 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2564 {
2565 return crtc->base.enabled && crtc->active &&
2566 crtc->config.has_pch_encoder;
2567 }
2568
2569 static void ivb_modeset_global_resources(struct drm_device *dev)
2570 {
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572 struct intel_crtc *pipe_B_crtc =
2573 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2574 struct intel_crtc *pipe_C_crtc =
2575 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2576 uint32_t temp;
2577
2578 /*
2579 * When everything is off disable fdi C so that we could enable fdi B
2580 * with all lanes. Note that we don't care about enabled pipes without
2581 * an enabled pch encoder.
2582 */
2583 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2584 !pipe_has_enabled_pch(pipe_C_crtc)) {
2585 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2586 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2587
2588 temp = I915_READ(SOUTH_CHICKEN1);
2589 temp &= ~FDI_BC_BIFURCATION_SELECT;
2590 DRM_DEBUG_KMS("disabling fdi C rx\n");
2591 I915_WRITE(SOUTH_CHICKEN1, temp);
2592 }
2593 }
2594
2595 /* The FDI link training functions for ILK/Ibexpeak. */
2596 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2597 {
2598 struct drm_device *dev = crtc->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 int pipe = intel_crtc->pipe;
2602 int plane = intel_crtc->plane;
2603 u32 reg, temp, tries;
2604
2605 /* FDI needs bits from pipe & plane first */
2606 assert_pipe_enabled(dev_priv, pipe);
2607 assert_plane_enabled(dev_priv, plane);
2608
2609 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2610 for train result */
2611 reg = FDI_RX_IMR(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_RX_SYMBOL_LOCK;
2614 temp &= ~FDI_RX_BIT_LOCK;
2615 I915_WRITE(reg, temp);
2616 I915_READ(reg);
2617 udelay(150);
2618
2619 /* enable CPU FDI TX and PCH FDI RX */
2620 reg = FDI_TX_CTL(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2623 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2624 temp &= ~FDI_LINK_TRAIN_NONE;
2625 temp |= FDI_LINK_TRAIN_PATTERN_1;
2626 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2627
2628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
2630 temp &= ~FDI_LINK_TRAIN_NONE;
2631 temp |= FDI_LINK_TRAIN_PATTERN_1;
2632 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2633
2634 POSTING_READ(reg);
2635 udelay(150);
2636
2637 /* Ironlake workaround, enable clock pointer after FDI enable*/
2638 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2639 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2640 FDI_RX_PHASE_SYNC_POINTER_EN);
2641
2642 reg = FDI_RX_IIR(pipe);
2643 for (tries = 0; tries < 5; tries++) {
2644 temp = I915_READ(reg);
2645 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2646
2647 if ((temp & FDI_RX_BIT_LOCK)) {
2648 DRM_DEBUG_KMS("FDI train 1 done.\n");
2649 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2650 break;
2651 }
2652 }
2653 if (tries == 5)
2654 DRM_ERROR("FDI train 1 fail!\n");
2655
2656 /* Train 2 */
2657 reg = FDI_TX_CTL(pipe);
2658 temp = I915_READ(reg);
2659 temp &= ~FDI_LINK_TRAIN_NONE;
2660 temp |= FDI_LINK_TRAIN_PATTERN_2;
2661 I915_WRITE(reg, temp);
2662
2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~FDI_LINK_TRAIN_NONE;
2666 temp |= FDI_LINK_TRAIN_PATTERN_2;
2667 I915_WRITE(reg, temp);
2668
2669 POSTING_READ(reg);
2670 udelay(150);
2671
2672 reg = FDI_RX_IIR(pipe);
2673 for (tries = 0; tries < 5; tries++) {
2674 temp = I915_READ(reg);
2675 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2676
2677 if (temp & FDI_RX_SYMBOL_LOCK) {
2678 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2679 DRM_DEBUG_KMS("FDI train 2 done.\n");
2680 break;
2681 }
2682 }
2683 if (tries == 5)
2684 DRM_ERROR("FDI train 2 fail!\n");
2685
2686 DRM_DEBUG_KMS("FDI train done\n");
2687
2688 }
2689
2690 static const int snb_b_fdi_train_param[] = {
2691 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2692 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2693 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2694 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2695 };
2696
2697 /* The FDI link training functions for SNB/Cougarpoint. */
2698 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2699 {
2700 struct drm_device *dev = crtc->dev;
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703 int pipe = intel_crtc->pipe;
2704 u32 reg, temp, i, retry;
2705
2706 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2707 for train result */
2708 reg = FDI_RX_IMR(pipe);
2709 temp = I915_READ(reg);
2710 temp &= ~FDI_RX_SYMBOL_LOCK;
2711 temp &= ~FDI_RX_BIT_LOCK;
2712 I915_WRITE(reg, temp);
2713
2714 POSTING_READ(reg);
2715 udelay(150);
2716
2717 /* enable CPU FDI TX and PCH FDI RX */
2718 reg = FDI_TX_CTL(pipe);
2719 temp = I915_READ(reg);
2720 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2721 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2722 temp &= ~FDI_LINK_TRAIN_NONE;
2723 temp |= FDI_LINK_TRAIN_PATTERN_1;
2724 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2725 /* SNB-B */
2726 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2727 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2728
2729 I915_WRITE(FDI_RX_MISC(pipe),
2730 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2731
2732 reg = FDI_RX_CTL(pipe);
2733 temp = I915_READ(reg);
2734 if (HAS_PCH_CPT(dev)) {
2735 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2736 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2737 } else {
2738 temp &= ~FDI_LINK_TRAIN_NONE;
2739 temp |= FDI_LINK_TRAIN_PATTERN_1;
2740 }
2741 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2742
2743 POSTING_READ(reg);
2744 udelay(150);
2745
2746 for (i = 0; i < 4; i++) {
2747 reg = FDI_TX_CTL(pipe);
2748 temp = I915_READ(reg);
2749 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2750 temp |= snb_b_fdi_train_param[i];
2751 I915_WRITE(reg, temp);
2752
2753 POSTING_READ(reg);
2754 udelay(500);
2755
2756 for (retry = 0; retry < 5; retry++) {
2757 reg = FDI_RX_IIR(pipe);
2758 temp = I915_READ(reg);
2759 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2760 if (temp & FDI_RX_BIT_LOCK) {
2761 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2762 DRM_DEBUG_KMS("FDI train 1 done.\n");
2763 break;
2764 }
2765 udelay(50);
2766 }
2767 if (retry < 5)
2768 break;
2769 }
2770 if (i == 4)
2771 DRM_ERROR("FDI train 1 fail!\n");
2772
2773 /* Train 2 */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~FDI_LINK_TRAIN_NONE;
2777 temp |= FDI_LINK_TRAIN_PATTERN_2;
2778 if (IS_GEN6(dev)) {
2779 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2780 /* SNB-B */
2781 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2782 }
2783 I915_WRITE(reg, temp);
2784
2785 reg = FDI_RX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 if (HAS_PCH_CPT(dev)) {
2788 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2789 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2790 } else {
2791 temp &= ~FDI_LINK_TRAIN_NONE;
2792 temp |= FDI_LINK_TRAIN_PATTERN_2;
2793 }
2794 I915_WRITE(reg, temp);
2795
2796 POSTING_READ(reg);
2797 udelay(150);
2798
2799 for (i = 0; i < 4; i++) {
2800 reg = FDI_TX_CTL(pipe);
2801 temp = I915_READ(reg);
2802 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2803 temp |= snb_b_fdi_train_param[i];
2804 I915_WRITE(reg, temp);
2805
2806 POSTING_READ(reg);
2807 udelay(500);
2808
2809 for (retry = 0; retry < 5; retry++) {
2810 reg = FDI_RX_IIR(pipe);
2811 temp = I915_READ(reg);
2812 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2813 if (temp & FDI_RX_SYMBOL_LOCK) {
2814 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2815 DRM_DEBUG_KMS("FDI train 2 done.\n");
2816 break;
2817 }
2818 udelay(50);
2819 }
2820 if (retry < 5)
2821 break;
2822 }
2823 if (i == 4)
2824 DRM_ERROR("FDI train 2 fail!\n");
2825
2826 DRM_DEBUG_KMS("FDI train done.\n");
2827 }
2828
2829 /* Manual link training for Ivy Bridge A0 parts */
2830 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2831 {
2832 struct drm_device *dev = crtc->dev;
2833 struct drm_i915_private *dev_priv = dev->dev_private;
2834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2835 int pipe = intel_crtc->pipe;
2836 u32 reg, temp, i, j;
2837
2838 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2839 for train result */
2840 reg = FDI_RX_IMR(pipe);
2841 temp = I915_READ(reg);
2842 temp &= ~FDI_RX_SYMBOL_LOCK;
2843 temp &= ~FDI_RX_BIT_LOCK;
2844 I915_WRITE(reg, temp);
2845
2846 POSTING_READ(reg);
2847 udelay(150);
2848
2849 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2850 I915_READ(FDI_RX_IIR(pipe)));
2851
2852 /* Try each vswing and preemphasis setting twice before moving on */
2853 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2854 /* disable first in case we need to retry */
2855 reg = FDI_TX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2858 temp &= ~FDI_TX_ENABLE;
2859 I915_WRITE(reg, temp);
2860
2861 reg = FDI_RX_CTL(pipe);
2862 temp = I915_READ(reg);
2863 temp &= ~FDI_LINK_TRAIN_AUTO;
2864 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2865 temp &= ~FDI_RX_ENABLE;
2866 I915_WRITE(reg, temp);
2867
2868 /* enable CPU FDI TX and PCH FDI RX */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2872 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2873 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2874 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2875 temp |= snb_b_fdi_train_param[j/2];
2876 temp |= FDI_COMPOSITE_SYNC;
2877 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2878
2879 I915_WRITE(FDI_RX_MISC(pipe),
2880 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2881
2882 reg = FDI_RX_CTL(pipe);
2883 temp = I915_READ(reg);
2884 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2885 temp |= FDI_COMPOSITE_SYNC;
2886 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2887
2888 POSTING_READ(reg);
2889 udelay(1); /* should be 0.5us */
2890
2891 for (i = 0; i < 4; i++) {
2892 reg = FDI_RX_IIR(pipe);
2893 temp = I915_READ(reg);
2894 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2895
2896 if (temp & FDI_RX_BIT_LOCK ||
2897 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2898 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2899 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2900 i);
2901 break;
2902 }
2903 udelay(1); /* should be 0.5us */
2904 }
2905 if (i == 4) {
2906 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2907 continue;
2908 }
2909
2910 /* Train 2 */
2911 reg = FDI_TX_CTL(pipe);
2912 temp = I915_READ(reg);
2913 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2914 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2915 I915_WRITE(reg, temp);
2916
2917 reg = FDI_RX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2920 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2921 I915_WRITE(reg, temp);
2922
2923 POSTING_READ(reg);
2924 udelay(2); /* should be 1.5us */
2925
2926 for (i = 0; i < 4; i++) {
2927 reg = FDI_RX_IIR(pipe);
2928 temp = I915_READ(reg);
2929 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2930
2931 if (temp & FDI_RX_SYMBOL_LOCK ||
2932 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2933 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2934 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2935 i);
2936 goto train_done;
2937 }
2938 udelay(2); /* should be 1.5us */
2939 }
2940 if (i == 4)
2941 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2942 }
2943
2944 train_done:
2945 DRM_DEBUG_KMS("FDI train done.\n");
2946 }
2947
2948 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2949 {
2950 struct drm_device *dev = intel_crtc->base.dev;
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 int pipe = intel_crtc->pipe;
2953 u32 reg, temp;
2954
2955
2956 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2957 reg = FDI_RX_CTL(pipe);
2958 temp = I915_READ(reg);
2959 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2960 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2961 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2962 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2963
2964 POSTING_READ(reg);
2965 udelay(200);
2966
2967 /* Switch from Rawclk to PCDclk */
2968 temp = I915_READ(reg);
2969 I915_WRITE(reg, temp | FDI_PCDCLK);
2970
2971 POSTING_READ(reg);
2972 udelay(200);
2973
2974 /* Enable CPU FDI TX PLL, always on for Ironlake */
2975 reg = FDI_TX_CTL(pipe);
2976 temp = I915_READ(reg);
2977 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2978 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2979
2980 POSTING_READ(reg);
2981 udelay(100);
2982 }
2983 }
2984
2985 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2986 {
2987 struct drm_device *dev = intel_crtc->base.dev;
2988 struct drm_i915_private *dev_priv = dev->dev_private;
2989 int pipe = intel_crtc->pipe;
2990 u32 reg, temp;
2991
2992 /* Switch from PCDclk to Rawclk */
2993 reg = FDI_RX_CTL(pipe);
2994 temp = I915_READ(reg);
2995 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2996
2997 /* Disable CPU FDI TX PLL */
2998 reg = FDI_TX_CTL(pipe);
2999 temp = I915_READ(reg);
3000 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3001
3002 POSTING_READ(reg);
3003 udelay(100);
3004
3005 reg = FDI_RX_CTL(pipe);
3006 temp = I915_READ(reg);
3007 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3008
3009 /* Wait for the clocks to turn off. */
3010 POSTING_READ(reg);
3011 udelay(100);
3012 }
3013
3014 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3015 {
3016 struct drm_device *dev = crtc->dev;
3017 struct drm_i915_private *dev_priv = dev->dev_private;
3018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3019 int pipe = intel_crtc->pipe;
3020 u32 reg, temp;
3021
3022 /* disable CPU FDI tx and PCH FDI rx */
3023 reg = FDI_TX_CTL(pipe);
3024 temp = I915_READ(reg);
3025 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3026 POSTING_READ(reg);
3027
3028 reg = FDI_RX_CTL(pipe);
3029 temp = I915_READ(reg);
3030 temp &= ~(0x7 << 16);
3031 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3032 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3033
3034 POSTING_READ(reg);
3035 udelay(100);
3036
3037 /* Ironlake workaround, disable clock pointer after downing FDI */
3038 if (HAS_PCH_IBX(dev)) {
3039 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3040 }
3041
3042 /* still set train pattern 1 */
3043 reg = FDI_TX_CTL(pipe);
3044 temp = I915_READ(reg);
3045 temp &= ~FDI_LINK_TRAIN_NONE;
3046 temp |= FDI_LINK_TRAIN_PATTERN_1;
3047 I915_WRITE(reg, temp);
3048
3049 reg = FDI_RX_CTL(pipe);
3050 temp = I915_READ(reg);
3051 if (HAS_PCH_CPT(dev)) {
3052 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3053 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3054 } else {
3055 temp &= ~FDI_LINK_TRAIN_NONE;
3056 temp |= FDI_LINK_TRAIN_PATTERN_1;
3057 }
3058 /* BPC in FDI rx is consistent with that in PIPECONF */
3059 temp &= ~(0x07 << 16);
3060 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3061 I915_WRITE(reg, temp);
3062
3063 POSTING_READ(reg);
3064 udelay(100);
3065 }
3066
3067 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3068 {
3069 struct intel_crtc *crtc;
3070
3071 /* Note that we don't need to be called with mode_config.lock here
3072 * as our list of CRTC objects is static for the lifetime of the
3073 * device and so cannot disappear as we iterate. Similarly, we can
3074 * happily treat the predicates as racy, atomic checks as userspace
3075 * cannot claim and pin a new fb without at least acquring the
3076 * struct_mutex and so serialising with us.
3077 */
3078 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3079 if (atomic_read(&crtc->unpin_work_count) == 0)
3080 continue;
3081
3082 if (crtc->unpin_work)
3083 intel_wait_for_vblank(dev, crtc->pipe);
3084
3085 return true;
3086 }
3087
3088 return false;
3089 }
3090
3091 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3092 {
3093 struct drm_device *dev = crtc->dev;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
3095
3096 if (crtc->primary->fb == NULL)
3097 return;
3098
3099 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3100
3101 wait_event(dev_priv->pending_flip_queue,
3102 !intel_crtc_has_pending_flip(crtc));
3103
3104 mutex_lock(&dev->struct_mutex);
3105 intel_finish_fb(crtc->primary->fb);
3106 mutex_unlock(&dev->struct_mutex);
3107 }
3108
3109 /* Program iCLKIP clock to the desired frequency */
3110 static void lpt_program_iclkip(struct drm_crtc *crtc)
3111 {
3112 struct drm_device *dev = crtc->dev;
3113 struct drm_i915_private *dev_priv = dev->dev_private;
3114 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3115 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3116 u32 temp;
3117
3118 mutex_lock(&dev_priv->dpio_lock);
3119
3120 /* It is necessary to ungate the pixclk gate prior to programming
3121 * the divisors, and gate it back when it is done.
3122 */
3123 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3124
3125 /* Disable SSCCTL */
3126 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3127 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3128 SBI_SSCCTL_DISABLE,
3129 SBI_ICLK);
3130
3131 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3132 if (clock == 20000) {
3133 auxdiv = 1;
3134 divsel = 0x41;
3135 phaseinc = 0x20;
3136 } else {
3137 /* The iCLK virtual clock root frequency is in MHz,
3138 * but the adjusted_mode->crtc_clock in in KHz. To get the
3139 * divisors, it is necessary to divide one by another, so we
3140 * convert the virtual clock precision to KHz here for higher
3141 * precision.
3142 */
3143 u32 iclk_virtual_root_freq = 172800 * 1000;
3144 u32 iclk_pi_range = 64;
3145 u32 desired_divisor, msb_divisor_value, pi_value;
3146
3147 desired_divisor = (iclk_virtual_root_freq / clock);
3148 msb_divisor_value = desired_divisor / iclk_pi_range;
3149 pi_value = desired_divisor % iclk_pi_range;
3150
3151 auxdiv = 0;
3152 divsel = msb_divisor_value - 2;
3153 phaseinc = pi_value;
3154 }
3155
3156 /* This should not happen with any sane values */
3157 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3158 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3159 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3160 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3161
3162 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3163 clock,
3164 auxdiv,
3165 divsel,
3166 phasedir,
3167 phaseinc);
3168
3169 /* Program SSCDIVINTPHASE6 */
3170 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3171 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3172 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3173 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3174 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3175 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3176 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3177 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3178
3179 /* Program SSCAUXDIV */
3180 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3181 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3182 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3183 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3184
3185 /* Enable modulator and associated divider */
3186 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3187 temp &= ~SBI_SSCCTL_DISABLE;
3188 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3189
3190 /* Wait for initialization time */
3191 udelay(24);
3192
3193 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3194
3195 mutex_unlock(&dev_priv->dpio_lock);
3196 }
3197
3198 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3199 enum pipe pch_transcoder)
3200 {
3201 struct drm_device *dev = crtc->base.dev;
3202 struct drm_i915_private *dev_priv = dev->dev_private;
3203 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3204
3205 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3206 I915_READ(HTOTAL(cpu_transcoder)));
3207 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3208 I915_READ(HBLANK(cpu_transcoder)));
3209 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3210 I915_READ(HSYNC(cpu_transcoder)));
3211
3212 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3213 I915_READ(VTOTAL(cpu_transcoder)));
3214 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3215 I915_READ(VBLANK(cpu_transcoder)));
3216 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3217 I915_READ(VSYNC(cpu_transcoder)));
3218 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3219 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3220 }
3221
3222 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3223 {
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 uint32_t temp;
3226
3227 temp = I915_READ(SOUTH_CHICKEN1);
3228 if (temp & FDI_BC_BIFURCATION_SELECT)
3229 return;
3230
3231 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3232 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3233
3234 temp |= FDI_BC_BIFURCATION_SELECT;
3235 DRM_DEBUG_KMS("enabling fdi C rx\n");
3236 I915_WRITE(SOUTH_CHICKEN1, temp);
3237 POSTING_READ(SOUTH_CHICKEN1);
3238 }
3239
3240 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3241 {
3242 struct drm_device *dev = intel_crtc->base.dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244
3245 switch (intel_crtc->pipe) {
3246 case PIPE_A:
3247 break;
3248 case PIPE_B:
3249 if (intel_crtc->config.fdi_lanes > 2)
3250 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3251 else
3252 cpt_enable_fdi_bc_bifurcation(dev);
3253
3254 break;
3255 case PIPE_C:
3256 cpt_enable_fdi_bc_bifurcation(dev);
3257
3258 break;
3259 default:
3260 BUG();
3261 }
3262 }
3263
3264 /*
3265 * Enable PCH resources required for PCH ports:
3266 * - PCH PLLs
3267 * - FDI training & RX/TX
3268 * - update transcoder timings
3269 * - DP transcoding bits
3270 * - transcoder
3271 */
3272 static void ironlake_pch_enable(struct drm_crtc *crtc)
3273 {
3274 struct drm_device *dev = crtc->dev;
3275 struct drm_i915_private *dev_priv = dev->dev_private;
3276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3277 int pipe = intel_crtc->pipe;
3278 u32 reg, temp;
3279
3280 assert_pch_transcoder_disabled(dev_priv, pipe);
3281
3282 if (IS_IVYBRIDGE(dev))
3283 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3284
3285 /* Write the TU size bits before fdi link training, so that error
3286 * detection works. */
3287 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3288 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3289
3290 /* For PCH output, training FDI link */
3291 dev_priv->display.fdi_link_train(crtc);
3292
3293 /* We need to program the right clock selection before writing the pixel
3294 * mutliplier into the DPLL. */
3295 if (HAS_PCH_CPT(dev)) {
3296 u32 sel;
3297
3298 temp = I915_READ(PCH_DPLL_SEL);
3299 temp |= TRANS_DPLL_ENABLE(pipe);
3300 sel = TRANS_DPLLB_SEL(pipe);
3301 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3302 temp |= sel;
3303 else
3304 temp &= ~sel;
3305 I915_WRITE(PCH_DPLL_SEL, temp);
3306 }
3307
3308 /* XXX: pch pll's can be enabled any time before we enable the PCH
3309 * transcoder, and we actually should do this to not upset any PCH
3310 * transcoder that already use the clock when we share it.
3311 *
3312 * Note that enable_shared_dpll tries to do the right thing, but
3313 * get_shared_dpll unconditionally resets the pll - we need that to have
3314 * the right LVDS enable sequence. */
3315 ironlake_enable_shared_dpll(intel_crtc);
3316
3317 /* set transcoder timing, panel must allow it */
3318 assert_panel_unlocked(dev_priv, pipe);
3319 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3320
3321 intel_fdi_normal_train(crtc);
3322
3323 /* For PCH DP, enable TRANS_DP_CTL */
3324 if (HAS_PCH_CPT(dev) &&
3325 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3326 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3327 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3328 reg = TRANS_DP_CTL(pipe);
3329 temp = I915_READ(reg);
3330 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3331 TRANS_DP_SYNC_MASK |
3332 TRANS_DP_BPC_MASK);
3333 temp |= (TRANS_DP_OUTPUT_ENABLE |
3334 TRANS_DP_ENH_FRAMING);
3335 temp |= bpc << 9; /* same format but at 11:9 */
3336
3337 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3338 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3339 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3340 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3341
3342 switch (intel_trans_dp_port_sel(crtc)) {
3343 case PCH_DP_B:
3344 temp |= TRANS_DP_PORT_SEL_B;
3345 break;
3346 case PCH_DP_C:
3347 temp |= TRANS_DP_PORT_SEL_C;
3348 break;
3349 case PCH_DP_D:
3350 temp |= TRANS_DP_PORT_SEL_D;
3351 break;
3352 default:
3353 BUG();
3354 }
3355
3356 I915_WRITE(reg, temp);
3357 }
3358
3359 ironlake_enable_pch_transcoder(dev_priv, pipe);
3360 }
3361
3362 static void lpt_pch_enable(struct drm_crtc *crtc)
3363 {
3364 struct drm_device *dev = crtc->dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3367 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3368
3369 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3370
3371 lpt_program_iclkip(crtc);
3372
3373 /* Set transcoder timing. */
3374 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3375
3376 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3377 }
3378
3379 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3380 {
3381 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3382
3383 if (pll == NULL)
3384 return;
3385
3386 if (pll->refcount == 0) {
3387 WARN(1, "bad %s refcount\n", pll->name);
3388 return;
3389 }
3390
3391 if (--pll->refcount == 0) {
3392 WARN_ON(pll->on);
3393 WARN_ON(pll->active);
3394 }
3395
3396 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3397 }
3398
3399 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3400 {
3401 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3402 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3403 enum intel_dpll_id i;
3404
3405 if (pll) {
3406 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3407 crtc->base.base.id, pll->name);
3408 intel_put_shared_dpll(crtc);
3409 }
3410
3411 if (HAS_PCH_IBX(dev_priv->dev)) {
3412 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3413 i = (enum intel_dpll_id) crtc->pipe;
3414 pll = &dev_priv->shared_dplls[i];
3415
3416 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3417 crtc->base.base.id, pll->name);
3418
3419 goto found;
3420 }
3421
3422 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3423 pll = &dev_priv->shared_dplls[i];
3424
3425 /* Only want to check enabled timings first */
3426 if (pll->refcount == 0)
3427 continue;
3428
3429 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3430 sizeof(pll->hw_state)) == 0) {
3431 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3432 crtc->base.base.id,
3433 pll->name, pll->refcount, pll->active);
3434
3435 goto found;
3436 }
3437 }
3438
3439 /* Ok no matching timings, maybe there's a free one? */
3440 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3441 pll = &dev_priv->shared_dplls[i];
3442 if (pll->refcount == 0) {
3443 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3444 crtc->base.base.id, pll->name);
3445 goto found;
3446 }
3447 }
3448
3449 return NULL;
3450
3451 found:
3452 crtc->config.shared_dpll = i;
3453 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3454 pipe_name(crtc->pipe));
3455
3456 if (pll->active == 0) {
3457 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3458 sizeof(pll->hw_state));
3459
3460 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3461 WARN_ON(pll->on);
3462 assert_shared_dpll_disabled(dev_priv, pll);
3463
3464 pll->mode_set(dev_priv, pll);
3465 }
3466 pll->refcount++;
3467
3468 return pll;
3469 }
3470
3471 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3472 {
3473 struct drm_i915_private *dev_priv = dev->dev_private;
3474 int dslreg = PIPEDSL(pipe);
3475 u32 temp;
3476
3477 temp = I915_READ(dslreg);
3478 udelay(500);
3479 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3480 if (wait_for(I915_READ(dslreg) != temp, 5))
3481 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3482 }
3483 }
3484
3485 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3486 {
3487 struct drm_device *dev = crtc->base.dev;
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 int pipe = crtc->pipe;
3490
3491 if (crtc->config.pch_pfit.enabled) {
3492 /* Force use of hard-coded filter coefficients
3493 * as some pre-programmed values are broken,
3494 * e.g. x201.
3495 */
3496 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3497 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3498 PF_PIPE_SEL_IVB(pipe));
3499 else
3500 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3501 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3502 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3503 }
3504 }
3505
3506 static void intel_enable_planes(struct drm_crtc *crtc)
3507 {
3508 struct drm_device *dev = crtc->dev;
3509 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3510 struct drm_plane *plane;
3511 struct intel_plane *intel_plane;
3512
3513 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3514 intel_plane = to_intel_plane(plane);
3515 if (intel_plane->pipe == pipe)
3516 intel_plane_restore(&intel_plane->base);
3517 }
3518 }
3519
3520 static void intel_disable_planes(struct drm_crtc *crtc)
3521 {
3522 struct drm_device *dev = crtc->dev;
3523 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3524 struct drm_plane *plane;
3525 struct intel_plane *intel_plane;
3526
3527 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3528 intel_plane = to_intel_plane(plane);
3529 if (intel_plane->pipe == pipe)
3530 intel_plane_disable(&intel_plane->base);
3531 }
3532 }
3533
3534 void hsw_enable_ips(struct intel_crtc *crtc)
3535 {
3536 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3537
3538 if (!crtc->config.ips_enabled)
3539 return;
3540
3541 /* We can only enable IPS after we enable a plane and wait for a vblank.
3542 * We guarantee that the plane is enabled by calling intel_enable_ips
3543 * only after intel_enable_plane. And intel_enable_plane already waits
3544 * for a vblank, so all we need to do here is to enable the IPS bit. */
3545 assert_plane_enabled(dev_priv, crtc->plane);
3546 if (IS_BROADWELL(crtc->base.dev)) {
3547 mutex_lock(&dev_priv->rps.hw_lock);
3548 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3549 mutex_unlock(&dev_priv->rps.hw_lock);
3550 /* Quoting Art Runyan: "its not safe to expect any particular
3551 * value in IPS_CTL bit 31 after enabling IPS through the
3552 * mailbox." Moreover, the mailbox may return a bogus state,
3553 * so we need to just enable it and continue on.
3554 */
3555 } else {
3556 I915_WRITE(IPS_CTL, IPS_ENABLE);
3557 /* The bit only becomes 1 in the next vblank, so this wait here
3558 * is essentially intel_wait_for_vblank. If we don't have this
3559 * and don't wait for vblanks until the end of crtc_enable, then
3560 * the HW state readout code will complain that the expected
3561 * IPS_CTL value is not the one we read. */
3562 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3563 DRM_ERROR("Timed out waiting for IPS enable\n");
3564 }
3565 }
3566
3567 void hsw_disable_ips(struct intel_crtc *crtc)
3568 {
3569 struct drm_device *dev = crtc->base.dev;
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3571
3572 if (!crtc->config.ips_enabled)
3573 return;
3574
3575 assert_plane_enabled(dev_priv, crtc->plane);
3576 if (IS_BROADWELL(dev)) {
3577 mutex_lock(&dev_priv->rps.hw_lock);
3578 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3579 mutex_unlock(&dev_priv->rps.hw_lock);
3580 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3581 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3582 DRM_ERROR("Timed out waiting for IPS disable\n");
3583 } else {
3584 I915_WRITE(IPS_CTL, 0);
3585 POSTING_READ(IPS_CTL);
3586 }
3587
3588 /* We need to wait for a vblank before we can disable the plane. */
3589 intel_wait_for_vblank(dev, crtc->pipe);
3590 }
3591
3592 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3593 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3594 {
3595 struct drm_device *dev = crtc->dev;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3598 enum pipe pipe = intel_crtc->pipe;
3599 int palreg = PALETTE(pipe);
3600 int i;
3601 bool reenable_ips = false;
3602
3603 /* The clocks have to be on to load the palette. */
3604 if (!crtc->enabled || !intel_crtc->active)
3605 return;
3606
3607 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3608 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3609 assert_dsi_pll_enabled(dev_priv);
3610 else
3611 assert_pll_enabled(dev_priv, pipe);
3612 }
3613
3614 /* use legacy palette for Ironlake */
3615 if (HAS_PCH_SPLIT(dev))
3616 palreg = LGC_PALETTE(pipe);
3617
3618 /* Workaround : Do not read or write the pipe palette/gamma data while
3619 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3620 */
3621 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3622 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3623 GAMMA_MODE_MODE_SPLIT)) {
3624 hsw_disable_ips(intel_crtc);
3625 reenable_ips = true;
3626 }
3627
3628 for (i = 0; i < 256; i++) {
3629 I915_WRITE(palreg + 4 * i,
3630 (intel_crtc->lut_r[i] << 16) |
3631 (intel_crtc->lut_g[i] << 8) |
3632 intel_crtc->lut_b[i]);
3633 }
3634
3635 if (reenable_ips)
3636 hsw_enable_ips(intel_crtc);
3637 }
3638
3639 static void ilk_crtc_enable_planes(struct drm_crtc *crtc)
3640 {
3641 struct drm_device *dev = crtc->dev;
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644 int pipe = intel_crtc->pipe;
3645 int plane = intel_crtc->plane;
3646
3647 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3648 intel_enable_planes(crtc);
3649 intel_crtc_update_cursor(crtc, true);
3650
3651 hsw_enable_ips(intel_crtc);
3652
3653 mutex_lock(&dev->struct_mutex);
3654 intel_update_fbc(dev);
3655 mutex_unlock(&dev->struct_mutex);
3656 }
3657
3658 static void ilk_crtc_disable_planes(struct drm_crtc *crtc)
3659 {
3660 struct drm_device *dev = crtc->dev;
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3663 int pipe = intel_crtc->pipe;
3664 int plane = intel_crtc->plane;
3665
3666 intel_crtc_wait_for_pending_flips(crtc);
3667 drm_vblank_off(dev, pipe);
3668
3669 if (dev_priv->fbc.plane == plane)
3670 intel_disable_fbc(dev);
3671
3672 hsw_disable_ips(intel_crtc);
3673
3674 intel_crtc_update_cursor(crtc, false);
3675 intel_disable_planes(crtc);
3676 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3677 }
3678
3679 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3680 {
3681 struct drm_device *dev = crtc->dev;
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3684 struct intel_encoder *encoder;
3685 int pipe = intel_crtc->pipe;
3686
3687 WARN_ON(!crtc->enabled);
3688
3689 if (intel_crtc->active)
3690 return;
3691
3692 intel_crtc->active = true;
3693
3694 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3695 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3696
3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 if (encoder->pre_enable)
3699 encoder->pre_enable(encoder);
3700
3701 if (intel_crtc->config.has_pch_encoder) {
3702 /* Note: FDI PLL enabling _must_ be done before we enable the
3703 * cpu pipes, hence this is separate from all the other fdi/pch
3704 * enabling. */
3705 ironlake_fdi_pll_enable(intel_crtc);
3706 } else {
3707 assert_fdi_tx_disabled(dev_priv, pipe);
3708 assert_fdi_rx_disabled(dev_priv, pipe);
3709 }
3710
3711 ironlake_pfit_enable(intel_crtc);
3712
3713 /*
3714 * On ILK+ LUT must be loaded before the pipe is running but with
3715 * clocks enabled
3716 */
3717 intel_crtc_load_lut(crtc);
3718
3719 intel_update_watermarks(crtc);
3720 intel_enable_pipe(intel_crtc);
3721
3722 if (intel_crtc->config.has_pch_encoder)
3723 ironlake_pch_enable(crtc);
3724
3725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->enable(encoder);
3727
3728 if (HAS_PCH_CPT(dev))
3729 cpt_verify_modeset(dev, intel_crtc->pipe);
3730
3731 ilk_crtc_enable_planes(crtc);
3732
3733 /*
3734 * There seems to be a race in PCH platform hw (at least on some
3735 * outputs) where an enabled pipe still completes any pageflip right
3736 * away (as if the pipe is off) instead of waiting for vblank. As soon
3737 * as the first vblank happend, everything works as expected. Hence just
3738 * wait for one vblank before returning to avoid strange things
3739 * happening.
3740 */
3741 intel_wait_for_vblank(dev, intel_crtc->pipe);
3742 }
3743
3744 /* IPS only exists on ULT machines and is tied to pipe A. */
3745 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3746 {
3747 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3748 }
3749
3750 /*
3751 * This implements the workaround described in the "notes" section of the mode
3752 * set sequence documentation. When going from no pipes or single pipe to
3753 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3754 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3755 */
3756 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3757 {
3758 struct drm_device *dev = crtc->base.dev;
3759 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3760
3761 /* We want to get the other_active_crtc only if there's only 1 other
3762 * active crtc. */
3763 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3764 if (!crtc_it->active || crtc_it == crtc)
3765 continue;
3766
3767 if (other_active_crtc)
3768 return;
3769
3770 other_active_crtc = crtc_it;
3771 }
3772 if (!other_active_crtc)
3773 return;
3774
3775 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3776 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3777 }
3778
3779 static void haswell_crtc_enable(struct drm_crtc *crtc)
3780 {
3781 struct drm_device *dev = crtc->dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3784 struct intel_encoder *encoder;
3785 int pipe = intel_crtc->pipe;
3786
3787 WARN_ON(!crtc->enabled);
3788
3789 if (intel_crtc->active)
3790 return;
3791
3792 intel_crtc->active = true;
3793
3794 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3795 if (intel_crtc->config.has_pch_encoder)
3796 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3797
3798 if (intel_crtc->config.has_pch_encoder)
3799 dev_priv->display.fdi_link_train(crtc);
3800
3801 for_each_encoder_on_crtc(dev, crtc, encoder)
3802 if (encoder->pre_enable)
3803 encoder->pre_enable(encoder);
3804
3805 intel_ddi_enable_pipe_clock(intel_crtc);
3806
3807 ironlake_pfit_enable(intel_crtc);
3808
3809 /*
3810 * On ILK+ LUT must be loaded before the pipe is running but with
3811 * clocks enabled
3812 */
3813 intel_crtc_load_lut(crtc);
3814
3815 intel_ddi_set_pipe_settings(crtc);
3816 intel_ddi_enable_transcoder_func(crtc);
3817
3818 intel_update_watermarks(crtc);
3819 intel_enable_pipe(intel_crtc);
3820
3821 if (intel_crtc->config.has_pch_encoder)
3822 lpt_pch_enable(crtc);
3823
3824 for_each_encoder_on_crtc(dev, crtc, encoder) {
3825 encoder->enable(encoder);
3826 intel_opregion_notify_encoder(encoder, true);
3827 }
3828
3829 /* If we change the relative order between pipe/planes enabling, we need
3830 * to change the workaround. */
3831 haswell_mode_set_planes_workaround(intel_crtc);
3832 ilk_crtc_enable_planes(crtc);
3833 }
3834
3835 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3836 {
3837 struct drm_device *dev = crtc->base.dev;
3838 struct drm_i915_private *dev_priv = dev->dev_private;
3839 int pipe = crtc->pipe;
3840
3841 /* To avoid upsetting the power well on haswell only disable the pfit if
3842 * it's in use. The hw state code will make sure we get this right. */
3843 if (crtc->config.pch_pfit.enabled) {
3844 I915_WRITE(PF_CTL(pipe), 0);
3845 I915_WRITE(PF_WIN_POS(pipe), 0);
3846 I915_WRITE(PF_WIN_SZ(pipe), 0);
3847 }
3848 }
3849
3850 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3851 {
3852 struct drm_device *dev = crtc->dev;
3853 struct drm_i915_private *dev_priv = dev->dev_private;
3854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3855 struct intel_encoder *encoder;
3856 int pipe = intel_crtc->pipe;
3857 u32 reg, temp;
3858
3859 if (!intel_crtc->active)
3860 return;
3861
3862 ilk_crtc_disable_planes(crtc);
3863
3864 for_each_encoder_on_crtc(dev, crtc, encoder)
3865 encoder->disable(encoder);
3866
3867 if (intel_crtc->config.has_pch_encoder)
3868 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3869
3870 intel_disable_pipe(dev_priv, pipe);
3871
3872 ironlake_pfit_disable(intel_crtc);
3873
3874 for_each_encoder_on_crtc(dev, crtc, encoder)
3875 if (encoder->post_disable)
3876 encoder->post_disable(encoder);
3877
3878 if (intel_crtc->config.has_pch_encoder) {
3879 ironlake_fdi_disable(crtc);
3880
3881 ironlake_disable_pch_transcoder(dev_priv, pipe);
3882 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3883
3884 if (HAS_PCH_CPT(dev)) {
3885 /* disable TRANS_DP_CTL */
3886 reg = TRANS_DP_CTL(pipe);
3887 temp = I915_READ(reg);
3888 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3889 TRANS_DP_PORT_SEL_MASK);
3890 temp |= TRANS_DP_PORT_SEL_NONE;
3891 I915_WRITE(reg, temp);
3892
3893 /* disable DPLL_SEL */
3894 temp = I915_READ(PCH_DPLL_SEL);
3895 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3896 I915_WRITE(PCH_DPLL_SEL, temp);
3897 }
3898
3899 /* disable PCH DPLL */
3900 intel_disable_shared_dpll(intel_crtc);
3901
3902 ironlake_fdi_pll_disable(intel_crtc);
3903 }
3904
3905 intel_crtc->active = false;
3906 intel_update_watermarks(crtc);
3907
3908 mutex_lock(&dev->struct_mutex);
3909 intel_update_fbc(dev);
3910 mutex_unlock(&dev->struct_mutex);
3911 }
3912
3913 static void haswell_crtc_disable(struct drm_crtc *crtc)
3914 {
3915 struct drm_device *dev = crtc->dev;
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3918 struct intel_encoder *encoder;
3919 int pipe = intel_crtc->pipe;
3920 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3921
3922 if (!intel_crtc->active)
3923 return;
3924
3925 ilk_crtc_disable_planes(crtc);
3926
3927 for_each_encoder_on_crtc(dev, crtc, encoder) {
3928 intel_opregion_notify_encoder(encoder, false);
3929 encoder->disable(encoder);
3930 }
3931
3932 if (intel_crtc->config.has_pch_encoder)
3933 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3934 intel_disable_pipe(dev_priv, pipe);
3935
3936 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3937
3938 ironlake_pfit_disable(intel_crtc);
3939
3940 intel_ddi_disable_pipe_clock(intel_crtc);
3941
3942 for_each_encoder_on_crtc(dev, crtc, encoder)
3943 if (encoder->post_disable)
3944 encoder->post_disable(encoder);
3945
3946 if (intel_crtc->config.has_pch_encoder) {
3947 lpt_disable_pch_transcoder(dev_priv);
3948 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3949 intel_ddi_fdi_disable(crtc);
3950 }
3951
3952 intel_crtc->active = false;
3953 intel_update_watermarks(crtc);
3954
3955 mutex_lock(&dev->struct_mutex);
3956 intel_update_fbc(dev);
3957 mutex_unlock(&dev->struct_mutex);
3958 }
3959
3960 static void ironlake_crtc_off(struct drm_crtc *crtc)
3961 {
3962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3963 intel_put_shared_dpll(intel_crtc);
3964 }
3965
3966 static void haswell_crtc_off(struct drm_crtc *crtc)
3967 {
3968 intel_ddi_put_crtc_pll(crtc);
3969 }
3970
3971 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3972 {
3973 if (!enable && intel_crtc->overlay) {
3974 struct drm_device *dev = intel_crtc->base.dev;
3975 struct drm_i915_private *dev_priv = dev->dev_private;
3976
3977 mutex_lock(&dev->struct_mutex);
3978 dev_priv->mm.interruptible = false;
3979 (void) intel_overlay_switch_off(intel_crtc->overlay);
3980 dev_priv->mm.interruptible = true;
3981 mutex_unlock(&dev->struct_mutex);
3982 }
3983
3984 /* Let userspace switch the overlay on again. In most cases userspace
3985 * has to recompute where to put it anyway.
3986 */
3987 }
3988
3989 /**
3990 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3991 * cursor plane briefly if not already running after enabling the display
3992 * plane.
3993 * This workaround avoids occasional blank screens when self refresh is
3994 * enabled.
3995 */
3996 static void
3997 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3998 {
3999 u32 cntl = I915_READ(CURCNTR(pipe));
4000
4001 if ((cntl & CURSOR_MODE) == 0) {
4002 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
4003
4004 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
4005 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
4006 intel_wait_for_vblank(dev_priv->dev, pipe);
4007 I915_WRITE(CURCNTR(pipe), cntl);
4008 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
4009 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
4010 }
4011 }
4012
4013 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4014 {
4015 struct drm_device *dev = crtc->base.dev;
4016 struct drm_i915_private *dev_priv = dev->dev_private;
4017 struct intel_crtc_config *pipe_config = &crtc->config;
4018
4019 if (!crtc->config.gmch_pfit.control)
4020 return;
4021
4022 /*
4023 * The panel fitter should only be adjusted whilst the pipe is disabled,
4024 * according to register description and PRM.
4025 */
4026 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4027 assert_pipe_disabled(dev_priv, crtc->pipe);
4028
4029 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4030 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4031
4032 /* Border color in case we don't scale up to the full screen. Black by
4033 * default, change to something else for debugging. */
4034 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4035 }
4036
4037 #define for_each_power_domain(domain, mask) \
4038 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4039 if ((1 << (domain)) & (mask))
4040
4041 enum intel_display_power_domain
4042 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4043 {
4044 struct drm_device *dev = intel_encoder->base.dev;
4045 struct intel_digital_port *intel_dig_port;
4046
4047 switch (intel_encoder->type) {
4048 case INTEL_OUTPUT_UNKNOWN:
4049 /* Only DDI platforms should ever use this output type */
4050 WARN_ON_ONCE(!HAS_DDI(dev));
4051 case INTEL_OUTPUT_DISPLAYPORT:
4052 case INTEL_OUTPUT_HDMI:
4053 case INTEL_OUTPUT_EDP:
4054 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4055 switch (intel_dig_port->port) {
4056 case PORT_A:
4057 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4058 case PORT_B:
4059 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4060 case PORT_C:
4061 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4062 case PORT_D:
4063 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4064 default:
4065 WARN_ON_ONCE(1);
4066 return POWER_DOMAIN_PORT_OTHER;
4067 }
4068 case INTEL_OUTPUT_ANALOG:
4069 return POWER_DOMAIN_PORT_CRT;
4070 case INTEL_OUTPUT_DSI:
4071 return POWER_DOMAIN_PORT_DSI;
4072 default:
4073 return POWER_DOMAIN_PORT_OTHER;
4074 }
4075 }
4076
4077 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4078 {
4079 struct drm_device *dev = crtc->dev;
4080 struct intel_encoder *intel_encoder;
4081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4082 enum pipe pipe = intel_crtc->pipe;
4083 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4084 unsigned long mask;
4085 enum transcoder transcoder;
4086
4087 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4088
4089 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4090 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4091 if (pfit_enabled)
4092 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4093
4094 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4095 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4096
4097 return mask;
4098 }
4099
4100 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4101 bool enable)
4102 {
4103 if (dev_priv->power_domains.init_power_on == enable)
4104 return;
4105
4106 if (enable)
4107 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4108 else
4109 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4110
4111 dev_priv->power_domains.init_power_on = enable;
4112 }
4113
4114 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4115 {
4116 struct drm_i915_private *dev_priv = dev->dev_private;
4117 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4118 struct intel_crtc *crtc;
4119
4120 /*
4121 * First get all needed power domains, then put all unneeded, to avoid
4122 * any unnecessary toggling of the power wells.
4123 */
4124 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4125 enum intel_display_power_domain domain;
4126
4127 if (!crtc->base.enabled)
4128 continue;
4129
4130 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4131
4132 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4133 intel_display_power_get(dev_priv, domain);
4134 }
4135
4136 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4137 enum intel_display_power_domain domain;
4138
4139 for_each_power_domain(domain, crtc->enabled_power_domains)
4140 intel_display_power_put(dev_priv, domain);
4141
4142 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4143 }
4144
4145 intel_display_set_init_power(dev_priv, false);
4146 }
4147
4148 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4149 {
4150 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4151
4152 /* Obtain SKU information */
4153 mutex_lock(&dev_priv->dpio_lock);
4154 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4155 CCK_FUSE_HPLL_FREQ_MASK;
4156 mutex_unlock(&dev_priv->dpio_lock);
4157
4158 return vco_freq[hpll_freq];
4159 }
4160
4161 /* Adjust CDclk dividers to allow high res or save power if possible */
4162 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4163 {
4164 struct drm_i915_private *dev_priv = dev->dev_private;
4165 u32 val, cmd;
4166
4167 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4168 dev_priv->vlv_cdclk_freq = cdclk;
4169
4170 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4171 cmd = 2;
4172 else if (cdclk == 266)
4173 cmd = 1;
4174 else
4175 cmd = 0;
4176
4177 mutex_lock(&dev_priv->rps.hw_lock);
4178 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4179 val &= ~DSPFREQGUAR_MASK;
4180 val |= (cmd << DSPFREQGUAR_SHIFT);
4181 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4182 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4183 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4184 50)) {
4185 DRM_ERROR("timed out waiting for CDclk change\n");
4186 }
4187 mutex_unlock(&dev_priv->rps.hw_lock);
4188
4189 if (cdclk == 400) {
4190 u32 divider, vco;
4191
4192 vco = valleyview_get_vco(dev_priv);
4193 divider = ((vco << 1) / cdclk) - 1;
4194
4195 mutex_lock(&dev_priv->dpio_lock);
4196 /* adjust cdclk divider */
4197 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4198 val &= ~0xf;
4199 val |= divider;
4200 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4201 mutex_unlock(&dev_priv->dpio_lock);
4202 }
4203
4204 mutex_lock(&dev_priv->dpio_lock);
4205 /* adjust self-refresh exit latency value */
4206 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4207 val &= ~0x7f;
4208
4209 /*
4210 * For high bandwidth configs, we set a higher latency in the bunit
4211 * so that the core display fetch happens in time to avoid underruns.
4212 */
4213 if (cdclk == 400)
4214 val |= 4500 / 250; /* 4.5 usec */
4215 else
4216 val |= 3000 / 250; /* 3.0 usec */
4217 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4218 mutex_unlock(&dev_priv->dpio_lock);
4219
4220 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4221 intel_i2c_reset(dev);
4222 }
4223
4224 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4225 {
4226 int cur_cdclk, vco;
4227 int divider;
4228
4229 vco = valleyview_get_vco(dev_priv);
4230
4231 mutex_lock(&dev_priv->dpio_lock);
4232 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4233 mutex_unlock(&dev_priv->dpio_lock);
4234
4235 divider &= 0xf;
4236
4237 cur_cdclk = (vco << 1) / (divider + 1);
4238
4239 return cur_cdclk;
4240 }
4241
4242 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4243 int max_pixclk)
4244 {
4245 /*
4246 * Really only a few cases to deal with, as only 4 CDclks are supported:
4247 * 200MHz
4248 * 267MHz
4249 * 320MHz
4250 * 400MHz
4251 * So we check to see whether we're above 90% of the lower bin and
4252 * adjust if needed.
4253 */
4254 if (max_pixclk > 288000) {
4255 return 400;
4256 } else if (max_pixclk > 240000) {
4257 return 320;
4258 } else
4259 return 266;
4260 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4261 }
4262
4263 /* compute the max pixel clock for new configuration */
4264 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4265 {
4266 struct drm_device *dev = dev_priv->dev;
4267 struct intel_crtc *intel_crtc;
4268 int max_pixclk = 0;
4269
4270 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4271 base.head) {
4272 if (intel_crtc->new_enabled)
4273 max_pixclk = max(max_pixclk,
4274 intel_crtc->new_config->adjusted_mode.crtc_clock);
4275 }
4276
4277 return max_pixclk;
4278 }
4279
4280 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4281 unsigned *prepare_pipes)
4282 {
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 struct intel_crtc *intel_crtc;
4285 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4286
4287 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4288 dev_priv->vlv_cdclk_freq)
4289 return;
4290
4291 /* disable/enable all currently active pipes while we change cdclk */
4292 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4293 base.head)
4294 if (intel_crtc->base.enabled)
4295 *prepare_pipes |= (1 << intel_crtc->pipe);
4296 }
4297
4298 static void valleyview_modeset_global_resources(struct drm_device *dev)
4299 {
4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4302 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4303
4304 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4305 valleyview_set_cdclk(dev, req_cdclk);
4306 modeset_update_crtc_power_domains(dev);
4307 }
4308
4309 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4310 {
4311 struct drm_device *dev = crtc->dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4314 struct intel_encoder *encoder;
4315 int pipe = intel_crtc->pipe;
4316 int plane = intel_crtc->plane;
4317 bool is_dsi;
4318
4319 WARN_ON(!crtc->enabled);
4320
4321 if (intel_crtc->active)
4322 return;
4323
4324 intel_crtc->active = true;
4325
4326 for_each_encoder_on_crtc(dev, crtc, encoder)
4327 if (encoder->pre_pll_enable)
4328 encoder->pre_pll_enable(encoder);
4329
4330 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4331
4332 if (!is_dsi)
4333 vlv_enable_pll(intel_crtc);
4334
4335 for_each_encoder_on_crtc(dev, crtc, encoder)
4336 if (encoder->pre_enable)
4337 encoder->pre_enable(encoder);
4338
4339 i9xx_pfit_enable(intel_crtc);
4340
4341 intel_crtc_load_lut(crtc);
4342
4343 intel_update_watermarks(crtc);
4344 intel_enable_pipe(intel_crtc);
4345 intel_wait_for_vblank(dev_priv->dev, pipe);
4346 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4347
4348 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4349 intel_enable_planes(crtc);
4350 intel_crtc_update_cursor(crtc, true);
4351
4352 intel_update_fbc(dev);
4353
4354 for_each_encoder_on_crtc(dev, crtc, encoder)
4355 encoder->enable(encoder);
4356 }
4357
4358 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4359 {
4360 struct drm_device *dev = crtc->dev;
4361 struct drm_i915_private *dev_priv = dev->dev_private;
4362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4363 struct intel_encoder *encoder;
4364 int pipe = intel_crtc->pipe;
4365 int plane = intel_crtc->plane;
4366
4367 WARN_ON(!crtc->enabled);
4368
4369 if (intel_crtc->active)
4370 return;
4371
4372 intel_crtc->active = true;
4373
4374 for_each_encoder_on_crtc(dev, crtc, encoder)
4375 if (encoder->pre_enable)
4376 encoder->pre_enable(encoder);
4377
4378 i9xx_enable_pll(intel_crtc);
4379
4380 i9xx_pfit_enable(intel_crtc);
4381
4382 intel_crtc_load_lut(crtc);
4383
4384 intel_update_watermarks(crtc);
4385 intel_enable_pipe(intel_crtc);
4386 intel_wait_for_vblank(dev_priv->dev, pipe);
4387 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4388
4389 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4390 intel_enable_planes(crtc);
4391 /* The fixup needs to happen before cursor is enabled */
4392 if (IS_G4X(dev))
4393 g4x_fixup_plane(dev_priv, pipe);
4394 intel_crtc_update_cursor(crtc, true);
4395
4396 /* Give the overlay scaler a chance to enable if it's on this pipe */
4397 intel_crtc_dpms_overlay(intel_crtc, true);
4398
4399 intel_update_fbc(dev);
4400
4401 for_each_encoder_on_crtc(dev, crtc, encoder)
4402 encoder->enable(encoder);
4403 }
4404
4405 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4406 {
4407 struct drm_device *dev = crtc->base.dev;
4408 struct drm_i915_private *dev_priv = dev->dev_private;
4409
4410 if (!crtc->config.gmch_pfit.control)
4411 return;
4412
4413 assert_pipe_disabled(dev_priv, crtc->pipe);
4414
4415 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4416 I915_READ(PFIT_CONTROL));
4417 I915_WRITE(PFIT_CONTROL, 0);
4418 }
4419
4420 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4421 {
4422 struct drm_device *dev = crtc->dev;
4423 struct drm_i915_private *dev_priv = dev->dev_private;
4424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4425 struct intel_encoder *encoder;
4426 int pipe = intel_crtc->pipe;
4427 int plane = intel_crtc->plane;
4428
4429 if (!intel_crtc->active)
4430 return;
4431
4432 for_each_encoder_on_crtc(dev, crtc, encoder)
4433 encoder->disable(encoder);
4434
4435 /* Give the overlay scaler a chance to disable if it's on this pipe */
4436 intel_crtc_wait_for_pending_flips(crtc);
4437 drm_vblank_off(dev, pipe);
4438
4439 if (dev_priv->fbc.plane == plane)
4440 intel_disable_fbc(dev);
4441
4442 intel_crtc_dpms_overlay(intel_crtc, false);
4443 intel_crtc_update_cursor(crtc, false);
4444 intel_disable_planes(crtc);
4445 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
4446
4447 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4448 intel_disable_pipe(dev_priv, pipe);
4449
4450 i9xx_pfit_disable(intel_crtc);
4451
4452 for_each_encoder_on_crtc(dev, crtc, encoder)
4453 if (encoder->post_disable)
4454 encoder->post_disable(encoder);
4455
4456 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4457 vlv_disable_pll(dev_priv, pipe);
4458 else if (!IS_VALLEYVIEW(dev))
4459 i9xx_disable_pll(dev_priv, pipe);
4460
4461 intel_crtc->active = false;
4462 intel_update_watermarks(crtc);
4463
4464 intel_update_fbc(dev);
4465 }
4466
4467 static void i9xx_crtc_off(struct drm_crtc *crtc)
4468 {
4469 }
4470
4471 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4472 bool enabled)
4473 {
4474 struct drm_device *dev = crtc->dev;
4475 struct drm_i915_master_private *master_priv;
4476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4477 int pipe = intel_crtc->pipe;
4478
4479 if (!dev->primary->master)
4480 return;
4481
4482 master_priv = dev->primary->master->driver_priv;
4483 if (!master_priv->sarea_priv)
4484 return;
4485
4486 switch (pipe) {
4487 case 0:
4488 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4489 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4490 break;
4491 case 1:
4492 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4493 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4494 break;
4495 default:
4496 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4497 break;
4498 }
4499 }
4500
4501 /**
4502 * Sets the power management mode of the pipe and plane.
4503 */
4504 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4505 {
4506 struct drm_device *dev = crtc->dev;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 struct intel_encoder *intel_encoder;
4509 bool enable = false;
4510
4511 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4512 enable |= intel_encoder->connectors_active;
4513
4514 if (enable)
4515 dev_priv->display.crtc_enable(crtc);
4516 else
4517 dev_priv->display.crtc_disable(crtc);
4518
4519 intel_crtc_update_sarea(crtc, enable);
4520 }
4521
4522 static void intel_crtc_disable(struct drm_crtc *crtc)
4523 {
4524 struct drm_device *dev = crtc->dev;
4525 struct drm_connector *connector;
4526 struct drm_i915_private *dev_priv = dev->dev_private;
4527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4528
4529 /* crtc should still be enabled when we disable it. */
4530 WARN_ON(!crtc->enabled);
4531
4532 dev_priv->display.crtc_disable(crtc);
4533 intel_crtc->eld_vld = false;
4534 intel_crtc_update_sarea(crtc, false);
4535 dev_priv->display.off(crtc);
4536
4537 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4538 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4539 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4540
4541 if (crtc->primary->fb) {
4542 mutex_lock(&dev->struct_mutex);
4543 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4544 mutex_unlock(&dev->struct_mutex);
4545 crtc->primary->fb = NULL;
4546 }
4547
4548 /* Update computed state. */
4549 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4550 if (!connector->encoder || !connector->encoder->crtc)
4551 continue;
4552
4553 if (connector->encoder->crtc != crtc)
4554 continue;
4555
4556 connector->dpms = DRM_MODE_DPMS_OFF;
4557 to_intel_encoder(connector->encoder)->connectors_active = false;
4558 }
4559 }
4560
4561 void intel_encoder_destroy(struct drm_encoder *encoder)
4562 {
4563 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4564
4565 drm_encoder_cleanup(encoder);
4566 kfree(intel_encoder);
4567 }
4568
4569 /* Simple dpms helper for encoders with just one connector, no cloning and only
4570 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4571 * state of the entire output pipe. */
4572 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4573 {
4574 if (mode == DRM_MODE_DPMS_ON) {
4575 encoder->connectors_active = true;
4576
4577 intel_crtc_update_dpms(encoder->base.crtc);
4578 } else {
4579 encoder->connectors_active = false;
4580
4581 intel_crtc_update_dpms(encoder->base.crtc);
4582 }
4583 }
4584
4585 /* Cross check the actual hw state with our own modeset state tracking (and it's
4586 * internal consistency). */
4587 static void intel_connector_check_state(struct intel_connector *connector)
4588 {
4589 if (connector->get_hw_state(connector)) {
4590 struct intel_encoder *encoder = connector->encoder;
4591 struct drm_crtc *crtc;
4592 bool encoder_enabled;
4593 enum pipe pipe;
4594
4595 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4596 connector->base.base.id,
4597 drm_get_connector_name(&connector->base));
4598
4599 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4600 "wrong connector dpms state\n");
4601 WARN(connector->base.encoder != &encoder->base,
4602 "active connector not linked to encoder\n");
4603 WARN(!encoder->connectors_active,
4604 "encoder->connectors_active not set\n");
4605
4606 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4607 WARN(!encoder_enabled, "encoder not enabled\n");
4608 if (WARN_ON(!encoder->base.crtc))
4609 return;
4610
4611 crtc = encoder->base.crtc;
4612
4613 WARN(!crtc->enabled, "crtc not enabled\n");
4614 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4615 WARN(pipe != to_intel_crtc(crtc)->pipe,
4616 "encoder active on the wrong pipe\n");
4617 }
4618 }
4619
4620 /* Even simpler default implementation, if there's really no special case to
4621 * consider. */
4622 void intel_connector_dpms(struct drm_connector *connector, int mode)
4623 {
4624 /* All the simple cases only support two dpms states. */
4625 if (mode != DRM_MODE_DPMS_ON)
4626 mode = DRM_MODE_DPMS_OFF;
4627
4628 if (mode == connector->dpms)
4629 return;
4630
4631 connector->dpms = mode;
4632
4633 /* Only need to change hw state when actually enabled */
4634 if (connector->encoder)
4635 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4636
4637 intel_modeset_check_state(connector->dev);
4638 }
4639
4640 /* Simple connector->get_hw_state implementation for encoders that support only
4641 * one connector and no cloning and hence the encoder state determines the state
4642 * of the connector. */
4643 bool intel_connector_get_hw_state(struct intel_connector *connector)
4644 {
4645 enum pipe pipe = 0;
4646 struct intel_encoder *encoder = connector->encoder;
4647
4648 return encoder->get_hw_state(encoder, &pipe);
4649 }
4650
4651 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4652 struct intel_crtc_config *pipe_config)
4653 {
4654 struct drm_i915_private *dev_priv = dev->dev_private;
4655 struct intel_crtc *pipe_B_crtc =
4656 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4657
4658 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4659 pipe_name(pipe), pipe_config->fdi_lanes);
4660 if (pipe_config->fdi_lanes > 4) {
4661 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4662 pipe_name(pipe), pipe_config->fdi_lanes);
4663 return false;
4664 }
4665
4666 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4667 if (pipe_config->fdi_lanes > 2) {
4668 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4669 pipe_config->fdi_lanes);
4670 return false;
4671 } else {
4672 return true;
4673 }
4674 }
4675
4676 if (INTEL_INFO(dev)->num_pipes == 2)
4677 return true;
4678
4679 /* Ivybridge 3 pipe is really complicated */
4680 switch (pipe) {
4681 case PIPE_A:
4682 return true;
4683 case PIPE_B:
4684 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4685 pipe_config->fdi_lanes > 2) {
4686 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4687 pipe_name(pipe), pipe_config->fdi_lanes);
4688 return false;
4689 }
4690 return true;
4691 case PIPE_C:
4692 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4693 pipe_B_crtc->config.fdi_lanes <= 2) {
4694 if (pipe_config->fdi_lanes > 2) {
4695 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4696 pipe_name(pipe), pipe_config->fdi_lanes);
4697 return false;
4698 }
4699 } else {
4700 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4701 return false;
4702 }
4703 return true;
4704 default:
4705 BUG();
4706 }
4707 }
4708
4709 #define RETRY 1
4710 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4711 struct intel_crtc_config *pipe_config)
4712 {
4713 struct drm_device *dev = intel_crtc->base.dev;
4714 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4715 int lane, link_bw, fdi_dotclock;
4716 bool setup_ok, needs_recompute = false;
4717
4718 retry:
4719 /* FDI is a binary signal running at ~2.7GHz, encoding
4720 * each output octet as 10 bits. The actual frequency
4721 * is stored as a divider into a 100MHz clock, and the
4722 * mode pixel clock is stored in units of 1KHz.
4723 * Hence the bw of each lane in terms of the mode signal
4724 * is:
4725 */
4726 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4727
4728 fdi_dotclock = adjusted_mode->crtc_clock;
4729
4730 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4731 pipe_config->pipe_bpp);
4732
4733 pipe_config->fdi_lanes = lane;
4734
4735 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4736 link_bw, &pipe_config->fdi_m_n);
4737
4738 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4739 intel_crtc->pipe, pipe_config);
4740 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4741 pipe_config->pipe_bpp -= 2*3;
4742 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4743 pipe_config->pipe_bpp);
4744 needs_recompute = true;
4745 pipe_config->bw_constrained = true;
4746
4747 goto retry;
4748 }
4749
4750 if (needs_recompute)
4751 return RETRY;
4752
4753 return setup_ok ? 0 : -EINVAL;
4754 }
4755
4756 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4757 struct intel_crtc_config *pipe_config)
4758 {
4759 pipe_config->ips_enabled = i915.enable_ips &&
4760 hsw_crtc_supports_ips(crtc) &&
4761 pipe_config->pipe_bpp <= 24;
4762 }
4763
4764 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4765 struct intel_crtc_config *pipe_config)
4766 {
4767 struct drm_device *dev = crtc->base.dev;
4768 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4769
4770 /* FIXME should check pixel clock limits on all platforms */
4771 if (INTEL_INFO(dev)->gen < 4) {
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 int clock_limit =
4774 dev_priv->display.get_display_clock_speed(dev);
4775
4776 /*
4777 * Enable pixel doubling when the dot clock
4778 * is > 90% of the (display) core speed.
4779 *
4780 * GDG double wide on either pipe,
4781 * otherwise pipe A only.
4782 */
4783 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4784 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4785 clock_limit *= 2;
4786 pipe_config->double_wide = true;
4787 }
4788
4789 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4790 return -EINVAL;
4791 }
4792
4793 /*
4794 * Pipe horizontal size must be even in:
4795 * - DVO ganged mode
4796 * - LVDS dual channel mode
4797 * - Double wide pipe
4798 */
4799 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4800 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4801 pipe_config->pipe_src_w &= ~1;
4802
4803 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4804 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4805 */
4806 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4807 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4808 return -EINVAL;
4809
4810 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4811 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4812 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4813 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4814 * for lvds. */
4815 pipe_config->pipe_bpp = 8*3;
4816 }
4817
4818 if (HAS_IPS(dev))
4819 hsw_compute_ips_config(crtc, pipe_config);
4820
4821 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4822 * clock survives for now. */
4823 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4824 pipe_config->shared_dpll = crtc->config.shared_dpll;
4825
4826 if (pipe_config->has_pch_encoder)
4827 return ironlake_fdi_compute_config(crtc, pipe_config);
4828
4829 return 0;
4830 }
4831
4832 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4833 {
4834 return 400000; /* FIXME */
4835 }
4836
4837 static int i945_get_display_clock_speed(struct drm_device *dev)
4838 {
4839 return 400000;
4840 }
4841
4842 static int i915_get_display_clock_speed(struct drm_device *dev)
4843 {
4844 return 333000;
4845 }
4846
4847 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4848 {
4849 return 200000;
4850 }
4851
4852 static int pnv_get_display_clock_speed(struct drm_device *dev)
4853 {
4854 u16 gcfgc = 0;
4855
4856 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4857
4858 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4859 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4860 return 267000;
4861 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4862 return 333000;
4863 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4864 return 444000;
4865 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4866 return 200000;
4867 default:
4868 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4869 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4870 return 133000;
4871 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4872 return 167000;
4873 }
4874 }
4875
4876 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4877 {
4878 u16 gcfgc = 0;
4879
4880 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4881
4882 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4883 return 133000;
4884 else {
4885 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4886 case GC_DISPLAY_CLOCK_333_MHZ:
4887 return 333000;
4888 default:
4889 case GC_DISPLAY_CLOCK_190_200_MHZ:
4890 return 190000;
4891 }
4892 }
4893 }
4894
4895 static int i865_get_display_clock_speed(struct drm_device *dev)
4896 {
4897 return 266000;
4898 }
4899
4900 static int i855_get_display_clock_speed(struct drm_device *dev)
4901 {
4902 u16 hpllcc = 0;
4903 /* Assume that the hardware is in the high speed state. This
4904 * should be the default.
4905 */
4906 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4907 case GC_CLOCK_133_200:
4908 case GC_CLOCK_100_200:
4909 return 200000;
4910 case GC_CLOCK_166_250:
4911 return 250000;
4912 case GC_CLOCK_100_133:
4913 return 133000;
4914 }
4915
4916 /* Shouldn't happen */
4917 return 0;
4918 }
4919
4920 static int i830_get_display_clock_speed(struct drm_device *dev)
4921 {
4922 return 133000;
4923 }
4924
4925 static void
4926 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4927 {
4928 while (*num > DATA_LINK_M_N_MASK ||
4929 *den > DATA_LINK_M_N_MASK) {
4930 *num >>= 1;
4931 *den >>= 1;
4932 }
4933 }
4934
4935 static void compute_m_n(unsigned int m, unsigned int n,
4936 uint32_t *ret_m, uint32_t *ret_n)
4937 {
4938 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4939 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4940 intel_reduce_m_n_ratio(ret_m, ret_n);
4941 }
4942
4943 void
4944 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4945 int pixel_clock, int link_clock,
4946 struct intel_link_m_n *m_n)
4947 {
4948 m_n->tu = 64;
4949
4950 compute_m_n(bits_per_pixel * pixel_clock,
4951 link_clock * nlanes * 8,
4952 &m_n->gmch_m, &m_n->gmch_n);
4953
4954 compute_m_n(pixel_clock, link_clock,
4955 &m_n->link_m, &m_n->link_n);
4956 }
4957
4958 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4959 {
4960 if (i915.panel_use_ssc >= 0)
4961 return i915.panel_use_ssc != 0;
4962 return dev_priv->vbt.lvds_use_ssc
4963 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4964 }
4965
4966 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4967 {
4968 struct drm_device *dev = crtc->dev;
4969 struct drm_i915_private *dev_priv = dev->dev_private;
4970 int refclk;
4971
4972 if (IS_VALLEYVIEW(dev)) {
4973 refclk = 100000;
4974 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4975 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4976 refclk = dev_priv->vbt.lvds_ssc_freq;
4977 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4978 } else if (!IS_GEN2(dev)) {
4979 refclk = 96000;
4980 } else {
4981 refclk = 48000;
4982 }
4983
4984 return refclk;
4985 }
4986
4987 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4988 {
4989 return (1 << dpll->n) << 16 | dpll->m2;
4990 }
4991
4992 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4993 {
4994 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4995 }
4996
4997 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4998 intel_clock_t *reduced_clock)
4999 {
5000 struct drm_device *dev = crtc->base.dev;
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 int pipe = crtc->pipe;
5003 u32 fp, fp2 = 0;
5004
5005 if (IS_PINEVIEW(dev)) {
5006 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5007 if (reduced_clock)
5008 fp2 = pnv_dpll_compute_fp(reduced_clock);
5009 } else {
5010 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5011 if (reduced_clock)
5012 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5013 }
5014
5015 I915_WRITE(FP0(pipe), fp);
5016 crtc->config.dpll_hw_state.fp0 = fp;
5017
5018 crtc->lowfreq_avail = false;
5019 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5020 reduced_clock && i915.powersave) {
5021 I915_WRITE(FP1(pipe), fp2);
5022 crtc->config.dpll_hw_state.fp1 = fp2;
5023 crtc->lowfreq_avail = true;
5024 } else {
5025 I915_WRITE(FP1(pipe), fp);
5026 crtc->config.dpll_hw_state.fp1 = fp;
5027 }
5028 }
5029
5030 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5031 pipe)
5032 {
5033 u32 reg_val;
5034
5035 /*
5036 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5037 * and set it to a reasonable value instead.
5038 */
5039 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5040 reg_val &= 0xffffff00;
5041 reg_val |= 0x00000030;
5042 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5043
5044 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5045 reg_val &= 0x8cffffff;
5046 reg_val = 0x8c000000;
5047 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5048
5049 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5050 reg_val &= 0xffffff00;
5051 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5052
5053 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5054 reg_val &= 0x00ffffff;
5055 reg_val |= 0xb0000000;
5056 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5057 }
5058
5059 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5060 struct intel_link_m_n *m_n)
5061 {
5062 struct drm_device *dev = crtc->base.dev;
5063 struct drm_i915_private *dev_priv = dev->dev_private;
5064 int pipe = crtc->pipe;
5065
5066 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5067 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5068 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5069 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5070 }
5071
5072 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5073 struct intel_link_m_n *m_n)
5074 {
5075 struct drm_device *dev = crtc->base.dev;
5076 struct drm_i915_private *dev_priv = dev->dev_private;
5077 int pipe = crtc->pipe;
5078 enum transcoder transcoder = crtc->config.cpu_transcoder;
5079
5080 if (INTEL_INFO(dev)->gen >= 5) {
5081 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5082 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5083 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5084 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5085 } else {
5086 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5087 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5088 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5089 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5090 }
5091 }
5092
5093 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5094 {
5095 if (crtc->config.has_pch_encoder)
5096 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5097 else
5098 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5099 }
5100
5101 static void vlv_update_pll(struct intel_crtc *crtc)
5102 {
5103 struct drm_device *dev = crtc->base.dev;
5104 struct drm_i915_private *dev_priv = dev->dev_private;
5105 int pipe = crtc->pipe;
5106 u32 dpll, mdiv;
5107 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5108 u32 coreclk, reg_val, dpll_md;
5109
5110 mutex_lock(&dev_priv->dpio_lock);
5111
5112 bestn = crtc->config.dpll.n;
5113 bestm1 = crtc->config.dpll.m1;
5114 bestm2 = crtc->config.dpll.m2;
5115 bestp1 = crtc->config.dpll.p1;
5116 bestp2 = crtc->config.dpll.p2;
5117
5118 /* See eDP HDMI DPIO driver vbios notes doc */
5119
5120 /* PLL B needs special handling */
5121 if (pipe)
5122 vlv_pllb_recal_opamp(dev_priv, pipe);
5123
5124 /* Set up Tx target for periodic Rcomp update */
5125 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5126
5127 /* Disable target IRef on PLL */
5128 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5129 reg_val &= 0x00ffffff;
5130 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5131
5132 /* Disable fast lock */
5133 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5134
5135 /* Set idtafcrecal before PLL is enabled */
5136 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5137 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5138 mdiv |= ((bestn << DPIO_N_SHIFT));
5139 mdiv |= (1 << DPIO_K_SHIFT);
5140
5141 /*
5142 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5143 * but we don't support that).
5144 * Note: don't use the DAC post divider as it seems unstable.
5145 */
5146 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5147 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5148
5149 mdiv |= DPIO_ENABLE_CALIBRATION;
5150 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5151
5152 /* Set HBR and RBR LPF coefficients */
5153 if (crtc->config.port_clock == 162000 ||
5154 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5155 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5156 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5157 0x009f0003);
5158 else
5159 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5160 0x00d0000f);
5161
5162 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5163 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5164 /* Use SSC source */
5165 if (!pipe)
5166 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5167 0x0df40000);
5168 else
5169 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5170 0x0df70000);
5171 } else { /* HDMI or VGA */
5172 /* Use bend source */
5173 if (!pipe)
5174 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5175 0x0df70000);
5176 else
5177 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5178 0x0df40000);
5179 }
5180
5181 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5182 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5183 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5184 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5185 coreclk |= 0x01000000;
5186 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5187
5188 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5189
5190 /*
5191 * Enable DPIO clock input. We should never disable the reference
5192 * clock for pipe B, since VGA hotplug / manual detection depends
5193 * on it.
5194 */
5195 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5196 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5197 /* We should never disable this, set it here for state tracking */
5198 if (pipe == PIPE_B)
5199 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5200 dpll |= DPLL_VCO_ENABLE;
5201 crtc->config.dpll_hw_state.dpll = dpll;
5202
5203 dpll_md = (crtc->config.pixel_multiplier - 1)
5204 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5205 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5206
5207 mutex_unlock(&dev_priv->dpio_lock);
5208 }
5209
5210 static void i9xx_update_pll(struct intel_crtc *crtc,
5211 intel_clock_t *reduced_clock,
5212 int num_connectors)
5213 {
5214 struct drm_device *dev = crtc->base.dev;
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216 u32 dpll;
5217 bool is_sdvo;
5218 struct dpll *clock = &crtc->config.dpll;
5219
5220 i9xx_update_pll_dividers(crtc, reduced_clock);
5221
5222 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5223 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5224
5225 dpll = DPLL_VGA_MODE_DIS;
5226
5227 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5228 dpll |= DPLLB_MODE_LVDS;
5229 else
5230 dpll |= DPLLB_MODE_DAC_SERIAL;
5231
5232 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5233 dpll |= (crtc->config.pixel_multiplier - 1)
5234 << SDVO_MULTIPLIER_SHIFT_HIRES;
5235 }
5236
5237 if (is_sdvo)
5238 dpll |= DPLL_SDVO_HIGH_SPEED;
5239
5240 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5241 dpll |= DPLL_SDVO_HIGH_SPEED;
5242
5243 /* compute bitmask from p1 value */
5244 if (IS_PINEVIEW(dev))
5245 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5246 else {
5247 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5248 if (IS_G4X(dev) && reduced_clock)
5249 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5250 }
5251 switch (clock->p2) {
5252 case 5:
5253 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5254 break;
5255 case 7:
5256 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5257 break;
5258 case 10:
5259 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5260 break;
5261 case 14:
5262 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5263 break;
5264 }
5265 if (INTEL_INFO(dev)->gen >= 4)
5266 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5267
5268 if (crtc->config.sdvo_tv_clock)
5269 dpll |= PLL_REF_INPUT_TVCLKINBC;
5270 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5271 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5272 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5273 else
5274 dpll |= PLL_REF_INPUT_DREFCLK;
5275
5276 dpll |= DPLL_VCO_ENABLE;
5277 crtc->config.dpll_hw_state.dpll = dpll;
5278
5279 if (INTEL_INFO(dev)->gen >= 4) {
5280 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5281 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5282 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5283 }
5284 }
5285
5286 static void i8xx_update_pll(struct intel_crtc *crtc,
5287 intel_clock_t *reduced_clock,
5288 int num_connectors)
5289 {
5290 struct drm_device *dev = crtc->base.dev;
5291 struct drm_i915_private *dev_priv = dev->dev_private;
5292 u32 dpll;
5293 struct dpll *clock = &crtc->config.dpll;
5294
5295 i9xx_update_pll_dividers(crtc, reduced_clock);
5296
5297 dpll = DPLL_VGA_MODE_DIS;
5298
5299 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5300 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5301 } else {
5302 if (clock->p1 == 2)
5303 dpll |= PLL_P1_DIVIDE_BY_TWO;
5304 else
5305 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5306 if (clock->p2 == 4)
5307 dpll |= PLL_P2_DIVIDE_BY_4;
5308 }
5309
5310 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5311 dpll |= DPLL_DVO_2X_MODE;
5312
5313 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5314 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5315 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5316 else
5317 dpll |= PLL_REF_INPUT_DREFCLK;
5318
5319 dpll |= DPLL_VCO_ENABLE;
5320 crtc->config.dpll_hw_state.dpll = dpll;
5321 }
5322
5323 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5324 {
5325 struct drm_device *dev = intel_crtc->base.dev;
5326 struct drm_i915_private *dev_priv = dev->dev_private;
5327 enum pipe pipe = intel_crtc->pipe;
5328 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5329 struct drm_display_mode *adjusted_mode =
5330 &intel_crtc->config.adjusted_mode;
5331 uint32_t crtc_vtotal, crtc_vblank_end;
5332 int vsyncshift = 0;
5333
5334 /* We need to be careful not to changed the adjusted mode, for otherwise
5335 * the hw state checker will get angry at the mismatch. */
5336 crtc_vtotal = adjusted_mode->crtc_vtotal;
5337 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5338
5339 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5340 /* the chip adds 2 halflines automatically */
5341 crtc_vtotal -= 1;
5342 crtc_vblank_end -= 1;
5343
5344 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5345 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5346 else
5347 vsyncshift = adjusted_mode->crtc_hsync_start -
5348 adjusted_mode->crtc_htotal / 2;
5349 if (vsyncshift < 0)
5350 vsyncshift += adjusted_mode->crtc_htotal;
5351 }
5352
5353 if (INTEL_INFO(dev)->gen > 3)
5354 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5355
5356 I915_WRITE(HTOTAL(cpu_transcoder),
5357 (adjusted_mode->crtc_hdisplay - 1) |
5358 ((adjusted_mode->crtc_htotal - 1) << 16));
5359 I915_WRITE(HBLANK(cpu_transcoder),
5360 (adjusted_mode->crtc_hblank_start - 1) |
5361 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5362 I915_WRITE(HSYNC(cpu_transcoder),
5363 (adjusted_mode->crtc_hsync_start - 1) |
5364 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5365
5366 I915_WRITE(VTOTAL(cpu_transcoder),
5367 (adjusted_mode->crtc_vdisplay - 1) |
5368 ((crtc_vtotal - 1) << 16));
5369 I915_WRITE(VBLANK(cpu_transcoder),
5370 (adjusted_mode->crtc_vblank_start - 1) |
5371 ((crtc_vblank_end - 1) << 16));
5372 I915_WRITE(VSYNC(cpu_transcoder),
5373 (adjusted_mode->crtc_vsync_start - 1) |
5374 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5375
5376 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5377 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5378 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5379 * bits. */
5380 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5381 (pipe == PIPE_B || pipe == PIPE_C))
5382 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5383
5384 /* pipesrc controls the size that is scaled from, which should
5385 * always be the user's requested size.
5386 */
5387 I915_WRITE(PIPESRC(pipe),
5388 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5389 (intel_crtc->config.pipe_src_h - 1));
5390 }
5391
5392 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5393 struct intel_crtc_config *pipe_config)
5394 {
5395 struct drm_device *dev = crtc->base.dev;
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5398 uint32_t tmp;
5399
5400 tmp = I915_READ(HTOTAL(cpu_transcoder));
5401 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5402 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5403 tmp = I915_READ(HBLANK(cpu_transcoder));
5404 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5405 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5406 tmp = I915_READ(HSYNC(cpu_transcoder));
5407 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5408 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5409
5410 tmp = I915_READ(VTOTAL(cpu_transcoder));
5411 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5412 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5413 tmp = I915_READ(VBLANK(cpu_transcoder));
5414 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5415 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5416 tmp = I915_READ(VSYNC(cpu_transcoder));
5417 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5418 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5419
5420 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5421 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5422 pipe_config->adjusted_mode.crtc_vtotal += 1;
5423 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5424 }
5425
5426 tmp = I915_READ(PIPESRC(crtc->pipe));
5427 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5428 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5429
5430 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5431 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5432 }
5433
5434 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5435 struct intel_crtc_config *pipe_config)
5436 {
5437 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5438 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5439 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5440 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5441
5442 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5443 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5444 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5445 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5446
5447 mode->flags = pipe_config->adjusted_mode.flags;
5448
5449 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5450 mode->flags |= pipe_config->adjusted_mode.flags;
5451 }
5452
5453 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5454 {
5455 struct drm_device *dev = intel_crtc->base.dev;
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457 uint32_t pipeconf;
5458
5459 pipeconf = 0;
5460
5461 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5462 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5463 pipeconf |= PIPECONF_ENABLE;
5464
5465 if (intel_crtc->config.double_wide)
5466 pipeconf |= PIPECONF_DOUBLE_WIDE;
5467
5468 /* only g4x and later have fancy bpc/dither controls */
5469 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5470 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5471 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5472 pipeconf |= PIPECONF_DITHER_EN |
5473 PIPECONF_DITHER_TYPE_SP;
5474
5475 switch (intel_crtc->config.pipe_bpp) {
5476 case 18:
5477 pipeconf |= PIPECONF_6BPC;
5478 break;
5479 case 24:
5480 pipeconf |= PIPECONF_8BPC;
5481 break;
5482 case 30:
5483 pipeconf |= PIPECONF_10BPC;
5484 break;
5485 default:
5486 /* Case prevented by intel_choose_pipe_bpp_dither. */
5487 BUG();
5488 }
5489 }
5490
5491 if (HAS_PIPE_CXSR(dev)) {
5492 if (intel_crtc->lowfreq_avail) {
5493 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5494 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5495 } else {
5496 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5497 }
5498 }
5499
5500 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5501 if (INTEL_INFO(dev)->gen < 4 ||
5502 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5503 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5504 else
5505 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5506 } else
5507 pipeconf |= PIPECONF_PROGRESSIVE;
5508
5509 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5510 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5511
5512 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5513 POSTING_READ(PIPECONF(intel_crtc->pipe));
5514 }
5515
5516 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5517 int x, int y,
5518 struct drm_framebuffer *fb)
5519 {
5520 struct drm_device *dev = crtc->dev;
5521 struct drm_i915_private *dev_priv = dev->dev_private;
5522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5523 int pipe = intel_crtc->pipe;
5524 int plane = intel_crtc->plane;
5525 int refclk, num_connectors = 0;
5526 intel_clock_t clock, reduced_clock;
5527 u32 dspcntr;
5528 bool ok, has_reduced_clock = false;
5529 bool is_lvds = false, is_dsi = false;
5530 struct intel_encoder *encoder;
5531 const intel_limit_t *limit;
5532 int ret;
5533
5534 for_each_encoder_on_crtc(dev, crtc, encoder) {
5535 switch (encoder->type) {
5536 case INTEL_OUTPUT_LVDS:
5537 is_lvds = true;
5538 break;
5539 case INTEL_OUTPUT_DSI:
5540 is_dsi = true;
5541 break;
5542 }
5543
5544 num_connectors++;
5545 }
5546
5547 if (is_dsi)
5548 goto skip_dpll;
5549
5550 if (!intel_crtc->config.clock_set) {
5551 refclk = i9xx_get_refclk(crtc, num_connectors);
5552
5553 /*
5554 * Returns a set of divisors for the desired target clock with
5555 * the given refclk, or FALSE. The returned values represent
5556 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5557 * 2) / p1 / p2.
5558 */
5559 limit = intel_limit(crtc, refclk);
5560 ok = dev_priv->display.find_dpll(limit, crtc,
5561 intel_crtc->config.port_clock,
5562 refclk, NULL, &clock);
5563 if (!ok) {
5564 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5565 return -EINVAL;
5566 }
5567
5568 if (is_lvds && dev_priv->lvds_downclock_avail) {
5569 /*
5570 * Ensure we match the reduced clock's P to the target
5571 * clock. If the clocks don't match, we can't switch
5572 * the display clock by using the FP0/FP1. In such case
5573 * we will disable the LVDS downclock feature.
5574 */
5575 has_reduced_clock =
5576 dev_priv->display.find_dpll(limit, crtc,
5577 dev_priv->lvds_downclock,
5578 refclk, &clock,
5579 &reduced_clock);
5580 }
5581 /* Compat-code for transition, will disappear. */
5582 intel_crtc->config.dpll.n = clock.n;
5583 intel_crtc->config.dpll.m1 = clock.m1;
5584 intel_crtc->config.dpll.m2 = clock.m2;
5585 intel_crtc->config.dpll.p1 = clock.p1;
5586 intel_crtc->config.dpll.p2 = clock.p2;
5587 }
5588
5589 if (IS_GEN2(dev)) {
5590 i8xx_update_pll(intel_crtc,
5591 has_reduced_clock ? &reduced_clock : NULL,
5592 num_connectors);
5593 } else if (IS_VALLEYVIEW(dev)) {
5594 vlv_update_pll(intel_crtc);
5595 } else {
5596 i9xx_update_pll(intel_crtc,
5597 has_reduced_clock ? &reduced_clock : NULL,
5598 num_connectors);
5599 }
5600
5601 skip_dpll:
5602 /* Set up the display plane register */
5603 dspcntr = DISPPLANE_GAMMA_ENABLE;
5604
5605 if (!IS_VALLEYVIEW(dev)) {
5606 if (pipe == 0)
5607 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5608 else
5609 dspcntr |= DISPPLANE_SEL_PIPE_B;
5610 }
5611
5612 if (intel_crtc->config.has_dp_encoder)
5613 intel_dp_set_m_n(intel_crtc);
5614
5615 intel_set_pipe_timings(intel_crtc);
5616
5617 /* pipesrc and dspsize control the size that is scaled from,
5618 * which should always be the user's requested size.
5619 */
5620 I915_WRITE(DSPSIZE(plane),
5621 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5622 (intel_crtc->config.pipe_src_w - 1));
5623 I915_WRITE(DSPPOS(plane), 0);
5624
5625 i9xx_set_pipeconf(intel_crtc);
5626
5627 I915_WRITE(DSPCNTR(plane), dspcntr);
5628 POSTING_READ(DSPCNTR(plane));
5629
5630 ret = intel_pipe_set_base(crtc, x, y, fb);
5631
5632 return ret;
5633 }
5634
5635 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5636 struct intel_crtc_config *pipe_config)
5637 {
5638 struct drm_device *dev = crtc->base.dev;
5639 struct drm_i915_private *dev_priv = dev->dev_private;
5640 uint32_t tmp;
5641
5642 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5643 return;
5644
5645 tmp = I915_READ(PFIT_CONTROL);
5646 if (!(tmp & PFIT_ENABLE))
5647 return;
5648
5649 /* Check whether the pfit is attached to our pipe. */
5650 if (INTEL_INFO(dev)->gen < 4) {
5651 if (crtc->pipe != PIPE_B)
5652 return;
5653 } else {
5654 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5655 return;
5656 }
5657
5658 pipe_config->gmch_pfit.control = tmp;
5659 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5660 if (INTEL_INFO(dev)->gen < 5)
5661 pipe_config->gmch_pfit.lvds_border_bits =
5662 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5663 }
5664
5665 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5666 struct intel_crtc_config *pipe_config)
5667 {
5668 struct drm_device *dev = crtc->base.dev;
5669 struct drm_i915_private *dev_priv = dev->dev_private;
5670 int pipe = pipe_config->cpu_transcoder;
5671 intel_clock_t clock;
5672 u32 mdiv;
5673 int refclk = 100000;
5674
5675 mutex_lock(&dev_priv->dpio_lock);
5676 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5677 mutex_unlock(&dev_priv->dpio_lock);
5678
5679 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5680 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5681 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5682 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5683 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5684
5685 vlv_clock(refclk, &clock);
5686
5687 /* clock.dot is the fast clock */
5688 pipe_config->port_clock = clock.dot / 5;
5689 }
5690
5691 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5692 struct intel_plane_config *plane_config)
5693 {
5694 struct drm_device *dev = crtc->base.dev;
5695 struct drm_i915_private *dev_priv = dev->dev_private;
5696 u32 val, base, offset;
5697 int pipe = crtc->pipe, plane = crtc->plane;
5698 int fourcc, pixel_format;
5699 int aligned_height;
5700
5701 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5702 if (!crtc->base.primary->fb) {
5703 DRM_DEBUG_KMS("failed to alloc fb\n");
5704 return;
5705 }
5706
5707 val = I915_READ(DSPCNTR(plane));
5708
5709 if (INTEL_INFO(dev)->gen >= 4)
5710 if (val & DISPPLANE_TILED)
5711 plane_config->tiled = true;
5712
5713 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5714 fourcc = intel_format_to_fourcc(pixel_format);
5715 crtc->base.primary->fb->pixel_format = fourcc;
5716 crtc->base.primary->fb->bits_per_pixel =
5717 drm_format_plane_cpp(fourcc, 0) * 8;
5718
5719 if (INTEL_INFO(dev)->gen >= 4) {
5720 if (plane_config->tiled)
5721 offset = I915_READ(DSPTILEOFF(plane));
5722 else
5723 offset = I915_READ(DSPLINOFF(plane));
5724 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5725 } else {
5726 base = I915_READ(DSPADDR(plane));
5727 }
5728 plane_config->base = base;
5729
5730 val = I915_READ(PIPESRC(pipe));
5731 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5732 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5733
5734 val = I915_READ(DSPSTRIDE(pipe));
5735 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5736
5737 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5738 plane_config->tiled);
5739
5740 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5741 aligned_height, PAGE_SIZE);
5742
5743 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5744 pipe, plane, crtc->base.primary->fb->width,
5745 crtc->base.primary->fb->height,
5746 crtc->base.primary->fb->bits_per_pixel, base,
5747 crtc->base.primary->fb->pitches[0],
5748 plane_config->size);
5749
5750 }
5751
5752 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5753 struct intel_crtc_config *pipe_config)
5754 {
5755 struct drm_device *dev = crtc->base.dev;
5756 struct drm_i915_private *dev_priv = dev->dev_private;
5757 uint32_t tmp;
5758
5759 if (!intel_display_power_enabled(dev_priv,
5760 POWER_DOMAIN_PIPE(crtc->pipe)))
5761 return false;
5762
5763 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5764 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5765
5766 tmp = I915_READ(PIPECONF(crtc->pipe));
5767 if (!(tmp & PIPECONF_ENABLE))
5768 return false;
5769
5770 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5771 switch (tmp & PIPECONF_BPC_MASK) {
5772 case PIPECONF_6BPC:
5773 pipe_config->pipe_bpp = 18;
5774 break;
5775 case PIPECONF_8BPC:
5776 pipe_config->pipe_bpp = 24;
5777 break;
5778 case PIPECONF_10BPC:
5779 pipe_config->pipe_bpp = 30;
5780 break;
5781 default:
5782 break;
5783 }
5784 }
5785
5786 if (INTEL_INFO(dev)->gen < 4)
5787 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5788
5789 intel_get_pipe_timings(crtc, pipe_config);
5790
5791 i9xx_get_pfit_config(crtc, pipe_config);
5792
5793 if (INTEL_INFO(dev)->gen >= 4) {
5794 tmp = I915_READ(DPLL_MD(crtc->pipe));
5795 pipe_config->pixel_multiplier =
5796 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5797 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5798 pipe_config->dpll_hw_state.dpll_md = tmp;
5799 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5800 tmp = I915_READ(DPLL(crtc->pipe));
5801 pipe_config->pixel_multiplier =
5802 ((tmp & SDVO_MULTIPLIER_MASK)
5803 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5804 } else {
5805 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5806 * port and will be fixed up in the encoder->get_config
5807 * function. */
5808 pipe_config->pixel_multiplier = 1;
5809 }
5810 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5811 if (!IS_VALLEYVIEW(dev)) {
5812 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5813 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5814 } else {
5815 /* Mask out read-only status bits. */
5816 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5817 DPLL_PORTC_READY_MASK |
5818 DPLL_PORTB_READY_MASK);
5819 }
5820
5821 if (IS_VALLEYVIEW(dev))
5822 vlv_crtc_clock_get(crtc, pipe_config);
5823 else
5824 i9xx_crtc_clock_get(crtc, pipe_config);
5825
5826 return true;
5827 }
5828
5829 static void ironlake_init_pch_refclk(struct drm_device *dev)
5830 {
5831 struct drm_i915_private *dev_priv = dev->dev_private;
5832 struct drm_mode_config *mode_config = &dev->mode_config;
5833 struct intel_encoder *encoder;
5834 u32 val, final;
5835 bool has_lvds = false;
5836 bool has_cpu_edp = false;
5837 bool has_panel = false;
5838 bool has_ck505 = false;
5839 bool can_ssc = false;
5840
5841 /* We need to take the global config into account */
5842 list_for_each_entry(encoder, &mode_config->encoder_list,
5843 base.head) {
5844 switch (encoder->type) {
5845 case INTEL_OUTPUT_LVDS:
5846 has_panel = true;
5847 has_lvds = true;
5848 break;
5849 case INTEL_OUTPUT_EDP:
5850 has_panel = true;
5851 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5852 has_cpu_edp = true;
5853 break;
5854 }
5855 }
5856
5857 if (HAS_PCH_IBX(dev)) {
5858 has_ck505 = dev_priv->vbt.display_clock_mode;
5859 can_ssc = has_ck505;
5860 } else {
5861 has_ck505 = false;
5862 can_ssc = true;
5863 }
5864
5865 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5866 has_panel, has_lvds, has_ck505);
5867
5868 /* Ironlake: try to setup display ref clock before DPLL
5869 * enabling. This is only under driver's control after
5870 * PCH B stepping, previous chipset stepping should be
5871 * ignoring this setting.
5872 */
5873 val = I915_READ(PCH_DREF_CONTROL);
5874
5875 /* As we must carefully and slowly disable/enable each source in turn,
5876 * compute the final state we want first and check if we need to
5877 * make any changes at all.
5878 */
5879 final = val;
5880 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5881 if (has_ck505)
5882 final |= DREF_NONSPREAD_CK505_ENABLE;
5883 else
5884 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5885
5886 final &= ~DREF_SSC_SOURCE_MASK;
5887 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5888 final &= ~DREF_SSC1_ENABLE;
5889
5890 if (has_panel) {
5891 final |= DREF_SSC_SOURCE_ENABLE;
5892
5893 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5894 final |= DREF_SSC1_ENABLE;
5895
5896 if (has_cpu_edp) {
5897 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5898 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5899 else
5900 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5901 } else
5902 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5903 } else {
5904 final |= DREF_SSC_SOURCE_DISABLE;
5905 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5906 }
5907
5908 if (final == val)
5909 return;
5910
5911 /* Always enable nonspread source */
5912 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5913
5914 if (has_ck505)
5915 val |= DREF_NONSPREAD_CK505_ENABLE;
5916 else
5917 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5918
5919 if (has_panel) {
5920 val &= ~DREF_SSC_SOURCE_MASK;
5921 val |= DREF_SSC_SOURCE_ENABLE;
5922
5923 /* SSC must be turned on before enabling the CPU output */
5924 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5925 DRM_DEBUG_KMS("Using SSC on panel\n");
5926 val |= DREF_SSC1_ENABLE;
5927 } else
5928 val &= ~DREF_SSC1_ENABLE;
5929
5930 /* Get SSC going before enabling the outputs */
5931 I915_WRITE(PCH_DREF_CONTROL, val);
5932 POSTING_READ(PCH_DREF_CONTROL);
5933 udelay(200);
5934
5935 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5936
5937 /* Enable CPU source on CPU attached eDP */
5938 if (has_cpu_edp) {
5939 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5940 DRM_DEBUG_KMS("Using SSC on eDP\n");
5941 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5942 }
5943 else
5944 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5945 } else
5946 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5947
5948 I915_WRITE(PCH_DREF_CONTROL, val);
5949 POSTING_READ(PCH_DREF_CONTROL);
5950 udelay(200);
5951 } else {
5952 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5953
5954 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5955
5956 /* Turn off CPU output */
5957 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5958
5959 I915_WRITE(PCH_DREF_CONTROL, val);
5960 POSTING_READ(PCH_DREF_CONTROL);
5961 udelay(200);
5962
5963 /* Turn off the SSC source */
5964 val &= ~DREF_SSC_SOURCE_MASK;
5965 val |= DREF_SSC_SOURCE_DISABLE;
5966
5967 /* Turn off SSC1 */
5968 val &= ~DREF_SSC1_ENABLE;
5969
5970 I915_WRITE(PCH_DREF_CONTROL, val);
5971 POSTING_READ(PCH_DREF_CONTROL);
5972 udelay(200);
5973 }
5974
5975 BUG_ON(val != final);
5976 }
5977
5978 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5979 {
5980 uint32_t tmp;
5981
5982 tmp = I915_READ(SOUTH_CHICKEN2);
5983 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5984 I915_WRITE(SOUTH_CHICKEN2, tmp);
5985
5986 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5987 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5988 DRM_ERROR("FDI mPHY reset assert timeout\n");
5989
5990 tmp = I915_READ(SOUTH_CHICKEN2);
5991 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5992 I915_WRITE(SOUTH_CHICKEN2, tmp);
5993
5994 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5995 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5996 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5997 }
5998
5999 /* WaMPhyProgramming:hsw */
6000 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6001 {
6002 uint32_t tmp;
6003
6004 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6005 tmp &= ~(0xFF << 24);
6006 tmp |= (0x12 << 24);
6007 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6008
6009 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6010 tmp |= (1 << 11);
6011 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6012
6013 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6014 tmp |= (1 << 11);
6015 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6016
6017 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6018 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6019 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6020
6021 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6022 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6023 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6024
6025 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6026 tmp &= ~(7 << 13);
6027 tmp |= (5 << 13);
6028 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6029
6030 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6031 tmp &= ~(7 << 13);
6032 tmp |= (5 << 13);
6033 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6034
6035 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6036 tmp &= ~0xFF;
6037 tmp |= 0x1C;
6038 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6039
6040 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6041 tmp &= ~0xFF;
6042 tmp |= 0x1C;
6043 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6044
6045 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6046 tmp &= ~(0xFF << 16);
6047 tmp |= (0x1C << 16);
6048 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6049
6050 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6051 tmp &= ~(0xFF << 16);
6052 tmp |= (0x1C << 16);
6053 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6054
6055 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6056 tmp |= (1 << 27);
6057 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6058
6059 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6060 tmp |= (1 << 27);
6061 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6062
6063 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6064 tmp &= ~(0xF << 28);
6065 tmp |= (4 << 28);
6066 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6067
6068 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6069 tmp &= ~(0xF << 28);
6070 tmp |= (4 << 28);
6071 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6072 }
6073
6074 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6075 * Programming" based on the parameters passed:
6076 * - Sequence to enable CLKOUT_DP
6077 * - Sequence to enable CLKOUT_DP without spread
6078 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6079 */
6080 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6081 bool with_fdi)
6082 {
6083 struct drm_i915_private *dev_priv = dev->dev_private;
6084 uint32_t reg, tmp;
6085
6086 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6087 with_spread = true;
6088 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6089 with_fdi, "LP PCH doesn't have FDI\n"))
6090 with_fdi = false;
6091
6092 mutex_lock(&dev_priv->dpio_lock);
6093
6094 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6095 tmp &= ~SBI_SSCCTL_DISABLE;
6096 tmp |= SBI_SSCCTL_PATHALT;
6097 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6098
6099 udelay(24);
6100
6101 if (with_spread) {
6102 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6103 tmp &= ~SBI_SSCCTL_PATHALT;
6104 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6105
6106 if (with_fdi) {
6107 lpt_reset_fdi_mphy(dev_priv);
6108 lpt_program_fdi_mphy(dev_priv);
6109 }
6110 }
6111
6112 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6113 SBI_GEN0 : SBI_DBUFF0;
6114 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6115 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6116 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6117
6118 mutex_unlock(&dev_priv->dpio_lock);
6119 }
6120
6121 /* Sequence to disable CLKOUT_DP */
6122 static void lpt_disable_clkout_dp(struct drm_device *dev)
6123 {
6124 struct drm_i915_private *dev_priv = dev->dev_private;
6125 uint32_t reg, tmp;
6126
6127 mutex_lock(&dev_priv->dpio_lock);
6128
6129 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6130 SBI_GEN0 : SBI_DBUFF0;
6131 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6132 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6133 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6134
6135 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6136 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6137 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6138 tmp |= SBI_SSCCTL_PATHALT;
6139 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6140 udelay(32);
6141 }
6142 tmp |= SBI_SSCCTL_DISABLE;
6143 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6144 }
6145
6146 mutex_unlock(&dev_priv->dpio_lock);
6147 }
6148
6149 static void lpt_init_pch_refclk(struct drm_device *dev)
6150 {
6151 struct drm_mode_config *mode_config = &dev->mode_config;
6152 struct intel_encoder *encoder;
6153 bool has_vga = false;
6154
6155 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6156 switch (encoder->type) {
6157 case INTEL_OUTPUT_ANALOG:
6158 has_vga = true;
6159 break;
6160 }
6161 }
6162
6163 if (has_vga)
6164 lpt_enable_clkout_dp(dev, true, true);
6165 else
6166 lpt_disable_clkout_dp(dev);
6167 }
6168
6169 /*
6170 * Initialize reference clocks when the driver loads
6171 */
6172 void intel_init_pch_refclk(struct drm_device *dev)
6173 {
6174 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6175 ironlake_init_pch_refclk(dev);
6176 else if (HAS_PCH_LPT(dev))
6177 lpt_init_pch_refclk(dev);
6178 }
6179
6180 static int ironlake_get_refclk(struct drm_crtc *crtc)
6181 {
6182 struct drm_device *dev = crtc->dev;
6183 struct drm_i915_private *dev_priv = dev->dev_private;
6184 struct intel_encoder *encoder;
6185 int num_connectors = 0;
6186 bool is_lvds = false;
6187
6188 for_each_encoder_on_crtc(dev, crtc, encoder) {
6189 switch (encoder->type) {
6190 case INTEL_OUTPUT_LVDS:
6191 is_lvds = true;
6192 break;
6193 }
6194 num_connectors++;
6195 }
6196
6197 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6198 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6199 dev_priv->vbt.lvds_ssc_freq);
6200 return dev_priv->vbt.lvds_ssc_freq;
6201 }
6202
6203 return 120000;
6204 }
6205
6206 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6207 {
6208 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210 int pipe = intel_crtc->pipe;
6211 uint32_t val;
6212
6213 val = 0;
6214
6215 switch (intel_crtc->config.pipe_bpp) {
6216 case 18:
6217 val |= PIPECONF_6BPC;
6218 break;
6219 case 24:
6220 val |= PIPECONF_8BPC;
6221 break;
6222 case 30:
6223 val |= PIPECONF_10BPC;
6224 break;
6225 case 36:
6226 val |= PIPECONF_12BPC;
6227 break;
6228 default:
6229 /* Case prevented by intel_choose_pipe_bpp_dither. */
6230 BUG();
6231 }
6232
6233 if (intel_crtc->config.dither)
6234 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6235
6236 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6237 val |= PIPECONF_INTERLACED_ILK;
6238 else
6239 val |= PIPECONF_PROGRESSIVE;
6240
6241 if (intel_crtc->config.limited_color_range)
6242 val |= PIPECONF_COLOR_RANGE_SELECT;
6243
6244 I915_WRITE(PIPECONF(pipe), val);
6245 POSTING_READ(PIPECONF(pipe));
6246 }
6247
6248 /*
6249 * Set up the pipe CSC unit.
6250 *
6251 * Currently only full range RGB to limited range RGB conversion
6252 * is supported, but eventually this should handle various
6253 * RGB<->YCbCr scenarios as well.
6254 */
6255 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6256 {
6257 struct drm_device *dev = crtc->dev;
6258 struct drm_i915_private *dev_priv = dev->dev_private;
6259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6260 int pipe = intel_crtc->pipe;
6261 uint16_t coeff = 0x7800; /* 1.0 */
6262
6263 /*
6264 * TODO: Check what kind of values actually come out of the pipe
6265 * with these coeff/postoff values and adjust to get the best
6266 * accuracy. Perhaps we even need to take the bpc value into
6267 * consideration.
6268 */
6269
6270 if (intel_crtc->config.limited_color_range)
6271 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6272
6273 /*
6274 * GY/GU and RY/RU should be the other way around according
6275 * to BSpec, but reality doesn't agree. Just set them up in
6276 * a way that results in the correct picture.
6277 */
6278 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6279 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6280
6281 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6282 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6283
6284 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6285 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6286
6287 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6288 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6289 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6290
6291 if (INTEL_INFO(dev)->gen > 6) {
6292 uint16_t postoff = 0;
6293
6294 if (intel_crtc->config.limited_color_range)
6295 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6296
6297 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6298 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6299 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6300
6301 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6302 } else {
6303 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6304
6305 if (intel_crtc->config.limited_color_range)
6306 mode |= CSC_BLACK_SCREEN_OFFSET;
6307
6308 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6309 }
6310 }
6311
6312 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6313 {
6314 struct drm_device *dev = crtc->dev;
6315 struct drm_i915_private *dev_priv = dev->dev_private;
6316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6317 enum pipe pipe = intel_crtc->pipe;
6318 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6319 uint32_t val;
6320
6321 val = 0;
6322
6323 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6324 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6325
6326 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6327 val |= PIPECONF_INTERLACED_ILK;
6328 else
6329 val |= PIPECONF_PROGRESSIVE;
6330
6331 I915_WRITE(PIPECONF(cpu_transcoder), val);
6332 POSTING_READ(PIPECONF(cpu_transcoder));
6333
6334 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6335 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6336
6337 if (IS_BROADWELL(dev)) {
6338 val = 0;
6339
6340 switch (intel_crtc->config.pipe_bpp) {
6341 case 18:
6342 val |= PIPEMISC_DITHER_6_BPC;
6343 break;
6344 case 24:
6345 val |= PIPEMISC_DITHER_8_BPC;
6346 break;
6347 case 30:
6348 val |= PIPEMISC_DITHER_10_BPC;
6349 break;
6350 case 36:
6351 val |= PIPEMISC_DITHER_12_BPC;
6352 break;
6353 default:
6354 /* Case prevented by pipe_config_set_bpp. */
6355 BUG();
6356 }
6357
6358 if (intel_crtc->config.dither)
6359 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6360
6361 I915_WRITE(PIPEMISC(pipe), val);
6362 }
6363 }
6364
6365 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6366 intel_clock_t *clock,
6367 bool *has_reduced_clock,
6368 intel_clock_t *reduced_clock)
6369 {
6370 struct drm_device *dev = crtc->dev;
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 struct intel_encoder *intel_encoder;
6373 int refclk;
6374 const intel_limit_t *limit;
6375 bool ret, is_lvds = false;
6376
6377 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6378 switch (intel_encoder->type) {
6379 case INTEL_OUTPUT_LVDS:
6380 is_lvds = true;
6381 break;
6382 }
6383 }
6384
6385 refclk = ironlake_get_refclk(crtc);
6386
6387 /*
6388 * Returns a set of divisors for the desired target clock with the given
6389 * refclk, or FALSE. The returned values represent the clock equation:
6390 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6391 */
6392 limit = intel_limit(crtc, refclk);
6393 ret = dev_priv->display.find_dpll(limit, crtc,
6394 to_intel_crtc(crtc)->config.port_clock,
6395 refclk, NULL, clock);
6396 if (!ret)
6397 return false;
6398
6399 if (is_lvds && dev_priv->lvds_downclock_avail) {
6400 /*
6401 * Ensure we match the reduced clock's P to the target clock.
6402 * If the clocks don't match, we can't switch the display clock
6403 * by using the FP0/FP1. In such case we will disable the LVDS
6404 * downclock feature.
6405 */
6406 *has_reduced_clock =
6407 dev_priv->display.find_dpll(limit, crtc,
6408 dev_priv->lvds_downclock,
6409 refclk, clock,
6410 reduced_clock);
6411 }
6412
6413 return true;
6414 }
6415
6416 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6417 {
6418 /*
6419 * Account for spread spectrum to avoid
6420 * oversubscribing the link. Max center spread
6421 * is 2.5%; use 5% for safety's sake.
6422 */
6423 u32 bps = target_clock * bpp * 21 / 20;
6424 return DIV_ROUND_UP(bps, link_bw * 8);
6425 }
6426
6427 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6428 {
6429 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6430 }
6431
6432 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6433 u32 *fp,
6434 intel_clock_t *reduced_clock, u32 *fp2)
6435 {
6436 struct drm_crtc *crtc = &intel_crtc->base;
6437 struct drm_device *dev = crtc->dev;
6438 struct drm_i915_private *dev_priv = dev->dev_private;
6439 struct intel_encoder *intel_encoder;
6440 uint32_t dpll;
6441 int factor, num_connectors = 0;
6442 bool is_lvds = false, is_sdvo = false;
6443
6444 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6445 switch (intel_encoder->type) {
6446 case INTEL_OUTPUT_LVDS:
6447 is_lvds = true;
6448 break;
6449 case INTEL_OUTPUT_SDVO:
6450 case INTEL_OUTPUT_HDMI:
6451 is_sdvo = true;
6452 break;
6453 }
6454
6455 num_connectors++;
6456 }
6457
6458 /* Enable autotuning of the PLL clock (if permissible) */
6459 factor = 21;
6460 if (is_lvds) {
6461 if ((intel_panel_use_ssc(dev_priv) &&
6462 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6463 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6464 factor = 25;
6465 } else if (intel_crtc->config.sdvo_tv_clock)
6466 factor = 20;
6467
6468 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6469 *fp |= FP_CB_TUNE;
6470
6471 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6472 *fp2 |= FP_CB_TUNE;
6473
6474 dpll = 0;
6475
6476 if (is_lvds)
6477 dpll |= DPLLB_MODE_LVDS;
6478 else
6479 dpll |= DPLLB_MODE_DAC_SERIAL;
6480
6481 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6482 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6483
6484 if (is_sdvo)
6485 dpll |= DPLL_SDVO_HIGH_SPEED;
6486 if (intel_crtc->config.has_dp_encoder)
6487 dpll |= DPLL_SDVO_HIGH_SPEED;
6488
6489 /* compute bitmask from p1 value */
6490 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6491 /* also FPA1 */
6492 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6493
6494 switch (intel_crtc->config.dpll.p2) {
6495 case 5:
6496 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6497 break;
6498 case 7:
6499 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6500 break;
6501 case 10:
6502 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6503 break;
6504 case 14:
6505 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6506 break;
6507 }
6508
6509 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6510 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6511 else
6512 dpll |= PLL_REF_INPUT_DREFCLK;
6513
6514 return dpll | DPLL_VCO_ENABLE;
6515 }
6516
6517 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6518 int x, int y,
6519 struct drm_framebuffer *fb)
6520 {
6521 struct drm_device *dev = crtc->dev;
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6524 int pipe = intel_crtc->pipe;
6525 int plane = intel_crtc->plane;
6526 int num_connectors = 0;
6527 intel_clock_t clock, reduced_clock;
6528 u32 dpll = 0, fp = 0, fp2 = 0;
6529 bool ok, has_reduced_clock = false;
6530 bool is_lvds = false;
6531 struct intel_encoder *encoder;
6532 struct intel_shared_dpll *pll;
6533 int ret;
6534
6535 for_each_encoder_on_crtc(dev, crtc, encoder) {
6536 switch (encoder->type) {
6537 case INTEL_OUTPUT_LVDS:
6538 is_lvds = true;
6539 break;
6540 }
6541
6542 num_connectors++;
6543 }
6544
6545 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6546 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6547
6548 ok = ironlake_compute_clocks(crtc, &clock,
6549 &has_reduced_clock, &reduced_clock);
6550 if (!ok && !intel_crtc->config.clock_set) {
6551 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6552 return -EINVAL;
6553 }
6554 /* Compat-code for transition, will disappear. */
6555 if (!intel_crtc->config.clock_set) {
6556 intel_crtc->config.dpll.n = clock.n;
6557 intel_crtc->config.dpll.m1 = clock.m1;
6558 intel_crtc->config.dpll.m2 = clock.m2;
6559 intel_crtc->config.dpll.p1 = clock.p1;
6560 intel_crtc->config.dpll.p2 = clock.p2;
6561 }
6562
6563 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6564 if (intel_crtc->config.has_pch_encoder) {
6565 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6566 if (has_reduced_clock)
6567 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6568
6569 dpll = ironlake_compute_dpll(intel_crtc,
6570 &fp, &reduced_clock,
6571 has_reduced_clock ? &fp2 : NULL);
6572
6573 intel_crtc->config.dpll_hw_state.dpll = dpll;
6574 intel_crtc->config.dpll_hw_state.fp0 = fp;
6575 if (has_reduced_clock)
6576 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6577 else
6578 intel_crtc->config.dpll_hw_state.fp1 = fp;
6579
6580 pll = intel_get_shared_dpll(intel_crtc);
6581 if (pll == NULL) {
6582 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6583 pipe_name(pipe));
6584 return -EINVAL;
6585 }
6586 } else
6587 intel_put_shared_dpll(intel_crtc);
6588
6589 if (intel_crtc->config.has_dp_encoder)
6590 intel_dp_set_m_n(intel_crtc);
6591
6592 if (is_lvds && has_reduced_clock && i915.powersave)
6593 intel_crtc->lowfreq_avail = true;
6594 else
6595 intel_crtc->lowfreq_avail = false;
6596
6597 intel_set_pipe_timings(intel_crtc);
6598
6599 if (intel_crtc->config.has_pch_encoder) {
6600 intel_cpu_transcoder_set_m_n(intel_crtc,
6601 &intel_crtc->config.fdi_m_n);
6602 }
6603
6604 ironlake_set_pipeconf(crtc);
6605
6606 /* Set up the display plane register */
6607 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6608 POSTING_READ(DSPCNTR(plane));
6609
6610 ret = intel_pipe_set_base(crtc, x, y, fb);
6611
6612 return ret;
6613 }
6614
6615 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6616 struct intel_link_m_n *m_n)
6617 {
6618 struct drm_device *dev = crtc->base.dev;
6619 struct drm_i915_private *dev_priv = dev->dev_private;
6620 enum pipe pipe = crtc->pipe;
6621
6622 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6623 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6624 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6625 & ~TU_SIZE_MASK;
6626 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6627 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6628 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6629 }
6630
6631 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6632 enum transcoder transcoder,
6633 struct intel_link_m_n *m_n)
6634 {
6635 struct drm_device *dev = crtc->base.dev;
6636 struct drm_i915_private *dev_priv = dev->dev_private;
6637 enum pipe pipe = crtc->pipe;
6638
6639 if (INTEL_INFO(dev)->gen >= 5) {
6640 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6641 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6642 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6643 & ~TU_SIZE_MASK;
6644 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6645 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6646 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6647 } else {
6648 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6649 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6650 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6651 & ~TU_SIZE_MASK;
6652 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6653 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6654 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6655 }
6656 }
6657
6658 void intel_dp_get_m_n(struct intel_crtc *crtc,
6659 struct intel_crtc_config *pipe_config)
6660 {
6661 if (crtc->config.has_pch_encoder)
6662 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6663 else
6664 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6665 &pipe_config->dp_m_n);
6666 }
6667
6668 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6669 struct intel_crtc_config *pipe_config)
6670 {
6671 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6672 &pipe_config->fdi_m_n);
6673 }
6674
6675 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6676 struct intel_crtc_config *pipe_config)
6677 {
6678 struct drm_device *dev = crtc->base.dev;
6679 struct drm_i915_private *dev_priv = dev->dev_private;
6680 uint32_t tmp;
6681
6682 tmp = I915_READ(PF_CTL(crtc->pipe));
6683
6684 if (tmp & PF_ENABLE) {
6685 pipe_config->pch_pfit.enabled = true;
6686 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6687 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6688
6689 /* We currently do not free assignements of panel fitters on
6690 * ivb/hsw (since we don't use the higher upscaling modes which
6691 * differentiates them) so just WARN about this case for now. */
6692 if (IS_GEN7(dev)) {
6693 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6694 PF_PIPE_SEL_IVB(crtc->pipe));
6695 }
6696 }
6697 }
6698
6699 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6700 struct intel_plane_config *plane_config)
6701 {
6702 struct drm_device *dev = crtc->base.dev;
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 u32 val, base, offset;
6705 int pipe = crtc->pipe, plane = crtc->plane;
6706 int fourcc, pixel_format;
6707 int aligned_height;
6708
6709 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6710 if (!crtc->base.primary->fb) {
6711 DRM_DEBUG_KMS("failed to alloc fb\n");
6712 return;
6713 }
6714
6715 val = I915_READ(DSPCNTR(plane));
6716
6717 if (INTEL_INFO(dev)->gen >= 4)
6718 if (val & DISPPLANE_TILED)
6719 plane_config->tiled = true;
6720
6721 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6722 fourcc = intel_format_to_fourcc(pixel_format);
6723 crtc->base.primary->fb->pixel_format = fourcc;
6724 crtc->base.primary->fb->bits_per_pixel =
6725 drm_format_plane_cpp(fourcc, 0) * 8;
6726
6727 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6728 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6729 offset = I915_READ(DSPOFFSET(plane));
6730 } else {
6731 if (plane_config->tiled)
6732 offset = I915_READ(DSPTILEOFF(plane));
6733 else
6734 offset = I915_READ(DSPLINOFF(plane));
6735 }
6736 plane_config->base = base;
6737
6738 val = I915_READ(PIPESRC(pipe));
6739 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6740 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6741
6742 val = I915_READ(DSPSTRIDE(pipe));
6743 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6744
6745 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6746 plane_config->tiled);
6747
6748 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6749 aligned_height, PAGE_SIZE);
6750
6751 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6752 pipe, plane, crtc->base.primary->fb->width,
6753 crtc->base.primary->fb->height,
6754 crtc->base.primary->fb->bits_per_pixel, base,
6755 crtc->base.primary->fb->pitches[0],
6756 plane_config->size);
6757 }
6758
6759 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6760 struct intel_crtc_config *pipe_config)
6761 {
6762 struct drm_device *dev = crtc->base.dev;
6763 struct drm_i915_private *dev_priv = dev->dev_private;
6764 uint32_t tmp;
6765
6766 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6767 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6768
6769 tmp = I915_READ(PIPECONF(crtc->pipe));
6770 if (!(tmp & PIPECONF_ENABLE))
6771 return false;
6772
6773 switch (tmp & PIPECONF_BPC_MASK) {
6774 case PIPECONF_6BPC:
6775 pipe_config->pipe_bpp = 18;
6776 break;
6777 case PIPECONF_8BPC:
6778 pipe_config->pipe_bpp = 24;
6779 break;
6780 case PIPECONF_10BPC:
6781 pipe_config->pipe_bpp = 30;
6782 break;
6783 case PIPECONF_12BPC:
6784 pipe_config->pipe_bpp = 36;
6785 break;
6786 default:
6787 break;
6788 }
6789
6790 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6791 struct intel_shared_dpll *pll;
6792
6793 pipe_config->has_pch_encoder = true;
6794
6795 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6796 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6797 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6798
6799 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6800
6801 if (HAS_PCH_IBX(dev_priv->dev)) {
6802 pipe_config->shared_dpll =
6803 (enum intel_dpll_id) crtc->pipe;
6804 } else {
6805 tmp = I915_READ(PCH_DPLL_SEL);
6806 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6807 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6808 else
6809 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6810 }
6811
6812 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6813
6814 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6815 &pipe_config->dpll_hw_state));
6816
6817 tmp = pipe_config->dpll_hw_state.dpll;
6818 pipe_config->pixel_multiplier =
6819 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6820 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6821
6822 ironlake_pch_clock_get(crtc, pipe_config);
6823 } else {
6824 pipe_config->pixel_multiplier = 1;
6825 }
6826
6827 intel_get_pipe_timings(crtc, pipe_config);
6828
6829 ironlake_get_pfit_config(crtc, pipe_config);
6830
6831 return true;
6832 }
6833
6834 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6835 {
6836 struct drm_device *dev = dev_priv->dev;
6837 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6838 struct intel_crtc *crtc;
6839
6840 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6841 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6842 pipe_name(crtc->pipe));
6843
6844 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6845 WARN(plls->spll_refcount, "SPLL enabled\n");
6846 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6847 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6848 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6849 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6850 "CPU PWM1 enabled\n");
6851 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6852 "CPU PWM2 enabled\n");
6853 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6854 "PCH PWM1 enabled\n");
6855 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6856 "Utility pin enabled\n");
6857 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6858
6859 /*
6860 * In theory we can still leave IRQs enabled, as long as only the HPD
6861 * interrupts remain enabled. We used to check for that, but since it's
6862 * gen-specific and since we only disable LCPLL after we fully disable
6863 * the interrupts, the check below should be enough.
6864 */
6865 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
6866 }
6867
6868 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
6869 {
6870 struct drm_device *dev = dev_priv->dev;
6871
6872 if (IS_HASWELL(dev)) {
6873 mutex_lock(&dev_priv->rps.hw_lock);
6874 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
6875 val))
6876 DRM_ERROR("Failed to disable D_COMP\n");
6877 mutex_unlock(&dev_priv->rps.hw_lock);
6878 } else {
6879 I915_WRITE(D_COMP, val);
6880 }
6881 POSTING_READ(D_COMP);
6882 }
6883
6884 /*
6885 * This function implements pieces of two sequences from BSpec:
6886 * - Sequence for display software to disable LCPLL
6887 * - Sequence for display software to allow package C8+
6888 * The steps implemented here are just the steps that actually touch the LCPLL
6889 * register. Callers should take care of disabling all the display engine
6890 * functions, doing the mode unset, fixing interrupts, etc.
6891 */
6892 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6893 bool switch_to_fclk, bool allow_power_down)
6894 {
6895 uint32_t val;
6896
6897 assert_can_disable_lcpll(dev_priv);
6898
6899 val = I915_READ(LCPLL_CTL);
6900
6901 if (switch_to_fclk) {
6902 val |= LCPLL_CD_SOURCE_FCLK;
6903 I915_WRITE(LCPLL_CTL, val);
6904
6905 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6906 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6907 DRM_ERROR("Switching to FCLK failed\n");
6908
6909 val = I915_READ(LCPLL_CTL);
6910 }
6911
6912 val |= LCPLL_PLL_DISABLE;
6913 I915_WRITE(LCPLL_CTL, val);
6914 POSTING_READ(LCPLL_CTL);
6915
6916 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6917 DRM_ERROR("LCPLL still locked\n");
6918
6919 val = I915_READ(D_COMP);
6920 val |= D_COMP_COMP_DISABLE;
6921 hsw_write_dcomp(dev_priv, val);
6922 ndelay(100);
6923
6924 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6925 DRM_ERROR("D_COMP RCOMP still in progress\n");
6926
6927 if (allow_power_down) {
6928 val = I915_READ(LCPLL_CTL);
6929 val |= LCPLL_POWER_DOWN_ALLOW;
6930 I915_WRITE(LCPLL_CTL, val);
6931 POSTING_READ(LCPLL_CTL);
6932 }
6933 }
6934
6935 /*
6936 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6937 * source.
6938 */
6939 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6940 {
6941 uint32_t val;
6942 unsigned long irqflags;
6943
6944 val = I915_READ(LCPLL_CTL);
6945
6946 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6947 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6948 return;
6949
6950 /*
6951 * Make sure we're not on PC8 state before disabling PC8, otherwise
6952 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6953 *
6954 * The other problem is that hsw_restore_lcpll() is called as part of
6955 * the runtime PM resume sequence, so we can't just call
6956 * gen6_gt_force_wake_get() because that function calls
6957 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6958 * while we are on the resume sequence. So to solve this problem we have
6959 * to call special forcewake code that doesn't touch runtime PM and
6960 * doesn't enable the forcewake delayed work.
6961 */
6962 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6963 if (dev_priv->uncore.forcewake_count++ == 0)
6964 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6965 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6966
6967 if (val & LCPLL_POWER_DOWN_ALLOW) {
6968 val &= ~LCPLL_POWER_DOWN_ALLOW;
6969 I915_WRITE(LCPLL_CTL, val);
6970 POSTING_READ(LCPLL_CTL);
6971 }
6972
6973 val = I915_READ(D_COMP);
6974 val |= D_COMP_COMP_FORCE;
6975 val &= ~D_COMP_COMP_DISABLE;
6976 hsw_write_dcomp(dev_priv, val);
6977
6978 val = I915_READ(LCPLL_CTL);
6979 val &= ~LCPLL_PLL_DISABLE;
6980 I915_WRITE(LCPLL_CTL, val);
6981
6982 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6983 DRM_ERROR("LCPLL not locked yet\n");
6984
6985 if (val & LCPLL_CD_SOURCE_FCLK) {
6986 val = I915_READ(LCPLL_CTL);
6987 val &= ~LCPLL_CD_SOURCE_FCLK;
6988 I915_WRITE(LCPLL_CTL, val);
6989
6990 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6991 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6992 DRM_ERROR("Switching back to LCPLL failed\n");
6993 }
6994
6995 /* See the big comment above. */
6996 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6997 if (--dev_priv->uncore.forcewake_count == 0)
6998 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6999 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7000 }
7001
7002 /*
7003 * Package states C8 and deeper are really deep PC states that can only be
7004 * reached when all the devices on the system allow it, so even if the graphics
7005 * device allows PC8+, it doesn't mean the system will actually get to these
7006 * states. Our driver only allows PC8+ when going into runtime PM.
7007 *
7008 * The requirements for PC8+ are that all the outputs are disabled, the power
7009 * well is disabled and most interrupts are disabled, and these are also
7010 * requirements for runtime PM. When these conditions are met, we manually do
7011 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7012 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7013 * hang the machine.
7014 *
7015 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7016 * the state of some registers, so when we come back from PC8+ we need to
7017 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7018 * need to take care of the registers kept by RC6. Notice that this happens even
7019 * if we don't put the device in PCI D3 state (which is what currently happens
7020 * because of the runtime PM support).
7021 *
7022 * For more, read "Display Sequences for Package C8" on the hardware
7023 * documentation.
7024 */
7025 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7026 {
7027 struct drm_device *dev = dev_priv->dev;
7028 uint32_t val;
7029
7030 DRM_DEBUG_KMS("Enabling package C8+\n");
7031
7032 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7033 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7034 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7035 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7036 }
7037
7038 lpt_disable_clkout_dp(dev);
7039 intel_runtime_pm_disable_interrupts(dev);
7040 hsw_disable_lcpll(dev_priv, true, true);
7041 }
7042
7043 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7044 {
7045 struct drm_device *dev = dev_priv->dev;
7046 uint32_t val;
7047
7048 DRM_DEBUG_KMS("Disabling package C8+\n");
7049
7050 hsw_restore_lcpll(dev_priv);
7051 intel_runtime_pm_restore_interrupts(dev);
7052 lpt_init_pch_refclk(dev);
7053
7054 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7055 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7056 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7057 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7058 }
7059
7060 intel_prepare_ddi(dev);
7061 i915_gem_init_swizzling(dev);
7062 mutex_lock(&dev_priv->rps.hw_lock);
7063 gen6_update_ring_freq(dev);
7064 mutex_unlock(&dev_priv->rps.hw_lock);
7065 }
7066
7067 static void snb_modeset_global_resources(struct drm_device *dev)
7068 {
7069 modeset_update_crtc_power_domains(dev);
7070 }
7071
7072 static void haswell_modeset_global_resources(struct drm_device *dev)
7073 {
7074 modeset_update_crtc_power_domains(dev);
7075 }
7076
7077 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7078 int x, int y,
7079 struct drm_framebuffer *fb)
7080 {
7081 struct drm_device *dev = crtc->dev;
7082 struct drm_i915_private *dev_priv = dev->dev_private;
7083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7084 int plane = intel_crtc->plane;
7085 int ret;
7086
7087 if (!intel_ddi_pll_select(intel_crtc))
7088 return -EINVAL;
7089 intel_ddi_pll_enable(intel_crtc);
7090
7091 if (intel_crtc->config.has_dp_encoder)
7092 intel_dp_set_m_n(intel_crtc);
7093
7094 intel_crtc->lowfreq_avail = false;
7095
7096 intel_set_pipe_timings(intel_crtc);
7097
7098 if (intel_crtc->config.has_pch_encoder) {
7099 intel_cpu_transcoder_set_m_n(intel_crtc,
7100 &intel_crtc->config.fdi_m_n);
7101 }
7102
7103 haswell_set_pipeconf(crtc);
7104
7105 intel_set_pipe_csc(crtc);
7106
7107 /* Set up the display plane register */
7108 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7109 POSTING_READ(DSPCNTR(plane));
7110
7111 ret = intel_pipe_set_base(crtc, x, y, fb);
7112
7113 return ret;
7114 }
7115
7116 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7117 struct intel_crtc_config *pipe_config)
7118 {
7119 struct drm_device *dev = crtc->base.dev;
7120 struct drm_i915_private *dev_priv = dev->dev_private;
7121 enum intel_display_power_domain pfit_domain;
7122 uint32_t tmp;
7123
7124 if (!intel_display_power_enabled(dev_priv,
7125 POWER_DOMAIN_PIPE(crtc->pipe)))
7126 return false;
7127
7128 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7129 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7130
7131 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7132 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7133 enum pipe trans_edp_pipe;
7134 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7135 default:
7136 WARN(1, "unknown pipe linked to edp transcoder\n");
7137 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7138 case TRANS_DDI_EDP_INPUT_A_ON:
7139 trans_edp_pipe = PIPE_A;
7140 break;
7141 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7142 trans_edp_pipe = PIPE_B;
7143 break;
7144 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7145 trans_edp_pipe = PIPE_C;
7146 break;
7147 }
7148
7149 if (trans_edp_pipe == crtc->pipe)
7150 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7151 }
7152
7153 if (!intel_display_power_enabled(dev_priv,
7154 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7155 return false;
7156
7157 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7158 if (!(tmp & PIPECONF_ENABLE))
7159 return false;
7160
7161 /*
7162 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7163 * DDI E. So just check whether this pipe is wired to DDI E and whether
7164 * the PCH transcoder is on.
7165 */
7166 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7167 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7168 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7169 pipe_config->has_pch_encoder = true;
7170
7171 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7172 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7173 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7174
7175 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7176 }
7177
7178 intel_get_pipe_timings(crtc, pipe_config);
7179
7180 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7181 if (intel_display_power_enabled(dev_priv, pfit_domain))
7182 ironlake_get_pfit_config(crtc, pipe_config);
7183
7184 if (IS_HASWELL(dev))
7185 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7186 (I915_READ(IPS_CTL) & IPS_ENABLE);
7187
7188 pipe_config->pixel_multiplier = 1;
7189
7190 return true;
7191 }
7192
7193 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7194 int x, int y,
7195 struct drm_framebuffer *fb)
7196 {
7197 struct drm_device *dev = crtc->dev;
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199 struct intel_encoder *encoder;
7200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7201 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7202 int pipe = intel_crtc->pipe;
7203 int ret;
7204
7205 drm_vblank_pre_modeset(dev, pipe);
7206
7207 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7208
7209 drm_vblank_post_modeset(dev, pipe);
7210
7211 if (ret != 0)
7212 return ret;
7213
7214 for_each_encoder_on_crtc(dev, crtc, encoder) {
7215 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7216 encoder->base.base.id,
7217 drm_get_encoder_name(&encoder->base),
7218 mode->base.id, mode->name);
7219 encoder->mode_set(encoder);
7220 }
7221
7222 return 0;
7223 }
7224
7225 static struct {
7226 int clock;
7227 u32 config;
7228 } hdmi_audio_clock[] = {
7229 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7230 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7231 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7232 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7233 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7234 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7235 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7236 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7237 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7238 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7239 };
7240
7241 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7242 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7243 {
7244 int i;
7245
7246 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7247 if (mode->clock == hdmi_audio_clock[i].clock)
7248 break;
7249 }
7250
7251 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7252 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7253 i = 1;
7254 }
7255
7256 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7257 hdmi_audio_clock[i].clock,
7258 hdmi_audio_clock[i].config);
7259
7260 return hdmi_audio_clock[i].config;
7261 }
7262
7263 static bool intel_eld_uptodate(struct drm_connector *connector,
7264 int reg_eldv, uint32_t bits_eldv,
7265 int reg_elda, uint32_t bits_elda,
7266 int reg_edid)
7267 {
7268 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7269 uint8_t *eld = connector->eld;
7270 uint32_t i;
7271
7272 i = I915_READ(reg_eldv);
7273 i &= bits_eldv;
7274
7275 if (!eld[0])
7276 return !i;
7277
7278 if (!i)
7279 return false;
7280
7281 i = I915_READ(reg_elda);
7282 i &= ~bits_elda;
7283 I915_WRITE(reg_elda, i);
7284
7285 for (i = 0; i < eld[2]; i++)
7286 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7287 return false;
7288
7289 return true;
7290 }
7291
7292 static void g4x_write_eld(struct drm_connector *connector,
7293 struct drm_crtc *crtc,
7294 struct drm_display_mode *mode)
7295 {
7296 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7297 uint8_t *eld = connector->eld;
7298 uint32_t eldv;
7299 uint32_t len;
7300 uint32_t i;
7301
7302 i = I915_READ(G4X_AUD_VID_DID);
7303
7304 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7305 eldv = G4X_ELDV_DEVCL_DEVBLC;
7306 else
7307 eldv = G4X_ELDV_DEVCTG;
7308
7309 if (intel_eld_uptodate(connector,
7310 G4X_AUD_CNTL_ST, eldv,
7311 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7312 G4X_HDMIW_HDMIEDID))
7313 return;
7314
7315 i = I915_READ(G4X_AUD_CNTL_ST);
7316 i &= ~(eldv | G4X_ELD_ADDR);
7317 len = (i >> 9) & 0x1f; /* ELD buffer size */
7318 I915_WRITE(G4X_AUD_CNTL_ST, i);
7319
7320 if (!eld[0])
7321 return;
7322
7323 len = min_t(uint8_t, eld[2], len);
7324 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7325 for (i = 0; i < len; i++)
7326 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7327
7328 i = I915_READ(G4X_AUD_CNTL_ST);
7329 i |= eldv;
7330 I915_WRITE(G4X_AUD_CNTL_ST, i);
7331 }
7332
7333 static void haswell_write_eld(struct drm_connector *connector,
7334 struct drm_crtc *crtc,
7335 struct drm_display_mode *mode)
7336 {
7337 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7338 uint8_t *eld = connector->eld;
7339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7340 uint32_t eldv;
7341 uint32_t i;
7342 int len;
7343 int pipe = to_intel_crtc(crtc)->pipe;
7344 int tmp;
7345
7346 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7347 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7348 int aud_config = HSW_AUD_CFG(pipe);
7349 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7350
7351 /* Audio output enable */
7352 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7353 tmp = I915_READ(aud_cntrl_st2);
7354 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7355 I915_WRITE(aud_cntrl_st2, tmp);
7356 POSTING_READ(aud_cntrl_st2);
7357
7358 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7359
7360 /* Set ELD valid state */
7361 tmp = I915_READ(aud_cntrl_st2);
7362 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7363 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7364 I915_WRITE(aud_cntrl_st2, tmp);
7365 tmp = I915_READ(aud_cntrl_st2);
7366 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7367
7368 /* Enable HDMI mode */
7369 tmp = I915_READ(aud_config);
7370 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7371 /* clear N_programing_enable and N_value_index */
7372 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7373 I915_WRITE(aud_config, tmp);
7374
7375 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7376
7377 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7378 intel_crtc->eld_vld = true;
7379
7380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7381 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7382 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7383 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7384 } else {
7385 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7386 }
7387
7388 if (intel_eld_uptodate(connector,
7389 aud_cntrl_st2, eldv,
7390 aud_cntl_st, IBX_ELD_ADDRESS,
7391 hdmiw_hdmiedid))
7392 return;
7393
7394 i = I915_READ(aud_cntrl_st2);
7395 i &= ~eldv;
7396 I915_WRITE(aud_cntrl_st2, i);
7397
7398 if (!eld[0])
7399 return;
7400
7401 i = I915_READ(aud_cntl_st);
7402 i &= ~IBX_ELD_ADDRESS;
7403 I915_WRITE(aud_cntl_st, i);
7404 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7405 DRM_DEBUG_DRIVER("port num:%d\n", i);
7406
7407 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7408 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7409 for (i = 0; i < len; i++)
7410 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7411
7412 i = I915_READ(aud_cntrl_st2);
7413 i |= eldv;
7414 I915_WRITE(aud_cntrl_st2, i);
7415
7416 }
7417
7418 static void ironlake_write_eld(struct drm_connector *connector,
7419 struct drm_crtc *crtc,
7420 struct drm_display_mode *mode)
7421 {
7422 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7423 uint8_t *eld = connector->eld;
7424 uint32_t eldv;
7425 uint32_t i;
7426 int len;
7427 int hdmiw_hdmiedid;
7428 int aud_config;
7429 int aud_cntl_st;
7430 int aud_cntrl_st2;
7431 int pipe = to_intel_crtc(crtc)->pipe;
7432
7433 if (HAS_PCH_IBX(connector->dev)) {
7434 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7435 aud_config = IBX_AUD_CFG(pipe);
7436 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7437 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7438 } else if (IS_VALLEYVIEW(connector->dev)) {
7439 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7440 aud_config = VLV_AUD_CFG(pipe);
7441 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7442 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7443 } else {
7444 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7445 aud_config = CPT_AUD_CFG(pipe);
7446 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7447 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7448 }
7449
7450 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7451
7452 if (IS_VALLEYVIEW(connector->dev)) {
7453 struct intel_encoder *intel_encoder;
7454 struct intel_digital_port *intel_dig_port;
7455
7456 intel_encoder = intel_attached_encoder(connector);
7457 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7458 i = intel_dig_port->port;
7459 } else {
7460 i = I915_READ(aud_cntl_st);
7461 i = (i >> 29) & DIP_PORT_SEL_MASK;
7462 /* DIP_Port_Select, 0x1 = PortB */
7463 }
7464
7465 if (!i) {
7466 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7467 /* operate blindly on all ports */
7468 eldv = IBX_ELD_VALIDB;
7469 eldv |= IBX_ELD_VALIDB << 4;
7470 eldv |= IBX_ELD_VALIDB << 8;
7471 } else {
7472 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7473 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7474 }
7475
7476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7477 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7478 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7479 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7480 } else {
7481 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7482 }
7483
7484 if (intel_eld_uptodate(connector,
7485 aud_cntrl_st2, eldv,
7486 aud_cntl_st, IBX_ELD_ADDRESS,
7487 hdmiw_hdmiedid))
7488 return;
7489
7490 i = I915_READ(aud_cntrl_st2);
7491 i &= ~eldv;
7492 I915_WRITE(aud_cntrl_st2, i);
7493
7494 if (!eld[0])
7495 return;
7496
7497 i = I915_READ(aud_cntl_st);
7498 i &= ~IBX_ELD_ADDRESS;
7499 I915_WRITE(aud_cntl_st, i);
7500
7501 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7502 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7503 for (i = 0; i < len; i++)
7504 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7505
7506 i = I915_READ(aud_cntrl_st2);
7507 i |= eldv;
7508 I915_WRITE(aud_cntrl_st2, i);
7509 }
7510
7511 void intel_write_eld(struct drm_encoder *encoder,
7512 struct drm_display_mode *mode)
7513 {
7514 struct drm_crtc *crtc = encoder->crtc;
7515 struct drm_connector *connector;
7516 struct drm_device *dev = encoder->dev;
7517 struct drm_i915_private *dev_priv = dev->dev_private;
7518
7519 connector = drm_select_eld(encoder, mode);
7520 if (!connector)
7521 return;
7522
7523 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7524 connector->base.id,
7525 drm_get_connector_name(connector),
7526 connector->encoder->base.id,
7527 drm_get_encoder_name(connector->encoder));
7528
7529 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7530
7531 if (dev_priv->display.write_eld)
7532 dev_priv->display.write_eld(connector, crtc, mode);
7533 }
7534
7535 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7536 {
7537 struct drm_device *dev = crtc->dev;
7538 struct drm_i915_private *dev_priv = dev->dev_private;
7539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7540 bool visible = base != 0;
7541 u32 cntl;
7542
7543 if (intel_crtc->cursor_visible == visible)
7544 return;
7545
7546 cntl = I915_READ(_CURACNTR);
7547 if (visible) {
7548 /* On these chipsets we can only modify the base whilst
7549 * the cursor is disabled.
7550 */
7551 I915_WRITE(_CURABASE, base);
7552
7553 cntl &= ~(CURSOR_FORMAT_MASK);
7554 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7555 cntl |= CURSOR_ENABLE |
7556 CURSOR_GAMMA_ENABLE |
7557 CURSOR_FORMAT_ARGB;
7558 } else
7559 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7560 I915_WRITE(_CURACNTR, cntl);
7561
7562 intel_crtc->cursor_visible = visible;
7563 }
7564
7565 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7566 {
7567 struct drm_device *dev = crtc->dev;
7568 struct drm_i915_private *dev_priv = dev->dev_private;
7569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7570 int pipe = intel_crtc->pipe;
7571 bool visible = base != 0;
7572
7573 if (intel_crtc->cursor_visible != visible) {
7574 int16_t width = intel_crtc->cursor_width;
7575 uint32_t cntl = I915_READ(CURCNTR(pipe));
7576 if (base) {
7577 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7578 cntl |= MCURSOR_GAMMA_ENABLE;
7579
7580 switch (width) {
7581 case 64:
7582 cntl |= CURSOR_MODE_64_ARGB_AX;
7583 break;
7584 case 128:
7585 cntl |= CURSOR_MODE_128_ARGB_AX;
7586 break;
7587 case 256:
7588 cntl |= CURSOR_MODE_256_ARGB_AX;
7589 break;
7590 default:
7591 WARN_ON(1);
7592 return;
7593 }
7594 cntl |= pipe << 28; /* Connect to correct pipe */
7595 } else {
7596 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7597 cntl |= CURSOR_MODE_DISABLE;
7598 }
7599 I915_WRITE(CURCNTR(pipe), cntl);
7600
7601 intel_crtc->cursor_visible = visible;
7602 }
7603 /* and commit changes on next vblank */
7604 POSTING_READ(CURCNTR(pipe));
7605 I915_WRITE(CURBASE(pipe), base);
7606 POSTING_READ(CURBASE(pipe));
7607 }
7608
7609 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7610 {
7611 struct drm_device *dev = crtc->dev;
7612 struct drm_i915_private *dev_priv = dev->dev_private;
7613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7614 int pipe = intel_crtc->pipe;
7615 bool visible = base != 0;
7616
7617 if (intel_crtc->cursor_visible != visible) {
7618 int16_t width = intel_crtc->cursor_width;
7619 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7620 if (base) {
7621 cntl &= ~CURSOR_MODE;
7622 cntl |= MCURSOR_GAMMA_ENABLE;
7623 switch (width) {
7624 case 64:
7625 cntl |= CURSOR_MODE_64_ARGB_AX;
7626 break;
7627 case 128:
7628 cntl |= CURSOR_MODE_128_ARGB_AX;
7629 break;
7630 case 256:
7631 cntl |= CURSOR_MODE_256_ARGB_AX;
7632 break;
7633 default:
7634 WARN_ON(1);
7635 return;
7636 }
7637 } else {
7638 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7639 cntl |= CURSOR_MODE_DISABLE;
7640 }
7641 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7642 cntl |= CURSOR_PIPE_CSC_ENABLE;
7643 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7644 }
7645 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7646
7647 intel_crtc->cursor_visible = visible;
7648 }
7649 /* and commit changes on next vblank */
7650 POSTING_READ(CURCNTR_IVB(pipe));
7651 I915_WRITE(CURBASE_IVB(pipe), base);
7652 POSTING_READ(CURBASE_IVB(pipe));
7653 }
7654
7655 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7656 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7657 bool on)
7658 {
7659 struct drm_device *dev = crtc->dev;
7660 struct drm_i915_private *dev_priv = dev->dev_private;
7661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7662 int pipe = intel_crtc->pipe;
7663 int x = intel_crtc->cursor_x;
7664 int y = intel_crtc->cursor_y;
7665 u32 base = 0, pos = 0;
7666 bool visible;
7667
7668 if (on)
7669 base = intel_crtc->cursor_addr;
7670
7671 if (x >= intel_crtc->config.pipe_src_w)
7672 base = 0;
7673
7674 if (y >= intel_crtc->config.pipe_src_h)
7675 base = 0;
7676
7677 if (x < 0) {
7678 if (x + intel_crtc->cursor_width <= 0)
7679 base = 0;
7680
7681 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7682 x = -x;
7683 }
7684 pos |= x << CURSOR_X_SHIFT;
7685
7686 if (y < 0) {
7687 if (y + intel_crtc->cursor_height <= 0)
7688 base = 0;
7689
7690 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7691 y = -y;
7692 }
7693 pos |= y << CURSOR_Y_SHIFT;
7694
7695 visible = base != 0;
7696 if (!visible && !intel_crtc->cursor_visible)
7697 return;
7698
7699 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7700 I915_WRITE(CURPOS_IVB(pipe), pos);
7701 ivb_update_cursor(crtc, base);
7702 } else {
7703 I915_WRITE(CURPOS(pipe), pos);
7704 if (IS_845G(dev) || IS_I865G(dev))
7705 i845_update_cursor(crtc, base);
7706 else
7707 i9xx_update_cursor(crtc, base);
7708 }
7709 }
7710
7711 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7712 struct drm_file *file,
7713 uint32_t handle,
7714 uint32_t width, uint32_t height)
7715 {
7716 struct drm_device *dev = crtc->dev;
7717 struct drm_i915_private *dev_priv = dev->dev_private;
7718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7719 struct drm_i915_gem_object *obj;
7720 unsigned old_width;
7721 uint32_t addr;
7722 int ret;
7723
7724 /* if we want to turn off the cursor ignore width and height */
7725 if (!handle) {
7726 DRM_DEBUG_KMS("cursor off\n");
7727 addr = 0;
7728 obj = NULL;
7729 mutex_lock(&dev->struct_mutex);
7730 goto finish;
7731 }
7732
7733 /* Check for which cursor types we support */
7734 if (!((width == 64 && height == 64) ||
7735 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7736 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7737 DRM_DEBUG("Cursor dimension not supported\n");
7738 return -EINVAL;
7739 }
7740
7741 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7742 if (&obj->base == NULL)
7743 return -ENOENT;
7744
7745 if (obj->base.size < width * height * 4) {
7746 DRM_DEBUG_KMS("buffer is to small\n");
7747 ret = -ENOMEM;
7748 goto fail;
7749 }
7750
7751 /* we only need to pin inside GTT if cursor is non-phy */
7752 mutex_lock(&dev->struct_mutex);
7753 if (!INTEL_INFO(dev)->cursor_needs_physical) {
7754 unsigned alignment;
7755
7756 if (obj->tiling_mode) {
7757 DRM_DEBUG_KMS("cursor cannot be tiled\n");
7758 ret = -EINVAL;
7759 goto fail_locked;
7760 }
7761
7762 /* Note that the w/a also requires 2 PTE of padding following
7763 * the bo. We currently fill all unused PTE with the shadow
7764 * page and so we should always have valid PTE following the
7765 * cursor preventing the VT-d warning.
7766 */
7767 alignment = 0;
7768 if (need_vtd_wa(dev))
7769 alignment = 64*1024;
7770
7771 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7772 if (ret) {
7773 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7774 goto fail_locked;
7775 }
7776
7777 ret = i915_gem_object_put_fence(obj);
7778 if (ret) {
7779 DRM_DEBUG_KMS("failed to release fence for cursor");
7780 goto fail_unpin;
7781 }
7782
7783 addr = i915_gem_obj_ggtt_offset(obj);
7784 } else {
7785 int align = IS_I830(dev) ? 16 * 1024 : 256;
7786 ret = i915_gem_attach_phys_object(dev, obj,
7787 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7788 align);
7789 if (ret) {
7790 DRM_DEBUG_KMS("failed to attach phys object\n");
7791 goto fail_locked;
7792 }
7793 addr = obj->phys_obj->handle->busaddr;
7794 }
7795
7796 if (IS_GEN2(dev))
7797 I915_WRITE(CURSIZE, (height << 12) | width);
7798
7799 finish:
7800 if (intel_crtc->cursor_bo) {
7801 if (INTEL_INFO(dev)->cursor_needs_physical) {
7802 if (intel_crtc->cursor_bo != obj)
7803 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7804 } else
7805 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7806 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7807 }
7808
7809 mutex_unlock(&dev->struct_mutex);
7810
7811 old_width = intel_crtc->cursor_width;
7812
7813 intel_crtc->cursor_addr = addr;
7814 intel_crtc->cursor_bo = obj;
7815 intel_crtc->cursor_width = width;
7816 intel_crtc->cursor_height = height;
7817
7818 if (intel_crtc->active) {
7819 if (old_width != width)
7820 intel_update_watermarks(crtc);
7821 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7822 }
7823
7824 return 0;
7825 fail_unpin:
7826 i915_gem_object_unpin_from_display_plane(obj);
7827 fail_locked:
7828 mutex_unlock(&dev->struct_mutex);
7829 fail:
7830 drm_gem_object_unreference_unlocked(&obj->base);
7831 return ret;
7832 }
7833
7834 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7835 {
7836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7837
7838 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7839 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7840
7841 if (intel_crtc->active)
7842 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7843
7844 return 0;
7845 }
7846
7847 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7848 u16 *blue, uint32_t start, uint32_t size)
7849 {
7850 int end = (start + size > 256) ? 256 : start + size, i;
7851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7852
7853 for (i = start; i < end; i++) {
7854 intel_crtc->lut_r[i] = red[i] >> 8;
7855 intel_crtc->lut_g[i] = green[i] >> 8;
7856 intel_crtc->lut_b[i] = blue[i] >> 8;
7857 }
7858
7859 intel_crtc_load_lut(crtc);
7860 }
7861
7862 /* VESA 640x480x72Hz mode to set on the pipe */
7863 static struct drm_display_mode load_detect_mode = {
7864 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7865 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7866 };
7867
7868 struct drm_framebuffer *
7869 __intel_framebuffer_create(struct drm_device *dev,
7870 struct drm_mode_fb_cmd2 *mode_cmd,
7871 struct drm_i915_gem_object *obj)
7872 {
7873 struct intel_framebuffer *intel_fb;
7874 int ret;
7875
7876 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7877 if (!intel_fb) {
7878 drm_gem_object_unreference_unlocked(&obj->base);
7879 return ERR_PTR(-ENOMEM);
7880 }
7881
7882 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7883 if (ret)
7884 goto err;
7885
7886 return &intel_fb->base;
7887 err:
7888 drm_gem_object_unreference_unlocked(&obj->base);
7889 kfree(intel_fb);
7890
7891 return ERR_PTR(ret);
7892 }
7893
7894 static struct drm_framebuffer *
7895 intel_framebuffer_create(struct drm_device *dev,
7896 struct drm_mode_fb_cmd2 *mode_cmd,
7897 struct drm_i915_gem_object *obj)
7898 {
7899 struct drm_framebuffer *fb;
7900 int ret;
7901
7902 ret = i915_mutex_lock_interruptible(dev);
7903 if (ret)
7904 return ERR_PTR(ret);
7905 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7906 mutex_unlock(&dev->struct_mutex);
7907
7908 return fb;
7909 }
7910
7911 static u32
7912 intel_framebuffer_pitch_for_width(int width, int bpp)
7913 {
7914 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7915 return ALIGN(pitch, 64);
7916 }
7917
7918 static u32
7919 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7920 {
7921 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7922 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7923 }
7924
7925 static struct drm_framebuffer *
7926 intel_framebuffer_create_for_mode(struct drm_device *dev,
7927 struct drm_display_mode *mode,
7928 int depth, int bpp)
7929 {
7930 struct drm_i915_gem_object *obj;
7931 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7932
7933 obj = i915_gem_alloc_object(dev,
7934 intel_framebuffer_size_for_mode(mode, bpp));
7935 if (obj == NULL)
7936 return ERR_PTR(-ENOMEM);
7937
7938 mode_cmd.width = mode->hdisplay;
7939 mode_cmd.height = mode->vdisplay;
7940 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7941 bpp);
7942 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7943
7944 return intel_framebuffer_create(dev, &mode_cmd, obj);
7945 }
7946
7947 static struct drm_framebuffer *
7948 mode_fits_in_fbdev(struct drm_device *dev,
7949 struct drm_display_mode *mode)
7950 {
7951 #ifdef CONFIG_DRM_I915_FBDEV
7952 struct drm_i915_private *dev_priv = dev->dev_private;
7953 struct drm_i915_gem_object *obj;
7954 struct drm_framebuffer *fb;
7955
7956 if (!dev_priv->fbdev)
7957 return NULL;
7958
7959 if (!dev_priv->fbdev->fb)
7960 return NULL;
7961
7962 obj = dev_priv->fbdev->fb->obj;
7963 BUG_ON(!obj);
7964
7965 fb = &dev_priv->fbdev->fb->base;
7966 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7967 fb->bits_per_pixel))
7968 return NULL;
7969
7970 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7971 return NULL;
7972
7973 return fb;
7974 #else
7975 return NULL;
7976 #endif
7977 }
7978
7979 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7980 struct drm_display_mode *mode,
7981 struct intel_load_detect_pipe *old)
7982 {
7983 struct intel_crtc *intel_crtc;
7984 struct intel_encoder *intel_encoder =
7985 intel_attached_encoder(connector);
7986 struct drm_crtc *possible_crtc;
7987 struct drm_encoder *encoder = &intel_encoder->base;
7988 struct drm_crtc *crtc = NULL;
7989 struct drm_device *dev = encoder->dev;
7990 struct drm_framebuffer *fb;
7991 int i = -1;
7992
7993 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7994 connector->base.id, drm_get_connector_name(connector),
7995 encoder->base.id, drm_get_encoder_name(encoder));
7996
7997 /*
7998 * Algorithm gets a little messy:
7999 *
8000 * - if the connector already has an assigned crtc, use it (but make
8001 * sure it's on first)
8002 *
8003 * - try to find the first unused crtc that can drive this connector,
8004 * and use that if we find one
8005 */
8006
8007 /* See if we already have a CRTC for this connector */
8008 if (encoder->crtc) {
8009 crtc = encoder->crtc;
8010
8011 mutex_lock(&crtc->mutex);
8012
8013 old->dpms_mode = connector->dpms;
8014 old->load_detect_temp = false;
8015
8016 /* Make sure the crtc and connector are running */
8017 if (connector->dpms != DRM_MODE_DPMS_ON)
8018 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8019
8020 return true;
8021 }
8022
8023 /* Find an unused one (if possible) */
8024 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8025 i++;
8026 if (!(encoder->possible_crtcs & (1 << i)))
8027 continue;
8028 if (!possible_crtc->enabled) {
8029 crtc = possible_crtc;
8030 break;
8031 }
8032 }
8033
8034 /*
8035 * If we didn't find an unused CRTC, don't use any.
8036 */
8037 if (!crtc) {
8038 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8039 return false;
8040 }
8041
8042 mutex_lock(&crtc->mutex);
8043 intel_encoder->new_crtc = to_intel_crtc(crtc);
8044 to_intel_connector(connector)->new_encoder = intel_encoder;
8045
8046 intel_crtc = to_intel_crtc(crtc);
8047 intel_crtc->new_enabled = true;
8048 intel_crtc->new_config = &intel_crtc->config;
8049 old->dpms_mode = connector->dpms;
8050 old->load_detect_temp = true;
8051 old->release_fb = NULL;
8052
8053 if (!mode)
8054 mode = &load_detect_mode;
8055
8056 /* We need a framebuffer large enough to accommodate all accesses
8057 * that the plane may generate whilst we perform load detection.
8058 * We can not rely on the fbcon either being present (we get called
8059 * during its initialisation to detect all boot displays, or it may
8060 * not even exist) or that it is large enough to satisfy the
8061 * requested mode.
8062 */
8063 fb = mode_fits_in_fbdev(dev, mode);
8064 if (fb == NULL) {
8065 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8066 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8067 old->release_fb = fb;
8068 } else
8069 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8070 if (IS_ERR(fb)) {
8071 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8072 goto fail;
8073 }
8074
8075 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8076 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8077 if (old->release_fb)
8078 old->release_fb->funcs->destroy(old->release_fb);
8079 goto fail;
8080 }
8081
8082 /* let the connector get through one full cycle before testing */
8083 intel_wait_for_vblank(dev, intel_crtc->pipe);
8084 return true;
8085
8086 fail:
8087 intel_crtc->new_enabled = crtc->enabled;
8088 if (intel_crtc->new_enabled)
8089 intel_crtc->new_config = &intel_crtc->config;
8090 else
8091 intel_crtc->new_config = NULL;
8092 mutex_unlock(&crtc->mutex);
8093 return false;
8094 }
8095
8096 void intel_release_load_detect_pipe(struct drm_connector *connector,
8097 struct intel_load_detect_pipe *old)
8098 {
8099 struct intel_encoder *intel_encoder =
8100 intel_attached_encoder(connector);
8101 struct drm_encoder *encoder = &intel_encoder->base;
8102 struct drm_crtc *crtc = encoder->crtc;
8103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8104
8105 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8106 connector->base.id, drm_get_connector_name(connector),
8107 encoder->base.id, drm_get_encoder_name(encoder));
8108
8109 if (old->load_detect_temp) {
8110 to_intel_connector(connector)->new_encoder = NULL;
8111 intel_encoder->new_crtc = NULL;
8112 intel_crtc->new_enabled = false;
8113 intel_crtc->new_config = NULL;
8114 intel_set_mode(crtc, NULL, 0, 0, NULL);
8115
8116 if (old->release_fb) {
8117 drm_framebuffer_unregister_private(old->release_fb);
8118 drm_framebuffer_unreference(old->release_fb);
8119 }
8120
8121 mutex_unlock(&crtc->mutex);
8122 return;
8123 }
8124
8125 /* Switch crtc and encoder back off if necessary */
8126 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8127 connector->funcs->dpms(connector, old->dpms_mode);
8128
8129 mutex_unlock(&crtc->mutex);
8130 }
8131
8132 static int i9xx_pll_refclk(struct drm_device *dev,
8133 const struct intel_crtc_config *pipe_config)
8134 {
8135 struct drm_i915_private *dev_priv = dev->dev_private;
8136 u32 dpll = pipe_config->dpll_hw_state.dpll;
8137
8138 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8139 return dev_priv->vbt.lvds_ssc_freq;
8140 else if (HAS_PCH_SPLIT(dev))
8141 return 120000;
8142 else if (!IS_GEN2(dev))
8143 return 96000;
8144 else
8145 return 48000;
8146 }
8147
8148 /* Returns the clock of the currently programmed mode of the given pipe. */
8149 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8150 struct intel_crtc_config *pipe_config)
8151 {
8152 struct drm_device *dev = crtc->base.dev;
8153 struct drm_i915_private *dev_priv = dev->dev_private;
8154 int pipe = pipe_config->cpu_transcoder;
8155 u32 dpll = pipe_config->dpll_hw_state.dpll;
8156 u32 fp;
8157 intel_clock_t clock;
8158 int refclk = i9xx_pll_refclk(dev, pipe_config);
8159
8160 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8161 fp = pipe_config->dpll_hw_state.fp0;
8162 else
8163 fp = pipe_config->dpll_hw_state.fp1;
8164
8165 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8166 if (IS_PINEVIEW(dev)) {
8167 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8168 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8169 } else {
8170 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8171 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8172 }
8173
8174 if (!IS_GEN2(dev)) {
8175 if (IS_PINEVIEW(dev))
8176 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8177 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8178 else
8179 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8180 DPLL_FPA01_P1_POST_DIV_SHIFT);
8181
8182 switch (dpll & DPLL_MODE_MASK) {
8183 case DPLLB_MODE_DAC_SERIAL:
8184 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8185 5 : 10;
8186 break;
8187 case DPLLB_MODE_LVDS:
8188 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8189 7 : 14;
8190 break;
8191 default:
8192 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8193 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8194 return;
8195 }
8196
8197 if (IS_PINEVIEW(dev))
8198 pineview_clock(refclk, &clock);
8199 else
8200 i9xx_clock(refclk, &clock);
8201 } else {
8202 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8203 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8204
8205 if (is_lvds) {
8206 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8207 DPLL_FPA01_P1_POST_DIV_SHIFT);
8208
8209 if (lvds & LVDS_CLKB_POWER_UP)
8210 clock.p2 = 7;
8211 else
8212 clock.p2 = 14;
8213 } else {
8214 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8215 clock.p1 = 2;
8216 else {
8217 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8218 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8219 }
8220 if (dpll & PLL_P2_DIVIDE_BY_4)
8221 clock.p2 = 4;
8222 else
8223 clock.p2 = 2;
8224 }
8225
8226 i9xx_clock(refclk, &clock);
8227 }
8228
8229 /*
8230 * This value includes pixel_multiplier. We will use
8231 * port_clock to compute adjusted_mode.crtc_clock in the
8232 * encoder's get_config() function.
8233 */
8234 pipe_config->port_clock = clock.dot;
8235 }
8236
8237 int intel_dotclock_calculate(int link_freq,
8238 const struct intel_link_m_n *m_n)
8239 {
8240 /*
8241 * The calculation for the data clock is:
8242 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8243 * But we want to avoid losing precison if possible, so:
8244 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8245 *
8246 * and the link clock is simpler:
8247 * link_clock = (m * link_clock) / n
8248 */
8249
8250 if (!m_n->link_n)
8251 return 0;
8252
8253 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8254 }
8255
8256 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8257 struct intel_crtc_config *pipe_config)
8258 {
8259 struct drm_device *dev = crtc->base.dev;
8260
8261 /* read out port_clock from the DPLL */
8262 i9xx_crtc_clock_get(crtc, pipe_config);
8263
8264 /*
8265 * This value does not include pixel_multiplier.
8266 * We will check that port_clock and adjusted_mode.crtc_clock
8267 * agree once we know their relationship in the encoder's
8268 * get_config() function.
8269 */
8270 pipe_config->adjusted_mode.crtc_clock =
8271 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8272 &pipe_config->fdi_m_n);
8273 }
8274
8275 /** Returns the currently programmed mode of the given pipe. */
8276 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8277 struct drm_crtc *crtc)
8278 {
8279 struct drm_i915_private *dev_priv = dev->dev_private;
8280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8281 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8282 struct drm_display_mode *mode;
8283 struct intel_crtc_config pipe_config;
8284 int htot = I915_READ(HTOTAL(cpu_transcoder));
8285 int hsync = I915_READ(HSYNC(cpu_transcoder));
8286 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8287 int vsync = I915_READ(VSYNC(cpu_transcoder));
8288 enum pipe pipe = intel_crtc->pipe;
8289
8290 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8291 if (!mode)
8292 return NULL;
8293
8294 /*
8295 * Construct a pipe_config sufficient for getting the clock info
8296 * back out of crtc_clock_get.
8297 *
8298 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8299 * to use a real value here instead.
8300 */
8301 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8302 pipe_config.pixel_multiplier = 1;
8303 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8304 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8305 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8306 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8307
8308 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8309 mode->hdisplay = (htot & 0xffff) + 1;
8310 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8311 mode->hsync_start = (hsync & 0xffff) + 1;
8312 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8313 mode->vdisplay = (vtot & 0xffff) + 1;
8314 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8315 mode->vsync_start = (vsync & 0xffff) + 1;
8316 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8317
8318 drm_mode_set_name(mode);
8319
8320 return mode;
8321 }
8322
8323 static void intel_increase_pllclock(struct drm_crtc *crtc)
8324 {
8325 struct drm_device *dev = crtc->dev;
8326 struct drm_i915_private *dev_priv = dev->dev_private;
8327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8328 int pipe = intel_crtc->pipe;
8329 int dpll_reg = DPLL(pipe);
8330 int dpll;
8331
8332 if (HAS_PCH_SPLIT(dev))
8333 return;
8334
8335 if (!dev_priv->lvds_downclock_avail)
8336 return;
8337
8338 dpll = I915_READ(dpll_reg);
8339 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8340 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8341
8342 assert_panel_unlocked(dev_priv, pipe);
8343
8344 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8345 I915_WRITE(dpll_reg, dpll);
8346 intel_wait_for_vblank(dev, pipe);
8347
8348 dpll = I915_READ(dpll_reg);
8349 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8350 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8351 }
8352 }
8353
8354 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8355 {
8356 struct drm_device *dev = crtc->dev;
8357 struct drm_i915_private *dev_priv = dev->dev_private;
8358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8359
8360 if (HAS_PCH_SPLIT(dev))
8361 return;
8362
8363 if (!dev_priv->lvds_downclock_avail)
8364 return;
8365
8366 /*
8367 * Since this is called by a timer, we should never get here in
8368 * the manual case.
8369 */
8370 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8371 int pipe = intel_crtc->pipe;
8372 int dpll_reg = DPLL(pipe);
8373 int dpll;
8374
8375 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8376
8377 assert_panel_unlocked(dev_priv, pipe);
8378
8379 dpll = I915_READ(dpll_reg);
8380 dpll |= DISPLAY_RATE_SELECT_FPA1;
8381 I915_WRITE(dpll_reg, dpll);
8382 intel_wait_for_vblank(dev, pipe);
8383 dpll = I915_READ(dpll_reg);
8384 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8385 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8386 }
8387
8388 }
8389
8390 void intel_mark_busy(struct drm_device *dev)
8391 {
8392 struct drm_i915_private *dev_priv = dev->dev_private;
8393
8394 if (dev_priv->mm.busy)
8395 return;
8396
8397 intel_runtime_pm_get(dev_priv);
8398 i915_update_gfx_val(dev_priv);
8399 dev_priv->mm.busy = true;
8400 }
8401
8402 void intel_mark_idle(struct drm_device *dev)
8403 {
8404 struct drm_i915_private *dev_priv = dev->dev_private;
8405 struct drm_crtc *crtc;
8406
8407 if (!dev_priv->mm.busy)
8408 return;
8409
8410 dev_priv->mm.busy = false;
8411
8412 if (!i915.powersave)
8413 goto out;
8414
8415 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8416 if (!crtc->primary->fb)
8417 continue;
8418
8419 intel_decrease_pllclock(crtc);
8420 }
8421
8422 if (INTEL_INFO(dev)->gen >= 6)
8423 gen6_rps_idle(dev->dev_private);
8424
8425 out:
8426 intel_runtime_pm_put(dev_priv);
8427 }
8428
8429 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8430 struct intel_ring_buffer *ring)
8431 {
8432 struct drm_device *dev = obj->base.dev;
8433 struct drm_crtc *crtc;
8434
8435 if (!i915.powersave)
8436 return;
8437
8438 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8439 if (!crtc->primary->fb)
8440 continue;
8441
8442 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8443 continue;
8444
8445 intel_increase_pllclock(crtc);
8446 if (ring && intel_fbc_enabled(dev))
8447 ring->fbc_dirty = true;
8448 }
8449 }
8450
8451 static void intel_crtc_destroy(struct drm_crtc *crtc)
8452 {
8453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8454 struct drm_device *dev = crtc->dev;
8455 struct intel_unpin_work *work;
8456 unsigned long flags;
8457
8458 spin_lock_irqsave(&dev->event_lock, flags);
8459 work = intel_crtc->unpin_work;
8460 intel_crtc->unpin_work = NULL;
8461 spin_unlock_irqrestore(&dev->event_lock, flags);
8462
8463 if (work) {
8464 cancel_work_sync(&work->work);
8465 kfree(work);
8466 }
8467
8468 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8469
8470 drm_crtc_cleanup(crtc);
8471
8472 kfree(intel_crtc);
8473 }
8474
8475 static void intel_unpin_work_fn(struct work_struct *__work)
8476 {
8477 struct intel_unpin_work *work =
8478 container_of(__work, struct intel_unpin_work, work);
8479 struct drm_device *dev = work->crtc->dev;
8480
8481 mutex_lock(&dev->struct_mutex);
8482 intel_unpin_fb_obj(work->old_fb_obj);
8483 drm_gem_object_unreference(&work->pending_flip_obj->base);
8484 drm_gem_object_unreference(&work->old_fb_obj->base);
8485
8486 intel_update_fbc(dev);
8487 mutex_unlock(&dev->struct_mutex);
8488
8489 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8490 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8491
8492 kfree(work);
8493 }
8494
8495 static void do_intel_finish_page_flip(struct drm_device *dev,
8496 struct drm_crtc *crtc)
8497 {
8498 struct drm_i915_private *dev_priv = dev->dev_private;
8499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8500 struct intel_unpin_work *work;
8501 unsigned long flags;
8502
8503 /* Ignore early vblank irqs */
8504 if (intel_crtc == NULL)
8505 return;
8506
8507 spin_lock_irqsave(&dev->event_lock, flags);
8508 work = intel_crtc->unpin_work;
8509
8510 /* Ensure we don't miss a work->pending update ... */
8511 smp_rmb();
8512
8513 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8514 spin_unlock_irqrestore(&dev->event_lock, flags);
8515 return;
8516 }
8517
8518 /* and that the unpin work is consistent wrt ->pending. */
8519 smp_rmb();
8520
8521 intel_crtc->unpin_work = NULL;
8522
8523 if (work->event)
8524 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8525
8526 drm_vblank_put(dev, intel_crtc->pipe);
8527
8528 spin_unlock_irqrestore(&dev->event_lock, flags);
8529
8530 wake_up_all(&dev_priv->pending_flip_queue);
8531
8532 queue_work(dev_priv->wq, &work->work);
8533
8534 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8535 }
8536
8537 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8538 {
8539 struct drm_i915_private *dev_priv = dev->dev_private;
8540 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8541
8542 do_intel_finish_page_flip(dev, crtc);
8543 }
8544
8545 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8546 {
8547 struct drm_i915_private *dev_priv = dev->dev_private;
8548 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8549
8550 do_intel_finish_page_flip(dev, crtc);
8551 }
8552
8553 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8554 {
8555 struct drm_i915_private *dev_priv = dev->dev_private;
8556 struct intel_crtc *intel_crtc =
8557 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8558 unsigned long flags;
8559
8560 /* NB: An MMIO update of the plane base pointer will also
8561 * generate a page-flip completion irq, i.e. every modeset
8562 * is also accompanied by a spurious intel_prepare_page_flip().
8563 */
8564 spin_lock_irqsave(&dev->event_lock, flags);
8565 if (intel_crtc->unpin_work)
8566 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8567 spin_unlock_irqrestore(&dev->event_lock, flags);
8568 }
8569
8570 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8571 {
8572 /* Ensure that the work item is consistent when activating it ... */
8573 smp_wmb();
8574 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8575 /* and that it is marked active as soon as the irq could fire. */
8576 smp_wmb();
8577 }
8578
8579 static int intel_gen2_queue_flip(struct drm_device *dev,
8580 struct drm_crtc *crtc,
8581 struct drm_framebuffer *fb,
8582 struct drm_i915_gem_object *obj,
8583 uint32_t flags)
8584 {
8585 struct drm_i915_private *dev_priv = dev->dev_private;
8586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8587 u32 flip_mask;
8588 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8589 int ret;
8590
8591 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8592 if (ret)
8593 goto err;
8594
8595 ret = intel_ring_begin(ring, 6);
8596 if (ret)
8597 goto err_unpin;
8598
8599 /* Can't queue multiple flips, so wait for the previous
8600 * one to finish before executing the next.
8601 */
8602 if (intel_crtc->plane)
8603 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8604 else
8605 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8606 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8607 intel_ring_emit(ring, MI_NOOP);
8608 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8609 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8610 intel_ring_emit(ring, fb->pitches[0]);
8611 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8612 intel_ring_emit(ring, 0); /* aux display base address, unused */
8613
8614 intel_mark_page_flip_active(intel_crtc);
8615 __intel_ring_advance(ring);
8616 return 0;
8617
8618 err_unpin:
8619 intel_unpin_fb_obj(obj);
8620 err:
8621 return ret;
8622 }
8623
8624 static int intel_gen3_queue_flip(struct drm_device *dev,
8625 struct drm_crtc *crtc,
8626 struct drm_framebuffer *fb,
8627 struct drm_i915_gem_object *obj,
8628 uint32_t flags)
8629 {
8630 struct drm_i915_private *dev_priv = dev->dev_private;
8631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8632 u32 flip_mask;
8633 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8634 int ret;
8635
8636 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8637 if (ret)
8638 goto err;
8639
8640 ret = intel_ring_begin(ring, 6);
8641 if (ret)
8642 goto err_unpin;
8643
8644 if (intel_crtc->plane)
8645 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8646 else
8647 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8648 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8649 intel_ring_emit(ring, MI_NOOP);
8650 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8651 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8652 intel_ring_emit(ring, fb->pitches[0]);
8653 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8654 intel_ring_emit(ring, MI_NOOP);
8655
8656 intel_mark_page_flip_active(intel_crtc);
8657 __intel_ring_advance(ring);
8658 return 0;
8659
8660 err_unpin:
8661 intel_unpin_fb_obj(obj);
8662 err:
8663 return ret;
8664 }
8665
8666 static int intel_gen4_queue_flip(struct drm_device *dev,
8667 struct drm_crtc *crtc,
8668 struct drm_framebuffer *fb,
8669 struct drm_i915_gem_object *obj,
8670 uint32_t flags)
8671 {
8672 struct drm_i915_private *dev_priv = dev->dev_private;
8673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8674 uint32_t pf, pipesrc;
8675 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8676 int ret;
8677
8678 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8679 if (ret)
8680 goto err;
8681
8682 ret = intel_ring_begin(ring, 4);
8683 if (ret)
8684 goto err_unpin;
8685
8686 /* i965+ uses the linear or tiled offsets from the
8687 * Display Registers (which do not change across a page-flip)
8688 * so we need only reprogram the base address.
8689 */
8690 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8691 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8692 intel_ring_emit(ring, fb->pitches[0]);
8693 intel_ring_emit(ring,
8694 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8695 obj->tiling_mode);
8696
8697 /* XXX Enabling the panel-fitter across page-flip is so far
8698 * untested on non-native modes, so ignore it for now.
8699 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8700 */
8701 pf = 0;
8702 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8703 intel_ring_emit(ring, pf | pipesrc);
8704
8705 intel_mark_page_flip_active(intel_crtc);
8706 __intel_ring_advance(ring);
8707 return 0;
8708
8709 err_unpin:
8710 intel_unpin_fb_obj(obj);
8711 err:
8712 return ret;
8713 }
8714
8715 static int intel_gen6_queue_flip(struct drm_device *dev,
8716 struct drm_crtc *crtc,
8717 struct drm_framebuffer *fb,
8718 struct drm_i915_gem_object *obj,
8719 uint32_t flags)
8720 {
8721 struct drm_i915_private *dev_priv = dev->dev_private;
8722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8723 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8724 uint32_t pf, pipesrc;
8725 int ret;
8726
8727 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8728 if (ret)
8729 goto err;
8730
8731 ret = intel_ring_begin(ring, 4);
8732 if (ret)
8733 goto err_unpin;
8734
8735 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8736 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8737 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8738 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8739
8740 /* Contrary to the suggestions in the documentation,
8741 * "Enable Panel Fitter" does not seem to be required when page
8742 * flipping with a non-native mode, and worse causes a normal
8743 * modeset to fail.
8744 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8745 */
8746 pf = 0;
8747 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8748 intel_ring_emit(ring, pf | pipesrc);
8749
8750 intel_mark_page_flip_active(intel_crtc);
8751 __intel_ring_advance(ring);
8752 return 0;
8753
8754 err_unpin:
8755 intel_unpin_fb_obj(obj);
8756 err:
8757 return ret;
8758 }
8759
8760 static int intel_gen7_queue_flip(struct drm_device *dev,
8761 struct drm_crtc *crtc,
8762 struct drm_framebuffer *fb,
8763 struct drm_i915_gem_object *obj,
8764 uint32_t flags)
8765 {
8766 struct drm_i915_private *dev_priv = dev->dev_private;
8767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8768 struct intel_ring_buffer *ring;
8769 uint32_t plane_bit = 0;
8770 int len, ret;
8771
8772 ring = obj->ring;
8773 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8774 ring = &dev_priv->ring[BCS];
8775
8776 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8777 if (ret)
8778 goto err;
8779
8780 switch(intel_crtc->plane) {
8781 case PLANE_A:
8782 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8783 break;
8784 case PLANE_B:
8785 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8786 break;
8787 case PLANE_C:
8788 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8789 break;
8790 default:
8791 WARN_ONCE(1, "unknown plane in flip command\n");
8792 ret = -ENODEV;
8793 goto err_unpin;
8794 }
8795
8796 len = 4;
8797 if (ring->id == RCS) {
8798 len += 6;
8799 /*
8800 * On Gen 8, SRM is now taking an extra dword to accommodate
8801 * 48bits addresses, and we need a NOOP for the batch size to
8802 * stay even.
8803 */
8804 if (IS_GEN8(dev))
8805 len += 2;
8806 }
8807
8808 /*
8809 * BSpec MI_DISPLAY_FLIP for IVB:
8810 * "The full packet must be contained within the same cache line."
8811 *
8812 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8813 * cacheline, if we ever start emitting more commands before
8814 * the MI_DISPLAY_FLIP we may need to first emit everything else,
8815 * then do the cacheline alignment, and finally emit the
8816 * MI_DISPLAY_FLIP.
8817 */
8818 ret = intel_ring_cacheline_align(ring);
8819 if (ret)
8820 goto err_unpin;
8821
8822 ret = intel_ring_begin(ring, len);
8823 if (ret)
8824 goto err_unpin;
8825
8826 /* Unmask the flip-done completion message. Note that the bspec says that
8827 * we should do this for both the BCS and RCS, and that we must not unmask
8828 * more than one flip event at any time (or ensure that one flip message
8829 * can be sent by waiting for flip-done prior to queueing new flips).
8830 * Experimentation says that BCS works despite DERRMR masking all
8831 * flip-done completion events and that unmasking all planes at once
8832 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8833 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8834 */
8835 if (ring->id == RCS) {
8836 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8837 intel_ring_emit(ring, DERRMR);
8838 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8839 DERRMR_PIPEB_PRI_FLIP_DONE |
8840 DERRMR_PIPEC_PRI_FLIP_DONE));
8841 if (IS_GEN8(dev))
8842 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
8843 MI_SRM_LRM_GLOBAL_GTT);
8844 else
8845 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8846 MI_SRM_LRM_GLOBAL_GTT);
8847 intel_ring_emit(ring, DERRMR);
8848 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8849 if (IS_GEN8(dev)) {
8850 intel_ring_emit(ring, 0);
8851 intel_ring_emit(ring, MI_NOOP);
8852 }
8853 }
8854
8855 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8856 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8857 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8858 intel_ring_emit(ring, (MI_NOOP));
8859
8860 intel_mark_page_flip_active(intel_crtc);
8861 __intel_ring_advance(ring);
8862 return 0;
8863
8864 err_unpin:
8865 intel_unpin_fb_obj(obj);
8866 err:
8867 return ret;
8868 }
8869
8870 static int intel_default_queue_flip(struct drm_device *dev,
8871 struct drm_crtc *crtc,
8872 struct drm_framebuffer *fb,
8873 struct drm_i915_gem_object *obj,
8874 uint32_t flags)
8875 {
8876 return -ENODEV;
8877 }
8878
8879 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8880 struct drm_framebuffer *fb,
8881 struct drm_pending_vblank_event *event,
8882 uint32_t page_flip_flags)
8883 {
8884 struct drm_device *dev = crtc->dev;
8885 struct drm_i915_private *dev_priv = dev->dev_private;
8886 struct drm_framebuffer *old_fb = crtc->primary->fb;
8887 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8889 struct intel_unpin_work *work;
8890 unsigned long flags;
8891 int ret;
8892
8893 /* Can't change pixel format via MI display flips. */
8894 if (fb->pixel_format != crtc->primary->fb->pixel_format)
8895 return -EINVAL;
8896
8897 /*
8898 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8899 * Note that pitch changes could also affect these register.
8900 */
8901 if (INTEL_INFO(dev)->gen > 3 &&
8902 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
8903 fb->pitches[0] != crtc->primary->fb->pitches[0]))
8904 return -EINVAL;
8905
8906 if (i915_terminally_wedged(&dev_priv->gpu_error))
8907 goto out_hang;
8908
8909 work = kzalloc(sizeof(*work), GFP_KERNEL);
8910 if (work == NULL)
8911 return -ENOMEM;
8912
8913 work->event = event;
8914 work->crtc = crtc;
8915 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8916 INIT_WORK(&work->work, intel_unpin_work_fn);
8917
8918 ret = drm_vblank_get(dev, intel_crtc->pipe);
8919 if (ret)
8920 goto free_work;
8921
8922 /* We borrow the event spin lock for protecting unpin_work */
8923 spin_lock_irqsave(&dev->event_lock, flags);
8924 if (intel_crtc->unpin_work) {
8925 spin_unlock_irqrestore(&dev->event_lock, flags);
8926 kfree(work);
8927 drm_vblank_put(dev, intel_crtc->pipe);
8928
8929 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8930 return -EBUSY;
8931 }
8932 intel_crtc->unpin_work = work;
8933 spin_unlock_irqrestore(&dev->event_lock, flags);
8934
8935 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8936 flush_workqueue(dev_priv->wq);
8937
8938 ret = i915_mutex_lock_interruptible(dev);
8939 if (ret)
8940 goto cleanup;
8941
8942 /* Reference the objects for the scheduled work. */
8943 drm_gem_object_reference(&work->old_fb_obj->base);
8944 drm_gem_object_reference(&obj->base);
8945
8946 crtc->primary->fb = fb;
8947
8948 work->pending_flip_obj = obj;
8949
8950 work->enable_stall_check = true;
8951
8952 atomic_inc(&intel_crtc->unpin_work_count);
8953 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8954
8955 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8956 if (ret)
8957 goto cleanup_pending;
8958
8959 intel_disable_fbc(dev);
8960 intel_mark_fb_busy(obj, NULL);
8961 mutex_unlock(&dev->struct_mutex);
8962
8963 trace_i915_flip_request(intel_crtc->plane, obj);
8964
8965 return 0;
8966
8967 cleanup_pending:
8968 atomic_dec(&intel_crtc->unpin_work_count);
8969 crtc->primary->fb = old_fb;
8970 drm_gem_object_unreference(&work->old_fb_obj->base);
8971 drm_gem_object_unreference(&obj->base);
8972 mutex_unlock(&dev->struct_mutex);
8973
8974 cleanup:
8975 spin_lock_irqsave(&dev->event_lock, flags);
8976 intel_crtc->unpin_work = NULL;
8977 spin_unlock_irqrestore(&dev->event_lock, flags);
8978
8979 drm_vblank_put(dev, intel_crtc->pipe);
8980 free_work:
8981 kfree(work);
8982
8983 if (ret == -EIO) {
8984 out_hang:
8985 intel_crtc_wait_for_pending_flips(crtc);
8986 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
8987 if (ret == 0 && event)
8988 drm_send_vblank_event(dev, intel_crtc->pipe, event);
8989 }
8990 return ret;
8991 }
8992
8993 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8994 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8995 .load_lut = intel_crtc_load_lut,
8996 };
8997
8998 /**
8999 * intel_modeset_update_staged_output_state
9000 *
9001 * Updates the staged output configuration state, e.g. after we've read out the
9002 * current hw state.
9003 */
9004 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9005 {
9006 struct intel_crtc *crtc;
9007 struct intel_encoder *encoder;
9008 struct intel_connector *connector;
9009
9010 list_for_each_entry(connector, &dev->mode_config.connector_list,
9011 base.head) {
9012 connector->new_encoder =
9013 to_intel_encoder(connector->base.encoder);
9014 }
9015
9016 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9017 base.head) {
9018 encoder->new_crtc =
9019 to_intel_crtc(encoder->base.crtc);
9020 }
9021
9022 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9023 base.head) {
9024 crtc->new_enabled = crtc->base.enabled;
9025
9026 if (crtc->new_enabled)
9027 crtc->new_config = &crtc->config;
9028 else
9029 crtc->new_config = NULL;
9030 }
9031 }
9032
9033 /**
9034 * intel_modeset_commit_output_state
9035 *
9036 * This function copies the stage display pipe configuration to the real one.
9037 */
9038 static void intel_modeset_commit_output_state(struct drm_device *dev)
9039 {
9040 struct intel_crtc *crtc;
9041 struct intel_encoder *encoder;
9042 struct intel_connector *connector;
9043
9044 list_for_each_entry(connector, &dev->mode_config.connector_list,
9045 base.head) {
9046 connector->base.encoder = &connector->new_encoder->base;
9047 }
9048
9049 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9050 base.head) {
9051 encoder->base.crtc = &encoder->new_crtc->base;
9052 }
9053
9054 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9055 base.head) {
9056 crtc->base.enabled = crtc->new_enabled;
9057 }
9058 }
9059
9060 static void
9061 connected_sink_compute_bpp(struct intel_connector * connector,
9062 struct intel_crtc_config *pipe_config)
9063 {
9064 int bpp = pipe_config->pipe_bpp;
9065
9066 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9067 connector->base.base.id,
9068 drm_get_connector_name(&connector->base));
9069
9070 /* Don't use an invalid EDID bpc value */
9071 if (connector->base.display_info.bpc &&
9072 connector->base.display_info.bpc * 3 < bpp) {
9073 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9074 bpp, connector->base.display_info.bpc*3);
9075 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9076 }
9077
9078 /* Clamp bpp to 8 on screens without EDID 1.4 */
9079 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9080 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9081 bpp);
9082 pipe_config->pipe_bpp = 24;
9083 }
9084 }
9085
9086 static int
9087 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9088 struct drm_framebuffer *fb,
9089 struct intel_crtc_config *pipe_config)
9090 {
9091 struct drm_device *dev = crtc->base.dev;
9092 struct intel_connector *connector;
9093 int bpp;
9094
9095 switch (fb->pixel_format) {
9096 case DRM_FORMAT_C8:
9097 bpp = 8*3; /* since we go through a colormap */
9098 break;
9099 case DRM_FORMAT_XRGB1555:
9100 case DRM_FORMAT_ARGB1555:
9101 /* checked in intel_framebuffer_init already */
9102 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9103 return -EINVAL;
9104 case DRM_FORMAT_RGB565:
9105 bpp = 6*3; /* min is 18bpp */
9106 break;
9107 case DRM_FORMAT_XBGR8888:
9108 case DRM_FORMAT_ABGR8888:
9109 /* checked in intel_framebuffer_init already */
9110 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9111 return -EINVAL;
9112 case DRM_FORMAT_XRGB8888:
9113 case DRM_FORMAT_ARGB8888:
9114 bpp = 8*3;
9115 break;
9116 case DRM_FORMAT_XRGB2101010:
9117 case DRM_FORMAT_ARGB2101010:
9118 case DRM_FORMAT_XBGR2101010:
9119 case DRM_FORMAT_ABGR2101010:
9120 /* checked in intel_framebuffer_init already */
9121 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9122 return -EINVAL;
9123 bpp = 10*3;
9124 break;
9125 /* TODO: gen4+ supports 16 bpc floating point, too. */
9126 default:
9127 DRM_DEBUG_KMS("unsupported depth\n");
9128 return -EINVAL;
9129 }
9130
9131 pipe_config->pipe_bpp = bpp;
9132
9133 /* Clamp display bpp to EDID value */
9134 list_for_each_entry(connector, &dev->mode_config.connector_list,
9135 base.head) {
9136 if (!connector->new_encoder ||
9137 connector->new_encoder->new_crtc != crtc)
9138 continue;
9139
9140 connected_sink_compute_bpp(connector, pipe_config);
9141 }
9142
9143 return bpp;
9144 }
9145
9146 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9147 {
9148 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9149 "type: 0x%x flags: 0x%x\n",
9150 mode->crtc_clock,
9151 mode->crtc_hdisplay, mode->crtc_hsync_start,
9152 mode->crtc_hsync_end, mode->crtc_htotal,
9153 mode->crtc_vdisplay, mode->crtc_vsync_start,
9154 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9155 }
9156
9157 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9158 struct intel_crtc_config *pipe_config,
9159 const char *context)
9160 {
9161 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9162 context, pipe_name(crtc->pipe));
9163
9164 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9165 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9166 pipe_config->pipe_bpp, pipe_config->dither);
9167 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9168 pipe_config->has_pch_encoder,
9169 pipe_config->fdi_lanes,
9170 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9171 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9172 pipe_config->fdi_m_n.tu);
9173 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9174 pipe_config->has_dp_encoder,
9175 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9176 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9177 pipe_config->dp_m_n.tu);
9178 DRM_DEBUG_KMS("requested mode:\n");
9179 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9180 DRM_DEBUG_KMS("adjusted mode:\n");
9181 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9182 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9183 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9184 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9185 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9186 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9187 pipe_config->gmch_pfit.control,
9188 pipe_config->gmch_pfit.pgm_ratios,
9189 pipe_config->gmch_pfit.lvds_border_bits);
9190 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9191 pipe_config->pch_pfit.pos,
9192 pipe_config->pch_pfit.size,
9193 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9194 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9195 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9196 }
9197
9198 static bool encoders_cloneable(const struct intel_encoder *a,
9199 const struct intel_encoder *b)
9200 {
9201 /* masks could be asymmetric, so check both ways */
9202 return a == b || (a->cloneable & (1 << b->type) &&
9203 b->cloneable & (1 << a->type));
9204 }
9205
9206 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9207 struct intel_encoder *encoder)
9208 {
9209 struct drm_device *dev = crtc->base.dev;
9210 struct intel_encoder *source_encoder;
9211
9212 list_for_each_entry(source_encoder,
9213 &dev->mode_config.encoder_list, base.head) {
9214 if (source_encoder->new_crtc != crtc)
9215 continue;
9216
9217 if (!encoders_cloneable(encoder, source_encoder))
9218 return false;
9219 }
9220
9221 return true;
9222 }
9223
9224 static bool check_encoder_cloning(struct intel_crtc *crtc)
9225 {
9226 struct drm_device *dev = crtc->base.dev;
9227 struct intel_encoder *encoder;
9228
9229 list_for_each_entry(encoder,
9230 &dev->mode_config.encoder_list, base.head) {
9231 if (encoder->new_crtc != crtc)
9232 continue;
9233
9234 if (!check_single_encoder_cloning(crtc, encoder))
9235 return false;
9236 }
9237
9238 return true;
9239 }
9240
9241 static struct intel_crtc_config *
9242 intel_modeset_pipe_config(struct drm_crtc *crtc,
9243 struct drm_framebuffer *fb,
9244 struct drm_display_mode *mode)
9245 {
9246 struct drm_device *dev = crtc->dev;
9247 struct intel_encoder *encoder;
9248 struct intel_crtc_config *pipe_config;
9249 int plane_bpp, ret = -EINVAL;
9250 bool retry = true;
9251
9252 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9253 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9254 return ERR_PTR(-EINVAL);
9255 }
9256
9257 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9258 if (!pipe_config)
9259 return ERR_PTR(-ENOMEM);
9260
9261 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9262 drm_mode_copy(&pipe_config->requested_mode, mode);
9263
9264 pipe_config->cpu_transcoder =
9265 (enum transcoder) to_intel_crtc(crtc)->pipe;
9266 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9267
9268 /*
9269 * Sanitize sync polarity flags based on requested ones. If neither
9270 * positive or negative polarity is requested, treat this as meaning
9271 * negative polarity.
9272 */
9273 if (!(pipe_config->adjusted_mode.flags &
9274 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9275 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9276
9277 if (!(pipe_config->adjusted_mode.flags &
9278 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9279 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9280
9281 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9282 * plane pixel format and any sink constraints into account. Returns the
9283 * source plane bpp so that dithering can be selected on mismatches
9284 * after encoders and crtc also have had their say. */
9285 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9286 fb, pipe_config);
9287 if (plane_bpp < 0)
9288 goto fail;
9289
9290 /*
9291 * Determine the real pipe dimensions. Note that stereo modes can
9292 * increase the actual pipe size due to the frame doubling and
9293 * insertion of additional space for blanks between the frame. This
9294 * is stored in the crtc timings. We use the requested mode to do this
9295 * computation to clearly distinguish it from the adjusted mode, which
9296 * can be changed by the connectors in the below retry loop.
9297 */
9298 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9299 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9300 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9301
9302 encoder_retry:
9303 /* Ensure the port clock defaults are reset when retrying. */
9304 pipe_config->port_clock = 0;
9305 pipe_config->pixel_multiplier = 1;
9306
9307 /* Fill in default crtc timings, allow encoders to overwrite them. */
9308 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9309
9310 /* Pass our mode to the connectors and the CRTC to give them a chance to
9311 * adjust it according to limitations or connector properties, and also
9312 * a chance to reject the mode entirely.
9313 */
9314 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9315 base.head) {
9316
9317 if (&encoder->new_crtc->base != crtc)
9318 continue;
9319
9320 if (!(encoder->compute_config(encoder, pipe_config))) {
9321 DRM_DEBUG_KMS("Encoder config failure\n");
9322 goto fail;
9323 }
9324 }
9325
9326 /* Set default port clock if not overwritten by the encoder. Needs to be
9327 * done afterwards in case the encoder adjusts the mode. */
9328 if (!pipe_config->port_clock)
9329 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9330 * pipe_config->pixel_multiplier;
9331
9332 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9333 if (ret < 0) {
9334 DRM_DEBUG_KMS("CRTC fixup failed\n");
9335 goto fail;
9336 }
9337
9338 if (ret == RETRY) {
9339 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9340 ret = -EINVAL;
9341 goto fail;
9342 }
9343
9344 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9345 retry = false;
9346 goto encoder_retry;
9347 }
9348
9349 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9350 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9351 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9352
9353 return pipe_config;
9354 fail:
9355 kfree(pipe_config);
9356 return ERR_PTR(ret);
9357 }
9358
9359 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9360 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9361 static void
9362 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9363 unsigned *prepare_pipes, unsigned *disable_pipes)
9364 {
9365 struct intel_crtc *intel_crtc;
9366 struct drm_device *dev = crtc->dev;
9367 struct intel_encoder *encoder;
9368 struct intel_connector *connector;
9369 struct drm_crtc *tmp_crtc;
9370
9371 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9372
9373 /* Check which crtcs have changed outputs connected to them, these need
9374 * to be part of the prepare_pipes mask. We don't (yet) support global
9375 * modeset across multiple crtcs, so modeset_pipes will only have one
9376 * bit set at most. */
9377 list_for_each_entry(connector, &dev->mode_config.connector_list,
9378 base.head) {
9379 if (connector->base.encoder == &connector->new_encoder->base)
9380 continue;
9381
9382 if (connector->base.encoder) {
9383 tmp_crtc = connector->base.encoder->crtc;
9384
9385 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9386 }
9387
9388 if (connector->new_encoder)
9389 *prepare_pipes |=
9390 1 << connector->new_encoder->new_crtc->pipe;
9391 }
9392
9393 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9394 base.head) {
9395 if (encoder->base.crtc == &encoder->new_crtc->base)
9396 continue;
9397
9398 if (encoder->base.crtc) {
9399 tmp_crtc = encoder->base.crtc;
9400
9401 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9402 }
9403
9404 if (encoder->new_crtc)
9405 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9406 }
9407
9408 /* Check for pipes that will be enabled/disabled ... */
9409 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9410 base.head) {
9411 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9412 continue;
9413
9414 if (!intel_crtc->new_enabled)
9415 *disable_pipes |= 1 << intel_crtc->pipe;
9416 else
9417 *prepare_pipes |= 1 << intel_crtc->pipe;
9418 }
9419
9420
9421 /* set_mode is also used to update properties on life display pipes. */
9422 intel_crtc = to_intel_crtc(crtc);
9423 if (intel_crtc->new_enabled)
9424 *prepare_pipes |= 1 << intel_crtc->pipe;
9425
9426 /*
9427 * For simplicity do a full modeset on any pipe where the output routing
9428 * changed. We could be more clever, but that would require us to be
9429 * more careful with calling the relevant encoder->mode_set functions.
9430 */
9431 if (*prepare_pipes)
9432 *modeset_pipes = *prepare_pipes;
9433
9434 /* ... and mask these out. */
9435 *modeset_pipes &= ~(*disable_pipes);
9436 *prepare_pipes &= ~(*disable_pipes);
9437
9438 /*
9439 * HACK: We don't (yet) fully support global modesets. intel_set_config
9440 * obies this rule, but the modeset restore mode of
9441 * intel_modeset_setup_hw_state does not.
9442 */
9443 *modeset_pipes &= 1 << intel_crtc->pipe;
9444 *prepare_pipes &= 1 << intel_crtc->pipe;
9445
9446 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9447 *modeset_pipes, *prepare_pipes, *disable_pipes);
9448 }
9449
9450 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9451 {
9452 struct drm_encoder *encoder;
9453 struct drm_device *dev = crtc->dev;
9454
9455 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9456 if (encoder->crtc == crtc)
9457 return true;
9458
9459 return false;
9460 }
9461
9462 static void
9463 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9464 {
9465 struct intel_encoder *intel_encoder;
9466 struct intel_crtc *intel_crtc;
9467 struct drm_connector *connector;
9468
9469 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9470 base.head) {
9471 if (!intel_encoder->base.crtc)
9472 continue;
9473
9474 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9475
9476 if (prepare_pipes & (1 << intel_crtc->pipe))
9477 intel_encoder->connectors_active = false;
9478 }
9479
9480 intel_modeset_commit_output_state(dev);
9481
9482 /* Double check state. */
9483 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9484 base.head) {
9485 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9486 WARN_ON(intel_crtc->new_config &&
9487 intel_crtc->new_config != &intel_crtc->config);
9488 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9489 }
9490
9491 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9492 if (!connector->encoder || !connector->encoder->crtc)
9493 continue;
9494
9495 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9496
9497 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9498 struct drm_property *dpms_property =
9499 dev->mode_config.dpms_property;
9500
9501 connector->dpms = DRM_MODE_DPMS_ON;
9502 drm_object_property_set_value(&connector->base,
9503 dpms_property,
9504 DRM_MODE_DPMS_ON);
9505
9506 intel_encoder = to_intel_encoder(connector->encoder);
9507 intel_encoder->connectors_active = true;
9508 }
9509 }
9510
9511 }
9512
9513 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9514 {
9515 int diff;
9516
9517 if (clock1 == clock2)
9518 return true;
9519
9520 if (!clock1 || !clock2)
9521 return false;
9522
9523 diff = abs(clock1 - clock2);
9524
9525 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9526 return true;
9527
9528 return false;
9529 }
9530
9531 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9532 list_for_each_entry((intel_crtc), \
9533 &(dev)->mode_config.crtc_list, \
9534 base.head) \
9535 if (mask & (1 <<(intel_crtc)->pipe))
9536
9537 static bool
9538 intel_pipe_config_compare(struct drm_device *dev,
9539 struct intel_crtc_config *current_config,
9540 struct intel_crtc_config *pipe_config)
9541 {
9542 #define PIPE_CONF_CHECK_X(name) \
9543 if (current_config->name != pipe_config->name) { \
9544 DRM_ERROR("mismatch in " #name " " \
9545 "(expected 0x%08x, found 0x%08x)\n", \
9546 current_config->name, \
9547 pipe_config->name); \
9548 return false; \
9549 }
9550
9551 #define PIPE_CONF_CHECK_I(name) \
9552 if (current_config->name != pipe_config->name) { \
9553 DRM_ERROR("mismatch in " #name " " \
9554 "(expected %i, found %i)\n", \
9555 current_config->name, \
9556 pipe_config->name); \
9557 return false; \
9558 }
9559
9560 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9561 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9562 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9563 "(expected %i, found %i)\n", \
9564 current_config->name & (mask), \
9565 pipe_config->name & (mask)); \
9566 return false; \
9567 }
9568
9569 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9570 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9571 DRM_ERROR("mismatch in " #name " " \
9572 "(expected %i, found %i)\n", \
9573 current_config->name, \
9574 pipe_config->name); \
9575 return false; \
9576 }
9577
9578 #define PIPE_CONF_QUIRK(quirk) \
9579 ((current_config->quirks | pipe_config->quirks) & (quirk))
9580
9581 PIPE_CONF_CHECK_I(cpu_transcoder);
9582
9583 PIPE_CONF_CHECK_I(has_pch_encoder);
9584 PIPE_CONF_CHECK_I(fdi_lanes);
9585 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9586 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9587 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9588 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9589 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9590
9591 PIPE_CONF_CHECK_I(has_dp_encoder);
9592 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9593 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9594 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9595 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9596 PIPE_CONF_CHECK_I(dp_m_n.tu);
9597
9598 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9599 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9600 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9601 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9602 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9603 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9604
9605 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9606 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9607 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9608 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9609 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9610 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9611
9612 PIPE_CONF_CHECK_I(pixel_multiplier);
9613
9614 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9615 DRM_MODE_FLAG_INTERLACE);
9616
9617 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9618 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9619 DRM_MODE_FLAG_PHSYNC);
9620 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9621 DRM_MODE_FLAG_NHSYNC);
9622 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9623 DRM_MODE_FLAG_PVSYNC);
9624 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9625 DRM_MODE_FLAG_NVSYNC);
9626 }
9627
9628 PIPE_CONF_CHECK_I(pipe_src_w);
9629 PIPE_CONF_CHECK_I(pipe_src_h);
9630
9631 /*
9632 * FIXME: BIOS likes to set up a cloned config with lvds+external
9633 * screen. Since we don't yet re-compute the pipe config when moving
9634 * just the lvds port away to another pipe the sw tracking won't match.
9635 *
9636 * Proper atomic modesets with recomputed global state will fix this.
9637 * Until then just don't check gmch state for inherited modes.
9638 */
9639 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9640 PIPE_CONF_CHECK_I(gmch_pfit.control);
9641 /* pfit ratios are autocomputed by the hw on gen4+ */
9642 if (INTEL_INFO(dev)->gen < 4)
9643 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9644 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9645 }
9646
9647 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9648 if (current_config->pch_pfit.enabled) {
9649 PIPE_CONF_CHECK_I(pch_pfit.pos);
9650 PIPE_CONF_CHECK_I(pch_pfit.size);
9651 }
9652
9653 /* BDW+ don't expose a synchronous way to read the state */
9654 if (IS_HASWELL(dev))
9655 PIPE_CONF_CHECK_I(ips_enabled);
9656
9657 PIPE_CONF_CHECK_I(double_wide);
9658
9659 PIPE_CONF_CHECK_I(shared_dpll);
9660 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9661 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9662 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9663 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9664
9665 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9666 PIPE_CONF_CHECK_I(pipe_bpp);
9667
9668 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9669 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9670
9671 #undef PIPE_CONF_CHECK_X
9672 #undef PIPE_CONF_CHECK_I
9673 #undef PIPE_CONF_CHECK_FLAGS
9674 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9675 #undef PIPE_CONF_QUIRK
9676
9677 return true;
9678 }
9679
9680 static void
9681 check_connector_state(struct drm_device *dev)
9682 {
9683 struct intel_connector *connector;
9684
9685 list_for_each_entry(connector, &dev->mode_config.connector_list,
9686 base.head) {
9687 /* This also checks the encoder/connector hw state with the
9688 * ->get_hw_state callbacks. */
9689 intel_connector_check_state(connector);
9690
9691 WARN(&connector->new_encoder->base != connector->base.encoder,
9692 "connector's staged encoder doesn't match current encoder\n");
9693 }
9694 }
9695
9696 static void
9697 check_encoder_state(struct drm_device *dev)
9698 {
9699 struct intel_encoder *encoder;
9700 struct intel_connector *connector;
9701
9702 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9703 base.head) {
9704 bool enabled = false;
9705 bool active = false;
9706 enum pipe pipe, tracked_pipe;
9707
9708 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9709 encoder->base.base.id,
9710 drm_get_encoder_name(&encoder->base));
9711
9712 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9713 "encoder's stage crtc doesn't match current crtc\n");
9714 WARN(encoder->connectors_active && !encoder->base.crtc,
9715 "encoder's active_connectors set, but no crtc\n");
9716
9717 list_for_each_entry(connector, &dev->mode_config.connector_list,
9718 base.head) {
9719 if (connector->base.encoder != &encoder->base)
9720 continue;
9721 enabled = true;
9722 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9723 active = true;
9724 }
9725 WARN(!!encoder->base.crtc != enabled,
9726 "encoder's enabled state mismatch "
9727 "(expected %i, found %i)\n",
9728 !!encoder->base.crtc, enabled);
9729 WARN(active && !encoder->base.crtc,
9730 "active encoder with no crtc\n");
9731
9732 WARN(encoder->connectors_active != active,
9733 "encoder's computed active state doesn't match tracked active state "
9734 "(expected %i, found %i)\n", active, encoder->connectors_active);
9735
9736 active = encoder->get_hw_state(encoder, &pipe);
9737 WARN(active != encoder->connectors_active,
9738 "encoder's hw state doesn't match sw tracking "
9739 "(expected %i, found %i)\n",
9740 encoder->connectors_active, active);
9741
9742 if (!encoder->base.crtc)
9743 continue;
9744
9745 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9746 WARN(active && pipe != tracked_pipe,
9747 "active encoder's pipe doesn't match"
9748 "(expected %i, found %i)\n",
9749 tracked_pipe, pipe);
9750
9751 }
9752 }
9753
9754 static void
9755 check_crtc_state(struct drm_device *dev)
9756 {
9757 struct drm_i915_private *dev_priv = dev->dev_private;
9758 struct intel_crtc *crtc;
9759 struct intel_encoder *encoder;
9760 struct intel_crtc_config pipe_config;
9761
9762 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9763 base.head) {
9764 bool enabled = false;
9765 bool active = false;
9766
9767 memset(&pipe_config, 0, sizeof(pipe_config));
9768
9769 DRM_DEBUG_KMS("[CRTC:%d]\n",
9770 crtc->base.base.id);
9771
9772 WARN(crtc->active && !crtc->base.enabled,
9773 "active crtc, but not enabled in sw tracking\n");
9774
9775 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9776 base.head) {
9777 if (encoder->base.crtc != &crtc->base)
9778 continue;
9779 enabled = true;
9780 if (encoder->connectors_active)
9781 active = true;
9782 }
9783
9784 WARN(active != crtc->active,
9785 "crtc's computed active state doesn't match tracked active state "
9786 "(expected %i, found %i)\n", active, crtc->active);
9787 WARN(enabled != crtc->base.enabled,
9788 "crtc's computed enabled state doesn't match tracked enabled state "
9789 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9790
9791 active = dev_priv->display.get_pipe_config(crtc,
9792 &pipe_config);
9793
9794 /* hw state is inconsistent with the pipe A quirk */
9795 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9796 active = crtc->active;
9797
9798 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9799 base.head) {
9800 enum pipe pipe;
9801 if (encoder->base.crtc != &crtc->base)
9802 continue;
9803 if (encoder->get_hw_state(encoder, &pipe))
9804 encoder->get_config(encoder, &pipe_config);
9805 }
9806
9807 WARN(crtc->active != active,
9808 "crtc active state doesn't match with hw state "
9809 "(expected %i, found %i)\n", crtc->active, active);
9810
9811 if (active &&
9812 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9813 WARN(1, "pipe state doesn't match!\n");
9814 intel_dump_pipe_config(crtc, &pipe_config,
9815 "[hw state]");
9816 intel_dump_pipe_config(crtc, &crtc->config,
9817 "[sw state]");
9818 }
9819 }
9820 }
9821
9822 static void
9823 check_shared_dpll_state(struct drm_device *dev)
9824 {
9825 struct drm_i915_private *dev_priv = dev->dev_private;
9826 struct intel_crtc *crtc;
9827 struct intel_dpll_hw_state dpll_hw_state;
9828 int i;
9829
9830 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9831 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9832 int enabled_crtcs = 0, active_crtcs = 0;
9833 bool active;
9834
9835 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9836
9837 DRM_DEBUG_KMS("%s\n", pll->name);
9838
9839 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9840
9841 WARN(pll->active > pll->refcount,
9842 "more active pll users than references: %i vs %i\n",
9843 pll->active, pll->refcount);
9844 WARN(pll->active && !pll->on,
9845 "pll in active use but not on in sw tracking\n");
9846 WARN(pll->on && !pll->active,
9847 "pll in on but not on in use in sw tracking\n");
9848 WARN(pll->on != active,
9849 "pll on state mismatch (expected %i, found %i)\n",
9850 pll->on, active);
9851
9852 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9853 base.head) {
9854 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9855 enabled_crtcs++;
9856 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9857 active_crtcs++;
9858 }
9859 WARN(pll->active != active_crtcs,
9860 "pll active crtcs mismatch (expected %i, found %i)\n",
9861 pll->active, active_crtcs);
9862 WARN(pll->refcount != enabled_crtcs,
9863 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9864 pll->refcount, enabled_crtcs);
9865
9866 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9867 sizeof(dpll_hw_state)),
9868 "pll hw state mismatch\n");
9869 }
9870 }
9871
9872 void
9873 intel_modeset_check_state(struct drm_device *dev)
9874 {
9875 check_connector_state(dev);
9876 check_encoder_state(dev);
9877 check_crtc_state(dev);
9878 check_shared_dpll_state(dev);
9879 }
9880
9881 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9882 int dotclock)
9883 {
9884 /*
9885 * FDI already provided one idea for the dotclock.
9886 * Yell if the encoder disagrees.
9887 */
9888 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9889 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9890 pipe_config->adjusted_mode.crtc_clock, dotclock);
9891 }
9892
9893 static int __intel_set_mode(struct drm_crtc *crtc,
9894 struct drm_display_mode *mode,
9895 int x, int y, struct drm_framebuffer *fb)
9896 {
9897 struct drm_device *dev = crtc->dev;
9898 struct drm_i915_private *dev_priv = dev->dev_private;
9899 struct drm_display_mode *saved_mode;
9900 struct intel_crtc_config *pipe_config = NULL;
9901 struct intel_crtc *intel_crtc;
9902 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9903 int ret = 0;
9904
9905 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9906 if (!saved_mode)
9907 return -ENOMEM;
9908
9909 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9910 &prepare_pipes, &disable_pipes);
9911
9912 *saved_mode = crtc->mode;
9913
9914 /* Hack: Because we don't (yet) support global modeset on multiple
9915 * crtcs, we don't keep track of the new mode for more than one crtc.
9916 * Hence simply check whether any bit is set in modeset_pipes in all the
9917 * pieces of code that are not yet converted to deal with mutliple crtcs
9918 * changing their mode at the same time. */
9919 if (modeset_pipes) {
9920 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9921 if (IS_ERR(pipe_config)) {
9922 ret = PTR_ERR(pipe_config);
9923 pipe_config = NULL;
9924
9925 goto out;
9926 }
9927 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9928 "[modeset]");
9929 to_intel_crtc(crtc)->new_config = pipe_config;
9930 }
9931
9932 /*
9933 * See if the config requires any additional preparation, e.g.
9934 * to adjust global state with pipes off. We need to do this
9935 * here so we can get the modeset_pipe updated config for the new
9936 * mode set on this crtc. For other crtcs we need to use the
9937 * adjusted_mode bits in the crtc directly.
9938 */
9939 if (IS_VALLEYVIEW(dev)) {
9940 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9941
9942 /* may have added more to prepare_pipes than we should */
9943 prepare_pipes &= ~disable_pipes;
9944 }
9945
9946 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9947 intel_crtc_disable(&intel_crtc->base);
9948
9949 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9950 if (intel_crtc->base.enabled)
9951 dev_priv->display.crtc_disable(&intel_crtc->base);
9952 }
9953
9954 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9955 * to set it here already despite that we pass it down the callchain.
9956 */
9957 if (modeset_pipes) {
9958 crtc->mode = *mode;
9959 /* mode_set/enable/disable functions rely on a correct pipe
9960 * config. */
9961 to_intel_crtc(crtc)->config = *pipe_config;
9962 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9963
9964 /*
9965 * Calculate and store various constants which
9966 * are later needed by vblank and swap-completion
9967 * timestamping. They are derived from true hwmode.
9968 */
9969 drm_calc_timestamping_constants(crtc,
9970 &pipe_config->adjusted_mode);
9971 }
9972
9973 /* Only after disabling all output pipelines that will be changed can we
9974 * update the the output configuration. */
9975 intel_modeset_update_state(dev, prepare_pipes);
9976
9977 if (dev_priv->display.modeset_global_resources)
9978 dev_priv->display.modeset_global_resources(dev);
9979
9980 /* Set up the DPLL and any encoders state that needs to adjust or depend
9981 * on the DPLL.
9982 */
9983 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9984 ret = intel_crtc_mode_set(&intel_crtc->base,
9985 x, y, fb);
9986 if (ret)
9987 goto done;
9988 }
9989
9990 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9991 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9992 dev_priv->display.crtc_enable(&intel_crtc->base);
9993
9994 /* FIXME: add subpixel order */
9995 done:
9996 if (ret && crtc->enabled)
9997 crtc->mode = *saved_mode;
9998
9999 out:
10000 kfree(pipe_config);
10001 kfree(saved_mode);
10002 return ret;
10003 }
10004
10005 static int intel_set_mode(struct drm_crtc *crtc,
10006 struct drm_display_mode *mode,
10007 int x, int y, struct drm_framebuffer *fb)
10008 {
10009 int ret;
10010
10011 ret = __intel_set_mode(crtc, mode, x, y, fb);
10012
10013 if (ret == 0)
10014 intel_modeset_check_state(crtc->dev);
10015
10016 return ret;
10017 }
10018
10019 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10020 {
10021 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10022 }
10023
10024 #undef for_each_intel_crtc_masked
10025
10026 static void intel_set_config_free(struct intel_set_config *config)
10027 {
10028 if (!config)
10029 return;
10030
10031 kfree(config->save_connector_encoders);
10032 kfree(config->save_encoder_crtcs);
10033 kfree(config->save_crtc_enabled);
10034 kfree(config);
10035 }
10036
10037 static int intel_set_config_save_state(struct drm_device *dev,
10038 struct intel_set_config *config)
10039 {
10040 struct drm_crtc *crtc;
10041 struct drm_encoder *encoder;
10042 struct drm_connector *connector;
10043 int count;
10044
10045 config->save_crtc_enabled =
10046 kcalloc(dev->mode_config.num_crtc,
10047 sizeof(bool), GFP_KERNEL);
10048 if (!config->save_crtc_enabled)
10049 return -ENOMEM;
10050
10051 config->save_encoder_crtcs =
10052 kcalloc(dev->mode_config.num_encoder,
10053 sizeof(struct drm_crtc *), GFP_KERNEL);
10054 if (!config->save_encoder_crtcs)
10055 return -ENOMEM;
10056
10057 config->save_connector_encoders =
10058 kcalloc(dev->mode_config.num_connector,
10059 sizeof(struct drm_encoder *), GFP_KERNEL);
10060 if (!config->save_connector_encoders)
10061 return -ENOMEM;
10062
10063 /* Copy data. Note that driver private data is not affected.
10064 * Should anything bad happen only the expected state is
10065 * restored, not the drivers personal bookkeeping.
10066 */
10067 count = 0;
10068 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10069 config->save_crtc_enabled[count++] = crtc->enabled;
10070 }
10071
10072 count = 0;
10073 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10074 config->save_encoder_crtcs[count++] = encoder->crtc;
10075 }
10076
10077 count = 0;
10078 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10079 config->save_connector_encoders[count++] = connector->encoder;
10080 }
10081
10082 return 0;
10083 }
10084
10085 static void intel_set_config_restore_state(struct drm_device *dev,
10086 struct intel_set_config *config)
10087 {
10088 struct intel_crtc *crtc;
10089 struct intel_encoder *encoder;
10090 struct intel_connector *connector;
10091 int count;
10092
10093 count = 0;
10094 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10095 crtc->new_enabled = config->save_crtc_enabled[count++];
10096
10097 if (crtc->new_enabled)
10098 crtc->new_config = &crtc->config;
10099 else
10100 crtc->new_config = NULL;
10101 }
10102
10103 count = 0;
10104 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10105 encoder->new_crtc =
10106 to_intel_crtc(config->save_encoder_crtcs[count++]);
10107 }
10108
10109 count = 0;
10110 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10111 connector->new_encoder =
10112 to_intel_encoder(config->save_connector_encoders[count++]);
10113 }
10114 }
10115
10116 static bool
10117 is_crtc_connector_off(struct drm_mode_set *set)
10118 {
10119 int i;
10120
10121 if (set->num_connectors == 0)
10122 return false;
10123
10124 if (WARN_ON(set->connectors == NULL))
10125 return false;
10126
10127 for (i = 0; i < set->num_connectors; i++)
10128 if (set->connectors[i]->encoder &&
10129 set->connectors[i]->encoder->crtc == set->crtc &&
10130 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10131 return true;
10132
10133 return false;
10134 }
10135
10136 static void
10137 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10138 struct intel_set_config *config)
10139 {
10140
10141 /* We should be able to check here if the fb has the same properties
10142 * and then just flip_or_move it */
10143 if (is_crtc_connector_off(set)) {
10144 config->mode_changed = true;
10145 } else if (set->crtc->primary->fb != set->fb) {
10146 /* If we have no fb then treat it as a full mode set */
10147 if (set->crtc->primary->fb == NULL) {
10148 struct intel_crtc *intel_crtc =
10149 to_intel_crtc(set->crtc);
10150
10151 if (intel_crtc->active && i915.fastboot) {
10152 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10153 config->fb_changed = true;
10154 } else {
10155 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10156 config->mode_changed = true;
10157 }
10158 } else if (set->fb == NULL) {
10159 config->mode_changed = true;
10160 } else if (set->fb->pixel_format !=
10161 set->crtc->primary->fb->pixel_format) {
10162 config->mode_changed = true;
10163 } else {
10164 config->fb_changed = true;
10165 }
10166 }
10167
10168 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10169 config->fb_changed = true;
10170
10171 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10172 DRM_DEBUG_KMS("modes are different, full mode set\n");
10173 drm_mode_debug_printmodeline(&set->crtc->mode);
10174 drm_mode_debug_printmodeline(set->mode);
10175 config->mode_changed = true;
10176 }
10177
10178 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10179 set->crtc->base.id, config->mode_changed, config->fb_changed);
10180 }
10181
10182 static int
10183 intel_modeset_stage_output_state(struct drm_device *dev,
10184 struct drm_mode_set *set,
10185 struct intel_set_config *config)
10186 {
10187 struct intel_connector *connector;
10188 struct intel_encoder *encoder;
10189 struct intel_crtc *crtc;
10190 int ro;
10191
10192 /* The upper layers ensure that we either disable a crtc or have a list
10193 * of connectors. For paranoia, double-check this. */
10194 WARN_ON(!set->fb && (set->num_connectors != 0));
10195 WARN_ON(set->fb && (set->num_connectors == 0));
10196
10197 list_for_each_entry(connector, &dev->mode_config.connector_list,
10198 base.head) {
10199 /* Otherwise traverse passed in connector list and get encoders
10200 * for them. */
10201 for (ro = 0; ro < set->num_connectors; ro++) {
10202 if (set->connectors[ro] == &connector->base) {
10203 connector->new_encoder = connector->encoder;
10204 break;
10205 }
10206 }
10207
10208 /* If we disable the crtc, disable all its connectors. Also, if
10209 * the connector is on the changing crtc but not on the new
10210 * connector list, disable it. */
10211 if ((!set->fb || ro == set->num_connectors) &&
10212 connector->base.encoder &&
10213 connector->base.encoder->crtc == set->crtc) {
10214 connector->new_encoder = NULL;
10215
10216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10217 connector->base.base.id,
10218 drm_get_connector_name(&connector->base));
10219 }
10220
10221
10222 if (&connector->new_encoder->base != connector->base.encoder) {
10223 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10224 config->mode_changed = true;
10225 }
10226 }
10227 /* connector->new_encoder is now updated for all connectors. */
10228
10229 /* Update crtc of enabled connectors. */
10230 list_for_each_entry(connector, &dev->mode_config.connector_list,
10231 base.head) {
10232 struct drm_crtc *new_crtc;
10233
10234 if (!connector->new_encoder)
10235 continue;
10236
10237 new_crtc = connector->new_encoder->base.crtc;
10238
10239 for (ro = 0; ro < set->num_connectors; ro++) {
10240 if (set->connectors[ro] == &connector->base)
10241 new_crtc = set->crtc;
10242 }
10243
10244 /* Make sure the new CRTC will work with the encoder */
10245 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10246 new_crtc)) {
10247 return -EINVAL;
10248 }
10249 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10250
10251 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10252 connector->base.base.id,
10253 drm_get_connector_name(&connector->base),
10254 new_crtc->base.id);
10255 }
10256
10257 /* Check for any encoders that needs to be disabled. */
10258 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10259 base.head) {
10260 int num_connectors = 0;
10261 list_for_each_entry(connector,
10262 &dev->mode_config.connector_list,
10263 base.head) {
10264 if (connector->new_encoder == encoder) {
10265 WARN_ON(!connector->new_encoder->new_crtc);
10266 num_connectors++;
10267 }
10268 }
10269
10270 if (num_connectors == 0)
10271 encoder->new_crtc = NULL;
10272 else if (num_connectors > 1)
10273 return -EINVAL;
10274
10275 /* Only now check for crtc changes so we don't miss encoders
10276 * that will be disabled. */
10277 if (&encoder->new_crtc->base != encoder->base.crtc) {
10278 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10279 config->mode_changed = true;
10280 }
10281 }
10282 /* Now we've also updated encoder->new_crtc for all encoders. */
10283
10284 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10285 base.head) {
10286 crtc->new_enabled = false;
10287
10288 list_for_each_entry(encoder,
10289 &dev->mode_config.encoder_list,
10290 base.head) {
10291 if (encoder->new_crtc == crtc) {
10292 crtc->new_enabled = true;
10293 break;
10294 }
10295 }
10296
10297 if (crtc->new_enabled != crtc->base.enabled) {
10298 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10299 crtc->new_enabled ? "en" : "dis");
10300 config->mode_changed = true;
10301 }
10302
10303 if (crtc->new_enabled)
10304 crtc->new_config = &crtc->config;
10305 else
10306 crtc->new_config = NULL;
10307 }
10308
10309 return 0;
10310 }
10311
10312 static void disable_crtc_nofb(struct intel_crtc *crtc)
10313 {
10314 struct drm_device *dev = crtc->base.dev;
10315 struct intel_encoder *encoder;
10316 struct intel_connector *connector;
10317
10318 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10319 pipe_name(crtc->pipe));
10320
10321 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10322 if (connector->new_encoder &&
10323 connector->new_encoder->new_crtc == crtc)
10324 connector->new_encoder = NULL;
10325 }
10326
10327 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10328 if (encoder->new_crtc == crtc)
10329 encoder->new_crtc = NULL;
10330 }
10331
10332 crtc->new_enabled = false;
10333 crtc->new_config = NULL;
10334 }
10335
10336 static int intel_crtc_set_config(struct drm_mode_set *set)
10337 {
10338 struct drm_device *dev;
10339 struct drm_mode_set save_set;
10340 struct intel_set_config *config;
10341 int ret;
10342
10343 BUG_ON(!set);
10344 BUG_ON(!set->crtc);
10345 BUG_ON(!set->crtc->helper_private);
10346
10347 /* Enforce sane interface api - has been abused by the fb helper. */
10348 BUG_ON(!set->mode && set->fb);
10349 BUG_ON(set->fb && set->num_connectors == 0);
10350
10351 if (set->fb) {
10352 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10353 set->crtc->base.id, set->fb->base.id,
10354 (int)set->num_connectors, set->x, set->y);
10355 } else {
10356 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10357 }
10358
10359 dev = set->crtc->dev;
10360
10361 ret = -ENOMEM;
10362 config = kzalloc(sizeof(*config), GFP_KERNEL);
10363 if (!config)
10364 goto out_config;
10365
10366 ret = intel_set_config_save_state(dev, config);
10367 if (ret)
10368 goto out_config;
10369
10370 save_set.crtc = set->crtc;
10371 save_set.mode = &set->crtc->mode;
10372 save_set.x = set->crtc->x;
10373 save_set.y = set->crtc->y;
10374 save_set.fb = set->crtc->primary->fb;
10375
10376 /* Compute whether we need a full modeset, only an fb base update or no
10377 * change at all. In the future we might also check whether only the
10378 * mode changed, e.g. for LVDS where we only change the panel fitter in
10379 * such cases. */
10380 intel_set_config_compute_mode_changes(set, config);
10381
10382 ret = intel_modeset_stage_output_state(dev, set, config);
10383 if (ret)
10384 goto fail;
10385
10386 if (config->mode_changed) {
10387 ret = intel_set_mode(set->crtc, set->mode,
10388 set->x, set->y, set->fb);
10389 } else if (config->fb_changed) {
10390 intel_crtc_wait_for_pending_flips(set->crtc);
10391
10392 ret = intel_pipe_set_base(set->crtc,
10393 set->x, set->y, set->fb);
10394 /*
10395 * In the fastboot case this may be our only check of the
10396 * state after boot. It would be better to only do it on
10397 * the first update, but we don't have a nice way of doing that
10398 * (and really, set_config isn't used much for high freq page
10399 * flipping, so increasing its cost here shouldn't be a big
10400 * deal).
10401 */
10402 if (i915.fastboot && ret == 0)
10403 intel_modeset_check_state(set->crtc->dev);
10404 }
10405
10406 if (ret) {
10407 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10408 set->crtc->base.id, ret);
10409 fail:
10410 intel_set_config_restore_state(dev, config);
10411
10412 /*
10413 * HACK: if the pipe was on, but we didn't have a framebuffer,
10414 * force the pipe off to avoid oopsing in the modeset code
10415 * due to fb==NULL. This should only happen during boot since
10416 * we don't yet reconstruct the FB from the hardware state.
10417 */
10418 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10419 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10420
10421 /* Try to restore the config */
10422 if (config->mode_changed &&
10423 intel_set_mode(save_set.crtc, save_set.mode,
10424 save_set.x, save_set.y, save_set.fb))
10425 DRM_ERROR("failed to restore config after modeset failure\n");
10426 }
10427
10428 out_config:
10429 intel_set_config_free(config);
10430 return ret;
10431 }
10432
10433 static const struct drm_crtc_funcs intel_crtc_funcs = {
10434 .cursor_set = intel_crtc_cursor_set,
10435 .cursor_move = intel_crtc_cursor_move,
10436 .gamma_set = intel_crtc_gamma_set,
10437 .set_config = intel_crtc_set_config,
10438 .destroy = intel_crtc_destroy,
10439 .page_flip = intel_crtc_page_flip,
10440 };
10441
10442 static void intel_cpu_pll_init(struct drm_device *dev)
10443 {
10444 if (HAS_DDI(dev))
10445 intel_ddi_pll_init(dev);
10446 }
10447
10448 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10449 struct intel_shared_dpll *pll,
10450 struct intel_dpll_hw_state *hw_state)
10451 {
10452 uint32_t val;
10453
10454 val = I915_READ(PCH_DPLL(pll->id));
10455 hw_state->dpll = val;
10456 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10457 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10458
10459 return val & DPLL_VCO_ENABLE;
10460 }
10461
10462 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10463 struct intel_shared_dpll *pll)
10464 {
10465 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10466 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10467 }
10468
10469 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10470 struct intel_shared_dpll *pll)
10471 {
10472 /* PCH refclock must be enabled first */
10473 ibx_assert_pch_refclk_enabled(dev_priv);
10474
10475 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10476
10477 /* Wait for the clocks to stabilize. */
10478 POSTING_READ(PCH_DPLL(pll->id));
10479 udelay(150);
10480
10481 /* The pixel multiplier can only be updated once the
10482 * DPLL is enabled and the clocks are stable.
10483 *
10484 * So write it again.
10485 */
10486 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10487 POSTING_READ(PCH_DPLL(pll->id));
10488 udelay(200);
10489 }
10490
10491 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10492 struct intel_shared_dpll *pll)
10493 {
10494 struct drm_device *dev = dev_priv->dev;
10495 struct intel_crtc *crtc;
10496
10497 /* Make sure no transcoder isn't still depending on us. */
10498 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10499 if (intel_crtc_to_shared_dpll(crtc) == pll)
10500 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10501 }
10502
10503 I915_WRITE(PCH_DPLL(pll->id), 0);
10504 POSTING_READ(PCH_DPLL(pll->id));
10505 udelay(200);
10506 }
10507
10508 static char *ibx_pch_dpll_names[] = {
10509 "PCH DPLL A",
10510 "PCH DPLL B",
10511 };
10512
10513 static void ibx_pch_dpll_init(struct drm_device *dev)
10514 {
10515 struct drm_i915_private *dev_priv = dev->dev_private;
10516 int i;
10517
10518 dev_priv->num_shared_dpll = 2;
10519
10520 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10521 dev_priv->shared_dplls[i].id = i;
10522 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10523 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10524 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10525 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10526 dev_priv->shared_dplls[i].get_hw_state =
10527 ibx_pch_dpll_get_hw_state;
10528 }
10529 }
10530
10531 static void intel_shared_dpll_init(struct drm_device *dev)
10532 {
10533 struct drm_i915_private *dev_priv = dev->dev_private;
10534
10535 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10536 ibx_pch_dpll_init(dev);
10537 else
10538 dev_priv->num_shared_dpll = 0;
10539
10540 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10541 }
10542
10543 static void intel_crtc_init(struct drm_device *dev, int pipe)
10544 {
10545 struct drm_i915_private *dev_priv = dev->dev_private;
10546 struct intel_crtc *intel_crtc;
10547 int i;
10548
10549 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10550 if (intel_crtc == NULL)
10551 return;
10552
10553 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10554
10555 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10556 for (i = 0; i < 256; i++) {
10557 intel_crtc->lut_r[i] = i;
10558 intel_crtc->lut_g[i] = i;
10559 intel_crtc->lut_b[i] = i;
10560 }
10561
10562 /*
10563 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10564 * is hooked to plane B. Hence we want plane A feeding pipe B.
10565 */
10566 intel_crtc->pipe = pipe;
10567 intel_crtc->plane = pipe;
10568 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10569 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10570 intel_crtc->plane = !pipe;
10571 }
10572
10573 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10574 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10575 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10576 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10577
10578 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10579 }
10580
10581 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10582 {
10583 struct drm_encoder *encoder = connector->base.encoder;
10584
10585 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10586
10587 if (!encoder)
10588 return INVALID_PIPE;
10589
10590 return to_intel_crtc(encoder->crtc)->pipe;
10591 }
10592
10593 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10594 struct drm_file *file)
10595 {
10596 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10597 struct drm_mode_object *drmmode_obj;
10598 struct intel_crtc *crtc;
10599
10600 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10601 return -ENODEV;
10602
10603 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10604 DRM_MODE_OBJECT_CRTC);
10605
10606 if (!drmmode_obj) {
10607 DRM_ERROR("no such CRTC id\n");
10608 return -ENOENT;
10609 }
10610
10611 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10612 pipe_from_crtc_id->pipe = crtc->pipe;
10613
10614 return 0;
10615 }
10616
10617 static int intel_encoder_clones(struct intel_encoder *encoder)
10618 {
10619 struct drm_device *dev = encoder->base.dev;
10620 struct intel_encoder *source_encoder;
10621 int index_mask = 0;
10622 int entry = 0;
10623
10624 list_for_each_entry(source_encoder,
10625 &dev->mode_config.encoder_list, base.head) {
10626 if (encoders_cloneable(encoder, source_encoder))
10627 index_mask |= (1 << entry);
10628
10629 entry++;
10630 }
10631
10632 return index_mask;
10633 }
10634
10635 static bool has_edp_a(struct drm_device *dev)
10636 {
10637 struct drm_i915_private *dev_priv = dev->dev_private;
10638
10639 if (!IS_MOBILE(dev))
10640 return false;
10641
10642 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10643 return false;
10644
10645 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10646 return false;
10647
10648 return true;
10649 }
10650
10651 const char *intel_output_name(int output)
10652 {
10653 static const char *names[] = {
10654 [INTEL_OUTPUT_UNUSED] = "Unused",
10655 [INTEL_OUTPUT_ANALOG] = "Analog",
10656 [INTEL_OUTPUT_DVO] = "DVO",
10657 [INTEL_OUTPUT_SDVO] = "SDVO",
10658 [INTEL_OUTPUT_LVDS] = "LVDS",
10659 [INTEL_OUTPUT_TVOUT] = "TV",
10660 [INTEL_OUTPUT_HDMI] = "HDMI",
10661 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10662 [INTEL_OUTPUT_EDP] = "eDP",
10663 [INTEL_OUTPUT_DSI] = "DSI",
10664 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10665 };
10666
10667 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10668 return "Invalid";
10669
10670 return names[output];
10671 }
10672
10673 static void intel_setup_outputs(struct drm_device *dev)
10674 {
10675 struct drm_i915_private *dev_priv = dev->dev_private;
10676 struct intel_encoder *encoder;
10677 bool dpd_is_edp = false;
10678
10679 intel_lvds_init(dev);
10680
10681 if (!IS_ULT(dev))
10682 intel_crt_init(dev);
10683
10684 if (HAS_DDI(dev)) {
10685 int found;
10686
10687 /* Haswell uses DDI functions to detect digital outputs */
10688 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10689 /* DDI A only supports eDP */
10690 if (found)
10691 intel_ddi_init(dev, PORT_A);
10692
10693 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10694 * register */
10695 found = I915_READ(SFUSE_STRAP);
10696
10697 if (found & SFUSE_STRAP_DDIB_DETECTED)
10698 intel_ddi_init(dev, PORT_B);
10699 if (found & SFUSE_STRAP_DDIC_DETECTED)
10700 intel_ddi_init(dev, PORT_C);
10701 if (found & SFUSE_STRAP_DDID_DETECTED)
10702 intel_ddi_init(dev, PORT_D);
10703 } else if (HAS_PCH_SPLIT(dev)) {
10704 int found;
10705 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10706
10707 if (has_edp_a(dev))
10708 intel_dp_init(dev, DP_A, PORT_A);
10709
10710 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10711 /* PCH SDVOB multiplex with HDMIB */
10712 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10713 if (!found)
10714 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10715 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10716 intel_dp_init(dev, PCH_DP_B, PORT_B);
10717 }
10718
10719 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10720 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10721
10722 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10723 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10724
10725 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10726 intel_dp_init(dev, PCH_DP_C, PORT_C);
10727
10728 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10729 intel_dp_init(dev, PCH_DP_D, PORT_D);
10730 } else if (IS_VALLEYVIEW(dev)) {
10731 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10732 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10733 PORT_B);
10734 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10735 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10736 }
10737
10738 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10739 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10740 PORT_C);
10741 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10742 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10743 }
10744
10745 intel_dsi_init(dev);
10746 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10747 bool found = false;
10748
10749 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10750 DRM_DEBUG_KMS("probing SDVOB\n");
10751 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10752 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10753 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10754 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10755 }
10756
10757 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10758 intel_dp_init(dev, DP_B, PORT_B);
10759 }
10760
10761 /* Before G4X SDVOC doesn't have its own detect register */
10762
10763 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10764 DRM_DEBUG_KMS("probing SDVOC\n");
10765 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10766 }
10767
10768 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10769
10770 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10771 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10772 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10773 }
10774 if (SUPPORTS_INTEGRATED_DP(dev))
10775 intel_dp_init(dev, DP_C, PORT_C);
10776 }
10777
10778 if (SUPPORTS_INTEGRATED_DP(dev) &&
10779 (I915_READ(DP_D) & DP_DETECTED))
10780 intel_dp_init(dev, DP_D, PORT_D);
10781 } else if (IS_GEN2(dev))
10782 intel_dvo_init(dev);
10783
10784 if (SUPPORTS_TV(dev))
10785 intel_tv_init(dev);
10786
10787 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10788 encoder->base.possible_crtcs = encoder->crtc_mask;
10789 encoder->base.possible_clones =
10790 intel_encoder_clones(encoder);
10791 }
10792
10793 intel_init_pch_refclk(dev);
10794
10795 drm_helper_move_panel_connectors_to_head(dev);
10796 }
10797
10798 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10799 {
10800 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10801
10802 drm_framebuffer_cleanup(fb);
10803 WARN_ON(!intel_fb->obj->framebuffer_references--);
10804 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10805 kfree(intel_fb);
10806 }
10807
10808 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10809 struct drm_file *file,
10810 unsigned int *handle)
10811 {
10812 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10813 struct drm_i915_gem_object *obj = intel_fb->obj;
10814
10815 return drm_gem_handle_create(file, &obj->base, handle);
10816 }
10817
10818 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10819 .destroy = intel_user_framebuffer_destroy,
10820 .create_handle = intel_user_framebuffer_create_handle,
10821 };
10822
10823 static int intel_framebuffer_init(struct drm_device *dev,
10824 struct intel_framebuffer *intel_fb,
10825 struct drm_mode_fb_cmd2 *mode_cmd,
10826 struct drm_i915_gem_object *obj)
10827 {
10828 int aligned_height;
10829 int pitch_limit;
10830 int ret;
10831
10832 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10833
10834 if (obj->tiling_mode == I915_TILING_Y) {
10835 DRM_DEBUG("hardware does not support tiling Y\n");
10836 return -EINVAL;
10837 }
10838
10839 if (mode_cmd->pitches[0] & 63) {
10840 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10841 mode_cmd->pitches[0]);
10842 return -EINVAL;
10843 }
10844
10845 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10846 pitch_limit = 32*1024;
10847 } else if (INTEL_INFO(dev)->gen >= 4) {
10848 if (obj->tiling_mode)
10849 pitch_limit = 16*1024;
10850 else
10851 pitch_limit = 32*1024;
10852 } else if (INTEL_INFO(dev)->gen >= 3) {
10853 if (obj->tiling_mode)
10854 pitch_limit = 8*1024;
10855 else
10856 pitch_limit = 16*1024;
10857 } else
10858 /* XXX DSPC is limited to 4k tiled */
10859 pitch_limit = 8*1024;
10860
10861 if (mode_cmd->pitches[0] > pitch_limit) {
10862 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10863 obj->tiling_mode ? "tiled" : "linear",
10864 mode_cmd->pitches[0], pitch_limit);
10865 return -EINVAL;
10866 }
10867
10868 if (obj->tiling_mode != I915_TILING_NONE &&
10869 mode_cmd->pitches[0] != obj->stride) {
10870 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10871 mode_cmd->pitches[0], obj->stride);
10872 return -EINVAL;
10873 }
10874
10875 /* Reject formats not supported by any plane early. */
10876 switch (mode_cmd->pixel_format) {
10877 case DRM_FORMAT_C8:
10878 case DRM_FORMAT_RGB565:
10879 case DRM_FORMAT_XRGB8888:
10880 case DRM_FORMAT_ARGB8888:
10881 break;
10882 case DRM_FORMAT_XRGB1555:
10883 case DRM_FORMAT_ARGB1555:
10884 if (INTEL_INFO(dev)->gen > 3) {
10885 DRM_DEBUG("unsupported pixel format: %s\n",
10886 drm_get_format_name(mode_cmd->pixel_format));
10887 return -EINVAL;
10888 }
10889 break;
10890 case DRM_FORMAT_XBGR8888:
10891 case DRM_FORMAT_ABGR8888:
10892 case DRM_FORMAT_XRGB2101010:
10893 case DRM_FORMAT_ARGB2101010:
10894 case DRM_FORMAT_XBGR2101010:
10895 case DRM_FORMAT_ABGR2101010:
10896 if (INTEL_INFO(dev)->gen < 4) {
10897 DRM_DEBUG("unsupported pixel format: %s\n",
10898 drm_get_format_name(mode_cmd->pixel_format));
10899 return -EINVAL;
10900 }
10901 break;
10902 case DRM_FORMAT_YUYV:
10903 case DRM_FORMAT_UYVY:
10904 case DRM_FORMAT_YVYU:
10905 case DRM_FORMAT_VYUY:
10906 if (INTEL_INFO(dev)->gen < 5) {
10907 DRM_DEBUG("unsupported pixel format: %s\n",
10908 drm_get_format_name(mode_cmd->pixel_format));
10909 return -EINVAL;
10910 }
10911 break;
10912 default:
10913 DRM_DEBUG("unsupported pixel format: %s\n",
10914 drm_get_format_name(mode_cmd->pixel_format));
10915 return -EINVAL;
10916 }
10917
10918 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10919 if (mode_cmd->offsets[0] != 0)
10920 return -EINVAL;
10921
10922 aligned_height = intel_align_height(dev, mode_cmd->height,
10923 obj->tiling_mode);
10924 /* FIXME drm helper for size checks (especially planar formats)? */
10925 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10926 return -EINVAL;
10927
10928 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10929 intel_fb->obj = obj;
10930 intel_fb->obj->framebuffer_references++;
10931
10932 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10933 if (ret) {
10934 DRM_ERROR("framebuffer init failed %d\n", ret);
10935 return ret;
10936 }
10937
10938 return 0;
10939 }
10940
10941 static struct drm_framebuffer *
10942 intel_user_framebuffer_create(struct drm_device *dev,
10943 struct drm_file *filp,
10944 struct drm_mode_fb_cmd2 *mode_cmd)
10945 {
10946 struct drm_i915_gem_object *obj;
10947
10948 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10949 mode_cmd->handles[0]));
10950 if (&obj->base == NULL)
10951 return ERR_PTR(-ENOENT);
10952
10953 return intel_framebuffer_create(dev, mode_cmd, obj);
10954 }
10955
10956 #ifndef CONFIG_DRM_I915_FBDEV
10957 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10958 {
10959 }
10960 #endif
10961
10962 static const struct drm_mode_config_funcs intel_mode_funcs = {
10963 .fb_create = intel_user_framebuffer_create,
10964 .output_poll_changed = intel_fbdev_output_poll_changed,
10965 };
10966
10967 /* Set up chip specific display functions */
10968 static void intel_init_display(struct drm_device *dev)
10969 {
10970 struct drm_i915_private *dev_priv = dev->dev_private;
10971
10972 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10973 dev_priv->display.find_dpll = g4x_find_best_dpll;
10974 else if (IS_VALLEYVIEW(dev))
10975 dev_priv->display.find_dpll = vlv_find_best_dpll;
10976 else if (IS_PINEVIEW(dev))
10977 dev_priv->display.find_dpll = pnv_find_best_dpll;
10978 else
10979 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10980
10981 if (HAS_DDI(dev)) {
10982 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10983 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10984 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10985 dev_priv->display.crtc_enable = haswell_crtc_enable;
10986 dev_priv->display.crtc_disable = haswell_crtc_disable;
10987 dev_priv->display.off = haswell_crtc_off;
10988 dev_priv->display.update_primary_plane =
10989 ironlake_update_primary_plane;
10990 } else if (HAS_PCH_SPLIT(dev)) {
10991 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10992 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10993 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10994 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10995 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10996 dev_priv->display.off = ironlake_crtc_off;
10997 dev_priv->display.update_primary_plane =
10998 ironlake_update_primary_plane;
10999 } else if (IS_VALLEYVIEW(dev)) {
11000 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11001 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11002 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11003 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11004 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11005 dev_priv->display.off = i9xx_crtc_off;
11006 dev_priv->display.update_primary_plane =
11007 i9xx_update_primary_plane;
11008 } else {
11009 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11010 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11011 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11012 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11013 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11014 dev_priv->display.off = i9xx_crtc_off;
11015 dev_priv->display.update_primary_plane =
11016 i9xx_update_primary_plane;
11017 }
11018
11019 /* Returns the core display clock speed */
11020 if (IS_VALLEYVIEW(dev))
11021 dev_priv->display.get_display_clock_speed =
11022 valleyview_get_display_clock_speed;
11023 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11024 dev_priv->display.get_display_clock_speed =
11025 i945_get_display_clock_speed;
11026 else if (IS_I915G(dev))
11027 dev_priv->display.get_display_clock_speed =
11028 i915_get_display_clock_speed;
11029 else if (IS_I945GM(dev) || IS_845G(dev))
11030 dev_priv->display.get_display_clock_speed =
11031 i9xx_misc_get_display_clock_speed;
11032 else if (IS_PINEVIEW(dev))
11033 dev_priv->display.get_display_clock_speed =
11034 pnv_get_display_clock_speed;
11035 else if (IS_I915GM(dev))
11036 dev_priv->display.get_display_clock_speed =
11037 i915gm_get_display_clock_speed;
11038 else if (IS_I865G(dev))
11039 dev_priv->display.get_display_clock_speed =
11040 i865_get_display_clock_speed;
11041 else if (IS_I85X(dev))
11042 dev_priv->display.get_display_clock_speed =
11043 i855_get_display_clock_speed;
11044 else /* 852, 830 */
11045 dev_priv->display.get_display_clock_speed =
11046 i830_get_display_clock_speed;
11047
11048 if (HAS_PCH_SPLIT(dev)) {
11049 if (IS_GEN5(dev)) {
11050 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11051 dev_priv->display.write_eld = ironlake_write_eld;
11052 } else if (IS_GEN6(dev)) {
11053 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11054 dev_priv->display.write_eld = ironlake_write_eld;
11055 dev_priv->display.modeset_global_resources =
11056 snb_modeset_global_resources;
11057 } else if (IS_IVYBRIDGE(dev)) {
11058 /* FIXME: detect B0+ stepping and use auto training */
11059 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11060 dev_priv->display.write_eld = ironlake_write_eld;
11061 dev_priv->display.modeset_global_resources =
11062 ivb_modeset_global_resources;
11063 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11064 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11065 dev_priv->display.write_eld = haswell_write_eld;
11066 dev_priv->display.modeset_global_resources =
11067 haswell_modeset_global_resources;
11068 }
11069 } else if (IS_G4X(dev)) {
11070 dev_priv->display.write_eld = g4x_write_eld;
11071 } else if (IS_VALLEYVIEW(dev)) {
11072 dev_priv->display.modeset_global_resources =
11073 valleyview_modeset_global_resources;
11074 dev_priv->display.write_eld = ironlake_write_eld;
11075 }
11076
11077 /* Default just returns -ENODEV to indicate unsupported */
11078 dev_priv->display.queue_flip = intel_default_queue_flip;
11079
11080 switch (INTEL_INFO(dev)->gen) {
11081 case 2:
11082 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11083 break;
11084
11085 case 3:
11086 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11087 break;
11088
11089 case 4:
11090 case 5:
11091 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11092 break;
11093
11094 case 6:
11095 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11096 break;
11097 case 7:
11098 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11099 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11100 break;
11101 }
11102
11103 intel_panel_init_backlight_funcs(dev);
11104 }
11105
11106 /*
11107 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11108 * resume, or other times. This quirk makes sure that's the case for
11109 * affected systems.
11110 */
11111 static void quirk_pipea_force(struct drm_device *dev)
11112 {
11113 struct drm_i915_private *dev_priv = dev->dev_private;
11114
11115 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11116 DRM_INFO("applying pipe a force quirk\n");
11117 }
11118
11119 /*
11120 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11121 */
11122 static void quirk_ssc_force_disable(struct drm_device *dev)
11123 {
11124 struct drm_i915_private *dev_priv = dev->dev_private;
11125 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11126 DRM_INFO("applying lvds SSC disable quirk\n");
11127 }
11128
11129 /*
11130 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11131 * brightness value
11132 */
11133 static void quirk_invert_brightness(struct drm_device *dev)
11134 {
11135 struct drm_i915_private *dev_priv = dev->dev_private;
11136 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11137 DRM_INFO("applying inverted panel brightness quirk\n");
11138 }
11139
11140 struct intel_quirk {
11141 int device;
11142 int subsystem_vendor;
11143 int subsystem_device;
11144 void (*hook)(struct drm_device *dev);
11145 };
11146
11147 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11148 struct intel_dmi_quirk {
11149 void (*hook)(struct drm_device *dev);
11150 const struct dmi_system_id (*dmi_id_list)[];
11151 };
11152
11153 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11154 {
11155 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11156 return 1;
11157 }
11158
11159 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11160 {
11161 .dmi_id_list = &(const struct dmi_system_id[]) {
11162 {
11163 .callback = intel_dmi_reverse_brightness,
11164 .ident = "NCR Corporation",
11165 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11166 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11167 },
11168 },
11169 { } /* terminating entry */
11170 },
11171 .hook = quirk_invert_brightness,
11172 },
11173 };
11174
11175 static struct intel_quirk intel_quirks[] = {
11176 /* HP Mini needs pipe A force quirk (LP: #322104) */
11177 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11178
11179 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11180 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11181
11182 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11183 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11184
11185 /* 830 needs to leave pipe A & dpll A up */
11186 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11187
11188 /* Lenovo U160 cannot use SSC on LVDS */
11189 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11190
11191 /* Sony Vaio Y cannot use SSC on LVDS */
11192 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11193
11194 /* Acer Aspire 5734Z must invert backlight brightness */
11195 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11196
11197 /* Acer/eMachines G725 */
11198 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11199
11200 /* Acer/eMachines e725 */
11201 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11202
11203 /* Acer/Packard Bell NCL20 */
11204 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11205
11206 /* Acer Aspire 4736Z */
11207 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11208
11209 /* Acer Aspire 5336 */
11210 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11211 };
11212
11213 static void intel_init_quirks(struct drm_device *dev)
11214 {
11215 struct pci_dev *d = dev->pdev;
11216 int i;
11217
11218 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11219 struct intel_quirk *q = &intel_quirks[i];
11220
11221 if (d->device == q->device &&
11222 (d->subsystem_vendor == q->subsystem_vendor ||
11223 q->subsystem_vendor == PCI_ANY_ID) &&
11224 (d->subsystem_device == q->subsystem_device ||
11225 q->subsystem_device == PCI_ANY_ID))
11226 q->hook(dev);
11227 }
11228 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11229 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11230 intel_dmi_quirks[i].hook(dev);
11231 }
11232 }
11233
11234 /* Disable the VGA plane that we never use */
11235 static void i915_disable_vga(struct drm_device *dev)
11236 {
11237 struct drm_i915_private *dev_priv = dev->dev_private;
11238 u8 sr1;
11239 u32 vga_reg = i915_vgacntrl_reg(dev);
11240
11241 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11242 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11243 outb(SR01, VGA_SR_INDEX);
11244 sr1 = inb(VGA_SR_DATA);
11245 outb(sr1 | 1<<5, VGA_SR_DATA);
11246 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11247 udelay(300);
11248
11249 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11250 POSTING_READ(vga_reg);
11251 }
11252
11253 void intel_modeset_init_hw(struct drm_device *dev)
11254 {
11255 intel_prepare_ddi(dev);
11256
11257 intel_init_clock_gating(dev);
11258
11259 intel_reset_dpio(dev);
11260
11261 mutex_lock(&dev->struct_mutex);
11262 intel_enable_gt_powersave(dev);
11263 mutex_unlock(&dev->struct_mutex);
11264 }
11265
11266 void intel_modeset_suspend_hw(struct drm_device *dev)
11267 {
11268 intel_suspend_hw(dev);
11269 }
11270
11271 void intel_modeset_init(struct drm_device *dev)
11272 {
11273 struct drm_i915_private *dev_priv = dev->dev_private;
11274 int sprite, ret;
11275 enum pipe pipe;
11276 struct intel_crtc *crtc;
11277
11278 drm_mode_config_init(dev);
11279
11280 dev->mode_config.min_width = 0;
11281 dev->mode_config.min_height = 0;
11282
11283 dev->mode_config.preferred_depth = 24;
11284 dev->mode_config.prefer_shadow = 1;
11285
11286 dev->mode_config.funcs = &intel_mode_funcs;
11287
11288 intel_init_quirks(dev);
11289
11290 intel_init_pm(dev);
11291
11292 if (INTEL_INFO(dev)->num_pipes == 0)
11293 return;
11294
11295 intel_init_display(dev);
11296
11297 if (IS_GEN2(dev)) {
11298 dev->mode_config.max_width = 2048;
11299 dev->mode_config.max_height = 2048;
11300 } else if (IS_GEN3(dev)) {
11301 dev->mode_config.max_width = 4096;
11302 dev->mode_config.max_height = 4096;
11303 } else {
11304 dev->mode_config.max_width = 8192;
11305 dev->mode_config.max_height = 8192;
11306 }
11307
11308 if (IS_GEN2(dev)) {
11309 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11310 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11311 } else {
11312 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11313 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11314 }
11315
11316 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11317
11318 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11319 INTEL_INFO(dev)->num_pipes,
11320 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11321
11322 for_each_pipe(pipe) {
11323 intel_crtc_init(dev, pipe);
11324 for_each_sprite(pipe, sprite) {
11325 ret = intel_plane_init(dev, pipe, sprite);
11326 if (ret)
11327 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11328 pipe_name(pipe), sprite_name(pipe, sprite), ret);
11329 }
11330 }
11331
11332 intel_init_dpio(dev);
11333 intel_reset_dpio(dev);
11334
11335 intel_cpu_pll_init(dev);
11336 intel_shared_dpll_init(dev);
11337
11338 /* Just disable it once at startup */
11339 i915_disable_vga(dev);
11340 intel_setup_outputs(dev);
11341
11342 /* Just in case the BIOS is doing something questionable. */
11343 intel_disable_fbc(dev);
11344
11345 mutex_lock(&dev->mode_config.mutex);
11346 intel_modeset_setup_hw_state(dev, false);
11347 mutex_unlock(&dev->mode_config.mutex);
11348
11349 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11350 base.head) {
11351 if (!crtc->active)
11352 continue;
11353
11354 /*
11355 * Note that reserving the BIOS fb up front prevents us
11356 * from stuffing other stolen allocations like the ring
11357 * on top. This prevents some ugliness at boot time, and
11358 * can even allow for smooth boot transitions if the BIOS
11359 * fb is large enough for the active pipe configuration.
11360 */
11361 if (dev_priv->display.get_plane_config) {
11362 dev_priv->display.get_plane_config(crtc,
11363 &crtc->plane_config);
11364 /*
11365 * If the fb is shared between multiple heads, we'll
11366 * just get the first one.
11367 */
11368 intel_find_plane_obj(crtc, &crtc->plane_config);
11369 }
11370 }
11371 }
11372
11373 static void
11374 intel_connector_break_all_links(struct intel_connector *connector)
11375 {
11376 connector->base.dpms = DRM_MODE_DPMS_OFF;
11377 connector->base.encoder = NULL;
11378 connector->encoder->connectors_active = false;
11379 connector->encoder->base.crtc = NULL;
11380 }
11381
11382 static void intel_enable_pipe_a(struct drm_device *dev)
11383 {
11384 struct intel_connector *connector;
11385 struct drm_connector *crt = NULL;
11386 struct intel_load_detect_pipe load_detect_temp;
11387
11388 /* We can't just switch on the pipe A, we need to set things up with a
11389 * proper mode and output configuration. As a gross hack, enable pipe A
11390 * by enabling the load detect pipe once. */
11391 list_for_each_entry(connector,
11392 &dev->mode_config.connector_list,
11393 base.head) {
11394 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11395 crt = &connector->base;
11396 break;
11397 }
11398 }
11399
11400 if (!crt)
11401 return;
11402
11403 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11404 intel_release_load_detect_pipe(crt, &load_detect_temp);
11405
11406
11407 }
11408
11409 static bool
11410 intel_check_plane_mapping(struct intel_crtc *crtc)
11411 {
11412 struct drm_device *dev = crtc->base.dev;
11413 struct drm_i915_private *dev_priv = dev->dev_private;
11414 u32 reg, val;
11415
11416 if (INTEL_INFO(dev)->num_pipes == 1)
11417 return true;
11418
11419 reg = DSPCNTR(!crtc->plane);
11420 val = I915_READ(reg);
11421
11422 if ((val & DISPLAY_PLANE_ENABLE) &&
11423 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11424 return false;
11425
11426 return true;
11427 }
11428
11429 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11430 {
11431 struct drm_device *dev = crtc->base.dev;
11432 struct drm_i915_private *dev_priv = dev->dev_private;
11433 u32 reg;
11434
11435 /* Clear any frame start delays used for debugging left by the BIOS */
11436 reg = PIPECONF(crtc->config.cpu_transcoder);
11437 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11438
11439 /* We need to sanitize the plane -> pipe mapping first because this will
11440 * disable the crtc (and hence change the state) if it is wrong. Note
11441 * that gen4+ has a fixed plane -> pipe mapping. */
11442 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11443 struct intel_connector *connector;
11444 bool plane;
11445
11446 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11447 crtc->base.base.id);
11448
11449 /* Pipe has the wrong plane attached and the plane is active.
11450 * Temporarily change the plane mapping and disable everything
11451 * ... */
11452 plane = crtc->plane;
11453 crtc->plane = !plane;
11454 dev_priv->display.crtc_disable(&crtc->base);
11455 crtc->plane = plane;
11456
11457 /* ... and break all links. */
11458 list_for_each_entry(connector, &dev->mode_config.connector_list,
11459 base.head) {
11460 if (connector->encoder->base.crtc != &crtc->base)
11461 continue;
11462
11463 intel_connector_break_all_links(connector);
11464 }
11465
11466 WARN_ON(crtc->active);
11467 crtc->base.enabled = false;
11468 }
11469
11470 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11471 crtc->pipe == PIPE_A && !crtc->active) {
11472 /* BIOS forgot to enable pipe A, this mostly happens after
11473 * resume. Force-enable the pipe to fix this, the update_dpms
11474 * call below we restore the pipe to the right state, but leave
11475 * the required bits on. */
11476 intel_enable_pipe_a(dev);
11477 }
11478
11479 /* Adjust the state of the output pipe according to whether we
11480 * have active connectors/encoders. */
11481 intel_crtc_update_dpms(&crtc->base);
11482
11483 if (crtc->active != crtc->base.enabled) {
11484 struct intel_encoder *encoder;
11485
11486 /* This can happen either due to bugs in the get_hw_state
11487 * functions or because the pipe is force-enabled due to the
11488 * pipe A quirk. */
11489 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11490 crtc->base.base.id,
11491 crtc->base.enabled ? "enabled" : "disabled",
11492 crtc->active ? "enabled" : "disabled");
11493
11494 crtc->base.enabled = crtc->active;
11495
11496 /* Because we only establish the connector -> encoder ->
11497 * crtc links if something is active, this means the
11498 * crtc is now deactivated. Break the links. connector
11499 * -> encoder links are only establish when things are
11500 * actually up, hence no need to break them. */
11501 WARN_ON(crtc->active);
11502
11503 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11504 WARN_ON(encoder->connectors_active);
11505 encoder->base.crtc = NULL;
11506 }
11507 }
11508 if (crtc->active) {
11509 /*
11510 * We start out with underrun reporting disabled to avoid races.
11511 * For correct bookkeeping mark this on active crtcs.
11512 *
11513 * No protection against concurrent access is required - at
11514 * worst a fifo underrun happens which also sets this to false.
11515 */
11516 crtc->cpu_fifo_underrun_disabled = true;
11517 crtc->pch_fifo_underrun_disabled = true;
11518 }
11519 }
11520
11521 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11522 {
11523 struct intel_connector *connector;
11524 struct drm_device *dev = encoder->base.dev;
11525
11526 /* We need to check both for a crtc link (meaning that the
11527 * encoder is active and trying to read from a pipe) and the
11528 * pipe itself being active. */
11529 bool has_active_crtc = encoder->base.crtc &&
11530 to_intel_crtc(encoder->base.crtc)->active;
11531
11532 if (encoder->connectors_active && !has_active_crtc) {
11533 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11534 encoder->base.base.id,
11535 drm_get_encoder_name(&encoder->base));
11536
11537 /* Connector is active, but has no active pipe. This is
11538 * fallout from our resume register restoring. Disable
11539 * the encoder manually again. */
11540 if (encoder->base.crtc) {
11541 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11542 encoder->base.base.id,
11543 drm_get_encoder_name(&encoder->base));
11544 encoder->disable(encoder);
11545 }
11546
11547 /* Inconsistent output/port/pipe state happens presumably due to
11548 * a bug in one of the get_hw_state functions. Or someplace else
11549 * in our code, like the register restore mess on resume. Clamp
11550 * things to off as a safer default. */
11551 list_for_each_entry(connector,
11552 &dev->mode_config.connector_list,
11553 base.head) {
11554 if (connector->encoder != encoder)
11555 continue;
11556
11557 intel_connector_break_all_links(connector);
11558 }
11559 }
11560 /* Enabled encoders without active connectors will be fixed in
11561 * the crtc fixup. */
11562 }
11563
11564 void i915_redisable_vga_power_on(struct drm_device *dev)
11565 {
11566 struct drm_i915_private *dev_priv = dev->dev_private;
11567 u32 vga_reg = i915_vgacntrl_reg(dev);
11568
11569 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11570 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11571 i915_disable_vga(dev);
11572 }
11573 }
11574
11575 void i915_redisable_vga(struct drm_device *dev)
11576 {
11577 struct drm_i915_private *dev_priv = dev->dev_private;
11578
11579 /* This function can be called both from intel_modeset_setup_hw_state or
11580 * at a very early point in our resume sequence, where the power well
11581 * structures are not yet restored. Since this function is at a very
11582 * paranoid "someone might have enabled VGA while we were not looking"
11583 * level, just check if the power well is enabled instead of trying to
11584 * follow the "don't touch the power well if we don't need it" policy
11585 * the rest of the driver uses. */
11586 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11587 return;
11588
11589 i915_redisable_vga_power_on(dev);
11590 }
11591
11592 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11593 {
11594 struct drm_i915_private *dev_priv = dev->dev_private;
11595 enum pipe pipe;
11596 struct intel_crtc *crtc;
11597 struct intel_encoder *encoder;
11598 struct intel_connector *connector;
11599 int i;
11600
11601 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11602 base.head) {
11603 memset(&crtc->config, 0, sizeof(crtc->config));
11604
11605 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11606
11607 crtc->active = dev_priv->display.get_pipe_config(crtc,
11608 &crtc->config);
11609
11610 crtc->base.enabled = crtc->active;
11611 crtc->primary_enabled = crtc->active;
11612
11613 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11614 crtc->base.base.id,
11615 crtc->active ? "enabled" : "disabled");
11616 }
11617
11618 /* FIXME: Smash this into the new shared dpll infrastructure. */
11619 if (HAS_DDI(dev))
11620 intel_ddi_setup_hw_pll_state(dev);
11621
11622 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11623 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11624
11625 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11626 pll->active = 0;
11627 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11628 base.head) {
11629 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11630 pll->active++;
11631 }
11632 pll->refcount = pll->active;
11633
11634 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11635 pll->name, pll->refcount, pll->on);
11636 }
11637
11638 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11639 base.head) {
11640 pipe = 0;
11641
11642 if (encoder->get_hw_state(encoder, &pipe)) {
11643 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11644 encoder->base.crtc = &crtc->base;
11645 encoder->get_config(encoder, &crtc->config);
11646 } else {
11647 encoder->base.crtc = NULL;
11648 }
11649
11650 encoder->connectors_active = false;
11651 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11652 encoder->base.base.id,
11653 drm_get_encoder_name(&encoder->base),
11654 encoder->base.crtc ? "enabled" : "disabled",
11655 pipe_name(pipe));
11656 }
11657
11658 list_for_each_entry(connector, &dev->mode_config.connector_list,
11659 base.head) {
11660 if (connector->get_hw_state(connector)) {
11661 connector->base.dpms = DRM_MODE_DPMS_ON;
11662 connector->encoder->connectors_active = true;
11663 connector->base.encoder = &connector->encoder->base;
11664 } else {
11665 connector->base.dpms = DRM_MODE_DPMS_OFF;
11666 connector->base.encoder = NULL;
11667 }
11668 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11669 connector->base.base.id,
11670 drm_get_connector_name(&connector->base),
11671 connector->base.encoder ? "enabled" : "disabled");
11672 }
11673 }
11674
11675 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11676 * and i915 state tracking structures. */
11677 void intel_modeset_setup_hw_state(struct drm_device *dev,
11678 bool force_restore)
11679 {
11680 struct drm_i915_private *dev_priv = dev->dev_private;
11681 enum pipe pipe;
11682 struct intel_crtc *crtc;
11683 struct intel_encoder *encoder;
11684 int i;
11685
11686 intel_modeset_readout_hw_state(dev);
11687
11688 /*
11689 * Now that we have the config, copy it to each CRTC struct
11690 * Note that this could go away if we move to using crtc_config
11691 * checking everywhere.
11692 */
11693 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11694 base.head) {
11695 if (crtc->active && i915.fastboot) {
11696 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11697 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11698 crtc->base.base.id);
11699 drm_mode_debug_printmodeline(&crtc->base.mode);
11700 }
11701 }
11702
11703 /* HW state is read out, now we need to sanitize this mess. */
11704 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11705 base.head) {
11706 intel_sanitize_encoder(encoder);
11707 }
11708
11709 for_each_pipe(pipe) {
11710 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11711 intel_sanitize_crtc(crtc);
11712 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11713 }
11714
11715 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11716 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11717
11718 if (!pll->on || pll->active)
11719 continue;
11720
11721 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11722
11723 pll->disable(dev_priv, pll);
11724 pll->on = false;
11725 }
11726
11727 if (HAS_PCH_SPLIT(dev))
11728 ilk_wm_get_hw_state(dev);
11729
11730 if (force_restore) {
11731 i915_redisable_vga(dev);
11732
11733 /*
11734 * We need to use raw interfaces for restoring state to avoid
11735 * checking (bogus) intermediate states.
11736 */
11737 for_each_pipe(pipe) {
11738 struct drm_crtc *crtc =
11739 dev_priv->pipe_to_crtc_mapping[pipe];
11740
11741 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11742 crtc->primary->fb);
11743 }
11744 } else {
11745 intel_modeset_update_staged_output_state(dev);
11746 }
11747
11748 intel_modeset_check_state(dev);
11749 }
11750
11751 void intel_modeset_gem_init(struct drm_device *dev)
11752 {
11753 struct drm_crtc *c;
11754 struct intel_framebuffer *fb;
11755
11756 mutex_lock(&dev->struct_mutex);
11757 intel_init_gt_powersave(dev);
11758 mutex_unlock(&dev->struct_mutex);
11759
11760 intel_modeset_init_hw(dev);
11761
11762 intel_setup_overlay(dev);
11763
11764 /*
11765 * Make sure any fbs we allocated at startup are properly
11766 * pinned & fenced. When we do the allocation it's too early
11767 * for this.
11768 */
11769 mutex_lock(&dev->struct_mutex);
11770 list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11771 if (!c->primary->fb)
11772 continue;
11773
11774 fb = to_intel_framebuffer(c->primary->fb);
11775 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11776 DRM_ERROR("failed to pin boot fb on pipe %d\n",
11777 to_intel_crtc(c)->pipe);
11778 drm_framebuffer_unreference(c->primary->fb);
11779 c->primary->fb = NULL;
11780 }
11781 }
11782 mutex_unlock(&dev->struct_mutex);
11783 }
11784
11785 void intel_connector_unregister(struct intel_connector *intel_connector)
11786 {
11787 struct drm_connector *connector = &intel_connector->base;
11788
11789 intel_panel_destroy_backlight(connector);
11790 drm_sysfs_connector_remove(connector);
11791 }
11792
11793 void intel_modeset_cleanup(struct drm_device *dev)
11794 {
11795 struct drm_i915_private *dev_priv = dev->dev_private;
11796 struct drm_crtc *crtc;
11797 struct drm_connector *connector;
11798
11799 /*
11800 * Interrupts and polling as the first thing to avoid creating havoc.
11801 * Too much stuff here (turning of rps, connectors, ...) would
11802 * experience fancy races otherwise.
11803 */
11804 drm_irq_uninstall(dev);
11805 cancel_work_sync(&dev_priv->hotplug_work);
11806 /*
11807 * Due to the hpd irq storm handling the hotplug work can re-arm the
11808 * poll handlers. Hence disable polling after hpd handling is shut down.
11809 */
11810 drm_kms_helper_poll_fini(dev);
11811
11812 mutex_lock(&dev->struct_mutex);
11813
11814 intel_unregister_dsm_handler();
11815
11816 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11817 /* Skip inactive CRTCs */
11818 if (!crtc->primary->fb)
11819 continue;
11820
11821 intel_increase_pllclock(crtc);
11822 }
11823
11824 intel_disable_fbc(dev);
11825
11826 intel_disable_gt_powersave(dev);
11827
11828 ironlake_teardown_rc6(dev);
11829
11830 mutex_unlock(&dev->struct_mutex);
11831
11832 /* flush any delayed tasks or pending work */
11833 flush_scheduled_work();
11834
11835 /* destroy the backlight and sysfs files before encoders/connectors */
11836 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11837 struct intel_connector *intel_connector;
11838
11839 intel_connector = to_intel_connector(connector);
11840 intel_connector->unregister(intel_connector);
11841 }
11842
11843 drm_mode_config_cleanup(dev);
11844
11845 intel_cleanup_overlay(dev);
11846
11847 mutex_lock(&dev->struct_mutex);
11848 intel_cleanup_gt_powersave(dev);
11849 mutex_unlock(&dev->struct_mutex);
11850 }
11851
11852 /*
11853 * Return which encoder is currently attached for connector.
11854 */
11855 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11856 {
11857 return &intel_attached_encoder(connector)->base;
11858 }
11859
11860 void intel_connector_attach_encoder(struct intel_connector *connector,
11861 struct intel_encoder *encoder)
11862 {
11863 connector->encoder = encoder;
11864 drm_mode_connector_attach_encoder(&connector->base,
11865 &encoder->base);
11866 }
11867
11868 /*
11869 * set vga decode state - true == enable VGA decode
11870 */
11871 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11872 {
11873 struct drm_i915_private *dev_priv = dev->dev_private;
11874 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11875 u16 gmch_ctrl;
11876
11877 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11878 DRM_ERROR("failed to read control word\n");
11879 return -EIO;
11880 }
11881
11882 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11883 return 0;
11884
11885 if (state)
11886 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11887 else
11888 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11889
11890 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11891 DRM_ERROR("failed to write control word\n");
11892 return -EIO;
11893 }
11894
11895 return 0;
11896 }
11897
11898 struct intel_display_error_state {
11899
11900 u32 power_well_driver;
11901
11902 int num_transcoders;
11903
11904 struct intel_cursor_error_state {
11905 u32 control;
11906 u32 position;
11907 u32 base;
11908 u32 size;
11909 } cursor[I915_MAX_PIPES];
11910
11911 struct intel_pipe_error_state {
11912 bool power_domain_on;
11913 u32 source;
11914 } pipe[I915_MAX_PIPES];
11915
11916 struct intel_plane_error_state {
11917 u32 control;
11918 u32 stride;
11919 u32 size;
11920 u32 pos;
11921 u32 addr;
11922 u32 surface;
11923 u32 tile_offset;
11924 } plane[I915_MAX_PIPES];
11925
11926 struct intel_transcoder_error_state {
11927 bool power_domain_on;
11928 enum transcoder cpu_transcoder;
11929
11930 u32 conf;
11931
11932 u32 htotal;
11933 u32 hblank;
11934 u32 hsync;
11935 u32 vtotal;
11936 u32 vblank;
11937 u32 vsync;
11938 } transcoder[4];
11939 };
11940
11941 struct intel_display_error_state *
11942 intel_display_capture_error_state(struct drm_device *dev)
11943 {
11944 struct drm_i915_private *dev_priv = dev->dev_private;
11945 struct intel_display_error_state *error;
11946 int transcoders[] = {
11947 TRANSCODER_A,
11948 TRANSCODER_B,
11949 TRANSCODER_C,
11950 TRANSCODER_EDP,
11951 };
11952 int i;
11953
11954 if (INTEL_INFO(dev)->num_pipes == 0)
11955 return NULL;
11956
11957 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11958 if (error == NULL)
11959 return NULL;
11960
11961 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11962 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11963
11964 for_each_pipe(i) {
11965 error->pipe[i].power_domain_on =
11966 intel_display_power_enabled_sw(dev_priv,
11967 POWER_DOMAIN_PIPE(i));
11968 if (!error->pipe[i].power_domain_on)
11969 continue;
11970
11971 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11972 error->cursor[i].control = I915_READ(CURCNTR(i));
11973 error->cursor[i].position = I915_READ(CURPOS(i));
11974 error->cursor[i].base = I915_READ(CURBASE(i));
11975 } else {
11976 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11977 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11978 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11979 }
11980
11981 error->plane[i].control = I915_READ(DSPCNTR(i));
11982 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11983 if (INTEL_INFO(dev)->gen <= 3) {
11984 error->plane[i].size = I915_READ(DSPSIZE(i));
11985 error->plane[i].pos = I915_READ(DSPPOS(i));
11986 }
11987 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11988 error->plane[i].addr = I915_READ(DSPADDR(i));
11989 if (INTEL_INFO(dev)->gen >= 4) {
11990 error->plane[i].surface = I915_READ(DSPSURF(i));
11991 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11992 }
11993
11994 error->pipe[i].source = I915_READ(PIPESRC(i));
11995 }
11996
11997 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11998 if (HAS_DDI(dev_priv->dev))
11999 error->num_transcoders++; /* Account for eDP. */
12000
12001 for (i = 0; i < error->num_transcoders; i++) {
12002 enum transcoder cpu_transcoder = transcoders[i];
12003
12004 error->transcoder[i].power_domain_on =
12005 intel_display_power_enabled_sw(dev_priv,
12006 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12007 if (!error->transcoder[i].power_domain_on)
12008 continue;
12009
12010 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12011
12012 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12013 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12014 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12015 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12016 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12017 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12018 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12019 }
12020
12021 return error;
12022 }
12023
12024 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12025
12026 void
12027 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12028 struct drm_device *dev,
12029 struct intel_display_error_state *error)
12030 {
12031 int i;
12032
12033 if (!error)
12034 return;
12035
12036 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12037 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12038 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12039 error->power_well_driver);
12040 for_each_pipe(i) {
12041 err_printf(m, "Pipe [%d]:\n", i);
12042 err_printf(m, " Power: %s\n",
12043 error->pipe[i].power_domain_on ? "on" : "off");
12044 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12045
12046 err_printf(m, "Plane [%d]:\n", i);
12047 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12048 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
12049 if (INTEL_INFO(dev)->gen <= 3) {
12050 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12051 err_printf(m, " POS: %08x\n", error->plane[i].pos);
12052 }
12053 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12054 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
12055 if (INTEL_INFO(dev)->gen >= 4) {
12056 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12057 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
12058 }
12059
12060 err_printf(m, "Cursor [%d]:\n", i);
12061 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12062 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12063 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
12064 }
12065
12066 for (i = 0; i < error->num_transcoders; i++) {
12067 err_printf(m, "CPU transcoder: %c\n",
12068 transcoder_name(error->transcoder[i].cpu_transcoder));
12069 err_printf(m, " Power: %s\n",
12070 error->transcoder[i].power_domain_on ? "on" : "off");
12071 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12072 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12073 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12074 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12075 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12076 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12077 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
12078 }
12079 }
Ubuntu Artful kernel mirror