]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: extract ironlake_fdi_pll_disable
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static bool
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
108 {
109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
114 }
115
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
127 .find_pll = intel_find_best_PLL,
128 };
129
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
141 .find_pll = intel_find_best_PLL,
142 };
143
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
155 .find_pll = intel_find_best_PLL,
156 };
157
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 .find_pll = intel_find_best_PLL,
170 };
171
172
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
185 },
186 .find_pll = intel_g4x_find_best_PLL,
187 };
188
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
200 .find_pll = intel_g4x_find_best_PLL,
201 };
202
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
214 },
215 .find_pll = intel_g4x_find_best_PLL,
216 };
217
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
229 },
230 .find_pll = intel_g4x_find_best_PLL,
231 };
232
233 static const intel_limit_t intel_limits_g4x_display_port = {
234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 10, .p2_fast = 10 },
244 .find_pll = intel_find_pll_g4x_dp,
245 };
246
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
260 .find_pll = intel_find_best_PLL,
261 };
262
263 static const intel_limit_t intel_limits_pineview_lvds = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
274 .find_pll = intel_find_best_PLL,
275 };
276
277 /* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
282 static const intel_limit_t intel_limits_ironlake_dac = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
293 .find_pll = intel_g4x_find_best_PLL,
294 };
295
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
307 .find_pll = intel_g4x_find_best_PLL,
308 };
309
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
321 .find_pll = intel_g4x_find_best_PLL,
322 };
323
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
336 .find_pll = intel_g4x_find_best_PLL,
337 };
338
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
347 .p1 = { .min = 2, .max = 6 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 .find_pll = intel_g4x_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 10, .p2_fast = 10 },
364 .find_pll = intel_find_pll_ironlake_dp,
365 };
366
367 static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379 };
380
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393 };
394
395 static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407 };
408
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410 {
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429 out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432 }
433
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436 {
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452 out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454 }
455
456 static void vlv_init_dpio(struct drm_device *dev)
457 {
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465 }
466
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468 {
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471 }
472
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483 };
484
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487 {
488 unsigned int val;
489
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511 }
512
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
515 {
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
536 else
537 limit = &intel_limits_ironlake_dac;
538
539 return limit;
540 }
541
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543 {
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
552 else
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
564
565 return limit;
566 }
567
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
569 {
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
580 else
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
597 else
598 limit = &intel_limits_i8xx_dvo;
599 }
600 return limit;
601 }
602
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
605 {
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610 }
611
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613 {
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
616 return;
617 }
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622 }
623
624 /**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
628 {
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
631
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
634 return true;
635
636 return false;
637 }
638
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
640 /**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
648 {
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
670
671 return true;
672 }
673
674 static bool
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
678
679 {
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
683 int err = target;
684
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
704 memset(best_clock, 0, sizeof(*best_clock));
705
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
717 int this_err;
718
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
722 continue;
723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738 }
739
740 static bool
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
744 {
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
755 int lvds_reg;
756
757 if (HAS_PCH_SPLIT(dev))
758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
789 continue;
790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
793
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
805 return found;
806 }
807
808 static bool
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815
816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832 }
833
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
835 static bool
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
860 }
861 static bool
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
872 flag = 0;
873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928 }
929
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931 {
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939 }
940
941 /**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 int pipestat_reg = PIPESTAT(pipe);
953
954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
979 DRM_DEBUG_KMS("vblank wait timed out\n");
980 }
981
982 /*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
997 *
998 */
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
1004 int reg = PIPECONF(pipe);
1005
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
1011 u32 last_line, line_mask;
1012 int reg = PIPEDSL(pipe);
1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 /* Wait for the display line to settle */
1021 do {
1022 last_line = I915_READ(reg) & line_mask;
1023 mdelay(5);
1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033 return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039 {
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
1059 {
1060 u32 val;
1061 bool cur_state;
1062
1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070 return;
1071
1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
1095 }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102 {
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126 {
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148 {
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167 {
1168 int reg;
1169 u32 val;
1170
1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182 {
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
1186 bool locked = true;
1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
1206 pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
1211 {
1212 int reg;
1213 u32 val;
1214 bool cur_state;
1215
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
1230 {
1231 int reg;
1232 u32 val;
1233 bool cur_state;
1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248 {
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
1260 return;
1261 }
1262
1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
1272 }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277 u32 val;
1278 bool enabled;
1279
1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326 {
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342 {
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358 {
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, int reg, u32 port_sel)
1373 {
1374 u32 val = I915_READ(reg);
1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe));
1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385 {
1386 u32 val = I915_READ(reg);
1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389 reg, pipe_name(pipe));
1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397 {
1398 int reg;
1399 u32 val;
1400
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
1409 pipe_name(pipe));
1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415 pipe_name(pipe));
1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1434 */
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461 }
1462
1463 /**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489 }
1490
1491 /* SBI access */
1492 static void
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494 {
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518 out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520 }
1521
1522 static u32
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524 {
1525 unsigned long flags;
1526 u32 value = 0;
1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549 out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552 }
1553
1554 /**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1563 {
1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565 struct intel_pch_pll *pll;
1566 int reg;
1567 u32 val;
1568
1569 /* PCH PLLs only available on ILK, SNB and IVB */
1570 BUG_ON(dev_priv->info->gen < 5);
1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
1585 if (pll->active++ && pll->on) {
1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
1598
1599 pll->on = true;
1600 }
1601
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1603 {
1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1606 int reg;
1607 u32 val;
1608
1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
1611 if (pll == NULL)
1612 return;
1613
1614 if (WARN_ON(pll->refcount == 0))
1615 return;
1616
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
1620
1621 if (WARN_ON(pll->active == 0)) {
1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
1623 return;
1624 }
1625
1626 if (--pll->active) {
1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
1628 return;
1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1635
1636 reg = pll->pll_reg;
1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
1642
1643 pll->on = false;
1644 }
1645
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648 {
1649 int reg;
1650 u32 val, pipeconf_val;
1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
1671 pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
1679 val |= pipeconf_val & PIPE_BPC_MASK;
1680 }
1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695 }
1696
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699 {
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1717 }
1718
1719 /**
1720 * intel_enable_pipe - enable a pipe, asserting requirements
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
1735 {
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765 * intel_disable_pipe - disable a pipe, asserting requirements
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778 {
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799 }
1800
1801 /*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1806 enum plane plane)
1807 {
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810 }
1811
1812 /**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822 {
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835 intel_flush_display_plane(dev_priv, plane);
1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837 }
1838
1839 /**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849 {
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861 }
1862
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864 enum pipe pipe, int reg, u32 port_sel)
1865 {
1866 u32 val = I915_READ(reg);
1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869 I915_WRITE(reg, val & ~DP_PORT_EN);
1870 }
1871 }
1872
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875 {
1876 u32 val = I915_READ(reg);
1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
1880 I915_WRITE(reg, val & ~PORT_ENABLE);
1881 }
1882 }
1883
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887 {
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914 }
1915
1916 int
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918 struct drm_i915_gem_object *obj,
1919 struct intel_ring_buffer *pipelined)
1920 {
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922 u32 alignment;
1923 int ret;
1924
1925 switch (obj->tiling_mode) {
1926 case I915_TILING_NONE:
1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
1929 else if (INTEL_INFO(dev)->gen >= 4)
1930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
1933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
1946 dev_priv->mm.interruptible = false;
1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1948 if (ret)
1949 goto err_interruptible;
1950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
1956 ret = i915_gem_object_get_fence(obj);
1957 if (ret)
1958 goto err_unpin;
1959
1960 i915_gem_object_pin_fence(obj);
1961
1962 dev_priv->mm.interruptible = true;
1963 return 0;
1964
1965 err_unpin:
1966 i915_gem_object_unpin(obj);
1967 err_interruptible:
1968 dev_priv->mm.interruptible = true;
1969 return ret;
1970 }
1971
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973 {
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976 }
1977
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983 {
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
1996 {
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
2001 struct drm_i915_gem_object *obj;
2002 int plane = intel_crtc->plane;
2003 unsigned long linear_offset;
2004 u32 dspcntr;
2005 u32 reg;
2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2018
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2039 return -EINVAL;
2040 }
2041 if (INTEL_INFO(dev)->gen >= 4) {
2042 if (obj->tiling_mode != I915_TILING_NONE)
2043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
2048 I915_WRITE(reg, dspcntr);
2049
2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2051
2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
2059 intel_crtc->dspaddr_offset = linear_offset;
2060 }
2061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065 if (INTEL_INFO(dev)->gen >= 4) {
2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
2070 } else
2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2072 POSTING_READ(reg);
2073
2074 return 0;
2075 }
2076
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079 {
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
2086 unsigned long linear_offset;
2087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
2093 case 2:
2094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
2147
2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
2155 POSTING_READ(reg);
2156
2157 return 0;
2158 }
2159
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2161 static int
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164 {
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
2170 intel_increase_pllclock(crtc);
2171
2172 return dev_priv->display.update_plane(crtc, fb, x, y);
2173 }
2174
2175 static int
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2177 {
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *old_fb)
2205 {
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210 int ret;
2211
2212 /* no fb bound */
2213 if (!crtc->fb) {
2214 DRM_ERROR("No FB bound\n");
2215 return 0;
2216 }
2217
2218 if(intel_crtc->plane > dev_priv->num_pipe) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220 intel_crtc->plane,
2221 dev_priv->num_pipe);
2222 return -EINVAL;
2223 }
2224
2225 mutex_lock(&dev->struct_mutex);
2226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
2228 NULL);
2229 if (ret != 0) {
2230 mutex_unlock(&dev->struct_mutex);
2231 DRM_ERROR("pin & fence failed\n");
2232 return ret;
2233 }
2234
2235 if (old_fb)
2236 intel_finish_fb(old_fb);
2237
2238 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2239 if (ret) {
2240 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2241 mutex_unlock(&dev->struct_mutex);
2242 DRM_ERROR("failed to update base address\n");
2243 return ret;
2244 }
2245
2246 if (old_fb) {
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2249 }
2250
2251 intel_update_fbc(dev);
2252 mutex_unlock(&dev->struct_mutex);
2253
2254 if (!dev->primary->master)
2255 return 0;
2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
2259 return 0;
2260
2261 if (intel_crtc->pipe) {
2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
2264 } else {
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
2267 }
2268
2269 return 0;
2270 }
2271
2272 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2273 {
2274 struct drm_device *dev = crtc->dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 u32 dpa_ctl;
2277
2278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2279 dpa_ctl = I915_READ(DP_A);
2280 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282 if (clock < 200000) {
2283 u32 temp;
2284 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2290 */
2291 temp = I915_READ(0x4600c);
2292 temp &= 0xffff0000;
2293 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295 temp = I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp | 1);
2297
2298 temp = I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp | (1 << 24));
2300 } else {
2301 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302 }
2303 I915_WRITE(DP_A, dpa_ctl);
2304
2305 POSTING_READ(DP_A);
2306 udelay(500);
2307 }
2308
2309 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310 {
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314 int pipe = intel_crtc->pipe;
2315 u32 reg, temp;
2316
2317 /* enable normal train */
2318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
2320 if (IS_IVYBRIDGE(dev)) {
2321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2323 } else {
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2326 }
2327 I915_WRITE(reg, temp);
2328
2329 reg = FDI_RX_CTL(pipe);
2330 temp = I915_READ(reg);
2331 if (HAS_PCH_CPT(dev)) {
2332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334 } else {
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_NONE;
2337 }
2338 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340 /* wait one idle pattern time */
2341 POSTING_READ(reg);
2342 udelay(1000);
2343
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev))
2346 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347 FDI_FE_ERRC_ENABLE);
2348 }
2349
2350 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351 {
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355 flags |= FDI_PHASE_SYNC_OVR(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357 flags |= FDI_PHASE_SYNC_EN(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1);
2360 }
2361
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364 {
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
2369 int plane = intel_crtc->plane;
2370 u32 reg, temp, tries;
2371
2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2375
2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377 for train result */
2378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
2380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
2382 I915_WRITE(reg, temp);
2383 I915_READ(reg);
2384 udelay(150);
2385
2386 /* enable CPU FDI TX and PCH FDI RX */
2387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~(7 << 19);
2390 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
2399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401 POSTING_READ(reg);
2402 udelay(150);
2403
2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
2405 if (HAS_PCH_IBX(dev)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408 FDI_RX_PHASE_SYNC_POINTER_EN);
2409 }
2410
2411 reg = FDI_RX_IIR(pipe);
2412 for (tries = 0; tries < 5; tries++) {
2413 temp = I915_READ(reg);
2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
2418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2419 break;
2420 }
2421 }
2422 if (tries == 5)
2423 DRM_ERROR("FDI train 1 fail!\n");
2424
2425 /* Train 2 */
2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
2430 I915_WRITE(reg, temp);
2431
2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
2436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
2439 udelay(150);
2440
2441 reg = FDI_RX_IIR(pipe);
2442 for (tries = 0; tries < 5; tries++) {
2443 temp = I915_READ(reg);
2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
2451 }
2452 if (tries == 5)
2453 DRM_ERROR("FDI train 2 fail!\n");
2454
2455 DRM_DEBUG_KMS("FDI train done\n");
2456
2457 }
2458
2459 static const int snb_b_fdi_train_param[] = {
2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464 };
2465
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468 {
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
2473 u32 reg, temp, i, retry;
2474
2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
2477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
2479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
2481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
2484 udelay(150);
2485
2486 /* enable CPU FDI TX and PCH FDI RX */
2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2497
2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503 } else {
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 }
2507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509 POSTING_READ(reg);
2510 udelay(150);
2511
2512 if (HAS_PCH_CPT(dev))
2513 cpt_phase_pointer_enable(dev, pipe);
2514
2515 for (i = 0; i < 4; i++) {
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
2523 udelay(500);
2524
2525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
2535 }
2536 if (retry < 5)
2537 break;
2538 }
2539 if (i == 4)
2540 DRM_ERROR("FDI train 1 fail!\n");
2541
2542 /* Train 2 */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
2552 I915_WRITE(reg, temp);
2553
2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
2568 for (i = 0; i < 4; i++) {
2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(500);
2577
2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
2588 }
2589 if (retry < 5)
2590 break;
2591 }
2592 if (i == 4)
2593 DRM_ERROR("FDI train 2 fail!\n");
2594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596 }
2597
2598 /* Manual link training for Ivy Bridge A0 parts */
2599 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600 {
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
2605 u32 reg, temp, i;
2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(7 << 19);
2622 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2627 temp |= FDI_COMPOSITE_SYNC;
2628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635 temp |= FDI_COMPOSITE_SYNC;
2636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
2641 if (HAS_PCH_CPT(dev))
2642 cpt_phase_pointer_enable(dev, pipe);
2643
2644 for (i = 0; i < 4; i++) {
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
2652 udelay(500);
2653
2654 reg = FDI_RX_IIR(pipe);
2655 temp = I915_READ(reg);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658 if (temp & FDI_RX_BIT_LOCK ||
2659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 }
2665 if (i == 4)
2666 DRM_ERROR("FDI train 1 fail!\n");
2667
2668 /* Train 2 */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 I915_WRITE(reg, temp);
2676
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
2686 for (i = 0; i < 4; i++) {
2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_SYMBOL_LOCK) {
2701 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2703 break;
2704 }
2705 }
2706 if (i == 4)
2707 DRM_ERROR("FDI train 2 fail!\n");
2708
2709 DRM_DEBUG_KMS("FDI train done.\n");
2710 }
2711
2712 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2713 {
2714 struct drm_device *dev = intel_crtc->base.dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 int pipe = intel_crtc->pipe;
2717 u32 reg, temp;
2718
2719 /* Write the TU size bits so error detection works */
2720 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2722
2723 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~((0x7 << 19) | (0x7 << 16));
2727 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2728 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2730
2731 POSTING_READ(reg);
2732 udelay(200);
2733
2734 /* Switch from Rawclk to PCDclk */
2735 temp = I915_READ(reg);
2736 I915_WRITE(reg, temp | FDI_PCDCLK);
2737
2738 POSTING_READ(reg);
2739 udelay(200);
2740
2741 /* On Haswell, the PLL configuration for ports and pipes is handled
2742 * separately, as part of DDI setup */
2743 if (!IS_HASWELL(dev)) {
2744 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2749
2750 POSTING_READ(reg);
2751 udelay(100);
2752 }
2753 }
2754 }
2755
2756 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2757 {
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 int pipe = intel_crtc->pipe;
2761 u32 reg, temp;
2762
2763 /* Switch from PCDclk to Rawclk */
2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2767
2768 /* Disable CPU FDI TX PLL */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(100);
2775
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2779
2780 /* Wait for the clocks to turn off. */
2781 POSTING_READ(reg);
2782 udelay(100);
2783 }
2784
2785 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2786 {
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 u32 flags = I915_READ(SOUTH_CHICKEN1);
2789
2790 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2791 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2792 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2794 POSTING_READ(SOUTH_CHICKEN1);
2795 }
2796 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2797 {
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801 int pipe = intel_crtc->pipe;
2802 u32 reg, temp;
2803
2804 /* disable CPU FDI tx and PCH FDI rx */
2805 reg = FDI_TX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2808 POSTING_READ(reg);
2809
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~(0x7 << 16);
2813 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2815
2816 POSTING_READ(reg);
2817 udelay(100);
2818
2819 /* Ironlake workaround, disable clock pointer after downing FDI */
2820 if (HAS_PCH_IBX(dev)) {
2821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2822 I915_WRITE(FDI_RX_CHICKEN(pipe),
2823 I915_READ(FDI_RX_CHICKEN(pipe) &
2824 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2825 } else if (HAS_PCH_CPT(dev)) {
2826 cpt_phase_pointer_disable(dev, pipe);
2827 }
2828
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 }
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848 I915_WRITE(reg, temp);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852 }
2853
2854 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855 {
2856 struct drm_device *dev = crtc->dev;
2857
2858 if (crtc->fb == NULL)
2859 return;
2860
2861 mutex_lock(&dev->struct_mutex);
2862 intel_finish_fb(crtc->fb);
2863 mutex_unlock(&dev->struct_mutex);
2864 }
2865
2866 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867 {
2868 struct drm_device *dev = crtc->dev;
2869 struct intel_encoder *intel_encoder;
2870
2871 /*
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2874 */
2875 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2876
2877 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2878 * CPU handles all others */
2879 if (IS_HASWELL(dev)) {
2880 /* It is still unclear how this will work on PPT, so throw up a warning */
2881 WARN_ON(!HAS_PCH_LPT(dev));
2882
2883 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2884 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2885 return true;
2886 } else {
2887 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2888 intel_encoder->type);
2889 return false;
2890 }
2891 }
2892
2893 switch (intel_encoder->type) {
2894 case INTEL_OUTPUT_EDP:
2895 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2896 return false;
2897 continue;
2898 }
2899 }
2900
2901 return true;
2902 }
2903
2904 /* Program iCLKIP clock to the desired frequency */
2905 static void lpt_program_iclkip(struct drm_crtc *crtc)
2906 {
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2914 */
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2920 SBI_SSCCTL_DISABLE);
2921
2922 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2923 if (crtc->mode.clock == 20000) {
2924 auxdiv = 1;
2925 divsel = 0x41;
2926 phaseinc = 0x20;
2927 } else {
2928 /* The iCLK virtual clock root frequency is in MHz,
2929 * but the crtc->mode.clock in in KHz. To get the divisors,
2930 * it is necessary to divide one by another, so we
2931 * convert the virtual clock precision to KHz here for higher
2932 * precision.
2933 */
2934 u32 iclk_virtual_root_freq = 172800 * 1000;
2935 u32 iclk_pi_range = 64;
2936 u32 desired_divisor, msb_divisor_value, pi_value;
2937
2938 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2939 msb_divisor_value = desired_divisor / iclk_pi_range;
2940 pi_value = desired_divisor % iclk_pi_range;
2941
2942 auxdiv = 0;
2943 divsel = msb_divisor_value - 2;
2944 phaseinc = pi_value;
2945 }
2946
2947 /* This should not happen with any sane values */
2948 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2949 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2950 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2951 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2952
2953 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2954 crtc->mode.clock,
2955 auxdiv,
2956 divsel,
2957 phasedir,
2958 phaseinc);
2959
2960 /* Program SSCDIVINTPHASE6 */
2961 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2962 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2963 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2964 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2965 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2966 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2967 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2968
2969 intel_sbi_write(dev_priv,
2970 SBI_SSCDIVINTPHASE6,
2971 temp);
2972
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv,
2978 SBI_SSCAUXDIV6,
2979 temp);
2980
2981
2982 /* Enable modulator and associated divider */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2984 temp &= ~SBI_SSCCTL_DISABLE;
2985 intel_sbi_write(dev_priv,
2986 SBI_SSCCTL6,
2987 temp);
2988
2989 /* Wait for initialization time */
2990 udelay(24);
2991
2992 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2993 }
2994
2995 /*
2996 * Enable PCH resources required for PCH ports:
2997 * - PCH PLLs
2998 * - FDI training & RX/TX
2999 * - update transcoder timings
3000 * - DP transcoding bits
3001 * - transcoder
3002 */
3003 static void ironlake_pch_enable(struct drm_crtc *crtc)
3004 {
3005 struct drm_device *dev = crtc->dev;
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008 int pipe = intel_crtc->pipe;
3009 u32 reg, temp;
3010
3011 assert_transcoder_disabled(dev_priv, pipe);
3012
3013 /* For PCH output, training FDI link */
3014 dev_priv->display.fdi_link_train(crtc);
3015
3016 intel_enable_pch_pll(intel_crtc);
3017
3018 if (HAS_PCH_LPT(dev)) {
3019 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3020 lpt_program_iclkip(crtc);
3021 } else if (HAS_PCH_CPT(dev)) {
3022 u32 sel;
3023
3024 temp = I915_READ(PCH_DPLL_SEL);
3025 switch (pipe) {
3026 default:
3027 case 0:
3028 temp |= TRANSA_DPLL_ENABLE;
3029 sel = TRANSA_DPLLB_SEL;
3030 break;
3031 case 1:
3032 temp |= TRANSB_DPLL_ENABLE;
3033 sel = TRANSB_DPLLB_SEL;
3034 break;
3035 case 2:
3036 temp |= TRANSC_DPLL_ENABLE;
3037 sel = TRANSC_DPLLB_SEL;
3038 break;
3039 }
3040 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3041 temp |= sel;
3042 else
3043 temp &= ~sel;
3044 I915_WRITE(PCH_DPLL_SEL, temp);
3045 }
3046
3047 /* set transcoder timing, panel must allow it */
3048 assert_panel_unlocked(dev_priv, pipe);
3049 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3050 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3051 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3052
3053 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3054 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3055 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3056 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3057
3058 if (!IS_HASWELL(dev))
3059 intel_fdi_normal_train(crtc);
3060
3061 /* For PCH DP, enable TRANS_DP_CTL */
3062 if (HAS_PCH_CPT(dev) &&
3063 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3064 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3065 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3066 reg = TRANS_DP_CTL(pipe);
3067 temp = I915_READ(reg);
3068 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3069 TRANS_DP_SYNC_MASK |
3070 TRANS_DP_BPC_MASK);
3071 temp |= (TRANS_DP_OUTPUT_ENABLE |
3072 TRANS_DP_ENH_FRAMING);
3073 temp |= bpc << 9; /* same format but at 11:9 */
3074
3075 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3076 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3077 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3078 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3079
3080 switch (intel_trans_dp_port_sel(crtc)) {
3081 case PCH_DP_B:
3082 temp |= TRANS_DP_PORT_SEL_B;
3083 break;
3084 case PCH_DP_C:
3085 temp |= TRANS_DP_PORT_SEL_C;
3086 break;
3087 case PCH_DP_D:
3088 temp |= TRANS_DP_PORT_SEL_D;
3089 break;
3090 default:
3091 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3092 temp |= TRANS_DP_PORT_SEL_B;
3093 break;
3094 }
3095
3096 I915_WRITE(reg, temp);
3097 }
3098
3099 intel_enable_transcoder(dev_priv, pipe);
3100 }
3101
3102 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3103 {
3104 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3105
3106 if (pll == NULL)
3107 return;
3108
3109 if (pll->refcount == 0) {
3110 WARN(1, "bad PCH PLL refcount\n");
3111 return;
3112 }
3113
3114 --pll->refcount;
3115 intel_crtc->pch_pll = NULL;
3116 }
3117
3118 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3119 {
3120 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121 struct intel_pch_pll *pll;
3122 int i;
3123
3124 pll = intel_crtc->pch_pll;
3125 if (pll) {
3126 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127 intel_crtc->base.base.id, pll->pll_reg);
3128 goto prepare;
3129 }
3130
3131 if (HAS_PCH_IBX(dev_priv->dev)) {
3132 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133 i = intel_crtc->pipe;
3134 pll = &dev_priv->pch_plls[i];
3135
3136 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137 intel_crtc->base.base.id, pll->pll_reg);
3138
3139 goto found;
3140 }
3141
3142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143 pll = &dev_priv->pch_plls[i];
3144
3145 /* Only want to check enabled timings first */
3146 if (pll->refcount == 0)
3147 continue;
3148
3149 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150 fp == I915_READ(pll->fp0_reg)) {
3151 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152 intel_crtc->base.base.id,
3153 pll->pll_reg, pll->refcount, pll->active);
3154
3155 goto found;
3156 }
3157 }
3158
3159 /* Ok no matching timings, maybe there's a free one? */
3160 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161 pll = &dev_priv->pch_plls[i];
3162 if (pll->refcount == 0) {
3163 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto found;
3166 }
3167 }
3168
3169 return NULL;
3170
3171 found:
3172 intel_crtc->pch_pll = pll;
3173 pll->refcount++;
3174 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3175 prepare: /* separate function? */
3176 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3177
3178 /* Wait for the clocks to stabilize before rewriting the regs */
3179 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3180 POSTING_READ(pll->pll_reg);
3181 udelay(150);
3182
3183 I915_WRITE(pll->fp0_reg, fp);
3184 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3185 pll->on = false;
3186 return pll;
3187 }
3188
3189 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3190 {
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3193 u32 temp;
3194
3195 temp = I915_READ(dslreg);
3196 udelay(500);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3198 /* Without this, mode sets may fail silently on FDI */
3199 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3200 udelay(250);
3201 I915_WRITE(tc2reg, 0);
3202 if (wait_for(I915_READ(dslreg) != temp, 5))
3203 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3204 }
3205 }
3206
3207 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208 {
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212 int pipe = intel_crtc->pipe;
3213 int plane = intel_crtc->plane;
3214 u32 temp;
3215 bool is_pch_port;
3216
3217 if (intel_crtc->active)
3218 return;
3219
3220 intel_crtc->active = true;
3221 intel_update_watermarks(dev);
3222
3223 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3224 temp = I915_READ(PCH_LVDS);
3225 if ((temp & LVDS_PORT_EN) == 0)
3226 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3227 }
3228
3229 is_pch_port = intel_crtc_driving_pch(crtc);
3230
3231 if (is_pch_port)
3232 ironlake_fdi_pll_enable(intel_crtc);
3233 else
3234 ironlake_fdi_disable(crtc);
3235
3236 /* Enable panel fitting for LVDS */
3237 if (dev_priv->pch_pf_size &&
3238 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3239 /* Force use of hard-coded filter coefficients
3240 * as some pre-programmed values are broken,
3241 * e.g. x201.
3242 */
3243 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3244 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3245 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3246 }
3247
3248 /*
3249 * On ILK+ LUT must be loaded before the pipe is running but with
3250 * clocks enabled
3251 */
3252 intel_crtc_load_lut(crtc);
3253
3254 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3255 intel_enable_plane(dev_priv, plane, pipe);
3256
3257 if (is_pch_port)
3258 ironlake_pch_enable(crtc);
3259
3260 mutex_lock(&dev->struct_mutex);
3261 intel_update_fbc(dev);
3262 mutex_unlock(&dev->struct_mutex);
3263
3264 intel_crtc_update_cursor(crtc, true);
3265 }
3266
3267 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3268 {
3269 struct drm_device *dev = crtc->dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272 int pipe = intel_crtc->pipe;
3273 int plane = intel_crtc->plane;
3274 u32 reg, temp;
3275
3276 if (!intel_crtc->active)
3277 return;
3278
3279 intel_crtc_wait_for_pending_flips(crtc);
3280 drm_vblank_off(dev, pipe);
3281 intel_crtc_update_cursor(crtc, false);
3282
3283 intel_disable_plane(dev_priv, plane, pipe);
3284
3285 if (dev_priv->cfb_plane == plane)
3286 intel_disable_fbc(dev);
3287
3288 intel_disable_pipe(dev_priv, pipe);
3289
3290 /* Disable PF */
3291 I915_WRITE(PF_CTL(pipe), 0);
3292 I915_WRITE(PF_WIN_SZ(pipe), 0);
3293
3294 ironlake_fdi_disable(crtc);
3295
3296 /* This is a horrible layering violation; we should be doing this in
3297 * the connector/encoder ->prepare instead, but we don't always have
3298 * enough information there about the config to know whether it will
3299 * actually be necessary or just cause undesired flicker.
3300 */
3301 intel_disable_pch_ports(dev_priv, pipe);
3302
3303 intel_disable_transcoder(dev_priv, pipe);
3304
3305 if (HAS_PCH_CPT(dev)) {
3306 /* disable TRANS_DP_CTL */
3307 reg = TRANS_DP_CTL(pipe);
3308 temp = I915_READ(reg);
3309 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3310 temp |= TRANS_DP_PORT_SEL_NONE;
3311 I915_WRITE(reg, temp);
3312
3313 /* disable DPLL_SEL */
3314 temp = I915_READ(PCH_DPLL_SEL);
3315 switch (pipe) {
3316 case 0:
3317 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3318 break;
3319 case 1:
3320 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3321 break;
3322 case 2:
3323 /* C shares PLL A or B */
3324 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3325 break;
3326 default:
3327 BUG(); /* wtf */
3328 }
3329 I915_WRITE(PCH_DPLL_SEL, temp);
3330 }
3331
3332 /* disable PCH DPLL */
3333 intel_disable_pch_pll(intel_crtc);
3334
3335 ironlake_fdi_pll_disable(intel_crtc);
3336
3337 intel_crtc->active = false;
3338 intel_update_watermarks(dev);
3339
3340 mutex_lock(&dev->struct_mutex);
3341 intel_update_fbc(dev);
3342 mutex_unlock(&dev->struct_mutex);
3343 }
3344
3345 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3346 {
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 int pipe = intel_crtc->pipe;
3349 int plane = intel_crtc->plane;
3350
3351 /* XXX: When our outputs are all unaware of DPMS modes other than off
3352 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3353 */
3354 switch (mode) {
3355 case DRM_MODE_DPMS_ON:
3356 case DRM_MODE_DPMS_STANDBY:
3357 case DRM_MODE_DPMS_SUSPEND:
3358 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3359 ironlake_crtc_enable(crtc);
3360 break;
3361
3362 case DRM_MODE_DPMS_OFF:
3363 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3364 ironlake_crtc_disable(crtc);
3365 break;
3366 }
3367 }
3368
3369 static void ironlake_crtc_off(struct drm_crtc *crtc)
3370 {
3371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3372 intel_put_pch_pll(intel_crtc);
3373 }
3374
3375 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3376 {
3377 if (!enable && intel_crtc->overlay) {
3378 struct drm_device *dev = intel_crtc->base.dev;
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380
3381 mutex_lock(&dev->struct_mutex);
3382 dev_priv->mm.interruptible = false;
3383 (void) intel_overlay_switch_off(intel_crtc->overlay);
3384 dev_priv->mm.interruptible = true;
3385 mutex_unlock(&dev->struct_mutex);
3386 }
3387
3388 /* Let userspace switch the overlay on again. In most cases userspace
3389 * has to recompute where to put it anyway.
3390 */
3391 }
3392
3393 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3394 {
3395 struct drm_device *dev = crtc->dev;
3396 struct drm_i915_private *dev_priv = dev->dev_private;
3397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398 int pipe = intel_crtc->pipe;
3399 int plane = intel_crtc->plane;
3400
3401 if (intel_crtc->active)
3402 return;
3403
3404 intel_crtc->active = true;
3405 intel_update_watermarks(dev);
3406
3407 intel_enable_pll(dev_priv, pipe);
3408 intel_enable_pipe(dev_priv, pipe, false);
3409 intel_enable_plane(dev_priv, plane, pipe);
3410
3411 intel_crtc_load_lut(crtc);
3412 intel_update_fbc(dev);
3413
3414 /* Give the overlay scaler a chance to enable if it's on this pipe */
3415 intel_crtc_dpms_overlay(intel_crtc, true);
3416 intel_crtc_update_cursor(crtc, true);
3417 }
3418
3419 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3420 {
3421 struct drm_device *dev = crtc->dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424 int pipe = intel_crtc->pipe;
3425 int plane = intel_crtc->plane;
3426
3427 if (!intel_crtc->active)
3428 return;
3429
3430 /* Give the overlay scaler a chance to disable if it's on this pipe */
3431 intel_crtc_wait_for_pending_flips(crtc);
3432 drm_vblank_off(dev, pipe);
3433 intel_crtc_dpms_overlay(intel_crtc, false);
3434 intel_crtc_update_cursor(crtc, false);
3435
3436 if (dev_priv->cfb_plane == plane)
3437 intel_disable_fbc(dev);
3438
3439 intel_disable_plane(dev_priv, plane, pipe);
3440 intel_disable_pipe(dev_priv, pipe);
3441 intel_disable_pll(dev_priv, pipe);
3442
3443 intel_crtc->active = false;
3444 intel_update_fbc(dev);
3445 intel_update_watermarks(dev);
3446 }
3447
3448 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3449 {
3450 /* XXX: When our outputs are all unaware of DPMS modes other than off
3451 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3452 */
3453 switch (mode) {
3454 case DRM_MODE_DPMS_ON:
3455 case DRM_MODE_DPMS_STANDBY:
3456 case DRM_MODE_DPMS_SUSPEND:
3457 i9xx_crtc_enable(crtc);
3458 break;
3459 case DRM_MODE_DPMS_OFF:
3460 i9xx_crtc_disable(crtc);
3461 break;
3462 }
3463 }
3464
3465 static void i9xx_crtc_off(struct drm_crtc *crtc)
3466 {
3467 }
3468
3469 /**
3470 * Sets the power management mode of the pipe and plane.
3471 */
3472 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3473 {
3474 struct drm_device *dev = crtc->dev;
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476 struct drm_i915_master_private *master_priv;
3477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3478 int pipe = intel_crtc->pipe;
3479 bool enabled;
3480
3481 if (intel_crtc->dpms_mode == mode)
3482 return;
3483
3484 intel_crtc->dpms_mode = mode;
3485
3486 dev_priv->display.dpms(crtc, mode);
3487
3488 if (!dev->primary->master)
3489 return;
3490
3491 master_priv = dev->primary->master->driver_priv;
3492 if (!master_priv->sarea_priv)
3493 return;
3494
3495 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3496
3497 switch (pipe) {
3498 case 0:
3499 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3500 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3501 break;
3502 case 1:
3503 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3504 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3505 break;
3506 default:
3507 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3508 break;
3509 }
3510 }
3511
3512 static void intel_crtc_disable(struct drm_crtc *crtc)
3513 {
3514 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3515 struct drm_device *dev = crtc->dev;
3516 struct drm_i915_private *dev_priv = dev->dev_private;
3517
3518 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3519 dev_priv->display.off(crtc);
3520
3521 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3522 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3523
3524 if (crtc->fb) {
3525 mutex_lock(&dev->struct_mutex);
3526 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3527 mutex_unlock(&dev->struct_mutex);
3528 }
3529 }
3530
3531 /* Prepare for a mode set.
3532 *
3533 * Note we could be a lot smarter here. We need to figure out which outputs
3534 * will be enabled, which disabled (in short, how the config will changes)
3535 * and perform the minimum necessary steps to accomplish that, e.g. updating
3536 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3537 * panel fitting is in the proper state, etc.
3538 */
3539 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3540 {
3541 i9xx_crtc_disable(crtc);
3542 }
3543
3544 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3545 {
3546 i9xx_crtc_enable(crtc);
3547 }
3548
3549 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3550 {
3551 ironlake_crtc_disable(crtc);
3552 }
3553
3554 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3555 {
3556 ironlake_crtc_enable(crtc);
3557 }
3558
3559 void intel_encoder_prepare(struct drm_encoder *encoder)
3560 {
3561 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3562 /* lvds has its own version of prepare see intel_lvds_prepare */
3563 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3564 }
3565
3566 void intel_encoder_commit(struct drm_encoder *encoder)
3567 {
3568 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3569 struct drm_device *dev = encoder->dev;
3570 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3571
3572 /* lvds has its own version of commit see intel_lvds_commit */
3573 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3574
3575 if (HAS_PCH_CPT(dev))
3576 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3577 }
3578
3579 void intel_encoder_destroy(struct drm_encoder *encoder)
3580 {
3581 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3582
3583 drm_encoder_cleanup(encoder);
3584 kfree(intel_encoder);
3585 }
3586
3587 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3588 const struct drm_display_mode *mode,
3589 struct drm_display_mode *adjusted_mode)
3590 {
3591 struct drm_device *dev = crtc->dev;
3592
3593 if (HAS_PCH_SPLIT(dev)) {
3594 /* FDI link clock is fixed at 2.7G */
3595 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3596 return false;
3597 }
3598
3599 /* All interlaced capable intel hw wants timings in frames. Note though
3600 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3601 * timings, so we need to be careful not to clobber these.*/
3602 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3603 drm_mode_set_crtcinfo(adjusted_mode, 0);
3604
3605 return true;
3606 }
3607
3608 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3609 {
3610 return 400000; /* FIXME */
3611 }
3612
3613 static int i945_get_display_clock_speed(struct drm_device *dev)
3614 {
3615 return 400000;
3616 }
3617
3618 static int i915_get_display_clock_speed(struct drm_device *dev)
3619 {
3620 return 333000;
3621 }
3622
3623 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3624 {
3625 return 200000;
3626 }
3627
3628 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3629 {
3630 u16 gcfgc = 0;
3631
3632 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3633
3634 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3635 return 133000;
3636 else {
3637 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3638 case GC_DISPLAY_CLOCK_333_MHZ:
3639 return 333000;
3640 default:
3641 case GC_DISPLAY_CLOCK_190_200_MHZ:
3642 return 190000;
3643 }
3644 }
3645 }
3646
3647 static int i865_get_display_clock_speed(struct drm_device *dev)
3648 {
3649 return 266000;
3650 }
3651
3652 static int i855_get_display_clock_speed(struct drm_device *dev)
3653 {
3654 u16 hpllcc = 0;
3655 /* Assume that the hardware is in the high speed state. This
3656 * should be the default.
3657 */
3658 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3659 case GC_CLOCK_133_200:
3660 case GC_CLOCK_100_200:
3661 return 200000;
3662 case GC_CLOCK_166_250:
3663 return 250000;
3664 case GC_CLOCK_100_133:
3665 return 133000;
3666 }
3667
3668 /* Shouldn't happen */
3669 return 0;
3670 }
3671
3672 static int i830_get_display_clock_speed(struct drm_device *dev)
3673 {
3674 return 133000;
3675 }
3676
3677 struct fdi_m_n {
3678 u32 tu;
3679 u32 gmch_m;
3680 u32 gmch_n;
3681 u32 link_m;
3682 u32 link_n;
3683 };
3684
3685 static void
3686 fdi_reduce_ratio(u32 *num, u32 *den)
3687 {
3688 while (*num > 0xffffff || *den > 0xffffff) {
3689 *num >>= 1;
3690 *den >>= 1;
3691 }
3692 }
3693
3694 static void
3695 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3696 int link_clock, struct fdi_m_n *m_n)
3697 {
3698 m_n->tu = 64; /* default size */
3699
3700 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3701 m_n->gmch_m = bits_per_pixel * pixel_clock;
3702 m_n->gmch_n = link_clock * nlanes * 8;
3703 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3704
3705 m_n->link_m = pixel_clock;
3706 m_n->link_n = link_clock;
3707 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3708 }
3709
3710 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3711 {
3712 if (i915_panel_use_ssc >= 0)
3713 return i915_panel_use_ssc != 0;
3714 return dev_priv->lvds_use_ssc
3715 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3716 }
3717
3718 /**
3719 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3720 * @crtc: CRTC structure
3721 * @mode: requested mode
3722 *
3723 * A pipe may be connected to one or more outputs. Based on the depth of the
3724 * attached framebuffer, choose a good color depth to use on the pipe.
3725 *
3726 * If possible, match the pipe depth to the fb depth. In some cases, this
3727 * isn't ideal, because the connected output supports a lesser or restricted
3728 * set of depths. Resolve that here:
3729 * LVDS typically supports only 6bpc, so clamp down in that case
3730 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3731 * Displays may support a restricted set as well, check EDID and clamp as
3732 * appropriate.
3733 * DP may want to dither down to 6bpc to fit larger modes
3734 *
3735 * RETURNS:
3736 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3737 * true if they don't match).
3738 */
3739 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3740 unsigned int *pipe_bpp,
3741 struct drm_display_mode *mode)
3742 {
3743 struct drm_device *dev = crtc->dev;
3744 struct drm_i915_private *dev_priv = dev->dev_private;
3745 struct drm_connector *connector;
3746 struct intel_encoder *intel_encoder;
3747 unsigned int display_bpc = UINT_MAX, bpc;
3748
3749 /* Walk the encoders & connectors on this crtc, get min bpc */
3750 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3751
3752 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3753 unsigned int lvds_bpc;
3754
3755 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3756 LVDS_A3_POWER_UP)
3757 lvds_bpc = 8;
3758 else
3759 lvds_bpc = 6;
3760
3761 if (lvds_bpc < display_bpc) {
3762 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3763 display_bpc = lvds_bpc;
3764 }
3765 continue;
3766 }
3767
3768 /* Not one of the known troublemakers, check the EDID */
3769 list_for_each_entry(connector, &dev->mode_config.connector_list,
3770 head) {
3771 if (connector->encoder != &intel_encoder->base)
3772 continue;
3773
3774 /* Don't use an invalid EDID bpc value */
3775 if (connector->display_info.bpc &&
3776 connector->display_info.bpc < display_bpc) {
3777 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3778 display_bpc = connector->display_info.bpc;
3779 }
3780 }
3781
3782 /*
3783 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3784 * through, clamp it down. (Note: >12bpc will be caught below.)
3785 */
3786 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3787 if (display_bpc > 8 && display_bpc < 12) {
3788 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3789 display_bpc = 12;
3790 } else {
3791 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3792 display_bpc = 8;
3793 }
3794 }
3795 }
3796
3797 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3798 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3799 display_bpc = 6;
3800 }
3801
3802 /*
3803 * We could just drive the pipe at the highest bpc all the time and
3804 * enable dithering as needed, but that costs bandwidth. So choose
3805 * the minimum value that expresses the full color range of the fb but
3806 * also stays within the max display bpc discovered above.
3807 */
3808
3809 switch (crtc->fb->depth) {
3810 case 8:
3811 bpc = 8; /* since we go through a colormap */
3812 break;
3813 case 15:
3814 case 16:
3815 bpc = 6; /* min is 18bpp */
3816 break;
3817 case 24:
3818 bpc = 8;
3819 break;
3820 case 30:
3821 bpc = 10;
3822 break;
3823 case 48:
3824 bpc = 12;
3825 break;
3826 default:
3827 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3828 bpc = min((unsigned int)8, display_bpc);
3829 break;
3830 }
3831
3832 display_bpc = min(display_bpc, bpc);
3833
3834 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3835 bpc, display_bpc);
3836
3837 *pipe_bpp = display_bpc * 3;
3838
3839 return display_bpc != bpc;
3840 }
3841
3842 static int vlv_get_refclk(struct drm_crtc *crtc)
3843 {
3844 struct drm_device *dev = crtc->dev;
3845 struct drm_i915_private *dev_priv = dev->dev_private;
3846 int refclk = 27000; /* for DP & HDMI */
3847
3848 return 100000; /* only one validated so far */
3849
3850 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3851 refclk = 96000;
3852 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3853 if (intel_panel_use_ssc(dev_priv))
3854 refclk = 100000;
3855 else
3856 refclk = 96000;
3857 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3858 refclk = 100000;
3859 }
3860
3861 return refclk;
3862 }
3863
3864 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3865 {
3866 struct drm_device *dev = crtc->dev;
3867 struct drm_i915_private *dev_priv = dev->dev_private;
3868 int refclk;
3869
3870 if (IS_VALLEYVIEW(dev)) {
3871 refclk = vlv_get_refclk(crtc);
3872 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3873 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3874 refclk = dev_priv->lvds_ssc_freq * 1000;
3875 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3876 refclk / 1000);
3877 } else if (!IS_GEN2(dev)) {
3878 refclk = 96000;
3879 } else {
3880 refclk = 48000;
3881 }
3882
3883 return refclk;
3884 }
3885
3886 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3887 intel_clock_t *clock)
3888 {
3889 /* SDVO TV has fixed PLL values depend on its clock range,
3890 this mirrors vbios setting. */
3891 if (adjusted_mode->clock >= 100000
3892 && adjusted_mode->clock < 140500) {
3893 clock->p1 = 2;
3894 clock->p2 = 10;
3895 clock->n = 3;
3896 clock->m1 = 16;
3897 clock->m2 = 8;
3898 } else if (adjusted_mode->clock >= 140500
3899 && adjusted_mode->clock <= 200000) {
3900 clock->p1 = 1;
3901 clock->p2 = 10;
3902 clock->n = 6;
3903 clock->m1 = 12;
3904 clock->m2 = 8;
3905 }
3906 }
3907
3908 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3909 intel_clock_t *clock,
3910 intel_clock_t *reduced_clock)
3911 {
3912 struct drm_device *dev = crtc->dev;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3915 int pipe = intel_crtc->pipe;
3916 u32 fp, fp2 = 0;
3917
3918 if (IS_PINEVIEW(dev)) {
3919 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3920 if (reduced_clock)
3921 fp2 = (1 << reduced_clock->n) << 16 |
3922 reduced_clock->m1 << 8 | reduced_clock->m2;
3923 } else {
3924 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3925 if (reduced_clock)
3926 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3927 reduced_clock->m2;
3928 }
3929
3930 I915_WRITE(FP0(pipe), fp);
3931
3932 intel_crtc->lowfreq_avail = false;
3933 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3934 reduced_clock && i915_powersave) {
3935 I915_WRITE(FP1(pipe), fp2);
3936 intel_crtc->lowfreq_avail = true;
3937 } else {
3938 I915_WRITE(FP1(pipe), fp);
3939 }
3940 }
3941
3942 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3943 struct drm_display_mode *adjusted_mode)
3944 {
3945 struct drm_device *dev = crtc->dev;
3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3948 int pipe = intel_crtc->pipe;
3949 u32 temp;
3950
3951 temp = I915_READ(LVDS);
3952 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3953 if (pipe == 1) {
3954 temp |= LVDS_PIPEB_SELECT;
3955 } else {
3956 temp &= ~LVDS_PIPEB_SELECT;
3957 }
3958 /* set the corresponsding LVDS_BORDER bit */
3959 temp |= dev_priv->lvds_border_bits;
3960 /* Set the B0-B3 data pairs corresponding to whether we're going to
3961 * set the DPLLs for dual-channel mode or not.
3962 */
3963 if (clock->p2 == 7)
3964 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3965 else
3966 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3967
3968 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3969 * appropriately here, but we need to look more thoroughly into how
3970 * panels behave in the two modes.
3971 */
3972 /* set the dithering flag on LVDS as needed */
3973 if (INTEL_INFO(dev)->gen >= 4) {
3974 if (dev_priv->lvds_dither)
3975 temp |= LVDS_ENABLE_DITHER;
3976 else
3977 temp &= ~LVDS_ENABLE_DITHER;
3978 }
3979 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3980 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3981 temp |= LVDS_HSYNC_POLARITY;
3982 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3983 temp |= LVDS_VSYNC_POLARITY;
3984 I915_WRITE(LVDS, temp);
3985 }
3986
3987 static void vlv_update_pll(struct drm_crtc *crtc,
3988 struct drm_display_mode *mode,
3989 struct drm_display_mode *adjusted_mode,
3990 intel_clock_t *clock, intel_clock_t *reduced_clock,
3991 int refclk, int num_connectors)
3992 {
3993 struct drm_device *dev = crtc->dev;
3994 struct drm_i915_private *dev_priv = dev->dev_private;
3995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996 int pipe = intel_crtc->pipe;
3997 u32 dpll, mdiv, pdiv;
3998 u32 bestn, bestm1, bestm2, bestp1, bestp2;
3999 bool is_hdmi;
4000
4001 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4002
4003 bestn = clock->n;
4004 bestm1 = clock->m1;
4005 bestm2 = clock->m2;
4006 bestp1 = clock->p1;
4007 bestp2 = clock->p2;
4008
4009 /* Enable DPIO clock input */
4010 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4011 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4012 I915_WRITE(DPLL(pipe), dpll);
4013 POSTING_READ(DPLL(pipe));
4014
4015 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4016 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4017 mdiv |= ((bestn << DPIO_N_SHIFT));
4018 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4019 mdiv |= (1 << DPIO_K_SHIFT);
4020 mdiv |= DPIO_ENABLE_CALIBRATION;
4021 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4022
4023 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4024
4025 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4026 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4027 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4028 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4029
4030 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4031
4032 dpll |= DPLL_VCO_ENABLE;
4033 I915_WRITE(DPLL(pipe), dpll);
4034 POSTING_READ(DPLL(pipe));
4035 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4036 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4037
4038 if (is_hdmi) {
4039 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4040
4041 if (temp > 1)
4042 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4043 else
4044 temp = 0;
4045
4046 I915_WRITE(DPLL_MD(pipe), temp);
4047 POSTING_READ(DPLL_MD(pipe));
4048 }
4049
4050 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4051 }
4052
4053 static void i9xx_update_pll(struct drm_crtc *crtc,
4054 struct drm_display_mode *mode,
4055 struct drm_display_mode *adjusted_mode,
4056 intel_clock_t *clock, intel_clock_t *reduced_clock,
4057 int num_connectors)
4058 {
4059 struct drm_device *dev = crtc->dev;
4060 struct drm_i915_private *dev_priv = dev->dev_private;
4061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4062 int pipe = intel_crtc->pipe;
4063 u32 dpll;
4064 bool is_sdvo;
4065
4066 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4067 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4068
4069 dpll = DPLL_VGA_MODE_DIS;
4070
4071 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4072 dpll |= DPLLB_MODE_LVDS;
4073 else
4074 dpll |= DPLLB_MODE_DAC_SERIAL;
4075 if (is_sdvo) {
4076 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4077 if (pixel_multiplier > 1) {
4078 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4079 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4080 }
4081 dpll |= DPLL_DVO_HIGH_SPEED;
4082 }
4083 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4084 dpll |= DPLL_DVO_HIGH_SPEED;
4085
4086 /* compute bitmask from p1 value */
4087 if (IS_PINEVIEW(dev))
4088 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4089 else {
4090 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4091 if (IS_G4X(dev) && reduced_clock)
4092 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4093 }
4094 switch (clock->p2) {
4095 case 5:
4096 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4097 break;
4098 case 7:
4099 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4100 break;
4101 case 10:
4102 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4103 break;
4104 case 14:
4105 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4106 break;
4107 }
4108 if (INTEL_INFO(dev)->gen >= 4)
4109 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4110
4111 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4112 dpll |= PLL_REF_INPUT_TVCLKINBC;
4113 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4114 /* XXX: just matching BIOS for now */
4115 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4116 dpll |= 3;
4117 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4118 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4119 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4120 else
4121 dpll |= PLL_REF_INPUT_DREFCLK;
4122
4123 dpll |= DPLL_VCO_ENABLE;
4124 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4125 POSTING_READ(DPLL(pipe));
4126 udelay(150);
4127
4128 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4129 * This is an exception to the general rule that mode_set doesn't turn
4130 * things on.
4131 */
4132 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4133 intel_update_lvds(crtc, clock, adjusted_mode);
4134
4135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4136 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4137
4138 I915_WRITE(DPLL(pipe), dpll);
4139
4140 /* Wait for the clocks to stabilize. */
4141 POSTING_READ(DPLL(pipe));
4142 udelay(150);
4143
4144 if (INTEL_INFO(dev)->gen >= 4) {
4145 u32 temp = 0;
4146 if (is_sdvo) {
4147 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4148 if (temp > 1)
4149 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4150 else
4151 temp = 0;
4152 }
4153 I915_WRITE(DPLL_MD(pipe), temp);
4154 } else {
4155 /* The pixel multiplier can only be updated once the
4156 * DPLL is enabled and the clocks are stable.
4157 *
4158 * So write it again.
4159 */
4160 I915_WRITE(DPLL(pipe), dpll);
4161 }
4162 }
4163
4164 static void i8xx_update_pll(struct drm_crtc *crtc,
4165 struct drm_display_mode *adjusted_mode,
4166 intel_clock_t *clock,
4167 int num_connectors)
4168 {
4169 struct drm_device *dev = crtc->dev;
4170 struct drm_i915_private *dev_priv = dev->dev_private;
4171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4172 int pipe = intel_crtc->pipe;
4173 u32 dpll;
4174
4175 dpll = DPLL_VGA_MODE_DIS;
4176
4177 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4178 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4179 } else {
4180 if (clock->p1 == 2)
4181 dpll |= PLL_P1_DIVIDE_BY_TWO;
4182 else
4183 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4184 if (clock->p2 == 4)
4185 dpll |= PLL_P2_DIVIDE_BY_4;
4186 }
4187
4188 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4189 /* XXX: just matching BIOS for now */
4190 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4191 dpll |= 3;
4192 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4193 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4194 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4195 else
4196 dpll |= PLL_REF_INPUT_DREFCLK;
4197
4198 dpll |= DPLL_VCO_ENABLE;
4199 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4200 POSTING_READ(DPLL(pipe));
4201 udelay(150);
4202
4203 I915_WRITE(DPLL(pipe), dpll);
4204
4205 /* Wait for the clocks to stabilize. */
4206 POSTING_READ(DPLL(pipe));
4207 udelay(150);
4208
4209 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4210 * This is an exception to the general rule that mode_set doesn't turn
4211 * things on.
4212 */
4213 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4214 intel_update_lvds(crtc, clock, adjusted_mode);
4215
4216 /* The pixel multiplier can only be updated once the
4217 * DPLL is enabled and the clocks are stable.
4218 *
4219 * So write it again.
4220 */
4221 I915_WRITE(DPLL(pipe), dpll);
4222 }
4223
4224 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4225 struct drm_display_mode *mode,
4226 struct drm_display_mode *adjusted_mode,
4227 int x, int y,
4228 struct drm_framebuffer *old_fb)
4229 {
4230 struct drm_device *dev = crtc->dev;
4231 struct drm_i915_private *dev_priv = dev->dev_private;
4232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233 int pipe = intel_crtc->pipe;
4234 int plane = intel_crtc->plane;
4235 int refclk, num_connectors = 0;
4236 intel_clock_t clock, reduced_clock;
4237 u32 dspcntr, pipeconf, vsyncshift;
4238 bool ok, has_reduced_clock = false, is_sdvo = false;
4239 bool is_lvds = false, is_tv = false, is_dp = false;
4240 struct intel_encoder *encoder;
4241 const intel_limit_t *limit;
4242 int ret;
4243
4244 for_each_encoder_on_crtc(dev, crtc, encoder) {
4245 switch (encoder->type) {
4246 case INTEL_OUTPUT_LVDS:
4247 is_lvds = true;
4248 break;
4249 case INTEL_OUTPUT_SDVO:
4250 case INTEL_OUTPUT_HDMI:
4251 is_sdvo = true;
4252 if (encoder->needs_tv_clock)
4253 is_tv = true;
4254 break;
4255 case INTEL_OUTPUT_TVOUT:
4256 is_tv = true;
4257 break;
4258 case INTEL_OUTPUT_DISPLAYPORT:
4259 is_dp = true;
4260 break;
4261 }
4262
4263 num_connectors++;
4264 }
4265
4266 refclk = i9xx_get_refclk(crtc, num_connectors);
4267
4268 /*
4269 * Returns a set of divisors for the desired target clock with the given
4270 * refclk, or FALSE. The returned values represent the clock equation:
4271 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4272 */
4273 limit = intel_limit(crtc, refclk);
4274 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4275 &clock);
4276 if (!ok) {
4277 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4278 return -EINVAL;
4279 }
4280
4281 /* Ensure that the cursor is valid for the new mode before changing... */
4282 intel_crtc_update_cursor(crtc, true);
4283
4284 if (is_lvds && dev_priv->lvds_downclock_avail) {
4285 /*
4286 * Ensure we match the reduced clock's P to the target clock.
4287 * If the clocks don't match, we can't switch the display clock
4288 * by using the FP0/FP1. In such case we will disable the LVDS
4289 * downclock feature.
4290 */
4291 has_reduced_clock = limit->find_pll(limit, crtc,
4292 dev_priv->lvds_downclock,
4293 refclk,
4294 &clock,
4295 &reduced_clock);
4296 }
4297
4298 if (is_sdvo && is_tv)
4299 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4300
4301 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4302 &reduced_clock : NULL);
4303
4304 if (IS_GEN2(dev))
4305 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4306 else if (IS_VALLEYVIEW(dev))
4307 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4308 refclk, num_connectors);
4309 else
4310 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4311 has_reduced_clock ? &reduced_clock : NULL,
4312 num_connectors);
4313
4314 /* setup pipeconf */
4315 pipeconf = I915_READ(PIPECONF(pipe));
4316
4317 /* Set up the display plane register */
4318 dspcntr = DISPPLANE_GAMMA_ENABLE;
4319
4320 if (pipe == 0)
4321 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4322 else
4323 dspcntr |= DISPPLANE_SEL_PIPE_B;
4324
4325 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4326 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4327 * core speed.
4328 *
4329 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4330 * pipe == 0 check?
4331 */
4332 if (mode->clock >
4333 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4334 pipeconf |= PIPECONF_DOUBLE_WIDE;
4335 else
4336 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4337 }
4338
4339 /* default to 8bpc */
4340 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4341 if (is_dp) {
4342 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4343 pipeconf |= PIPECONF_BPP_6 |
4344 PIPECONF_DITHER_EN |
4345 PIPECONF_DITHER_TYPE_SP;
4346 }
4347 }
4348
4349 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4350 drm_mode_debug_printmodeline(mode);
4351
4352 if (HAS_PIPE_CXSR(dev)) {
4353 if (intel_crtc->lowfreq_avail) {
4354 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4355 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4356 } else {
4357 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4358 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4359 }
4360 }
4361
4362 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4363 if (!IS_GEN2(dev) &&
4364 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4365 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4366 /* the chip adds 2 halflines automatically */
4367 adjusted_mode->crtc_vtotal -= 1;
4368 adjusted_mode->crtc_vblank_end -= 1;
4369 vsyncshift = adjusted_mode->crtc_hsync_start
4370 - adjusted_mode->crtc_htotal/2;
4371 } else {
4372 pipeconf |= PIPECONF_PROGRESSIVE;
4373 vsyncshift = 0;
4374 }
4375
4376 if (!IS_GEN3(dev))
4377 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4378
4379 I915_WRITE(HTOTAL(pipe),
4380 (adjusted_mode->crtc_hdisplay - 1) |
4381 ((adjusted_mode->crtc_htotal - 1) << 16));
4382 I915_WRITE(HBLANK(pipe),
4383 (adjusted_mode->crtc_hblank_start - 1) |
4384 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4385 I915_WRITE(HSYNC(pipe),
4386 (adjusted_mode->crtc_hsync_start - 1) |
4387 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4388
4389 I915_WRITE(VTOTAL(pipe),
4390 (adjusted_mode->crtc_vdisplay - 1) |
4391 ((adjusted_mode->crtc_vtotal - 1) << 16));
4392 I915_WRITE(VBLANK(pipe),
4393 (adjusted_mode->crtc_vblank_start - 1) |
4394 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4395 I915_WRITE(VSYNC(pipe),
4396 (adjusted_mode->crtc_vsync_start - 1) |
4397 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4398
4399 /* pipesrc and dspsize control the size that is scaled from,
4400 * which should always be the user's requested size.
4401 */
4402 I915_WRITE(DSPSIZE(plane),
4403 ((mode->vdisplay - 1) << 16) |
4404 (mode->hdisplay - 1));
4405 I915_WRITE(DSPPOS(plane), 0);
4406 I915_WRITE(PIPESRC(pipe),
4407 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4408
4409 I915_WRITE(PIPECONF(pipe), pipeconf);
4410 POSTING_READ(PIPECONF(pipe));
4411 intel_enable_pipe(dev_priv, pipe, false);
4412
4413 intel_wait_for_vblank(dev, pipe);
4414
4415 I915_WRITE(DSPCNTR(plane), dspcntr);
4416 POSTING_READ(DSPCNTR(plane));
4417
4418 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4419
4420 intel_update_watermarks(dev);
4421
4422 return ret;
4423 }
4424
4425 /*
4426 * Initialize reference clocks when the driver loads
4427 */
4428 void ironlake_init_pch_refclk(struct drm_device *dev)
4429 {
4430 struct drm_i915_private *dev_priv = dev->dev_private;
4431 struct drm_mode_config *mode_config = &dev->mode_config;
4432 struct intel_encoder *encoder;
4433 u32 temp;
4434 bool has_lvds = false;
4435 bool has_cpu_edp = false;
4436 bool has_pch_edp = false;
4437 bool has_panel = false;
4438 bool has_ck505 = false;
4439 bool can_ssc = false;
4440
4441 /* We need to take the global config into account */
4442 list_for_each_entry(encoder, &mode_config->encoder_list,
4443 base.head) {
4444 switch (encoder->type) {
4445 case INTEL_OUTPUT_LVDS:
4446 has_panel = true;
4447 has_lvds = true;
4448 break;
4449 case INTEL_OUTPUT_EDP:
4450 has_panel = true;
4451 if (intel_encoder_is_pch_edp(&encoder->base))
4452 has_pch_edp = true;
4453 else
4454 has_cpu_edp = true;
4455 break;
4456 }
4457 }
4458
4459 if (HAS_PCH_IBX(dev)) {
4460 has_ck505 = dev_priv->display_clock_mode;
4461 can_ssc = has_ck505;
4462 } else {
4463 has_ck505 = false;
4464 can_ssc = true;
4465 }
4466
4467 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4468 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4469 has_ck505);
4470
4471 /* Ironlake: try to setup display ref clock before DPLL
4472 * enabling. This is only under driver's control after
4473 * PCH B stepping, previous chipset stepping should be
4474 * ignoring this setting.
4475 */
4476 temp = I915_READ(PCH_DREF_CONTROL);
4477 /* Always enable nonspread source */
4478 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4479
4480 if (has_ck505)
4481 temp |= DREF_NONSPREAD_CK505_ENABLE;
4482 else
4483 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4484
4485 if (has_panel) {
4486 temp &= ~DREF_SSC_SOURCE_MASK;
4487 temp |= DREF_SSC_SOURCE_ENABLE;
4488
4489 /* SSC must be turned on before enabling the CPU output */
4490 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4491 DRM_DEBUG_KMS("Using SSC on panel\n");
4492 temp |= DREF_SSC1_ENABLE;
4493 } else
4494 temp &= ~DREF_SSC1_ENABLE;
4495
4496 /* Get SSC going before enabling the outputs */
4497 I915_WRITE(PCH_DREF_CONTROL, temp);
4498 POSTING_READ(PCH_DREF_CONTROL);
4499 udelay(200);
4500
4501 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4502
4503 /* Enable CPU source on CPU attached eDP */
4504 if (has_cpu_edp) {
4505 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4506 DRM_DEBUG_KMS("Using SSC on eDP\n");
4507 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4508 }
4509 else
4510 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4511 } else
4512 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4513
4514 I915_WRITE(PCH_DREF_CONTROL, temp);
4515 POSTING_READ(PCH_DREF_CONTROL);
4516 udelay(200);
4517 } else {
4518 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4519
4520 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4521
4522 /* Turn off CPU output */
4523 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4524
4525 I915_WRITE(PCH_DREF_CONTROL, temp);
4526 POSTING_READ(PCH_DREF_CONTROL);
4527 udelay(200);
4528
4529 /* Turn off the SSC source */
4530 temp &= ~DREF_SSC_SOURCE_MASK;
4531 temp |= DREF_SSC_SOURCE_DISABLE;
4532
4533 /* Turn off SSC1 */
4534 temp &= ~ DREF_SSC1_ENABLE;
4535
4536 I915_WRITE(PCH_DREF_CONTROL, temp);
4537 POSTING_READ(PCH_DREF_CONTROL);
4538 udelay(200);
4539 }
4540 }
4541
4542 static int ironlake_get_refclk(struct drm_crtc *crtc)
4543 {
4544 struct drm_device *dev = crtc->dev;
4545 struct drm_i915_private *dev_priv = dev->dev_private;
4546 struct intel_encoder *encoder;
4547 struct intel_encoder *edp_encoder = NULL;
4548 int num_connectors = 0;
4549 bool is_lvds = false;
4550
4551 for_each_encoder_on_crtc(dev, crtc, encoder) {
4552 switch (encoder->type) {
4553 case INTEL_OUTPUT_LVDS:
4554 is_lvds = true;
4555 break;
4556 case INTEL_OUTPUT_EDP:
4557 edp_encoder = encoder;
4558 break;
4559 }
4560 num_connectors++;
4561 }
4562
4563 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4564 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4565 dev_priv->lvds_ssc_freq);
4566 return dev_priv->lvds_ssc_freq * 1000;
4567 }
4568
4569 return 120000;
4570 }
4571
4572 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4573 struct drm_display_mode *mode,
4574 struct drm_display_mode *adjusted_mode,
4575 int x, int y,
4576 struct drm_framebuffer *old_fb)
4577 {
4578 struct drm_device *dev = crtc->dev;
4579 struct drm_i915_private *dev_priv = dev->dev_private;
4580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4581 int pipe = intel_crtc->pipe;
4582 int plane = intel_crtc->plane;
4583 int refclk, num_connectors = 0;
4584 intel_clock_t clock, reduced_clock;
4585 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4586 bool ok, has_reduced_clock = false, is_sdvo = false;
4587 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4588 struct intel_encoder *encoder, *edp_encoder = NULL;
4589 const intel_limit_t *limit;
4590 int ret;
4591 struct fdi_m_n m_n = {0};
4592 u32 temp;
4593 int target_clock, pixel_multiplier, lane, link_bw, factor;
4594 unsigned int pipe_bpp;
4595 bool dither;
4596 bool is_cpu_edp = false, is_pch_edp = false;
4597
4598 for_each_encoder_on_crtc(dev, crtc, encoder) {
4599 switch (encoder->type) {
4600 case INTEL_OUTPUT_LVDS:
4601 is_lvds = true;
4602 break;
4603 case INTEL_OUTPUT_SDVO:
4604 case INTEL_OUTPUT_HDMI:
4605 is_sdvo = true;
4606 if (encoder->needs_tv_clock)
4607 is_tv = true;
4608 break;
4609 case INTEL_OUTPUT_TVOUT:
4610 is_tv = true;
4611 break;
4612 case INTEL_OUTPUT_ANALOG:
4613 is_crt = true;
4614 break;
4615 case INTEL_OUTPUT_DISPLAYPORT:
4616 is_dp = true;
4617 break;
4618 case INTEL_OUTPUT_EDP:
4619 is_dp = true;
4620 if (intel_encoder_is_pch_edp(&encoder->base))
4621 is_pch_edp = true;
4622 else
4623 is_cpu_edp = true;
4624 edp_encoder = encoder;
4625 break;
4626 }
4627
4628 num_connectors++;
4629 }
4630
4631 refclk = ironlake_get_refclk(crtc);
4632
4633 /*
4634 * Returns a set of divisors for the desired target clock with the given
4635 * refclk, or FALSE. The returned values represent the clock equation:
4636 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4637 */
4638 limit = intel_limit(crtc, refclk);
4639 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4640 &clock);
4641 if (!ok) {
4642 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4643 return -EINVAL;
4644 }
4645
4646 /* Ensure that the cursor is valid for the new mode before changing... */
4647 intel_crtc_update_cursor(crtc, true);
4648
4649 if (is_lvds && dev_priv->lvds_downclock_avail) {
4650 /*
4651 * Ensure we match the reduced clock's P to the target clock.
4652 * If the clocks don't match, we can't switch the display clock
4653 * by using the FP0/FP1. In such case we will disable the LVDS
4654 * downclock feature.
4655 */
4656 has_reduced_clock = limit->find_pll(limit, crtc,
4657 dev_priv->lvds_downclock,
4658 refclk,
4659 &clock,
4660 &reduced_clock);
4661 }
4662
4663 if (is_sdvo && is_tv)
4664 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4665
4666
4667 /* FDI link */
4668 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4669 lane = 0;
4670 /* CPU eDP doesn't require FDI link, so just set DP M/N
4671 according to current link config */
4672 if (is_cpu_edp) {
4673 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4674 } else {
4675 /* FDI is a binary signal running at ~2.7GHz, encoding
4676 * each output octet as 10 bits. The actual frequency
4677 * is stored as a divider into a 100MHz clock, and the
4678 * mode pixel clock is stored in units of 1KHz.
4679 * Hence the bw of each lane in terms of the mode signal
4680 * is:
4681 */
4682 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4683 }
4684
4685 /* [e]DP over FDI requires target mode clock instead of link clock. */
4686 if (edp_encoder)
4687 target_clock = intel_edp_target_clock(edp_encoder, mode);
4688 else if (is_dp)
4689 target_clock = mode->clock;
4690 else
4691 target_clock = adjusted_mode->clock;
4692
4693 /* determine panel color depth */
4694 temp = I915_READ(PIPECONF(pipe));
4695 temp &= ~PIPE_BPC_MASK;
4696 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4697 switch (pipe_bpp) {
4698 case 18:
4699 temp |= PIPE_6BPC;
4700 break;
4701 case 24:
4702 temp |= PIPE_8BPC;
4703 break;
4704 case 30:
4705 temp |= PIPE_10BPC;
4706 break;
4707 case 36:
4708 temp |= PIPE_12BPC;
4709 break;
4710 default:
4711 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4712 pipe_bpp);
4713 temp |= PIPE_8BPC;
4714 pipe_bpp = 24;
4715 break;
4716 }
4717
4718 intel_crtc->bpp = pipe_bpp;
4719 I915_WRITE(PIPECONF(pipe), temp);
4720
4721 if (!lane) {
4722 /*
4723 * Account for spread spectrum to avoid
4724 * oversubscribing the link. Max center spread
4725 * is 2.5%; use 5% for safety's sake.
4726 */
4727 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4728 lane = bps / (link_bw * 8) + 1;
4729 }
4730
4731 intel_crtc->fdi_lanes = lane;
4732
4733 if (pixel_multiplier > 1)
4734 link_bw *= pixel_multiplier;
4735 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4736 &m_n);
4737
4738 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4739 if (has_reduced_clock)
4740 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4741 reduced_clock.m2;
4742
4743 /* Enable autotuning of the PLL clock (if permissible) */
4744 factor = 21;
4745 if (is_lvds) {
4746 if ((intel_panel_use_ssc(dev_priv) &&
4747 dev_priv->lvds_ssc_freq == 100) ||
4748 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4749 factor = 25;
4750 } else if (is_sdvo && is_tv)
4751 factor = 20;
4752
4753 if (clock.m < factor * clock.n)
4754 fp |= FP_CB_TUNE;
4755
4756 dpll = 0;
4757
4758 if (is_lvds)
4759 dpll |= DPLLB_MODE_LVDS;
4760 else
4761 dpll |= DPLLB_MODE_DAC_SERIAL;
4762 if (is_sdvo) {
4763 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4764 if (pixel_multiplier > 1) {
4765 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4766 }
4767 dpll |= DPLL_DVO_HIGH_SPEED;
4768 }
4769 if (is_dp && !is_cpu_edp)
4770 dpll |= DPLL_DVO_HIGH_SPEED;
4771
4772 /* compute bitmask from p1 value */
4773 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4774 /* also FPA1 */
4775 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4776
4777 switch (clock.p2) {
4778 case 5:
4779 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4780 break;
4781 case 7:
4782 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4783 break;
4784 case 10:
4785 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4786 break;
4787 case 14:
4788 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4789 break;
4790 }
4791
4792 if (is_sdvo && is_tv)
4793 dpll |= PLL_REF_INPUT_TVCLKINBC;
4794 else if (is_tv)
4795 /* XXX: just matching BIOS for now */
4796 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4797 dpll |= 3;
4798 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4799 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4800 else
4801 dpll |= PLL_REF_INPUT_DREFCLK;
4802
4803 /* setup pipeconf */
4804 pipeconf = I915_READ(PIPECONF(pipe));
4805
4806 /* Set up the display plane register */
4807 dspcntr = DISPPLANE_GAMMA_ENABLE;
4808
4809 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4810 drm_mode_debug_printmodeline(mode);
4811
4812 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4813 * pre-Haswell/LPT generation */
4814 if (HAS_PCH_LPT(dev)) {
4815 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4816 pipe);
4817 } else if (!is_cpu_edp) {
4818 struct intel_pch_pll *pll;
4819
4820 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4821 if (pll == NULL) {
4822 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4823 pipe);
4824 return -EINVAL;
4825 }
4826 } else
4827 intel_put_pch_pll(intel_crtc);
4828
4829 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4830 * This is an exception to the general rule that mode_set doesn't turn
4831 * things on.
4832 */
4833 if (is_lvds) {
4834 temp = I915_READ(PCH_LVDS);
4835 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4836 if (HAS_PCH_CPT(dev)) {
4837 temp &= ~PORT_TRANS_SEL_MASK;
4838 temp |= PORT_TRANS_SEL_CPT(pipe);
4839 } else {
4840 if (pipe == 1)
4841 temp |= LVDS_PIPEB_SELECT;
4842 else
4843 temp &= ~LVDS_PIPEB_SELECT;
4844 }
4845
4846 /* set the corresponsding LVDS_BORDER bit */
4847 temp |= dev_priv->lvds_border_bits;
4848 /* Set the B0-B3 data pairs corresponding to whether we're going to
4849 * set the DPLLs for dual-channel mode or not.
4850 */
4851 if (clock.p2 == 7)
4852 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4853 else
4854 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4855
4856 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4857 * appropriately here, but we need to look more thoroughly into how
4858 * panels behave in the two modes.
4859 */
4860 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4861 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4862 temp |= LVDS_HSYNC_POLARITY;
4863 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4864 temp |= LVDS_VSYNC_POLARITY;
4865 I915_WRITE(PCH_LVDS, temp);
4866 }
4867
4868 pipeconf &= ~PIPECONF_DITHER_EN;
4869 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4870 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4871 pipeconf |= PIPECONF_DITHER_EN;
4872 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4873 }
4874 if (is_dp && !is_cpu_edp) {
4875 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4876 } else {
4877 /* For non-DP output, clear any trans DP clock recovery setting.*/
4878 I915_WRITE(TRANSDATA_M1(pipe), 0);
4879 I915_WRITE(TRANSDATA_N1(pipe), 0);
4880 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4881 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4882 }
4883
4884 if (intel_crtc->pch_pll) {
4885 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4886
4887 /* Wait for the clocks to stabilize. */
4888 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4889 udelay(150);
4890
4891 /* The pixel multiplier can only be updated once the
4892 * DPLL is enabled and the clocks are stable.
4893 *
4894 * So write it again.
4895 */
4896 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4897 }
4898
4899 intel_crtc->lowfreq_avail = false;
4900 if (intel_crtc->pch_pll) {
4901 if (is_lvds && has_reduced_clock && i915_powersave) {
4902 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4903 intel_crtc->lowfreq_avail = true;
4904 } else {
4905 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4906 }
4907 }
4908
4909 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4910 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4911 pipeconf |= PIPECONF_INTERLACED_ILK;
4912 /* the chip adds 2 halflines automatically */
4913 adjusted_mode->crtc_vtotal -= 1;
4914 adjusted_mode->crtc_vblank_end -= 1;
4915 I915_WRITE(VSYNCSHIFT(pipe),
4916 adjusted_mode->crtc_hsync_start
4917 - adjusted_mode->crtc_htotal/2);
4918 } else {
4919 pipeconf |= PIPECONF_PROGRESSIVE;
4920 I915_WRITE(VSYNCSHIFT(pipe), 0);
4921 }
4922
4923 I915_WRITE(HTOTAL(pipe),
4924 (adjusted_mode->crtc_hdisplay - 1) |
4925 ((adjusted_mode->crtc_htotal - 1) << 16));
4926 I915_WRITE(HBLANK(pipe),
4927 (adjusted_mode->crtc_hblank_start - 1) |
4928 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4929 I915_WRITE(HSYNC(pipe),
4930 (adjusted_mode->crtc_hsync_start - 1) |
4931 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4932
4933 I915_WRITE(VTOTAL(pipe),
4934 (adjusted_mode->crtc_vdisplay - 1) |
4935 ((adjusted_mode->crtc_vtotal - 1) << 16));
4936 I915_WRITE(VBLANK(pipe),
4937 (adjusted_mode->crtc_vblank_start - 1) |
4938 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4939 I915_WRITE(VSYNC(pipe),
4940 (adjusted_mode->crtc_vsync_start - 1) |
4941 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4942
4943 /* pipesrc controls the size that is scaled from, which should
4944 * always be the user's requested size.
4945 */
4946 I915_WRITE(PIPESRC(pipe),
4947 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4948
4949 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4950 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4951 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4952 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4953
4954 if (is_cpu_edp)
4955 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4956
4957 I915_WRITE(PIPECONF(pipe), pipeconf);
4958 POSTING_READ(PIPECONF(pipe));
4959
4960 intel_wait_for_vblank(dev, pipe);
4961
4962 I915_WRITE(DSPCNTR(plane), dspcntr);
4963 POSTING_READ(DSPCNTR(plane));
4964
4965 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4966
4967 intel_update_watermarks(dev);
4968
4969 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4970
4971 return ret;
4972 }
4973
4974 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4975 struct drm_display_mode *mode,
4976 struct drm_display_mode *adjusted_mode,
4977 int x, int y,
4978 struct drm_framebuffer *old_fb)
4979 {
4980 struct drm_device *dev = crtc->dev;
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4983 int pipe = intel_crtc->pipe;
4984 int ret;
4985
4986 drm_vblank_pre_modeset(dev, pipe);
4987
4988 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4989 x, y, old_fb);
4990 drm_vblank_post_modeset(dev, pipe);
4991
4992 if (ret)
4993 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4994 else
4995 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4996
4997 return ret;
4998 }
4999
5000 static bool intel_eld_uptodate(struct drm_connector *connector,
5001 int reg_eldv, uint32_t bits_eldv,
5002 int reg_elda, uint32_t bits_elda,
5003 int reg_edid)
5004 {
5005 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5006 uint8_t *eld = connector->eld;
5007 uint32_t i;
5008
5009 i = I915_READ(reg_eldv);
5010 i &= bits_eldv;
5011
5012 if (!eld[0])
5013 return !i;
5014
5015 if (!i)
5016 return false;
5017
5018 i = I915_READ(reg_elda);
5019 i &= ~bits_elda;
5020 I915_WRITE(reg_elda, i);
5021
5022 for (i = 0; i < eld[2]; i++)
5023 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5024 return false;
5025
5026 return true;
5027 }
5028
5029 static void g4x_write_eld(struct drm_connector *connector,
5030 struct drm_crtc *crtc)
5031 {
5032 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5033 uint8_t *eld = connector->eld;
5034 uint32_t eldv;
5035 uint32_t len;
5036 uint32_t i;
5037
5038 i = I915_READ(G4X_AUD_VID_DID);
5039
5040 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5041 eldv = G4X_ELDV_DEVCL_DEVBLC;
5042 else
5043 eldv = G4X_ELDV_DEVCTG;
5044
5045 if (intel_eld_uptodate(connector,
5046 G4X_AUD_CNTL_ST, eldv,
5047 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5048 G4X_HDMIW_HDMIEDID))
5049 return;
5050
5051 i = I915_READ(G4X_AUD_CNTL_ST);
5052 i &= ~(eldv | G4X_ELD_ADDR);
5053 len = (i >> 9) & 0x1f; /* ELD buffer size */
5054 I915_WRITE(G4X_AUD_CNTL_ST, i);
5055
5056 if (!eld[0])
5057 return;
5058
5059 len = min_t(uint8_t, eld[2], len);
5060 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5061 for (i = 0; i < len; i++)
5062 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5063
5064 i = I915_READ(G4X_AUD_CNTL_ST);
5065 i |= eldv;
5066 I915_WRITE(G4X_AUD_CNTL_ST, i);
5067 }
5068
5069 static void ironlake_write_eld(struct drm_connector *connector,
5070 struct drm_crtc *crtc)
5071 {
5072 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5073 uint8_t *eld = connector->eld;
5074 uint32_t eldv;
5075 uint32_t i;
5076 int len;
5077 int hdmiw_hdmiedid;
5078 int aud_config;
5079 int aud_cntl_st;
5080 int aud_cntrl_st2;
5081
5082 if (HAS_PCH_IBX(connector->dev)) {
5083 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
5084 aud_config = IBX_AUD_CONFIG_A;
5085 aud_cntl_st = IBX_AUD_CNTL_ST_A;
5086 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5087 } else {
5088 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
5089 aud_config = CPT_AUD_CONFIG_A;
5090 aud_cntl_st = CPT_AUD_CNTL_ST_A;
5091 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5092 }
5093
5094 i = to_intel_crtc(crtc)->pipe;
5095 hdmiw_hdmiedid += i * 0x100;
5096 aud_cntl_st += i * 0x100;
5097 aud_config += i * 0x100;
5098
5099 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5100
5101 i = I915_READ(aud_cntl_st);
5102 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5103 if (!i) {
5104 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5105 /* operate blindly on all ports */
5106 eldv = IBX_ELD_VALIDB;
5107 eldv |= IBX_ELD_VALIDB << 4;
5108 eldv |= IBX_ELD_VALIDB << 8;
5109 } else {
5110 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5111 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5112 }
5113
5114 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5115 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5116 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5117 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5118 } else
5119 I915_WRITE(aud_config, 0);
5120
5121 if (intel_eld_uptodate(connector,
5122 aud_cntrl_st2, eldv,
5123 aud_cntl_st, IBX_ELD_ADDRESS,
5124 hdmiw_hdmiedid))
5125 return;
5126
5127 i = I915_READ(aud_cntrl_st2);
5128 i &= ~eldv;
5129 I915_WRITE(aud_cntrl_st2, i);
5130
5131 if (!eld[0])
5132 return;
5133
5134 i = I915_READ(aud_cntl_st);
5135 i &= ~IBX_ELD_ADDRESS;
5136 I915_WRITE(aud_cntl_st, i);
5137
5138 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5139 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5140 for (i = 0; i < len; i++)
5141 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5142
5143 i = I915_READ(aud_cntrl_st2);
5144 i |= eldv;
5145 I915_WRITE(aud_cntrl_st2, i);
5146 }
5147
5148 void intel_write_eld(struct drm_encoder *encoder,
5149 struct drm_display_mode *mode)
5150 {
5151 struct drm_crtc *crtc = encoder->crtc;
5152 struct drm_connector *connector;
5153 struct drm_device *dev = encoder->dev;
5154 struct drm_i915_private *dev_priv = dev->dev_private;
5155
5156 connector = drm_select_eld(encoder, mode);
5157 if (!connector)
5158 return;
5159
5160 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5161 connector->base.id,
5162 drm_get_connector_name(connector),
5163 connector->encoder->base.id,
5164 drm_get_encoder_name(connector->encoder));
5165
5166 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5167
5168 if (dev_priv->display.write_eld)
5169 dev_priv->display.write_eld(connector, crtc);
5170 }
5171
5172 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5173 void intel_crtc_load_lut(struct drm_crtc *crtc)
5174 {
5175 struct drm_device *dev = crtc->dev;
5176 struct drm_i915_private *dev_priv = dev->dev_private;
5177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5178 int palreg = PALETTE(intel_crtc->pipe);
5179 int i;
5180
5181 /* The clocks have to be on to load the palette. */
5182 if (!crtc->enabled || !intel_crtc->active)
5183 return;
5184
5185 /* use legacy palette for Ironlake */
5186 if (HAS_PCH_SPLIT(dev))
5187 palreg = LGC_PALETTE(intel_crtc->pipe);
5188
5189 for (i = 0; i < 256; i++) {
5190 I915_WRITE(palreg + 4 * i,
5191 (intel_crtc->lut_r[i] << 16) |
5192 (intel_crtc->lut_g[i] << 8) |
5193 intel_crtc->lut_b[i]);
5194 }
5195 }
5196
5197 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5198 {
5199 struct drm_device *dev = crtc->dev;
5200 struct drm_i915_private *dev_priv = dev->dev_private;
5201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5202 bool visible = base != 0;
5203 u32 cntl;
5204
5205 if (intel_crtc->cursor_visible == visible)
5206 return;
5207
5208 cntl = I915_READ(_CURACNTR);
5209 if (visible) {
5210 /* On these chipsets we can only modify the base whilst
5211 * the cursor is disabled.
5212 */
5213 I915_WRITE(_CURABASE, base);
5214
5215 cntl &= ~(CURSOR_FORMAT_MASK);
5216 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5217 cntl |= CURSOR_ENABLE |
5218 CURSOR_GAMMA_ENABLE |
5219 CURSOR_FORMAT_ARGB;
5220 } else
5221 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5222 I915_WRITE(_CURACNTR, cntl);
5223
5224 intel_crtc->cursor_visible = visible;
5225 }
5226
5227 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5228 {
5229 struct drm_device *dev = crtc->dev;
5230 struct drm_i915_private *dev_priv = dev->dev_private;
5231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5232 int pipe = intel_crtc->pipe;
5233 bool visible = base != 0;
5234
5235 if (intel_crtc->cursor_visible != visible) {
5236 uint32_t cntl = I915_READ(CURCNTR(pipe));
5237 if (base) {
5238 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5239 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5240 cntl |= pipe << 28; /* Connect to correct pipe */
5241 } else {
5242 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5243 cntl |= CURSOR_MODE_DISABLE;
5244 }
5245 I915_WRITE(CURCNTR(pipe), cntl);
5246
5247 intel_crtc->cursor_visible = visible;
5248 }
5249 /* and commit changes on next vblank */
5250 I915_WRITE(CURBASE(pipe), base);
5251 }
5252
5253 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5254 {
5255 struct drm_device *dev = crtc->dev;
5256 struct drm_i915_private *dev_priv = dev->dev_private;
5257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5258 int pipe = intel_crtc->pipe;
5259 bool visible = base != 0;
5260
5261 if (intel_crtc->cursor_visible != visible) {
5262 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5263 if (base) {
5264 cntl &= ~CURSOR_MODE;
5265 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5266 } else {
5267 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5268 cntl |= CURSOR_MODE_DISABLE;
5269 }
5270 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5271
5272 intel_crtc->cursor_visible = visible;
5273 }
5274 /* and commit changes on next vblank */
5275 I915_WRITE(CURBASE_IVB(pipe), base);
5276 }
5277
5278 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5279 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5280 bool on)
5281 {
5282 struct drm_device *dev = crtc->dev;
5283 struct drm_i915_private *dev_priv = dev->dev_private;
5284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5285 int pipe = intel_crtc->pipe;
5286 int x = intel_crtc->cursor_x;
5287 int y = intel_crtc->cursor_y;
5288 u32 base, pos;
5289 bool visible;
5290
5291 pos = 0;
5292
5293 if (on && crtc->enabled && crtc->fb) {
5294 base = intel_crtc->cursor_addr;
5295 if (x > (int) crtc->fb->width)
5296 base = 0;
5297
5298 if (y > (int) crtc->fb->height)
5299 base = 0;
5300 } else
5301 base = 0;
5302
5303 if (x < 0) {
5304 if (x + intel_crtc->cursor_width < 0)
5305 base = 0;
5306
5307 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5308 x = -x;
5309 }
5310 pos |= x << CURSOR_X_SHIFT;
5311
5312 if (y < 0) {
5313 if (y + intel_crtc->cursor_height < 0)
5314 base = 0;
5315
5316 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5317 y = -y;
5318 }
5319 pos |= y << CURSOR_Y_SHIFT;
5320
5321 visible = base != 0;
5322 if (!visible && !intel_crtc->cursor_visible)
5323 return;
5324
5325 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5326 I915_WRITE(CURPOS_IVB(pipe), pos);
5327 ivb_update_cursor(crtc, base);
5328 } else {
5329 I915_WRITE(CURPOS(pipe), pos);
5330 if (IS_845G(dev) || IS_I865G(dev))
5331 i845_update_cursor(crtc, base);
5332 else
5333 i9xx_update_cursor(crtc, base);
5334 }
5335 }
5336
5337 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5338 struct drm_file *file,
5339 uint32_t handle,
5340 uint32_t width, uint32_t height)
5341 {
5342 struct drm_device *dev = crtc->dev;
5343 struct drm_i915_private *dev_priv = dev->dev_private;
5344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5345 struct drm_i915_gem_object *obj;
5346 uint32_t addr;
5347 int ret;
5348
5349 DRM_DEBUG_KMS("\n");
5350
5351 /* if we want to turn off the cursor ignore width and height */
5352 if (!handle) {
5353 DRM_DEBUG_KMS("cursor off\n");
5354 addr = 0;
5355 obj = NULL;
5356 mutex_lock(&dev->struct_mutex);
5357 goto finish;
5358 }
5359
5360 /* Currently we only support 64x64 cursors */
5361 if (width != 64 || height != 64) {
5362 DRM_ERROR("we currently only support 64x64 cursors\n");
5363 return -EINVAL;
5364 }
5365
5366 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5367 if (&obj->base == NULL)
5368 return -ENOENT;
5369
5370 if (obj->base.size < width * height * 4) {
5371 DRM_ERROR("buffer is to small\n");
5372 ret = -ENOMEM;
5373 goto fail;
5374 }
5375
5376 /* we only need to pin inside GTT if cursor is non-phy */
5377 mutex_lock(&dev->struct_mutex);
5378 if (!dev_priv->info->cursor_needs_physical) {
5379 if (obj->tiling_mode) {
5380 DRM_ERROR("cursor cannot be tiled\n");
5381 ret = -EINVAL;
5382 goto fail_locked;
5383 }
5384
5385 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5386 if (ret) {
5387 DRM_ERROR("failed to move cursor bo into the GTT\n");
5388 goto fail_locked;
5389 }
5390
5391 ret = i915_gem_object_put_fence(obj);
5392 if (ret) {
5393 DRM_ERROR("failed to release fence for cursor");
5394 goto fail_unpin;
5395 }
5396
5397 addr = obj->gtt_offset;
5398 } else {
5399 int align = IS_I830(dev) ? 16 * 1024 : 256;
5400 ret = i915_gem_attach_phys_object(dev, obj,
5401 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5402 align);
5403 if (ret) {
5404 DRM_ERROR("failed to attach phys object\n");
5405 goto fail_locked;
5406 }
5407 addr = obj->phys_obj->handle->busaddr;
5408 }
5409
5410 if (IS_GEN2(dev))
5411 I915_WRITE(CURSIZE, (height << 12) | width);
5412
5413 finish:
5414 if (intel_crtc->cursor_bo) {
5415 if (dev_priv->info->cursor_needs_physical) {
5416 if (intel_crtc->cursor_bo != obj)
5417 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5418 } else
5419 i915_gem_object_unpin(intel_crtc->cursor_bo);
5420 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5421 }
5422
5423 mutex_unlock(&dev->struct_mutex);
5424
5425 intel_crtc->cursor_addr = addr;
5426 intel_crtc->cursor_bo = obj;
5427 intel_crtc->cursor_width = width;
5428 intel_crtc->cursor_height = height;
5429
5430 intel_crtc_update_cursor(crtc, true);
5431
5432 return 0;
5433 fail_unpin:
5434 i915_gem_object_unpin(obj);
5435 fail_locked:
5436 mutex_unlock(&dev->struct_mutex);
5437 fail:
5438 drm_gem_object_unreference_unlocked(&obj->base);
5439 return ret;
5440 }
5441
5442 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5443 {
5444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5445
5446 intel_crtc->cursor_x = x;
5447 intel_crtc->cursor_y = y;
5448
5449 intel_crtc_update_cursor(crtc, true);
5450
5451 return 0;
5452 }
5453
5454 /** Sets the color ramps on behalf of RandR */
5455 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5456 u16 blue, int regno)
5457 {
5458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5459
5460 intel_crtc->lut_r[regno] = red >> 8;
5461 intel_crtc->lut_g[regno] = green >> 8;
5462 intel_crtc->lut_b[regno] = blue >> 8;
5463 }
5464
5465 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5466 u16 *blue, int regno)
5467 {
5468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5469
5470 *red = intel_crtc->lut_r[regno] << 8;
5471 *green = intel_crtc->lut_g[regno] << 8;
5472 *blue = intel_crtc->lut_b[regno] << 8;
5473 }
5474
5475 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5476 u16 *blue, uint32_t start, uint32_t size)
5477 {
5478 int end = (start + size > 256) ? 256 : start + size, i;
5479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5480
5481 for (i = start; i < end; i++) {
5482 intel_crtc->lut_r[i] = red[i] >> 8;
5483 intel_crtc->lut_g[i] = green[i] >> 8;
5484 intel_crtc->lut_b[i] = blue[i] >> 8;
5485 }
5486
5487 intel_crtc_load_lut(crtc);
5488 }
5489
5490 /**
5491 * Get a pipe with a simple mode set on it for doing load-based monitor
5492 * detection.
5493 *
5494 * It will be up to the load-detect code to adjust the pipe as appropriate for
5495 * its requirements. The pipe will be connected to no other encoders.
5496 *
5497 * Currently this code will only succeed if there is a pipe with no encoders
5498 * configured for it. In the future, it could choose to temporarily disable
5499 * some outputs to free up a pipe for its use.
5500 *
5501 * \return crtc, or NULL if no pipes are available.
5502 */
5503
5504 /* VESA 640x480x72Hz mode to set on the pipe */
5505 static struct drm_display_mode load_detect_mode = {
5506 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5507 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5508 };
5509
5510 static struct drm_framebuffer *
5511 intel_framebuffer_create(struct drm_device *dev,
5512 struct drm_mode_fb_cmd2 *mode_cmd,
5513 struct drm_i915_gem_object *obj)
5514 {
5515 struct intel_framebuffer *intel_fb;
5516 int ret;
5517
5518 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5519 if (!intel_fb) {
5520 drm_gem_object_unreference_unlocked(&obj->base);
5521 return ERR_PTR(-ENOMEM);
5522 }
5523
5524 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5525 if (ret) {
5526 drm_gem_object_unreference_unlocked(&obj->base);
5527 kfree(intel_fb);
5528 return ERR_PTR(ret);
5529 }
5530
5531 return &intel_fb->base;
5532 }
5533
5534 static u32
5535 intel_framebuffer_pitch_for_width(int width, int bpp)
5536 {
5537 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5538 return ALIGN(pitch, 64);
5539 }
5540
5541 static u32
5542 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5543 {
5544 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5545 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5546 }
5547
5548 static struct drm_framebuffer *
5549 intel_framebuffer_create_for_mode(struct drm_device *dev,
5550 struct drm_display_mode *mode,
5551 int depth, int bpp)
5552 {
5553 struct drm_i915_gem_object *obj;
5554 struct drm_mode_fb_cmd2 mode_cmd;
5555
5556 obj = i915_gem_alloc_object(dev,
5557 intel_framebuffer_size_for_mode(mode, bpp));
5558 if (obj == NULL)
5559 return ERR_PTR(-ENOMEM);
5560
5561 mode_cmd.width = mode->hdisplay;
5562 mode_cmd.height = mode->vdisplay;
5563 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5564 bpp);
5565 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5566
5567 return intel_framebuffer_create(dev, &mode_cmd, obj);
5568 }
5569
5570 static struct drm_framebuffer *
5571 mode_fits_in_fbdev(struct drm_device *dev,
5572 struct drm_display_mode *mode)
5573 {
5574 struct drm_i915_private *dev_priv = dev->dev_private;
5575 struct drm_i915_gem_object *obj;
5576 struct drm_framebuffer *fb;
5577
5578 if (dev_priv->fbdev == NULL)
5579 return NULL;
5580
5581 obj = dev_priv->fbdev->ifb.obj;
5582 if (obj == NULL)
5583 return NULL;
5584
5585 fb = &dev_priv->fbdev->ifb.base;
5586 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5587 fb->bits_per_pixel))
5588 return NULL;
5589
5590 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5591 return NULL;
5592
5593 return fb;
5594 }
5595
5596 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5597 struct drm_display_mode *mode,
5598 struct intel_load_detect_pipe *old)
5599 {
5600 struct intel_crtc *intel_crtc;
5601 struct intel_encoder *intel_encoder =
5602 intel_attached_encoder(connector);
5603 struct drm_crtc *possible_crtc;
5604 struct drm_encoder *encoder = &intel_encoder->base;
5605 struct drm_crtc *crtc = NULL;
5606 struct drm_device *dev = encoder->dev;
5607 struct drm_framebuffer *old_fb;
5608 int i = -1;
5609
5610 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5611 connector->base.id, drm_get_connector_name(connector),
5612 encoder->base.id, drm_get_encoder_name(encoder));
5613
5614 /*
5615 * Algorithm gets a little messy:
5616 *
5617 * - if the connector already has an assigned crtc, use it (but make
5618 * sure it's on first)
5619 *
5620 * - try to find the first unused crtc that can drive this connector,
5621 * and use that if we find one
5622 */
5623
5624 /* See if we already have a CRTC for this connector */
5625 if (encoder->crtc) {
5626 crtc = encoder->crtc;
5627
5628 old->dpms_mode = connector->dpms;
5629 old->load_detect_temp = false;
5630
5631 /* Make sure the crtc and connector are running */
5632 if (connector->dpms != DRM_MODE_DPMS_ON)
5633 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5634
5635 return true;
5636 }
5637
5638 /* Find an unused one (if possible) */
5639 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5640 i++;
5641 if (!(encoder->possible_crtcs & (1 << i)))
5642 continue;
5643 if (!possible_crtc->enabled) {
5644 crtc = possible_crtc;
5645 break;
5646 }
5647 }
5648
5649 /*
5650 * If we didn't find an unused CRTC, don't use any.
5651 */
5652 if (!crtc) {
5653 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5654 return false;
5655 }
5656
5657 encoder->crtc = crtc;
5658 connector->encoder = encoder;
5659
5660 intel_crtc = to_intel_crtc(crtc);
5661 old->dpms_mode = connector->dpms;
5662 old->load_detect_temp = true;
5663 old->release_fb = NULL;
5664
5665 if (!mode)
5666 mode = &load_detect_mode;
5667
5668 old_fb = crtc->fb;
5669
5670 /* We need a framebuffer large enough to accommodate all accesses
5671 * that the plane may generate whilst we perform load detection.
5672 * We can not rely on the fbcon either being present (we get called
5673 * during its initialisation to detect all boot displays, or it may
5674 * not even exist) or that it is large enough to satisfy the
5675 * requested mode.
5676 */
5677 crtc->fb = mode_fits_in_fbdev(dev, mode);
5678 if (crtc->fb == NULL) {
5679 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5680 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5681 old->release_fb = crtc->fb;
5682 } else
5683 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5684 if (IS_ERR(crtc->fb)) {
5685 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5686 goto fail;
5687 }
5688
5689 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5690 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5691 if (old->release_fb)
5692 old->release_fb->funcs->destroy(old->release_fb);
5693 goto fail;
5694 }
5695
5696 /* let the connector get through one full cycle before testing */
5697 intel_wait_for_vblank(dev, intel_crtc->pipe);
5698
5699 return true;
5700 fail:
5701 connector->encoder = NULL;
5702 encoder->crtc = NULL;
5703 crtc->fb = old_fb;
5704 return false;
5705 }
5706
5707 void intel_release_load_detect_pipe(struct drm_connector *connector,
5708 struct intel_load_detect_pipe *old)
5709 {
5710 struct intel_encoder *intel_encoder =
5711 intel_attached_encoder(connector);
5712 struct drm_encoder *encoder = &intel_encoder->base;
5713 struct drm_device *dev = encoder->dev;
5714
5715 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5716 connector->base.id, drm_get_connector_name(connector),
5717 encoder->base.id, drm_get_encoder_name(encoder));
5718
5719 if (old->load_detect_temp) {
5720 connector->encoder = NULL;
5721 encoder->crtc = NULL;
5722 drm_helper_disable_unused_functions(dev);
5723
5724 if (old->release_fb)
5725 old->release_fb->funcs->destroy(old->release_fb);
5726
5727 return;
5728 }
5729
5730 /* Switch crtc and encoder back off if necessary */
5731 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5732 connector->funcs->dpms(connector, old->dpms_mode);
5733 }
5734
5735 /* Returns the clock of the currently programmed mode of the given pipe. */
5736 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5737 {
5738 struct drm_i915_private *dev_priv = dev->dev_private;
5739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5740 int pipe = intel_crtc->pipe;
5741 u32 dpll = I915_READ(DPLL(pipe));
5742 u32 fp;
5743 intel_clock_t clock;
5744
5745 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5746 fp = I915_READ(FP0(pipe));
5747 else
5748 fp = I915_READ(FP1(pipe));
5749
5750 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5751 if (IS_PINEVIEW(dev)) {
5752 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5753 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5754 } else {
5755 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5756 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5757 }
5758
5759 if (!IS_GEN2(dev)) {
5760 if (IS_PINEVIEW(dev))
5761 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5762 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5763 else
5764 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5765 DPLL_FPA01_P1_POST_DIV_SHIFT);
5766
5767 switch (dpll & DPLL_MODE_MASK) {
5768 case DPLLB_MODE_DAC_SERIAL:
5769 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5770 5 : 10;
5771 break;
5772 case DPLLB_MODE_LVDS:
5773 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5774 7 : 14;
5775 break;
5776 default:
5777 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5778 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5779 return 0;
5780 }
5781
5782 /* XXX: Handle the 100Mhz refclk */
5783 intel_clock(dev, 96000, &clock);
5784 } else {
5785 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5786
5787 if (is_lvds) {
5788 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5789 DPLL_FPA01_P1_POST_DIV_SHIFT);
5790 clock.p2 = 14;
5791
5792 if ((dpll & PLL_REF_INPUT_MASK) ==
5793 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5794 /* XXX: might not be 66MHz */
5795 intel_clock(dev, 66000, &clock);
5796 } else
5797 intel_clock(dev, 48000, &clock);
5798 } else {
5799 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5800 clock.p1 = 2;
5801 else {
5802 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5803 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5804 }
5805 if (dpll & PLL_P2_DIVIDE_BY_4)
5806 clock.p2 = 4;
5807 else
5808 clock.p2 = 2;
5809
5810 intel_clock(dev, 48000, &clock);
5811 }
5812 }
5813
5814 /* XXX: It would be nice to validate the clocks, but we can't reuse
5815 * i830PllIsValid() because it relies on the xf86_config connector
5816 * configuration being accurate, which it isn't necessarily.
5817 */
5818
5819 return clock.dot;
5820 }
5821
5822 /** Returns the currently programmed mode of the given pipe. */
5823 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5824 struct drm_crtc *crtc)
5825 {
5826 struct drm_i915_private *dev_priv = dev->dev_private;
5827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5828 int pipe = intel_crtc->pipe;
5829 struct drm_display_mode *mode;
5830 int htot = I915_READ(HTOTAL(pipe));
5831 int hsync = I915_READ(HSYNC(pipe));
5832 int vtot = I915_READ(VTOTAL(pipe));
5833 int vsync = I915_READ(VSYNC(pipe));
5834
5835 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5836 if (!mode)
5837 return NULL;
5838
5839 mode->clock = intel_crtc_clock_get(dev, crtc);
5840 mode->hdisplay = (htot & 0xffff) + 1;
5841 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5842 mode->hsync_start = (hsync & 0xffff) + 1;
5843 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5844 mode->vdisplay = (vtot & 0xffff) + 1;
5845 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5846 mode->vsync_start = (vsync & 0xffff) + 1;
5847 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5848
5849 drm_mode_set_name(mode);
5850
5851 return mode;
5852 }
5853
5854 static void intel_increase_pllclock(struct drm_crtc *crtc)
5855 {
5856 struct drm_device *dev = crtc->dev;
5857 drm_i915_private_t *dev_priv = dev->dev_private;
5858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5859 int pipe = intel_crtc->pipe;
5860 int dpll_reg = DPLL(pipe);
5861 int dpll;
5862
5863 if (HAS_PCH_SPLIT(dev))
5864 return;
5865
5866 if (!dev_priv->lvds_downclock_avail)
5867 return;
5868
5869 dpll = I915_READ(dpll_reg);
5870 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5871 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5872
5873 assert_panel_unlocked(dev_priv, pipe);
5874
5875 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5876 I915_WRITE(dpll_reg, dpll);
5877 intel_wait_for_vblank(dev, pipe);
5878
5879 dpll = I915_READ(dpll_reg);
5880 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5881 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5882 }
5883 }
5884
5885 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5886 {
5887 struct drm_device *dev = crtc->dev;
5888 drm_i915_private_t *dev_priv = dev->dev_private;
5889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5890
5891 if (HAS_PCH_SPLIT(dev))
5892 return;
5893
5894 if (!dev_priv->lvds_downclock_avail)
5895 return;
5896
5897 /*
5898 * Since this is called by a timer, we should never get here in
5899 * the manual case.
5900 */
5901 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5902 int pipe = intel_crtc->pipe;
5903 int dpll_reg = DPLL(pipe);
5904 int dpll;
5905
5906 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5907
5908 assert_panel_unlocked(dev_priv, pipe);
5909
5910 dpll = I915_READ(dpll_reg);
5911 dpll |= DISPLAY_RATE_SELECT_FPA1;
5912 I915_WRITE(dpll_reg, dpll);
5913 intel_wait_for_vblank(dev, pipe);
5914 dpll = I915_READ(dpll_reg);
5915 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5916 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5917 }
5918
5919 }
5920
5921 void intel_mark_busy(struct drm_device *dev)
5922 {
5923 i915_update_gfx_val(dev->dev_private);
5924 }
5925
5926 void intel_mark_idle(struct drm_device *dev)
5927 {
5928 }
5929
5930 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
5931 {
5932 struct drm_device *dev = obj->base.dev;
5933 struct drm_crtc *crtc;
5934
5935 if (!i915_powersave)
5936 return;
5937
5938 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5939 if (!crtc->fb)
5940 continue;
5941
5942 if (to_intel_framebuffer(crtc->fb)->obj == obj)
5943 intel_increase_pllclock(crtc);
5944 }
5945 }
5946
5947 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
5948 {
5949 struct drm_device *dev = obj->base.dev;
5950 struct drm_crtc *crtc;
5951
5952 if (!i915_powersave)
5953 return;
5954
5955 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5956 if (!crtc->fb)
5957 continue;
5958
5959 if (to_intel_framebuffer(crtc->fb)->obj == obj)
5960 intel_decrease_pllclock(crtc);
5961 }
5962 }
5963
5964 static void intel_crtc_destroy(struct drm_crtc *crtc)
5965 {
5966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5967 struct drm_device *dev = crtc->dev;
5968 struct intel_unpin_work *work;
5969 unsigned long flags;
5970
5971 spin_lock_irqsave(&dev->event_lock, flags);
5972 work = intel_crtc->unpin_work;
5973 intel_crtc->unpin_work = NULL;
5974 spin_unlock_irqrestore(&dev->event_lock, flags);
5975
5976 if (work) {
5977 cancel_work_sync(&work->work);
5978 kfree(work);
5979 }
5980
5981 drm_crtc_cleanup(crtc);
5982
5983 kfree(intel_crtc);
5984 }
5985
5986 static void intel_unpin_work_fn(struct work_struct *__work)
5987 {
5988 struct intel_unpin_work *work =
5989 container_of(__work, struct intel_unpin_work, work);
5990
5991 mutex_lock(&work->dev->struct_mutex);
5992 intel_unpin_fb_obj(work->old_fb_obj);
5993 drm_gem_object_unreference(&work->pending_flip_obj->base);
5994 drm_gem_object_unreference(&work->old_fb_obj->base);
5995
5996 intel_update_fbc(work->dev);
5997 mutex_unlock(&work->dev->struct_mutex);
5998 kfree(work);
5999 }
6000
6001 static void do_intel_finish_page_flip(struct drm_device *dev,
6002 struct drm_crtc *crtc)
6003 {
6004 drm_i915_private_t *dev_priv = dev->dev_private;
6005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6006 struct intel_unpin_work *work;
6007 struct drm_i915_gem_object *obj;
6008 struct drm_pending_vblank_event *e;
6009 struct timeval tnow, tvbl;
6010 unsigned long flags;
6011
6012 /* Ignore early vblank irqs */
6013 if (intel_crtc == NULL)
6014 return;
6015
6016 do_gettimeofday(&tnow);
6017
6018 spin_lock_irqsave(&dev->event_lock, flags);
6019 work = intel_crtc->unpin_work;
6020 if (work == NULL || !work->pending) {
6021 spin_unlock_irqrestore(&dev->event_lock, flags);
6022 return;
6023 }
6024
6025 intel_crtc->unpin_work = NULL;
6026
6027 if (work->event) {
6028 e = work->event;
6029 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6030
6031 /* Called before vblank count and timestamps have
6032 * been updated for the vblank interval of flip
6033 * completion? Need to increment vblank count and
6034 * add one videorefresh duration to returned timestamp
6035 * to account for this. We assume this happened if we
6036 * get called over 0.9 frame durations after the last
6037 * timestamped vblank.
6038 *
6039 * This calculation can not be used with vrefresh rates
6040 * below 5Hz (10Hz to be on the safe side) without
6041 * promoting to 64 integers.
6042 */
6043 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6044 9 * crtc->framedur_ns) {
6045 e->event.sequence++;
6046 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6047 crtc->framedur_ns);
6048 }
6049
6050 e->event.tv_sec = tvbl.tv_sec;
6051 e->event.tv_usec = tvbl.tv_usec;
6052
6053 list_add_tail(&e->base.link,
6054 &e->base.file_priv->event_list);
6055 wake_up_interruptible(&e->base.file_priv->event_wait);
6056 }
6057
6058 drm_vblank_put(dev, intel_crtc->pipe);
6059
6060 spin_unlock_irqrestore(&dev->event_lock, flags);
6061
6062 obj = work->old_fb_obj;
6063
6064 atomic_clear_mask(1 << intel_crtc->plane,
6065 &obj->pending_flip.counter);
6066 if (atomic_read(&obj->pending_flip) == 0)
6067 wake_up(&dev_priv->pending_flip_queue);
6068
6069 schedule_work(&work->work);
6070
6071 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6072 }
6073
6074 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6075 {
6076 drm_i915_private_t *dev_priv = dev->dev_private;
6077 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6078
6079 do_intel_finish_page_flip(dev, crtc);
6080 }
6081
6082 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6083 {
6084 drm_i915_private_t *dev_priv = dev->dev_private;
6085 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6086
6087 do_intel_finish_page_flip(dev, crtc);
6088 }
6089
6090 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6091 {
6092 drm_i915_private_t *dev_priv = dev->dev_private;
6093 struct intel_crtc *intel_crtc =
6094 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6095 unsigned long flags;
6096
6097 spin_lock_irqsave(&dev->event_lock, flags);
6098 if (intel_crtc->unpin_work) {
6099 if ((++intel_crtc->unpin_work->pending) > 1)
6100 DRM_ERROR("Prepared flip multiple times\n");
6101 } else {
6102 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6103 }
6104 spin_unlock_irqrestore(&dev->event_lock, flags);
6105 }
6106
6107 static int intel_gen2_queue_flip(struct drm_device *dev,
6108 struct drm_crtc *crtc,
6109 struct drm_framebuffer *fb,
6110 struct drm_i915_gem_object *obj)
6111 {
6112 struct drm_i915_private *dev_priv = dev->dev_private;
6113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6114 u32 flip_mask;
6115 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6116 int ret;
6117
6118 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6119 if (ret)
6120 goto err;
6121
6122 ret = intel_ring_begin(ring, 6);
6123 if (ret)
6124 goto err_unpin;
6125
6126 /* Can't queue multiple flips, so wait for the previous
6127 * one to finish before executing the next.
6128 */
6129 if (intel_crtc->plane)
6130 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6131 else
6132 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6133 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6134 intel_ring_emit(ring, MI_NOOP);
6135 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6136 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6137 intel_ring_emit(ring, fb->pitches[0]);
6138 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6139 intel_ring_emit(ring, 0); /* aux display base address, unused */
6140 intel_ring_advance(ring);
6141 return 0;
6142
6143 err_unpin:
6144 intel_unpin_fb_obj(obj);
6145 err:
6146 return ret;
6147 }
6148
6149 static int intel_gen3_queue_flip(struct drm_device *dev,
6150 struct drm_crtc *crtc,
6151 struct drm_framebuffer *fb,
6152 struct drm_i915_gem_object *obj)
6153 {
6154 struct drm_i915_private *dev_priv = dev->dev_private;
6155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6156 u32 flip_mask;
6157 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6158 int ret;
6159
6160 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6161 if (ret)
6162 goto err;
6163
6164 ret = intel_ring_begin(ring, 6);
6165 if (ret)
6166 goto err_unpin;
6167
6168 if (intel_crtc->plane)
6169 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6170 else
6171 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6172 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6173 intel_ring_emit(ring, MI_NOOP);
6174 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6175 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6176 intel_ring_emit(ring, fb->pitches[0]);
6177 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6178 intel_ring_emit(ring, MI_NOOP);
6179
6180 intel_ring_advance(ring);
6181 return 0;
6182
6183 err_unpin:
6184 intel_unpin_fb_obj(obj);
6185 err:
6186 return ret;
6187 }
6188
6189 static int intel_gen4_queue_flip(struct drm_device *dev,
6190 struct drm_crtc *crtc,
6191 struct drm_framebuffer *fb,
6192 struct drm_i915_gem_object *obj)
6193 {
6194 struct drm_i915_private *dev_priv = dev->dev_private;
6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196 uint32_t pf, pipesrc;
6197 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6198 int ret;
6199
6200 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6201 if (ret)
6202 goto err;
6203
6204 ret = intel_ring_begin(ring, 4);
6205 if (ret)
6206 goto err_unpin;
6207
6208 /* i965+ uses the linear or tiled offsets from the
6209 * Display Registers (which do not change across a page-flip)
6210 * so we need only reprogram the base address.
6211 */
6212 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6213 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6214 intel_ring_emit(ring, fb->pitches[0]);
6215 intel_ring_emit(ring,
6216 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6217 obj->tiling_mode);
6218
6219 /* XXX Enabling the panel-fitter across page-flip is so far
6220 * untested on non-native modes, so ignore it for now.
6221 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6222 */
6223 pf = 0;
6224 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6225 intel_ring_emit(ring, pf | pipesrc);
6226 intel_ring_advance(ring);
6227 return 0;
6228
6229 err_unpin:
6230 intel_unpin_fb_obj(obj);
6231 err:
6232 return ret;
6233 }
6234
6235 static int intel_gen6_queue_flip(struct drm_device *dev,
6236 struct drm_crtc *crtc,
6237 struct drm_framebuffer *fb,
6238 struct drm_i915_gem_object *obj)
6239 {
6240 struct drm_i915_private *dev_priv = dev->dev_private;
6241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6242 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6243 uint32_t pf, pipesrc;
6244 int ret;
6245
6246 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6247 if (ret)
6248 goto err;
6249
6250 ret = intel_ring_begin(ring, 4);
6251 if (ret)
6252 goto err_unpin;
6253
6254 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6255 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6256 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6257 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6258
6259 /* Contrary to the suggestions in the documentation,
6260 * "Enable Panel Fitter" does not seem to be required when page
6261 * flipping with a non-native mode, and worse causes a normal
6262 * modeset to fail.
6263 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6264 */
6265 pf = 0;
6266 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6267 intel_ring_emit(ring, pf | pipesrc);
6268 intel_ring_advance(ring);
6269 return 0;
6270
6271 err_unpin:
6272 intel_unpin_fb_obj(obj);
6273 err:
6274 return ret;
6275 }
6276
6277 /*
6278 * On gen7 we currently use the blit ring because (in early silicon at least)
6279 * the render ring doesn't give us interrpts for page flip completion, which
6280 * means clients will hang after the first flip is queued. Fortunately the
6281 * blit ring generates interrupts properly, so use it instead.
6282 */
6283 static int intel_gen7_queue_flip(struct drm_device *dev,
6284 struct drm_crtc *crtc,
6285 struct drm_framebuffer *fb,
6286 struct drm_i915_gem_object *obj)
6287 {
6288 struct drm_i915_private *dev_priv = dev->dev_private;
6289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6290 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6291 uint32_t plane_bit = 0;
6292 int ret;
6293
6294 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6295 if (ret)
6296 goto err;
6297
6298 switch(intel_crtc->plane) {
6299 case PLANE_A:
6300 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6301 break;
6302 case PLANE_B:
6303 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6304 break;
6305 case PLANE_C:
6306 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6307 break;
6308 default:
6309 WARN_ONCE(1, "unknown plane in flip command\n");
6310 ret = -ENODEV;
6311 goto err_unpin;
6312 }
6313
6314 ret = intel_ring_begin(ring, 4);
6315 if (ret)
6316 goto err_unpin;
6317
6318 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6319 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6320 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6321 intel_ring_emit(ring, (MI_NOOP));
6322 intel_ring_advance(ring);
6323 return 0;
6324
6325 err_unpin:
6326 intel_unpin_fb_obj(obj);
6327 err:
6328 return ret;
6329 }
6330
6331 static int intel_default_queue_flip(struct drm_device *dev,
6332 struct drm_crtc *crtc,
6333 struct drm_framebuffer *fb,
6334 struct drm_i915_gem_object *obj)
6335 {
6336 return -ENODEV;
6337 }
6338
6339 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6340 struct drm_framebuffer *fb,
6341 struct drm_pending_vblank_event *event)
6342 {
6343 struct drm_device *dev = crtc->dev;
6344 struct drm_i915_private *dev_priv = dev->dev_private;
6345 struct intel_framebuffer *intel_fb;
6346 struct drm_i915_gem_object *obj;
6347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6348 struct intel_unpin_work *work;
6349 unsigned long flags;
6350 int ret;
6351
6352 /* Can't change pixel format via MI display flips. */
6353 if (fb->pixel_format != crtc->fb->pixel_format)
6354 return -EINVAL;
6355
6356 /*
6357 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6358 * Note that pitch changes could also affect these register.
6359 */
6360 if (INTEL_INFO(dev)->gen > 3 &&
6361 (fb->offsets[0] != crtc->fb->offsets[0] ||
6362 fb->pitches[0] != crtc->fb->pitches[0]))
6363 return -EINVAL;
6364
6365 work = kzalloc(sizeof *work, GFP_KERNEL);
6366 if (work == NULL)
6367 return -ENOMEM;
6368
6369 work->event = event;
6370 work->dev = crtc->dev;
6371 intel_fb = to_intel_framebuffer(crtc->fb);
6372 work->old_fb_obj = intel_fb->obj;
6373 INIT_WORK(&work->work, intel_unpin_work_fn);
6374
6375 ret = drm_vblank_get(dev, intel_crtc->pipe);
6376 if (ret)
6377 goto free_work;
6378
6379 /* We borrow the event spin lock for protecting unpin_work */
6380 spin_lock_irqsave(&dev->event_lock, flags);
6381 if (intel_crtc->unpin_work) {
6382 spin_unlock_irqrestore(&dev->event_lock, flags);
6383 kfree(work);
6384 drm_vblank_put(dev, intel_crtc->pipe);
6385
6386 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6387 return -EBUSY;
6388 }
6389 intel_crtc->unpin_work = work;
6390 spin_unlock_irqrestore(&dev->event_lock, flags);
6391
6392 intel_fb = to_intel_framebuffer(fb);
6393 obj = intel_fb->obj;
6394
6395 ret = i915_mutex_lock_interruptible(dev);
6396 if (ret)
6397 goto cleanup;
6398
6399 /* Reference the objects for the scheduled work. */
6400 drm_gem_object_reference(&work->old_fb_obj->base);
6401 drm_gem_object_reference(&obj->base);
6402
6403 crtc->fb = fb;
6404
6405 work->pending_flip_obj = obj;
6406
6407 work->enable_stall_check = true;
6408
6409 /* Block clients from rendering to the new back buffer until
6410 * the flip occurs and the object is no longer visible.
6411 */
6412 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6413
6414 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6415 if (ret)
6416 goto cleanup_pending;
6417
6418 intel_disable_fbc(dev);
6419 intel_mark_fb_busy(obj);
6420 mutex_unlock(&dev->struct_mutex);
6421
6422 trace_i915_flip_request(intel_crtc->plane, obj);
6423
6424 return 0;
6425
6426 cleanup_pending:
6427 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6428 drm_gem_object_unreference(&work->old_fb_obj->base);
6429 drm_gem_object_unreference(&obj->base);
6430 mutex_unlock(&dev->struct_mutex);
6431
6432 cleanup:
6433 spin_lock_irqsave(&dev->event_lock, flags);
6434 intel_crtc->unpin_work = NULL;
6435 spin_unlock_irqrestore(&dev->event_lock, flags);
6436
6437 drm_vblank_put(dev, intel_crtc->pipe);
6438 free_work:
6439 kfree(work);
6440
6441 return ret;
6442 }
6443
6444 static void intel_sanitize_modesetting(struct drm_device *dev,
6445 int pipe, int plane)
6446 {
6447 struct drm_i915_private *dev_priv = dev->dev_private;
6448 u32 reg, val;
6449 int i;
6450
6451 /* Clear any frame start delays used for debugging left by the BIOS */
6452 for_each_pipe(i) {
6453 reg = PIPECONF(i);
6454 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6455 }
6456
6457 if (HAS_PCH_SPLIT(dev))
6458 return;
6459
6460 /* Who knows what state these registers were left in by the BIOS or
6461 * grub?
6462 *
6463 * If we leave the registers in a conflicting state (e.g. with the
6464 * display plane reading from the other pipe than the one we intend
6465 * to use) then when we attempt to teardown the active mode, we will
6466 * not disable the pipes and planes in the correct order -- leaving
6467 * a plane reading from a disabled pipe and possibly leading to
6468 * undefined behaviour.
6469 */
6470
6471 reg = DSPCNTR(plane);
6472 val = I915_READ(reg);
6473
6474 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6475 return;
6476 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6477 return;
6478
6479 /* This display plane is active and attached to the other CPU pipe. */
6480 pipe = !pipe;
6481
6482 /* Disable the plane and wait for it to stop reading from the pipe. */
6483 intel_disable_plane(dev_priv, plane, pipe);
6484 intel_disable_pipe(dev_priv, pipe);
6485 }
6486
6487 static void intel_crtc_reset(struct drm_crtc *crtc)
6488 {
6489 struct drm_device *dev = crtc->dev;
6490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6491
6492 /* Reset flags back to the 'unknown' status so that they
6493 * will be correctly set on the initial modeset.
6494 */
6495 intel_crtc->dpms_mode = -1;
6496
6497 /* We need to fix up any BIOS configuration that conflicts with
6498 * our expectations.
6499 */
6500 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6501 }
6502
6503 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6504 .dpms = intel_crtc_dpms,
6505 .mode_fixup = intel_crtc_mode_fixup,
6506 .mode_set = intel_crtc_mode_set,
6507 .mode_set_base = intel_pipe_set_base,
6508 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6509 .load_lut = intel_crtc_load_lut,
6510 .disable = intel_crtc_disable,
6511 };
6512
6513 static const struct drm_crtc_funcs intel_crtc_funcs = {
6514 .reset = intel_crtc_reset,
6515 .cursor_set = intel_crtc_cursor_set,
6516 .cursor_move = intel_crtc_cursor_move,
6517 .gamma_set = intel_crtc_gamma_set,
6518 .set_config = drm_crtc_helper_set_config,
6519 .destroy = intel_crtc_destroy,
6520 .page_flip = intel_crtc_page_flip,
6521 };
6522
6523 static void intel_pch_pll_init(struct drm_device *dev)
6524 {
6525 drm_i915_private_t *dev_priv = dev->dev_private;
6526 int i;
6527
6528 if (dev_priv->num_pch_pll == 0) {
6529 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6530 return;
6531 }
6532
6533 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6534 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6535 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6536 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6537 }
6538 }
6539
6540 static void intel_crtc_init(struct drm_device *dev, int pipe)
6541 {
6542 drm_i915_private_t *dev_priv = dev->dev_private;
6543 struct intel_crtc *intel_crtc;
6544 int i;
6545
6546 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6547 if (intel_crtc == NULL)
6548 return;
6549
6550 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6551
6552 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6553 for (i = 0; i < 256; i++) {
6554 intel_crtc->lut_r[i] = i;
6555 intel_crtc->lut_g[i] = i;
6556 intel_crtc->lut_b[i] = i;
6557 }
6558
6559 /* Swap pipes & planes for FBC on pre-965 */
6560 intel_crtc->pipe = pipe;
6561 intel_crtc->plane = pipe;
6562 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6563 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6564 intel_crtc->plane = !pipe;
6565 }
6566
6567 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6568 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6569 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6570 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6571
6572 intel_crtc_reset(&intel_crtc->base);
6573 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6574 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6575
6576 if (HAS_PCH_SPLIT(dev)) {
6577 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6578 intel_helper_funcs.commit = ironlake_crtc_commit;
6579 } else {
6580 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6581 intel_helper_funcs.commit = i9xx_crtc_commit;
6582 }
6583
6584 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6585 }
6586
6587 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6588 struct drm_file *file)
6589 {
6590 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6591 struct drm_mode_object *drmmode_obj;
6592 struct intel_crtc *crtc;
6593
6594 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6595 return -ENODEV;
6596
6597 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6598 DRM_MODE_OBJECT_CRTC);
6599
6600 if (!drmmode_obj) {
6601 DRM_ERROR("no such CRTC id\n");
6602 return -EINVAL;
6603 }
6604
6605 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6606 pipe_from_crtc_id->pipe = crtc->pipe;
6607
6608 return 0;
6609 }
6610
6611 static int intel_encoder_clones(struct intel_encoder *encoder)
6612 {
6613 struct drm_device *dev = encoder->base.dev;
6614 struct intel_encoder *source_encoder;
6615 int index_mask = 0;
6616 int entry = 0;
6617
6618 list_for_each_entry(source_encoder,
6619 &dev->mode_config.encoder_list, base.head) {
6620
6621 if (encoder == source_encoder)
6622 index_mask |= (1 << entry);
6623
6624 /* Intel hw has only one MUX where enocoders could be cloned. */
6625 if (encoder->cloneable && source_encoder->cloneable)
6626 index_mask |= (1 << entry);
6627
6628 entry++;
6629 }
6630
6631 return index_mask;
6632 }
6633
6634 static bool has_edp_a(struct drm_device *dev)
6635 {
6636 struct drm_i915_private *dev_priv = dev->dev_private;
6637
6638 if (!IS_MOBILE(dev))
6639 return false;
6640
6641 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6642 return false;
6643
6644 if (IS_GEN5(dev) &&
6645 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6646 return false;
6647
6648 return true;
6649 }
6650
6651 static void intel_setup_outputs(struct drm_device *dev)
6652 {
6653 struct drm_i915_private *dev_priv = dev->dev_private;
6654 struct intel_encoder *encoder;
6655 bool dpd_is_edp = false;
6656 bool has_lvds;
6657
6658 has_lvds = intel_lvds_init(dev);
6659 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6660 /* disable the panel fitter on everything but LVDS */
6661 I915_WRITE(PFIT_CONTROL, 0);
6662 }
6663
6664 if (HAS_PCH_SPLIT(dev)) {
6665 dpd_is_edp = intel_dpd_is_edp(dev);
6666
6667 if (has_edp_a(dev))
6668 intel_dp_init(dev, DP_A, PORT_A);
6669
6670 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6671 intel_dp_init(dev, PCH_DP_D, PORT_D);
6672 }
6673
6674 intel_crt_init(dev);
6675
6676 if (IS_HASWELL(dev)) {
6677 int found;
6678
6679 /* Haswell uses DDI functions to detect digital outputs */
6680 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6681 /* DDI A only supports eDP */
6682 if (found)
6683 intel_ddi_init(dev, PORT_A);
6684
6685 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6686 * register */
6687 found = I915_READ(SFUSE_STRAP);
6688
6689 if (found & SFUSE_STRAP_DDIB_DETECTED)
6690 intel_ddi_init(dev, PORT_B);
6691 if (found & SFUSE_STRAP_DDIC_DETECTED)
6692 intel_ddi_init(dev, PORT_C);
6693 if (found & SFUSE_STRAP_DDID_DETECTED)
6694 intel_ddi_init(dev, PORT_D);
6695 } else if (HAS_PCH_SPLIT(dev)) {
6696 int found;
6697
6698 if (I915_READ(HDMIB) & PORT_DETECTED) {
6699 /* PCH SDVOB multiplex with HDMIB */
6700 found = intel_sdvo_init(dev, PCH_SDVOB, true);
6701 if (!found)
6702 intel_hdmi_init(dev, HDMIB, PORT_B);
6703 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6704 intel_dp_init(dev, PCH_DP_B, PORT_B);
6705 }
6706
6707 if (I915_READ(HDMIC) & PORT_DETECTED)
6708 intel_hdmi_init(dev, HDMIC, PORT_C);
6709
6710 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
6711 intel_hdmi_init(dev, HDMID, PORT_D);
6712
6713 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6714 intel_dp_init(dev, PCH_DP_C, PORT_C);
6715
6716 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6717 intel_dp_init(dev, PCH_DP_D, PORT_D);
6718 } else if (IS_VALLEYVIEW(dev)) {
6719 int found;
6720
6721 if (I915_READ(SDVOB) & PORT_DETECTED) {
6722 /* SDVOB multiplex with HDMIB */
6723 found = intel_sdvo_init(dev, SDVOB, true);
6724 if (!found)
6725 intel_hdmi_init(dev, SDVOB, PORT_B);
6726 if (!found && (I915_READ(DP_B) & DP_DETECTED))
6727 intel_dp_init(dev, DP_B, PORT_B);
6728 }
6729
6730 if (I915_READ(SDVOC) & PORT_DETECTED)
6731 intel_hdmi_init(dev, SDVOC, PORT_C);
6732
6733 /* Shares lanes with HDMI on SDVOC */
6734 if (I915_READ(DP_C) & DP_DETECTED)
6735 intel_dp_init(dev, DP_C, PORT_C);
6736 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6737 bool found = false;
6738
6739 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6740 DRM_DEBUG_KMS("probing SDVOB\n");
6741 found = intel_sdvo_init(dev, SDVOB, true);
6742 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6743 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6744 intel_hdmi_init(dev, SDVOB, PORT_B);
6745 }
6746
6747 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6748 DRM_DEBUG_KMS("probing DP_B\n");
6749 intel_dp_init(dev, DP_B, PORT_B);
6750 }
6751 }
6752
6753 /* Before G4X SDVOC doesn't have its own detect register */
6754
6755 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6756 DRM_DEBUG_KMS("probing SDVOC\n");
6757 found = intel_sdvo_init(dev, SDVOC, false);
6758 }
6759
6760 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6761
6762 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6763 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6764 intel_hdmi_init(dev, SDVOC, PORT_C);
6765 }
6766 if (SUPPORTS_INTEGRATED_DP(dev)) {
6767 DRM_DEBUG_KMS("probing DP_C\n");
6768 intel_dp_init(dev, DP_C, PORT_C);
6769 }
6770 }
6771
6772 if (SUPPORTS_INTEGRATED_DP(dev) &&
6773 (I915_READ(DP_D) & DP_DETECTED)) {
6774 DRM_DEBUG_KMS("probing DP_D\n");
6775 intel_dp_init(dev, DP_D, PORT_D);
6776 }
6777 } else if (IS_GEN2(dev))
6778 intel_dvo_init(dev);
6779
6780 if (SUPPORTS_TV(dev))
6781 intel_tv_init(dev);
6782
6783 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6784 encoder->base.possible_crtcs = encoder->crtc_mask;
6785 encoder->base.possible_clones =
6786 intel_encoder_clones(encoder);
6787 }
6788
6789 /* disable all the possible outputs/crtcs before entering KMS mode */
6790 drm_helper_disable_unused_functions(dev);
6791
6792 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6793 ironlake_init_pch_refclk(dev);
6794 }
6795
6796 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6797 {
6798 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6799
6800 drm_framebuffer_cleanup(fb);
6801 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6802
6803 kfree(intel_fb);
6804 }
6805
6806 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6807 struct drm_file *file,
6808 unsigned int *handle)
6809 {
6810 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6811 struct drm_i915_gem_object *obj = intel_fb->obj;
6812
6813 return drm_gem_handle_create(file, &obj->base, handle);
6814 }
6815
6816 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6817 .destroy = intel_user_framebuffer_destroy,
6818 .create_handle = intel_user_framebuffer_create_handle,
6819 };
6820
6821 int intel_framebuffer_init(struct drm_device *dev,
6822 struct intel_framebuffer *intel_fb,
6823 struct drm_mode_fb_cmd2 *mode_cmd,
6824 struct drm_i915_gem_object *obj)
6825 {
6826 int ret;
6827
6828 if (obj->tiling_mode == I915_TILING_Y)
6829 return -EINVAL;
6830
6831 if (mode_cmd->pitches[0] & 63)
6832 return -EINVAL;
6833
6834 switch (mode_cmd->pixel_format) {
6835 case DRM_FORMAT_RGB332:
6836 case DRM_FORMAT_RGB565:
6837 case DRM_FORMAT_XRGB8888:
6838 case DRM_FORMAT_XBGR8888:
6839 case DRM_FORMAT_ARGB8888:
6840 case DRM_FORMAT_XRGB2101010:
6841 case DRM_FORMAT_ARGB2101010:
6842 /* RGB formats are common across chipsets */
6843 break;
6844 case DRM_FORMAT_YUYV:
6845 case DRM_FORMAT_UYVY:
6846 case DRM_FORMAT_YVYU:
6847 case DRM_FORMAT_VYUY:
6848 break;
6849 default:
6850 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6851 mode_cmd->pixel_format);
6852 return -EINVAL;
6853 }
6854
6855 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6856 if (ret) {
6857 DRM_ERROR("framebuffer init failed %d\n", ret);
6858 return ret;
6859 }
6860
6861 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6862 intel_fb->obj = obj;
6863 return 0;
6864 }
6865
6866 static struct drm_framebuffer *
6867 intel_user_framebuffer_create(struct drm_device *dev,
6868 struct drm_file *filp,
6869 struct drm_mode_fb_cmd2 *mode_cmd)
6870 {
6871 struct drm_i915_gem_object *obj;
6872
6873 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6874 mode_cmd->handles[0]));
6875 if (&obj->base == NULL)
6876 return ERR_PTR(-ENOENT);
6877
6878 return intel_framebuffer_create(dev, mode_cmd, obj);
6879 }
6880
6881 static const struct drm_mode_config_funcs intel_mode_funcs = {
6882 .fb_create = intel_user_framebuffer_create,
6883 .output_poll_changed = intel_fb_output_poll_changed,
6884 };
6885
6886 /* Set up chip specific display functions */
6887 static void intel_init_display(struct drm_device *dev)
6888 {
6889 struct drm_i915_private *dev_priv = dev->dev_private;
6890
6891 /* We always want a DPMS function */
6892 if (HAS_PCH_SPLIT(dev)) {
6893 dev_priv->display.dpms = ironlake_crtc_dpms;
6894 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6895 dev_priv->display.off = ironlake_crtc_off;
6896 dev_priv->display.update_plane = ironlake_update_plane;
6897 } else {
6898 dev_priv->display.dpms = i9xx_crtc_dpms;
6899 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6900 dev_priv->display.off = i9xx_crtc_off;
6901 dev_priv->display.update_plane = i9xx_update_plane;
6902 }
6903
6904 /* Returns the core display clock speed */
6905 if (IS_VALLEYVIEW(dev))
6906 dev_priv->display.get_display_clock_speed =
6907 valleyview_get_display_clock_speed;
6908 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6909 dev_priv->display.get_display_clock_speed =
6910 i945_get_display_clock_speed;
6911 else if (IS_I915G(dev))
6912 dev_priv->display.get_display_clock_speed =
6913 i915_get_display_clock_speed;
6914 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6915 dev_priv->display.get_display_clock_speed =
6916 i9xx_misc_get_display_clock_speed;
6917 else if (IS_I915GM(dev))
6918 dev_priv->display.get_display_clock_speed =
6919 i915gm_get_display_clock_speed;
6920 else if (IS_I865G(dev))
6921 dev_priv->display.get_display_clock_speed =
6922 i865_get_display_clock_speed;
6923 else if (IS_I85X(dev))
6924 dev_priv->display.get_display_clock_speed =
6925 i855_get_display_clock_speed;
6926 else /* 852, 830 */
6927 dev_priv->display.get_display_clock_speed =
6928 i830_get_display_clock_speed;
6929
6930 if (HAS_PCH_SPLIT(dev)) {
6931 if (IS_GEN5(dev)) {
6932 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6933 dev_priv->display.write_eld = ironlake_write_eld;
6934 } else if (IS_GEN6(dev)) {
6935 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6936 dev_priv->display.write_eld = ironlake_write_eld;
6937 } else if (IS_IVYBRIDGE(dev)) {
6938 /* FIXME: detect B0+ stepping and use auto training */
6939 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6940 dev_priv->display.write_eld = ironlake_write_eld;
6941 } else if (IS_HASWELL(dev)) {
6942 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
6943 dev_priv->display.write_eld = ironlake_write_eld;
6944 } else
6945 dev_priv->display.update_wm = NULL;
6946 } else if (IS_G4X(dev)) {
6947 dev_priv->display.write_eld = g4x_write_eld;
6948 }
6949
6950 /* Default just returns -ENODEV to indicate unsupported */
6951 dev_priv->display.queue_flip = intel_default_queue_flip;
6952
6953 switch (INTEL_INFO(dev)->gen) {
6954 case 2:
6955 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6956 break;
6957
6958 case 3:
6959 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6960 break;
6961
6962 case 4:
6963 case 5:
6964 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6965 break;
6966
6967 case 6:
6968 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6969 break;
6970 case 7:
6971 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6972 break;
6973 }
6974 }
6975
6976 /*
6977 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6978 * resume, or other times. This quirk makes sure that's the case for
6979 * affected systems.
6980 */
6981 static void quirk_pipea_force(struct drm_device *dev)
6982 {
6983 struct drm_i915_private *dev_priv = dev->dev_private;
6984
6985 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6986 DRM_INFO("applying pipe a force quirk\n");
6987 }
6988
6989 /*
6990 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6991 */
6992 static void quirk_ssc_force_disable(struct drm_device *dev)
6993 {
6994 struct drm_i915_private *dev_priv = dev->dev_private;
6995 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6996 DRM_INFO("applying lvds SSC disable quirk\n");
6997 }
6998
6999 /*
7000 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7001 * brightness value
7002 */
7003 static void quirk_invert_brightness(struct drm_device *dev)
7004 {
7005 struct drm_i915_private *dev_priv = dev->dev_private;
7006 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7007 DRM_INFO("applying inverted panel brightness quirk\n");
7008 }
7009
7010 struct intel_quirk {
7011 int device;
7012 int subsystem_vendor;
7013 int subsystem_device;
7014 void (*hook)(struct drm_device *dev);
7015 };
7016
7017 static struct intel_quirk intel_quirks[] = {
7018 /* HP Mini needs pipe A force quirk (LP: #322104) */
7019 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7020
7021 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7022 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7023
7024 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7025 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7026
7027 /* 855 & before need to leave pipe A & dpll A up */
7028 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7029 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7030 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7031
7032 /* Lenovo U160 cannot use SSC on LVDS */
7033 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7034
7035 /* Sony Vaio Y cannot use SSC on LVDS */
7036 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7037
7038 /* Acer Aspire 5734Z must invert backlight brightness */
7039 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7040 };
7041
7042 static void intel_init_quirks(struct drm_device *dev)
7043 {
7044 struct pci_dev *d = dev->pdev;
7045 int i;
7046
7047 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7048 struct intel_quirk *q = &intel_quirks[i];
7049
7050 if (d->device == q->device &&
7051 (d->subsystem_vendor == q->subsystem_vendor ||
7052 q->subsystem_vendor == PCI_ANY_ID) &&
7053 (d->subsystem_device == q->subsystem_device ||
7054 q->subsystem_device == PCI_ANY_ID))
7055 q->hook(dev);
7056 }
7057 }
7058
7059 /* Disable the VGA plane that we never use */
7060 static void i915_disable_vga(struct drm_device *dev)
7061 {
7062 struct drm_i915_private *dev_priv = dev->dev_private;
7063 u8 sr1;
7064 u32 vga_reg;
7065
7066 if (HAS_PCH_SPLIT(dev))
7067 vga_reg = CPU_VGACNTRL;
7068 else
7069 vga_reg = VGACNTRL;
7070
7071 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7072 outb(SR01, VGA_SR_INDEX);
7073 sr1 = inb(VGA_SR_DATA);
7074 outb(sr1 | 1<<5, VGA_SR_DATA);
7075 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7076 udelay(300);
7077
7078 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7079 POSTING_READ(vga_reg);
7080 }
7081
7082 void intel_modeset_init_hw(struct drm_device *dev)
7083 {
7084 /* We attempt to init the necessary power wells early in the initialization
7085 * time, so the subsystems that expect power to be enabled can work.
7086 */
7087 intel_init_power_wells(dev);
7088
7089 intel_prepare_ddi(dev);
7090
7091 intel_init_clock_gating(dev);
7092
7093 mutex_lock(&dev->struct_mutex);
7094 intel_enable_gt_powersave(dev);
7095 mutex_unlock(&dev->struct_mutex);
7096 }
7097
7098 void intel_modeset_init(struct drm_device *dev)
7099 {
7100 struct drm_i915_private *dev_priv = dev->dev_private;
7101 int i, ret;
7102
7103 drm_mode_config_init(dev);
7104
7105 dev->mode_config.min_width = 0;
7106 dev->mode_config.min_height = 0;
7107
7108 dev->mode_config.preferred_depth = 24;
7109 dev->mode_config.prefer_shadow = 1;
7110
7111 dev->mode_config.funcs = &intel_mode_funcs;
7112
7113 intel_init_quirks(dev);
7114
7115 intel_init_pm(dev);
7116
7117 intel_init_display(dev);
7118
7119 if (IS_GEN2(dev)) {
7120 dev->mode_config.max_width = 2048;
7121 dev->mode_config.max_height = 2048;
7122 } else if (IS_GEN3(dev)) {
7123 dev->mode_config.max_width = 4096;
7124 dev->mode_config.max_height = 4096;
7125 } else {
7126 dev->mode_config.max_width = 8192;
7127 dev->mode_config.max_height = 8192;
7128 }
7129 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7130
7131 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7132 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7133
7134 for (i = 0; i < dev_priv->num_pipe; i++) {
7135 intel_crtc_init(dev, i);
7136 ret = intel_plane_init(dev, i);
7137 if (ret)
7138 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7139 }
7140
7141 intel_pch_pll_init(dev);
7142
7143 /* Just disable it once at startup */
7144 i915_disable_vga(dev);
7145 intel_setup_outputs(dev);
7146 }
7147
7148 void intel_modeset_gem_init(struct drm_device *dev)
7149 {
7150 intel_modeset_init_hw(dev);
7151
7152 intel_setup_overlay(dev);
7153 }
7154
7155 void intel_modeset_cleanup(struct drm_device *dev)
7156 {
7157 struct drm_i915_private *dev_priv = dev->dev_private;
7158 struct drm_crtc *crtc;
7159 struct intel_crtc *intel_crtc;
7160
7161 drm_kms_helper_poll_fini(dev);
7162 mutex_lock(&dev->struct_mutex);
7163
7164 intel_unregister_dsm_handler();
7165
7166
7167 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7168 /* Skip inactive CRTCs */
7169 if (!crtc->fb)
7170 continue;
7171
7172 intel_crtc = to_intel_crtc(crtc);
7173 intel_increase_pllclock(crtc);
7174 }
7175
7176 intel_disable_fbc(dev);
7177
7178 intel_disable_gt_powersave(dev);
7179
7180 ironlake_teardown_rc6(dev);
7181
7182 if (IS_VALLEYVIEW(dev))
7183 vlv_init_dpio(dev);
7184
7185 mutex_unlock(&dev->struct_mutex);
7186
7187 /* Disable the irq before mode object teardown, for the irq might
7188 * enqueue unpin/hotplug work. */
7189 drm_irq_uninstall(dev);
7190 cancel_work_sync(&dev_priv->hotplug_work);
7191 cancel_work_sync(&dev_priv->rps.work);
7192
7193 /* flush any delayed tasks or pending work */
7194 flush_scheduled_work();
7195
7196 drm_mode_config_cleanup(dev);
7197 }
7198
7199 /*
7200 * Return which encoder is currently attached for connector.
7201 */
7202 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7203 {
7204 return &intel_attached_encoder(connector)->base;
7205 }
7206
7207 void intel_connector_attach_encoder(struct intel_connector *connector,
7208 struct intel_encoder *encoder)
7209 {
7210 connector->encoder = encoder;
7211 drm_mode_connector_attach_encoder(&connector->base,
7212 &encoder->base);
7213 }
7214
7215 /*
7216 * set vga decode state - true == enable VGA decode
7217 */
7218 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7219 {
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7221 u16 gmch_ctrl;
7222
7223 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7224 if (state)
7225 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7226 else
7227 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7228 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7229 return 0;
7230 }
7231
7232 #ifdef CONFIG_DEBUG_FS
7233 #include <linux/seq_file.h>
7234
7235 struct intel_display_error_state {
7236 struct intel_cursor_error_state {
7237 u32 control;
7238 u32 position;
7239 u32 base;
7240 u32 size;
7241 } cursor[2];
7242
7243 struct intel_pipe_error_state {
7244 u32 conf;
7245 u32 source;
7246
7247 u32 htotal;
7248 u32 hblank;
7249 u32 hsync;
7250 u32 vtotal;
7251 u32 vblank;
7252 u32 vsync;
7253 } pipe[2];
7254
7255 struct intel_plane_error_state {
7256 u32 control;
7257 u32 stride;
7258 u32 size;
7259 u32 pos;
7260 u32 addr;
7261 u32 surface;
7262 u32 tile_offset;
7263 } plane[2];
7264 };
7265
7266 struct intel_display_error_state *
7267 intel_display_capture_error_state(struct drm_device *dev)
7268 {
7269 drm_i915_private_t *dev_priv = dev->dev_private;
7270 struct intel_display_error_state *error;
7271 int i;
7272
7273 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7274 if (error == NULL)
7275 return NULL;
7276
7277 for (i = 0; i < 2; i++) {
7278 error->cursor[i].control = I915_READ(CURCNTR(i));
7279 error->cursor[i].position = I915_READ(CURPOS(i));
7280 error->cursor[i].base = I915_READ(CURBASE(i));
7281
7282 error->plane[i].control = I915_READ(DSPCNTR(i));
7283 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7284 error->plane[i].size = I915_READ(DSPSIZE(i));
7285 error->plane[i].pos = I915_READ(DSPPOS(i));
7286 error->plane[i].addr = I915_READ(DSPADDR(i));
7287 if (INTEL_INFO(dev)->gen >= 4) {
7288 error->plane[i].surface = I915_READ(DSPSURF(i));
7289 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7290 }
7291
7292 error->pipe[i].conf = I915_READ(PIPECONF(i));
7293 error->pipe[i].source = I915_READ(PIPESRC(i));
7294 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7295 error->pipe[i].hblank = I915_READ(HBLANK(i));
7296 error->pipe[i].hsync = I915_READ(HSYNC(i));
7297 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7298 error->pipe[i].vblank = I915_READ(VBLANK(i));
7299 error->pipe[i].vsync = I915_READ(VSYNC(i));
7300 }
7301
7302 return error;
7303 }
7304
7305 void
7306 intel_display_print_error_state(struct seq_file *m,
7307 struct drm_device *dev,
7308 struct intel_display_error_state *error)
7309 {
7310 int i;
7311
7312 for (i = 0; i < 2; i++) {
7313 seq_printf(m, "Pipe [%d]:\n", i);
7314 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7315 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7316 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7317 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7318 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7319 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7320 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7321 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7322
7323 seq_printf(m, "Plane [%d]:\n", i);
7324 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7325 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7326 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7327 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7328 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7329 if (INTEL_INFO(dev)->gen >= 4) {
7330 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7331 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7332 }
7333
7334 seq_printf(m, "Cursor [%d]:\n", i);
7335 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7336 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7337 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7338 }
7339 }
7340 #endif
ubuntu-bionic-kernel mirror