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drm/i915: Preserve the state of power wells not explicitly enabled
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
100 struct drm_i915_gem_object *obj,
101 struct drm_mode_fb_cmd2 *mode_cmd);
102 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
103 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
105 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
106 struct intel_link_m_n *m_n,
107 struct intel_link_m_n *m2_n2);
108 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
109 static void haswell_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipemisc(struct drm_crtc *crtc);
111 static void vlv_prepare_pll(struct intel_crtc *crtc,
112 const struct intel_crtc_state *pipe_config);
113 static void chv_prepare_pll(struct intel_crtc *crtc,
114 const struct intel_crtc_state *pipe_config);
115 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
116 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
118 struct intel_crtc_state *crtc_state);
119 static void skylake_pfit_enable(struct intel_crtc *crtc);
120 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
121 static void ironlake_pfit_enable(struct intel_crtc *crtc);
122 static void intel_modeset_setup_hw_state(struct drm_device *dev);
123 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
124
125 struct intel_limit {
126 struct {
127 int min, max;
128 } dot, vco, n, m, m1, m2, p, p1;
129
130 struct {
131 int dot_limit;
132 int p2_slow, p2_fast;
133 } p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg, int ref_freq)
152 {
153 u32 val;
154 int divider;
155
156 mutex_lock(&dev_priv->sb_lock);
157 val = vlv_cck_read(dev_priv, reg);
158 mutex_unlock(&dev_priv->sb_lock);
159
160 divider = val & CCK_FREQUENCY_VALUES;
161
162 WARN((val & CCK_FREQUENCY_STATUS) !=
163 (divider << CCK_FREQUENCY_STATUS_SHIFT),
164 "%s change in progress\n", name);
165
166 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
167 }
168
169 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
170 const char *name, u32 reg)
171 {
172 if (dev_priv->hpll_freq == 0)
173 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
174
175 return vlv_get_cck_clock(dev_priv, name, reg,
176 dev_priv->hpll_freq);
177 }
178
179 static void intel_update_czclk(struct drm_i915_private *dev_priv)
180 {
181 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
182 return;
183
184 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
185 CCK_CZ_CLOCK_CONTROL);
186
187 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
188 }
189
190 static inline u32 /* units of 100MHz */
191 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
192 const struct intel_crtc_state *pipe_config)
193 {
194 if (HAS_DDI(dev_priv))
195 return pipe_config->port_clock; /* SPLL */
196 else if (IS_GEN5(dev_priv))
197 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
198 else
199 return 270000;
200 }
201
202 static const struct intel_limit intel_limits_i8xx_dac = {
203 .dot = { .min = 25000, .max = 350000 },
204 .vco = { .min = 908000, .max = 1512000 },
205 .n = { .min = 2, .max = 16 },
206 .m = { .min = 96, .max = 140 },
207 .m1 = { .min = 18, .max = 26 },
208 .m2 = { .min = 6, .max = 16 },
209 .p = { .min = 4, .max = 128 },
210 .p1 = { .min = 2, .max = 33 },
211 .p2 = { .dot_limit = 165000,
212 .p2_slow = 4, .p2_fast = 2 },
213 };
214
215 static const struct intel_limit intel_limits_i8xx_dvo = {
216 .dot = { .min = 25000, .max = 350000 },
217 .vco = { .min = 908000, .max = 1512000 },
218 .n = { .min = 2, .max = 16 },
219 .m = { .min = 96, .max = 140 },
220 .m1 = { .min = 18, .max = 26 },
221 .m2 = { .min = 6, .max = 16 },
222 .p = { .min = 4, .max = 128 },
223 .p1 = { .min = 2, .max = 33 },
224 .p2 = { .dot_limit = 165000,
225 .p2_slow = 4, .p2_fast = 4 },
226 };
227
228 static const struct intel_limit intel_limits_i8xx_lvds = {
229 .dot = { .min = 25000, .max = 350000 },
230 .vco = { .min = 908000, .max = 1512000 },
231 .n = { .min = 2, .max = 16 },
232 .m = { .min = 96, .max = 140 },
233 .m1 = { .min = 18, .max = 26 },
234 .m2 = { .min = 6, .max = 16 },
235 .p = { .min = 4, .max = 128 },
236 .p1 = { .min = 1, .max = 6 },
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 14, .p2_fast = 7 },
239 };
240
241 static const struct intel_limit intel_limits_i9xx_sdvo = {
242 .dot = { .min = 20000, .max = 400000 },
243 .vco = { .min = 1400000, .max = 2800000 },
244 .n = { .min = 1, .max = 6 },
245 .m = { .min = 70, .max = 120 },
246 .m1 = { .min = 8, .max = 18 },
247 .m2 = { .min = 3, .max = 7 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
252 };
253
254 static const struct intel_limit intel_limits_i9xx_lvds = {
255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1400000, .max = 2800000 },
257 .n = { .min = 1, .max = 6 },
258 .m = { .min = 70, .max = 120 },
259 .m1 = { .min = 8, .max = 18 },
260 .m2 = { .min = 3, .max = 7 },
261 .p = { .min = 7, .max = 98 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 7 },
265 };
266
267
268 static const struct intel_limit intel_limits_g4x_sdvo = {
269 .dot = { .min = 25000, .max = 270000 },
270 .vco = { .min = 1750000, .max = 3500000},
271 .n = { .min = 1, .max = 4 },
272 .m = { .min = 104, .max = 138 },
273 .m1 = { .min = 17, .max = 23 },
274 .m2 = { .min = 5, .max = 11 },
275 .p = { .min = 10, .max = 30 },
276 .p1 = { .min = 1, .max = 3},
277 .p2 = { .dot_limit = 270000,
278 .p2_slow = 10,
279 .p2_fast = 10
280 },
281 };
282
283 static const struct intel_limit intel_limits_g4x_hdmi = {
284 .dot = { .min = 22000, .max = 400000 },
285 .vco = { .min = 1750000, .max = 3500000},
286 .n = { .min = 1, .max = 4 },
287 .m = { .min = 104, .max = 138 },
288 .m1 = { .min = 16, .max = 23 },
289 .m2 = { .min = 5, .max = 11 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8},
292 .p2 = { .dot_limit = 165000,
293 .p2_slow = 10, .p2_fast = 5 },
294 };
295
296 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
297 .dot = { .min = 20000, .max = 115000 },
298 .vco = { .min = 1750000, .max = 3500000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 104, .max = 138 },
301 .m1 = { .min = 17, .max = 23 },
302 .m2 = { .min = 5, .max = 11 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 0,
306 .p2_slow = 14, .p2_fast = 14
307 },
308 };
309
310 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
311 .dot = { .min = 80000, .max = 224000 },
312 .vco = { .min = 1750000, .max = 3500000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 104, .max = 138 },
315 .m1 = { .min = 17, .max = 23 },
316 .m2 = { .min = 5, .max = 11 },
317 .p = { .min = 14, .max = 42 },
318 .p1 = { .min = 2, .max = 6 },
319 .p2 = { .dot_limit = 0,
320 .p2_slow = 7, .p2_fast = 7
321 },
322 };
323
324 static const struct intel_limit intel_limits_pineview_sdvo = {
325 .dot = { .min = 20000, .max = 400000},
326 .vco = { .min = 1700000, .max = 3500000 },
327 /* Pineview's Ncounter is a ring counter */
328 .n = { .min = 3, .max = 6 },
329 .m = { .min = 2, .max = 256 },
330 /* Pineview only has one combined m divider, which we treat as m2. */
331 .m1 = { .min = 0, .max = 0 },
332 .m2 = { .min = 0, .max = 254 },
333 .p = { .min = 5, .max = 80 },
334 .p1 = { .min = 1, .max = 8 },
335 .p2 = { .dot_limit = 200000,
336 .p2_slow = 10, .p2_fast = 5 },
337 };
338
339 static const struct intel_limit intel_limits_pineview_lvds = {
340 .dot = { .min = 20000, .max = 400000 },
341 .vco = { .min = 1700000, .max = 3500000 },
342 .n = { .min = 3, .max = 6 },
343 .m = { .min = 2, .max = 256 },
344 .m1 = { .min = 0, .max = 0 },
345 .m2 = { .min = 0, .max = 254 },
346 .p = { .min = 7, .max = 112 },
347 .p1 = { .min = 1, .max = 8 },
348 .p2 = { .dot_limit = 112000,
349 .p2_slow = 14, .p2_fast = 14 },
350 };
351
352 /* Ironlake / Sandybridge
353 *
354 * We calculate clock using (register_value + 2) for N/M1/M2, so here
355 * the range value for them is (actual_value - 2).
356 */
357 static const struct intel_limit intel_limits_ironlake_dac = {
358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 5 },
361 .m = { .min = 79, .max = 127 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 5, .max = 80 },
365 .p1 = { .min = 1, .max = 8 },
366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 10, .p2_fast = 5 },
368 };
369
370 static const struct intel_limit intel_limits_ironlake_single_lvds = {
371 .dot = { .min = 25000, .max = 350000 },
372 .vco = { .min = 1760000, .max = 3510000 },
373 .n = { .min = 1, .max = 3 },
374 .m = { .min = 79, .max = 118 },
375 .m1 = { .min = 12, .max = 22 },
376 .m2 = { .min = 5, .max = 9 },
377 .p = { .min = 28, .max = 112 },
378 .p1 = { .min = 2, .max = 8 },
379 .p2 = { .dot_limit = 225000,
380 .p2_slow = 14, .p2_fast = 14 },
381 };
382
383 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
384 .dot = { .min = 25000, .max = 350000 },
385 .vco = { .min = 1760000, .max = 3510000 },
386 .n = { .min = 1, .max = 3 },
387 .m = { .min = 79, .max = 127 },
388 .m1 = { .min = 12, .max = 22 },
389 .m2 = { .min = 5, .max = 9 },
390 .p = { .min = 14, .max = 56 },
391 .p1 = { .min = 2, .max = 8 },
392 .p2 = { .dot_limit = 225000,
393 .p2_slow = 7, .p2_fast = 7 },
394 };
395
396 /* LVDS 100mhz refclk limits. */
397 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
398 .dot = { .min = 25000, .max = 350000 },
399 .vco = { .min = 1760000, .max = 3510000 },
400 .n = { .min = 1, .max = 2 },
401 .m = { .min = 79, .max = 126 },
402 .m1 = { .min = 12, .max = 22 },
403 .m2 = { .min = 5, .max = 9 },
404 .p = { .min = 28, .max = 112 },
405 .p1 = { .min = 2, .max = 8 },
406 .p2 = { .dot_limit = 225000,
407 .p2_slow = 14, .p2_fast = 14 },
408 };
409
410 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
411 .dot = { .min = 25000, .max = 350000 },
412 .vco = { .min = 1760000, .max = 3510000 },
413 .n = { .min = 1, .max = 3 },
414 .m = { .min = 79, .max = 126 },
415 .m1 = { .min = 12, .max = 22 },
416 .m2 = { .min = 5, .max = 9 },
417 .p = { .min = 14, .max = 42 },
418 .p1 = { .min = 2, .max = 6 },
419 .p2 = { .dot_limit = 225000,
420 .p2_slow = 7, .p2_fast = 7 },
421 };
422
423 static const struct intel_limit intel_limits_vlv = {
424 /*
425 * These are the data rate limits (measured in fast clocks)
426 * since those are the strictest limits we have. The fast
427 * clock and actual rate limits are more relaxed, so checking
428 * them would make no difference.
429 */
430 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
431 .vco = { .min = 4000000, .max = 6000000 },
432 .n = { .min = 1, .max = 7 },
433 .m1 = { .min = 2, .max = 3 },
434 .m2 = { .min = 11, .max = 156 },
435 .p1 = { .min = 2, .max = 3 },
436 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
437 };
438
439 static const struct intel_limit intel_limits_chv = {
440 /*
441 * These are the data rate limits (measured in fast clocks)
442 * since those are the strictest limits we have. The fast
443 * clock and actual rate limits are more relaxed, so checking
444 * them would make no difference.
445 */
446 .dot = { .min = 25000 * 5, .max = 540000 * 5},
447 .vco = { .min = 4800000, .max = 6480000 },
448 .n = { .min = 1, .max = 1 },
449 .m1 = { .min = 2, .max = 2 },
450 .m2 = { .min = 24 << 22, .max = 175 << 22 },
451 .p1 = { .min = 2, .max = 4 },
452 .p2 = { .p2_slow = 1, .p2_fast = 14 },
453 };
454
455 static const struct intel_limit intel_limits_bxt = {
456 /* FIXME: find real dot limits */
457 .dot = { .min = 0, .max = INT_MAX },
458 .vco = { .min = 4800000, .max = 6700000 },
459 .n = { .min = 1, .max = 1 },
460 .m1 = { .min = 2, .max = 2 },
461 /* FIXME: find real m2 limits */
462 .m2 = { .min = 2 << 22, .max = 255 << 22 },
463 .p1 = { .min = 2, .max = 4 },
464 .p2 = { .p2_slow = 1, .p2_fast = 20 },
465 };
466
467 static bool
468 needs_modeset(struct drm_crtc_state *state)
469 {
470 return drm_atomic_crtc_needs_modeset(state);
471 }
472
473 /*
474 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
475 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
476 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
477 * The helpers' return value is the rate of the clock that is fed to the
478 * display engine's pipe which can be the above fast dot clock rate or a
479 * divided-down version of it.
480 */
481 /* m1 is reserved as 0 in Pineview, n is a ring counter */
482 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
483 {
484 clock->m = clock->m2 + 2;
485 clock->p = clock->p1 * clock->p2;
486 if (WARN_ON(clock->n == 0 || clock->p == 0))
487 return 0;
488 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
489 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
490
491 return clock->dot;
492 }
493
494 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
495 {
496 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
497 }
498
499 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
500 {
501 clock->m = i9xx_dpll_compute_m(clock);
502 clock->p = clock->p1 * clock->p2;
503 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
504 return 0;
505 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
506 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
507
508 return clock->dot;
509 }
510
511 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
512 {
513 clock->m = clock->m1 * clock->m2;
514 clock->p = clock->p1 * clock->p2;
515 if (WARN_ON(clock->n == 0 || clock->p == 0))
516 return 0;
517 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
518 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
519
520 return clock->dot / 5;
521 }
522
523 int chv_calc_dpll_params(int refclk, struct dpll *clock)
524 {
525 clock->m = clock->m1 * clock->m2;
526 clock->p = clock->p1 * clock->p2;
527 if (WARN_ON(clock->n == 0 || clock->p == 0))
528 return 0;
529 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
530 clock->n << 22);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532
533 return clock->dot / 5;
534 }
535
536 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
537 /**
538 * Returns whether the given set of divisors are valid for a given refclk with
539 * the given connectors.
540 */
541
542 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
543 const struct intel_limit *limit,
544 const struct dpll *clock)
545 {
546 if (clock->n < limit->n.min || limit->n.max < clock->n)
547 INTELPllInvalid("n out of range\n");
548 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
549 INTELPllInvalid("p1 out of range\n");
550 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
551 INTELPllInvalid("m2 out of range\n");
552 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
553 INTELPllInvalid("m1 out of range\n");
554
555 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
556 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
557 if (clock->m1 <= clock->m2)
558 INTELPllInvalid("m1 <= m2\n");
559
560 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
561 !IS_GEN9_LP(dev_priv)) {
562 if (clock->p < limit->p.min || limit->p.max < clock->p)
563 INTELPllInvalid("p out of range\n");
564 if (clock->m < limit->m.min || limit->m.max < clock->m)
565 INTELPllInvalid("m out of range\n");
566 }
567
568 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
569 INTELPllInvalid("vco out of range\n");
570 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
571 * connector, etc., rather than just a single range.
572 */
573 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
574 INTELPllInvalid("dot out of range\n");
575
576 return true;
577 }
578
579 static int
580 i9xx_select_p2_div(const struct intel_limit *limit,
581 const struct intel_crtc_state *crtc_state,
582 int target)
583 {
584 struct drm_device *dev = crtc_state->base.crtc->dev;
585
586 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
587 /*
588 * For LVDS just rely on its current settings for dual-channel.
589 * We haven't figured out how to reliably set up different
590 * single/dual channel state, if we even can.
591 */
592 if (intel_is_dual_link_lvds(dev))
593 return limit->p2.p2_fast;
594 else
595 return limit->p2.p2_slow;
596 } else {
597 if (target < limit->p2.dot_limit)
598 return limit->p2.p2_slow;
599 else
600 return limit->p2.p2_fast;
601 }
602 }
603
604 /*
605 * Returns a set of divisors for the desired target clock with the given
606 * refclk, or FALSE. The returned values represent the clock equation:
607 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
608 *
609 * Target and reference clocks are specified in kHz.
610 *
611 * If match_clock is provided, then best_clock P divider must match the P
612 * divider from @match_clock used for LVDS downclocking.
613 */
614 static bool
615 i9xx_find_best_dpll(const struct intel_limit *limit,
616 struct intel_crtc_state *crtc_state,
617 int target, int refclk, struct dpll *match_clock,
618 struct dpll *best_clock)
619 {
620 struct drm_device *dev = crtc_state->base.crtc->dev;
621 struct dpll clock;
622 int err = target;
623
624 memset(best_clock, 0, sizeof(*best_clock));
625
626 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
627
628 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
629 clock.m1++) {
630 for (clock.m2 = limit->m2.min;
631 clock.m2 <= limit->m2.max; clock.m2++) {
632 if (clock.m2 >= clock.m1)
633 break;
634 for (clock.n = limit->n.min;
635 clock.n <= limit->n.max; clock.n++) {
636 for (clock.p1 = limit->p1.min;
637 clock.p1 <= limit->p1.max; clock.p1++) {
638 int this_err;
639
640 i9xx_calc_dpll_params(refclk, &clock);
641 if (!intel_PLL_is_valid(to_i915(dev),
642 limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 /*
663 * Returns a set of divisors for the desired target clock with the given
664 * refclk, or FALSE. The returned values represent the clock equation:
665 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
666 *
667 * Target and reference clocks are specified in kHz.
668 *
669 * If match_clock is provided, then best_clock P divider must match the P
670 * divider from @match_clock used for LVDS downclocking.
671 */
672 static bool
673 pnv_find_best_dpll(const struct intel_limit *limit,
674 struct intel_crtc_state *crtc_state,
675 int target, int refclk, struct dpll *match_clock,
676 struct dpll *best_clock)
677 {
678 struct drm_device *dev = crtc_state->base.crtc->dev;
679 struct dpll clock;
680 int err = target;
681
682 memset(best_clock, 0, sizeof(*best_clock));
683
684 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
685
686 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
687 clock.m1++) {
688 for (clock.m2 = limit->m2.min;
689 clock.m2 <= limit->m2.max; clock.m2++) {
690 for (clock.n = limit->n.min;
691 clock.n <= limit->n.max; clock.n++) {
692 for (clock.p1 = limit->p1.min;
693 clock.p1 <= limit->p1.max; clock.p1++) {
694 int this_err;
695
696 pnv_calc_dpll_params(refclk, &clock);
697 if (!intel_PLL_is_valid(to_i915(dev),
698 limit,
699 &clock))
700 continue;
701 if (match_clock &&
702 clock.p != match_clock->p)
703 continue;
704
705 this_err = abs(clock.dot - target);
706 if (this_err < err) {
707 *best_clock = clock;
708 err = this_err;
709 }
710 }
711 }
712 }
713 }
714
715 return (err != target);
716 }
717
718 /*
719 * Returns a set of divisors for the desired target clock with the given
720 * refclk, or FALSE. The returned values represent the clock equation:
721 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
722 *
723 * Target and reference clocks are specified in kHz.
724 *
725 * If match_clock is provided, then best_clock P divider must match the P
726 * divider from @match_clock used for LVDS downclocking.
727 */
728 static bool
729 g4x_find_best_dpll(const struct intel_limit *limit,
730 struct intel_crtc_state *crtc_state,
731 int target, int refclk, struct dpll *match_clock,
732 struct dpll *best_clock)
733 {
734 struct drm_device *dev = crtc_state->base.crtc->dev;
735 struct dpll clock;
736 int max_n;
737 bool found = false;
738 /* approximately equals target * 0.00585 */
739 int err_most = (target >> 8) + (target >> 9);
740
741 memset(best_clock, 0, sizeof(*best_clock));
742
743 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
744
745 max_n = limit->n.max;
746 /* based on hardware requirement, prefer smaller n to precision */
747 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
748 /* based on hardware requirement, prefere larger m1,m2 */
749 for (clock.m1 = limit->m1.max;
750 clock.m1 >= limit->m1.min; clock.m1--) {
751 for (clock.m2 = limit->m2.max;
752 clock.m2 >= limit->m2.min; clock.m2--) {
753 for (clock.p1 = limit->p1.max;
754 clock.p1 >= limit->p1.min; clock.p1--) {
755 int this_err;
756
757 i9xx_calc_dpll_params(refclk, &clock);
758 if (!intel_PLL_is_valid(to_i915(dev),
759 limit,
760 &clock))
761 continue;
762
763 this_err = abs(clock.dot - target);
764 if (this_err < err_most) {
765 *best_clock = clock;
766 err_most = this_err;
767 max_n = clock.n;
768 found = true;
769 }
770 }
771 }
772 }
773 }
774 return found;
775 }
776
777 /*
778 * Check if the calculated PLL configuration is more optimal compared to the
779 * best configuration and error found so far. Return the calculated error.
780 */
781 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
782 const struct dpll *calculated_clock,
783 const struct dpll *best_clock,
784 unsigned int best_error_ppm,
785 unsigned int *error_ppm)
786 {
787 /*
788 * For CHV ignore the error and consider only the P value.
789 * Prefer a bigger P value based on HW requirements.
790 */
791 if (IS_CHERRYVIEW(to_i915(dev))) {
792 *error_ppm = 0;
793
794 return calculated_clock->p > best_clock->p;
795 }
796
797 if (WARN_ON_ONCE(!target_freq))
798 return false;
799
800 *error_ppm = div_u64(1000000ULL *
801 abs(target_freq - calculated_clock->dot),
802 target_freq);
803 /*
804 * Prefer a better P value over a better (smaller) error if the error
805 * is small. Ensure this preference for future configurations too by
806 * setting the error to 0.
807 */
808 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
809 *error_ppm = 0;
810
811 return true;
812 }
813
814 return *error_ppm + 10 < best_error_ppm;
815 }
816
817 /*
818 * Returns a set of divisors for the desired target clock with the given
819 * refclk, or FALSE. The returned values represent the clock equation:
820 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
821 */
822 static bool
823 vlv_find_best_dpll(const struct intel_limit *limit,
824 struct intel_crtc_state *crtc_state,
825 int target, int refclk, struct dpll *match_clock,
826 struct dpll *best_clock)
827 {
828 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
829 struct drm_device *dev = crtc->base.dev;
830 struct dpll clock;
831 unsigned int bestppm = 1000000;
832 /* min update 19.2 MHz */
833 int max_n = min(limit->n.max, refclk / 19200);
834 bool found = false;
835
836 target *= 5; /* fast clock */
837
838 memset(best_clock, 0, sizeof(*best_clock));
839
840 /* based on hardware requirement, prefer smaller n to precision */
841 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
842 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
843 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
844 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
845 clock.p = clock.p1 * clock.p2;
846 /* based on hardware requirement, prefer bigger m1,m2 values */
847 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
848 unsigned int ppm;
849
850 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
851 refclk * clock.m1);
852
853 vlv_calc_dpll_params(refclk, &clock);
854
855 if (!intel_PLL_is_valid(to_i915(dev),
856 limit,
857 &clock))
858 continue;
859
860 if (!vlv_PLL_is_optimal(dev, target,
861 &clock,
862 best_clock,
863 bestppm, &ppm))
864 continue;
865
866 *best_clock = clock;
867 bestppm = ppm;
868 found = true;
869 }
870 }
871 }
872 }
873
874 return found;
875 }
876
877 /*
878 * Returns a set of divisors for the desired target clock with the given
879 * refclk, or FALSE. The returned values represent the clock equation:
880 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
881 */
882 static bool
883 chv_find_best_dpll(const struct intel_limit *limit,
884 struct intel_crtc_state *crtc_state,
885 int target, int refclk, struct dpll *match_clock,
886 struct dpll *best_clock)
887 {
888 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
889 struct drm_device *dev = crtc->base.dev;
890 unsigned int best_error_ppm;
891 struct dpll clock;
892 uint64_t m2;
893 int found = false;
894
895 memset(best_clock, 0, sizeof(*best_clock));
896 best_error_ppm = 1000000;
897
898 /*
899 * Based on hardware doc, the n always set to 1, and m1 always
900 * set to 2. If requires to support 200Mhz refclk, we need to
901 * revisit this because n may not 1 anymore.
902 */
903 clock.n = 1, clock.m1 = 2;
904 target *= 5; /* fast clock */
905
906 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
907 for (clock.p2 = limit->p2.p2_fast;
908 clock.p2 >= limit->p2.p2_slow;
909 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
910 unsigned int error_ppm;
911
912 clock.p = clock.p1 * clock.p2;
913
914 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
915 clock.n) << 22, refclk * clock.m1);
916
917 if (m2 > INT_MAX/clock.m1)
918 continue;
919
920 clock.m2 = m2;
921
922 chv_calc_dpll_params(refclk, &clock);
923
924 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
925 continue;
926
927 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
928 best_error_ppm, &error_ppm))
929 continue;
930
931 *best_clock = clock;
932 best_error_ppm = error_ppm;
933 found = true;
934 }
935 }
936
937 return found;
938 }
939
940 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
941 struct dpll *best_clock)
942 {
943 int refclk = 100000;
944 const struct intel_limit *limit = &intel_limits_bxt;
945
946 return chv_find_best_dpll(limit, crtc_state,
947 target_clock, refclk, NULL, best_clock);
948 }
949
950 bool intel_crtc_active(struct intel_crtc *crtc)
951 {
952 /* Be paranoid as we can arrive here with only partial
953 * state retrieved from the hardware during setup.
954 *
955 * We can ditch the adjusted_mode.crtc_clock check as soon
956 * as Haswell has gained clock readout/fastboot support.
957 *
958 * We can ditch the crtc->primary->fb check as soon as we can
959 * properly reconstruct framebuffers.
960 *
961 * FIXME: The intel_crtc->active here should be switched to
962 * crtc->state->active once we have proper CRTC states wired up
963 * for atomic.
964 */
965 return crtc->active && crtc->base.primary->state->fb &&
966 crtc->config->base.adjusted_mode.crtc_clock;
967 }
968
969 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971 {
972 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
973
974 return crtc->config->cpu_transcoder;
975 }
976
977 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
978 {
979 i915_reg_t reg = PIPEDSL(pipe);
980 u32 line1, line2;
981 u32 line_mask;
982
983 if (IS_GEN2(dev_priv))
984 line_mask = DSL_LINEMASK_GEN2;
985 else
986 line_mask = DSL_LINEMASK_GEN3;
987
988 line1 = I915_READ(reg) & line_mask;
989 msleep(5);
990 line2 = I915_READ(reg) & line_mask;
991
992 return line1 == line2;
993 }
994
995 /*
996 * intel_wait_for_pipe_off - wait for pipe to turn off
997 * @crtc: crtc whose pipe to wait for
998 *
999 * After disabling a pipe, we can't wait for vblank in the usual way,
1000 * spinning on the vblank interrupt status bit, since we won't actually
1001 * see an interrupt when the pipe is disabled.
1002 *
1003 * On Gen4 and above:
1004 * wait for the pipe register state bit to turn off
1005 *
1006 * Otherwise:
1007 * wait for the display line value to settle (it usually
1008 * ends up stopping at the start of the next frame).
1009 *
1010 */
1011 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1012 {
1013 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1014 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1015 enum pipe pipe = crtc->pipe;
1016
1017 if (INTEL_GEN(dev_priv) >= 4) {
1018 i915_reg_t reg = PIPECONF(cpu_transcoder);
1019
1020 /* Wait for the Pipe State to go off */
1021 if (intel_wait_for_register(dev_priv,
1022 reg, I965_PIPECONF_ACTIVE, 0,
1023 100))
1024 WARN(1, "pipe_off wait timed out\n");
1025 } else {
1026 /* Wait for the display line to settle */
1027 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1028 WARN(1, "pipe_off wait timed out\n");
1029 }
1030 }
1031
1032 /* Only for pre-ILK configs */
1033 void assert_pll(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, bool state)
1035 {
1036 u32 val;
1037 bool cur_state;
1038
1039 val = I915_READ(DPLL(pipe));
1040 cur_state = !!(val & DPLL_VCO_ENABLE);
1041 I915_STATE_WARN(cur_state != state,
1042 "PLL state assertion failure (expected %s, current %s)\n",
1043 onoff(state), onoff(cur_state));
1044 }
1045
1046 /* XXX: the dsi pll is shared between MIPI DSI ports */
1047 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1048 {
1049 u32 val;
1050 bool cur_state;
1051
1052 mutex_lock(&dev_priv->sb_lock);
1053 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1054 mutex_unlock(&dev_priv->sb_lock);
1055
1056 cur_state = val & DSI_PLL_VCO_EN;
1057 I915_STATE_WARN(cur_state != state,
1058 "DSI PLL state assertion failure (expected %s, current %s)\n",
1059 onoff(state), onoff(cur_state));
1060 }
1061
1062 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1063 enum pipe pipe, bool state)
1064 {
1065 bool cur_state;
1066 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067 pipe);
1068
1069 if (HAS_DDI(dev_priv)) {
1070 /* DDI does not have a specific FDI_TX register */
1071 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1072 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1073 } else {
1074 u32 val = I915_READ(FDI_TX_CTL(pipe));
1075 cur_state = !!(val & FDI_TX_ENABLE);
1076 }
1077 I915_STATE_WARN(cur_state != state,
1078 "FDI TX state assertion failure (expected %s, current %s)\n",
1079 onoff(state), onoff(cur_state));
1080 }
1081 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1082 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1083
1084 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1085 enum pipe pipe, bool state)
1086 {
1087 u32 val;
1088 bool cur_state;
1089
1090 val = I915_READ(FDI_RX_CTL(pipe));
1091 cur_state = !!(val & FDI_RX_ENABLE);
1092 I915_STATE_WARN(cur_state != state,
1093 "FDI RX state assertion failure (expected %s, current %s)\n",
1094 onoff(state), onoff(cur_state));
1095 }
1096 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1097 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1098
1099 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1100 enum pipe pipe)
1101 {
1102 u32 val;
1103
1104 /* ILK FDI PLL is always enabled */
1105 if (IS_GEN5(dev_priv))
1106 return;
1107
1108 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1109 if (HAS_DDI(dev_priv))
1110 return;
1111
1112 val = I915_READ(FDI_TX_CTL(pipe));
1113 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1114 }
1115
1116 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1117 enum pipe pipe, bool state)
1118 {
1119 u32 val;
1120 bool cur_state;
1121
1122 val = I915_READ(FDI_RX_CTL(pipe));
1123 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1124 I915_STATE_WARN(cur_state != state,
1125 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1126 onoff(state), onoff(cur_state));
1127 }
1128
1129 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1130 {
1131 i915_reg_t pp_reg;
1132 u32 val;
1133 enum pipe panel_pipe = PIPE_A;
1134 bool locked = true;
1135
1136 if (WARN_ON(HAS_DDI(dev_priv)))
1137 return;
1138
1139 if (HAS_PCH_SPLIT(dev_priv)) {
1140 u32 port_sel;
1141
1142 pp_reg = PP_CONTROL(0);
1143 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1144
1145 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1146 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1147 panel_pipe = PIPE_B;
1148 /* XXX: else fix for eDP */
1149 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1150 /* presumably write lock depends on pipe, not port select */
1151 pp_reg = PP_CONTROL(pipe);
1152 panel_pipe = pipe;
1153 } else {
1154 pp_reg = PP_CONTROL(0);
1155 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1156 panel_pipe = PIPE_B;
1157 }
1158
1159 val = I915_READ(pp_reg);
1160 if (!(val & PANEL_POWER_ON) ||
1161 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1162 locked = false;
1163
1164 I915_STATE_WARN(panel_pipe == pipe && locked,
1165 "panel assertion failure, pipe %c regs locked\n",
1166 pipe_name(pipe));
1167 }
1168
1169 static void assert_cursor(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, bool state)
1171 {
1172 bool cur_state;
1173
1174 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1175 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1176 else
1177 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1178
1179 I915_STATE_WARN(cur_state != state,
1180 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1181 pipe_name(pipe), onoff(state), onoff(cur_state));
1182 }
1183 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1184 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1185
1186 void assert_pipe(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, bool state)
1188 {
1189 bool cur_state;
1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
1192 enum intel_display_power_domain power_domain;
1193
1194 /* if we need the pipe quirk it must be always on */
1195 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1196 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1197 state = true;
1198
1199 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1200 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1201 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1202 cur_state = !!(val & PIPECONF_ENABLE);
1203
1204 intel_display_power_put(dev_priv, power_domain);
1205 } else {
1206 cur_state = false;
1207 }
1208
1209 I915_STATE_WARN(cur_state != state,
1210 "pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe), onoff(state), onoff(cur_state));
1212 }
1213
1214 static void assert_plane(struct drm_i915_private *dev_priv,
1215 enum plane plane, bool state)
1216 {
1217 u32 val;
1218 bool cur_state;
1219
1220 val = I915_READ(DSPCNTR(plane));
1221 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1222 I915_STATE_WARN(cur_state != state,
1223 "plane %c assertion failure (expected %s, current %s)\n",
1224 plane_name(plane), onoff(state), onoff(cur_state));
1225 }
1226
1227 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1228 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1229
1230 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 int i;
1234
1235 /* Primary planes are fixed to pipes on gen4+ */
1236 if (INTEL_GEN(dev_priv) >= 4) {
1237 u32 val = I915_READ(DSPCNTR(pipe));
1238 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1239 "plane %c assertion failure, should be disabled but not\n",
1240 plane_name(pipe));
1241 return;
1242 }
1243
1244 /* Need to check both planes against the pipe */
1245 for_each_pipe(dev_priv, i) {
1246 u32 val = I915_READ(DSPCNTR(i));
1247 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1248 DISPPLANE_SEL_PIPE_SHIFT;
1249 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1250 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1251 plane_name(i), pipe_name(pipe));
1252 }
1253 }
1254
1255 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1256 enum pipe pipe)
1257 {
1258 int sprite;
1259
1260 if (INTEL_GEN(dev_priv) >= 9) {
1261 for_each_sprite(dev_priv, pipe, sprite) {
1262 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1263 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1264 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1265 sprite, pipe_name(pipe));
1266 }
1267 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1268 for_each_sprite(dev_priv, pipe, sprite) {
1269 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1270 I915_STATE_WARN(val & SP_ENABLE,
1271 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1272 sprite_name(pipe, sprite), pipe_name(pipe));
1273 }
1274 } else if (INTEL_GEN(dev_priv) >= 7) {
1275 u32 val = I915_READ(SPRCTL(pipe));
1276 I915_STATE_WARN(val & SPRITE_ENABLE,
1277 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1278 plane_name(pipe), pipe_name(pipe));
1279 } else if (INTEL_GEN(dev_priv) >= 5) {
1280 u32 val = I915_READ(DVSCNTR(pipe));
1281 I915_STATE_WARN(val & DVS_ENABLE,
1282 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1283 plane_name(pipe), pipe_name(pipe));
1284 }
1285 }
1286
1287 static void assert_vblank_disabled(struct drm_crtc *crtc)
1288 {
1289 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1290 drm_crtc_vblank_put(crtc);
1291 }
1292
1293 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1294 enum pipe pipe)
1295 {
1296 u32 val;
1297 bool enabled;
1298
1299 val = I915_READ(PCH_TRANSCONF(pipe));
1300 enabled = !!(val & TRANS_ENABLE);
1301 I915_STATE_WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv)) {
1313 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1314 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1315 return false;
1316 } else if (IS_CHERRYVIEW(dev_priv)) {
1317 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1318 return false;
1319 } else {
1320 if ((val & DP_PIPE_MASK) != (pipe << 30))
1321 return false;
1322 }
1323 return true;
1324 }
1325
1326 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, u32 val)
1328 {
1329 if ((val & SDVO_ENABLE) == 0)
1330 return false;
1331
1332 if (HAS_PCH_CPT(dev_priv)) {
1333 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1334 return false;
1335 } else if (IS_CHERRYVIEW(dev_priv)) {
1336 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1337 return false;
1338 } else {
1339 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1340 return false;
1341 }
1342 return true;
1343 }
1344
1345 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1346 enum pipe pipe, u32 val)
1347 {
1348 if ((val & LVDS_PORT_EN) == 0)
1349 return false;
1350
1351 if (HAS_PCH_CPT(dev_priv)) {
1352 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1353 return false;
1354 } else {
1355 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1356 return false;
1357 }
1358 return true;
1359 }
1360
1361 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1362 enum pipe pipe, u32 val)
1363 {
1364 if ((val & ADPA_DAC_ENABLE) == 0)
1365 return false;
1366 if (HAS_PCH_CPT(dev_priv)) {
1367 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1368 return false;
1369 } else {
1370 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1371 return false;
1372 }
1373 return true;
1374 }
1375
1376 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1377 enum pipe pipe, i915_reg_t reg,
1378 u32 port_sel)
1379 {
1380 u32 val = I915_READ(reg);
1381 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1382 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1383 i915_mmio_reg_offset(reg), pipe_name(pipe));
1384
1385 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1386 && (val & DP_PIPEB_SELECT),
1387 "IBX PCH dp port still using transcoder B\n");
1388 }
1389
1390 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe, i915_reg_t reg)
1392 {
1393 u32 val = I915_READ(reg);
1394 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1395 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1396 i915_mmio_reg_offset(reg), pipe_name(pipe));
1397
1398 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1399 && (val & SDVO_PIPE_B_SELECT),
1400 "IBX PCH hdmi port still using transcoder B\n");
1401 }
1402
1403 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe)
1405 {
1406 u32 val;
1407
1408 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1411
1412 val = I915_READ(PCH_ADPA);
1413 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1414 "PCH VGA enabled on transcoder %c, should be disabled\n",
1415 pipe_name(pipe));
1416
1417 val = I915_READ(PCH_LVDS);
1418 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1419 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1420 pipe_name(pipe));
1421
1422 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1425 }
1426
1427 static void _vlv_enable_pll(struct intel_crtc *crtc,
1428 const struct intel_crtc_state *pipe_config)
1429 {
1430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1431 enum pipe pipe = crtc->pipe;
1432
1433 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1434 POSTING_READ(DPLL(pipe));
1435 udelay(150);
1436
1437 if (intel_wait_for_register(dev_priv,
1438 DPLL(pipe),
1439 DPLL_LOCK_VLV,
1440 DPLL_LOCK_VLV,
1441 1))
1442 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1443 }
1444
1445 static void vlv_enable_pll(struct intel_crtc *crtc,
1446 const struct intel_crtc_state *pipe_config)
1447 {
1448 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1449 enum pipe pipe = crtc->pipe;
1450
1451 assert_pipe_disabled(dev_priv, pipe);
1452
1453 /* PLL is protected by panel, make sure we can write it */
1454 assert_panel_unlocked(dev_priv, pipe);
1455
1456 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1457 _vlv_enable_pll(crtc, pipe_config);
1458
1459 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1460 POSTING_READ(DPLL_MD(pipe));
1461 }
1462
1463
1464 static void _chv_enable_pll(struct intel_crtc *crtc,
1465 const struct intel_crtc_state *pipe_config)
1466 {
1467 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1468 enum pipe pipe = crtc->pipe;
1469 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1470 u32 tmp;
1471
1472 mutex_lock(&dev_priv->sb_lock);
1473
1474 /* Enable back the 10bit clock to display controller */
1475 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1476 tmp |= DPIO_DCLKP_EN;
1477 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1478
1479 mutex_unlock(&dev_priv->sb_lock);
1480
1481 /*
1482 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1483 */
1484 udelay(1);
1485
1486 /* Enable PLL */
1487 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1488
1489 /* Check PLL is locked */
1490 if (intel_wait_for_register(dev_priv,
1491 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1492 1))
1493 DRM_ERROR("PLL %d failed to lock\n", pipe);
1494 }
1495
1496 static void chv_enable_pll(struct intel_crtc *crtc,
1497 const struct intel_crtc_state *pipe_config)
1498 {
1499 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1500 enum pipe pipe = crtc->pipe;
1501
1502 assert_pipe_disabled(dev_priv, pipe);
1503
1504 /* PLL is protected by panel, make sure we can write it */
1505 assert_panel_unlocked(dev_priv, pipe);
1506
1507 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1508 _chv_enable_pll(crtc, pipe_config);
1509
1510 if (pipe != PIPE_A) {
1511 /*
1512 * WaPixelRepeatModeFixForC0:chv
1513 *
1514 * DPLLCMD is AWOL. Use chicken bits to propagate
1515 * the value from DPLLBMD to either pipe B or C.
1516 */
1517 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1518 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1519 I915_WRITE(CBR4_VLV, 0);
1520 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1521
1522 /*
1523 * DPLLB VGA mode also seems to cause problems.
1524 * We should always have it disabled.
1525 */
1526 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1527 } else {
1528 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1529 POSTING_READ(DPLL_MD(pipe));
1530 }
1531 }
1532
1533 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1534 {
1535 struct intel_crtc *crtc;
1536 int count = 0;
1537
1538 for_each_intel_crtc(&dev_priv->drm, crtc) {
1539 count += crtc->base.state->active &&
1540 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1541 }
1542
1543 return count;
1544 }
1545
1546 static void i9xx_enable_pll(struct intel_crtc *crtc)
1547 {
1548 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1549 i915_reg_t reg = DPLL(crtc->pipe);
1550 u32 dpll = crtc->config->dpll_hw_state.dpll;
1551
1552 assert_pipe_disabled(dev_priv, crtc->pipe);
1553
1554 /* PLL is protected by panel, make sure we can write it */
1555 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1556 assert_panel_unlocked(dev_priv, crtc->pipe);
1557
1558 /* Enable DVO 2x clock on both PLLs if necessary */
1559 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1560 /*
1561 * It appears to be important that we don't enable this
1562 * for the current pipe before otherwise configuring the
1563 * PLL. No idea how this should be handled if multiple
1564 * DVO outputs are enabled simultaneosly.
1565 */
1566 dpll |= DPLL_DVO_2X_MODE;
1567 I915_WRITE(DPLL(!crtc->pipe),
1568 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1569 }
1570
1571 /*
1572 * Apparently we need to have VGA mode enabled prior to changing
1573 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1574 * dividers, even though the register value does change.
1575 */
1576 I915_WRITE(reg, 0);
1577
1578 I915_WRITE(reg, dpll);
1579
1580 /* Wait for the clocks to stabilize. */
1581 POSTING_READ(reg);
1582 udelay(150);
1583
1584 if (INTEL_GEN(dev_priv) >= 4) {
1585 I915_WRITE(DPLL_MD(crtc->pipe),
1586 crtc->config->dpll_hw_state.dpll_md);
1587 } else {
1588 /* The pixel multiplier can only be updated once the
1589 * DPLL is enabled and the clocks are stable.
1590 *
1591 * So write it again.
1592 */
1593 I915_WRITE(reg, dpll);
1594 }
1595
1596 /* We do this three times for luck */
1597 I915_WRITE(reg, dpll);
1598 POSTING_READ(reg);
1599 udelay(150); /* wait for warmup */
1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150); /* wait for warmup */
1603 I915_WRITE(reg, dpll);
1604 POSTING_READ(reg);
1605 udelay(150); /* wait for warmup */
1606 }
1607
1608 /**
1609 * i9xx_disable_pll - disable a PLL
1610 * @dev_priv: i915 private structure
1611 * @pipe: pipe PLL to disable
1612 *
1613 * Disable the PLL for @pipe, making sure the pipe is off first.
1614 *
1615 * Note! This is for pre-ILK only.
1616 */
1617 static void i9xx_disable_pll(struct intel_crtc *crtc)
1618 {
1619 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1620 enum pipe pipe = crtc->pipe;
1621
1622 /* Disable DVO 2x clock on both PLLs if necessary */
1623 if (IS_I830(dev_priv) &&
1624 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1625 !intel_num_dvo_pipes(dev_priv)) {
1626 I915_WRITE(DPLL(PIPE_B),
1627 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1628 I915_WRITE(DPLL(PIPE_A),
1629 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1630 }
1631
1632 /* Don't disable pipe or pipe PLLs if needed */
1633 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1634 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1635 return;
1636
1637 /* Make sure the pipe isn't still relying on us */
1638 assert_pipe_disabled(dev_priv, pipe);
1639
1640 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1641 POSTING_READ(DPLL(pipe));
1642 }
1643
1644 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1645 {
1646 u32 val;
1647
1648 /* Make sure the pipe isn't still relying on us */
1649 assert_pipe_disabled(dev_priv, pipe);
1650
1651 val = DPLL_INTEGRATED_REF_CLK_VLV |
1652 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1653 if (pipe != PIPE_A)
1654 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1655
1656 I915_WRITE(DPLL(pipe), val);
1657 POSTING_READ(DPLL(pipe));
1658 }
1659
1660 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1661 {
1662 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1663 u32 val;
1664
1665 /* Make sure the pipe isn't still relying on us */
1666 assert_pipe_disabled(dev_priv, pipe);
1667
1668 val = DPLL_SSC_REF_CLK_CHV |
1669 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1670 if (pipe != PIPE_A)
1671 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1672
1673 I915_WRITE(DPLL(pipe), val);
1674 POSTING_READ(DPLL(pipe));
1675
1676 mutex_lock(&dev_priv->sb_lock);
1677
1678 /* Disable 10bit clock to display controller */
1679 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1680 val &= ~DPIO_DCLKP_EN;
1681 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1682
1683 mutex_unlock(&dev_priv->sb_lock);
1684 }
1685
1686 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1687 struct intel_digital_port *dport,
1688 unsigned int expected_mask)
1689 {
1690 u32 port_mask;
1691 i915_reg_t dpll_reg;
1692
1693 switch (dport->port) {
1694 case PORT_B:
1695 port_mask = DPLL_PORTB_READY_MASK;
1696 dpll_reg = DPLL(0);
1697 break;
1698 case PORT_C:
1699 port_mask = DPLL_PORTC_READY_MASK;
1700 dpll_reg = DPLL(0);
1701 expected_mask <<= 4;
1702 break;
1703 case PORT_D:
1704 port_mask = DPLL_PORTD_READY_MASK;
1705 dpll_reg = DPIO_PHY_STATUS;
1706 break;
1707 default:
1708 BUG();
1709 }
1710
1711 if (intel_wait_for_register(dev_priv,
1712 dpll_reg, port_mask, expected_mask,
1713 1000))
1714 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1715 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1716 }
1717
1718 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1719 enum pipe pipe)
1720 {
1721 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1722 pipe);
1723 i915_reg_t reg;
1724 uint32_t val, pipeconf_val;
1725
1726 /* Make sure PCH DPLL is enabled */
1727 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1728
1729 /* FDI must be feeding us bits for PCH ports */
1730 assert_fdi_tx_enabled(dev_priv, pipe);
1731 assert_fdi_rx_enabled(dev_priv, pipe);
1732
1733 if (HAS_PCH_CPT(dev_priv)) {
1734 /* Workaround: Set the timing override bit before enabling the
1735 * pch transcoder. */
1736 reg = TRANS_CHICKEN2(pipe);
1737 val = I915_READ(reg);
1738 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1739 I915_WRITE(reg, val);
1740 }
1741
1742 reg = PCH_TRANSCONF(pipe);
1743 val = I915_READ(reg);
1744 pipeconf_val = I915_READ(PIPECONF(pipe));
1745
1746 if (HAS_PCH_IBX(dev_priv)) {
1747 /*
1748 * Make the BPC in transcoder be consistent with
1749 * that in pipeconf reg. For HDMI we must use 8bpc
1750 * here for both 8bpc and 12bpc.
1751 */
1752 val &= ~PIPECONF_BPC_MASK;
1753 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1754 val |= PIPECONF_8BPC;
1755 else
1756 val |= pipeconf_val & PIPECONF_BPC_MASK;
1757 }
1758
1759 val &= ~TRANS_INTERLACE_MASK;
1760 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1761 if (HAS_PCH_IBX(dev_priv) &&
1762 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1763 val |= TRANS_LEGACY_INTERLACED_ILK;
1764 else
1765 val |= TRANS_INTERLACED;
1766 else
1767 val |= TRANS_PROGRESSIVE;
1768
1769 I915_WRITE(reg, val | TRANS_ENABLE);
1770 if (intel_wait_for_register(dev_priv,
1771 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1772 100))
1773 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1774 }
1775
1776 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1777 enum transcoder cpu_transcoder)
1778 {
1779 u32 val, pipeconf_val;
1780
1781 /* FDI must be feeding us bits for PCH ports */
1782 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1783 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1784
1785 /* Workaround: set timing override bit. */
1786 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1787 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1788 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1789
1790 val = TRANS_ENABLE;
1791 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1792
1793 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1794 PIPECONF_INTERLACED_ILK)
1795 val |= TRANS_INTERLACED;
1796 else
1797 val |= TRANS_PROGRESSIVE;
1798
1799 I915_WRITE(LPT_TRANSCONF, val);
1800 if (intel_wait_for_register(dev_priv,
1801 LPT_TRANSCONF,
1802 TRANS_STATE_ENABLE,
1803 TRANS_STATE_ENABLE,
1804 100))
1805 DRM_ERROR("Failed to enable PCH transcoder\n");
1806 }
1807
1808 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1809 enum pipe pipe)
1810 {
1811 i915_reg_t reg;
1812 uint32_t val;
1813
1814 /* FDI relies on the transcoder */
1815 assert_fdi_tx_disabled(dev_priv, pipe);
1816 assert_fdi_rx_disabled(dev_priv, pipe);
1817
1818 /* Ports must be off as well */
1819 assert_pch_ports_disabled(dev_priv, pipe);
1820
1821 reg = PCH_TRANSCONF(pipe);
1822 val = I915_READ(reg);
1823 val &= ~TRANS_ENABLE;
1824 I915_WRITE(reg, val);
1825 /* wait for PCH transcoder off, transcoder state */
1826 if (intel_wait_for_register(dev_priv,
1827 reg, TRANS_STATE_ENABLE, 0,
1828 50))
1829 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1830
1831 if (HAS_PCH_CPT(dev_priv)) {
1832 /* Workaround: Clear the timing override chicken bit again. */
1833 reg = TRANS_CHICKEN2(pipe);
1834 val = I915_READ(reg);
1835 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1836 I915_WRITE(reg, val);
1837 }
1838 }
1839
1840 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1841 {
1842 u32 val;
1843
1844 val = I915_READ(LPT_TRANSCONF);
1845 val &= ~TRANS_ENABLE;
1846 I915_WRITE(LPT_TRANSCONF, val);
1847 /* wait for PCH transcoder off, transcoder state */
1848 if (intel_wait_for_register(dev_priv,
1849 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1850 50))
1851 DRM_ERROR("Failed to disable PCH transcoder\n");
1852
1853 /* Workaround: clear timing override bit. */
1854 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1855 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1856 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1857 }
1858
1859 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1860 {
1861 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1862
1863 WARN_ON(!crtc->config->has_pch_encoder);
1864
1865 if (HAS_PCH_LPT(dev_priv))
1866 return TRANSCODER_A;
1867 else
1868 return (enum transcoder) crtc->pipe;
1869 }
1870
1871 /**
1872 * intel_enable_pipe - enable a pipe, asserting requirements
1873 * @crtc: crtc responsible for the pipe
1874 *
1875 * Enable @crtc's pipe, making sure that various hardware specific requirements
1876 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1877 */
1878 static void intel_enable_pipe(struct intel_crtc *crtc)
1879 {
1880 struct drm_device *dev = crtc->base.dev;
1881 struct drm_i915_private *dev_priv = to_i915(dev);
1882 enum pipe pipe = crtc->pipe;
1883 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1884 i915_reg_t reg;
1885 u32 val;
1886
1887 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1888
1889 assert_planes_disabled(dev_priv, pipe);
1890 assert_cursor_disabled(dev_priv, pipe);
1891 assert_sprites_disabled(dev_priv, pipe);
1892
1893 /*
1894 * A pipe without a PLL won't actually be able to drive bits from
1895 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1896 * need the check.
1897 */
1898 if (HAS_GMCH_DISPLAY(dev_priv)) {
1899 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1900 assert_dsi_pll_enabled(dev_priv);
1901 else
1902 assert_pll_enabled(dev_priv, pipe);
1903 } else {
1904 if (crtc->config->has_pch_encoder) {
1905 /* if driving the PCH, we need FDI enabled */
1906 assert_fdi_rx_pll_enabled(dev_priv,
1907 (enum pipe) intel_crtc_pch_transcoder(crtc));
1908 assert_fdi_tx_pll_enabled(dev_priv,
1909 (enum pipe) cpu_transcoder);
1910 }
1911 /* FIXME: assert CPU port conditions for SNB+ */
1912 }
1913
1914 reg = PIPECONF(cpu_transcoder);
1915 val = I915_READ(reg);
1916 if (val & PIPECONF_ENABLE) {
1917 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1918 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1919 return;
1920 }
1921
1922 I915_WRITE(reg, val | PIPECONF_ENABLE);
1923 POSTING_READ(reg);
1924
1925 /*
1926 * Until the pipe starts DSL will read as 0, which would cause
1927 * an apparent vblank timestamp jump, which messes up also the
1928 * frame count when it's derived from the timestamps. So let's
1929 * wait for the pipe to start properly before we call
1930 * drm_crtc_vblank_on()
1931 */
1932 if (dev->max_vblank_count == 0 &&
1933 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1934 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1935 }
1936
1937 /**
1938 * intel_disable_pipe - disable a pipe, asserting requirements
1939 * @crtc: crtc whose pipes is to be disabled
1940 *
1941 * Disable the pipe of @crtc, making sure that various hardware
1942 * specific requirements are met, if applicable, e.g. plane
1943 * disabled, panel fitter off, etc.
1944 *
1945 * Will wait until the pipe has shut down before returning.
1946 */
1947 static void intel_disable_pipe(struct intel_crtc *crtc)
1948 {
1949 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1950 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1951 enum pipe pipe = crtc->pipe;
1952 i915_reg_t reg;
1953 u32 val;
1954
1955 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1956
1957 /*
1958 * Make sure planes won't keep trying to pump pixels to us,
1959 * or we might hang the display.
1960 */
1961 assert_planes_disabled(dev_priv, pipe);
1962 assert_cursor_disabled(dev_priv, pipe);
1963 assert_sprites_disabled(dev_priv, pipe);
1964
1965 reg = PIPECONF(cpu_transcoder);
1966 val = I915_READ(reg);
1967 if ((val & PIPECONF_ENABLE) == 0)
1968 return;
1969
1970 /*
1971 * Double wide has implications for planes
1972 * so best keep it disabled when not needed.
1973 */
1974 if (crtc->config->double_wide)
1975 val &= ~PIPECONF_DOUBLE_WIDE;
1976
1977 /* Don't disable pipe or pipe PLLs if needed */
1978 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1979 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1980 val &= ~PIPECONF_ENABLE;
1981
1982 I915_WRITE(reg, val);
1983 if ((val & PIPECONF_ENABLE) == 0)
1984 intel_wait_for_pipe_off(crtc);
1985 }
1986
1987 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1988 {
1989 return IS_GEN2(dev_priv) ? 2048 : 4096;
1990 }
1991
1992 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
1993 uint64_t fb_modifier, unsigned int cpp)
1994 {
1995 switch (fb_modifier) {
1996 case DRM_FORMAT_MOD_NONE:
1997 return cpp;
1998 case I915_FORMAT_MOD_X_TILED:
1999 if (IS_GEN2(dev_priv))
2000 return 128;
2001 else
2002 return 512;
2003 case I915_FORMAT_MOD_Y_TILED:
2004 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2005 return 128;
2006 else
2007 return 512;
2008 case I915_FORMAT_MOD_Yf_TILED:
2009 switch (cpp) {
2010 case 1:
2011 return 64;
2012 case 2:
2013 case 4:
2014 return 128;
2015 case 8:
2016 case 16:
2017 return 256;
2018 default:
2019 MISSING_CASE(cpp);
2020 return cpp;
2021 }
2022 break;
2023 default:
2024 MISSING_CASE(fb_modifier);
2025 return cpp;
2026 }
2027 }
2028
2029 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2030 uint64_t fb_modifier, unsigned int cpp)
2031 {
2032 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2033 return 1;
2034 else
2035 return intel_tile_size(dev_priv) /
2036 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2037 }
2038
2039 /* Return the tile dimensions in pixel units */
2040 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2041 unsigned int *tile_width,
2042 unsigned int *tile_height,
2043 uint64_t fb_modifier,
2044 unsigned int cpp)
2045 {
2046 unsigned int tile_width_bytes =
2047 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2048
2049 *tile_width = tile_width_bytes / cpp;
2050 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2051 }
2052
2053 unsigned int
2054 intel_fb_align_height(struct drm_i915_private *dev_priv,
2055 unsigned int height,
2056 uint32_t pixel_format,
2057 uint64_t fb_modifier)
2058 {
2059 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2060 unsigned int tile_height = intel_tile_height(dev_priv, fb_modifier, cpp);
2061
2062 return ALIGN(height, tile_height);
2063 }
2064
2065 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2066 {
2067 unsigned int size = 0;
2068 int i;
2069
2070 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2071 size += rot_info->plane[i].width * rot_info->plane[i].height;
2072
2073 return size;
2074 }
2075
2076 static void
2077 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2078 const struct drm_framebuffer *fb,
2079 unsigned int rotation)
2080 {
2081 view->type = I915_GGTT_VIEW_NORMAL;
2082 if (drm_rotation_90_or_270(rotation)) {
2083 view->type = I915_GGTT_VIEW_ROTATED;
2084 view->rotated = to_intel_framebuffer(fb)->rot_info;
2085 }
2086 }
2087
2088 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2089 {
2090 if (INTEL_INFO(dev_priv)->gen >= 9)
2091 return 256 * 1024;
2092 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2093 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2094 return 128 * 1024;
2095 else if (INTEL_INFO(dev_priv)->gen >= 4)
2096 return 4 * 1024;
2097 else
2098 return 0;
2099 }
2100
2101 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2102 uint64_t fb_modifier)
2103 {
2104 switch (fb_modifier) {
2105 case DRM_FORMAT_MOD_NONE:
2106 return intel_linear_alignment(dev_priv);
2107 case I915_FORMAT_MOD_X_TILED:
2108 if (INTEL_INFO(dev_priv)->gen >= 9)
2109 return 256 * 1024;
2110 return 0;
2111 case I915_FORMAT_MOD_Y_TILED:
2112 case I915_FORMAT_MOD_Yf_TILED:
2113 return 1 * 1024 * 1024;
2114 default:
2115 MISSING_CASE(fb_modifier);
2116 return 0;
2117 }
2118 }
2119
2120 struct i915_vma *
2121 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2122 {
2123 struct drm_device *dev = fb->dev;
2124 struct drm_i915_private *dev_priv = to_i915(dev);
2125 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2126 struct i915_ggtt_view view;
2127 struct i915_vma *vma;
2128 u32 alignment;
2129
2130 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2131
2132 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2133
2134 intel_fill_fb_ggtt_view(&view, fb, rotation);
2135
2136 /* Note that the w/a also requires 64 PTE of padding following the
2137 * bo. We currently fill all unused PTE with the shadow page and so
2138 * we should always have valid PTE following the scanout preventing
2139 * the VT-d warning.
2140 */
2141 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2142 alignment = 256 * 1024;
2143
2144 /*
2145 * Global gtt pte registers are special registers which actually forward
2146 * writes to a chunk of system memory. Which means that there is no risk
2147 * that the register values disappear as soon as we call
2148 * intel_runtime_pm_put(), so it is correct to wrap only the
2149 * pin/unpin/fence and not more.
2150 */
2151 intel_runtime_pm_get(dev_priv);
2152
2153 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2154 if (IS_ERR(vma))
2155 goto err;
2156
2157 if (i915_vma_is_map_and_fenceable(vma)) {
2158 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2159 * fence, whereas 965+ only requires a fence if using
2160 * framebuffer compression. For simplicity, we always, when
2161 * possible, install a fence as the cost is not that onerous.
2162 *
2163 * If we fail to fence the tiled scanout, then either the
2164 * modeset will reject the change (which is highly unlikely as
2165 * the affected systems, all but one, do not have unmappable
2166 * space) or we will not be able to enable full powersaving
2167 * techniques (also likely not to apply due to various limits
2168 * FBC and the like impose on the size of the buffer, which
2169 * presumably we violated anyway with this unmappable buffer).
2170 * Anyway, it is presumably better to stumble onwards with
2171 * something and try to run the system in a "less than optimal"
2172 * mode that matches the user configuration.
2173 */
2174 if (i915_vma_get_fence(vma) == 0)
2175 i915_vma_pin_fence(vma);
2176 }
2177
2178 i915_vma_get(vma);
2179 err:
2180 intel_runtime_pm_put(dev_priv);
2181 return vma;
2182 }
2183
2184 void intel_unpin_fb_vma(struct i915_vma *vma)
2185 {
2186 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2187
2188 i915_vma_unpin_fence(vma);
2189 i915_gem_object_unpin_from_display_plane(vma);
2190 i915_vma_put(vma);
2191 }
2192
2193 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2194 unsigned int rotation)
2195 {
2196 if (drm_rotation_90_or_270(rotation))
2197 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2198 else
2199 return fb->pitches[plane];
2200 }
2201
2202 /*
2203 * Convert the x/y offsets into a linear offset.
2204 * Only valid with 0/180 degree rotation, which is fine since linear
2205 * offset is only used with linear buffers on pre-hsw and tiled buffers
2206 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2207 */
2208 u32 intel_fb_xy_to_linear(int x, int y,
2209 const struct intel_plane_state *state,
2210 int plane)
2211 {
2212 const struct drm_framebuffer *fb = state->base.fb;
2213 unsigned int cpp = fb->format->cpp[plane];
2214 unsigned int pitch = fb->pitches[plane];
2215
2216 return y * pitch + x * cpp;
2217 }
2218
2219 /*
2220 * Add the x/y offsets derived from fb->offsets[] to the user
2221 * specified plane src x/y offsets. The resulting x/y offsets
2222 * specify the start of scanout from the beginning of the gtt mapping.
2223 */
2224 void intel_add_fb_offsets(int *x, int *y,
2225 const struct intel_plane_state *state,
2226 int plane)
2227
2228 {
2229 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2230 unsigned int rotation = state->base.rotation;
2231
2232 if (drm_rotation_90_or_270(rotation)) {
2233 *x += intel_fb->rotated[plane].x;
2234 *y += intel_fb->rotated[plane].y;
2235 } else {
2236 *x += intel_fb->normal[plane].x;
2237 *y += intel_fb->normal[plane].y;
2238 }
2239 }
2240
2241 /*
2242 * Input tile dimensions and pitch must already be
2243 * rotated to match x and y, and in pixel units.
2244 */
2245 static u32 _intel_adjust_tile_offset(int *x, int *y,
2246 unsigned int tile_width,
2247 unsigned int tile_height,
2248 unsigned int tile_size,
2249 unsigned int pitch_tiles,
2250 u32 old_offset,
2251 u32 new_offset)
2252 {
2253 unsigned int pitch_pixels = pitch_tiles * tile_width;
2254 unsigned int tiles;
2255
2256 WARN_ON(old_offset & (tile_size - 1));
2257 WARN_ON(new_offset & (tile_size - 1));
2258 WARN_ON(new_offset > old_offset);
2259
2260 tiles = (old_offset - new_offset) / tile_size;
2261
2262 *y += tiles / pitch_tiles * tile_height;
2263 *x += tiles % pitch_tiles * tile_width;
2264
2265 /* minimize x in case it got needlessly big */
2266 *y += *x / pitch_pixels * tile_height;
2267 *x %= pitch_pixels;
2268
2269 return new_offset;
2270 }
2271
2272 /*
2273 * Adjust the tile offset by moving the difference into
2274 * the x/y offsets.
2275 */
2276 static u32 intel_adjust_tile_offset(int *x, int *y,
2277 const struct intel_plane_state *state, int plane,
2278 u32 old_offset, u32 new_offset)
2279 {
2280 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2281 const struct drm_framebuffer *fb = state->base.fb;
2282 unsigned int cpp = fb->format->cpp[plane];
2283 unsigned int rotation = state->base.rotation;
2284 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2285
2286 WARN_ON(new_offset > old_offset);
2287
2288 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2289 unsigned int tile_size, tile_width, tile_height;
2290 unsigned int pitch_tiles;
2291
2292 tile_size = intel_tile_size(dev_priv);
2293 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2294 fb->modifier, cpp);
2295
2296 if (drm_rotation_90_or_270(rotation)) {
2297 pitch_tiles = pitch / tile_height;
2298 swap(tile_width, tile_height);
2299 } else {
2300 pitch_tiles = pitch / (tile_width * cpp);
2301 }
2302
2303 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2304 tile_size, pitch_tiles,
2305 old_offset, new_offset);
2306 } else {
2307 old_offset += *y * pitch + *x * cpp;
2308
2309 *y = (old_offset - new_offset) / pitch;
2310 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2311 }
2312
2313 return new_offset;
2314 }
2315
2316 /*
2317 * Computes the linear offset to the base tile and adjusts
2318 * x, y. bytes per pixel is assumed to be a power-of-two.
2319 *
2320 * In the 90/270 rotated case, x and y are assumed
2321 * to be already rotated to match the rotated GTT view, and
2322 * pitch is the tile_height aligned framebuffer height.
2323 *
2324 * This function is used when computing the derived information
2325 * under intel_framebuffer, so using any of that information
2326 * here is not allowed. Anything under drm_framebuffer can be
2327 * used. This is why the user has to pass in the pitch since it
2328 * is specified in the rotated orientation.
2329 */
2330 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2331 int *x, int *y,
2332 const struct drm_framebuffer *fb, int plane,
2333 unsigned int pitch,
2334 unsigned int rotation,
2335 u32 alignment)
2336 {
2337 uint64_t fb_modifier = fb->modifier;
2338 unsigned int cpp = fb->format->cpp[plane];
2339 u32 offset, offset_aligned;
2340
2341 if (alignment)
2342 alignment--;
2343
2344 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2345 unsigned int tile_size, tile_width, tile_height;
2346 unsigned int tile_rows, tiles, pitch_tiles;
2347
2348 tile_size = intel_tile_size(dev_priv);
2349 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2350 fb_modifier, cpp);
2351
2352 if (drm_rotation_90_or_270(rotation)) {
2353 pitch_tiles = pitch / tile_height;
2354 swap(tile_width, tile_height);
2355 } else {
2356 pitch_tiles = pitch / (tile_width * cpp);
2357 }
2358
2359 tile_rows = *y / tile_height;
2360 *y %= tile_height;
2361
2362 tiles = *x / tile_width;
2363 *x %= tile_width;
2364
2365 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2366 offset_aligned = offset & ~alignment;
2367
2368 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2369 tile_size, pitch_tiles,
2370 offset, offset_aligned);
2371 } else {
2372 offset = *y * pitch + *x * cpp;
2373 offset_aligned = offset & ~alignment;
2374
2375 *y = (offset & alignment) / pitch;
2376 *x = ((offset & alignment) - *y * pitch) / cpp;
2377 }
2378
2379 return offset_aligned;
2380 }
2381
2382 u32 intel_compute_tile_offset(int *x, int *y,
2383 const struct intel_plane_state *state,
2384 int plane)
2385 {
2386 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2387 const struct drm_framebuffer *fb = state->base.fb;
2388 unsigned int rotation = state->base.rotation;
2389 int pitch = intel_fb_pitch(fb, plane, rotation);
2390 u32 alignment;
2391
2392 /* AUX_DIST needs only 4K alignment */
2393 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2394 alignment = 4096;
2395 else
2396 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2397
2398 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2399 rotation, alignment);
2400 }
2401
2402 /* Convert the fb->offset[] linear offset into x/y offsets */
2403 static void intel_fb_offset_to_xy(int *x, int *y,
2404 const struct drm_framebuffer *fb, int plane)
2405 {
2406 unsigned int cpp = fb->format->cpp[plane];
2407 unsigned int pitch = fb->pitches[plane];
2408 u32 linear_offset = fb->offsets[plane];
2409
2410 *y = linear_offset / pitch;
2411 *x = linear_offset % pitch / cpp;
2412 }
2413
2414 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2415 {
2416 switch (fb_modifier) {
2417 case I915_FORMAT_MOD_X_TILED:
2418 return I915_TILING_X;
2419 case I915_FORMAT_MOD_Y_TILED:
2420 return I915_TILING_Y;
2421 default:
2422 return I915_TILING_NONE;
2423 }
2424 }
2425
2426 static int
2427 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2428 struct drm_framebuffer *fb)
2429 {
2430 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2431 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2432 u32 gtt_offset_rotated = 0;
2433 unsigned int max_size = 0;
2434 int i, num_planes = fb->format->num_planes;
2435 unsigned int tile_size = intel_tile_size(dev_priv);
2436
2437 for (i = 0; i < num_planes; i++) {
2438 unsigned int width, height;
2439 unsigned int cpp, size;
2440 u32 offset;
2441 int x, y;
2442
2443 cpp = fb->format->cpp[i];
2444 width = drm_framebuffer_plane_width(fb->width, fb, i);
2445 height = drm_framebuffer_plane_height(fb->height, fb, i);
2446
2447 intel_fb_offset_to_xy(&x, &y, fb, i);
2448
2449 /*
2450 * The fence (if used) is aligned to the start of the object
2451 * so having the framebuffer wrap around across the edge of the
2452 * fenced region doesn't really work. We have no API to configure
2453 * the fence start offset within the object (nor could we probably
2454 * on gen2/3). So it's just easier if we just require that the
2455 * fb layout agrees with the fence layout. We already check that the
2456 * fb stride matches the fence stride elsewhere.
2457 */
2458 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2459 (x + width) * cpp > fb->pitches[i]) {
2460 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2461 i, fb->offsets[i]);
2462 return -EINVAL;
2463 }
2464
2465 /*
2466 * First pixel of the framebuffer from
2467 * the start of the normal gtt mapping.
2468 */
2469 intel_fb->normal[i].x = x;
2470 intel_fb->normal[i].y = y;
2471
2472 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2473 fb, 0, fb->pitches[i],
2474 DRM_ROTATE_0, tile_size);
2475 offset /= tile_size;
2476
2477 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2478 unsigned int tile_width, tile_height;
2479 unsigned int pitch_tiles;
2480 struct drm_rect r;
2481
2482 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2483 fb->modifier, cpp);
2484
2485 rot_info->plane[i].offset = offset;
2486 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2487 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2488 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2489
2490 intel_fb->rotated[i].pitch =
2491 rot_info->plane[i].height * tile_height;
2492
2493 /* how many tiles does this plane need */
2494 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2495 /*
2496 * If the plane isn't horizontally tile aligned,
2497 * we need one more tile.
2498 */
2499 if (x != 0)
2500 size++;
2501
2502 /* rotate the x/y offsets to match the GTT view */
2503 r.x1 = x;
2504 r.y1 = y;
2505 r.x2 = x + width;
2506 r.y2 = y + height;
2507 drm_rect_rotate(&r,
2508 rot_info->plane[i].width * tile_width,
2509 rot_info->plane[i].height * tile_height,
2510 DRM_ROTATE_270);
2511 x = r.x1;
2512 y = r.y1;
2513
2514 /* rotate the tile dimensions to match the GTT view */
2515 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2516 swap(tile_width, tile_height);
2517
2518 /*
2519 * We only keep the x/y offsets, so push all of the
2520 * gtt offset into the x/y offsets.
2521 */
2522 _intel_adjust_tile_offset(&x, &y,
2523 tile_width, tile_height,
2524 tile_size, pitch_tiles,
2525 gtt_offset_rotated * tile_size, 0);
2526
2527 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2528
2529 /*
2530 * First pixel of the framebuffer from
2531 * the start of the rotated gtt mapping.
2532 */
2533 intel_fb->rotated[i].x = x;
2534 intel_fb->rotated[i].y = y;
2535 } else {
2536 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2537 x * cpp, tile_size);
2538 }
2539
2540 /* how many tiles in total needed in the bo */
2541 max_size = max(max_size, offset + size);
2542 }
2543
2544 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2545 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2546 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2547 return -EINVAL;
2548 }
2549
2550 return 0;
2551 }
2552
2553 static int i9xx_format_to_fourcc(int format)
2554 {
2555 switch (format) {
2556 case DISPPLANE_8BPP:
2557 return DRM_FORMAT_C8;
2558 case DISPPLANE_BGRX555:
2559 return DRM_FORMAT_XRGB1555;
2560 case DISPPLANE_BGRX565:
2561 return DRM_FORMAT_RGB565;
2562 default:
2563 case DISPPLANE_BGRX888:
2564 return DRM_FORMAT_XRGB8888;
2565 case DISPPLANE_RGBX888:
2566 return DRM_FORMAT_XBGR8888;
2567 case DISPPLANE_BGRX101010:
2568 return DRM_FORMAT_XRGB2101010;
2569 case DISPPLANE_RGBX101010:
2570 return DRM_FORMAT_XBGR2101010;
2571 }
2572 }
2573
2574 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2575 {
2576 switch (format) {
2577 case PLANE_CTL_FORMAT_RGB_565:
2578 return DRM_FORMAT_RGB565;
2579 default:
2580 case PLANE_CTL_FORMAT_XRGB_8888:
2581 if (rgb_order) {
2582 if (alpha)
2583 return DRM_FORMAT_ABGR8888;
2584 else
2585 return DRM_FORMAT_XBGR8888;
2586 } else {
2587 if (alpha)
2588 return DRM_FORMAT_ARGB8888;
2589 else
2590 return DRM_FORMAT_XRGB8888;
2591 }
2592 case PLANE_CTL_FORMAT_XRGB_2101010:
2593 if (rgb_order)
2594 return DRM_FORMAT_XBGR2101010;
2595 else
2596 return DRM_FORMAT_XRGB2101010;
2597 }
2598 }
2599
2600 static bool
2601 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2602 struct intel_initial_plane_config *plane_config)
2603 {
2604 struct drm_device *dev = crtc->base.dev;
2605 struct drm_i915_private *dev_priv = to_i915(dev);
2606 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2607 struct drm_i915_gem_object *obj = NULL;
2608 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2609 struct drm_framebuffer *fb = &plane_config->fb->base;
2610 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2611 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2612 PAGE_SIZE);
2613
2614 size_aligned -= base_aligned;
2615
2616 if (plane_config->size == 0)
2617 return false;
2618
2619 /* If the FB is too big, just don't use it since fbdev is not very
2620 * important and we should probably use that space with FBC or other
2621 * features. */
2622 if (size_aligned * 2 > ggtt->stolen_usable_size)
2623 return false;
2624
2625 mutex_lock(&dev->struct_mutex);
2626 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2627 base_aligned,
2628 base_aligned,
2629 size_aligned);
2630 mutex_unlock(&dev->struct_mutex);
2631 if (!obj)
2632 return false;
2633
2634 if (plane_config->tiling == I915_TILING_X)
2635 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2636
2637 mode_cmd.pixel_format = fb->format->format;
2638 mode_cmd.width = fb->width;
2639 mode_cmd.height = fb->height;
2640 mode_cmd.pitches[0] = fb->pitches[0];
2641 mode_cmd.modifier[0] = fb->modifier;
2642 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2643
2644 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2645 DRM_DEBUG_KMS("intel fb init failed\n");
2646 goto out_unref_obj;
2647 }
2648
2649
2650 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2651 return true;
2652
2653 out_unref_obj:
2654 i915_gem_object_put(obj);
2655 return false;
2656 }
2657
2658 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2659 static void
2660 update_state_fb(struct drm_plane *plane)
2661 {
2662 if (plane->fb == plane->state->fb)
2663 return;
2664
2665 if (plane->state->fb)
2666 drm_framebuffer_unreference(plane->state->fb);
2667 plane->state->fb = plane->fb;
2668 if (plane->state->fb)
2669 drm_framebuffer_reference(plane->state->fb);
2670 }
2671
2672 static void
2673 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2674 struct intel_initial_plane_config *plane_config)
2675 {
2676 struct drm_device *dev = intel_crtc->base.dev;
2677 struct drm_i915_private *dev_priv = to_i915(dev);
2678 struct drm_crtc *c;
2679 struct drm_i915_gem_object *obj;
2680 struct drm_plane *primary = intel_crtc->base.primary;
2681 struct drm_plane_state *plane_state = primary->state;
2682 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2683 struct intel_plane *intel_plane = to_intel_plane(primary);
2684 struct intel_plane_state *intel_state =
2685 to_intel_plane_state(plane_state);
2686 struct drm_framebuffer *fb;
2687
2688 if (!plane_config->fb)
2689 return;
2690
2691 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2692 fb = &plane_config->fb->base;
2693 goto valid_fb;
2694 }
2695
2696 kfree(plane_config->fb);
2697
2698 /*
2699 * Failed to alloc the obj, check to see if we should share
2700 * an fb with another CRTC instead
2701 */
2702 for_each_crtc(dev, c) {
2703 struct intel_plane_state *state;
2704
2705 if (c == &intel_crtc->base)
2706 continue;
2707
2708 if (!to_intel_crtc(c)->active)
2709 continue;
2710
2711 state = to_intel_plane_state(c->primary->state);
2712 if (!state->vma)
2713 continue;
2714
2715 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2716 fb = c->primary->fb;
2717 drm_framebuffer_reference(fb);
2718 goto valid_fb;
2719 }
2720 }
2721
2722 /*
2723 * We've failed to reconstruct the BIOS FB. Current display state
2724 * indicates that the primary plane is visible, but has a NULL FB,
2725 * which will lead to problems later if we don't fix it up. The
2726 * simplest solution is to just disable the primary plane now and
2727 * pretend the BIOS never had it enabled.
2728 */
2729 plane_state->visible = false;
2730 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2731 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2732 intel_plane->disable_plane(primary, &intel_crtc->base);
2733
2734 return;
2735
2736 valid_fb:
2737 mutex_lock(&dev->struct_mutex);
2738 intel_state->vma =
2739 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2740 mutex_unlock(&dev->struct_mutex);
2741 if (IS_ERR(intel_state->vma)) {
2742 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2743 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2744
2745 intel_state->vma = NULL;
2746 drm_framebuffer_unreference(fb);
2747 return;
2748 }
2749
2750 plane_state->src_x = 0;
2751 plane_state->src_y = 0;
2752 plane_state->src_w = fb->width << 16;
2753 plane_state->src_h = fb->height << 16;
2754
2755 plane_state->crtc_x = 0;
2756 plane_state->crtc_y = 0;
2757 plane_state->crtc_w = fb->width;
2758 plane_state->crtc_h = fb->height;
2759
2760 intel_state->base.src = drm_plane_state_src(plane_state);
2761 intel_state->base.dst = drm_plane_state_dest(plane_state);
2762
2763 obj = intel_fb_obj(fb);
2764 if (i915_gem_object_is_tiled(obj))
2765 dev_priv->preserve_bios_swizzle = true;
2766
2767 drm_framebuffer_reference(fb);
2768 primary->fb = primary->state->fb = fb;
2769 primary->crtc = primary->state->crtc = &intel_crtc->base;
2770 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2771 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2772 &obj->frontbuffer_bits);
2773 }
2774
2775 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2776 unsigned int rotation)
2777 {
2778 int cpp = fb->format->cpp[plane];
2779
2780 switch (fb->modifier) {
2781 case DRM_FORMAT_MOD_NONE:
2782 case I915_FORMAT_MOD_X_TILED:
2783 switch (cpp) {
2784 case 8:
2785 return 4096;
2786 case 4:
2787 case 2:
2788 case 1:
2789 return 8192;
2790 default:
2791 MISSING_CASE(cpp);
2792 break;
2793 }
2794 break;
2795 case I915_FORMAT_MOD_Y_TILED:
2796 case I915_FORMAT_MOD_Yf_TILED:
2797 switch (cpp) {
2798 case 8:
2799 return 2048;
2800 case 4:
2801 return 4096;
2802 case 2:
2803 case 1:
2804 return 8192;
2805 default:
2806 MISSING_CASE(cpp);
2807 break;
2808 }
2809 break;
2810 default:
2811 MISSING_CASE(fb->modifier);
2812 }
2813
2814 return 2048;
2815 }
2816
2817 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2818 {
2819 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2820 const struct drm_framebuffer *fb = plane_state->base.fb;
2821 unsigned int rotation = plane_state->base.rotation;
2822 int x = plane_state->base.src.x1 >> 16;
2823 int y = plane_state->base.src.y1 >> 16;
2824 int w = drm_rect_width(&plane_state->base.src) >> 16;
2825 int h = drm_rect_height(&plane_state->base.src) >> 16;
2826 int max_width = skl_max_plane_width(fb, 0, rotation);
2827 int max_height = 4096;
2828 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2829
2830 if (w > max_width || h > max_height) {
2831 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2832 w, h, max_width, max_height);
2833 return -EINVAL;
2834 }
2835
2836 intel_add_fb_offsets(&x, &y, plane_state, 0);
2837 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2838
2839 alignment = intel_surf_alignment(dev_priv, fb->modifier);
2840
2841 /*
2842 * AUX surface offset is specified as the distance from the
2843 * main surface offset, and it must be non-negative. Make
2844 * sure that is what we will get.
2845 */
2846 if (offset > aux_offset)
2847 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2848 offset, aux_offset & ~(alignment - 1));
2849
2850 /*
2851 * When using an X-tiled surface, the plane blows up
2852 * if the x offset + width exceed the stride.
2853 *
2854 * TODO: linear and Y-tiled seem fine, Yf untested,
2855 */
2856 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2857 int cpp = fb->format->cpp[0];
2858
2859 while ((x + w) * cpp > fb->pitches[0]) {
2860 if (offset == 0) {
2861 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2862 return -EINVAL;
2863 }
2864
2865 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2866 offset, offset - alignment);
2867 }
2868 }
2869
2870 plane_state->main.offset = offset;
2871 plane_state->main.x = x;
2872 plane_state->main.y = y;
2873
2874 return 0;
2875 }
2876
2877 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2878 {
2879 const struct drm_framebuffer *fb = plane_state->base.fb;
2880 unsigned int rotation = plane_state->base.rotation;
2881 int max_width = skl_max_plane_width(fb, 1, rotation);
2882 int max_height = 4096;
2883 int x = plane_state->base.src.x1 >> 17;
2884 int y = plane_state->base.src.y1 >> 17;
2885 int w = drm_rect_width(&plane_state->base.src) >> 17;
2886 int h = drm_rect_height(&plane_state->base.src) >> 17;
2887 u32 offset;
2888
2889 intel_add_fb_offsets(&x, &y, plane_state, 1);
2890 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2891
2892 /* FIXME not quite sure how/if these apply to the chroma plane */
2893 if (w > max_width || h > max_height) {
2894 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2895 w, h, max_width, max_height);
2896 return -EINVAL;
2897 }
2898
2899 plane_state->aux.offset = offset;
2900 plane_state->aux.x = x;
2901 plane_state->aux.y = y;
2902
2903 return 0;
2904 }
2905
2906 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2907 {
2908 const struct drm_framebuffer *fb = plane_state->base.fb;
2909 unsigned int rotation = plane_state->base.rotation;
2910 int ret;
2911
2912 if (!plane_state->base.visible)
2913 return 0;
2914
2915 /* Rotate src coordinates to match rotated GTT view */
2916 if (drm_rotation_90_or_270(rotation))
2917 drm_rect_rotate(&plane_state->base.src,
2918 fb->width << 16, fb->height << 16,
2919 DRM_ROTATE_270);
2920
2921 /*
2922 * Handle the AUX surface first since
2923 * the main surface setup depends on it.
2924 */
2925 if (fb->format->format == DRM_FORMAT_NV12) {
2926 ret = skl_check_nv12_aux_surface(plane_state);
2927 if (ret)
2928 return ret;
2929 } else {
2930 plane_state->aux.offset = ~0xfff;
2931 plane_state->aux.x = 0;
2932 plane_state->aux.y = 0;
2933 }
2934
2935 ret = skl_check_main_surface(plane_state);
2936 if (ret)
2937 return ret;
2938
2939 return 0;
2940 }
2941
2942 static void i9xx_update_primary_plane(struct drm_plane *primary,
2943 const struct intel_crtc_state *crtc_state,
2944 const struct intel_plane_state *plane_state)
2945 {
2946 struct drm_i915_private *dev_priv = to_i915(primary->dev);
2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2948 struct drm_framebuffer *fb = plane_state->base.fb;
2949 int plane = intel_crtc->plane;
2950 u32 linear_offset;
2951 u32 dspcntr;
2952 i915_reg_t reg = DSPCNTR(plane);
2953 unsigned int rotation = plane_state->base.rotation;
2954 int x = plane_state->base.src.x1 >> 16;
2955 int y = plane_state->base.src.y1 >> 16;
2956
2957 dspcntr = DISPPLANE_GAMMA_ENABLE;
2958
2959 dspcntr |= DISPLAY_PLANE_ENABLE;
2960
2961 if (INTEL_GEN(dev_priv) < 4) {
2962 if (intel_crtc->pipe == PIPE_B)
2963 dspcntr |= DISPPLANE_SEL_PIPE_B;
2964
2965 /* pipesrc and dspsize control the size that is scaled from,
2966 * which should always be the user's requested size.
2967 */
2968 I915_WRITE(DSPSIZE(plane),
2969 ((crtc_state->pipe_src_h - 1) << 16) |
2970 (crtc_state->pipe_src_w - 1));
2971 I915_WRITE(DSPPOS(plane), 0);
2972 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
2973 I915_WRITE(PRIMSIZE(plane),
2974 ((crtc_state->pipe_src_h - 1) << 16) |
2975 (crtc_state->pipe_src_w - 1));
2976 I915_WRITE(PRIMPOS(plane), 0);
2977 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2978 }
2979
2980 switch (fb->format->format) {
2981 case DRM_FORMAT_C8:
2982 dspcntr |= DISPPLANE_8BPP;
2983 break;
2984 case DRM_FORMAT_XRGB1555:
2985 dspcntr |= DISPPLANE_BGRX555;
2986 break;
2987 case DRM_FORMAT_RGB565:
2988 dspcntr |= DISPPLANE_BGRX565;
2989 break;
2990 case DRM_FORMAT_XRGB8888:
2991 dspcntr |= DISPPLANE_BGRX888;
2992 break;
2993 case DRM_FORMAT_XBGR8888:
2994 dspcntr |= DISPPLANE_RGBX888;
2995 break;
2996 case DRM_FORMAT_XRGB2101010:
2997 dspcntr |= DISPPLANE_BGRX101010;
2998 break;
2999 case DRM_FORMAT_XBGR2101010:
3000 dspcntr |= DISPPLANE_RGBX101010;
3001 break;
3002 default:
3003 BUG();
3004 }
3005
3006 if (INTEL_GEN(dev_priv) >= 4 &&
3007 fb->modifier == I915_FORMAT_MOD_X_TILED)
3008 dspcntr |= DISPPLANE_TILED;
3009
3010 if (rotation & DRM_ROTATE_180)
3011 dspcntr |= DISPPLANE_ROTATE_180;
3012
3013 if (rotation & DRM_REFLECT_X)
3014 dspcntr |= DISPPLANE_MIRROR;
3015
3016 if (IS_G4X(dev_priv))
3017 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3018
3019 intel_add_fb_offsets(&x, &y, plane_state, 0);
3020
3021 if (INTEL_GEN(dev_priv) >= 4)
3022 intel_crtc->dspaddr_offset =
3023 intel_compute_tile_offset(&x, &y, plane_state, 0);
3024
3025 if (rotation & DRM_ROTATE_180) {
3026 x += crtc_state->pipe_src_w - 1;
3027 y += crtc_state->pipe_src_h - 1;
3028 } else if (rotation & DRM_REFLECT_X) {
3029 x += crtc_state->pipe_src_w - 1;
3030 }
3031
3032 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3033
3034 if (INTEL_GEN(dev_priv) < 4)
3035 intel_crtc->dspaddr_offset = linear_offset;
3036
3037 intel_crtc->adjusted_x = x;
3038 intel_crtc->adjusted_y = y;
3039
3040 I915_WRITE(reg, dspcntr);
3041
3042 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3043 if (INTEL_GEN(dev_priv) >= 4) {
3044 I915_WRITE(DSPSURF(plane),
3045 intel_plane_ggtt_offset(plane_state) +
3046 intel_crtc->dspaddr_offset);
3047 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3048 I915_WRITE(DSPLINOFF(plane), linear_offset);
3049 } else {
3050 I915_WRITE(DSPADDR(plane),
3051 intel_plane_ggtt_offset(plane_state) +
3052 intel_crtc->dspaddr_offset);
3053 }
3054 POSTING_READ(reg);
3055 }
3056
3057 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3058 struct drm_crtc *crtc)
3059 {
3060 struct drm_device *dev = crtc->dev;
3061 struct drm_i915_private *dev_priv = to_i915(dev);
3062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3063 int plane = intel_crtc->plane;
3064
3065 I915_WRITE(DSPCNTR(plane), 0);
3066 if (INTEL_INFO(dev_priv)->gen >= 4)
3067 I915_WRITE(DSPSURF(plane), 0);
3068 else
3069 I915_WRITE(DSPADDR(plane), 0);
3070 POSTING_READ(DSPCNTR(plane));
3071 }
3072
3073 static void ironlake_update_primary_plane(struct drm_plane *primary,
3074 const struct intel_crtc_state *crtc_state,
3075 const struct intel_plane_state *plane_state)
3076 {
3077 struct drm_device *dev = primary->dev;
3078 struct drm_i915_private *dev_priv = to_i915(dev);
3079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3080 struct drm_framebuffer *fb = plane_state->base.fb;
3081 int plane = intel_crtc->plane;
3082 u32 linear_offset;
3083 u32 dspcntr;
3084 i915_reg_t reg = DSPCNTR(plane);
3085 unsigned int rotation = plane_state->base.rotation;
3086 int x = plane_state->base.src.x1 >> 16;
3087 int y = plane_state->base.src.y1 >> 16;
3088
3089 dspcntr = DISPPLANE_GAMMA_ENABLE;
3090 dspcntr |= DISPLAY_PLANE_ENABLE;
3091
3092 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3093 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3094
3095 switch (fb->format->format) {
3096 case DRM_FORMAT_C8:
3097 dspcntr |= DISPPLANE_8BPP;
3098 break;
3099 case DRM_FORMAT_RGB565:
3100 dspcntr |= DISPPLANE_BGRX565;
3101 break;
3102 case DRM_FORMAT_XRGB8888:
3103 dspcntr |= DISPPLANE_BGRX888;
3104 break;
3105 case DRM_FORMAT_XBGR8888:
3106 dspcntr |= DISPPLANE_RGBX888;
3107 break;
3108 case DRM_FORMAT_XRGB2101010:
3109 dspcntr |= DISPPLANE_BGRX101010;
3110 break;
3111 case DRM_FORMAT_XBGR2101010:
3112 dspcntr |= DISPPLANE_RGBX101010;
3113 break;
3114 default:
3115 BUG();
3116 }
3117
3118 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
3119 dspcntr |= DISPPLANE_TILED;
3120
3121 if (rotation & DRM_ROTATE_180)
3122 dspcntr |= DISPPLANE_ROTATE_180;
3123
3124 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
3125 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3126
3127 intel_add_fb_offsets(&x, &y, plane_state, 0);
3128
3129 intel_crtc->dspaddr_offset =
3130 intel_compute_tile_offset(&x, &y, plane_state, 0);
3131
3132 /* HSW+ does this automagically in hardware */
3133 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
3134 rotation & DRM_ROTATE_180) {
3135 x += crtc_state->pipe_src_w - 1;
3136 y += crtc_state->pipe_src_h - 1;
3137 }
3138
3139 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3140
3141 intel_crtc->adjusted_x = x;
3142 intel_crtc->adjusted_y = y;
3143
3144 I915_WRITE(reg, dspcntr);
3145
3146 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3147 I915_WRITE(DSPSURF(plane),
3148 intel_plane_ggtt_offset(plane_state) +
3149 intel_crtc->dspaddr_offset);
3150 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3151 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3152 } else {
3153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3154 I915_WRITE(DSPLINOFF(plane), linear_offset);
3155 }
3156 POSTING_READ(reg);
3157 }
3158
3159 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3160 uint64_t fb_modifier, uint32_t pixel_format)
3161 {
3162 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3163 return 64;
3164 } else {
3165 int cpp = drm_format_plane_cpp(pixel_format, 0);
3166
3167 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3168 }
3169 }
3170
3171 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3172 {
3173 struct drm_device *dev = intel_crtc->base.dev;
3174 struct drm_i915_private *dev_priv = to_i915(dev);
3175
3176 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3177 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3178 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3179 }
3180
3181 /*
3182 * This function detaches (aka. unbinds) unused scalers in hardware
3183 */
3184 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3185 {
3186 struct intel_crtc_scaler_state *scaler_state;
3187 int i;
3188
3189 scaler_state = &intel_crtc->config->scaler_state;
3190
3191 /* loop through and disable scalers that aren't in use */
3192 for (i = 0; i < intel_crtc->num_scalers; i++) {
3193 if (!scaler_state->scalers[i].in_use)
3194 skl_detach_scaler(intel_crtc, i);
3195 }
3196 }
3197
3198 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3199 unsigned int rotation)
3200 {
3201 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3202 u32 stride = intel_fb_pitch(fb, plane, rotation);
3203
3204 /*
3205 * The stride is either expressed as a multiple of 64 bytes chunks for
3206 * linear buffers or in number of tiles for tiled buffers.
3207 */
3208 if (drm_rotation_90_or_270(rotation)) {
3209 int cpp = fb->format->cpp[plane];
3210
3211 stride /= intel_tile_height(dev_priv, fb->modifier, cpp);
3212 } else {
3213 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier,
3214 fb->format->format);
3215 }
3216
3217 return stride;
3218 }
3219
3220 u32 skl_plane_ctl_format(uint32_t pixel_format)
3221 {
3222 switch (pixel_format) {
3223 case DRM_FORMAT_C8:
3224 return PLANE_CTL_FORMAT_INDEXED;
3225 case DRM_FORMAT_RGB565:
3226 return PLANE_CTL_FORMAT_RGB_565;
3227 case DRM_FORMAT_XBGR8888:
3228 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3229 case DRM_FORMAT_XRGB8888:
3230 return PLANE_CTL_FORMAT_XRGB_8888;
3231 /*
3232 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3233 * to be already pre-multiplied. We need to add a knob (or a different
3234 * DRM_FORMAT) for user-space to configure that.
3235 */
3236 case DRM_FORMAT_ABGR8888:
3237 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3238 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3239 case DRM_FORMAT_ARGB8888:
3240 return PLANE_CTL_FORMAT_XRGB_8888 |
3241 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3242 case DRM_FORMAT_XRGB2101010:
3243 return PLANE_CTL_FORMAT_XRGB_2101010;
3244 case DRM_FORMAT_XBGR2101010:
3245 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3246 case DRM_FORMAT_YUYV:
3247 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3248 case DRM_FORMAT_YVYU:
3249 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3250 case DRM_FORMAT_UYVY:
3251 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3252 case DRM_FORMAT_VYUY:
3253 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3254 default:
3255 MISSING_CASE(pixel_format);
3256 }
3257
3258 return 0;
3259 }
3260
3261 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3262 {
3263 switch (fb_modifier) {
3264 case DRM_FORMAT_MOD_NONE:
3265 break;
3266 case I915_FORMAT_MOD_X_TILED:
3267 return PLANE_CTL_TILED_X;
3268 case I915_FORMAT_MOD_Y_TILED:
3269 return PLANE_CTL_TILED_Y;
3270 case I915_FORMAT_MOD_Yf_TILED:
3271 return PLANE_CTL_TILED_YF;
3272 default:
3273 MISSING_CASE(fb_modifier);
3274 }
3275
3276 return 0;
3277 }
3278
3279 u32 skl_plane_ctl_rotation(unsigned int rotation)
3280 {
3281 switch (rotation) {
3282 case DRM_ROTATE_0:
3283 break;
3284 /*
3285 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3286 * while i915 HW rotation is clockwise, thats why this swapping.
3287 */
3288 case DRM_ROTATE_90:
3289 return PLANE_CTL_ROTATE_270;
3290 case DRM_ROTATE_180:
3291 return PLANE_CTL_ROTATE_180;
3292 case DRM_ROTATE_270:
3293 return PLANE_CTL_ROTATE_90;
3294 default:
3295 MISSING_CASE(rotation);
3296 }
3297
3298 return 0;
3299 }
3300
3301 static void skylake_update_primary_plane(struct drm_plane *plane,
3302 const struct intel_crtc_state *crtc_state,
3303 const struct intel_plane_state *plane_state)
3304 {
3305 struct drm_device *dev = plane->dev;
3306 struct drm_i915_private *dev_priv = to_i915(dev);
3307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3308 struct drm_framebuffer *fb = plane_state->base.fb;
3309 enum plane_id plane_id = to_intel_plane(plane)->id;
3310 enum pipe pipe = to_intel_plane(plane)->pipe;
3311 u32 plane_ctl;
3312 unsigned int rotation = plane_state->base.rotation;
3313 u32 stride = skl_plane_stride(fb, 0, rotation);
3314 u32 surf_addr = plane_state->main.offset;
3315 int scaler_id = plane_state->scaler_id;
3316 int src_x = plane_state->main.x;
3317 int src_y = plane_state->main.y;
3318 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3319 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3320 int dst_x = plane_state->base.dst.x1;
3321 int dst_y = plane_state->base.dst.y1;
3322 int dst_w = drm_rect_width(&plane_state->base.dst);
3323 int dst_h = drm_rect_height(&plane_state->base.dst);
3324
3325 plane_ctl = PLANE_CTL_ENABLE;
3326
3327 if (IS_GEMINILAKE(dev_priv)) {
3328 I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
3329 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3330 PLANE_COLOR_PIPE_CSC_ENABLE |
3331 PLANE_COLOR_PLANE_GAMMA_DISABLE);
3332 } else {
3333 plane_ctl |=
3334 PLANE_CTL_PIPE_GAMMA_ENABLE |
3335 PLANE_CTL_PIPE_CSC_ENABLE |
3336 PLANE_CTL_PLANE_GAMMA_DISABLE;
3337 }
3338
3339 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3340 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3341 plane_ctl |= skl_plane_ctl_rotation(rotation);
3342
3343 /* Sizes are 0 based */
3344 src_w--;
3345 src_h--;
3346 dst_w--;
3347 dst_h--;
3348
3349 intel_crtc->dspaddr_offset = surf_addr;
3350
3351 intel_crtc->adjusted_x = src_x;
3352 intel_crtc->adjusted_y = src_y;
3353
3354 I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
3355 I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3356 I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
3357 I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3358
3359 if (scaler_id >= 0) {
3360 uint32_t ps_ctrl = 0;
3361
3362 WARN_ON(!dst_w || !dst_h);
3363 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3364 crtc_state->scaler_state.scalers[scaler_id].mode;
3365 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3366 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3367 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3368 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3369 I915_WRITE(PLANE_POS(pipe, plane_id), 0);
3370 } else {
3371 I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3372 }
3373
3374 I915_WRITE(PLANE_SURF(pipe, plane_id),
3375 intel_plane_ggtt_offset(plane_state) + surf_addr);
3376
3377 POSTING_READ(PLANE_SURF(pipe, plane_id));
3378 }
3379
3380 static void skylake_disable_primary_plane(struct drm_plane *primary,
3381 struct drm_crtc *crtc)
3382 {
3383 struct drm_device *dev = crtc->dev;
3384 struct drm_i915_private *dev_priv = to_i915(dev);
3385 enum plane_id plane_id = to_intel_plane(primary)->id;
3386 enum pipe pipe = to_intel_plane(primary)->pipe;
3387
3388 I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
3389 I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
3390 POSTING_READ(PLANE_SURF(pipe, plane_id));
3391 }
3392
3393 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3394 static int
3395 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3396 int x, int y, enum mode_set_atomic state)
3397 {
3398 /* Support for kgdboc is disabled, this needs a major rework. */
3399 DRM_ERROR("legacy panic handler not supported any more.\n");
3400
3401 return -ENODEV;
3402 }
3403
3404 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3405 {
3406 struct intel_crtc *crtc;
3407
3408 for_each_intel_crtc(&dev_priv->drm, crtc)
3409 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3410 }
3411
3412 static void intel_update_primary_planes(struct drm_device *dev)
3413 {
3414 struct drm_crtc *crtc;
3415
3416 for_each_crtc(dev, crtc) {
3417 struct intel_plane *plane = to_intel_plane(crtc->primary);
3418 struct intel_plane_state *plane_state =
3419 to_intel_plane_state(plane->base.state);
3420
3421 if (plane_state->base.visible)
3422 plane->update_plane(&plane->base,
3423 to_intel_crtc_state(crtc->state),
3424 plane_state);
3425 }
3426 }
3427
3428 static int
3429 __intel_display_resume(struct drm_device *dev,
3430 struct drm_atomic_state *state)
3431 {
3432 struct drm_crtc_state *crtc_state;
3433 struct drm_crtc *crtc;
3434 int i, ret;
3435
3436 intel_modeset_setup_hw_state(dev);
3437 i915_redisable_vga(to_i915(dev));
3438
3439 if (!state)
3440 return 0;
3441
3442 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3443 /*
3444 * Force recalculation even if we restore
3445 * current state. With fast modeset this may not result
3446 * in a modeset when the state is compatible.
3447 */
3448 crtc_state->mode_changed = true;
3449 }
3450
3451 /* ignore any reset values/BIOS leftovers in the WM registers */
3452 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3453
3454 ret = drm_atomic_commit(state);
3455
3456 WARN_ON(ret == -EDEADLK);
3457 return ret;
3458 }
3459
3460 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3461 {
3462 return intel_has_gpu_reset(dev_priv) &&
3463 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3464 }
3465
3466 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3467 {
3468 struct drm_device *dev = &dev_priv->drm;
3469 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3470 struct drm_atomic_state *state;
3471 int ret;
3472
3473 /*
3474 * Need mode_config.mutex so that we don't
3475 * trample ongoing ->detect() and whatnot.
3476 */
3477 mutex_lock(&dev->mode_config.mutex);
3478 drm_modeset_acquire_init(ctx, 0);
3479 while (1) {
3480 ret = drm_modeset_lock_all_ctx(dev, ctx);
3481 if (ret != -EDEADLK)
3482 break;
3483
3484 drm_modeset_backoff(ctx);
3485 }
3486
3487 /* reset doesn't touch the display, but flips might get nuked anyway, */
3488 if (!i915.force_reset_modeset_test &&
3489 !gpu_reset_clobbers_display(dev_priv))
3490 return;
3491
3492 /*
3493 * Disabling the crtcs gracefully seems nicer. Also the
3494 * g33 docs say we should at least disable all the planes.
3495 */
3496 state = drm_atomic_helper_duplicate_state(dev, ctx);
3497 if (IS_ERR(state)) {
3498 ret = PTR_ERR(state);
3499 DRM_ERROR("Duplicating state failed with %i\n", ret);
3500 return;
3501 }
3502
3503 ret = drm_atomic_helper_disable_all(dev, ctx);
3504 if (ret) {
3505 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3506 drm_atomic_state_put(state);
3507 return;
3508 }
3509
3510 dev_priv->modeset_restore_state = state;
3511 state->acquire_ctx = ctx;
3512 }
3513
3514 void intel_finish_reset(struct drm_i915_private *dev_priv)
3515 {
3516 struct drm_device *dev = &dev_priv->drm;
3517 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3518 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3519 int ret;
3520
3521 /*
3522 * Flips in the rings will be nuked by the reset,
3523 * so complete all pending flips so that user space
3524 * will get its events and not get stuck.
3525 */
3526 intel_complete_page_flips(dev_priv);
3527
3528 dev_priv->modeset_restore_state = NULL;
3529
3530 /* reset doesn't touch the display */
3531 if (!gpu_reset_clobbers_display(dev_priv)) {
3532 if (!state) {
3533 /*
3534 * Flips in the rings have been nuked by the reset,
3535 * so update the base address of all primary
3536 * planes to the the last fb to make sure we're
3537 * showing the correct fb after a reset.
3538 *
3539 * FIXME: Atomic will make this obsolete since we won't schedule
3540 * CS-based flips (which might get lost in gpu resets) any more.
3541 */
3542 intel_update_primary_planes(dev);
3543 } else {
3544 ret = __intel_display_resume(dev, state);
3545 if (ret)
3546 DRM_ERROR("Restoring old state failed with %i\n", ret);
3547 }
3548 } else {
3549 /*
3550 * The display has been reset as well,
3551 * so need a full re-initialization.
3552 */
3553 intel_runtime_pm_disable_interrupts(dev_priv);
3554 intel_runtime_pm_enable_interrupts(dev_priv);
3555
3556 intel_pps_unlock_regs_wa(dev_priv);
3557 intel_modeset_init_hw(dev);
3558
3559 spin_lock_irq(&dev_priv->irq_lock);
3560 if (dev_priv->display.hpd_irq_setup)
3561 dev_priv->display.hpd_irq_setup(dev_priv);
3562 spin_unlock_irq(&dev_priv->irq_lock);
3563
3564 ret = __intel_display_resume(dev, state);
3565 if (ret)
3566 DRM_ERROR("Restoring old state failed with %i\n", ret);
3567
3568 intel_hpd_init(dev_priv);
3569 }
3570
3571 if (state)
3572 drm_atomic_state_put(state);
3573 drm_modeset_drop_locks(ctx);
3574 drm_modeset_acquire_fini(ctx);
3575 mutex_unlock(&dev->mode_config.mutex);
3576 }
3577
3578 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3579 {
3580 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3581
3582 if (i915_reset_in_progress(error))
3583 return true;
3584
3585 if (crtc->reset_count != i915_reset_count(error))
3586 return true;
3587
3588 return false;
3589 }
3590
3591 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3592 {
3593 struct drm_device *dev = crtc->dev;
3594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3595 bool pending;
3596
3597 if (abort_flip_on_reset(intel_crtc))
3598 return false;
3599
3600 spin_lock_irq(&dev->event_lock);
3601 pending = to_intel_crtc(crtc)->flip_work != NULL;
3602 spin_unlock_irq(&dev->event_lock);
3603
3604 return pending;
3605 }
3606
3607 static void intel_update_pipe_config(struct intel_crtc *crtc,
3608 struct intel_crtc_state *old_crtc_state)
3609 {
3610 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3611 struct intel_crtc_state *pipe_config =
3612 to_intel_crtc_state(crtc->base.state);
3613
3614 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3615 crtc->base.mode = crtc->base.state->mode;
3616
3617 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3618 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3619 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3620
3621 /*
3622 * Update pipe size and adjust fitter if needed: the reason for this is
3623 * that in compute_mode_changes we check the native mode (not the pfit
3624 * mode) to see if we can flip rather than do a full mode set. In the
3625 * fastboot case, we'll flip, but if we don't update the pipesrc and
3626 * pfit state, we'll end up with a big fb scanned out into the wrong
3627 * sized surface.
3628 */
3629
3630 I915_WRITE(PIPESRC(crtc->pipe),
3631 ((pipe_config->pipe_src_w - 1) << 16) |
3632 (pipe_config->pipe_src_h - 1));
3633
3634 /* on skylake this is done by detaching scalers */
3635 if (INTEL_GEN(dev_priv) >= 9) {
3636 skl_detach_scalers(crtc);
3637
3638 if (pipe_config->pch_pfit.enabled)
3639 skylake_pfit_enable(crtc);
3640 } else if (HAS_PCH_SPLIT(dev_priv)) {
3641 if (pipe_config->pch_pfit.enabled)
3642 ironlake_pfit_enable(crtc);
3643 else if (old_crtc_state->pch_pfit.enabled)
3644 ironlake_pfit_disable(crtc, true);
3645 }
3646 }
3647
3648 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3649 {
3650 struct drm_device *dev = crtc->dev;
3651 struct drm_i915_private *dev_priv = to_i915(dev);
3652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3653 int pipe = intel_crtc->pipe;
3654 i915_reg_t reg;
3655 u32 temp;
3656
3657 /* enable normal train */
3658 reg = FDI_TX_CTL(pipe);
3659 temp = I915_READ(reg);
3660 if (IS_IVYBRIDGE(dev_priv)) {
3661 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3662 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3663 } else {
3664 temp &= ~FDI_LINK_TRAIN_NONE;
3665 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3666 }
3667 I915_WRITE(reg, temp);
3668
3669 reg = FDI_RX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 if (HAS_PCH_CPT(dev_priv)) {
3672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3673 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3674 } else {
3675 temp &= ~FDI_LINK_TRAIN_NONE;
3676 temp |= FDI_LINK_TRAIN_NONE;
3677 }
3678 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3679
3680 /* wait one idle pattern time */
3681 POSTING_READ(reg);
3682 udelay(1000);
3683
3684 /* IVB wants error correction enabled */
3685 if (IS_IVYBRIDGE(dev_priv))
3686 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3687 FDI_FE_ERRC_ENABLE);
3688 }
3689
3690 /* The FDI link training functions for ILK/Ibexpeak. */
3691 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3692 {
3693 struct drm_device *dev = crtc->dev;
3694 struct drm_i915_private *dev_priv = to_i915(dev);
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3696 int pipe = intel_crtc->pipe;
3697 i915_reg_t reg;
3698 u32 temp, tries;
3699
3700 /* FDI needs bits from pipe first */
3701 assert_pipe_enabled(dev_priv, pipe);
3702
3703 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3704 for train result */
3705 reg = FDI_RX_IMR(pipe);
3706 temp = I915_READ(reg);
3707 temp &= ~FDI_RX_SYMBOL_LOCK;
3708 temp &= ~FDI_RX_BIT_LOCK;
3709 I915_WRITE(reg, temp);
3710 I915_READ(reg);
3711 udelay(150);
3712
3713 /* enable CPU FDI TX and PCH FDI RX */
3714 reg = FDI_TX_CTL(pipe);
3715 temp = I915_READ(reg);
3716 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3717 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3718 temp &= ~FDI_LINK_TRAIN_NONE;
3719 temp |= FDI_LINK_TRAIN_PATTERN_1;
3720 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3721
3722 reg = FDI_RX_CTL(pipe);
3723 temp = I915_READ(reg);
3724 temp &= ~FDI_LINK_TRAIN_NONE;
3725 temp |= FDI_LINK_TRAIN_PATTERN_1;
3726 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3727
3728 POSTING_READ(reg);
3729 udelay(150);
3730
3731 /* Ironlake workaround, enable clock pointer after FDI enable*/
3732 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3733 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3734 FDI_RX_PHASE_SYNC_POINTER_EN);
3735
3736 reg = FDI_RX_IIR(pipe);
3737 for (tries = 0; tries < 5; tries++) {
3738 temp = I915_READ(reg);
3739 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3740
3741 if ((temp & FDI_RX_BIT_LOCK)) {
3742 DRM_DEBUG_KMS("FDI train 1 done.\n");
3743 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3744 break;
3745 }
3746 }
3747 if (tries == 5)
3748 DRM_ERROR("FDI train 1 fail!\n");
3749
3750 /* Train 2 */
3751 reg = FDI_TX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 temp &= ~FDI_LINK_TRAIN_NONE;
3754 temp |= FDI_LINK_TRAIN_PATTERN_2;
3755 I915_WRITE(reg, temp);
3756
3757 reg = FDI_RX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 temp &= ~FDI_LINK_TRAIN_NONE;
3760 temp |= FDI_LINK_TRAIN_PATTERN_2;
3761 I915_WRITE(reg, temp);
3762
3763 POSTING_READ(reg);
3764 udelay(150);
3765
3766 reg = FDI_RX_IIR(pipe);
3767 for (tries = 0; tries < 5; tries++) {
3768 temp = I915_READ(reg);
3769 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3770
3771 if (temp & FDI_RX_SYMBOL_LOCK) {
3772 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3773 DRM_DEBUG_KMS("FDI train 2 done.\n");
3774 break;
3775 }
3776 }
3777 if (tries == 5)
3778 DRM_ERROR("FDI train 2 fail!\n");
3779
3780 DRM_DEBUG_KMS("FDI train done\n");
3781
3782 }
3783
3784 static const int snb_b_fdi_train_param[] = {
3785 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3786 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3787 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3788 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3789 };
3790
3791 /* The FDI link training functions for SNB/Cougarpoint. */
3792 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3793 {
3794 struct drm_device *dev = crtc->dev;
3795 struct drm_i915_private *dev_priv = to_i915(dev);
3796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3797 int pipe = intel_crtc->pipe;
3798 i915_reg_t reg;
3799 u32 temp, i, retry;
3800
3801 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3802 for train result */
3803 reg = FDI_RX_IMR(pipe);
3804 temp = I915_READ(reg);
3805 temp &= ~FDI_RX_SYMBOL_LOCK;
3806 temp &= ~FDI_RX_BIT_LOCK;
3807 I915_WRITE(reg, temp);
3808
3809 POSTING_READ(reg);
3810 udelay(150);
3811
3812 /* enable CPU FDI TX and PCH FDI RX */
3813 reg = FDI_TX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3816 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3817 temp &= ~FDI_LINK_TRAIN_NONE;
3818 temp |= FDI_LINK_TRAIN_PATTERN_1;
3819 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3820 /* SNB-B */
3821 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3822 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3823
3824 I915_WRITE(FDI_RX_MISC(pipe),
3825 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3826
3827 reg = FDI_RX_CTL(pipe);
3828 temp = I915_READ(reg);
3829 if (HAS_PCH_CPT(dev_priv)) {
3830 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3831 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3832 } else {
3833 temp &= ~FDI_LINK_TRAIN_NONE;
3834 temp |= FDI_LINK_TRAIN_PATTERN_1;
3835 }
3836 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3837
3838 POSTING_READ(reg);
3839 udelay(150);
3840
3841 for (i = 0; i < 4; i++) {
3842 reg = FDI_TX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3845 temp |= snb_b_fdi_train_param[i];
3846 I915_WRITE(reg, temp);
3847
3848 POSTING_READ(reg);
3849 udelay(500);
3850
3851 for (retry = 0; retry < 5; retry++) {
3852 reg = FDI_RX_IIR(pipe);
3853 temp = I915_READ(reg);
3854 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3855 if (temp & FDI_RX_BIT_LOCK) {
3856 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3857 DRM_DEBUG_KMS("FDI train 1 done.\n");
3858 break;
3859 }
3860 udelay(50);
3861 }
3862 if (retry < 5)
3863 break;
3864 }
3865 if (i == 4)
3866 DRM_ERROR("FDI train 1 fail!\n");
3867
3868 /* Train 2 */
3869 reg = FDI_TX_CTL(pipe);
3870 temp = I915_READ(reg);
3871 temp &= ~FDI_LINK_TRAIN_NONE;
3872 temp |= FDI_LINK_TRAIN_PATTERN_2;
3873 if (IS_GEN6(dev_priv)) {
3874 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3875 /* SNB-B */
3876 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3877 }
3878 I915_WRITE(reg, temp);
3879
3880 reg = FDI_RX_CTL(pipe);
3881 temp = I915_READ(reg);
3882 if (HAS_PCH_CPT(dev_priv)) {
3883 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3884 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3885 } else {
3886 temp &= ~FDI_LINK_TRAIN_NONE;
3887 temp |= FDI_LINK_TRAIN_PATTERN_2;
3888 }
3889 I915_WRITE(reg, temp);
3890
3891 POSTING_READ(reg);
3892 udelay(150);
3893
3894 for (i = 0; i < 4; i++) {
3895 reg = FDI_TX_CTL(pipe);
3896 temp = I915_READ(reg);
3897 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3898 temp |= snb_b_fdi_train_param[i];
3899 I915_WRITE(reg, temp);
3900
3901 POSTING_READ(reg);
3902 udelay(500);
3903
3904 for (retry = 0; retry < 5; retry++) {
3905 reg = FDI_RX_IIR(pipe);
3906 temp = I915_READ(reg);
3907 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3908 if (temp & FDI_RX_SYMBOL_LOCK) {
3909 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3910 DRM_DEBUG_KMS("FDI train 2 done.\n");
3911 break;
3912 }
3913 udelay(50);
3914 }
3915 if (retry < 5)
3916 break;
3917 }
3918 if (i == 4)
3919 DRM_ERROR("FDI train 2 fail!\n");
3920
3921 DRM_DEBUG_KMS("FDI train done.\n");
3922 }
3923
3924 /* Manual link training for Ivy Bridge A0 parts */
3925 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3926 {
3927 struct drm_device *dev = crtc->dev;
3928 struct drm_i915_private *dev_priv = to_i915(dev);
3929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3930 int pipe = intel_crtc->pipe;
3931 i915_reg_t reg;
3932 u32 temp, i, j;
3933
3934 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3935 for train result */
3936 reg = FDI_RX_IMR(pipe);
3937 temp = I915_READ(reg);
3938 temp &= ~FDI_RX_SYMBOL_LOCK;
3939 temp &= ~FDI_RX_BIT_LOCK;
3940 I915_WRITE(reg, temp);
3941
3942 POSTING_READ(reg);
3943 udelay(150);
3944
3945 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3946 I915_READ(FDI_RX_IIR(pipe)));
3947
3948 /* Try each vswing and preemphasis setting twice before moving on */
3949 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3950 /* disable first in case we need to retry */
3951 reg = FDI_TX_CTL(pipe);
3952 temp = I915_READ(reg);
3953 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3954 temp &= ~FDI_TX_ENABLE;
3955 I915_WRITE(reg, temp);
3956
3957 reg = FDI_RX_CTL(pipe);
3958 temp = I915_READ(reg);
3959 temp &= ~FDI_LINK_TRAIN_AUTO;
3960 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3961 temp &= ~FDI_RX_ENABLE;
3962 I915_WRITE(reg, temp);
3963
3964 /* enable CPU FDI TX and PCH FDI RX */
3965 reg = FDI_TX_CTL(pipe);
3966 temp = I915_READ(reg);
3967 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3968 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3969 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3970 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3971 temp |= snb_b_fdi_train_param[j/2];
3972 temp |= FDI_COMPOSITE_SYNC;
3973 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3974
3975 I915_WRITE(FDI_RX_MISC(pipe),
3976 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3977
3978 reg = FDI_RX_CTL(pipe);
3979 temp = I915_READ(reg);
3980 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3981 temp |= FDI_COMPOSITE_SYNC;
3982 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3983
3984 POSTING_READ(reg);
3985 udelay(1); /* should be 0.5us */
3986
3987 for (i = 0; i < 4; i++) {
3988 reg = FDI_RX_IIR(pipe);
3989 temp = I915_READ(reg);
3990 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3991
3992 if (temp & FDI_RX_BIT_LOCK ||
3993 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3994 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3995 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3996 i);
3997 break;
3998 }
3999 udelay(1); /* should be 0.5us */
4000 }
4001 if (i == 4) {
4002 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4003 continue;
4004 }
4005
4006 /* Train 2 */
4007 reg = FDI_TX_CTL(pipe);
4008 temp = I915_READ(reg);
4009 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4010 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4011 I915_WRITE(reg, temp);
4012
4013 reg = FDI_RX_CTL(pipe);
4014 temp = I915_READ(reg);
4015 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4016 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4017 I915_WRITE(reg, temp);
4018
4019 POSTING_READ(reg);
4020 udelay(2); /* should be 1.5us */
4021
4022 for (i = 0; i < 4; i++) {
4023 reg = FDI_RX_IIR(pipe);
4024 temp = I915_READ(reg);
4025 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4026
4027 if (temp & FDI_RX_SYMBOL_LOCK ||
4028 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4029 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4030 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4031 i);
4032 goto train_done;
4033 }
4034 udelay(2); /* should be 1.5us */
4035 }
4036 if (i == 4)
4037 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4038 }
4039
4040 train_done:
4041 DRM_DEBUG_KMS("FDI train done.\n");
4042 }
4043
4044 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4045 {
4046 struct drm_device *dev = intel_crtc->base.dev;
4047 struct drm_i915_private *dev_priv = to_i915(dev);
4048 int pipe = intel_crtc->pipe;
4049 i915_reg_t reg;
4050 u32 temp;
4051
4052 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4053 reg = FDI_RX_CTL(pipe);
4054 temp = I915_READ(reg);
4055 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4056 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4057 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4058 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4059
4060 POSTING_READ(reg);
4061 udelay(200);
4062
4063 /* Switch from Rawclk to PCDclk */
4064 temp = I915_READ(reg);
4065 I915_WRITE(reg, temp | FDI_PCDCLK);
4066
4067 POSTING_READ(reg);
4068 udelay(200);
4069
4070 /* Enable CPU FDI TX PLL, always on for Ironlake */
4071 reg = FDI_TX_CTL(pipe);
4072 temp = I915_READ(reg);
4073 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4074 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4075
4076 POSTING_READ(reg);
4077 udelay(100);
4078 }
4079 }
4080
4081 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4082 {
4083 struct drm_device *dev = intel_crtc->base.dev;
4084 struct drm_i915_private *dev_priv = to_i915(dev);
4085 int pipe = intel_crtc->pipe;
4086 i915_reg_t reg;
4087 u32 temp;
4088
4089 /* Switch from PCDclk to Rawclk */
4090 reg = FDI_RX_CTL(pipe);
4091 temp = I915_READ(reg);
4092 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4093
4094 /* Disable CPU FDI TX PLL */
4095 reg = FDI_TX_CTL(pipe);
4096 temp = I915_READ(reg);
4097 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4098
4099 POSTING_READ(reg);
4100 udelay(100);
4101
4102 reg = FDI_RX_CTL(pipe);
4103 temp = I915_READ(reg);
4104 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4105
4106 /* Wait for the clocks to turn off. */
4107 POSTING_READ(reg);
4108 udelay(100);
4109 }
4110
4111 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4112 {
4113 struct drm_device *dev = crtc->dev;
4114 struct drm_i915_private *dev_priv = to_i915(dev);
4115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4116 int pipe = intel_crtc->pipe;
4117 i915_reg_t reg;
4118 u32 temp;
4119
4120 /* disable CPU FDI tx and PCH FDI rx */
4121 reg = FDI_TX_CTL(pipe);
4122 temp = I915_READ(reg);
4123 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4124 POSTING_READ(reg);
4125
4126 reg = FDI_RX_CTL(pipe);
4127 temp = I915_READ(reg);
4128 temp &= ~(0x7 << 16);
4129 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4130 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4131
4132 POSTING_READ(reg);
4133 udelay(100);
4134
4135 /* Ironlake workaround, disable clock pointer after downing FDI */
4136 if (HAS_PCH_IBX(dev_priv))
4137 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4138
4139 /* still set train pattern 1 */
4140 reg = FDI_TX_CTL(pipe);
4141 temp = I915_READ(reg);
4142 temp &= ~FDI_LINK_TRAIN_NONE;
4143 temp |= FDI_LINK_TRAIN_PATTERN_1;
4144 I915_WRITE(reg, temp);
4145
4146 reg = FDI_RX_CTL(pipe);
4147 temp = I915_READ(reg);
4148 if (HAS_PCH_CPT(dev_priv)) {
4149 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4150 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4151 } else {
4152 temp &= ~FDI_LINK_TRAIN_NONE;
4153 temp |= FDI_LINK_TRAIN_PATTERN_1;
4154 }
4155 /* BPC in FDI rx is consistent with that in PIPECONF */
4156 temp &= ~(0x07 << 16);
4157 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4158 I915_WRITE(reg, temp);
4159
4160 POSTING_READ(reg);
4161 udelay(100);
4162 }
4163
4164 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4165 {
4166 struct intel_crtc *crtc;
4167
4168 /* Note that we don't need to be called with mode_config.lock here
4169 * as our list of CRTC objects is static for the lifetime of the
4170 * device and so cannot disappear as we iterate. Similarly, we can
4171 * happily treat the predicates as racy, atomic checks as userspace
4172 * cannot claim and pin a new fb without at least acquring the
4173 * struct_mutex and so serialising with us.
4174 */
4175 for_each_intel_crtc(&dev_priv->drm, crtc) {
4176 if (atomic_read(&crtc->unpin_work_count) == 0)
4177 continue;
4178
4179 if (crtc->flip_work)
4180 intel_wait_for_vblank(dev_priv, crtc->pipe);
4181
4182 return true;
4183 }
4184
4185 return false;
4186 }
4187
4188 static void page_flip_completed(struct intel_crtc *intel_crtc)
4189 {
4190 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4191 struct intel_flip_work *work = intel_crtc->flip_work;
4192
4193 intel_crtc->flip_work = NULL;
4194
4195 if (work->event)
4196 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4197
4198 drm_crtc_vblank_put(&intel_crtc->base);
4199
4200 wake_up_all(&dev_priv->pending_flip_queue);
4201 trace_i915_flip_complete(intel_crtc->plane,
4202 work->pending_flip_obj);
4203
4204 queue_work(dev_priv->wq, &work->unpin_work);
4205 }
4206
4207 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4208 {
4209 struct drm_device *dev = crtc->dev;
4210 struct drm_i915_private *dev_priv = to_i915(dev);
4211 long ret;
4212
4213 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4214
4215 ret = wait_event_interruptible_timeout(
4216 dev_priv->pending_flip_queue,
4217 !intel_crtc_has_pending_flip(crtc),
4218 60*HZ);
4219
4220 if (ret < 0)
4221 return ret;
4222
4223 if (ret == 0) {
4224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4225 struct intel_flip_work *work;
4226
4227 spin_lock_irq(&dev->event_lock);
4228 work = intel_crtc->flip_work;
4229 if (work && !is_mmio_work(work)) {
4230 WARN_ONCE(1, "Removing stuck page flip\n");
4231 page_flip_completed(intel_crtc);
4232 }
4233 spin_unlock_irq(&dev->event_lock);
4234 }
4235
4236 return 0;
4237 }
4238
4239 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4240 {
4241 u32 temp;
4242
4243 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4244
4245 mutex_lock(&dev_priv->sb_lock);
4246
4247 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4248 temp |= SBI_SSCCTL_DISABLE;
4249 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4250
4251 mutex_unlock(&dev_priv->sb_lock);
4252 }
4253
4254 /* Program iCLKIP clock to the desired frequency */
4255 static void lpt_program_iclkip(struct drm_crtc *crtc)
4256 {
4257 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4258 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4259 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4260 u32 temp;
4261
4262 lpt_disable_iclkip(dev_priv);
4263
4264 /* The iCLK virtual clock root frequency is in MHz,
4265 * but the adjusted_mode->crtc_clock in in KHz. To get the
4266 * divisors, it is necessary to divide one by another, so we
4267 * convert the virtual clock precision to KHz here for higher
4268 * precision.
4269 */
4270 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4271 u32 iclk_virtual_root_freq = 172800 * 1000;
4272 u32 iclk_pi_range = 64;
4273 u32 desired_divisor;
4274
4275 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4276 clock << auxdiv);
4277 divsel = (desired_divisor / iclk_pi_range) - 2;
4278 phaseinc = desired_divisor % iclk_pi_range;
4279
4280 /*
4281 * Near 20MHz is a corner case which is
4282 * out of range for the 7-bit divisor
4283 */
4284 if (divsel <= 0x7f)
4285 break;
4286 }
4287
4288 /* This should not happen with any sane values */
4289 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4290 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4291 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4292 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4293
4294 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4295 clock,
4296 auxdiv,
4297 divsel,
4298 phasedir,
4299 phaseinc);
4300
4301 mutex_lock(&dev_priv->sb_lock);
4302
4303 /* Program SSCDIVINTPHASE6 */
4304 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4305 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4306 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4307 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4308 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4309 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4310 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4311 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4312
4313 /* Program SSCAUXDIV */
4314 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4315 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4316 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4317 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4318
4319 /* Enable modulator and associated divider */
4320 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4321 temp &= ~SBI_SSCCTL_DISABLE;
4322 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4323
4324 mutex_unlock(&dev_priv->sb_lock);
4325
4326 /* Wait for initialization time */
4327 udelay(24);
4328
4329 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4330 }
4331
4332 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4333 {
4334 u32 divsel, phaseinc, auxdiv;
4335 u32 iclk_virtual_root_freq = 172800 * 1000;
4336 u32 iclk_pi_range = 64;
4337 u32 desired_divisor;
4338 u32 temp;
4339
4340 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4341 return 0;
4342
4343 mutex_lock(&dev_priv->sb_lock);
4344
4345 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4346 if (temp & SBI_SSCCTL_DISABLE) {
4347 mutex_unlock(&dev_priv->sb_lock);
4348 return 0;
4349 }
4350
4351 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4352 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4353 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4354 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4355 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4356
4357 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4358 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4359 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4360
4361 mutex_unlock(&dev_priv->sb_lock);
4362
4363 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4364
4365 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4366 desired_divisor << auxdiv);
4367 }
4368
4369 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4370 enum pipe pch_transcoder)
4371 {
4372 struct drm_device *dev = crtc->base.dev;
4373 struct drm_i915_private *dev_priv = to_i915(dev);
4374 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4375
4376 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4377 I915_READ(HTOTAL(cpu_transcoder)));
4378 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4379 I915_READ(HBLANK(cpu_transcoder)));
4380 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4381 I915_READ(HSYNC(cpu_transcoder)));
4382
4383 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4384 I915_READ(VTOTAL(cpu_transcoder)));
4385 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4386 I915_READ(VBLANK(cpu_transcoder)));
4387 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4388 I915_READ(VSYNC(cpu_transcoder)));
4389 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4390 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4391 }
4392
4393 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4394 {
4395 struct drm_i915_private *dev_priv = to_i915(dev);
4396 uint32_t temp;
4397
4398 temp = I915_READ(SOUTH_CHICKEN1);
4399 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4400 return;
4401
4402 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4403 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4404
4405 temp &= ~FDI_BC_BIFURCATION_SELECT;
4406 if (enable)
4407 temp |= FDI_BC_BIFURCATION_SELECT;
4408
4409 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4410 I915_WRITE(SOUTH_CHICKEN1, temp);
4411 POSTING_READ(SOUTH_CHICKEN1);
4412 }
4413
4414 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4415 {
4416 struct drm_device *dev = intel_crtc->base.dev;
4417
4418 switch (intel_crtc->pipe) {
4419 case PIPE_A:
4420 break;
4421 case PIPE_B:
4422 if (intel_crtc->config->fdi_lanes > 2)
4423 cpt_set_fdi_bc_bifurcation(dev, false);
4424 else
4425 cpt_set_fdi_bc_bifurcation(dev, true);
4426
4427 break;
4428 case PIPE_C:
4429 cpt_set_fdi_bc_bifurcation(dev, true);
4430
4431 break;
4432 default:
4433 BUG();
4434 }
4435 }
4436
4437 /* Return which DP Port should be selected for Transcoder DP control */
4438 static enum port
4439 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4440 {
4441 struct drm_device *dev = crtc->dev;
4442 struct intel_encoder *encoder;
4443
4444 for_each_encoder_on_crtc(dev, crtc, encoder) {
4445 if (encoder->type == INTEL_OUTPUT_DP ||
4446 encoder->type == INTEL_OUTPUT_EDP)
4447 return enc_to_dig_port(&encoder->base)->port;
4448 }
4449
4450 return -1;
4451 }
4452
4453 /*
4454 * Enable PCH resources required for PCH ports:
4455 * - PCH PLLs
4456 * - FDI training & RX/TX
4457 * - update transcoder timings
4458 * - DP transcoding bits
4459 * - transcoder
4460 */
4461 static void ironlake_pch_enable(struct drm_crtc *crtc)
4462 {
4463 struct drm_device *dev = crtc->dev;
4464 struct drm_i915_private *dev_priv = to_i915(dev);
4465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4466 int pipe = intel_crtc->pipe;
4467 u32 temp;
4468
4469 assert_pch_transcoder_disabled(dev_priv, pipe);
4470
4471 if (IS_IVYBRIDGE(dev_priv))
4472 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4473
4474 /* Write the TU size bits before fdi link training, so that error
4475 * detection works. */
4476 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4477 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4478
4479 /* For PCH output, training FDI link */
4480 dev_priv->display.fdi_link_train(crtc);
4481
4482 /* We need to program the right clock selection before writing the pixel
4483 * mutliplier into the DPLL. */
4484 if (HAS_PCH_CPT(dev_priv)) {
4485 u32 sel;
4486
4487 temp = I915_READ(PCH_DPLL_SEL);
4488 temp |= TRANS_DPLL_ENABLE(pipe);
4489 sel = TRANS_DPLLB_SEL(pipe);
4490 if (intel_crtc->config->shared_dpll ==
4491 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4492 temp |= sel;
4493 else
4494 temp &= ~sel;
4495 I915_WRITE(PCH_DPLL_SEL, temp);
4496 }
4497
4498 /* XXX: pch pll's can be enabled any time before we enable the PCH
4499 * transcoder, and we actually should do this to not upset any PCH
4500 * transcoder that already use the clock when we share it.
4501 *
4502 * Note that enable_shared_dpll tries to do the right thing, but
4503 * get_shared_dpll unconditionally resets the pll - we need that to have
4504 * the right LVDS enable sequence. */
4505 intel_enable_shared_dpll(intel_crtc);
4506
4507 /* set transcoder timing, panel must allow it */
4508 assert_panel_unlocked(dev_priv, pipe);
4509 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4510
4511 intel_fdi_normal_train(crtc);
4512
4513 /* For PCH DP, enable TRANS_DP_CTL */
4514 if (HAS_PCH_CPT(dev_priv) &&
4515 intel_crtc_has_dp_encoder(intel_crtc->config)) {
4516 const struct drm_display_mode *adjusted_mode =
4517 &intel_crtc->config->base.adjusted_mode;
4518 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4519 i915_reg_t reg = TRANS_DP_CTL(pipe);
4520 temp = I915_READ(reg);
4521 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4522 TRANS_DP_SYNC_MASK |
4523 TRANS_DP_BPC_MASK);
4524 temp |= TRANS_DP_OUTPUT_ENABLE;
4525 temp |= bpc << 9; /* same format but at 11:9 */
4526
4527 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4528 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4529 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4530 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4531
4532 switch (intel_trans_dp_port_sel(crtc)) {
4533 case PORT_B:
4534 temp |= TRANS_DP_PORT_SEL_B;
4535 break;
4536 case PORT_C:
4537 temp |= TRANS_DP_PORT_SEL_C;
4538 break;
4539 case PORT_D:
4540 temp |= TRANS_DP_PORT_SEL_D;
4541 break;
4542 default:
4543 BUG();
4544 }
4545
4546 I915_WRITE(reg, temp);
4547 }
4548
4549 ironlake_enable_pch_transcoder(dev_priv, pipe);
4550 }
4551
4552 static void lpt_pch_enable(struct drm_crtc *crtc)
4553 {
4554 struct drm_device *dev = crtc->dev;
4555 struct drm_i915_private *dev_priv = to_i915(dev);
4556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4557 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4558
4559 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4560
4561 lpt_program_iclkip(crtc);
4562
4563 /* Set transcoder timing. */
4564 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4565
4566 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4567 }
4568
4569 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4570 {
4571 struct drm_i915_private *dev_priv = to_i915(dev);
4572 i915_reg_t dslreg = PIPEDSL(pipe);
4573 u32 temp;
4574
4575 temp = I915_READ(dslreg);
4576 udelay(500);
4577 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4578 if (wait_for(I915_READ(dslreg) != temp, 5))
4579 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4580 }
4581 }
4582
4583 static int
4584 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4585 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4586 int src_w, int src_h, int dst_w, int dst_h)
4587 {
4588 struct intel_crtc_scaler_state *scaler_state =
4589 &crtc_state->scaler_state;
4590 struct intel_crtc *intel_crtc =
4591 to_intel_crtc(crtc_state->base.crtc);
4592 int need_scaling;
4593
4594 need_scaling = drm_rotation_90_or_270(rotation) ?
4595 (src_h != dst_w || src_w != dst_h):
4596 (src_w != dst_w || src_h != dst_h);
4597
4598 /*
4599 * if plane is being disabled or scaler is no more required or force detach
4600 * - free scaler binded to this plane/crtc
4601 * - in order to do this, update crtc->scaler_usage
4602 *
4603 * Here scaler state in crtc_state is set free so that
4604 * scaler can be assigned to other user. Actual register
4605 * update to free the scaler is done in plane/panel-fit programming.
4606 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4607 */
4608 if (force_detach || !need_scaling) {
4609 if (*scaler_id >= 0) {
4610 scaler_state->scaler_users &= ~(1 << scaler_user);
4611 scaler_state->scalers[*scaler_id].in_use = 0;
4612
4613 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4614 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4615 intel_crtc->pipe, scaler_user, *scaler_id,
4616 scaler_state->scaler_users);
4617 *scaler_id = -1;
4618 }
4619 return 0;
4620 }
4621
4622 /* range checks */
4623 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4624 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4625
4626 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4627 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4628 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4629 "size is out of scaler range\n",
4630 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4631 return -EINVAL;
4632 }
4633
4634 /* mark this plane as a scaler user in crtc_state */
4635 scaler_state->scaler_users |= (1 << scaler_user);
4636 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4637 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4638 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4639 scaler_state->scaler_users);
4640
4641 return 0;
4642 }
4643
4644 /**
4645 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4646 *
4647 * @state: crtc's scaler state
4648 *
4649 * Return
4650 * 0 - scaler_usage updated successfully
4651 * error - requested scaling cannot be supported or other error condition
4652 */
4653 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4654 {
4655 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4656
4657 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4658 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4659 state->pipe_src_w, state->pipe_src_h,
4660 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4661 }
4662
4663 /**
4664 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4665 *
4666 * @state: crtc's scaler state
4667 * @plane_state: atomic plane state to update
4668 *
4669 * Return
4670 * 0 - scaler_usage updated successfully
4671 * error - requested scaling cannot be supported or other error condition
4672 */
4673 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4674 struct intel_plane_state *plane_state)
4675 {
4676
4677 struct intel_plane *intel_plane =
4678 to_intel_plane(plane_state->base.plane);
4679 struct drm_framebuffer *fb = plane_state->base.fb;
4680 int ret;
4681
4682 bool force_detach = !fb || !plane_state->base.visible;
4683
4684 ret = skl_update_scaler(crtc_state, force_detach,
4685 drm_plane_index(&intel_plane->base),
4686 &plane_state->scaler_id,
4687 plane_state->base.rotation,
4688 drm_rect_width(&plane_state->base.src) >> 16,
4689 drm_rect_height(&plane_state->base.src) >> 16,
4690 drm_rect_width(&plane_state->base.dst),
4691 drm_rect_height(&plane_state->base.dst));
4692
4693 if (ret || plane_state->scaler_id < 0)
4694 return ret;
4695
4696 /* check colorkey */
4697 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4698 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4699 intel_plane->base.base.id,
4700 intel_plane->base.name);
4701 return -EINVAL;
4702 }
4703
4704 /* Check src format */
4705 switch (fb->format->format) {
4706 case DRM_FORMAT_RGB565:
4707 case DRM_FORMAT_XBGR8888:
4708 case DRM_FORMAT_XRGB8888:
4709 case DRM_FORMAT_ABGR8888:
4710 case DRM_FORMAT_ARGB8888:
4711 case DRM_FORMAT_XRGB2101010:
4712 case DRM_FORMAT_XBGR2101010:
4713 case DRM_FORMAT_YUYV:
4714 case DRM_FORMAT_YVYU:
4715 case DRM_FORMAT_UYVY:
4716 case DRM_FORMAT_VYUY:
4717 break;
4718 default:
4719 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4720 intel_plane->base.base.id, intel_plane->base.name,
4721 fb->base.id, fb->format->format);
4722 return -EINVAL;
4723 }
4724
4725 return 0;
4726 }
4727
4728 static void skylake_scaler_disable(struct intel_crtc *crtc)
4729 {
4730 int i;
4731
4732 for (i = 0; i < crtc->num_scalers; i++)
4733 skl_detach_scaler(crtc, i);
4734 }
4735
4736 static void skylake_pfit_enable(struct intel_crtc *crtc)
4737 {
4738 struct drm_device *dev = crtc->base.dev;
4739 struct drm_i915_private *dev_priv = to_i915(dev);
4740 int pipe = crtc->pipe;
4741 struct intel_crtc_scaler_state *scaler_state =
4742 &crtc->config->scaler_state;
4743
4744 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4745
4746 if (crtc->config->pch_pfit.enabled) {
4747 int id;
4748
4749 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4750 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4751 return;
4752 }
4753
4754 id = scaler_state->scaler_id;
4755 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4756 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4757 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4758 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4759
4760 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4761 }
4762 }
4763
4764 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4765 {
4766 struct drm_device *dev = crtc->base.dev;
4767 struct drm_i915_private *dev_priv = to_i915(dev);
4768 int pipe = crtc->pipe;
4769
4770 if (crtc->config->pch_pfit.enabled) {
4771 /* Force use of hard-coded filter coefficients
4772 * as some pre-programmed values are broken,
4773 * e.g. x201.
4774 */
4775 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4776 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4777 PF_PIPE_SEL_IVB(pipe));
4778 else
4779 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4780 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4781 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4782 }
4783 }
4784
4785 void hsw_enable_ips(struct intel_crtc *crtc)
4786 {
4787 struct drm_device *dev = crtc->base.dev;
4788 struct drm_i915_private *dev_priv = to_i915(dev);
4789
4790 if (!crtc->config->ips_enabled)
4791 return;
4792
4793 /*
4794 * We can only enable IPS after we enable a plane and wait for a vblank
4795 * This function is called from post_plane_update, which is run after
4796 * a vblank wait.
4797 */
4798
4799 assert_plane_enabled(dev_priv, crtc->plane);
4800 if (IS_BROADWELL(dev_priv)) {
4801 mutex_lock(&dev_priv->rps.hw_lock);
4802 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4803 mutex_unlock(&dev_priv->rps.hw_lock);
4804 /* Quoting Art Runyan: "its not safe to expect any particular
4805 * value in IPS_CTL bit 31 after enabling IPS through the
4806 * mailbox." Moreover, the mailbox may return a bogus state,
4807 * so we need to just enable it and continue on.
4808 */
4809 } else {
4810 I915_WRITE(IPS_CTL, IPS_ENABLE);
4811 /* The bit only becomes 1 in the next vblank, so this wait here
4812 * is essentially intel_wait_for_vblank. If we don't have this
4813 * and don't wait for vblanks until the end of crtc_enable, then
4814 * the HW state readout code will complain that the expected
4815 * IPS_CTL value is not the one we read. */
4816 if (intel_wait_for_register(dev_priv,
4817 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4818 50))
4819 DRM_ERROR("Timed out waiting for IPS enable\n");
4820 }
4821 }
4822
4823 void hsw_disable_ips(struct intel_crtc *crtc)
4824 {
4825 struct drm_device *dev = crtc->base.dev;
4826 struct drm_i915_private *dev_priv = to_i915(dev);
4827
4828 if (!crtc->config->ips_enabled)
4829 return;
4830
4831 assert_plane_enabled(dev_priv, crtc->plane);
4832 if (IS_BROADWELL(dev_priv)) {
4833 mutex_lock(&dev_priv->rps.hw_lock);
4834 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4835 mutex_unlock(&dev_priv->rps.hw_lock);
4836 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4837 if (intel_wait_for_register(dev_priv,
4838 IPS_CTL, IPS_ENABLE, 0,
4839 42))
4840 DRM_ERROR("Timed out waiting for IPS disable\n");
4841 } else {
4842 I915_WRITE(IPS_CTL, 0);
4843 POSTING_READ(IPS_CTL);
4844 }
4845
4846 /* We need to wait for a vblank before we can disable the plane. */
4847 intel_wait_for_vblank(dev_priv, crtc->pipe);
4848 }
4849
4850 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4851 {
4852 if (intel_crtc->overlay) {
4853 struct drm_device *dev = intel_crtc->base.dev;
4854 struct drm_i915_private *dev_priv = to_i915(dev);
4855
4856 mutex_lock(&dev->struct_mutex);
4857 dev_priv->mm.interruptible = false;
4858 (void) intel_overlay_switch_off(intel_crtc->overlay);
4859 dev_priv->mm.interruptible = true;
4860 mutex_unlock(&dev->struct_mutex);
4861 }
4862
4863 /* Let userspace switch the overlay on again. In most cases userspace
4864 * has to recompute where to put it anyway.
4865 */
4866 }
4867
4868 /**
4869 * intel_post_enable_primary - Perform operations after enabling primary plane
4870 * @crtc: the CRTC whose primary plane was just enabled
4871 *
4872 * Performs potentially sleeping operations that must be done after the primary
4873 * plane is enabled, such as updating FBC and IPS. Note that this may be
4874 * called due to an explicit primary plane update, or due to an implicit
4875 * re-enable that is caused when a sprite plane is updated to no longer
4876 * completely hide the primary plane.
4877 */
4878 static void
4879 intel_post_enable_primary(struct drm_crtc *crtc)
4880 {
4881 struct drm_device *dev = crtc->dev;
4882 struct drm_i915_private *dev_priv = to_i915(dev);
4883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4884 int pipe = intel_crtc->pipe;
4885
4886 /*
4887 * FIXME IPS should be fine as long as one plane is
4888 * enabled, but in practice it seems to have problems
4889 * when going from primary only to sprite only and vice
4890 * versa.
4891 */
4892 hsw_enable_ips(intel_crtc);
4893
4894 /*
4895 * Gen2 reports pipe underruns whenever all planes are disabled.
4896 * So don't enable underrun reporting before at least some planes
4897 * are enabled.
4898 * FIXME: Need to fix the logic to work when we turn off all planes
4899 * but leave the pipe running.
4900 */
4901 if (IS_GEN2(dev_priv))
4902 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4903
4904 /* Underruns don't always raise interrupts, so check manually. */
4905 intel_check_cpu_fifo_underruns(dev_priv);
4906 intel_check_pch_fifo_underruns(dev_priv);
4907 }
4908
4909 /* FIXME move all this to pre_plane_update() with proper state tracking */
4910 static void
4911 intel_pre_disable_primary(struct drm_crtc *crtc)
4912 {
4913 struct drm_device *dev = crtc->dev;
4914 struct drm_i915_private *dev_priv = to_i915(dev);
4915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4916 int pipe = intel_crtc->pipe;
4917
4918 /*
4919 * Gen2 reports pipe underruns whenever all planes are disabled.
4920 * So diasble underrun reporting before all the planes get disabled.
4921 * FIXME: Need to fix the logic to work when we turn off all planes
4922 * but leave the pipe running.
4923 */
4924 if (IS_GEN2(dev_priv))
4925 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4926
4927 /*
4928 * FIXME IPS should be fine as long as one plane is
4929 * enabled, but in practice it seems to have problems
4930 * when going from primary only to sprite only and vice
4931 * versa.
4932 */
4933 hsw_disable_ips(intel_crtc);
4934 }
4935
4936 /* FIXME get rid of this and use pre_plane_update */
4937 static void
4938 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4939 {
4940 struct drm_device *dev = crtc->dev;
4941 struct drm_i915_private *dev_priv = to_i915(dev);
4942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4943 int pipe = intel_crtc->pipe;
4944
4945 intel_pre_disable_primary(crtc);
4946
4947 /*
4948 * Vblank time updates from the shadow to live plane control register
4949 * are blocked if the memory self-refresh mode is active at that
4950 * moment. So to make sure the plane gets truly disabled, disable
4951 * first the self-refresh mode. The self-refresh enable bit in turn
4952 * will be checked/applied by the HW only at the next frame start
4953 * event which is after the vblank start event, so we need to have a
4954 * wait-for-vblank between disabling the plane and the pipe.
4955 */
4956 if (HAS_GMCH_DISPLAY(dev_priv) &&
4957 intel_set_memory_cxsr(dev_priv, false))
4958 intel_wait_for_vblank(dev_priv, pipe);
4959 }
4960
4961 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4962 {
4963 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4964 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4965 struct intel_crtc_state *pipe_config =
4966 to_intel_crtc_state(crtc->base.state);
4967 struct drm_plane *primary = crtc->base.primary;
4968 struct drm_plane_state *old_pri_state =
4969 drm_atomic_get_existing_plane_state(old_state, primary);
4970
4971 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
4972
4973 crtc->wm.cxsr_allowed = true;
4974
4975 if (pipe_config->update_wm_post && pipe_config->base.active)
4976 intel_update_watermarks(crtc);
4977
4978 if (old_pri_state) {
4979 struct intel_plane_state *primary_state =
4980 to_intel_plane_state(primary->state);
4981 struct intel_plane_state *old_primary_state =
4982 to_intel_plane_state(old_pri_state);
4983
4984 intel_fbc_post_update(crtc);
4985
4986 if (primary_state->base.visible &&
4987 (needs_modeset(&pipe_config->base) ||
4988 !old_primary_state->base.visible))
4989 intel_post_enable_primary(&crtc->base);
4990 }
4991 }
4992
4993 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4994 {
4995 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4996 struct drm_device *dev = crtc->base.dev;
4997 struct drm_i915_private *dev_priv = to_i915(dev);
4998 struct intel_crtc_state *pipe_config =
4999 to_intel_crtc_state(crtc->base.state);
5000 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5001 struct drm_plane *primary = crtc->base.primary;
5002 struct drm_plane_state *old_pri_state =
5003 drm_atomic_get_existing_plane_state(old_state, primary);
5004 bool modeset = needs_modeset(&pipe_config->base);
5005 struct intel_atomic_state *old_intel_state =
5006 to_intel_atomic_state(old_state);
5007
5008 if (old_pri_state) {
5009 struct intel_plane_state *primary_state =
5010 to_intel_plane_state(primary->state);
5011 struct intel_plane_state *old_primary_state =
5012 to_intel_plane_state(old_pri_state);
5013
5014 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5015
5016 if (old_primary_state->base.visible &&
5017 (modeset || !primary_state->base.visible))
5018 intel_pre_disable_primary(&crtc->base);
5019 }
5020
5021 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
5022 crtc->wm.cxsr_allowed = false;
5023
5024 /*
5025 * Vblank time updates from the shadow to live plane control register
5026 * are blocked if the memory self-refresh mode is active at that
5027 * moment. So to make sure the plane gets truly disabled, disable
5028 * first the self-refresh mode. The self-refresh enable bit in turn
5029 * will be checked/applied by the HW only at the next frame start
5030 * event which is after the vblank start event, so we need to have a
5031 * wait-for-vblank between disabling the plane and the pipe.
5032 */
5033 if (old_crtc_state->base.active &&
5034 intel_set_memory_cxsr(dev_priv, false))
5035 intel_wait_for_vblank(dev_priv, crtc->pipe);
5036 }
5037
5038 /*
5039 * IVB workaround: must disable low power watermarks for at least
5040 * one frame before enabling scaling. LP watermarks can be re-enabled
5041 * when scaling is disabled.
5042 *
5043 * WaCxSRDisabledForSpriteScaling:ivb
5044 */
5045 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5046 intel_wait_for_vblank(dev_priv, crtc->pipe);
5047
5048 /*
5049 * If we're doing a modeset, we're done. No need to do any pre-vblank
5050 * watermark programming here.
5051 */
5052 if (needs_modeset(&pipe_config->base))
5053 return;
5054
5055 /*
5056 * For platforms that support atomic watermarks, program the
5057 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5058 * will be the intermediate values that are safe for both pre- and
5059 * post- vblank; when vblank happens, the 'active' values will be set
5060 * to the final 'target' values and we'll do this again to get the
5061 * optimal watermarks. For gen9+ platforms, the values we program here
5062 * will be the final target values which will get automatically latched
5063 * at vblank time; no further programming will be necessary.
5064 *
5065 * If a platform hasn't been transitioned to atomic watermarks yet,
5066 * we'll continue to update watermarks the old way, if flags tell
5067 * us to.
5068 */
5069 if (dev_priv->display.initial_watermarks != NULL)
5070 dev_priv->display.initial_watermarks(old_intel_state,
5071 pipe_config);
5072 else if (pipe_config->update_wm_pre)
5073 intel_update_watermarks(crtc);
5074 }
5075
5076 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5077 {
5078 struct drm_device *dev = crtc->dev;
5079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5080 struct drm_plane *p;
5081 int pipe = intel_crtc->pipe;
5082
5083 intel_crtc_dpms_overlay_disable(intel_crtc);
5084
5085 drm_for_each_plane_mask(p, dev, plane_mask)
5086 to_intel_plane(p)->disable_plane(p, crtc);
5087
5088 /*
5089 * FIXME: Once we grow proper nuclear flip support out of this we need
5090 * to compute the mask of flip planes precisely. For the time being
5091 * consider this a flip to a NULL plane.
5092 */
5093 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5094 }
5095
5096 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5097 struct intel_crtc_state *crtc_state,
5098 struct drm_atomic_state *old_state)
5099 {
5100 struct drm_connector_state *old_conn_state;
5101 struct drm_connector *conn;
5102 int i;
5103
5104 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5105 struct drm_connector_state *conn_state = conn->state;
5106 struct intel_encoder *encoder =
5107 to_intel_encoder(conn_state->best_encoder);
5108
5109 if (conn_state->crtc != crtc)
5110 continue;
5111
5112 if (encoder->pre_pll_enable)
5113 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5114 }
5115 }
5116
5117 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5118 struct intel_crtc_state *crtc_state,
5119 struct drm_atomic_state *old_state)
5120 {
5121 struct drm_connector_state *old_conn_state;
5122 struct drm_connector *conn;
5123 int i;
5124
5125 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5126 struct drm_connector_state *conn_state = conn->state;
5127 struct intel_encoder *encoder =
5128 to_intel_encoder(conn_state->best_encoder);
5129
5130 if (conn_state->crtc != crtc)
5131 continue;
5132
5133 if (encoder->pre_enable)
5134 encoder->pre_enable(encoder, crtc_state, conn_state);
5135 }
5136 }
5137
5138 static void intel_encoders_enable(struct drm_crtc *crtc,
5139 struct intel_crtc_state *crtc_state,
5140 struct drm_atomic_state *old_state)
5141 {
5142 struct drm_connector_state *old_conn_state;
5143 struct drm_connector *conn;
5144 int i;
5145
5146 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5147 struct drm_connector_state *conn_state = conn->state;
5148 struct intel_encoder *encoder =
5149 to_intel_encoder(conn_state->best_encoder);
5150
5151 if (conn_state->crtc != crtc)
5152 continue;
5153
5154 encoder->enable(encoder, crtc_state, conn_state);
5155 intel_opregion_notify_encoder(encoder, true);
5156 }
5157 }
5158
5159 static void intel_encoders_disable(struct drm_crtc *crtc,
5160 struct intel_crtc_state *old_crtc_state,
5161 struct drm_atomic_state *old_state)
5162 {
5163 struct drm_connector_state *old_conn_state;
5164 struct drm_connector *conn;
5165 int i;
5166
5167 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5168 struct intel_encoder *encoder =
5169 to_intel_encoder(old_conn_state->best_encoder);
5170
5171 if (old_conn_state->crtc != crtc)
5172 continue;
5173
5174 intel_opregion_notify_encoder(encoder, false);
5175 encoder->disable(encoder, old_crtc_state, old_conn_state);
5176 }
5177 }
5178
5179 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5180 struct intel_crtc_state *old_crtc_state,
5181 struct drm_atomic_state *old_state)
5182 {
5183 struct drm_connector_state *old_conn_state;
5184 struct drm_connector *conn;
5185 int i;
5186
5187 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5188 struct intel_encoder *encoder =
5189 to_intel_encoder(old_conn_state->best_encoder);
5190
5191 if (old_conn_state->crtc != crtc)
5192 continue;
5193
5194 if (encoder->post_disable)
5195 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5196 }
5197 }
5198
5199 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5200 struct intel_crtc_state *old_crtc_state,
5201 struct drm_atomic_state *old_state)
5202 {
5203 struct drm_connector_state *old_conn_state;
5204 struct drm_connector *conn;
5205 int i;
5206
5207 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5208 struct intel_encoder *encoder =
5209 to_intel_encoder(old_conn_state->best_encoder);
5210
5211 if (old_conn_state->crtc != crtc)
5212 continue;
5213
5214 if (encoder->post_pll_disable)
5215 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5216 }
5217 }
5218
5219 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5220 struct drm_atomic_state *old_state)
5221 {
5222 struct drm_crtc *crtc = pipe_config->base.crtc;
5223 struct drm_device *dev = crtc->dev;
5224 struct drm_i915_private *dev_priv = to_i915(dev);
5225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5226 int pipe = intel_crtc->pipe;
5227 struct intel_atomic_state *old_intel_state =
5228 to_intel_atomic_state(old_state);
5229
5230 if (WARN_ON(intel_crtc->active))
5231 return;
5232
5233 /*
5234 * Sometimes spurious CPU pipe underruns happen during FDI
5235 * training, at least with VGA+HDMI cloning. Suppress them.
5236 *
5237 * On ILK we get an occasional spurious CPU pipe underruns
5238 * between eDP port A enable and vdd enable. Also PCH port
5239 * enable seems to result in the occasional CPU pipe underrun.
5240 *
5241 * Spurious PCH underruns also occur during PCH enabling.
5242 */
5243 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5244 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5245 if (intel_crtc->config->has_pch_encoder)
5246 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5247
5248 if (intel_crtc->config->has_pch_encoder)
5249 intel_prepare_shared_dpll(intel_crtc);
5250
5251 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5252 intel_dp_set_m_n(intel_crtc, M1_N1);
5253
5254 intel_set_pipe_timings(intel_crtc);
5255 intel_set_pipe_src_size(intel_crtc);
5256
5257 if (intel_crtc->config->has_pch_encoder) {
5258 intel_cpu_transcoder_set_m_n(intel_crtc,
5259 &intel_crtc->config->fdi_m_n, NULL);
5260 }
5261
5262 ironlake_set_pipeconf(crtc);
5263
5264 intel_crtc->active = true;
5265
5266 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5267
5268 if (intel_crtc->config->has_pch_encoder) {
5269 /* Note: FDI PLL enabling _must_ be done before we enable the
5270 * cpu pipes, hence this is separate from all the other fdi/pch
5271 * enabling. */
5272 ironlake_fdi_pll_enable(intel_crtc);
5273 } else {
5274 assert_fdi_tx_disabled(dev_priv, pipe);
5275 assert_fdi_rx_disabled(dev_priv, pipe);
5276 }
5277
5278 ironlake_pfit_enable(intel_crtc);
5279
5280 /*
5281 * On ILK+ LUT must be loaded before the pipe is running but with
5282 * clocks enabled
5283 */
5284 intel_color_load_luts(&pipe_config->base);
5285
5286 if (dev_priv->display.initial_watermarks != NULL)
5287 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5288 intel_enable_pipe(intel_crtc);
5289
5290 if (intel_crtc->config->has_pch_encoder)
5291 ironlake_pch_enable(crtc);
5292
5293 assert_vblank_disabled(crtc);
5294 drm_crtc_vblank_on(crtc);
5295
5296 intel_encoders_enable(crtc, pipe_config, old_state);
5297
5298 if (HAS_PCH_CPT(dev_priv))
5299 cpt_verify_modeset(dev, intel_crtc->pipe);
5300
5301 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5302 if (intel_crtc->config->has_pch_encoder)
5303 intel_wait_for_vblank(dev_priv, pipe);
5304 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5305 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5306 }
5307
5308 /* IPS only exists on ULT machines and is tied to pipe A. */
5309 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5310 {
5311 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5312 }
5313
5314 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5315 struct drm_atomic_state *old_state)
5316 {
5317 struct drm_crtc *crtc = pipe_config->base.crtc;
5318 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5320 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5321 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5322 struct intel_atomic_state *old_intel_state =
5323 to_intel_atomic_state(old_state);
5324
5325 if (WARN_ON(intel_crtc->active))
5326 return;
5327
5328 if (intel_crtc->config->has_pch_encoder)
5329 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5330 false);
5331
5332 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5333
5334 if (intel_crtc->config->shared_dpll)
5335 intel_enable_shared_dpll(intel_crtc);
5336
5337 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5338 intel_dp_set_m_n(intel_crtc, M1_N1);
5339
5340 if (!transcoder_is_dsi(cpu_transcoder))
5341 intel_set_pipe_timings(intel_crtc);
5342
5343 intel_set_pipe_src_size(intel_crtc);
5344
5345 if (cpu_transcoder != TRANSCODER_EDP &&
5346 !transcoder_is_dsi(cpu_transcoder)) {
5347 I915_WRITE(PIPE_MULT(cpu_transcoder),
5348 intel_crtc->config->pixel_multiplier - 1);
5349 }
5350
5351 if (intel_crtc->config->has_pch_encoder) {
5352 intel_cpu_transcoder_set_m_n(intel_crtc,
5353 &intel_crtc->config->fdi_m_n, NULL);
5354 }
5355
5356 if (!transcoder_is_dsi(cpu_transcoder))
5357 haswell_set_pipeconf(crtc);
5358
5359 haswell_set_pipemisc(crtc);
5360
5361 intel_color_set_csc(&pipe_config->base);
5362
5363 intel_crtc->active = true;
5364
5365 if (intel_crtc->config->has_pch_encoder)
5366 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5367 else
5368 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5369
5370 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5371
5372 if (intel_crtc->config->has_pch_encoder)
5373 dev_priv->display.fdi_link_train(crtc);
5374
5375 if (!transcoder_is_dsi(cpu_transcoder))
5376 intel_ddi_enable_pipe_clock(intel_crtc);
5377
5378 if (INTEL_GEN(dev_priv) >= 9)
5379 skylake_pfit_enable(intel_crtc);
5380 else
5381 ironlake_pfit_enable(intel_crtc);
5382
5383 /*
5384 * On ILK+ LUT must be loaded before the pipe is running but with
5385 * clocks enabled
5386 */
5387 intel_color_load_luts(&pipe_config->base);
5388
5389 intel_ddi_set_pipe_settings(crtc);
5390 if (!transcoder_is_dsi(cpu_transcoder))
5391 intel_ddi_enable_transcoder_func(crtc);
5392
5393 if (dev_priv->display.initial_watermarks != NULL)
5394 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5395
5396 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5397 if (!transcoder_is_dsi(cpu_transcoder))
5398 intel_enable_pipe(intel_crtc);
5399
5400 if (intel_crtc->config->has_pch_encoder)
5401 lpt_pch_enable(crtc);
5402
5403 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5404 intel_ddi_set_vc_payload_alloc(crtc, true);
5405
5406 assert_vblank_disabled(crtc);
5407 drm_crtc_vblank_on(crtc);
5408
5409 intel_encoders_enable(crtc, pipe_config, old_state);
5410
5411 if (intel_crtc->config->has_pch_encoder) {
5412 intel_wait_for_vblank(dev_priv, pipe);
5413 intel_wait_for_vblank(dev_priv, pipe);
5414 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5415 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5416 true);
5417 }
5418
5419 /* If we change the relative order between pipe/planes enabling, we need
5420 * to change the workaround. */
5421 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5422 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5423 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5424 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5425 }
5426 }
5427
5428 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5429 {
5430 struct drm_device *dev = crtc->base.dev;
5431 struct drm_i915_private *dev_priv = to_i915(dev);
5432 int pipe = crtc->pipe;
5433
5434 /* To avoid upsetting the power well on haswell only disable the pfit if
5435 * it's in use. The hw state code will make sure we get this right. */
5436 if (force || crtc->config->pch_pfit.enabled) {
5437 I915_WRITE(PF_CTL(pipe), 0);
5438 I915_WRITE(PF_WIN_POS(pipe), 0);
5439 I915_WRITE(PF_WIN_SZ(pipe), 0);
5440 }
5441 }
5442
5443 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5444 struct drm_atomic_state *old_state)
5445 {
5446 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5447 struct drm_device *dev = crtc->dev;
5448 struct drm_i915_private *dev_priv = to_i915(dev);
5449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5450 int pipe = intel_crtc->pipe;
5451
5452 /*
5453 * Sometimes spurious CPU pipe underruns happen when the
5454 * pipe is already disabled, but FDI RX/TX is still enabled.
5455 * Happens at least with VGA+HDMI cloning. Suppress them.
5456 */
5457 if (intel_crtc->config->has_pch_encoder) {
5458 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5459 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5460 }
5461
5462 intel_encoders_disable(crtc, old_crtc_state, old_state);
5463
5464 drm_crtc_vblank_off(crtc);
5465 assert_vblank_disabled(crtc);
5466
5467 intel_disable_pipe(intel_crtc);
5468
5469 ironlake_pfit_disable(intel_crtc, false);
5470
5471 if (intel_crtc->config->has_pch_encoder)
5472 ironlake_fdi_disable(crtc);
5473
5474 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5475
5476 if (intel_crtc->config->has_pch_encoder) {
5477 ironlake_disable_pch_transcoder(dev_priv, pipe);
5478
5479 if (HAS_PCH_CPT(dev_priv)) {
5480 i915_reg_t reg;
5481 u32 temp;
5482
5483 /* disable TRANS_DP_CTL */
5484 reg = TRANS_DP_CTL(pipe);
5485 temp = I915_READ(reg);
5486 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5487 TRANS_DP_PORT_SEL_MASK);
5488 temp |= TRANS_DP_PORT_SEL_NONE;
5489 I915_WRITE(reg, temp);
5490
5491 /* disable DPLL_SEL */
5492 temp = I915_READ(PCH_DPLL_SEL);
5493 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5494 I915_WRITE(PCH_DPLL_SEL, temp);
5495 }
5496
5497 ironlake_fdi_pll_disable(intel_crtc);
5498 }
5499
5500 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5501 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5502 }
5503
5504 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5505 struct drm_atomic_state *old_state)
5506 {
5507 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5508 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5510 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5511
5512 if (intel_crtc->config->has_pch_encoder)
5513 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5514 false);
5515
5516 intel_encoders_disable(crtc, old_crtc_state, old_state);
5517
5518 drm_crtc_vblank_off(crtc);
5519 assert_vblank_disabled(crtc);
5520
5521 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5522 if (!transcoder_is_dsi(cpu_transcoder))
5523 intel_disable_pipe(intel_crtc);
5524
5525 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5526 intel_ddi_set_vc_payload_alloc(crtc, false);
5527
5528 if (!transcoder_is_dsi(cpu_transcoder))
5529 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5530
5531 if (INTEL_GEN(dev_priv) >= 9)
5532 skylake_scaler_disable(intel_crtc);
5533 else
5534 ironlake_pfit_disable(intel_crtc, false);
5535
5536 if (!transcoder_is_dsi(cpu_transcoder))
5537 intel_ddi_disable_pipe_clock(intel_crtc);
5538
5539 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5540
5541 if (old_crtc_state->has_pch_encoder)
5542 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5543 true);
5544 }
5545
5546 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5547 {
5548 struct drm_device *dev = crtc->base.dev;
5549 struct drm_i915_private *dev_priv = to_i915(dev);
5550 struct intel_crtc_state *pipe_config = crtc->config;
5551
5552 if (!pipe_config->gmch_pfit.control)
5553 return;
5554
5555 /*
5556 * The panel fitter should only be adjusted whilst the pipe is disabled,
5557 * according to register description and PRM.
5558 */
5559 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5560 assert_pipe_disabled(dev_priv, crtc->pipe);
5561
5562 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5563 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5564
5565 /* Border color in case we don't scale up to the full screen. Black by
5566 * default, change to something else for debugging. */
5567 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5568 }
5569
5570 static enum intel_display_power_domain port_to_power_domain(enum port port)
5571 {
5572 switch (port) {
5573 case PORT_A:
5574 return POWER_DOMAIN_PORT_DDI_A_LANES;
5575 case PORT_B:
5576 return POWER_DOMAIN_PORT_DDI_B_LANES;
5577 case PORT_C:
5578 return POWER_DOMAIN_PORT_DDI_C_LANES;
5579 case PORT_D:
5580 return POWER_DOMAIN_PORT_DDI_D_LANES;
5581 case PORT_E:
5582 return POWER_DOMAIN_PORT_DDI_E_LANES;
5583 default:
5584 MISSING_CASE(port);
5585 return POWER_DOMAIN_PORT_OTHER;
5586 }
5587 }
5588
5589 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5590 {
5591 switch (port) {
5592 case PORT_A:
5593 return POWER_DOMAIN_AUX_A;
5594 case PORT_B:
5595 return POWER_DOMAIN_AUX_B;
5596 case PORT_C:
5597 return POWER_DOMAIN_AUX_C;
5598 case PORT_D:
5599 return POWER_DOMAIN_AUX_D;
5600 case PORT_E:
5601 /* FIXME: Check VBT for actual wiring of PORT E */
5602 return POWER_DOMAIN_AUX_D;
5603 default:
5604 MISSING_CASE(port);
5605 return POWER_DOMAIN_AUX_A;
5606 }
5607 }
5608
5609 enum intel_display_power_domain
5610 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5611 {
5612 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5613 struct intel_digital_port *intel_dig_port;
5614
5615 switch (intel_encoder->type) {
5616 case INTEL_OUTPUT_UNKNOWN:
5617 /* Only DDI platforms should ever use this output type */
5618 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5619 case INTEL_OUTPUT_DP:
5620 case INTEL_OUTPUT_HDMI:
5621 case INTEL_OUTPUT_EDP:
5622 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5623 return port_to_power_domain(intel_dig_port->port);
5624 case INTEL_OUTPUT_DP_MST:
5625 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5626 return port_to_power_domain(intel_dig_port->port);
5627 case INTEL_OUTPUT_ANALOG:
5628 return POWER_DOMAIN_PORT_CRT;
5629 case INTEL_OUTPUT_DSI:
5630 return POWER_DOMAIN_PORT_DSI;
5631 default:
5632 return POWER_DOMAIN_PORT_OTHER;
5633 }
5634 }
5635
5636 enum intel_display_power_domain
5637 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5638 {
5639 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5640 struct intel_digital_port *intel_dig_port;
5641
5642 switch (intel_encoder->type) {
5643 case INTEL_OUTPUT_UNKNOWN:
5644 case INTEL_OUTPUT_HDMI:
5645 /*
5646 * Only DDI platforms should ever use these output types.
5647 * We can get here after the HDMI detect code has already set
5648 * the type of the shared encoder. Since we can't be sure
5649 * what's the status of the given connectors, play safe and
5650 * run the DP detection too.
5651 */
5652 WARN_ON_ONCE(!HAS_DDI(dev_priv));
5653 case INTEL_OUTPUT_DP:
5654 case INTEL_OUTPUT_EDP:
5655 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5656 return port_to_aux_power_domain(intel_dig_port->port);
5657 case INTEL_OUTPUT_DP_MST:
5658 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5659 return port_to_aux_power_domain(intel_dig_port->port);
5660 default:
5661 MISSING_CASE(intel_encoder->type);
5662 return POWER_DOMAIN_AUX_A;
5663 }
5664 }
5665
5666 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5667 struct intel_crtc_state *crtc_state)
5668 {
5669 struct drm_device *dev = crtc->dev;
5670 struct drm_i915_private *dev_priv = to_i915(dev);
5671 struct drm_encoder *encoder;
5672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5673 enum pipe pipe = intel_crtc->pipe;
5674 u64 mask;
5675 enum transcoder transcoder = crtc_state->cpu_transcoder;
5676
5677 if (!crtc_state->base.active)
5678 return 0;
5679
5680 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5681 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5682 if (crtc_state->pch_pfit.enabled ||
5683 crtc_state->pch_pfit.force_thru)
5684 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5685
5686 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5687 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5688
5689 mask |= BIT_ULL(intel_display_port_power_domain(intel_encoder));
5690 }
5691
5692 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5693 mask |= BIT(POWER_DOMAIN_AUDIO);
5694
5695 if (crtc_state->shared_dpll)
5696 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5697
5698 return mask;
5699 }
5700
5701 static u64
5702 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5703 struct intel_crtc_state *crtc_state)
5704 {
5705 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5707 enum intel_display_power_domain domain;
5708 u64 domains, new_domains, old_domains;
5709
5710 old_domains = intel_crtc->enabled_power_domains;
5711 intel_crtc->enabled_power_domains = new_domains =
5712 get_crtc_power_domains(crtc, crtc_state);
5713
5714 domains = new_domains & ~old_domains;
5715
5716 for_each_power_domain(domain, domains)
5717 intel_display_power_get(dev_priv, domain);
5718
5719 return old_domains & ~new_domains;
5720 }
5721
5722 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5723 u64 domains)
5724 {
5725 enum intel_display_power_domain domain;
5726
5727 for_each_power_domain(domain, domains)
5728 intel_display_power_put(dev_priv, domain);
5729 }
5730
5731 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5732 struct drm_atomic_state *old_state)
5733 {
5734 struct drm_crtc *crtc = pipe_config->base.crtc;
5735 struct drm_device *dev = crtc->dev;
5736 struct drm_i915_private *dev_priv = to_i915(dev);
5737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5738 int pipe = intel_crtc->pipe;
5739
5740 if (WARN_ON(intel_crtc->active))
5741 return;
5742
5743 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5744 intel_dp_set_m_n(intel_crtc, M1_N1);
5745
5746 intel_set_pipe_timings(intel_crtc);
5747 intel_set_pipe_src_size(intel_crtc);
5748
5749 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5750 struct drm_i915_private *dev_priv = to_i915(dev);
5751
5752 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5753 I915_WRITE(CHV_CANVAS(pipe), 0);
5754 }
5755
5756 i9xx_set_pipeconf(intel_crtc);
5757
5758 intel_crtc->active = true;
5759
5760 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5761
5762 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5763
5764 if (IS_CHERRYVIEW(dev_priv)) {
5765 chv_prepare_pll(intel_crtc, intel_crtc->config);
5766 chv_enable_pll(intel_crtc, intel_crtc->config);
5767 } else {
5768 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5769 vlv_enable_pll(intel_crtc, intel_crtc->config);
5770 }
5771
5772 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5773
5774 i9xx_pfit_enable(intel_crtc);
5775
5776 intel_color_load_luts(&pipe_config->base);
5777
5778 intel_update_watermarks(intel_crtc);
5779 intel_enable_pipe(intel_crtc);
5780
5781 assert_vblank_disabled(crtc);
5782 drm_crtc_vblank_on(crtc);
5783
5784 intel_encoders_enable(crtc, pipe_config, old_state);
5785 }
5786
5787 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5788 {
5789 struct drm_device *dev = crtc->base.dev;
5790 struct drm_i915_private *dev_priv = to_i915(dev);
5791
5792 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5793 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5794 }
5795
5796 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5797 struct drm_atomic_state *old_state)
5798 {
5799 struct drm_crtc *crtc = pipe_config->base.crtc;
5800 struct drm_device *dev = crtc->dev;
5801 struct drm_i915_private *dev_priv = to_i915(dev);
5802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5803 enum pipe pipe = intel_crtc->pipe;
5804
5805 if (WARN_ON(intel_crtc->active))
5806 return;
5807
5808 i9xx_set_pll_dividers(intel_crtc);
5809
5810 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5811 intel_dp_set_m_n(intel_crtc, M1_N1);
5812
5813 intel_set_pipe_timings(intel_crtc);
5814 intel_set_pipe_src_size(intel_crtc);
5815
5816 i9xx_set_pipeconf(intel_crtc);
5817
5818 intel_crtc->active = true;
5819
5820 if (!IS_GEN2(dev_priv))
5821 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5822
5823 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5824
5825 i9xx_enable_pll(intel_crtc);
5826
5827 i9xx_pfit_enable(intel_crtc);
5828
5829 intel_color_load_luts(&pipe_config->base);
5830
5831 intel_update_watermarks(intel_crtc);
5832 intel_enable_pipe(intel_crtc);
5833
5834 assert_vblank_disabled(crtc);
5835 drm_crtc_vblank_on(crtc);
5836
5837 intel_encoders_enable(crtc, pipe_config, old_state);
5838 }
5839
5840 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5841 {
5842 struct drm_device *dev = crtc->base.dev;
5843 struct drm_i915_private *dev_priv = to_i915(dev);
5844
5845 if (!crtc->config->gmch_pfit.control)
5846 return;
5847
5848 assert_pipe_disabled(dev_priv, crtc->pipe);
5849
5850 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5851 I915_READ(PFIT_CONTROL));
5852 I915_WRITE(PFIT_CONTROL, 0);
5853 }
5854
5855 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5856 struct drm_atomic_state *old_state)
5857 {
5858 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5859 struct drm_device *dev = crtc->dev;
5860 struct drm_i915_private *dev_priv = to_i915(dev);
5861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5862 int pipe = intel_crtc->pipe;
5863
5864 /*
5865 * On gen2 planes are double buffered but the pipe isn't, so we must
5866 * wait for planes to fully turn off before disabling the pipe.
5867 */
5868 if (IS_GEN2(dev_priv))
5869 intel_wait_for_vblank(dev_priv, pipe);
5870
5871 intel_encoders_disable(crtc, old_crtc_state, old_state);
5872
5873 drm_crtc_vblank_off(crtc);
5874 assert_vblank_disabled(crtc);
5875
5876 intel_disable_pipe(intel_crtc);
5877
5878 i9xx_pfit_disable(intel_crtc);
5879
5880 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5881
5882 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5883 if (IS_CHERRYVIEW(dev_priv))
5884 chv_disable_pll(dev_priv, pipe);
5885 else if (IS_VALLEYVIEW(dev_priv))
5886 vlv_disable_pll(dev_priv, pipe);
5887 else
5888 i9xx_disable_pll(intel_crtc);
5889 }
5890
5891 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5892
5893 if (!IS_GEN2(dev_priv))
5894 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5895 }
5896
5897 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5898 {
5899 struct intel_encoder *encoder;
5900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5901 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5902 enum intel_display_power_domain domain;
5903 u64 domains;
5904 struct drm_atomic_state *state;
5905 struct intel_crtc_state *crtc_state;
5906 int ret;
5907
5908 if (!intel_crtc->active)
5909 return;
5910
5911 if (crtc->primary->state->visible) {
5912 WARN_ON(intel_crtc->flip_work);
5913
5914 intel_pre_disable_primary_noatomic(crtc);
5915
5916 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5917 crtc->primary->state->visible = false;
5918 }
5919
5920 state = drm_atomic_state_alloc(crtc->dev);
5921 if (!state) {
5922 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5923 crtc->base.id, crtc->name);
5924 return;
5925 }
5926
5927 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5928
5929 /* Everything's already locked, -EDEADLK can't happen. */
5930 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5931 ret = drm_atomic_add_affected_connectors(state, crtc);
5932
5933 WARN_ON(IS_ERR(crtc_state) || ret);
5934
5935 dev_priv->display.crtc_disable(crtc_state, state);
5936
5937 drm_atomic_state_put(state);
5938
5939 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5940 crtc->base.id, crtc->name);
5941
5942 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5943 crtc->state->active = false;
5944 intel_crtc->active = false;
5945 crtc->enabled = false;
5946 crtc->state->connector_mask = 0;
5947 crtc->state->encoder_mask = 0;
5948
5949 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5950 encoder->base.crtc = NULL;
5951
5952 intel_fbc_disable(intel_crtc);
5953 intel_update_watermarks(intel_crtc);
5954 intel_disable_shared_dpll(intel_crtc);
5955
5956 domains = intel_crtc->enabled_power_domains;
5957 for_each_power_domain(domain, domains)
5958 intel_display_power_put(dev_priv, domain);
5959 intel_crtc->enabled_power_domains = 0;
5960
5961 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5962 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5963 }
5964
5965 /*
5966 * turn all crtc's off, but do not adjust state
5967 * This has to be paired with a call to intel_modeset_setup_hw_state.
5968 */
5969 int intel_display_suspend(struct drm_device *dev)
5970 {
5971 struct drm_i915_private *dev_priv = to_i915(dev);
5972 struct drm_atomic_state *state;
5973 int ret;
5974
5975 state = drm_atomic_helper_suspend(dev);
5976 ret = PTR_ERR_OR_ZERO(state);
5977 if (ret)
5978 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5979 else
5980 dev_priv->modeset_restore_state = state;
5981 return ret;
5982 }
5983
5984 void intel_encoder_destroy(struct drm_encoder *encoder)
5985 {
5986 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5987
5988 drm_encoder_cleanup(encoder);
5989 kfree(intel_encoder);
5990 }
5991
5992 /* Cross check the actual hw state with our own modeset state tracking (and it's
5993 * internal consistency). */
5994 static void intel_connector_verify_state(struct intel_connector *connector)
5995 {
5996 struct drm_crtc *crtc = connector->base.state->crtc;
5997
5998 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5999 connector->base.base.id,
6000 connector->base.name);
6001
6002 if (connector->get_hw_state(connector)) {
6003 struct intel_encoder *encoder = connector->encoder;
6004 struct drm_connector_state *conn_state = connector->base.state;
6005
6006 I915_STATE_WARN(!crtc,
6007 "connector enabled without attached crtc\n");
6008
6009 if (!crtc)
6010 return;
6011
6012 I915_STATE_WARN(!crtc->state->active,
6013 "connector is active, but attached crtc isn't\n");
6014
6015 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6016 return;
6017
6018 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6019 "atomic encoder doesn't match attached encoder\n");
6020
6021 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6022 "attached encoder crtc differs from connector crtc\n");
6023 } else {
6024 I915_STATE_WARN(crtc && crtc->state->active,
6025 "attached crtc is active, but connector isn't\n");
6026 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6027 "best encoder set without crtc!\n");
6028 }
6029 }
6030
6031 int intel_connector_init(struct intel_connector *connector)
6032 {
6033 drm_atomic_helper_connector_reset(&connector->base);
6034
6035 if (!connector->base.state)
6036 return -ENOMEM;
6037
6038 return 0;
6039 }
6040
6041 struct intel_connector *intel_connector_alloc(void)
6042 {
6043 struct intel_connector *connector;
6044
6045 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6046 if (!connector)
6047 return NULL;
6048
6049 if (intel_connector_init(connector) < 0) {
6050 kfree(connector);
6051 return NULL;
6052 }
6053
6054 return connector;
6055 }
6056
6057 /* Simple connector->get_hw_state implementation for encoders that support only
6058 * one connector and no cloning and hence the encoder state determines the state
6059 * of the connector. */
6060 bool intel_connector_get_hw_state(struct intel_connector *connector)
6061 {
6062 enum pipe pipe = 0;
6063 struct intel_encoder *encoder = connector->encoder;
6064
6065 return encoder->get_hw_state(encoder, &pipe);
6066 }
6067
6068 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6069 {
6070 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6071 return crtc_state->fdi_lanes;
6072
6073 return 0;
6074 }
6075
6076 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6077 struct intel_crtc_state *pipe_config)
6078 {
6079 struct drm_i915_private *dev_priv = to_i915(dev);
6080 struct drm_atomic_state *state = pipe_config->base.state;
6081 struct intel_crtc *other_crtc;
6082 struct intel_crtc_state *other_crtc_state;
6083
6084 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6085 pipe_name(pipe), pipe_config->fdi_lanes);
6086 if (pipe_config->fdi_lanes > 4) {
6087 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6088 pipe_name(pipe), pipe_config->fdi_lanes);
6089 return -EINVAL;
6090 }
6091
6092 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6093 if (pipe_config->fdi_lanes > 2) {
6094 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6095 pipe_config->fdi_lanes);
6096 return -EINVAL;
6097 } else {
6098 return 0;
6099 }
6100 }
6101
6102 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6103 return 0;
6104
6105 /* Ivybridge 3 pipe is really complicated */
6106 switch (pipe) {
6107 case PIPE_A:
6108 return 0;
6109 case PIPE_B:
6110 if (pipe_config->fdi_lanes <= 2)
6111 return 0;
6112
6113 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6114 other_crtc_state =
6115 intel_atomic_get_crtc_state(state, other_crtc);
6116 if (IS_ERR(other_crtc_state))
6117 return PTR_ERR(other_crtc_state);
6118
6119 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6120 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6121 pipe_name(pipe), pipe_config->fdi_lanes);
6122 return -EINVAL;
6123 }
6124 return 0;
6125 case PIPE_C:
6126 if (pipe_config->fdi_lanes > 2) {
6127 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6128 pipe_name(pipe), pipe_config->fdi_lanes);
6129 return -EINVAL;
6130 }
6131
6132 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6133 other_crtc_state =
6134 intel_atomic_get_crtc_state(state, other_crtc);
6135 if (IS_ERR(other_crtc_state))
6136 return PTR_ERR(other_crtc_state);
6137
6138 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6139 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6140 return -EINVAL;
6141 }
6142 return 0;
6143 default:
6144 BUG();
6145 }
6146 }
6147
6148 #define RETRY 1
6149 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6150 struct intel_crtc_state *pipe_config)
6151 {
6152 struct drm_device *dev = intel_crtc->base.dev;
6153 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6154 int lane, link_bw, fdi_dotclock, ret;
6155 bool needs_recompute = false;
6156
6157 retry:
6158 /* FDI is a binary signal running at ~2.7GHz, encoding
6159 * each output octet as 10 bits. The actual frequency
6160 * is stored as a divider into a 100MHz clock, and the
6161 * mode pixel clock is stored in units of 1KHz.
6162 * Hence the bw of each lane in terms of the mode signal
6163 * is:
6164 */
6165 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6166
6167 fdi_dotclock = adjusted_mode->crtc_clock;
6168
6169 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6170 pipe_config->pipe_bpp);
6171
6172 pipe_config->fdi_lanes = lane;
6173
6174 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6175 link_bw, &pipe_config->fdi_m_n);
6176
6177 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6178 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6179 pipe_config->pipe_bpp -= 2*3;
6180 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6181 pipe_config->pipe_bpp);
6182 needs_recompute = true;
6183 pipe_config->bw_constrained = true;
6184
6185 goto retry;
6186 }
6187
6188 if (needs_recompute)
6189 return RETRY;
6190
6191 return ret;
6192 }
6193
6194 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6195 struct intel_crtc_state *pipe_config)
6196 {
6197 if (pipe_config->pipe_bpp > 24)
6198 return false;
6199
6200 /* HSW can handle pixel rate up to cdclk? */
6201 if (IS_HASWELL(dev_priv))
6202 return true;
6203
6204 /*
6205 * We compare against max which means we must take
6206 * the increased cdclk requirement into account when
6207 * calculating the new cdclk.
6208 *
6209 * Should measure whether using a lower cdclk w/o IPS
6210 */
6211 return pipe_config->pixel_rate <=
6212 dev_priv->max_cdclk_freq * 95 / 100;
6213 }
6214
6215 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6216 struct intel_crtc_state *pipe_config)
6217 {
6218 struct drm_device *dev = crtc->base.dev;
6219 struct drm_i915_private *dev_priv = to_i915(dev);
6220
6221 pipe_config->ips_enabled = i915.enable_ips &&
6222 hsw_crtc_supports_ips(crtc) &&
6223 pipe_config_supports_ips(dev_priv, pipe_config);
6224 }
6225
6226 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6227 {
6228 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6229
6230 /* GDG double wide on either pipe, otherwise pipe A only */
6231 return INTEL_INFO(dev_priv)->gen < 4 &&
6232 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6233 }
6234
6235 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6236 {
6237 uint32_t pixel_rate;
6238
6239 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6240
6241 /*
6242 * We only use IF-ID interlacing. If we ever use
6243 * PF-ID we'll need to adjust the pixel_rate here.
6244 */
6245
6246 if (pipe_config->pch_pfit.enabled) {
6247 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6248 uint32_t pfit_size = pipe_config->pch_pfit.size;
6249
6250 pipe_w = pipe_config->pipe_src_w;
6251 pipe_h = pipe_config->pipe_src_h;
6252
6253 pfit_w = (pfit_size >> 16) & 0xFFFF;
6254 pfit_h = pfit_size & 0xFFFF;
6255 if (pipe_w < pfit_w)
6256 pipe_w = pfit_w;
6257 if (pipe_h < pfit_h)
6258 pipe_h = pfit_h;
6259
6260 if (WARN_ON(!pfit_w || !pfit_h))
6261 return pixel_rate;
6262
6263 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6264 pfit_w * pfit_h);
6265 }
6266
6267 return pixel_rate;
6268 }
6269
6270 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6271 {
6272 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6273
6274 if (HAS_GMCH_DISPLAY(dev_priv))
6275 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6276 crtc_state->pixel_rate =
6277 crtc_state->base.adjusted_mode.crtc_clock;
6278 else
6279 crtc_state->pixel_rate =
6280 ilk_pipe_pixel_rate(crtc_state);
6281 }
6282
6283 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6284 struct intel_crtc_state *pipe_config)
6285 {
6286 struct drm_device *dev = crtc->base.dev;
6287 struct drm_i915_private *dev_priv = to_i915(dev);
6288 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6289 int clock_limit = dev_priv->max_dotclk_freq;
6290
6291 if (INTEL_GEN(dev_priv) < 4) {
6292 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6293
6294 /*
6295 * Enable double wide mode when the dot clock
6296 * is > 90% of the (display) core speed.
6297 */
6298 if (intel_crtc_supports_double_wide(crtc) &&
6299 adjusted_mode->crtc_clock > clock_limit) {
6300 clock_limit = dev_priv->max_dotclk_freq;
6301 pipe_config->double_wide = true;
6302 }
6303 }
6304
6305 if (adjusted_mode->crtc_clock > clock_limit) {
6306 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6307 adjusted_mode->crtc_clock, clock_limit,
6308 yesno(pipe_config->double_wide));
6309 return -EINVAL;
6310 }
6311
6312 /*
6313 * Pipe horizontal size must be even in:
6314 * - DVO ganged mode
6315 * - LVDS dual channel mode
6316 * - Double wide pipe
6317 */
6318 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6319 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6320 pipe_config->pipe_src_w &= ~1;
6321
6322 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6323 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6324 */
6325 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6326 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6327 return -EINVAL;
6328
6329 intel_crtc_compute_pixel_rate(pipe_config);
6330
6331 if (HAS_IPS(dev_priv))
6332 hsw_compute_ips_config(crtc, pipe_config);
6333
6334 if (pipe_config->has_pch_encoder)
6335 return ironlake_fdi_compute_config(crtc, pipe_config);
6336
6337 return 0;
6338 }
6339
6340 static void
6341 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6342 {
6343 while (*num > DATA_LINK_M_N_MASK ||
6344 *den > DATA_LINK_M_N_MASK) {
6345 *num >>= 1;
6346 *den >>= 1;
6347 }
6348 }
6349
6350 static void compute_m_n(unsigned int m, unsigned int n,
6351 uint32_t *ret_m, uint32_t *ret_n)
6352 {
6353 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6354 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6355 intel_reduce_m_n_ratio(ret_m, ret_n);
6356 }
6357
6358 void
6359 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6360 int pixel_clock, int link_clock,
6361 struct intel_link_m_n *m_n)
6362 {
6363 m_n->tu = 64;
6364
6365 compute_m_n(bits_per_pixel * pixel_clock,
6366 link_clock * nlanes * 8,
6367 &m_n->gmch_m, &m_n->gmch_n);
6368
6369 compute_m_n(pixel_clock, link_clock,
6370 &m_n->link_m, &m_n->link_n);
6371 }
6372
6373 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6374 {
6375 if (i915.panel_use_ssc >= 0)
6376 return i915.panel_use_ssc != 0;
6377 return dev_priv->vbt.lvds_use_ssc
6378 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6379 }
6380
6381 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6382 {
6383 return (1 << dpll->n) << 16 | dpll->m2;
6384 }
6385
6386 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6387 {
6388 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6389 }
6390
6391 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6392 struct intel_crtc_state *crtc_state,
6393 struct dpll *reduced_clock)
6394 {
6395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6396 u32 fp, fp2 = 0;
6397
6398 if (IS_PINEVIEW(dev_priv)) {
6399 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6400 if (reduced_clock)
6401 fp2 = pnv_dpll_compute_fp(reduced_clock);
6402 } else {
6403 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6404 if (reduced_clock)
6405 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6406 }
6407
6408 crtc_state->dpll_hw_state.fp0 = fp;
6409
6410 crtc->lowfreq_avail = false;
6411 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6412 reduced_clock) {
6413 crtc_state->dpll_hw_state.fp1 = fp2;
6414 crtc->lowfreq_avail = true;
6415 } else {
6416 crtc_state->dpll_hw_state.fp1 = fp;
6417 }
6418 }
6419
6420 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6421 pipe)
6422 {
6423 u32 reg_val;
6424
6425 /*
6426 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6427 * and set it to a reasonable value instead.
6428 */
6429 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6430 reg_val &= 0xffffff00;
6431 reg_val |= 0x00000030;
6432 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6433
6434 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6435 reg_val &= 0x8cffffff;
6436 reg_val = 0x8c000000;
6437 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6438
6439 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6440 reg_val &= 0xffffff00;
6441 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6442
6443 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6444 reg_val &= 0x00ffffff;
6445 reg_val |= 0xb0000000;
6446 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6447 }
6448
6449 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6450 struct intel_link_m_n *m_n)
6451 {
6452 struct drm_device *dev = crtc->base.dev;
6453 struct drm_i915_private *dev_priv = to_i915(dev);
6454 int pipe = crtc->pipe;
6455
6456 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6457 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6458 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6459 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6460 }
6461
6462 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6463 struct intel_link_m_n *m_n,
6464 struct intel_link_m_n *m2_n2)
6465 {
6466 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6467 int pipe = crtc->pipe;
6468 enum transcoder transcoder = crtc->config->cpu_transcoder;
6469
6470 if (INTEL_GEN(dev_priv) >= 5) {
6471 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6472 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6473 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6474 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6475 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6476 * for gen < 8) and if DRRS is supported (to make sure the
6477 * registers are not unnecessarily accessed).
6478 */
6479 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6480 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6481 I915_WRITE(PIPE_DATA_M2(transcoder),
6482 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6483 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6484 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6485 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6486 }
6487 } else {
6488 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6489 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6490 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6491 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6492 }
6493 }
6494
6495 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6496 {
6497 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6498
6499 if (m_n == M1_N1) {
6500 dp_m_n = &crtc->config->dp_m_n;
6501 dp_m2_n2 = &crtc->config->dp_m2_n2;
6502 } else if (m_n == M2_N2) {
6503
6504 /*
6505 * M2_N2 registers are not supported. Hence m2_n2 divider value
6506 * needs to be programmed into M1_N1.
6507 */
6508 dp_m_n = &crtc->config->dp_m2_n2;
6509 } else {
6510 DRM_ERROR("Unsupported divider value\n");
6511 return;
6512 }
6513
6514 if (crtc->config->has_pch_encoder)
6515 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6516 else
6517 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6518 }
6519
6520 static void vlv_compute_dpll(struct intel_crtc *crtc,
6521 struct intel_crtc_state *pipe_config)
6522 {
6523 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6524 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6525 if (crtc->pipe != PIPE_A)
6526 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6527
6528 /* DPLL not used with DSI, but still need the rest set up */
6529 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6530 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6531 DPLL_EXT_BUFFER_ENABLE_VLV;
6532
6533 pipe_config->dpll_hw_state.dpll_md =
6534 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6535 }
6536
6537 static void chv_compute_dpll(struct intel_crtc *crtc,
6538 struct intel_crtc_state *pipe_config)
6539 {
6540 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6541 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6542 if (crtc->pipe != PIPE_A)
6543 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6544
6545 /* DPLL not used with DSI, but still need the rest set up */
6546 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6547 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6548
6549 pipe_config->dpll_hw_state.dpll_md =
6550 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6551 }
6552
6553 static void vlv_prepare_pll(struct intel_crtc *crtc,
6554 const struct intel_crtc_state *pipe_config)
6555 {
6556 struct drm_device *dev = crtc->base.dev;
6557 struct drm_i915_private *dev_priv = to_i915(dev);
6558 enum pipe pipe = crtc->pipe;
6559 u32 mdiv;
6560 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6561 u32 coreclk, reg_val;
6562
6563 /* Enable Refclk */
6564 I915_WRITE(DPLL(pipe),
6565 pipe_config->dpll_hw_state.dpll &
6566 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6567
6568 /* No need to actually set up the DPLL with DSI */
6569 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6570 return;
6571
6572 mutex_lock(&dev_priv->sb_lock);
6573
6574 bestn = pipe_config->dpll.n;
6575 bestm1 = pipe_config->dpll.m1;
6576 bestm2 = pipe_config->dpll.m2;
6577 bestp1 = pipe_config->dpll.p1;
6578 bestp2 = pipe_config->dpll.p2;
6579
6580 /* See eDP HDMI DPIO driver vbios notes doc */
6581
6582 /* PLL B needs special handling */
6583 if (pipe == PIPE_B)
6584 vlv_pllb_recal_opamp(dev_priv, pipe);
6585
6586 /* Set up Tx target for periodic Rcomp update */
6587 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6588
6589 /* Disable target IRef on PLL */
6590 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6591 reg_val &= 0x00ffffff;
6592 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6593
6594 /* Disable fast lock */
6595 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6596
6597 /* Set idtafcrecal before PLL is enabled */
6598 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6599 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6600 mdiv |= ((bestn << DPIO_N_SHIFT));
6601 mdiv |= (1 << DPIO_K_SHIFT);
6602
6603 /*
6604 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6605 * but we don't support that).
6606 * Note: don't use the DAC post divider as it seems unstable.
6607 */
6608 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6609 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6610
6611 mdiv |= DPIO_ENABLE_CALIBRATION;
6612 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6613
6614 /* Set HBR and RBR LPF coefficients */
6615 if (pipe_config->port_clock == 162000 ||
6616 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6617 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6618 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6619 0x009f0003);
6620 else
6621 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6622 0x00d0000f);
6623
6624 if (intel_crtc_has_dp_encoder(pipe_config)) {
6625 /* Use SSC source */
6626 if (pipe == PIPE_A)
6627 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6628 0x0df40000);
6629 else
6630 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6631 0x0df70000);
6632 } else { /* HDMI or VGA */
6633 /* Use bend source */
6634 if (pipe == PIPE_A)
6635 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6636 0x0df70000);
6637 else
6638 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6639 0x0df40000);
6640 }
6641
6642 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6643 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6644 if (intel_crtc_has_dp_encoder(crtc->config))
6645 coreclk |= 0x01000000;
6646 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6647
6648 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6649 mutex_unlock(&dev_priv->sb_lock);
6650 }
6651
6652 static void chv_prepare_pll(struct intel_crtc *crtc,
6653 const struct intel_crtc_state *pipe_config)
6654 {
6655 struct drm_device *dev = crtc->base.dev;
6656 struct drm_i915_private *dev_priv = to_i915(dev);
6657 enum pipe pipe = crtc->pipe;
6658 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6659 u32 loopfilter, tribuf_calcntr;
6660 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6661 u32 dpio_val;
6662 int vco;
6663
6664 /* Enable Refclk and SSC */
6665 I915_WRITE(DPLL(pipe),
6666 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6667
6668 /* No need to actually set up the DPLL with DSI */
6669 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6670 return;
6671
6672 bestn = pipe_config->dpll.n;
6673 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6674 bestm1 = pipe_config->dpll.m1;
6675 bestm2 = pipe_config->dpll.m2 >> 22;
6676 bestp1 = pipe_config->dpll.p1;
6677 bestp2 = pipe_config->dpll.p2;
6678 vco = pipe_config->dpll.vco;
6679 dpio_val = 0;
6680 loopfilter = 0;
6681
6682 mutex_lock(&dev_priv->sb_lock);
6683
6684 /* p1 and p2 divider */
6685 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6686 5 << DPIO_CHV_S1_DIV_SHIFT |
6687 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6688 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6689 1 << DPIO_CHV_K_DIV_SHIFT);
6690
6691 /* Feedback post-divider - m2 */
6692 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6693
6694 /* Feedback refclk divider - n and m1 */
6695 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6696 DPIO_CHV_M1_DIV_BY_2 |
6697 1 << DPIO_CHV_N_DIV_SHIFT);
6698
6699 /* M2 fraction division */
6700 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6701
6702 /* M2 fraction division enable */
6703 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6704 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6705 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6706 if (bestm2_frac)
6707 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6708 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6709
6710 /* Program digital lock detect threshold */
6711 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6712 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6713 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6714 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6715 if (!bestm2_frac)
6716 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6717 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6718
6719 /* Loop filter */
6720 if (vco == 5400000) {
6721 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6722 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6723 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6724 tribuf_calcntr = 0x9;
6725 } else if (vco <= 6200000) {
6726 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6727 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6728 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6729 tribuf_calcntr = 0x9;
6730 } else if (vco <= 6480000) {
6731 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6732 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6733 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6734 tribuf_calcntr = 0x8;
6735 } else {
6736 /* Not supported. Apply the same limits as in the max case */
6737 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6738 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6739 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6740 tribuf_calcntr = 0;
6741 }
6742 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6743
6744 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6745 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6746 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6747 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6748
6749 /* AFC Recal */
6750 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6751 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6752 DPIO_AFC_RECAL);
6753
6754 mutex_unlock(&dev_priv->sb_lock);
6755 }
6756
6757 /**
6758 * vlv_force_pll_on - forcibly enable just the PLL
6759 * @dev_priv: i915 private structure
6760 * @pipe: pipe PLL to enable
6761 * @dpll: PLL configuration
6762 *
6763 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6764 * in cases where we need the PLL enabled even when @pipe is not going to
6765 * be enabled.
6766 */
6767 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6768 const struct dpll *dpll)
6769 {
6770 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6771 struct intel_crtc_state *pipe_config;
6772
6773 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6774 if (!pipe_config)
6775 return -ENOMEM;
6776
6777 pipe_config->base.crtc = &crtc->base;
6778 pipe_config->pixel_multiplier = 1;
6779 pipe_config->dpll = *dpll;
6780
6781 if (IS_CHERRYVIEW(dev_priv)) {
6782 chv_compute_dpll(crtc, pipe_config);
6783 chv_prepare_pll(crtc, pipe_config);
6784 chv_enable_pll(crtc, pipe_config);
6785 } else {
6786 vlv_compute_dpll(crtc, pipe_config);
6787 vlv_prepare_pll(crtc, pipe_config);
6788 vlv_enable_pll(crtc, pipe_config);
6789 }
6790
6791 kfree(pipe_config);
6792
6793 return 0;
6794 }
6795
6796 /**
6797 * vlv_force_pll_off - forcibly disable just the PLL
6798 * @dev_priv: i915 private structure
6799 * @pipe: pipe PLL to disable
6800 *
6801 * Disable the PLL for @pipe. To be used in cases where we need
6802 * the PLL enabled even when @pipe is not going to be enabled.
6803 */
6804 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6805 {
6806 if (IS_CHERRYVIEW(dev_priv))
6807 chv_disable_pll(dev_priv, pipe);
6808 else
6809 vlv_disable_pll(dev_priv, pipe);
6810 }
6811
6812 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6813 struct intel_crtc_state *crtc_state,
6814 struct dpll *reduced_clock)
6815 {
6816 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6817 u32 dpll;
6818 struct dpll *clock = &crtc_state->dpll;
6819
6820 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6821
6822 dpll = DPLL_VGA_MODE_DIS;
6823
6824 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6825 dpll |= DPLLB_MODE_LVDS;
6826 else
6827 dpll |= DPLLB_MODE_DAC_SERIAL;
6828
6829 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6830 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6831 dpll |= (crtc_state->pixel_multiplier - 1)
6832 << SDVO_MULTIPLIER_SHIFT_HIRES;
6833 }
6834
6835 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6836 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6837 dpll |= DPLL_SDVO_HIGH_SPEED;
6838
6839 if (intel_crtc_has_dp_encoder(crtc_state))
6840 dpll |= DPLL_SDVO_HIGH_SPEED;
6841
6842 /* compute bitmask from p1 value */
6843 if (IS_PINEVIEW(dev_priv))
6844 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6845 else {
6846 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6847 if (IS_G4X(dev_priv) && reduced_clock)
6848 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6849 }
6850 switch (clock->p2) {
6851 case 5:
6852 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6853 break;
6854 case 7:
6855 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6856 break;
6857 case 10:
6858 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6859 break;
6860 case 14:
6861 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6862 break;
6863 }
6864 if (INTEL_GEN(dev_priv) >= 4)
6865 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6866
6867 if (crtc_state->sdvo_tv_clock)
6868 dpll |= PLL_REF_INPUT_TVCLKINBC;
6869 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6870 intel_panel_use_ssc(dev_priv))
6871 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6872 else
6873 dpll |= PLL_REF_INPUT_DREFCLK;
6874
6875 dpll |= DPLL_VCO_ENABLE;
6876 crtc_state->dpll_hw_state.dpll = dpll;
6877
6878 if (INTEL_GEN(dev_priv) >= 4) {
6879 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6880 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6881 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6882 }
6883 }
6884
6885 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6886 struct intel_crtc_state *crtc_state,
6887 struct dpll *reduced_clock)
6888 {
6889 struct drm_device *dev = crtc->base.dev;
6890 struct drm_i915_private *dev_priv = to_i915(dev);
6891 u32 dpll;
6892 struct dpll *clock = &crtc_state->dpll;
6893
6894 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6895
6896 dpll = DPLL_VGA_MODE_DIS;
6897
6898 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6899 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6900 } else {
6901 if (clock->p1 == 2)
6902 dpll |= PLL_P1_DIVIDE_BY_TWO;
6903 else
6904 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6905 if (clock->p2 == 4)
6906 dpll |= PLL_P2_DIVIDE_BY_4;
6907 }
6908
6909 if (!IS_I830(dev_priv) &&
6910 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6911 dpll |= DPLL_DVO_2X_MODE;
6912
6913 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6914 intel_panel_use_ssc(dev_priv))
6915 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6916 else
6917 dpll |= PLL_REF_INPUT_DREFCLK;
6918
6919 dpll |= DPLL_VCO_ENABLE;
6920 crtc_state->dpll_hw_state.dpll = dpll;
6921 }
6922
6923 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6924 {
6925 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6926 enum pipe pipe = intel_crtc->pipe;
6927 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6928 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6929 uint32_t crtc_vtotal, crtc_vblank_end;
6930 int vsyncshift = 0;
6931
6932 /* We need to be careful not to changed the adjusted mode, for otherwise
6933 * the hw state checker will get angry at the mismatch. */
6934 crtc_vtotal = adjusted_mode->crtc_vtotal;
6935 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6936
6937 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6938 /* the chip adds 2 halflines automatically */
6939 crtc_vtotal -= 1;
6940 crtc_vblank_end -= 1;
6941
6942 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6943 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6944 else
6945 vsyncshift = adjusted_mode->crtc_hsync_start -
6946 adjusted_mode->crtc_htotal / 2;
6947 if (vsyncshift < 0)
6948 vsyncshift += adjusted_mode->crtc_htotal;
6949 }
6950
6951 if (INTEL_GEN(dev_priv) > 3)
6952 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6953
6954 I915_WRITE(HTOTAL(cpu_transcoder),
6955 (adjusted_mode->crtc_hdisplay - 1) |
6956 ((adjusted_mode->crtc_htotal - 1) << 16));
6957 I915_WRITE(HBLANK(cpu_transcoder),
6958 (adjusted_mode->crtc_hblank_start - 1) |
6959 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6960 I915_WRITE(HSYNC(cpu_transcoder),
6961 (adjusted_mode->crtc_hsync_start - 1) |
6962 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6963
6964 I915_WRITE(VTOTAL(cpu_transcoder),
6965 (adjusted_mode->crtc_vdisplay - 1) |
6966 ((crtc_vtotal - 1) << 16));
6967 I915_WRITE(VBLANK(cpu_transcoder),
6968 (adjusted_mode->crtc_vblank_start - 1) |
6969 ((crtc_vblank_end - 1) << 16));
6970 I915_WRITE(VSYNC(cpu_transcoder),
6971 (adjusted_mode->crtc_vsync_start - 1) |
6972 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6973
6974 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6975 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6976 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6977 * bits. */
6978 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6979 (pipe == PIPE_B || pipe == PIPE_C))
6980 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6981
6982 }
6983
6984 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6985 {
6986 struct drm_device *dev = intel_crtc->base.dev;
6987 struct drm_i915_private *dev_priv = to_i915(dev);
6988 enum pipe pipe = intel_crtc->pipe;
6989
6990 /* pipesrc controls the size that is scaled from, which should
6991 * always be the user's requested size.
6992 */
6993 I915_WRITE(PIPESRC(pipe),
6994 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6995 (intel_crtc->config->pipe_src_h - 1));
6996 }
6997
6998 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6999 struct intel_crtc_state *pipe_config)
7000 {
7001 struct drm_device *dev = crtc->base.dev;
7002 struct drm_i915_private *dev_priv = to_i915(dev);
7003 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7004 uint32_t tmp;
7005
7006 tmp = I915_READ(HTOTAL(cpu_transcoder));
7007 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7008 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7009 tmp = I915_READ(HBLANK(cpu_transcoder));
7010 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7011 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7012 tmp = I915_READ(HSYNC(cpu_transcoder));
7013 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7014 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7015
7016 tmp = I915_READ(VTOTAL(cpu_transcoder));
7017 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7018 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7019 tmp = I915_READ(VBLANK(cpu_transcoder));
7020 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7021 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7022 tmp = I915_READ(VSYNC(cpu_transcoder));
7023 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7024 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7025
7026 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7027 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7028 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7029 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7030 }
7031 }
7032
7033 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7034 struct intel_crtc_state *pipe_config)
7035 {
7036 struct drm_device *dev = crtc->base.dev;
7037 struct drm_i915_private *dev_priv = to_i915(dev);
7038 u32 tmp;
7039
7040 tmp = I915_READ(PIPESRC(crtc->pipe));
7041 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7042 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7043
7044 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7045 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7046 }
7047
7048 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7049 struct intel_crtc_state *pipe_config)
7050 {
7051 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7052 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7053 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7054 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7055
7056 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7057 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7058 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7059 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7060
7061 mode->flags = pipe_config->base.adjusted_mode.flags;
7062 mode->type = DRM_MODE_TYPE_DRIVER;
7063
7064 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7065
7066 mode->hsync = drm_mode_hsync(mode);
7067 mode->vrefresh = drm_mode_vrefresh(mode);
7068 drm_mode_set_name(mode);
7069 }
7070
7071 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7072 {
7073 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7074 uint32_t pipeconf;
7075
7076 pipeconf = 0;
7077
7078 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7079 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7080 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7081
7082 if (intel_crtc->config->double_wide)
7083 pipeconf |= PIPECONF_DOUBLE_WIDE;
7084
7085 /* only g4x and later have fancy bpc/dither controls */
7086 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7087 IS_CHERRYVIEW(dev_priv)) {
7088 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7089 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7090 pipeconf |= PIPECONF_DITHER_EN |
7091 PIPECONF_DITHER_TYPE_SP;
7092
7093 switch (intel_crtc->config->pipe_bpp) {
7094 case 18:
7095 pipeconf |= PIPECONF_6BPC;
7096 break;
7097 case 24:
7098 pipeconf |= PIPECONF_8BPC;
7099 break;
7100 case 30:
7101 pipeconf |= PIPECONF_10BPC;
7102 break;
7103 default:
7104 /* Case prevented by intel_choose_pipe_bpp_dither. */
7105 BUG();
7106 }
7107 }
7108
7109 if (HAS_PIPE_CXSR(dev_priv)) {
7110 if (intel_crtc->lowfreq_avail) {
7111 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7112 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7113 } else {
7114 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7115 }
7116 }
7117
7118 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7119 if (INTEL_GEN(dev_priv) < 4 ||
7120 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7121 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7122 else
7123 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7124 } else
7125 pipeconf |= PIPECONF_PROGRESSIVE;
7126
7127 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7128 intel_crtc->config->limited_color_range)
7129 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7130
7131 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7132 POSTING_READ(PIPECONF(intel_crtc->pipe));
7133 }
7134
7135 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7136 struct intel_crtc_state *crtc_state)
7137 {
7138 struct drm_device *dev = crtc->base.dev;
7139 struct drm_i915_private *dev_priv = to_i915(dev);
7140 const struct intel_limit *limit;
7141 int refclk = 48000;
7142
7143 memset(&crtc_state->dpll_hw_state, 0,
7144 sizeof(crtc_state->dpll_hw_state));
7145
7146 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7147 if (intel_panel_use_ssc(dev_priv)) {
7148 refclk = dev_priv->vbt.lvds_ssc_freq;
7149 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7150 }
7151
7152 limit = &intel_limits_i8xx_lvds;
7153 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7154 limit = &intel_limits_i8xx_dvo;
7155 } else {
7156 limit = &intel_limits_i8xx_dac;
7157 }
7158
7159 if (!crtc_state->clock_set &&
7160 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7161 refclk, NULL, &crtc_state->dpll)) {
7162 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7163 return -EINVAL;
7164 }
7165
7166 i8xx_compute_dpll(crtc, crtc_state, NULL);
7167
7168 return 0;
7169 }
7170
7171 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7172 struct intel_crtc_state *crtc_state)
7173 {
7174 struct drm_device *dev = crtc->base.dev;
7175 struct drm_i915_private *dev_priv = to_i915(dev);
7176 const struct intel_limit *limit;
7177 int refclk = 96000;
7178
7179 memset(&crtc_state->dpll_hw_state, 0,
7180 sizeof(crtc_state->dpll_hw_state));
7181
7182 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7183 if (intel_panel_use_ssc(dev_priv)) {
7184 refclk = dev_priv->vbt.lvds_ssc_freq;
7185 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7186 }
7187
7188 if (intel_is_dual_link_lvds(dev))
7189 limit = &intel_limits_g4x_dual_channel_lvds;
7190 else
7191 limit = &intel_limits_g4x_single_channel_lvds;
7192 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7193 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7194 limit = &intel_limits_g4x_hdmi;
7195 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7196 limit = &intel_limits_g4x_sdvo;
7197 } else {
7198 /* The option is for other outputs */
7199 limit = &intel_limits_i9xx_sdvo;
7200 }
7201
7202 if (!crtc_state->clock_set &&
7203 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7204 refclk, NULL, &crtc_state->dpll)) {
7205 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7206 return -EINVAL;
7207 }
7208
7209 i9xx_compute_dpll(crtc, crtc_state, NULL);
7210
7211 return 0;
7212 }
7213
7214 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7215 struct intel_crtc_state *crtc_state)
7216 {
7217 struct drm_device *dev = crtc->base.dev;
7218 struct drm_i915_private *dev_priv = to_i915(dev);
7219 const struct intel_limit *limit;
7220 int refclk = 96000;
7221
7222 memset(&crtc_state->dpll_hw_state, 0,
7223 sizeof(crtc_state->dpll_hw_state));
7224
7225 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7226 if (intel_panel_use_ssc(dev_priv)) {
7227 refclk = dev_priv->vbt.lvds_ssc_freq;
7228 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7229 }
7230
7231 limit = &intel_limits_pineview_lvds;
7232 } else {
7233 limit = &intel_limits_pineview_sdvo;
7234 }
7235
7236 if (!crtc_state->clock_set &&
7237 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7238 refclk, NULL, &crtc_state->dpll)) {
7239 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7240 return -EINVAL;
7241 }
7242
7243 i9xx_compute_dpll(crtc, crtc_state, NULL);
7244
7245 return 0;
7246 }
7247
7248 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7249 struct intel_crtc_state *crtc_state)
7250 {
7251 struct drm_device *dev = crtc->base.dev;
7252 struct drm_i915_private *dev_priv = to_i915(dev);
7253 const struct intel_limit *limit;
7254 int refclk = 96000;
7255
7256 memset(&crtc_state->dpll_hw_state, 0,
7257 sizeof(crtc_state->dpll_hw_state));
7258
7259 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7260 if (intel_panel_use_ssc(dev_priv)) {
7261 refclk = dev_priv->vbt.lvds_ssc_freq;
7262 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7263 }
7264
7265 limit = &intel_limits_i9xx_lvds;
7266 } else {
7267 limit = &intel_limits_i9xx_sdvo;
7268 }
7269
7270 if (!crtc_state->clock_set &&
7271 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7272 refclk, NULL, &crtc_state->dpll)) {
7273 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7274 return -EINVAL;
7275 }
7276
7277 i9xx_compute_dpll(crtc, crtc_state, NULL);
7278
7279 return 0;
7280 }
7281
7282 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7283 struct intel_crtc_state *crtc_state)
7284 {
7285 int refclk = 100000;
7286 const struct intel_limit *limit = &intel_limits_chv;
7287
7288 memset(&crtc_state->dpll_hw_state, 0,
7289 sizeof(crtc_state->dpll_hw_state));
7290
7291 if (!crtc_state->clock_set &&
7292 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7293 refclk, NULL, &crtc_state->dpll)) {
7294 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7295 return -EINVAL;
7296 }
7297
7298 chv_compute_dpll(crtc, crtc_state);
7299
7300 return 0;
7301 }
7302
7303 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7304 struct intel_crtc_state *crtc_state)
7305 {
7306 int refclk = 100000;
7307 const struct intel_limit *limit = &intel_limits_vlv;
7308
7309 memset(&crtc_state->dpll_hw_state, 0,
7310 sizeof(crtc_state->dpll_hw_state));
7311
7312 if (!crtc_state->clock_set &&
7313 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7314 refclk, NULL, &crtc_state->dpll)) {
7315 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7316 return -EINVAL;
7317 }
7318
7319 vlv_compute_dpll(crtc, crtc_state);
7320
7321 return 0;
7322 }
7323
7324 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7325 struct intel_crtc_state *pipe_config)
7326 {
7327 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7328 uint32_t tmp;
7329
7330 if (INTEL_GEN(dev_priv) <= 3 &&
7331 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7332 return;
7333
7334 tmp = I915_READ(PFIT_CONTROL);
7335 if (!(tmp & PFIT_ENABLE))
7336 return;
7337
7338 /* Check whether the pfit is attached to our pipe. */
7339 if (INTEL_GEN(dev_priv) < 4) {
7340 if (crtc->pipe != PIPE_B)
7341 return;
7342 } else {
7343 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7344 return;
7345 }
7346
7347 pipe_config->gmch_pfit.control = tmp;
7348 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7349 }
7350
7351 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7352 struct intel_crtc_state *pipe_config)
7353 {
7354 struct drm_device *dev = crtc->base.dev;
7355 struct drm_i915_private *dev_priv = to_i915(dev);
7356 int pipe = pipe_config->cpu_transcoder;
7357 struct dpll clock;
7358 u32 mdiv;
7359 int refclk = 100000;
7360
7361 /* In case of DSI, DPLL will not be used */
7362 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7363 return;
7364
7365 mutex_lock(&dev_priv->sb_lock);
7366 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7367 mutex_unlock(&dev_priv->sb_lock);
7368
7369 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7370 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7371 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7372 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7373 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7374
7375 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7376 }
7377
7378 static void
7379 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7380 struct intel_initial_plane_config *plane_config)
7381 {
7382 struct drm_device *dev = crtc->base.dev;
7383 struct drm_i915_private *dev_priv = to_i915(dev);
7384 u32 val, base, offset;
7385 int pipe = crtc->pipe, plane = crtc->plane;
7386 int fourcc, pixel_format;
7387 unsigned int aligned_height;
7388 struct drm_framebuffer *fb;
7389 struct intel_framebuffer *intel_fb;
7390
7391 val = I915_READ(DSPCNTR(plane));
7392 if (!(val & DISPLAY_PLANE_ENABLE))
7393 return;
7394
7395 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7396 if (!intel_fb) {
7397 DRM_DEBUG_KMS("failed to alloc fb\n");
7398 return;
7399 }
7400
7401 fb = &intel_fb->base;
7402
7403 fb->dev = dev;
7404
7405 if (INTEL_GEN(dev_priv) >= 4) {
7406 if (val & DISPPLANE_TILED) {
7407 plane_config->tiling = I915_TILING_X;
7408 fb->modifier = I915_FORMAT_MOD_X_TILED;
7409 }
7410 }
7411
7412 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7413 fourcc = i9xx_format_to_fourcc(pixel_format);
7414 fb->format = drm_format_info(fourcc);
7415
7416 if (INTEL_GEN(dev_priv) >= 4) {
7417 if (plane_config->tiling)
7418 offset = I915_READ(DSPTILEOFF(plane));
7419 else
7420 offset = I915_READ(DSPLINOFF(plane));
7421 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7422 } else {
7423 base = I915_READ(DSPADDR(plane));
7424 }
7425 plane_config->base = base;
7426
7427 val = I915_READ(PIPESRC(pipe));
7428 fb->width = ((val >> 16) & 0xfff) + 1;
7429 fb->height = ((val >> 0) & 0xfff) + 1;
7430
7431 val = I915_READ(DSPSTRIDE(pipe));
7432 fb->pitches[0] = val & 0xffffffc0;
7433
7434 aligned_height = intel_fb_align_height(dev_priv,
7435 fb->height,
7436 fb->format->format,
7437 fb->modifier);
7438
7439 plane_config->size = fb->pitches[0] * aligned_height;
7440
7441 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7442 pipe_name(pipe), plane, fb->width, fb->height,
7443 fb->format->cpp[0] * 8, base, fb->pitches[0],
7444 plane_config->size);
7445
7446 plane_config->fb = intel_fb;
7447 }
7448
7449 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7450 struct intel_crtc_state *pipe_config)
7451 {
7452 struct drm_device *dev = crtc->base.dev;
7453 struct drm_i915_private *dev_priv = to_i915(dev);
7454 int pipe = pipe_config->cpu_transcoder;
7455 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7456 struct dpll clock;
7457 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7458 int refclk = 100000;
7459
7460 /* In case of DSI, DPLL will not be used */
7461 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7462 return;
7463
7464 mutex_lock(&dev_priv->sb_lock);
7465 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7466 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7467 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7468 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7469 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7470 mutex_unlock(&dev_priv->sb_lock);
7471
7472 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7473 clock.m2 = (pll_dw0 & 0xff) << 22;
7474 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7475 clock.m2 |= pll_dw2 & 0x3fffff;
7476 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7477 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7478 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7479
7480 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7481 }
7482
7483 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7484 struct intel_crtc_state *pipe_config)
7485 {
7486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7487 enum intel_display_power_domain power_domain;
7488 uint32_t tmp;
7489 bool ret;
7490
7491 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7492 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7493 return false;
7494
7495 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7496 pipe_config->shared_dpll = NULL;
7497
7498 ret = false;
7499
7500 tmp = I915_READ(PIPECONF(crtc->pipe));
7501 if (!(tmp & PIPECONF_ENABLE))
7502 goto out;
7503
7504 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7505 IS_CHERRYVIEW(dev_priv)) {
7506 switch (tmp & PIPECONF_BPC_MASK) {
7507 case PIPECONF_6BPC:
7508 pipe_config->pipe_bpp = 18;
7509 break;
7510 case PIPECONF_8BPC:
7511 pipe_config->pipe_bpp = 24;
7512 break;
7513 case PIPECONF_10BPC:
7514 pipe_config->pipe_bpp = 30;
7515 break;
7516 default:
7517 break;
7518 }
7519 }
7520
7521 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7522 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7523 pipe_config->limited_color_range = true;
7524
7525 if (INTEL_GEN(dev_priv) < 4)
7526 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7527
7528 intel_get_pipe_timings(crtc, pipe_config);
7529 intel_get_pipe_src_size(crtc, pipe_config);
7530
7531 i9xx_get_pfit_config(crtc, pipe_config);
7532
7533 if (INTEL_GEN(dev_priv) >= 4) {
7534 /* No way to read it out on pipes B and C */
7535 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7536 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7537 else
7538 tmp = I915_READ(DPLL_MD(crtc->pipe));
7539 pipe_config->pixel_multiplier =
7540 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7541 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7542 pipe_config->dpll_hw_state.dpll_md = tmp;
7543 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7544 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7545 tmp = I915_READ(DPLL(crtc->pipe));
7546 pipe_config->pixel_multiplier =
7547 ((tmp & SDVO_MULTIPLIER_MASK)
7548 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7549 } else {
7550 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7551 * port and will be fixed up in the encoder->get_config
7552 * function. */
7553 pipe_config->pixel_multiplier = 1;
7554 }
7555 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7556 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7557 /*
7558 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7559 * on 830. Filter it out here so that we don't
7560 * report errors due to that.
7561 */
7562 if (IS_I830(dev_priv))
7563 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7564
7565 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7566 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7567 } else {
7568 /* Mask out read-only status bits. */
7569 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7570 DPLL_PORTC_READY_MASK |
7571 DPLL_PORTB_READY_MASK);
7572 }
7573
7574 if (IS_CHERRYVIEW(dev_priv))
7575 chv_crtc_clock_get(crtc, pipe_config);
7576 else if (IS_VALLEYVIEW(dev_priv))
7577 vlv_crtc_clock_get(crtc, pipe_config);
7578 else
7579 i9xx_crtc_clock_get(crtc, pipe_config);
7580
7581 /*
7582 * Normally the dotclock is filled in by the encoder .get_config()
7583 * but in case the pipe is enabled w/o any ports we need a sane
7584 * default.
7585 */
7586 pipe_config->base.adjusted_mode.crtc_clock =
7587 pipe_config->port_clock / pipe_config->pixel_multiplier;
7588
7589 ret = true;
7590
7591 out:
7592 intel_display_power_put(dev_priv, power_domain);
7593
7594 return ret;
7595 }
7596
7597 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7598 {
7599 struct intel_encoder *encoder;
7600 int i;
7601 u32 val, final;
7602 bool has_lvds = false;
7603 bool has_cpu_edp = false;
7604 bool has_panel = false;
7605 bool has_ck505 = false;
7606 bool can_ssc = false;
7607 bool using_ssc_source = false;
7608
7609 /* We need to take the global config into account */
7610 for_each_intel_encoder(&dev_priv->drm, encoder) {
7611 switch (encoder->type) {
7612 case INTEL_OUTPUT_LVDS:
7613 has_panel = true;
7614 has_lvds = true;
7615 break;
7616 case INTEL_OUTPUT_EDP:
7617 has_panel = true;
7618 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7619 has_cpu_edp = true;
7620 break;
7621 default:
7622 break;
7623 }
7624 }
7625
7626 if (HAS_PCH_IBX(dev_priv)) {
7627 has_ck505 = dev_priv->vbt.display_clock_mode;
7628 can_ssc = has_ck505;
7629 } else {
7630 has_ck505 = false;
7631 can_ssc = true;
7632 }
7633
7634 /* Check if any DPLLs are using the SSC source */
7635 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7636 u32 temp = I915_READ(PCH_DPLL(i));
7637
7638 if (!(temp & DPLL_VCO_ENABLE))
7639 continue;
7640
7641 if ((temp & PLL_REF_INPUT_MASK) ==
7642 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7643 using_ssc_source = true;
7644 break;
7645 }
7646 }
7647
7648 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7649 has_panel, has_lvds, has_ck505, using_ssc_source);
7650
7651 /* Ironlake: try to setup display ref clock before DPLL
7652 * enabling. This is only under driver's control after
7653 * PCH B stepping, previous chipset stepping should be
7654 * ignoring this setting.
7655 */
7656 val = I915_READ(PCH_DREF_CONTROL);
7657
7658 /* As we must carefully and slowly disable/enable each source in turn,
7659 * compute the final state we want first and check if we need to
7660 * make any changes at all.
7661 */
7662 final = val;
7663 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7664 if (has_ck505)
7665 final |= DREF_NONSPREAD_CK505_ENABLE;
7666 else
7667 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7668
7669 final &= ~DREF_SSC_SOURCE_MASK;
7670 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7671 final &= ~DREF_SSC1_ENABLE;
7672
7673 if (has_panel) {
7674 final |= DREF_SSC_SOURCE_ENABLE;
7675
7676 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7677 final |= DREF_SSC1_ENABLE;
7678
7679 if (has_cpu_edp) {
7680 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7681 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7682 else
7683 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7684 } else
7685 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7686 } else if (using_ssc_source) {
7687 final |= DREF_SSC_SOURCE_ENABLE;
7688 final |= DREF_SSC1_ENABLE;
7689 }
7690
7691 if (final == val)
7692 return;
7693
7694 /* Always enable nonspread source */
7695 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7696
7697 if (has_ck505)
7698 val |= DREF_NONSPREAD_CK505_ENABLE;
7699 else
7700 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7701
7702 if (has_panel) {
7703 val &= ~DREF_SSC_SOURCE_MASK;
7704 val |= DREF_SSC_SOURCE_ENABLE;
7705
7706 /* SSC must be turned on before enabling the CPU output */
7707 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7708 DRM_DEBUG_KMS("Using SSC on panel\n");
7709 val |= DREF_SSC1_ENABLE;
7710 } else
7711 val &= ~DREF_SSC1_ENABLE;
7712
7713 /* Get SSC going before enabling the outputs */
7714 I915_WRITE(PCH_DREF_CONTROL, val);
7715 POSTING_READ(PCH_DREF_CONTROL);
7716 udelay(200);
7717
7718 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7719
7720 /* Enable CPU source on CPU attached eDP */
7721 if (has_cpu_edp) {
7722 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7723 DRM_DEBUG_KMS("Using SSC on eDP\n");
7724 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7725 } else
7726 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7727 } else
7728 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7729
7730 I915_WRITE(PCH_DREF_CONTROL, val);
7731 POSTING_READ(PCH_DREF_CONTROL);
7732 udelay(200);
7733 } else {
7734 DRM_DEBUG_KMS("Disabling CPU source output\n");
7735
7736 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7737
7738 /* Turn off CPU output */
7739 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7740
7741 I915_WRITE(PCH_DREF_CONTROL, val);
7742 POSTING_READ(PCH_DREF_CONTROL);
7743 udelay(200);
7744
7745 if (!using_ssc_source) {
7746 DRM_DEBUG_KMS("Disabling SSC source\n");
7747
7748 /* Turn off the SSC source */
7749 val &= ~DREF_SSC_SOURCE_MASK;
7750 val |= DREF_SSC_SOURCE_DISABLE;
7751
7752 /* Turn off SSC1 */
7753 val &= ~DREF_SSC1_ENABLE;
7754
7755 I915_WRITE(PCH_DREF_CONTROL, val);
7756 POSTING_READ(PCH_DREF_CONTROL);
7757 udelay(200);
7758 }
7759 }
7760
7761 BUG_ON(val != final);
7762 }
7763
7764 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7765 {
7766 uint32_t tmp;
7767
7768 tmp = I915_READ(SOUTH_CHICKEN2);
7769 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7770 I915_WRITE(SOUTH_CHICKEN2, tmp);
7771
7772 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7773 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7774 DRM_ERROR("FDI mPHY reset assert timeout\n");
7775
7776 tmp = I915_READ(SOUTH_CHICKEN2);
7777 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7778 I915_WRITE(SOUTH_CHICKEN2, tmp);
7779
7780 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7781 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7782 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7783 }
7784
7785 /* WaMPhyProgramming:hsw */
7786 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7787 {
7788 uint32_t tmp;
7789
7790 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7791 tmp &= ~(0xFF << 24);
7792 tmp |= (0x12 << 24);
7793 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7794
7795 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7796 tmp |= (1 << 11);
7797 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7798
7799 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7800 tmp |= (1 << 11);
7801 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7802
7803 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7804 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7805 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7806
7807 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7808 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7809 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7810
7811 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7812 tmp &= ~(7 << 13);
7813 tmp |= (5 << 13);
7814 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7815
7816 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7817 tmp &= ~(7 << 13);
7818 tmp |= (5 << 13);
7819 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7820
7821 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7822 tmp &= ~0xFF;
7823 tmp |= 0x1C;
7824 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7825
7826 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7827 tmp &= ~0xFF;
7828 tmp |= 0x1C;
7829 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7830
7831 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7832 tmp &= ~(0xFF << 16);
7833 tmp |= (0x1C << 16);
7834 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7835
7836 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7837 tmp &= ~(0xFF << 16);
7838 tmp |= (0x1C << 16);
7839 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7840
7841 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7842 tmp |= (1 << 27);
7843 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7844
7845 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7846 tmp |= (1 << 27);
7847 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7848
7849 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7850 tmp &= ~(0xF << 28);
7851 tmp |= (4 << 28);
7852 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7853
7854 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7855 tmp &= ~(0xF << 28);
7856 tmp |= (4 << 28);
7857 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7858 }
7859
7860 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7861 * Programming" based on the parameters passed:
7862 * - Sequence to enable CLKOUT_DP
7863 * - Sequence to enable CLKOUT_DP without spread
7864 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7865 */
7866 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7867 bool with_spread, bool with_fdi)
7868 {
7869 uint32_t reg, tmp;
7870
7871 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7872 with_spread = true;
7873 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7874 with_fdi, "LP PCH doesn't have FDI\n"))
7875 with_fdi = false;
7876
7877 mutex_lock(&dev_priv->sb_lock);
7878
7879 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7880 tmp &= ~SBI_SSCCTL_DISABLE;
7881 tmp |= SBI_SSCCTL_PATHALT;
7882 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7883
7884 udelay(24);
7885
7886 if (with_spread) {
7887 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7888 tmp &= ~SBI_SSCCTL_PATHALT;
7889 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7890
7891 if (with_fdi) {
7892 lpt_reset_fdi_mphy(dev_priv);
7893 lpt_program_fdi_mphy(dev_priv);
7894 }
7895 }
7896
7897 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7898 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7899 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7900 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7901
7902 mutex_unlock(&dev_priv->sb_lock);
7903 }
7904
7905 /* Sequence to disable CLKOUT_DP */
7906 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7907 {
7908 uint32_t reg, tmp;
7909
7910 mutex_lock(&dev_priv->sb_lock);
7911
7912 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7913 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7914 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7915 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7916
7917 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7918 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7919 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7920 tmp |= SBI_SSCCTL_PATHALT;
7921 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7922 udelay(32);
7923 }
7924 tmp |= SBI_SSCCTL_DISABLE;
7925 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7926 }
7927
7928 mutex_unlock(&dev_priv->sb_lock);
7929 }
7930
7931 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7932
7933 static const uint16_t sscdivintphase[] = {
7934 [BEND_IDX( 50)] = 0x3B23,
7935 [BEND_IDX( 45)] = 0x3B23,
7936 [BEND_IDX( 40)] = 0x3C23,
7937 [BEND_IDX( 35)] = 0x3C23,
7938 [BEND_IDX( 30)] = 0x3D23,
7939 [BEND_IDX( 25)] = 0x3D23,
7940 [BEND_IDX( 20)] = 0x3E23,
7941 [BEND_IDX( 15)] = 0x3E23,
7942 [BEND_IDX( 10)] = 0x3F23,
7943 [BEND_IDX( 5)] = 0x3F23,
7944 [BEND_IDX( 0)] = 0x0025,
7945 [BEND_IDX( -5)] = 0x0025,
7946 [BEND_IDX(-10)] = 0x0125,
7947 [BEND_IDX(-15)] = 0x0125,
7948 [BEND_IDX(-20)] = 0x0225,
7949 [BEND_IDX(-25)] = 0x0225,
7950 [BEND_IDX(-30)] = 0x0325,
7951 [BEND_IDX(-35)] = 0x0325,
7952 [BEND_IDX(-40)] = 0x0425,
7953 [BEND_IDX(-45)] = 0x0425,
7954 [BEND_IDX(-50)] = 0x0525,
7955 };
7956
7957 /*
7958 * Bend CLKOUT_DP
7959 * steps -50 to 50 inclusive, in steps of 5
7960 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7961 * change in clock period = -(steps / 10) * 5.787 ps
7962 */
7963 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7964 {
7965 uint32_t tmp;
7966 int idx = BEND_IDX(steps);
7967
7968 if (WARN_ON(steps % 5 != 0))
7969 return;
7970
7971 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7972 return;
7973
7974 mutex_lock(&dev_priv->sb_lock);
7975
7976 if (steps % 10 != 0)
7977 tmp = 0xAAAAAAAB;
7978 else
7979 tmp = 0x00000000;
7980 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7981
7982 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7983 tmp &= 0xffff0000;
7984 tmp |= sscdivintphase[idx];
7985 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7986
7987 mutex_unlock(&dev_priv->sb_lock);
7988 }
7989
7990 #undef BEND_IDX
7991
7992 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7993 {
7994 struct intel_encoder *encoder;
7995 bool has_vga = false;
7996
7997 for_each_intel_encoder(&dev_priv->drm, encoder) {
7998 switch (encoder->type) {
7999 case INTEL_OUTPUT_ANALOG:
8000 has_vga = true;
8001 break;
8002 default:
8003 break;
8004 }
8005 }
8006
8007 if (has_vga) {
8008 lpt_bend_clkout_dp(dev_priv, 0);
8009 lpt_enable_clkout_dp(dev_priv, true, true);
8010 } else {
8011 lpt_disable_clkout_dp(dev_priv);
8012 }
8013 }
8014
8015 /*
8016 * Initialize reference clocks when the driver loads
8017 */
8018 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8019 {
8020 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8021 ironlake_init_pch_refclk(dev_priv);
8022 else if (HAS_PCH_LPT(dev_priv))
8023 lpt_init_pch_refclk(dev_priv);
8024 }
8025
8026 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8027 {
8028 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8030 int pipe = intel_crtc->pipe;
8031 uint32_t val;
8032
8033 val = 0;
8034
8035 switch (intel_crtc->config->pipe_bpp) {
8036 case 18:
8037 val |= PIPECONF_6BPC;
8038 break;
8039 case 24:
8040 val |= PIPECONF_8BPC;
8041 break;
8042 case 30:
8043 val |= PIPECONF_10BPC;
8044 break;
8045 case 36:
8046 val |= PIPECONF_12BPC;
8047 break;
8048 default:
8049 /* Case prevented by intel_choose_pipe_bpp_dither. */
8050 BUG();
8051 }
8052
8053 if (intel_crtc->config->dither)
8054 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8055
8056 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8057 val |= PIPECONF_INTERLACED_ILK;
8058 else
8059 val |= PIPECONF_PROGRESSIVE;
8060
8061 if (intel_crtc->config->limited_color_range)
8062 val |= PIPECONF_COLOR_RANGE_SELECT;
8063
8064 I915_WRITE(PIPECONF(pipe), val);
8065 POSTING_READ(PIPECONF(pipe));
8066 }
8067
8068 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8069 {
8070 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8072 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8073 u32 val = 0;
8074
8075 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8076 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8077
8078 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8079 val |= PIPECONF_INTERLACED_ILK;
8080 else
8081 val |= PIPECONF_PROGRESSIVE;
8082
8083 I915_WRITE(PIPECONF(cpu_transcoder), val);
8084 POSTING_READ(PIPECONF(cpu_transcoder));
8085 }
8086
8087 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8088 {
8089 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8091
8092 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8093 u32 val = 0;
8094
8095 switch (intel_crtc->config->pipe_bpp) {
8096 case 18:
8097 val |= PIPEMISC_DITHER_6_BPC;
8098 break;
8099 case 24:
8100 val |= PIPEMISC_DITHER_8_BPC;
8101 break;
8102 case 30:
8103 val |= PIPEMISC_DITHER_10_BPC;
8104 break;
8105 case 36:
8106 val |= PIPEMISC_DITHER_12_BPC;
8107 break;
8108 default:
8109 /* Case prevented by pipe_config_set_bpp. */
8110 BUG();
8111 }
8112
8113 if (intel_crtc->config->dither)
8114 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8115
8116 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8117 }
8118 }
8119
8120 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8121 {
8122 /*
8123 * Account for spread spectrum to avoid
8124 * oversubscribing the link. Max center spread
8125 * is 2.5%; use 5% for safety's sake.
8126 */
8127 u32 bps = target_clock * bpp * 21 / 20;
8128 return DIV_ROUND_UP(bps, link_bw * 8);
8129 }
8130
8131 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8132 {
8133 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8134 }
8135
8136 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8137 struct intel_crtc_state *crtc_state,
8138 struct dpll *reduced_clock)
8139 {
8140 struct drm_crtc *crtc = &intel_crtc->base;
8141 struct drm_device *dev = crtc->dev;
8142 struct drm_i915_private *dev_priv = to_i915(dev);
8143 u32 dpll, fp, fp2;
8144 int factor;
8145
8146 /* Enable autotuning of the PLL clock (if permissible) */
8147 factor = 21;
8148 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8149 if ((intel_panel_use_ssc(dev_priv) &&
8150 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8151 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8152 factor = 25;
8153 } else if (crtc_state->sdvo_tv_clock)
8154 factor = 20;
8155
8156 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8157
8158 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8159 fp |= FP_CB_TUNE;
8160
8161 if (reduced_clock) {
8162 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8163
8164 if (reduced_clock->m < factor * reduced_clock->n)
8165 fp2 |= FP_CB_TUNE;
8166 } else {
8167 fp2 = fp;
8168 }
8169
8170 dpll = 0;
8171
8172 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8173 dpll |= DPLLB_MODE_LVDS;
8174 else
8175 dpll |= DPLLB_MODE_DAC_SERIAL;
8176
8177 dpll |= (crtc_state->pixel_multiplier - 1)
8178 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8179
8180 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8181 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8182 dpll |= DPLL_SDVO_HIGH_SPEED;
8183
8184 if (intel_crtc_has_dp_encoder(crtc_state))
8185 dpll |= DPLL_SDVO_HIGH_SPEED;
8186
8187 /*
8188 * The high speed IO clock is only really required for
8189 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8190 * possible to share the DPLL between CRT and HDMI. Enabling
8191 * the clock needlessly does no real harm, except use up a
8192 * bit of power potentially.
8193 *
8194 * We'll limit this to IVB with 3 pipes, since it has only two
8195 * DPLLs and so DPLL sharing is the only way to get three pipes
8196 * driving PCH ports at the same time. On SNB we could do this,
8197 * and potentially avoid enabling the second DPLL, but it's not
8198 * clear if it''s a win or loss power wise. No point in doing
8199 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8200 */
8201 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8202 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8203 dpll |= DPLL_SDVO_HIGH_SPEED;
8204
8205 /* compute bitmask from p1 value */
8206 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8207 /* also FPA1 */
8208 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8209
8210 switch (crtc_state->dpll.p2) {
8211 case 5:
8212 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8213 break;
8214 case 7:
8215 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8216 break;
8217 case 10:
8218 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8219 break;
8220 case 14:
8221 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8222 break;
8223 }
8224
8225 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8226 intel_panel_use_ssc(dev_priv))
8227 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8228 else
8229 dpll |= PLL_REF_INPUT_DREFCLK;
8230
8231 dpll |= DPLL_VCO_ENABLE;
8232
8233 crtc_state->dpll_hw_state.dpll = dpll;
8234 crtc_state->dpll_hw_state.fp0 = fp;
8235 crtc_state->dpll_hw_state.fp1 = fp2;
8236 }
8237
8238 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8239 struct intel_crtc_state *crtc_state)
8240 {
8241 struct drm_device *dev = crtc->base.dev;
8242 struct drm_i915_private *dev_priv = to_i915(dev);
8243 struct dpll reduced_clock;
8244 bool has_reduced_clock = false;
8245 struct intel_shared_dpll *pll;
8246 const struct intel_limit *limit;
8247 int refclk = 120000;
8248
8249 memset(&crtc_state->dpll_hw_state, 0,
8250 sizeof(crtc_state->dpll_hw_state));
8251
8252 crtc->lowfreq_avail = false;
8253
8254 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8255 if (!crtc_state->has_pch_encoder)
8256 return 0;
8257
8258 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8259 if (intel_panel_use_ssc(dev_priv)) {
8260 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8261 dev_priv->vbt.lvds_ssc_freq);
8262 refclk = dev_priv->vbt.lvds_ssc_freq;
8263 }
8264
8265 if (intel_is_dual_link_lvds(dev)) {
8266 if (refclk == 100000)
8267 limit = &intel_limits_ironlake_dual_lvds_100m;
8268 else
8269 limit = &intel_limits_ironlake_dual_lvds;
8270 } else {
8271 if (refclk == 100000)
8272 limit = &intel_limits_ironlake_single_lvds_100m;
8273 else
8274 limit = &intel_limits_ironlake_single_lvds;
8275 }
8276 } else {
8277 limit = &intel_limits_ironlake_dac;
8278 }
8279
8280 if (!crtc_state->clock_set &&
8281 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8282 refclk, NULL, &crtc_state->dpll)) {
8283 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8284 return -EINVAL;
8285 }
8286
8287 ironlake_compute_dpll(crtc, crtc_state,
8288 has_reduced_clock ? &reduced_clock : NULL);
8289
8290 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8291 if (pll == NULL) {
8292 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8293 pipe_name(crtc->pipe));
8294 return -EINVAL;
8295 }
8296
8297 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8298 has_reduced_clock)
8299 crtc->lowfreq_avail = true;
8300
8301 return 0;
8302 }
8303
8304 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8305 struct intel_link_m_n *m_n)
8306 {
8307 struct drm_device *dev = crtc->base.dev;
8308 struct drm_i915_private *dev_priv = to_i915(dev);
8309 enum pipe pipe = crtc->pipe;
8310
8311 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8312 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8313 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8314 & ~TU_SIZE_MASK;
8315 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8316 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8317 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8318 }
8319
8320 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8321 enum transcoder transcoder,
8322 struct intel_link_m_n *m_n,
8323 struct intel_link_m_n *m2_n2)
8324 {
8325 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8326 enum pipe pipe = crtc->pipe;
8327
8328 if (INTEL_GEN(dev_priv) >= 5) {
8329 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8330 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8331 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8332 & ~TU_SIZE_MASK;
8333 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8334 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8335 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8336 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8337 * gen < 8) and if DRRS is supported (to make sure the
8338 * registers are not unnecessarily read).
8339 */
8340 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8341 crtc->config->has_drrs) {
8342 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8343 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8344 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8345 & ~TU_SIZE_MASK;
8346 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8347 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8348 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8349 }
8350 } else {
8351 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8352 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8353 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8354 & ~TU_SIZE_MASK;
8355 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8356 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8357 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8358 }
8359 }
8360
8361 void intel_dp_get_m_n(struct intel_crtc *crtc,
8362 struct intel_crtc_state *pipe_config)
8363 {
8364 if (pipe_config->has_pch_encoder)
8365 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8366 else
8367 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8368 &pipe_config->dp_m_n,
8369 &pipe_config->dp_m2_n2);
8370 }
8371
8372 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8373 struct intel_crtc_state *pipe_config)
8374 {
8375 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8376 &pipe_config->fdi_m_n, NULL);
8377 }
8378
8379 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8380 struct intel_crtc_state *pipe_config)
8381 {
8382 struct drm_device *dev = crtc->base.dev;
8383 struct drm_i915_private *dev_priv = to_i915(dev);
8384 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8385 uint32_t ps_ctrl = 0;
8386 int id = -1;
8387 int i;
8388
8389 /* find scaler attached to this pipe */
8390 for (i = 0; i < crtc->num_scalers; i++) {
8391 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8392 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8393 id = i;
8394 pipe_config->pch_pfit.enabled = true;
8395 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8396 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8397 break;
8398 }
8399 }
8400
8401 scaler_state->scaler_id = id;
8402 if (id >= 0) {
8403 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8404 } else {
8405 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8406 }
8407 }
8408
8409 static void
8410 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8411 struct intel_initial_plane_config *plane_config)
8412 {
8413 struct drm_device *dev = crtc->base.dev;
8414 struct drm_i915_private *dev_priv = to_i915(dev);
8415 u32 val, base, offset, stride_mult, tiling;
8416 int pipe = crtc->pipe;
8417 int fourcc, pixel_format;
8418 unsigned int aligned_height;
8419 struct drm_framebuffer *fb;
8420 struct intel_framebuffer *intel_fb;
8421
8422 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8423 if (!intel_fb) {
8424 DRM_DEBUG_KMS("failed to alloc fb\n");
8425 return;
8426 }
8427
8428 fb = &intel_fb->base;
8429
8430 fb->dev = dev;
8431
8432 val = I915_READ(PLANE_CTL(pipe, 0));
8433 if (!(val & PLANE_CTL_ENABLE))
8434 goto error;
8435
8436 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8437 fourcc = skl_format_to_fourcc(pixel_format,
8438 val & PLANE_CTL_ORDER_RGBX,
8439 val & PLANE_CTL_ALPHA_MASK);
8440 fb->format = drm_format_info(fourcc);
8441
8442 tiling = val & PLANE_CTL_TILED_MASK;
8443 switch (tiling) {
8444 case PLANE_CTL_TILED_LINEAR:
8445 fb->modifier = DRM_FORMAT_MOD_NONE;
8446 break;
8447 case PLANE_CTL_TILED_X:
8448 plane_config->tiling = I915_TILING_X;
8449 fb->modifier = I915_FORMAT_MOD_X_TILED;
8450 break;
8451 case PLANE_CTL_TILED_Y:
8452 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8453 break;
8454 case PLANE_CTL_TILED_YF:
8455 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8456 break;
8457 default:
8458 MISSING_CASE(tiling);
8459 goto error;
8460 }
8461
8462 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8463 plane_config->base = base;
8464
8465 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8466
8467 val = I915_READ(PLANE_SIZE(pipe, 0));
8468 fb->height = ((val >> 16) & 0xfff) + 1;
8469 fb->width = ((val >> 0) & 0x1fff) + 1;
8470
8471 val = I915_READ(PLANE_STRIDE(pipe, 0));
8472 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier,
8473 fb->format->format);
8474 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8475
8476 aligned_height = intel_fb_align_height(dev_priv,
8477 fb->height,
8478 fb->format->format,
8479 fb->modifier);
8480
8481 plane_config->size = fb->pitches[0] * aligned_height;
8482
8483 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8484 pipe_name(pipe), fb->width, fb->height,
8485 fb->format->cpp[0] * 8, base, fb->pitches[0],
8486 plane_config->size);
8487
8488 plane_config->fb = intel_fb;
8489 return;
8490
8491 error:
8492 kfree(intel_fb);
8493 }
8494
8495 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8496 struct intel_crtc_state *pipe_config)
8497 {
8498 struct drm_device *dev = crtc->base.dev;
8499 struct drm_i915_private *dev_priv = to_i915(dev);
8500 uint32_t tmp;
8501
8502 tmp = I915_READ(PF_CTL(crtc->pipe));
8503
8504 if (tmp & PF_ENABLE) {
8505 pipe_config->pch_pfit.enabled = true;
8506 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8507 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8508
8509 /* We currently do not free assignements of panel fitters on
8510 * ivb/hsw (since we don't use the higher upscaling modes which
8511 * differentiates them) so just WARN about this case for now. */
8512 if (IS_GEN7(dev_priv)) {
8513 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8514 PF_PIPE_SEL_IVB(crtc->pipe));
8515 }
8516 }
8517 }
8518
8519 static void
8520 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8521 struct intel_initial_plane_config *plane_config)
8522 {
8523 struct drm_device *dev = crtc->base.dev;
8524 struct drm_i915_private *dev_priv = to_i915(dev);
8525 u32 val, base, offset;
8526 int pipe = crtc->pipe;
8527 int fourcc, pixel_format;
8528 unsigned int aligned_height;
8529 struct drm_framebuffer *fb;
8530 struct intel_framebuffer *intel_fb;
8531
8532 val = I915_READ(DSPCNTR(pipe));
8533 if (!(val & DISPLAY_PLANE_ENABLE))
8534 return;
8535
8536 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8537 if (!intel_fb) {
8538 DRM_DEBUG_KMS("failed to alloc fb\n");
8539 return;
8540 }
8541
8542 fb = &intel_fb->base;
8543
8544 fb->dev = dev;
8545
8546 if (INTEL_GEN(dev_priv) >= 4) {
8547 if (val & DISPPLANE_TILED) {
8548 plane_config->tiling = I915_TILING_X;
8549 fb->modifier = I915_FORMAT_MOD_X_TILED;
8550 }
8551 }
8552
8553 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8554 fourcc = i9xx_format_to_fourcc(pixel_format);
8555 fb->format = drm_format_info(fourcc);
8556
8557 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8558 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8559 offset = I915_READ(DSPOFFSET(pipe));
8560 } else {
8561 if (plane_config->tiling)
8562 offset = I915_READ(DSPTILEOFF(pipe));
8563 else
8564 offset = I915_READ(DSPLINOFF(pipe));
8565 }
8566 plane_config->base = base;
8567
8568 val = I915_READ(PIPESRC(pipe));
8569 fb->width = ((val >> 16) & 0xfff) + 1;
8570 fb->height = ((val >> 0) & 0xfff) + 1;
8571
8572 val = I915_READ(DSPSTRIDE(pipe));
8573 fb->pitches[0] = val & 0xffffffc0;
8574
8575 aligned_height = intel_fb_align_height(dev_priv,
8576 fb->height,
8577 fb->format->format,
8578 fb->modifier);
8579
8580 plane_config->size = fb->pitches[0] * aligned_height;
8581
8582 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8583 pipe_name(pipe), fb->width, fb->height,
8584 fb->format->cpp[0] * 8, base, fb->pitches[0],
8585 plane_config->size);
8586
8587 plane_config->fb = intel_fb;
8588 }
8589
8590 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8591 struct intel_crtc_state *pipe_config)
8592 {
8593 struct drm_device *dev = crtc->base.dev;
8594 struct drm_i915_private *dev_priv = to_i915(dev);
8595 enum intel_display_power_domain power_domain;
8596 uint32_t tmp;
8597 bool ret;
8598
8599 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8600 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8601 return false;
8602
8603 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8604 pipe_config->shared_dpll = NULL;
8605
8606 ret = false;
8607 tmp = I915_READ(PIPECONF(crtc->pipe));
8608 if (!(tmp & PIPECONF_ENABLE))
8609 goto out;
8610
8611 switch (tmp & PIPECONF_BPC_MASK) {
8612 case PIPECONF_6BPC:
8613 pipe_config->pipe_bpp = 18;
8614 break;
8615 case PIPECONF_8BPC:
8616 pipe_config->pipe_bpp = 24;
8617 break;
8618 case PIPECONF_10BPC:
8619 pipe_config->pipe_bpp = 30;
8620 break;
8621 case PIPECONF_12BPC:
8622 pipe_config->pipe_bpp = 36;
8623 break;
8624 default:
8625 break;
8626 }
8627
8628 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8629 pipe_config->limited_color_range = true;
8630
8631 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8632 struct intel_shared_dpll *pll;
8633 enum intel_dpll_id pll_id;
8634
8635 pipe_config->has_pch_encoder = true;
8636
8637 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8638 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8639 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8640
8641 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8642
8643 if (HAS_PCH_IBX(dev_priv)) {
8644 /*
8645 * The pipe->pch transcoder and pch transcoder->pll
8646 * mapping is fixed.
8647 */
8648 pll_id = (enum intel_dpll_id) crtc->pipe;
8649 } else {
8650 tmp = I915_READ(PCH_DPLL_SEL);
8651 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8652 pll_id = DPLL_ID_PCH_PLL_B;
8653 else
8654 pll_id= DPLL_ID_PCH_PLL_A;
8655 }
8656
8657 pipe_config->shared_dpll =
8658 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8659 pll = pipe_config->shared_dpll;
8660
8661 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8662 &pipe_config->dpll_hw_state));
8663
8664 tmp = pipe_config->dpll_hw_state.dpll;
8665 pipe_config->pixel_multiplier =
8666 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8667 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8668
8669 ironlake_pch_clock_get(crtc, pipe_config);
8670 } else {
8671 pipe_config->pixel_multiplier = 1;
8672 }
8673
8674 intel_get_pipe_timings(crtc, pipe_config);
8675 intel_get_pipe_src_size(crtc, pipe_config);
8676
8677 ironlake_get_pfit_config(crtc, pipe_config);
8678
8679 ret = true;
8680
8681 out:
8682 intel_display_power_put(dev_priv, power_domain);
8683
8684 return ret;
8685 }
8686
8687 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8688 {
8689 struct drm_device *dev = &dev_priv->drm;
8690 struct intel_crtc *crtc;
8691
8692 for_each_intel_crtc(dev, crtc)
8693 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8694 pipe_name(crtc->pipe));
8695
8696 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8697 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8698 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8699 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8700 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8701 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8702 "CPU PWM1 enabled\n");
8703 if (IS_HASWELL(dev_priv))
8704 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8705 "CPU PWM2 enabled\n");
8706 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8707 "PCH PWM1 enabled\n");
8708 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8709 "Utility pin enabled\n");
8710 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8711
8712 /*
8713 * In theory we can still leave IRQs enabled, as long as only the HPD
8714 * interrupts remain enabled. We used to check for that, but since it's
8715 * gen-specific and since we only disable LCPLL after we fully disable
8716 * the interrupts, the check below should be enough.
8717 */
8718 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8719 }
8720
8721 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8722 {
8723 if (IS_HASWELL(dev_priv))
8724 return I915_READ(D_COMP_HSW);
8725 else
8726 return I915_READ(D_COMP_BDW);
8727 }
8728
8729 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8730 {
8731 if (IS_HASWELL(dev_priv)) {
8732 mutex_lock(&dev_priv->rps.hw_lock);
8733 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8734 val))
8735 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8736 mutex_unlock(&dev_priv->rps.hw_lock);
8737 } else {
8738 I915_WRITE(D_COMP_BDW, val);
8739 POSTING_READ(D_COMP_BDW);
8740 }
8741 }
8742
8743 /*
8744 * This function implements pieces of two sequences from BSpec:
8745 * - Sequence for display software to disable LCPLL
8746 * - Sequence for display software to allow package C8+
8747 * The steps implemented here are just the steps that actually touch the LCPLL
8748 * register. Callers should take care of disabling all the display engine
8749 * functions, doing the mode unset, fixing interrupts, etc.
8750 */
8751 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8752 bool switch_to_fclk, bool allow_power_down)
8753 {
8754 uint32_t val;
8755
8756 assert_can_disable_lcpll(dev_priv);
8757
8758 val = I915_READ(LCPLL_CTL);
8759
8760 if (switch_to_fclk) {
8761 val |= LCPLL_CD_SOURCE_FCLK;
8762 I915_WRITE(LCPLL_CTL, val);
8763
8764 if (wait_for_us(I915_READ(LCPLL_CTL) &
8765 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8766 DRM_ERROR("Switching to FCLK failed\n");
8767
8768 val = I915_READ(LCPLL_CTL);
8769 }
8770
8771 val |= LCPLL_PLL_DISABLE;
8772 I915_WRITE(LCPLL_CTL, val);
8773 POSTING_READ(LCPLL_CTL);
8774
8775 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8776 DRM_ERROR("LCPLL still locked\n");
8777
8778 val = hsw_read_dcomp(dev_priv);
8779 val |= D_COMP_COMP_DISABLE;
8780 hsw_write_dcomp(dev_priv, val);
8781 ndelay(100);
8782
8783 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8784 1))
8785 DRM_ERROR("D_COMP RCOMP still in progress\n");
8786
8787 if (allow_power_down) {
8788 val = I915_READ(LCPLL_CTL);
8789 val |= LCPLL_POWER_DOWN_ALLOW;
8790 I915_WRITE(LCPLL_CTL, val);
8791 POSTING_READ(LCPLL_CTL);
8792 }
8793 }
8794
8795 /*
8796 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8797 * source.
8798 */
8799 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8800 {
8801 uint32_t val;
8802
8803 val = I915_READ(LCPLL_CTL);
8804
8805 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8806 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8807 return;
8808
8809 /*
8810 * Make sure we're not on PC8 state before disabling PC8, otherwise
8811 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8812 */
8813 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8814
8815 if (val & LCPLL_POWER_DOWN_ALLOW) {
8816 val &= ~LCPLL_POWER_DOWN_ALLOW;
8817 I915_WRITE(LCPLL_CTL, val);
8818 POSTING_READ(LCPLL_CTL);
8819 }
8820
8821 val = hsw_read_dcomp(dev_priv);
8822 val |= D_COMP_COMP_FORCE;
8823 val &= ~D_COMP_COMP_DISABLE;
8824 hsw_write_dcomp(dev_priv, val);
8825
8826 val = I915_READ(LCPLL_CTL);
8827 val &= ~LCPLL_PLL_DISABLE;
8828 I915_WRITE(LCPLL_CTL, val);
8829
8830 if (intel_wait_for_register(dev_priv,
8831 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8832 5))
8833 DRM_ERROR("LCPLL not locked yet\n");
8834
8835 if (val & LCPLL_CD_SOURCE_FCLK) {
8836 val = I915_READ(LCPLL_CTL);
8837 val &= ~LCPLL_CD_SOURCE_FCLK;
8838 I915_WRITE(LCPLL_CTL, val);
8839
8840 if (wait_for_us((I915_READ(LCPLL_CTL) &
8841 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8842 DRM_ERROR("Switching back to LCPLL failed\n");
8843 }
8844
8845 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8846 intel_update_cdclk(dev_priv);
8847 }
8848
8849 /*
8850 * Package states C8 and deeper are really deep PC states that can only be
8851 * reached when all the devices on the system allow it, so even if the graphics
8852 * device allows PC8+, it doesn't mean the system will actually get to these
8853 * states. Our driver only allows PC8+ when going into runtime PM.
8854 *
8855 * The requirements for PC8+ are that all the outputs are disabled, the power
8856 * well is disabled and most interrupts are disabled, and these are also
8857 * requirements for runtime PM. When these conditions are met, we manually do
8858 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8859 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8860 * hang the machine.
8861 *
8862 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8863 * the state of some registers, so when we come back from PC8+ we need to
8864 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8865 * need to take care of the registers kept by RC6. Notice that this happens even
8866 * if we don't put the device in PCI D3 state (which is what currently happens
8867 * because of the runtime PM support).
8868 *
8869 * For more, read "Display Sequences for Package C8" on the hardware
8870 * documentation.
8871 */
8872 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8873 {
8874 uint32_t val;
8875
8876 DRM_DEBUG_KMS("Enabling package C8+\n");
8877
8878 if (HAS_PCH_LPT_LP(dev_priv)) {
8879 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8880 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8881 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8882 }
8883
8884 lpt_disable_clkout_dp(dev_priv);
8885 hsw_disable_lcpll(dev_priv, true, true);
8886 }
8887
8888 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8889 {
8890 uint32_t val;
8891
8892 DRM_DEBUG_KMS("Disabling package C8+\n");
8893
8894 hsw_restore_lcpll(dev_priv);
8895 lpt_init_pch_refclk(dev_priv);
8896
8897 if (HAS_PCH_LPT_LP(dev_priv)) {
8898 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8899 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8900 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8901 }
8902 }
8903
8904 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8905 struct intel_crtc_state *crtc_state)
8906 {
8907 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8908 if (!intel_ddi_pll_select(crtc, crtc_state))
8909 return -EINVAL;
8910 }
8911
8912 crtc->lowfreq_avail = false;
8913
8914 return 0;
8915 }
8916
8917 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8918 enum port port,
8919 struct intel_crtc_state *pipe_config)
8920 {
8921 enum intel_dpll_id id;
8922
8923 switch (port) {
8924 case PORT_A:
8925 id = DPLL_ID_SKL_DPLL0;
8926 break;
8927 case PORT_B:
8928 id = DPLL_ID_SKL_DPLL1;
8929 break;
8930 case PORT_C:
8931 id = DPLL_ID_SKL_DPLL2;
8932 break;
8933 default:
8934 DRM_ERROR("Incorrect port type\n");
8935 return;
8936 }
8937
8938 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8939 }
8940
8941 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8942 enum port port,
8943 struct intel_crtc_state *pipe_config)
8944 {
8945 enum intel_dpll_id id;
8946 u32 temp;
8947
8948 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8949 id = temp >> (port * 3 + 1);
8950
8951 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8952 return;
8953
8954 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8955 }
8956
8957 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8958 enum port port,
8959 struct intel_crtc_state *pipe_config)
8960 {
8961 enum intel_dpll_id id;
8962 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8963
8964 switch (ddi_pll_sel) {
8965 case PORT_CLK_SEL_WRPLL1:
8966 id = DPLL_ID_WRPLL1;
8967 break;
8968 case PORT_CLK_SEL_WRPLL2:
8969 id = DPLL_ID_WRPLL2;
8970 break;
8971 case PORT_CLK_SEL_SPLL:
8972 id = DPLL_ID_SPLL;
8973 break;
8974 case PORT_CLK_SEL_LCPLL_810:
8975 id = DPLL_ID_LCPLL_810;
8976 break;
8977 case PORT_CLK_SEL_LCPLL_1350:
8978 id = DPLL_ID_LCPLL_1350;
8979 break;
8980 case PORT_CLK_SEL_LCPLL_2700:
8981 id = DPLL_ID_LCPLL_2700;
8982 break;
8983 default:
8984 MISSING_CASE(ddi_pll_sel);
8985 /* fall through */
8986 case PORT_CLK_SEL_NONE:
8987 return;
8988 }
8989
8990 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8991 }
8992
8993 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8994 struct intel_crtc_state *pipe_config,
8995 u64 *power_domain_mask)
8996 {
8997 struct drm_device *dev = crtc->base.dev;
8998 struct drm_i915_private *dev_priv = to_i915(dev);
8999 enum intel_display_power_domain power_domain;
9000 u32 tmp;
9001
9002 /*
9003 * The pipe->transcoder mapping is fixed with the exception of the eDP
9004 * transcoder handled below.
9005 */
9006 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9007
9008 /*
9009 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9010 * consistency and less surprising code; it's in always on power).
9011 */
9012 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9013 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9014 enum pipe trans_edp_pipe;
9015 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9016 default:
9017 WARN(1, "unknown pipe linked to edp transcoder\n");
9018 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9019 case TRANS_DDI_EDP_INPUT_A_ON:
9020 trans_edp_pipe = PIPE_A;
9021 break;
9022 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9023 trans_edp_pipe = PIPE_B;
9024 break;
9025 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9026 trans_edp_pipe = PIPE_C;
9027 break;
9028 }
9029
9030 if (trans_edp_pipe == crtc->pipe)
9031 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9032 }
9033
9034 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9035 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9036 return false;
9037 *power_domain_mask |= BIT_ULL(power_domain);
9038
9039 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9040
9041 return tmp & PIPECONF_ENABLE;
9042 }
9043
9044 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9045 struct intel_crtc_state *pipe_config,
9046 u64 *power_domain_mask)
9047 {
9048 struct drm_device *dev = crtc->base.dev;
9049 struct drm_i915_private *dev_priv = to_i915(dev);
9050 enum intel_display_power_domain power_domain;
9051 enum port port;
9052 enum transcoder cpu_transcoder;
9053 u32 tmp;
9054
9055 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9056 if (port == PORT_A)
9057 cpu_transcoder = TRANSCODER_DSI_A;
9058 else
9059 cpu_transcoder = TRANSCODER_DSI_C;
9060
9061 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9062 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9063 continue;
9064 *power_domain_mask |= BIT_ULL(power_domain);
9065
9066 /*
9067 * The PLL needs to be enabled with a valid divider
9068 * configuration, otherwise accessing DSI registers will hang
9069 * the machine. See BSpec North Display Engine
9070 * registers/MIPI[BXT]. We can break out here early, since we
9071 * need the same DSI PLL to be enabled for both DSI ports.
9072 */
9073 if (!intel_dsi_pll_is_enabled(dev_priv))
9074 break;
9075
9076 /* XXX: this works for video mode only */
9077 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9078 if (!(tmp & DPI_ENABLE))
9079 continue;
9080
9081 tmp = I915_READ(MIPI_CTRL(port));
9082 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9083 continue;
9084
9085 pipe_config->cpu_transcoder = cpu_transcoder;
9086 break;
9087 }
9088
9089 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9090 }
9091
9092 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9093 struct intel_crtc_state *pipe_config)
9094 {
9095 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9096 struct intel_shared_dpll *pll;
9097 enum port port;
9098 uint32_t tmp;
9099
9100 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9101
9102 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9103
9104 if (IS_GEN9_BC(dev_priv))
9105 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9106 else if (IS_GEN9_LP(dev_priv))
9107 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9108 else
9109 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9110
9111 pll = pipe_config->shared_dpll;
9112 if (pll) {
9113 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9114 &pipe_config->dpll_hw_state));
9115 }
9116
9117 /*
9118 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9119 * DDI E. So just check whether this pipe is wired to DDI E and whether
9120 * the PCH transcoder is on.
9121 */
9122 if (INTEL_GEN(dev_priv) < 9 &&
9123 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9124 pipe_config->has_pch_encoder = true;
9125
9126 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9127 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9128 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9129
9130 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9131 }
9132 }
9133
9134 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9135 struct intel_crtc_state *pipe_config)
9136 {
9137 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9138 enum intel_display_power_domain power_domain;
9139 u64 power_domain_mask;
9140 bool active;
9141
9142 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9143 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9144 return false;
9145 power_domain_mask = BIT_ULL(power_domain);
9146
9147 pipe_config->shared_dpll = NULL;
9148
9149 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9150
9151 if (IS_GEN9_LP(dev_priv) &&
9152 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9153 WARN_ON(active);
9154 active = true;
9155 }
9156
9157 if (!active)
9158 goto out;
9159
9160 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9161 haswell_get_ddi_port_state(crtc, pipe_config);
9162 intel_get_pipe_timings(crtc, pipe_config);
9163 }
9164
9165 intel_get_pipe_src_size(crtc, pipe_config);
9166
9167 pipe_config->gamma_mode =
9168 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9169
9170 if (INTEL_GEN(dev_priv) >= 9) {
9171 intel_crtc_init_scalers(crtc, pipe_config);
9172
9173 pipe_config->scaler_state.scaler_id = -1;
9174 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9175 }
9176
9177 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9178 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9179 power_domain_mask |= BIT_ULL(power_domain);
9180 if (INTEL_GEN(dev_priv) >= 9)
9181 skylake_get_pfit_config(crtc, pipe_config);
9182 else
9183 ironlake_get_pfit_config(crtc, pipe_config);
9184 }
9185
9186 if (IS_HASWELL(dev_priv))
9187 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9188 (I915_READ(IPS_CTL) & IPS_ENABLE);
9189
9190 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9191 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9192 pipe_config->pixel_multiplier =
9193 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9194 } else {
9195 pipe_config->pixel_multiplier = 1;
9196 }
9197
9198 out:
9199 for_each_power_domain(power_domain, power_domain_mask)
9200 intel_display_power_put(dev_priv, power_domain);
9201
9202 return active;
9203 }
9204
9205 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9206 const struct intel_plane_state *plane_state)
9207 {
9208 struct drm_device *dev = crtc->dev;
9209 struct drm_i915_private *dev_priv = to_i915(dev);
9210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9211 uint32_t cntl = 0, size = 0;
9212
9213 if (plane_state && plane_state->base.visible) {
9214 unsigned int width = plane_state->base.crtc_w;
9215 unsigned int height = plane_state->base.crtc_h;
9216 unsigned int stride = roundup_pow_of_two(width) * 4;
9217
9218 switch (stride) {
9219 default:
9220 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9221 width, stride);
9222 stride = 256;
9223 /* fallthrough */
9224 case 256:
9225 case 512:
9226 case 1024:
9227 case 2048:
9228 break;
9229 }
9230
9231 cntl |= CURSOR_ENABLE |
9232 CURSOR_GAMMA_ENABLE |
9233 CURSOR_FORMAT_ARGB |
9234 CURSOR_STRIDE(stride);
9235
9236 size = (height << 12) | width;
9237 }
9238
9239 if (intel_crtc->cursor_cntl != 0 &&
9240 (intel_crtc->cursor_base != base ||
9241 intel_crtc->cursor_size != size ||
9242 intel_crtc->cursor_cntl != cntl)) {
9243 /* On these chipsets we can only modify the base/size/stride
9244 * whilst the cursor is disabled.
9245 */
9246 I915_WRITE(CURCNTR(PIPE_A), 0);
9247 POSTING_READ(CURCNTR(PIPE_A));
9248 intel_crtc->cursor_cntl = 0;
9249 }
9250
9251 if (intel_crtc->cursor_base != base) {
9252 I915_WRITE(CURBASE(PIPE_A), base);
9253 intel_crtc->cursor_base = base;
9254 }
9255
9256 if (intel_crtc->cursor_size != size) {
9257 I915_WRITE(CURSIZE, size);
9258 intel_crtc->cursor_size = size;
9259 }
9260
9261 if (intel_crtc->cursor_cntl != cntl) {
9262 I915_WRITE(CURCNTR(PIPE_A), cntl);
9263 POSTING_READ(CURCNTR(PIPE_A));
9264 intel_crtc->cursor_cntl = cntl;
9265 }
9266 }
9267
9268 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9269 const struct intel_plane_state *plane_state)
9270 {
9271 struct drm_device *dev = crtc->dev;
9272 struct drm_i915_private *dev_priv = to_i915(dev);
9273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9274 int pipe = intel_crtc->pipe;
9275 uint32_t cntl = 0;
9276
9277 if (plane_state && plane_state->base.visible) {
9278 cntl = MCURSOR_GAMMA_ENABLE;
9279 switch (plane_state->base.crtc_w) {
9280 case 64:
9281 cntl |= CURSOR_MODE_64_ARGB_AX;
9282 break;
9283 case 128:
9284 cntl |= CURSOR_MODE_128_ARGB_AX;
9285 break;
9286 case 256:
9287 cntl |= CURSOR_MODE_256_ARGB_AX;
9288 break;
9289 default:
9290 MISSING_CASE(plane_state->base.crtc_w);
9291 return;
9292 }
9293 cntl |= pipe << 28; /* Connect to correct pipe */
9294
9295 if (HAS_DDI(dev_priv))
9296 cntl |= CURSOR_PIPE_CSC_ENABLE;
9297
9298 if (plane_state->base.rotation & DRM_ROTATE_180)
9299 cntl |= CURSOR_ROTATE_180;
9300 }
9301
9302 if (intel_crtc->cursor_cntl != cntl) {
9303 I915_WRITE(CURCNTR(pipe), cntl);
9304 POSTING_READ(CURCNTR(pipe));
9305 intel_crtc->cursor_cntl = cntl;
9306 }
9307
9308 /* and commit changes on next vblank */
9309 I915_WRITE(CURBASE(pipe), base);
9310 POSTING_READ(CURBASE(pipe));
9311
9312 intel_crtc->cursor_base = base;
9313 }
9314
9315 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9316 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9317 const struct intel_plane_state *plane_state)
9318 {
9319 struct drm_device *dev = crtc->dev;
9320 struct drm_i915_private *dev_priv = to_i915(dev);
9321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9322 int pipe = intel_crtc->pipe;
9323 u32 base = intel_crtc->cursor_addr;
9324 u32 pos = 0;
9325
9326 if (plane_state) {
9327 int x = plane_state->base.crtc_x;
9328 int y = plane_state->base.crtc_y;
9329
9330 if (x < 0) {
9331 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9332 x = -x;
9333 }
9334 pos |= x << CURSOR_X_SHIFT;
9335
9336 if (y < 0) {
9337 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9338 y = -y;
9339 }
9340 pos |= y << CURSOR_Y_SHIFT;
9341
9342 /* ILK+ do this automagically */
9343 if (HAS_GMCH_DISPLAY(dev_priv) &&
9344 plane_state->base.rotation & DRM_ROTATE_180) {
9345 base += (plane_state->base.crtc_h *
9346 plane_state->base.crtc_w - 1) * 4;
9347 }
9348 }
9349
9350 I915_WRITE(CURPOS(pipe), pos);
9351
9352 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9353 i845_update_cursor(crtc, base, plane_state);
9354 else
9355 i9xx_update_cursor(crtc, base, plane_state);
9356 }
9357
9358 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9359 uint32_t width, uint32_t height)
9360 {
9361 if (width == 0 || height == 0)
9362 return false;
9363
9364 /*
9365 * 845g/865g are special in that they are only limited by
9366 * the width of their cursors, the height is arbitrary up to
9367 * the precision of the register. Everything else requires
9368 * square cursors, limited to a few power-of-two sizes.
9369 */
9370 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9371 if ((width & 63) != 0)
9372 return false;
9373
9374 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9375 return false;
9376
9377 if (height > 1023)
9378 return false;
9379 } else {
9380 switch (width | height) {
9381 case 256:
9382 case 128:
9383 if (IS_GEN2(dev_priv))
9384 return false;
9385 case 64:
9386 break;
9387 default:
9388 return false;
9389 }
9390 }
9391
9392 return true;
9393 }
9394
9395 /* VESA 640x480x72Hz mode to set on the pipe */
9396 static struct drm_display_mode load_detect_mode = {
9397 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9398 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9399 };
9400
9401 struct drm_framebuffer *
9402 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9403 struct drm_mode_fb_cmd2 *mode_cmd)
9404 {
9405 struct intel_framebuffer *intel_fb;
9406 int ret;
9407
9408 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9409 if (!intel_fb)
9410 return ERR_PTR(-ENOMEM);
9411
9412 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9413 if (ret)
9414 goto err;
9415
9416 return &intel_fb->base;
9417
9418 err:
9419 kfree(intel_fb);
9420 return ERR_PTR(ret);
9421 }
9422
9423 static u32
9424 intel_framebuffer_pitch_for_width(int width, int bpp)
9425 {
9426 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9427 return ALIGN(pitch, 64);
9428 }
9429
9430 static u32
9431 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9432 {
9433 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9434 return PAGE_ALIGN(pitch * mode->vdisplay);
9435 }
9436
9437 static struct drm_framebuffer *
9438 intel_framebuffer_create_for_mode(struct drm_device *dev,
9439 struct drm_display_mode *mode,
9440 int depth, int bpp)
9441 {
9442 struct drm_framebuffer *fb;
9443 struct drm_i915_gem_object *obj;
9444 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9445
9446 obj = i915_gem_object_create(to_i915(dev),
9447 intel_framebuffer_size_for_mode(mode, bpp));
9448 if (IS_ERR(obj))
9449 return ERR_CAST(obj);
9450
9451 mode_cmd.width = mode->hdisplay;
9452 mode_cmd.height = mode->vdisplay;
9453 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9454 bpp);
9455 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9456
9457 fb = intel_framebuffer_create(obj, &mode_cmd);
9458 if (IS_ERR(fb))
9459 i915_gem_object_put(obj);
9460
9461 return fb;
9462 }
9463
9464 static struct drm_framebuffer *
9465 mode_fits_in_fbdev(struct drm_device *dev,
9466 struct drm_display_mode *mode)
9467 {
9468 #ifdef CONFIG_DRM_FBDEV_EMULATION
9469 struct drm_i915_private *dev_priv = to_i915(dev);
9470 struct drm_i915_gem_object *obj;
9471 struct drm_framebuffer *fb;
9472
9473 if (!dev_priv->fbdev)
9474 return NULL;
9475
9476 if (!dev_priv->fbdev->fb)
9477 return NULL;
9478
9479 obj = dev_priv->fbdev->fb->obj;
9480 BUG_ON(!obj);
9481
9482 fb = &dev_priv->fbdev->fb->base;
9483 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9484 fb->format->cpp[0] * 8))
9485 return NULL;
9486
9487 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9488 return NULL;
9489
9490 drm_framebuffer_reference(fb);
9491 return fb;
9492 #else
9493 return NULL;
9494 #endif
9495 }
9496
9497 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9498 struct drm_crtc *crtc,
9499 struct drm_display_mode *mode,
9500 struct drm_framebuffer *fb,
9501 int x, int y)
9502 {
9503 struct drm_plane_state *plane_state;
9504 int hdisplay, vdisplay;
9505 int ret;
9506
9507 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9508 if (IS_ERR(plane_state))
9509 return PTR_ERR(plane_state);
9510
9511 if (mode)
9512 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9513 else
9514 hdisplay = vdisplay = 0;
9515
9516 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9517 if (ret)
9518 return ret;
9519 drm_atomic_set_fb_for_plane(plane_state, fb);
9520 plane_state->crtc_x = 0;
9521 plane_state->crtc_y = 0;
9522 plane_state->crtc_w = hdisplay;
9523 plane_state->crtc_h = vdisplay;
9524 plane_state->src_x = x << 16;
9525 plane_state->src_y = y << 16;
9526 plane_state->src_w = hdisplay << 16;
9527 plane_state->src_h = vdisplay << 16;
9528
9529 return 0;
9530 }
9531
9532 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9533 struct drm_display_mode *mode,
9534 struct intel_load_detect_pipe *old,
9535 struct drm_modeset_acquire_ctx *ctx)
9536 {
9537 struct intel_crtc *intel_crtc;
9538 struct intel_encoder *intel_encoder =
9539 intel_attached_encoder(connector);
9540 struct drm_crtc *possible_crtc;
9541 struct drm_encoder *encoder = &intel_encoder->base;
9542 struct drm_crtc *crtc = NULL;
9543 struct drm_device *dev = encoder->dev;
9544 struct drm_i915_private *dev_priv = to_i915(dev);
9545 struct drm_framebuffer *fb;
9546 struct drm_mode_config *config = &dev->mode_config;
9547 struct drm_atomic_state *state = NULL, *restore_state = NULL;
9548 struct drm_connector_state *connector_state;
9549 struct intel_crtc_state *crtc_state;
9550 int ret, i = -1;
9551
9552 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9553 connector->base.id, connector->name,
9554 encoder->base.id, encoder->name);
9555
9556 old->restore_state = NULL;
9557
9558 retry:
9559 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9560 if (ret)
9561 goto fail;
9562
9563 /*
9564 * Algorithm gets a little messy:
9565 *
9566 * - if the connector already has an assigned crtc, use it (but make
9567 * sure it's on first)
9568 *
9569 * - try to find the first unused crtc that can drive this connector,
9570 * and use that if we find one
9571 */
9572
9573 /* See if we already have a CRTC for this connector */
9574 if (connector->state->crtc) {
9575 crtc = connector->state->crtc;
9576
9577 ret = drm_modeset_lock(&crtc->mutex, ctx);
9578 if (ret)
9579 goto fail;
9580
9581 /* Make sure the crtc and connector are running */
9582 goto found;
9583 }
9584
9585 /* Find an unused one (if possible) */
9586 for_each_crtc(dev, possible_crtc) {
9587 i++;
9588 if (!(encoder->possible_crtcs & (1 << i)))
9589 continue;
9590
9591 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9592 if (ret)
9593 goto fail;
9594
9595 if (possible_crtc->state->enable) {
9596 drm_modeset_unlock(&possible_crtc->mutex);
9597 continue;
9598 }
9599
9600 crtc = possible_crtc;
9601 break;
9602 }
9603
9604 /*
9605 * If we didn't find an unused CRTC, don't use any.
9606 */
9607 if (!crtc) {
9608 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9609 goto fail;
9610 }
9611
9612 found:
9613 intel_crtc = to_intel_crtc(crtc);
9614
9615 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9616 if (ret)
9617 goto fail;
9618
9619 state = drm_atomic_state_alloc(dev);
9620 restore_state = drm_atomic_state_alloc(dev);
9621 if (!state || !restore_state) {
9622 ret = -ENOMEM;
9623 goto fail;
9624 }
9625
9626 state->acquire_ctx = ctx;
9627 restore_state->acquire_ctx = ctx;
9628
9629 connector_state = drm_atomic_get_connector_state(state, connector);
9630 if (IS_ERR(connector_state)) {
9631 ret = PTR_ERR(connector_state);
9632 goto fail;
9633 }
9634
9635 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9636 if (ret)
9637 goto fail;
9638
9639 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9640 if (IS_ERR(crtc_state)) {
9641 ret = PTR_ERR(crtc_state);
9642 goto fail;
9643 }
9644
9645 crtc_state->base.active = crtc_state->base.enable = true;
9646
9647 if (!mode)
9648 mode = &load_detect_mode;
9649
9650 /* We need a framebuffer large enough to accommodate all accesses
9651 * that the plane may generate whilst we perform load detection.
9652 * We can not rely on the fbcon either being present (we get called
9653 * during its initialisation to detect all boot displays, or it may
9654 * not even exist) or that it is large enough to satisfy the
9655 * requested mode.
9656 */
9657 fb = mode_fits_in_fbdev(dev, mode);
9658 if (fb == NULL) {
9659 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9660 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9661 } else
9662 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9663 if (IS_ERR(fb)) {
9664 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9665 goto fail;
9666 }
9667
9668 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9669 if (ret)
9670 goto fail;
9671
9672 drm_framebuffer_unreference(fb);
9673
9674 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9675 if (ret)
9676 goto fail;
9677
9678 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9679 if (!ret)
9680 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9681 if (!ret)
9682 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9683 if (ret) {
9684 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9685 goto fail;
9686 }
9687
9688 ret = drm_atomic_commit(state);
9689 if (ret) {
9690 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9691 goto fail;
9692 }
9693
9694 old->restore_state = restore_state;
9695 drm_atomic_state_put(state);
9696
9697 /* let the connector get through one full cycle before testing */
9698 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9699 return true;
9700
9701 fail:
9702 if (state) {
9703 drm_atomic_state_put(state);
9704 state = NULL;
9705 }
9706 if (restore_state) {
9707 drm_atomic_state_put(restore_state);
9708 restore_state = NULL;
9709 }
9710
9711 if (ret == -EDEADLK) {
9712 drm_modeset_backoff(ctx);
9713 goto retry;
9714 }
9715
9716 return false;
9717 }
9718
9719 void intel_release_load_detect_pipe(struct drm_connector *connector,
9720 struct intel_load_detect_pipe *old,
9721 struct drm_modeset_acquire_ctx *ctx)
9722 {
9723 struct intel_encoder *intel_encoder =
9724 intel_attached_encoder(connector);
9725 struct drm_encoder *encoder = &intel_encoder->base;
9726 struct drm_atomic_state *state = old->restore_state;
9727 int ret;
9728
9729 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9730 connector->base.id, connector->name,
9731 encoder->base.id, encoder->name);
9732
9733 if (!state)
9734 return;
9735
9736 ret = drm_atomic_commit(state);
9737 if (ret)
9738 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9739 drm_atomic_state_put(state);
9740 }
9741
9742 static int i9xx_pll_refclk(struct drm_device *dev,
9743 const struct intel_crtc_state *pipe_config)
9744 {
9745 struct drm_i915_private *dev_priv = to_i915(dev);
9746 u32 dpll = pipe_config->dpll_hw_state.dpll;
9747
9748 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9749 return dev_priv->vbt.lvds_ssc_freq;
9750 else if (HAS_PCH_SPLIT(dev_priv))
9751 return 120000;
9752 else if (!IS_GEN2(dev_priv))
9753 return 96000;
9754 else
9755 return 48000;
9756 }
9757
9758 /* Returns the clock of the currently programmed mode of the given pipe. */
9759 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9760 struct intel_crtc_state *pipe_config)
9761 {
9762 struct drm_device *dev = crtc->base.dev;
9763 struct drm_i915_private *dev_priv = to_i915(dev);
9764 int pipe = pipe_config->cpu_transcoder;
9765 u32 dpll = pipe_config->dpll_hw_state.dpll;
9766 u32 fp;
9767 struct dpll clock;
9768 int port_clock;
9769 int refclk = i9xx_pll_refclk(dev, pipe_config);
9770
9771 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9772 fp = pipe_config->dpll_hw_state.fp0;
9773 else
9774 fp = pipe_config->dpll_hw_state.fp1;
9775
9776 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9777 if (IS_PINEVIEW(dev_priv)) {
9778 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9779 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9780 } else {
9781 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9782 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9783 }
9784
9785 if (!IS_GEN2(dev_priv)) {
9786 if (IS_PINEVIEW(dev_priv))
9787 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9788 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9789 else
9790 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9791 DPLL_FPA01_P1_POST_DIV_SHIFT);
9792
9793 switch (dpll & DPLL_MODE_MASK) {
9794 case DPLLB_MODE_DAC_SERIAL:
9795 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9796 5 : 10;
9797 break;
9798 case DPLLB_MODE_LVDS:
9799 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9800 7 : 14;
9801 break;
9802 default:
9803 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9804 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9805 return;
9806 }
9807
9808 if (IS_PINEVIEW(dev_priv))
9809 port_clock = pnv_calc_dpll_params(refclk, &clock);
9810 else
9811 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9812 } else {
9813 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9814 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9815
9816 if (is_lvds) {
9817 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9818 DPLL_FPA01_P1_POST_DIV_SHIFT);
9819
9820 if (lvds & LVDS_CLKB_POWER_UP)
9821 clock.p2 = 7;
9822 else
9823 clock.p2 = 14;
9824 } else {
9825 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9826 clock.p1 = 2;
9827 else {
9828 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9829 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9830 }
9831 if (dpll & PLL_P2_DIVIDE_BY_4)
9832 clock.p2 = 4;
9833 else
9834 clock.p2 = 2;
9835 }
9836
9837 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9838 }
9839
9840 /*
9841 * This value includes pixel_multiplier. We will use
9842 * port_clock to compute adjusted_mode.crtc_clock in the
9843 * encoder's get_config() function.
9844 */
9845 pipe_config->port_clock = port_clock;
9846 }
9847
9848 int intel_dotclock_calculate(int link_freq,
9849 const struct intel_link_m_n *m_n)
9850 {
9851 /*
9852 * The calculation for the data clock is:
9853 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9854 * But we want to avoid losing precison if possible, so:
9855 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9856 *
9857 * and the link clock is simpler:
9858 * link_clock = (m * link_clock) / n
9859 */
9860
9861 if (!m_n->link_n)
9862 return 0;
9863
9864 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9865 }
9866
9867 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9868 struct intel_crtc_state *pipe_config)
9869 {
9870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9871
9872 /* read out port_clock from the DPLL */
9873 i9xx_crtc_clock_get(crtc, pipe_config);
9874
9875 /*
9876 * In case there is an active pipe without active ports,
9877 * we may need some idea for the dotclock anyway.
9878 * Calculate one based on the FDI configuration.
9879 */
9880 pipe_config->base.adjusted_mode.crtc_clock =
9881 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9882 &pipe_config->fdi_m_n);
9883 }
9884
9885 /** Returns the currently programmed mode of the given pipe. */
9886 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9887 struct drm_crtc *crtc)
9888 {
9889 struct drm_i915_private *dev_priv = to_i915(dev);
9890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9891 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9892 struct drm_display_mode *mode;
9893 struct intel_crtc_state *pipe_config;
9894 int htot = I915_READ(HTOTAL(cpu_transcoder));
9895 int hsync = I915_READ(HSYNC(cpu_transcoder));
9896 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9897 int vsync = I915_READ(VSYNC(cpu_transcoder));
9898 enum pipe pipe = intel_crtc->pipe;
9899
9900 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9901 if (!mode)
9902 return NULL;
9903
9904 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9905 if (!pipe_config) {
9906 kfree(mode);
9907 return NULL;
9908 }
9909
9910 /*
9911 * Construct a pipe_config sufficient for getting the clock info
9912 * back out of crtc_clock_get.
9913 *
9914 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9915 * to use a real value here instead.
9916 */
9917 pipe_config->cpu_transcoder = (enum transcoder) pipe;
9918 pipe_config->pixel_multiplier = 1;
9919 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9920 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9921 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9922 i9xx_crtc_clock_get(intel_crtc, pipe_config);
9923
9924 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9925 mode->hdisplay = (htot & 0xffff) + 1;
9926 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9927 mode->hsync_start = (hsync & 0xffff) + 1;
9928 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9929 mode->vdisplay = (vtot & 0xffff) + 1;
9930 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9931 mode->vsync_start = (vsync & 0xffff) + 1;
9932 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9933
9934 drm_mode_set_name(mode);
9935
9936 kfree(pipe_config);
9937
9938 return mode;
9939 }
9940
9941 static void intel_crtc_destroy(struct drm_crtc *crtc)
9942 {
9943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9944 struct drm_device *dev = crtc->dev;
9945 struct intel_flip_work *work;
9946
9947 spin_lock_irq(&dev->event_lock);
9948 work = intel_crtc->flip_work;
9949 intel_crtc->flip_work = NULL;
9950 spin_unlock_irq(&dev->event_lock);
9951
9952 if (work) {
9953 cancel_work_sync(&work->mmio_work);
9954 cancel_work_sync(&work->unpin_work);
9955 kfree(work);
9956 }
9957
9958 drm_crtc_cleanup(crtc);
9959
9960 kfree(intel_crtc);
9961 }
9962
9963 static void intel_unpin_work_fn(struct work_struct *__work)
9964 {
9965 struct intel_flip_work *work =
9966 container_of(__work, struct intel_flip_work, unpin_work);
9967 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9968 struct drm_device *dev = crtc->base.dev;
9969 struct drm_plane *primary = crtc->base.primary;
9970
9971 if (is_mmio_work(work))
9972 flush_work(&work->mmio_work);
9973
9974 mutex_lock(&dev->struct_mutex);
9975 intel_unpin_fb_vma(work->old_vma);
9976 i915_gem_object_put(work->pending_flip_obj);
9977 mutex_unlock(&dev->struct_mutex);
9978
9979 i915_gem_request_put(work->flip_queued_req);
9980
9981 intel_frontbuffer_flip_complete(to_i915(dev),
9982 to_intel_plane(primary)->frontbuffer_bit);
9983 intel_fbc_post_update(crtc);
9984 drm_framebuffer_unreference(work->old_fb);
9985
9986 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
9987 atomic_dec(&crtc->unpin_work_count);
9988
9989 kfree(work);
9990 }
9991
9992 /* Is 'a' after or equal to 'b'? */
9993 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9994 {
9995 return !((a - b) & 0x80000000);
9996 }
9997
9998 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
9999 struct intel_flip_work *work)
10000 {
10001 struct drm_device *dev = crtc->base.dev;
10002 struct drm_i915_private *dev_priv = to_i915(dev);
10003
10004 if (abort_flip_on_reset(crtc))
10005 return true;
10006
10007 /*
10008 * The relevant registers doen't exist on pre-ctg.
10009 * As the flip done interrupt doesn't trigger for mmio
10010 * flips on gmch platforms, a flip count check isn't
10011 * really needed there. But since ctg has the registers,
10012 * include it in the check anyway.
10013 */
10014 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10015 return true;
10016
10017 /*
10018 * BDW signals flip done immediately if the plane
10019 * is disabled, even if the plane enable is already
10020 * armed to occur at the next vblank :(
10021 */
10022
10023 /*
10024 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10025 * used the same base address. In that case the mmio flip might
10026 * have completed, but the CS hasn't even executed the flip yet.
10027 *
10028 * A flip count check isn't enough as the CS might have updated
10029 * the base address just after start of vblank, but before we
10030 * managed to process the interrupt. This means we'd complete the
10031 * CS flip too soon.
10032 *
10033 * Combining both checks should get us a good enough result. It may
10034 * still happen that the CS flip has been executed, but has not
10035 * yet actually completed. But in case the base address is the same
10036 * anyway, we don't really care.
10037 */
10038 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10039 crtc->flip_work->gtt_offset &&
10040 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10041 crtc->flip_work->flip_count);
10042 }
10043
10044 static bool
10045 __pageflip_finished_mmio(struct intel_crtc *crtc,
10046 struct intel_flip_work *work)
10047 {
10048 /*
10049 * MMIO work completes when vblank is different from
10050 * flip_queued_vblank.
10051 *
10052 * Reset counter value doesn't matter, this is handled by
10053 * i915_wait_request finishing early, so no need to handle
10054 * reset here.
10055 */
10056 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10057 }
10058
10059
10060 static bool pageflip_finished(struct intel_crtc *crtc,
10061 struct intel_flip_work *work)
10062 {
10063 if (!atomic_read(&work->pending))
10064 return false;
10065
10066 smp_rmb();
10067
10068 if (is_mmio_work(work))
10069 return __pageflip_finished_mmio(crtc, work);
10070 else
10071 return __pageflip_finished_cs(crtc, work);
10072 }
10073
10074 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10075 {
10076 struct drm_device *dev = &dev_priv->drm;
10077 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10078 struct intel_flip_work *work;
10079 unsigned long flags;
10080
10081 /* Ignore early vblank irqs */
10082 if (!crtc)
10083 return;
10084
10085 /*
10086 * This is called both by irq handlers and the reset code (to complete
10087 * lost pageflips) so needs the full irqsave spinlocks.
10088 */
10089 spin_lock_irqsave(&dev->event_lock, flags);
10090 work = crtc->flip_work;
10091
10092 if (work != NULL &&
10093 !is_mmio_work(work) &&
10094 pageflip_finished(crtc, work))
10095 page_flip_completed(crtc);
10096
10097 spin_unlock_irqrestore(&dev->event_lock, flags);
10098 }
10099
10100 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10101 {
10102 struct drm_device *dev = &dev_priv->drm;
10103 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10104 struct intel_flip_work *work;
10105 unsigned long flags;
10106
10107 /* Ignore early vblank irqs */
10108 if (!crtc)
10109 return;
10110
10111 /*
10112 * This is called both by irq handlers and the reset code (to complete
10113 * lost pageflips) so needs the full irqsave spinlocks.
10114 */
10115 spin_lock_irqsave(&dev->event_lock, flags);
10116 work = crtc->flip_work;
10117
10118 if (work != NULL &&
10119 is_mmio_work(work) &&
10120 pageflip_finished(crtc, work))
10121 page_flip_completed(crtc);
10122
10123 spin_unlock_irqrestore(&dev->event_lock, flags);
10124 }
10125
10126 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10127 struct intel_flip_work *work)
10128 {
10129 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10130
10131 /* Ensure that the work item is consistent when activating it ... */
10132 smp_mb__before_atomic();
10133 atomic_set(&work->pending, 1);
10134 }
10135
10136 static int intel_gen2_queue_flip(struct drm_device *dev,
10137 struct drm_crtc *crtc,
10138 struct drm_framebuffer *fb,
10139 struct drm_i915_gem_object *obj,
10140 struct drm_i915_gem_request *req,
10141 uint32_t flags)
10142 {
10143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10144 u32 flip_mask, *cs;
10145
10146 cs = intel_ring_begin(req, 6);
10147 if (IS_ERR(cs))
10148 return PTR_ERR(cs);
10149
10150 /* Can't queue multiple flips, so wait for the previous
10151 * one to finish before executing the next.
10152 */
10153 if (intel_crtc->plane)
10154 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10155 else
10156 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10157 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10158 *cs++ = MI_NOOP;
10159 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10160 *cs++ = fb->pitches[0];
10161 *cs++ = intel_crtc->flip_work->gtt_offset;
10162 *cs++ = 0; /* aux display base address, unused */
10163
10164 return 0;
10165 }
10166
10167 static int intel_gen3_queue_flip(struct drm_device *dev,
10168 struct drm_crtc *crtc,
10169 struct drm_framebuffer *fb,
10170 struct drm_i915_gem_object *obj,
10171 struct drm_i915_gem_request *req,
10172 uint32_t flags)
10173 {
10174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10175 u32 flip_mask, *cs;
10176
10177 cs = intel_ring_begin(req, 6);
10178 if (IS_ERR(cs))
10179 return PTR_ERR(cs);
10180
10181 if (intel_crtc->plane)
10182 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10183 else
10184 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10185 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10186 *cs++ = MI_NOOP;
10187 *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10188 *cs++ = fb->pitches[0];
10189 *cs++ = intel_crtc->flip_work->gtt_offset;
10190 *cs++ = MI_NOOP;
10191
10192 return 0;
10193 }
10194
10195 static int intel_gen4_queue_flip(struct drm_device *dev,
10196 struct drm_crtc *crtc,
10197 struct drm_framebuffer *fb,
10198 struct drm_i915_gem_object *obj,
10199 struct drm_i915_gem_request *req,
10200 uint32_t flags)
10201 {
10202 struct drm_i915_private *dev_priv = to_i915(dev);
10203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10204 u32 pf, pipesrc, *cs;
10205
10206 cs = intel_ring_begin(req, 4);
10207 if (IS_ERR(cs))
10208 return PTR_ERR(cs);
10209
10210 /* i965+ uses the linear or tiled offsets from the
10211 * Display Registers (which do not change across a page-flip)
10212 * so we need only reprogram the base address.
10213 */
10214 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10215 *cs++ = fb->pitches[0];
10216 *cs++ = intel_crtc->flip_work->gtt_offset |
10217 intel_fb_modifier_to_tiling(fb->modifier);
10218
10219 /* XXX Enabling the panel-fitter across page-flip is so far
10220 * untested on non-native modes, so ignore it for now.
10221 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10222 */
10223 pf = 0;
10224 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10225 *cs++ = pf | pipesrc;
10226
10227 return 0;
10228 }
10229
10230 static int intel_gen6_queue_flip(struct drm_device *dev,
10231 struct drm_crtc *crtc,
10232 struct drm_framebuffer *fb,
10233 struct drm_i915_gem_object *obj,
10234 struct drm_i915_gem_request *req,
10235 uint32_t flags)
10236 {
10237 struct drm_i915_private *dev_priv = to_i915(dev);
10238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10239 u32 pf, pipesrc, *cs;
10240
10241 cs = intel_ring_begin(req, 4);
10242 if (IS_ERR(cs))
10243 return PTR_ERR(cs);
10244
10245 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10246 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10247 *cs++ = intel_crtc->flip_work->gtt_offset;
10248
10249 /* Contrary to the suggestions in the documentation,
10250 * "Enable Panel Fitter" does not seem to be required when page
10251 * flipping with a non-native mode, and worse causes a normal
10252 * modeset to fail.
10253 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10254 */
10255 pf = 0;
10256 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10257 *cs++ = pf | pipesrc;
10258
10259 return 0;
10260 }
10261
10262 static int intel_gen7_queue_flip(struct drm_device *dev,
10263 struct drm_crtc *crtc,
10264 struct drm_framebuffer *fb,
10265 struct drm_i915_gem_object *obj,
10266 struct drm_i915_gem_request *req,
10267 uint32_t flags)
10268 {
10269 struct drm_i915_private *dev_priv = to_i915(dev);
10270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10271 u32 *cs, plane_bit = 0;
10272 int len, ret;
10273
10274 switch (intel_crtc->plane) {
10275 case PLANE_A:
10276 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10277 break;
10278 case PLANE_B:
10279 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10280 break;
10281 case PLANE_C:
10282 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10283 break;
10284 default:
10285 WARN_ONCE(1, "unknown plane in flip command\n");
10286 return -ENODEV;
10287 }
10288
10289 len = 4;
10290 if (req->engine->id == RCS) {
10291 len += 6;
10292 /*
10293 * On Gen 8, SRM is now taking an extra dword to accommodate
10294 * 48bits addresses, and we need a NOOP for the batch size to
10295 * stay even.
10296 */
10297 if (IS_GEN8(dev_priv))
10298 len += 2;
10299 }
10300
10301 /*
10302 * BSpec MI_DISPLAY_FLIP for IVB:
10303 * "The full packet must be contained within the same cache line."
10304 *
10305 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10306 * cacheline, if we ever start emitting more commands before
10307 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10308 * then do the cacheline alignment, and finally emit the
10309 * MI_DISPLAY_FLIP.
10310 */
10311 ret = intel_ring_cacheline_align(req);
10312 if (ret)
10313 return ret;
10314
10315 cs = intel_ring_begin(req, len);
10316 if (IS_ERR(cs))
10317 return PTR_ERR(cs);
10318
10319 /* Unmask the flip-done completion message. Note that the bspec says that
10320 * we should do this for both the BCS and RCS, and that we must not unmask
10321 * more than one flip event at any time (or ensure that one flip message
10322 * can be sent by waiting for flip-done prior to queueing new flips).
10323 * Experimentation says that BCS works despite DERRMR masking all
10324 * flip-done completion events and that unmasking all planes at once
10325 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10326 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10327 */
10328 if (req->engine->id == RCS) {
10329 *cs++ = MI_LOAD_REGISTER_IMM(1);
10330 *cs++ = i915_mmio_reg_offset(DERRMR);
10331 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10332 DERRMR_PIPEB_PRI_FLIP_DONE |
10333 DERRMR_PIPEC_PRI_FLIP_DONE);
10334 if (IS_GEN8(dev_priv))
10335 *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10336 MI_SRM_LRM_GLOBAL_GTT;
10337 else
10338 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10339 *cs++ = i915_mmio_reg_offset(DERRMR);
10340 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10341 if (IS_GEN8(dev_priv)) {
10342 *cs++ = 0;
10343 *cs++ = MI_NOOP;
10344 }
10345 }
10346
10347 *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10348 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10349 *cs++ = intel_crtc->flip_work->gtt_offset;
10350 *cs++ = MI_NOOP;
10351
10352 return 0;
10353 }
10354
10355 static bool use_mmio_flip(struct intel_engine_cs *engine,
10356 struct drm_i915_gem_object *obj)
10357 {
10358 /*
10359 * This is not being used for older platforms, because
10360 * non-availability of flip done interrupt forces us to use
10361 * CS flips. Older platforms derive flip done using some clever
10362 * tricks involving the flip_pending status bits and vblank irqs.
10363 * So using MMIO flips there would disrupt this mechanism.
10364 */
10365
10366 if (engine == NULL)
10367 return true;
10368
10369 if (INTEL_GEN(engine->i915) < 5)
10370 return false;
10371
10372 if (i915.use_mmio_flip < 0)
10373 return false;
10374 else if (i915.use_mmio_flip > 0)
10375 return true;
10376 else if (i915.enable_execlists)
10377 return true;
10378
10379 return engine != i915_gem_object_last_write_engine(obj);
10380 }
10381
10382 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10383 unsigned int rotation,
10384 struct intel_flip_work *work)
10385 {
10386 struct drm_device *dev = intel_crtc->base.dev;
10387 struct drm_i915_private *dev_priv = to_i915(dev);
10388 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10389 const enum pipe pipe = intel_crtc->pipe;
10390 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10391
10392 ctl = I915_READ(PLANE_CTL(pipe, 0));
10393 ctl &= ~PLANE_CTL_TILED_MASK;
10394 switch (fb->modifier) {
10395 case DRM_FORMAT_MOD_NONE:
10396 break;
10397 case I915_FORMAT_MOD_X_TILED:
10398 ctl |= PLANE_CTL_TILED_X;
10399 break;
10400 case I915_FORMAT_MOD_Y_TILED:
10401 ctl |= PLANE_CTL_TILED_Y;
10402 break;
10403 case I915_FORMAT_MOD_Yf_TILED:
10404 ctl |= PLANE_CTL_TILED_YF;
10405 break;
10406 default:
10407 MISSING_CASE(fb->modifier);
10408 }
10409
10410 /*
10411 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10412 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10413 */
10414 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10415 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10416
10417 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10418 POSTING_READ(PLANE_SURF(pipe, 0));
10419 }
10420
10421 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10422 struct intel_flip_work *work)
10423 {
10424 struct drm_device *dev = intel_crtc->base.dev;
10425 struct drm_i915_private *dev_priv = to_i915(dev);
10426 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10427 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10428 u32 dspcntr;
10429
10430 dspcntr = I915_READ(reg);
10431
10432 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10433 dspcntr |= DISPPLANE_TILED;
10434 else
10435 dspcntr &= ~DISPPLANE_TILED;
10436
10437 I915_WRITE(reg, dspcntr);
10438
10439 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10440 POSTING_READ(DSPSURF(intel_crtc->plane));
10441 }
10442
10443 static void intel_mmio_flip_work_func(struct work_struct *w)
10444 {
10445 struct intel_flip_work *work =
10446 container_of(w, struct intel_flip_work, mmio_work);
10447 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10448 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10449 struct intel_framebuffer *intel_fb =
10450 to_intel_framebuffer(crtc->base.primary->fb);
10451 struct drm_i915_gem_object *obj = intel_fb->obj;
10452
10453 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10454
10455 intel_pipe_update_start(crtc);
10456
10457 if (INTEL_GEN(dev_priv) >= 9)
10458 skl_do_mmio_flip(crtc, work->rotation, work);
10459 else
10460 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10461 ilk_do_mmio_flip(crtc, work);
10462
10463 intel_pipe_update_end(crtc, work);
10464 }
10465
10466 static int intel_default_queue_flip(struct drm_device *dev,
10467 struct drm_crtc *crtc,
10468 struct drm_framebuffer *fb,
10469 struct drm_i915_gem_object *obj,
10470 struct drm_i915_gem_request *req,
10471 uint32_t flags)
10472 {
10473 return -ENODEV;
10474 }
10475
10476 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10477 struct intel_crtc *intel_crtc,
10478 struct intel_flip_work *work)
10479 {
10480 u32 addr, vblank;
10481
10482 if (!atomic_read(&work->pending))
10483 return false;
10484
10485 smp_rmb();
10486
10487 vblank = intel_crtc_get_vblank_counter(intel_crtc);
10488 if (work->flip_ready_vblank == 0) {
10489 if (work->flip_queued_req &&
10490 !i915_gem_request_completed(work->flip_queued_req))
10491 return false;
10492
10493 work->flip_ready_vblank = vblank;
10494 }
10495
10496 if (vblank - work->flip_ready_vblank < 3)
10497 return false;
10498
10499 /* Potential stall - if we see that the flip has happened,
10500 * assume a missed interrupt. */
10501 if (INTEL_GEN(dev_priv) >= 4)
10502 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10503 else
10504 addr = I915_READ(DSPADDR(intel_crtc->plane));
10505
10506 /* There is a potential issue here with a false positive after a flip
10507 * to the same address. We could address this by checking for a
10508 * non-incrementing frame counter.
10509 */
10510 return addr == work->gtt_offset;
10511 }
10512
10513 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10514 {
10515 struct drm_device *dev = &dev_priv->drm;
10516 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10517 struct intel_flip_work *work;
10518
10519 WARN_ON(!in_interrupt());
10520
10521 if (crtc == NULL)
10522 return;
10523
10524 spin_lock(&dev->event_lock);
10525 work = crtc->flip_work;
10526
10527 if (work != NULL && !is_mmio_work(work) &&
10528 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10529 WARN_ONCE(1,
10530 "Kicking stuck page flip: queued at %d, now %d\n",
10531 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10532 page_flip_completed(crtc);
10533 work = NULL;
10534 }
10535
10536 if (work != NULL && !is_mmio_work(work) &&
10537 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10538 intel_queue_rps_boost_for_request(work->flip_queued_req);
10539 spin_unlock(&dev->event_lock);
10540 }
10541
10542 __maybe_unused
10543 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10544 struct drm_framebuffer *fb,
10545 struct drm_pending_vblank_event *event,
10546 uint32_t page_flip_flags)
10547 {
10548 struct drm_device *dev = crtc->dev;
10549 struct drm_i915_private *dev_priv = to_i915(dev);
10550 struct drm_framebuffer *old_fb = crtc->primary->fb;
10551 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10553 struct drm_plane *primary = crtc->primary;
10554 enum pipe pipe = intel_crtc->pipe;
10555 struct intel_flip_work *work;
10556 struct intel_engine_cs *engine;
10557 bool mmio_flip;
10558 struct drm_i915_gem_request *request;
10559 struct i915_vma *vma;
10560 int ret;
10561
10562 /*
10563 * drm_mode_page_flip_ioctl() should already catch this, but double
10564 * check to be safe. In the future we may enable pageflipping from
10565 * a disabled primary plane.
10566 */
10567 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10568 return -EBUSY;
10569
10570 /* Can't change pixel format via MI display flips. */
10571 if (fb->format != crtc->primary->fb->format)
10572 return -EINVAL;
10573
10574 /*
10575 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10576 * Note that pitch changes could also affect these register.
10577 */
10578 if (INTEL_GEN(dev_priv) > 3 &&
10579 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10580 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10581 return -EINVAL;
10582
10583 if (i915_terminally_wedged(&dev_priv->gpu_error))
10584 goto out_hang;
10585
10586 work = kzalloc(sizeof(*work), GFP_KERNEL);
10587 if (work == NULL)
10588 return -ENOMEM;
10589
10590 work->event = event;
10591 work->crtc = crtc;
10592 work->old_fb = old_fb;
10593 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10594
10595 ret = drm_crtc_vblank_get(crtc);
10596 if (ret)
10597 goto free_work;
10598
10599 /* We borrow the event spin lock for protecting flip_work */
10600 spin_lock_irq(&dev->event_lock);
10601 if (intel_crtc->flip_work) {
10602 /* Before declaring the flip queue wedged, check if
10603 * the hardware completed the operation behind our backs.
10604 */
10605 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10606 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10607 page_flip_completed(intel_crtc);
10608 } else {
10609 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10610 spin_unlock_irq(&dev->event_lock);
10611
10612 drm_crtc_vblank_put(crtc);
10613 kfree(work);
10614 return -EBUSY;
10615 }
10616 }
10617 intel_crtc->flip_work = work;
10618 spin_unlock_irq(&dev->event_lock);
10619
10620 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10621 flush_workqueue(dev_priv->wq);
10622
10623 /* Reference the objects for the scheduled work. */
10624 drm_framebuffer_reference(work->old_fb);
10625
10626 crtc->primary->fb = fb;
10627 update_state_fb(crtc->primary);
10628
10629 work->pending_flip_obj = i915_gem_object_get(obj);
10630
10631 ret = i915_mutex_lock_interruptible(dev);
10632 if (ret)
10633 goto cleanup;
10634
10635 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10636 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
10637 ret = -EIO;
10638 goto unlock;
10639 }
10640
10641 atomic_inc(&intel_crtc->unpin_work_count);
10642
10643 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10644 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10645
10646 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10647 engine = dev_priv->engine[BCS];
10648 if (fb->modifier != old_fb->modifier)
10649 /* vlv: DISPLAY_FLIP fails to change tiling */
10650 engine = NULL;
10651 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10652 engine = dev_priv->engine[BCS];
10653 } else if (INTEL_GEN(dev_priv) >= 7) {
10654 engine = i915_gem_object_last_write_engine(obj);
10655 if (engine == NULL || engine->id != RCS)
10656 engine = dev_priv->engine[BCS];
10657 } else {
10658 engine = dev_priv->engine[RCS];
10659 }
10660
10661 mmio_flip = use_mmio_flip(engine, obj);
10662
10663 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10664 if (IS_ERR(vma)) {
10665 ret = PTR_ERR(vma);
10666 goto cleanup_pending;
10667 }
10668
10669 work->old_vma = to_intel_plane_state(primary->state)->vma;
10670 to_intel_plane_state(primary->state)->vma = vma;
10671
10672 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10673 work->rotation = crtc->primary->state->rotation;
10674
10675 /*
10676 * There's the potential that the next frame will not be compatible with
10677 * FBC, so we want to call pre_update() before the actual page flip.
10678 * The problem is that pre_update() caches some information about the fb
10679 * object, so we want to do this only after the object is pinned. Let's
10680 * be on the safe side and do this immediately before scheduling the
10681 * flip.
10682 */
10683 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10684 to_intel_plane_state(primary->state));
10685
10686 if (mmio_flip) {
10687 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10688 queue_work(system_unbound_wq, &work->mmio_work);
10689 } else {
10690 request = i915_gem_request_alloc(engine,
10691 dev_priv->kernel_context);
10692 if (IS_ERR(request)) {
10693 ret = PTR_ERR(request);
10694 goto cleanup_unpin;
10695 }
10696
10697 ret = i915_gem_request_await_object(request, obj, false);
10698 if (ret)
10699 goto cleanup_request;
10700
10701 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10702 page_flip_flags);
10703 if (ret)
10704 goto cleanup_request;
10705
10706 intel_mark_page_flip_active(intel_crtc, work);
10707
10708 work->flip_queued_req = i915_gem_request_get(request);
10709 i915_add_request_no_flush(request);
10710 }
10711
10712 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10713 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10714 to_intel_plane(primary)->frontbuffer_bit);
10715 mutex_unlock(&dev->struct_mutex);
10716
10717 intel_frontbuffer_flip_prepare(to_i915(dev),
10718 to_intel_plane(primary)->frontbuffer_bit);
10719
10720 trace_i915_flip_request(intel_crtc->plane, obj);
10721
10722 return 0;
10723
10724 cleanup_request:
10725 i915_add_request_no_flush(request);
10726 cleanup_unpin:
10727 to_intel_plane_state(primary->state)->vma = work->old_vma;
10728 intel_unpin_fb_vma(vma);
10729 cleanup_pending:
10730 atomic_dec(&intel_crtc->unpin_work_count);
10731 unlock:
10732 mutex_unlock(&dev->struct_mutex);
10733 cleanup:
10734 crtc->primary->fb = old_fb;
10735 update_state_fb(crtc->primary);
10736
10737 i915_gem_object_put(obj);
10738 drm_framebuffer_unreference(work->old_fb);
10739
10740 spin_lock_irq(&dev->event_lock);
10741 intel_crtc->flip_work = NULL;
10742 spin_unlock_irq(&dev->event_lock);
10743
10744 drm_crtc_vblank_put(crtc);
10745 free_work:
10746 kfree(work);
10747
10748 if (ret == -EIO) {
10749 struct drm_atomic_state *state;
10750 struct drm_plane_state *plane_state;
10751
10752 out_hang:
10753 state = drm_atomic_state_alloc(dev);
10754 if (!state)
10755 return -ENOMEM;
10756 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
10757
10758 retry:
10759 plane_state = drm_atomic_get_plane_state(state, primary);
10760 ret = PTR_ERR_OR_ZERO(plane_state);
10761 if (!ret) {
10762 drm_atomic_set_fb_for_plane(plane_state, fb);
10763
10764 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10765 if (!ret)
10766 ret = drm_atomic_commit(state);
10767 }
10768
10769 if (ret == -EDEADLK) {
10770 drm_modeset_backoff(state->acquire_ctx);
10771 drm_atomic_state_clear(state);
10772 goto retry;
10773 }
10774
10775 drm_atomic_state_put(state);
10776
10777 if (ret == 0 && event) {
10778 spin_lock_irq(&dev->event_lock);
10779 drm_crtc_send_vblank_event(crtc, event);
10780 spin_unlock_irq(&dev->event_lock);
10781 }
10782 }
10783 return ret;
10784 }
10785
10786
10787 /**
10788 * intel_wm_need_update - Check whether watermarks need updating
10789 * @plane: drm plane
10790 * @state: new plane state
10791 *
10792 * Check current plane state versus the new one to determine whether
10793 * watermarks need to be recalculated.
10794 *
10795 * Returns true or false.
10796 */
10797 static bool intel_wm_need_update(struct drm_plane *plane,
10798 struct drm_plane_state *state)
10799 {
10800 struct intel_plane_state *new = to_intel_plane_state(state);
10801 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10802
10803 /* Update watermarks on tiling or size changes. */
10804 if (new->base.visible != cur->base.visible)
10805 return true;
10806
10807 if (!cur->base.fb || !new->base.fb)
10808 return false;
10809
10810 if (cur->base.fb->modifier != new->base.fb->modifier ||
10811 cur->base.rotation != new->base.rotation ||
10812 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10813 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10814 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10815 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10816 return true;
10817
10818 return false;
10819 }
10820
10821 static bool needs_scaling(struct intel_plane_state *state)
10822 {
10823 int src_w = drm_rect_width(&state->base.src) >> 16;
10824 int src_h = drm_rect_height(&state->base.src) >> 16;
10825 int dst_w = drm_rect_width(&state->base.dst);
10826 int dst_h = drm_rect_height(&state->base.dst);
10827
10828 return (src_w != dst_w || src_h != dst_h);
10829 }
10830
10831 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10832 struct drm_plane_state *plane_state)
10833 {
10834 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10835 struct drm_crtc *crtc = crtc_state->crtc;
10836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10837 struct drm_plane *plane = plane_state->plane;
10838 struct drm_device *dev = crtc->dev;
10839 struct drm_i915_private *dev_priv = to_i915(dev);
10840 struct intel_plane_state *old_plane_state =
10841 to_intel_plane_state(plane->state);
10842 bool mode_changed = needs_modeset(crtc_state);
10843 bool was_crtc_enabled = crtc->state->active;
10844 bool is_crtc_enabled = crtc_state->active;
10845 bool turn_off, turn_on, visible, was_visible;
10846 struct drm_framebuffer *fb = plane_state->fb;
10847 int ret;
10848
10849 if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
10850 ret = skl_update_scaler_plane(
10851 to_intel_crtc_state(crtc_state),
10852 to_intel_plane_state(plane_state));
10853 if (ret)
10854 return ret;
10855 }
10856
10857 was_visible = old_plane_state->base.visible;
10858 visible = plane_state->visible;
10859
10860 if (!was_crtc_enabled && WARN_ON(was_visible))
10861 was_visible = false;
10862
10863 /*
10864 * Visibility is calculated as if the crtc was on, but
10865 * after scaler setup everything depends on it being off
10866 * when the crtc isn't active.
10867 *
10868 * FIXME this is wrong for watermarks. Watermarks should also
10869 * be computed as if the pipe would be active. Perhaps move
10870 * per-plane wm computation to the .check_plane() hook, and
10871 * only combine the results from all planes in the current place?
10872 */
10873 if (!is_crtc_enabled)
10874 plane_state->visible = visible = false;
10875
10876 if (!was_visible && !visible)
10877 return 0;
10878
10879 if (fb != old_plane_state->base.fb)
10880 pipe_config->fb_changed = true;
10881
10882 turn_off = was_visible && (!visible || mode_changed);
10883 turn_on = visible && (!was_visible || mode_changed);
10884
10885 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10886 intel_crtc->base.base.id,
10887 intel_crtc->base.name,
10888 plane->base.id, plane->name,
10889 fb ? fb->base.id : -1);
10890
10891 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10892 plane->base.id, plane->name,
10893 was_visible, visible,
10894 turn_off, turn_on, mode_changed);
10895
10896 if (turn_on) {
10897 pipe_config->update_wm_pre = true;
10898
10899 /* must disable cxsr around plane enable/disable */
10900 if (plane->type != DRM_PLANE_TYPE_CURSOR)
10901 pipe_config->disable_cxsr = true;
10902 } else if (turn_off) {
10903 pipe_config->update_wm_post = true;
10904
10905 /* must disable cxsr around plane enable/disable */
10906 if (plane->type != DRM_PLANE_TYPE_CURSOR)
10907 pipe_config->disable_cxsr = true;
10908 } else if (intel_wm_need_update(plane, plane_state)) {
10909 /* FIXME bollocks */
10910 pipe_config->update_wm_pre = true;
10911 pipe_config->update_wm_post = true;
10912 }
10913
10914 /* Pre-gen9 platforms need two-step watermark updates */
10915 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
10916 INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks)
10917 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
10918
10919 if (visible || was_visible)
10920 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
10921
10922 /*
10923 * WaCxSRDisabledForSpriteScaling:ivb
10924 *
10925 * cstate->update_wm was already set above, so this flag will
10926 * take effect when we commit and program watermarks.
10927 */
10928 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
10929 needs_scaling(to_intel_plane_state(plane_state)) &&
10930 !needs_scaling(old_plane_state))
10931 pipe_config->disable_lp_wm = true;
10932
10933 return 0;
10934 }
10935
10936 static bool encoders_cloneable(const struct intel_encoder *a,
10937 const struct intel_encoder *b)
10938 {
10939 /* masks could be asymmetric, so check both ways */
10940 return a == b || (a->cloneable & (1 << b->type) &&
10941 b->cloneable & (1 << a->type));
10942 }
10943
10944 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10945 struct intel_crtc *crtc,
10946 struct intel_encoder *encoder)
10947 {
10948 struct intel_encoder *source_encoder;
10949 struct drm_connector *connector;
10950 struct drm_connector_state *connector_state;
10951 int i;
10952
10953 for_each_connector_in_state(state, connector, connector_state, i) {
10954 if (connector_state->crtc != &crtc->base)
10955 continue;
10956
10957 source_encoder =
10958 to_intel_encoder(connector_state->best_encoder);
10959 if (!encoders_cloneable(encoder, source_encoder))
10960 return false;
10961 }
10962
10963 return true;
10964 }
10965
10966 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10967 struct drm_crtc_state *crtc_state)
10968 {
10969 struct drm_device *dev = crtc->dev;
10970 struct drm_i915_private *dev_priv = to_i915(dev);
10971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10972 struct intel_crtc_state *pipe_config =
10973 to_intel_crtc_state(crtc_state);
10974 struct drm_atomic_state *state = crtc_state->state;
10975 int ret;
10976 bool mode_changed = needs_modeset(crtc_state);
10977
10978 if (mode_changed && !crtc_state->active)
10979 pipe_config->update_wm_post = true;
10980
10981 if (mode_changed && crtc_state->enable &&
10982 dev_priv->display.crtc_compute_clock &&
10983 !WARN_ON(pipe_config->shared_dpll)) {
10984 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10985 pipe_config);
10986 if (ret)
10987 return ret;
10988 }
10989
10990 if (crtc_state->color_mgmt_changed) {
10991 ret = intel_color_check(crtc, crtc_state);
10992 if (ret)
10993 return ret;
10994
10995 /*
10996 * Changing color management on Intel hardware is
10997 * handled as part of planes update.
10998 */
10999 crtc_state->planes_changed = true;
11000 }
11001
11002 ret = 0;
11003 if (dev_priv->display.compute_pipe_wm) {
11004 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11005 if (ret) {
11006 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11007 return ret;
11008 }
11009 }
11010
11011 if (dev_priv->display.compute_intermediate_wm &&
11012 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11013 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11014 return 0;
11015
11016 /*
11017 * Calculate 'intermediate' watermarks that satisfy both the
11018 * old state and the new state. We can program these
11019 * immediately.
11020 */
11021 ret = dev_priv->display.compute_intermediate_wm(dev,
11022 intel_crtc,
11023 pipe_config);
11024 if (ret) {
11025 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11026 return ret;
11027 }
11028 } else if (dev_priv->display.compute_intermediate_wm) {
11029 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11030 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11031 }
11032
11033 if (INTEL_GEN(dev_priv) >= 9) {
11034 if (mode_changed)
11035 ret = skl_update_scaler_crtc(pipe_config);
11036
11037 if (!ret)
11038 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11039 pipe_config);
11040 }
11041
11042 return ret;
11043 }
11044
11045 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11046 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11047 .atomic_begin = intel_begin_crtc_commit,
11048 .atomic_flush = intel_finish_crtc_commit,
11049 .atomic_check = intel_crtc_atomic_check,
11050 };
11051
11052 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11053 {
11054 struct intel_connector *connector;
11055
11056 for_each_intel_connector(dev, connector) {
11057 if (connector->base.state->crtc)
11058 drm_connector_unreference(&connector->base);
11059
11060 if (connector->base.encoder) {
11061 connector->base.state->best_encoder =
11062 connector->base.encoder;
11063 connector->base.state->crtc =
11064 connector->base.encoder->crtc;
11065
11066 drm_connector_reference(&connector->base);
11067 } else {
11068 connector->base.state->best_encoder = NULL;
11069 connector->base.state->crtc = NULL;
11070 }
11071 }
11072 }
11073
11074 static void
11075 connected_sink_compute_bpp(struct intel_connector *connector,
11076 struct intel_crtc_state *pipe_config)
11077 {
11078 const struct drm_display_info *info = &connector->base.display_info;
11079 int bpp = pipe_config->pipe_bpp;
11080
11081 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11082 connector->base.base.id,
11083 connector->base.name);
11084
11085 /* Don't use an invalid EDID bpc value */
11086 if (info->bpc != 0 && info->bpc * 3 < bpp) {
11087 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11088 bpp, info->bpc * 3);
11089 pipe_config->pipe_bpp = info->bpc * 3;
11090 }
11091
11092 /* Clamp bpp to 8 on screens without EDID 1.4 */
11093 if (info->bpc == 0 && bpp > 24) {
11094 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11095 bpp);
11096 pipe_config->pipe_bpp = 24;
11097 }
11098 }
11099
11100 static int
11101 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11102 struct intel_crtc_state *pipe_config)
11103 {
11104 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11105 struct drm_atomic_state *state;
11106 struct drm_connector *connector;
11107 struct drm_connector_state *connector_state;
11108 int bpp, i;
11109
11110 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11111 IS_CHERRYVIEW(dev_priv)))
11112 bpp = 10*3;
11113 else if (INTEL_GEN(dev_priv) >= 5)
11114 bpp = 12*3;
11115 else
11116 bpp = 8*3;
11117
11118
11119 pipe_config->pipe_bpp = bpp;
11120
11121 state = pipe_config->base.state;
11122
11123 /* Clamp display bpp to EDID value */
11124 for_each_connector_in_state(state, connector, connector_state, i) {
11125 if (connector_state->crtc != &crtc->base)
11126 continue;
11127
11128 connected_sink_compute_bpp(to_intel_connector(connector),
11129 pipe_config);
11130 }
11131
11132 return bpp;
11133 }
11134
11135 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11136 {
11137 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11138 "type: 0x%x flags: 0x%x\n",
11139 mode->crtc_clock,
11140 mode->crtc_hdisplay, mode->crtc_hsync_start,
11141 mode->crtc_hsync_end, mode->crtc_htotal,
11142 mode->crtc_vdisplay, mode->crtc_vsync_start,
11143 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11144 }
11145
11146 static inline void
11147 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11148 unsigned int lane_count, struct intel_link_m_n *m_n)
11149 {
11150 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11151 id, lane_count,
11152 m_n->gmch_m, m_n->gmch_n,
11153 m_n->link_m, m_n->link_n, m_n->tu);
11154 }
11155
11156 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11157 struct intel_crtc_state *pipe_config,
11158 const char *context)
11159 {
11160 struct drm_device *dev = crtc->base.dev;
11161 struct drm_i915_private *dev_priv = to_i915(dev);
11162 struct drm_plane *plane;
11163 struct intel_plane *intel_plane;
11164 struct intel_plane_state *state;
11165 struct drm_framebuffer *fb;
11166
11167 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11168 crtc->base.base.id, crtc->base.name, context);
11169
11170 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11171 transcoder_name(pipe_config->cpu_transcoder),
11172 pipe_config->pipe_bpp, pipe_config->dither);
11173
11174 if (pipe_config->has_pch_encoder)
11175 intel_dump_m_n_config(pipe_config, "fdi",
11176 pipe_config->fdi_lanes,
11177 &pipe_config->fdi_m_n);
11178
11179 if (intel_crtc_has_dp_encoder(pipe_config)) {
11180 intel_dump_m_n_config(pipe_config, "dp m_n",
11181 pipe_config->lane_count, &pipe_config->dp_m_n);
11182 if (pipe_config->has_drrs)
11183 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11184 pipe_config->lane_count,
11185 &pipe_config->dp_m2_n2);
11186 }
11187
11188 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11189 pipe_config->has_audio, pipe_config->has_infoframe);
11190
11191 DRM_DEBUG_KMS("requested mode:\n");
11192 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11193 DRM_DEBUG_KMS("adjusted mode:\n");
11194 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11195 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11196 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11197 pipe_config->port_clock,
11198 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11199 pipe_config->pixel_rate);
11200
11201 if (INTEL_GEN(dev_priv) >= 9)
11202 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11203 crtc->num_scalers,
11204 pipe_config->scaler_state.scaler_users,
11205 pipe_config->scaler_state.scaler_id);
11206
11207 if (HAS_GMCH_DISPLAY(dev_priv))
11208 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11209 pipe_config->gmch_pfit.control,
11210 pipe_config->gmch_pfit.pgm_ratios,
11211 pipe_config->gmch_pfit.lvds_border_bits);
11212 else
11213 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11214 pipe_config->pch_pfit.pos,
11215 pipe_config->pch_pfit.size,
11216 enableddisabled(pipe_config->pch_pfit.enabled));
11217
11218 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11219 pipe_config->ips_enabled, pipe_config->double_wide);
11220
11221 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11222
11223 DRM_DEBUG_KMS("planes on this crtc\n");
11224 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11225 struct drm_format_name_buf format_name;
11226 intel_plane = to_intel_plane(plane);
11227 if (intel_plane->pipe != crtc->pipe)
11228 continue;
11229
11230 state = to_intel_plane_state(plane->state);
11231 fb = state->base.fb;
11232 if (!fb) {
11233 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11234 plane->base.id, plane->name, state->scaler_id);
11235 continue;
11236 }
11237
11238 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11239 plane->base.id, plane->name,
11240 fb->base.id, fb->width, fb->height,
11241 drm_get_format_name(fb->format->format, &format_name));
11242 if (INTEL_GEN(dev_priv) >= 9)
11243 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11244 state->scaler_id,
11245 state->base.src.x1 >> 16,
11246 state->base.src.y1 >> 16,
11247 drm_rect_width(&state->base.src) >> 16,
11248 drm_rect_height(&state->base.src) >> 16,
11249 state->base.dst.x1, state->base.dst.y1,
11250 drm_rect_width(&state->base.dst),
11251 drm_rect_height(&state->base.dst));
11252 }
11253 }
11254
11255 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11256 {
11257 struct drm_device *dev = state->dev;
11258 struct drm_connector *connector;
11259 unsigned int used_ports = 0;
11260 unsigned int used_mst_ports = 0;
11261
11262 /*
11263 * Walk the connector list instead of the encoder
11264 * list to detect the problem on ddi platforms
11265 * where there's just one encoder per digital port.
11266 */
11267 drm_for_each_connector(connector, dev) {
11268 struct drm_connector_state *connector_state;
11269 struct intel_encoder *encoder;
11270
11271 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11272 if (!connector_state)
11273 connector_state = connector->state;
11274
11275 if (!connector_state->best_encoder)
11276 continue;
11277
11278 encoder = to_intel_encoder(connector_state->best_encoder);
11279
11280 WARN_ON(!connector_state->crtc);
11281
11282 switch (encoder->type) {
11283 unsigned int port_mask;
11284 case INTEL_OUTPUT_UNKNOWN:
11285 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11286 break;
11287 case INTEL_OUTPUT_DP:
11288 case INTEL_OUTPUT_HDMI:
11289 case INTEL_OUTPUT_EDP:
11290 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11291
11292 /* the same port mustn't appear more than once */
11293 if (used_ports & port_mask)
11294 return false;
11295
11296 used_ports |= port_mask;
11297 break;
11298 case INTEL_OUTPUT_DP_MST:
11299 used_mst_ports |=
11300 1 << enc_to_mst(&encoder->base)->primary->port;
11301 break;
11302 default:
11303 break;
11304 }
11305 }
11306
11307 /* can't mix MST and SST/HDMI on the same port */
11308 if (used_ports & used_mst_ports)
11309 return false;
11310
11311 return true;
11312 }
11313
11314 static void
11315 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11316 {
11317 struct drm_crtc_state tmp_state;
11318 struct intel_crtc_scaler_state scaler_state;
11319 struct intel_dpll_hw_state dpll_hw_state;
11320 struct intel_shared_dpll *shared_dpll;
11321 bool force_thru;
11322
11323 /* FIXME: before the switch to atomic started, a new pipe_config was
11324 * kzalloc'd. Code that depends on any field being zero should be
11325 * fixed, so that the crtc_state can be safely duplicated. For now,
11326 * only fields that are know to not cause problems are preserved. */
11327
11328 tmp_state = crtc_state->base;
11329 scaler_state = crtc_state->scaler_state;
11330 shared_dpll = crtc_state->shared_dpll;
11331 dpll_hw_state = crtc_state->dpll_hw_state;
11332 force_thru = crtc_state->pch_pfit.force_thru;
11333
11334 memset(crtc_state, 0, sizeof *crtc_state);
11335
11336 crtc_state->base = tmp_state;
11337 crtc_state->scaler_state = scaler_state;
11338 crtc_state->shared_dpll = shared_dpll;
11339 crtc_state->dpll_hw_state = dpll_hw_state;
11340 crtc_state->pch_pfit.force_thru = force_thru;
11341 }
11342
11343 static int
11344 intel_modeset_pipe_config(struct drm_crtc *crtc,
11345 struct intel_crtc_state *pipe_config)
11346 {
11347 struct drm_atomic_state *state = pipe_config->base.state;
11348 struct intel_encoder *encoder;
11349 struct drm_connector *connector;
11350 struct drm_connector_state *connector_state;
11351 int base_bpp, ret = -EINVAL;
11352 int i;
11353 bool retry = true;
11354
11355 clear_intel_crtc_state(pipe_config);
11356
11357 pipe_config->cpu_transcoder =
11358 (enum transcoder) to_intel_crtc(crtc)->pipe;
11359
11360 /*
11361 * Sanitize sync polarity flags based on requested ones. If neither
11362 * positive or negative polarity is requested, treat this as meaning
11363 * negative polarity.
11364 */
11365 if (!(pipe_config->base.adjusted_mode.flags &
11366 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11367 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11368
11369 if (!(pipe_config->base.adjusted_mode.flags &
11370 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11371 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11372
11373 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11374 pipe_config);
11375 if (base_bpp < 0)
11376 goto fail;
11377
11378 /*
11379 * Determine the real pipe dimensions. Note that stereo modes can
11380 * increase the actual pipe size due to the frame doubling and
11381 * insertion of additional space for blanks between the frame. This
11382 * is stored in the crtc timings. We use the requested mode to do this
11383 * computation to clearly distinguish it from the adjusted mode, which
11384 * can be changed by the connectors in the below retry loop.
11385 */
11386 drm_mode_get_hv_timing(&pipe_config->base.mode,
11387 &pipe_config->pipe_src_w,
11388 &pipe_config->pipe_src_h);
11389
11390 for_each_connector_in_state(state, connector, connector_state, i) {
11391 if (connector_state->crtc != crtc)
11392 continue;
11393
11394 encoder = to_intel_encoder(connector_state->best_encoder);
11395
11396 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11397 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11398 goto fail;
11399 }
11400
11401 /*
11402 * Determine output_types before calling the .compute_config()
11403 * hooks so that the hooks can use this information safely.
11404 */
11405 pipe_config->output_types |= 1 << encoder->type;
11406 }
11407
11408 encoder_retry:
11409 /* Ensure the port clock defaults are reset when retrying. */
11410 pipe_config->port_clock = 0;
11411 pipe_config->pixel_multiplier = 1;
11412
11413 /* Fill in default crtc timings, allow encoders to overwrite them. */
11414 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11415 CRTC_STEREO_DOUBLE);
11416
11417 /* Pass our mode to the connectors and the CRTC to give them a chance to
11418 * adjust it according to limitations or connector properties, and also
11419 * a chance to reject the mode entirely.
11420 */
11421 for_each_connector_in_state(state, connector, connector_state, i) {
11422 if (connector_state->crtc != crtc)
11423 continue;
11424
11425 encoder = to_intel_encoder(connector_state->best_encoder);
11426
11427 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11428 DRM_DEBUG_KMS("Encoder config failure\n");
11429 goto fail;
11430 }
11431 }
11432
11433 /* Set default port clock if not overwritten by the encoder. Needs to be
11434 * done afterwards in case the encoder adjusts the mode. */
11435 if (!pipe_config->port_clock)
11436 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11437 * pipe_config->pixel_multiplier;
11438
11439 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11440 if (ret < 0) {
11441 DRM_DEBUG_KMS("CRTC fixup failed\n");
11442 goto fail;
11443 }
11444
11445 if (ret == RETRY) {
11446 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11447 ret = -EINVAL;
11448 goto fail;
11449 }
11450
11451 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11452 retry = false;
11453 goto encoder_retry;
11454 }
11455
11456 /* Dithering seems to not pass-through bits correctly when it should, so
11457 * only enable it on 6bpc panels and when its not a compliance
11458 * test requesting 6bpc video pattern.
11459 */
11460 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11461 !pipe_config->dither_force_disable;
11462 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11463 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11464
11465 fail:
11466 return ret;
11467 }
11468
11469 static void
11470 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11471 {
11472 struct drm_crtc *crtc;
11473 struct drm_crtc_state *crtc_state;
11474 int i;
11475
11476 /* Double check state. */
11477 for_each_crtc_in_state(state, crtc, crtc_state, i) {
11478 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
11479
11480 /* Update hwmode for vblank functions */
11481 if (crtc->state->active)
11482 crtc->hwmode = crtc->state->adjusted_mode;
11483 else
11484 crtc->hwmode.crtc_clock = 0;
11485
11486 /*
11487 * Update legacy state to satisfy fbc code. This can
11488 * be removed when fbc uses the atomic state.
11489 */
11490 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11491 struct drm_plane_state *plane_state = crtc->primary->state;
11492
11493 crtc->primary->fb = plane_state->fb;
11494 crtc->x = plane_state->src_x >> 16;
11495 crtc->y = plane_state->src_y >> 16;
11496 }
11497 }
11498 }
11499
11500 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11501 {
11502 int diff;
11503
11504 if (clock1 == clock2)
11505 return true;
11506
11507 if (!clock1 || !clock2)
11508 return false;
11509
11510 diff = abs(clock1 - clock2);
11511
11512 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11513 return true;
11514
11515 return false;
11516 }
11517
11518 static bool
11519 intel_compare_m_n(unsigned int m, unsigned int n,
11520 unsigned int m2, unsigned int n2,
11521 bool exact)
11522 {
11523 if (m == m2 && n == n2)
11524 return true;
11525
11526 if (exact || !m || !n || !m2 || !n2)
11527 return false;
11528
11529 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11530
11531 if (n > n2) {
11532 while (n > n2) {
11533 m2 <<= 1;
11534 n2 <<= 1;
11535 }
11536 } else if (n < n2) {
11537 while (n < n2) {
11538 m <<= 1;
11539 n <<= 1;
11540 }
11541 }
11542
11543 if (n != n2)
11544 return false;
11545
11546 return intel_fuzzy_clock_check(m, m2);
11547 }
11548
11549 static bool
11550 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11551 struct intel_link_m_n *m2_n2,
11552 bool adjust)
11553 {
11554 if (m_n->tu == m2_n2->tu &&
11555 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11556 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11557 intel_compare_m_n(m_n->link_m, m_n->link_n,
11558 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11559 if (adjust)
11560 *m2_n2 = *m_n;
11561
11562 return true;
11563 }
11564
11565 return false;
11566 }
11567
11568 static void __printf(3, 4)
11569 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11570 {
11571 char *level;
11572 unsigned int category;
11573 struct va_format vaf;
11574 va_list args;
11575
11576 if (adjust) {
11577 level = KERN_DEBUG;
11578 category = DRM_UT_KMS;
11579 } else {
11580 level = KERN_ERR;
11581 category = DRM_UT_NONE;
11582 }
11583
11584 va_start(args, format);
11585 vaf.fmt = format;
11586 vaf.va = &args;
11587
11588 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11589
11590 va_end(args);
11591 }
11592
11593 static bool
11594 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11595 struct intel_crtc_state *current_config,
11596 struct intel_crtc_state *pipe_config,
11597 bool adjust)
11598 {
11599 bool ret = true;
11600
11601 #define PIPE_CONF_CHECK_X(name) \
11602 if (current_config->name != pipe_config->name) { \
11603 pipe_config_err(adjust, __stringify(name), \
11604 "(expected 0x%08x, found 0x%08x)\n", \
11605 current_config->name, \
11606 pipe_config->name); \
11607 ret = false; \
11608 }
11609
11610 #define PIPE_CONF_CHECK_I(name) \
11611 if (current_config->name != pipe_config->name) { \
11612 pipe_config_err(adjust, __stringify(name), \
11613 "(expected %i, found %i)\n", \
11614 current_config->name, \
11615 pipe_config->name); \
11616 ret = false; \
11617 }
11618
11619 #define PIPE_CONF_CHECK_P(name) \
11620 if (current_config->name != pipe_config->name) { \
11621 pipe_config_err(adjust, __stringify(name), \
11622 "(expected %p, found %p)\n", \
11623 current_config->name, \
11624 pipe_config->name); \
11625 ret = false; \
11626 }
11627
11628 #define PIPE_CONF_CHECK_M_N(name) \
11629 if (!intel_compare_link_m_n(&current_config->name, \
11630 &pipe_config->name,\
11631 adjust)) { \
11632 pipe_config_err(adjust, __stringify(name), \
11633 "(expected tu %i gmch %i/%i link %i/%i, " \
11634 "found tu %i, gmch %i/%i link %i/%i)\n", \
11635 current_config->name.tu, \
11636 current_config->name.gmch_m, \
11637 current_config->name.gmch_n, \
11638 current_config->name.link_m, \
11639 current_config->name.link_n, \
11640 pipe_config->name.tu, \
11641 pipe_config->name.gmch_m, \
11642 pipe_config->name.gmch_n, \
11643 pipe_config->name.link_m, \
11644 pipe_config->name.link_n); \
11645 ret = false; \
11646 }
11647
11648 /* This is required for BDW+ where there is only one set of registers for
11649 * switching between high and low RR.
11650 * This macro can be used whenever a comparison has to be made between one
11651 * hw state and multiple sw state variables.
11652 */
11653 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11654 if (!intel_compare_link_m_n(&current_config->name, \
11655 &pipe_config->name, adjust) && \
11656 !intel_compare_link_m_n(&current_config->alt_name, \
11657 &pipe_config->name, adjust)) { \
11658 pipe_config_err(adjust, __stringify(name), \
11659 "(expected tu %i gmch %i/%i link %i/%i, " \
11660 "or tu %i gmch %i/%i link %i/%i, " \
11661 "found tu %i, gmch %i/%i link %i/%i)\n", \
11662 current_config->name.tu, \
11663 current_config->name.gmch_m, \
11664 current_config->name.gmch_n, \
11665 current_config->name.link_m, \
11666 current_config->name.link_n, \
11667 current_config->alt_name.tu, \
11668 current_config->alt_name.gmch_m, \
11669 current_config->alt_name.gmch_n, \
11670 current_config->alt_name.link_m, \
11671 current_config->alt_name.link_n, \
11672 pipe_config->name.tu, \
11673 pipe_config->name.gmch_m, \
11674 pipe_config->name.gmch_n, \
11675 pipe_config->name.link_m, \
11676 pipe_config->name.link_n); \
11677 ret = false; \
11678 }
11679
11680 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11681 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11682 pipe_config_err(adjust, __stringify(name), \
11683 "(%x) (expected %i, found %i)\n", \
11684 (mask), \
11685 current_config->name & (mask), \
11686 pipe_config->name & (mask)); \
11687 ret = false; \
11688 }
11689
11690 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11691 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11692 pipe_config_err(adjust, __stringify(name), \
11693 "(expected %i, found %i)\n", \
11694 current_config->name, \
11695 pipe_config->name); \
11696 ret = false; \
11697 }
11698
11699 #define PIPE_CONF_QUIRK(quirk) \
11700 ((current_config->quirks | pipe_config->quirks) & (quirk))
11701
11702 PIPE_CONF_CHECK_I(cpu_transcoder);
11703
11704 PIPE_CONF_CHECK_I(has_pch_encoder);
11705 PIPE_CONF_CHECK_I(fdi_lanes);
11706 PIPE_CONF_CHECK_M_N(fdi_m_n);
11707
11708 PIPE_CONF_CHECK_I(lane_count);
11709 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11710
11711 if (INTEL_GEN(dev_priv) < 8) {
11712 PIPE_CONF_CHECK_M_N(dp_m_n);
11713
11714 if (current_config->has_drrs)
11715 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11716 } else
11717 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11718
11719 PIPE_CONF_CHECK_X(output_types);
11720
11721 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11722 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11723 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11724 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11725 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11726 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11727
11728 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11729 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11730 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11731 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11732 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11733 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11734
11735 PIPE_CONF_CHECK_I(pixel_multiplier);
11736 PIPE_CONF_CHECK_I(has_hdmi_sink);
11737 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11738 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11739 PIPE_CONF_CHECK_I(limited_color_range);
11740 PIPE_CONF_CHECK_I(has_infoframe);
11741
11742 PIPE_CONF_CHECK_I(has_audio);
11743
11744 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11745 DRM_MODE_FLAG_INTERLACE);
11746
11747 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11748 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11749 DRM_MODE_FLAG_PHSYNC);
11750 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11751 DRM_MODE_FLAG_NHSYNC);
11752 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11753 DRM_MODE_FLAG_PVSYNC);
11754 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11755 DRM_MODE_FLAG_NVSYNC);
11756 }
11757
11758 PIPE_CONF_CHECK_X(gmch_pfit.control);
11759 /* pfit ratios are autocomputed by the hw on gen4+ */
11760 if (INTEL_GEN(dev_priv) < 4)
11761 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11762 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11763
11764 if (!adjust) {
11765 PIPE_CONF_CHECK_I(pipe_src_w);
11766 PIPE_CONF_CHECK_I(pipe_src_h);
11767
11768 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11769 if (current_config->pch_pfit.enabled) {
11770 PIPE_CONF_CHECK_X(pch_pfit.pos);
11771 PIPE_CONF_CHECK_X(pch_pfit.size);
11772 }
11773
11774 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11775 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11776 }
11777
11778 /* BDW+ don't expose a synchronous way to read the state */
11779 if (IS_HASWELL(dev_priv))
11780 PIPE_CONF_CHECK_I(ips_enabled);
11781
11782 PIPE_CONF_CHECK_I(double_wide);
11783
11784 PIPE_CONF_CHECK_P(shared_dpll);
11785 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11786 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11787 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11788 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11789 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11790 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11791 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11792 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11793 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11794
11795 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11796 PIPE_CONF_CHECK_X(dsi_pll.div);
11797
11798 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11799 PIPE_CONF_CHECK_I(pipe_bpp);
11800
11801 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11802 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11803
11804 #undef PIPE_CONF_CHECK_X
11805 #undef PIPE_CONF_CHECK_I
11806 #undef PIPE_CONF_CHECK_P
11807 #undef PIPE_CONF_CHECK_FLAGS
11808 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11809 #undef PIPE_CONF_QUIRK
11810
11811 return ret;
11812 }
11813
11814 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11815 const struct intel_crtc_state *pipe_config)
11816 {
11817 if (pipe_config->has_pch_encoder) {
11818 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11819 &pipe_config->fdi_m_n);
11820 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11821
11822 /*
11823 * FDI already provided one idea for the dotclock.
11824 * Yell if the encoder disagrees.
11825 */
11826 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11827 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11828 fdi_dotclock, dotclock);
11829 }
11830 }
11831
11832 static void verify_wm_state(struct drm_crtc *crtc,
11833 struct drm_crtc_state *new_state)
11834 {
11835 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11836 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11837 struct skl_pipe_wm hw_wm, *sw_wm;
11838 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11839 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11841 const enum pipe pipe = intel_crtc->pipe;
11842 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11843
11844 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11845 return;
11846
11847 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11848 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11849
11850 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11851 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11852
11853 /* planes */
11854 for_each_universal_plane(dev_priv, pipe, plane) {
11855 hw_plane_wm = &hw_wm.planes[plane];
11856 sw_plane_wm = &sw_wm->planes[plane];
11857
11858 /* Watermarks */
11859 for (level = 0; level <= max_level; level++) {
11860 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11861 &sw_plane_wm->wm[level]))
11862 continue;
11863
11864 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11865 pipe_name(pipe), plane + 1, level,
11866 sw_plane_wm->wm[level].plane_en,
11867 sw_plane_wm->wm[level].plane_res_b,
11868 sw_plane_wm->wm[level].plane_res_l,
11869 hw_plane_wm->wm[level].plane_en,
11870 hw_plane_wm->wm[level].plane_res_b,
11871 hw_plane_wm->wm[level].plane_res_l);
11872 }
11873
11874 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11875 &sw_plane_wm->trans_wm)) {
11876 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11877 pipe_name(pipe), plane + 1,
11878 sw_plane_wm->trans_wm.plane_en,
11879 sw_plane_wm->trans_wm.plane_res_b,
11880 sw_plane_wm->trans_wm.plane_res_l,
11881 hw_plane_wm->trans_wm.plane_en,
11882 hw_plane_wm->trans_wm.plane_res_b,
11883 hw_plane_wm->trans_wm.plane_res_l);
11884 }
11885
11886 /* DDB */
11887 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11888 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11889
11890 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11891 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11892 pipe_name(pipe), plane + 1,
11893 sw_ddb_entry->start, sw_ddb_entry->end,
11894 hw_ddb_entry->start, hw_ddb_entry->end);
11895 }
11896 }
11897
11898 /*
11899 * cursor
11900 * If the cursor plane isn't active, we may not have updated it's ddb
11901 * allocation. In that case since the ddb allocation will be updated
11902 * once the plane becomes visible, we can skip this check
11903 */
11904 if (intel_crtc->cursor_addr) {
11905 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11906 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11907
11908 /* Watermarks */
11909 for (level = 0; level <= max_level; level++) {
11910 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11911 &sw_plane_wm->wm[level]))
11912 continue;
11913
11914 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11915 pipe_name(pipe), level,
11916 sw_plane_wm->wm[level].plane_en,
11917 sw_plane_wm->wm[level].plane_res_b,
11918 sw_plane_wm->wm[level].plane_res_l,
11919 hw_plane_wm->wm[level].plane_en,
11920 hw_plane_wm->wm[level].plane_res_b,
11921 hw_plane_wm->wm[level].plane_res_l);
11922 }
11923
11924 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11925 &sw_plane_wm->trans_wm)) {
11926 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11927 pipe_name(pipe),
11928 sw_plane_wm->trans_wm.plane_en,
11929 sw_plane_wm->trans_wm.plane_res_b,
11930 sw_plane_wm->trans_wm.plane_res_l,
11931 hw_plane_wm->trans_wm.plane_en,
11932 hw_plane_wm->trans_wm.plane_res_b,
11933 hw_plane_wm->trans_wm.plane_res_l);
11934 }
11935
11936 /* DDB */
11937 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11938 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11939
11940 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11941 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11942 pipe_name(pipe),
11943 sw_ddb_entry->start, sw_ddb_entry->end,
11944 hw_ddb_entry->start, hw_ddb_entry->end);
11945 }
11946 }
11947 }
11948
11949 static void
11950 verify_connector_state(struct drm_device *dev,
11951 struct drm_atomic_state *state,
11952 struct drm_crtc *crtc)
11953 {
11954 struct drm_connector *connector;
11955 struct drm_connector_state *old_conn_state;
11956 int i;
11957
11958 for_each_connector_in_state(state, connector, old_conn_state, i) {
11959 struct drm_encoder *encoder = connector->encoder;
11960 struct drm_connector_state *state = connector->state;
11961
11962 if (state->crtc != crtc)
11963 continue;
11964
11965 intel_connector_verify_state(to_intel_connector(connector));
11966
11967 I915_STATE_WARN(state->best_encoder != encoder,
11968 "connector's atomic encoder doesn't match legacy encoder\n");
11969 }
11970 }
11971
11972 static void
11973 verify_encoder_state(struct drm_device *dev)
11974 {
11975 struct intel_encoder *encoder;
11976 struct intel_connector *connector;
11977
11978 for_each_intel_encoder(dev, encoder) {
11979 bool enabled = false;
11980 enum pipe pipe;
11981
11982 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11983 encoder->base.base.id,
11984 encoder->base.name);
11985
11986 for_each_intel_connector(dev, connector) {
11987 if (connector->base.state->best_encoder != &encoder->base)
11988 continue;
11989 enabled = true;
11990
11991 I915_STATE_WARN(connector->base.state->crtc !=
11992 encoder->base.crtc,
11993 "connector's crtc doesn't match encoder crtc\n");
11994 }
11995
11996 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11997 "encoder's enabled state mismatch "
11998 "(expected %i, found %i)\n",
11999 !!encoder->base.crtc, enabled);
12000
12001 if (!encoder->base.crtc) {
12002 bool active;
12003
12004 active = encoder->get_hw_state(encoder, &pipe);
12005 I915_STATE_WARN(active,
12006 "encoder detached but still enabled on pipe %c.\n",
12007 pipe_name(pipe));
12008 }
12009 }
12010 }
12011
12012 static void
12013 verify_crtc_state(struct drm_crtc *crtc,
12014 struct drm_crtc_state *old_crtc_state,
12015 struct drm_crtc_state *new_crtc_state)
12016 {
12017 struct drm_device *dev = crtc->dev;
12018 struct drm_i915_private *dev_priv = to_i915(dev);
12019 struct intel_encoder *encoder;
12020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12021 struct intel_crtc_state *pipe_config, *sw_config;
12022 struct drm_atomic_state *old_state;
12023 bool active;
12024
12025 old_state = old_crtc_state->state;
12026 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12027 pipe_config = to_intel_crtc_state(old_crtc_state);
12028 memset(pipe_config, 0, sizeof(*pipe_config));
12029 pipe_config->base.crtc = crtc;
12030 pipe_config->base.state = old_state;
12031
12032 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12033
12034 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12035
12036 /* hw state is inconsistent with the pipe quirk */
12037 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12038 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12039 active = new_crtc_state->active;
12040
12041 I915_STATE_WARN(new_crtc_state->active != active,
12042 "crtc active state doesn't match with hw state "
12043 "(expected %i, found %i)\n", new_crtc_state->active, active);
12044
12045 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12046 "transitional active state does not match atomic hw state "
12047 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12048
12049 for_each_encoder_on_crtc(dev, crtc, encoder) {
12050 enum pipe pipe;
12051
12052 active = encoder->get_hw_state(encoder, &pipe);
12053 I915_STATE_WARN(active != new_crtc_state->active,
12054 "[ENCODER:%i] active %i with crtc active %i\n",
12055 encoder->base.base.id, active, new_crtc_state->active);
12056
12057 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12058 "Encoder connected to wrong pipe %c\n",
12059 pipe_name(pipe));
12060
12061 if (active) {
12062 pipe_config->output_types |= 1 << encoder->type;
12063 encoder->get_config(encoder, pipe_config);
12064 }
12065 }
12066
12067 intel_crtc_compute_pixel_rate(pipe_config);
12068
12069 if (!new_crtc_state->active)
12070 return;
12071
12072 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12073
12074 sw_config = to_intel_crtc_state(crtc->state);
12075 if (!intel_pipe_config_compare(dev_priv, sw_config,
12076 pipe_config, false)) {
12077 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12078 intel_dump_pipe_config(intel_crtc, pipe_config,
12079 "[hw state]");
12080 intel_dump_pipe_config(intel_crtc, sw_config,
12081 "[sw state]");
12082 }
12083 }
12084
12085 static void
12086 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12087 struct intel_shared_dpll *pll,
12088 struct drm_crtc *crtc,
12089 struct drm_crtc_state *new_state)
12090 {
12091 struct intel_dpll_hw_state dpll_hw_state;
12092 unsigned crtc_mask;
12093 bool active;
12094
12095 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12096
12097 DRM_DEBUG_KMS("%s\n", pll->name);
12098
12099 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12100
12101 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12102 I915_STATE_WARN(!pll->on && pll->active_mask,
12103 "pll in active use but not on in sw tracking\n");
12104 I915_STATE_WARN(pll->on && !pll->active_mask,
12105 "pll is on but not used by any active crtc\n");
12106 I915_STATE_WARN(pll->on != active,
12107 "pll on state mismatch (expected %i, found %i)\n",
12108 pll->on, active);
12109 }
12110
12111 if (!crtc) {
12112 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12113 "more active pll users than references: %x vs %x\n",
12114 pll->active_mask, pll->state.crtc_mask);
12115
12116 return;
12117 }
12118
12119 crtc_mask = 1 << drm_crtc_index(crtc);
12120
12121 if (new_state->active)
12122 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12123 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12124 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12125 else
12126 I915_STATE_WARN(pll->active_mask & crtc_mask,
12127 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12128 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12129
12130 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12131 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12132 crtc_mask, pll->state.crtc_mask);
12133
12134 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12135 &dpll_hw_state,
12136 sizeof(dpll_hw_state)),
12137 "pll hw state mismatch\n");
12138 }
12139
12140 static void
12141 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12142 struct drm_crtc_state *old_crtc_state,
12143 struct drm_crtc_state *new_crtc_state)
12144 {
12145 struct drm_i915_private *dev_priv = to_i915(dev);
12146 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12147 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12148
12149 if (new_state->shared_dpll)
12150 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12151
12152 if (old_state->shared_dpll &&
12153 old_state->shared_dpll != new_state->shared_dpll) {
12154 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12155 struct intel_shared_dpll *pll = old_state->shared_dpll;
12156
12157 I915_STATE_WARN(pll->active_mask & crtc_mask,
12158 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12159 pipe_name(drm_crtc_index(crtc)));
12160 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12161 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12162 pipe_name(drm_crtc_index(crtc)));
12163 }
12164 }
12165
12166 static void
12167 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12168 struct drm_atomic_state *state,
12169 struct drm_crtc_state *old_state,
12170 struct drm_crtc_state *new_state)
12171 {
12172 if (!needs_modeset(new_state) &&
12173 !to_intel_crtc_state(new_state)->update_pipe)
12174 return;
12175
12176 verify_wm_state(crtc, new_state);
12177 verify_connector_state(crtc->dev, state, crtc);
12178 verify_crtc_state(crtc, old_state, new_state);
12179 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12180 }
12181
12182 static void
12183 verify_disabled_dpll_state(struct drm_device *dev)
12184 {
12185 struct drm_i915_private *dev_priv = to_i915(dev);
12186 int i;
12187
12188 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12189 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12190 }
12191
12192 static void
12193 intel_modeset_verify_disabled(struct drm_device *dev,
12194 struct drm_atomic_state *state)
12195 {
12196 verify_encoder_state(dev);
12197 verify_connector_state(dev, state, NULL);
12198 verify_disabled_dpll_state(dev);
12199 }
12200
12201 static void update_scanline_offset(struct intel_crtc *crtc)
12202 {
12203 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12204
12205 /*
12206 * The scanline counter increments at the leading edge of hsync.
12207 *
12208 * On most platforms it starts counting from vtotal-1 on the
12209 * first active line. That means the scanline counter value is
12210 * always one less than what we would expect. Ie. just after
12211 * start of vblank, which also occurs at start of hsync (on the
12212 * last active line), the scanline counter will read vblank_start-1.
12213 *
12214 * On gen2 the scanline counter starts counting from 1 instead
12215 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12216 * to keep the value positive), instead of adding one.
12217 *
12218 * On HSW+ the behaviour of the scanline counter depends on the output
12219 * type. For DP ports it behaves like most other platforms, but on HDMI
12220 * there's an extra 1 line difference. So we need to add two instead of
12221 * one to the value.
12222 */
12223 if (IS_GEN2(dev_priv)) {
12224 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12225 int vtotal;
12226
12227 vtotal = adjusted_mode->crtc_vtotal;
12228 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12229 vtotal /= 2;
12230
12231 crtc->scanline_offset = vtotal - 1;
12232 } else if (HAS_DDI(dev_priv) &&
12233 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12234 crtc->scanline_offset = 2;
12235 } else
12236 crtc->scanline_offset = 1;
12237 }
12238
12239 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12240 {
12241 struct drm_device *dev = state->dev;
12242 struct drm_i915_private *dev_priv = to_i915(dev);
12243 struct drm_crtc *crtc;
12244 struct drm_crtc_state *crtc_state;
12245 int i;
12246
12247 if (!dev_priv->display.crtc_compute_clock)
12248 return;
12249
12250 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12252 struct intel_shared_dpll *old_dpll =
12253 to_intel_crtc_state(crtc->state)->shared_dpll;
12254
12255 if (!needs_modeset(crtc_state))
12256 continue;
12257
12258 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
12259
12260 if (!old_dpll)
12261 continue;
12262
12263 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12264 }
12265 }
12266
12267 /*
12268 * This implements the workaround described in the "notes" section of the mode
12269 * set sequence documentation. When going from no pipes or single pipe to
12270 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12271 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12272 */
12273 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12274 {
12275 struct drm_crtc_state *crtc_state;
12276 struct intel_crtc *intel_crtc;
12277 struct drm_crtc *crtc;
12278 struct intel_crtc_state *first_crtc_state = NULL;
12279 struct intel_crtc_state *other_crtc_state = NULL;
12280 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12281 int i;
12282
12283 /* look at all crtc's that are going to be enabled in during modeset */
12284 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12285 intel_crtc = to_intel_crtc(crtc);
12286
12287 if (!crtc_state->active || !needs_modeset(crtc_state))
12288 continue;
12289
12290 if (first_crtc_state) {
12291 other_crtc_state = to_intel_crtc_state(crtc_state);
12292 break;
12293 } else {
12294 first_crtc_state = to_intel_crtc_state(crtc_state);
12295 first_pipe = intel_crtc->pipe;
12296 }
12297 }
12298
12299 /* No workaround needed? */
12300 if (!first_crtc_state)
12301 return 0;
12302
12303 /* w/a possibly needed, check how many crtc's are already enabled. */
12304 for_each_intel_crtc(state->dev, intel_crtc) {
12305 struct intel_crtc_state *pipe_config;
12306
12307 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12308 if (IS_ERR(pipe_config))
12309 return PTR_ERR(pipe_config);
12310
12311 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12312
12313 if (!pipe_config->base.active ||
12314 needs_modeset(&pipe_config->base))
12315 continue;
12316
12317 /* 2 or more enabled crtcs means no need for w/a */
12318 if (enabled_pipe != INVALID_PIPE)
12319 return 0;
12320
12321 enabled_pipe = intel_crtc->pipe;
12322 }
12323
12324 if (enabled_pipe != INVALID_PIPE)
12325 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12326 else if (other_crtc_state)
12327 other_crtc_state->hsw_workaround_pipe = first_pipe;
12328
12329 return 0;
12330 }
12331
12332 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12333 {
12334 struct drm_crtc *crtc;
12335
12336 /* Add all pipes to the state */
12337 for_each_crtc(state->dev, crtc) {
12338 struct drm_crtc_state *crtc_state;
12339
12340 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12341 if (IS_ERR(crtc_state))
12342 return PTR_ERR(crtc_state);
12343 }
12344
12345 return 0;
12346 }
12347
12348 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12349 {
12350 struct drm_crtc *crtc;
12351
12352 /*
12353 * Add all pipes to the state, and force
12354 * a modeset on all the active ones.
12355 */
12356 for_each_crtc(state->dev, crtc) {
12357 struct drm_crtc_state *crtc_state;
12358 int ret;
12359
12360 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12361 if (IS_ERR(crtc_state))
12362 return PTR_ERR(crtc_state);
12363
12364 if (!crtc_state->active || needs_modeset(crtc_state))
12365 continue;
12366
12367 crtc_state->mode_changed = true;
12368
12369 ret = drm_atomic_add_affected_connectors(state, crtc);
12370 if (ret)
12371 return ret;
12372
12373 ret = drm_atomic_add_affected_planes(state, crtc);
12374 if (ret)
12375 return ret;
12376 }
12377
12378 return 0;
12379 }
12380
12381 static int intel_modeset_checks(struct drm_atomic_state *state)
12382 {
12383 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12384 struct drm_i915_private *dev_priv = to_i915(state->dev);
12385 struct drm_crtc *crtc;
12386 struct drm_crtc_state *crtc_state;
12387 int ret = 0, i;
12388
12389 if (!check_digital_port_conflicts(state)) {
12390 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12391 return -EINVAL;
12392 }
12393
12394 intel_state->modeset = true;
12395 intel_state->active_crtcs = dev_priv->active_crtcs;
12396 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12397 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12398
12399 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12400 if (crtc_state->active)
12401 intel_state->active_crtcs |= 1 << i;
12402 else
12403 intel_state->active_crtcs &= ~(1 << i);
12404
12405 if (crtc_state->active != crtc->state->active)
12406 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12407 }
12408
12409 /*
12410 * See if the config requires any additional preparation, e.g.
12411 * to adjust global state with pipes off. We need to do this
12412 * here so we can get the modeset_pipe updated config for the new
12413 * mode set on this crtc. For other crtcs we need to use the
12414 * adjusted_mode bits in the crtc directly.
12415 */
12416 if (dev_priv->display.modeset_calc_cdclk) {
12417 ret = dev_priv->display.modeset_calc_cdclk(state);
12418 if (ret < 0)
12419 return ret;
12420
12421 /*
12422 * Writes to dev_priv->cdclk.logical must protected by
12423 * holding all the crtc locks, even if we don't end up
12424 * touching the hardware
12425 */
12426 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12427 &intel_state->cdclk.logical)) {
12428 ret = intel_lock_all_pipes(state);
12429 if (ret < 0)
12430 return ret;
12431 }
12432
12433 /* All pipes must be switched off while we change the cdclk. */
12434 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12435 &intel_state->cdclk.actual)) {
12436 ret = intel_modeset_all_pipes(state);
12437 if (ret < 0)
12438 return ret;
12439 }
12440
12441 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12442 intel_state->cdclk.logical.cdclk,
12443 intel_state->cdclk.actual.cdclk);
12444 } else {
12445 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12446 }
12447
12448 intel_modeset_clear_plls(state);
12449
12450 if (IS_HASWELL(dev_priv))
12451 return haswell_mode_set_planes_workaround(state);
12452
12453 return 0;
12454 }
12455
12456 /*
12457 * Handle calculation of various watermark data at the end of the atomic check
12458 * phase. The code here should be run after the per-crtc and per-plane 'check'
12459 * handlers to ensure that all derived state has been updated.
12460 */
12461 static int calc_watermark_data(struct drm_atomic_state *state)
12462 {
12463 struct drm_device *dev = state->dev;
12464 struct drm_i915_private *dev_priv = to_i915(dev);
12465
12466 /* Is there platform-specific watermark information to calculate? */
12467 if (dev_priv->display.compute_global_watermarks)
12468 return dev_priv->display.compute_global_watermarks(state);
12469
12470 return 0;
12471 }
12472
12473 /**
12474 * intel_atomic_check - validate state object
12475 * @dev: drm device
12476 * @state: state to validate
12477 */
12478 static int intel_atomic_check(struct drm_device *dev,
12479 struct drm_atomic_state *state)
12480 {
12481 struct drm_i915_private *dev_priv = to_i915(dev);
12482 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12483 struct drm_crtc *crtc;
12484 struct drm_crtc_state *crtc_state;
12485 int ret, i;
12486 bool any_ms = false;
12487
12488 ret = drm_atomic_helper_check_modeset(dev, state);
12489 if (ret)
12490 return ret;
12491
12492 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12493 struct intel_crtc_state *pipe_config =
12494 to_intel_crtc_state(crtc_state);
12495
12496 /* Catch I915_MODE_FLAG_INHERITED */
12497 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12498 crtc_state->mode_changed = true;
12499
12500 if (!needs_modeset(crtc_state))
12501 continue;
12502
12503 if (!crtc_state->enable) {
12504 any_ms = true;
12505 continue;
12506 }
12507
12508 /* FIXME: For only active_changed we shouldn't need to do any
12509 * state recomputation at all. */
12510
12511 ret = drm_atomic_add_affected_connectors(state, crtc);
12512 if (ret)
12513 return ret;
12514
12515 ret = intel_modeset_pipe_config(crtc, pipe_config);
12516 if (ret) {
12517 intel_dump_pipe_config(to_intel_crtc(crtc),
12518 pipe_config, "[failed]");
12519 return ret;
12520 }
12521
12522 if (i915.fastboot &&
12523 intel_pipe_config_compare(dev_priv,
12524 to_intel_crtc_state(crtc->state),
12525 pipe_config, true)) {
12526 crtc_state->mode_changed = false;
12527 to_intel_crtc_state(crtc_state)->update_pipe = true;
12528 }
12529
12530 if (needs_modeset(crtc_state))
12531 any_ms = true;
12532
12533 ret = drm_atomic_add_affected_planes(state, crtc);
12534 if (ret)
12535 return ret;
12536
12537 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12538 needs_modeset(crtc_state) ?
12539 "[modeset]" : "[fastset]");
12540 }
12541
12542 if (any_ms) {
12543 ret = intel_modeset_checks(state);
12544
12545 if (ret)
12546 return ret;
12547 } else {
12548 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12549 }
12550
12551 ret = drm_atomic_helper_check_planes(dev, state);
12552 if (ret)
12553 return ret;
12554
12555 intel_fbc_choose_crtc(dev_priv, state);
12556 return calc_watermark_data(state);
12557 }
12558
12559 static int intel_atomic_prepare_commit(struct drm_device *dev,
12560 struct drm_atomic_state *state)
12561 {
12562 struct drm_i915_private *dev_priv = to_i915(dev);
12563 struct drm_crtc_state *crtc_state;
12564 struct drm_crtc *crtc;
12565 int i, ret;
12566
12567 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12568 if (state->legacy_cursor_update)
12569 continue;
12570
12571 ret = intel_crtc_wait_for_pending_flips(crtc);
12572 if (ret)
12573 return ret;
12574
12575 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12576 flush_workqueue(dev_priv->wq);
12577 }
12578
12579 ret = mutex_lock_interruptible(&dev->struct_mutex);
12580 if (ret)
12581 return ret;
12582
12583 ret = drm_atomic_helper_prepare_planes(dev, state);
12584 mutex_unlock(&dev->struct_mutex);
12585
12586 return ret;
12587 }
12588
12589 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12590 {
12591 struct drm_device *dev = crtc->base.dev;
12592
12593 if (!dev->max_vblank_count)
12594 return drm_accurate_vblank_count(&crtc->base);
12595
12596 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12597 }
12598
12599 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12600 struct drm_i915_private *dev_priv,
12601 unsigned crtc_mask)
12602 {
12603 unsigned last_vblank_count[I915_MAX_PIPES];
12604 enum pipe pipe;
12605 int ret;
12606
12607 if (!crtc_mask)
12608 return;
12609
12610 for_each_pipe(dev_priv, pipe) {
12611 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12612 pipe);
12613
12614 if (!((1 << pipe) & crtc_mask))
12615 continue;
12616
12617 ret = drm_crtc_vblank_get(&crtc->base);
12618 if (WARN_ON(ret != 0)) {
12619 crtc_mask &= ~(1 << pipe);
12620 continue;
12621 }
12622
12623 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12624 }
12625
12626 for_each_pipe(dev_priv, pipe) {
12627 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12628 pipe);
12629 long lret;
12630
12631 if (!((1 << pipe) & crtc_mask))
12632 continue;
12633
12634 lret = wait_event_timeout(dev->vblank[pipe].queue,
12635 last_vblank_count[pipe] !=
12636 drm_crtc_vblank_count(&crtc->base),
12637 msecs_to_jiffies(50));
12638
12639 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12640
12641 drm_crtc_vblank_put(&crtc->base);
12642 }
12643 }
12644
12645 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12646 {
12647 /* fb updated, need to unpin old fb */
12648 if (crtc_state->fb_changed)
12649 return true;
12650
12651 /* wm changes, need vblank before final wm's */
12652 if (crtc_state->update_wm_post)
12653 return true;
12654
12655 /*
12656 * cxsr is re-enabled after vblank.
12657 * This is already handled by crtc_state->update_wm_post,
12658 * but added for clarity.
12659 */
12660 if (crtc_state->disable_cxsr)
12661 return true;
12662
12663 return false;
12664 }
12665
12666 static void intel_update_crtc(struct drm_crtc *crtc,
12667 struct drm_atomic_state *state,
12668 struct drm_crtc_state *old_crtc_state,
12669 unsigned int *crtc_vblank_mask)
12670 {
12671 struct drm_device *dev = crtc->dev;
12672 struct drm_i915_private *dev_priv = to_i915(dev);
12673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12674 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
12675 bool modeset = needs_modeset(crtc->state);
12676
12677 if (modeset) {
12678 update_scanline_offset(intel_crtc);
12679 dev_priv->display.crtc_enable(pipe_config, state);
12680 } else {
12681 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
12682 }
12683
12684 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12685 intel_fbc_enable(
12686 intel_crtc, pipe_config,
12687 to_intel_plane_state(crtc->primary->state));
12688 }
12689
12690 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12691
12692 if (needs_vblank_wait(pipe_config))
12693 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12694 }
12695
12696 static void intel_update_crtcs(struct drm_atomic_state *state,
12697 unsigned int *crtc_vblank_mask)
12698 {
12699 struct drm_crtc *crtc;
12700 struct drm_crtc_state *old_crtc_state;
12701 int i;
12702
12703 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12704 if (!crtc->state->active)
12705 continue;
12706
12707 intel_update_crtc(crtc, state, old_crtc_state,
12708 crtc_vblank_mask);
12709 }
12710 }
12711
12712 static void skl_update_crtcs(struct drm_atomic_state *state,
12713 unsigned int *crtc_vblank_mask)
12714 {
12715 struct drm_i915_private *dev_priv = to_i915(state->dev);
12716 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12717 struct drm_crtc *crtc;
12718 struct intel_crtc *intel_crtc;
12719 struct drm_crtc_state *old_crtc_state;
12720 struct intel_crtc_state *cstate;
12721 unsigned int updated = 0;
12722 bool progress;
12723 enum pipe pipe;
12724 int i;
12725
12726 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12727
12728 for_each_crtc_in_state(state, crtc, old_crtc_state, i)
12729 /* ignore allocations for crtc's that have been turned off. */
12730 if (crtc->state->active)
12731 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12732
12733 /*
12734 * Whenever the number of active pipes changes, we need to make sure we
12735 * update the pipes in the right order so that their ddb allocations
12736 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12737 * cause pipe underruns and other bad stuff.
12738 */
12739 do {
12740 progress = false;
12741
12742 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12743 bool vbl_wait = false;
12744 unsigned int cmask = drm_crtc_mask(crtc);
12745
12746 intel_crtc = to_intel_crtc(crtc);
12747 cstate = to_intel_crtc_state(crtc->state);
12748 pipe = intel_crtc->pipe;
12749
12750 if (updated & cmask || !cstate->base.active)
12751 continue;
12752
12753 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12754 continue;
12755
12756 updated |= cmask;
12757 entries[i] = &cstate->wm.skl.ddb;
12758
12759 /*
12760 * If this is an already active pipe, it's DDB changed,
12761 * and this isn't the last pipe that needs updating
12762 * then we need to wait for a vblank to pass for the
12763 * new ddb allocation to take effect.
12764 */
12765 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12766 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12767 !crtc->state->active_changed &&
12768 intel_state->wm_results.dirty_pipes != updated)
12769 vbl_wait = true;
12770
12771 intel_update_crtc(crtc, state, old_crtc_state,
12772 crtc_vblank_mask);
12773
12774 if (vbl_wait)
12775 intel_wait_for_vblank(dev_priv, pipe);
12776
12777 progress = true;
12778 }
12779 } while (progress);
12780 }
12781
12782 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12783 {
12784 struct intel_atomic_state *state, *next;
12785 struct llist_node *freed;
12786
12787 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12788 llist_for_each_entry_safe(state, next, freed, freed)
12789 drm_atomic_state_put(&state->base);
12790 }
12791
12792 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12793 {
12794 struct drm_i915_private *dev_priv =
12795 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12796
12797 intel_atomic_helper_free_state(dev_priv);
12798 }
12799
12800 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12801 {
12802 struct drm_device *dev = state->dev;
12803 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12804 struct drm_i915_private *dev_priv = to_i915(dev);
12805 struct drm_crtc_state *old_crtc_state;
12806 struct drm_crtc *crtc;
12807 struct intel_crtc_state *intel_cstate;
12808 bool hw_check = intel_state->modeset;
12809 u64 put_domains[I915_MAX_PIPES] = {};
12810 unsigned crtc_vblank_mask = 0;
12811 int i;
12812
12813 drm_atomic_helper_wait_for_dependencies(state);
12814
12815 if (intel_state->modeset)
12816 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12817
12818 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12820
12821 if (needs_modeset(crtc->state) ||
12822 to_intel_crtc_state(crtc->state)->update_pipe) {
12823 hw_check = true;
12824
12825 put_domains[to_intel_crtc(crtc)->pipe] =
12826 modeset_get_crtc_power_domains(crtc,
12827 to_intel_crtc_state(crtc->state));
12828 }
12829
12830 if (!needs_modeset(crtc->state))
12831 continue;
12832
12833 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
12834
12835 if (old_crtc_state->active) {
12836 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12837 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12838 intel_crtc->active = false;
12839 intel_fbc_disable(intel_crtc);
12840 intel_disable_shared_dpll(intel_crtc);
12841
12842 /*
12843 * Underruns don't always raise
12844 * interrupts, so check manually.
12845 */
12846 intel_check_cpu_fifo_underruns(dev_priv);
12847 intel_check_pch_fifo_underruns(dev_priv);
12848
12849 if (!crtc->state->active) {
12850 /*
12851 * Make sure we don't call initial_watermarks
12852 * for ILK-style watermark updates.
12853 */
12854 if (dev_priv->display.atomic_update_watermarks)
12855 dev_priv->display.initial_watermarks(intel_state,
12856 to_intel_crtc_state(crtc->state));
12857 else
12858 intel_update_watermarks(intel_crtc);
12859 }
12860 }
12861 }
12862
12863 /* Only after disabling all output pipelines that will be changed can we
12864 * update the the output configuration. */
12865 intel_modeset_update_crtc_state(state);
12866
12867 if (intel_state->modeset) {
12868 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12869
12870 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12871
12872 /*
12873 * SKL workaround: bspec recommends we disable the SAGV when we
12874 * have more then one pipe enabled
12875 */
12876 if (!intel_can_enable_sagv(state))
12877 intel_disable_sagv(dev_priv);
12878
12879 intel_modeset_verify_disabled(dev, state);
12880 }
12881
12882 /* Complete the events for pipes that have now been disabled */
12883 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12884 bool modeset = needs_modeset(crtc->state);
12885
12886 /* Complete events for now disable pipes here. */
12887 if (modeset && !crtc->state->active && crtc->state->event) {
12888 spin_lock_irq(&dev->event_lock);
12889 drm_crtc_send_vblank_event(crtc, crtc->state->event);
12890 spin_unlock_irq(&dev->event_lock);
12891
12892 crtc->state->event = NULL;
12893 }
12894 }
12895
12896 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12897 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12898
12899 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12900 * already, but still need the state for the delayed optimization. To
12901 * fix this:
12902 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12903 * - schedule that vblank worker _before_ calling hw_done
12904 * - at the start of commit_tail, cancel it _synchrously
12905 * - switch over to the vblank wait helper in the core after that since
12906 * we don't need out special handling any more.
12907 */
12908 if (!state->legacy_cursor_update)
12909 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12910
12911 /*
12912 * Now that the vblank has passed, we can go ahead and program the
12913 * optimal watermarks on platforms that need two-step watermark
12914 * programming.
12915 *
12916 * TODO: Move this (and other cleanup) to an async worker eventually.
12917 */
12918 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12919 intel_cstate = to_intel_crtc_state(crtc->state);
12920
12921 if (dev_priv->display.optimize_watermarks)
12922 dev_priv->display.optimize_watermarks(intel_state,
12923 intel_cstate);
12924 }
12925
12926 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
12927 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12928
12929 if (put_domains[i])
12930 modeset_put_power_domains(dev_priv, put_domains[i]);
12931
12932 intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state);
12933 }
12934
12935 if (intel_state->modeset && intel_can_enable_sagv(state))
12936 intel_enable_sagv(dev_priv);
12937
12938 drm_atomic_helper_commit_hw_done(state);
12939
12940 if (intel_state->modeset)
12941 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12942
12943 mutex_lock(&dev->struct_mutex);
12944 drm_atomic_helper_cleanup_planes(dev, state);
12945 mutex_unlock(&dev->struct_mutex);
12946
12947 drm_atomic_helper_commit_cleanup_done(state);
12948
12949 drm_atomic_state_put(state);
12950
12951 /* As one of the primary mmio accessors, KMS has a high likelihood
12952 * of triggering bugs in unclaimed access. After we finish
12953 * modesetting, see if an error has been flagged, and if so
12954 * enable debugging for the next modeset - and hope we catch
12955 * the culprit.
12956 *
12957 * XXX note that we assume display power is on at this point.
12958 * This might hold true now but we need to add pm helper to check
12959 * unclaimed only when the hardware is on, as atomic commits
12960 * can happen also when the device is completely off.
12961 */
12962 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12963
12964 intel_atomic_helper_free_state(dev_priv);
12965 }
12966
12967 static void intel_atomic_commit_work(struct work_struct *work)
12968 {
12969 struct drm_atomic_state *state =
12970 container_of(work, struct drm_atomic_state, commit_work);
12971
12972 intel_atomic_commit_tail(state);
12973 }
12974
12975 static int __i915_sw_fence_call
12976 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12977 enum i915_sw_fence_notify notify)
12978 {
12979 struct intel_atomic_state *state =
12980 container_of(fence, struct intel_atomic_state, commit_ready);
12981
12982 switch (notify) {
12983 case FENCE_COMPLETE:
12984 if (state->base.commit_work.func)
12985 queue_work(system_unbound_wq, &state->base.commit_work);
12986 break;
12987
12988 case FENCE_FREE:
12989 {
12990 struct intel_atomic_helper *helper =
12991 &to_i915(state->base.dev)->atomic_helper;
12992
12993 if (llist_add(&state->freed, &helper->free_list))
12994 schedule_work(&helper->free_work);
12995 break;
12996 }
12997 }
12998
12999 return NOTIFY_DONE;
13000 }
13001
13002 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13003 {
13004 struct drm_plane_state *old_plane_state;
13005 struct drm_plane *plane;
13006 int i;
13007
13008 for_each_plane_in_state(state, plane, old_plane_state, i)
13009 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13010 intel_fb_obj(plane->state->fb),
13011 to_intel_plane(plane)->frontbuffer_bit);
13012 }
13013
13014 /**
13015 * intel_atomic_commit - commit validated state object
13016 * @dev: DRM device
13017 * @state: the top-level driver state object
13018 * @nonblock: nonblocking commit
13019 *
13020 * This function commits a top-level state object that has been validated
13021 * with drm_atomic_helper_check().
13022 *
13023 * RETURNS
13024 * Zero for success or -errno.
13025 */
13026 static int intel_atomic_commit(struct drm_device *dev,
13027 struct drm_atomic_state *state,
13028 bool nonblock)
13029 {
13030 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13031 struct drm_i915_private *dev_priv = to_i915(dev);
13032 int ret = 0;
13033
13034 ret = drm_atomic_helper_setup_commit(state, nonblock);
13035 if (ret)
13036 return ret;
13037
13038 drm_atomic_state_get(state);
13039 i915_sw_fence_init(&intel_state->commit_ready,
13040 intel_atomic_commit_ready);
13041
13042 ret = intel_atomic_prepare_commit(dev, state);
13043 if (ret) {
13044 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13045 i915_sw_fence_commit(&intel_state->commit_ready);
13046 return ret;
13047 }
13048
13049 drm_atomic_helper_swap_state(state, true);
13050 dev_priv->wm.distrust_bios_wm = false;
13051 intel_shared_dpll_swap_state(state);
13052 intel_atomic_track_fbs(state);
13053
13054 if (intel_state->modeset) {
13055 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13056 sizeof(intel_state->min_pixclk));
13057 dev_priv->active_crtcs = intel_state->active_crtcs;
13058 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13059 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13060 }
13061
13062 drm_atomic_state_get(state);
13063 INIT_WORK(&state->commit_work,
13064 nonblock ? intel_atomic_commit_work : NULL);
13065
13066 i915_sw_fence_commit(&intel_state->commit_ready);
13067 if (!nonblock) {
13068 i915_sw_fence_wait(&intel_state->commit_ready);
13069 intel_atomic_commit_tail(state);
13070 }
13071
13072 return 0;
13073 }
13074
13075 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13076 {
13077 struct drm_device *dev = crtc->dev;
13078 struct drm_atomic_state *state;
13079 struct drm_crtc_state *crtc_state;
13080 int ret;
13081
13082 state = drm_atomic_state_alloc(dev);
13083 if (!state) {
13084 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13085 crtc->base.id, crtc->name);
13086 return;
13087 }
13088
13089 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13090
13091 retry:
13092 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13093 ret = PTR_ERR_OR_ZERO(crtc_state);
13094 if (!ret) {
13095 if (!crtc_state->active)
13096 goto out;
13097
13098 crtc_state->mode_changed = true;
13099 ret = drm_atomic_commit(state);
13100 }
13101
13102 if (ret == -EDEADLK) {
13103 drm_atomic_state_clear(state);
13104 drm_modeset_backoff(state->acquire_ctx);
13105 goto retry;
13106 }
13107
13108 out:
13109 drm_atomic_state_put(state);
13110 }
13111
13112 /*
13113 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13114 * drm_atomic_helper_legacy_gamma_set() directly.
13115 */
13116 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13117 u16 *red, u16 *green, u16 *blue,
13118 uint32_t size)
13119 {
13120 struct drm_device *dev = crtc->dev;
13121 struct drm_mode_config *config = &dev->mode_config;
13122 struct drm_crtc_state *state;
13123 int ret;
13124
13125 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13126 if (ret)
13127 return ret;
13128
13129 /*
13130 * Make sure we update the legacy properties so this works when
13131 * atomic is not enabled.
13132 */
13133
13134 state = crtc->state;
13135
13136 drm_object_property_set_value(&crtc->base,
13137 config->degamma_lut_property,
13138 (state->degamma_lut) ?
13139 state->degamma_lut->base.id : 0);
13140
13141 drm_object_property_set_value(&crtc->base,
13142 config->ctm_property,
13143 (state->ctm) ?
13144 state->ctm->base.id : 0);
13145
13146 drm_object_property_set_value(&crtc->base,
13147 config->gamma_lut_property,
13148 (state->gamma_lut) ?
13149 state->gamma_lut->base.id : 0);
13150
13151 return 0;
13152 }
13153
13154 static const struct drm_crtc_funcs intel_crtc_funcs = {
13155 .gamma_set = intel_atomic_legacy_gamma_set,
13156 .set_config = drm_atomic_helper_set_config,
13157 .set_property = drm_atomic_helper_crtc_set_property,
13158 .destroy = intel_crtc_destroy,
13159 .page_flip = drm_atomic_helper_page_flip,
13160 .atomic_duplicate_state = intel_crtc_duplicate_state,
13161 .atomic_destroy_state = intel_crtc_destroy_state,
13162 .set_crc_source = intel_crtc_set_crc_source,
13163 };
13164
13165 /**
13166 * intel_prepare_plane_fb - Prepare fb for usage on plane
13167 * @plane: drm plane to prepare for
13168 * @fb: framebuffer to prepare for presentation
13169 *
13170 * Prepares a framebuffer for usage on a display plane. Generally this
13171 * involves pinning the underlying object and updating the frontbuffer tracking
13172 * bits. Some older platforms need special physical address handling for
13173 * cursor planes.
13174 *
13175 * Must be called with struct_mutex held.
13176 *
13177 * Returns 0 on success, negative error code on failure.
13178 */
13179 int
13180 intel_prepare_plane_fb(struct drm_plane *plane,
13181 struct drm_plane_state *new_state)
13182 {
13183 struct intel_atomic_state *intel_state =
13184 to_intel_atomic_state(new_state->state);
13185 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13186 struct drm_framebuffer *fb = new_state->fb;
13187 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13188 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13189 int ret;
13190
13191 if (!obj && !old_obj)
13192 return 0;
13193
13194 if (old_obj) {
13195 struct drm_crtc_state *crtc_state =
13196 drm_atomic_get_existing_crtc_state(new_state->state,
13197 plane->state->crtc);
13198
13199 /* Big Hammer, we also need to ensure that any pending
13200 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13201 * current scanout is retired before unpinning the old
13202 * framebuffer. Note that we rely on userspace rendering
13203 * into the buffer attached to the pipe they are waiting
13204 * on. If not, userspace generates a GPU hang with IPEHR
13205 * point to the MI_WAIT_FOR_EVENT.
13206 *
13207 * This should only fail upon a hung GPU, in which case we
13208 * can safely continue.
13209 */
13210 if (needs_modeset(crtc_state)) {
13211 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13212 old_obj->resv, NULL,
13213 false, 0,
13214 GFP_KERNEL);
13215 if (ret < 0)
13216 return ret;
13217 }
13218 }
13219
13220 if (new_state->fence) { /* explicit fencing */
13221 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13222 new_state->fence,
13223 I915_FENCE_TIMEOUT,
13224 GFP_KERNEL);
13225 if (ret < 0)
13226 return ret;
13227 }
13228
13229 if (!obj)
13230 return 0;
13231
13232 if (!new_state->fence) { /* implicit fencing */
13233 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13234 obj->resv, NULL,
13235 false, I915_FENCE_TIMEOUT,
13236 GFP_KERNEL);
13237 if (ret < 0)
13238 return ret;
13239
13240 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13241 }
13242
13243 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13244 INTEL_INFO(dev_priv)->cursor_needs_physical) {
13245 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13246 ret = i915_gem_object_attach_phys(obj, align);
13247 if (ret) {
13248 DRM_DEBUG_KMS("failed to attach phys object\n");
13249 return ret;
13250 }
13251 } else {
13252 struct i915_vma *vma;
13253
13254 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13255 if (IS_ERR(vma)) {
13256 DRM_DEBUG_KMS("failed to pin object\n");
13257 return PTR_ERR(vma);
13258 }
13259
13260 to_intel_plane_state(new_state)->vma = vma;
13261 }
13262
13263 return 0;
13264 }
13265
13266 /**
13267 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13268 * @plane: drm plane to clean up for
13269 * @fb: old framebuffer that was on plane
13270 *
13271 * Cleans up a framebuffer that has just been removed from a plane.
13272 *
13273 * Must be called with struct_mutex held.
13274 */
13275 void
13276 intel_cleanup_plane_fb(struct drm_plane *plane,
13277 struct drm_plane_state *old_state)
13278 {
13279 struct i915_vma *vma;
13280
13281 /* Should only be called after a successful intel_prepare_plane_fb()! */
13282 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13283 if (vma)
13284 intel_unpin_fb_vma(vma);
13285 }
13286
13287 int
13288 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13289 {
13290 int max_scale;
13291 int crtc_clock, cdclk;
13292
13293 if (!intel_crtc || !crtc_state->base.enable)
13294 return DRM_PLANE_HELPER_NO_SCALING;
13295
13296 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13297 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13298
13299 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13300 return DRM_PLANE_HELPER_NO_SCALING;
13301
13302 /*
13303 * skl max scale is lower of:
13304 * close to 3 but not 3, -1 is for that purpose
13305 * or
13306 * cdclk/crtc_clock
13307 */
13308 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13309
13310 return max_scale;
13311 }
13312
13313 static int
13314 intel_check_primary_plane(struct drm_plane *plane,
13315 struct intel_crtc_state *crtc_state,
13316 struct intel_plane_state *state)
13317 {
13318 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13319 struct drm_crtc *crtc = state->base.crtc;
13320 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13321 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13322 bool can_position = false;
13323 int ret;
13324
13325 if (INTEL_GEN(dev_priv) >= 9) {
13326 /* use scaler when colorkey is not required */
13327 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13328 min_scale = 1;
13329 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13330 }
13331 can_position = true;
13332 }
13333
13334 ret = drm_plane_helper_check_state(&state->base,
13335 &state->clip,
13336 min_scale, max_scale,
13337 can_position, true);
13338 if (ret)
13339 return ret;
13340
13341 if (!state->base.fb)
13342 return 0;
13343
13344 if (INTEL_GEN(dev_priv) >= 9) {
13345 ret = skl_check_plane_surface(state);
13346 if (ret)
13347 return ret;
13348 }
13349
13350 return 0;
13351 }
13352
13353 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13354 struct drm_crtc_state *old_crtc_state)
13355 {
13356 struct drm_device *dev = crtc->dev;
13357 struct drm_i915_private *dev_priv = to_i915(dev);
13358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13359 struct intel_crtc_state *intel_cstate =
13360 to_intel_crtc_state(crtc->state);
13361 struct intel_crtc_state *old_intel_cstate =
13362 to_intel_crtc_state(old_crtc_state);
13363 struct intel_atomic_state *old_intel_state =
13364 to_intel_atomic_state(old_crtc_state->state);
13365 bool modeset = needs_modeset(crtc->state);
13366
13367 /* Perform vblank evasion around commit operation */
13368 intel_pipe_update_start(intel_crtc);
13369
13370 if (modeset)
13371 goto out;
13372
13373 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13374 intel_color_set_csc(crtc->state);
13375 intel_color_load_luts(crtc->state);
13376 }
13377
13378 if (intel_cstate->update_pipe)
13379 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13380 else if (INTEL_GEN(dev_priv) >= 9)
13381 skl_detach_scalers(intel_crtc);
13382
13383 out:
13384 if (dev_priv->display.atomic_update_watermarks)
13385 dev_priv->display.atomic_update_watermarks(old_intel_state,
13386 intel_cstate);
13387 }
13388
13389 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13390 struct drm_crtc_state *old_crtc_state)
13391 {
13392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13393
13394 intel_pipe_update_end(intel_crtc, NULL);
13395 }
13396
13397 /**
13398 * intel_plane_destroy - destroy a plane
13399 * @plane: plane to destroy
13400 *
13401 * Common destruction function for all types of planes (primary, cursor,
13402 * sprite).
13403 */
13404 void intel_plane_destroy(struct drm_plane *plane)
13405 {
13406 drm_plane_cleanup(plane);
13407 kfree(to_intel_plane(plane));
13408 }
13409
13410 const struct drm_plane_funcs intel_plane_funcs = {
13411 .update_plane = drm_atomic_helper_update_plane,
13412 .disable_plane = drm_atomic_helper_disable_plane,
13413 .destroy = intel_plane_destroy,
13414 .set_property = drm_atomic_helper_plane_set_property,
13415 .atomic_get_property = intel_plane_atomic_get_property,
13416 .atomic_set_property = intel_plane_atomic_set_property,
13417 .atomic_duplicate_state = intel_plane_duplicate_state,
13418 .atomic_destroy_state = intel_plane_destroy_state,
13419 };
13420
13421 static int
13422 intel_legacy_cursor_update(struct drm_plane *plane,
13423 struct drm_crtc *crtc,
13424 struct drm_framebuffer *fb,
13425 int crtc_x, int crtc_y,
13426 unsigned int crtc_w, unsigned int crtc_h,
13427 uint32_t src_x, uint32_t src_y,
13428 uint32_t src_w, uint32_t src_h)
13429 {
13430 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13431 int ret;
13432 struct drm_plane_state *old_plane_state, *new_plane_state;
13433 struct intel_plane *intel_plane = to_intel_plane(plane);
13434 struct drm_framebuffer *old_fb;
13435 struct drm_crtc_state *crtc_state = crtc->state;
13436 struct i915_vma *old_vma;
13437
13438 /*
13439 * When crtc is inactive or there is a modeset pending,
13440 * wait for it to complete in the slowpath
13441 */
13442 if (!crtc_state->active || needs_modeset(crtc_state) ||
13443 to_intel_crtc_state(crtc_state)->update_pipe)
13444 goto slow;
13445
13446 old_plane_state = plane->state;
13447
13448 /*
13449 * If any parameters change that may affect watermarks,
13450 * take the slowpath. Only changing fb or position should be
13451 * in the fastpath.
13452 */
13453 if (old_plane_state->crtc != crtc ||
13454 old_plane_state->src_w != src_w ||
13455 old_plane_state->src_h != src_h ||
13456 old_plane_state->crtc_w != crtc_w ||
13457 old_plane_state->crtc_h != crtc_h ||
13458 !old_plane_state->visible ||
13459 old_plane_state->fb->modifier != fb->modifier)
13460 goto slow;
13461
13462 new_plane_state = intel_plane_duplicate_state(plane);
13463 if (!new_plane_state)
13464 return -ENOMEM;
13465
13466 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13467
13468 new_plane_state->src_x = src_x;
13469 new_plane_state->src_y = src_y;
13470 new_plane_state->src_w = src_w;
13471 new_plane_state->src_h = src_h;
13472 new_plane_state->crtc_x = crtc_x;
13473 new_plane_state->crtc_y = crtc_y;
13474 new_plane_state->crtc_w = crtc_w;
13475 new_plane_state->crtc_h = crtc_h;
13476
13477 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13478 to_intel_plane_state(new_plane_state));
13479 if (ret)
13480 goto out_free;
13481
13482 /* Visibility changed, must take slowpath. */
13483 if (!new_plane_state->visible)
13484 goto slow_free;
13485
13486 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13487 if (ret)
13488 goto out_free;
13489
13490 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13491 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13492
13493 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13494 if (ret) {
13495 DRM_DEBUG_KMS("failed to attach phys object\n");
13496 goto out_unlock;
13497 }
13498 } else {
13499 struct i915_vma *vma;
13500
13501 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13502 if (IS_ERR(vma)) {
13503 DRM_DEBUG_KMS("failed to pin object\n");
13504
13505 ret = PTR_ERR(vma);
13506 goto out_unlock;
13507 }
13508
13509 to_intel_plane_state(new_plane_state)->vma = vma;
13510 }
13511
13512 old_fb = old_plane_state->fb;
13513 old_vma = to_intel_plane_state(old_plane_state)->vma;
13514
13515 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13516 intel_plane->frontbuffer_bit);
13517
13518 /* Swap plane state */
13519 new_plane_state->fence = old_plane_state->fence;
13520 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13521 new_plane_state->fence = NULL;
13522 new_plane_state->fb = old_fb;
13523 to_intel_plane_state(new_plane_state)->vma = old_vma;
13524
13525 intel_plane->update_plane(plane,
13526 to_intel_crtc_state(crtc->state),
13527 to_intel_plane_state(plane->state));
13528
13529 intel_cleanup_plane_fb(plane, new_plane_state);
13530
13531 out_unlock:
13532 mutex_unlock(&dev_priv->drm.struct_mutex);
13533 out_free:
13534 intel_plane_destroy_state(plane, new_plane_state);
13535 return ret;
13536
13537 slow_free:
13538 intel_plane_destroy_state(plane, new_plane_state);
13539 slow:
13540 return drm_atomic_helper_update_plane(plane, crtc, fb,
13541 crtc_x, crtc_y, crtc_w, crtc_h,
13542 src_x, src_y, src_w, src_h);
13543 }
13544
13545 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13546 .update_plane = intel_legacy_cursor_update,
13547 .disable_plane = drm_atomic_helper_disable_plane,
13548 .destroy = intel_plane_destroy,
13549 .set_property = drm_atomic_helper_plane_set_property,
13550 .atomic_get_property = intel_plane_atomic_get_property,
13551 .atomic_set_property = intel_plane_atomic_set_property,
13552 .atomic_duplicate_state = intel_plane_duplicate_state,
13553 .atomic_destroy_state = intel_plane_destroy_state,
13554 };
13555
13556 static struct intel_plane *
13557 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13558 {
13559 struct intel_plane *primary = NULL;
13560 struct intel_plane_state *state = NULL;
13561 const uint32_t *intel_primary_formats;
13562 unsigned int supported_rotations;
13563 unsigned int num_formats;
13564 int ret;
13565
13566 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13567 if (!primary) {
13568 ret = -ENOMEM;
13569 goto fail;
13570 }
13571
13572 state = intel_create_plane_state(&primary->base);
13573 if (!state) {
13574 ret = -ENOMEM;
13575 goto fail;
13576 }
13577
13578 primary->base.state = &state->base;
13579
13580 primary->can_scale = false;
13581 primary->max_downscale = 1;
13582 if (INTEL_GEN(dev_priv) >= 9) {
13583 primary->can_scale = true;
13584 state->scaler_id = -1;
13585 }
13586 primary->pipe = pipe;
13587 /*
13588 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13589 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13590 */
13591 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13592 primary->plane = (enum plane) !pipe;
13593 else
13594 primary->plane = (enum plane) pipe;
13595 primary->id = PLANE_PRIMARY;
13596 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13597 primary->check_plane = intel_check_primary_plane;
13598
13599 if (INTEL_GEN(dev_priv) >= 9) {
13600 intel_primary_formats = skl_primary_formats;
13601 num_formats = ARRAY_SIZE(skl_primary_formats);
13602
13603 primary->update_plane = skylake_update_primary_plane;
13604 primary->disable_plane = skylake_disable_primary_plane;
13605 } else if (HAS_PCH_SPLIT(dev_priv)) {
13606 intel_primary_formats = i965_primary_formats;
13607 num_formats = ARRAY_SIZE(i965_primary_formats);
13608
13609 primary->update_plane = ironlake_update_primary_plane;
13610 primary->disable_plane = i9xx_disable_primary_plane;
13611 } else if (INTEL_GEN(dev_priv) >= 4) {
13612 intel_primary_formats = i965_primary_formats;
13613 num_formats = ARRAY_SIZE(i965_primary_formats);
13614
13615 primary->update_plane = i9xx_update_primary_plane;
13616 primary->disable_plane = i9xx_disable_primary_plane;
13617 } else {
13618 intel_primary_formats = i8xx_primary_formats;
13619 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13620
13621 primary->update_plane = i9xx_update_primary_plane;
13622 primary->disable_plane = i9xx_disable_primary_plane;
13623 }
13624
13625 if (INTEL_GEN(dev_priv) >= 9)
13626 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13627 0, &intel_plane_funcs,
13628 intel_primary_formats, num_formats,
13629 DRM_PLANE_TYPE_PRIMARY,
13630 "plane 1%c", pipe_name(pipe));
13631 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13632 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13633 0, &intel_plane_funcs,
13634 intel_primary_formats, num_formats,
13635 DRM_PLANE_TYPE_PRIMARY,
13636 "primary %c", pipe_name(pipe));
13637 else
13638 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13639 0, &intel_plane_funcs,
13640 intel_primary_formats, num_formats,
13641 DRM_PLANE_TYPE_PRIMARY,
13642 "plane %c", plane_name(primary->plane));
13643 if (ret)
13644 goto fail;
13645
13646 if (INTEL_GEN(dev_priv) >= 9) {
13647 supported_rotations =
13648 DRM_ROTATE_0 | DRM_ROTATE_90 |
13649 DRM_ROTATE_180 | DRM_ROTATE_270;
13650 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13651 supported_rotations =
13652 DRM_ROTATE_0 | DRM_ROTATE_180 |
13653 DRM_REFLECT_X;
13654 } else if (INTEL_GEN(dev_priv) >= 4) {
13655 supported_rotations =
13656 DRM_ROTATE_0 | DRM_ROTATE_180;
13657 } else {
13658 supported_rotations = DRM_ROTATE_0;
13659 }
13660
13661 if (INTEL_GEN(dev_priv) >= 4)
13662 drm_plane_create_rotation_property(&primary->base,
13663 DRM_ROTATE_0,
13664 supported_rotations);
13665
13666 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13667
13668 return primary;
13669
13670 fail:
13671 kfree(state);
13672 kfree(primary);
13673
13674 return ERR_PTR(ret);
13675 }
13676
13677 static int
13678 intel_check_cursor_plane(struct drm_plane *plane,
13679 struct intel_crtc_state *crtc_state,
13680 struct intel_plane_state *state)
13681 {
13682 struct drm_framebuffer *fb = state->base.fb;
13683 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13684 enum pipe pipe = to_intel_plane(plane)->pipe;
13685 unsigned stride;
13686 int ret;
13687
13688 ret = drm_plane_helper_check_state(&state->base,
13689 &state->clip,
13690 DRM_PLANE_HELPER_NO_SCALING,
13691 DRM_PLANE_HELPER_NO_SCALING,
13692 true, true);
13693 if (ret)
13694 return ret;
13695
13696 /* if we want to turn off the cursor ignore width and height */
13697 if (!obj)
13698 return 0;
13699
13700 /* Check for which cursor types we support */
13701 if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
13702 state->base.crtc_h)) {
13703 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13704 state->base.crtc_w, state->base.crtc_h);
13705 return -EINVAL;
13706 }
13707
13708 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13709 if (obj->base.size < stride * state->base.crtc_h) {
13710 DRM_DEBUG_KMS("buffer is too small\n");
13711 return -ENOMEM;
13712 }
13713
13714 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
13715 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13716 return -EINVAL;
13717 }
13718
13719 /*
13720 * There's something wrong with the cursor on CHV pipe C.
13721 * If it straddles the left edge of the screen then
13722 * moving it away from the edge or disabling it often
13723 * results in a pipe underrun, and often that can lead to
13724 * dead pipe (constant underrun reported, and it scans
13725 * out just a solid color). To recover from that, the
13726 * display power well must be turned off and on again.
13727 * Refuse the put the cursor into that compromised position.
13728 */
13729 if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
13730 state->base.visible && state->base.crtc_x < 0) {
13731 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13732 return -EINVAL;
13733 }
13734
13735 return 0;
13736 }
13737
13738 static void
13739 intel_disable_cursor_plane(struct drm_plane *plane,
13740 struct drm_crtc *crtc)
13741 {
13742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13743
13744 intel_crtc->cursor_addr = 0;
13745 intel_crtc_update_cursor(crtc, NULL);
13746 }
13747
13748 static void
13749 intel_update_cursor_plane(struct drm_plane *plane,
13750 const struct intel_crtc_state *crtc_state,
13751 const struct intel_plane_state *state)
13752 {
13753 struct drm_crtc *crtc = crtc_state->base.crtc;
13754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13755 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13756 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13757 uint32_t addr;
13758
13759 if (!obj)
13760 addr = 0;
13761 else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13762 addr = intel_plane_ggtt_offset(state);
13763 else
13764 addr = obj->phys_handle->busaddr;
13765
13766 intel_crtc->cursor_addr = addr;
13767 intel_crtc_update_cursor(crtc, state);
13768 }
13769
13770 static struct intel_plane *
13771 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13772 {
13773 struct intel_plane *cursor = NULL;
13774 struct intel_plane_state *state = NULL;
13775 int ret;
13776
13777 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13778 if (!cursor) {
13779 ret = -ENOMEM;
13780 goto fail;
13781 }
13782
13783 state = intel_create_plane_state(&cursor->base);
13784 if (!state) {
13785 ret = -ENOMEM;
13786 goto fail;
13787 }
13788
13789 cursor->base.state = &state->base;
13790
13791 cursor->can_scale = false;
13792 cursor->max_downscale = 1;
13793 cursor->pipe = pipe;
13794 cursor->plane = pipe;
13795 cursor->id = PLANE_CURSOR;
13796 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13797 cursor->check_plane = intel_check_cursor_plane;
13798 cursor->update_plane = intel_update_cursor_plane;
13799 cursor->disable_plane = intel_disable_cursor_plane;
13800
13801 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13802 0, &intel_cursor_plane_funcs,
13803 intel_cursor_formats,
13804 ARRAY_SIZE(intel_cursor_formats),
13805 DRM_PLANE_TYPE_CURSOR,
13806 "cursor %c", pipe_name(pipe));
13807 if (ret)
13808 goto fail;
13809
13810 if (INTEL_GEN(dev_priv) >= 4)
13811 drm_plane_create_rotation_property(&cursor->base,
13812 DRM_ROTATE_0,
13813 DRM_ROTATE_0 |
13814 DRM_ROTATE_180);
13815
13816 if (INTEL_GEN(dev_priv) >= 9)
13817 state->scaler_id = -1;
13818
13819 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13820
13821 return cursor;
13822
13823 fail:
13824 kfree(state);
13825 kfree(cursor);
13826
13827 return ERR_PTR(ret);
13828 }
13829
13830 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13831 struct intel_crtc_state *crtc_state)
13832 {
13833 struct intel_crtc_scaler_state *scaler_state =
13834 &crtc_state->scaler_state;
13835 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13836 int i;
13837
13838 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13839 if (!crtc->num_scalers)
13840 return;
13841
13842 for (i = 0; i < crtc->num_scalers; i++) {
13843 struct intel_scaler *scaler = &scaler_state->scalers[i];
13844
13845 scaler->in_use = 0;
13846 scaler->mode = PS_SCALER_MODE_DYN;
13847 }
13848
13849 scaler_state->scaler_id = -1;
13850 }
13851
13852 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13853 {
13854 struct intel_crtc *intel_crtc;
13855 struct intel_crtc_state *crtc_state = NULL;
13856 struct intel_plane *primary = NULL;
13857 struct intel_plane *cursor = NULL;
13858 int sprite, ret;
13859
13860 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13861 if (!intel_crtc)
13862 return -ENOMEM;
13863
13864 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13865 if (!crtc_state) {
13866 ret = -ENOMEM;
13867 goto fail;
13868 }
13869 intel_crtc->config = crtc_state;
13870 intel_crtc->base.state = &crtc_state->base;
13871 crtc_state->base.crtc = &intel_crtc->base;
13872
13873 primary = intel_primary_plane_create(dev_priv, pipe);
13874 if (IS_ERR(primary)) {
13875 ret = PTR_ERR(primary);
13876 goto fail;
13877 }
13878 intel_crtc->plane_ids_mask |= BIT(primary->id);
13879
13880 for_each_sprite(dev_priv, pipe, sprite) {
13881 struct intel_plane *plane;
13882
13883 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13884 if (IS_ERR(plane)) {
13885 ret = PTR_ERR(plane);
13886 goto fail;
13887 }
13888 intel_crtc->plane_ids_mask |= BIT(plane->id);
13889 }
13890
13891 cursor = intel_cursor_plane_create(dev_priv, pipe);
13892 if (IS_ERR(cursor)) {
13893 ret = PTR_ERR(cursor);
13894 goto fail;
13895 }
13896 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13897
13898 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13899 &primary->base, &cursor->base,
13900 &intel_crtc_funcs,
13901 "pipe %c", pipe_name(pipe));
13902 if (ret)
13903 goto fail;
13904
13905 intel_crtc->pipe = pipe;
13906 intel_crtc->plane = primary->plane;
13907
13908 intel_crtc->cursor_base = ~0;
13909 intel_crtc->cursor_cntl = ~0;
13910 intel_crtc->cursor_size = ~0;
13911
13912 intel_crtc->wm.cxsr_allowed = true;
13913
13914 /* initialize shared scalers */
13915 intel_crtc_init_scalers(intel_crtc, crtc_state);
13916
13917 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13918 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13919 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13920 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13921
13922 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13923
13924 intel_color_init(&intel_crtc->base);
13925
13926 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13927
13928 return 0;
13929
13930 fail:
13931 /*
13932 * drm_mode_config_cleanup() will free up any
13933 * crtcs/planes already initialized.
13934 */
13935 kfree(crtc_state);
13936 kfree(intel_crtc);
13937
13938 return ret;
13939 }
13940
13941 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13942 {
13943 struct drm_encoder *encoder = connector->base.encoder;
13944 struct drm_device *dev = connector->base.dev;
13945
13946 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13947
13948 if (!encoder || WARN_ON(!encoder->crtc))
13949 return INVALID_PIPE;
13950
13951 return to_intel_crtc(encoder->crtc)->pipe;
13952 }
13953
13954 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13955 struct drm_file *file)
13956 {
13957 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13958 struct drm_crtc *drmmode_crtc;
13959 struct intel_crtc *crtc;
13960
13961 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13962 if (!drmmode_crtc)
13963 return -ENOENT;
13964
13965 crtc = to_intel_crtc(drmmode_crtc);
13966 pipe_from_crtc_id->pipe = crtc->pipe;
13967
13968 return 0;
13969 }
13970
13971 static int intel_encoder_clones(struct intel_encoder *encoder)
13972 {
13973 struct drm_device *dev = encoder->base.dev;
13974 struct intel_encoder *source_encoder;
13975 int index_mask = 0;
13976 int entry = 0;
13977
13978 for_each_intel_encoder(dev, source_encoder) {
13979 if (encoders_cloneable(encoder, source_encoder))
13980 index_mask |= (1 << entry);
13981
13982 entry++;
13983 }
13984
13985 return index_mask;
13986 }
13987
13988 static bool has_edp_a(struct drm_i915_private *dev_priv)
13989 {
13990 if (!IS_MOBILE(dev_priv))
13991 return false;
13992
13993 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13994 return false;
13995
13996 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13997 return false;
13998
13999 return true;
14000 }
14001
14002 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14003 {
14004 if (INTEL_GEN(dev_priv) >= 9)
14005 return false;
14006
14007 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14008 return false;
14009
14010 if (IS_CHERRYVIEW(dev_priv))
14011 return false;
14012
14013 if (HAS_PCH_LPT_H(dev_priv) &&
14014 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14015 return false;
14016
14017 /* DDI E can't be used if DDI A requires 4 lanes */
14018 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14019 return false;
14020
14021 if (!dev_priv->vbt.int_crt_support)
14022 return false;
14023
14024 return true;
14025 }
14026
14027 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14028 {
14029 int pps_num;
14030 int pps_idx;
14031
14032 if (HAS_DDI(dev_priv))
14033 return;
14034 /*
14035 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14036 * everywhere where registers can be write protected.
14037 */
14038 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14039 pps_num = 2;
14040 else
14041 pps_num = 1;
14042
14043 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14044 u32 val = I915_READ(PP_CONTROL(pps_idx));
14045
14046 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14047 I915_WRITE(PP_CONTROL(pps_idx), val);
14048 }
14049 }
14050
14051 static void intel_pps_init(struct drm_i915_private *dev_priv)
14052 {
14053 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14054 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14055 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14056 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14057 else
14058 dev_priv->pps_mmio_base = PPS_BASE;
14059
14060 intel_pps_unlock_regs_wa(dev_priv);
14061 }
14062
14063 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14064 {
14065 struct intel_encoder *encoder;
14066 bool dpd_is_edp = false;
14067
14068 intel_pps_init(dev_priv);
14069
14070 /*
14071 * intel_edp_init_connector() depends on this completing first, to
14072 * prevent the registeration of both eDP and LVDS and the incorrect
14073 * sharing of the PPS.
14074 */
14075 intel_lvds_init(dev_priv);
14076
14077 if (intel_crt_present(dev_priv))
14078 intel_crt_init(dev_priv);
14079
14080 if (IS_GEN9_LP(dev_priv)) {
14081 /*
14082 * FIXME: Broxton doesn't support port detection via the
14083 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14084 * detect the ports.
14085 */
14086 intel_ddi_init(dev_priv, PORT_A);
14087 intel_ddi_init(dev_priv, PORT_B);
14088 intel_ddi_init(dev_priv, PORT_C);
14089
14090 intel_dsi_init(dev_priv);
14091 } else if (HAS_DDI(dev_priv)) {
14092 int found;
14093
14094 /*
14095 * Haswell uses DDI functions to detect digital outputs.
14096 * On SKL pre-D0 the strap isn't connected, so we assume
14097 * it's there.
14098 */
14099 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14100 /* WaIgnoreDDIAStrap: skl */
14101 if (found || IS_GEN9_BC(dev_priv))
14102 intel_ddi_init(dev_priv, PORT_A);
14103
14104 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14105 * register */
14106 found = I915_READ(SFUSE_STRAP);
14107
14108 if (found & SFUSE_STRAP_DDIB_DETECTED)
14109 intel_ddi_init(dev_priv, PORT_B);
14110 if (found & SFUSE_STRAP_DDIC_DETECTED)
14111 intel_ddi_init(dev_priv, PORT_C);
14112 if (found & SFUSE_STRAP_DDID_DETECTED)
14113 intel_ddi_init(dev_priv, PORT_D);
14114 /*
14115 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14116 */
14117 if (IS_GEN9_BC(dev_priv) &&
14118 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14119 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14120 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14121 intel_ddi_init(dev_priv, PORT_E);
14122
14123 } else if (HAS_PCH_SPLIT(dev_priv)) {
14124 int found;
14125 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14126
14127 if (has_edp_a(dev_priv))
14128 intel_dp_init(dev_priv, DP_A, PORT_A);
14129
14130 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14131 /* PCH SDVOB multiplex with HDMIB */
14132 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14133 if (!found)
14134 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14135 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14136 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14137 }
14138
14139 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14140 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14141
14142 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14143 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14144
14145 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14146 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14147
14148 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14149 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14150 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14151 bool has_edp, has_port;
14152
14153 /*
14154 * The DP_DETECTED bit is the latched state of the DDC
14155 * SDA pin at boot. However since eDP doesn't require DDC
14156 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14157 * eDP ports may have been muxed to an alternate function.
14158 * Thus we can't rely on the DP_DETECTED bit alone to detect
14159 * eDP ports. Consult the VBT as well as DP_DETECTED to
14160 * detect eDP ports.
14161 *
14162 * Sadly the straps seem to be missing sometimes even for HDMI
14163 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14164 * and VBT for the presence of the port. Additionally we can't
14165 * trust the port type the VBT declares as we've seen at least
14166 * HDMI ports that the VBT claim are DP or eDP.
14167 */
14168 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14169 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14170 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14171 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14172 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14173 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14174
14175 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14176 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14177 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14178 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14179 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14180 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14181
14182 if (IS_CHERRYVIEW(dev_priv)) {
14183 /*
14184 * eDP not supported on port D,
14185 * so no need to worry about it
14186 */
14187 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14188 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14189 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14190 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14191 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14192 }
14193
14194 intel_dsi_init(dev_priv);
14195 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14196 bool found = false;
14197
14198 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14199 DRM_DEBUG_KMS("probing SDVOB\n");
14200 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14201 if (!found && IS_G4X(dev_priv)) {
14202 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14203 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14204 }
14205
14206 if (!found && IS_G4X(dev_priv))
14207 intel_dp_init(dev_priv, DP_B, PORT_B);
14208 }
14209
14210 /* Before G4X SDVOC doesn't have its own detect register */
14211
14212 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14213 DRM_DEBUG_KMS("probing SDVOC\n");
14214 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14215 }
14216
14217 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14218
14219 if (IS_G4X(dev_priv)) {
14220 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14221 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14222 }
14223 if (IS_G4X(dev_priv))
14224 intel_dp_init(dev_priv, DP_C, PORT_C);
14225 }
14226
14227 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14228 intel_dp_init(dev_priv, DP_D, PORT_D);
14229 } else if (IS_GEN2(dev_priv))
14230 intel_dvo_init(dev_priv);
14231
14232 if (SUPPORTS_TV(dev_priv))
14233 intel_tv_init(dev_priv);
14234
14235 intel_psr_init(dev_priv);
14236
14237 for_each_intel_encoder(&dev_priv->drm, encoder) {
14238 encoder->base.possible_crtcs = encoder->crtc_mask;
14239 encoder->base.possible_clones =
14240 intel_encoder_clones(encoder);
14241 }
14242
14243 intel_init_pch_refclk(dev_priv);
14244
14245 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14246 }
14247
14248 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14249 {
14250 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14251
14252 drm_framebuffer_cleanup(fb);
14253
14254 WARN_ON(atomic_dec_return(&intel_fb->obj->framebuffer_references) < 0);
14255 i915_gem_object_put(intel_fb->obj);
14256
14257 kfree(intel_fb);
14258 }
14259
14260 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14261 struct drm_file *file,
14262 unsigned int *handle)
14263 {
14264 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14265 struct drm_i915_gem_object *obj = intel_fb->obj;
14266
14267 if (obj->userptr.mm) {
14268 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14269 return -EINVAL;
14270 }
14271
14272 return drm_gem_handle_create(file, &obj->base, handle);
14273 }
14274
14275 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14276 struct drm_file *file,
14277 unsigned flags, unsigned color,
14278 struct drm_clip_rect *clips,
14279 unsigned num_clips)
14280 {
14281 struct drm_device *dev = fb->dev;
14282 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14283 struct drm_i915_gem_object *obj = intel_fb->obj;
14284
14285 mutex_lock(&dev->struct_mutex);
14286 if (obj->pin_display && obj->cache_dirty)
14287 i915_gem_clflush_object(obj, true);
14288 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14289 mutex_unlock(&dev->struct_mutex);
14290
14291 return 0;
14292 }
14293
14294 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14295 .destroy = intel_user_framebuffer_destroy,
14296 .create_handle = intel_user_framebuffer_create_handle,
14297 .dirty = intel_user_framebuffer_dirty,
14298 };
14299
14300 static
14301 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14302 uint64_t fb_modifier, uint32_t pixel_format)
14303 {
14304 u32 gen = INTEL_GEN(dev_priv);
14305
14306 if (gen >= 9) {
14307 int cpp = drm_format_plane_cpp(pixel_format, 0);
14308
14309 /* "The stride in bytes must not exceed the of the size of 8K
14310 * pixels and 32K bytes."
14311 */
14312 return min(8192 * cpp, 32768);
14313 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14314 return 32*1024;
14315 } else if (gen >= 4) {
14316 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14317 return 16*1024;
14318 else
14319 return 32*1024;
14320 } else if (gen >= 3) {
14321 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14322 return 8*1024;
14323 else
14324 return 16*1024;
14325 } else {
14326 /* XXX DSPC is limited to 4k tiled */
14327 return 8*1024;
14328 }
14329 }
14330
14331 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14332 struct drm_i915_gem_object *obj,
14333 struct drm_mode_fb_cmd2 *mode_cmd)
14334 {
14335 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14336 unsigned int tiling = i915_gem_object_get_tiling(obj);
14337 u32 pitch_limit, stride_alignment;
14338 struct drm_format_name_buf format_name;
14339 int ret = -EINVAL;
14340
14341 atomic_inc(&obj->framebuffer_references);
14342
14343 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14344 /*
14345 * If there's a fence, enforce that
14346 * the fb modifier and tiling mode match.
14347 */
14348 if (tiling != I915_TILING_NONE &&
14349 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14350 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14351 goto err;
14352 }
14353 } else {
14354 if (tiling == I915_TILING_X) {
14355 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14356 } else if (tiling == I915_TILING_Y) {
14357 DRM_DEBUG("No Y tiling for legacy addfb\n");
14358 goto err;
14359 }
14360 }
14361
14362 /* Passed in modifier sanity checking. */
14363 switch (mode_cmd->modifier[0]) {
14364 case I915_FORMAT_MOD_Y_TILED:
14365 case I915_FORMAT_MOD_Yf_TILED:
14366 if (INTEL_GEN(dev_priv) < 9) {
14367 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14368 mode_cmd->modifier[0]);
14369 goto err;
14370 }
14371 case DRM_FORMAT_MOD_NONE:
14372 case I915_FORMAT_MOD_X_TILED:
14373 break;
14374 default:
14375 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14376 mode_cmd->modifier[0]);
14377 goto err;
14378 }
14379
14380 /*
14381 * gen2/3 display engine uses the fence if present,
14382 * so the tiling mode must match the fb modifier exactly.
14383 */
14384 if (INTEL_INFO(dev_priv)->gen < 4 &&
14385 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14386 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
14387 return -EINVAL;
14388 }
14389
14390 stride_alignment = intel_fb_stride_alignment(dev_priv,
14391 mode_cmd->modifier[0],
14392 mode_cmd->pixel_format);
14393 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14394 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14395 mode_cmd->pitches[0], stride_alignment);
14396 goto err;
14397 }
14398
14399 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14400 mode_cmd->pixel_format);
14401 if (mode_cmd->pitches[0] > pitch_limit) {
14402 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14403 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14404 "tiled" : "linear",
14405 mode_cmd->pitches[0], pitch_limit);
14406 goto err;
14407 }
14408
14409 /*
14410 * If there's a fence, enforce that
14411 * the fb pitch and fence stride match.
14412 */
14413 if (tiling != I915_TILING_NONE &&
14414 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
14415 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14416 mode_cmd->pitches[0],
14417 i915_gem_object_get_stride(obj));
14418 goto err;
14419 }
14420
14421 /* Reject formats not supported by any plane early. */
14422 switch (mode_cmd->pixel_format) {
14423 case DRM_FORMAT_C8:
14424 case DRM_FORMAT_RGB565:
14425 case DRM_FORMAT_XRGB8888:
14426 case DRM_FORMAT_ARGB8888:
14427 break;
14428 case DRM_FORMAT_XRGB1555:
14429 if (INTEL_GEN(dev_priv) > 3) {
14430 DRM_DEBUG("unsupported pixel format: %s\n",
14431 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14432 return -EINVAL;
14433 }
14434 break;
14435 case DRM_FORMAT_ABGR8888:
14436 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14437 INTEL_GEN(dev_priv) < 9) {
14438 DRM_DEBUG("unsupported pixel format: %s\n",
14439 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14440 return -EINVAL;
14441 }
14442 break;
14443 case DRM_FORMAT_XBGR8888:
14444 case DRM_FORMAT_XRGB2101010:
14445 case DRM_FORMAT_XBGR2101010:
14446 if (INTEL_GEN(dev_priv) < 4) {
14447 DRM_DEBUG("unsupported pixel format: %s\n",
14448 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14449 return -EINVAL;
14450 }
14451 break;
14452 case DRM_FORMAT_ABGR2101010:
14453 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14454 DRM_DEBUG("unsupported pixel format: %s\n",
14455 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14456 return -EINVAL;
14457 }
14458 break;
14459 case DRM_FORMAT_YUYV:
14460 case DRM_FORMAT_UYVY:
14461 case DRM_FORMAT_YVYU:
14462 case DRM_FORMAT_VYUY:
14463 if (INTEL_GEN(dev_priv) < 5) {
14464 DRM_DEBUG("unsupported pixel format: %s\n",
14465 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14466 return -EINVAL;
14467 }
14468 break;
14469 default:
14470 DRM_DEBUG("unsupported pixel format: %s\n",
14471 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14472 return -EINVAL;
14473 }
14474
14475 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14476 if (mode_cmd->offsets[0] != 0)
14477 goto err;
14478
14479 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14480 &intel_fb->base, mode_cmd);
14481 intel_fb->obj = obj;
14482
14483 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14484 if (ret)
14485 return ret;
14486
14487 ret = drm_framebuffer_init(obj->base.dev,
14488 &intel_fb->base,
14489 &intel_fb_funcs);
14490 if (ret) {
14491 DRM_ERROR("framebuffer init failed %d\n", ret);
14492 goto err;
14493 }
14494
14495 return 0;
14496
14497 err:
14498 atomic_dec(&obj->framebuffer_references);
14499 return ret;
14500 }
14501
14502 static struct drm_framebuffer *
14503 intel_user_framebuffer_create(struct drm_device *dev,
14504 struct drm_file *filp,
14505 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14506 {
14507 struct drm_framebuffer *fb;
14508 struct drm_i915_gem_object *obj;
14509 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14510
14511 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14512 if (!obj)
14513 return ERR_PTR(-ENOENT);
14514
14515 fb = intel_framebuffer_create(obj, &mode_cmd);
14516 if (IS_ERR(fb))
14517 i915_gem_object_put(obj);
14518
14519 return fb;
14520 }
14521
14522 static void intel_atomic_state_free(struct drm_atomic_state *state)
14523 {
14524 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14525
14526 drm_atomic_state_default_release(state);
14527
14528 i915_sw_fence_fini(&intel_state->commit_ready);
14529
14530 kfree(state);
14531 }
14532
14533 static const struct drm_mode_config_funcs intel_mode_funcs = {
14534 .fb_create = intel_user_framebuffer_create,
14535 .output_poll_changed = intel_fbdev_output_poll_changed,
14536 .atomic_check = intel_atomic_check,
14537 .atomic_commit = intel_atomic_commit,
14538 .atomic_state_alloc = intel_atomic_state_alloc,
14539 .atomic_state_clear = intel_atomic_state_clear,
14540 .atomic_state_free = intel_atomic_state_free,
14541 };
14542
14543 /**
14544 * intel_init_display_hooks - initialize the display modesetting hooks
14545 * @dev_priv: device private
14546 */
14547 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14548 {
14549 intel_init_cdclk_hooks(dev_priv);
14550
14551 if (INTEL_INFO(dev_priv)->gen >= 9) {
14552 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14553 dev_priv->display.get_initial_plane_config =
14554 skylake_get_initial_plane_config;
14555 dev_priv->display.crtc_compute_clock =
14556 haswell_crtc_compute_clock;
14557 dev_priv->display.crtc_enable = haswell_crtc_enable;
14558 dev_priv->display.crtc_disable = haswell_crtc_disable;
14559 } else if (HAS_DDI(dev_priv)) {
14560 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14561 dev_priv->display.get_initial_plane_config =
14562 ironlake_get_initial_plane_config;
14563 dev_priv->display.crtc_compute_clock =
14564 haswell_crtc_compute_clock;
14565 dev_priv->display.crtc_enable = haswell_crtc_enable;
14566 dev_priv->display.crtc_disable = haswell_crtc_disable;
14567 } else if (HAS_PCH_SPLIT(dev_priv)) {
14568 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14569 dev_priv->display.get_initial_plane_config =
14570 ironlake_get_initial_plane_config;
14571 dev_priv->display.crtc_compute_clock =
14572 ironlake_crtc_compute_clock;
14573 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14574 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14575 } else if (IS_CHERRYVIEW(dev_priv)) {
14576 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14577 dev_priv->display.get_initial_plane_config =
14578 i9xx_get_initial_plane_config;
14579 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14580 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14581 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14582 } else if (IS_VALLEYVIEW(dev_priv)) {
14583 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14584 dev_priv->display.get_initial_plane_config =
14585 i9xx_get_initial_plane_config;
14586 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14587 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14588 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14589 } else if (IS_G4X(dev_priv)) {
14590 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14591 dev_priv->display.get_initial_plane_config =
14592 i9xx_get_initial_plane_config;
14593 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14594 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14595 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14596 } else if (IS_PINEVIEW(dev_priv)) {
14597 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14598 dev_priv->display.get_initial_plane_config =
14599 i9xx_get_initial_plane_config;
14600 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14601 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14602 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14603 } else if (!IS_GEN2(dev_priv)) {
14604 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14605 dev_priv->display.get_initial_plane_config =
14606 i9xx_get_initial_plane_config;
14607 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14608 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14609 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14610 } else {
14611 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14612 dev_priv->display.get_initial_plane_config =
14613 i9xx_get_initial_plane_config;
14614 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14615 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14616 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14617 }
14618
14619 if (IS_GEN5(dev_priv)) {
14620 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14621 } else if (IS_GEN6(dev_priv)) {
14622 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14623 } else if (IS_IVYBRIDGE(dev_priv)) {
14624 /* FIXME: detect B0+ stepping and use auto training */
14625 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14626 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14627 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14628 }
14629
14630 if (dev_priv->info.gen >= 9)
14631 dev_priv->display.update_crtcs = skl_update_crtcs;
14632 else
14633 dev_priv->display.update_crtcs = intel_update_crtcs;
14634
14635 switch (INTEL_INFO(dev_priv)->gen) {
14636 case 2:
14637 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14638 break;
14639
14640 case 3:
14641 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14642 break;
14643
14644 case 4:
14645 case 5:
14646 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14647 break;
14648
14649 case 6:
14650 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14651 break;
14652 case 7:
14653 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14654 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14655 break;
14656 case 9:
14657 /* Drop through - unsupported since execlist only. */
14658 default:
14659 /* Default just returns -ENODEV to indicate unsupported */
14660 dev_priv->display.queue_flip = intel_default_queue_flip;
14661 }
14662 }
14663
14664 /*
14665 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14666 * resume, or other times. This quirk makes sure that's the case for
14667 * affected systems.
14668 */
14669 static void quirk_pipea_force(struct drm_device *dev)
14670 {
14671 struct drm_i915_private *dev_priv = to_i915(dev);
14672
14673 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14674 DRM_INFO("applying pipe a force quirk\n");
14675 }
14676
14677 static void quirk_pipeb_force(struct drm_device *dev)
14678 {
14679 struct drm_i915_private *dev_priv = to_i915(dev);
14680
14681 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14682 DRM_INFO("applying pipe b force quirk\n");
14683 }
14684
14685 /*
14686 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14687 */
14688 static void quirk_ssc_force_disable(struct drm_device *dev)
14689 {
14690 struct drm_i915_private *dev_priv = to_i915(dev);
14691 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14692 DRM_INFO("applying lvds SSC disable quirk\n");
14693 }
14694
14695 /*
14696 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14697 * brightness value
14698 */
14699 static void quirk_invert_brightness(struct drm_device *dev)
14700 {
14701 struct drm_i915_private *dev_priv = to_i915(dev);
14702 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14703 DRM_INFO("applying inverted panel brightness quirk\n");
14704 }
14705
14706 /* Some VBT's incorrectly indicate no backlight is present */
14707 static void quirk_backlight_present(struct drm_device *dev)
14708 {
14709 struct drm_i915_private *dev_priv = to_i915(dev);
14710 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14711 DRM_INFO("applying backlight present quirk\n");
14712 }
14713
14714 struct intel_quirk {
14715 int device;
14716 int subsystem_vendor;
14717 int subsystem_device;
14718 void (*hook)(struct drm_device *dev);
14719 };
14720
14721 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14722 struct intel_dmi_quirk {
14723 void (*hook)(struct drm_device *dev);
14724 const struct dmi_system_id (*dmi_id_list)[];
14725 };
14726
14727 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14728 {
14729 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14730 return 1;
14731 }
14732
14733 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14734 {
14735 .dmi_id_list = &(const struct dmi_system_id[]) {
14736 {
14737 .callback = intel_dmi_reverse_brightness,
14738 .ident = "NCR Corporation",
14739 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14740 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14741 },
14742 },
14743 { } /* terminating entry */
14744 },
14745 .hook = quirk_invert_brightness,
14746 },
14747 };
14748
14749 static struct intel_quirk intel_quirks[] = {
14750 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14751 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14752
14753 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14754 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14755
14756 /* 830 needs to leave pipe A & dpll A up */
14757 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14758
14759 /* 830 needs to leave pipe B & dpll B up */
14760 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14761
14762 /* Lenovo U160 cannot use SSC on LVDS */
14763 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14764
14765 /* Sony Vaio Y cannot use SSC on LVDS */
14766 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14767
14768 /* Acer Aspire 5734Z must invert backlight brightness */
14769 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14770
14771 /* Acer/eMachines G725 */
14772 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14773
14774 /* Acer/eMachines e725 */
14775 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14776
14777 /* Acer/Packard Bell NCL20 */
14778 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14779
14780 /* Acer Aspire 4736Z */
14781 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14782
14783 /* Acer Aspire 5336 */
14784 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14785
14786 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14787 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14788
14789 /* Acer C720 Chromebook (Core i3 4005U) */
14790 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14791
14792 /* Apple Macbook 2,1 (Core 2 T7400) */
14793 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14794
14795 /* Apple Macbook 4,1 */
14796 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14797
14798 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14799 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14800
14801 /* HP Chromebook 14 (Celeron 2955U) */
14802 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14803
14804 /* Dell Chromebook 11 */
14805 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14806
14807 /* Dell Chromebook 11 (2015 version) */
14808 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14809 };
14810
14811 static void intel_init_quirks(struct drm_device *dev)
14812 {
14813 struct pci_dev *d = dev->pdev;
14814 int i;
14815
14816 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14817 struct intel_quirk *q = &intel_quirks[i];
14818
14819 if (d->device == q->device &&
14820 (d->subsystem_vendor == q->subsystem_vendor ||
14821 q->subsystem_vendor == PCI_ANY_ID) &&
14822 (d->subsystem_device == q->subsystem_device ||
14823 q->subsystem_device == PCI_ANY_ID))
14824 q->hook(dev);
14825 }
14826 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14827 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14828 intel_dmi_quirks[i].hook(dev);
14829 }
14830 }
14831
14832 /* Disable the VGA plane that we never use */
14833 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14834 {
14835 struct pci_dev *pdev = dev_priv->drm.pdev;
14836 u8 sr1;
14837 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14838
14839 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14840 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14841 outb(SR01, VGA_SR_INDEX);
14842 sr1 = inb(VGA_SR_DATA);
14843 outb(sr1 | 1<<5, VGA_SR_DATA);
14844 vga_put(pdev, VGA_RSRC_LEGACY_IO);
14845 udelay(300);
14846
14847 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14848 POSTING_READ(vga_reg);
14849 }
14850
14851 void intel_modeset_init_hw(struct drm_device *dev)
14852 {
14853 struct drm_i915_private *dev_priv = to_i915(dev);
14854
14855 intel_update_cdclk(dev_priv);
14856 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14857
14858 intel_init_clock_gating(dev_priv);
14859 }
14860
14861 /*
14862 * Calculate what we think the watermarks should be for the state we've read
14863 * out of the hardware and then immediately program those watermarks so that
14864 * we ensure the hardware settings match our internal state.
14865 *
14866 * We can calculate what we think WM's should be by creating a duplicate of the
14867 * current state (which was constructed during hardware readout) and running it
14868 * through the atomic check code to calculate new watermark values in the
14869 * state object.
14870 */
14871 static void sanitize_watermarks(struct drm_device *dev)
14872 {
14873 struct drm_i915_private *dev_priv = to_i915(dev);
14874 struct drm_atomic_state *state;
14875 struct intel_atomic_state *intel_state;
14876 struct drm_crtc *crtc;
14877 struct drm_crtc_state *cstate;
14878 struct drm_modeset_acquire_ctx ctx;
14879 int ret;
14880 int i;
14881
14882 /* Only supported on platforms that use atomic watermark design */
14883 if (!dev_priv->display.optimize_watermarks)
14884 return;
14885
14886 /*
14887 * We need to hold connection_mutex before calling duplicate_state so
14888 * that the connector loop is protected.
14889 */
14890 drm_modeset_acquire_init(&ctx, 0);
14891 retry:
14892 ret = drm_modeset_lock_all_ctx(dev, &ctx);
14893 if (ret == -EDEADLK) {
14894 drm_modeset_backoff(&ctx);
14895 goto retry;
14896 } else if (WARN_ON(ret)) {
14897 goto fail;
14898 }
14899
14900 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14901 if (WARN_ON(IS_ERR(state)))
14902 goto fail;
14903
14904 intel_state = to_intel_atomic_state(state);
14905
14906 /*
14907 * Hardware readout is the only time we don't want to calculate
14908 * intermediate watermarks (since we don't trust the current
14909 * watermarks).
14910 */
14911 intel_state->skip_intermediate_wm = true;
14912
14913 ret = intel_atomic_check(dev, state);
14914 if (ret) {
14915 /*
14916 * If we fail here, it means that the hardware appears to be
14917 * programmed in a way that shouldn't be possible, given our
14918 * understanding of watermark requirements. This might mean a
14919 * mistake in the hardware readout code or a mistake in the
14920 * watermark calculations for a given platform. Raise a WARN
14921 * so that this is noticeable.
14922 *
14923 * If this actually happens, we'll have to just leave the
14924 * BIOS-programmed watermarks untouched and hope for the best.
14925 */
14926 WARN(true, "Could not determine valid watermarks for inherited state\n");
14927 goto put_state;
14928 }
14929
14930 /* Write calculated watermark values back */
14931 for_each_crtc_in_state(state, crtc, cstate, i) {
14932 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14933
14934 cs->wm.need_postvbl_update = true;
14935 dev_priv->display.optimize_watermarks(intel_state, cs);
14936 }
14937
14938 put_state:
14939 drm_atomic_state_put(state);
14940 fail:
14941 drm_modeset_drop_locks(&ctx);
14942 drm_modeset_acquire_fini(&ctx);
14943 }
14944
14945 int intel_modeset_init(struct drm_device *dev)
14946 {
14947 struct drm_i915_private *dev_priv = to_i915(dev);
14948 struct i915_ggtt *ggtt = &dev_priv->ggtt;
14949 enum pipe pipe;
14950 struct intel_crtc *crtc;
14951
14952 drm_mode_config_init(dev);
14953
14954 dev->mode_config.min_width = 0;
14955 dev->mode_config.min_height = 0;
14956
14957 dev->mode_config.preferred_depth = 24;
14958 dev->mode_config.prefer_shadow = 1;
14959
14960 dev->mode_config.allow_fb_modifiers = true;
14961
14962 dev->mode_config.funcs = &intel_mode_funcs;
14963
14964 INIT_WORK(&dev_priv->atomic_helper.free_work,
14965 intel_atomic_helper_free_state_worker);
14966
14967 intel_init_quirks(dev);
14968
14969 intel_init_pm(dev_priv);
14970
14971 if (INTEL_INFO(dev_priv)->num_pipes == 0)
14972 return 0;
14973
14974 /*
14975 * There may be no VBT; and if the BIOS enabled SSC we can
14976 * just keep using it to avoid unnecessary flicker. Whereas if the
14977 * BIOS isn't using it, don't assume it will work even if the VBT
14978 * indicates as much.
14979 */
14980 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14981 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14982 DREF_SSC1_ENABLE);
14983
14984 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14985 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14986 bios_lvds_use_ssc ? "en" : "dis",
14987 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14988 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14989 }
14990 }
14991
14992 if (IS_GEN2(dev_priv)) {
14993 dev->mode_config.max_width = 2048;
14994 dev->mode_config.max_height = 2048;
14995 } else if (IS_GEN3(dev_priv)) {
14996 dev->mode_config.max_width = 4096;
14997 dev->mode_config.max_height = 4096;
14998 } else {
14999 dev->mode_config.max_width = 8192;
15000 dev->mode_config.max_height = 8192;
15001 }
15002
15003 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15004 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15005 dev->mode_config.cursor_height = 1023;
15006 } else if (IS_GEN2(dev_priv)) {
15007 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15008 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15009 } else {
15010 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15011 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15012 }
15013
15014 dev->mode_config.fb_base = ggtt->mappable_base;
15015
15016 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15017 INTEL_INFO(dev_priv)->num_pipes,
15018 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15019
15020 for_each_pipe(dev_priv, pipe) {
15021 int ret;
15022
15023 ret = intel_crtc_init(dev_priv, pipe);
15024 if (ret) {
15025 drm_mode_config_cleanup(dev);
15026 return ret;
15027 }
15028 }
15029
15030 intel_update_czclk(dev_priv);
15031 intel_update_cdclk(dev_priv);
15032 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
15033
15034 intel_shared_dpll_init(dev);
15035
15036 if (dev_priv->max_cdclk_freq == 0)
15037 intel_update_max_cdclk(dev_priv);
15038
15039 /* Just disable it once at startup */
15040 i915_disable_vga(dev_priv);
15041 intel_setup_outputs(dev_priv);
15042
15043 drm_modeset_lock_all(dev);
15044 intel_modeset_setup_hw_state(dev);
15045 drm_modeset_unlock_all(dev);
15046
15047 for_each_intel_crtc(dev, crtc) {
15048 struct intel_initial_plane_config plane_config = {};
15049
15050 if (!crtc->active)
15051 continue;
15052
15053 /*
15054 * Note that reserving the BIOS fb up front prevents us
15055 * from stuffing other stolen allocations like the ring
15056 * on top. This prevents some ugliness at boot time, and
15057 * can even allow for smooth boot transitions if the BIOS
15058 * fb is large enough for the active pipe configuration.
15059 */
15060 dev_priv->display.get_initial_plane_config(crtc,
15061 &plane_config);
15062
15063 /*
15064 * If the fb is shared between multiple heads, we'll
15065 * just get the first one.
15066 */
15067 intel_find_initial_plane_obj(crtc, &plane_config);
15068 }
15069
15070 /*
15071 * Make sure hardware watermarks really match the state we read out.
15072 * Note that we need to do this after reconstructing the BIOS fb's
15073 * since the watermark calculation done here will use pstate->fb.
15074 */
15075 sanitize_watermarks(dev);
15076
15077 return 0;
15078 }
15079
15080 static void intel_enable_pipe_a(struct drm_device *dev)
15081 {
15082 struct intel_connector *connector;
15083 struct drm_connector *crt = NULL;
15084 struct intel_load_detect_pipe load_detect_temp;
15085 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15086
15087 /* We can't just switch on the pipe A, we need to set things up with a
15088 * proper mode and output configuration. As a gross hack, enable pipe A
15089 * by enabling the load detect pipe once. */
15090 for_each_intel_connector(dev, connector) {
15091 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15092 crt = &connector->base;
15093 break;
15094 }
15095 }
15096
15097 if (!crt)
15098 return;
15099
15100 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15101 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15102 }
15103
15104 static bool
15105 intel_check_plane_mapping(struct intel_crtc *crtc)
15106 {
15107 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15108 u32 val;
15109
15110 if (INTEL_INFO(dev_priv)->num_pipes == 1)
15111 return true;
15112
15113 val = I915_READ(DSPCNTR(!crtc->plane));
15114
15115 if ((val & DISPLAY_PLANE_ENABLE) &&
15116 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15117 return false;
15118
15119 return true;
15120 }
15121
15122 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15123 {
15124 struct drm_device *dev = crtc->base.dev;
15125 struct intel_encoder *encoder;
15126
15127 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15128 return true;
15129
15130 return false;
15131 }
15132
15133 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15134 {
15135 struct drm_device *dev = encoder->base.dev;
15136 struct intel_connector *connector;
15137
15138 for_each_connector_on_encoder(dev, &encoder->base, connector)
15139 return connector;
15140
15141 return NULL;
15142 }
15143
15144 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15145 enum transcoder pch_transcoder)
15146 {
15147 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15148 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15149 }
15150
15151 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15152 {
15153 struct drm_device *dev = crtc->base.dev;
15154 struct drm_i915_private *dev_priv = to_i915(dev);
15155 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15156
15157 /* Clear any frame start delays used for debugging left by the BIOS */
15158 if (!transcoder_is_dsi(cpu_transcoder)) {
15159 i915_reg_t reg = PIPECONF(cpu_transcoder);
15160
15161 I915_WRITE(reg,
15162 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15163 }
15164
15165 /* restore vblank interrupts to correct state */
15166 drm_crtc_vblank_reset(&crtc->base);
15167 if (crtc->active) {
15168 struct intel_plane *plane;
15169
15170 drm_crtc_vblank_on(&crtc->base);
15171
15172 /* Disable everything but the primary plane */
15173 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15174 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15175 continue;
15176
15177 plane->disable_plane(&plane->base, &crtc->base);
15178 }
15179 }
15180
15181 /* We need to sanitize the plane -> pipe mapping first because this will
15182 * disable the crtc (and hence change the state) if it is wrong. Note
15183 * that gen4+ has a fixed plane -> pipe mapping. */
15184 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15185 bool plane;
15186
15187 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15188 crtc->base.base.id, crtc->base.name);
15189
15190 /* Pipe has the wrong plane attached and the plane is active.
15191 * Temporarily change the plane mapping and disable everything
15192 * ... */
15193 plane = crtc->plane;
15194 crtc->base.primary->state->visible = true;
15195 crtc->plane = !plane;
15196 intel_crtc_disable_noatomic(&crtc->base);
15197 crtc->plane = plane;
15198 }
15199
15200 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15201 crtc->pipe == PIPE_A && !crtc->active) {
15202 /* BIOS forgot to enable pipe A, this mostly happens after
15203 * resume. Force-enable the pipe to fix this, the update_dpms
15204 * call below we restore the pipe to the right state, but leave
15205 * the required bits on. */
15206 intel_enable_pipe_a(dev);
15207 }
15208
15209 /* Adjust the state of the output pipe according to whether we
15210 * have active connectors/encoders. */
15211 if (crtc->active && !intel_crtc_has_encoders(crtc))
15212 intel_crtc_disable_noatomic(&crtc->base);
15213
15214 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15215 /*
15216 * We start out with underrun reporting disabled to avoid races.
15217 * For correct bookkeeping mark this on active crtcs.
15218 *
15219 * Also on gmch platforms we dont have any hardware bits to
15220 * disable the underrun reporting. Which means we need to start
15221 * out with underrun reporting disabled also on inactive pipes,
15222 * since otherwise we'll complain about the garbage we read when
15223 * e.g. coming up after runtime pm.
15224 *
15225 * No protection against concurrent access is required - at
15226 * worst a fifo underrun happens which also sets this to false.
15227 */
15228 crtc->cpu_fifo_underrun_disabled = true;
15229 /*
15230 * We track the PCH trancoder underrun reporting state
15231 * within the crtc. With crtc for pipe A housing the underrun
15232 * reporting state for PCH transcoder A, crtc for pipe B housing
15233 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15234 * and marking underrun reporting as disabled for the non-existing
15235 * PCH transcoders B and C would prevent enabling the south
15236 * error interrupt (see cpt_can_enable_serr_int()).
15237 */
15238 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15239 crtc->pch_fifo_underrun_disabled = true;
15240 }
15241 }
15242
15243 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15244 {
15245 struct intel_connector *connector;
15246
15247 /* We need to check both for a crtc link (meaning that the
15248 * encoder is active and trying to read from a pipe) and the
15249 * pipe itself being active. */
15250 bool has_active_crtc = encoder->base.crtc &&
15251 to_intel_crtc(encoder->base.crtc)->active;
15252
15253 connector = intel_encoder_find_connector(encoder);
15254 if (connector && !has_active_crtc) {
15255 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15256 encoder->base.base.id,
15257 encoder->base.name);
15258
15259 /* Connector is active, but has no active pipe. This is
15260 * fallout from our resume register restoring. Disable
15261 * the encoder manually again. */
15262 if (encoder->base.crtc) {
15263 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15264
15265 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15266 encoder->base.base.id,
15267 encoder->base.name);
15268 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15269 if (encoder->post_disable)
15270 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15271 }
15272 encoder->base.crtc = NULL;
15273
15274 /* Inconsistent output/port/pipe state happens presumably due to
15275 * a bug in one of the get_hw_state functions. Or someplace else
15276 * in our code, like the register restore mess on resume. Clamp
15277 * things to off as a safer default. */
15278
15279 connector->base.dpms = DRM_MODE_DPMS_OFF;
15280 connector->base.encoder = NULL;
15281 }
15282 /* Enabled encoders without active connectors will be fixed in
15283 * the crtc fixup. */
15284 }
15285
15286 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15287 {
15288 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15289
15290 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15291 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15292 i915_disable_vga(dev_priv);
15293 }
15294 }
15295
15296 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15297 {
15298 /* This function can be called both from intel_modeset_setup_hw_state or
15299 * at a very early point in our resume sequence, where the power well
15300 * structures are not yet restored. Since this function is at a very
15301 * paranoid "someone might have enabled VGA while we were not looking"
15302 * level, just check if the power well is enabled instead of trying to
15303 * follow the "don't touch the power well if we don't need it" policy
15304 * the rest of the driver uses. */
15305 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15306 return;
15307
15308 i915_redisable_vga_power_on(dev_priv);
15309
15310 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15311 }
15312
15313 static bool primary_get_hw_state(struct intel_plane *plane)
15314 {
15315 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15316
15317 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15318 }
15319
15320 /* FIXME read out full plane state for all planes */
15321 static void readout_plane_state(struct intel_crtc *crtc)
15322 {
15323 struct drm_plane *primary = crtc->base.primary;
15324 struct intel_plane_state *plane_state =
15325 to_intel_plane_state(primary->state);
15326
15327 plane_state->base.visible = crtc->active &&
15328 primary_get_hw_state(to_intel_plane(primary));
15329
15330 if (plane_state->base.visible)
15331 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15332 }
15333
15334 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15335 {
15336 struct drm_i915_private *dev_priv = to_i915(dev);
15337 enum pipe pipe;
15338 struct intel_crtc *crtc;
15339 struct intel_encoder *encoder;
15340 struct intel_connector *connector;
15341 int i;
15342
15343 dev_priv->active_crtcs = 0;
15344
15345 for_each_intel_crtc(dev, crtc) {
15346 struct intel_crtc_state *crtc_state =
15347 to_intel_crtc_state(crtc->base.state);
15348
15349 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15350 memset(crtc_state, 0, sizeof(*crtc_state));
15351 crtc_state->base.crtc = &crtc->base;
15352
15353 crtc_state->base.active = crtc_state->base.enable =
15354 dev_priv->display.get_pipe_config(crtc, crtc_state);
15355
15356 crtc->base.enabled = crtc_state->base.enable;
15357 crtc->active = crtc_state->base.active;
15358
15359 if (crtc_state->base.active)
15360 dev_priv->active_crtcs |= 1 << crtc->pipe;
15361
15362 readout_plane_state(crtc);
15363
15364 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15365 crtc->base.base.id, crtc->base.name,
15366 enableddisabled(crtc_state->base.active));
15367 }
15368
15369 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15370 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15371
15372 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15373 &pll->state.hw_state);
15374 pll->state.crtc_mask = 0;
15375 for_each_intel_crtc(dev, crtc) {
15376 struct intel_crtc_state *crtc_state =
15377 to_intel_crtc_state(crtc->base.state);
15378
15379 if (crtc_state->base.active &&
15380 crtc_state->shared_dpll == pll)
15381 pll->state.crtc_mask |= 1 << crtc->pipe;
15382 }
15383 pll->active_mask = pll->state.crtc_mask;
15384
15385 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15386 pll->name, pll->state.crtc_mask, pll->on);
15387 }
15388
15389 for_each_intel_encoder(dev, encoder) {
15390 pipe = 0;
15391
15392 if (encoder->get_hw_state(encoder, &pipe)) {
15393 struct intel_crtc_state *crtc_state;
15394
15395 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15396 crtc_state = to_intel_crtc_state(crtc->base.state);
15397
15398 encoder->base.crtc = &crtc->base;
15399 crtc_state->output_types |= 1 << encoder->type;
15400 encoder->get_config(encoder, crtc_state);
15401 } else {
15402 encoder->base.crtc = NULL;
15403 }
15404
15405 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15406 encoder->base.base.id, encoder->base.name,
15407 enableddisabled(encoder->base.crtc),
15408 pipe_name(pipe));
15409 }
15410
15411 for_each_intel_connector(dev, connector) {
15412 if (connector->get_hw_state(connector)) {
15413 connector->base.dpms = DRM_MODE_DPMS_ON;
15414
15415 encoder = connector->encoder;
15416 connector->base.encoder = &encoder->base;
15417
15418 if (encoder->base.crtc &&
15419 encoder->base.crtc->state->active) {
15420 /*
15421 * This has to be done during hardware readout
15422 * because anything calling .crtc_disable may
15423 * rely on the connector_mask being accurate.
15424 */
15425 encoder->base.crtc->state->connector_mask |=
15426 1 << drm_connector_index(&connector->base);
15427 encoder->base.crtc->state->encoder_mask |=
15428 1 << drm_encoder_index(&encoder->base);
15429 }
15430
15431 } else {
15432 connector->base.dpms = DRM_MODE_DPMS_OFF;
15433 connector->base.encoder = NULL;
15434 }
15435 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15436 connector->base.base.id, connector->base.name,
15437 enableddisabled(connector->base.encoder));
15438 }
15439
15440 for_each_intel_crtc(dev, crtc) {
15441 struct intel_crtc_state *crtc_state =
15442 to_intel_crtc_state(crtc->base.state);
15443 int pixclk = 0;
15444
15445 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15446
15447 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15448 if (crtc_state->base.active) {
15449 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15450 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15451 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15452
15453 /*
15454 * The initial mode needs to be set in order to keep
15455 * the atomic core happy. It wants a valid mode if the
15456 * crtc's enabled, so we do the above call.
15457 *
15458 * But we don't set all the derived state fully, hence
15459 * set a flag to indicate that a full recalculation is
15460 * needed on the next commit.
15461 */
15462 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15463
15464 intel_crtc_compute_pixel_rate(crtc_state);
15465
15466 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15467 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15468 pixclk = crtc_state->pixel_rate;
15469 else
15470 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15471
15472 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15473 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15474 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15475
15476 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15477 update_scanline_offset(crtc);
15478 }
15479
15480 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15481
15482 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15483 }
15484 }
15485
15486 /* Scan out the current hw modeset state,
15487 * and sanitizes it to the current state
15488 */
15489 static void
15490 intel_modeset_setup_hw_state(struct drm_device *dev)
15491 {
15492 struct drm_i915_private *dev_priv = to_i915(dev);
15493 enum pipe pipe;
15494 struct intel_crtc *crtc;
15495 struct intel_encoder *encoder;
15496 int i;
15497
15498 intel_modeset_readout_hw_state(dev);
15499
15500 /* HW state is read out, now we need to sanitize this mess. */
15501 for_each_intel_encoder(dev, encoder) {
15502 intel_sanitize_encoder(encoder);
15503 }
15504
15505 for_each_pipe(dev_priv, pipe) {
15506 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15507
15508 intel_sanitize_crtc(crtc);
15509 intel_dump_pipe_config(crtc, crtc->config,
15510 "[setup_hw_state]");
15511 }
15512
15513 intel_modeset_update_connector_atomic_state(dev);
15514
15515 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15516 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15517
15518 if (!pll->on || pll->active_mask)
15519 continue;
15520
15521 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15522
15523 pll->funcs.disable(dev_priv, pll);
15524 pll->on = false;
15525 }
15526
15527 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15528 vlv_wm_get_hw_state(dev);
15529 else if (IS_GEN9(dev_priv))
15530 skl_wm_get_hw_state(dev);
15531 else if (HAS_PCH_SPLIT(dev_priv))
15532 ilk_wm_get_hw_state(dev);
15533
15534 for_each_intel_crtc(dev, crtc) {
15535 u64 put_domains;
15536
15537 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15538 if (WARN_ON(put_domains))
15539 modeset_put_power_domains(dev_priv, put_domains);
15540 }
15541 intel_display_set_init_power(dev_priv, false);
15542
15543 intel_fbc_init_pipe_state(dev_priv);
15544 }
15545
15546 void intel_display_resume(struct drm_device *dev)
15547 {
15548 struct drm_i915_private *dev_priv = to_i915(dev);
15549 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15550 struct drm_modeset_acquire_ctx ctx;
15551 int ret;
15552
15553 dev_priv->modeset_restore_state = NULL;
15554 if (state)
15555 state->acquire_ctx = &ctx;
15556
15557 /*
15558 * This is a cludge because with real atomic modeset mode_config.mutex
15559 * won't be taken. Unfortunately some probed state like
15560 * audio_codec_enable is still protected by mode_config.mutex, so lock
15561 * it here for now.
15562 */
15563 mutex_lock(&dev->mode_config.mutex);
15564 drm_modeset_acquire_init(&ctx, 0);
15565
15566 while (1) {
15567 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15568 if (ret != -EDEADLK)
15569 break;
15570
15571 drm_modeset_backoff(&ctx);
15572 }
15573
15574 if (!ret)
15575 ret = __intel_display_resume(dev, state);
15576
15577 drm_modeset_drop_locks(&ctx);
15578 drm_modeset_acquire_fini(&ctx);
15579 mutex_unlock(&dev->mode_config.mutex);
15580
15581 if (ret)
15582 DRM_ERROR("Restoring old state failed with %i\n", ret);
15583 if (state)
15584 drm_atomic_state_put(state);
15585 }
15586
15587 void intel_modeset_gem_init(struct drm_device *dev)
15588 {
15589 struct drm_i915_private *dev_priv = to_i915(dev);
15590
15591 intel_init_gt_powersave(dev_priv);
15592
15593 intel_modeset_init_hw(dev);
15594
15595 intel_setup_overlay(dev_priv);
15596 }
15597
15598 int intel_connector_register(struct drm_connector *connector)
15599 {
15600 struct intel_connector *intel_connector = to_intel_connector(connector);
15601 int ret;
15602
15603 ret = intel_backlight_device_register(intel_connector);
15604 if (ret)
15605 goto err;
15606
15607 return 0;
15608
15609 err:
15610 return ret;
15611 }
15612
15613 void intel_connector_unregister(struct drm_connector *connector)
15614 {
15615 struct intel_connector *intel_connector = to_intel_connector(connector);
15616
15617 intel_backlight_device_unregister(intel_connector);
15618 intel_panel_destroy_backlight(connector);
15619 }
15620
15621 void intel_modeset_cleanup(struct drm_device *dev)
15622 {
15623 struct drm_i915_private *dev_priv = to_i915(dev);
15624
15625 flush_work(&dev_priv->atomic_helper.free_work);
15626 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15627
15628 intel_disable_gt_powersave(dev_priv);
15629
15630 /*
15631 * Interrupts and polling as the first thing to avoid creating havoc.
15632 * Too much stuff here (turning of connectors, ...) would
15633 * experience fancy races otherwise.
15634 */
15635 intel_irq_uninstall(dev_priv);
15636
15637 /*
15638 * Due to the hpd irq storm handling the hotplug work can re-arm the
15639 * poll handlers. Hence disable polling after hpd handling is shut down.
15640 */
15641 drm_kms_helper_poll_fini(dev);
15642
15643 intel_unregister_dsm_handler();
15644
15645 intel_fbc_global_disable(dev_priv);
15646
15647 /* flush any delayed tasks or pending work */
15648 flush_scheduled_work();
15649
15650 drm_mode_config_cleanup(dev);
15651
15652 intel_cleanup_overlay(dev_priv);
15653
15654 intel_cleanup_gt_powersave(dev_priv);
15655
15656 intel_teardown_gmbus(dev_priv);
15657 }
15658
15659 void intel_connector_attach_encoder(struct intel_connector *connector,
15660 struct intel_encoder *encoder)
15661 {
15662 connector->encoder = encoder;
15663 drm_mode_connector_attach_encoder(&connector->base,
15664 &encoder->base);
15665 }
15666
15667 /*
15668 * set vga decode state - true == enable VGA decode
15669 */
15670 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15671 {
15672 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15673 u16 gmch_ctrl;
15674
15675 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15676 DRM_ERROR("failed to read control word\n");
15677 return -EIO;
15678 }
15679
15680 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15681 return 0;
15682
15683 if (state)
15684 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15685 else
15686 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15687
15688 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15689 DRM_ERROR("failed to write control word\n");
15690 return -EIO;
15691 }
15692
15693 return 0;
15694 }
15695
15696 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15697
15698 struct intel_display_error_state {
15699
15700 u32 power_well_driver;
15701
15702 int num_transcoders;
15703
15704 struct intel_cursor_error_state {
15705 u32 control;
15706 u32 position;
15707 u32 base;
15708 u32 size;
15709 } cursor[I915_MAX_PIPES];
15710
15711 struct intel_pipe_error_state {
15712 bool power_domain_on;
15713 u32 source;
15714 u32 stat;
15715 } pipe[I915_MAX_PIPES];
15716
15717 struct intel_plane_error_state {
15718 u32 control;
15719 u32 stride;
15720 u32 size;
15721 u32 pos;
15722 u32 addr;
15723 u32 surface;
15724 u32 tile_offset;
15725 } plane[I915_MAX_PIPES];
15726
15727 struct intel_transcoder_error_state {
15728 bool power_domain_on;
15729 enum transcoder cpu_transcoder;
15730
15731 u32 conf;
15732
15733 u32 htotal;
15734 u32 hblank;
15735 u32 hsync;
15736 u32 vtotal;
15737 u32 vblank;
15738 u32 vsync;
15739 } transcoder[4];
15740 };
15741
15742 struct intel_display_error_state *
15743 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15744 {
15745 struct intel_display_error_state *error;
15746 int transcoders[] = {
15747 TRANSCODER_A,
15748 TRANSCODER_B,
15749 TRANSCODER_C,
15750 TRANSCODER_EDP,
15751 };
15752 int i;
15753
15754 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15755 return NULL;
15756
15757 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15758 if (error == NULL)
15759 return NULL;
15760
15761 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15762 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15763
15764 for_each_pipe(dev_priv, i) {
15765 error->pipe[i].power_domain_on =
15766 __intel_display_power_is_enabled(dev_priv,
15767 POWER_DOMAIN_PIPE(i));
15768 if (!error->pipe[i].power_domain_on)
15769 continue;
15770
15771 error->cursor[i].control = I915_READ(CURCNTR(i));
15772 error->cursor[i].position = I915_READ(CURPOS(i));
15773 error->cursor[i].base = I915_READ(CURBASE(i));
15774
15775 error->plane[i].control = I915_READ(DSPCNTR(i));
15776 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15777 if (INTEL_GEN(dev_priv) <= 3) {
15778 error->plane[i].size = I915_READ(DSPSIZE(i));
15779 error->plane[i].pos = I915_READ(DSPPOS(i));
15780 }
15781 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15782 error->plane[i].addr = I915_READ(DSPADDR(i));
15783 if (INTEL_GEN(dev_priv) >= 4) {
15784 error->plane[i].surface = I915_READ(DSPSURF(i));
15785 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15786 }
15787
15788 error->pipe[i].source = I915_READ(PIPESRC(i));
15789
15790 if (HAS_GMCH_DISPLAY(dev_priv))
15791 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15792 }
15793
15794 /* Note: this does not include DSI transcoders. */
15795 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15796 if (HAS_DDI(dev_priv))
15797 error->num_transcoders++; /* Account for eDP. */
15798
15799 for (i = 0; i < error->num_transcoders; i++) {
15800 enum transcoder cpu_transcoder = transcoders[i];
15801
15802 error->transcoder[i].power_domain_on =
15803 __intel_display_power_is_enabled(dev_priv,
15804 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15805 if (!error->transcoder[i].power_domain_on)
15806 continue;
15807
15808 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15809
15810 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15811 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15812 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15813 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15814 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15815 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15816 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15817 }
15818
15819 return error;
15820 }
15821
15822 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15823
15824 void
15825 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15826 struct intel_display_error_state *error)
15827 {
15828 struct drm_i915_private *dev_priv = m->i915;
15829 int i;
15830
15831 if (!error)
15832 return;
15833
15834 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15835 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15836 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15837 error->power_well_driver);
15838 for_each_pipe(dev_priv, i) {
15839 err_printf(m, "Pipe [%d]:\n", i);
15840 err_printf(m, " Power: %s\n",
15841 onoff(error->pipe[i].power_domain_on));
15842 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15843 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15844
15845 err_printf(m, "Plane [%d]:\n", i);
15846 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15847 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15848 if (INTEL_GEN(dev_priv) <= 3) {
15849 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15850 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15851 }
15852 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15853 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15854 if (INTEL_GEN(dev_priv) >= 4) {
15855 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15856 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15857 }
15858
15859 err_printf(m, "Cursor [%d]:\n", i);
15860 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15861 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15862 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15863 }
15864
15865 for (i = 0; i < error->num_transcoders; i++) {
15866 err_printf(m, "CPU transcoder: %s\n",
15867 transcoder_name(error->transcoder[i].cpu_transcoder));
15868 err_printf(m, " Power: %s\n",
15869 onoff(error->transcoder[i].power_domain_on));
15870 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15871 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15872 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15873 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15874 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15875 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15876 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15877 }
15878 }
15879
15880 #endif
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