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Merge tag 'drm-intel-next-2015-02-27' of git://anongit.freedesktop.org/drm-intel...
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
46
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70 };
71
72 /* Cursor formats */
73 static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75 };
76
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415 {
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 /**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433 {
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469 {
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487 }
488
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490 {
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521 }
522
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
525 {
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532 }
533
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535 {
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537 }
538
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
540 {
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547 }
548
549 static void chv_clock(int refclk, intel_clock_t *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599 }
600
601 static bool
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605 {
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 static bool
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666 {
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 static bool
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725 {
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 static bool
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833 }
834
835 static bool
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885 }
886
887 bool intel_crtc_active(struct drm_crtc *crtc)
888 {
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 */
900 return intel_crtc->active && crtc->primary->fb &&
901 intel_crtc->config->base.adjusted_mode.crtc_clock;
902 }
903
904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
905 enum pipe pipe)
906 {
907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
909
910 return intel_crtc->config->cpu_transcoder;
911 }
912
913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
914 {
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 u32 reg = PIPEDSL(pipe);
917 u32 line1, line2;
918 u32 line_mask;
919
920 if (IS_GEN2(dev))
921 line_mask = DSL_LINEMASK_GEN2;
922 else
923 line_mask = DSL_LINEMASK_GEN3;
924
925 line1 = I915_READ(reg) & line_mask;
926 mdelay(5);
927 line2 = I915_READ(reg) & line_mask;
928
929 return line1 == line2;
930 }
931
932 /*
933 * intel_wait_for_pipe_off - wait for pipe to turn off
934 * @crtc: crtc whose pipe to wait for
935 *
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
939 *
940 * On Gen4 and above:
941 * wait for the pipe register state bit to turn off
942 *
943 * Otherwise:
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
946 *
947 */
948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
949 {
950 struct drm_device *dev = crtc->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
953 enum pipe pipe = crtc->pipe;
954
955 if (INTEL_INFO(dev)->gen >= 4) {
956 int reg = PIPECONF(cpu_transcoder);
957
958 /* Wait for the Pipe State to go off */
959 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
960 100))
961 WARN(1, "pipe_off wait timed out\n");
962 } else {
963 /* Wait for the display line to settle */
964 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
965 WARN(1, "pipe_off wait timed out\n");
966 }
967 }
968
969 /*
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
973 *
974 * Returns true if @port is connected, false otherwise.
975 */
976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
977 struct intel_digital_port *port)
978 {
979 u32 bit;
980
981 if (HAS_PCH_IBX(dev_priv->dev)) {
982 switch (port->port) {
983 case PORT_B:
984 bit = SDE_PORTB_HOTPLUG;
985 break;
986 case PORT_C:
987 bit = SDE_PORTC_HOTPLUG;
988 break;
989 case PORT_D:
990 bit = SDE_PORTD_HOTPLUG;
991 break;
992 default:
993 return true;
994 }
995 } else {
996 switch (port->port) {
997 case PORT_B:
998 bit = SDE_PORTB_HOTPLUG_CPT;
999 break;
1000 case PORT_C:
1001 bit = SDE_PORTC_HOTPLUG_CPT;
1002 break;
1003 case PORT_D:
1004 bit = SDE_PORTD_HOTPLUG_CPT;
1005 break;
1006 default:
1007 return true;
1008 }
1009 }
1010
1011 return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016 return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state)
1022 {
1023 int reg;
1024 u32 val;
1025 bool cur_state;
1026
1027 reg = DPLL(pipe);
1028 val = I915_READ(reg);
1029 cur_state = !!(val & DPLL_VCO_ENABLE);
1030 I915_STATE_WARN(cur_state != state,
1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 mutex_lock(&dev_priv->dpio_lock);
1042 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043 mutex_unlock(&dev_priv->dpio_lock);
1044
1045 cur_state = val & DSI_PLL_VCO_EN;
1046 I915_STATE_WARN(cur_state != state,
1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058 if (crtc->config->shared_dpll < 0)
1059 return NULL;
1060
1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066 struct intel_shared_dpll *pll,
1067 bool state)
1068 {
1069 bool cur_state;
1070 struct intel_dpll_hw_state hw_state;
1071
1072 if (WARN (!pll,
1073 "asserting DPLL %s with no DPLL\n", state_string(state)))
1074 return;
1075
1076 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077 I915_STATE_WARN(cur_state != state,
1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083 enum pipe pipe, bool state)
1084 {
1085 int reg;
1086 u32 val;
1087 bool cur_state;
1088 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089 pipe);
1090
1091 if (HAS_DDI(dev_priv->dev)) {
1092 /* DDI does not have a specific FDI_TX register */
1093 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094 val = I915_READ(reg);
1095 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096 } else {
1097 reg = FDI_TX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_TX_ENABLE);
1100 }
1101 I915_STATE_WARN(cur_state != state,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1110 {
1111 int reg;
1112 u32 val;
1113 bool cur_state;
1114
1115 reg = FDI_RX_CTL(pipe);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 int reg;
1129 u32 val;
1130
1131 /* ILK FDI PLL is always enabled */
1132 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133 return;
1134
1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136 if (HAS_DDI(dev_priv->dev))
1137 return;
1138
1139 reg = FDI_TX_CTL(pipe);
1140 val = I915_READ(reg);
1141 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154 I915_STATE_WARN(cur_state != state,
1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161 {
1162 struct drm_device *dev = dev_priv->dev;
1163 int pp_reg;
1164 u32 val;
1165 enum pipe panel_pipe = PIPE_A;
1166 bool locked = true;
1167
1168 if (WARN_ON(HAS_DDI(dev)))
1169 return;
1170
1171 if (HAS_PCH_SPLIT(dev)) {
1172 u32 port_sel;
1173
1174 pp_reg = PCH_PP_CONTROL;
1175 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179 panel_pipe = PIPE_B;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184 panel_pipe = pipe;
1185 } else {
1186 pp_reg = PP_CONTROL;
1187 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188 panel_pipe = PIPE_B;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 I915_STATE_WARN(panel_pipe == pipe && locked,
1197 "panel assertion failure, pipe %c regs locked\n",
1198 pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1203 {
1204 struct drm_device *dev = dev_priv->dev;
1205 bool cur_state;
1206
1207 if (IS_845G(dev) || IS_I865G(dev))
1208 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209 else
1210 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212 I915_STATE_WARN(cur_state != state,
1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221 {
1222 int reg;
1223 u32 val;
1224 bool cur_state;
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
1227
1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231 state = true;
1232
1233 if (!intel_display_power_is_enabled(dev_priv,
1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235 cur_state = false;
1236 } else {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1240 }
1241
1242 I915_STATE_WARN(cur_state != state,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
1249 {
1250 int reg;
1251 u32 val;
1252 bool cur_state;
1253
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267 {
1268 struct drm_device *dev = dev_priv->dev;
1269 int reg, i;
1270 u32 val;
1271 int cur_pipe;
1272
1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev)->gen >= 4) {
1275 reg = DSPCNTR(pipe);
1276 val = I915_READ(reg);
1277 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278 "plane %c assertion failure, should be disabled but not\n",
1279 plane_name(pipe));
1280 return;
1281 }
1282
1283 /* Need to check both planes against the pipe */
1284 for_each_pipe(dev_priv, i) {
1285 reg = DSPCNTR(i);
1286 val = I915_READ(reg);
1287 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288 DISPPLANE_SEL_PIPE_SHIFT;
1289 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i), pipe_name(pipe));
1292 }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe)
1297 {
1298 struct drm_device *dev = dev_priv->dev;
1299 int reg, sprite;
1300 u32 val;
1301
1302 if (INTEL_INFO(dev)->gen >= 9) {
1303 for_each_sprite(pipe, sprite) {
1304 val = I915_READ(PLANE_CTL(pipe, sprite));
1305 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite, pipe_name(pipe));
1308 }
1309 } else if (IS_VALLEYVIEW(dev)) {
1310 for_each_sprite(pipe, sprite) {
1311 reg = SPCNTR(pipe, sprite);
1312 val = I915_READ(reg);
1313 I915_STATE_WARN(val & SP_ENABLE,
1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315 sprite_name(pipe, sprite), pipe_name(pipe));
1316 }
1317 } else if (INTEL_INFO(dev)->gen >= 7) {
1318 reg = SPRCTL(pipe);
1319 val = I915_READ(reg);
1320 I915_STATE_WARN(val & SPRITE_ENABLE,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe), pipe_name(pipe));
1323 } else if (INTEL_INFO(dev)->gen >= 5) {
1324 reg = DVSCNTR(pipe);
1325 val = I915_READ(reg);
1326 I915_STATE_WARN(val & DVS_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 plane_name(pipe), pipe_name(pipe));
1329 }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340 u32 val;
1341 bool enabled;
1342
1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345 val = I915_READ(PCH_DREF_CONTROL);
1346 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347 DREF_SUPERSPREAD_SOURCE_MASK));
1348 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe)
1353 {
1354 int reg;
1355 u32 val;
1356 bool enabled;
1357
1358 reg = PCH_TRANSCONF(pipe);
1359 val = I915_READ(reg);
1360 enabled = !!(val & TRANS_ENABLE);
1361 I915_STATE_WARN(enabled,
1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369 if ((val & DP_PORT_EN) == 0)
1370 return false;
1371
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
1377 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389 {
1390 if ((val & SDVO_ENABLE) == 0)
1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395 return false;
1396 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1399 } else {
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408 {
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv->dev)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424 {
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv->dev)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, int reg, u32 port_sel)
1439 {
1440 u32 val = I915_READ(reg);
1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443 reg, pipe_name(pipe));
1444
1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446 && (val & DP_PIPEB_SELECT),
1447 "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg)
1452 {
1453 u32 val = I915_READ(reg);
1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1457
1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459 && (val & SDVO_PIPE_B_SELECT),
1460 "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 int reg;
1467 u32 val;
1468
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473 reg = PCH_ADPA;
1474 val = I915_READ(reg);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 pipe_name(pipe));
1478
1479 reg = PCH_LVDS;
1480 val = I915_READ(reg);
1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483 pipe_name(pipe));
1484
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494 if (!IS_VALLEYVIEW(dev))
1495 return;
1496
1497 /*
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501 */
1502 if (IS_CHERRYVIEW(dev)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505 } else {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507 }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511 const struct intel_crtc_state *pipe_config)
1512 {
1513 struct drm_device *dev = crtc->base.dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 int reg = DPLL(crtc->pipe);
1516 u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518 assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523 /* PLL is protected by panel, make sure we can write it */
1524 if (IS_MOBILE(dev_priv->dev))
1525 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527 I915_WRITE(reg, dpll);
1528 POSTING_READ(reg);
1529 udelay(150);
1530
1531 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535 POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537 /* We do this three times for luck */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 I915_WRITE(reg, dpll);
1545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550 const struct intel_crtc_state *pipe_config)
1551 {
1552 struct drm_device *dev = crtc->base.dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = crtc->pipe;
1555 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556 u32 tmp;
1557
1558 assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562 mutex_lock(&dev_priv->dpio_lock);
1563
1564 /* Enable back the 10bit clock to display controller */
1565 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566 tmp |= DPIO_DCLKP_EN;
1567 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569 /*
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571 */
1572 udelay(1);
1573
1574 /* Enable PLL */
1575 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577 /* Check PLL is locked */
1578 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581 /* not sure when this should be written */
1582 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583 POSTING_READ(DPLL_MD(pipe));
1584
1585 mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590 struct intel_crtc *crtc;
1591 int count = 0;
1592
1593 for_each_intel_crtc(dev, crtc)
1594 count += crtc->active &&
1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597 return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 int reg = DPLL(crtc->pipe);
1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609 /* No really, not for ILK+ */
1610 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612 /* PLL is protected by panel, make sure we can write it */
1613 if (IS_MOBILE(dev) && !IS_I830(dev))
1614 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618 /*
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1623 */
1624 dpll |= DPLL_DVO_2X_MODE;
1625 I915_WRITE(DPLL(!crtc->pipe),
1626 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627 }
1628
1629 /* Wait for the clocks to stabilize. */
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (INTEL_INFO(dev)->gen >= 4) {
1634 I915_WRITE(DPLL_MD(crtc->pipe),
1635 crtc->config->dpll_hw_state.dpll_md);
1636 } else {
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1639 *
1640 * So write it again.
1641 */
1642 I915_WRITE(reg, dpll);
1643 }
1644
1645 /* We do this three times for luck */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 I915_WRITE(reg, dpll);
1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658 * i9xx_disable_pll - disable a PLL
1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1661 *
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1663 *
1664 * Note! This is for pre-ILK only.
1665 */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668 struct drm_device *dev = crtc->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 enum pipe pipe = crtc->pipe;
1671
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1673 if (IS_I830(dev) &&
1674 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675 intel_num_dvo_pipes(dev) == 1) {
1676 I915_WRITE(DPLL(PIPE_B),
1677 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678 I915_WRITE(DPLL(PIPE_A),
1679 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680 }
1681
1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685 return;
1686
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv, pipe);
1689
1690 I915_WRITE(DPLL(pipe), 0);
1691 POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696 u32 val = 0;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 /*
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1704 */
1705 if (pipe == PIPE_B)
1706 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715 u32 val;
1716
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1719
1720 /* Set PLL en = 0 */
1721 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722 if (pipe != PIPE_A)
1723 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726
1727 mutex_lock(&dev_priv->dpio_lock);
1728
1729 /* Disable 10bit clock to display controller */
1730 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731 val &= ~DPIO_DCLKP_EN;
1732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734 /* disable left/right clock distribution */
1735 if (pipe != PIPE_B) {
1736 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739 } else {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743 }
1744
1745 mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749 struct intel_digital_port *dport)
1750 {
1751 u32 port_mask;
1752 int dpll_reg;
1753
1754 switch (dport->port) {
1755 case PORT_B:
1756 port_mask = DPLL_PORTB_READY_MASK;
1757 dpll_reg = DPLL(0);
1758 break;
1759 case PORT_C:
1760 port_mask = DPLL_PORTC_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_D:
1764 port_mask = DPLL_PORTD_READY_MASK;
1765 dpll_reg = DPIO_PHY_STATUS;
1766 break;
1767 default:
1768 BUG();
1769 }
1770
1771 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773 port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 WARN_ON(!pll->config.crtc_mask);
1786 if (pll->active == 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788 WARN_ON(pll->on);
1789 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791 pll->mode_set(dev_priv, pll);
1792 }
1793 }
1794
1795 /**
1796 * intel_enable_shared_dpll - enable PCH PLL
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1799 *
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1802 */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809 if (WARN_ON(pll == NULL))
1810 return;
1811
1812 if (WARN_ON(pll->config.crtc_mask == 0))
1813 return;
1814
1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816 pll->name, pll->active, pll->on,
1817 crtc->base.base.id);
1818
1819 if (pll->active++) {
1820 WARN_ON(!pll->on);
1821 assert_shared_dpll_enabled(dev_priv, pll);
1822 return;
1823 }
1824 WARN_ON(pll->on);
1825
1826 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829 pll->enable(dev_priv, pll);
1830 pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841 if (WARN_ON(pll == NULL))
1842 return;
1843
1844 if (WARN_ON(pll->config.crtc_mask == 0))
1845 return;
1846
1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll->name, pll->active, pll->on,
1849 crtc->base.base.id);
1850
1851 if (WARN_ON(pll->active == 0)) {
1852 assert_shared_dpll_disabled(dev_priv, pll);
1853 return;
1854 }
1855
1856 assert_shared_dpll_enabled(dev_priv, pll);
1857 WARN_ON(!pll->on);
1858 if (--pll->active)
1859 return;
1860
1861 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862 pll->disable(dev_priv, pll);
1863 pll->on = false;
1864
1865 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869 enum pipe pipe)
1870 {
1871 struct drm_device *dev = dev_priv->dev;
1872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874 uint32_t reg, val, pipeconf_val;
1875
1876 /* PCH only available on ILK+ */
1877 BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879 /* Make sure PCH DPLL is enabled */
1880 assert_shared_dpll_enabled(dev_priv,
1881 intel_crtc_to_shared_dpll(intel_crtc));
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, pipe);
1885 assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887 if (HAS_PCH_CPT(dev)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg = TRANS_CHICKEN2(pipe);
1891 val = I915_READ(reg);
1892 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893 I915_WRITE(reg, val);
1894 }
1895
1896 reg = PCH_TRANSCONF(pipe);
1897 val = I915_READ(reg);
1898 pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900 if (HAS_PCH_IBX(dev_priv->dev)) {
1901 /*
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1904 */
1905 val &= ~PIPECONF_BPC_MASK;
1906 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907 }
1908
1909 val &= ~TRANS_INTERLACE_MASK;
1910 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911 if (HAS_PCH_IBX(dev_priv->dev) &&
1912 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913 val |= TRANS_LEGACY_INTERLACED_ILK;
1914 else
1915 val |= TRANS_INTERLACED;
1916 else
1917 val |= TRANS_PROGRESSIVE;
1918
1919 I915_WRITE(reg, val | TRANS_ENABLE);
1920 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925 enum transcoder cpu_transcoder)
1926 {
1927 u32 val, pipeconf_val;
1928
1929 /* PCH only available on ILK+ */
1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932 /* FDI must be feeding us bits for PCH ports */
1933 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936 /* Workaround: set timing override bit. */
1937 val = I915_READ(_TRANSA_CHICKEN2);
1938 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939 I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941 val = TRANS_ENABLE;
1942 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945 PIPECONF_INTERLACED_ILK)
1946 val |= TRANS_INTERLACED;
1947 else
1948 val |= TRANS_PROGRESSIVE;
1949
1950 I915_WRITE(LPT_TRANSCONF, val);
1951 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956 enum pipe pipe)
1957 {
1958 struct drm_device *dev = dev_priv->dev;
1959 uint32_t reg, val;
1960
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv, pipe);
1963 assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv, pipe);
1967
1968 reg = PCH_TRANSCONF(pipe);
1969 val = I915_READ(reg);
1970 val &= ~TRANS_ENABLE;
1971 I915_WRITE(reg, val);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976 if (!HAS_PCH_IBX(dev)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg = TRANS_CHICKEN2(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(reg, val);
1982 }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987 u32 val;
1988
1989 val = I915_READ(LPT_TRANSCONF);
1990 val &= ~TRANS_ENABLE;
1991 I915_WRITE(LPT_TRANSCONF, val);
1992 /* wait for PCH transcoder off, transcoder state */
1993 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996 /* Workaround: clear timing override bit. */
1997 val = I915_READ(_TRANSA_CHICKEN2);
1998 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999 I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003 * intel_enable_pipe - enable a pipe, asserting requirements
2004 * @crtc: crtc responsible for the pipe
2005 *
2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008 */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011 struct drm_device *dev = crtc->base.dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 enum pipe pipe = crtc->pipe;
2014 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015 pipe);
2016 enum pipe pch_transcoder;
2017 int reg;
2018 u32 val;
2019
2020 assert_planes_disabled(dev_priv, pipe);
2021 assert_cursor_disabled(dev_priv, pipe);
2022 assert_sprites_disabled(dev_priv, pipe);
2023
2024 if (HAS_PCH_LPT(dev_priv->dev))
2025 pch_transcoder = TRANSCODER_A;
2026 else
2027 pch_transcoder = pipe;
2028
2029 /*
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2032 * need the check.
2033 */
2034 if (!HAS_PCH_SPLIT(dev_priv->dev))
2035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036 assert_dsi_pll_enabled(dev_priv);
2037 else
2038 assert_pll_enabled(dev_priv, pipe);
2039 else {
2040 if (crtc->config->has_pch_encoder) {
2041 /* if driving the PCH, we need FDI enabled */
2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043 assert_fdi_tx_pll_enabled(dev_priv,
2044 (enum pipe) cpu_transcoder);
2045 }
2046 /* FIXME: assert CPU port conditions for SNB+ */
2047 }
2048
2049 reg = PIPECONF(cpu_transcoder);
2050 val = I915_READ(reg);
2051 if (val & PIPECONF_ENABLE) {
2052 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054 return;
2055 }
2056
2057 I915_WRITE(reg, val | PIPECONF_ENABLE);
2058 POSTING_READ(reg);
2059 }
2060
2061 /**
2062 * intel_disable_pipe - disable a pipe, asserting requirements
2063 * @crtc: crtc whose pipes is to be disabled
2064 *
2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
2068 *
2069 * Will wait until the pipe has shut down before returning.
2070 */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075 enum pipe pipe = crtc->pipe;
2076 int reg;
2077 u32 val;
2078
2079 /*
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2082 */
2083 assert_planes_disabled(dev_priv, pipe);
2084 assert_cursor_disabled(dev_priv, pipe);
2085 assert_sprites_disabled(dev_priv, pipe);
2086
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2090 return;
2091
2092 /*
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2095 */
2096 if (crtc->config->double_wide)
2097 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099 /* Don't disable pipe or pipe PLLs if needed */
2100 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102 val &= ~PIPECONF_ENABLE;
2103
2104 I915_WRITE(reg, val);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2112 */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114 enum plane plane)
2115 {
2116 struct drm_device *dev = dev_priv->dev;
2117 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119 I915_WRITE(reg, I915_READ(reg));
2120 POSTING_READ(reg);
2121 }
2122
2123 /**
2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
2127 *
2128 * Enable @plane on @crtc, making sure that the pipe is running first.
2129 */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2132 {
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140 if (intel_crtc->primary_enabled)
2141 return;
2142
2143 intel_crtc->primary_enabled = true;
2144
2145 dev_priv->display.update_primary_plane(crtc, plane->fb,
2146 crtc->x, crtc->y);
2147
2148 /*
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2152 */
2153 if (IS_BROADWELL(dev))
2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
2161 *
2162 * Disable @plane on @crtc, making sure that the pipe is running first.
2163 */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165 struct drm_crtc *crtc)
2166 {
2167 struct drm_device *dev = plane->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171 if (WARN_ON(!intel_crtc->active))
2172 return;
2173
2174 if (!intel_crtc->primary_enabled)
2175 return;
2176
2177 intel_crtc->primary_enabled = false;
2178
2179 dev_priv->display.update_primary_plane(crtc, plane->fb,
2180 crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187 return true;
2188 #endif
2189 return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height,
2194 uint32_t pixel_format,
2195 uint64_t fb_format_modifier)
2196 {
2197 int tile_height;
2198 uint32_t bits_per_pixel;
2199
2200 switch (fb_format_modifier) {
2201 case DRM_FORMAT_MOD_NONE:
2202 tile_height = 1;
2203 break;
2204 case I915_FORMAT_MOD_X_TILED:
2205 tile_height = IS_GEN2(dev) ? 16 : 8;
2206 break;
2207 case I915_FORMAT_MOD_Y_TILED:
2208 tile_height = 32;
2209 break;
2210 case I915_FORMAT_MOD_Yf_TILED:
2211 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2212 switch (bits_per_pixel) {
2213 default:
2214 case 8:
2215 tile_height = 64;
2216 break;
2217 case 16:
2218 case 32:
2219 tile_height = 32;
2220 break;
2221 case 64:
2222 tile_height = 16;
2223 break;
2224 case 128:
2225 WARN_ONCE(1,
2226 "128-bit pixels are not supported for display!");
2227 tile_height = 16;
2228 break;
2229 }
2230 break;
2231 default:
2232 MISSING_CASE(fb_format_modifier);
2233 tile_height = 1;
2234 break;
2235 }
2236
2237 return ALIGN(height, tile_height);
2238 }
2239
2240 int
2241 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2242 struct drm_framebuffer *fb,
2243 struct intel_engine_cs *pipelined)
2244 {
2245 struct drm_device *dev = fb->dev;
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248 u32 alignment;
2249 int ret;
2250
2251 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2252
2253 switch (fb->modifier[0]) {
2254 case DRM_FORMAT_MOD_NONE:
2255 if (INTEL_INFO(dev)->gen >= 9)
2256 alignment = 256 * 1024;
2257 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2258 alignment = 128 * 1024;
2259 else if (INTEL_INFO(dev)->gen >= 4)
2260 alignment = 4 * 1024;
2261 else
2262 alignment = 64 * 1024;
2263 break;
2264 case I915_FORMAT_MOD_X_TILED:
2265 if (INTEL_INFO(dev)->gen >= 9)
2266 alignment = 256 * 1024;
2267 else {
2268 /* pin() will align the object as required by fence */
2269 alignment = 0;
2270 }
2271 break;
2272 case I915_FORMAT_MOD_Y_TILED:
2273 case I915_FORMAT_MOD_Yf_TILED:
2274 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2275 "Y tiling bo slipped through, driver bug!\n"))
2276 return -EINVAL;
2277 alignment = 1 * 1024 * 1024;
2278 break;
2279 default:
2280 MISSING_CASE(fb->modifier[0]);
2281 return -EINVAL;
2282 }
2283
2284 /* Note that the w/a also requires 64 PTE of padding following the
2285 * bo. We currently fill all unused PTE with the shadow page and so
2286 * we should always have valid PTE following the scanout preventing
2287 * the VT-d warning.
2288 */
2289 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2290 alignment = 256 * 1024;
2291
2292 /*
2293 * Global gtt pte registers are special registers which actually forward
2294 * writes to a chunk of system memory. Which means that there is no risk
2295 * that the register values disappear as soon as we call
2296 * intel_runtime_pm_put(), so it is correct to wrap only the
2297 * pin/unpin/fence and not more.
2298 */
2299 intel_runtime_pm_get(dev_priv);
2300
2301 dev_priv->mm.interruptible = false;
2302 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2303 if (ret)
2304 goto err_interruptible;
2305
2306 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2307 * fence, whereas 965+ only requires a fence if using
2308 * framebuffer compression. For simplicity, we always install
2309 * a fence as the cost is not that onerous.
2310 */
2311 ret = i915_gem_object_get_fence(obj);
2312 if (ret)
2313 goto err_unpin;
2314
2315 i915_gem_object_pin_fence(obj);
2316
2317 dev_priv->mm.interruptible = true;
2318 intel_runtime_pm_put(dev_priv);
2319 return 0;
2320
2321 err_unpin:
2322 i915_gem_object_unpin_from_display_plane(obj);
2323 err_interruptible:
2324 dev_priv->mm.interruptible = true;
2325 intel_runtime_pm_put(dev_priv);
2326 return ret;
2327 }
2328
2329 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2330 {
2331 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2332
2333 i915_gem_object_unpin_fence(obj);
2334 i915_gem_object_unpin_from_display_plane(obj);
2335 }
2336
2337 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2338 * is assumed to be a power-of-two. */
2339 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2340 unsigned int tiling_mode,
2341 unsigned int cpp,
2342 unsigned int pitch)
2343 {
2344 if (tiling_mode != I915_TILING_NONE) {
2345 unsigned int tile_rows, tiles;
2346
2347 tile_rows = *y / 8;
2348 *y %= 8;
2349
2350 tiles = *x / (512/cpp);
2351 *x %= 512/cpp;
2352
2353 return tile_rows * pitch * 8 + tiles * 4096;
2354 } else {
2355 unsigned int offset;
2356
2357 offset = *y * pitch + *x * cpp;
2358 *y = 0;
2359 *x = (offset & 4095) / cpp;
2360 return offset & -4096;
2361 }
2362 }
2363
2364 static int i9xx_format_to_fourcc(int format)
2365 {
2366 switch (format) {
2367 case DISPPLANE_8BPP:
2368 return DRM_FORMAT_C8;
2369 case DISPPLANE_BGRX555:
2370 return DRM_FORMAT_XRGB1555;
2371 case DISPPLANE_BGRX565:
2372 return DRM_FORMAT_RGB565;
2373 default:
2374 case DISPPLANE_BGRX888:
2375 return DRM_FORMAT_XRGB8888;
2376 case DISPPLANE_RGBX888:
2377 return DRM_FORMAT_XBGR8888;
2378 case DISPPLANE_BGRX101010:
2379 return DRM_FORMAT_XRGB2101010;
2380 case DISPPLANE_RGBX101010:
2381 return DRM_FORMAT_XBGR2101010;
2382 }
2383 }
2384
2385 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2386 {
2387 switch (format) {
2388 case PLANE_CTL_FORMAT_RGB_565:
2389 return DRM_FORMAT_RGB565;
2390 default:
2391 case PLANE_CTL_FORMAT_XRGB_8888:
2392 if (rgb_order) {
2393 if (alpha)
2394 return DRM_FORMAT_ABGR8888;
2395 else
2396 return DRM_FORMAT_XBGR8888;
2397 } else {
2398 if (alpha)
2399 return DRM_FORMAT_ARGB8888;
2400 else
2401 return DRM_FORMAT_XRGB8888;
2402 }
2403 case PLANE_CTL_FORMAT_XRGB_2101010:
2404 if (rgb_order)
2405 return DRM_FORMAT_XBGR2101010;
2406 else
2407 return DRM_FORMAT_XRGB2101010;
2408 }
2409 }
2410
2411 static bool
2412 intel_alloc_plane_obj(struct intel_crtc *crtc,
2413 struct intel_initial_plane_config *plane_config)
2414 {
2415 struct drm_device *dev = crtc->base.dev;
2416 struct drm_i915_gem_object *obj = NULL;
2417 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2418 struct drm_framebuffer *fb = &plane_config->fb->base;
2419 u32 base = plane_config->base;
2420
2421 if (plane_config->size == 0)
2422 return false;
2423
2424 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2425 plane_config->size);
2426 if (!obj)
2427 return false;
2428
2429 obj->tiling_mode = plane_config->tiling;
2430 if (obj->tiling_mode == I915_TILING_X)
2431 obj->stride = fb->pitches[0];
2432
2433 mode_cmd.pixel_format = fb->pixel_format;
2434 mode_cmd.width = fb->width;
2435 mode_cmd.height = fb->height;
2436 mode_cmd.pitches[0] = fb->pitches[0];
2437 mode_cmd.modifier[0] = fb->modifier[0];
2438 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2439
2440 mutex_lock(&dev->struct_mutex);
2441
2442 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2443 &mode_cmd, obj)) {
2444 DRM_DEBUG_KMS("intel fb init failed\n");
2445 goto out_unref_obj;
2446 }
2447
2448 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2449 mutex_unlock(&dev->struct_mutex);
2450
2451 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2452 return true;
2453
2454 out_unref_obj:
2455 drm_gem_object_unreference(&obj->base);
2456 mutex_unlock(&dev->struct_mutex);
2457 return false;
2458 }
2459
2460 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2461 static void
2462 update_state_fb(struct drm_plane *plane)
2463 {
2464 if (plane->fb == plane->state->fb)
2465 return;
2466
2467 if (plane->state->fb)
2468 drm_framebuffer_unreference(plane->state->fb);
2469 plane->state->fb = plane->fb;
2470 if (plane->state->fb)
2471 drm_framebuffer_reference(plane->state->fb);
2472 }
2473
2474 static void
2475 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2476 struct intel_initial_plane_config *plane_config)
2477 {
2478 struct drm_device *dev = intel_crtc->base.dev;
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct drm_crtc *c;
2481 struct intel_crtc *i;
2482 struct drm_i915_gem_object *obj;
2483
2484 if (!plane_config->fb)
2485 return;
2486
2487 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2488 struct drm_plane *primary = intel_crtc->base.primary;
2489
2490 primary->fb = &plane_config->fb->base;
2491 primary->state->crtc = &intel_crtc->base;
2492 update_state_fb(primary);
2493
2494 return;
2495 }
2496
2497 kfree(plane_config->fb);
2498
2499 /*
2500 * Failed to alloc the obj, check to see if we should share
2501 * an fb with another CRTC instead
2502 */
2503 for_each_crtc(dev, c) {
2504 i = to_intel_crtc(c);
2505
2506 if (c == &intel_crtc->base)
2507 continue;
2508
2509 if (!i->active)
2510 continue;
2511
2512 obj = intel_fb_obj(c->primary->fb);
2513 if (obj == NULL)
2514 continue;
2515
2516 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2517 struct drm_plane *primary = intel_crtc->base.primary;
2518
2519 if (obj->tiling_mode != I915_TILING_NONE)
2520 dev_priv->preserve_bios_swizzle = true;
2521
2522 drm_framebuffer_reference(c->primary->fb);
2523 primary->fb = c->primary->fb;
2524 primary->state->crtc = &intel_crtc->base;
2525 update_state_fb(intel_crtc->base.primary);
2526 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2527 break;
2528 }
2529 }
2530
2531 }
2532
2533 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2534 struct drm_framebuffer *fb,
2535 int x, int y)
2536 {
2537 struct drm_device *dev = crtc->dev;
2538 struct drm_i915_private *dev_priv = dev->dev_private;
2539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2540 struct drm_i915_gem_object *obj;
2541 int plane = intel_crtc->plane;
2542 unsigned long linear_offset;
2543 u32 dspcntr;
2544 u32 reg = DSPCNTR(plane);
2545 int pixel_size;
2546
2547 if (!intel_crtc->primary_enabled) {
2548 I915_WRITE(reg, 0);
2549 if (INTEL_INFO(dev)->gen >= 4)
2550 I915_WRITE(DSPSURF(plane), 0);
2551 else
2552 I915_WRITE(DSPADDR(plane), 0);
2553 POSTING_READ(reg);
2554 return;
2555 }
2556
2557 obj = intel_fb_obj(fb);
2558 if (WARN_ON(obj == NULL))
2559 return;
2560
2561 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2562
2563 dspcntr = DISPPLANE_GAMMA_ENABLE;
2564
2565 dspcntr |= DISPLAY_PLANE_ENABLE;
2566
2567 if (INTEL_INFO(dev)->gen < 4) {
2568 if (intel_crtc->pipe == PIPE_B)
2569 dspcntr |= DISPPLANE_SEL_PIPE_B;
2570
2571 /* pipesrc and dspsize control the size that is scaled from,
2572 * which should always be the user's requested size.
2573 */
2574 I915_WRITE(DSPSIZE(plane),
2575 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2576 (intel_crtc->config->pipe_src_w - 1));
2577 I915_WRITE(DSPPOS(plane), 0);
2578 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2579 I915_WRITE(PRIMSIZE(plane),
2580 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2581 (intel_crtc->config->pipe_src_w - 1));
2582 I915_WRITE(PRIMPOS(plane), 0);
2583 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2584 }
2585
2586 switch (fb->pixel_format) {
2587 case DRM_FORMAT_C8:
2588 dspcntr |= DISPPLANE_8BPP;
2589 break;
2590 case DRM_FORMAT_XRGB1555:
2591 case DRM_FORMAT_ARGB1555:
2592 dspcntr |= DISPPLANE_BGRX555;
2593 break;
2594 case DRM_FORMAT_RGB565:
2595 dspcntr |= DISPPLANE_BGRX565;
2596 break;
2597 case DRM_FORMAT_XRGB8888:
2598 case DRM_FORMAT_ARGB8888:
2599 dspcntr |= DISPPLANE_BGRX888;
2600 break;
2601 case DRM_FORMAT_XBGR8888:
2602 case DRM_FORMAT_ABGR8888:
2603 dspcntr |= DISPPLANE_RGBX888;
2604 break;
2605 case DRM_FORMAT_XRGB2101010:
2606 case DRM_FORMAT_ARGB2101010:
2607 dspcntr |= DISPPLANE_BGRX101010;
2608 break;
2609 case DRM_FORMAT_XBGR2101010:
2610 case DRM_FORMAT_ABGR2101010:
2611 dspcntr |= DISPPLANE_RGBX101010;
2612 break;
2613 default:
2614 BUG();
2615 }
2616
2617 if (INTEL_INFO(dev)->gen >= 4 &&
2618 obj->tiling_mode != I915_TILING_NONE)
2619 dspcntr |= DISPPLANE_TILED;
2620
2621 if (IS_G4X(dev))
2622 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2623
2624 linear_offset = y * fb->pitches[0] + x * pixel_size;
2625
2626 if (INTEL_INFO(dev)->gen >= 4) {
2627 intel_crtc->dspaddr_offset =
2628 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2629 pixel_size,
2630 fb->pitches[0]);
2631 linear_offset -= intel_crtc->dspaddr_offset;
2632 } else {
2633 intel_crtc->dspaddr_offset = linear_offset;
2634 }
2635
2636 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2637 dspcntr |= DISPPLANE_ROTATE_180;
2638
2639 x += (intel_crtc->config->pipe_src_w - 1);
2640 y += (intel_crtc->config->pipe_src_h - 1);
2641
2642 /* Finding the last pixel of the last line of the display
2643 data and adding to linear_offset*/
2644 linear_offset +=
2645 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2646 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2647 }
2648
2649 I915_WRITE(reg, dspcntr);
2650
2651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653 fb->pitches[0]);
2654 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655 if (INTEL_INFO(dev)->gen >= 4) {
2656 I915_WRITE(DSPSURF(plane),
2657 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2658 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2659 I915_WRITE(DSPLINOFF(plane), linear_offset);
2660 } else
2661 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2662 POSTING_READ(reg);
2663 }
2664
2665 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2666 struct drm_framebuffer *fb,
2667 int x, int y)
2668 {
2669 struct drm_device *dev = crtc->dev;
2670 struct drm_i915_private *dev_priv = dev->dev_private;
2671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2672 struct drm_i915_gem_object *obj;
2673 int plane = intel_crtc->plane;
2674 unsigned long linear_offset;
2675 u32 dspcntr;
2676 u32 reg = DSPCNTR(plane);
2677 int pixel_size;
2678
2679 if (!intel_crtc->primary_enabled) {
2680 I915_WRITE(reg, 0);
2681 I915_WRITE(DSPSURF(plane), 0);
2682 POSTING_READ(reg);
2683 return;
2684 }
2685
2686 obj = intel_fb_obj(fb);
2687 if (WARN_ON(obj == NULL))
2688 return;
2689
2690 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2691
2692 dspcntr = DISPPLANE_GAMMA_ENABLE;
2693
2694 dspcntr |= DISPLAY_PLANE_ENABLE;
2695
2696 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2697 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2698
2699 switch (fb->pixel_format) {
2700 case DRM_FORMAT_C8:
2701 dspcntr |= DISPPLANE_8BPP;
2702 break;
2703 case DRM_FORMAT_RGB565:
2704 dspcntr |= DISPPLANE_BGRX565;
2705 break;
2706 case DRM_FORMAT_XRGB8888:
2707 case DRM_FORMAT_ARGB8888:
2708 dspcntr |= DISPPLANE_BGRX888;
2709 break;
2710 case DRM_FORMAT_XBGR8888:
2711 case DRM_FORMAT_ABGR8888:
2712 dspcntr |= DISPPLANE_RGBX888;
2713 break;
2714 case DRM_FORMAT_XRGB2101010:
2715 case DRM_FORMAT_ARGB2101010:
2716 dspcntr |= DISPPLANE_BGRX101010;
2717 break;
2718 case DRM_FORMAT_XBGR2101010:
2719 case DRM_FORMAT_ABGR2101010:
2720 dspcntr |= DISPPLANE_RGBX101010;
2721 break;
2722 default:
2723 BUG();
2724 }
2725
2726 if (obj->tiling_mode != I915_TILING_NONE)
2727 dspcntr |= DISPPLANE_TILED;
2728
2729 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2730 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2731
2732 linear_offset = y * fb->pitches[0] + x * pixel_size;
2733 intel_crtc->dspaddr_offset =
2734 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2735 pixel_size,
2736 fb->pitches[0]);
2737 linear_offset -= intel_crtc->dspaddr_offset;
2738 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2739 dspcntr |= DISPPLANE_ROTATE_180;
2740
2741 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2742 x += (intel_crtc->config->pipe_src_w - 1);
2743 y += (intel_crtc->config->pipe_src_h - 1);
2744
2745 /* Finding the last pixel of the last line of the display
2746 data and adding to linear_offset*/
2747 linear_offset +=
2748 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2749 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2750 }
2751 }
2752
2753 I915_WRITE(reg, dspcntr);
2754
2755 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2756 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2757 fb->pitches[0]);
2758 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2759 I915_WRITE(DSPSURF(plane),
2760 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2761 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2762 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2763 } else {
2764 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2765 I915_WRITE(DSPLINOFF(plane), linear_offset);
2766 }
2767 POSTING_READ(reg);
2768 }
2769
2770 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2771 uint32_t pixel_format)
2772 {
2773 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2774
2775 /*
2776 * The stride is either expressed as a multiple of 64 bytes
2777 * chunks for linear buffers or in number of tiles for tiled
2778 * buffers.
2779 */
2780 switch (fb_modifier) {
2781 case DRM_FORMAT_MOD_NONE:
2782 return 64;
2783 case I915_FORMAT_MOD_X_TILED:
2784 if (INTEL_INFO(dev)->gen == 2)
2785 return 128;
2786 return 512;
2787 case I915_FORMAT_MOD_Y_TILED:
2788 /* No need to check for old gens and Y tiling since this is
2789 * about the display engine and those will be blocked before
2790 * we get here.
2791 */
2792 return 128;
2793 case I915_FORMAT_MOD_Yf_TILED:
2794 if (bits_per_pixel == 8)
2795 return 64;
2796 else
2797 return 128;
2798 default:
2799 MISSING_CASE(fb_modifier);
2800 return 64;
2801 }
2802 }
2803
2804 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2805 struct drm_framebuffer *fb,
2806 int x, int y)
2807 {
2808 struct drm_device *dev = crtc->dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2811 struct drm_i915_gem_object *obj;
2812 int pipe = intel_crtc->pipe;
2813 u32 plane_ctl, stride_div;
2814
2815 if (!intel_crtc->primary_enabled) {
2816 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2817 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2818 POSTING_READ(PLANE_CTL(pipe, 0));
2819 return;
2820 }
2821
2822 plane_ctl = PLANE_CTL_ENABLE |
2823 PLANE_CTL_PIPE_GAMMA_ENABLE |
2824 PLANE_CTL_PIPE_CSC_ENABLE;
2825
2826 switch (fb->pixel_format) {
2827 case DRM_FORMAT_RGB565:
2828 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2829 break;
2830 case DRM_FORMAT_XRGB8888:
2831 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2832 break;
2833 case DRM_FORMAT_XBGR8888:
2834 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2835 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2836 break;
2837 case DRM_FORMAT_XRGB2101010:
2838 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2839 break;
2840 case DRM_FORMAT_XBGR2101010:
2841 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2842 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2843 break;
2844 default:
2845 BUG();
2846 }
2847
2848 switch (fb->modifier[0]) {
2849 case DRM_FORMAT_MOD_NONE:
2850 break;
2851 case I915_FORMAT_MOD_X_TILED:
2852 plane_ctl |= PLANE_CTL_TILED_X;
2853 break;
2854 case I915_FORMAT_MOD_Y_TILED:
2855 plane_ctl |= PLANE_CTL_TILED_Y;
2856 break;
2857 case I915_FORMAT_MOD_Yf_TILED:
2858 plane_ctl |= PLANE_CTL_TILED_YF;
2859 break;
2860 default:
2861 MISSING_CASE(fb->modifier[0]);
2862 }
2863
2864 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2865 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2866 plane_ctl |= PLANE_CTL_ROTATE_180;
2867
2868 obj = intel_fb_obj(fb);
2869 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2870 fb->pixel_format);
2871
2872 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2873
2874 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2875 i915_gem_obj_ggtt_offset(obj),
2876 x, y, fb->width, fb->height,
2877 fb->pitches[0]);
2878
2879 I915_WRITE(PLANE_POS(pipe, 0), 0);
2880 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2881 I915_WRITE(PLANE_SIZE(pipe, 0),
2882 (intel_crtc->config->pipe_src_h - 1) << 16 |
2883 (intel_crtc->config->pipe_src_w - 1));
2884 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2885 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2886
2887 POSTING_READ(PLANE_SURF(pipe, 0));
2888 }
2889
2890 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2891 static int
2892 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2893 int x, int y, enum mode_set_atomic state)
2894 {
2895 struct drm_device *dev = crtc->dev;
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897
2898 if (dev_priv->display.disable_fbc)
2899 dev_priv->display.disable_fbc(dev);
2900
2901 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2902
2903 return 0;
2904 }
2905
2906 static void intel_complete_page_flips(struct drm_device *dev)
2907 {
2908 struct drm_crtc *crtc;
2909
2910 for_each_crtc(dev, crtc) {
2911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2912 enum plane plane = intel_crtc->plane;
2913
2914 intel_prepare_page_flip(dev, plane);
2915 intel_finish_page_flip_plane(dev, plane);
2916 }
2917 }
2918
2919 static void intel_update_primary_planes(struct drm_device *dev)
2920 {
2921 struct drm_i915_private *dev_priv = dev->dev_private;
2922 struct drm_crtc *crtc;
2923
2924 for_each_crtc(dev, crtc) {
2925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2926
2927 drm_modeset_lock(&crtc->mutex, NULL);
2928 /*
2929 * FIXME: Once we have proper support for primary planes (and
2930 * disabling them without disabling the entire crtc) allow again
2931 * a NULL crtc->primary->fb.
2932 */
2933 if (intel_crtc->active && crtc->primary->fb)
2934 dev_priv->display.update_primary_plane(crtc,
2935 crtc->primary->fb,
2936 crtc->x,
2937 crtc->y);
2938 drm_modeset_unlock(&crtc->mutex);
2939 }
2940 }
2941
2942 void intel_prepare_reset(struct drm_device *dev)
2943 {
2944 struct drm_i915_private *dev_priv = to_i915(dev);
2945 struct intel_crtc *crtc;
2946
2947 /* no reset support for gen2 */
2948 if (IS_GEN2(dev))
2949 return;
2950
2951 /* reset doesn't touch the display */
2952 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2953 return;
2954
2955 drm_modeset_lock_all(dev);
2956
2957 /*
2958 * Disabling the crtcs gracefully seems nicer. Also the
2959 * g33 docs say we should at least disable all the planes.
2960 */
2961 for_each_intel_crtc(dev, crtc) {
2962 if (crtc->active)
2963 dev_priv->display.crtc_disable(&crtc->base);
2964 }
2965 }
2966
2967 void intel_finish_reset(struct drm_device *dev)
2968 {
2969 struct drm_i915_private *dev_priv = to_i915(dev);
2970
2971 /*
2972 * Flips in the rings will be nuked by the reset,
2973 * so complete all pending flips so that user space
2974 * will get its events and not get stuck.
2975 */
2976 intel_complete_page_flips(dev);
2977
2978 /* no reset support for gen2 */
2979 if (IS_GEN2(dev))
2980 return;
2981
2982 /* reset doesn't touch the display */
2983 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2984 /*
2985 * Flips in the rings have been nuked by the reset,
2986 * so update the base address of all primary
2987 * planes to the the last fb to make sure we're
2988 * showing the correct fb after a reset.
2989 */
2990 intel_update_primary_planes(dev);
2991 return;
2992 }
2993
2994 /*
2995 * The display has been reset as well,
2996 * so need a full re-initialization.
2997 */
2998 intel_runtime_pm_disable_interrupts(dev_priv);
2999 intel_runtime_pm_enable_interrupts(dev_priv);
3000
3001 intel_modeset_init_hw(dev);
3002
3003 spin_lock_irq(&dev_priv->irq_lock);
3004 if (dev_priv->display.hpd_irq_setup)
3005 dev_priv->display.hpd_irq_setup(dev);
3006 spin_unlock_irq(&dev_priv->irq_lock);
3007
3008 intel_modeset_setup_hw_state(dev, true);
3009
3010 intel_hpd_init(dev_priv);
3011
3012 drm_modeset_unlock_all(dev);
3013 }
3014
3015 static int
3016 intel_finish_fb(struct drm_framebuffer *old_fb)
3017 {
3018 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3019 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3020 bool was_interruptible = dev_priv->mm.interruptible;
3021 int ret;
3022
3023 /* Big Hammer, we also need to ensure that any pending
3024 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3025 * current scanout is retired before unpinning the old
3026 * framebuffer.
3027 *
3028 * This should only fail upon a hung GPU, in which case we
3029 * can safely continue.
3030 */
3031 dev_priv->mm.interruptible = false;
3032 ret = i915_gem_object_finish_gpu(obj);
3033 dev_priv->mm.interruptible = was_interruptible;
3034
3035 return ret;
3036 }
3037
3038 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3039 {
3040 struct drm_device *dev = crtc->dev;
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3043 bool pending;
3044
3045 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3046 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3047 return false;
3048
3049 spin_lock_irq(&dev->event_lock);
3050 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3051 spin_unlock_irq(&dev->event_lock);
3052
3053 return pending;
3054 }
3055
3056 static void intel_update_pipe_size(struct intel_crtc *crtc)
3057 {
3058 struct drm_device *dev = crtc->base.dev;
3059 struct drm_i915_private *dev_priv = dev->dev_private;
3060 const struct drm_display_mode *adjusted_mode;
3061
3062 if (!i915.fastboot)
3063 return;
3064
3065 /*
3066 * Update pipe size and adjust fitter if needed: the reason for this is
3067 * that in compute_mode_changes we check the native mode (not the pfit
3068 * mode) to see if we can flip rather than do a full mode set. In the
3069 * fastboot case, we'll flip, but if we don't update the pipesrc and
3070 * pfit state, we'll end up with a big fb scanned out into the wrong
3071 * sized surface.
3072 *
3073 * To fix this properly, we need to hoist the checks up into
3074 * compute_mode_changes (or above), check the actual pfit state and
3075 * whether the platform allows pfit disable with pipe active, and only
3076 * then update the pipesrc and pfit state, even on the flip path.
3077 */
3078
3079 adjusted_mode = &crtc->config->base.adjusted_mode;
3080
3081 I915_WRITE(PIPESRC(crtc->pipe),
3082 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3083 (adjusted_mode->crtc_vdisplay - 1));
3084 if (!crtc->config->pch_pfit.enabled &&
3085 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3086 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3087 I915_WRITE(PF_CTL(crtc->pipe), 0);
3088 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3089 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3090 }
3091 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3092 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3093 }
3094
3095 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3096 {
3097 struct drm_device *dev = crtc->dev;
3098 struct drm_i915_private *dev_priv = dev->dev_private;
3099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3100 int pipe = intel_crtc->pipe;
3101 u32 reg, temp;
3102
3103 /* enable normal train */
3104 reg = FDI_TX_CTL(pipe);
3105 temp = I915_READ(reg);
3106 if (IS_IVYBRIDGE(dev)) {
3107 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3108 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3109 } else {
3110 temp &= ~FDI_LINK_TRAIN_NONE;
3111 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3112 }
3113 I915_WRITE(reg, temp);
3114
3115 reg = FDI_RX_CTL(pipe);
3116 temp = I915_READ(reg);
3117 if (HAS_PCH_CPT(dev)) {
3118 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3119 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3120 } else {
3121 temp &= ~FDI_LINK_TRAIN_NONE;
3122 temp |= FDI_LINK_TRAIN_NONE;
3123 }
3124 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3125
3126 /* wait one idle pattern time */
3127 POSTING_READ(reg);
3128 udelay(1000);
3129
3130 /* IVB wants error correction enabled */
3131 if (IS_IVYBRIDGE(dev))
3132 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3133 FDI_FE_ERRC_ENABLE);
3134 }
3135
3136 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3137 {
3138 return crtc->base.state->enable && crtc->active &&
3139 crtc->config->has_pch_encoder;
3140 }
3141
3142 static void ivb_modeset_global_resources(struct drm_device *dev)
3143 {
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct intel_crtc *pipe_B_crtc =
3146 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3147 struct intel_crtc *pipe_C_crtc =
3148 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3149 uint32_t temp;
3150
3151 /*
3152 * When everything is off disable fdi C so that we could enable fdi B
3153 * with all lanes. Note that we don't care about enabled pipes without
3154 * an enabled pch encoder.
3155 */
3156 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3157 !pipe_has_enabled_pch(pipe_C_crtc)) {
3158 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3159 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3160
3161 temp = I915_READ(SOUTH_CHICKEN1);
3162 temp &= ~FDI_BC_BIFURCATION_SELECT;
3163 DRM_DEBUG_KMS("disabling fdi C rx\n");
3164 I915_WRITE(SOUTH_CHICKEN1, temp);
3165 }
3166 }
3167
3168 /* The FDI link training functions for ILK/Ibexpeak. */
3169 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3170 {
3171 struct drm_device *dev = crtc->dev;
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3174 int pipe = intel_crtc->pipe;
3175 u32 reg, temp, tries;
3176
3177 /* FDI needs bits from pipe first */
3178 assert_pipe_enabled(dev_priv, pipe);
3179
3180 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3181 for train result */
3182 reg = FDI_RX_IMR(pipe);
3183 temp = I915_READ(reg);
3184 temp &= ~FDI_RX_SYMBOL_LOCK;
3185 temp &= ~FDI_RX_BIT_LOCK;
3186 I915_WRITE(reg, temp);
3187 I915_READ(reg);
3188 udelay(150);
3189
3190 /* enable CPU FDI TX and PCH FDI RX */
3191 reg = FDI_TX_CTL(pipe);
3192 temp = I915_READ(reg);
3193 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3194 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3195 temp &= ~FDI_LINK_TRAIN_NONE;
3196 temp |= FDI_LINK_TRAIN_PATTERN_1;
3197 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3198
3199 reg = FDI_RX_CTL(pipe);
3200 temp = I915_READ(reg);
3201 temp &= ~FDI_LINK_TRAIN_NONE;
3202 temp |= FDI_LINK_TRAIN_PATTERN_1;
3203 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3204
3205 POSTING_READ(reg);
3206 udelay(150);
3207
3208 /* Ironlake workaround, enable clock pointer after FDI enable*/
3209 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3210 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3211 FDI_RX_PHASE_SYNC_POINTER_EN);
3212
3213 reg = FDI_RX_IIR(pipe);
3214 for (tries = 0; tries < 5; tries++) {
3215 temp = I915_READ(reg);
3216 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3217
3218 if ((temp & FDI_RX_BIT_LOCK)) {
3219 DRM_DEBUG_KMS("FDI train 1 done.\n");
3220 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3221 break;
3222 }
3223 }
3224 if (tries == 5)
3225 DRM_ERROR("FDI train 1 fail!\n");
3226
3227 /* Train 2 */
3228 reg = FDI_TX_CTL(pipe);
3229 temp = I915_READ(reg);
3230 temp &= ~FDI_LINK_TRAIN_NONE;
3231 temp |= FDI_LINK_TRAIN_PATTERN_2;
3232 I915_WRITE(reg, temp);
3233
3234 reg = FDI_RX_CTL(pipe);
3235 temp = I915_READ(reg);
3236 temp &= ~FDI_LINK_TRAIN_NONE;
3237 temp |= FDI_LINK_TRAIN_PATTERN_2;
3238 I915_WRITE(reg, temp);
3239
3240 POSTING_READ(reg);
3241 udelay(150);
3242
3243 reg = FDI_RX_IIR(pipe);
3244 for (tries = 0; tries < 5; tries++) {
3245 temp = I915_READ(reg);
3246 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3247
3248 if (temp & FDI_RX_SYMBOL_LOCK) {
3249 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3250 DRM_DEBUG_KMS("FDI train 2 done.\n");
3251 break;
3252 }
3253 }
3254 if (tries == 5)
3255 DRM_ERROR("FDI train 2 fail!\n");
3256
3257 DRM_DEBUG_KMS("FDI train done\n");
3258
3259 }
3260
3261 static const int snb_b_fdi_train_param[] = {
3262 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3263 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3264 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3265 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3266 };
3267
3268 /* The FDI link training functions for SNB/Cougarpoint. */
3269 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3270 {
3271 struct drm_device *dev = crtc->dev;
3272 struct drm_i915_private *dev_priv = dev->dev_private;
3273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3274 int pipe = intel_crtc->pipe;
3275 u32 reg, temp, i, retry;
3276
3277 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3278 for train result */
3279 reg = FDI_RX_IMR(pipe);
3280 temp = I915_READ(reg);
3281 temp &= ~FDI_RX_SYMBOL_LOCK;
3282 temp &= ~FDI_RX_BIT_LOCK;
3283 I915_WRITE(reg, temp);
3284
3285 POSTING_READ(reg);
3286 udelay(150);
3287
3288 /* enable CPU FDI TX and PCH FDI RX */
3289 reg = FDI_TX_CTL(pipe);
3290 temp = I915_READ(reg);
3291 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3292 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3293 temp &= ~FDI_LINK_TRAIN_NONE;
3294 temp |= FDI_LINK_TRAIN_PATTERN_1;
3295 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3296 /* SNB-B */
3297 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3298 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3299
3300 I915_WRITE(FDI_RX_MISC(pipe),
3301 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3302
3303 reg = FDI_RX_CTL(pipe);
3304 temp = I915_READ(reg);
3305 if (HAS_PCH_CPT(dev)) {
3306 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3307 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3308 } else {
3309 temp &= ~FDI_LINK_TRAIN_NONE;
3310 temp |= FDI_LINK_TRAIN_PATTERN_1;
3311 }
3312 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3313
3314 POSTING_READ(reg);
3315 udelay(150);
3316
3317 for (i = 0; i < 4; i++) {
3318 reg = FDI_TX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3321 temp |= snb_b_fdi_train_param[i];
3322 I915_WRITE(reg, temp);
3323
3324 POSTING_READ(reg);
3325 udelay(500);
3326
3327 for (retry = 0; retry < 5; retry++) {
3328 reg = FDI_RX_IIR(pipe);
3329 temp = I915_READ(reg);
3330 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331 if (temp & FDI_RX_BIT_LOCK) {
3332 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3333 DRM_DEBUG_KMS("FDI train 1 done.\n");
3334 break;
3335 }
3336 udelay(50);
3337 }
3338 if (retry < 5)
3339 break;
3340 }
3341 if (i == 4)
3342 DRM_ERROR("FDI train 1 fail!\n");
3343
3344 /* Train 2 */
3345 reg = FDI_TX_CTL(pipe);
3346 temp = I915_READ(reg);
3347 temp &= ~FDI_LINK_TRAIN_NONE;
3348 temp |= FDI_LINK_TRAIN_PATTERN_2;
3349 if (IS_GEN6(dev)) {
3350 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3351 /* SNB-B */
3352 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3353 }
3354 I915_WRITE(reg, temp);
3355
3356 reg = FDI_RX_CTL(pipe);
3357 temp = I915_READ(reg);
3358 if (HAS_PCH_CPT(dev)) {
3359 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3360 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3361 } else {
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_PATTERN_2;
3364 }
3365 I915_WRITE(reg, temp);
3366
3367 POSTING_READ(reg);
3368 udelay(150);
3369
3370 for (i = 0; i < 4; i++) {
3371 reg = FDI_TX_CTL(pipe);
3372 temp = I915_READ(reg);
3373 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3374 temp |= snb_b_fdi_train_param[i];
3375 I915_WRITE(reg, temp);
3376
3377 POSTING_READ(reg);
3378 udelay(500);
3379
3380 for (retry = 0; retry < 5; retry++) {
3381 reg = FDI_RX_IIR(pipe);
3382 temp = I915_READ(reg);
3383 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3384 if (temp & FDI_RX_SYMBOL_LOCK) {
3385 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3386 DRM_DEBUG_KMS("FDI train 2 done.\n");
3387 break;
3388 }
3389 udelay(50);
3390 }
3391 if (retry < 5)
3392 break;
3393 }
3394 if (i == 4)
3395 DRM_ERROR("FDI train 2 fail!\n");
3396
3397 DRM_DEBUG_KMS("FDI train done.\n");
3398 }
3399
3400 /* Manual link training for Ivy Bridge A0 parts */
3401 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3402 {
3403 struct drm_device *dev = crtc->dev;
3404 struct drm_i915_private *dev_priv = dev->dev_private;
3405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3406 int pipe = intel_crtc->pipe;
3407 u32 reg, temp, i, j;
3408
3409 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3410 for train result */
3411 reg = FDI_RX_IMR(pipe);
3412 temp = I915_READ(reg);
3413 temp &= ~FDI_RX_SYMBOL_LOCK;
3414 temp &= ~FDI_RX_BIT_LOCK;
3415 I915_WRITE(reg, temp);
3416
3417 POSTING_READ(reg);
3418 udelay(150);
3419
3420 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3421 I915_READ(FDI_RX_IIR(pipe)));
3422
3423 /* Try each vswing and preemphasis setting twice before moving on */
3424 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3425 /* disable first in case we need to retry */
3426 reg = FDI_TX_CTL(pipe);
3427 temp = I915_READ(reg);
3428 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3429 temp &= ~FDI_TX_ENABLE;
3430 I915_WRITE(reg, temp);
3431
3432 reg = FDI_RX_CTL(pipe);
3433 temp = I915_READ(reg);
3434 temp &= ~FDI_LINK_TRAIN_AUTO;
3435 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3436 temp &= ~FDI_RX_ENABLE;
3437 I915_WRITE(reg, temp);
3438
3439 /* enable CPU FDI TX and PCH FDI RX */
3440 reg = FDI_TX_CTL(pipe);
3441 temp = I915_READ(reg);
3442 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3443 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3444 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3445 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3446 temp |= snb_b_fdi_train_param[j/2];
3447 temp |= FDI_COMPOSITE_SYNC;
3448 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3449
3450 I915_WRITE(FDI_RX_MISC(pipe),
3451 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3452
3453 reg = FDI_RX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3456 temp |= FDI_COMPOSITE_SYNC;
3457 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3458
3459 POSTING_READ(reg);
3460 udelay(1); /* should be 0.5us */
3461
3462 for (i = 0; i < 4; i++) {
3463 reg = FDI_RX_IIR(pipe);
3464 temp = I915_READ(reg);
3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466
3467 if (temp & FDI_RX_BIT_LOCK ||
3468 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3469 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3470 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3471 i);
3472 break;
3473 }
3474 udelay(1); /* should be 0.5us */
3475 }
3476 if (i == 4) {
3477 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3478 continue;
3479 }
3480
3481 /* Train 2 */
3482 reg = FDI_TX_CTL(pipe);
3483 temp = I915_READ(reg);
3484 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3485 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3486 I915_WRITE(reg, temp);
3487
3488 reg = FDI_RX_CTL(pipe);
3489 temp = I915_READ(reg);
3490 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3491 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3492 I915_WRITE(reg, temp);
3493
3494 POSTING_READ(reg);
3495 udelay(2); /* should be 1.5us */
3496
3497 for (i = 0; i < 4; i++) {
3498 reg = FDI_RX_IIR(pipe);
3499 temp = I915_READ(reg);
3500 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3501
3502 if (temp & FDI_RX_SYMBOL_LOCK ||
3503 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3504 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3505 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3506 i);
3507 goto train_done;
3508 }
3509 udelay(2); /* should be 1.5us */
3510 }
3511 if (i == 4)
3512 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3513 }
3514
3515 train_done:
3516 DRM_DEBUG_KMS("FDI train done.\n");
3517 }
3518
3519 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3520 {
3521 struct drm_device *dev = intel_crtc->base.dev;
3522 struct drm_i915_private *dev_priv = dev->dev_private;
3523 int pipe = intel_crtc->pipe;
3524 u32 reg, temp;
3525
3526
3527 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3528 reg = FDI_RX_CTL(pipe);
3529 temp = I915_READ(reg);
3530 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3531 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3532 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3533 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3534
3535 POSTING_READ(reg);
3536 udelay(200);
3537
3538 /* Switch from Rawclk to PCDclk */
3539 temp = I915_READ(reg);
3540 I915_WRITE(reg, temp | FDI_PCDCLK);
3541
3542 POSTING_READ(reg);
3543 udelay(200);
3544
3545 /* Enable CPU FDI TX PLL, always on for Ironlake */
3546 reg = FDI_TX_CTL(pipe);
3547 temp = I915_READ(reg);
3548 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3549 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3550
3551 POSTING_READ(reg);
3552 udelay(100);
3553 }
3554 }
3555
3556 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3557 {
3558 struct drm_device *dev = intel_crtc->base.dev;
3559 struct drm_i915_private *dev_priv = dev->dev_private;
3560 int pipe = intel_crtc->pipe;
3561 u32 reg, temp;
3562
3563 /* Switch from PCDclk to Rawclk */
3564 reg = FDI_RX_CTL(pipe);
3565 temp = I915_READ(reg);
3566 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3567
3568 /* Disable CPU FDI TX PLL */
3569 reg = FDI_TX_CTL(pipe);
3570 temp = I915_READ(reg);
3571 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3572
3573 POSTING_READ(reg);
3574 udelay(100);
3575
3576 reg = FDI_RX_CTL(pipe);
3577 temp = I915_READ(reg);
3578 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3579
3580 /* Wait for the clocks to turn off. */
3581 POSTING_READ(reg);
3582 udelay(100);
3583 }
3584
3585 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3586 {
3587 struct drm_device *dev = crtc->dev;
3588 struct drm_i915_private *dev_priv = dev->dev_private;
3589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3590 int pipe = intel_crtc->pipe;
3591 u32 reg, temp;
3592
3593 /* disable CPU FDI tx and PCH FDI rx */
3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
3596 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3597 POSTING_READ(reg);
3598
3599 reg = FDI_RX_CTL(pipe);
3600 temp = I915_READ(reg);
3601 temp &= ~(0x7 << 16);
3602 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3603 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3604
3605 POSTING_READ(reg);
3606 udelay(100);
3607
3608 /* Ironlake workaround, disable clock pointer after downing FDI */
3609 if (HAS_PCH_IBX(dev))
3610 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3611
3612 /* still set train pattern 1 */
3613 reg = FDI_TX_CTL(pipe);
3614 temp = I915_READ(reg);
3615 temp &= ~FDI_LINK_TRAIN_NONE;
3616 temp |= FDI_LINK_TRAIN_PATTERN_1;
3617 I915_WRITE(reg, temp);
3618
3619 reg = FDI_RX_CTL(pipe);
3620 temp = I915_READ(reg);
3621 if (HAS_PCH_CPT(dev)) {
3622 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3623 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3624 } else {
3625 temp &= ~FDI_LINK_TRAIN_NONE;
3626 temp |= FDI_LINK_TRAIN_PATTERN_1;
3627 }
3628 /* BPC in FDI rx is consistent with that in PIPECONF */
3629 temp &= ~(0x07 << 16);
3630 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3631 I915_WRITE(reg, temp);
3632
3633 POSTING_READ(reg);
3634 udelay(100);
3635 }
3636
3637 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3638 {
3639 struct intel_crtc *crtc;
3640
3641 /* Note that we don't need to be called with mode_config.lock here
3642 * as our list of CRTC objects is static for the lifetime of the
3643 * device and so cannot disappear as we iterate. Similarly, we can
3644 * happily treat the predicates as racy, atomic checks as userspace
3645 * cannot claim and pin a new fb without at least acquring the
3646 * struct_mutex and so serialising with us.
3647 */
3648 for_each_intel_crtc(dev, crtc) {
3649 if (atomic_read(&crtc->unpin_work_count) == 0)
3650 continue;
3651
3652 if (crtc->unpin_work)
3653 intel_wait_for_vblank(dev, crtc->pipe);
3654
3655 return true;
3656 }
3657
3658 return false;
3659 }
3660
3661 static void page_flip_completed(struct intel_crtc *intel_crtc)
3662 {
3663 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3664 struct intel_unpin_work *work = intel_crtc->unpin_work;
3665
3666 /* ensure that the unpin work is consistent wrt ->pending. */
3667 smp_rmb();
3668 intel_crtc->unpin_work = NULL;
3669
3670 if (work->event)
3671 drm_send_vblank_event(intel_crtc->base.dev,
3672 intel_crtc->pipe,
3673 work->event);
3674
3675 drm_crtc_vblank_put(&intel_crtc->base);
3676
3677 wake_up_all(&dev_priv->pending_flip_queue);
3678 queue_work(dev_priv->wq, &work->work);
3679
3680 trace_i915_flip_complete(intel_crtc->plane,
3681 work->pending_flip_obj);
3682 }
3683
3684 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3685 {
3686 struct drm_device *dev = crtc->dev;
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688
3689 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3690 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3691 !intel_crtc_has_pending_flip(crtc),
3692 60*HZ) == 0)) {
3693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3694
3695 spin_lock_irq(&dev->event_lock);
3696 if (intel_crtc->unpin_work) {
3697 WARN_ONCE(1, "Removing stuck page flip\n");
3698 page_flip_completed(intel_crtc);
3699 }
3700 spin_unlock_irq(&dev->event_lock);
3701 }
3702
3703 if (crtc->primary->fb) {
3704 mutex_lock(&dev->struct_mutex);
3705 intel_finish_fb(crtc->primary->fb);
3706 mutex_unlock(&dev->struct_mutex);
3707 }
3708 }
3709
3710 /* Program iCLKIP clock to the desired frequency */
3711 static void lpt_program_iclkip(struct drm_crtc *crtc)
3712 {
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3716 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3717 u32 temp;
3718
3719 mutex_lock(&dev_priv->dpio_lock);
3720
3721 /* It is necessary to ungate the pixclk gate prior to programming
3722 * the divisors, and gate it back when it is done.
3723 */
3724 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3725
3726 /* Disable SSCCTL */
3727 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3728 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3729 SBI_SSCCTL_DISABLE,
3730 SBI_ICLK);
3731
3732 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3733 if (clock == 20000) {
3734 auxdiv = 1;
3735 divsel = 0x41;
3736 phaseinc = 0x20;
3737 } else {
3738 /* The iCLK virtual clock root frequency is in MHz,
3739 * but the adjusted_mode->crtc_clock in in KHz. To get the
3740 * divisors, it is necessary to divide one by another, so we
3741 * convert the virtual clock precision to KHz here for higher
3742 * precision.
3743 */
3744 u32 iclk_virtual_root_freq = 172800 * 1000;
3745 u32 iclk_pi_range = 64;
3746 u32 desired_divisor, msb_divisor_value, pi_value;
3747
3748 desired_divisor = (iclk_virtual_root_freq / clock);
3749 msb_divisor_value = desired_divisor / iclk_pi_range;
3750 pi_value = desired_divisor % iclk_pi_range;
3751
3752 auxdiv = 0;
3753 divsel = msb_divisor_value - 2;
3754 phaseinc = pi_value;
3755 }
3756
3757 /* This should not happen with any sane values */
3758 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3759 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3760 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3761 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3762
3763 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3764 clock,
3765 auxdiv,
3766 divsel,
3767 phasedir,
3768 phaseinc);
3769
3770 /* Program SSCDIVINTPHASE6 */
3771 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3772 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3773 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3774 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3775 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3776 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3777 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3778 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3779
3780 /* Program SSCAUXDIV */
3781 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3782 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3783 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3784 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3785
3786 /* Enable modulator and associated divider */
3787 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3788 temp &= ~SBI_SSCCTL_DISABLE;
3789 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3790
3791 /* Wait for initialization time */
3792 udelay(24);
3793
3794 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3795
3796 mutex_unlock(&dev_priv->dpio_lock);
3797 }
3798
3799 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3800 enum pipe pch_transcoder)
3801 {
3802 struct drm_device *dev = crtc->base.dev;
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3805
3806 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3807 I915_READ(HTOTAL(cpu_transcoder)));
3808 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3809 I915_READ(HBLANK(cpu_transcoder)));
3810 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3811 I915_READ(HSYNC(cpu_transcoder)));
3812
3813 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3814 I915_READ(VTOTAL(cpu_transcoder)));
3815 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3816 I915_READ(VBLANK(cpu_transcoder)));
3817 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3818 I915_READ(VSYNC(cpu_transcoder)));
3819 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3820 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3821 }
3822
3823 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3824 {
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 uint32_t temp;
3827
3828 temp = I915_READ(SOUTH_CHICKEN1);
3829 if (temp & FDI_BC_BIFURCATION_SELECT)
3830 return;
3831
3832 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3833 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3834
3835 temp |= FDI_BC_BIFURCATION_SELECT;
3836 DRM_DEBUG_KMS("enabling fdi C rx\n");
3837 I915_WRITE(SOUTH_CHICKEN1, temp);
3838 POSTING_READ(SOUTH_CHICKEN1);
3839 }
3840
3841 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3842 {
3843 struct drm_device *dev = intel_crtc->base.dev;
3844 struct drm_i915_private *dev_priv = dev->dev_private;
3845
3846 switch (intel_crtc->pipe) {
3847 case PIPE_A:
3848 break;
3849 case PIPE_B:
3850 if (intel_crtc->config->fdi_lanes > 2)
3851 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3852 else
3853 cpt_enable_fdi_bc_bifurcation(dev);
3854
3855 break;
3856 case PIPE_C:
3857 cpt_enable_fdi_bc_bifurcation(dev);
3858
3859 break;
3860 default:
3861 BUG();
3862 }
3863 }
3864
3865 /*
3866 * Enable PCH resources required for PCH ports:
3867 * - PCH PLLs
3868 * - FDI training & RX/TX
3869 * - update transcoder timings
3870 * - DP transcoding bits
3871 * - transcoder
3872 */
3873 static void ironlake_pch_enable(struct drm_crtc *crtc)
3874 {
3875 struct drm_device *dev = crtc->dev;
3876 struct drm_i915_private *dev_priv = dev->dev_private;
3877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3878 int pipe = intel_crtc->pipe;
3879 u32 reg, temp;
3880
3881 assert_pch_transcoder_disabled(dev_priv, pipe);
3882
3883 if (IS_IVYBRIDGE(dev))
3884 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3885
3886 /* Write the TU size bits before fdi link training, so that error
3887 * detection works. */
3888 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3889 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3890
3891 /* For PCH output, training FDI link */
3892 dev_priv->display.fdi_link_train(crtc);
3893
3894 /* We need to program the right clock selection before writing the pixel
3895 * mutliplier into the DPLL. */
3896 if (HAS_PCH_CPT(dev)) {
3897 u32 sel;
3898
3899 temp = I915_READ(PCH_DPLL_SEL);
3900 temp |= TRANS_DPLL_ENABLE(pipe);
3901 sel = TRANS_DPLLB_SEL(pipe);
3902 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3903 temp |= sel;
3904 else
3905 temp &= ~sel;
3906 I915_WRITE(PCH_DPLL_SEL, temp);
3907 }
3908
3909 /* XXX: pch pll's can be enabled any time before we enable the PCH
3910 * transcoder, and we actually should do this to not upset any PCH
3911 * transcoder that already use the clock when we share it.
3912 *
3913 * Note that enable_shared_dpll tries to do the right thing, but
3914 * get_shared_dpll unconditionally resets the pll - we need that to have
3915 * the right LVDS enable sequence. */
3916 intel_enable_shared_dpll(intel_crtc);
3917
3918 /* set transcoder timing, panel must allow it */
3919 assert_panel_unlocked(dev_priv, pipe);
3920 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3921
3922 intel_fdi_normal_train(crtc);
3923
3924 /* For PCH DP, enable TRANS_DP_CTL */
3925 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3926 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3927 reg = TRANS_DP_CTL(pipe);
3928 temp = I915_READ(reg);
3929 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3930 TRANS_DP_SYNC_MASK |
3931 TRANS_DP_BPC_MASK);
3932 temp |= (TRANS_DP_OUTPUT_ENABLE |
3933 TRANS_DP_ENH_FRAMING);
3934 temp |= bpc << 9; /* same format but at 11:9 */
3935
3936 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3937 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3938 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3939 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3940
3941 switch (intel_trans_dp_port_sel(crtc)) {
3942 case PCH_DP_B:
3943 temp |= TRANS_DP_PORT_SEL_B;
3944 break;
3945 case PCH_DP_C:
3946 temp |= TRANS_DP_PORT_SEL_C;
3947 break;
3948 case PCH_DP_D:
3949 temp |= TRANS_DP_PORT_SEL_D;
3950 break;
3951 default:
3952 BUG();
3953 }
3954
3955 I915_WRITE(reg, temp);
3956 }
3957
3958 ironlake_enable_pch_transcoder(dev_priv, pipe);
3959 }
3960
3961 static void lpt_pch_enable(struct drm_crtc *crtc)
3962 {
3963 struct drm_device *dev = crtc->dev;
3964 struct drm_i915_private *dev_priv = dev->dev_private;
3965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3966 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3967
3968 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3969
3970 lpt_program_iclkip(crtc);
3971
3972 /* Set transcoder timing. */
3973 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3974
3975 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3976 }
3977
3978 void intel_put_shared_dpll(struct intel_crtc *crtc)
3979 {
3980 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3981
3982 if (pll == NULL)
3983 return;
3984
3985 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3986 WARN(1, "bad %s crtc mask\n", pll->name);
3987 return;
3988 }
3989
3990 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3991 if (pll->config.crtc_mask == 0) {
3992 WARN_ON(pll->on);
3993 WARN_ON(pll->active);
3994 }
3995
3996 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3997 }
3998
3999 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4000 struct intel_crtc_state *crtc_state)
4001 {
4002 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4003 struct intel_shared_dpll *pll;
4004 enum intel_dpll_id i;
4005
4006 if (HAS_PCH_IBX(dev_priv->dev)) {
4007 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4008 i = (enum intel_dpll_id) crtc->pipe;
4009 pll = &dev_priv->shared_dplls[i];
4010
4011 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4012 crtc->base.base.id, pll->name);
4013
4014 WARN_ON(pll->new_config->crtc_mask);
4015
4016 goto found;
4017 }
4018
4019 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4020 pll = &dev_priv->shared_dplls[i];
4021
4022 /* Only want to check enabled timings first */
4023 if (pll->new_config->crtc_mask == 0)
4024 continue;
4025
4026 if (memcmp(&crtc_state->dpll_hw_state,
4027 &pll->new_config->hw_state,
4028 sizeof(pll->new_config->hw_state)) == 0) {
4029 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4030 crtc->base.base.id, pll->name,
4031 pll->new_config->crtc_mask,
4032 pll->active);
4033 goto found;
4034 }
4035 }
4036
4037 /* Ok no matching timings, maybe there's a free one? */
4038 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4039 pll = &dev_priv->shared_dplls[i];
4040 if (pll->new_config->crtc_mask == 0) {
4041 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4042 crtc->base.base.id, pll->name);
4043 goto found;
4044 }
4045 }
4046
4047 return NULL;
4048
4049 found:
4050 if (pll->new_config->crtc_mask == 0)
4051 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4052
4053 crtc_state->shared_dpll = i;
4054 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4055 pipe_name(crtc->pipe));
4056
4057 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4058
4059 return pll;
4060 }
4061
4062 /**
4063 * intel_shared_dpll_start_config - start a new PLL staged config
4064 * @dev_priv: DRM device
4065 * @clear_pipes: mask of pipes that will have their PLLs freed
4066 *
4067 * Starts a new PLL staged config, copying the current config but
4068 * releasing the references of pipes specified in clear_pipes.
4069 */
4070 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4071 unsigned clear_pipes)
4072 {
4073 struct intel_shared_dpll *pll;
4074 enum intel_dpll_id i;
4075
4076 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4077 pll = &dev_priv->shared_dplls[i];
4078
4079 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4080 GFP_KERNEL);
4081 if (!pll->new_config)
4082 goto cleanup;
4083
4084 pll->new_config->crtc_mask &= ~clear_pipes;
4085 }
4086
4087 return 0;
4088
4089 cleanup:
4090 while (--i >= 0) {
4091 pll = &dev_priv->shared_dplls[i];
4092 kfree(pll->new_config);
4093 pll->new_config = NULL;
4094 }
4095
4096 return -ENOMEM;
4097 }
4098
4099 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4100 {
4101 struct intel_shared_dpll *pll;
4102 enum intel_dpll_id i;
4103
4104 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4105 pll = &dev_priv->shared_dplls[i];
4106
4107 WARN_ON(pll->new_config == &pll->config);
4108
4109 pll->config = *pll->new_config;
4110 kfree(pll->new_config);
4111 pll->new_config = NULL;
4112 }
4113 }
4114
4115 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4116 {
4117 struct intel_shared_dpll *pll;
4118 enum intel_dpll_id i;
4119
4120 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4121 pll = &dev_priv->shared_dplls[i];
4122
4123 WARN_ON(pll->new_config == &pll->config);
4124
4125 kfree(pll->new_config);
4126 pll->new_config = NULL;
4127 }
4128 }
4129
4130 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4131 {
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 int dslreg = PIPEDSL(pipe);
4134 u32 temp;
4135
4136 temp = I915_READ(dslreg);
4137 udelay(500);
4138 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4139 if (wait_for(I915_READ(dslreg) != temp, 5))
4140 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4141 }
4142 }
4143
4144 static void skylake_pfit_enable(struct intel_crtc *crtc)
4145 {
4146 struct drm_device *dev = crtc->base.dev;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int pipe = crtc->pipe;
4149
4150 if (crtc->config->pch_pfit.enabled) {
4151 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4152 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4153 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4154 }
4155 }
4156
4157 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4158 {
4159 struct drm_device *dev = crtc->base.dev;
4160 struct drm_i915_private *dev_priv = dev->dev_private;
4161 int pipe = crtc->pipe;
4162
4163 if (crtc->config->pch_pfit.enabled) {
4164 /* Force use of hard-coded filter coefficients
4165 * as some pre-programmed values are broken,
4166 * e.g. x201.
4167 */
4168 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4169 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4170 PF_PIPE_SEL_IVB(pipe));
4171 else
4172 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4173 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4174 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4175 }
4176 }
4177
4178 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4179 {
4180 struct drm_device *dev = crtc->dev;
4181 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4182 struct drm_plane *plane;
4183 struct intel_plane *intel_plane;
4184
4185 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4186 intel_plane = to_intel_plane(plane);
4187 if (intel_plane->pipe == pipe)
4188 intel_plane_restore(&intel_plane->base);
4189 }
4190 }
4191
4192 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4193 {
4194 struct drm_device *dev = crtc->dev;
4195 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4196 struct drm_plane *plane;
4197 struct intel_plane *intel_plane;
4198
4199 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4200 intel_plane = to_intel_plane(plane);
4201 if (intel_plane->pipe == pipe)
4202 plane->funcs->disable_plane(plane);
4203 }
4204 }
4205
4206 void hsw_enable_ips(struct intel_crtc *crtc)
4207 {
4208 struct drm_device *dev = crtc->base.dev;
4209 struct drm_i915_private *dev_priv = dev->dev_private;
4210
4211 if (!crtc->config->ips_enabled)
4212 return;
4213
4214 /* We can only enable IPS after we enable a plane and wait for a vblank */
4215 intel_wait_for_vblank(dev, crtc->pipe);
4216
4217 assert_plane_enabled(dev_priv, crtc->plane);
4218 if (IS_BROADWELL(dev)) {
4219 mutex_lock(&dev_priv->rps.hw_lock);
4220 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4221 mutex_unlock(&dev_priv->rps.hw_lock);
4222 /* Quoting Art Runyan: "its not safe to expect any particular
4223 * value in IPS_CTL bit 31 after enabling IPS through the
4224 * mailbox." Moreover, the mailbox may return a bogus state,
4225 * so we need to just enable it and continue on.
4226 */
4227 } else {
4228 I915_WRITE(IPS_CTL, IPS_ENABLE);
4229 /* The bit only becomes 1 in the next vblank, so this wait here
4230 * is essentially intel_wait_for_vblank. If we don't have this
4231 * and don't wait for vblanks until the end of crtc_enable, then
4232 * the HW state readout code will complain that the expected
4233 * IPS_CTL value is not the one we read. */
4234 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4235 DRM_ERROR("Timed out waiting for IPS enable\n");
4236 }
4237 }
4238
4239 void hsw_disable_ips(struct intel_crtc *crtc)
4240 {
4241 struct drm_device *dev = crtc->base.dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243
4244 if (!crtc->config->ips_enabled)
4245 return;
4246
4247 assert_plane_enabled(dev_priv, crtc->plane);
4248 if (IS_BROADWELL(dev)) {
4249 mutex_lock(&dev_priv->rps.hw_lock);
4250 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4251 mutex_unlock(&dev_priv->rps.hw_lock);
4252 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4253 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4254 DRM_ERROR("Timed out waiting for IPS disable\n");
4255 } else {
4256 I915_WRITE(IPS_CTL, 0);
4257 POSTING_READ(IPS_CTL);
4258 }
4259
4260 /* We need to wait for a vblank before we can disable the plane. */
4261 intel_wait_for_vblank(dev, crtc->pipe);
4262 }
4263
4264 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4265 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4266 {
4267 struct drm_device *dev = crtc->dev;
4268 struct drm_i915_private *dev_priv = dev->dev_private;
4269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4270 enum pipe pipe = intel_crtc->pipe;
4271 int palreg = PALETTE(pipe);
4272 int i;
4273 bool reenable_ips = false;
4274
4275 /* The clocks have to be on to load the palette. */
4276 if (!crtc->state->enable || !intel_crtc->active)
4277 return;
4278
4279 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4280 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4281 assert_dsi_pll_enabled(dev_priv);
4282 else
4283 assert_pll_enabled(dev_priv, pipe);
4284 }
4285
4286 /* use legacy palette for Ironlake */
4287 if (!HAS_GMCH_DISPLAY(dev))
4288 palreg = LGC_PALETTE(pipe);
4289
4290 /* Workaround : Do not read or write the pipe palette/gamma data while
4291 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4292 */
4293 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4294 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4295 GAMMA_MODE_MODE_SPLIT)) {
4296 hsw_disable_ips(intel_crtc);
4297 reenable_ips = true;
4298 }
4299
4300 for (i = 0; i < 256; i++) {
4301 I915_WRITE(palreg + 4 * i,
4302 (intel_crtc->lut_r[i] << 16) |
4303 (intel_crtc->lut_g[i] << 8) |
4304 intel_crtc->lut_b[i]);
4305 }
4306
4307 if (reenable_ips)
4308 hsw_enable_ips(intel_crtc);
4309 }
4310
4311 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4312 {
4313 if (!enable && intel_crtc->overlay) {
4314 struct drm_device *dev = intel_crtc->base.dev;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316
4317 mutex_lock(&dev->struct_mutex);
4318 dev_priv->mm.interruptible = false;
4319 (void) intel_overlay_switch_off(intel_crtc->overlay);
4320 dev_priv->mm.interruptible = true;
4321 mutex_unlock(&dev->struct_mutex);
4322 }
4323
4324 /* Let userspace switch the overlay on again. In most cases userspace
4325 * has to recompute where to put it anyway.
4326 */
4327 }
4328
4329 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4330 {
4331 struct drm_device *dev = crtc->dev;
4332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4333 int pipe = intel_crtc->pipe;
4334
4335 intel_enable_primary_hw_plane(crtc->primary, crtc);
4336 intel_enable_sprite_planes(crtc);
4337 intel_crtc_update_cursor(crtc, true);
4338 intel_crtc_dpms_overlay(intel_crtc, true);
4339
4340 hsw_enable_ips(intel_crtc);
4341
4342 mutex_lock(&dev->struct_mutex);
4343 intel_fbc_update(dev);
4344 mutex_unlock(&dev->struct_mutex);
4345
4346 /*
4347 * FIXME: Once we grow proper nuclear flip support out of this we need
4348 * to compute the mask of flip planes precisely. For the time being
4349 * consider this a flip from a NULL plane.
4350 */
4351 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4352 }
4353
4354 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4355 {
4356 struct drm_device *dev = crtc->dev;
4357 struct drm_i915_private *dev_priv = dev->dev_private;
4358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4359 int pipe = intel_crtc->pipe;
4360
4361 intel_crtc_wait_for_pending_flips(crtc);
4362
4363 if (dev_priv->fbc.crtc == intel_crtc)
4364 intel_fbc_disable(dev);
4365
4366 hsw_disable_ips(intel_crtc);
4367
4368 intel_crtc_dpms_overlay(intel_crtc, false);
4369 intel_crtc_update_cursor(crtc, false);
4370 intel_disable_sprite_planes(crtc);
4371 intel_disable_primary_hw_plane(crtc->primary, crtc);
4372
4373 /*
4374 * FIXME: Once we grow proper nuclear flip support out of this we need
4375 * to compute the mask of flip planes precisely. For the time being
4376 * consider this a flip to a NULL plane.
4377 */
4378 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4379 }
4380
4381 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4382 {
4383 struct drm_device *dev = crtc->dev;
4384 struct drm_i915_private *dev_priv = dev->dev_private;
4385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4386 struct intel_encoder *encoder;
4387 int pipe = intel_crtc->pipe;
4388
4389 WARN_ON(!crtc->state->enable);
4390
4391 if (intel_crtc->active)
4392 return;
4393
4394 if (intel_crtc->config->has_pch_encoder)
4395 intel_prepare_shared_dpll(intel_crtc);
4396
4397 if (intel_crtc->config->has_dp_encoder)
4398 intel_dp_set_m_n(intel_crtc, M1_N1);
4399
4400 intel_set_pipe_timings(intel_crtc);
4401
4402 if (intel_crtc->config->has_pch_encoder) {
4403 intel_cpu_transcoder_set_m_n(intel_crtc,
4404 &intel_crtc->config->fdi_m_n, NULL);
4405 }
4406
4407 ironlake_set_pipeconf(crtc);
4408
4409 intel_crtc->active = true;
4410
4411 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4412 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4413
4414 for_each_encoder_on_crtc(dev, crtc, encoder)
4415 if (encoder->pre_enable)
4416 encoder->pre_enable(encoder);
4417
4418 if (intel_crtc->config->has_pch_encoder) {
4419 /* Note: FDI PLL enabling _must_ be done before we enable the
4420 * cpu pipes, hence this is separate from all the other fdi/pch
4421 * enabling. */
4422 ironlake_fdi_pll_enable(intel_crtc);
4423 } else {
4424 assert_fdi_tx_disabled(dev_priv, pipe);
4425 assert_fdi_rx_disabled(dev_priv, pipe);
4426 }
4427
4428 ironlake_pfit_enable(intel_crtc);
4429
4430 /*
4431 * On ILK+ LUT must be loaded before the pipe is running but with
4432 * clocks enabled
4433 */
4434 intel_crtc_load_lut(crtc);
4435
4436 intel_update_watermarks(crtc);
4437 intel_enable_pipe(intel_crtc);
4438
4439 if (intel_crtc->config->has_pch_encoder)
4440 ironlake_pch_enable(crtc);
4441
4442 assert_vblank_disabled(crtc);
4443 drm_crtc_vblank_on(crtc);
4444
4445 for_each_encoder_on_crtc(dev, crtc, encoder)
4446 encoder->enable(encoder);
4447
4448 if (HAS_PCH_CPT(dev))
4449 cpt_verify_modeset(dev, intel_crtc->pipe);
4450
4451 intel_crtc_enable_planes(crtc);
4452 }
4453
4454 /* IPS only exists on ULT machines and is tied to pipe A. */
4455 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4456 {
4457 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4458 }
4459
4460 /*
4461 * This implements the workaround described in the "notes" section of the mode
4462 * set sequence documentation. When going from no pipes or single pipe to
4463 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4464 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4465 */
4466 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4467 {
4468 struct drm_device *dev = crtc->base.dev;
4469 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4470
4471 /* We want to get the other_active_crtc only if there's only 1 other
4472 * active crtc. */
4473 for_each_intel_crtc(dev, crtc_it) {
4474 if (!crtc_it->active || crtc_it == crtc)
4475 continue;
4476
4477 if (other_active_crtc)
4478 return;
4479
4480 other_active_crtc = crtc_it;
4481 }
4482 if (!other_active_crtc)
4483 return;
4484
4485 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4486 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4487 }
4488
4489 static void haswell_crtc_enable(struct drm_crtc *crtc)
4490 {
4491 struct drm_device *dev = crtc->dev;
4492 struct drm_i915_private *dev_priv = dev->dev_private;
4493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4494 struct intel_encoder *encoder;
4495 int pipe = intel_crtc->pipe;
4496
4497 WARN_ON(!crtc->state->enable);
4498
4499 if (intel_crtc->active)
4500 return;
4501
4502 if (intel_crtc_to_shared_dpll(intel_crtc))
4503 intel_enable_shared_dpll(intel_crtc);
4504
4505 if (intel_crtc->config->has_dp_encoder)
4506 intel_dp_set_m_n(intel_crtc, M1_N1);
4507
4508 intel_set_pipe_timings(intel_crtc);
4509
4510 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4511 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4512 intel_crtc->config->pixel_multiplier - 1);
4513 }
4514
4515 if (intel_crtc->config->has_pch_encoder) {
4516 intel_cpu_transcoder_set_m_n(intel_crtc,
4517 &intel_crtc->config->fdi_m_n, NULL);
4518 }
4519
4520 haswell_set_pipeconf(crtc);
4521
4522 intel_set_pipe_csc(crtc);
4523
4524 intel_crtc->active = true;
4525
4526 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4527 for_each_encoder_on_crtc(dev, crtc, encoder)
4528 if (encoder->pre_enable)
4529 encoder->pre_enable(encoder);
4530
4531 if (intel_crtc->config->has_pch_encoder) {
4532 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4533 true);
4534 dev_priv->display.fdi_link_train(crtc);
4535 }
4536
4537 intel_ddi_enable_pipe_clock(intel_crtc);
4538
4539 if (IS_SKYLAKE(dev))
4540 skylake_pfit_enable(intel_crtc);
4541 else
4542 ironlake_pfit_enable(intel_crtc);
4543
4544 /*
4545 * On ILK+ LUT must be loaded before the pipe is running but with
4546 * clocks enabled
4547 */
4548 intel_crtc_load_lut(crtc);
4549
4550 intel_ddi_set_pipe_settings(crtc);
4551 intel_ddi_enable_transcoder_func(crtc);
4552
4553 intel_update_watermarks(crtc);
4554 intel_enable_pipe(intel_crtc);
4555
4556 if (intel_crtc->config->has_pch_encoder)
4557 lpt_pch_enable(crtc);
4558
4559 if (intel_crtc->config->dp_encoder_is_mst)
4560 intel_ddi_set_vc_payload_alloc(crtc, true);
4561
4562 assert_vblank_disabled(crtc);
4563 drm_crtc_vblank_on(crtc);
4564
4565 for_each_encoder_on_crtc(dev, crtc, encoder) {
4566 encoder->enable(encoder);
4567 intel_opregion_notify_encoder(encoder, true);
4568 }
4569
4570 /* If we change the relative order between pipe/planes enabling, we need
4571 * to change the workaround. */
4572 haswell_mode_set_planes_workaround(intel_crtc);
4573 intel_crtc_enable_planes(crtc);
4574 }
4575
4576 static void skylake_pfit_disable(struct intel_crtc *crtc)
4577 {
4578 struct drm_device *dev = crtc->base.dev;
4579 struct drm_i915_private *dev_priv = dev->dev_private;
4580 int pipe = crtc->pipe;
4581
4582 /* To avoid upsetting the power well on haswell only disable the pfit if
4583 * it's in use. The hw state code will make sure we get this right. */
4584 if (crtc->config->pch_pfit.enabled) {
4585 I915_WRITE(PS_CTL(pipe), 0);
4586 I915_WRITE(PS_WIN_POS(pipe), 0);
4587 I915_WRITE(PS_WIN_SZ(pipe), 0);
4588 }
4589 }
4590
4591 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4592 {
4593 struct drm_device *dev = crtc->base.dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 int pipe = crtc->pipe;
4596
4597 /* To avoid upsetting the power well on haswell only disable the pfit if
4598 * it's in use. The hw state code will make sure we get this right. */
4599 if (crtc->config->pch_pfit.enabled) {
4600 I915_WRITE(PF_CTL(pipe), 0);
4601 I915_WRITE(PF_WIN_POS(pipe), 0);
4602 I915_WRITE(PF_WIN_SZ(pipe), 0);
4603 }
4604 }
4605
4606 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4607 {
4608 struct drm_device *dev = crtc->dev;
4609 struct drm_i915_private *dev_priv = dev->dev_private;
4610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4611 struct intel_encoder *encoder;
4612 int pipe = intel_crtc->pipe;
4613 u32 reg, temp;
4614
4615 if (!intel_crtc->active)
4616 return;
4617
4618 intel_crtc_disable_planes(crtc);
4619
4620 for_each_encoder_on_crtc(dev, crtc, encoder)
4621 encoder->disable(encoder);
4622
4623 drm_crtc_vblank_off(crtc);
4624 assert_vblank_disabled(crtc);
4625
4626 if (intel_crtc->config->has_pch_encoder)
4627 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4628
4629 intel_disable_pipe(intel_crtc);
4630
4631 ironlake_pfit_disable(intel_crtc);
4632
4633 for_each_encoder_on_crtc(dev, crtc, encoder)
4634 if (encoder->post_disable)
4635 encoder->post_disable(encoder);
4636
4637 if (intel_crtc->config->has_pch_encoder) {
4638 ironlake_fdi_disable(crtc);
4639
4640 ironlake_disable_pch_transcoder(dev_priv, pipe);
4641
4642 if (HAS_PCH_CPT(dev)) {
4643 /* disable TRANS_DP_CTL */
4644 reg = TRANS_DP_CTL(pipe);
4645 temp = I915_READ(reg);
4646 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4647 TRANS_DP_PORT_SEL_MASK);
4648 temp |= TRANS_DP_PORT_SEL_NONE;
4649 I915_WRITE(reg, temp);
4650
4651 /* disable DPLL_SEL */
4652 temp = I915_READ(PCH_DPLL_SEL);
4653 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4654 I915_WRITE(PCH_DPLL_SEL, temp);
4655 }
4656
4657 /* disable PCH DPLL */
4658 intel_disable_shared_dpll(intel_crtc);
4659
4660 ironlake_fdi_pll_disable(intel_crtc);
4661 }
4662
4663 intel_crtc->active = false;
4664 intel_update_watermarks(crtc);
4665
4666 mutex_lock(&dev->struct_mutex);
4667 intel_fbc_update(dev);
4668 mutex_unlock(&dev->struct_mutex);
4669 }
4670
4671 static void haswell_crtc_disable(struct drm_crtc *crtc)
4672 {
4673 struct drm_device *dev = crtc->dev;
4674 struct drm_i915_private *dev_priv = dev->dev_private;
4675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4676 struct intel_encoder *encoder;
4677 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4678
4679 if (!intel_crtc->active)
4680 return;
4681
4682 intel_crtc_disable_planes(crtc);
4683
4684 for_each_encoder_on_crtc(dev, crtc, encoder) {
4685 intel_opregion_notify_encoder(encoder, false);
4686 encoder->disable(encoder);
4687 }
4688
4689 drm_crtc_vblank_off(crtc);
4690 assert_vblank_disabled(crtc);
4691
4692 if (intel_crtc->config->has_pch_encoder)
4693 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4694 false);
4695 intel_disable_pipe(intel_crtc);
4696
4697 if (intel_crtc->config->dp_encoder_is_mst)
4698 intel_ddi_set_vc_payload_alloc(crtc, false);
4699
4700 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4701
4702 if (IS_SKYLAKE(dev))
4703 skylake_pfit_disable(intel_crtc);
4704 else
4705 ironlake_pfit_disable(intel_crtc);
4706
4707 intel_ddi_disable_pipe_clock(intel_crtc);
4708
4709 if (intel_crtc->config->has_pch_encoder) {
4710 lpt_disable_pch_transcoder(dev_priv);
4711 intel_ddi_fdi_disable(crtc);
4712 }
4713
4714 for_each_encoder_on_crtc(dev, crtc, encoder)
4715 if (encoder->post_disable)
4716 encoder->post_disable(encoder);
4717
4718 intel_crtc->active = false;
4719 intel_update_watermarks(crtc);
4720
4721 mutex_lock(&dev->struct_mutex);
4722 intel_fbc_update(dev);
4723 mutex_unlock(&dev->struct_mutex);
4724
4725 if (intel_crtc_to_shared_dpll(intel_crtc))
4726 intel_disable_shared_dpll(intel_crtc);
4727 }
4728
4729 static void ironlake_crtc_off(struct drm_crtc *crtc)
4730 {
4731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4732 intel_put_shared_dpll(intel_crtc);
4733 }
4734
4735
4736 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4737 {
4738 struct drm_device *dev = crtc->base.dev;
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740 struct intel_crtc_state *pipe_config = crtc->config;
4741
4742 if (!pipe_config->gmch_pfit.control)
4743 return;
4744
4745 /*
4746 * The panel fitter should only be adjusted whilst the pipe is disabled,
4747 * according to register description and PRM.
4748 */
4749 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4750 assert_pipe_disabled(dev_priv, crtc->pipe);
4751
4752 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4753 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4754
4755 /* Border color in case we don't scale up to the full screen. Black by
4756 * default, change to something else for debugging. */
4757 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4758 }
4759
4760 static enum intel_display_power_domain port_to_power_domain(enum port port)
4761 {
4762 switch (port) {
4763 case PORT_A:
4764 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4765 case PORT_B:
4766 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4767 case PORT_C:
4768 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4769 case PORT_D:
4770 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4771 default:
4772 WARN_ON_ONCE(1);
4773 return POWER_DOMAIN_PORT_OTHER;
4774 }
4775 }
4776
4777 #define for_each_power_domain(domain, mask) \
4778 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4779 if ((1 << (domain)) & (mask))
4780
4781 enum intel_display_power_domain
4782 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4783 {
4784 struct drm_device *dev = intel_encoder->base.dev;
4785 struct intel_digital_port *intel_dig_port;
4786
4787 switch (intel_encoder->type) {
4788 case INTEL_OUTPUT_UNKNOWN:
4789 /* Only DDI platforms should ever use this output type */
4790 WARN_ON_ONCE(!HAS_DDI(dev));
4791 case INTEL_OUTPUT_DISPLAYPORT:
4792 case INTEL_OUTPUT_HDMI:
4793 case INTEL_OUTPUT_EDP:
4794 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4795 return port_to_power_domain(intel_dig_port->port);
4796 case INTEL_OUTPUT_DP_MST:
4797 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4798 return port_to_power_domain(intel_dig_port->port);
4799 case INTEL_OUTPUT_ANALOG:
4800 return POWER_DOMAIN_PORT_CRT;
4801 case INTEL_OUTPUT_DSI:
4802 return POWER_DOMAIN_PORT_DSI;
4803 default:
4804 return POWER_DOMAIN_PORT_OTHER;
4805 }
4806 }
4807
4808 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4809 {
4810 struct drm_device *dev = crtc->dev;
4811 struct intel_encoder *intel_encoder;
4812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4813 enum pipe pipe = intel_crtc->pipe;
4814 unsigned long mask;
4815 enum transcoder transcoder;
4816
4817 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4818
4819 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4820 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4821 if (intel_crtc->config->pch_pfit.enabled ||
4822 intel_crtc->config->pch_pfit.force_thru)
4823 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4824
4825 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4826 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4827
4828 return mask;
4829 }
4830
4831 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4832 {
4833 struct drm_i915_private *dev_priv = dev->dev_private;
4834 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4835 struct intel_crtc *crtc;
4836
4837 /*
4838 * First get all needed power domains, then put all unneeded, to avoid
4839 * any unnecessary toggling of the power wells.
4840 */
4841 for_each_intel_crtc(dev, crtc) {
4842 enum intel_display_power_domain domain;
4843
4844 if (!crtc->base.state->enable)
4845 continue;
4846
4847 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4848
4849 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4850 intel_display_power_get(dev_priv, domain);
4851 }
4852
4853 if (dev_priv->display.modeset_global_resources)
4854 dev_priv->display.modeset_global_resources(dev);
4855
4856 for_each_intel_crtc(dev, crtc) {
4857 enum intel_display_power_domain domain;
4858
4859 for_each_power_domain(domain, crtc->enabled_power_domains)
4860 intel_display_power_put(dev_priv, domain);
4861
4862 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4863 }
4864
4865 intel_display_set_init_power(dev_priv, false);
4866 }
4867
4868 /* returns HPLL frequency in kHz */
4869 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4870 {
4871 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4872
4873 /* Obtain SKU information */
4874 mutex_lock(&dev_priv->dpio_lock);
4875 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4876 CCK_FUSE_HPLL_FREQ_MASK;
4877 mutex_unlock(&dev_priv->dpio_lock);
4878
4879 return vco_freq[hpll_freq] * 1000;
4880 }
4881
4882 static void vlv_update_cdclk(struct drm_device *dev)
4883 {
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885
4886 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4887 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4888 dev_priv->vlv_cdclk_freq);
4889
4890 /*
4891 * Program the gmbus_freq based on the cdclk frequency.
4892 * BSpec erroneously claims we should aim for 4MHz, but
4893 * in fact 1MHz is the correct frequency.
4894 */
4895 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4896 }
4897
4898 /* Adjust CDclk dividers to allow high res or save power if possible */
4899 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4900 {
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4902 u32 val, cmd;
4903
4904 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4905
4906 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4907 cmd = 2;
4908 else if (cdclk == 266667)
4909 cmd = 1;
4910 else
4911 cmd = 0;
4912
4913 mutex_lock(&dev_priv->rps.hw_lock);
4914 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4915 val &= ~DSPFREQGUAR_MASK;
4916 val |= (cmd << DSPFREQGUAR_SHIFT);
4917 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4918 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4919 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4920 50)) {
4921 DRM_ERROR("timed out waiting for CDclk change\n");
4922 }
4923 mutex_unlock(&dev_priv->rps.hw_lock);
4924
4925 if (cdclk == 400000) {
4926 u32 divider;
4927
4928 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4929
4930 mutex_lock(&dev_priv->dpio_lock);
4931 /* adjust cdclk divider */
4932 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4933 val &= ~DISPLAY_FREQUENCY_VALUES;
4934 val |= divider;
4935 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4936
4937 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4938 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4939 50))
4940 DRM_ERROR("timed out waiting for CDclk change\n");
4941 mutex_unlock(&dev_priv->dpio_lock);
4942 }
4943
4944 mutex_lock(&dev_priv->dpio_lock);
4945 /* adjust self-refresh exit latency value */
4946 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4947 val &= ~0x7f;
4948
4949 /*
4950 * For high bandwidth configs, we set a higher latency in the bunit
4951 * so that the core display fetch happens in time to avoid underruns.
4952 */
4953 if (cdclk == 400000)
4954 val |= 4500 / 250; /* 4.5 usec */
4955 else
4956 val |= 3000 / 250; /* 3.0 usec */
4957 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4958 mutex_unlock(&dev_priv->dpio_lock);
4959
4960 vlv_update_cdclk(dev);
4961 }
4962
4963 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4964 {
4965 struct drm_i915_private *dev_priv = dev->dev_private;
4966 u32 val, cmd;
4967
4968 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4969
4970 switch (cdclk) {
4971 case 400000:
4972 cmd = 3;
4973 break;
4974 case 333333:
4975 case 320000:
4976 cmd = 2;
4977 break;
4978 case 266667:
4979 cmd = 1;
4980 break;
4981 case 200000:
4982 cmd = 0;
4983 break;
4984 default:
4985 MISSING_CASE(cdclk);
4986 return;
4987 }
4988
4989 mutex_lock(&dev_priv->rps.hw_lock);
4990 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4991 val &= ~DSPFREQGUAR_MASK_CHV;
4992 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4993 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4994 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4995 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4996 50)) {
4997 DRM_ERROR("timed out waiting for CDclk change\n");
4998 }
4999 mutex_unlock(&dev_priv->rps.hw_lock);
5000
5001 vlv_update_cdclk(dev);
5002 }
5003
5004 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5005 int max_pixclk)
5006 {
5007 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5008
5009 /* FIXME: Punit isn't quite ready yet */
5010 if (IS_CHERRYVIEW(dev_priv->dev))
5011 return 400000;
5012
5013 /*
5014 * Really only a few cases to deal with, as only 4 CDclks are supported:
5015 * 200MHz
5016 * 267MHz
5017 * 320/333MHz (depends on HPLL freq)
5018 * 400MHz
5019 * So we check to see whether we're above 90% of the lower bin and
5020 * adjust if needed.
5021 *
5022 * We seem to get an unstable or solid color picture at 200MHz.
5023 * Not sure what's wrong. For now use 200MHz only when all pipes
5024 * are off.
5025 */
5026 if (max_pixclk > freq_320*9/10)
5027 return 400000;
5028 else if (max_pixclk > 266667*9/10)
5029 return freq_320;
5030 else if (max_pixclk > 0)
5031 return 266667;
5032 else
5033 return 200000;
5034 }
5035
5036 /* compute the max pixel clock for new configuration */
5037 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5038 {
5039 struct drm_device *dev = dev_priv->dev;
5040 struct intel_crtc *intel_crtc;
5041 int max_pixclk = 0;
5042
5043 for_each_intel_crtc(dev, intel_crtc) {
5044 if (intel_crtc->new_enabled)
5045 max_pixclk = max(max_pixclk,
5046 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5047 }
5048
5049 return max_pixclk;
5050 }
5051
5052 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5053 unsigned *prepare_pipes)
5054 {
5055 struct drm_i915_private *dev_priv = dev->dev_private;
5056 struct intel_crtc *intel_crtc;
5057 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5058
5059 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5060 dev_priv->vlv_cdclk_freq)
5061 return;
5062
5063 /* disable/enable all currently active pipes while we change cdclk */
5064 for_each_intel_crtc(dev, intel_crtc)
5065 if (intel_crtc->base.state->enable)
5066 *prepare_pipes |= (1 << intel_crtc->pipe);
5067 }
5068
5069 static void valleyview_modeset_global_resources(struct drm_device *dev)
5070 {
5071 struct drm_i915_private *dev_priv = dev->dev_private;
5072 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5073 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5074
5075 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5076 /*
5077 * FIXME: We can end up here with all power domains off, yet
5078 * with a CDCLK frequency other than the minimum. To account
5079 * for this take the PIPE-A power domain, which covers the HW
5080 * blocks needed for the following programming. This can be
5081 * removed once it's guaranteed that we get here either with
5082 * the minimum CDCLK set, or the required power domains
5083 * enabled.
5084 */
5085 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5086
5087 if (IS_CHERRYVIEW(dev))
5088 cherryview_set_cdclk(dev, req_cdclk);
5089 else
5090 valleyview_set_cdclk(dev, req_cdclk);
5091
5092 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5093 }
5094 }
5095
5096 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5097 {
5098 struct drm_device *dev = crtc->dev;
5099 struct drm_i915_private *dev_priv = to_i915(dev);
5100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5101 struct intel_encoder *encoder;
5102 int pipe = intel_crtc->pipe;
5103 bool is_dsi;
5104
5105 WARN_ON(!crtc->state->enable);
5106
5107 if (intel_crtc->active)
5108 return;
5109
5110 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5111
5112 if (!is_dsi) {
5113 if (IS_CHERRYVIEW(dev))
5114 chv_prepare_pll(intel_crtc, intel_crtc->config);
5115 else
5116 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5117 }
5118
5119 if (intel_crtc->config->has_dp_encoder)
5120 intel_dp_set_m_n(intel_crtc, M1_N1);
5121
5122 intel_set_pipe_timings(intel_crtc);
5123
5124 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5125 struct drm_i915_private *dev_priv = dev->dev_private;
5126
5127 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5128 I915_WRITE(CHV_CANVAS(pipe), 0);
5129 }
5130
5131 i9xx_set_pipeconf(intel_crtc);
5132
5133 intel_crtc->active = true;
5134
5135 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5136
5137 for_each_encoder_on_crtc(dev, crtc, encoder)
5138 if (encoder->pre_pll_enable)
5139 encoder->pre_pll_enable(encoder);
5140
5141 if (!is_dsi) {
5142 if (IS_CHERRYVIEW(dev))
5143 chv_enable_pll(intel_crtc, intel_crtc->config);
5144 else
5145 vlv_enable_pll(intel_crtc, intel_crtc->config);
5146 }
5147
5148 for_each_encoder_on_crtc(dev, crtc, encoder)
5149 if (encoder->pre_enable)
5150 encoder->pre_enable(encoder);
5151
5152 i9xx_pfit_enable(intel_crtc);
5153
5154 intel_crtc_load_lut(crtc);
5155
5156 intel_update_watermarks(crtc);
5157 intel_enable_pipe(intel_crtc);
5158
5159 assert_vblank_disabled(crtc);
5160 drm_crtc_vblank_on(crtc);
5161
5162 for_each_encoder_on_crtc(dev, crtc, encoder)
5163 encoder->enable(encoder);
5164
5165 intel_crtc_enable_planes(crtc);
5166
5167 /* Underruns don't raise interrupts, so check manually. */
5168 i9xx_check_fifo_underruns(dev_priv);
5169 }
5170
5171 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5172 {
5173 struct drm_device *dev = crtc->base.dev;
5174 struct drm_i915_private *dev_priv = dev->dev_private;
5175
5176 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5177 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5178 }
5179
5180 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5181 {
5182 struct drm_device *dev = crtc->dev;
5183 struct drm_i915_private *dev_priv = to_i915(dev);
5184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5185 struct intel_encoder *encoder;
5186 int pipe = intel_crtc->pipe;
5187
5188 WARN_ON(!crtc->state->enable);
5189
5190 if (intel_crtc->active)
5191 return;
5192
5193 i9xx_set_pll_dividers(intel_crtc);
5194
5195 if (intel_crtc->config->has_dp_encoder)
5196 intel_dp_set_m_n(intel_crtc, M1_N1);
5197
5198 intel_set_pipe_timings(intel_crtc);
5199
5200 i9xx_set_pipeconf(intel_crtc);
5201
5202 intel_crtc->active = true;
5203
5204 if (!IS_GEN2(dev))
5205 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5206
5207 for_each_encoder_on_crtc(dev, crtc, encoder)
5208 if (encoder->pre_enable)
5209 encoder->pre_enable(encoder);
5210
5211 i9xx_enable_pll(intel_crtc);
5212
5213 i9xx_pfit_enable(intel_crtc);
5214
5215 intel_crtc_load_lut(crtc);
5216
5217 intel_update_watermarks(crtc);
5218 intel_enable_pipe(intel_crtc);
5219
5220 assert_vblank_disabled(crtc);
5221 drm_crtc_vblank_on(crtc);
5222
5223 for_each_encoder_on_crtc(dev, crtc, encoder)
5224 encoder->enable(encoder);
5225
5226 intel_crtc_enable_planes(crtc);
5227
5228 /*
5229 * Gen2 reports pipe underruns whenever all planes are disabled.
5230 * So don't enable underrun reporting before at least some planes
5231 * are enabled.
5232 * FIXME: Need to fix the logic to work when we turn off all planes
5233 * but leave the pipe running.
5234 */
5235 if (IS_GEN2(dev))
5236 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5237
5238 /* Underruns don't raise interrupts, so check manually. */
5239 i9xx_check_fifo_underruns(dev_priv);
5240 }
5241
5242 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5243 {
5244 struct drm_device *dev = crtc->base.dev;
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246
5247 if (!crtc->config->gmch_pfit.control)
5248 return;
5249
5250 assert_pipe_disabled(dev_priv, crtc->pipe);
5251
5252 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5253 I915_READ(PFIT_CONTROL));
5254 I915_WRITE(PFIT_CONTROL, 0);
5255 }
5256
5257 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5258 {
5259 struct drm_device *dev = crtc->dev;
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5262 struct intel_encoder *encoder;
5263 int pipe = intel_crtc->pipe;
5264
5265 if (!intel_crtc->active)
5266 return;
5267
5268 /*
5269 * Gen2 reports pipe underruns whenever all planes are disabled.
5270 * So diasble underrun reporting before all the planes get disabled.
5271 * FIXME: Need to fix the logic to work when we turn off all planes
5272 * but leave the pipe running.
5273 */
5274 if (IS_GEN2(dev))
5275 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5276
5277 /*
5278 * Vblank time updates from the shadow to live plane control register
5279 * are blocked if the memory self-refresh mode is active at that
5280 * moment. So to make sure the plane gets truly disabled, disable
5281 * first the self-refresh mode. The self-refresh enable bit in turn
5282 * will be checked/applied by the HW only at the next frame start
5283 * event which is after the vblank start event, so we need to have a
5284 * wait-for-vblank between disabling the plane and the pipe.
5285 */
5286 intel_set_memory_cxsr(dev_priv, false);
5287 intel_crtc_disable_planes(crtc);
5288
5289 /*
5290 * On gen2 planes are double buffered but the pipe isn't, so we must
5291 * wait for planes to fully turn off before disabling the pipe.
5292 * We also need to wait on all gmch platforms because of the
5293 * self-refresh mode constraint explained above.
5294 */
5295 intel_wait_for_vblank(dev, pipe);
5296
5297 for_each_encoder_on_crtc(dev, crtc, encoder)
5298 encoder->disable(encoder);
5299
5300 drm_crtc_vblank_off(crtc);
5301 assert_vblank_disabled(crtc);
5302
5303 intel_disable_pipe(intel_crtc);
5304
5305 i9xx_pfit_disable(intel_crtc);
5306
5307 for_each_encoder_on_crtc(dev, crtc, encoder)
5308 if (encoder->post_disable)
5309 encoder->post_disable(encoder);
5310
5311 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5312 if (IS_CHERRYVIEW(dev))
5313 chv_disable_pll(dev_priv, pipe);
5314 else if (IS_VALLEYVIEW(dev))
5315 vlv_disable_pll(dev_priv, pipe);
5316 else
5317 i9xx_disable_pll(intel_crtc);
5318 }
5319
5320 if (!IS_GEN2(dev))
5321 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5322
5323 intel_crtc->active = false;
5324 intel_update_watermarks(crtc);
5325
5326 mutex_lock(&dev->struct_mutex);
5327 intel_fbc_update(dev);
5328 mutex_unlock(&dev->struct_mutex);
5329 }
5330
5331 static void i9xx_crtc_off(struct drm_crtc *crtc)
5332 {
5333 }
5334
5335 /* Master function to enable/disable CRTC and corresponding power wells */
5336 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5337 {
5338 struct drm_device *dev = crtc->dev;
5339 struct drm_i915_private *dev_priv = dev->dev_private;
5340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5341 enum intel_display_power_domain domain;
5342 unsigned long domains;
5343
5344 if (enable) {
5345 if (!intel_crtc->active) {
5346 domains = get_crtc_power_domains(crtc);
5347 for_each_power_domain(domain, domains)
5348 intel_display_power_get(dev_priv, domain);
5349 intel_crtc->enabled_power_domains = domains;
5350
5351 dev_priv->display.crtc_enable(crtc);
5352 }
5353 } else {
5354 if (intel_crtc->active) {
5355 dev_priv->display.crtc_disable(crtc);
5356
5357 domains = intel_crtc->enabled_power_domains;
5358 for_each_power_domain(domain, domains)
5359 intel_display_power_put(dev_priv, domain);
5360 intel_crtc->enabled_power_domains = 0;
5361 }
5362 }
5363 }
5364
5365 /**
5366 * Sets the power management mode of the pipe and plane.
5367 */
5368 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5369 {
5370 struct drm_device *dev = crtc->dev;
5371 struct intel_encoder *intel_encoder;
5372 bool enable = false;
5373
5374 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5375 enable |= intel_encoder->connectors_active;
5376
5377 intel_crtc_control(crtc, enable);
5378 }
5379
5380 static void intel_crtc_disable(struct drm_crtc *crtc)
5381 {
5382 struct drm_device *dev = crtc->dev;
5383 struct drm_connector *connector;
5384 struct drm_i915_private *dev_priv = dev->dev_private;
5385
5386 /* crtc should still be enabled when we disable it. */
5387 WARN_ON(!crtc->state->enable);
5388
5389 dev_priv->display.crtc_disable(crtc);
5390 dev_priv->display.off(crtc);
5391
5392 crtc->primary->funcs->disable_plane(crtc->primary);
5393
5394 /* Update computed state. */
5395 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5396 if (!connector->encoder || !connector->encoder->crtc)
5397 continue;
5398
5399 if (connector->encoder->crtc != crtc)
5400 continue;
5401
5402 connector->dpms = DRM_MODE_DPMS_OFF;
5403 to_intel_encoder(connector->encoder)->connectors_active = false;
5404 }
5405 }
5406
5407 void intel_encoder_destroy(struct drm_encoder *encoder)
5408 {
5409 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5410
5411 drm_encoder_cleanup(encoder);
5412 kfree(intel_encoder);
5413 }
5414
5415 /* Simple dpms helper for encoders with just one connector, no cloning and only
5416 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5417 * state of the entire output pipe. */
5418 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5419 {
5420 if (mode == DRM_MODE_DPMS_ON) {
5421 encoder->connectors_active = true;
5422
5423 intel_crtc_update_dpms(encoder->base.crtc);
5424 } else {
5425 encoder->connectors_active = false;
5426
5427 intel_crtc_update_dpms(encoder->base.crtc);
5428 }
5429 }
5430
5431 /* Cross check the actual hw state with our own modeset state tracking (and it's
5432 * internal consistency). */
5433 static void intel_connector_check_state(struct intel_connector *connector)
5434 {
5435 if (connector->get_hw_state(connector)) {
5436 struct intel_encoder *encoder = connector->encoder;
5437 struct drm_crtc *crtc;
5438 bool encoder_enabled;
5439 enum pipe pipe;
5440
5441 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5442 connector->base.base.id,
5443 connector->base.name);
5444
5445 /* there is no real hw state for MST connectors */
5446 if (connector->mst_port)
5447 return;
5448
5449 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5450 "wrong connector dpms state\n");
5451 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5452 "active connector not linked to encoder\n");
5453
5454 if (encoder) {
5455 I915_STATE_WARN(!encoder->connectors_active,
5456 "encoder->connectors_active not set\n");
5457
5458 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5459 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5460 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5461 return;
5462
5463 crtc = encoder->base.crtc;
5464
5465 I915_STATE_WARN(!crtc->state->enable,
5466 "crtc not enabled\n");
5467 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5468 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5469 "encoder active on the wrong pipe\n");
5470 }
5471 }
5472 }
5473
5474 /* Even simpler default implementation, if there's really no special case to
5475 * consider. */
5476 void intel_connector_dpms(struct drm_connector *connector, int mode)
5477 {
5478 /* All the simple cases only support two dpms states. */
5479 if (mode != DRM_MODE_DPMS_ON)
5480 mode = DRM_MODE_DPMS_OFF;
5481
5482 if (mode == connector->dpms)
5483 return;
5484
5485 connector->dpms = mode;
5486
5487 /* Only need to change hw state when actually enabled */
5488 if (connector->encoder)
5489 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5490
5491 intel_modeset_check_state(connector->dev);
5492 }
5493
5494 /* Simple connector->get_hw_state implementation for encoders that support only
5495 * one connector and no cloning and hence the encoder state determines the state
5496 * of the connector. */
5497 bool intel_connector_get_hw_state(struct intel_connector *connector)
5498 {
5499 enum pipe pipe = 0;
5500 struct intel_encoder *encoder = connector->encoder;
5501
5502 return encoder->get_hw_state(encoder, &pipe);
5503 }
5504
5505 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5506 struct intel_crtc_state *pipe_config)
5507 {
5508 struct drm_i915_private *dev_priv = dev->dev_private;
5509 struct intel_crtc *pipe_B_crtc =
5510 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5511
5512 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5513 pipe_name(pipe), pipe_config->fdi_lanes);
5514 if (pipe_config->fdi_lanes > 4) {
5515 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5516 pipe_name(pipe), pipe_config->fdi_lanes);
5517 return false;
5518 }
5519
5520 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5521 if (pipe_config->fdi_lanes > 2) {
5522 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5523 pipe_config->fdi_lanes);
5524 return false;
5525 } else {
5526 return true;
5527 }
5528 }
5529
5530 if (INTEL_INFO(dev)->num_pipes == 2)
5531 return true;
5532
5533 /* Ivybridge 3 pipe is really complicated */
5534 switch (pipe) {
5535 case PIPE_A:
5536 return true;
5537 case PIPE_B:
5538 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5539 pipe_config->fdi_lanes > 2) {
5540 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5541 pipe_name(pipe), pipe_config->fdi_lanes);
5542 return false;
5543 }
5544 return true;
5545 case PIPE_C:
5546 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5547 pipe_B_crtc->config->fdi_lanes <= 2) {
5548 if (pipe_config->fdi_lanes > 2) {
5549 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5550 pipe_name(pipe), pipe_config->fdi_lanes);
5551 return false;
5552 }
5553 } else {
5554 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5555 return false;
5556 }
5557 return true;
5558 default:
5559 BUG();
5560 }
5561 }
5562
5563 #define RETRY 1
5564 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5565 struct intel_crtc_state *pipe_config)
5566 {
5567 struct drm_device *dev = intel_crtc->base.dev;
5568 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5569 int lane, link_bw, fdi_dotclock;
5570 bool setup_ok, needs_recompute = false;
5571
5572 retry:
5573 /* FDI is a binary signal running at ~2.7GHz, encoding
5574 * each output octet as 10 bits. The actual frequency
5575 * is stored as a divider into a 100MHz clock, and the
5576 * mode pixel clock is stored in units of 1KHz.
5577 * Hence the bw of each lane in terms of the mode signal
5578 * is:
5579 */
5580 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5581
5582 fdi_dotclock = adjusted_mode->crtc_clock;
5583
5584 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5585 pipe_config->pipe_bpp);
5586
5587 pipe_config->fdi_lanes = lane;
5588
5589 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5590 link_bw, &pipe_config->fdi_m_n);
5591
5592 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5593 intel_crtc->pipe, pipe_config);
5594 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5595 pipe_config->pipe_bpp -= 2*3;
5596 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5597 pipe_config->pipe_bpp);
5598 needs_recompute = true;
5599 pipe_config->bw_constrained = true;
5600
5601 goto retry;
5602 }
5603
5604 if (needs_recompute)
5605 return RETRY;
5606
5607 return setup_ok ? 0 : -EINVAL;
5608 }
5609
5610 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5611 struct intel_crtc_state *pipe_config)
5612 {
5613 pipe_config->ips_enabled = i915.enable_ips &&
5614 hsw_crtc_supports_ips(crtc) &&
5615 pipe_config->pipe_bpp <= 24;
5616 }
5617
5618 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5619 struct intel_crtc_state *pipe_config)
5620 {
5621 struct drm_device *dev = crtc->base.dev;
5622 struct drm_i915_private *dev_priv = dev->dev_private;
5623 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5624
5625 /* FIXME should check pixel clock limits on all platforms */
5626 if (INTEL_INFO(dev)->gen < 4) {
5627 int clock_limit =
5628 dev_priv->display.get_display_clock_speed(dev);
5629
5630 /*
5631 * Enable pixel doubling when the dot clock
5632 * is > 90% of the (display) core speed.
5633 *
5634 * GDG double wide on either pipe,
5635 * otherwise pipe A only.
5636 */
5637 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5638 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5639 clock_limit *= 2;
5640 pipe_config->double_wide = true;
5641 }
5642
5643 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5644 return -EINVAL;
5645 }
5646
5647 /*
5648 * Pipe horizontal size must be even in:
5649 * - DVO ganged mode
5650 * - LVDS dual channel mode
5651 * - Double wide pipe
5652 */
5653 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5654 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5655 pipe_config->pipe_src_w &= ~1;
5656
5657 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5658 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5659 */
5660 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5661 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5662 return -EINVAL;
5663
5664 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5665 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5666 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5667 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5668 * for lvds. */
5669 pipe_config->pipe_bpp = 8*3;
5670 }
5671
5672 if (HAS_IPS(dev))
5673 hsw_compute_ips_config(crtc, pipe_config);
5674
5675 if (pipe_config->has_pch_encoder)
5676 return ironlake_fdi_compute_config(crtc, pipe_config);
5677
5678 return 0;
5679 }
5680
5681 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5682 {
5683 struct drm_i915_private *dev_priv = dev->dev_private;
5684 u32 val;
5685 int divider;
5686
5687 /* FIXME: Punit isn't quite ready yet */
5688 if (IS_CHERRYVIEW(dev))
5689 return 400000;
5690
5691 if (dev_priv->hpll_freq == 0)
5692 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5693
5694 mutex_lock(&dev_priv->dpio_lock);
5695 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5696 mutex_unlock(&dev_priv->dpio_lock);
5697
5698 divider = val & DISPLAY_FREQUENCY_VALUES;
5699
5700 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5701 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5702 "cdclk change in progress\n");
5703
5704 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5705 }
5706
5707 static int i945_get_display_clock_speed(struct drm_device *dev)
5708 {
5709 return 400000;
5710 }
5711
5712 static int i915_get_display_clock_speed(struct drm_device *dev)
5713 {
5714 return 333000;
5715 }
5716
5717 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5718 {
5719 return 200000;
5720 }
5721
5722 static int pnv_get_display_clock_speed(struct drm_device *dev)
5723 {
5724 u16 gcfgc = 0;
5725
5726 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5727
5728 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5729 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5730 return 267000;
5731 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5732 return 333000;
5733 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5734 return 444000;
5735 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5736 return 200000;
5737 default:
5738 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5739 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5740 return 133000;
5741 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5742 return 167000;
5743 }
5744 }
5745
5746 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5747 {
5748 u16 gcfgc = 0;
5749
5750 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5751
5752 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5753 return 133000;
5754 else {
5755 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5756 case GC_DISPLAY_CLOCK_333_MHZ:
5757 return 333000;
5758 default:
5759 case GC_DISPLAY_CLOCK_190_200_MHZ:
5760 return 190000;
5761 }
5762 }
5763 }
5764
5765 static int i865_get_display_clock_speed(struct drm_device *dev)
5766 {
5767 return 266000;
5768 }
5769
5770 static int i855_get_display_clock_speed(struct drm_device *dev)
5771 {
5772 u16 hpllcc = 0;
5773 /* Assume that the hardware is in the high speed state. This
5774 * should be the default.
5775 */
5776 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5777 case GC_CLOCK_133_200:
5778 case GC_CLOCK_100_200:
5779 return 200000;
5780 case GC_CLOCK_166_250:
5781 return 250000;
5782 case GC_CLOCK_100_133:
5783 return 133000;
5784 }
5785
5786 /* Shouldn't happen */
5787 return 0;
5788 }
5789
5790 static int i830_get_display_clock_speed(struct drm_device *dev)
5791 {
5792 return 133000;
5793 }
5794
5795 static void
5796 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5797 {
5798 while (*num > DATA_LINK_M_N_MASK ||
5799 *den > DATA_LINK_M_N_MASK) {
5800 *num >>= 1;
5801 *den >>= 1;
5802 }
5803 }
5804
5805 static void compute_m_n(unsigned int m, unsigned int n,
5806 uint32_t *ret_m, uint32_t *ret_n)
5807 {
5808 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5809 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5810 intel_reduce_m_n_ratio(ret_m, ret_n);
5811 }
5812
5813 void
5814 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5815 int pixel_clock, int link_clock,
5816 struct intel_link_m_n *m_n)
5817 {
5818 m_n->tu = 64;
5819
5820 compute_m_n(bits_per_pixel * pixel_clock,
5821 link_clock * nlanes * 8,
5822 &m_n->gmch_m, &m_n->gmch_n);
5823
5824 compute_m_n(pixel_clock, link_clock,
5825 &m_n->link_m, &m_n->link_n);
5826 }
5827
5828 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5829 {
5830 if (i915.panel_use_ssc >= 0)
5831 return i915.panel_use_ssc != 0;
5832 return dev_priv->vbt.lvds_use_ssc
5833 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5834 }
5835
5836 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5837 {
5838 struct drm_device *dev = crtc->base.dev;
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840 int refclk;
5841
5842 if (IS_VALLEYVIEW(dev)) {
5843 refclk = 100000;
5844 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5845 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5846 refclk = dev_priv->vbt.lvds_ssc_freq;
5847 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5848 } else if (!IS_GEN2(dev)) {
5849 refclk = 96000;
5850 } else {
5851 refclk = 48000;
5852 }
5853
5854 return refclk;
5855 }
5856
5857 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5858 {
5859 return (1 << dpll->n) << 16 | dpll->m2;
5860 }
5861
5862 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5863 {
5864 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5865 }
5866
5867 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5868 struct intel_crtc_state *crtc_state,
5869 intel_clock_t *reduced_clock)
5870 {
5871 struct drm_device *dev = crtc->base.dev;
5872 u32 fp, fp2 = 0;
5873
5874 if (IS_PINEVIEW(dev)) {
5875 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5876 if (reduced_clock)
5877 fp2 = pnv_dpll_compute_fp(reduced_clock);
5878 } else {
5879 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5880 if (reduced_clock)
5881 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5882 }
5883
5884 crtc_state->dpll_hw_state.fp0 = fp;
5885
5886 crtc->lowfreq_avail = false;
5887 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5888 reduced_clock && i915.powersave) {
5889 crtc_state->dpll_hw_state.fp1 = fp2;
5890 crtc->lowfreq_avail = true;
5891 } else {
5892 crtc_state->dpll_hw_state.fp1 = fp;
5893 }
5894 }
5895
5896 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5897 pipe)
5898 {
5899 u32 reg_val;
5900
5901 /*
5902 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5903 * and set it to a reasonable value instead.
5904 */
5905 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5906 reg_val &= 0xffffff00;
5907 reg_val |= 0x00000030;
5908 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5909
5910 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5911 reg_val &= 0x8cffffff;
5912 reg_val = 0x8c000000;
5913 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5914
5915 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5916 reg_val &= 0xffffff00;
5917 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5918
5919 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5920 reg_val &= 0x00ffffff;
5921 reg_val |= 0xb0000000;
5922 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5923 }
5924
5925 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5926 struct intel_link_m_n *m_n)
5927 {
5928 struct drm_device *dev = crtc->base.dev;
5929 struct drm_i915_private *dev_priv = dev->dev_private;
5930 int pipe = crtc->pipe;
5931
5932 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5933 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5934 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5935 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5936 }
5937
5938 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5939 struct intel_link_m_n *m_n,
5940 struct intel_link_m_n *m2_n2)
5941 {
5942 struct drm_device *dev = crtc->base.dev;
5943 struct drm_i915_private *dev_priv = dev->dev_private;
5944 int pipe = crtc->pipe;
5945 enum transcoder transcoder = crtc->config->cpu_transcoder;
5946
5947 if (INTEL_INFO(dev)->gen >= 5) {
5948 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5949 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5950 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5951 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5952 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5953 * for gen < 8) and if DRRS is supported (to make sure the
5954 * registers are not unnecessarily accessed).
5955 */
5956 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5957 crtc->config->has_drrs) {
5958 I915_WRITE(PIPE_DATA_M2(transcoder),
5959 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5960 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5961 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5962 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5963 }
5964 } else {
5965 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5966 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5967 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5968 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5969 }
5970 }
5971
5972 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
5973 {
5974 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
5975
5976 if (m_n == M1_N1) {
5977 dp_m_n = &crtc->config->dp_m_n;
5978 dp_m2_n2 = &crtc->config->dp_m2_n2;
5979 } else if (m_n == M2_N2) {
5980
5981 /*
5982 * M2_N2 registers are not supported. Hence m2_n2 divider value
5983 * needs to be programmed into M1_N1.
5984 */
5985 dp_m_n = &crtc->config->dp_m2_n2;
5986 } else {
5987 DRM_ERROR("Unsupported divider value\n");
5988 return;
5989 }
5990
5991 if (crtc->config->has_pch_encoder)
5992 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5993 else
5994 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
5995 }
5996
5997 static void vlv_update_pll(struct intel_crtc *crtc,
5998 struct intel_crtc_state *pipe_config)
5999 {
6000 u32 dpll, dpll_md;
6001
6002 /*
6003 * Enable DPIO clock input. We should never disable the reference
6004 * clock for pipe B, since VGA hotplug / manual detection depends
6005 * on it.
6006 */
6007 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6008 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6009 /* We should never disable this, set it here for state tracking */
6010 if (crtc->pipe == PIPE_B)
6011 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6012 dpll |= DPLL_VCO_ENABLE;
6013 pipe_config->dpll_hw_state.dpll = dpll;
6014
6015 dpll_md = (pipe_config->pixel_multiplier - 1)
6016 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6017 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6018 }
6019
6020 static void vlv_prepare_pll(struct intel_crtc *crtc,
6021 const struct intel_crtc_state *pipe_config)
6022 {
6023 struct drm_device *dev = crtc->base.dev;
6024 struct drm_i915_private *dev_priv = dev->dev_private;
6025 int pipe = crtc->pipe;
6026 u32 mdiv;
6027 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6028 u32 coreclk, reg_val;
6029
6030 mutex_lock(&dev_priv->dpio_lock);
6031
6032 bestn = pipe_config->dpll.n;
6033 bestm1 = pipe_config->dpll.m1;
6034 bestm2 = pipe_config->dpll.m2;
6035 bestp1 = pipe_config->dpll.p1;
6036 bestp2 = pipe_config->dpll.p2;
6037
6038 /* See eDP HDMI DPIO driver vbios notes doc */
6039
6040 /* PLL B needs special handling */
6041 if (pipe == PIPE_B)
6042 vlv_pllb_recal_opamp(dev_priv, pipe);
6043
6044 /* Set up Tx target for periodic Rcomp update */
6045 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6046
6047 /* Disable target IRef on PLL */
6048 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6049 reg_val &= 0x00ffffff;
6050 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6051
6052 /* Disable fast lock */
6053 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6054
6055 /* Set idtafcrecal before PLL is enabled */
6056 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6057 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6058 mdiv |= ((bestn << DPIO_N_SHIFT));
6059 mdiv |= (1 << DPIO_K_SHIFT);
6060
6061 /*
6062 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6063 * but we don't support that).
6064 * Note: don't use the DAC post divider as it seems unstable.
6065 */
6066 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6067 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6068
6069 mdiv |= DPIO_ENABLE_CALIBRATION;
6070 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6071
6072 /* Set HBR and RBR LPF coefficients */
6073 if (pipe_config->port_clock == 162000 ||
6074 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6075 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6076 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6077 0x009f0003);
6078 else
6079 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6080 0x00d0000f);
6081
6082 if (pipe_config->has_dp_encoder) {
6083 /* Use SSC source */
6084 if (pipe == PIPE_A)
6085 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6086 0x0df40000);
6087 else
6088 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6089 0x0df70000);
6090 } else { /* HDMI or VGA */
6091 /* Use bend source */
6092 if (pipe == PIPE_A)
6093 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6094 0x0df70000);
6095 else
6096 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6097 0x0df40000);
6098 }
6099
6100 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6101 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6102 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6103 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6104 coreclk |= 0x01000000;
6105 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6106
6107 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6108 mutex_unlock(&dev_priv->dpio_lock);
6109 }
6110
6111 static void chv_update_pll(struct intel_crtc *crtc,
6112 struct intel_crtc_state *pipe_config)
6113 {
6114 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6115 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6116 DPLL_VCO_ENABLE;
6117 if (crtc->pipe != PIPE_A)
6118 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6119
6120 pipe_config->dpll_hw_state.dpll_md =
6121 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6122 }
6123
6124 static void chv_prepare_pll(struct intel_crtc *crtc,
6125 const struct intel_crtc_state *pipe_config)
6126 {
6127 struct drm_device *dev = crtc->base.dev;
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129 int pipe = crtc->pipe;
6130 int dpll_reg = DPLL(crtc->pipe);
6131 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6132 u32 loopfilter, intcoeff;
6133 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6134 int refclk;
6135
6136 bestn = pipe_config->dpll.n;
6137 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6138 bestm1 = pipe_config->dpll.m1;
6139 bestm2 = pipe_config->dpll.m2 >> 22;
6140 bestp1 = pipe_config->dpll.p1;
6141 bestp2 = pipe_config->dpll.p2;
6142
6143 /*
6144 * Enable Refclk and SSC
6145 */
6146 I915_WRITE(dpll_reg,
6147 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6148
6149 mutex_lock(&dev_priv->dpio_lock);
6150
6151 /* p1 and p2 divider */
6152 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6153 5 << DPIO_CHV_S1_DIV_SHIFT |
6154 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6155 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6156 1 << DPIO_CHV_K_DIV_SHIFT);
6157
6158 /* Feedback post-divider - m2 */
6159 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6160
6161 /* Feedback refclk divider - n and m1 */
6162 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6163 DPIO_CHV_M1_DIV_BY_2 |
6164 1 << DPIO_CHV_N_DIV_SHIFT);
6165
6166 /* M2 fraction division */
6167 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6168
6169 /* M2 fraction division enable */
6170 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6171 DPIO_CHV_FRAC_DIV_EN |
6172 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6173
6174 /* Loop filter */
6175 refclk = i9xx_get_refclk(crtc, 0);
6176 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6177 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6178 if (refclk == 100000)
6179 intcoeff = 11;
6180 else if (refclk == 38400)
6181 intcoeff = 10;
6182 else
6183 intcoeff = 9;
6184 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6185 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6186
6187 /* AFC Recal */
6188 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6189 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6190 DPIO_AFC_RECAL);
6191
6192 mutex_unlock(&dev_priv->dpio_lock);
6193 }
6194
6195 /**
6196 * vlv_force_pll_on - forcibly enable just the PLL
6197 * @dev_priv: i915 private structure
6198 * @pipe: pipe PLL to enable
6199 * @dpll: PLL configuration
6200 *
6201 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6202 * in cases where we need the PLL enabled even when @pipe is not going to
6203 * be enabled.
6204 */
6205 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6206 const struct dpll *dpll)
6207 {
6208 struct intel_crtc *crtc =
6209 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6210 struct intel_crtc_state pipe_config = {
6211 .pixel_multiplier = 1,
6212 .dpll = *dpll,
6213 };
6214
6215 if (IS_CHERRYVIEW(dev)) {
6216 chv_update_pll(crtc, &pipe_config);
6217 chv_prepare_pll(crtc, &pipe_config);
6218 chv_enable_pll(crtc, &pipe_config);
6219 } else {
6220 vlv_update_pll(crtc, &pipe_config);
6221 vlv_prepare_pll(crtc, &pipe_config);
6222 vlv_enable_pll(crtc, &pipe_config);
6223 }
6224 }
6225
6226 /**
6227 * vlv_force_pll_off - forcibly disable just the PLL
6228 * @dev_priv: i915 private structure
6229 * @pipe: pipe PLL to disable
6230 *
6231 * Disable the PLL for @pipe. To be used in cases where we need
6232 * the PLL enabled even when @pipe is not going to be enabled.
6233 */
6234 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6235 {
6236 if (IS_CHERRYVIEW(dev))
6237 chv_disable_pll(to_i915(dev), pipe);
6238 else
6239 vlv_disable_pll(to_i915(dev), pipe);
6240 }
6241
6242 static void i9xx_update_pll(struct intel_crtc *crtc,
6243 struct intel_crtc_state *crtc_state,
6244 intel_clock_t *reduced_clock,
6245 int num_connectors)
6246 {
6247 struct drm_device *dev = crtc->base.dev;
6248 struct drm_i915_private *dev_priv = dev->dev_private;
6249 u32 dpll;
6250 bool is_sdvo;
6251 struct dpll *clock = &crtc_state->dpll;
6252
6253 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6254
6255 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6256 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6257
6258 dpll = DPLL_VGA_MODE_DIS;
6259
6260 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6261 dpll |= DPLLB_MODE_LVDS;
6262 else
6263 dpll |= DPLLB_MODE_DAC_SERIAL;
6264
6265 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6266 dpll |= (crtc_state->pixel_multiplier - 1)
6267 << SDVO_MULTIPLIER_SHIFT_HIRES;
6268 }
6269
6270 if (is_sdvo)
6271 dpll |= DPLL_SDVO_HIGH_SPEED;
6272
6273 if (crtc_state->has_dp_encoder)
6274 dpll |= DPLL_SDVO_HIGH_SPEED;
6275
6276 /* compute bitmask from p1 value */
6277 if (IS_PINEVIEW(dev))
6278 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6279 else {
6280 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6281 if (IS_G4X(dev) && reduced_clock)
6282 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6283 }
6284 switch (clock->p2) {
6285 case 5:
6286 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6287 break;
6288 case 7:
6289 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6290 break;
6291 case 10:
6292 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6293 break;
6294 case 14:
6295 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6296 break;
6297 }
6298 if (INTEL_INFO(dev)->gen >= 4)
6299 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6300
6301 if (crtc_state->sdvo_tv_clock)
6302 dpll |= PLL_REF_INPUT_TVCLKINBC;
6303 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6304 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6305 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6306 else
6307 dpll |= PLL_REF_INPUT_DREFCLK;
6308
6309 dpll |= DPLL_VCO_ENABLE;
6310 crtc_state->dpll_hw_state.dpll = dpll;
6311
6312 if (INTEL_INFO(dev)->gen >= 4) {
6313 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6314 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6315 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6316 }
6317 }
6318
6319 static void i8xx_update_pll(struct intel_crtc *crtc,
6320 struct intel_crtc_state *crtc_state,
6321 intel_clock_t *reduced_clock,
6322 int num_connectors)
6323 {
6324 struct drm_device *dev = crtc->base.dev;
6325 struct drm_i915_private *dev_priv = dev->dev_private;
6326 u32 dpll;
6327 struct dpll *clock = &crtc_state->dpll;
6328
6329 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6330
6331 dpll = DPLL_VGA_MODE_DIS;
6332
6333 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6334 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6335 } else {
6336 if (clock->p1 == 2)
6337 dpll |= PLL_P1_DIVIDE_BY_TWO;
6338 else
6339 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6340 if (clock->p2 == 4)
6341 dpll |= PLL_P2_DIVIDE_BY_4;
6342 }
6343
6344 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6345 dpll |= DPLL_DVO_2X_MODE;
6346
6347 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6348 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6349 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6350 else
6351 dpll |= PLL_REF_INPUT_DREFCLK;
6352
6353 dpll |= DPLL_VCO_ENABLE;
6354 crtc_state->dpll_hw_state.dpll = dpll;
6355 }
6356
6357 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6358 {
6359 struct drm_device *dev = intel_crtc->base.dev;
6360 struct drm_i915_private *dev_priv = dev->dev_private;
6361 enum pipe pipe = intel_crtc->pipe;
6362 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6363 struct drm_display_mode *adjusted_mode =
6364 &intel_crtc->config->base.adjusted_mode;
6365 uint32_t crtc_vtotal, crtc_vblank_end;
6366 int vsyncshift = 0;
6367
6368 /* We need to be careful not to changed the adjusted mode, for otherwise
6369 * the hw state checker will get angry at the mismatch. */
6370 crtc_vtotal = adjusted_mode->crtc_vtotal;
6371 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6372
6373 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6374 /* the chip adds 2 halflines automatically */
6375 crtc_vtotal -= 1;
6376 crtc_vblank_end -= 1;
6377
6378 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6379 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6380 else
6381 vsyncshift = adjusted_mode->crtc_hsync_start -
6382 adjusted_mode->crtc_htotal / 2;
6383 if (vsyncshift < 0)
6384 vsyncshift += adjusted_mode->crtc_htotal;
6385 }
6386
6387 if (INTEL_INFO(dev)->gen > 3)
6388 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6389
6390 I915_WRITE(HTOTAL(cpu_transcoder),
6391 (adjusted_mode->crtc_hdisplay - 1) |
6392 ((adjusted_mode->crtc_htotal - 1) << 16));
6393 I915_WRITE(HBLANK(cpu_transcoder),
6394 (adjusted_mode->crtc_hblank_start - 1) |
6395 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6396 I915_WRITE(HSYNC(cpu_transcoder),
6397 (adjusted_mode->crtc_hsync_start - 1) |
6398 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6399
6400 I915_WRITE(VTOTAL(cpu_transcoder),
6401 (adjusted_mode->crtc_vdisplay - 1) |
6402 ((crtc_vtotal - 1) << 16));
6403 I915_WRITE(VBLANK(cpu_transcoder),
6404 (adjusted_mode->crtc_vblank_start - 1) |
6405 ((crtc_vblank_end - 1) << 16));
6406 I915_WRITE(VSYNC(cpu_transcoder),
6407 (adjusted_mode->crtc_vsync_start - 1) |
6408 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6409
6410 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6411 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6412 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6413 * bits. */
6414 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6415 (pipe == PIPE_B || pipe == PIPE_C))
6416 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6417
6418 /* pipesrc controls the size that is scaled from, which should
6419 * always be the user's requested size.
6420 */
6421 I915_WRITE(PIPESRC(pipe),
6422 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6423 (intel_crtc->config->pipe_src_h - 1));
6424 }
6425
6426 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6427 struct intel_crtc_state *pipe_config)
6428 {
6429 struct drm_device *dev = crtc->base.dev;
6430 struct drm_i915_private *dev_priv = dev->dev_private;
6431 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6432 uint32_t tmp;
6433
6434 tmp = I915_READ(HTOTAL(cpu_transcoder));
6435 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6436 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6437 tmp = I915_READ(HBLANK(cpu_transcoder));
6438 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6439 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6440 tmp = I915_READ(HSYNC(cpu_transcoder));
6441 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6442 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6443
6444 tmp = I915_READ(VTOTAL(cpu_transcoder));
6445 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6446 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6447 tmp = I915_READ(VBLANK(cpu_transcoder));
6448 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6449 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6450 tmp = I915_READ(VSYNC(cpu_transcoder));
6451 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6452 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6453
6454 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6455 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6456 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6457 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6458 }
6459
6460 tmp = I915_READ(PIPESRC(crtc->pipe));
6461 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6462 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6463
6464 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6465 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6466 }
6467
6468 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6469 struct intel_crtc_state *pipe_config)
6470 {
6471 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6472 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6473 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6474 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6475
6476 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6477 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6478 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6479 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6480
6481 mode->flags = pipe_config->base.adjusted_mode.flags;
6482
6483 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6484 mode->flags |= pipe_config->base.adjusted_mode.flags;
6485 }
6486
6487 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6488 {
6489 struct drm_device *dev = intel_crtc->base.dev;
6490 struct drm_i915_private *dev_priv = dev->dev_private;
6491 uint32_t pipeconf;
6492
6493 pipeconf = 0;
6494
6495 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6496 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6497 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6498
6499 if (intel_crtc->config->double_wide)
6500 pipeconf |= PIPECONF_DOUBLE_WIDE;
6501
6502 /* only g4x and later have fancy bpc/dither controls */
6503 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6504 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6505 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6506 pipeconf |= PIPECONF_DITHER_EN |
6507 PIPECONF_DITHER_TYPE_SP;
6508
6509 switch (intel_crtc->config->pipe_bpp) {
6510 case 18:
6511 pipeconf |= PIPECONF_6BPC;
6512 break;
6513 case 24:
6514 pipeconf |= PIPECONF_8BPC;
6515 break;
6516 case 30:
6517 pipeconf |= PIPECONF_10BPC;
6518 break;
6519 default:
6520 /* Case prevented by intel_choose_pipe_bpp_dither. */
6521 BUG();
6522 }
6523 }
6524
6525 if (HAS_PIPE_CXSR(dev)) {
6526 if (intel_crtc->lowfreq_avail) {
6527 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6528 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6529 } else {
6530 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6531 }
6532 }
6533
6534 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6535 if (INTEL_INFO(dev)->gen < 4 ||
6536 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6537 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6538 else
6539 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6540 } else
6541 pipeconf |= PIPECONF_PROGRESSIVE;
6542
6543 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6544 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6545
6546 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6547 POSTING_READ(PIPECONF(intel_crtc->pipe));
6548 }
6549
6550 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6551 struct intel_crtc_state *crtc_state)
6552 {
6553 struct drm_device *dev = crtc->base.dev;
6554 struct drm_i915_private *dev_priv = dev->dev_private;
6555 int refclk, num_connectors = 0;
6556 intel_clock_t clock, reduced_clock;
6557 bool ok, has_reduced_clock = false;
6558 bool is_lvds = false, is_dsi = false;
6559 struct intel_encoder *encoder;
6560 const intel_limit_t *limit;
6561
6562 for_each_intel_encoder(dev, encoder) {
6563 if (encoder->new_crtc != crtc)
6564 continue;
6565
6566 switch (encoder->type) {
6567 case INTEL_OUTPUT_LVDS:
6568 is_lvds = true;
6569 break;
6570 case INTEL_OUTPUT_DSI:
6571 is_dsi = true;
6572 break;
6573 default:
6574 break;
6575 }
6576
6577 num_connectors++;
6578 }
6579
6580 if (is_dsi)
6581 return 0;
6582
6583 if (!crtc_state->clock_set) {
6584 refclk = i9xx_get_refclk(crtc, num_connectors);
6585
6586 /*
6587 * Returns a set of divisors for the desired target clock with
6588 * the given refclk, or FALSE. The returned values represent
6589 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6590 * 2) / p1 / p2.
6591 */
6592 limit = intel_limit(crtc, refclk);
6593 ok = dev_priv->display.find_dpll(limit, crtc,
6594 crtc_state->port_clock,
6595 refclk, NULL, &clock);
6596 if (!ok) {
6597 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6598 return -EINVAL;
6599 }
6600
6601 if (is_lvds && dev_priv->lvds_downclock_avail) {
6602 /*
6603 * Ensure we match the reduced clock's P to the target
6604 * clock. If the clocks don't match, we can't switch
6605 * the display clock by using the FP0/FP1. In such case
6606 * we will disable the LVDS downclock feature.
6607 */
6608 has_reduced_clock =
6609 dev_priv->display.find_dpll(limit, crtc,
6610 dev_priv->lvds_downclock,
6611 refclk, &clock,
6612 &reduced_clock);
6613 }
6614 /* Compat-code for transition, will disappear. */
6615 crtc_state->dpll.n = clock.n;
6616 crtc_state->dpll.m1 = clock.m1;
6617 crtc_state->dpll.m2 = clock.m2;
6618 crtc_state->dpll.p1 = clock.p1;
6619 crtc_state->dpll.p2 = clock.p2;
6620 }
6621
6622 if (IS_GEN2(dev)) {
6623 i8xx_update_pll(crtc, crtc_state,
6624 has_reduced_clock ? &reduced_clock : NULL,
6625 num_connectors);
6626 } else if (IS_CHERRYVIEW(dev)) {
6627 chv_update_pll(crtc, crtc_state);
6628 } else if (IS_VALLEYVIEW(dev)) {
6629 vlv_update_pll(crtc, crtc_state);
6630 } else {
6631 i9xx_update_pll(crtc, crtc_state,
6632 has_reduced_clock ? &reduced_clock : NULL,
6633 num_connectors);
6634 }
6635
6636 return 0;
6637 }
6638
6639 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6640 struct intel_crtc_state *pipe_config)
6641 {
6642 struct drm_device *dev = crtc->base.dev;
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 uint32_t tmp;
6645
6646 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6647 return;
6648
6649 tmp = I915_READ(PFIT_CONTROL);
6650 if (!(tmp & PFIT_ENABLE))
6651 return;
6652
6653 /* Check whether the pfit is attached to our pipe. */
6654 if (INTEL_INFO(dev)->gen < 4) {
6655 if (crtc->pipe != PIPE_B)
6656 return;
6657 } else {
6658 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6659 return;
6660 }
6661
6662 pipe_config->gmch_pfit.control = tmp;
6663 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6664 if (INTEL_INFO(dev)->gen < 5)
6665 pipe_config->gmch_pfit.lvds_border_bits =
6666 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6667 }
6668
6669 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6670 struct intel_crtc_state *pipe_config)
6671 {
6672 struct drm_device *dev = crtc->base.dev;
6673 struct drm_i915_private *dev_priv = dev->dev_private;
6674 int pipe = pipe_config->cpu_transcoder;
6675 intel_clock_t clock;
6676 u32 mdiv;
6677 int refclk = 100000;
6678
6679 /* In case of MIPI DPLL will not even be used */
6680 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6681 return;
6682
6683 mutex_lock(&dev_priv->dpio_lock);
6684 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6685 mutex_unlock(&dev_priv->dpio_lock);
6686
6687 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6688 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6689 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6690 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6691 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6692
6693 vlv_clock(refclk, &clock);
6694
6695 /* clock.dot is the fast clock */
6696 pipe_config->port_clock = clock.dot / 5;
6697 }
6698
6699 static void
6700 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6701 struct intel_initial_plane_config *plane_config)
6702 {
6703 struct drm_device *dev = crtc->base.dev;
6704 struct drm_i915_private *dev_priv = dev->dev_private;
6705 u32 val, base, offset;
6706 int pipe = crtc->pipe, plane = crtc->plane;
6707 int fourcc, pixel_format;
6708 int aligned_height;
6709 struct drm_framebuffer *fb;
6710 struct intel_framebuffer *intel_fb;
6711
6712 val = I915_READ(DSPCNTR(plane));
6713 if (!(val & DISPLAY_PLANE_ENABLE))
6714 return;
6715
6716 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6717 if (!intel_fb) {
6718 DRM_DEBUG_KMS("failed to alloc fb\n");
6719 return;
6720 }
6721
6722 fb = &intel_fb->base;
6723
6724 if (INTEL_INFO(dev)->gen >= 4) {
6725 if (val & DISPPLANE_TILED) {
6726 plane_config->tiling = I915_TILING_X;
6727 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6728 }
6729 }
6730
6731 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6732 fourcc = i9xx_format_to_fourcc(pixel_format);
6733 fb->pixel_format = fourcc;
6734 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6735
6736 if (INTEL_INFO(dev)->gen >= 4) {
6737 if (plane_config->tiling)
6738 offset = I915_READ(DSPTILEOFF(plane));
6739 else
6740 offset = I915_READ(DSPLINOFF(plane));
6741 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6742 } else {
6743 base = I915_READ(DSPADDR(plane));
6744 }
6745 plane_config->base = base;
6746
6747 val = I915_READ(PIPESRC(pipe));
6748 fb->width = ((val >> 16) & 0xfff) + 1;
6749 fb->height = ((val >> 0) & 0xfff) + 1;
6750
6751 val = I915_READ(DSPSTRIDE(pipe));
6752 fb->pitches[0] = val & 0xffffffc0;
6753
6754 aligned_height = intel_fb_align_height(dev, fb->height,
6755 fb->pixel_format,
6756 fb->modifier[0]);
6757
6758 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
6759
6760 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6761 pipe_name(pipe), plane, fb->width, fb->height,
6762 fb->bits_per_pixel, base, fb->pitches[0],
6763 plane_config->size);
6764
6765 plane_config->fb = intel_fb;
6766 }
6767
6768 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6769 struct intel_crtc_state *pipe_config)
6770 {
6771 struct drm_device *dev = crtc->base.dev;
6772 struct drm_i915_private *dev_priv = dev->dev_private;
6773 int pipe = pipe_config->cpu_transcoder;
6774 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6775 intel_clock_t clock;
6776 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6777 int refclk = 100000;
6778
6779 mutex_lock(&dev_priv->dpio_lock);
6780 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6781 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6782 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6783 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6784 mutex_unlock(&dev_priv->dpio_lock);
6785
6786 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6787 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6788 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6789 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6790 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6791
6792 chv_clock(refclk, &clock);
6793
6794 /* clock.dot is the fast clock */
6795 pipe_config->port_clock = clock.dot / 5;
6796 }
6797
6798 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6799 struct intel_crtc_state *pipe_config)
6800 {
6801 struct drm_device *dev = crtc->base.dev;
6802 struct drm_i915_private *dev_priv = dev->dev_private;
6803 uint32_t tmp;
6804
6805 if (!intel_display_power_is_enabled(dev_priv,
6806 POWER_DOMAIN_PIPE(crtc->pipe)))
6807 return false;
6808
6809 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6810 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6811
6812 tmp = I915_READ(PIPECONF(crtc->pipe));
6813 if (!(tmp & PIPECONF_ENABLE))
6814 return false;
6815
6816 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6817 switch (tmp & PIPECONF_BPC_MASK) {
6818 case PIPECONF_6BPC:
6819 pipe_config->pipe_bpp = 18;
6820 break;
6821 case PIPECONF_8BPC:
6822 pipe_config->pipe_bpp = 24;
6823 break;
6824 case PIPECONF_10BPC:
6825 pipe_config->pipe_bpp = 30;
6826 break;
6827 default:
6828 break;
6829 }
6830 }
6831
6832 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6833 pipe_config->limited_color_range = true;
6834
6835 if (INTEL_INFO(dev)->gen < 4)
6836 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6837
6838 intel_get_pipe_timings(crtc, pipe_config);
6839
6840 i9xx_get_pfit_config(crtc, pipe_config);
6841
6842 if (INTEL_INFO(dev)->gen >= 4) {
6843 tmp = I915_READ(DPLL_MD(crtc->pipe));
6844 pipe_config->pixel_multiplier =
6845 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6846 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6847 pipe_config->dpll_hw_state.dpll_md = tmp;
6848 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6849 tmp = I915_READ(DPLL(crtc->pipe));
6850 pipe_config->pixel_multiplier =
6851 ((tmp & SDVO_MULTIPLIER_MASK)
6852 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6853 } else {
6854 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6855 * port and will be fixed up in the encoder->get_config
6856 * function. */
6857 pipe_config->pixel_multiplier = 1;
6858 }
6859 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6860 if (!IS_VALLEYVIEW(dev)) {
6861 /*
6862 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6863 * on 830. Filter it out here so that we don't
6864 * report errors due to that.
6865 */
6866 if (IS_I830(dev))
6867 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6868
6869 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6870 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6871 } else {
6872 /* Mask out read-only status bits. */
6873 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6874 DPLL_PORTC_READY_MASK |
6875 DPLL_PORTB_READY_MASK);
6876 }
6877
6878 if (IS_CHERRYVIEW(dev))
6879 chv_crtc_clock_get(crtc, pipe_config);
6880 else if (IS_VALLEYVIEW(dev))
6881 vlv_crtc_clock_get(crtc, pipe_config);
6882 else
6883 i9xx_crtc_clock_get(crtc, pipe_config);
6884
6885 return true;
6886 }
6887
6888 static void ironlake_init_pch_refclk(struct drm_device *dev)
6889 {
6890 struct drm_i915_private *dev_priv = dev->dev_private;
6891 struct intel_encoder *encoder;
6892 u32 val, final;
6893 bool has_lvds = false;
6894 bool has_cpu_edp = false;
6895 bool has_panel = false;
6896 bool has_ck505 = false;
6897 bool can_ssc = false;
6898
6899 /* We need to take the global config into account */
6900 for_each_intel_encoder(dev, encoder) {
6901 switch (encoder->type) {
6902 case INTEL_OUTPUT_LVDS:
6903 has_panel = true;
6904 has_lvds = true;
6905 break;
6906 case INTEL_OUTPUT_EDP:
6907 has_panel = true;
6908 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6909 has_cpu_edp = true;
6910 break;
6911 default:
6912 break;
6913 }
6914 }
6915
6916 if (HAS_PCH_IBX(dev)) {
6917 has_ck505 = dev_priv->vbt.display_clock_mode;
6918 can_ssc = has_ck505;
6919 } else {
6920 has_ck505 = false;
6921 can_ssc = true;
6922 }
6923
6924 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6925 has_panel, has_lvds, has_ck505);
6926
6927 /* Ironlake: try to setup display ref clock before DPLL
6928 * enabling. This is only under driver's control after
6929 * PCH B stepping, previous chipset stepping should be
6930 * ignoring this setting.
6931 */
6932 val = I915_READ(PCH_DREF_CONTROL);
6933
6934 /* As we must carefully and slowly disable/enable each source in turn,
6935 * compute the final state we want first and check if we need to
6936 * make any changes at all.
6937 */
6938 final = val;
6939 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6940 if (has_ck505)
6941 final |= DREF_NONSPREAD_CK505_ENABLE;
6942 else
6943 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6944
6945 final &= ~DREF_SSC_SOURCE_MASK;
6946 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6947 final &= ~DREF_SSC1_ENABLE;
6948
6949 if (has_panel) {
6950 final |= DREF_SSC_SOURCE_ENABLE;
6951
6952 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6953 final |= DREF_SSC1_ENABLE;
6954
6955 if (has_cpu_edp) {
6956 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6957 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6958 else
6959 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6960 } else
6961 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6962 } else {
6963 final |= DREF_SSC_SOURCE_DISABLE;
6964 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6965 }
6966
6967 if (final == val)
6968 return;
6969
6970 /* Always enable nonspread source */
6971 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6972
6973 if (has_ck505)
6974 val |= DREF_NONSPREAD_CK505_ENABLE;
6975 else
6976 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6977
6978 if (has_panel) {
6979 val &= ~DREF_SSC_SOURCE_MASK;
6980 val |= DREF_SSC_SOURCE_ENABLE;
6981
6982 /* SSC must be turned on before enabling the CPU output */
6983 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6984 DRM_DEBUG_KMS("Using SSC on panel\n");
6985 val |= DREF_SSC1_ENABLE;
6986 } else
6987 val &= ~DREF_SSC1_ENABLE;
6988
6989 /* Get SSC going before enabling the outputs */
6990 I915_WRITE(PCH_DREF_CONTROL, val);
6991 POSTING_READ(PCH_DREF_CONTROL);
6992 udelay(200);
6993
6994 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6995
6996 /* Enable CPU source on CPU attached eDP */
6997 if (has_cpu_edp) {
6998 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6999 DRM_DEBUG_KMS("Using SSC on eDP\n");
7000 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7001 } else
7002 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7003 } else
7004 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7005
7006 I915_WRITE(PCH_DREF_CONTROL, val);
7007 POSTING_READ(PCH_DREF_CONTROL);
7008 udelay(200);
7009 } else {
7010 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7011
7012 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7013
7014 /* Turn off CPU output */
7015 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7016
7017 I915_WRITE(PCH_DREF_CONTROL, val);
7018 POSTING_READ(PCH_DREF_CONTROL);
7019 udelay(200);
7020
7021 /* Turn off the SSC source */
7022 val &= ~DREF_SSC_SOURCE_MASK;
7023 val |= DREF_SSC_SOURCE_DISABLE;
7024
7025 /* Turn off SSC1 */
7026 val &= ~DREF_SSC1_ENABLE;
7027
7028 I915_WRITE(PCH_DREF_CONTROL, val);
7029 POSTING_READ(PCH_DREF_CONTROL);
7030 udelay(200);
7031 }
7032
7033 BUG_ON(val != final);
7034 }
7035
7036 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7037 {
7038 uint32_t tmp;
7039
7040 tmp = I915_READ(SOUTH_CHICKEN2);
7041 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7042 I915_WRITE(SOUTH_CHICKEN2, tmp);
7043
7044 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7045 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7046 DRM_ERROR("FDI mPHY reset assert timeout\n");
7047
7048 tmp = I915_READ(SOUTH_CHICKEN2);
7049 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7050 I915_WRITE(SOUTH_CHICKEN2, tmp);
7051
7052 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7053 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7054 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7055 }
7056
7057 /* WaMPhyProgramming:hsw */
7058 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7059 {
7060 uint32_t tmp;
7061
7062 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7063 tmp &= ~(0xFF << 24);
7064 tmp |= (0x12 << 24);
7065 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7066
7067 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7068 tmp |= (1 << 11);
7069 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7070
7071 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7072 tmp |= (1 << 11);
7073 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7074
7075 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7076 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7077 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7078
7079 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7080 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7081 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7082
7083 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7084 tmp &= ~(7 << 13);
7085 tmp |= (5 << 13);
7086 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7087
7088 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7089 tmp &= ~(7 << 13);
7090 tmp |= (5 << 13);
7091 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7092
7093 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7094 tmp &= ~0xFF;
7095 tmp |= 0x1C;
7096 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7097
7098 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7099 tmp &= ~0xFF;
7100 tmp |= 0x1C;
7101 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7102
7103 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7104 tmp &= ~(0xFF << 16);
7105 tmp |= (0x1C << 16);
7106 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7107
7108 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7109 tmp &= ~(0xFF << 16);
7110 tmp |= (0x1C << 16);
7111 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7112
7113 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7114 tmp |= (1 << 27);
7115 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7116
7117 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7118 tmp |= (1 << 27);
7119 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7120
7121 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7122 tmp &= ~(0xF << 28);
7123 tmp |= (4 << 28);
7124 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7125
7126 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7127 tmp &= ~(0xF << 28);
7128 tmp |= (4 << 28);
7129 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7130 }
7131
7132 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7133 * Programming" based on the parameters passed:
7134 * - Sequence to enable CLKOUT_DP
7135 * - Sequence to enable CLKOUT_DP without spread
7136 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7137 */
7138 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7139 bool with_fdi)
7140 {
7141 struct drm_i915_private *dev_priv = dev->dev_private;
7142 uint32_t reg, tmp;
7143
7144 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7145 with_spread = true;
7146 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7147 with_fdi, "LP PCH doesn't have FDI\n"))
7148 with_fdi = false;
7149
7150 mutex_lock(&dev_priv->dpio_lock);
7151
7152 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7153 tmp &= ~SBI_SSCCTL_DISABLE;
7154 tmp |= SBI_SSCCTL_PATHALT;
7155 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7156
7157 udelay(24);
7158
7159 if (with_spread) {
7160 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7161 tmp &= ~SBI_SSCCTL_PATHALT;
7162 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7163
7164 if (with_fdi) {
7165 lpt_reset_fdi_mphy(dev_priv);
7166 lpt_program_fdi_mphy(dev_priv);
7167 }
7168 }
7169
7170 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7171 SBI_GEN0 : SBI_DBUFF0;
7172 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7173 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7174 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7175
7176 mutex_unlock(&dev_priv->dpio_lock);
7177 }
7178
7179 /* Sequence to disable CLKOUT_DP */
7180 static void lpt_disable_clkout_dp(struct drm_device *dev)
7181 {
7182 struct drm_i915_private *dev_priv = dev->dev_private;
7183 uint32_t reg, tmp;
7184
7185 mutex_lock(&dev_priv->dpio_lock);
7186
7187 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7188 SBI_GEN0 : SBI_DBUFF0;
7189 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7190 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7191 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7192
7193 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7194 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7195 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7196 tmp |= SBI_SSCCTL_PATHALT;
7197 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7198 udelay(32);
7199 }
7200 tmp |= SBI_SSCCTL_DISABLE;
7201 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7202 }
7203
7204 mutex_unlock(&dev_priv->dpio_lock);
7205 }
7206
7207 static void lpt_init_pch_refclk(struct drm_device *dev)
7208 {
7209 struct intel_encoder *encoder;
7210 bool has_vga = false;
7211
7212 for_each_intel_encoder(dev, encoder) {
7213 switch (encoder->type) {
7214 case INTEL_OUTPUT_ANALOG:
7215 has_vga = true;
7216 break;
7217 default:
7218 break;
7219 }
7220 }
7221
7222 if (has_vga)
7223 lpt_enable_clkout_dp(dev, true, true);
7224 else
7225 lpt_disable_clkout_dp(dev);
7226 }
7227
7228 /*
7229 * Initialize reference clocks when the driver loads
7230 */
7231 void intel_init_pch_refclk(struct drm_device *dev)
7232 {
7233 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7234 ironlake_init_pch_refclk(dev);
7235 else if (HAS_PCH_LPT(dev))
7236 lpt_init_pch_refclk(dev);
7237 }
7238
7239 static int ironlake_get_refclk(struct drm_crtc *crtc)
7240 {
7241 struct drm_device *dev = crtc->dev;
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243 struct intel_encoder *encoder;
7244 int num_connectors = 0;
7245 bool is_lvds = false;
7246
7247 for_each_intel_encoder(dev, encoder) {
7248 if (encoder->new_crtc != to_intel_crtc(crtc))
7249 continue;
7250
7251 switch (encoder->type) {
7252 case INTEL_OUTPUT_LVDS:
7253 is_lvds = true;
7254 break;
7255 default:
7256 break;
7257 }
7258 num_connectors++;
7259 }
7260
7261 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7262 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7263 dev_priv->vbt.lvds_ssc_freq);
7264 return dev_priv->vbt.lvds_ssc_freq;
7265 }
7266
7267 return 120000;
7268 }
7269
7270 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7271 {
7272 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7274 int pipe = intel_crtc->pipe;
7275 uint32_t val;
7276
7277 val = 0;
7278
7279 switch (intel_crtc->config->pipe_bpp) {
7280 case 18:
7281 val |= PIPECONF_6BPC;
7282 break;
7283 case 24:
7284 val |= PIPECONF_8BPC;
7285 break;
7286 case 30:
7287 val |= PIPECONF_10BPC;
7288 break;
7289 case 36:
7290 val |= PIPECONF_12BPC;
7291 break;
7292 default:
7293 /* Case prevented by intel_choose_pipe_bpp_dither. */
7294 BUG();
7295 }
7296
7297 if (intel_crtc->config->dither)
7298 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7299
7300 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7301 val |= PIPECONF_INTERLACED_ILK;
7302 else
7303 val |= PIPECONF_PROGRESSIVE;
7304
7305 if (intel_crtc->config->limited_color_range)
7306 val |= PIPECONF_COLOR_RANGE_SELECT;
7307
7308 I915_WRITE(PIPECONF(pipe), val);
7309 POSTING_READ(PIPECONF(pipe));
7310 }
7311
7312 /*
7313 * Set up the pipe CSC unit.
7314 *
7315 * Currently only full range RGB to limited range RGB conversion
7316 * is supported, but eventually this should handle various
7317 * RGB<->YCbCr scenarios as well.
7318 */
7319 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7320 {
7321 struct drm_device *dev = crtc->dev;
7322 struct drm_i915_private *dev_priv = dev->dev_private;
7323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7324 int pipe = intel_crtc->pipe;
7325 uint16_t coeff = 0x7800; /* 1.0 */
7326
7327 /*
7328 * TODO: Check what kind of values actually come out of the pipe
7329 * with these coeff/postoff values and adjust to get the best
7330 * accuracy. Perhaps we even need to take the bpc value into
7331 * consideration.
7332 */
7333
7334 if (intel_crtc->config->limited_color_range)
7335 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7336
7337 /*
7338 * GY/GU and RY/RU should be the other way around according
7339 * to BSpec, but reality doesn't agree. Just set them up in
7340 * a way that results in the correct picture.
7341 */
7342 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7343 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7344
7345 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7346 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7347
7348 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7349 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7350
7351 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7352 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7353 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7354
7355 if (INTEL_INFO(dev)->gen > 6) {
7356 uint16_t postoff = 0;
7357
7358 if (intel_crtc->config->limited_color_range)
7359 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7360
7361 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7362 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7363 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7364
7365 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7366 } else {
7367 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7368
7369 if (intel_crtc->config->limited_color_range)
7370 mode |= CSC_BLACK_SCREEN_OFFSET;
7371
7372 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7373 }
7374 }
7375
7376 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7377 {
7378 struct drm_device *dev = crtc->dev;
7379 struct drm_i915_private *dev_priv = dev->dev_private;
7380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7381 enum pipe pipe = intel_crtc->pipe;
7382 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7383 uint32_t val;
7384
7385 val = 0;
7386
7387 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7388 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7389
7390 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7391 val |= PIPECONF_INTERLACED_ILK;
7392 else
7393 val |= PIPECONF_PROGRESSIVE;
7394
7395 I915_WRITE(PIPECONF(cpu_transcoder), val);
7396 POSTING_READ(PIPECONF(cpu_transcoder));
7397
7398 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7399 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7400
7401 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7402 val = 0;
7403
7404 switch (intel_crtc->config->pipe_bpp) {
7405 case 18:
7406 val |= PIPEMISC_DITHER_6_BPC;
7407 break;
7408 case 24:
7409 val |= PIPEMISC_DITHER_8_BPC;
7410 break;
7411 case 30:
7412 val |= PIPEMISC_DITHER_10_BPC;
7413 break;
7414 case 36:
7415 val |= PIPEMISC_DITHER_12_BPC;
7416 break;
7417 default:
7418 /* Case prevented by pipe_config_set_bpp. */
7419 BUG();
7420 }
7421
7422 if (intel_crtc->config->dither)
7423 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7424
7425 I915_WRITE(PIPEMISC(pipe), val);
7426 }
7427 }
7428
7429 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7430 struct intel_crtc_state *crtc_state,
7431 intel_clock_t *clock,
7432 bool *has_reduced_clock,
7433 intel_clock_t *reduced_clock)
7434 {
7435 struct drm_device *dev = crtc->dev;
7436 struct drm_i915_private *dev_priv = dev->dev_private;
7437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7438 int refclk;
7439 const intel_limit_t *limit;
7440 bool ret, is_lvds = false;
7441
7442 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7443
7444 refclk = ironlake_get_refclk(crtc);
7445
7446 /*
7447 * Returns a set of divisors for the desired target clock with the given
7448 * refclk, or FALSE. The returned values represent the clock equation:
7449 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7450 */
7451 limit = intel_limit(intel_crtc, refclk);
7452 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7453 crtc_state->port_clock,
7454 refclk, NULL, clock);
7455 if (!ret)
7456 return false;
7457
7458 if (is_lvds && dev_priv->lvds_downclock_avail) {
7459 /*
7460 * Ensure we match the reduced clock's P to the target clock.
7461 * If the clocks don't match, we can't switch the display clock
7462 * by using the FP0/FP1. In such case we will disable the LVDS
7463 * downclock feature.
7464 */
7465 *has_reduced_clock =
7466 dev_priv->display.find_dpll(limit, intel_crtc,
7467 dev_priv->lvds_downclock,
7468 refclk, clock,
7469 reduced_clock);
7470 }
7471
7472 return true;
7473 }
7474
7475 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7476 {
7477 /*
7478 * Account for spread spectrum to avoid
7479 * oversubscribing the link. Max center spread
7480 * is 2.5%; use 5% for safety's sake.
7481 */
7482 u32 bps = target_clock * bpp * 21 / 20;
7483 return DIV_ROUND_UP(bps, link_bw * 8);
7484 }
7485
7486 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7487 {
7488 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7489 }
7490
7491 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7492 struct intel_crtc_state *crtc_state,
7493 u32 *fp,
7494 intel_clock_t *reduced_clock, u32 *fp2)
7495 {
7496 struct drm_crtc *crtc = &intel_crtc->base;
7497 struct drm_device *dev = crtc->dev;
7498 struct drm_i915_private *dev_priv = dev->dev_private;
7499 struct intel_encoder *intel_encoder;
7500 uint32_t dpll;
7501 int factor, num_connectors = 0;
7502 bool is_lvds = false, is_sdvo = false;
7503
7504 for_each_intel_encoder(dev, intel_encoder) {
7505 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7506 continue;
7507
7508 switch (intel_encoder->type) {
7509 case INTEL_OUTPUT_LVDS:
7510 is_lvds = true;
7511 break;
7512 case INTEL_OUTPUT_SDVO:
7513 case INTEL_OUTPUT_HDMI:
7514 is_sdvo = true;
7515 break;
7516 default:
7517 break;
7518 }
7519
7520 num_connectors++;
7521 }
7522
7523 /* Enable autotuning of the PLL clock (if permissible) */
7524 factor = 21;
7525 if (is_lvds) {
7526 if ((intel_panel_use_ssc(dev_priv) &&
7527 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7528 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7529 factor = 25;
7530 } else if (crtc_state->sdvo_tv_clock)
7531 factor = 20;
7532
7533 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7534 *fp |= FP_CB_TUNE;
7535
7536 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7537 *fp2 |= FP_CB_TUNE;
7538
7539 dpll = 0;
7540
7541 if (is_lvds)
7542 dpll |= DPLLB_MODE_LVDS;
7543 else
7544 dpll |= DPLLB_MODE_DAC_SERIAL;
7545
7546 dpll |= (crtc_state->pixel_multiplier - 1)
7547 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7548
7549 if (is_sdvo)
7550 dpll |= DPLL_SDVO_HIGH_SPEED;
7551 if (crtc_state->has_dp_encoder)
7552 dpll |= DPLL_SDVO_HIGH_SPEED;
7553
7554 /* compute bitmask from p1 value */
7555 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7556 /* also FPA1 */
7557 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7558
7559 switch (crtc_state->dpll.p2) {
7560 case 5:
7561 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7562 break;
7563 case 7:
7564 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7565 break;
7566 case 10:
7567 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7568 break;
7569 case 14:
7570 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7571 break;
7572 }
7573
7574 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7575 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7576 else
7577 dpll |= PLL_REF_INPUT_DREFCLK;
7578
7579 return dpll | DPLL_VCO_ENABLE;
7580 }
7581
7582 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7583 struct intel_crtc_state *crtc_state)
7584 {
7585 struct drm_device *dev = crtc->base.dev;
7586 intel_clock_t clock, reduced_clock;
7587 u32 dpll = 0, fp = 0, fp2 = 0;
7588 bool ok, has_reduced_clock = false;
7589 bool is_lvds = false;
7590 struct intel_shared_dpll *pll;
7591
7592 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7593
7594 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7595 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7596
7597 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7598 &has_reduced_clock, &reduced_clock);
7599 if (!ok && !crtc_state->clock_set) {
7600 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7601 return -EINVAL;
7602 }
7603 /* Compat-code for transition, will disappear. */
7604 if (!crtc_state->clock_set) {
7605 crtc_state->dpll.n = clock.n;
7606 crtc_state->dpll.m1 = clock.m1;
7607 crtc_state->dpll.m2 = clock.m2;
7608 crtc_state->dpll.p1 = clock.p1;
7609 crtc_state->dpll.p2 = clock.p2;
7610 }
7611
7612 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7613 if (crtc_state->has_pch_encoder) {
7614 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7615 if (has_reduced_clock)
7616 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7617
7618 dpll = ironlake_compute_dpll(crtc, crtc_state,
7619 &fp, &reduced_clock,
7620 has_reduced_clock ? &fp2 : NULL);
7621
7622 crtc_state->dpll_hw_state.dpll = dpll;
7623 crtc_state->dpll_hw_state.fp0 = fp;
7624 if (has_reduced_clock)
7625 crtc_state->dpll_hw_state.fp1 = fp2;
7626 else
7627 crtc_state->dpll_hw_state.fp1 = fp;
7628
7629 pll = intel_get_shared_dpll(crtc, crtc_state);
7630 if (pll == NULL) {
7631 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7632 pipe_name(crtc->pipe));
7633 return -EINVAL;
7634 }
7635 }
7636
7637 if (is_lvds && has_reduced_clock && i915.powersave)
7638 crtc->lowfreq_avail = true;
7639 else
7640 crtc->lowfreq_avail = false;
7641
7642 return 0;
7643 }
7644
7645 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7646 struct intel_link_m_n *m_n)
7647 {
7648 struct drm_device *dev = crtc->base.dev;
7649 struct drm_i915_private *dev_priv = dev->dev_private;
7650 enum pipe pipe = crtc->pipe;
7651
7652 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7653 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7654 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7655 & ~TU_SIZE_MASK;
7656 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7657 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7658 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7659 }
7660
7661 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7662 enum transcoder transcoder,
7663 struct intel_link_m_n *m_n,
7664 struct intel_link_m_n *m2_n2)
7665 {
7666 struct drm_device *dev = crtc->base.dev;
7667 struct drm_i915_private *dev_priv = dev->dev_private;
7668 enum pipe pipe = crtc->pipe;
7669
7670 if (INTEL_INFO(dev)->gen >= 5) {
7671 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7672 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7673 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7674 & ~TU_SIZE_MASK;
7675 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7676 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7677 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7678 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7679 * gen < 8) and if DRRS is supported (to make sure the
7680 * registers are not unnecessarily read).
7681 */
7682 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7683 crtc->config->has_drrs) {
7684 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7685 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7686 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7687 & ~TU_SIZE_MASK;
7688 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7689 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7690 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7691 }
7692 } else {
7693 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7694 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7695 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7696 & ~TU_SIZE_MASK;
7697 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7698 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7699 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7700 }
7701 }
7702
7703 void intel_dp_get_m_n(struct intel_crtc *crtc,
7704 struct intel_crtc_state *pipe_config)
7705 {
7706 if (pipe_config->has_pch_encoder)
7707 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7708 else
7709 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7710 &pipe_config->dp_m_n,
7711 &pipe_config->dp_m2_n2);
7712 }
7713
7714 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7715 struct intel_crtc_state *pipe_config)
7716 {
7717 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7718 &pipe_config->fdi_m_n, NULL);
7719 }
7720
7721 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7722 struct intel_crtc_state *pipe_config)
7723 {
7724 struct drm_device *dev = crtc->base.dev;
7725 struct drm_i915_private *dev_priv = dev->dev_private;
7726 uint32_t tmp;
7727
7728 tmp = I915_READ(PS_CTL(crtc->pipe));
7729
7730 if (tmp & PS_ENABLE) {
7731 pipe_config->pch_pfit.enabled = true;
7732 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7733 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7734 }
7735 }
7736
7737 static void
7738 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7739 struct intel_initial_plane_config *plane_config)
7740 {
7741 struct drm_device *dev = crtc->base.dev;
7742 struct drm_i915_private *dev_priv = dev->dev_private;
7743 u32 val, base, offset, stride_mult, tiling;
7744 int pipe = crtc->pipe;
7745 int fourcc, pixel_format;
7746 int aligned_height;
7747 struct drm_framebuffer *fb;
7748 struct intel_framebuffer *intel_fb;
7749
7750 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7751 if (!intel_fb) {
7752 DRM_DEBUG_KMS("failed to alloc fb\n");
7753 return;
7754 }
7755
7756 fb = &intel_fb->base;
7757
7758 val = I915_READ(PLANE_CTL(pipe, 0));
7759 if (!(val & PLANE_CTL_ENABLE))
7760 goto error;
7761
7762 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7763 fourcc = skl_format_to_fourcc(pixel_format,
7764 val & PLANE_CTL_ORDER_RGBX,
7765 val & PLANE_CTL_ALPHA_MASK);
7766 fb->pixel_format = fourcc;
7767 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7768
7769 tiling = val & PLANE_CTL_TILED_MASK;
7770 switch (tiling) {
7771 case PLANE_CTL_TILED_LINEAR:
7772 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7773 break;
7774 case PLANE_CTL_TILED_X:
7775 plane_config->tiling = I915_TILING_X;
7776 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7777 break;
7778 case PLANE_CTL_TILED_Y:
7779 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7780 break;
7781 case PLANE_CTL_TILED_YF:
7782 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7783 break;
7784 default:
7785 MISSING_CASE(tiling);
7786 goto error;
7787 }
7788
7789 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7790 plane_config->base = base;
7791
7792 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7793
7794 val = I915_READ(PLANE_SIZE(pipe, 0));
7795 fb->height = ((val >> 16) & 0xfff) + 1;
7796 fb->width = ((val >> 0) & 0x1fff) + 1;
7797
7798 val = I915_READ(PLANE_STRIDE(pipe, 0));
7799 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7800 fb->pixel_format);
7801 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7802
7803 aligned_height = intel_fb_align_height(dev, fb->height,
7804 fb->pixel_format,
7805 fb->modifier[0]);
7806
7807 plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
7808
7809 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7810 pipe_name(pipe), fb->width, fb->height,
7811 fb->bits_per_pixel, base, fb->pitches[0],
7812 plane_config->size);
7813
7814 plane_config->fb = intel_fb;
7815 return;
7816
7817 error:
7818 kfree(fb);
7819 }
7820
7821 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7822 struct intel_crtc_state *pipe_config)
7823 {
7824 struct drm_device *dev = crtc->base.dev;
7825 struct drm_i915_private *dev_priv = dev->dev_private;
7826 uint32_t tmp;
7827
7828 tmp = I915_READ(PF_CTL(crtc->pipe));
7829
7830 if (tmp & PF_ENABLE) {
7831 pipe_config->pch_pfit.enabled = true;
7832 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7833 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7834
7835 /* We currently do not free assignements of panel fitters on
7836 * ivb/hsw (since we don't use the higher upscaling modes which
7837 * differentiates them) so just WARN about this case for now. */
7838 if (IS_GEN7(dev)) {
7839 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7840 PF_PIPE_SEL_IVB(crtc->pipe));
7841 }
7842 }
7843 }
7844
7845 static void
7846 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7847 struct intel_initial_plane_config *plane_config)
7848 {
7849 struct drm_device *dev = crtc->base.dev;
7850 struct drm_i915_private *dev_priv = dev->dev_private;
7851 u32 val, base, offset;
7852 int pipe = crtc->pipe;
7853 int fourcc, pixel_format;
7854 int aligned_height;
7855 struct drm_framebuffer *fb;
7856 struct intel_framebuffer *intel_fb;
7857
7858 val = I915_READ(DSPCNTR(pipe));
7859 if (!(val & DISPLAY_PLANE_ENABLE))
7860 return;
7861
7862 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7863 if (!intel_fb) {
7864 DRM_DEBUG_KMS("failed to alloc fb\n");
7865 return;
7866 }
7867
7868 fb = &intel_fb->base;
7869
7870 if (INTEL_INFO(dev)->gen >= 4) {
7871 if (val & DISPPLANE_TILED) {
7872 plane_config->tiling = I915_TILING_X;
7873 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7874 }
7875 }
7876
7877 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7878 fourcc = i9xx_format_to_fourcc(pixel_format);
7879 fb->pixel_format = fourcc;
7880 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7881
7882 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7883 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7884 offset = I915_READ(DSPOFFSET(pipe));
7885 } else {
7886 if (plane_config->tiling)
7887 offset = I915_READ(DSPTILEOFF(pipe));
7888 else
7889 offset = I915_READ(DSPLINOFF(pipe));
7890 }
7891 plane_config->base = base;
7892
7893 val = I915_READ(PIPESRC(pipe));
7894 fb->width = ((val >> 16) & 0xfff) + 1;
7895 fb->height = ((val >> 0) & 0xfff) + 1;
7896
7897 val = I915_READ(DSPSTRIDE(pipe));
7898 fb->pitches[0] = val & 0xffffffc0;
7899
7900 aligned_height = intel_fb_align_height(dev, fb->height,
7901 fb->pixel_format,
7902 fb->modifier[0]);
7903
7904 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
7905
7906 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7907 pipe_name(pipe), fb->width, fb->height,
7908 fb->bits_per_pixel, base, fb->pitches[0],
7909 plane_config->size);
7910
7911 plane_config->fb = intel_fb;
7912 }
7913
7914 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7915 struct intel_crtc_state *pipe_config)
7916 {
7917 struct drm_device *dev = crtc->base.dev;
7918 struct drm_i915_private *dev_priv = dev->dev_private;
7919 uint32_t tmp;
7920
7921 if (!intel_display_power_is_enabled(dev_priv,
7922 POWER_DOMAIN_PIPE(crtc->pipe)))
7923 return false;
7924
7925 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7926 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7927
7928 tmp = I915_READ(PIPECONF(crtc->pipe));
7929 if (!(tmp & PIPECONF_ENABLE))
7930 return false;
7931
7932 switch (tmp & PIPECONF_BPC_MASK) {
7933 case PIPECONF_6BPC:
7934 pipe_config->pipe_bpp = 18;
7935 break;
7936 case PIPECONF_8BPC:
7937 pipe_config->pipe_bpp = 24;
7938 break;
7939 case PIPECONF_10BPC:
7940 pipe_config->pipe_bpp = 30;
7941 break;
7942 case PIPECONF_12BPC:
7943 pipe_config->pipe_bpp = 36;
7944 break;
7945 default:
7946 break;
7947 }
7948
7949 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7950 pipe_config->limited_color_range = true;
7951
7952 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7953 struct intel_shared_dpll *pll;
7954
7955 pipe_config->has_pch_encoder = true;
7956
7957 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7958 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7959 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7960
7961 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7962
7963 if (HAS_PCH_IBX(dev_priv->dev)) {
7964 pipe_config->shared_dpll =
7965 (enum intel_dpll_id) crtc->pipe;
7966 } else {
7967 tmp = I915_READ(PCH_DPLL_SEL);
7968 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7969 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7970 else
7971 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7972 }
7973
7974 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7975
7976 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7977 &pipe_config->dpll_hw_state));
7978
7979 tmp = pipe_config->dpll_hw_state.dpll;
7980 pipe_config->pixel_multiplier =
7981 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7982 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7983
7984 ironlake_pch_clock_get(crtc, pipe_config);
7985 } else {
7986 pipe_config->pixel_multiplier = 1;
7987 }
7988
7989 intel_get_pipe_timings(crtc, pipe_config);
7990
7991 ironlake_get_pfit_config(crtc, pipe_config);
7992
7993 return true;
7994 }
7995
7996 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7997 {
7998 struct drm_device *dev = dev_priv->dev;
7999 struct intel_crtc *crtc;
8000
8001 for_each_intel_crtc(dev, crtc)
8002 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8003 pipe_name(crtc->pipe));
8004
8005 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8006 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8007 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8008 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8009 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8010 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8011 "CPU PWM1 enabled\n");
8012 if (IS_HASWELL(dev))
8013 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8014 "CPU PWM2 enabled\n");
8015 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8016 "PCH PWM1 enabled\n");
8017 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8018 "Utility pin enabled\n");
8019 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8020
8021 /*
8022 * In theory we can still leave IRQs enabled, as long as only the HPD
8023 * interrupts remain enabled. We used to check for that, but since it's
8024 * gen-specific and since we only disable LCPLL after we fully disable
8025 * the interrupts, the check below should be enough.
8026 */
8027 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8028 }
8029
8030 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8031 {
8032 struct drm_device *dev = dev_priv->dev;
8033
8034 if (IS_HASWELL(dev))
8035 return I915_READ(D_COMP_HSW);
8036 else
8037 return I915_READ(D_COMP_BDW);
8038 }
8039
8040 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8041 {
8042 struct drm_device *dev = dev_priv->dev;
8043
8044 if (IS_HASWELL(dev)) {
8045 mutex_lock(&dev_priv->rps.hw_lock);
8046 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8047 val))
8048 DRM_ERROR("Failed to write to D_COMP\n");
8049 mutex_unlock(&dev_priv->rps.hw_lock);
8050 } else {
8051 I915_WRITE(D_COMP_BDW, val);
8052 POSTING_READ(D_COMP_BDW);
8053 }
8054 }
8055
8056 /*
8057 * This function implements pieces of two sequences from BSpec:
8058 * - Sequence for display software to disable LCPLL
8059 * - Sequence for display software to allow package C8+
8060 * The steps implemented here are just the steps that actually touch the LCPLL
8061 * register. Callers should take care of disabling all the display engine
8062 * functions, doing the mode unset, fixing interrupts, etc.
8063 */
8064 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8065 bool switch_to_fclk, bool allow_power_down)
8066 {
8067 uint32_t val;
8068
8069 assert_can_disable_lcpll(dev_priv);
8070
8071 val = I915_READ(LCPLL_CTL);
8072
8073 if (switch_to_fclk) {
8074 val |= LCPLL_CD_SOURCE_FCLK;
8075 I915_WRITE(LCPLL_CTL, val);
8076
8077 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8078 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8079 DRM_ERROR("Switching to FCLK failed\n");
8080
8081 val = I915_READ(LCPLL_CTL);
8082 }
8083
8084 val |= LCPLL_PLL_DISABLE;
8085 I915_WRITE(LCPLL_CTL, val);
8086 POSTING_READ(LCPLL_CTL);
8087
8088 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8089 DRM_ERROR("LCPLL still locked\n");
8090
8091 val = hsw_read_dcomp(dev_priv);
8092 val |= D_COMP_COMP_DISABLE;
8093 hsw_write_dcomp(dev_priv, val);
8094 ndelay(100);
8095
8096 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8097 1))
8098 DRM_ERROR("D_COMP RCOMP still in progress\n");
8099
8100 if (allow_power_down) {
8101 val = I915_READ(LCPLL_CTL);
8102 val |= LCPLL_POWER_DOWN_ALLOW;
8103 I915_WRITE(LCPLL_CTL, val);
8104 POSTING_READ(LCPLL_CTL);
8105 }
8106 }
8107
8108 /*
8109 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8110 * source.
8111 */
8112 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8113 {
8114 uint32_t val;
8115
8116 val = I915_READ(LCPLL_CTL);
8117
8118 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8119 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8120 return;
8121
8122 /*
8123 * Make sure we're not on PC8 state before disabling PC8, otherwise
8124 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8125 */
8126 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8127
8128 if (val & LCPLL_POWER_DOWN_ALLOW) {
8129 val &= ~LCPLL_POWER_DOWN_ALLOW;
8130 I915_WRITE(LCPLL_CTL, val);
8131 POSTING_READ(LCPLL_CTL);
8132 }
8133
8134 val = hsw_read_dcomp(dev_priv);
8135 val |= D_COMP_COMP_FORCE;
8136 val &= ~D_COMP_COMP_DISABLE;
8137 hsw_write_dcomp(dev_priv, val);
8138
8139 val = I915_READ(LCPLL_CTL);
8140 val &= ~LCPLL_PLL_DISABLE;
8141 I915_WRITE(LCPLL_CTL, val);
8142
8143 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8144 DRM_ERROR("LCPLL not locked yet\n");
8145
8146 if (val & LCPLL_CD_SOURCE_FCLK) {
8147 val = I915_READ(LCPLL_CTL);
8148 val &= ~LCPLL_CD_SOURCE_FCLK;
8149 I915_WRITE(LCPLL_CTL, val);
8150
8151 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8152 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8153 DRM_ERROR("Switching back to LCPLL failed\n");
8154 }
8155
8156 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8157 }
8158
8159 /*
8160 * Package states C8 and deeper are really deep PC states that can only be
8161 * reached when all the devices on the system allow it, so even if the graphics
8162 * device allows PC8+, it doesn't mean the system will actually get to these
8163 * states. Our driver only allows PC8+ when going into runtime PM.
8164 *
8165 * The requirements for PC8+ are that all the outputs are disabled, the power
8166 * well is disabled and most interrupts are disabled, and these are also
8167 * requirements for runtime PM. When these conditions are met, we manually do
8168 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8169 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8170 * hang the machine.
8171 *
8172 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8173 * the state of some registers, so when we come back from PC8+ we need to
8174 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8175 * need to take care of the registers kept by RC6. Notice that this happens even
8176 * if we don't put the device in PCI D3 state (which is what currently happens
8177 * because of the runtime PM support).
8178 *
8179 * For more, read "Display Sequences for Package C8" on the hardware
8180 * documentation.
8181 */
8182 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8183 {
8184 struct drm_device *dev = dev_priv->dev;
8185 uint32_t val;
8186
8187 DRM_DEBUG_KMS("Enabling package C8+\n");
8188
8189 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8190 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8191 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8192 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8193 }
8194
8195 lpt_disable_clkout_dp(dev);
8196 hsw_disable_lcpll(dev_priv, true, true);
8197 }
8198
8199 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8200 {
8201 struct drm_device *dev = dev_priv->dev;
8202 uint32_t val;
8203
8204 DRM_DEBUG_KMS("Disabling package C8+\n");
8205
8206 hsw_restore_lcpll(dev_priv);
8207 lpt_init_pch_refclk(dev);
8208
8209 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8210 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8211 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8212 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8213 }
8214
8215 intel_prepare_ddi(dev);
8216 }
8217
8218 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8219 struct intel_crtc_state *crtc_state)
8220 {
8221 if (!intel_ddi_pll_select(crtc, crtc_state))
8222 return -EINVAL;
8223
8224 crtc->lowfreq_avail = false;
8225
8226 return 0;
8227 }
8228
8229 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8230 enum port port,
8231 struct intel_crtc_state *pipe_config)
8232 {
8233 u32 temp, dpll_ctl1;
8234
8235 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8236 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8237
8238 switch (pipe_config->ddi_pll_sel) {
8239 case SKL_DPLL0:
8240 /*
8241 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8242 * of the shared DPLL framework and thus needs to be read out
8243 * separately
8244 */
8245 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8246 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8247 break;
8248 case SKL_DPLL1:
8249 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8250 break;
8251 case SKL_DPLL2:
8252 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8253 break;
8254 case SKL_DPLL3:
8255 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8256 break;
8257 }
8258 }
8259
8260 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8261 enum port port,
8262 struct intel_crtc_state *pipe_config)
8263 {
8264 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8265
8266 switch (pipe_config->ddi_pll_sel) {
8267 case PORT_CLK_SEL_WRPLL1:
8268 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8269 break;
8270 case PORT_CLK_SEL_WRPLL2:
8271 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8272 break;
8273 }
8274 }
8275
8276 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8277 struct intel_crtc_state *pipe_config)
8278 {
8279 struct drm_device *dev = crtc->base.dev;
8280 struct drm_i915_private *dev_priv = dev->dev_private;
8281 struct intel_shared_dpll *pll;
8282 enum port port;
8283 uint32_t tmp;
8284
8285 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8286
8287 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8288
8289 if (IS_SKYLAKE(dev))
8290 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8291 else
8292 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8293
8294 if (pipe_config->shared_dpll >= 0) {
8295 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8296
8297 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8298 &pipe_config->dpll_hw_state));
8299 }
8300
8301 /*
8302 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8303 * DDI E. So just check whether this pipe is wired to DDI E and whether
8304 * the PCH transcoder is on.
8305 */
8306 if (INTEL_INFO(dev)->gen < 9 &&
8307 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8308 pipe_config->has_pch_encoder = true;
8309
8310 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8311 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8312 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8313
8314 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8315 }
8316 }
8317
8318 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8319 struct intel_crtc_state *pipe_config)
8320 {
8321 struct drm_device *dev = crtc->base.dev;
8322 struct drm_i915_private *dev_priv = dev->dev_private;
8323 enum intel_display_power_domain pfit_domain;
8324 uint32_t tmp;
8325
8326 if (!intel_display_power_is_enabled(dev_priv,
8327 POWER_DOMAIN_PIPE(crtc->pipe)))
8328 return false;
8329
8330 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8331 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8332
8333 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8334 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8335 enum pipe trans_edp_pipe;
8336 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8337 default:
8338 WARN(1, "unknown pipe linked to edp transcoder\n");
8339 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8340 case TRANS_DDI_EDP_INPUT_A_ON:
8341 trans_edp_pipe = PIPE_A;
8342 break;
8343 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8344 trans_edp_pipe = PIPE_B;
8345 break;
8346 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8347 trans_edp_pipe = PIPE_C;
8348 break;
8349 }
8350
8351 if (trans_edp_pipe == crtc->pipe)
8352 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8353 }
8354
8355 if (!intel_display_power_is_enabled(dev_priv,
8356 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8357 return false;
8358
8359 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8360 if (!(tmp & PIPECONF_ENABLE))
8361 return false;
8362
8363 haswell_get_ddi_port_state(crtc, pipe_config);
8364
8365 intel_get_pipe_timings(crtc, pipe_config);
8366
8367 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8368 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8369 if (IS_SKYLAKE(dev))
8370 skylake_get_pfit_config(crtc, pipe_config);
8371 else
8372 ironlake_get_pfit_config(crtc, pipe_config);
8373 }
8374
8375 if (IS_HASWELL(dev))
8376 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8377 (I915_READ(IPS_CTL) & IPS_ENABLE);
8378
8379 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8380 pipe_config->pixel_multiplier =
8381 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8382 } else {
8383 pipe_config->pixel_multiplier = 1;
8384 }
8385
8386 return true;
8387 }
8388
8389 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8390 {
8391 struct drm_device *dev = crtc->dev;
8392 struct drm_i915_private *dev_priv = dev->dev_private;
8393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8394 uint32_t cntl = 0, size = 0;
8395
8396 if (base) {
8397 unsigned int width = intel_crtc->cursor_width;
8398 unsigned int height = intel_crtc->cursor_height;
8399 unsigned int stride = roundup_pow_of_two(width) * 4;
8400
8401 switch (stride) {
8402 default:
8403 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8404 width, stride);
8405 stride = 256;
8406 /* fallthrough */
8407 case 256:
8408 case 512:
8409 case 1024:
8410 case 2048:
8411 break;
8412 }
8413
8414 cntl |= CURSOR_ENABLE |
8415 CURSOR_GAMMA_ENABLE |
8416 CURSOR_FORMAT_ARGB |
8417 CURSOR_STRIDE(stride);
8418
8419 size = (height << 12) | width;
8420 }
8421
8422 if (intel_crtc->cursor_cntl != 0 &&
8423 (intel_crtc->cursor_base != base ||
8424 intel_crtc->cursor_size != size ||
8425 intel_crtc->cursor_cntl != cntl)) {
8426 /* On these chipsets we can only modify the base/size/stride
8427 * whilst the cursor is disabled.
8428 */
8429 I915_WRITE(_CURACNTR, 0);
8430 POSTING_READ(_CURACNTR);
8431 intel_crtc->cursor_cntl = 0;
8432 }
8433
8434 if (intel_crtc->cursor_base != base) {
8435 I915_WRITE(_CURABASE, base);
8436 intel_crtc->cursor_base = base;
8437 }
8438
8439 if (intel_crtc->cursor_size != size) {
8440 I915_WRITE(CURSIZE, size);
8441 intel_crtc->cursor_size = size;
8442 }
8443
8444 if (intel_crtc->cursor_cntl != cntl) {
8445 I915_WRITE(_CURACNTR, cntl);
8446 POSTING_READ(_CURACNTR);
8447 intel_crtc->cursor_cntl = cntl;
8448 }
8449 }
8450
8451 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8452 {
8453 struct drm_device *dev = crtc->dev;
8454 struct drm_i915_private *dev_priv = dev->dev_private;
8455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8456 int pipe = intel_crtc->pipe;
8457 uint32_t cntl;
8458
8459 cntl = 0;
8460 if (base) {
8461 cntl = MCURSOR_GAMMA_ENABLE;
8462 switch (intel_crtc->cursor_width) {
8463 case 64:
8464 cntl |= CURSOR_MODE_64_ARGB_AX;
8465 break;
8466 case 128:
8467 cntl |= CURSOR_MODE_128_ARGB_AX;
8468 break;
8469 case 256:
8470 cntl |= CURSOR_MODE_256_ARGB_AX;
8471 break;
8472 default:
8473 MISSING_CASE(intel_crtc->cursor_width);
8474 return;
8475 }
8476 cntl |= pipe << 28; /* Connect to correct pipe */
8477
8478 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8479 cntl |= CURSOR_PIPE_CSC_ENABLE;
8480 }
8481
8482 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8483 cntl |= CURSOR_ROTATE_180;
8484
8485 if (intel_crtc->cursor_cntl != cntl) {
8486 I915_WRITE(CURCNTR(pipe), cntl);
8487 POSTING_READ(CURCNTR(pipe));
8488 intel_crtc->cursor_cntl = cntl;
8489 }
8490
8491 /* and commit changes on next vblank */
8492 I915_WRITE(CURBASE(pipe), base);
8493 POSTING_READ(CURBASE(pipe));
8494
8495 intel_crtc->cursor_base = base;
8496 }
8497
8498 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8499 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8500 bool on)
8501 {
8502 struct drm_device *dev = crtc->dev;
8503 struct drm_i915_private *dev_priv = dev->dev_private;
8504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8505 int pipe = intel_crtc->pipe;
8506 int x = crtc->cursor_x;
8507 int y = crtc->cursor_y;
8508 u32 base = 0, pos = 0;
8509
8510 if (on)
8511 base = intel_crtc->cursor_addr;
8512
8513 if (x >= intel_crtc->config->pipe_src_w)
8514 base = 0;
8515
8516 if (y >= intel_crtc->config->pipe_src_h)
8517 base = 0;
8518
8519 if (x < 0) {
8520 if (x + intel_crtc->cursor_width <= 0)
8521 base = 0;
8522
8523 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8524 x = -x;
8525 }
8526 pos |= x << CURSOR_X_SHIFT;
8527
8528 if (y < 0) {
8529 if (y + intel_crtc->cursor_height <= 0)
8530 base = 0;
8531
8532 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8533 y = -y;
8534 }
8535 pos |= y << CURSOR_Y_SHIFT;
8536
8537 if (base == 0 && intel_crtc->cursor_base == 0)
8538 return;
8539
8540 I915_WRITE(CURPOS(pipe), pos);
8541
8542 /* ILK+ do this automagically */
8543 if (HAS_GMCH_DISPLAY(dev) &&
8544 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8545 base += (intel_crtc->cursor_height *
8546 intel_crtc->cursor_width - 1) * 4;
8547 }
8548
8549 if (IS_845G(dev) || IS_I865G(dev))
8550 i845_update_cursor(crtc, base);
8551 else
8552 i9xx_update_cursor(crtc, base);
8553 }
8554
8555 static bool cursor_size_ok(struct drm_device *dev,
8556 uint32_t width, uint32_t height)
8557 {
8558 if (width == 0 || height == 0)
8559 return false;
8560
8561 /*
8562 * 845g/865g are special in that they are only limited by
8563 * the width of their cursors, the height is arbitrary up to
8564 * the precision of the register. Everything else requires
8565 * square cursors, limited to a few power-of-two sizes.
8566 */
8567 if (IS_845G(dev) || IS_I865G(dev)) {
8568 if ((width & 63) != 0)
8569 return false;
8570
8571 if (width > (IS_845G(dev) ? 64 : 512))
8572 return false;
8573
8574 if (height > 1023)
8575 return false;
8576 } else {
8577 switch (width | height) {
8578 case 256:
8579 case 128:
8580 if (IS_GEN2(dev))
8581 return false;
8582 case 64:
8583 break;
8584 default:
8585 return false;
8586 }
8587 }
8588
8589 return true;
8590 }
8591
8592 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8593 u16 *blue, uint32_t start, uint32_t size)
8594 {
8595 int end = (start + size > 256) ? 256 : start + size, i;
8596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8597
8598 for (i = start; i < end; i++) {
8599 intel_crtc->lut_r[i] = red[i] >> 8;
8600 intel_crtc->lut_g[i] = green[i] >> 8;
8601 intel_crtc->lut_b[i] = blue[i] >> 8;
8602 }
8603
8604 intel_crtc_load_lut(crtc);
8605 }
8606
8607 /* VESA 640x480x72Hz mode to set on the pipe */
8608 static struct drm_display_mode load_detect_mode = {
8609 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8610 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8611 };
8612
8613 struct drm_framebuffer *
8614 __intel_framebuffer_create(struct drm_device *dev,
8615 struct drm_mode_fb_cmd2 *mode_cmd,
8616 struct drm_i915_gem_object *obj)
8617 {
8618 struct intel_framebuffer *intel_fb;
8619 int ret;
8620
8621 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8622 if (!intel_fb) {
8623 drm_gem_object_unreference(&obj->base);
8624 return ERR_PTR(-ENOMEM);
8625 }
8626
8627 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8628 if (ret)
8629 goto err;
8630
8631 return &intel_fb->base;
8632 err:
8633 drm_gem_object_unreference(&obj->base);
8634 kfree(intel_fb);
8635
8636 return ERR_PTR(ret);
8637 }
8638
8639 static struct drm_framebuffer *
8640 intel_framebuffer_create(struct drm_device *dev,
8641 struct drm_mode_fb_cmd2 *mode_cmd,
8642 struct drm_i915_gem_object *obj)
8643 {
8644 struct drm_framebuffer *fb;
8645 int ret;
8646
8647 ret = i915_mutex_lock_interruptible(dev);
8648 if (ret)
8649 return ERR_PTR(ret);
8650 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8651 mutex_unlock(&dev->struct_mutex);
8652
8653 return fb;
8654 }
8655
8656 static u32
8657 intel_framebuffer_pitch_for_width(int width, int bpp)
8658 {
8659 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8660 return ALIGN(pitch, 64);
8661 }
8662
8663 static u32
8664 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8665 {
8666 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8667 return PAGE_ALIGN(pitch * mode->vdisplay);
8668 }
8669
8670 static struct drm_framebuffer *
8671 intel_framebuffer_create_for_mode(struct drm_device *dev,
8672 struct drm_display_mode *mode,
8673 int depth, int bpp)
8674 {
8675 struct drm_i915_gem_object *obj;
8676 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8677
8678 obj = i915_gem_alloc_object(dev,
8679 intel_framebuffer_size_for_mode(mode, bpp));
8680 if (obj == NULL)
8681 return ERR_PTR(-ENOMEM);
8682
8683 mode_cmd.width = mode->hdisplay;
8684 mode_cmd.height = mode->vdisplay;
8685 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8686 bpp);
8687 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8688
8689 return intel_framebuffer_create(dev, &mode_cmd, obj);
8690 }
8691
8692 static struct drm_framebuffer *
8693 mode_fits_in_fbdev(struct drm_device *dev,
8694 struct drm_display_mode *mode)
8695 {
8696 #ifdef CONFIG_DRM_I915_FBDEV
8697 struct drm_i915_private *dev_priv = dev->dev_private;
8698 struct drm_i915_gem_object *obj;
8699 struct drm_framebuffer *fb;
8700
8701 if (!dev_priv->fbdev)
8702 return NULL;
8703
8704 if (!dev_priv->fbdev->fb)
8705 return NULL;
8706
8707 obj = dev_priv->fbdev->fb->obj;
8708 BUG_ON(!obj);
8709
8710 fb = &dev_priv->fbdev->fb->base;
8711 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8712 fb->bits_per_pixel))
8713 return NULL;
8714
8715 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8716 return NULL;
8717
8718 return fb;
8719 #else
8720 return NULL;
8721 #endif
8722 }
8723
8724 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8725 struct drm_display_mode *mode,
8726 struct intel_load_detect_pipe *old,
8727 struct drm_modeset_acquire_ctx *ctx)
8728 {
8729 struct intel_crtc *intel_crtc;
8730 struct intel_encoder *intel_encoder =
8731 intel_attached_encoder(connector);
8732 struct drm_crtc *possible_crtc;
8733 struct drm_encoder *encoder = &intel_encoder->base;
8734 struct drm_crtc *crtc = NULL;
8735 struct drm_device *dev = encoder->dev;
8736 struct drm_framebuffer *fb;
8737 struct drm_mode_config *config = &dev->mode_config;
8738 int ret, i = -1;
8739
8740 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8741 connector->base.id, connector->name,
8742 encoder->base.id, encoder->name);
8743
8744 retry:
8745 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8746 if (ret)
8747 goto fail_unlock;
8748
8749 /*
8750 * Algorithm gets a little messy:
8751 *
8752 * - if the connector already has an assigned crtc, use it (but make
8753 * sure it's on first)
8754 *
8755 * - try to find the first unused crtc that can drive this connector,
8756 * and use that if we find one
8757 */
8758
8759 /* See if we already have a CRTC for this connector */
8760 if (encoder->crtc) {
8761 crtc = encoder->crtc;
8762
8763 ret = drm_modeset_lock(&crtc->mutex, ctx);
8764 if (ret)
8765 goto fail_unlock;
8766 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8767 if (ret)
8768 goto fail_unlock;
8769
8770 old->dpms_mode = connector->dpms;
8771 old->load_detect_temp = false;
8772
8773 /* Make sure the crtc and connector are running */
8774 if (connector->dpms != DRM_MODE_DPMS_ON)
8775 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8776
8777 return true;
8778 }
8779
8780 /* Find an unused one (if possible) */
8781 for_each_crtc(dev, possible_crtc) {
8782 i++;
8783 if (!(encoder->possible_crtcs & (1 << i)))
8784 continue;
8785 if (possible_crtc->state->enable)
8786 continue;
8787 /* This can occur when applying the pipe A quirk on resume. */
8788 if (to_intel_crtc(possible_crtc)->new_enabled)
8789 continue;
8790
8791 crtc = possible_crtc;
8792 break;
8793 }
8794
8795 /*
8796 * If we didn't find an unused CRTC, don't use any.
8797 */
8798 if (!crtc) {
8799 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8800 goto fail_unlock;
8801 }
8802
8803 ret = drm_modeset_lock(&crtc->mutex, ctx);
8804 if (ret)
8805 goto fail_unlock;
8806 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8807 if (ret)
8808 goto fail_unlock;
8809 intel_encoder->new_crtc = to_intel_crtc(crtc);
8810 to_intel_connector(connector)->new_encoder = intel_encoder;
8811
8812 intel_crtc = to_intel_crtc(crtc);
8813 intel_crtc->new_enabled = true;
8814 intel_crtc->new_config = intel_crtc->config;
8815 old->dpms_mode = connector->dpms;
8816 old->load_detect_temp = true;
8817 old->release_fb = NULL;
8818
8819 if (!mode)
8820 mode = &load_detect_mode;
8821
8822 /* We need a framebuffer large enough to accommodate all accesses
8823 * that the plane may generate whilst we perform load detection.
8824 * We can not rely on the fbcon either being present (we get called
8825 * during its initialisation to detect all boot displays, or it may
8826 * not even exist) or that it is large enough to satisfy the
8827 * requested mode.
8828 */
8829 fb = mode_fits_in_fbdev(dev, mode);
8830 if (fb == NULL) {
8831 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8832 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8833 old->release_fb = fb;
8834 } else
8835 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8836 if (IS_ERR(fb)) {
8837 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8838 goto fail;
8839 }
8840
8841 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8842 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8843 if (old->release_fb)
8844 old->release_fb->funcs->destroy(old->release_fb);
8845 goto fail;
8846 }
8847
8848 /* let the connector get through one full cycle before testing */
8849 intel_wait_for_vblank(dev, intel_crtc->pipe);
8850 return true;
8851
8852 fail:
8853 intel_crtc->new_enabled = crtc->state->enable;
8854 if (intel_crtc->new_enabled)
8855 intel_crtc->new_config = intel_crtc->config;
8856 else
8857 intel_crtc->new_config = NULL;
8858 fail_unlock:
8859 if (ret == -EDEADLK) {
8860 drm_modeset_backoff(ctx);
8861 goto retry;
8862 }
8863
8864 return false;
8865 }
8866
8867 void intel_release_load_detect_pipe(struct drm_connector *connector,
8868 struct intel_load_detect_pipe *old)
8869 {
8870 struct intel_encoder *intel_encoder =
8871 intel_attached_encoder(connector);
8872 struct drm_encoder *encoder = &intel_encoder->base;
8873 struct drm_crtc *crtc = encoder->crtc;
8874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8875
8876 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8877 connector->base.id, connector->name,
8878 encoder->base.id, encoder->name);
8879
8880 if (old->load_detect_temp) {
8881 to_intel_connector(connector)->new_encoder = NULL;
8882 intel_encoder->new_crtc = NULL;
8883 intel_crtc->new_enabled = false;
8884 intel_crtc->new_config = NULL;
8885 intel_set_mode(crtc, NULL, 0, 0, NULL);
8886
8887 if (old->release_fb) {
8888 drm_framebuffer_unregister_private(old->release_fb);
8889 drm_framebuffer_unreference(old->release_fb);
8890 }
8891
8892 return;
8893 }
8894
8895 /* Switch crtc and encoder back off if necessary */
8896 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8897 connector->funcs->dpms(connector, old->dpms_mode);
8898 }
8899
8900 static int i9xx_pll_refclk(struct drm_device *dev,
8901 const struct intel_crtc_state *pipe_config)
8902 {
8903 struct drm_i915_private *dev_priv = dev->dev_private;
8904 u32 dpll = pipe_config->dpll_hw_state.dpll;
8905
8906 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8907 return dev_priv->vbt.lvds_ssc_freq;
8908 else if (HAS_PCH_SPLIT(dev))
8909 return 120000;
8910 else if (!IS_GEN2(dev))
8911 return 96000;
8912 else
8913 return 48000;
8914 }
8915
8916 /* Returns the clock of the currently programmed mode of the given pipe. */
8917 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8918 struct intel_crtc_state *pipe_config)
8919 {
8920 struct drm_device *dev = crtc->base.dev;
8921 struct drm_i915_private *dev_priv = dev->dev_private;
8922 int pipe = pipe_config->cpu_transcoder;
8923 u32 dpll = pipe_config->dpll_hw_state.dpll;
8924 u32 fp;
8925 intel_clock_t clock;
8926 int refclk = i9xx_pll_refclk(dev, pipe_config);
8927
8928 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8929 fp = pipe_config->dpll_hw_state.fp0;
8930 else
8931 fp = pipe_config->dpll_hw_state.fp1;
8932
8933 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8934 if (IS_PINEVIEW(dev)) {
8935 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8936 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8937 } else {
8938 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8939 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8940 }
8941
8942 if (!IS_GEN2(dev)) {
8943 if (IS_PINEVIEW(dev))
8944 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8945 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8946 else
8947 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8948 DPLL_FPA01_P1_POST_DIV_SHIFT);
8949
8950 switch (dpll & DPLL_MODE_MASK) {
8951 case DPLLB_MODE_DAC_SERIAL:
8952 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8953 5 : 10;
8954 break;
8955 case DPLLB_MODE_LVDS:
8956 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8957 7 : 14;
8958 break;
8959 default:
8960 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8961 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8962 return;
8963 }
8964
8965 if (IS_PINEVIEW(dev))
8966 pineview_clock(refclk, &clock);
8967 else
8968 i9xx_clock(refclk, &clock);
8969 } else {
8970 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8971 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8972
8973 if (is_lvds) {
8974 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8975 DPLL_FPA01_P1_POST_DIV_SHIFT);
8976
8977 if (lvds & LVDS_CLKB_POWER_UP)
8978 clock.p2 = 7;
8979 else
8980 clock.p2 = 14;
8981 } else {
8982 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8983 clock.p1 = 2;
8984 else {
8985 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8986 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8987 }
8988 if (dpll & PLL_P2_DIVIDE_BY_4)
8989 clock.p2 = 4;
8990 else
8991 clock.p2 = 2;
8992 }
8993
8994 i9xx_clock(refclk, &clock);
8995 }
8996
8997 /*
8998 * This value includes pixel_multiplier. We will use
8999 * port_clock to compute adjusted_mode.crtc_clock in the
9000 * encoder's get_config() function.
9001 */
9002 pipe_config->port_clock = clock.dot;
9003 }
9004
9005 int intel_dotclock_calculate(int link_freq,
9006 const struct intel_link_m_n *m_n)
9007 {
9008 /*
9009 * The calculation for the data clock is:
9010 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9011 * But we want to avoid losing precison if possible, so:
9012 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9013 *
9014 * and the link clock is simpler:
9015 * link_clock = (m * link_clock) / n
9016 */
9017
9018 if (!m_n->link_n)
9019 return 0;
9020
9021 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9022 }
9023
9024 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9025 struct intel_crtc_state *pipe_config)
9026 {
9027 struct drm_device *dev = crtc->base.dev;
9028
9029 /* read out port_clock from the DPLL */
9030 i9xx_crtc_clock_get(crtc, pipe_config);
9031
9032 /*
9033 * This value does not include pixel_multiplier.
9034 * We will check that port_clock and adjusted_mode.crtc_clock
9035 * agree once we know their relationship in the encoder's
9036 * get_config() function.
9037 */
9038 pipe_config->base.adjusted_mode.crtc_clock =
9039 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9040 &pipe_config->fdi_m_n);
9041 }
9042
9043 /** Returns the currently programmed mode of the given pipe. */
9044 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9045 struct drm_crtc *crtc)
9046 {
9047 struct drm_i915_private *dev_priv = dev->dev_private;
9048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9049 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9050 struct drm_display_mode *mode;
9051 struct intel_crtc_state pipe_config;
9052 int htot = I915_READ(HTOTAL(cpu_transcoder));
9053 int hsync = I915_READ(HSYNC(cpu_transcoder));
9054 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9055 int vsync = I915_READ(VSYNC(cpu_transcoder));
9056 enum pipe pipe = intel_crtc->pipe;
9057
9058 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9059 if (!mode)
9060 return NULL;
9061
9062 /*
9063 * Construct a pipe_config sufficient for getting the clock info
9064 * back out of crtc_clock_get.
9065 *
9066 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9067 * to use a real value here instead.
9068 */
9069 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9070 pipe_config.pixel_multiplier = 1;
9071 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9072 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9073 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9074 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9075
9076 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9077 mode->hdisplay = (htot & 0xffff) + 1;
9078 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9079 mode->hsync_start = (hsync & 0xffff) + 1;
9080 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9081 mode->vdisplay = (vtot & 0xffff) + 1;
9082 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9083 mode->vsync_start = (vsync & 0xffff) + 1;
9084 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9085
9086 drm_mode_set_name(mode);
9087
9088 return mode;
9089 }
9090
9091 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9092 {
9093 struct drm_device *dev = crtc->dev;
9094 struct drm_i915_private *dev_priv = dev->dev_private;
9095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9096
9097 if (!HAS_GMCH_DISPLAY(dev))
9098 return;
9099
9100 if (!dev_priv->lvds_downclock_avail)
9101 return;
9102
9103 /*
9104 * Since this is called by a timer, we should never get here in
9105 * the manual case.
9106 */
9107 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9108 int pipe = intel_crtc->pipe;
9109 int dpll_reg = DPLL(pipe);
9110 int dpll;
9111
9112 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9113
9114 assert_panel_unlocked(dev_priv, pipe);
9115
9116 dpll = I915_READ(dpll_reg);
9117 dpll |= DISPLAY_RATE_SELECT_FPA1;
9118 I915_WRITE(dpll_reg, dpll);
9119 intel_wait_for_vblank(dev, pipe);
9120 dpll = I915_READ(dpll_reg);
9121 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9122 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9123 }
9124
9125 }
9126
9127 void intel_mark_busy(struct drm_device *dev)
9128 {
9129 struct drm_i915_private *dev_priv = dev->dev_private;
9130
9131 if (dev_priv->mm.busy)
9132 return;
9133
9134 intel_runtime_pm_get(dev_priv);
9135 i915_update_gfx_val(dev_priv);
9136 dev_priv->mm.busy = true;
9137 }
9138
9139 void intel_mark_idle(struct drm_device *dev)
9140 {
9141 struct drm_i915_private *dev_priv = dev->dev_private;
9142 struct drm_crtc *crtc;
9143
9144 if (!dev_priv->mm.busy)
9145 return;
9146
9147 dev_priv->mm.busy = false;
9148
9149 if (!i915.powersave)
9150 goto out;
9151
9152 for_each_crtc(dev, crtc) {
9153 if (!crtc->primary->fb)
9154 continue;
9155
9156 intel_decrease_pllclock(crtc);
9157 }
9158
9159 if (INTEL_INFO(dev)->gen >= 6)
9160 gen6_rps_idle(dev->dev_private);
9161
9162 out:
9163 intel_runtime_pm_put(dev_priv);
9164 }
9165
9166 static void intel_crtc_set_state(struct intel_crtc *crtc,
9167 struct intel_crtc_state *crtc_state)
9168 {
9169 kfree(crtc->config);
9170 crtc->config = crtc_state;
9171 crtc->base.state = &crtc_state->base;
9172 }
9173
9174 static void intel_crtc_destroy(struct drm_crtc *crtc)
9175 {
9176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9177 struct drm_device *dev = crtc->dev;
9178 struct intel_unpin_work *work;
9179
9180 spin_lock_irq(&dev->event_lock);
9181 work = intel_crtc->unpin_work;
9182 intel_crtc->unpin_work = NULL;
9183 spin_unlock_irq(&dev->event_lock);
9184
9185 if (work) {
9186 cancel_work_sync(&work->work);
9187 kfree(work);
9188 }
9189
9190 intel_crtc_set_state(intel_crtc, NULL);
9191 drm_crtc_cleanup(crtc);
9192
9193 kfree(intel_crtc);
9194 }
9195
9196 static void intel_unpin_work_fn(struct work_struct *__work)
9197 {
9198 struct intel_unpin_work *work =
9199 container_of(__work, struct intel_unpin_work, work);
9200 struct drm_device *dev = work->crtc->dev;
9201 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9202
9203 mutex_lock(&dev->struct_mutex);
9204 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9205 drm_gem_object_unreference(&work->pending_flip_obj->base);
9206 drm_framebuffer_unreference(work->old_fb);
9207
9208 intel_fbc_update(dev);
9209
9210 if (work->flip_queued_req)
9211 i915_gem_request_assign(&work->flip_queued_req, NULL);
9212 mutex_unlock(&dev->struct_mutex);
9213
9214 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9215
9216 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9217 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9218
9219 kfree(work);
9220 }
9221
9222 static void do_intel_finish_page_flip(struct drm_device *dev,
9223 struct drm_crtc *crtc)
9224 {
9225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9226 struct intel_unpin_work *work;
9227 unsigned long flags;
9228
9229 /* Ignore early vblank irqs */
9230 if (intel_crtc == NULL)
9231 return;
9232
9233 /*
9234 * This is called both by irq handlers and the reset code (to complete
9235 * lost pageflips) so needs the full irqsave spinlocks.
9236 */
9237 spin_lock_irqsave(&dev->event_lock, flags);
9238 work = intel_crtc->unpin_work;
9239
9240 /* Ensure we don't miss a work->pending update ... */
9241 smp_rmb();
9242
9243 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9244 spin_unlock_irqrestore(&dev->event_lock, flags);
9245 return;
9246 }
9247
9248 page_flip_completed(intel_crtc);
9249
9250 spin_unlock_irqrestore(&dev->event_lock, flags);
9251 }
9252
9253 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9254 {
9255 struct drm_i915_private *dev_priv = dev->dev_private;
9256 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9257
9258 do_intel_finish_page_flip(dev, crtc);
9259 }
9260
9261 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9262 {
9263 struct drm_i915_private *dev_priv = dev->dev_private;
9264 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9265
9266 do_intel_finish_page_flip(dev, crtc);
9267 }
9268
9269 /* Is 'a' after or equal to 'b'? */
9270 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9271 {
9272 return !((a - b) & 0x80000000);
9273 }
9274
9275 static bool page_flip_finished(struct intel_crtc *crtc)
9276 {
9277 struct drm_device *dev = crtc->base.dev;
9278 struct drm_i915_private *dev_priv = dev->dev_private;
9279
9280 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9281 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9282 return true;
9283
9284 /*
9285 * The relevant registers doen't exist on pre-ctg.
9286 * As the flip done interrupt doesn't trigger for mmio
9287 * flips on gmch platforms, a flip count check isn't
9288 * really needed there. But since ctg has the registers,
9289 * include it in the check anyway.
9290 */
9291 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9292 return true;
9293
9294 /*
9295 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9296 * used the same base address. In that case the mmio flip might
9297 * have completed, but the CS hasn't even executed the flip yet.
9298 *
9299 * A flip count check isn't enough as the CS might have updated
9300 * the base address just after start of vblank, but before we
9301 * managed to process the interrupt. This means we'd complete the
9302 * CS flip too soon.
9303 *
9304 * Combining both checks should get us a good enough result. It may
9305 * still happen that the CS flip has been executed, but has not
9306 * yet actually completed. But in case the base address is the same
9307 * anyway, we don't really care.
9308 */
9309 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9310 crtc->unpin_work->gtt_offset &&
9311 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9312 crtc->unpin_work->flip_count);
9313 }
9314
9315 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9316 {
9317 struct drm_i915_private *dev_priv = dev->dev_private;
9318 struct intel_crtc *intel_crtc =
9319 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9320 unsigned long flags;
9321
9322
9323 /*
9324 * This is called both by irq handlers and the reset code (to complete
9325 * lost pageflips) so needs the full irqsave spinlocks.
9326 *
9327 * NB: An MMIO update of the plane base pointer will also
9328 * generate a page-flip completion irq, i.e. every modeset
9329 * is also accompanied by a spurious intel_prepare_page_flip().
9330 */
9331 spin_lock_irqsave(&dev->event_lock, flags);
9332 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9333 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9334 spin_unlock_irqrestore(&dev->event_lock, flags);
9335 }
9336
9337 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9338 {
9339 /* Ensure that the work item is consistent when activating it ... */
9340 smp_wmb();
9341 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9342 /* and that it is marked active as soon as the irq could fire. */
9343 smp_wmb();
9344 }
9345
9346 static int intel_gen2_queue_flip(struct drm_device *dev,
9347 struct drm_crtc *crtc,
9348 struct drm_framebuffer *fb,
9349 struct drm_i915_gem_object *obj,
9350 struct intel_engine_cs *ring,
9351 uint32_t flags)
9352 {
9353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9354 u32 flip_mask;
9355 int ret;
9356
9357 ret = intel_ring_begin(ring, 6);
9358 if (ret)
9359 return ret;
9360
9361 /* Can't queue multiple flips, so wait for the previous
9362 * one to finish before executing the next.
9363 */
9364 if (intel_crtc->plane)
9365 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9366 else
9367 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9368 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9369 intel_ring_emit(ring, MI_NOOP);
9370 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9371 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9372 intel_ring_emit(ring, fb->pitches[0]);
9373 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9374 intel_ring_emit(ring, 0); /* aux display base address, unused */
9375
9376 intel_mark_page_flip_active(intel_crtc);
9377 __intel_ring_advance(ring);
9378 return 0;
9379 }
9380
9381 static int intel_gen3_queue_flip(struct drm_device *dev,
9382 struct drm_crtc *crtc,
9383 struct drm_framebuffer *fb,
9384 struct drm_i915_gem_object *obj,
9385 struct intel_engine_cs *ring,
9386 uint32_t flags)
9387 {
9388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9389 u32 flip_mask;
9390 int ret;
9391
9392 ret = intel_ring_begin(ring, 6);
9393 if (ret)
9394 return ret;
9395
9396 if (intel_crtc->plane)
9397 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9398 else
9399 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9400 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9401 intel_ring_emit(ring, MI_NOOP);
9402 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9403 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9404 intel_ring_emit(ring, fb->pitches[0]);
9405 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9406 intel_ring_emit(ring, MI_NOOP);
9407
9408 intel_mark_page_flip_active(intel_crtc);
9409 __intel_ring_advance(ring);
9410 return 0;
9411 }
9412
9413 static int intel_gen4_queue_flip(struct drm_device *dev,
9414 struct drm_crtc *crtc,
9415 struct drm_framebuffer *fb,
9416 struct drm_i915_gem_object *obj,
9417 struct intel_engine_cs *ring,
9418 uint32_t flags)
9419 {
9420 struct drm_i915_private *dev_priv = dev->dev_private;
9421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9422 uint32_t pf, pipesrc;
9423 int ret;
9424
9425 ret = intel_ring_begin(ring, 4);
9426 if (ret)
9427 return ret;
9428
9429 /* i965+ uses the linear or tiled offsets from the
9430 * Display Registers (which do not change across a page-flip)
9431 * so we need only reprogram the base address.
9432 */
9433 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9434 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9435 intel_ring_emit(ring, fb->pitches[0]);
9436 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9437 obj->tiling_mode);
9438
9439 /* XXX Enabling the panel-fitter across page-flip is so far
9440 * untested on non-native modes, so ignore it for now.
9441 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9442 */
9443 pf = 0;
9444 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9445 intel_ring_emit(ring, pf | pipesrc);
9446
9447 intel_mark_page_flip_active(intel_crtc);
9448 __intel_ring_advance(ring);
9449 return 0;
9450 }
9451
9452 static int intel_gen6_queue_flip(struct drm_device *dev,
9453 struct drm_crtc *crtc,
9454 struct drm_framebuffer *fb,
9455 struct drm_i915_gem_object *obj,
9456 struct intel_engine_cs *ring,
9457 uint32_t flags)
9458 {
9459 struct drm_i915_private *dev_priv = dev->dev_private;
9460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9461 uint32_t pf, pipesrc;
9462 int ret;
9463
9464 ret = intel_ring_begin(ring, 4);
9465 if (ret)
9466 return ret;
9467
9468 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9469 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9470 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9471 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9472
9473 /* Contrary to the suggestions in the documentation,
9474 * "Enable Panel Fitter" does not seem to be required when page
9475 * flipping with a non-native mode, and worse causes a normal
9476 * modeset to fail.
9477 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9478 */
9479 pf = 0;
9480 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9481 intel_ring_emit(ring, pf | pipesrc);
9482
9483 intel_mark_page_flip_active(intel_crtc);
9484 __intel_ring_advance(ring);
9485 return 0;
9486 }
9487
9488 static int intel_gen7_queue_flip(struct drm_device *dev,
9489 struct drm_crtc *crtc,
9490 struct drm_framebuffer *fb,
9491 struct drm_i915_gem_object *obj,
9492 struct intel_engine_cs *ring,
9493 uint32_t flags)
9494 {
9495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9496 uint32_t plane_bit = 0;
9497 int len, ret;
9498
9499 switch (intel_crtc->plane) {
9500 case PLANE_A:
9501 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9502 break;
9503 case PLANE_B:
9504 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9505 break;
9506 case PLANE_C:
9507 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9508 break;
9509 default:
9510 WARN_ONCE(1, "unknown plane in flip command\n");
9511 return -ENODEV;
9512 }
9513
9514 len = 4;
9515 if (ring->id == RCS) {
9516 len += 6;
9517 /*
9518 * On Gen 8, SRM is now taking an extra dword to accommodate
9519 * 48bits addresses, and we need a NOOP for the batch size to
9520 * stay even.
9521 */
9522 if (IS_GEN8(dev))
9523 len += 2;
9524 }
9525
9526 /*
9527 * BSpec MI_DISPLAY_FLIP for IVB:
9528 * "The full packet must be contained within the same cache line."
9529 *
9530 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9531 * cacheline, if we ever start emitting more commands before
9532 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9533 * then do the cacheline alignment, and finally emit the
9534 * MI_DISPLAY_FLIP.
9535 */
9536 ret = intel_ring_cacheline_align(ring);
9537 if (ret)
9538 return ret;
9539
9540 ret = intel_ring_begin(ring, len);
9541 if (ret)
9542 return ret;
9543
9544 /* Unmask the flip-done completion message. Note that the bspec says that
9545 * we should do this for both the BCS and RCS, and that we must not unmask
9546 * more than one flip event at any time (or ensure that one flip message
9547 * can be sent by waiting for flip-done prior to queueing new flips).
9548 * Experimentation says that BCS works despite DERRMR masking all
9549 * flip-done completion events and that unmasking all planes at once
9550 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9551 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9552 */
9553 if (ring->id == RCS) {
9554 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9555 intel_ring_emit(ring, DERRMR);
9556 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9557 DERRMR_PIPEB_PRI_FLIP_DONE |
9558 DERRMR_PIPEC_PRI_FLIP_DONE));
9559 if (IS_GEN8(dev))
9560 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9561 MI_SRM_LRM_GLOBAL_GTT);
9562 else
9563 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9564 MI_SRM_LRM_GLOBAL_GTT);
9565 intel_ring_emit(ring, DERRMR);
9566 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9567 if (IS_GEN8(dev)) {
9568 intel_ring_emit(ring, 0);
9569 intel_ring_emit(ring, MI_NOOP);
9570 }
9571 }
9572
9573 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9574 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9575 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9576 intel_ring_emit(ring, (MI_NOOP));
9577
9578 intel_mark_page_flip_active(intel_crtc);
9579 __intel_ring_advance(ring);
9580 return 0;
9581 }
9582
9583 static bool use_mmio_flip(struct intel_engine_cs *ring,
9584 struct drm_i915_gem_object *obj)
9585 {
9586 /*
9587 * This is not being used for older platforms, because
9588 * non-availability of flip done interrupt forces us to use
9589 * CS flips. Older platforms derive flip done using some clever
9590 * tricks involving the flip_pending status bits and vblank irqs.
9591 * So using MMIO flips there would disrupt this mechanism.
9592 */
9593
9594 if (ring == NULL)
9595 return true;
9596
9597 if (INTEL_INFO(ring->dev)->gen < 5)
9598 return false;
9599
9600 if (i915.use_mmio_flip < 0)
9601 return false;
9602 else if (i915.use_mmio_flip > 0)
9603 return true;
9604 else if (i915.enable_execlists)
9605 return true;
9606 else
9607 return ring != i915_gem_request_get_ring(obj->last_read_req);
9608 }
9609
9610 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9611 {
9612 struct drm_device *dev = intel_crtc->base.dev;
9613 struct drm_i915_private *dev_priv = dev->dev_private;
9614 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9615 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9616 struct drm_i915_gem_object *obj = intel_fb->obj;
9617 const enum pipe pipe = intel_crtc->pipe;
9618 u32 ctl, stride;
9619
9620 ctl = I915_READ(PLANE_CTL(pipe, 0));
9621 ctl &= ~PLANE_CTL_TILED_MASK;
9622 if (obj->tiling_mode == I915_TILING_X)
9623 ctl |= PLANE_CTL_TILED_X;
9624
9625 /*
9626 * The stride is either expressed as a multiple of 64 bytes chunks for
9627 * linear buffers or in number of tiles for tiled buffers.
9628 */
9629 stride = fb->pitches[0] >> 6;
9630 if (obj->tiling_mode == I915_TILING_X)
9631 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9632
9633 /*
9634 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9635 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9636 */
9637 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9638 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9639
9640 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9641 POSTING_READ(PLANE_SURF(pipe, 0));
9642 }
9643
9644 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9645 {
9646 struct drm_device *dev = intel_crtc->base.dev;
9647 struct drm_i915_private *dev_priv = dev->dev_private;
9648 struct intel_framebuffer *intel_fb =
9649 to_intel_framebuffer(intel_crtc->base.primary->fb);
9650 struct drm_i915_gem_object *obj = intel_fb->obj;
9651 u32 dspcntr;
9652 u32 reg;
9653
9654 reg = DSPCNTR(intel_crtc->plane);
9655 dspcntr = I915_READ(reg);
9656
9657 if (obj->tiling_mode != I915_TILING_NONE)
9658 dspcntr |= DISPPLANE_TILED;
9659 else
9660 dspcntr &= ~DISPPLANE_TILED;
9661
9662 I915_WRITE(reg, dspcntr);
9663
9664 I915_WRITE(DSPSURF(intel_crtc->plane),
9665 intel_crtc->unpin_work->gtt_offset);
9666 POSTING_READ(DSPSURF(intel_crtc->plane));
9667
9668 }
9669
9670 /*
9671 * XXX: This is the temporary way to update the plane registers until we get
9672 * around to using the usual plane update functions for MMIO flips
9673 */
9674 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9675 {
9676 struct drm_device *dev = intel_crtc->base.dev;
9677 bool atomic_update;
9678 u32 start_vbl_count;
9679
9680 intel_mark_page_flip_active(intel_crtc);
9681
9682 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9683
9684 if (INTEL_INFO(dev)->gen >= 9)
9685 skl_do_mmio_flip(intel_crtc);
9686 else
9687 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9688 ilk_do_mmio_flip(intel_crtc);
9689
9690 if (atomic_update)
9691 intel_pipe_update_end(intel_crtc, start_vbl_count);
9692 }
9693
9694 static void intel_mmio_flip_work_func(struct work_struct *work)
9695 {
9696 struct intel_crtc *crtc =
9697 container_of(work, struct intel_crtc, mmio_flip.work);
9698 struct intel_mmio_flip *mmio_flip;
9699
9700 mmio_flip = &crtc->mmio_flip;
9701 if (mmio_flip->req)
9702 WARN_ON(__i915_wait_request(mmio_flip->req,
9703 crtc->reset_counter,
9704 false, NULL, NULL) != 0);
9705
9706 intel_do_mmio_flip(crtc);
9707 if (mmio_flip->req) {
9708 mutex_lock(&crtc->base.dev->struct_mutex);
9709 i915_gem_request_assign(&mmio_flip->req, NULL);
9710 mutex_unlock(&crtc->base.dev->struct_mutex);
9711 }
9712 }
9713
9714 static int intel_queue_mmio_flip(struct drm_device *dev,
9715 struct drm_crtc *crtc,
9716 struct drm_framebuffer *fb,
9717 struct drm_i915_gem_object *obj,
9718 struct intel_engine_cs *ring,
9719 uint32_t flags)
9720 {
9721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9722
9723 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9724 obj->last_write_req);
9725
9726 schedule_work(&intel_crtc->mmio_flip.work);
9727
9728 return 0;
9729 }
9730
9731 static int intel_default_queue_flip(struct drm_device *dev,
9732 struct drm_crtc *crtc,
9733 struct drm_framebuffer *fb,
9734 struct drm_i915_gem_object *obj,
9735 struct intel_engine_cs *ring,
9736 uint32_t flags)
9737 {
9738 return -ENODEV;
9739 }
9740
9741 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9742 struct drm_crtc *crtc)
9743 {
9744 struct drm_i915_private *dev_priv = dev->dev_private;
9745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9746 struct intel_unpin_work *work = intel_crtc->unpin_work;
9747 u32 addr;
9748
9749 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9750 return true;
9751
9752 if (!work->enable_stall_check)
9753 return false;
9754
9755 if (work->flip_ready_vblank == 0) {
9756 if (work->flip_queued_req &&
9757 !i915_gem_request_completed(work->flip_queued_req, true))
9758 return false;
9759
9760 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9761 }
9762
9763 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9764 return false;
9765
9766 /* Potential stall - if we see that the flip has happened,
9767 * assume a missed interrupt. */
9768 if (INTEL_INFO(dev)->gen >= 4)
9769 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9770 else
9771 addr = I915_READ(DSPADDR(intel_crtc->plane));
9772
9773 /* There is a potential issue here with a false positive after a flip
9774 * to the same address. We could address this by checking for a
9775 * non-incrementing frame counter.
9776 */
9777 return addr == work->gtt_offset;
9778 }
9779
9780 void intel_check_page_flip(struct drm_device *dev, int pipe)
9781 {
9782 struct drm_i915_private *dev_priv = dev->dev_private;
9783 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9785
9786 WARN_ON(!in_irq());
9787
9788 if (crtc == NULL)
9789 return;
9790
9791 spin_lock(&dev->event_lock);
9792 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9793 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9794 intel_crtc->unpin_work->flip_queued_vblank,
9795 drm_vblank_count(dev, pipe));
9796 page_flip_completed(intel_crtc);
9797 }
9798 spin_unlock(&dev->event_lock);
9799 }
9800
9801 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9802 struct drm_framebuffer *fb,
9803 struct drm_pending_vblank_event *event,
9804 uint32_t page_flip_flags)
9805 {
9806 struct drm_device *dev = crtc->dev;
9807 struct drm_i915_private *dev_priv = dev->dev_private;
9808 struct drm_framebuffer *old_fb = crtc->primary->fb;
9809 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9811 struct drm_plane *primary = crtc->primary;
9812 enum pipe pipe = intel_crtc->pipe;
9813 struct intel_unpin_work *work;
9814 struct intel_engine_cs *ring;
9815 int ret;
9816
9817 /*
9818 * drm_mode_page_flip_ioctl() should already catch this, but double
9819 * check to be safe. In the future we may enable pageflipping from
9820 * a disabled primary plane.
9821 */
9822 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9823 return -EBUSY;
9824
9825 /* Can't change pixel format via MI display flips. */
9826 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9827 return -EINVAL;
9828
9829 /*
9830 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9831 * Note that pitch changes could also affect these register.
9832 */
9833 if (INTEL_INFO(dev)->gen > 3 &&
9834 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9835 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9836 return -EINVAL;
9837
9838 if (i915_terminally_wedged(&dev_priv->gpu_error))
9839 goto out_hang;
9840
9841 work = kzalloc(sizeof(*work), GFP_KERNEL);
9842 if (work == NULL)
9843 return -ENOMEM;
9844
9845 work->event = event;
9846 work->crtc = crtc;
9847 work->old_fb = old_fb;
9848 INIT_WORK(&work->work, intel_unpin_work_fn);
9849
9850 ret = drm_crtc_vblank_get(crtc);
9851 if (ret)
9852 goto free_work;
9853
9854 /* We borrow the event spin lock for protecting unpin_work */
9855 spin_lock_irq(&dev->event_lock);
9856 if (intel_crtc->unpin_work) {
9857 /* Before declaring the flip queue wedged, check if
9858 * the hardware completed the operation behind our backs.
9859 */
9860 if (__intel_pageflip_stall_check(dev, crtc)) {
9861 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9862 page_flip_completed(intel_crtc);
9863 } else {
9864 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9865 spin_unlock_irq(&dev->event_lock);
9866
9867 drm_crtc_vblank_put(crtc);
9868 kfree(work);
9869 return -EBUSY;
9870 }
9871 }
9872 intel_crtc->unpin_work = work;
9873 spin_unlock_irq(&dev->event_lock);
9874
9875 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9876 flush_workqueue(dev_priv->wq);
9877
9878 ret = i915_mutex_lock_interruptible(dev);
9879 if (ret)
9880 goto cleanup;
9881
9882 /* Reference the objects for the scheduled work. */
9883 drm_framebuffer_reference(work->old_fb);
9884 drm_gem_object_reference(&obj->base);
9885
9886 crtc->primary->fb = fb;
9887 update_state_fb(crtc->primary);
9888
9889 work->pending_flip_obj = obj;
9890
9891 atomic_inc(&intel_crtc->unpin_work_count);
9892 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9893
9894 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9895 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9896
9897 if (IS_VALLEYVIEW(dev)) {
9898 ring = &dev_priv->ring[BCS];
9899 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9900 /* vlv: DISPLAY_FLIP fails to change tiling */
9901 ring = NULL;
9902 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9903 ring = &dev_priv->ring[BCS];
9904 } else if (INTEL_INFO(dev)->gen >= 7) {
9905 ring = i915_gem_request_get_ring(obj->last_read_req);
9906 if (ring == NULL || ring->id != RCS)
9907 ring = &dev_priv->ring[BCS];
9908 } else {
9909 ring = &dev_priv->ring[RCS];
9910 }
9911
9912 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9913 if (ret)
9914 goto cleanup_pending;
9915
9916 work->gtt_offset =
9917 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9918
9919 if (use_mmio_flip(ring, obj)) {
9920 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9921 page_flip_flags);
9922 if (ret)
9923 goto cleanup_unpin;
9924
9925 i915_gem_request_assign(&work->flip_queued_req,
9926 obj->last_write_req);
9927 } else {
9928 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9929 page_flip_flags);
9930 if (ret)
9931 goto cleanup_unpin;
9932
9933 i915_gem_request_assign(&work->flip_queued_req,
9934 intel_ring_get_request(ring));
9935 }
9936
9937 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
9938 work->enable_stall_check = true;
9939
9940 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9941 INTEL_FRONTBUFFER_PRIMARY(pipe));
9942
9943 intel_fbc_disable(dev);
9944 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9945 mutex_unlock(&dev->struct_mutex);
9946
9947 trace_i915_flip_request(intel_crtc->plane, obj);
9948
9949 return 0;
9950
9951 cleanup_unpin:
9952 intel_unpin_fb_obj(obj);
9953 cleanup_pending:
9954 atomic_dec(&intel_crtc->unpin_work_count);
9955 crtc->primary->fb = old_fb;
9956 update_state_fb(crtc->primary);
9957 drm_framebuffer_unreference(work->old_fb);
9958 drm_gem_object_unreference(&obj->base);
9959 mutex_unlock(&dev->struct_mutex);
9960
9961 cleanup:
9962 spin_lock_irq(&dev->event_lock);
9963 intel_crtc->unpin_work = NULL;
9964 spin_unlock_irq(&dev->event_lock);
9965
9966 drm_crtc_vblank_put(crtc);
9967 free_work:
9968 kfree(work);
9969
9970 if (ret == -EIO) {
9971 out_hang:
9972 ret = intel_plane_restore(primary);
9973 if (ret == 0 && event) {
9974 spin_lock_irq(&dev->event_lock);
9975 drm_send_vblank_event(dev, pipe, event);
9976 spin_unlock_irq(&dev->event_lock);
9977 }
9978 }
9979 return ret;
9980 }
9981
9982 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9983 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9984 .load_lut = intel_crtc_load_lut,
9985 .atomic_begin = intel_begin_crtc_commit,
9986 .atomic_flush = intel_finish_crtc_commit,
9987 };
9988
9989 /**
9990 * intel_modeset_update_staged_output_state
9991 *
9992 * Updates the staged output configuration state, e.g. after we've read out the
9993 * current hw state.
9994 */
9995 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9996 {
9997 struct intel_crtc *crtc;
9998 struct intel_encoder *encoder;
9999 struct intel_connector *connector;
10000
10001 list_for_each_entry(connector, &dev->mode_config.connector_list,
10002 base.head) {
10003 connector->new_encoder =
10004 to_intel_encoder(connector->base.encoder);
10005 }
10006
10007 for_each_intel_encoder(dev, encoder) {
10008 encoder->new_crtc =
10009 to_intel_crtc(encoder->base.crtc);
10010 }
10011
10012 for_each_intel_crtc(dev, crtc) {
10013 crtc->new_enabled = crtc->base.state->enable;
10014
10015 if (crtc->new_enabled)
10016 crtc->new_config = crtc->config;
10017 else
10018 crtc->new_config = NULL;
10019 }
10020 }
10021
10022 /**
10023 * intel_modeset_commit_output_state
10024 *
10025 * This function copies the stage display pipe configuration to the real one.
10026 */
10027 static void intel_modeset_commit_output_state(struct drm_device *dev)
10028 {
10029 struct intel_crtc *crtc;
10030 struct intel_encoder *encoder;
10031 struct intel_connector *connector;
10032
10033 list_for_each_entry(connector, &dev->mode_config.connector_list,
10034 base.head) {
10035 connector->base.encoder = &connector->new_encoder->base;
10036 }
10037
10038 for_each_intel_encoder(dev, encoder) {
10039 encoder->base.crtc = &encoder->new_crtc->base;
10040 }
10041
10042 for_each_intel_crtc(dev, crtc) {
10043 crtc->base.state->enable = crtc->new_enabled;
10044 crtc->base.enabled = crtc->new_enabled;
10045 }
10046 }
10047
10048 static void
10049 connected_sink_compute_bpp(struct intel_connector *connector,
10050 struct intel_crtc_state *pipe_config)
10051 {
10052 int bpp = pipe_config->pipe_bpp;
10053
10054 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10055 connector->base.base.id,
10056 connector->base.name);
10057
10058 /* Don't use an invalid EDID bpc value */
10059 if (connector->base.display_info.bpc &&
10060 connector->base.display_info.bpc * 3 < bpp) {
10061 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10062 bpp, connector->base.display_info.bpc*3);
10063 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10064 }
10065
10066 /* Clamp bpp to 8 on screens without EDID 1.4 */
10067 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10068 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10069 bpp);
10070 pipe_config->pipe_bpp = 24;
10071 }
10072 }
10073
10074 static int
10075 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10076 struct drm_framebuffer *fb,
10077 struct intel_crtc_state *pipe_config)
10078 {
10079 struct drm_device *dev = crtc->base.dev;
10080 struct intel_connector *connector;
10081 int bpp;
10082
10083 switch (fb->pixel_format) {
10084 case DRM_FORMAT_C8:
10085 bpp = 8*3; /* since we go through a colormap */
10086 break;
10087 case DRM_FORMAT_XRGB1555:
10088 case DRM_FORMAT_ARGB1555:
10089 /* checked in intel_framebuffer_init already */
10090 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10091 return -EINVAL;
10092 case DRM_FORMAT_RGB565:
10093 bpp = 6*3; /* min is 18bpp */
10094 break;
10095 case DRM_FORMAT_XBGR8888:
10096 case DRM_FORMAT_ABGR8888:
10097 /* checked in intel_framebuffer_init already */
10098 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10099 return -EINVAL;
10100 case DRM_FORMAT_XRGB8888:
10101 case DRM_FORMAT_ARGB8888:
10102 bpp = 8*3;
10103 break;
10104 case DRM_FORMAT_XRGB2101010:
10105 case DRM_FORMAT_ARGB2101010:
10106 case DRM_FORMAT_XBGR2101010:
10107 case DRM_FORMAT_ABGR2101010:
10108 /* checked in intel_framebuffer_init already */
10109 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10110 return -EINVAL;
10111 bpp = 10*3;
10112 break;
10113 /* TODO: gen4+ supports 16 bpc floating point, too. */
10114 default:
10115 DRM_DEBUG_KMS("unsupported depth\n");
10116 return -EINVAL;
10117 }
10118
10119 pipe_config->pipe_bpp = bpp;
10120
10121 /* Clamp display bpp to EDID value */
10122 list_for_each_entry(connector, &dev->mode_config.connector_list,
10123 base.head) {
10124 if (!connector->new_encoder ||
10125 connector->new_encoder->new_crtc != crtc)
10126 continue;
10127
10128 connected_sink_compute_bpp(connector, pipe_config);
10129 }
10130
10131 return bpp;
10132 }
10133
10134 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10135 {
10136 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10137 "type: 0x%x flags: 0x%x\n",
10138 mode->crtc_clock,
10139 mode->crtc_hdisplay, mode->crtc_hsync_start,
10140 mode->crtc_hsync_end, mode->crtc_htotal,
10141 mode->crtc_vdisplay, mode->crtc_vsync_start,
10142 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10143 }
10144
10145 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10146 struct intel_crtc_state *pipe_config,
10147 const char *context)
10148 {
10149 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10150 context, pipe_name(crtc->pipe));
10151
10152 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10153 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10154 pipe_config->pipe_bpp, pipe_config->dither);
10155 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10156 pipe_config->has_pch_encoder,
10157 pipe_config->fdi_lanes,
10158 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10159 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10160 pipe_config->fdi_m_n.tu);
10161 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10162 pipe_config->has_dp_encoder,
10163 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10164 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10165 pipe_config->dp_m_n.tu);
10166
10167 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10168 pipe_config->has_dp_encoder,
10169 pipe_config->dp_m2_n2.gmch_m,
10170 pipe_config->dp_m2_n2.gmch_n,
10171 pipe_config->dp_m2_n2.link_m,
10172 pipe_config->dp_m2_n2.link_n,
10173 pipe_config->dp_m2_n2.tu);
10174
10175 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10176 pipe_config->has_audio,
10177 pipe_config->has_infoframe);
10178
10179 DRM_DEBUG_KMS("requested mode:\n");
10180 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10181 DRM_DEBUG_KMS("adjusted mode:\n");
10182 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10183 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10184 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10185 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10186 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10187 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10188 pipe_config->gmch_pfit.control,
10189 pipe_config->gmch_pfit.pgm_ratios,
10190 pipe_config->gmch_pfit.lvds_border_bits);
10191 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10192 pipe_config->pch_pfit.pos,
10193 pipe_config->pch_pfit.size,
10194 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10195 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10196 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10197 }
10198
10199 static bool encoders_cloneable(const struct intel_encoder *a,
10200 const struct intel_encoder *b)
10201 {
10202 /* masks could be asymmetric, so check both ways */
10203 return a == b || (a->cloneable & (1 << b->type) &&
10204 b->cloneable & (1 << a->type));
10205 }
10206
10207 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10208 struct intel_encoder *encoder)
10209 {
10210 struct drm_device *dev = crtc->base.dev;
10211 struct intel_encoder *source_encoder;
10212
10213 for_each_intel_encoder(dev, source_encoder) {
10214 if (source_encoder->new_crtc != crtc)
10215 continue;
10216
10217 if (!encoders_cloneable(encoder, source_encoder))
10218 return false;
10219 }
10220
10221 return true;
10222 }
10223
10224 static bool check_encoder_cloning(struct intel_crtc *crtc)
10225 {
10226 struct drm_device *dev = crtc->base.dev;
10227 struct intel_encoder *encoder;
10228
10229 for_each_intel_encoder(dev, encoder) {
10230 if (encoder->new_crtc != crtc)
10231 continue;
10232
10233 if (!check_single_encoder_cloning(crtc, encoder))
10234 return false;
10235 }
10236
10237 return true;
10238 }
10239
10240 static bool check_digital_port_conflicts(struct drm_device *dev)
10241 {
10242 struct intel_connector *connector;
10243 unsigned int used_ports = 0;
10244
10245 /*
10246 * Walk the connector list instead of the encoder
10247 * list to detect the problem on ddi platforms
10248 * where there's just one encoder per digital port.
10249 */
10250 list_for_each_entry(connector,
10251 &dev->mode_config.connector_list, base.head) {
10252 struct intel_encoder *encoder = connector->new_encoder;
10253
10254 if (!encoder)
10255 continue;
10256
10257 WARN_ON(!encoder->new_crtc);
10258
10259 switch (encoder->type) {
10260 unsigned int port_mask;
10261 case INTEL_OUTPUT_UNKNOWN:
10262 if (WARN_ON(!HAS_DDI(dev)))
10263 break;
10264 case INTEL_OUTPUT_DISPLAYPORT:
10265 case INTEL_OUTPUT_HDMI:
10266 case INTEL_OUTPUT_EDP:
10267 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10268
10269 /* the same port mustn't appear more than once */
10270 if (used_ports & port_mask)
10271 return false;
10272
10273 used_ports |= port_mask;
10274 default:
10275 break;
10276 }
10277 }
10278
10279 return true;
10280 }
10281
10282 static struct intel_crtc_state *
10283 intel_modeset_pipe_config(struct drm_crtc *crtc,
10284 struct drm_framebuffer *fb,
10285 struct drm_display_mode *mode)
10286 {
10287 struct drm_device *dev = crtc->dev;
10288 struct intel_encoder *encoder;
10289 struct intel_crtc_state *pipe_config;
10290 int plane_bpp, ret = -EINVAL;
10291 bool retry = true;
10292
10293 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10294 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10295 return ERR_PTR(-EINVAL);
10296 }
10297
10298 if (!check_digital_port_conflicts(dev)) {
10299 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10300 return ERR_PTR(-EINVAL);
10301 }
10302
10303 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10304 if (!pipe_config)
10305 return ERR_PTR(-ENOMEM);
10306
10307 pipe_config->base.crtc = crtc;
10308 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10309 drm_mode_copy(&pipe_config->base.mode, mode);
10310
10311 pipe_config->cpu_transcoder =
10312 (enum transcoder) to_intel_crtc(crtc)->pipe;
10313 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10314
10315 /*
10316 * Sanitize sync polarity flags based on requested ones. If neither
10317 * positive or negative polarity is requested, treat this as meaning
10318 * negative polarity.
10319 */
10320 if (!(pipe_config->base.adjusted_mode.flags &
10321 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10322 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10323
10324 if (!(pipe_config->base.adjusted_mode.flags &
10325 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10326 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10327
10328 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10329 * plane pixel format and any sink constraints into account. Returns the
10330 * source plane bpp so that dithering can be selected on mismatches
10331 * after encoders and crtc also have had their say. */
10332 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10333 fb, pipe_config);
10334 if (plane_bpp < 0)
10335 goto fail;
10336
10337 /*
10338 * Determine the real pipe dimensions. Note that stereo modes can
10339 * increase the actual pipe size due to the frame doubling and
10340 * insertion of additional space for blanks between the frame. This
10341 * is stored in the crtc timings. We use the requested mode to do this
10342 * computation to clearly distinguish it from the adjusted mode, which
10343 * can be changed by the connectors in the below retry loop.
10344 */
10345 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10346 &pipe_config->pipe_src_w,
10347 &pipe_config->pipe_src_h);
10348
10349 encoder_retry:
10350 /* Ensure the port clock defaults are reset when retrying. */
10351 pipe_config->port_clock = 0;
10352 pipe_config->pixel_multiplier = 1;
10353
10354 /* Fill in default crtc timings, allow encoders to overwrite them. */
10355 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10356 CRTC_STEREO_DOUBLE);
10357
10358 /* Pass our mode to the connectors and the CRTC to give them a chance to
10359 * adjust it according to limitations or connector properties, and also
10360 * a chance to reject the mode entirely.
10361 */
10362 for_each_intel_encoder(dev, encoder) {
10363
10364 if (&encoder->new_crtc->base != crtc)
10365 continue;
10366
10367 if (!(encoder->compute_config(encoder, pipe_config))) {
10368 DRM_DEBUG_KMS("Encoder config failure\n");
10369 goto fail;
10370 }
10371 }
10372
10373 /* Set default port clock if not overwritten by the encoder. Needs to be
10374 * done afterwards in case the encoder adjusts the mode. */
10375 if (!pipe_config->port_clock)
10376 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10377 * pipe_config->pixel_multiplier;
10378
10379 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10380 if (ret < 0) {
10381 DRM_DEBUG_KMS("CRTC fixup failed\n");
10382 goto fail;
10383 }
10384
10385 if (ret == RETRY) {
10386 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10387 ret = -EINVAL;
10388 goto fail;
10389 }
10390
10391 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10392 retry = false;
10393 goto encoder_retry;
10394 }
10395
10396 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10397 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10398 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10399
10400 return pipe_config;
10401 fail:
10402 kfree(pipe_config);
10403 return ERR_PTR(ret);
10404 }
10405
10406 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10407 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10408 static void
10409 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10410 unsigned *prepare_pipes, unsigned *disable_pipes)
10411 {
10412 struct intel_crtc *intel_crtc;
10413 struct drm_device *dev = crtc->dev;
10414 struct intel_encoder *encoder;
10415 struct intel_connector *connector;
10416 struct drm_crtc *tmp_crtc;
10417
10418 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10419
10420 /* Check which crtcs have changed outputs connected to them, these need
10421 * to be part of the prepare_pipes mask. We don't (yet) support global
10422 * modeset across multiple crtcs, so modeset_pipes will only have one
10423 * bit set at most. */
10424 list_for_each_entry(connector, &dev->mode_config.connector_list,
10425 base.head) {
10426 if (connector->base.encoder == &connector->new_encoder->base)
10427 continue;
10428
10429 if (connector->base.encoder) {
10430 tmp_crtc = connector->base.encoder->crtc;
10431
10432 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10433 }
10434
10435 if (connector->new_encoder)
10436 *prepare_pipes |=
10437 1 << connector->new_encoder->new_crtc->pipe;
10438 }
10439
10440 for_each_intel_encoder(dev, encoder) {
10441 if (encoder->base.crtc == &encoder->new_crtc->base)
10442 continue;
10443
10444 if (encoder->base.crtc) {
10445 tmp_crtc = encoder->base.crtc;
10446
10447 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10448 }
10449
10450 if (encoder->new_crtc)
10451 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10452 }
10453
10454 /* Check for pipes that will be enabled/disabled ... */
10455 for_each_intel_crtc(dev, intel_crtc) {
10456 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10457 continue;
10458
10459 if (!intel_crtc->new_enabled)
10460 *disable_pipes |= 1 << intel_crtc->pipe;
10461 else
10462 *prepare_pipes |= 1 << intel_crtc->pipe;
10463 }
10464
10465
10466 /* set_mode is also used to update properties on life display pipes. */
10467 intel_crtc = to_intel_crtc(crtc);
10468 if (intel_crtc->new_enabled)
10469 *prepare_pipes |= 1 << intel_crtc->pipe;
10470
10471 /*
10472 * For simplicity do a full modeset on any pipe where the output routing
10473 * changed. We could be more clever, but that would require us to be
10474 * more careful with calling the relevant encoder->mode_set functions.
10475 */
10476 if (*prepare_pipes)
10477 *modeset_pipes = *prepare_pipes;
10478
10479 /* ... and mask these out. */
10480 *modeset_pipes &= ~(*disable_pipes);
10481 *prepare_pipes &= ~(*disable_pipes);
10482
10483 /*
10484 * HACK: We don't (yet) fully support global modesets. intel_set_config
10485 * obies this rule, but the modeset restore mode of
10486 * intel_modeset_setup_hw_state does not.
10487 */
10488 *modeset_pipes &= 1 << intel_crtc->pipe;
10489 *prepare_pipes &= 1 << intel_crtc->pipe;
10490
10491 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10492 *modeset_pipes, *prepare_pipes, *disable_pipes);
10493 }
10494
10495 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10496 {
10497 struct drm_encoder *encoder;
10498 struct drm_device *dev = crtc->dev;
10499
10500 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10501 if (encoder->crtc == crtc)
10502 return true;
10503
10504 return false;
10505 }
10506
10507 static void
10508 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10509 {
10510 struct drm_i915_private *dev_priv = dev->dev_private;
10511 struct intel_encoder *intel_encoder;
10512 struct intel_crtc *intel_crtc;
10513 struct drm_connector *connector;
10514
10515 intel_shared_dpll_commit(dev_priv);
10516
10517 for_each_intel_encoder(dev, intel_encoder) {
10518 if (!intel_encoder->base.crtc)
10519 continue;
10520
10521 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10522
10523 if (prepare_pipes & (1 << intel_crtc->pipe))
10524 intel_encoder->connectors_active = false;
10525 }
10526
10527 intel_modeset_commit_output_state(dev);
10528
10529 /* Double check state. */
10530 for_each_intel_crtc(dev, intel_crtc) {
10531 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10532 WARN_ON(intel_crtc->new_config &&
10533 intel_crtc->new_config != intel_crtc->config);
10534 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10535 }
10536
10537 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10538 if (!connector->encoder || !connector->encoder->crtc)
10539 continue;
10540
10541 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10542
10543 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10544 struct drm_property *dpms_property =
10545 dev->mode_config.dpms_property;
10546
10547 connector->dpms = DRM_MODE_DPMS_ON;
10548 drm_object_property_set_value(&connector->base,
10549 dpms_property,
10550 DRM_MODE_DPMS_ON);
10551
10552 intel_encoder = to_intel_encoder(connector->encoder);
10553 intel_encoder->connectors_active = true;
10554 }
10555 }
10556
10557 }
10558
10559 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10560 {
10561 int diff;
10562
10563 if (clock1 == clock2)
10564 return true;
10565
10566 if (!clock1 || !clock2)
10567 return false;
10568
10569 diff = abs(clock1 - clock2);
10570
10571 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10572 return true;
10573
10574 return false;
10575 }
10576
10577 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10578 list_for_each_entry((intel_crtc), \
10579 &(dev)->mode_config.crtc_list, \
10580 base.head) \
10581 if (mask & (1 <<(intel_crtc)->pipe))
10582
10583 static bool
10584 intel_pipe_config_compare(struct drm_device *dev,
10585 struct intel_crtc_state *current_config,
10586 struct intel_crtc_state *pipe_config)
10587 {
10588 #define PIPE_CONF_CHECK_X(name) \
10589 if (current_config->name != pipe_config->name) { \
10590 DRM_ERROR("mismatch in " #name " " \
10591 "(expected 0x%08x, found 0x%08x)\n", \
10592 current_config->name, \
10593 pipe_config->name); \
10594 return false; \
10595 }
10596
10597 #define PIPE_CONF_CHECK_I(name) \
10598 if (current_config->name != pipe_config->name) { \
10599 DRM_ERROR("mismatch in " #name " " \
10600 "(expected %i, found %i)\n", \
10601 current_config->name, \
10602 pipe_config->name); \
10603 return false; \
10604 }
10605
10606 /* This is required for BDW+ where there is only one set of registers for
10607 * switching between high and low RR.
10608 * This macro can be used whenever a comparison has to be made between one
10609 * hw state and multiple sw state variables.
10610 */
10611 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10612 if ((current_config->name != pipe_config->name) && \
10613 (current_config->alt_name != pipe_config->name)) { \
10614 DRM_ERROR("mismatch in " #name " " \
10615 "(expected %i or %i, found %i)\n", \
10616 current_config->name, \
10617 current_config->alt_name, \
10618 pipe_config->name); \
10619 return false; \
10620 }
10621
10622 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10623 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10624 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10625 "(expected %i, found %i)\n", \
10626 current_config->name & (mask), \
10627 pipe_config->name & (mask)); \
10628 return false; \
10629 }
10630
10631 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10632 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10633 DRM_ERROR("mismatch in " #name " " \
10634 "(expected %i, found %i)\n", \
10635 current_config->name, \
10636 pipe_config->name); \
10637 return false; \
10638 }
10639
10640 #define PIPE_CONF_QUIRK(quirk) \
10641 ((current_config->quirks | pipe_config->quirks) & (quirk))
10642
10643 PIPE_CONF_CHECK_I(cpu_transcoder);
10644
10645 PIPE_CONF_CHECK_I(has_pch_encoder);
10646 PIPE_CONF_CHECK_I(fdi_lanes);
10647 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10648 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10649 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10650 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10651 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10652
10653 PIPE_CONF_CHECK_I(has_dp_encoder);
10654
10655 if (INTEL_INFO(dev)->gen < 8) {
10656 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10657 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10658 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10659 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10660 PIPE_CONF_CHECK_I(dp_m_n.tu);
10661
10662 if (current_config->has_drrs) {
10663 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10664 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10665 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10666 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10667 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10668 }
10669 } else {
10670 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10671 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10672 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10673 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10674 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10675 }
10676
10677 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10678 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10679 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10680 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10681 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10682 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10683
10684 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10685 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10686 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10687 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10688 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10689 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10690
10691 PIPE_CONF_CHECK_I(pixel_multiplier);
10692 PIPE_CONF_CHECK_I(has_hdmi_sink);
10693 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10694 IS_VALLEYVIEW(dev))
10695 PIPE_CONF_CHECK_I(limited_color_range);
10696 PIPE_CONF_CHECK_I(has_infoframe);
10697
10698 PIPE_CONF_CHECK_I(has_audio);
10699
10700 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10701 DRM_MODE_FLAG_INTERLACE);
10702
10703 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10704 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10705 DRM_MODE_FLAG_PHSYNC);
10706 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10707 DRM_MODE_FLAG_NHSYNC);
10708 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10709 DRM_MODE_FLAG_PVSYNC);
10710 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10711 DRM_MODE_FLAG_NVSYNC);
10712 }
10713
10714 PIPE_CONF_CHECK_I(pipe_src_w);
10715 PIPE_CONF_CHECK_I(pipe_src_h);
10716
10717 /*
10718 * FIXME: BIOS likes to set up a cloned config with lvds+external
10719 * screen. Since we don't yet re-compute the pipe config when moving
10720 * just the lvds port away to another pipe the sw tracking won't match.
10721 *
10722 * Proper atomic modesets with recomputed global state will fix this.
10723 * Until then just don't check gmch state for inherited modes.
10724 */
10725 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10726 PIPE_CONF_CHECK_I(gmch_pfit.control);
10727 /* pfit ratios are autocomputed by the hw on gen4+ */
10728 if (INTEL_INFO(dev)->gen < 4)
10729 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10730 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10731 }
10732
10733 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10734 if (current_config->pch_pfit.enabled) {
10735 PIPE_CONF_CHECK_I(pch_pfit.pos);
10736 PIPE_CONF_CHECK_I(pch_pfit.size);
10737 }
10738
10739 /* BDW+ don't expose a synchronous way to read the state */
10740 if (IS_HASWELL(dev))
10741 PIPE_CONF_CHECK_I(ips_enabled);
10742
10743 PIPE_CONF_CHECK_I(double_wide);
10744
10745 PIPE_CONF_CHECK_X(ddi_pll_sel);
10746
10747 PIPE_CONF_CHECK_I(shared_dpll);
10748 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10749 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10750 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10751 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10752 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10753 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10754 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10755 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10756
10757 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10758 PIPE_CONF_CHECK_I(pipe_bpp);
10759
10760 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10761 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10762
10763 #undef PIPE_CONF_CHECK_X
10764 #undef PIPE_CONF_CHECK_I
10765 #undef PIPE_CONF_CHECK_I_ALT
10766 #undef PIPE_CONF_CHECK_FLAGS
10767 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10768 #undef PIPE_CONF_QUIRK
10769
10770 return true;
10771 }
10772
10773 static void check_wm_state(struct drm_device *dev)
10774 {
10775 struct drm_i915_private *dev_priv = dev->dev_private;
10776 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10777 struct intel_crtc *intel_crtc;
10778 int plane;
10779
10780 if (INTEL_INFO(dev)->gen < 9)
10781 return;
10782
10783 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10784 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10785
10786 for_each_intel_crtc(dev, intel_crtc) {
10787 struct skl_ddb_entry *hw_entry, *sw_entry;
10788 const enum pipe pipe = intel_crtc->pipe;
10789
10790 if (!intel_crtc->active)
10791 continue;
10792
10793 /* planes */
10794 for_each_plane(pipe, plane) {
10795 hw_entry = &hw_ddb.plane[pipe][plane];
10796 sw_entry = &sw_ddb->plane[pipe][plane];
10797
10798 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10799 continue;
10800
10801 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10802 "(expected (%u,%u), found (%u,%u))\n",
10803 pipe_name(pipe), plane + 1,
10804 sw_entry->start, sw_entry->end,
10805 hw_entry->start, hw_entry->end);
10806 }
10807
10808 /* cursor */
10809 hw_entry = &hw_ddb.cursor[pipe];
10810 sw_entry = &sw_ddb->cursor[pipe];
10811
10812 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10813 continue;
10814
10815 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10816 "(expected (%u,%u), found (%u,%u))\n",
10817 pipe_name(pipe),
10818 sw_entry->start, sw_entry->end,
10819 hw_entry->start, hw_entry->end);
10820 }
10821 }
10822
10823 static void
10824 check_connector_state(struct drm_device *dev)
10825 {
10826 struct intel_connector *connector;
10827
10828 list_for_each_entry(connector, &dev->mode_config.connector_list,
10829 base.head) {
10830 /* This also checks the encoder/connector hw state with the
10831 * ->get_hw_state callbacks. */
10832 intel_connector_check_state(connector);
10833
10834 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10835 "connector's staged encoder doesn't match current encoder\n");
10836 }
10837 }
10838
10839 static void
10840 check_encoder_state(struct drm_device *dev)
10841 {
10842 struct intel_encoder *encoder;
10843 struct intel_connector *connector;
10844
10845 for_each_intel_encoder(dev, encoder) {
10846 bool enabled = false;
10847 bool active = false;
10848 enum pipe pipe, tracked_pipe;
10849
10850 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10851 encoder->base.base.id,
10852 encoder->base.name);
10853
10854 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10855 "encoder's stage crtc doesn't match current crtc\n");
10856 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10857 "encoder's active_connectors set, but no crtc\n");
10858
10859 list_for_each_entry(connector, &dev->mode_config.connector_list,
10860 base.head) {
10861 if (connector->base.encoder != &encoder->base)
10862 continue;
10863 enabled = true;
10864 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10865 active = true;
10866 }
10867 /*
10868 * for MST connectors if we unplug the connector is gone
10869 * away but the encoder is still connected to a crtc
10870 * until a modeset happens in response to the hotplug.
10871 */
10872 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10873 continue;
10874
10875 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10876 "encoder's enabled state mismatch "
10877 "(expected %i, found %i)\n",
10878 !!encoder->base.crtc, enabled);
10879 I915_STATE_WARN(active && !encoder->base.crtc,
10880 "active encoder with no crtc\n");
10881
10882 I915_STATE_WARN(encoder->connectors_active != active,
10883 "encoder's computed active state doesn't match tracked active state "
10884 "(expected %i, found %i)\n", active, encoder->connectors_active);
10885
10886 active = encoder->get_hw_state(encoder, &pipe);
10887 I915_STATE_WARN(active != encoder->connectors_active,
10888 "encoder's hw state doesn't match sw tracking "
10889 "(expected %i, found %i)\n",
10890 encoder->connectors_active, active);
10891
10892 if (!encoder->base.crtc)
10893 continue;
10894
10895 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10896 I915_STATE_WARN(active && pipe != tracked_pipe,
10897 "active encoder's pipe doesn't match"
10898 "(expected %i, found %i)\n",
10899 tracked_pipe, pipe);
10900
10901 }
10902 }
10903
10904 static void
10905 check_crtc_state(struct drm_device *dev)
10906 {
10907 struct drm_i915_private *dev_priv = dev->dev_private;
10908 struct intel_crtc *crtc;
10909 struct intel_encoder *encoder;
10910 struct intel_crtc_state pipe_config;
10911
10912 for_each_intel_crtc(dev, crtc) {
10913 bool enabled = false;
10914 bool active = false;
10915
10916 memset(&pipe_config, 0, sizeof(pipe_config));
10917
10918 DRM_DEBUG_KMS("[CRTC:%d]\n",
10919 crtc->base.base.id);
10920
10921 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10922 "active crtc, but not enabled in sw tracking\n");
10923
10924 for_each_intel_encoder(dev, encoder) {
10925 if (encoder->base.crtc != &crtc->base)
10926 continue;
10927 enabled = true;
10928 if (encoder->connectors_active)
10929 active = true;
10930 }
10931
10932 I915_STATE_WARN(active != crtc->active,
10933 "crtc's computed active state doesn't match tracked active state "
10934 "(expected %i, found %i)\n", active, crtc->active);
10935 I915_STATE_WARN(enabled != crtc->base.state->enable,
10936 "crtc's computed enabled state doesn't match tracked enabled state "
10937 "(expected %i, found %i)\n", enabled,
10938 crtc->base.state->enable);
10939
10940 active = dev_priv->display.get_pipe_config(crtc,
10941 &pipe_config);
10942
10943 /* hw state is inconsistent with the pipe quirk */
10944 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10945 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10946 active = crtc->active;
10947
10948 for_each_intel_encoder(dev, encoder) {
10949 enum pipe pipe;
10950 if (encoder->base.crtc != &crtc->base)
10951 continue;
10952 if (encoder->get_hw_state(encoder, &pipe))
10953 encoder->get_config(encoder, &pipe_config);
10954 }
10955
10956 I915_STATE_WARN(crtc->active != active,
10957 "crtc active state doesn't match with hw state "
10958 "(expected %i, found %i)\n", crtc->active, active);
10959
10960 if (active &&
10961 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10962 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10963 intel_dump_pipe_config(crtc, &pipe_config,
10964 "[hw state]");
10965 intel_dump_pipe_config(crtc, crtc->config,
10966 "[sw state]");
10967 }
10968 }
10969 }
10970
10971 static void
10972 check_shared_dpll_state(struct drm_device *dev)
10973 {
10974 struct drm_i915_private *dev_priv = dev->dev_private;
10975 struct intel_crtc *crtc;
10976 struct intel_dpll_hw_state dpll_hw_state;
10977 int i;
10978
10979 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10980 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10981 int enabled_crtcs = 0, active_crtcs = 0;
10982 bool active;
10983
10984 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10985
10986 DRM_DEBUG_KMS("%s\n", pll->name);
10987
10988 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10989
10990 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10991 "more active pll users than references: %i vs %i\n",
10992 pll->active, hweight32(pll->config.crtc_mask));
10993 I915_STATE_WARN(pll->active && !pll->on,
10994 "pll in active use but not on in sw tracking\n");
10995 I915_STATE_WARN(pll->on && !pll->active,
10996 "pll in on but not on in use in sw tracking\n");
10997 I915_STATE_WARN(pll->on != active,
10998 "pll on state mismatch (expected %i, found %i)\n",
10999 pll->on, active);
11000
11001 for_each_intel_crtc(dev, crtc) {
11002 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11003 enabled_crtcs++;
11004 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11005 active_crtcs++;
11006 }
11007 I915_STATE_WARN(pll->active != active_crtcs,
11008 "pll active crtcs mismatch (expected %i, found %i)\n",
11009 pll->active, active_crtcs);
11010 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11011 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11012 hweight32(pll->config.crtc_mask), enabled_crtcs);
11013
11014 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11015 sizeof(dpll_hw_state)),
11016 "pll hw state mismatch\n");
11017 }
11018 }
11019
11020 void
11021 intel_modeset_check_state(struct drm_device *dev)
11022 {
11023 check_wm_state(dev);
11024 check_connector_state(dev);
11025 check_encoder_state(dev);
11026 check_crtc_state(dev);
11027 check_shared_dpll_state(dev);
11028 }
11029
11030 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11031 int dotclock)
11032 {
11033 /*
11034 * FDI already provided one idea for the dotclock.
11035 * Yell if the encoder disagrees.
11036 */
11037 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11038 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11039 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11040 }
11041
11042 static void update_scanline_offset(struct intel_crtc *crtc)
11043 {
11044 struct drm_device *dev = crtc->base.dev;
11045
11046 /*
11047 * The scanline counter increments at the leading edge of hsync.
11048 *
11049 * On most platforms it starts counting from vtotal-1 on the
11050 * first active line. That means the scanline counter value is
11051 * always one less than what we would expect. Ie. just after
11052 * start of vblank, which also occurs at start of hsync (on the
11053 * last active line), the scanline counter will read vblank_start-1.
11054 *
11055 * On gen2 the scanline counter starts counting from 1 instead
11056 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11057 * to keep the value positive), instead of adding one.
11058 *
11059 * On HSW+ the behaviour of the scanline counter depends on the output
11060 * type. For DP ports it behaves like most other platforms, but on HDMI
11061 * there's an extra 1 line difference. So we need to add two instead of
11062 * one to the value.
11063 */
11064 if (IS_GEN2(dev)) {
11065 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11066 int vtotal;
11067
11068 vtotal = mode->crtc_vtotal;
11069 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11070 vtotal /= 2;
11071
11072 crtc->scanline_offset = vtotal - 1;
11073 } else if (HAS_DDI(dev) &&
11074 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11075 crtc->scanline_offset = 2;
11076 } else
11077 crtc->scanline_offset = 1;
11078 }
11079
11080 static struct intel_crtc_state *
11081 intel_modeset_compute_config(struct drm_crtc *crtc,
11082 struct drm_display_mode *mode,
11083 struct drm_framebuffer *fb,
11084 unsigned *modeset_pipes,
11085 unsigned *prepare_pipes,
11086 unsigned *disable_pipes)
11087 {
11088 struct intel_crtc_state *pipe_config = NULL;
11089
11090 intel_modeset_affected_pipes(crtc, modeset_pipes,
11091 prepare_pipes, disable_pipes);
11092
11093 if ((*modeset_pipes) == 0)
11094 goto out;
11095
11096 /*
11097 * Note this needs changes when we start tracking multiple modes
11098 * and crtcs. At that point we'll need to compute the whole config
11099 * (i.e. one pipe_config for each crtc) rather than just the one
11100 * for this crtc.
11101 */
11102 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11103 if (IS_ERR(pipe_config)) {
11104 goto out;
11105 }
11106 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11107 "[modeset]");
11108
11109 out:
11110 return pipe_config;
11111 }
11112
11113 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11114 unsigned modeset_pipes,
11115 unsigned disable_pipes)
11116 {
11117 struct drm_i915_private *dev_priv = to_i915(dev);
11118 unsigned clear_pipes = modeset_pipes | disable_pipes;
11119 struct intel_crtc *intel_crtc;
11120 int ret = 0;
11121
11122 if (!dev_priv->display.crtc_compute_clock)
11123 return 0;
11124
11125 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11126 if (ret)
11127 goto done;
11128
11129 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11130 struct intel_crtc_state *state = intel_crtc->new_config;
11131 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11132 state);
11133 if (ret) {
11134 intel_shared_dpll_abort_config(dev_priv);
11135 goto done;
11136 }
11137 }
11138
11139 done:
11140 return ret;
11141 }
11142
11143 static int __intel_set_mode(struct drm_crtc *crtc,
11144 struct drm_display_mode *mode,
11145 int x, int y, struct drm_framebuffer *fb,
11146 struct intel_crtc_state *pipe_config,
11147 unsigned modeset_pipes,
11148 unsigned prepare_pipes,
11149 unsigned disable_pipes)
11150 {
11151 struct drm_device *dev = crtc->dev;
11152 struct drm_i915_private *dev_priv = dev->dev_private;
11153 struct drm_display_mode *saved_mode;
11154 struct intel_crtc *intel_crtc;
11155 int ret = 0;
11156
11157 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11158 if (!saved_mode)
11159 return -ENOMEM;
11160
11161 *saved_mode = crtc->mode;
11162
11163 if (modeset_pipes)
11164 to_intel_crtc(crtc)->new_config = pipe_config;
11165
11166 /*
11167 * See if the config requires any additional preparation, e.g.
11168 * to adjust global state with pipes off. We need to do this
11169 * here so we can get the modeset_pipe updated config for the new
11170 * mode set on this crtc. For other crtcs we need to use the
11171 * adjusted_mode bits in the crtc directly.
11172 */
11173 if (IS_VALLEYVIEW(dev)) {
11174 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11175
11176 /* may have added more to prepare_pipes than we should */
11177 prepare_pipes &= ~disable_pipes;
11178 }
11179
11180 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11181 if (ret)
11182 goto done;
11183
11184 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11185 intel_crtc_disable(&intel_crtc->base);
11186
11187 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11188 if (intel_crtc->base.state->enable)
11189 dev_priv->display.crtc_disable(&intel_crtc->base);
11190 }
11191
11192 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11193 * to set it here already despite that we pass it down the callchain.
11194 *
11195 * Note we'll need to fix this up when we start tracking multiple
11196 * pipes; here we assume a single modeset_pipe and only track the
11197 * single crtc and mode.
11198 */
11199 if (modeset_pipes) {
11200 crtc->mode = *mode;
11201 /* mode_set/enable/disable functions rely on a correct pipe
11202 * config. */
11203 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11204
11205 /*
11206 * Calculate and store various constants which
11207 * are later needed by vblank and swap-completion
11208 * timestamping. They are derived from true hwmode.
11209 */
11210 drm_calc_timestamping_constants(crtc,
11211 &pipe_config->base.adjusted_mode);
11212 }
11213
11214 /* Only after disabling all output pipelines that will be changed can we
11215 * update the the output configuration. */
11216 intel_modeset_update_state(dev, prepare_pipes);
11217
11218 modeset_update_crtc_power_domains(dev);
11219
11220 /* Set up the DPLL and any encoders state that needs to adjust or depend
11221 * on the DPLL.
11222 */
11223 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11224 struct drm_plane *primary = intel_crtc->base.primary;
11225 int vdisplay, hdisplay;
11226
11227 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11228 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11229 fb, 0, 0,
11230 hdisplay, vdisplay,
11231 x << 16, y << 16,
11232 hdisplay << 16, vdisplay << 16);
11233 }
11234
11235 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11236 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11237 update_scanline_offset(intel_crtc);
11238
11239 dev_priv->display.crtc_enable(&intel_crtc->base);
11240 }
11241
11242 /* FIXME: add subpixel order */
11243 done:
11244 if (ret && crtc->state->enable)
11245 crtc->mode = *saved_mode;
11246
11247 kfree(saved_mode);
11248 return ret;
11249 }
11250
11251 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11252 struct drm_display_mode *mode,
11253 int x, int y, struct drm_framebuffer *fb,
11254 struct intel_crtc_state *pipe_config,
11255 unsigned modeset_pipes,
11256 unsigned prepare_pipes,
11257 unsigned disable_pipes)
11258 {
11259 int ret;
11260
11261 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11262 prepare_pipes, disable_pipes);
11263
11264 if (ret == 0)
11265 intel_modeset_check_state(crtc->dev);
11266
11267 return ret;
11268 }
11269
11270 static int intel_set_mode(struct drm_crtc *crtc,
11271 struct drm_display_mode *mode,
11272 int x, int y, struct drm_framebuffer *fb)
11273 {
11274 struct intel_crtc_state *pipe_config;
11275 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11276
11277 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11278 &modeset_pipes,
11279 &prepare_pipes,
11280 &disable_pipes);
11281
11282 if (IS_ERR(pipe_config))
11283 return PTR_ERR(pipe_config);
11284
11285 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11286 modeset_pipes, prepare_pipes,
11287 disable_pipes);
11288 }
11289
11290 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11291 {
11292 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11293 }
11294
11295 #undef for_each_intel_crtc_masked
11296
11297 static void intel_set_config_free(struct intel_set_config *config)
11298 {
11299 if (!config)
11300 return;
11301
11302 kfree(config->save_connector_encoders);
11303 kfree(config->save_encoder_crtcs);
11304 kfree(config->save_crtc_enabled);
11305 kfree(config);
11306 }
11307
11308 static int intel_set_config_save_state(struct drm_device *dev,
11309 struct intel_set_config *config)
11310 {
11311 struct drm_crtc *crtc;
11312 struct drm_encoder *encoder;
11313 struct drm_connector *connector;
11314 int count;
11315
11316 config->save_crtc_enabled =
11317 kcalloc(dev->mode_config.num_crtc,
11318 sizeof(bool), GFP_KERNEL);
11319 if (!config->save_crtc_enabled)
11320 return -ENOMEM;
11321
11322 config->save_encoder_crtcs =
11323 kcalloc(dev->mode_config.num_encoder,
11324 sizeof(struct drm_crtc *), GFP_KERNEL);
11325 if (!config->save_encoder_crtcs)
11326 return -ENOMEM;
11327
11328 config->save_connector_encoders =
11329 kcalloc(dev->mode_config.num_connector,
11330 sizeof(struct drm_encoder *), GFP_KERNEL);
11331 if (!config->save_connector_encoders)
11332 return -ENOMEM;
11333
11334 /* Copy data. Note that driver private data is not affected.
11335 * Should anything bad happen only the expected state is
11336 * restored, not the drivers personal bookkeeping.
11337 */
11338 count = 0;
11339 for_each_crtc(dev, crtc) {
11340 config->save_crtc_enabled[count++] = crtc->state->enable;
11341 }
11342
11343 count = 0;
11344 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11345 config->save_encoder_crtcs[count++] = encoder->crtc;
11346 }
11347
11348 count = 0;
11349 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11350 config->save_connector_encoders[count++] = connector->encoder;
11351 }
11352
11353 return 0;
11354 }
11355
11356 static void intel_set_config_restore_state(struct drm_device *dev,
11357 struct intel_set_config *config)
11358 {
11359 struct intel_crtc *crtc;
11360 struct intel_encoder *encoder;
11361 struct intel_connector *connector;
11362 int count;
11363
11364 count = 0;
11365 for_each_intel_crtc(dev, crtc) {
11366 crtc->new_enabled = config->save_crtc_enabled[count++];
11367
11368 if (crtc->new_enabled)
11369 crtc->new_config = crtc->config;
11370 else
11371 crtc->new_config = NULL;
11372 }
11373
11374 count = 0;
11375 for_each_intel_encoder(dev, encoder) {
11376 encoder->new_crtc =
11377 to_intel_crtc(config->save_encoder_crtcs[count++]);
11378 }
11379
11380 count = 0;
11381 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11382 connector->new_encoder =
11383 to_intel_encoder(config->save_connector_encoders[count++]);
11384 }
11385 }
11386
11387 static bool
11388 is_crtc_connector_off(struct drm_mode_set *set)
11389 {
11390 int i;
11391
11392 if (set->num_connectors == 0)
11393 return false;
11394
11395 if (WARN_ON(set->connectors == NULL))
11396 return false;
11397
11398 for (i = 0; i < set->num_connectors; i++)
11399 if (set->connectors[i]->encoder &&
11400 set->connectors[i]->encoder->crtc == set->crtc &&
11401 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11402 return true;
11403
11404 return false;
11405 }
11406
11407 static void
11408 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11409 struct intel_set_config *config)
11410 {
11411
11412 /* We should be able to check here if the fb has the same properties
11413 * and then just flip_or_move it */
11414 if (is_crtc_connector_off(set)) {
11415 config->mode_changed = true;
11416 } else if (set->crtc->primary->fb != set->fb) {
11417 /*
11418 * If we have no fb, we can only flip as long as the crtc is
11419 * active, otherwise we need a full mode set. The crtc may
11420 * be active if we've only disabled the primary plane, or
11421 * in fastboot situations.
11422 */
11423 if (set->crtc->primary->fb == NULL) {
11424 struct intel_crtc *intel_crtc =
11425 to_intel_crtc(set->crtc);
11426
11427 if (intel_crtc->active) {
11428 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11429 config->fb_changed = true;
11430 } else {
11431 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11432 config->mode_changed = true;
11433 }
11434 } else if (set->fb == NULL) {
11435 config->mode_changed = true;
11436 } else if (set->fb->pixel_format !=
11437 set->crtc->primary->fb->pixel_format) {
11438 config->mode_changed = true;
11439 } else {
11440 config->fb_changed = true;
11441 }
11442 }
11443
11444 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11445 config->fb_changed = true;
11446
11447 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11448 DRM_DEBUG_KMS("modes are different, full mode set\n");
11449 drm_mode_debug_printmodeline(&set->crtc->mode);
11450 drm_mode_debug_printmodeline(set->mode);
11451 config->mode_changed = true;
11452 }
11453
11454 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11455 set->crtc->base.id, config->mode_changed, config->fb_changed);
11456 }
11457
11458 static int
11459 intel_modeset_stage_output_state(struct drm_device *dev,
11460 struct drm_mode_set *set,
11461 struct intel_set_config *config)
11462 {
11463 struct intel_connector *connector;
11464 struct intel_encoder *encoder;
11465 struct intel_crtc *crtc;
11466 int ro;
11467
11468 /* The upper layers ensure that we either disable a crtc or have a list
11469 * of connectors. For paranoia, double-check this. */
11470 WARN_ON(!set->fb && (set->num_connectors != 0));
11471 WARN_ON(set->fb && (set->num_connectors == 0));
11472
11473 list_for_each_entry(connector, &dev->mode_config.connector_list,
11474 base.head) {
11475 /* Otherwise traverse passed in connector list and get encoders
11476 * for them. */
11477 for (ro = 0; ro < set->num_connectors; ro++) {
11478 if (set->connectors[ro] == &connector->base) {
11479 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11480 break;
11481 }
11482 }
11483
11484 /* If we disable the crtc, disable all its connectors. Also, if
11485 * the connector is on the changing crtc but not on the new
11486 * connector list, disable it. */
11487 if ((!set->fb || ro == set->num_connectors) &&
11488 connector->base.encoder &&
11489 connector->base.encoder->crtc == set->crtc) {
11490 connector->new_encoder = NULL;
11491
11492 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11493 connector->base.base.id,
11494 connector->base.name);
11495 }
11496
11497
11498 if (&connector->new_encoder->base != connector->base.encoder) {
11499 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11500 config->mode_changed = true;
11501 }
11502 }
11503 /* connector->new_encoder is now updated for all connectors. */
11504
11505 /* Update crtc of enabled connectors. */
11506 list_for_each_entry(connector, &dev->mode_config.connector_list,
11507 base.head) {
11508 struct drm_crtc *new_crtc;
11509
11510 if (!connector->new_encoder)
11511 continue;
11512
11513 new_crtc = connector->new_encoder->base.crtc;
11514
11515 for (ro = 0; ro < set->num_connectors; ro++) {
11516 if (set->connectors[ro] == &connector->base)
11517 new_crtc = set->crtc;
11518 }
11519
11520 /* Make sure the new CRTC will work with the encoder */
11521 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11522 new_crtc)) {
11523 return -EINVAL;
11524 }
11525 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11526
11527 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11528 connector->base.base.id,
11529 connector->base.name,
11530 new_crtc->base.id);
11531 }
11532
11533 /* Check for any encoders that needs to be disabled. */
11534 for_each_intel_encoder(dev, encoder) {
11535 int num_connectors = 0;
11536 list_for_each_entry(connector,
11537 &dev->mode_config.connector_list,
11538 base.head) {
11539 if (connector->new_encoder == encoder) {
11540 WARN_ON(!connector->new_encoder->new_crtc);
11541 num_connectors++;
11542 }
11543 }
11544
11545 if (num_connectors == 0)
11546 encoder->new_crtc = NULL;
11547 else if (num_connectors > 1)
11548 return -EINVAL;
11549
11550 /* Only now check for crtc changes so we don't miss encoders
11551 * that will be disabled. */
11552 if (&encoder->new_crtc->base != encoder->base.crtc) {
11553 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11554 config->mode_changed = true;
11555 }
11556 }
11557 /* Now we've also updated encoder->new_crtc for all encoders. */
11558 list_for_each_entry(connector, &dev->mode_config.connector_list,
11559 base.head) {
11560 if (connector->new_encoder)
11561 if (connector->new_encoder != connector->encoder)
11562 connector->encoder = connector->new_encoder;
11563 }
11564 for_each_intel_crtc(dev, crtc) {
11565 crtc->new_enabled = false;
11566
11567 for_each_intel_encoder(dev, encoder) {
11568 if (encoder->new_crtc == crtc) {
11569 crtc->new_enabled = true;
11570 break;
11571 }
11572 }
11573
11574 if (crtc->new_enabled != crtc->base.state->enable) {
11575 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11576 crtc->new_enabled ? "en" : "dis");
11577 config->mode_changed = true;
11578 }
11579
11580 if (crtc->new_enabled)
11581 crtc->new_config = crtc->config;
11582 else
11583 crtc->new_config = NULL;
11584 }
11585
11586 return 0;
11587 }
11588
11589 static void disable_crtc_nofb(struct intel_crtc *crtc)
11590 {
11591 struct drm_device *dev = crtc->base.dev;
11592 struct intel_encoder *encoder;
11593 struct intel_connector *connector;
11594
11595 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11596 pipe_name(crtc->pipe));
11597
11598 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11599 if (connector->new_encoder &&
11600 connector->new_encoder->new_crtc == crtc)
11601 connector->new_encoder = NULL;
11602 }
11603
11604 for_each_intel_encoder(dev, encoder) {
11605 if (encoder->new_crtc == crtc)
11606 encoder->new_crtc = NULL;
11607 }
11608
11609 crtc->new_enabled = false;
11610 crtc->new_config = NULL;
11611 }
11612
11613 static int intel_crtc_set_config(struct drm_mode_set *set)
11614 {
11615 struct drm_device *dev;
11616 struct drm_mode_set save_set;
11617 struct intel_set_config *config;
11618 struct intel_crtc_state *pipe_config;
11619 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11620 int ret;
11621
11622 BUG_ON(!set);
11623 BUG_ON(!set->crtc);
11624 BUG_ON(!set->crtc->helper_private);
11625
11626 /* Enforce sane interface api - has been abused by the fb helper. */
11627 BUG_ON(!set->mode && set->fb);
11628 BUG_ON(set->fb && set->num_connectors == 0);
11629
11630 if (set->fb) {
11631 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11632 set->crtc->base.id, set->fb->base.id,
11633 (int)set->num_connectors, set->x, set->y);
11634 } else {
11635 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11636 }
11637
11638 dev = set->crtc->dev;
11639
11640 ret = -ENOMEM;
11641 config = kzalloc(sizeof(*config), GFP_KERNEL);
11642 if (!config)
11643 goto out_config;
11644
11645 ret = intel_set_config_save_state(dev, config);
11646 if (ret)
11647 goto out_config;
11648
11649 save_set.crtc = set->crtc;
11650 save_set.mode = &set->crtc->mode;
11651 save_set.x = set->crtc->x;
11652 save_set.y = set->crtc->y;
11653 save_set.fb = set->crtc->primary->fb;
11654
11655 /* Compute whether we need a full modeset, only an fb base update or no
11656 * change at all. In the future we might also check whether only the
11657 * mode changed, e.g. for LVDS where we only change the panel fitter in
11658 * such cases. */
11659 intel_set_config_compute_mode_changes(set, config);
11660
11661 ret = intel_modeset_stage_output_state(dev, set, config);
11662 if (ret)
11663 goto fail;
11664
11665 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11666 set->fb,
11667 &modeset_pipes,
11668 &prepare_pipes,
11669 &disable_pipes);
11670 if (IS_ERR(pipe_config)) {
11671 ret = PTR_ERR(pipe_config);
11672 goto fail;
11673 } else if (pipe_config) {
11674 if (pipe_config->has_audio !=
11675 to_intel_crtc(set->crtc)->config->has_audio)
11676 config->mode_changed = true;
11677
11678 /*
11679 * Note we have an issue here with infoframes: current code
11680 * only updates them on the full mode set path per hw
11681 * requirements. So here we should be checking for any
11682 * required changes and forcing a mode set.
11683 */
11684 }
11685
11686 /* set_mode will free it in the mode_changed case */
11687 if (!config->mode_changed)
11688 kfree(pipe_config);
11689
11690 intel_update_pipe_size(to_intel_crtc(set->crtc));
11691
11692 if (config->mode_changed) {
11693 ret = intel_set_mode_pipes(set->crtc, set->mode,
11694 set->x, set->y, set->fb, pipe_config,
11695 modeset_pipes, prepare_pipes,
11696 disable_pipes);
11697 } else if (config->fb_changed) {
11698 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11699 struct drm_plane *primary = set->crtc->primary;
11700 int vdisplay, hdisplay;
11701
11702 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11703 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11704 0, 0, hdisplay, vdisplay,
11705 set->x << 16, set->y << 16,
11706 hdisplay << 16, vdisplay << 16);
11707
11708 /*
11709 * We need to make sure the primary plane is re-enabled if it
11710 * has previously been turned off.
11711 */
11712 if (!intel_crtc->primary_enabled && ret == 0) {
11713 WARN_ON(!intel_crtc->active);
11714 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11715 }
11716
11717 /*
11718 * In the fastboot case this may be our only check of the
11719 * state after boot. It would be better to only do it on
11720 * the first update, but we don't have a nice way of doing that
11721 * (and really, set_config isn't used much for high freq page
11722 * flipping, so increasing its cost here shouldn't be a big
11723 * deal).
11724 */
11725 if (i915.fastboot && ret == 0)
11726 intel_modeset_check_state(set->crtc->dev);
11727 }
11728
11729 if (ret) {
11730 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11731 set->crtc->base.id, ret);
11732 fail:
11733 intel_set_config_restore_state(dev, config);
11734
11735 /*
11736 * HACK: if the pipe was on, but we didn't have a framebuffer,
11737 * force the pipe off to avoid oopsing in the modeset code
11738 * due to fb==NULL. This should only happen during boot since
11739 * we don't yet reconstruct the FB from the hardware state.
11740 */
11741 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11742 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11743
11744 /* Try to restore the config */
11745 if (config->mode_changed &&
11746 intel_set_mode(save_set.crtc, save_set.mode,
11747 save_set.x, save_set.y, save_set.fb))
11748 DRM_ERROR("failed to restore config after modeset failure\n");
11749 }
11750
11751 out_config:
11752 intel_set_config_free(config);
11753 return ret;
11754 }
11755
11756 static const struct drm_crtc_funcs intel_crtc_funcs = {
11757 .gamma_set = intel_crtc_gamma_set,
11758 .set_config = intel_crtc_set_config,
11759 .destroy = intel_crtc_destroy,
11760 .page_flip = intel_crtc_page_flip,
11761 .atomic_duplicate_state = intel_crtc_duplicate_state,
11762 .atomic_destroy_state = intel_crtc_destroy_state,
11763 };
11764
11765 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11766 struct intel_shared_dpll *pll,
11767 struct intel_dpll_hw_state *hw_state)
11768 {
11769 uint32_t val;
11770
11771 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11772 return false;
11773
11774 val = I915_READ(PCH_DPLL(pll->id));
11775 hw_state->dpll = val;
11776 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11777 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11778
11779 return val & DPLL_VCO_ENABLE;
11780 }
11781
11782 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11783 struct intel_shared_dpll *pll)
11784 {
11785 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11786 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11787 }
11788
11789 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11790 struct intel_shared_dpll *pll)
11791 {
11792 /* PCH refclock must be enabled first */
11793 ibx_assert_pch_refclk_enabled(dev_priv);
11794
11795 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11796
11797 /* Wait for the clocks to stabilize. */
11798 POSTING_READ(PCH_DPLL(pll->id));
11799 udelay(150);
11800
11801 /* The pixel multiplier can only be updated once the
11802 * DPLL is enabled and the clocks are stable.
11803 *
11804 * So write it again.
11805 */
11806 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11807 POSTING_READ(PCH_DPLL(pll->id));
11808 udelay(200);
11809 }
11810
11811 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11812 struct intel_shared_dpll *pll)
11813 {
11814 struct drm_device *dev = dev_priv->dev;
11815 struct intel_crtc *crtc;
11816
11817 /* Make sure no transcoder isn't still depending on us. */
11818 for_each_intel_crtc(dev, crtc) {
11819 if (intel_crtc_to_shared_dpll(crtc) == pll)
11820 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11821 }
11822
11823 I915_WRITE(PCH_DPLL(pll->id), 0);
11824 POSTING_READ(PCH_DPLL(pll->id));
11825 udelay(200);
11826 }
11827
11828 static char *ibx_pch_dpll_names[] = {
11829 "PCH DPLL A",
11830 "PCH DPLL B",
11831 };
11832
11833 static void ibx_pch_dpll_init(struct drm_device *dev)
11834 {
11835 struct drm_i915_private *dev_priv = dev->dev_private;
11836 int i;
11837
11838 dev_priv->num_shared_dpll = 2;
11839
11840 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11841 dev_priv->shared_dplls[i].id = i;
11842 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11843 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11844 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11845 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11846 dev_priv->shared_dplls[i].get_hw_state =
11847 ibx_pch_dpll_get_hw_state;
11848 }
11849 }
11850
11851 static void intel_shared_dpll_init(struct drm_device *dev)
11852 {
11853 struct drm_i915_private *dev_priv = dev->dev_private;
11854
11855 if (HAS_DDI(dev))
11856 intel_ddi_pll_init(dev);
11857 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11858 ibx_pch_dpll_init(dev);
11859 else
11860 dev_priv->num_shared_dpll = 0;
11861
11862 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11863 }
11864
11865 /**
11866 * intel_prepare_plane_fb - Prepare fb for usage on plane
11867 * @plane: drm plane to prepare for
11868 * @fb: framebuffer to prepare for presentation
11869 *
11870 * Prepares a framebuffer for usage on a display plane. Generally this
11871 * involves pinning the underlying object and updating the frontbuffer tracking
11872 * bits. Some older platforms need special physical address handling for
11873 * cursor planes.
11874 *
11875 * Returns 0 on success, negative error code on failure.
11876 */
11877 int
11878 intel_prepare_plane_fb(struct drm_plane *plane,
11879 struct drm_framebuffer *fb,
11880 const struct drm_plane_state *new_state)
11881 {
11882 struct drm_device *dev = plane->dev;
11883 struct intel_plane *intel_plane = to_intel_plane(plane);
11884 enum pipe pipe = intel_plane->pipe;
11885 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11886 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11887 unsigned frontbuffer_bits = 0;
11888 int ret = 0;
11889
11890 if (!obj)
11891 return 0;
11892
11893 switch (plane->type) {
11894 case DRM_PLANE_TYPE_PRIMARY:
11895 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11896 break;
11897 case DRM_PLANE_TYPE_CURSOR:
11898 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11899 break;
11900 case DRM_PLANE_TYPE_OVERLAY:
11901 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11902 break;
11903 }
11904
11905 mutex_lock(&dev->struct_mutex);
11906
11907 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11908 INTEL_INFO(dev)->cursor_needs_physical) {
11909 int align = IS_I830(dev) ? 16 * 1024 : 256;
11910 ret = i915_gem_object_attach_phys(obj, align);
11911 if (ret)
11912 DRM_DEBUG_KMS("failed to attach phys object\n");
11913 } else {
11914 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11915 }
11916
11917 if (ret == 0)
11918 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11919
11920 mutex_unlock(&dev->struct_mutex);
11921
11922 return ret;
11923 }
11924
11925 /**
11926 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11927 * @plane: drm plane to clean up for
11928 * @fb: old framebuffer that was on plane
11929 *
11930 * Cleans up a framebuffer that has just been removed from a plane.
11931 */
11932 void
11933 intel_cleanup_plane_fb(struct drm_plane *plane,
11934 struct drm_framebuffer *fb,
11935 const struct drm_plane_state *old_state)
11936 {
11937 struct drm_device *dev = plane->dev;
11938 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11939
11940 if (WARN_ON(!obj))
11941 return;
11942
11943 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11944 !INTEL_INFO(dev)->cursor_needs_physical) {
11945 mutex_lock(&dev->struct_mutex);
11946 intel_unpin_fb_obj(obj);
11947 mutex_unlock(&dev->struct_mutex);
11948 }
11949 }
11950
11951 static int
11952 intel_check_primary_plane(struct drm_plane *plane,
11953 struct intel_plane_state *state)
11954 {
11955 struct drm_device *dev = plane->dev;
11956 struct drm_i915_private *dev_priv = dev->dev_private;
11957 struct drm_crtc *crtc = state->base.crtc;
11958 struct intel_crtc *intel_crtc;
11959 struct drm_framebuffer *fb = state->base.fb;
11960 struct drm_rect *dest = &state->dst;
11961 struct drm_rect *src = &state->src;
11962 const struct drm_rect *clip = &state->clip;
11963 int ret;
11964
11965 crtc = crtc ? crtc : plane->crtc;
11966 intel_crtc = to_intel_crtc(crtc);
11967
11968 ret = drm_plane_helper_check_update(plane, crtc, fb,
11969 src, dest, clip,
11970 DRM_PLANE_HELPER_NO_SCALING,
11971 DRM_PLANE_HELPER_NO_SCALING,
11972 false, true, &state->visible);
11973 if (ret)
11974 return ret;
11975
11976 if (intel_crtc->active) {
11977 intel_crtc->atomic.wait_for_flips = true;
11978
11979 /*
11980 * FBC does not work on some platforms for rotated
11981 * planes, so disable it when rotation is not 0 and
11982 * update it when rotation is set back to 0.
11983 *
11984 * FIXME: This is redundant with the fbc update done in
11985 * the primary plane enable function except that that
11986 * one is done too late. We eventually need to unify
11987 * this.
11988 */
11989 if (intel_crtc->primary_enabled &&
11990 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11991 dev_priv->fbc.crtc == intel_crtc &&
11992 state->base.rotation != BIT(DRM_ROTATE_0)) {
11993 intel_crtc->atomic.disable_fbc = true;
11994 }
11995
11996 if (state->visible) {
11997 /*
11998 * BDW signals flip done immediately if the plane
11999 * is disabled, even if the plane enable is already
12000 * armed to occur at the next vblank :(
12001 */
12002 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12003 intel_crtc->atomic.wait_vblank = true;
12004 }
12005
12006 intel_crtc->atomic.fb_bits |=
12007 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12008
12009 intel_crtc->atomic.update_fbc = true;
12010
12011 /* Update watermarks on tiling changes. */
12012 if (!plane->state->fb || !state->base.fb ||
12013 plane->state->fb->modifier[0] !=
12014 state->base.fb->modifier[0])
12015 intel_crtc->atomic.update_wm = true;
12016 }
12017
12018 return 0;
12019 }
12020
12021 static void
12022 intel_commit_primary_plane(struct drm_plane *plane,
12023 struct intel_plane_state *state)
12024 {
12025 struct drm_crtc *crtc = state->base.crtc;
12026 struct drm_framebuffer *fb = state->base.fb;
12027 struct drm_device *dev = plane->dev;
12028 struct drm_i915_private *dev_priv = dev->dev_private;
12029 struct intel_crtc *intel_crtc;
12030 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12031 struct intel_plane *intel_plane = to_intel_plane(plane);
12032 struct drm_rect *src = &state->src;
12033
12034 crtc = crtc ? crtc : plane->crtc;
12035 intel_crtc = to_intel_crtc(crtc);
12036
12037 plane->fb = fb;
12038 crtc->x = src->x1 >> 16;
12039 crtc->y = src->y1 >> 16;
12040
12041 intel_plane->obj = obj;
12042
12043 if (intel_crtc->active) {
12044 if (state->visible) {
12045 /* FIXME: kill this fastboot hack */
12046 intel_update_pipe_size(intel_crtc);
12047
12048 intel_crtc->primary_enabled = true;
12049
12050 dev_priv->display.update_primary_plane(crtc, plane->fb,
12051 crtc->x, crtc->y);
12052 } else {
12053 /*
12054 * If clipping results in a non-visible primary plane,
12055 * we'll disable the primary plane. Note that this is
12056 * a bit different than what happens if userspace
12057 * explicitly disables the plane by passing fb=0
12058 * because plane->fb still gets set and pinned.
12059 */
12060 intel_disable_primary_hw_plane(plane, crtc);
12061 }
12062 }
12063 }
12064
12065 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12066 {
12067 struct drm_device *dev = crtc->dev;
12068 struct drm_i915_private *dev_priv = dev->dev_private;
12069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12070 struct intel_plane *intel_plane;
12071 struct drm_plane *p;
12072 unsigned fb_bits = 0;
12073
12074 /* Track fb's for any planes being disabled */
12075 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12076 intel_plane = to_intel_plane(p);
12077
12078 if (intel_crtc->atomic.disabled_planes &
12079 (1 << drm_plane_index(p))) {
12080 switch (p->type) {
12081 case DRM_PLANE_TYPE_PRIMARY:
12082 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12083 break;
12084 case DRM_PLANE_TYPE_CURSOR:
12085 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12086 break;
12087 case DRM_PLANE_TYPE_OVERLAY:
12088 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12089 break;
12090 }
12091
12092 mutex_lock(&dev->struct_mutex);
12093 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12094 mutex_unlock(&dev->struct_mutex);
12095 }
12096 }
12097
12098 if (intel_crtc->atomic.wait_for_flips)
12099 intel_crtc_wait_for_pending_flips(crtc);
12100
12101 if (intel_crtc->atomic.disable_fbc)
12102 intel_fbc_disable(dev);
12103
12104 if (intel_crtc->atomic.pre_disable_primary)
12105 intel_pre_disable_primary(crtc);
12106
12107 if (intel_crtc->atomic.update_wm)
12108 intel_update_watermarks(crtc);
12109
12110 intel_runtime_pm_get(dev_priv);
12111
12112 /* Perform vblank evasion around commit operation */
12113 if (intel_crtc->active)
12114 intel_crtc->atomic.evade =
12115 intel_pipe_update_start(intel_crtc,
12116 &intel_crtc->atomic.start_vbl_count);
12117 }
12118
12119 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12120 {
12121 struct drm_device *dev = crtc->dev;
12122 struct drm_i915_private *dev_priv = dev->dev_private;
12123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12124 struct drm_plane *p;
12125
12126 if (intel_crtc->atomic.evade)
12127 intel_pipe_update_end(intel_crtc,
12128 intel_crtc->atomic.start_vbl_count);
12129
12130 intel_runtime_pm_put(dev_priv);
12131
12132 if (intel_crtc->atomic.wait_vblank)
12133 intel_wait_for_vblank(dev, intel_crtc->pipe);
12134
12135 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12136
12137 if (intel_crtc->atomic.update_fbc) {
12138 mutex_lock(&dev->struct_mutex);
12139 intel_fbc_update(dev);
12140 mutex_unlock(&dev->struct_mutex);
12141 }
12142
12143 if (intel_crtc->atomic.post_enable_primary)
12144 intel_post_enable_primary(crtc);
12145
12146 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12147 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12148 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12149 false, false);
12150
12151 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12152 }
12153
12154 /**
12155 * intel_plane_destroy - destroy a plane
12156 * @plane: plane to destroy
12157 *
12158 * Common destruction function for all types of planes (primary, cursor,
12159 * sprite).
12160 */
12161 void intel_plane_destroy(struct drm_plane *plane)
12162 {
12163 struct intel_plane *intel_plane = to_intel_plane(plane);
12164 drm_plane_cleanup(plane);
12165 kfree(intel_plane);
12166 }
12167
12168 const struct drm_plane_funcs intel_plane_funcs = {
12169 .update_plane = drm_atomic_helper_update_plane,
12170 .disable_plane = drm_atomic_helper_disable_plane,
12171 .destroy = intel_plane_destroy,
12172 .set_property = drm_atomic_helper_plane_set_property,
12173 .atomic_get_property = intel_plane_atomic_get_property,
12174 .atomic_set_property = intel_plane_atomic_set_property,
12175 .atomic_duplicate_state = intel_plane_duplicate_state,
12176 .atomic_destroy_state = intel_plane_destroy_state,
12177
12178 };
12179
12180 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12181 int pipe)
12182 {
12183 struct intel_plane *primary;
12184 struct intel_plane_state *state;
12185 const uint32_t *intel_primary_formats;
12186 int num_formats;
12187
12188 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12189 if (primary == NULL)
12190 return NULL;
12191
12192 state = intel_create_plane_state(&primary->base);
12193 if (!state) {
12194 kfree(primary);
12195 return NULL;
12196 }
12197 primary->base.state = &state->base;
12198
12199 primary->can_scale = false;
12200 primary->max_downscale = 1;
12201 primary->pipe = pipe;
12202 primary->plane = pipe;
12203 primary->check_plane = intel_check_primary_plane;
12204 primary->commit_plane = intel_commit_primary_plane;
12205 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12206 primary->plane = !pipe;
12207
12208 if (INTEL_INFO(dev)->gen <= 3) {
12209 intel_primary_formats = intel_primary_formats_gen2;
12210 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12211 } else {
12212 intel_primary_formats = intel_primary_formats_gen4;
12213 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12214 }
12215
12216 drm_universal_plane_init(dev, &primary->base, 0,
12217 &intel_plane_funcs,
12218 intel_primary_formats, num_formats,
12219 DRM_PLANE_TYPE_PRIMARY);
12220
12221 if (INTEL_INFO(dev)->gen >= 4) {
12222 if (!dev->mode_config.rotation_property)
12223 dev->mode_config.rotation_property =
12224 drm_mode_create_rotation_property(dev,
12225 BIT(DRM_ROTATE_0) |
12226 BIT(DRM_ROTATE_180));
12227 if (dev->mode_config.rotation_property)
12228 drm_object_attach_property(&primary->base.base,
12229 dev->mode_config.rotation_property,
12230 state->base.rotation);
12231 }
12232
12233 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12234
12235 return &primary->base;
12236 }
12237
12238 static int
12239 intel_check_cursor_plane(struct drm_plane *plane,
12240 struct intel_plane_state *state)
12241 {
12242 struct drm_crtc *crtc = state->base.crtc;
12243 struct drm_device *dev = plane->dev;
12244 struct drm_framebuffer *fb = state->base.fb;
12245 struct drm_rect *dest = &state->dst;
12246 struct drm_rect *src = &state->src;
12247 const struct drm_rect *clip = &state->clip;
12248 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12249 struct intel_crtc *intel_crtc;
12250 unsigned stride;
12251 int ret;
12252
12253 crtc = crtc ? crtc : plane->crtc;
12254 intel_crtc = to_intel_crtc(crtc);
12255
12256 ret = drm_plane_helper_check_update(plane, crtc, fb,
12257 src, dest, clip,
12258 DRM_PLANE_HELPER_NO_SCALING,
12259 DRM_PLANE_HELPER_NO_SCALING,
12260 true, true, &state->visible);
12261 if (ret)
12262 return ret;
12263
12264
12265 /* if we want to turn off the cursor ignore width and height */
12266 if (!obj)
12267 goto finish;
12268
12269 /* Check for which cursor types we support */
12270 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12271 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12272 state->base.crtc_w, state->base.crtc_h);
12273 return -EINVAL;
12274 }
12275
12276 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12277 if (obj->base.size < stride * state->base.crtc_h) {
12278 DRM_DEBUG_KMS("buffer is too small\n");
12279 return -ENOMEM;
12280 }
12281
12282 if (fb == crtc->cursor->fb)
12283 return 0;
12284
12285 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12286 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12287 ret = -EINVAL;
12288 }
12289
12290 finish:
12291 if (intel_crtc->active) {
12292 if (intel_crtc->cursor_width != state->base.crtc_w)
12293 intel_crtc->atomic.update_wm = true;
12294
12295 intel_crtc->atomic.fb_bits |=
12296 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12297 }
12298
12299 return ret;
12300 }
12301
12302 static void
12303 intel_commit_cursor_plane(struct drm_plane *plane,
12304 struct intel_plane_state *state)
12305 {
12306 struct drm_crtc *crtc = state->base.crtc;
12307 struct drm_device *dev = plane->dev;
12308 struct intel_crtc *intel_crtc;
12309 struct intel_plane *intel_plane = to_intel_plane(plane);
12310 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12311 uint32_t addr;
12312
12313 crtc = crtc ? crtc : plane->crtc;
12314 intel_crtc = to_intel_crtc(crtc);
12315
12316 plane->fb = state->base.fb;
12317 crtc->cursor_x = state->base.crtc_x;
12318 crtc->cursor_y = state->base.crtc_y;
12319
12320 intel_plane->obj = obj;
12321
12322 if (intel_crtc->cursor_bo == obj)
12323 goto update;
12324
12325 if (!obj)
12326 addr = 0;
12327 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12328 addr = i915_gem_obj_ggtt_offset(obj);
12329 else
12330 addr = obj->phys_handle->busaddr;
12331
12332 intel_crtc->cursor_addr = addr;
12333 intel_crtc->cursor_bo = obj;
12334 update:
12335 intel_crtc->cursor_width = state->base.crtc_w;
12336 intel_crtc->cursor_height = state->base.crtc_h;
12337
12338 if (intel_crtc->active)
12339 intel_crtc_update_cursor(crtc, state->visible);
12340 }
12341
12342 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12343 int pipe)
12344 {
12345 struct intel_plane *cursor;
12346 struct intel_plane_state *state;
12347
12348 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12349 if (cursor == NULL)
12350 return NULL;
12351
12352 state = intel_create_plane_state(&cursor->base);
12353 if (!state) {
12354 kfree(cursor);
12355 return NULL;
12356 }
12357 cursor->base.state = &state->base;
12358
12359 cursor->can_scale = false;
12360 cursor->max_downscale = 1;
12361 cursor->pipe = pipe;
12362 cursor->plane = pipe;
12363 cursor->check_plane = intel_check_cursor_plane;
12364 cursor->commit_plane = intel_commit_cursor_plane;
12365
12366 drm_universal_plane_init(dev, &cursor->base, 0,
12367 &intel_plane_funcs,
12368 intel_cursor_formats,
12369 ARRAY_SIZE(intel_cursor_formats),
12370 DRM_PLANE_TYPE_CURSOR);
12371
12372 if (INTEL_INFO(dev)->gen >= 4) {
12373 if (!dev->mode_config.rotation_property)
12374 dev->mode_config.rotation_property =
12375 drm_mode_create_rotation_property(dev,
12376 BIT(DRM_ROTATE_0) |
12377 BIT(DRM_ROTATE_180));
12378 if (dev->mode_config.rotation_property)
12379 drm_object_attach_property(&cursor->base.base,
12380 dev->mode_config.rotation_property,
12381 state->base.rotation);
12382 }
12383
12384 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12385
12386 return &cursor->base;
12387 }
12388
12389 static void intel_crtc_init(struct drm_device *dev, int pipe)
12390 {
12391 struct drm_i915_private *dev_priv = dev->dev_private;
12392 struct intel_crtc *intel_crtc;
12393 struct intel_crtc_state *crtc_state = NULL;
12394 struct drm_plane *primary = NULL;
12395 struct drm_plane *cursor = NULL;
12396 int i, ret;
12397
12398 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12399 if (intel_crtc == NULL)
12400 return;
12401
12402 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12403 if (!crtc_state)
12404 goto fail;
12405 intel_crtc_set_state(intel_crtc, crtc_state);
12406 crtc_state->base.crtc = &intel_crtc->base;
12407
12408 primary = intel_primary_plane_create(dev, pipe);
12409 if (!primary)
12410 goto fail;
12411
12412 cursor = intel_cursor_plane_create(dev, pipe);
12413 if (!cursor)
12414 goto fail;
12415
12416 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12417 cursor, &intel_crtc_funcs);
12418 if (ret)
12419 goto fail;
12420
12421 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12422 for (i = 0; i < 256; i++) {
12423 intel_crtc->lut_r[i] = i;
12424 intel_crtc->lut_g[i] = i;
12425 intel_crtc->lut_b[i] = i;
12426 }
12427
12428 /*
12429 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12430 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12431 */
12432 intel_crtc->pipe = pipe;
12433 intel_crtc->plane = pipe;
12434 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12435 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12436 intel_crtc->plane = !pipe;
12437 }
12438
12439 intel_crtc->cursor_base = ~0;
12440 intel_crtc->cursor_cntl = ~0;
12441 intel_crtc->cursor_size = ~0;
12442
12443 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12444 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12445 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12446 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12447
12448 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12449
12450 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12451
12452 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12453 return;
12454
12455 fail:
12456 if (primary)
12457 drm_plane_cleanup(primary);
12458 if (cursor)
12459 drm_plane_cleanup(cursor);
12460 kfree(crtc_state);
12461 kfree(intel_crtc);
12462 }
12463
12464 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12465 {
12466 struct drm_encoder *encoder = connector->base.encoder;
12467 struct drm_device *dev = connector->base.dev;
12468
12469 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12470
12471 if (!encoder || WARN_ON(!encoder->crtc))
12472 return INVALID_PIPE;
12473
12474 return to_intel_crtc(encoder->crtc)->pipe;
12475 }
12476
12477 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12478 struct drm_file *file)
12479 {
12480 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12481 struct drm_crtc *drmmode_crtc;
12482 struct intel_crtc *crtc;
12483
12484 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12485
12486 if (!drmmode_crtc) {
12487 DRM_ERROR("no such CRTC id\n");
12488 return -ENOENT;
12489 }
12490
12491 crtc = to_intel_crtc(drmmode_crtc);
12492 pipe_from_crtc_id->pipe = crtc->pipe;
12493
12494 return 0;
12495 }
12496
12497 static int intel_encoder_clones(struct intel_encoder *encoder)
12498 {
12499 struct drm_device *dev = encoder->base.dev;
12500 struct intel_encoder *source_encoder;
12501 int index_mask = 0;
12502 int entry = 0;
12503
12504 for_each_intel_encoder(dev, source_encoder) {
12505 if (encoders_cloneable(encoder, source_encoder))
12506 index_mask |= (1 << entry);
12507
12508 entry++;
12509 }
12510
12511 return index_mask;
12512 }
12513
12514 static bool has_edp_a(struct drm_device *dev)
12515 {
12516 struct drm_i915_private *dev_priv = dev->dev_private;
12517
12518 if (!IS_MOBILE(dev))
12519 return false;
12520
12521 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12522 return false;
12523
12524 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12525 return false;
12526
12527 return true;
12528 }
12529
12530 static bool intel_crt_present(struct drm_device *dev)
12531 {
12532 struct drm_i915_private *dev_priv = dev->dev_private;
12533
12534 if (INTEL_INFO(dev)->gen >= 9)
12535 return false;
12536
12537 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12538 return false;
12539
12540 if (IS_CHERRYVIEW(dev))
12541 return false;
12542
12543 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12544 return false;
12545
12546 return true;
12547 }
12548
12549 static void intel_setup_outputs(struct drm_device *dev)
12550 {
12551 struct drm_i915_private *dev_priv = dev->dev_private;
12552 struct intel_encoder *encoder;
12553 struct drm_connector *connector;
12554 bool dpd_is_edp = false;
12555
12556 intel_lvds_init(dev);
12557
12558 if (intel_crt_present(dev))
12559 intel_crt_init(dev);
12560
12561 if (HAS_DDI(dev)) {
12562 int found;
12563
12564 /* Haswell uses DDI functions to detect digital outputs */
12565 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12566 /* DDI A only supports eDP */
12567 if (found)
12568 intel_ddi_init(dev, PORT_A);
12569
12570 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12571 * register */
12572 found = I915_READ(SFUSE_STRAP);
12573
12574 if (found & SFUSE_STRAP_DDIB_DETECTED)
12575 intel_ddi_init(dev, PORT_B);
12576 if (found & SFUSE_STRAP_DDIC_DETECTED)
12577 intel_ddi_init(dev, PORT_C);
12578 if (found & SFUSE_STRAP_DDID_DETECTED)
12579 intel_ddi_init(dev, PORT_D);
12580 } else if (HAS_PCH_SPLIT(dev)) {
12581 int found;
12582 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12583
12584 if (has_edp_a(dev))
12585 intel_dp_init(dev, DP_A, PORT_A);
12586
12587 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12588 /* PCH SDVOB multiplex with HDMIB */
12589 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12590 if (!found)
12591 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12592 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12593 intel_dp_init(dev, PCH_DP_B, PORT_B);
12594 }
12595
12596 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12597 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12598
12599 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12600 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12601
12602 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12603 intel_dp_init(dev, PCH_DP_C, PORT_C);
12604
12605 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12606 intel_dp_init(dev, PCH_DP_D, PORT_D);
12607 } else if (IS_VALLEYVIEW(dev)) {
12608 /*
12609 * The DP_DETECTED bit is the latched state of the DDC
12610 * SDA pin at boot. However since eDP doesn't require DDC
12611 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12612 * eDP ports may have been muxed to an alternate function.
12613 * Thus we can't rely on the DP_DETECTED bit alone to detect
12614 * eDP ports. Consult the VBT as well as DP_DETECTED to
12615 * detect eDP ports.
12616 */
12617 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12618 !intel_dp_is_edp(dev, PORT_B))
12619 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12620 PORT_B);
12621 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12622 intel_dp_is_edp(dev, PORT_B))
12623 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12624
12625 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12626 !intel_dp_is_edp(dev, PORT_C))
12627 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12628 PORT_C);
12629 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12630 intel_dp_is_edp(dev, PORT_C))
12631 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12632
12633 if (IS_CHERRYVIEW(dev)) {
12634 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12635 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12636 PORT_D);
12637 /* eDP not supported on port D, so don't check VBT */
12638 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12639 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12640 }
12641
12642 intel_dsi_init(dev);
12643 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12644 bool found = false;
12645
12646 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12647 DRM_DEBUG_KMS("probing SDVOB\n");
12648 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12649 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12650 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12651 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12652 }
12653
12654 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12655 intel_dp_init(dev, DP_B, PORT_B);
12656 }
12657
12658 /* Before G4X SDVOC doesn't have its own detect register */
12659
12660 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12661 DRM_DEBUG_KMS("probing SDVOC\n");
12662 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12663 }
12664
12665 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12666
12667 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12668 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12669 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12670 }
12671 if (SUPPORTS_INTEGRATED_DP(dev))
12672 intel_dp_init(dev, DP_C, PORT_C);
12673 }
12674
12675 if (SUPPORTS_INTEGRATED_DP(dev) &&
12676 (I915_READ(DP_D) & DP_DETECTED))
12677 intel_dp_init(dev, DP_D, PORT_D);
12678 } else if (IS_GEN2(dev))
12679 intel_dvo_init(dev);
12680
12681 if (SUPPORTS_TV(dev))
12682 intel_tv_init(dev);
12683
12684 /*
12685 * FIXME: We don't have full atomic support yet, but we want to be
12686 * able to enable/test plane updates via the atomic interface in the
12687 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12688 * will take some atomic codepaths to lookup properties during
12689 * drmModeGetConnector() that unconditionally dereference
12690 * connector->state.
12691 *
12692 * We create a dummy connector state here for each connector to ensure
12693 * the DRM core doesn't try to dereference a NULL connector->state.
12694 * The actual connector properties will never be updated or contain
12695 * useful information, but since we're doing this specifically for
12696 * testing/debug of the plane operations (and only when a specific
12697 * kernel module option is given), that shouldn't really matter.
12698 *
12699 * Once atomic support for crtc's + connectors lands, this loop should
12700 * be removed since we'll be setting up real connector state, which
12701 * will contain Intel-specific properties.
12702 */
12703 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12704 list_for_each_entry(connector,
12705 &dev->mode_config.connector_list,
12706 head) {
12707 if (!WARN_ON(connector->state)) {
12708 connector->state =
12709 kzalloc(sizeof(*connector->state),
12710 GFP_KERNEL);
12711 }
12712 }
12713 }
12714
12715 intel_psr_init(dev);
12716
12717 for_each_intel_encoder(dev, encoder) {
12718 encoder->base.possible_crtcs = encoder->crtc_mask;
12719 encoder->base.possible_clones =
12720 intel_encoder_clones(encoder);
12721 }
12722
12723 intel_init_pch_refclk(dev);
12724
12725 drm_helper_move_panel_connectors_to_head(dev);
12726 }
12727
12728 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12729 {
12730 struct drm_device *dev = fb->dev;
12731 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12732
12733 drm_framebuffer_cleanup(fb);
12734 mutex_lock(&dev->struct_mutex);
12735 WARN_ON(!intel_fb->obj->framebuffer_references--);
12736 drm_gem_object_unreference(&intel_fb->obj->base);
12737 mutex_unlock(&dev->struct_mutex);
12738 kfree(intel_fb);
12739 }
12740
12741 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12742 struct drm_file *file,
12743 unsigned int *handle)
12744 {
12745 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12746 struct drm_i915_gem_object *obj = intel_fb->obj;
12747
12748 return drm_gem_handle_create(file, &obj->base, handle);
12749 }
12750
12751 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12752 .destroy = intel_user_framebuffer_destroy,
12753 .create_handle = intel_user_framebuffer_create_handle,
12754 };
12755
12756 static
12757 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12758 uint32_t pixel_format)
12759 {
12760 u32 gen = INTEL_INFO(dev)->gen;
12761
12762 if (gen >= 9) {
12763 /* "The stride in bytes must not exceed the of the size of 8K
12764 * pixels and 32K bytes."
12765 */
12766 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12767 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12768 return 32*1024;
12769 } else if (gen >= 4) {
12770 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12771 return 16*1024;
12772 else
12773 return 32*1024;
12774 } else if (gen >= 3) {
12775 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12776 return 8*1024;
12777 else
12778 return 16*1024;
12779 } else {
12780 /* XXX DSPC is limited to 4k tiled */
12781 return 8*1024;
12782 }
12783 }
12784
12785 static int intel_framebuffer_init(struct drm_device *dev,
12786 struct intel_framebuffer *intel_fb,
12787 struct drm_mode_fb_cmd2 *mode_cmd,
12788 struct drm_i915_gem_object *obj)
12789 {
12790 int aligned_height;
12791 int ret;
12792 u32 pitch_limit, stride_alignment;
12793
12794 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12795
12796 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12797 /* Enforce that fb modifier and tiling mode match, but only for
12798 * X-tiled. This is needed for FBC. */
12799 if (!!(obj->tiling_mode == I915_TILING_X) !=
12800 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12801 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12802 return -EINVAL;
12803 }
12804 } else {
12805 if (obj->tiling_mode == I915_TILING_X)
12806 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12807 else if (obj->tiling_mode == I915_TILING_Y) {
12808 DRM_DEBUG("No Y tiling for legacy addfb\n");
12809 return -EINVAL;
12810 }
12811 }
12812
12813 /* Passed in modifier sanity checking. */
12814 switch (mode_cmd->modifier[0]) {
12815 case I915_FORMAT_MOD_Y_TILED:
12816 case I915_FORMAT_MOD_Yf_TILED:
12817 if (INTEL_INFO(dev)->gen < 9) {
12818 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12819 mode_cmd->modifier[0]);
12820 return -EINVAL;
12821 }
12822 case DRM_FORMAT_MOD_NONE:
12823 case I915_FORMAT_MOD_X_TILED:
12824 break;
12825 default:
12826 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12827 mode_cmd->modifier[0]);
12828 return -EINVAL;
12829 }
12830
12831 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12832 mode_cmd->pixel_format);
12833 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12834 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12835 mode_cmd->pitches[0], stride_alignment);
12836 return -EINVAL;
12837 }
12838
12839 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12840 mode_cmd->pixel_format);
12841 if (mode_cmd->pitches[0] > pitch_limit) {
12842 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12843 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12844 "tiled" : "linear",
12845 mode_cmd->pitches[0], pitch_limit);
12846 return -EINVAL;
12847 }
12848
12849 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12850 mode_cmd->pitches[0] != obj->stride) {
12851 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12852 mode_cmd->pitches[0], obj->stride);
12853 return -EINVAL;
12854 }
12855
12856 /* Reject formats not supported by any plane early. */
12857 switch (mode_cmd->pixel_format) {
12858 case DRM_FORMAT_C8:
12859 case DRM_FORMAT_RGB565:
12860 case DRM_FORMAT_XRGB8888:
12861 case DRM_FORMAT_ARGB8888:
12862 break;
12863 case DRM_FORMAT_XRGB1555:
12864 case DRM_FORMAT_ARGB1555:
12865 if (INTEL_INFO(dev)->gen > 3) {
12866 DRM_DEBUG("unsupported pixel format: %s\n",
12867 drm_get_format_name(mode_cmd->pixel_format));
12868 return -EINVAL;
12869 }
12870 break;
12871 case DRM_FORMAT_XBGR8888:
12872 case DRM_FORMAT_ABGR8888:
12873 case DRM_FORMAT_XRGB2101010:
12874 case DRM_FORMAT_ARGB2101010:
12875 case DRM_FORMAT_XBGR2101010:
12876 case DRM_FORMAT_ABGR2101010:
12877 if (INTEL_INFO(dev)->gen < 4) {
12878 DRM_DEBUG("unsupported pixel format: %s\n",
12879 drm_get_format_name(mode_cmd->pixel_format));
12880 return -EINVAL;
12881 }
12882 break;
12883 case DRM_FORMAT_YUYV:
12884 case DRM_FORMAT_UYVY:
12885 case DRM_FORMAT_YVYU:
12886 case DRM_FORMAT_VYUY:
12887 if (INTEL_INFO(dev)->gen < 5) {
12888 DRM_DEBUG("unsupported pixel format: %s\n",
12889 drm_get_format_name(mode_cmd->pixel_format));
12890 return -EINVAL;
12891 }
12892 break;
12893 default:
12894 DRM_DEBUG("unsupported pixel format: %s\n",
12895 drm_get_format_name(mode_cmd->pixel_format));
12896 return -EINVAL;
12897 }
12898
12899 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12900 if (mode_cmd->offsets[0] != 0)
12901 return -EINVAL;
12902
12903 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12904 mode_cmd->pixel_format,
12905 mode_cmd->modifier[0]);
12906 /* FIXME drm helper for size checks (especially planar formats)? */
12907 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12908 return -EINVAL;
12909
12910 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12911 intel_fb->obj = obj;
12912 intel_fb->obj->framebuffer_references++;
12913
12914 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12915 if (ret) {
12916 DRM_ERROR("framebuffer init failed %d\n", ret);
12917 return ret;
12918 }
12919
12920 return 0;
12921 }
12922
12923 static struct drm_framebuffer *
12924 intel_user_framebuffer_create(struct drm_device *dev,
12925 struct drm_file *filp,
12926 struct drm_mode_fb_cmd2 *mode_cmd)
12927 {
12928 struct drm_i915_gem_object *obj;
12929
12930 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12931 mode_cmd->handles[0]));
12932 if (&obj->base == NULL)
12933 return ERR_PTR(-ENOENT);
12934
12935 return intel_framebuffer_create(dev, mode_cmd, obj);
12936 }
12937
12938 #ifndef CONFIG_DRM_I915_FBDEV
12939 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12940 {
12941 }
12942 #endif
12943
12944 static const struct drm_mode_config_funcs intel_mode_funcs = {
12945 .fb_create = intel_user_framebuffer_create,
12946 .output_poll_changed = intel_fbdev_output_poll_changed,
12947 .atomic_check = intel_atomic_check,
12948 .atomic_commit = intel_atomic_commit,
12949 };
12950
12951 /* Set up chip specific display functions */
12952 static void intel_init_display(struct drm_device *dev)
12953 {
12954 struct drm_i915_private *dev_priv = dev->dev_private;
12955
12956 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12957 dev_priv->display.find_dpll = g4x_find_best_dpll;
12958 else if (IS_CHERRYVIEW(dev))
12959 dev_priv->display.find_dpll = chv_find_best_dpll;
12960 else if (IS_VALLEYVIEW(dev))
12961 dev_priv->display.find_dpll = vlv_find_best_dpll;
12962 else if (IS_PINEVIEW(dev))
12963 dev_priv->display.find_dpll = pnv_find_best_dpll;
12964 else
12965 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12966
12967 if (INTEL_INFO(dev)->gen >= 9) {
12968 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12969 dev_priv->display.get_initial_plane_config =
12970 skylake_get_initial_plane_config;
12971 dev_priv->display.crtc_compute_clock =
12972 haswell_crtc_compute_clock;
12973 dev_priv->display.crtc_enable = haswell_crtc_enable;
12974 dev_priv->display.crtc_disable = haswell_crtc_disable;
12975 dev_priv->display.off = ironlake_crtc_off;
12976 dev_priv->display.update_primary_plane =
12977 skylake_update_primary_plane;
12978 } else if (HAS_DDI(dev)) {
12979 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12980 dev_priv->display.get_initial_plane_config =
12981 ironlake_get_initial_plane_config;
12982 dev_priv->display.crtc_compute_clock =
12983 haswell_crtc_compute_clock;
12984 dev_priv->display.crtc_enable = haswell_crtc_enable;
12985 dev_priv->display.crtc_disable = haswell_crtc_disable;
12986 dev_priv->display.off = ironlake_crtc_off;
12987 dev_priv->display.update_primary_plane =
12988 ironlake_update_primary_plane;
12989 } else if (HAS_PCH_SPLIT(dev)) {
12990 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12991 dev_priv->display.get_initial_plane_config =
12992 ironlake_get_initial_plane_config;
12993 dev_priv->display.crtc_compute_clock =
12994 ironlake_crtc_compute_clock;
12995 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12996 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12997 dev_priv->display.off = ironlake_crtc_off;
12998 dev_priv->display.update_primary_plane =
12999 ironlake_update_primary_plane;
13000 } else if (IS_VALLEYVIEW(dev)) {
13001 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13002 dev_priv->display.get_initial_plane_config =
13003 i9xx_get_initial_plane_config;
13004 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13005 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13006 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13007 dev_priv->display.off = i9xx_crtc_off;
13008 dev_priv->display.update_primary_plane =
13009 i9xx_update_primary_plane;
13010 } else {
13011 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13012 dev_priv->display.get_initial_plane_config =
13013 i9xx_get_initial_plane_config;
13014 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13015 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13016 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13017 dev_priv->display.off = i9xx_crtc_off;
13018 dev_priv->display.update_primary_plane =
13019 i9xx_update_primary_plane;
13020 }
13021
13022 /* Returns the core display clock speed */
13023 if (IS_VALLEYVIEW(dev))
13024 dev_priv->display.get_display_clock_speed =
13025 valleyview_get_display_clock_speed;
13026 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13027 dev_priv->display.get_display_clock_speed =
13028 i945_get_display_clock_speed;
13029 else if (IS_I915G(dev))
13030 dev_priv->display.get_display_clock_speed =
13031 i915_get_display_clock_speed;
13032 else if (IS_I945GM(dev) || IS_845G(dev))
13033 dev_priv->display.get_display_clock_speed =
13034 i9xx_misc_get_display_clock_speed;
13035 else if (IS_PINEVIEW(dev))
13036 dev_priv->display.get_display_clock_speed =
13037 pnv_get_display_clock_speed;
13038 else if (IS_I915GM(dev))
13039 dev_priv->display.get_display_clock_speed =
13040 i915gm_get_display_clock_speed;
13041 else if (IS_I865G(dev))
13042 dev_priv->display.get_display_clock_speed =
13043 i865_get_display_clock_speed;
13044 else if (IS_I85X(dev))
13045 dev_priv->display.get_display_clock_speed =
13046 i855_get_display_clock_speed;
13047 else /* 852, 830 */
13048 dev_priv->display.get_display_clock_speed =
13049 i830_get_display_clock_speed;
13050
13051 if (IS_GEN5(dev)) {
13052 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13053 } else if (IS_GEN6(dev)) {
13054 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13055 } else if (IS_IVYBRIDGE(dev)) {
13056 /* FIXME: detect B0+ stepping and use auto training */
13057 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13058 dev_priv->display.modeset_global_resources =
13059 ivb_modeset_global_resources;
13060 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13061 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13062 } else if (IS_VALLEYVIEW(dev)) {
13063 dev_priv->display.modeset_global_resources =
13064 valleyview_modeset_global_resources;
13065 }
13066
13067 switch (INTEL_INFO(dev)->gen) {
13068 case 2:
13069 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13070 break;
13071
13072 case 3:
13073 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13074 break;
13075
13076 case 4:
13077 case 5:
13078 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13079 break;
13080
13081 case 6:
13082 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13083 break;
13084 case 7:
13085 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13086 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13087 break;
13088 case 9:
13089 /* Drop through - unsupported since execlist only. */
13090 default:
13091 /* Default just returns -ENODEV to indicate unsupported */
13092 dev_priv->display.queue_flip = intel_default_queue_flip;
13093 }
13094
13095 intel_panel_init_backlight_funcs(dev);
13096
13097 mutex_init(&dev_priv->pps_mutex);
13098 }
13099
13100 /*
13101 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13102 * resume, or other times. This quirk makes sure that's the case for
13103 * affected systems.
13104 */
13105 static void quirk_pipea_force(struct drm_device *dev)
13106 {
13107 struct drm_i915_private *dev_priv = dev->dev_private;
13108
13109 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13110 DRM_INFO("applying pipe a force quirk\n");
13111 }
13112
13113 static void quirk_pipeb_force(struct drm_device *dev)
13114 {
13115 struct drm_i915_private *dev_priv = dev->dev_private;
13116
13117 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13118 DRM_INFO("applying pipe b force quirk\n");
13119 }
13120
13121 /*
13122 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13123 */
13124 static void quirk_ssc_force_disable(struct drm_device *dev)
13125 {
13126 struct drm_i915_private *dev_priv = dev->dev_private;
13127 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13128 DRM_INFO("applying lvds SSC disable quirk\n");
13129 }
13130
13131 /*
13132 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13133 * brightness value
13134 */
13135 static void quirk_invert_brightness(struct drm_device *dev)
13136 {
13137 struct drm_i915_private *dev_priv = dev->dev_private;
13138 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13139 DRM_INFO("applying inverted panel brightness quirk\n");
13140 }
13141
13142 /* Some VBT's incorrectly indicate no backlight is present */
13143 static void quirk_backlight_present(struct drm_device *dev)
13144 {
13145 struct drm_i915_private *dev_priv = dev->dev_private;
13146 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13147 DRM_INFO("applying backlight present quirk\n");
13148 }
13149
13150 struct intel_quirk {
13151 int device;
13152 int subsystem_vendor;
13153 int subsystem_device;
13154 void (*hook)(struct drm_device *dev);
13155 };
13156
13157 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13158 struct intel_dmi_quirk {
13159 void (*hook)(struct drm_device *dev);
13160 const struct dmi_system_id (*dmi_id_list)[];
13161 };
13162
13163 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13164 {
13165 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13166 return 1;
13167 }
13168
13169 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13170 {
13171 .dmi_id_list = &(const struct dmi_system_id[]) {
13172 {
13173 .callback = intel_dmi_reverse_brightness,
13174 .ident = "NCR Corporation",
13175 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13176 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13177 },
13178 },
13179 { } /* terminating entry */
13180 },
13181 .hook = quirk_invert_brightness,
13182 },
13183 };
13184
13185 static struct intel_quirk intel_quirks[] = {
13186 /* HP Mini needs pipe A force quirk (LP: #322104) */
13187 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13188
13189 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13190 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13191
13192 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13193 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13194
13195 /* 830 needs to leave pipe A & dpll A up */
13196 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13197
13198 /* 830 needs to leave pipe B & dpll B up */
13199 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13200
13201 /* Lenovo U160 cannot use SSC on LVDS */
13202 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13203
13204 /* Sony Vaio Y cannot use SSC on LVDS */
13205 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13206
13207 /* Acer Aspire 5734Z must invert backlight brightness */
13208 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13209
13210 /* Acer/eMachines G725 */
13211 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13212
13213 /* Acer/eMachines e725 */
13214 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13215
13216 /* Acer/Packard Bell NCL20 */
13217 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13218
13219 /* Acer Aspire 4736Z */
13220 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13221
13222 /* Acer Aspire 5336 */
13223 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13224
13225 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13226 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13227
13228 /* Acer C720 Chromebook (Core i3 4005U) */
13229 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13230
13231 /* Apple Macbook 2,1 (Core 2 T7400) */
13232 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13233
13234 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13235 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13236
13237 /* HP Chromebook 14 (Celeron 2955U) */
13238 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13239 };
13240
13241 static void intel_init_quirks(struct drm_device *dev)
13242 {
13243 struct pci_dev *d = dev->pdev;
13244 int i;
13245
13246 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13247 struct intel_quirk *q = &intel_quirks[i];
13248
13249 if (d->device == q->device &&
13250 (d->subsystem_vendor == q->subsystem_vendor ||
13251 q->subsystem_vendor == PCI_ANY_ID) &&
13252 (d->subsystem_device == q->subsystem_device ||
13253 q->subsystem_device == PCI_ANY_ID))
13254 q->hook(dev);
13255 }
13256 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13257 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13258 intel_dmi_quirks[i].hook(dev);
13259 }
13260 }
13261
13262 /* Disable the VGA plane that we never use */
13263 static void i915_disable_vga(struct drm_device *dev)
13264 {
13265 struct drm_i915_private *dev_priv = dev->dev_private;
13266 u8 sr1;
13267 u32 vga_reg = i915_vgacntrl_reg(dev);
13268
13269 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13270 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13271 outb(SR01, VGA_SR_INDEX);
13272 sr1 = inb(VGA_SR_DATA);
13273 outb(sr1 | 1<<5, VGA_SR_DATA);
13274 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13275 udelay(300);
13276
13277 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13278 POSTING_READ(vga_reg);
13279 }
13280
13281 void intel_modeset_init_hw(struct drm_device *dev)
13282 {
13283 intel_prepare_ddi(dev);
13284
13285 if (IS_VALLEYVIEW(dev))
13286 vlv_update_cdclk(dev);
13287
13288 intel_init_clock_gating(dev);
13289
13290 intel_enable_gt_powersave(dev);
13291 }
13292
13293 void intel_modeset_init(struct drm_device *dev)
13294 {
13295 struct drm_i915_private *dev_priv = dev->dev_private;
13296 int sprite, ret;
13297 enum pipe pipe;
13298 struct intel_crtc *crtc;
13299
13300 drm_mode_config_init(dev);
13301
13302 dev->mode_config.min_width = 0;
13303 dev->mode_config.min_height = 0;
13304
13305 dev->mode_config.preferred_depth = 24;
13306 dev->mode_config.prefer_shadow = 1;
13307
13308 dev->mode_config.allow_fb_modifiers = true;
13309
13310 dev->mode_config.funcs = &intel_mode_funcs;
13311
13312 intel_init_quirks(dev);
13313
13314 intel_init_pm(dev);
13315
13316 if (INTEL_INFO(dev)->num_pipes == 0)
13317 return;
13318
13319 intel_init_display(dev);
13320 intel_init_audio(dev);
13321
13322 if (IS_GEN2(dev)) {
13323 dev->mode_config.max_width = 2048;
13324 dev->mode_config.max_height = 2048;
13325 } else if (IS_GEN3(dev)) {
13326 dev->mode_config.max_width = 4096;
13327 dev->mode_config.max_height = 4096;
13328 } else {
13329 dev->mode_config.max_width = 8192;
13330 dev->mode_config.max_height = 8192;
13331 }
13332
13333 if (IS_845G(dev) || IS_I865G(dev)) {
13334 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13335 dev->mode_config.cursor_height = 1023;
13336 } else if (IS_GEN2(dev)) {
13337 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13338 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13339 } else {
13340 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13341 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13342 }
13343
13344 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13345
13346 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13347 INTEL_INFO(dev)->num_pipes,
13348 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13349
13350 for_each_pipe(dev_priv, pipe) {
13351 intel_crtc_init(dev, pipe);
13352 for_each_sprite(pipe, sprite) {
13353 ret = intel_plane_init(dev, pipe, sprite);
13354 if (ret)
13355 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13356 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13357 }
13358 }
13359
13360 intel_init_dpio(dev);
13361
13362 intel_shared_dpll_init(dev);
13363
13364 /* Just disable it once at startup */
13365 i915_disable_vga(dev);
13366 intel_setup_outputs(dev);
13367
13368 /* Just in case the BIOS is doing something questionable. */
13369 intel_fbc_disable(dev);
13370
13371 drm_modeset_lock_all(dev);
13372 intel_modeset_setup_hw_state(dev, false);
13373 drm_modeset_unlock_all(dev);
13374
13375 for_each_intel_crtc(dev, crtc) {
13376 if (!crtc->active)
13377 continue;
13378
13379 /*
13380 * Note that reserving the BIOS fb up front prevents us
13381 * from stuffing other stolen allocations like the ring
13382 * on top. This prevents some ugliness at boot time, and
13383 * can even allow for smooth boot transitions if the BIOS
13384 * fb is large enough for the active pipe configuration.
13385 */
13386 if (dev_priv->display.get_initial_plane_config) {
13387 dev_priv->display.get_initial_plane_config(crtc,
13388 &crtc->plane_config);
13389 /*
13390 * If the fb is shared between multiple heads, we'll
13391 * just get the first one.
13392 */
13393 intel_find_plane_obj(crtc, &crtc->plane_config);
13394 }
13395 }
13396 }
13397
13398 static void intel_enable_pipe_a(struct drm_device *dev)
13399 {
13400 struct intel_connector *connector;
13401 struct drm_connector *crt = NULL;
13402 struct intel_load_detect_pipe load_detect_temp;
13403 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13404
13405 /* We can't just switch on the pipe A, we need to set things up with a
13406 * proper mode and output configuration. As a gross hack, enable pipe A
13407 * by enabling the load detect pipe once. */
13408 list_for_each_entry(connector,
13409 &dev->mode_config.connector_list,
13410 base.head) {
13411 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13412 crt = &connector->base;
13413 break;
13414 }
13415 }
13416
13417 if (!crt)
13418 return;
13419
13420 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13421 intel_release_load_detect_pipe(crt, &load_detect_temp);
13422 }
13423
13424 static bool
13425 intel_check_plane_mapping(struct intel_crtc *crtc)
13426 {
13427 struct drm_device *dev = crtc->base.dev;
13428 struct drm_i915_private *dev_priv = dev->dev_private;
13429 u32 reg, val;
13430
13431 if (INTEL_INFO(dev)->num_pipes == 1)
13432 return true;
13433
13434 reg = DSPCNTR(!crtc->plane);
13435 val = I915_READ(reg);
13436
13437 if ((val & DISPLAY_PLANE_ENABLE) &&
13438 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13439 return false;
13440
13441 return true;
13442 }
13443
13444 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13445 {
13446 struct drm_device *dev = crtc->base.dev;
13447 struct drm_i915_private *dev_priv = dev->dev_private;
13448 u32 reg;
13449
13450 /* Clear any frame start delays used for debugging left by the BIOS */
13451 reg = PIPECONF(crtc->config->cpu_transcoder);
13452 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13453
13454 /* restore vblank interrupts to correct state */
13455 drm_crtc_vblank_reset(&crtc->base);
13456 if (crtc->active) {
13457 update_scanline_offset(crtc);
13458 drm_crtc_vblank_on(&crtc->base);
13459 }
13460
13461 /* We need to sanitize the plane -> pipe mapping first because this will
13462 * disable the crtc (and hence change the state) if it is wrong. Note
13463 * that gen4+ has a fixed plane -> pipe mapping. */
13464 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13465 struct intel_connector *connector;
13466 bool plane;
13467
13468 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13469 crtc->base.base.id);
13470
13471 /* Pipe has the wrong plane attached and the plane is active.
13472 * Temporarily change the plane mapping and disable everything
13473 * ... */
13474 plane = crtc->plane;
13475 crtc->plane = !plane;
13476 crtc->primary_enabled = true;
13477 dev_priv->display.crtc_disable(&crtc->base);
13478 crtc->plane = plane;
13479
13480 /* ... and break all links. */
13481 list_for_each_entry(connector, &dev->mode_config.connector_list,
13482 base.head) {
13483 if (connector->encoder->base.crtc != &crtc->base)
13484 continue;
13485
13486 connector->base.dpms = DRM_MODE_DPMS_OFF;
13487 connector->base.encoder = NULL;
13488 }
13489 /* multiple connectors may have the same encoder:
13490 * handle them and break crtc link separately */
13491 list_for_each_entry(connector, &dev->mode_config.connector_list,
13492 base.head)
13493 if (connector->encoder->base.crtc == &crtc->base) {
13494 connector->encoder->base.crtc = NULL;
13495 connector->encoder->connectors_active = false;
13496 }
13497
13498 WARN_ON(crtc->active);
13499 crtc->base.state->enable = false;
13500 crtc->base.enabled = false;
13501 }
13502
13503 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13504 crtc->pipe == PIPE_A && !crtc->active) {
13505 /* BIOS forgot to enable pipe A, this mostly happens after
13506 * resume. Force-enable the pipe to fix this, the update_dpms
13507 * call below we restore the pipe to the right state, but leave
13508 * the required bits on. */
13509 intel_enable_pipe_a(dev);
13510 }
13511
13512 /* Adjust the state of the output pipe according to whether we
13513 * have active connectors/encoders. */
13514 intel_crtc_update_dpms(&crtc->base);
13515
13516 if (crtc->active != crtc->base.state->enable) {
13517 struct intel_encoder *encoder;
13518
13519 /* This can happen either due to bugs in the get_hw_state
13520 * functions or because the pipe is force-enabled due to the
13521 * pipe A quirk. */
13522 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13523 crtc->base.base.id,
13524 crtc->base.state->enable ? "enabled" : "disabled",
13525 crtc->active ? "enabled" : "disabled");
13526
13527 crtc->base.state->enable = crtc->active;
13528 crtc->base.enabled = crtc->active;
13529
13530 /* Because we only establish the connector -> encoder ->
13531 * crtc links if something is active, this means the
13532 * crtc is now deactivated. Break the links. connector
13533 * -> encoder links are only establish when things are
13534 * actually up, hence no need to break them. */
13535 WARN_ON(crtc->active);
13536
13537 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13538 WARN_ON(encoder->connectors_active);
13539 encoder->base.crtc = NULL;
13540 }
13541 }
13542
13543 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13544 /*
13545 * We start out with underrun reporting disabled to avoid races.
13546 * For correct bookkeeping mark this on active crtcs.
13547 *
13548 * Also on gmch platforms we dont have any hardware bits to
13549 * disable the underrun reporting. Which means we need to start
13550 * out with underrun reporting disabled also on inactive pipes,
13551 * since otherwise we'll complain about the garbage we read when
13552 * e.g. coming up after runtime pm.
13553 *
13554 * No protection against concurrent access is required - at
13555 * worst a fifo underrun happens which also sets this to false.
13556 */
13557 crtc->cpu_fifo_underrun_disabled = true;
13558 crtc->pch_fifo_underrun_disabled = true;
13559 }
13560 }
13561
13562 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13563 {
13564 struct intel_connector *connector;
13565 struct drm_device *dev = encoder->base.dev;
13566
13567 /* We need to check both for a crtc link (meaning that the
13568 * encoder is active and trying to read from a pipe) and the
13569 * pipe itself being active. */
13570 bool has_active_crtc = encoder->base.crtc &&
13571 to_intel_crtc(encoder->base.crtc)->active;
13572
13573 if (encoder->connectors_active && !has_active_crtc) {
13574 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13575 encoder->base.base.id,
13576 encoder->base.name);
13577
13578 /* Connector is active, but has no active pipe. This is
13579 * fallout from our resume register restoring. Disable
13580 * the encoder manually again. */
13581 if (encoder->base.crtc) {
13582 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13583 encoder->base.base.id,
13584 encoder->base.name);
13585 encoder->disable(encoder);
13586 if (encoder->post_disable)
13587 encoder->post_disable(encoder);
13588 }
13589 encoder->base.crtc = NULL;
13590 encoder->connectors_active = false;
13591
13592 /* Inconsistent output/port/pipe state happens presumably due to
13593 * a bug in one of the get_hw_state functions. Or someplace else
13594 * in our code, like the register restore mess on resume. Clamp
13595 * things to off as a safer default. */
13596 list_for_each_entry(connector,
13597 &dev->mode_config.connector_list,
13598 base.head) {
13599 if (connector->encoder != encoder)
13600 continue;
13601 connector->base.dpms = DRM_MODE_DPMS_OFF;
13602 connector->base.encoder = NULL;
13603 }
13604 }
13605 /* Enabled encoders without active connectors will be fixed in
13606 * the crtc fixup. */
13607 }
13608
13609 void i915_redisable_vga_power_on(struct drm_device *dev)
13610 {
13611 struct drm_i915_private *dev_priv = dev->dev_private;
13612 u32 vga_reg = i915_vgacntrl_reg(dev);
13613
13614 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13615 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13616 i915_disable_vga(dev);
13617 }
13618 }
13619
13620 void i915_redisable_vga(struct drm_device *dev)
13621 {
13622 struct drm_i915_private *dev_priv = dev->dev_private;
13623
13624 /* This function can be called both from intel_modeset_setup_hw_state or
13625 * at a very early point in our resume sequence, where the power well
13626 * structures are not yet restored. Since this function is at a very
13627 * paranoid "someone might have enabled VGA while we were not looking"
13628 * level, just check if the power well is enabled instead of trying to
13629 * follow the "don't touch the power well if we don't need it" policy
13630 * the rest of the driver uses. */
13631 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13632 return;
13633
13634 i915_redisable_vga_power_on(dev);
13635 }
13636
13637 static bool primary_get_hw_state(struct intel_crtc *crtc)
13638 {
13639 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13640
13641 if (!crtc->active)
13642 return false;
13643
13644 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13645 }
13646
13647 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13648 {
13649 struct drm_i915_private *dev_priv = dev->dev_private;
13650 enum pipe pipe;
13651 struct intel_crtc *crtc;
13652 struct intel_encoder *encoder;
13653 struct intel_connector *connector;
13654 int i;
13655
13656 for_each_intel_crtc(dev, crtc) {
13657 memset(crtc->config, 0, sizeof(*crtc->config));
13658
13659 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13660
13661 crtc->active = dev_priv->display.get_pipe_config(crtc,
13662 crtc->config);
13663
13664 crtc->base.state->enable = crtc->active;
13665 crtc->base.enabled = crtc->active;
13666 crtc->primary_enabled = primary_get_hw_state(crtc);
13667
13668 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13669 crtc->base.base.id,
13670 crtc->active ? "enabled" : "disabled");
13671 }
13672
13673 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13674 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13675
13676 pll->on = pll->get_hw_state(dev_priv, pll,
13677 &pll->config.hw_state);
13678 pll->active = 0;
13679 pll->config.crtc_mask = 0;
13680 for_each_intel_crtc(dev, crtc) {
13681 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13682 pll->active++;
13683 pll->config.crtc_mask |= 1 << crtc->pipe;
13684 }
13685 }
13686
13687 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13688 pll->name, pll->config.crtc_mask, pll->on);
13689
13690 if (pll->config.crtc_mask)
13691 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13692 }
13693
13694 for_each_intel_encoder(dev, encoder) {
13695 pipe = 0;
13696
13697 if (encoder->get_hw_state(encoder, &pipe)) {
13698 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13699 encoder->base.crtc = &crtc->base;
13700 encoder->get_config(encoder, crtc->config);
13701 } else {
13702 encoder->base.crtc = NULL;
13703 }
13704
13705 encoder->connectors_active = false;
13706 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13707 encoder->base.base.id,
13708 encoder->base.name,
13709 encoder->base.crtc ? "enabled" : "disabled",
13710 pipe_name(pipe));
13711 }
13712
13713 list_for_each_entry(connector, &dev->mode_config.connector_list,
13714 base.head) {
13715 if (connector->get_hw_state(connector)) {
13716 connector->base.dpms = DRM_MODE_DPMS_ON;
13717 connector->encoder->connectors_active = true;
13718 connector->base.encoder = &connector->encoder->base;
13719 } else {
13720 connector->base.dpms = DRM_MODE_DPMS_OFF;
13721 connector->base.encoder = NULL;
13722 }
13723 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13724 connector->base.base.id,
13725 connector->base.name,
13726 connector->base.encoder ? "enabled" : "disabled");
13727 }
13728 }
13729
13730 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13731 * and i915 state tracking structures. */
13732 void intel_modeset_setup_hw_state(struct drm_device *dev,
13733 bool force_restore)
13734 {
13735 struct drm_i915_private *dev_priv = dev->dev_private;
13736 enum pipe pipe;
13737 struct intel_crtc *crtc;
13738 struct intel_encoder *encoder;
13739 int i;
13740
13741 intel_modeset_readout_hw_state(dev);
13742
13743 /*
13744 * Now that we have the config, copy it to each CRTC struct
13745 * Note that this could go away if we move to using crtc_config
13746 * checking everywhere.
13747 */
13748 for_each_intel_crtc(dev, crtc) {
13749 if (crtc->active && i915.fastboot) {
13750 intel_mode_from_pipe_config(&crtc->base.mode,
13751 crtc->config);
13752 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13753 crtc->base.base.id);
13754 drm_mode_debug_printmodeline(&crtc->base.mode);
13755 }
13756 }
13757
13758 /* HW state is read out, now we need to sanitize this mess. */
13759 for_each_intel_encoder(dev, encoder) {
13760 intel_sanitize_encoder(encoder);
13761 }
13762
13763 for_each_pipe(dev_priv, pipe) {
13764 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13765 intel_sanitize_crtc(crtc);
13766 intel_dump_pipe_config(crtc, crtc->config,
13767 "[setup_hw_state]");
13768 }
13769
13770 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13771 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13772
13773 if (!pll->on || pll->active)
13774 continue;
13775
13776 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13777
13778 pll->disable(dev_priv, pll);
13779 pll->on = false;
13780 }
13781
13782 if (IS_GEN9(dev))
13783 skl_wm_get_hw_state(dev);
13784 else if (HAS_PCH_SPLIT(dev))
13785 ilk_wm_get_hw_state(dev);
13786
13787 if (force_restore) {
13788 i915_redisable_vga(dev);
13789
13790 /*
13791 * We need to use raw interfaces for restoring state to avoid
13792 * checking (bogus) intermediate states.
13793 */
13794 for_each_pipe(dev_priv, pipe) {
13795 struct drm_crtc *crtc =
13796 dev_priv->pipe_to_crtc_mapping[pipe];
13797
13798 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13799 crtc->primary->fb);
13800 }
13801 } else {
13802 intel_modeset_update_staged_output_state(dev);
13803 }
13804
13805 intel_modeset_check_state(dev);
13806 }
13807
13808 void intel_modeset_gem_init(struct drm_device *dev)
13809 {
13810 struct drm_i915_private *dev_priv = dev->dev_private;
13811 struct drm_crtc *c;
13812 struct drm_i915_gem_object *obj;
13813
13814 mutex_lock(&dev->struct_mutex);
13815 intel_init_gt_powersave(dev);
13816 mutex_unlock(&dev->struct_mutex);
13817
13818 /*
13819 * There may be no VBT; and if the BIOS enabled SSC we can
13820 * just keep using it to avoid unnecessary flicker. Whereas if the
13821 * BIOS isn't using it, don't assume it will work even if the VBT
13822 * indicates as much.
13823 */
13824 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13825 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13826 DREF_SSC1_ENABLE);
13827
13828 intel_modeset_init_hw(dev);
13829
13830 intel_setup_overlay(dev);
13831
13832 /*
13833 * Make sure any fbs we allocated at startup are properly
13834 * pinned & fenced. When we do the allocation it's too early
13835 * for this.
13836 */
13837 mutex_lock(&dev->struct_mutex);
13838 for_each_crtc(dev, c) {
13839 obj = intel_fb_obj(c->primary->fb);
13840 if (obj == NULL)
13841 continue;
13842
13843 if (intel_pin_and_fence_fb_obj(c->primary,
13844 c->primary->fb,
13845 NULL)) {
13846 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13847 to_intel_crtc(c)->pipe);
13848 drm_framebuffer_unreference(c->primary->fb);
13849 c->primary->fb = NULL;
13850 update_state_fb(c->primary);
13851 }
13852 }
13853 mutex_unlock(&dev->struct_mutex);
13854
13855 intel_backlight_register(dev);
13856 }
13857
13858 void intel_connector_unregister(struct intel_connector *intel_connector)
13859 {
13860 struct drm_connector *connector = &intel_connector->base;
13861
13862 intel_panel_destroy_backlight(connector);
13863 drm_connector_unregister(connector);
13864 }
13865
13866 void intel_modeset_cleanup(struct drm_device *dev)
13867 {
13868 struct drm_i915_private *dev_priv = dev->dev_private;
13869 struct drm_connector *connector;
13870
13871 intel_disable_gt_powersave(dev);
13872
13873 intel_backlight_unregister(dev);
13874
13875 /*
13876 * Interrupts and polling as the first thing to avoid creating havoc.
13877 * Too much stuff here (turning of connectors, ...) would
13878 * experience fancy races otherwise.
13879 */
13880 intel_irq_uninstall(dev_priv);
13881
13882 /*
13883 * Due to the hpd irq storm handling the hotplug work can re-arm the
13884 * poll handlers. Hence disable polling after hpd handling is shut down.
13885 */
13886 drm_kms_helper_poll_fini(dev);
13887
13888 mutex_lock(&dev->struct_mutex);
13889
13890 intel_unregister_dsm_handler();
13891
13892 intel_fbc_disable(dev);
13893
13894 ironlake_teardown_rc6(dev);
13895
13896 mutex_unlock(&dev->struct_mutex);
13897
13898 /* flush any delayed tasks or pending work */
13899 flush_scheduled_work();
13900
13901 /* destroy the backlight and sysfs files before encoders/connectors */
13902 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13903 struct intel_connector *intel_connector;
13904
13905 intel_connector = to_intel_connector(connector);
13906 intel_connector->unregister(intel_connector);
13907 }
13908
13909 drm_mode_config_cleanup(dev);
13910
13911 intel_cleanup_overlay(dev);
13912
13913 mutex_lock(&dev->struct_mutex);
13914 intel_cleanup_gt_powersave(dev);
13915 mutex_unlock(&dev->struct_mutex);
13916 }
13917
13918 /*
13919 * Return which encoder is currently attached for connector.
13920 */
13921 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13922 {
13923 return &intel_attached_encoder(connector)->base;
13924 }
13925
13926 void intel_connector_attach_encoder(struct intel_connector *connector,
13927 struct intel_encoder *encoder)
13928 {
13929 connector->encoder = encoder;
13930 drm_mode_connector_attach_encoder(&connector->base,
13931 &encoder->base);
13932 }
13933
13934 /*
13935 * set vga decode state - true == enable VGA decode
13936 */
13937 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13938 {
13939 struct drm_i915_private *dev_priv = dev->dev_private;
13940 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13941 u16 gmch_ctrl;
13942
13943 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13944 DRM_ERROR("failed to read control word\n");
13945 return -EIO;
13946 }
13947
13948 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13949 return 0;
13950
13951 if (state)
13952 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13953 else
13954 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13955
13956 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13957 DRM_ERROR("failed to write control word\n");
13958 return -EIO;
13959 }
13960
13961 return 0;
13962 }
13963
13964 struct intel_display_error_state {
13965
13966 u32 power_well_driver;
13967
13968 int num_transcoders;
13969
13970 struct intel_cursor_error_state {
13971 u32 control;
13972 u32 position;
13973 u32 base;
13974 u32 size;
13975 } cursor[I915_MAX_PIPES];
13976
13977 struct intel_pipe_error_state {
13978 bool power_domain_on;
13979 u32 source;
13980 u32 stat;
13981 } pipe[I915_MAX_PIPES];
13982
13983 struct intel_plane_error_state {
13984 u32 control;
13985 u32 stride;
13986 u32 size;
13987 u32 pos;
13988 u32 addr;
13989 u32 surface;
13990 u32 tile_offset;
13991 } plane[I915_MAX_PIPES];
13992
13993 struct intel_transcoder_error_state {
13994 bool power_domain_on;
13995 enum transcoder cpu_transcoder;
13996
13997 u32 conf;
13998
13999 u32 htotal;
14000 u32 hblank;
14001 u32 hsync;
14002 u32 vtotal;
14003 u32 vblank;
14004 u32 vsync;
14005 } transcoder[4];
14006 };
14007
14008 struct intel_display_error_state *
14009 intel_display_capture_error_state(struct drm_device *dev)
14010 {
14011 struct drm_i915_private *dev_priv = dev->dev_private;
14012 struct intel_display_error_state *error;
14013 int transcoders[] = {
14014 TRANSCODER_A,
14015 TRANSCODER_B,
14016 TRANSCODER_C,
14017 TRANSCODER_EDP,
14018 };
14019 int i;
14020
14021 if (INTEL_INFO(dev)->num_pipes == 0)
14022 return NULL;
14023
14024 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14025 if (error == NULL)
14026 return NULL;
14027
14028 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14029 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14030
14031 for_each_pipe(dev_priv, i) {
14032 error->pipe[i].power_domain_on =
14033 __intel_display_power_is_enabled(dev_priv,
14034 POWER_DOMAIN_PIPE(i));
14035 if (!error->pipe[i].power_domain_on)
14036 continue;
14037
14038 error->cursor[i].control = I915_READ(CURCNTR(i));
14039 error->cursor[i].position = I915_READ(CURPOS(i));
14040 error->cursor[i].base = I915_READ(CURBASE(i));
14041
14042 error->plane[i].control = I915_READ(DSPCNTR(i));
14043 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14044 if (INTEL_INFO(dev)->gen <= 3) {
14045 error->plane[i].size = I915_READ(DSPSIZE(i));
14046 error->plane[i].pos = I915_READ(DSPPOS(i));
14047 }
14048 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14049 error->plane[i].addr = I915_READ(DSPADDR(i));
14050 if (INTEL_INFO(dev)->gen >= 4) {
14051 error->plane[i].surface = I915_READ(DSPSURF(i));
14052 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14053 }
14054
14055 error->pipe[i].source = I915_READ(PIPESRC(i));
14056
14057 if (HAS_GMCH_DISPLAY(dev))
14058 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14059 }
14060
14061 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14062 if (HAS_DDI(dev_priv->dev))
14063 error->num_transcoders++; /* Account for eDP. */
14064
14065 for (i = 0; i < error->num_transcoders; i++) {
14066 enum transcoder cpu_transcoder = transcoders[i];
14067
14068 error->transcoder[i].power_domain_on =
14069 __intel_display_power_is_enabled(dev_priv,
14070 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14071 if (!error->transcoder[i].power_domain_on)
14072 continue;
14073
14074 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14075
14076 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14077 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14078 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14079 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14080 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14081 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14082 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14083 }
14084
14085 return error;
14086 }
14087
14088 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14089
14090 void
14091 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14092 struct drm_device *dev,
14093 struct intel_display_error_state *error)
14094 {
14095 struct drm_i915_private *dev_priv = dev->dev_private;
14096 int i;
14097
14098 if (!error)
14099 return;
14100
14101 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14102 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14103 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14104 error->power_well_driver);
14105 for_each_pipe(dev_priv, i) {
14106 err_printf(m, "Pipe [%d]:\n", i);
14107 err_printf(m, " Power: %s\n",
14108 error->pipe[i].power_domain_on ? "on" : "off");
14109 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14110 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14111
14112 err_printf(m, "Plane [%d]:\n", i);
14113 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14114 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14115 if (INTEL_INFO(dev)->gen <= 3) {
14116 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14117 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14118 }
14119 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14120 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14121 if (INTEL_INFO(dev)->gen >= 4) {
14122 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14123 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14124 }
14125
14126 err_printf(m, "Cursor [%d]:\n", i);
14127 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14128 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14129 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14130 }
14131
14132 for (i = 0; i < error->num_transcoders; i++) {
14133 err_printf(m, "CPU transcoder: %c\n",
14134 transcoder_name(error->transcoder[i].cpu_transcoder));
14135 err_printf(m, " Power: %s\n",
14136 error->transcoder[i].power_domain_on ? "on" : "off");
14137 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14138 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14139 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14140 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14141 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14142 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14143 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14144 }
14145 }
14146
14147 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14148 {
14149 struct intel_crtc *crtc;
14150
14151 for_each_intel_crtc(dev, crtc) {
14152 struct intel_unpin_work *work;
14153
14154 spin_lock_irq(&dev->event_lock);
14155
14156 work = crtc->unpin_work;
14157
14158 if (work && work->event &&
14159 work->event->base.file_priv == file) {
14160 kfree(work->event);
14161 work->event = NULL;
14162 }
14163
14164 spin_unlock_irq(&dev->event_lock);
14165 }
14166 }
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